1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef ARCH_X86_KVM_X86_H 3 #define ARCH_X86_KVM_X86_H 4 5 #include <linux/kvm_host.h> 6 #include <asm/pvclock.h> 7 #include "kvm_cache_regs.h" 8 9 #define MSR_IA32_CR_PAT_DEFAULT 0x0007040600070406ULL 10 11 static inline void kvm_clear_exception_queue(struct kvm_vcpu *vcpu) 12 { 13 vcpu->arch.exception.pending = false; 14 vcpu->arch.exception.injected = false; 15 } 16 17 static inline void kvm_queue_interrupt(struct kvm_vcpu *vcpu, u8 vector, 18 bool soft) 19 { 20 vcpu->arch.interrupt.pending = true; 21 vcpu->arch.interrupt.soft = soft; 22 vcpu->arch.interrupt.nr = vector; 23 } 24 25 static inline void kvm_clear_interrupt_queue(struct kvm_vcpu *vcpu) 26 { 27 vcpu->arch.interrupt.pending = false; 28 } 29 30 static inline bool kvm_event_needs_reinjection(struct kvm_vcpu *vcpu) 31 { 32 return vcpu->arch.exception.injected || vcpu->arch.interrupt.pending || 33 vcpu->arch.nmi_injected; 34 } 35 36 static inline bool kvm_exception_is_soft(unsigned int nr) 37 { 38 return (nr == BP_VECTOR) || (nr == OF_VECTOR); 39 } 40 41 static inline bool is_protmode(struct kvm_vcpu *vcpu) 42 { 43 return kvm_read_cr0_bits(vcpu, X86_CR0_PE); 44 } 45 46 static inline int is_long_mode(struct kvm_vcpu *vcpu) 47 { 48 #ifdef CONFIG_X86_64 49 return vcpu->arch.efer & EFER_LMA; 50 #else 51 return 0; 52 #endif 53 } 54 55 static inline bool is_64_bit_mode(struct kvm_vcpu *vcpu) 56 { 57 int cs_db, cs_l; 58 59 if (!is_long_mode(vcpu)) 60 return false; 61 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l); 62 return cs_l; 63 } 64 65 static inline bool is_la57_mode(struct kvm_vcpu *vcpu) 66 { 67 #ifdef CONFIG_X86_64 68 return (vcpu->arch.efer & EFER_LMA) && 69 kvm_read_cr4_bits(vcpu, X86_CR4_LA57); 70 #else 71 return 0; 72 #endif 73 } 74 75 static inline bool mmu_is_nested(struct kvm_vcpu *vcpu) 76 { 77 return vcpu->arch.walk_mmu == &vcpu->arch.nested_mmu; 78 } 79 80 static inline int is_pae(struct kvm_vcpu *vcpu) 81 { 82 return kvm_read_cr4_bits(vcpu, X86_CR4_PAE); 83 } 84 85 static inline int is_pse(struct kvm_vcpu *vcpu) 86 { 87 return kvm_read_cr4_bits(vcpu, X86_CR4_PSE); 88 } 89 90 static inline int is_paging(struct kvm_vcpu *vcpu) 91 { 92 return likely(kvm_read_cr0_bits(vcpu, X86_CR0_PG)); 93 } 94 95 static inline u32 bit(int bitno) 96 { 97 return 1 << (bitno & 31); 98 } 99 100 static inline u8 vcpu_virt_addr_bits(struct kvm_vcpu *vcpu) 101 { 102 return kvm_read_cr4_bits(vcpu, X86_CR4_LA57) ? 57 : 48; 103 } 104 105 static inline u8 ctxt_virt_addr_bits(struct x86_emulate_ctxt *ctxt) 106 { 107 return (ctxt->ops->get_cr(ctxt, 4) & X86_CR4_LA57) ? 57 : 48; 108 } 109 110 static inline u64 get_canonical(u64 la, u8 vaddr_bits) 111 { 112 return ((int64_t)la << (64 - vaddr_bits)) >> (64 - vaddr_bits); 113 } 114 115 static inline bool is_noncanonical_address(u64 la, struct kvm_vcpu *vcpu) 116 { 117 #ifdef CONFIG_X86_64 118 return get_canonical(la, vcpu_virt_addr_bits(vcpu)) != la; 119 #else 120 return false; 121 #endif 122 } 123 124 static inline bool emul_is_noncanonical_address(u64 la, 125 struct x86_emulate_ctxt *ctxt) 126 { 127 #ifdef CONFIG_X86_64 128 return get_canonical(la, ctxt_virt_addr_bits(ctxt)) != la; 129 #else 130 return false; 131 #endif 132 } 133 134 static inline void vcpu_cache_mmio_info(struct kvm_vcpu *vcpu, 135 gva_t gva, gfn_t gfn, unsigned access) 136 { 137 /* 138 * If this is a shadow nested page table, the "GVA" is 139 * actually a nGPA. 140 */ 141 vcpu->arch.mmio_gva = mmu_is_nested(vcpu) ? 0 : gva & PAGE_MASK; 142 vcpu->arch.access = access; 143 vcpu->arch.mmio_gfn = gfn; 144 vcpu->arch.mmio_gen = kvm_memslots(vcpu->kvm)->generation; 145 } 146 147 static inline bool vcpu_match_mmio_gen(struct kvm_vcpu *vcpu) 148 { 149 return vcpu->arch.mmio_gen == kvm_memslots(vcpu->kvm)->generation; 150 } 151 152 /* 153 * Clear the mmio cache info for the given gva. If gva is MMIO_GVA_ANY, we 154 * clear all mmio cache info. 155 */ 156 #define MMIO_GVA_ANY (~(gva_t)0) 157 158 static inline void vcpu_clear_mmio_info(struct kvm_vcpu *vcpu, gva_t gva) 159 { 160 if (gva != MMIO_GVA_ANY && vcpu->arch.mmio_gva != (gva & PAGE_MASK)) 161 return; 162 163 vcpu->arch.mmio_gva = 0; 164 } 165 166 static inline bool vcpu_match_mmio_gva(struct kvm_vcpu *vcpu, unsigned long gva) 167 { 168 if (vcpu_match_mmio_gen(vcpu) && vcpu->arch.mmio_gva && 169 vcpu->arch.mmio_gva == (gva & PAGE_MASK)) 170 return true; 171 172 return false; 173 } 174 175 static inline bool vcpu_match_mmio_gpa(struct kvm_vcpu *vcpu, gpa_t gpa) 176 { 177 if (vcpu_match_mmio_gen(vcpu) && vcpu->arch.mmio_gfn && 178 vcpu->arch.mmio_gfn == gpa >> PAGE_SHIFT) 179 return true; 180 181 return false; 182 } 183 184 static inline unsigned long kvm_register_readl(struct kvm_vcpu *vcpu, 185 enum kvm_reg reg) 186 { 187 unsigned long val = kvm_register_read(vcpu, reg); 188 189 return is_64_bit_mode(vcpu) ? val : (u32)val; 190 } 191 192 static inline void kvm_register_writel(struct kvm_vcpu *vcpu, 193 enum kvm_reg reg, 194 unsigned long val) 195 { 196 if (!is_64_bit_mode(vcpu)) 197 val = (u32)val; 198 return kvm_register_write(vcpu, reg, val); 199 } 200 201 static inline bool kvm_check_has_quirk(struct kvm *kvm, u64 quirk) 202 { 203 return !(kvm->arch.disabled_quirks & quirk); 204 } 205 206 void kvm_before_handle_nmi(struct kvm_vcpu *vcpu); 207 void kvm_after_handle_nmi(struct kvm_vcpu *vcpu); 208 void kvm_set_pending_timer(struct kvm_vcpu *vcpu); 209 int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip); 210 211 void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr); 212 u64 get_kvmclock_ns(struct kvm *kvm); 213 214 int kvm_read_guest_virt(struct x86_emulate_ctxt *ctxt, 215 gva_t addr, void *val, unsigned int bytes, 216 struct x86_exception *exception); 217 218 int kvm_write_guest_virt_system(struct x86_emulate_ctxt *ctxt, 219 gva_t addr, void *val, unsigned int bytes, 220 struct x86_exception *exception); 221 222 void kvm_vcpu_mtrr_init(struct kvm_vcpu *vcpu); 223 u8 kvm_mtrr_get_guest_memory_type(struct kvm_vcpu *vcpu, gfn_t gfn); 224 bool kvm_mtrr_valid(struct kvm_vcpu *vcpu, u32 msr, u64 data); 225 int kvm_mtrr_set_msr(struct kvm_vcpu *vcpu, u32 msr, u64 data); 226 int kvm_mtrr_get_msr(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata); 227 bool kvm_mtrr_check_gfn_range_consistency(struct kvm_vcpu *vcpu, gfn_t gfn, 228 int page_num); 229 bool kvm_vector_hashing_enabled(void); 230 231 #define KVM_SUPPORTED_XCR0 (XFEATURE_MASK_FP | XFEATURE_MASK_SSE \ 232 | XFEATURE_MASK_YMM | XFEATURE_MASK_BNDREGS \ 233 | XFEATURE_MASK_BNDCSR | XFEATURE_MASK_AVX512 \ 234 | XFEATURE_MASK_PKRU) 235 extern u64 host_xcr0; 236 237 extern u64 kvm_supported_xcr0(void); 238 239 extern unsigned int min_timer_period_us; 240 241 extern unsigned int lapic_timer_advance_ns; 242 243 extern bool enable_vmware_backdoor; 244 245 extern struct static_key kvm_no_apic_vcpu; 246 247 static inline u64 nsec_to_cycles(struct kvm_vcpu *vcpu, u64 nsec) 248 { 249 return pvclock_scale_delta(nsec, vcpu->arch.virtual_tsc_mult, 250 vcpu->arch.virtual_tsc_shift); 251 } 252 253 /* Same "calling convention" as do_div: 254 * - divide (n << 32) by base 255 * - put result in n 256 * - return remainder 257 */ 258 #define do_shl32_div32(n, base) \ 259 ({ \ 260 u32 __quot, __rem; \ 261 asm("divl %2" : "=a" (__quot), "=d" (__rem) \ 262 : "rm" (base), "0" (0), "1" ((u32) n)); \ 263 n = __quot; \ 264 __rem; \ 265 }) 266 267 #define KVM_X86_DISABLE_EXITS_MWAIT (1 << 0) 268 #define KVM_X86_DISABLE_VALID_EXITS (KVM_X86_DISABLE_EXITS_MWAIT) 269 270 static inline bool kvm_mwait_in_guest(struct kvm *kvm) 271 { 272 return kvm->arch.mwait_in_guest; 273 } 274 275 #endif 276