1 /* 2 * Kernel-based Virtual Machine driver for Linux 3 * 4 * derived from drivers/kvm/kvm_main.c 5 * 6 * Copyright (C) 2006 Qumranet, Inc. 7 * Copyright (C) 2008 Qumranet, Inc. 8 * Copyright IBM Corporation, 2008 9 * Copyright 2010 Red Hat, Inc. and/or its affiliates. 10 * 11 * Authors: 12 * Avi Kivity <avi@qumranet.com> 13 * Yaniv Kamay <yaniv@qumranet.com> 14 * Amit Shah <amit.shah@qumranet.com> 15 * Ben-Ami Yassour <benami@il.ibm.com> 16 * 17 * This work is licensed under the terms of the GNU GPL, version 2. See 18 * the COPYING file in the top-level directory. 19 * 20 */ 21 22 #include <linux/kvm_host.h> 23 #include "irq.h" 24 #include "mmu.h" 25 #include "i8254.h" 26 #include "tss.h" 27 #include "kvm_cache_regs.h" 28 #include "x86.h" 29 #include "cpuid.h" 30 #include "pmu.h" 31 #include "hyperv.h" 32 33 #include <linux/clocksource.h> 34 #include <linux/interrupt.h> 35 #include <linux/kvm.h> 36 #include <linux/fs.h> 37 #include <linux/vmalloc.h> 38 #include <linux/export.h> 39 #include <linux/moduleparam.h> 40 #include <linux/mman.h> 41 #include <linux/highmem.h> 42 #include <linux/iommu.h> 43 #include <linux/intel-iommu.h> 44 #include <linux/cpufreq.h> 45 #include <linux/user-return-notifier.h> 46 #include <linux/srcu.h> 47 #include <linux/slab.h> 48 #include <linux/perf_event.h> 49 #include <linux/uaccess.h> 50 #include <linux/hash.h> 51 #include <linux/pci.h> 52 #include <linux/timekeeper_internal.h> 53 #include <linux/pvclock_gtod.h> 54 #include <linux/kvm_irqfd.h> 55 #include <linux/irqbypass.h> 56 #include <linux/sched/stat.h> 57 #include <linux/mem_encrypt.h> 58 59 #include <trace/events/kvm.h> 60 61 #include <asm/debugreg.h> 62 #include <asm/msr.h> 63 #include <asm/desc.h> 64 #include <asm/mce.h> 65 #include <linux/kernel_stat.h> 66 #include <asm/fpu/internal.h> /* Ugh! */ 67 #include <asm/pvclock.h> 68 #include <asm/div64.h> 69 #include <asm/irq_remapping.h> 70 71 #define CREATE_TRACE_POINTS 72 #include "trace.h" 73 74 #define MAX_IO_MSRS 256 75 #define KVM_MAX_MCE_BANKS 32 76 u64 __read_mostly kvm_mce_cap_supported = MCG_CTL_P | MCG_SER_P; 77 EXPORT_SYMBOL_GPL(kvm_mce_cap_supported); 78 79 #define emul_to_vcpu(ctxt) \ 80 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt) 81 82 /* EFER defaults: 83 * - enable syscall per default because its emulated by KVM 84 * - enable LME and LMA per default on 64 bit KVM 85 */ 86 #ifdef CONFIG_X86_64 87 static 88 u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA)); 89 #else 90 static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE); 91 #endif 92 93 #define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM 94 #define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU 95 96 #define KVM_X2APIC_API_VALID_FLAGS (KVM_X2APIC_API_USE_32BIT_IDS | \ 97 KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK) 98 99 static void update_cr8_intercept(struct kvm_vcpu *vcpu); 100 static void process_nmi(struct kvm_vcpu *vcpu); 101 static void enter_smm(struct kvm_vcpu *vcpu); 102 static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags); 103 104 struct kvm_x86_ops *kvm_x86_ops __read_mostly; 105 EXPORT_SYMBOL_GPL(kvm_x86_ops); 106 107 static bool __read_mostly ignore_msrs = 0; 108 module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR); 109 110 static bool __read_mostly report_ignored_msrs = true; 111 module_param(report_ignored_msrs, bool, S_IRUGO | S_IWUSR); 112 113 unsigned int min_timer_period_us = 500; 114 module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR); 115 116 static bool __read_mostly kvmclock_periodic_sync = true; 117 module_param(kvmclock_periodic_sync, bool, S_IRUGO); 118 119 bool __read_mostly kvm_has_tsc_control; 120 EXPORT_SYMBOL_GPL(kvm_has_tsc_control); 121 u32 __read_mostly kvm_max_guest_tsc_khz; 122 EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz); 123 u8 __read_mostly kvm_tsc_scaling_ratio_frac_bits; 124 EXPORT_SYMBOL_GPL(kvm_tsc_scaling_ratio_frac_bits); 125 u64 __read_mostly kvm_max_tsc_scaling_ratio; 126 EXPORT_SYMBOL_GPL(kvm_max_tsc_scaling_ratio); 127 u64 __read_mostly kvm_default_tsc_scaling_ratio; 128 EXPORT_SYMBOL_GPL(kvm_default_tsc_scaling_ratio); 129 130 /* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */ 131 static u32 __read_mostly tsc_tolerance_ppm = 250; 132 module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR); 133 134 /* lapic timer advance (tscdeadline mode only) in nanoseconds */ 135 unsigned int __read_mostly lapic_timer_advance_ns = 0; 136 module_param(lapic_timer_advance_ns, uint, S_IRUGO | S_IWUSR); 137 138 static bool __read_mostly vector_hashing = true; 139 module_param(vector_hashing, bool, S_IRUGO); 140 141 #define KVM_NR_SHARED_MSRS 16 142 143 struct kvm_shared_msrs_global { 144 int nr; 145 u32 msrs[KVM_NR_SHARED_MSRS]; 146 }; 147 148 struct kvm_shared_msrs { 149 struct user_return_notifier urn; 150 bool registered; 151 struct kvm_shared_msr_values { 152 u64 host; 153 u64 curr; 154 } values[KVM_NR_SHARED_MSRS]; 155 }; 156 157 static struct kvm_shared_msrs_global __read_mostly shared_msrs_global; 158 static struct kvm_shared_msrs __percpu *shared_msrs; 159 160 struct kvm_stats_debugfs_item debugfs_entries[] = { 161 { "pf_fixed", VCPU_STAT(pf_fixed) }, 162 { "pf_guest", VCPU_STAT(pf_guest) }, 163 { "tlb_flush", VCPU_STAT(tlb_flush) }, 164 { "invlpg", VCPU_STAT(invlpg) }, 165 { "exits", VCPU_STAT(exits) }, 166 { "io_exits", VCPU_STAT(io_exits) }, 167 { "mmio_exits", VCPU_STAT(mmio_exits) }, 168 { "signal_exits", VCPU_STAT(signal_exits) }, 169 { "irq_window", VCPU_STAT(irq_window_exits) }, 170 { "nmi_window", VCPU_STAT(nmi_window_exits) }, 171 { "halt_exits", VCPU_STAT(halt_exits) }, 172 { "halt_successful_poll", VCPU_STAT(halt_successful_poll) }, 173 { "halt_attempted_poll", VCPU_STAT(halt_attempted_poll) }, 174 { "halt_poll_invalid", VCPU_STAT(halt_poll_invalid) }, 175 { "halt_wakeup", VCPU_STAT(halt_wakeup) }, 176 { "hypercalls", VCPU_STAT(hypercalls) }, 177 { "request_irq", VCPU_STAT(request_irq_exits) }, 178 { "irq_exits", VCPU_STAT(irq_exits) }, 179 { "host_state_reload", VCPU_STAT(host_state_reload) }, 180 { "efer_reload", VCPU_STAT(efer_reload) }, 181 { "fpu_reload", VCPU_STAT(fpu_reload) }, 182 { "insn_emulation", VCPU_STAT(insn_emulation) }, 183 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) }, 184 { "irq_injections", VCPU_STAT(irq_injections) }, 185 { "nmi_injections", VCPU_STAT(nmi_injections) }, 186 { "req_event", VCPU_STAT(req_event) }, 187 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) }, 188 { "mmu_pte_write", VM_STAT(mmu_pte_write) }, 189 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) }, 190 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) }, 191 { "mmu_flooded", VM_STAT(mmu_flooded) }, 192 { "mmu_recycled", VM_STAT(mmu_recycled) }, 193 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) }, 194 { "mmu_unsync", VM_STAT(mmu_unsync) }, 195 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) }, 196 { "largepages", VM_STAT(lpages) }, 197 { "max_mmu_page_hash_collisions", 198 VM_STAT(max_mmu_page_hash_collisions) }, 199 { NULL } 200 }; 201 202 u64 __read_mostly host_xcr0; 203 204 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt); 205 206 static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu) 207 { 208 int i; 209 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++) 210 vcpu->arch.apf.gfns[i] = ~0; 211 } 212 213 static void kvm_on_user_return(struct user_return_notifier *urn) 214 { 215 unsigned slot; 216 struct kvm_shared_msrs *locals 217 = container_of(urn, struct kvm_shared_msrs, urn); 218 struct kvm_shared_msr_values *values; 219 unsigned long flags; 220 221 /* 222 * Disabling irqs at this point since the following code could be 223 * interrupted and executed through kvm_arch_hardware_disable() 224 */ 225 local_irq_save(flags); 226 if (locals->registered) { 227 locals->registered = false; 228 user_return_notifier_unregister(urn); 229 } 230 local_irq_restore(flags); 231 for (slot = 0; slot < shared_msrs_global.nr; ++slot) { 232 values = &locals->values[slot]; 233 if (values->host != values->curr) { 234 wrmsrl(shared_msrs_global.msrs[slot], values->host); 235 values->curr = values->host; 236 } 237 } 238 } 239 240 static void shared_msr_update(unsigned slot, u32 msr) 241 { 242 u64 value; 243 unsigned int cpu = smp_processor_id(); 244 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu); 245 246 /* only read, and nobody should modify it at this time, 247 * so don't need lock */ 248 if (slot >= shared_msrs_global.nr) { 249 printk(KERN_ERR "kvm: invalid MSR slot!"); 250 return; 251 } 252 rdmsrl_safe(msr, &value); 253 smsr->values[slot].host = value; 254 smsr->values[slot].curr = value; 255 } 256 257 void kvm_define_shared_msr(unsigned slot, u32 msr) 258 { 259 BUG_ON(slot >= KVM_NR_SHARED_MSRS); 260 shared_msrs_global.msrs[slot] = msr; 261 if (slot >= shared_msrs_global.nr) 262 shared_msrs_global.nr = slot + 1; 263 } 264 EXPORT_SYMBOL_GPL(kvm_define_shared_msr); 265 266 static void kvm_shared_msr_cpu_online(void) 267 { 268 unsigned i; 269 270 for (i = 0; i < shared_msrs_global.nr; ++i) 271 shared_msr_update(i, shared_msrs_global.msrs[i]); 272 } 273 274 int kvm_set_shared_msr(unsigned slot, u64 value, u64 mask) 275 { 276 unsigned int cpu = smp_processor_id(); 277 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu); 278 int err; 279 280 if (((value ^ smsr->values[slot].curr) & mask) == 0) 281 return 0; 282 smsr->values[slot].curr = value; 283 err = wrmsrl_safe(shared_msrs_global.msrs[slot], value); 284 if (err) 285 return 1; 286 287 if (!smsr->registered) { 288 smsr->urn.on_user_return = kvm_on_user_return; 289 user_return_notifier_register(&smsr->urn); 290 smsr->registered = true; 291 } 292 return 0; 293 } 294 EXPORT_SYMBOL_GPL(kvm_set_shared_msr); 295 296 static void drop_user_return_notifiers(void) 297 { 298 unsigned int cpu = smp_processor_id(); 299 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu); 300 301 if (smsr->registered) 302 kvm_on_user_return(&smsr->urn); 303 } 304 305 u64 kvm_get_apic_base(struct kvm_vcpu *vcpu) 306 { 307 return vcpu->arch.apic_base; 308 } 309 EXPORT_SYMBOL_GPL(kvm_get_apic_base); 310 311 int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info) 312 { 313 u64 old_state = vcpu->arch.apic_base & 314 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE); 315 u64 new_state = msr_info->data & 316 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE); 317 u64 reserved_bits = ((~0ULL) << cpuid_maxphyaddr(vcpu)) | 0x2ff | 318 (guest_cpuid_has(vcpu, X86_FEATURE_X2APIC) ? 0 : X2APIC_ENABLE); 319 320 if ((msr_info->data & reserved_bits) || new_state == X2APIC_ENABLE) 321 return 1; 322 if (!msr_info->host_initiated && 323 ((new_state == MSR_IA32_APICBASE_ENABLE && 324 old_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE)) || 325 (new_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE) && 326 old_state == 0))) 327 return 1; 328 329 kvm_lapic_set_base(vcpu, msr_info->data); 330 return 0; 331 } 332 EXPORT_SYMBOL_GPL(kvm_set_apic_base); 333 334 asmlinkage __visible void kvm_spurious_fault(void) 335 { 336 /* Fault while not rebooting. We want the trace. */ 337 BUG(); 338 } 339 EXPORT_SYMBOL_GPL(kvm_spurious_fault); 340 341 #define EXCPT_BENIGN 0 342 #define EXCPT_CONTRIBUTORY 1 343 #define EXCPT_PF 2 344 345 static int exception_class(int vector) 346 { 347 switch (vector) { 348 case PF_VECTOR: 349 return EXCPT_PF; 350 case DE_VECTOR: 351 case TS_VECTOR: 352 case NP_VECTOR: 353 case SS_VECTOR: 354 case GP_VECTOR: 355 return EXCPT_CONTRIBUTORY; 356 default: 357 break; 358 } 359 return EXCPT_BENIGN; 360 } 361 362 #define EXCPT_FAULT 0 363 #define EXCPT_TRAP 1 364 #define EXCPT_ABORT 2 365 #define EXCPT_INTERRUPT 3 366 367 static int exception_type(int vector) 368 { 369 unsigned int mask; 370 371 if (WARN_ON(vector > 31 || vector == NMI_VECTOR)) 372 return EXCPT_INTERRUPT; 373 374 mask = 1 << vector; 375 376 /* #DB is trap, as instruction watchpoints are handled elsewhere */ 377 if (mask & ((1 << DB_VECTOR) | (1 << BP_VECTOR) | (1 << OF_VECTOR))) 378 return EXCPT_TRAP; 379 380 if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR))) 381 return EXCPT_ABORT; 382 383 /* Reserved exceptions will result in fault */ 384 return EXCPT_FAULT; 385 } 386 387 static void kvm_multiple_exception(struct kvm_vcpu *vcpu, 388 unsigned nr, bool has_error, u32 error_code, 389 bool reinject) 390 { 391 u32 prev_nr; 392 int class1, class2; 393 394 kvm_make_request(KVM_REQ_EVENT, vcpu); 395 396 if (!vcpu->arch.exception.pending && !vcpu->arch.exception.injected) { 397 queue: 398 if (has_error && !is_protmode(vcpu)) 399 has_error = false; 400 if (reinject) { 401 /* 402 * On vmentry, vcpu->arch.exception.pending is only 403 * true if an event injection was blocked by 404 * nested_run_pending. In that case, however, 405 * vcpu_enter_guest requests an immediate exit, 406 * and the guest shouldn't proceed far enough to 407 * need reinjection. 408 */ 409 WARN_ON_ONCE(vcpu->arch.exception.pending); 410 vcpu->arch.exception.injected = true; 411 } else { 412 vcpu->arch.exception.pending = true; 413 vcpu->arch.exception.injected = false; 414 } 415 vcpu->arch.exception.has_error_code = has_error; 416 vcpu->arch.exception.nr = nr; 417 vcpu->arch.exception.error_code = error_code; 418 return; 419 } 420 421 /* to check exception */ 422 prev_nr = vcpu->arch.exception.nr; 423 if (prev_nr == DF_VECTOR) { 424 /* triple fault -> shutdown */ 425 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); 426 return; 427 } 428 class1 = exception_class(prev_nr); 429 class2 = exception_class(nr); 430 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY) 431 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) { 432 /* 433 * Generate double fault per SDM Table 5-5. Set 434 * exception.pending = true so that the double fault 435 * can trigger a nested vmexit. 436 */ 437 vcpu->arch.exception.pending = true; 438 vcpu->arch.exception.injected = false; 439 vcpu->arch.exception.has_error_code = true; 440 vcpu->arch.exception.nr = DF_VECTOR; 441 vcpu->arch.exception.error_code = 0; 442 } else 443 /* replace previous exception with a new one in a hope 444 that instruction re-execution will regenerate lost 445 exception */ 446 goto queue; 447 } 448 449 void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr) 450 { 451 kvm_multiple_exception(vcpu, nr, false, 0, false); 452 } 453 EXPORT_SYMBOL_GPL(kvm_queue_exception); 454 455 void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr) 456 { 457 kvm_multiple_exception(vcpu, nr, false, 0, true); 458 } 459 EXPORT_SYMBOL_GPL(kvm_requeue_exception); 460 461 int kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err) 462 { 463 if (err) 464 kvm_inject_gp(vcpu, 0); 465 else 466 return kvm_skip_emulated_instruction(vcpu); 467 468 return 1; 469 } 470 EXPORT_SYMBOL_GPL(kvm_complete_insn_gp); 471 472 void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault) 473 { 474 ++vcpu->stat.pf_guest; 475 vcpu->arch.exception.nested_apf = 476 is_guest_mode(vcpu) && fault->async_page_fault; 477 if (vcpu->arch.exception.nested_apf) 478 vcpu->arch.apf.nested_apf_token = fault->address; 479 else 480 vcpu->arch.cr2 = fault->address; 481 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code); 482 } 483 EXPORT_SYMBOL_GPL(kvm_inject_page_fault); 484 485 static bool kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault) 486 { 487 if (mmu_is_nested(vcpu) && !fault->nested_page_fault) 488 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault); 489 else 490 vcpu->arch.mmu.inject_page_fault(vcpu, fault); 491 492 return fault->nested_page_fault; 493 } 494 495 void kvm_inject_nmi(struct kvm_vcpu *vcpu) 496 { 497 atomic_inc(&vcpu->arch.nmi_queued); 498 kvm_make_request(KVM_REQ_NMI, vcpu); 499 } 500 EXPORT_SYMBOL_GPL(kvm_inject_nmi); 501 502 void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code) 503 { 504 kvm_multiple_exception(vcpu, nr, true, error_code, false); 505 } 506 EXPORT_SYMBOL_GPL(kvm_queue_exception_e); 507 508 void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code) 509 { 510 kvm_multiple_exception(vcpu, nr, true, error_code, true); 511 } 512 EXPORT_SYMBOL_GPL(kvm_requeue_exception_e); 513 514 /* 515 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue 516 * a #GP and return false. 517 */ 518 bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl) 519 { 520 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl) 521 return true; 522 kvm_queue_exception_e(vcpu, GP_VECTOR, 0); 523 return false; 524 } 525 EXPORT_SYMBOL_GPL(kvm_require_cpl); 526 527 bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr) 528 { 529 if ((dr != 4 && dr != 5) || !kvm_read_cr4_bits(vcpu, X86_CR4_DE)) 530 return true; 531 532 kvm_queue_exception(vcpu, UD_VECTOR); 533 return false; 534 } 535 EXPORT_SYMBOL_GPL(kvm_require_dr); 536 537 /* 538 * This function will be used to read from the physical memory of the currently 539 * running guest. The difference to kvm_vcpu_read_guest_page is that this function 540 * can read from guest physical or from the guest's guest physical memory. 541 */ 542 int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, 543 gfn_t ngfn, void *data, int offset, int len, 544 u32 access) 545 { 546 struct x86_exception exception; 547 gfn_t real_gfn; 548 gpa_t ngpa; 549 550 ngpa = gfn_to_gpa(ngfn); 551 real_gfn = mmu->translate_gpa(vcpu, ngpa, access, &exception); 552 if (real_gfn == UNMAPPED_GVA) 553 return -EFAULT; 554 555 real_gfn = gpa_to_gfn(real_gfn); 556 557 return kvm_vcpu_read_guest_page(vcpu, real_gfn, data, offset, len); 558 } 559 EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu); 560 561 static int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn, 562 void *data, int offset, int len, u32 access) 563 { 564 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn, 565 data, offset, len, access); 566 } 567 568 /* 569 * Load the pae pdptrs. Return true is they are all valid. 570 */ 571 int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3) 572 { 573 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT; 574 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2; 575 int i; 576 int ret; 577 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)]; 578 579 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte, 580 offset * sizeof(u64), sizeof(pdpte), 581 PFERR_USER_MASK|PFERR_WRITE_MASK); 582 if (ret < 0) { 583 ret = 0; 584 goto out; 585 } 586 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) { 587 if ((pdpte[i] & PT_PRESENT_MASK) && 588 (pdpte[i] & 589 vcpu->arch.mmu.guest_rsvd_check.rsvd_bits_mask[0][2])) { 590 ret = 0; 591 goto out; 592 } 593 } 594 ret = 1; 595 596 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs)); 597 __set_bit(VCPU_EXREG_PDPTR, 598 (unsigned long *)&vcpu->arch.regs_avail); 599 __set_bit(VCPU_EXREG_PDPTR, 600 (unsigned long *)&vcpu->arch.regs_dirty); 601 out: 602 603 return ret; 604 } 605 EXPORT_SYMBOL_GPL(load_pdptrs); 606 607 bool pdptrs_changed(struct kvm_vcpu *vcpu) 608 { 609 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)]; 610 bool changed = true; 611 int offset; 612 gfn_t gfn; 613 int r; 614 615 if (is_long_mode(vcpu) || !is_pae(vcpu)) 616 return false; 617 618 if (!test_bit(VCPU_EXREG_PDPTR, 619 (unsigned long *)&vcpu->arch.regs_avail)) 620 return true; 621 622 gfn = (kvm_read_cr3(vcpu) & 0xffffffe0ul) >> PAGE_SHIFT; 623 offset = (kvm_read_cr3(vcpu) & 0xffffffe0ul) & (PAGE_SIZE - 1); 624 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte), 625 PFERR_USER_MASK | PFERR_WRITE_MASK); 626 if (r < 0) 627 goto out; 628 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0; 629 out: 630 631 return changed; 632 } 633 EXPORT_SYMBOL_GPL(pdptrs_changed); 634 635 int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0) 636 { 637 unsigned long old_cr0 = kvm_read_cr0(vcpu); 638 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP; 639 640 cr0 |= X86_CR0_ET; 641 642 #ifdef CONFIG_X86_64 643 if (cr0 & 0xffffffff00000000UL) 644 return 1; 645 #endif 646 647 cr0 &= ~CR0_RESERVED_BITS; 648 649 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD)) 650 return 1; 651 652 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE)) 653 return 1; 654 655 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) { 656 #ifdef CONFIG_X86_64 657 if ((vcpu->arch.efer & EFER_LME)) { 658 int cs_db, cs_l; 659 660 if (!is_pae(vcpu)) 661 return 1; 662 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l); 663 if (cs_l) 664 return 1; 665 } else 666 #endif 667 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu, 668 kvm_read_cr3(vcpu))) 669 return 1; 670 } 671 672 if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE)) 673 return 1; 674 675 kvm_x86_ops->set_cr0(vcpu, cr0); 676 677 if ((cr0 ^ old_cr0) & X86_CR0_PG) { 678 kvm_clear_async_pf_completion_queue(vcpu); 679 kvm_async_pf_hash_reset(vcpu); 680 } 681 682 if ((cr0 ^ old_cr0) & update_bits) 683 kvm_mmu_reset_context(vcpu); 684 685 if (((cr0 ^ old_cr0) & X86_CR0_CD) && 686 kvm_arch_has_noncoherent_dma(vcpu->kvm) && 687 !kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED)) 688 kvm_zap_gfn_range(vcpu->kvm, 0, ~0ULL); 689 690 return 0; 691 } 692 EXPORT_SYMBOL_GPL(kvm_set_cr0); 693 694 void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw) 695 { 696 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f)); 697 } 698 EXPORT_SYMBOL_GPL(kvm_lmsw); 699 700 static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu) 701 { 702 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) && 703 !vcpu->guest_xcr0_loaded) { 704 /* kvm_set_xcr() also depends on this */ 705 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0); 706 vcpu->guest_xcr0_loaded = 1; 707 } 708 } 709 710 static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu) 711 { 712 if (vcpu->guest_xcr0_loaded) { 713 if (vcpu->arch.xcr0 != host_xcr0) 714 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0); 715 vcpu->guest_xcr0_loaded = 0; 716 } 717 } 718 719 static int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr) 720 { 721 u64 xcr0 = xcr; 722 u64 old_xcr0 = vcpu->arch.xcr0; 723 u64 valid_bits; 724 725 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */ 726 if (index != XCR_XFEATURE_ENABLED_MASK) 727 return 1; 728 if (!(xcr0 & XFEATURE_MASK_FP)) 729 return 1; 730 if ((xcr0 & XFEATURE_MASK_YMM) && !(xcr0 & XFEATURE_MASK_SSE)) 731 return 1; 732 733 /* 734 * Do not allow the guest to set bits that we do not support 735 * saving. However, xcr0 bit 0 is always set, even if the 736 * emulated CPU does not support XSAVE (see fx_init). 737 */ 738 valid_bits = vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FP; 739 if (xcr0 & ~valid_bits) 740 return 1; 741 742 if ((!(xcr0 & XFEATURE_MASK_BNDREGS)) != 743 (!(xcr0 & XFEATURE_MASK_BNDCSR))) 744 return 1; 745 746 if (xcr0 & XFEATURE_MASK_AVX512) { 747 if (!(xcr0 & XFEATURE_MASK_YMM)) 748 return 1; 749 if ((xcr0 & XFEATURE_MASK_AVX512) != XFEATURE_MASK_AVX512) 750 return 1; 751 } 752 vcpu->arch.xcr0 = xcr0; 753 754 if ((xcr0 ^ old_xcr0) & XFEATURE_MASK_EXTEND) 755 kvm_update_cpuid(vcpu); 756 return 0; 757 } 758 759 int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr) 760 { 761 if (kvm_x86_ops->get_cpl(vcpu) != 0 || 762 __kvm_set_xcr(vcpu, index, xcr)) { 763 kvm_inject_gp(vcpu, 0); 764 return 1; 765 } 766 return 0; 767 } 768 EXPORT_SYMBOL_GPL(kvm_set_xcr); 769 770 int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4) 771 { 772 unsigned long old_cr4 = kvm_read_cr4(vcpu); 773 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE | 774 X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE; 775 776 if (cr4 & CR4_RESERVED_BITS) 777 return 1; 778 779 if (!guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) && (cr4 & X86_CR4_OSXSAVE)) 780 return 1; 781 782 if (!guest_cpuid_has(vcpu, X86_FEATURE_SMEP) && (cr4 & X86_CR4_SMEP)) 783 return 1; 784 785 if (!guest_cpuid_has(vcpu, X86_FEATURE_SMAP) && (cr4 & X86_CR4_SMAP)) 786 return 1; 787 788 if (!guest_cpuid_has(vcpu, X86_FEATURE_FSGSBASE) && (cr4 & X86_CR4_FSGSBASE)) 789 return 1; 790 791 if (!guest_cpuid_has(vcpu, X86_FEATURE_PKU) && (cr4 & X86_CR4_PKE)) 792 return 1; 793 794 if (!guest_cpuid_has(vcpu, X86_FEATURE_LA57) && (cr4 & X86_CR4_LA57)) 795 return 1; 796 797 if (is_long_mode(vcpu)) { 798 if (!(cr4 & X86_CR4_PAE)) 799 return 1; 800 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE) 801 && ((cr4 ^ old_cr4) & pdptr_bits) 802 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu, 803 kvm_read_cr3(vcpu))) 804 return 1; 805 806 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) { 807 if (!guest_cpuid_has(vcpu, X86_FEATURE_PCID)) 808 return 1; 809 810 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */ 811 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu)) 812 return 1; 813 } 814 815 if (kvm_x86_ops->set_cr4(vcpu, cr4)) 816 return 1; 817 818 if (((cr4 ^ old_cr4) & pdptr_bits) || 819 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE))) 820 kvm_mmu_reset_context(vcpu); 821 822 if ((cr4 ^ old_cr4) & (X86_CR4_OSXSAVE | X86_CR4_PKE)) 823 kvm_update_cpuid(vcpu); 824 825 return 0; 826 } 827 EXPORT_SYMBOL_GPL(kvm_set_cr4); 828 829 int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3) 830 { 831 #ifdef CONFIG_X86_64 832 cr3 &= ~CR3_PCID_INVD; 833 #endif 834 835 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) { 836 kvm_mmu_sync_roots(vcpu); 837 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu); 838 return 0; 839 } 840 841 if (is_long_mode(vcpu) && 842 (cr3 & rsvd_bits(cpuid_maxphyaddr(vcpu), 62))) 843 return 1; 844 else if (is_pae(vcpu) && is_paging(vcpu) && 845 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3)) 846 return 1; 847 848 vcpu->arch.cr3 = cr3; 849 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail); 850 kvm_mmu_new_cr3(vcpu); 851 return 0; 852 } 853 EXPORT_SYMBOL_GPL(kvm_set_cr3); 854 855 int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8) 856 { 857 if (cr8 & CR8_RESERVED_BITS) 858 return 1; 859 if (lapic_in_kernel(vcpu)) 860 kvm_lapic_set_tpr(vcpu, cr8); 861 else 862 vcpu->arch.cr8 = cr8; 863 return 0; 864 } 865 EXPORT_SYMBOL_GPL(kvm_set_cr8); 866 867 unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu) 868 { 869 if (lapic_in_kernel(vcpu)) 870 return kvm_lapic_get_cr8(vcpu); 871 else 872 return vcpu->arch.cr8; 873 } 874 EXPORT_SYMBOL_GPL(kvm_get_cr8); 875 876 static void kvm_update_dr0123(struct kvm_vcpu *vcpu) 877 { 878 int i; 879 880 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) { 881 for (i = 0; i < KVM_NR_DB_REGS; i++) 882 vcpu->arch.eff_db[i] = vcpu->arch.db[i]; 883 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_RELOAD; 884 } 885 } 886 887 static void kvm_update_dr6(struct kvm_vcpu *vcpu) 888 { 889 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) 890 kvm_x86_ops->set_dr6(vcpu, vcpu->arch.dr6); 891 } 892 893 static void kvm_update_dr7(struct kvm_vcpu *vcpu) 894 { 895 unsigned long dr7; 896 897 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) 898 dr7 = vcpu->arch.guest_debug_dr7; 899 else 900 dr7 = vcpu->arch.dr7; 901 kvm_x86_ops->set_dr7(vcpu, dr7); 902 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED; 903 if (dr7 & DR7_BP_EN_MASK) 904 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED; 905 } 906 907 static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu) 908 { 909 u64 fixed = DR6_FIXED_1; 910 911 if (!guest_cpuid_has(vcpu, X86_FEATURE_RTM)) 912 fixed |= DR6_RTM; 913 return fixed; 914 } 915 916 static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val) 917 { 918 switch (dr) { 919 case 0 ... 3: 920 vcpu->arch.db[dr] = val; 921 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) 922 vcpu->arch.eff_db[dr] = val; 923 break; 924 case 4: 925 /* fall through */ 926 case 6: 927 if (val & 0xffffffff00000000ULL) 928 return -1; /* #GP */ 929 vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu); 930 kvm_update_dr6(vcpu); 931 break; 932 case 5: 933 /* fall through */ 934 default: /* 7 */ 935 if (val & 0xffffffff00000000ULL) 936 return -1; /* #GP */ 937 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1; 938 kvm_update_dr7(vcpu); 939 break; 940 } 941 942 return 0; 943 } 944 945 int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val) 946 { 947 if (__kvm_set_dr(vcpu, dr, val)) { 948 kvm_inject_gp(vcpu, 0); 949 return 1; 950 } 951 return 0; 952 } 953 EXPORT_SYMBOL_GPL(kvm_set_dr); 954 955 int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val) 956 { 957 switch (dr) { 958 case 0 ... 3: 959 *val = vcpu->arch.db[dr]; 960 break; 961 case 4: 962 /* fall through */ 963 case 6: 964 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) 965 *val = vcpu->arch.dr6; 966 else 967 *val = kvm_x86_ops->get_dr6(vcpu); 968 break; 969 case 5: 970 /* fall through */ 971 default: /* 7 */ 972 *val = vcpu->arch.dr7; 973 break; 974 } 975 return 0; 976 } 977 EXPORT_SYMBOL_GPL(kvm_get_dr); 978 979 bool kvm_rdpmc(struct kvm_vcpu *vcpu) 980 { 981 u32 ecx = kvm_register_read(vcpu, VCPU_REGS_RCX); 982 u64 data; 983 int err; 984 985 err = kvm_pmu_rdpmc(vcpu, ecx, &data); 986 if (err) 987 return err; 988 kvm_register_write(vcpu, VCPU_REGS_RAX, (u32)data); 989 kvm_register_write(vcpu, VCPU_REGS_RDX, data >> 32); 990 return err; 991 } 992 EXPORT_SYMBOL_GPL(kvm_rdpmc); 993 994 /* 995 * List of msr numbers which we expose to userspace through KVM_GET_MSRS 996 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST. 997 * 998 * This list is modified at module load time to reflect the 999 * capabilities of the host cpu. This capabilities test skips MSRs that are 1000 * kvm-specific. Those are put in emulated_msrs; filtering of emulated_msrs 1001 * may depend on host virtualization features rather than host cpu features. 1002 */ 1003 1004 static u32 msrs_to_save[] = { 1005 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP, 1006 MSR_STAR, 1007 #ifdef CONFIG_X86_64 1008 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR, 1009 #endif 1010 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA, 1011 MSR_IA32_FEATURE_CONTROL, MSR_IA32_BNDCFGS, MSR_TSC_AUX, 1012 }; 1013 1014 static unsigned num_msrs_to_save; 1015 1016 static u32 emulated_msrs[] = { 1017 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK, 1018 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW, 1019 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL, 1020 HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC, 1021 HV_X64_MSR_TSC_FREQUENCY, HV_X64_MSR_APIC_FREQUENCY, 1022 HV_X64_MSR_CRASH_P0, HV_X64_MSR_CRASH_P1, HV_X64_MSR_CRASH_P2, 1023 HV_X64_MSR_CRASH_P3, HV_X64_MSR_CRASH_P4, HV_X64_MSR_CRASH_CTL, 1024 HV_X64_MSR_RESET, 1025 HV_X64_MSR_VP_INDEX, 1026 HV_X64_MSR_VP_RUNTIME, 1027 HV_X64_MSR_SCONTROL, 1028 HV_X64_MSR_STIMER0_CONFIG, 1029 HV_X64_MSR_APIC_ASSIST_PAGE, MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME, 1030 MSR_KVM_PV_EOI_EN, 1031 1032 MSR_IA32_TSC_ADJUST, 1033 MSR_IA32_TSCDEADLINE, 1034 MSR_IA32_MISC_ENABLE, 1035 MSR_IA32_MCG_STATUS, 1036 MSR_IA32_MCG_CTL, 1037 MSR_IA32_MCG_EXT_CTL, 1038 MSR_IA32_SMBASE, 1039 MSR_PLATFORM_INFO, 1040 MSR_MISC_FEATURES_ENABLES, 1041 }; 1042 1043 static unsigned num_emulated_msrs; 1044 1045 bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer) 1046 { 1047 if (efer & efer_reserved_bits) 1048 return false; 1049 1050 if (efer & EFER_FFXSR && !guest_cpuid_has(vcpu, X86_FEATURE_FXSR_OPT)) 1051 return false; 1052 1053 if (efer & EFER_SVME && !guest_cpuid_has(vcpu, X86_FEATURE_SVM)) 1054 return false; 1055 1056 return true; 1057 } 1058 EXPORT_SYMBOL_GPL(kvm_valid_efer); 1059 1060 static int set_efer(struct kvm_vcpu *vcpu, u64 efer) 1061 { 1062 u64 old_efer = vcpu->arch.efer; 1063 1064 if (!kvm_valid_efer(vcpu, efer)) 1065 return 1; 1066 1067 if (is_paging(vcpu) 1068 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME)) 1069 return 1; 1070 1071 efer &= ~EFER_LMA; 1072 efer |= vcpu->arch.efer & EFER_LMA; 1073 1074 kvm_x86_ops->set_efer(vcpu, efer); 1075 1076 /* Update reserved bits */ 1077 if ((efer ^ old_efer) & EFER_NX) 1078 kvm_mmu_reset_context(vcpu); 1079 1080 return 0; 1081 } 1082 1083 void kvm_enable_efer_bits(u64 mask) 1084 { 1085 efer_reserved_bits &= ~mask; 1086 } 1087 EXPORT_SYMBOL_GPL(kvm_enable_efer_bits); 1088 1089 /* 1090 * Writes msr value into into the appropriate "register". 1091 * Returns 0 on success, non-0 otherwise. 1092 * Assumes vcpu_load() was already called. 1093 */ 1094 int kvm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr) 1095 { 1096 switch (msr->index) { 1097 case MSR_FS_BASE: 1098 case MSR_GS_BASE: 1099 case MSR_KERNEL_GS_BASE: 1100 case MSR_CSTAR: 1101 case MSR_LSTAR: 1102 if (is_noncanonical_address(msr->data, vcpu)) 1103 return 1; 1104 break; 1105 case MSR_IA32_SYSENTER_EIP: 1106 case MSR_IA32_SYSENTER_ESP: 1107 /* 1108 * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if 1109 * non-canonical address is written on Intel but not on 1110 * AMD (which ignores the top 32-bits, because it does 1111 * not implement 64-bit SYSENTER). 1112 * 1113 * 64-bit code should hence be able to write a non-canonical 1114 * value on AMD. Making the address canonical ensures that 1115 * vmentry does not fail on Intel after writing a non-canonical 1116 * value, and that something deterministic happens if the guest 1117 * invokes 64-bit SYSENTER. 1118 */ 1119 msr->data = get_canonical(msr->data, vcpu_virt_addr_bits(vcpu)); 1120 } 1121 return kvm_x86_ops->set_msr(vcpu, msr); 1122 } 1123 EXPORT_SYMBOL_GPL(kvm_set_msr); 1124 1125 /* 1126 * Adapt set_msr() to msr_io()'s calling convention 1127 */ 1128 static int do_get_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data) 1129 { 1130 struct msr_data msr; 1131 int r; 1132 1133 msr.index = index; 1134 msr.host_initiated = true; 1135 r = kvm_get_msr(vcpu, &msr); 1136 if (r) 1137 return r; 1138 1139 *data = msr.data; 1140 return 0; 1141 } 1142 1143 static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data) 1144 { 1145 struct msr_data msr; 1146 1147 msr.data = *data; 1148 msr.index = index; 1149 msr.host_initiated = true; 1150 return kvm_set_msr(vcpu, &msr); 1151 } 1152 1153 #ifdef CONFIG_X86_64 1154 struct pvclock_gtod_data { 1155 seqcount_t seq; 1156 1157 struct { /* extract of a clocksource struct */ 1158 int vclock_mode; 1159 u64 cycle_last; 1160 u64 mask; 1161 u32 mult; 1162 u32 shift; 1163 } clock; 1164 1165 u64 boot_ns; 1166 u64 nsec_base; 1167 u64 wall_time_sec; 1168 }; 1169 1170 static struct pvclock_gtod_data pvclock_gtod_data; 1171 1172 static void update_pvclock_gtod(struct timekeeper *tk) 1173 { 1174 struct pvclock_gtod_data *vdata = &pvclock_gtod_data; 1175 u64 boot_ns; 1176 1177 boot_ns = ktime_to_ns(ktime_add(tk->tkr_mono.base, tk->offs_boot)); 1178 1179 write_seqcount_begin(&vdata->seq); 1180 1181 /* copy pvclock gtod data */ 1182 vdata->clock.vclock_mode = tk->tkr_mono.clock->archdata.vclock_mode; 1183 vdata->clock.cycle_last = tk->tkr_mono.cycle_last; 1184 vdata->clock.mask = tk->tkr_mono.mask; 1185 vdata->clock.mult = tk->tkr_mono.mult; 1186 vdata->clock.shift = tk->tkr_mono.shift; 1187 1188 vdata->boot_ns = boot_ns; 1189 vdata->nsec_base = tk->tkr_mono.xtime_nsec; 1190 1191 vdata->wall_time_sec = tk->xtime_sec; 1192 1193 write_seqcount_end(&vdata->seq); 1194 } 1195 #endif 1196 1197 void kvm_set_pending_timer(struct kvm_vcpu *vcpu) 1198 { 1199 /* 1200 * Note: KVM_REQ_PENDING_TIMER is implicitly checked in 1201 * vcpu_enter_guest. This function is only called from 1202 * the physical CPU that is running vcpu. 1203 */ 1204 kvm_make_request(KVM_REQ_PENDING_TIMER, vcpu); 1205 } 1206 1207 static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock) 1208 { 1209 int version; 1210 int r; 1211 struct pvclock_wall_clock wc; 1212 struct timespec64 boot; 1213 1214 if (!wall_clock) 1215 return; 1216 1217 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version)); 1218 if (r) 1219 return; 1220 1221 if (version & 1) 1222 ++version; /* first time write, random junk */ 1223 1224 ++version; 1225 1226 if (kvm_write_guest(kvm, wall_clock, &version, sizeof(version))) 1227 return; 1228 1229 /* 1230 * The guest calculates current wall clock time by adding 1231 * system time (updated by kvm_guest_time_update below) to the 1232 * wall clock specified here. guest system time equals host 1233 * system time for us, thus we must fill in host boot time here. 1234 */ 1235 getboottime64(&boot); 1236 1237 if (kvm->arch.kvmclock_offset) { 1238 struct timespec64 ts = ns_to_timespec64(kvm->arch.kvmclock_offset); 1239 boot = timespec64_sub(boot, ts); 1240 } 1241 wc.sec = (u32)boot.tv_sec; /* overflow in 2106 guest time */ 1242 wc.nsec = boot.tv_nsec; 1243 wc.version = version; 1244 1245 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc)); 1246 1247 version++; 1248 kvm_write_guest(kvm, wall_clock, &version, sizeof(version)); 1249 } 1250 1251 static uint32_t div_frac(uint32_t dividend, uint32_t divisor) 1252 { 1253 do_shl32_div32(dividend, divisor); 1254 return dividend; 1255 } 1256 1257 static void kvm_get_time_scale(uint64_t scaled_hz, uint64_t base_hz, 1258 s8 *pshift, u32 *pmultiplier) 1259 { 1260 uint64_t scaled64; 1261 int32_t shift = 0; 1262 uint64_t tps64; 1263 uint32_t tps32; 1264 1265 tps64 = base_hz; 1266 scaled64 = scaled_hz; 1267 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) { 1268 tps64 >>= 1; 1269 shift--; 1270 } 1271 1272 tps32 = (uint32_t)tps64; 1273 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) { 1274 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000) 1275 scaled64 >>= 1; 1276 else 1277 tps32 <<= 1; 1278 shift++; 1279 } 1280 1281 *pshift = shift; 1282 *pmultiplier = div_frac(scaled64, tps32); 1283 1284 pr_debug("%s: base_hz %llu => %llu, shift %d, mul %u\n", 1285 __func__, base_hz, scaled_hz, shift, *pmultiplier); 1286 } 1287 1288 #ifdef CONFIG_X86_64 1289 static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0); 1290 #endif 1291 1292 static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz); 1293 static unsigned long max_tsc_khz; 1294 1295 static u32 adjust_tsc_khz(u32 khz, s32 ppm) 1296 { 1297 u64 v = (u64)khz * (1000000 + ppm); 1298 do_div(v, 1000000); 1299 return v; 1300 } 1301 1302 static int set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale) 1303 { 1304 u64 ratio; 1305 1306 /* Guest TSC same frequency as host TSC? */ 1307 if (!scale) { 1308 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio; 1309 return 0; 1310 } 1311 1312 /* TSC scaling supported? */ 1313 if (!kvm_has_tsc_control) { 1314 if (user_tsc_khz > tsc_khz) { 1315 vcpu->arch.tsc_catchup = 1; 1316 vcpu->arch.tsc_always_catchup = 1; 1317 return 0; 1318 } else { 1319 WARN(1, "user requested TSC rate below hardware speed\n"); 1320 return -1; 1321 } 1322 } 1323 1324 /* TSC scaling required - calculate ratio */ 1325 ratio = mul_u64_u32_div(1ULL << kvm_tsc_scaling_ratio_frac_bits, 1326 user_tsc_khz, tsc_khz); 1327 1328 if (ratio == 0 || ratio >= kvm_max_tsc_scaling_ratio) { 1329 WARN_ONCE(1, "Invalid TSC scaling ratio - virtual-tsc-khz=%u\n", 1330 user_tsc_khz); 1331 return -1; 1332 } 1333 1334 vcpu->arch.tsc_scaling_ratio = ratio; 1335 return 0; 1336 } 1337 1338 static int kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz) 1339 { 1340 u32 thresh_lo, thresh_hi; 1341 int use_scaling = 0; 1342 1343 /* tsc_khz can be zero if TSC calibration fails */ 1344 if (user_tsc_khz == 0) { 1345 /* set tsc_scaling_ratio to a safe value */ 1346 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio; 1347 return -1; 1348 } 1349 1350 /* Compute a scale to convert nanoseconds in TSC cycles */ 1351 kvm_get_time_scale(user_tsc_khz * 1000LL, NSEC_PER_SEC, 1352 &vcpu->arch.virtual_tsc_shift, 1353 &vcpu->arch.virtual_tsc_mult); 1354 vcpu->arch.virtual_tsc_khz = user_tsc_khz; 1355 1356 /* 1357 * Compute the variation in TSC rate which is acceptable 1358 * within the range of tolerance and decide if the 1359 * rate being applied is within that bounds of the hardware 1360 * rate. If so, no scaling or compensation need be done. 1361 */ 1362 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm); 1363 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm); 1364 if (user_tsc_khz < thresh_lo || user_tsc_khz > thresh_hi) { 1365 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", user_tsc_khz, thresh_lo, thresh_hi); 1366 use_scaling = 1; 1367 } 1368 return set_tsc_khz(vcpu, user_tsc_khz, use_scaling); 1369 } 1370 1371 static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns) 1372 { 1373 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec, 1374 vcpu->arch.virtual_tsc_mult, 1375 vcpu->arch.virtual_tsc_shift); 1376 tsc += vcpu->arch.this_tsc_write; 1377 return tsc; 1378 } 1379 1380 static void kvm_track_tsc_matching(struct kvm_vcpu *vcpu) 1381 { 1382 #ifdef CONFIG_X86_64 1383 bool vcpus_matched; 1384 struct kvm_arch *ka = &vcpu->kvm->arch; 1385 struct pvclock_gtod_data *gtod = &pvclock_gtod_data; 1386 1387 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 == 1388 atomic_read(&vcpu->kvm->online_vcpus)); 1389 1390 /* 1391 * Once the masterclock is enabled, always perform request in 1392 * order to update it. 1393 * 1394 * In order to enable masterclock, the host clocksource must be TSC 1395 * and the vcpus need to have matched TSCs. When that happens, 1396 * perform request to enable masterclock. 1397 */ 1398 if (ka->use_master_clock || 1399 (gtod->clock.vclock_mode == VCLOCK_TSC && vcpus_matched)) 1400 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu); 1401 1402 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc, 1403 atomic_read(&vcpu->kvm->online_vcpus), 1404 ka->use_master_clock, gtod->clock.vclock_mode); 1405 #endif 1406 } 1407 1408 static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset) 1409 { 1410 u64 curr_offset = vcpu->arch.tsc_offset; 1411 vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset; 1412 } 1413 1414 /* 1415 * Multiply tsc by a fixed point number represented by ratio. 1416 * 1417 * The most significant 64-N bits (mult) of ratio represent the 1418 * integral part of the fixed point number; the remaining N bits 1419 * (frac) represent the fractional part, ie. ratio represents a fixed 1420 * point number (mult + frac * 2^(-N)). 1421 * 1422 * N equals to kvm_tsc_scaling_ratio_frac_bits. 1423 */ 1424 static inline u64 __scale_tsc(u64 ratio, u64 tsc) 1425 { 1426 return mul_u64_u64_shr(tsc, ratio, kvm_tsc_scaling_ratio_frac_bits); 1427 } 1428 1429 u64 kvm_scale_tsc(struct kvm_vcpu *vcpu, u64 tsc) 1430 { 1431 u64 _tsc = tsc; 1432 u64 ratio = vcpu->arch.tsc_scaling_ratio; 1433 1434 if (ratio != kvm_default_tsc_scaling_ratio) 1435 _tsc = __scale_tsc(ratio, tsc); 1436 1437 return _tsc; 1438 } 1439 EXPORT_SYMBOL_GPL(kvm_scale_tsc); 1440 1441 static u64 kvm_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc) 1442 { 1443 u64 tsc; 1444 1445 tsc = kvm_scale_tsc(vcpu, rdtsc()); 1446 1447 return target_tsc - tsc; 1448 } 1449 1450 u64 kvm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc) 1451 { 1452 return vcpu->arch.tsc_offset + kvm_scale_tsc(vcpu, host_tsc); 1453 } 1454 EXPORT_SYMBOL_GPL(kvm_read_l1_tsc); 1455 1456 static void kvm_vcpu_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset) 1457 { 1458 kvm_x86_ops->write_tsc_offset(vcpu, offset); 1459 vcpu->arch.tsc_offset = offset; 1460 } 1461 1462 void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr) 1463 { 1464 struct kvm *kvm = vcpu->kvm; 1465 u64 offset, ns, elapsed; 1466 unsigned long flags; 1467 bool matched; 1468 bool already_matched; 1469 u64 data = msr->data; 1470 bool synchronizing = false; 1471 1472 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags); 1473 offset = kvm_compute_tsc_offset(vcpu, data); 1474 ns = ktime_get_boot_ns(); 1475 elapsed = ns - kvm->arch.last_tsc_nsec; 1476 1477 if (vcpu->arch.virtual_tsc_khz) { 1478 if (data == 0 && msr->host_initiated) { 1479 /* 1480 * detection of vcpu initialization -- need to sync 1481 * with other vCPUs. This particularly helps to keep 1482 * kvm_clock stable after CPU hotplug 1483 */ 1484 synchronizing = true; 1485 } else { 1486 u64 tsc_exp = kvm->arch.last_tsc_write + 1487 nsec_to_cycles(vcpu, elapsed); 1488 u64 tsc_hz = vcpu->arch.virtual_tsc_khz * 1000LL; 1489 /* 1490 * Special case: TSC write with a small delta (1 second) 1491 * of virtual cycle time against real time is 1492 * interpreted as an attempt to synchronize the CPU. 1493 */ 1494 synchronizing = data < tsc_exp + tsc_hz && 1495 data + tsc_hz > tsc_exp; 1496 } 1497 } 1498 1499 /* 1500 * For a reliable TSC, we can match TSC offsets, and for an unstable 1501 * TSC, we add elapsed time in this computation. We could let the 1502 * compensation code attempt to catch up if we fall behind, but 1503 * it's better to try to match offsets from the beginning. 1504 */ 1505 if (synchronizing && 1506 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) { 1507 if (!check_tsc_unstable()) { 1508 offset = kvm->arch.cur_tsc_offset; 1509 pr_debug("kvm: matched tsc offset for %llu\n", data); 1510 } else { 1511 u64 delta = nsec_to_cycles(vcpu, elapsed); 1512 data += delta; 1513 offset = kvm_compute_tsc_offset(vcpu, data); 1514 pr_debug("kvm: adjusted tsc offset by %llu\n", delta); 1515 } 1516 matched = true; 1517 already_matched = (vcpu->arch.this_tsc_generation == kvm->arch.cur_tsc_generation); 1518 } else { 1519 /* 1520 * We split periods of matched TSC writes into generations. 1521 * For each generation, we track the original measured 1522 * nanosecond time, offset, and write, so if TSCs are in 1523 * sync, we can match exact offset, and if not, we can match 1524 * exact software computation in compute_guest_tsc() 1525 * 1526 * These values are tracked in kvm->arch.cur_xxx variables. 1527 */ 1528 kvm->arch.cur_tsc_generation++; 1529 kvm->arch.cur_tsc_nsec = ns; 1530 kvm->arch.cur_tsc_write = data; 1531 kvm->arch.cur_tsc_offset = offset; 1532 matched = false; 1533 pr_debug("kvm: new tsc generation %llu, clock %llu\n", 1534 kvm->arch.cur_tsc_generation, data); 1535 } 1536 1537 /* 1538 * We also track th most recent recorded KHZ, write and time to 1539 * allow the matching interval to be extended at each write. 1540 */ 1541 kvm->arch.last_tsc_nsec = ns; 1542 kvm->arch.last_tsc_write = data; 1543 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz; 1544 1545 vcpu->arch.last_guest_tsc = data; 1546 1547 /* Keep track of which generation this VCPU has synchronized to */ 1548 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation; 1549 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec; 1550 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write; 1551 1552 if (!msr->host_initiated && guest_cpuid_has(vcpu, X86_FEATURE_TSC_ADJUST)) 1553 update_ia32_tsc_adjust_msr(vcpu, offset); 1554 1555 kvm_vcpu_write_tsc_offset(vcpu, offset); 1556 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags); 1557 1558 spin_lock(&kvm->arch.pvclock_gtod_sync_lock); 1559 if (!matched) { 1560 kvm->arch.nr_vcpus_matched_tsc = 0; 1561 } else if (!already_matched) { 1562 kvm->arch.nr_vcpus_matched_tsc++; 1563 } 1564 1565 kvm_track_tsc_matching(vcpu); 1566 spin_unlock(&kvm->arch.pvclock_gtod_sync_lock); 1567 } 1568 1569 EXPORT_SYMBOL_GPL(kvm_write_tsc); 1570 1571 static inline void adjust_tsc_offset_guest(struct kvm_vcpu *vcpu, 1572 s64 adjustment) 1573 { 1574 kvm_vcpu_write_tsc_offset(vcpu, vcpu->arch.tsc_offset + adjustment); 1575 } 1576 1577 static inline void adjust_tsc_offset_host(struct kvm_vcpu *vcpu, s64 adjustment) 1578 { 1579 if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio) 1580 WARN_ON(adjustment < 0); 1581 adjustment = kvm_scale_tsc(vcpu, (u64) adjustment); 1582 adjust_tsc_offset_guest(vcpu, adjustment); 1583 } 1584 1585 #ifdef CONFIG_X86_64 1586 1587 static u64 read_tsc(void) 1588 { 1589 u64 ret = (u64)rdtsc_ordered(); 1590 u64 last = pvclock_gtod_data.clock.cycle_last; 1591 1592 if (likely(ret >= last)) 1593 return ret; 1594 1595 /* 1596 * GCC likes to generate cmov here, but this branch is extremely 1597 * predictable (it's just a function of time and the likely is 1598 * very likely) and there's a data dependence, so force GCC 1599 * to generate a branch instead. I don't barrier() because 1600 * we don't actually need a barrier, and if this function 1601 * ever gets inlined it will generate worse code. 1602 */ 1603 asm volatile (""); 1604 return last; 1605 } 1606 1607 static inline u64 vgettsc(u64 *cycle_now) 1608 { 1609 long v; 1610 struct pvclock_gtod_data *gtod = &pvclock_gtod_data; 1611 1612 *cycle_now = read_tsc(); 1613 1614 v = (*cycle_now - gtod->clock.cycle_last) & gtod->clock.mask; 1615 return v * gtod->clock.mult; 1616 } 1617 1618 static int do_monotonic_boot(s64 *t, u64 *cycle_now) 1619 { 1620 struct pvclock_gtod_data *gtod = &pvclock_gtod_data; 1621 unsigned long seq; 1622 int mode; 1623 u64 ns; 1624 1625 do { 1626 seq = read_seqcount_begin(>od->seq); 1627 mode = gtod->clock.vclock_mode; 1628 ns = gtod->nsec_base; 1629 ns += vgettsc(cycle_now); 1630 ns >>= gtod->clock.shift; 1631 ns += gtod->boot_ns; 1632 } while (unlikely(read_seqcount_retry(>od->seq, seq))); 1633 *t = ns; 1634 1635 return mode; 1636 } 1637 1638 static int do_realtime(struct timespec *ts, u64 *cycle_now) 1639 { 1640 struct pvclock_gtod_data *gtod = &pvclock_gtod_data; 1641 unsigned long seq; 1642 int mode; 1643 u64 ns; 1644 1645 do { 1646 seq = read_seqcount_begin(>od->seq); 1647 mode = gtod->clock.vclock_mode; 1648 ts->tv_sec = gtod->wall_time_sec; 1649 ns = gtod->nsec_base; 1650 ns += vgettsc(cycle_now); 1651 ns >>= gtod->clock.shift; 1652 } while (unlikely(read_seqcount_retry(>od->seq, seq))); 1653 1654 ts->tv_sec += __iter_div_u64_rem(ns, NSEC_PER_SEC, &ns); 1655 ts->tv_nsec = ns; 1656 1657 return mode; 1658 } 1659 1660 /* returns true if host is using tsc clocksource */ 1661 static bool kvm_get_time_and_clockread(s64 *kernel_ns, u64 *cycle_now) 1662 { 1663 /* checked again under seqlock below */ 1664 if (pvclock_gtod_data.clock.vclock_mode != VCLOCK_TSC) 1665 return false; 1666 1667 return do_monotonic_boot(kernel_ns, cycle_now) == VCLOCK_TSC; 1668 } 1669 1670 /* returns true if host is using tsc clocksource */ 1671 static bool kvm_get_walltime_and_clockread(struct timespec *ts, 1672 u64 *cycle_now) 1673 { 1674 /* checked again under seqlock below */ 1675 if (pvclock_gtod_data.clock.vclock_mode != VCLOCK_TSC) 1676 return false; 1677 1678 return do_realtime(ts, cycle_now) == VCLOCK_TSC; 1679 } 1680 #endif 1681 1682 /* 1683 * 1684 * Assuming a stable TSC across physical CPUS, and a stable TSC 1685 * across virtual CPUs, the following condition is possible. 1686 * Each numbered line represents an event visible to both 1687 * CPUs at the next numbered event. 1688 * 1689 * "timespecX" represents host monotonic time. "tscX" represents 1690 * RDTSC value. 1691 * 1692 * VCPU0 on CPU0 | VCPU1 on CPU1 1693 * 1694 * 1. read timespec0,tsc0 1695 * 2. | timespec1 = timespec0 + N 1696 * | tsc1 = tsc0 + M 1697 * 3. transition to guest | transition to guest 1698 * 4. ret0 = timespec0 + (rdtsc - tsc0) | 1699 * 5. | ret1 = timespec1 + (rdtsc - tsc1) 1700 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M)) 1701 * 1702 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity: 1703 * 1704 * - ret0 < ret1 1705 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M)) 1706 * ... 1707 * - 0 < N - M => M < N 1708 * 1709 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not 1710 * always the case (the difference between two distinct xtime instances 1711 * might be smaller then the difference between corresponding TSC reads, 1712 * when updating guest vcpus pvclock areas). 1713 * 1714 * To avoid that problem, do not allow visibility of distinct 1715 * system_timestamp/tsc_timestamp values simultaneously: use a master 1716 * copy of host monotonic time values. Update that master copy 1717 * in lockstep. 1718 * 1719 * Rely on synchronization of host TSCs and guest TSCs for monotonicity. 1720 * 1721 */ 1722 1723 static void pvclock_update_vm_gtod_copy(struct kvm *kvm) 1724 { 1725 #ifdef CONFIG_X86_64 1726 struct kvm_arch *ka = &kvm->arch; 1727 int vclock_mode; 1728 bool host_tsc_clocksource, vcpus_matched; 1729 1730 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 == 1731 atomic_read(&kvm->online_vcpus)); 1732 1733 /* 1734 * If the host uses TSC clock, then passthrough TSC as stable 1735 * to the guest. 1736 */ 1737 host_tsc_clocksource = kvm_get_time_and_clockread( 1738 &ka->master_kernel_ns, 1739 &ka->master_cycle_now); 1740 1741 ka->use_master_clock = host_tsc_clocksource && vcpus_matched 1742 && !ka->backwards_tsc_observed 1743 && !ka->boot_vcpu_runs_old_kvmclock; 1744 1745 if (ka->use_master_clock) 1746 atomic_set(&kvm_guest_has_master_clock, 1); 1747 1748 vclock_mode = pvclock_gtod_data.clock.vclock_mode; 1749 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode, 1750 vcpus_matched); 1751 #endif 1752 } 1753 1754 void kvm_make_mclock_inprogress_request(struct kvm *kvm) 1755 { 1756 kvm_make_all_cpus_request(kvm, KVM_REQ_MCLOCK_INPROGRESS); 1757 } 1758 1759 static void kvm_gen_update_masterclock(struct kvm *kvm) 1760 { 1761 #ifdef CONFIG_X86_64 1762 int i; 1763 struct kvm_vcpu *vcpu; 1764 struct kvm_arch *ka = &kvm->arch; 1765 1766 spin_lock(&ka->pvclock_gtod_sync_lock); 1767 kvm_make_mclock_inprogress_request(kvm); 1768 /* no guest entries from this point */ 1769 pvclock_update_vm_gtod_copy(kvm); 1770 1771 kvm_for_each_vcpu(i, vcpu, kvm) 1772 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 1773 1774 /* guest entries allowed */ 1775 kvm_for_each_vcpu(i, vcpu, kvm) 1776 kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu); 1777 1778 spin_unlock(&ka->pvclock_gtod_sync_lock); 1779 #endif 1780 } 1781 1782 u64 get_kvmclock_ns(struct kvm *kvm) 1783 { 1784 struct kvm_arch *ka = &kvm->arch; 1785 struct pvclock_vcpu_time_info hv_clock; 1786 u64 ret; 1787 1788 spin_lock(&ka->pvclock_gtod_sync_lock); 1789 if (!ka->use_master_clock) { 1790 spin_unlock(&ka->pvclock_gtod_sync_lock); 1791 return ktime_get_boot_ns() + ka->kvmclock_offset; 1792 } 1793 1794 hv_clock.tsc_timestamp = ka->master_cycle_now; 1795 hv_clock.system_time = ka->master_kernel_ns + ka->kvmclock_offset; 1796 spin_unlock(&ka->pvclock_gtod_sync_lock); 1797 1798 /* both __this_cpu_read() and rdtsc() should be on the same cpu */ 1799 get_cpu(); 1800 1801 if (__this_cpu_read(cpu_tsc_khz)) { 1802 kvm_get_time_scale(NSEC_PER_SEC, __this_cpu_read(cpu_tsc_khz) * 1000LL, 1803 &hv_clock.tsc_shift, 1804 &hv_clock.tsc_to_system_mul); 1805 ret = __pvclock_read_cycles(&hv_clock, rdtsc()); 1806 } else 1807 ret = ktime_get_boot_ns() + ka->kvmclock_offset; 1808 1809 put_cpu(); 1810 1811 return ret; 1812 } 1813 1814 static void kvm_setup_pvclock_page(struct kvm_vcpu *v) 1815 { 1816 struct kvm_vcpu_arch *vcpu = &v->arch; 1817 struct pvclock_vcpu_time_info guest_hv_clock; 1818 1819 if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time, 1820 &guest_hv_clock, sizeof(guest_hv_clock)))) 1821 return; 1822 1823 /* This VCPU is paused, but it's legal for a guest to read another 1824 * VCPU's kvmclock, so we really have to follow the specification where 1825 * it says that version is odd if data is being modified, and even after 1826 * it is consistent. 1827 * 1828 * Version field updates must be kept separate. This is because 1829 * kvm_write_guest_cached might use a "rep movs" instruction, and 1830 * writes within a string instruction are weakly ordered. So there 1831 * are three writes overall. 1832 * 1833 * As a small optimization, only write the version field in the first 1834 * and third write. The vcpu->pv_time cache is still valid, because the 1835 * version field is the first in the struct. 1836 */ 1837 BUILD_BUG_ON(offsetof(struct pvclock_vcpu_time_info, version) != 0); 1838 1839 if (guest_hv_clock.version & 1) 1840 ++guest_hv_clock.version; /* first time write, random junk */ 1841 1842 vcpu->hv_clock.version = guest_hv_clock.version + 1; 1843 kvm_write_guest_cached(v->kvm, &vcpu->pv_time, 1844 &vcpu->hv_clock, 1845 sizeof(vcpu->hv_clock.version)); 1846 1847 smp_wmb(); 1848 1849 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */ 1850 vcpu->hv_clock.flags |= (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED); 1851 1852 if (vcpu->pvclock_set_guest_stopped_request) { 1853 vcpu->hv_clock.flags |= PVCLOCK_GUEST_STOPPED; 1854 vcpu->pvclock_set_guest_stopped_request = false; 1855 } 1856 1857 trace_kvm_pvclock_update(v->vcpu_id, &vcpu->hv_clock); 1858 1859 kvm_write_guest_cached(v->kvm, &vcpu->pv_time, 1860 &vcpu->hv_clock, 1861 sizeof(vcpu->hv_clock)); 1862 1863 smp_wmb(); 1864 1865 vcpu->hv_clock.version++; 1866 kvm_write_guest_cached(v->kvm, &vcpu->pv_time, 1867 &vcpu->hv_clock, 1868 sizeof(vcpu->hv_clock.version)); 1869 } 1870 1871 static int kvm_guest_time_update(struct kvm_vcpu *v) 1872 { 1873 unsigned long flags, tgt_tsc_khz; 1874 struct kvm_vcpu_arch *vcpu = &v->arch; 1875 struct kvm_arch *ka = &v->kvm->arch; 1876 s64 kernel_ns; 1877 u64 tsc_timestamp, host_tsc; 1878 u8 pvclock_flags; 1879 bool use_master_clock; 1880 1881 kernel_ns = 0; 1882 host_tsc = 0; 1883 1884 /* 1885 * If the host uses TSC clock, then passthrough TSC as stable 1886 * to the guest. 1887 */ 1888 spin_lock(&ka->pvclock_gtod_sync_lock); 1889 use_master_clock = ka->use_master_clock; 1890 if (use_master_clock) { 1891 host_tsc = ka->master_cycle_now; 1892 kernel_ns = ka->master_kernel_ns; 1893 } 1894 spin_unlock(&ka->pvclock_gtod_sync_lock); 1895 1896 /* Keep irq disabled to prevent changes to the clock */ 1897 local_irq_save(flags); 1898 tgt_tsc_khz = __this_cpu_read(cpu_tsc_khz); 1899 if (unlikely(tgt_tsc_khz == 0)) { 1900 local_irq_restore(flags); 1901 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v); 1902 return 1; 1903 } 1904 if (!use_master_clock) { 1905 host_tsc = rdtsc(); 1906 kernel_ns = ktime_get_boot_ns(); 1907 } 1908 1909 tsc_timestamp = kvm_read_l1_tsc(v, host_tsc); 1910 1911 /* 1912 * We may have to catch up the TSC to match elapsed wall clock 1913 * time for two reasons, even if kvmclock is used. 1914 * 1) CPU could have been running below the maximum TSC rate 1915 * 2) Broken TSC compensation resets the base at each VCPU 1916 * entry to avoid unknown leaps of TSC even when running 1917 * again on the same CPU. This may cause apparent elapsed 1918 * time to disappear, and the guest to stand still or run 1919 * very slowly. 1920 */ 1921 if (vcpu->tsc_catchup) { 1922 u64 tsc = compute_guest_tsc(v, kernel_ns); 1923 if (tsc > tsc_timestamp) { 1924 adjust_tsc_offset_guest(v, tsc - tsc_timestamp); 1925 tsc_timestamp = tsc; 1926 } 1927 } 1928 1929 local_irq_restore(flags); 1930 1931 /* With all the info we got, fill in the values */ 1932 1933 if (kvm_has_tsc_control) 1934 tgt_tsc_khz = kvm_scale_tsc(v, tgt_tsc_khz); 1935 1936 if (unlikely(vcpu->hw_tsc_khz != tgt_tsc_khz)) { 1937 kvm_get_time_scale(NSEC_PER_SEC, tgt_tsc_khz * 1000LL, 1938 &vcpu->hv_clock.tsc_shift, 1939 &vcpu->hv_clock.tsc_to_system_mul); 1940 vcpu->hw_tsc_khz = tgt_tsc_khz; 1941 } 1942 1943 vcpu->hv_clock.tsc_timestamp = tsc_timestamp; 1944 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset; 1945 vcpu->last_guest_tsc = tsc_timestamp; 1946 1947 /* If the host uses TSC clocksource, then it is stable */ 1948 pvclock_flags = 0; 1949 if (use_master_clock) 1950 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT; 1951 1952 vcpu->hv_clock.flags = pvclock_flags; 1953 1954 if (vcpu->pv_time_enabled) 1955 kvm_setup_pvclock_page(v); 1956 if (v == kvm_get_vcpu(v->kvm, 0)) 1957 kvm_hv_setup_tsc_page(v->kvm, &vcpu->hv_clock); 1958 return 0; 1959 } 1960 1961 /* 1962 * kvmclock updates which are isolated to a given vcpu, such as 1963 * vcpu->cpu migration, should not allow system_timestamp from 1964 * the rest of the vcpus to remain static. Otherwise ntp frequency 1965 * correction applies to one vcpu's system_timestamp but not 1966 * the others. 1967 * 1968 * So in those cases, request a kvmclock update for all vcpus. 1969 * We need to rate-limit these requests though, as they can 1970 * considerably slow guests that have a large number of vcpus. 1971 * The time for a remote vcpu to update its kvmclock is bound 1972 * by the delay we use to rate-limit the updates. 1973 */ 1974 1975 #define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100) 1976 1977 static void kvmclock_update_fn(struct work_struct *work) 1978 { 1979 int i; 1980 struct delayed_work *dwork = to_delayed_work(work); 1981 struct kvm_arch *ka = container_of(dwork, struct kvm_arch, 1982 kvmclock_update_work); 1983 struct kvm *kvm = container_of(ka, struct kvm, arch); 1984 struct kvm_vcpu *vcpu; 1985 1986 kvm_for_each_vcpu(i, vcpu, kvm) { 1987 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 1988 kvm_vcpu_kick(vcpu); 1989 } 1990 } 1991 1992 static void kvm_gen_kvmclock_update(struct kvm_vcpu *v) 1993 { 1994 struct kvm *kvm = v->kvm; 1995 1996 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v); 1997 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 1998 KVMCLOCK_UPDATE_DELAY); 1999 } 2000 2001 #define KVMCLOCK_SYNC_PERIOD (300 * HZ) 2002 2003 static void kvmclock_sync_fn(struct work_struct *work) 2004 { 2005 struct delayed_work *dwork = to_delayed_work(work); 2006 struct kvm_arch *ka = container_of(dwork, struct kvm_arch, 2007 kvmclock_sync_work); 2008 struct kvm *kvm = container_of(ka, struct kvm, arch); 2009 2010 if (!kvmclock_periodic_sync) 2011 return; 2012 2013 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0); 2014 schedule_delayed_work(&kvm->arch.kvmclock_sync_work, 2015 KVMCLOCK_SYNC_PERIOD); 2016 } 2017 2018 static int set_msr_mce(struct kvm_vcpu *vcpu, struct msr_data *msr_info) 2019 { 2020 u64 mcg_cap = vcpu->arch.mcg_cap; 2021 unsigned bank_num = mcg_cap & 0xff; 2022 u32 msr = msr_info->index; 2023 u64 data = msr_info->data; 2024 2025 switch (msr) { 2026 case MSR_IA32_MCG_STATUS: 2027 vcpu->arch.mcg_status = data; 2028 break; 2029 case MSR_IA32_MCG_CTL: 2030 if (!(mcg_cap & MCG_CTL_P)) 2031 return 1; 2032 if (data != 0 && data != ~(u64)0) 2033 return -1; 2034 vcpu->arch.mcg_ctl = data; 2035 break; 2036 default: 2037 if (msr >= MSR_IA32_MC0_CTL && 2038 msr < MSR_IA32_MCx_CTL(bank_num)) { 2039 u32 offset = msr - MSR_IA32_MC0_CTL; 2040 /* only 0 or all 1s can be written to IA32_MCi_CTL 2041 * some Linux kernels though clear bit 10 in bank 4 to 2042 * workaround a BIOS/GART TBL issue on AMD K8s, ignore 2043 * this to avoid an uncatched #GP in the guest 2044 */ 2045 if ((offset & 0x3) == 0 && 2046 data != 0 && (data | (1 << 10)) != ~(u64)0) 2047 return -1; 2048 if (!msr_info->host_initiated && 2049 (offset & 0x3) == 1 && data != 0) 2050 return -1; 2051 vcpu->arch.mce_banks[offset] = data; 2052 break; 2053 } 2054 return 1; 2055 } 2056 return 0; 2057 } 2058 2059 static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data) 2060 { 2061 struct kvm *kvm = vcpu->kvm; 2062 int lm = is_long_mode(vcpu); 2063 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64 2064 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32; 2065 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64 2066 : kvm->arch.xen_hvm_config.blob_size_32; 2067 u32 page_num = data & ~PAGE_MASK; 2068 u64 page_addr = data & PAGE_MASK; 2069 u8 *page; 2070 int r; 2071 2072 r = -E2BIG; 2073 if (page_num >= blob_size) 2074 goto out; 2075 r = -ENOMEM; 2076 page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE); 2077 if (IS_ERR(page)) { 2078 r = PTR_ERR(page); 2079 goto out; 2080 } 2081 if (kvm_vcpu_write_guest(vcpu, page_addr, page, PAGE_SIZE)) 2082 goto out_free; 2083 r = 0; 2084 out_free: 2085 kfree(page); 2086 out: 2087 return r; 2088 } 2089 2090 static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data) 2091 { 2092 gpa_t gpa = data & ~0x3f; 2093 2094 /* Bits 3:5 are reserved, Should be zero */ 2095 if (data & 0x38) 2096 return 1; 2097 2098 vcpu->arch.apf.msr_val = data; 2099 2100 if (!(data & KVM_ASYNC_PF_ENABLED)) { 2101 kvm_clear_async_pf_completion_queue(vcpu); 2102 kvm_async_pf_hash_reset(vcpu); 2103 return 0; 2104 } 2105 2106 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa, 2107 sizeof(u32))) 2108 return 1; 2109 2110 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS); 2111 vcpu->arch.apf.delivery_as_pf_vmexit = data & KVM_ASYNC_PF_DELIVERY_AS_PF_VMEXIT; 2112 kvm_async_pf_wakeup_all(vcpu); 2113 return 0; 2114 } 2115 2116 static void kvmclock_reset(struct kvm_vcpu *vcpu) 2117 { 2118 vcpu->arch.pv_time_enabled = false; 2119 } 2120 2121 static void record_steal_time(struct kvm_vcpu *vcpu) 2122 { 2123 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED)) 2124 return; 2125 2126 if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime, 2127 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time)))) 2128 return; 2129 2130 vcpu->arch.st.steal.preempted = 0; 2131 2132 if (vcpu->arch.st.steal.version & 1) 2133 vcpu->arch.st.steal.version += 1; /* first time write, random junk */ 2134 2135 vcpu->arch.st.steal.version += 1; 2136 2137 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime, 2138 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time)); 2139 2140 smp_wmb(); 2141 2142 vcpu->arch.st.steal.steal += current->sched_info.run_delay - 2143 vcpu->arch.st.last_steal; 2144 vcpu->arch.st.last_steal = current->sched_info.run_delay; 2145 2146 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime, 2147 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time)); 2148 2149 smp_wmb(); 2150 2151 vcpu->arch.st.steal.version += 1; 2152 2153 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime, 2154 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time)); 2155 } 2156 2157 int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info) 2158 { 2159 bool pr = false; 2160 u32 msr = msr_info->index; 2161 u64 data = msr_info->data; 2162 2163 switch (msr) { 2164 case MSR_AMD64_NB_CFG: 2165 case MSR_IA32_UCODE_REV: 2166 case MSR_IA32_UCODE_WRITE: 2167 case MSR_VM_HSAVE_PA: 2168 case MSR_AMD64_PATCH_LOADER: 2169 case MSR_AMD64_BU_CFG2: 2170 case MSR_AMD64_DC_CFG: 2171 break; 2172 2173 case MSR_EFER: 2174 return set_efer(vcpu, data); 2175 case MSR_K7_HWCR: 2176 data &= ~(u64)0x40; /* ignore flush filter disable */ 2177 data &= ~(u64)0x100; /* ignore ignne emulation enable */ 2178 data &= ~(u64)0x8; /* ignore TLB cache disable */ 2179 data &= ~(u64)0x40000; /* ignore Mc status write enable */ 2180 if (data != 0) { 2181 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n", 2182 data); 2183 return 1; 2184 } 2185 break; 2186 case MSR_FAM10H_MMIO_CONF_BASE: 2187 if (data != 0) { 2188 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: " 2189 "0x%llx\n", data); 2190 return 1; 2191 } 2192 break; 2193 case MSR_IA32_DEBUGCTLMSR: 2194 if (!data) { 2195 /* We support the non-activated case already */ 2196 break; 2197 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) { 2198 /* Values other than LBR and BTF are vendor-specific, 2199 thus reserved and should throw a #GP */ 2200 return 1; 2201 } 2202 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n", 2203 __func__, data); 2204 break; 2205 case 0x200 ... 0x2ff: 2206 return kvm_mtrr_set_msr(vcpu, msr, data); 2207 case MSR_IA32_APICBASE: 2208 return kvm_set_apic_base(vcpu, msr_info); 2209 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff: 2210 return kvm_x2apic_msr_write(vcpu, msr, data); 2211 case MSR_IA32_TSCDEADLINE: 2212 kvm_set_lapic_tscdeadline_msr(vcpu, data); 2213 break; 2214 case MSR_IA32_TSC_ADJUST: 2215 if (guest_cpuid_has(vcpu, X86_FEATURE_TSC_ADJUST)) { 2216 if (!msr_info->host_initiated) { 2217 s64 adj = data - vcpu->arch.ia32_tsc_adjust_msr; 2218 adjust_tsc_offset_guest(vcpu, adj); 2219 } 2220 vcpu->arch.ia32_tsc_adjust_msr = data; 2221 } 2222 break; 2223 case MSR_IA32_MISC_ENABLE: 2224 vcpu->arch.ia32_misc_enable_msr = data; 2225 break; 2226 case MSR_IA32_SMBASE: 2227 if (!msr_info->host_initiated) 2228 return 1; 2229 vcpu->arch.smbase = data; 2230 break; 2231 case MSR_KVM_WALL_CLOCK_NEW: 2232 case MSR_KVM_WALL_CLOCK: 2233 vcpu->kvm->arch.wall_clock = data; 2234 kvm_write_wall_clock(vcpu->kvm, data); 2235 break; 2236 case MSR_KVM_SYSTEM_TIME_NEW: 2237 case MSR_KVM_SYSTEM_TIME: { 2238 struct kvm_arch *ka = &vcpu->kvm->arch; 2239 2240 kvmclock_reset(vcpu); 2241 2242 if (vcpu->vcpu_id == 0 && !msr_info->host_initiated) { 2243 bool tmp = (msr == MSR_KVM_SYSTEM_TIME); 2244 2245 if (ka->boot_vcpu_runs_old_kvmclock != tmp) 2246 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu); 2247 2248 ka->boot_vcpu_runs_old_kvmclock = tmp; 2249 } 2250 2251 vcpu->arch.time = data; 2252 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu); 2253 2254 /* we verify if the enable bit is set... */ 2255 if (!(data & 1)) 2256 break; 2257 2258 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, 2259 &vcpu->arch.pv_time, data & ~1ULL, 2260 sizeof(struct pvclock_vcpu_time_info))) 2261 vcpu->arch.pv_time_enabled = false; 2262 else 2263 vcpu->arch.pv_time_enabled = true; 2264 2265 break; 2266 } 2267 case MSR_KVM_ASYNC_PF_EN: 2268 if (kvm_pv_enable_async_pf(vcpu, data)) 2269 return 1; 2270 break; 2271 case MSR_KVM_STEAL_TIME: 2272 2273 if (unlikely(!sched_info_on())) 2274 return 1; 2275 2276 if (data & KVM_STEAL_RESERVED_MASK) 2277 return 1; 2278 2279 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime, 2280 data & KVM_STEAL_VALID_BITS, 2281 sizeof(struct kvm_steal_time))) 2282 return 1; 2283 2284 vcpu->arch.st.msr_val = data; 2285 2286 if (!(data & KVM_MSR_ENABLED)) 2287 break; 2288 2289 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu); 2290 2291 break; 2292 case MSR_KVM_PV_EOI_EN: 2293 if (kvm_lapic_enable_pv_eoi(vcpu, data)) 2294 return 1; 2295 break; 2296 2297 case MSR_IA32_MCG_CTL: 2298 case MSR_IA32_MCG_STATUS: 2299 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1: 2300 return set_msr_mce(vcpu, msr_info); 2301 2302 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3: 2303 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1: 2304 pr = true; /* fall through */ 2305 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3: 2306 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1: 2307 if (kvm_pmu_is_valid_msr(vcpu, msr)) 2308 return kvm_pmu_set_msr(vcpu, msr_info); 2309 2310 if (pr || data != 0) 2311 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: " 2312 "0x%x data 0x%llx\n", msr, data); 2313 break; 2314 case MSR_K7_CLK_CTL: 2315 /* 2316 * Ignore all writes to this no longer documented MSR. 2317 * Writes are only relevant for old K7 processors, 2318 * all pre-dating SVM, but a recommended workaround from 2319 * AMD for these chips. It is possible to specify the 2320 * affected processor models on the command line, hence 2321 * the need to ignore the workaround. 2322 */ 2323 break; 2324 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15: 2325 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4: 2326 case HV_X64_MSR_CRASH_CTL: 2327 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT: 2328 return kvm_hv_set_msr_common(vcpu, msr, data, 2329 msr_info->host_initiated); 2330 case MSR_IA32_BBL_CR_CTL3: 2331 /* Drop writes to this legacy MSR -- see rdmsr 2332 * counterpart for further detail. 2333 */ 2334 if (report_ignored_msrs) 2335 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data 0x%llx\n", 2336 msr, data); 2337 break; 2338 case MSR_AMD64_OSVW_ID_LENGTH: 2339 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW)) 2340 return 1; 2341 vcpu->arch.osvw.length = data; 2342 break; 2343 case MSR_AMD64_OSVW_STATUS: 2344 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW)) 2345 return 1; 2346 vcpu->arch.osvw.status = data; 2347 break; 2348 case MSR_PLATFORM_INFO: 2349 if (!msr_info->host_initiated || 2350 data & ~MSR_PLATFORM_INFO_CPUID_FAULT || 2351 (!(data & MSR_PLATFORM_INFO_CPUID_FAULT) && 2352 cpuid_fault_enabled(vcpu))) 2353 return 1; 2354 vcpu->arch.msr_platform_info = data; 2355 break; 2356 case MSR_MISC_FEATURES_ENABLES: 2357 if (data & ~MSR_MISC_FEATURES_ENABLES_CPUID_FAULT || 2358 (data & MSR_MISC_FEATURES_ENABLES_CPUID_FAULT && 2359 !supports_cpuid_fault(vcpu))) 2360 return 1; 2361 vcpu->arch.msr_misc_features_enables = data; 2362 break; 2363 default: 2364 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr)) 2365 return xen_hvm_config(vcpu, data); 2366 if (kvm_pmu_is_valid_msr(vcpu, msr)) 2367 return kvm_pmu_set_msr(vcpu, msr_info); 2368 if (!ignore_msrs) { 2369 vcpu_debug_ratelimited(vcpu, "unhandled wrmsr: 0x%x data 0x%llx\n", 2370 msr, data); 2371 return 1; 2372 } else { 2373 if (report_ignored_msrs) 2374 vcpu_unimpl(vcpu, 2375 "ignored wrmsr: 0x%x data 0x%llx\n", 2376 msr, data); 2377 break; 2378 } 2379 } 2380 return 0; 2381 } 2382 EXPORT_SYMBOL_GPL(kvm_set_msr_common); 2383 2384 2385 /* 2386 * Reads an msr value (of 'msr_index') into 'pdata'. 2387 * Returns 0 on success, non-0 otherwise. 2388 * Assumes vcpu_load() was already called. 2389 */ 2390 int kvm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr) 2391 { 2392 return kvm_x86_ops->get_msr(vcpu, msr); 2393 } 2394 EXPORT_SYMBOL_GPL(kvm_get_msr); 2395 2396 static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata) 2397 { 2398 u64 data; 2399 u64 mcg_cap = vcpu->arch.mcg_cap; 2400 unsigned bank_num = mcg_cap & 0xff; 2401 2402 switch (msr) { 2403 case MSR_IA32_P5_MC_ADDR: 2404 case MSR_IA32_P5_MC_TYPE: 2405 data = 0; 2406 break; 2407 case MSR_IA32_MCG_CAP: 2408 data = vcpu->arch.mcg_cap; 2409 break; 2410 case MSR_IA32_MCG_CTL: 2411 if (!(mcg_cap & MCG_CTL_P)) 2412 return 1; 2413 data = vcpu->arch.mcg_ctl; 2414 break; 2415 case MSR_IA32_MCG_STATUS: 2416 data = vcpu->arch.mcg_status; 2417 break; 2418 default: 2419 if (msr >= MSR_IA32_MC0_CTL && 2420 msr < MSR_IA32_MCx_CTL(bank_num)) { 2421 u32 offset = msr - MSR_IA32_MC0_CTL; 2422 data = vcpu->arch.mce_banks[offset]; 2423 break; 2424 } 2425 return 1; 2426 } 2427 *pdata = data; 2428 return 0; 2429 } 2430 2431 int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info) 2432 { 2433 switch (msr_info->index) { 2434 case MSR_IA32_PLATFORM_ID: 2435 case MSR_IA32_EBL_CR_POWERON: 2436 case MSR_IA32_DEBUGCTLMSR: 2437 case MSR_IA32_LASTBRANCHFROMIP: 2438 case MSR_IA32_LASTBRANCHTOIP: 2439 case MSR_IA32_LASTINTFROMIP: 2440 case MSR_IA32_LASTINTTOIP: 2441 case MSR_K8_SYSCFG: 2442 case MSR_K8_TSEG_ADDR: 2443 case MSR_K8_TSEG_MASK: 2444 case MSR_K7_HWCR: 2445 case MSR_VM_HSAVE_PA: 2446 case MSR_K8_INT_PENDING_MSG: 2447 case MSR_AMD64_NB_CFG: 2448 case MSR_FAM10H_MMIO_CONF_BASE: 2449 case MSR_AMD64_BU_CFG2: 2450 case MSR_IA32_PERF_CTL: 2451 case MSR_AMD64_DC_CFG: 2452 msr_info->data = 0; 2453 break; 2454 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3: 2455 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3: 2456 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1: 2457 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1: 2458 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index)) 2459 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data); 2460 msr_info->data = 0; 2461 break; 2462 case MSR_IA32_UCODE_REV: 2463 msr_info->data = 0x100000000ULL; 2464 break; 2465 case MSR_MTRRcap: 2466 case 0x200 ... 0x2ff: 2467 return kvm_mtrr_get_msr(vcpu, msr_info->index, &msr_info->data); 2468 case 0xcd: /* fsb frequency */ 2469 msr_info->data = 3; 2470 break; 2471 /* 2472 * MSR_EBC_FREQUENCY_ID 2473 * Conservative value valid for even the basic CPU models. 2474 * Models 0,1: 000 in bits 23:21 indicating a bus speed of 2475 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz, 2476 * and 266MHz for model 3, or 4. Set Core Clock 2477 * Frequency to System Bus Frequency Ratio to 1 (bits 2478 * 31:24) even though these are only valid for CPU 2479 * models > 2, however guests may end up dividing or 2480 * multiplying by zero otherwise. 2481 */ 2482 case MSR_EBC_FREQUENCY_ID: 2483 msr_info->data = 1 << 24; 2484 break; 2485 case MSR_IA32_APICBASE: 2486 msr_info->data = kvm_get_apic_base(vcpu); 2487 break; 2488 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff: 2489 return kvm_x2apic_msr_read(vcpu, msr_info->index, &msr_info->data); 2490 break; 2491 case MSR_IA32_TSCDEADLINE: 2492 msr_info->data = kvm_get_lapic_tscdeadline_msr(vcpu); 2493 break; 2494 case MSR_IA32_TSC_ADJUST: 2495 msr_info->data = (u64)vcpu->arch.ia32_tsc_adjust_msr; 2496 break; 2497 case MSR_IA32_MISC_ENABLE: 2498 msr_info->data = vcpu->arch.ia32_misc_enable_msr; 2499 break; 2500 case MSR_IA32_SMBASE: 2501 if (!msr_info->host_initiated) 2502 return 1; 2503 msr_info->data = vcpu->arch.smbase; 2504 break; 2505 case MSR_IA32_PERF_STATUS: 2506 /* TSC increment by tick */ 2507 msr_info->data = 1000ULL; 2508 /* CPU multiplier */ 2509 msr_info->data |= (((uint64_t)4ULL) << 40); 2510 break; 2511 case MSR_EFER: 2512 msr_info->data = vcpu->arch.efer; 2513 break; 2514 case MSR_KVM_WALL_CLOCK: 2515 case MSR_KVM_WALL_CLOCK_NEW: 2516 msr_info->data = vcpu->kvm->arch.wall_clock; 2517 break; 2518 case MSR_KVM_SYSTEM_TIME: 2519 case MSR_KVM_SYSTEM_TIME_NEW: 2520 msr_info->data = vcpu->arch.time; 2521 break; 2522 case MSR_KVM_ASYNC_PF_EN: 2523 msr_info->data = vcpu->arch.apf.msr_val; 2524 break; 2525 case MSR_KVM_STEAL_TIME: 2526 msr_info->data = vcpu->arch.st.msr_val; 2527 break; 2528 case MSR_KVM_PV_EOI_EN: 2529 msr_info->data = vcpu->arch.pv_eoi.msr_val; 2530 break; 2531 case MSR_IA32_P5_MC_ADDR: 2532 case MSR_IA32_P5_MC_TYPE: 2533 case MSR_IA32_MCG_CAP: 2534 case MSR_IA32_MCG_CTL: 2535 case MSR_IA32_MCG_STATUS: 2536 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1: 2537 return get_msr_mce(vcpu, msr_info->index, &msr_info->data); 2538 case MSR_K7_CLK_CTL: 2539 /* 2540 * Provide expected ramp-up count for K7. All other 2541 * are set to zero, indicating minimum divisors for 2542 * every field. 2543 * 2544 * This prevents guest kernels on AMD host with CPU 2545 * type 6, model 8 and higher from exploding due to 2546 * the rdmsr failing. 2547 */ 2548 msr_info->data = 0x20000000; 2549 break; 2550 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15: 2551 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4: 2552 case HV_X64_MSR_CRASH_CTL: 2553 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT: 2554 return kvm_hv_get_msr_common(vcpu, 2555 msr_info->index, &msr_info->data); 2556 break; 2557 case MSR_IA32_BBL_CR_CTL3: 2558 /* This legacy MSR exists but isn't fully documented in current 2559 * silicon. It is however accessed by winxp in very narrow 2560 * scenarios where it sets bit #19, itself documented as 2561 * a "reserved" bit. Best effort attempt to source coherent 2562 * read data here should the balance of the register be 2563 * interpreted by the guest: 2564 * 2565 * L2 cache control register 3: 64GB range, 256KB size, 2566 * enabled, latency 0x1, configured 2567 */ 2568 msr_info->data = 0xbe702111; 2569 break; 2570 case MSR_AMD64_OSVW_ID_LENGTH: 2571 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW)) 2572 return 1; 2573 msr_info->data = vcpu->arch.osvw.length; 2574 break; 2575 case MSR_AMD64_OSVW_STATUS: 2576 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW)) 2577 return 1; 2578 msr_info->data = vcpu->arch.osvw.status; 2579 break; 2580 case MSR_PLATFORM_INFO: 2581 msr_info->data = vcpu->arch.msr_platform_info; 2582 break; 2583 case MSR_MISC_FEATURES_ENABLES: 2584 msr_info->data = vcpu->arch.msr_misc_features_enables; 2585 break; 2586 default: 2587 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index)) 2588 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data); 2589 if (!ignore_msrs) { 2590 vcpu_debug_ratelimited(vcpu, "unhandled rdmsr: 0x%x\n", 2591 msr_info->index); 2592 return 1; 2593 } else { 2594 if (report_ignored_msrs) 2595 vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n", 2596 msr_info->index); 2597 msr_info->data = 0; 2598 } 2599 break; 2600 } 2601 return 0; 2602 } 2603 EXPORT_SYMBOL_GPL(kvm_get_msr_common); 2604 2605 /* 2606 * Read or write a bunch of msrs. All parameters are kernel addresses. 2607 * 2608 * @return number of msrs set successfully. 2609 */ 2610 static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs, 2611 struct kvm_msr_entry *entries, 2612 int (*do_msr)(struct kvm_vcpu *vcpu, 2613 unsigned index, u64 *data)) 2614 { 2615 int i, idx; 2616 2617 idx = srcu_read_lock(&vcpu->kvm->srcu); 2618 for (i = 0; i < msrs->nmsrs; ++i) 2619 if (do_msr(vcpu, entries[i].index, &entries[i].data)) 2620 break; 2621 srcu_read_unlock(&vcpu->kvm->srcu, idx); 2622 2623 return i; 2624 } 2625 2626 /* 2627 * Read or write a bunch of msrs. Parameters are user addresses. 2628 * 2629 * @return number of msrs set successfully. 2630 */ 2631 static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs, 2632 int (*do_msr)(struct kvm_vcpu *vcpu, 2633 unsigned index, u64 *data), 2634 int writeback) 2635 { 2636 struct kvm_msrs msrs; 2637 struct kvm_msr_entry *entries; 2638 int r, n; 2639 unsigned size; 2640 2641 r = -EFAULT; 2642 if (copy_from_user(&msrs, user_msrs, sizeof msrs)) 2643 goto out; 2644 2645 r = -E2BIG; 2646 if (msrs.nmsrs >= MAX_IO_MSRS) 2647 goto out; 2648 2649 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs; 2650 entries = memdup_user(user_msrs->entries, size); 2651 if (IS_ERR(entries)) { 2652 r = PTR_ERR(entries); 2653 goto out; 2654 } 2655 2656 r = n = __msr_io(vcpu, &msrs, entries, do_msr); 2657 if (r < 0) 2658 goto out_free; 2659 2660 r = -EFAULT; 2661 if (writeback && copy_to_user(user_msrs->entries, entries, size)) 2662 goto out_free; 2663 2664 r = n; 2665 2666 out_free: 2667 kfree(entries); 2668 out: 2669 return r; 2670 } 2671 2672 int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext) 2673 { 2674 int r; 2675 2676 switch (ext) { 2677 case KVM_CAP_IRQCHIP: 2678 case KVM_CAP_HLT: 2679 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL: 2680 case KVM_CAP_SET_TSS_ADDR: 2681 case KVM_CAP_EXT_CPUID: 2682 case KVM_CAP_EXT_EMUL_CPUID: 2683 case KVM_CAP_CLOCKSOURCE: 2684 case KVM_CAP_PIT: 2685 case KVM_CAP_NOP_IO_DELAY: 2686 case KVM_CAP_MP_STATE: 2687 case KVM_CAP_SYNC_MMU: 2688 case KVM_CAP_USER_NMI: 2689 case KVM_CAP_REINJECT_CONTROL: 2690 case KVM_CAP_IRQ_INJECT_STATUS: 2691 case KVM_CAP_IOEVENTFD: 2692 case KVM_CAP_IOEVENTFD_NO_LENGTH: 2693 case KVM_CAP_PIT2: 2694 case KVM_CAP_PIT_STATE2: 2695 case KVM_CAP_SET_IDENTITY_MAP_ADDR: 2696 case KVM_CAP_XEN_HVM: 2697 case KVM_CAP_VCPU_EVENTS: 2698 case KVM_CAP_HYPERV: 2699 case KVM_CAP_HYPERV_VAPIC: 2700 case KVM_CAP_HYPERV_SPIN: 2701 case KVM_CAP_HYPERV_SYNIC: 2702 case KVM_CAP_HYPERV_SYNIC2: 2703 case KVM_CAP_HYPERV_VP_INDEX: 2704 case KVM_CAP_PCI_SEGMENT: 2705 case KVM_CAP_DEBUGREGS: 2706 case KVM_CAP_X86_ROBUST_SINGLESTEP: 2707 case KVM_CAP_XSAVE: 2708 case KVM_CAP_ASYNC_PF: 2709 case KVM_CAP_GET_TSC_KHZ: 2710 case KVM_CAP_KVMCLOCK_CTRL: 2711 case KVM_CAP_READONLY_MEM: 2712 case KVM_CAP_HYPERV_TIME: 2713 case KVM_CAP_IOAPIC_POLARITY_IGNORED: 2714 case KVM_CAP_TSC_DEADLINE_TIMER: 2715 case KVM_CAP_ENABLE_CAP_VM: 2716 case KVM_CAP_DISABLE_QUIRKS: 2717 case KVM_CAP_SET_BOOT_CPU_ID: 2718 case KVM_CAP_SPLIT_IRQCHIP: 2719 case KVM_CAP_IMMEDIATE_EXIT: 2720 r = 1; 2721 break; 2722 case KVM_CAP_ADJUST_CLOCK: 2723 r = KVM_CLOCK_TSC_STABLE; 2724 break; 2725 case KVM_CAP_X86_GUEST_MWAIT: 2726 r = kvm_mwait_in_guest(); 2727 break; 2728 case KVM_CAP_X86_SMM: 2729 /* SMBASE is usually relocated above 1M on modern chipsets, 2730 * and SMM handlers might indeed rely on 4G segment limits, 2731 * so do not report SMM to be available if real mode is 2732 * emulated via vm86 mode. Still, do not go to great lengths 2733 * to avoid userspace's usage of the feature, because it is a 2734 * fringe case that is not enabled except via specific settings 2735 * of the module parameters. 2736 */ 2737 r = kvm_x86_ops->cpu_has_high_real_mode_segbase(); 2738 break; 2739 case KVM_CAP_VAPIC: 2740 r = !kvm_x86_ops->cpu_has_accelerated_tpr(); 2741 break; 2742 case KVM_CAP_NR_VCPUS: 2743 r = KVM_SOFT_MAX_VCPUS; 2744 break; 2745 case KVM_CAP_MAX_VCPUS: 2746 r = KVM_MAX_VCPUS; 2747 break; 2748 case KVM_CAP_NR_MEMSLOTS: 2749 r = KVM_USER_MEM_SLOTS; 2750 break; 2751 case KVM_CAP_PV_MMU: /* obsolete */ 2752 r = 0; 2753 break; 2754 case KVM_CAP_MCE: 2755 r = KVM_MAX_MCE_BANKS; 2756 break; 2757 case KVM_CAP_XCRS: 2758 r = boot_cpu_has(X86_FEATURE_XSAVE); 2759 break; 2760 case KVM_CAP_TSC_CONTROL: 2761 r = kvm_has_tsc_control; 2762 break; 2763 case KVM_CAP_X2APIC_API: 2764 r = KVM_X2APIC_API_VALID_FLAGS; 2765 break; 2766 default: 2767 r = 0; 2768 break; 2769 } 2770 return r; 2771 2772 } 2773 2774 long kvm_arch_dev_ioctl(struct file *filp, 2775 unsigned int ioctl, unsigned long arg) 2776 { 2777 void __user *argp = (void __user *)arg; 2778 long r; 2779 2780 switch (ioctl) { 2781 case KVM_GET_MSR_INDEX_LIST: { 2782 struct kvm_msr_list __user *user_msr_list = argp; 2783 struct kvm_msr_list msr_list; 2784 unsigned n; 2785 2786 r = -EFAULT; 2787 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list)) 2788 goto out; 2789 n = msr_list.nmsrs; 2790 msr_list.nmsrs = num_msrs_to_save + num_emulated_msrs; 2791 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list)) 2792 goto out; 2793 r = -E2BIG; 2794 if (n < msr_list.nmsrs) 2795 goto out; 2796 r = -EFAULT; 2797 if (copy_to_user(user_msr_list->indices, &msrs_to_save, 2798 num_msrs_to_save * sizeof(u32))) 2799 goto out; 2800 if (copy_to_user(user_msr_list->indices + num_msrs_to_save, 2801 &emulated_msrs, 2802 num_emulated_msrs * sizeof(u32))) 2803 goto out; 2804 r = 0; 2805 break; 2806 } 2807 case KVM_GET_SUPPORTED_CPUID: 2808 case KVM_GET_EMULATED_CPUID: { 2809 struct kvm_cpuid2 __user *cpuid_arg = argp; 2810 struct kvm_cpuid2 cpuid; 2811 2812 r = -EFAULT; 2813 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid)) 2814 goto out; 2815 2816 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries, 2817 ioctl); 2818 if (r) 2819 goto out; 2820 2821 r = -EFAULT; 2822 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid)) 2823 goto out; 2824 r = 0; 2825 break; 2826 } 2827 case KVM_X86_GET_MCE_CAP_SUPPORTED: { 2828 r = -EFAULT; 2829 if (copy_to_user(argp, &kvm_mce_cap_supported, 2830 sizeof(kvm_mce_cap_supported))) 2831 goto out; 2832 r = 0; 2833 break; 2834 } 2835 default: 2836 r = -EINVAL; 2837 } 2838 out: 2839 return r; 2840 } 2841 2842 static void wbinvd_ipi(void *garbage) 2843 { 2844 wbinvd(); 2845 } 2846 2847 static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu) 2848 { 2849 return kvm_arch_has_noncoherent_dma(vcpu->kvm); 2850 } 2851 2852 void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu) 2853 { 2854 /* Address WBINVD may be executed by guest */ 2855 if (need_emulate_wbinvd(vcpu)) { 2856 if (kvm_x86_ops->has_wbinvd_exit()) 2857 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask); 2858 else if (vcpu->cpu != -1 && vcpu->cpu != cpu) 2859 smp_call_function_single(vcpu->cpu, 2860 wbinvd_ipi, NULL, 1); 2861 } 2862 2863 kvm_x86_ops->vcpu_load(vcpu, cpu); 2864 2865 /* Apply any externally detected TSC adjustments (due to suspend) */ 2866 if (unlikely(vcpu->arch.tsc_offset_adjustment)) { 2867 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment); 2868 vcpu->arch.tsc_offset_adjustment = 0; 2869 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 2870 } 2871 2872 if (unlikely(vcpu->cpu != cpu) || check_tsc_unstable()) { 2873 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 : 2874 rdtsc() - vcpu->arch.last_host_tsc; 2875 if (tsc_delta < 0) 2876 mark_tsc_unstable("KVM discovered backwards TSC"); 2877 2878 if (check_tsc_unstable()) { 2879 u64 offset = kvm_compute_tsc_offset(vcpu, 2880 vcpu->arch.last_guest_tsc); 2881 kvm_vcpu_write_tsc_offset(vcpu, offset); 2882 vcpu->arch.tsc_catchup = 1; 2883 } 2884 2885 if (kvm_lapic_hv_timer_in_use(vcpu)) 2886 kvm_lapic_restart_hv_timer(vcpu); 2887 2888 /* 2889 * On a host with synchronized TSC, there is no need to update 2890 * kvmclock on vcpu->cpu migration 2891 */ 2892 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1) 2893 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu); 2894 if (vcpu->cpu != cpu) 2895 kvm_make_request(KVM_REQ_MIGRATE_TIMER, vcpu); 2896 vcpu->cpu = cpu; 2897 } 2898 2899 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu); 2900 } 2901 2902 static void kvm_steal_time_set_preempted(struct kvm_vcpu *vcpu) 2903 { 2904 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED)) 2905 return; 2906 2907 vcpu->arch.st.steal.preempted = 1; 2908 2909 kvm_write_guest_offset_cached(vcpu->kvm, &vcpu->arch.st.stime, 2910 &vcpu->arch.st.steal.preempted, 2911 offsetof(struct kvm_steal_time, preempted), 2912 sizeof(vcpu->arch.st.steal.preempted)); 2913 } 2914 2915 void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu) 2916 { 2917 int idx; 2918 2919 if (vcpu->preempted) 2920 vcpu->arch.preempted_in_kernel = !kvm_x86_ops->get_cpl(vcpu); 2921 2922 /* 2923 * Disable page faults because we're in atomic context here. 2924 * kvm_write_guest_offset_cached() would call might_fault() 2925 * that relies on pagefault_disable() to tell if there's a 2926 * bug. NOTE: the write to guest memory may not go through if 2927 * during postcopy live migration or if there's heavy guest 2928 * paging. 2929 */ 2930 pagefault_disable(); 2931 /* 2932 * kvm_memslots() will be called by 2933 * kvm_write_guest_offset_cached() so take the srcu lock. 2934 */ 2935 idx = srcu_read_lock(&vcpu->kvm->srcu); 2936 kvm_steal_time_set_preempted(vcpu); 2937 srcu_read_unlock(&vcpu->kvm->srcu, idx); 2938 pagefault_enable(); 2939 kvm_x86_ops->vcpu_put(vcpu); 2940 vcpu->arch.last_host_tsc = rdtsc(); 2941 } 2942 2943 static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu, 2944 struct kvm_lapic_state *s) 2945 { 2946 if (kvm_x86_ops->sync_pir_to_irr && vcpu->arch.apicv_active) 2947 kvm_x86_ops->sync_pir_to_irr(vcpu); 2948 2949 return kvm_apic_get_state(vcpu, s); 2950 } 2951 2952 static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu, 2953 struct kvm_lapic_state *s) 2954 { 2955 int r; 2956 2957 r = kvm_apic_set_state(vcpu, s); 2958 if (r) 2959 return r; 2960 update_cr8_intercept(vcpu); 2961 2962 return 0; 2963 } 2964 2965 static int kvm_cpu_accept_dm_intr(struct kvm_vcpu *vcpu) 2966 { 2967 return (!lapic_in_kernel(vcpu) || 2968 kvm_apic_accept_pic_intr(vcpu)); 2969 } 2970 2971 /* 2972 * if userspace requested an interrupt window, check that the 2973 * interrupt window is open. 2974 * 2975 * No need to exit to userspace if we already have an interrupt queued. 2976 */ 2977 static int kvm_vcpu_ready_for_interrupt_injection(struct kvm_vcpu *vcpu) 2978 { 2979 return kvm_arch_interrupt_allowed(vcpu) && 2980 !kvm_cpu_has_interrupt(vcpu) && 2981 !kvm_event_needs_reinjection(vcpu) && 2982 kvm_cpu_accept_dm_intr(vcpu); 2983 } 2984 2985 static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu, 2986 struct kvm_interrupt *irq) 2987 { 2988 if (irq->irq >= KVM_NR_INTERRUPTS) 2989 return -EINVAL; 2990 2991 if (!irqchip_in_kernel(vcpu->kvm)) { 2992 kvm_queue_interrupt(vcpu, irq->irq, false); 2993 kvm_make_request(KVM_REQ_EVENT, vcpu); 2994 return 0; 2995 } 2996 2997 /* 2998 * With in-kernel LAPIC, we only use this to inject EXTINT, so 2999 * fail for in-kernel 8259. 3000 */ 3001 if (pic_in_kernel(vcpu->kvm)) 3002 return -ENXIO; 3003 3004 if (vcpu->arch.pending_external_vector != -1) 3005 return -EEXIST; 3006 3007 vcpu->arch.pending_external_vector = irq->irq; 3008 kvm_make_request(KVM_REQ_EVENT, vcpu); 3009 return 0; 3010 } 3011 3012 static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu) 3013 { 3014 kvm_inject_nmi(vcpu); 3015 3016 return 0; 3017 } 3018 3019 static int kvm_vcpu_ioctl_smi(struct kvm_vcpu *vcpu) 3020 { 3021 kvm_make_request(KVM_REQ_SMI, vcpu); 3022 3023 return 0; 3024 } 3025 3026 static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu, 3027 struct kvm_tpr_access_ctl *tac) 3028 { 3029 if (tac->flags) 3030 return -EINVAL; 3031 vcpu->arch.tpr_access_reporting = !!tac->enabled; 3032 return 0; 3033 } 3034 3035 static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu, 3036 u64 mcg_cap) 3037 { 3038 int r; 3039 unsigned bank_num = mcg_cap & 0xff, bank; 3040 3041 r = -EINVAL; 3042 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS) 3043 goto out; 3044 if (mcg_cap & ~(kvm_mce_cap_supported | 0xff | 0xff0000)) 3045 goto out; 3046 r = 0; 3047 vcpu->arch.mcg_cap = mcg_cap; 3048 /* Init IA32_MCG_CTL to all 1s */ 3049 if (mcg_cap & MCG_CTL_P) 3050 vcpu->arch.mcg_ctl = ~(u64)0; 3051 /* Init IA32_MCi_CTL to all 1s */ 3052 for (bank = 0; bank < bank_num; bank++) 3053 vcpu->arch.mce_banks[bank*4] = ~(u64)0; 3054 3055 if (kvm_x86_ops->setup_mce) 3056 kvm_x86_ops->setup_mce(vcpu); 3057 out: 3058 return r; 3059 } 3060 3061 static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu, 3062 struct kvm_x86_mce *mce) 3063 { 3064 u64 mcg_cap = vcpu->arch.mcg_cap; 3065 unsigned bank_num = mcg_cap & 0xff; 3066 u64 *banks = vcpu->arch.mce_banks; 3067 3068 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL)) 3069 return -EINVAL; 3070 /* 3071 * if IA32_MCG_CTL is not all 1s, the uncorrected error 3072 * reporting is disabled 3073 */ 3074 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) && 3075 vcpu->arch.mcg_ctl != ~(u64)0) 3076 return 0; 3077 banks += 4 * mce->bank; 3078 /* 3079 * if IA32_MCi_CTL is not all 1s, the uncorrected error 3080 * reporting is disabled for the bank 3081 */ 3082 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0) 3083 return 0; 3084 if (mce->status & MCI_STATUS_UC) { 3085 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) || 3086 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) { 3087 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); 3088 return 0; 3089 } 3090 if (banks[1] & MCI_STATUS_VAL) 3091 mce->status |= MCI_STATUS_OVER; 3092 banks[2] = mce->addr; 3093 banks[3] = mce->misc; 3094 vcpu->arch.mcg_status = mce->mcg_status; 3095 banks[1] = mce->status; 3096 kvm_queue_exception(vcpu, MC_VECTOR); 3097 } else if (!(banks[1] & MCI_STATUS_VAL) 3098 || !(banks[1] & MCI_STATUS_UC)) { 3099 if (banks[1] & MCI_STATUS_VAL) 3100 mce->status |= MCI_STATUS_OVER; 3101 banks[2] = mce->addr; 3102 banks[3] = mce->misc; 3103 banks[1] = mce->status; 3104 } else 3105 banks[1] |= MCI_STATUS_OVER; 3106 return 0; 3107 } 3108 3109 static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu, 3110 struct kvm_vcpu_events *events) 3111 { 3112 process_nmi(vcpu); 3113 /* 3114 * FIXME: pass injected and pending separately. This is only 3115 * needed for nested virtualization, whose state cannot be 3116 * migrated yet. For now we can combine them. 3117 */ 3118 events->exception.injected = 3119 (vcpu->arch.exception.pending || 3120 vcpu->arch.exception.injected) && 3121 !kvm_exception_is_soft(vcpu->arch.exception.nr); 3122 events->exception.nr = vcpu->arch.exception.nr; 3123 events->exception.has_error_code = vcpu->arch.exception.has_error_code; 3124 events->exception.pad = 0; 3125 events->exception.error_code = vcpu->arch.exception.error_code; 3126 3127 events->interrupt.injected = 3128 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft; 3129 events->interrupt.nr = vcpu->arch.interrupt.nr; 3130 events->interrupt.soft = 0; 3131 events->interrupt.shadow = kvm_x86_ops->get_interrupt_shadow(vcpu); 3132 3133 events->nmi.injected = vcpu->arch.nmi_injected; 3134 events->nmi.pending = vcpu->arch.nmi_pending != 0; 3135 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu); 3136 events->nmi.pad = 0; 3137 3138 events->sipi_vector = 0; /* never valid when reporting to user space */ 3139 3140 events->smi.smm = is_smm(vcpu); 3141 events->smi.pending = vcpu->arch.smi_pending; 3142 events->smi.smm_inside_nmi = 3143 !!(vcpu->arch.hflags & HF_SMM_INSIDE_NMI_MASK); 3144 events->smi.latched_init = kvm_lapic_latched_init(vcpu); 3145 3146 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING 3147 | KVM_VCPUEVENT_VALID_SHADOW 3148 | KVM_VCPUEVENT_VALID_SMM); 3149 memset(&events->reserved, 0, sizeof(events->reserved)); 3150 } 3151 3152 static void kvm_set_hflags(struct kvm_vcpu *vcpu, unsigned emul_flags); 3153 3154 static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu, 3155 struct kvm_vcpu_events *events) 3156 { 3157 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING 3158 | KVM_VCPUEVENT_VALID_SIPI_VECTOR 3159 | KVM_VCPUEVENT_VALID_SHADOW 3160 | KVM_VCPUEVENT_VALID_SMM)) 3161 return -EINVAL; 3162 3163 if (events->exception.injected && 3164 (events->exception.nr > 31 || events->exception.nr == NMI_VECTOR || 3165 is_guest_mode(vcpu))) 3166 return -EINVAL; 3167 3168 /* INITs are latched while in SMM */ 3169 if (events->flags & KVM_VCPUEVENT_VALID_SMM && 3170 (events->smi.smm || events->smi.pending) && 3171 vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) 3172 return -EINVAL; 3173 3174 process_nmi(vcpu); 3175 vcpu->arch.exception.injected = false; 3176 vcpu->arch.exception.pending = events->exception.injected; 3177 vcpu->arch.exception.nr = events->exception.nr; 3178 vcpu->arch.exception.has_error_code = events->exception.has_error_code; 3179 vcpu->arch.exception.error_code = events->exception.error_code; 3180 3181 vcpu->arch.interrupt.pending = events->interrupt.injected; 3182 vcpu->arch.interrupt.nr = events->interrupt.nr; 3183 vcpu->arch.interrupt.soft = events->interrupt.soft; 3184 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW) 3185 kvm_x86_ops->set_interrupt_shadow(vcpu, 3186 events->interrupt.shadow); 3187 3188 vcpu->arch.nmi_injected = events->nmi.injected; 3189 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING) 3190 vcpu->arch.nmi_pending = events->nmi.pending; 3191 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked); 3192 3193 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR && 3194 lapic_in_kernel(vcpu)) 3195 vcpu->arch.apic->sipi_vector = events->sipi_vector; 3196 3197 if (events->flags & KVM_VCPUEVENT_VALID_SMM) { 3198 u32 hflags = vcpu->arch.hflags; 3199 if (events->smi.smm) 3200 hflags |= HF_SMM_MASK; 3201 else 3202 hflags &= ~HF_SMM_MASK; 3203 kvm_set_hflags(vcpu, hflags); 3204 3205 vcpu->arch.smi_pending = events->smi.pending; 3206 3207 if (events->smi.smm) { 3208 if (events->smi.smm_inside_nmi) 3209 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK; 3210 else 3211 vcpu->arch.hflags &= ~HF_SMM_INSIDE_NMI_MASK; 3212 if (lapic_in_kernel(vcpu)) { 3213 if (events->smi.latched_init) 3214 set_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events); 3215 else 3216 clear_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events); 3217 } 3218 } 3219 } 3220 3221 kvm_make_request(KVM_REQ_EVENT, vcpu); 3222 3223 return 0; 3224 } 3225 3226 static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu, 3227 struct kvm_debugregs *dbgregs) 3228 { 3229 unsigned long val; 3230 3231 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db)); 3232 kvm_get_dr(vcpu, 6, &val); 3233 dbgregs->dr6 = val; 3234 dbgregs->dr7 = vcpu->arch.dr7; 3235 dbgregs->flags = 0; 3236 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved)); 3237 } 3238 3239 static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu, 3240 struct kvm_debugregs *dbgregs) 3241 { 3242 if (dbgregs->flags) 3243 return -EINVAL; 3244 3245 if (dbgregs->dr6 & ~0xffffffffull) 3246 return -EINVAL; 3247 if (dbgregs->dr7 & ~0xffffffffull) 3248 return -EINVAL; 3249 3250 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db)); 3251 kvm_update_dr0123(vcpu); 3252 vcpu->arch.dr6 = dbgregs->dr6; 3253 kvm_update_dr6(vcpu); 3254 vcpu->arch.dr7 = dbgregs->dr7; 3255 kvm_update_dr7(vcpu); 3256 3257 return 0; 3258 } 3259 3260 #define XSTATE_COMPACTION_ENABLED (1ULL << 63) 3261 3262 static void fill_xsave(u8 *dest, struct kvm_vcpu *vcpu) 3263 { 3264 struct xregs_state *xsave = &vcpu->arch.guest_fpu.state.xsave; 3265 u64 xstate_bv = xsave->header.xfeatures; 3266 u64 valid; 3267 3268 /* 3269 * Copy legacy XSAVE area, to avoid complications with CPUID 3270 * leaves 0 and 1 in the loop below. 3271 */ 3272 memcpy(dest, xsave, XSAVE_HDR_OFFSET); 3273 3274 /* Set XSTATE_BV */ 3275 xstate_bv &= vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FPSSE; 3276 *(u64 *)(dest + XSAVE_HDR_OFFSET) = xstate_bv; 3277 3278 /* 3279 * Copy each region from the possibly compacted offset to the 3280 * non-compacted offset. 3281 */ 3282 valid = xstate_bv & ~XFEATURE_MASK_FPSSE; 3283 while (valid) { 3284 u64 feature = valid & -valid; 3285 int index = fls64(feature) - 1; 3286 void *src = get_xsave_addr(xsave, feature); 3287 3288 if (src) { 3289 u32 size, offset, ecx, edx; 3290 cpuid_count(XSTATE_CPUID, index, 3291 &size, &offset, &ecx, &edx); 3292 if (feature == XFEATURE_MASK_PKRU) 3293 memcpy(dest + offset, &vcpu->arch.pkru, 3294 sizeof(vcpu->arch.pkru)); 3295 else 3296 memcpy(dest + offset, src, size); 3297 3298 } 3299 3300 valid -= feature; 3301 } 3302 } 3303 3304 static void load_xsave(struct kvm_vcpu *vcpu, u8 *src) 3305 { 3306 struct xregs_state *xsave = &vcpu->arch.guest_fpu.state.xsave; 3307 u64 xstate_bv = *(u64 *)(src + XSAVE_HDR_OFFSET); 3308 u64 valid; 3309 3310 /* 3311 * Copy legacy XSAVE area, to avoid complications with CPUID 3312 * leaves 0 and 1 in the loop below. 3313 */ 3314 memcpy(xsave, src, XSAVE_HDR_OFFSET); 3315 3316 /* Set XSTATE_BV and possibly XCOMP_BV. */ 3317 xsave->header.xfeatures = xstate_bv; 3318 if (boot_cpu_has(X86_FEATURE_XSAVES)) 3319 xsave->header.xcomp_bv = host_xcr0 | XSTATE_COMPACTION_ENABLED; 3320 3321 /* 3322 * Copy each region from the non-compacted offset to the 3323 * possibly compacted offset. 3324 */ 3325 valid = xstate_bv & ~XFEATURE_MASK_FPSSE; 3326 while (valid) { 3327 u64 feature = valid & -valid; 3328 int index = fls64(feature) - 1; 3329 void *dest = get_xsave_addr(xsave, feature); 3330 3331 if (dest) { 3332 u32 size, offset, ecx, edx; 3333 cpuid_count(XSTATE_CPUID, index, 3334 &size, &offset, &ecx, &edx); 3335 if (feature == XFEATURE_MASK_PKRU) 3336 memcpy(&vcpu->arch.pkru, src + offset, 3337 sizeof(vcpu->arch.pkru)); 3338 else 3339 memcpy(dest, src + offset, size); 3340 } 3341 3342 valid -= feature; 3343 } 3344 } 3345 3346 static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu, 3347 struct kvm_xsave *guest_xsave) 3348 { 3349 if (boot_cpu_has(X86_FEATURE_XSAVE)) { 3350 memset(guest_xsave, 0, sizeof(struct kvm_xsave)); 3351 fill_xsave((u8 *) guest_xsave->region, vcpu); 3352 } else { 3353 memcpy(guest_xsave->region, 3354 &vcpu->arch.guest_fpu.state.fxsave, 3355 sizeof(struct fxregs_state)); 3356 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] = 3357 XFEATURE_MASK_FPSSE; 3358 } 3359 } 3360 3361 #define XSAVE_MXCSR_OFFSET 24 3362 3363 static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu, 3364 struct kvm_xsave *guest_xsave) 3365 { 3366 u64 xstate_bv = 3367 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)]; 3368 u32 mxcsr = *(u32 *)&guest_xsave->region[XSAVE_MXCSR_OFFSET / sizeof(u32)]; 3369 3370 if (boot_cpu_has(X86_FEATURE_XSAVE)) { 3371 /* 3372 * Here we allow setting states that are not present in 3373 * CPUID leaf 0xD, index 0, EDX:EAX. This is for compatibility 3374 * with old userspace. 3375 */ 3376 if (xstate_bv & ~kvm_supported_xcr0() || 3377 mxcsr & ~mxcsr_feature_mask) 3378 return -EINVAL; 3379 load_xsave(vcpu, (u8 *)guest_xsave->region); 3380 } else { 3381 if (xstate_bv & ~XFEATURE_MASK_FPSSE || 3382 mxcsr & ~mxcsr_feature_mask) 3383 return -EINVAL; 3384 memcpy(&vcpu->arch.guest_fpu.state.fxsave, 3385 guest_xsave->region, sizeof(struct fxregs_state)); 3386 } 3387 return 0; 3388 } 3389 3390 static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu, 3391 struct kvm_xcrs *guest_xcrs) 3392 { 3393 if (!boot_cpu_has(X86_FEATURE_XSAVE)) { 3394 guest_xcrs->nr_xcrs = 0; 3395 return; 3396 } 3397 3398 guest_xcrs->nr_xcrs = 1; 3399 guest_xcrs->flags = 0; 3400 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK; 3401 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0; 3402 } 3403 3404 static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu, 3405 struct kvm_xcrs *guest_xcrs) 3406 { 3407 int i, r = 0; 3408 3409 if (!boot_cpu_has(X86_FEATURE_XSAVE)) 3410 return -EINVAL; 3411 3412 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags) 3413 return -EINVAL; 3414 3415 for (i = 0; i < guest_xcrs->nr_xcrs; i++) 3416 /* Only support XCR0 currently */ 3417 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) { 3418 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK, 3419 guest_xcrs->xcrs[i].value); 3420 break; 3421 } 3422 if (r) 3423 r = -EINVAL; 3424 return r; 3425 } 3426 3427 /* 3428 * kvm_set_guest_paused() indicates to the guest kernel that it has been 3429 * stopped by the hypervisor. This function will be called from the host only. 3430 * EINVAL is returned when the host attempts to set the flag for a guest that 3431 * does not support pv clocks. 3432 */ 3433 static int kvm_set_guest_paused(struct kvm_vcpu *vcpu) 3434 { 3435 if (!vcpu->arch.pv_time_enabled) 3436 return -EINVAL; 3437 vcpu->arch.pvclock_set_guest_stopped_request = true; 3438 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 3439 return 0; 3440 } 3441 3442 static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu, 3443 struct kvm_enable_cap *cap) 3444 { 3445 if (cap->flags) 3446 return -EINVAL; 3447 3448 switch (cap->cap) { 3449 case KVM_CAP_HYPERV_SYNIC2: 3450 if (cap->args[0]) 3451 return -EINVAL; 3452 case KVM_CAP_HYPERV_SYNIC: 3453 if (!irqchip_in_kernel(vcpu->kvm)) 3454 return -EINVAL; 3455 return kvm_hv_activate_synic(vcpu, cap->cap == 3456 KVM_CAP_HYPERV_SYNIC2); 3457 default: 3458 return -EINVAL; 3459 } 3460 } 3461 3462 long kvm_arch_vcpu_ioctl(struct file *filp, 3463 unsigned int ioctl, unsigned long arg) 3464 { 3465 struct kvm_vcpu *vcpu = filp->private_data; 3466 void __user *argp = (void __user *)arg; 3467 int r; 3468 union { 3469 struct kvm_lapic_state *lapic; 3470 struct kvm_xsave *xsave; 3471 struct kvm_xcrs *xcrs; 3472 void *buffer; 3473 } u; 3474 3475 u.buffer = NULL; 3476 switch (ioctl) { 3477 case KVM_GET_LAPIC: { 3478 r = -EINVAL; 3479 if (!lapic_in_kernel(vcpu)) 3480 goto out; 3481 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL); 3482 3483 r = -ENOMEM; 3484 if (!u.lapic) 3485 goto out; 3486 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic); 3487 if (r) 3488 goto out; 3489 r = -EFAULT; 3490 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state))) 3491 goto out; 3492 r = 0; 3493 break; 3494 } 3495 case KVM_SET_LAPIC: { 3496 r = -EINVAL; 3497 if (!lapic_in_kernel(vcpu)) 3498 goto out; 3499 u.lapic = memdup_user(argp, sizeof(*u.lapic)); 3500 if (IS_ERR(u.lapic)) 3501 return PTR_ERR(u.lapic); 3502 3503 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic); 3504 break; 3505 } 3506 case KVM_INTERRUPT: { 3507 struct kvm_interrupt irq; 3508 3509 r = -EFAULT; 3510 if (copy_from_user(&irq, argp, sizeof irq)) 3511 goto out; 3512 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq); 3513 break; 3514 } 3515 case KVM_NMI: { 3516 r = kvm_vcpu_ioctl_nmi(vcpu); 3517 break; 3518 } 3519 case KVM_SMI: { 3520 r = kvm_vcpu_ioctl_smi(vcpu); 3521 break; 3522 } 3523 case KVM_SET_CPUID: { 3524 struct kvm_cpuid __user *cpuid_arg = argp; 3525 struct kvm_cpuid cpuid; 3526 3527 r = -EFAULT; 3528 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid)) 3529 goto out; 3530 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries); 3531 break; 3532 } 3533 case KVM_SET_CPUID2: { 3534 struct kvm_cpuid2 __user *cpuid_arg = argp; 3535 struct kvm_cpuid2 cpuid; 3536 3537 r = -EFAULT; 3538 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid)) 3539 goto out; 3540 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid, 3541 cpuid_arg->entries); 3542 break; 3543 } 3544 case KVM_GET_CPUID2: { 3545 struct kvm_cpuid2 __user *cpuid_arg = argp; 3546 struct kvm_cpuid2 cpuid; 3547 3548 r = -EFAULT; 3549 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid)) 3550 goto out; 3551 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid, 3552 cpuid_arg->entries); 3553 if (r) 3554 goto out; 3555 r = -EFAULT; 3556 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid)) 3557 goto out; 3558 r = 0; 3559 break; 3560 } 3561 case KVM_GET_MSRS: 3562 r = msr_io(vcpu, argp, do_get_msr, 1); 3563 break; 3564 case KVM_SET_MSRS: 3565 r = msr_io(vcpu, argp, do_set_msr, 0); 3566 break; 3567 case KVM_TPR_ACCESS_REPORTING: { 3568 struct kvm_tpr_access_ctl tac; 3569 3570 r = -EFAULT; 3571 if (copy_from_user(&tac, argp, sizeof tac)) 3572 goto out; 3573 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac); 3574 if (r) 3575 goto out; 3576 r = -EFAULT; 3577 if (copy_to_user(argp, &tac, sizeof tac)) 3578 goto out; 3579 r = 0; 3580 break; 3581 }; 3582 case KVM_SET_VAPIC_ADDR: { 3583 struct kvm_vapic_addr va; 3584 int idx; 3585 3586 r = -EINVAL; 3587 if (!lapic_in_kernel(vcpu)) 3588 goto out; 3589 r = -EFAULT; 3590 if (copy_from_user(&va, argp, sizeof va)) 3591 goto out; 3592 idx = srcu_read_lock(&vcpu->kvm->srcu); 3593 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr); 3594 srcu_read_unlock(&vcpu->kvm->srcu, idx); 3595 break; 3596 } 3597 case KVM_X86_SETUP_MCE: { 3598 u64 mcg_cap; 3599 3600 r = -EFAULT; 3601 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap)) 3602 goto out; 3603 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap); 3604 break; 3605 } 3606 case KVM_X86_SET_MCE: { 3607 struct kvm_x86_mce mce; 3608 3609 r = -EFAULT; 3610 if (copy_from_user(&mce, argp, sizeof mce)) 3611 goto out; 3612 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce); 3613 break; 3614 } 3615 case KVM_GET_VCPU_EVENTS: { 3616 struct kvm_vcpu_events events; 3617 3618 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events); 3619 3620 r = -EFAULT; 3621 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events))) 3622 break; 3623 r = 0; 3624 break; 3625 } 3626 case KVM_SET_VCPU_EVENTS: { 3627 struct kvm_vcpu_events events; 3628 3629 r = -EFAULT; 3630 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events))) 3631 break; 3632 3633 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events); 3634 break; 3635 } 3636 case KVM_GET_DEBUGREGS: { 3637 struct kvm_debugregs dbgregs; 3638 3639 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs); 3640 3641 r = -EFAULT; 3642 if (copy_to_user(argp, &dbgregs, 3643 sizeof(struct kvm_debugregs))) 3644 break; 3645 r = 0; 3646 break; 3647 } 3648 case KVM_SET_DEBUGREGS: { 3649 struct kvm_debugregs dbgregs; 3650 3651 r = -EFAULT; 3652 if (copy_from_user(&dbgregs, argp, 3653 sizeof(struct kvm_debugregs))) 3654 break; 3655 3656 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs); 3657 break; 3658 } 3659 case KVM_GET_XSAVE: { 3660 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL); 3661 r = -ENOMEM; 3662 if (!u.xsave) 3663 break; 3664 3665 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave); 3666 3667 r = -EFAULT; 3668 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave))) 3669 break; 3670 r = 0; 3671 break; 3672 } 3673 case KVM_SET_XSAVE: { 3674 u.xsave = memdup_user(argp, sizeof(*u.xsave)); 3675 if (IS_ERR(u.xsave)) 3676 return PTR_ERR(u.xsave); 3677 3678 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave); 3679 break; 3680 } 3681 case KVM_GET_XCRS: { 3682 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL); 3683 r = -ENOMEM; 3684 if (!u.xcrs) 3685 break; 3686 3687 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs); 3688 3689 r = -EFAULT; 3690 if (copy_to_user(argp, u.xcrs, 3691 sizeof(struct kvm_xcrs))) 3692 break; 3693 r = 0; 3694 break; 3695 } 3696 case KVM_SET_XCRS: { 3697 u.xcrs = memdup_user(argp, sizeof(*u.xcrs)); 3698 if (IS_ERR(u.xcrs)) 3699 return PTR_ERR(u.xcrs); 3700 3701 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs); 3702 break; 3703 } 3704 case KVM_SET_TSC_KHZ: { 3705 u32 user_tsc_khz; 3706 3707 r = -EINVAL; 3708 user_tsc_khz = (u32)arg; 3709 3710 if (user_tsc_khz >= kvm_max_guest_tsc_khz) 3711 goto out; 3712 3713 if (user_tsc_khz == 0) 3714 user_tsc_khz = tsc_khz; 3715 3716 if (!kvm_set_tsc_khz(vcpu, user_tsc_khz)) 3717 r = 0; 3718 3719 goto out; 3720 } 3721 case KVM_GET_TSC_KHZ: { 3722 r = vcpu->arch.virtual_tsc_khz; 3723 goto out; 3724 } 3725 case KVM_KVMCLOCK_CTRL: { 3726 r = kvm_set_guest_paused(vcpu); 3727 goto out; 3728 } 3729 case KVM_ENABLE_CAP: { 3730 struct kvm_enable_cap cap; 3731 3732 r = -EFAULT; 3733 if (copy_from_user(&cap, argp, sizeof(cap))) 3734 goto out; 3735 r = kvm_vcpu_ioctl_enable_cap(vcpu, &cap); 3736 break; 3737 } 3738 default: 3739 r = -EINVAL; 3740 } 3741 out: 3742 kfree(u.buffer); 3743 return r; 3744 } 3745 3746 int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf) 3747 { 3748 return VM_FAULT_SIGBUS; 3749 } 3750 3751 static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr) 3752 { 3753 int ret; 3754 3755 if (addr > (unsigned int)(-3 * PAGE_SIZE)) 3756 return -EINVAL; 3757 ret = kvm_x86_ops->set_tss_addr(kvm, addr); 3758 return ret; 3759 } 3760 3761 static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm, 3762 u64 ident_addr) 3763 { 3764 kvm->arch.ept_identity_map_addr = ident_addr; 3765 return 0; 3766 } 3767 3768 static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm, 3769 u32 kvm_nr_mmu_pages) 3770 { 3771 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES) 3772 return -EINVAL; 3773 3774 mutex_lock(&kvm->slots_lock); 3775 3776 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages); 3777 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages; 3778 3779 mutex_unlock(&kvm->slots_lock); 3780 return 0; 3781 } 3782 3783 static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm) 3784 { 3785 return kvm->arch.n_max_mmu_pages; 3786 } 3787 3788 static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip) 3789 { 3790 struct kvm_pic *pic = kvm->arch.vpic; 3791 int r; 3792 3793 r = 0; 3794 switch (chip->chip_id) { 3795 case KVM_IRQCHIP_PIC_MASTER: 3796 memcpy(&chip->chip.pic, &pic->pics[0], 3797 sizeof(struct kvm_pic_state)); 3798 break; 3799 case KVM_IRQCHIP_PIC_SLAVE: 3800 memcpy(&chip->chip.pic, &pic->pics[1], 3801 sizeof(struct kvm_pic_state)); 3802 break; 3803 case KVM_IRQCHIP_IOAPIC: 3804 kvm_get_ioapic(kvm, &chip->chip.ioapic); 3805 break; 3806 default: 3807 r = -EINVAL; 3808 break; 3809 } 3810 return r; 3811 } 3812 3813 static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip) 3814 { 3815 struct kvm_pic *pic = kvm->arch.vpic; 3816 int r; 3817 3818 r = 0; 3819 switch (chip->chip_id) { 3820 case KVM_IRQCHIP_PIC_MASTER: 3821 spin_lock(&pic->lock); 3822 memcpy(&pic->pics[0], &chip->chip.pic, 3823 sizeof(struct kvm_pic_state)); 3824 spin_unlock(&pic->lock); 3825 break; 3826 case KVM_IRQCHIP_PIC_SLAVE: 3827 spin_lock(&pic->lock); 3828 memcpy(&pic->pics[1], &chip->chip.pic, 3829 sizeof(struct kvm_pic_state)); 3830 spin_unlock(&pic->lock); 3831 break; 3832 case KVM_IRQCHIP_IOAPIC: 3833 kvm_set_ioapic(kvm, &chip->chip.ioapic); 3834 break; 3835 default: 3836 r = -EINVAL; 3837 break; 3838 } 3839 kvm_pic_update_irq(pic); 3840 return r; 3841 } 3842 3843 static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps) 3844 { 3845 struct kvm_kpit_state *kps = &kvm->arch.vpit->pit_state; 3846 3847 BUILD_BUG_ON(sizeof(*ps) != sizeof(kps->channels)); 3848 3849 mutex_lock(&kps->lock); 3850 memcpy(ps, &kps->channels, sizeof(*ps)); 3851 mutex_unlock(&kps->lock); 3852 return 0; 3853 } 3854 3855 static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps) 3856 { 3857 int i; 3858 struct kvm_pit *pit = kvm->arch.vpit; 3859 3860 mutex_lock(&pit->pit_state.lock); 3861 memcpy(&pit->pit_state.channels, ps, sizeof(*ps)); 3862 for (i = 0; i < 3; i++) 3863 kvm_pit_load_count(pit, i, ps->channels[i].count, 0); 3864 mutex_unlock(&pit->pit_state.lock); 3865 return 0; 3866 } 3867 3868 static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps) 3869 { 3870 mutex_lock(&kvm->arch.vpit->pit_state.lock); 3871 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels, 3872 sizeof(ps->channels)); 3873 ps->flags = kvm->arch.vpit->pit_state.flags; 3874 mutex_unlock(&kvm->arch.vpit->pit_state.lock); 3875 memset(&ps->reserved, 0, sizeof(ps->reserved)); 3876 return 0; 3877 } 3878 3879 static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps) 3880 { 3881 int start = 0; 3882 int i; 3883 u32 prev_legacy, cur_legacy; 3884 struct kvm_pit *pit = kvm->arch.vpit; 3885 3886 mutex_lock(&pit->pit_state.lock); 3887 prev_legacy = pit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY; 3888 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY; 3889 if (!prev_legacy && cur_legacy) 3890 start = 1; 3891 memcpy(&pit->pit_state.channels, &ps->channels, 3892 sizeof(pit->pit_state.channels)); 3893 pit->pit_state.flags = ps->flags; 3894 for (i = 0; i < 3; i++) 3895 kvm_pit_load_count(pit, i, pit->pit_state.channels[i].count, 3896 start && i == 0); 3897 mutex_unlock(&pit->pit_state.lock); 3898 return 0; 3899 } 3900 3901 static int kvm_vm_ioctl_reinject(struct kvm *kvm, 3902 struct kvm_reinject_control *control) 3903 { 3904 struct kvm_pit *pit = kvm->arch.vpit; 3905 3906 if (!pit) 3907 return -ENXIO; 3908 3909 /* pit->pit_state.lock was overloaded to prevent userspace from getting 3910 * an inconsistent state after running multiple KVM_REINJECT_CONTROL 3911 * ioctls in parallel. Use a separate lock if that ioctl isn't rare. 3912 */ 3913 mutex_lock(&pit->pit_state.lock); 3914 kvm_pit_set_reinject(pit, control->pit_reinject); 3915 mutex_unlock(&pit->pit_state.lock); 3916 3917 return 0; 3918 } 3919 3920 /** 3921 * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot 3922 * @kvm: kvm instance 3923 * @log: slot id and address to which we copy the log 3924 * 3925 * Steps 1-4 below provide general overview of dirty page logging. See 3926 * kvm_get_dirty_log_protect() function description for additional details. 3927 * 3928 * We call kvm_get_dirty_log_protect() to handle steps 1-3, upon return we 3929 * always flush the TLB (step 4) even if previous step failed and the dirty 3930 * bitmap may be corrupt. Regardless of previous outcome the KVM logging API 3931 * does not preclude user space subsequent dirty log read. Flushing TLB ensures 3932 * writes will be marked dirty for next log read. 3933 * 3934 * 1. Take a snapshot of the bit and clear it if needed. 3935 * 2. Write protect the corresponding page. 3936 * 3. Copy the snapshot to the userspace. 3937 * 4. Flush TLB's if needed. 3938 */ 3939 int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log) 3940 { 3941 bool is_dirty = false; 3942 int r; 3943 3944 mutex_lock(&kvm->slots_lock); 3945 3946 /* 3947 * Flush potentially hardware-cached dirty pages to dirty_bitmap. 3948 */ 3949 if (kvm_x86_ops->flush_log_dirty) 3950 kvm_x86_ops->flush_log_dirty(kvm); 3951 3952 r = kvm_get_dirty_log_protect(kvm, log, &is_dirty); 3953 3954 /* 3955 * All the TLBs can be flushed out of mmu lock, see the comments in 3956 * kvm_mmu_slot_remove_write_access(). 3957 */ 3958 lockdep_assert_held(&kvm->slots_lock); 3959 if (is_dirty) 3960 kvm_flush_remote_tlbs(kvm); 3961 3962 mutex_unlock(&kvm->slots_lock); 3963 return r; 3964 } 3965 3966 int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event, 3967 bool line_status) 3968 { 3969 if (!irqchip_in_kernel(kvm)) 3970 return -ENXIO; 3971 3972 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID, 3973 irq_event->irq, irq_event->level, 3974 line_status); 3975 return 0; 3976 } 3977 3978 static int kvm_vm_ioctl_enable_cap(struct kvm *kvm, 3979 struct kvm_enable_cap *cap) 3980 { 3981 int r; 3982 3983 if (cap->flags) 3984 return -EINVAL; 3985 3986 switch (cap->cap) { 3987 case KVM_CAP_DISABLE_QUIRKS: 3988 kvm->arch.disabled_quirks = cap->args[0]; 3989 r = 0; 3990 break; 3991 case KVM_CAP_SPLIT_IRQCHIP: { 3992 mutex_lock(&kvm->lock); 3993 r = -EINVAL; 3994 if (cap->args[0] > MAX_NR_RESERVED_IOAPIC_PINS) 3995 goto split_irqchip_unlock; 3996 r = -EEXIST; 3997 if (irqchip_in_kernel(kvm)) 3998 goto split_irqchip_unlock; 3999 if (kvm->created_vcpus) 4000 goto split_irqchip_unlock; 4001 r = kvm_setup_empty_irq_routing(kvm); 4002 if (r) 4003 goto split_irqchip_unlock; 4004 /* Pairs with irqchip_in_kernel. */ 4005 smp_wmb(); 4006 kvm->arch.irqchip_mode = KVM_IRQCHIP_SPLIT; 4007 kvm->arch.nr_reserved_ioapic_pins = cap->args[0]; 4008 r = 0; 4009 split_irqchip_unlock: 4010 mutex_unlock(&kvm->lock); 4011 break; 4012 } 4013 case KVM_CAP_X2APIC_API: 4014 r = -EINVAL; 4015 if (cap->args[0] & ~KVM_X2APIC_API_VALID_FLAGS) 4016 break; 4017 4018 if (cap->args[0] & KVM_X2APIC_API_USE_32BIT_IDS) 4019 kvm->arch.x2apic_format = true; 4020 if (cap->args[0] & KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK) 4021 kvm->arch.x2apic_broadcast_quirk_disabled = true; 4022 4023 r = 0; 4024 break; 4025 default: 4026 r = -EINVAL; 4027 break; 4028 } 4029 return r; 4030 } 4031 4032 long kvm_arch_vm_ioctl(struct file *filp, 4033 unsigned int ioctl, unsigned long arg) 4034 { 4035 struct kvm *kvm = filp->private_data; 4036 void __user *argp = (void __user *)arg; 4037 int r = -ENOTTY; 4038 /* 4039 * This union makes it completely explicit to gcc-3.x 4040 * that these two variables' stack usage should be 4041 * combined, not added together. 4042 */ 4043 union { 4044 struct kvm_pit_state ps; 4045 struct kvm_pit_state2 ps2; 4046 struct kvm_pit_config pit_config; 4047 } u; 4048 4049 switch (ioctl) { 4050 case KVM_SET_TSS_ADDR: 4051 r = kvm_vm_ioctl_set_tss_addr(kvm, arg); 4052 break; 4053 case KVM_SET_IDENTITY_MAP_ADDR: { 4054 u64 ident_addr; 4055 4056 mutex_lock(&kvm->lock); 4057 r = -EINVAL; 4058 if (kvm->created_vcpus) 4059 goto set_identity_unlock; 4060 r = -EFAULT; 4061 if (copy_from_user(&ident_addr, argp, sizeof ident_addr)) 4062 goto set_identity_unlock; 4063 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr); 4064 set_identity_unlock: 4065 mutex_unlock(&kvm->lock); 4066 break; 4067 } 4068 case KVM_SET_NR_MMU_PAGES: 4069 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg); 4070 break; 4071 case KVM_GET_NR_MMU_PAGES: 4072 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm); 4073 break; 4074 case KVM_CREATE_IRQCHIP: { 4075 mutex_lock(&kvm->lock); 4076 4077 r = -EEXIST; 4078 if (irqchip_in_kernel(kvm)) 4079 goto create_irqchip_unlock; 4080 4081 r = -EINVAL; 4082 if (kvm->created_vcpus) 4083 goto create_irqchip_unlock; 4084 4085 r = kvm_pic_init(kvm); 4086 if (r) 4087 goto create_irqchip_unlock; 4088 4089 r = kvm_ioapic_init(kvm); 4090 if (r) { 4091 kvm_pic_destroy(kvm); 4092 goto create_irqchip_unlock; 4093 } 4094 4095 r = kvm_setup_default_irq_routing(kvm); 4096 if (r) { 4097 kvm_ioapic_destroy(kvm); 4098 kvm_pic_destroy(kvm); 4099 goto create_irqchip_unlock; 4100 } 4101 /* Write kvm->irq_routing before enabling irqchip_in_kernel. */ 4102 smp_wmb(); 4103 kvm->arch.irqchip_mode = KVM_IRQCHIP_KERNEL; 4104 create_irqchip_unlock: 4105 mutex_unlock(&kvm->lock); 4106 break; 4107 } 4108 case KVM_CREATE_PIT: 4109 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY; 4110 goto create_pit; 4111 case KVM_CREATE_PIT2: 4112 r = -EFAULT; 4113 if (copy_from_user(&u.pit_config, argp, 4114 sizeof(struct kvm_pit_config))) 4115 goto out; 4116 create_pit: 4117 mutex_lock(&kvm->lock); 4118 r = -EEXIST; 4119 if (kvm->arch.vpit) 4120 goto create_pit_unlock; 4121 r = -ENOMEM; 4122 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags); 4123 if (kvm->arch.vpit) 4124 r = 0; 4125 create_pit_unlock: 4126 mutex_unlock(&kvm->lock); 4127 break; 4128 case KVM_GET_IRQCHIP: { 4129 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */ 4130 struct kvm_irqchip *chip; 4131 4132 chip = memdup_user(argp, sizeof(*chip)); 4133 if (IS_ERR(chip)) { 4134 r = PTR_ERR(chip); 4135 goto out; 4136 } 4137 4138 r = -ENXIO; 4139 if (!irqchip_kernel(kvm)) 4140 goto get_irqchip_out; 4141 r = kvm_vm_ioctl_get_irqchip(kvm, chip); 4142 if (r) 4143 goto get_irqchip_out; 4144 r = -EFAULT; 4145 if (copy_to_user(argp, chip, sizeof *chip)) 4146 goto get_irqchip_out; 4147 r = 0; 4148 get_irqchip_out: 4149 kfree(chip); 4150 break; 4151 } 4152 case KVM_SET_IRQCHIP: { 4153 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */ 4154 struct kvm_irqchip *chip; 4155 4156 chip = memdup_user(argp, sizeof(*chip)); 4157 if (IS_ERR(chip)) { 4158 r = PTR_ERR(chip); 4159 goto out; 4160 } 4161 4162 r = -ENXIO; 4163 if (!irqchip_kernel(kvm)) 4164 goto set_irqchip_out; 4165 r = kvm_vm_ioctl_set_irqchip(kvm, chip); 4166 if (r) 4167 goto set_irqchip_out; 4168 r = 0; 4169 set_irqchip_out: 4170 kfree(chip); 4171 break; 4172 } 4173 case KVM_GET_PIT: { 4174 r = -EFAULT; 4175 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state))) 4176 goto out; 4177 r = -ENXIO; 4178 if (!kvm->arch.vpit) 4179 goto out; 4180 r = kvm_vm_ioctl_get_pit(kvm, &u.ps); 4181 if (r) 4182 goto out; 4183 r = -EFAULT; 4184 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state))) 4185 goto out; 4186 r = 0; 4187 break; 4188 } 4189 case KVM_SET_PIT: { 4190 r = -EFAULT; 4191 if (copy_from_user(&u.ps, argp, sizeof u.ps)) 4192 goto out; 4193 r = -ENXIO; 4194 if (!kvm->arch.vpit) 4195 goto out; 4196 r = kvm_vm_ioctl_set_pit(kvm, &u.ps); 4197 break; 4198 } 4199 case KVM_GET_PIT2: { 4200 r = -ENXIO; 4201 if (!kvm->arch.vpit) 4202 goto out; 4203 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2); 4204 if (r) 4205 goto out; 4206 r = -EFAULT; 4207 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2))) 4208 goto out; 4209 r = 0; 4210 break; 4211 } 4212 case KVM_SET_PIT2: { 4213 r = -EFAULT; 4214 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2))) 4215 goto out; 4216 r = -ENXIO; 4217 if (!kvm->arch.vpit) 4218 goto out; 4219 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2); 4220 break; 4221 } 4222 case KVM_REINJECT_CONTROL: { 4223 struct kvm_reinject_control control; 4224 r = -EFAULT; 4225 if (copy_from_user(&control, argp, sizeof(control))) 4226 goto out; 4227 r = kvm_vm_ioctl_reinject(kvm, &control); 4228 break; 4229 } 4230 case KVM_SET_BOOT_CPU_ID: 4231 r = 0; 4232 mutex_lock(&kvm->lock); 4233 if (kvm->created_vcpus) 4234 r = -EBUSY; 4235 else 4236 kvm->arch.bsp_vcpu_id = arg; 4237 mutex_unlock(&kvm->lock); 4238 break; 4239 case KVM_XEN_HVM_CONFIG: { 4240 r = -EFAULT; 4241 if (copy_from_user(&kvm->arch.xen_hvm_config, argp, 4242 sizeof(struct kvm_xen_hvm_config))) 4243 goto out; 4244 r = -EINVAL; 4245 if (kvm->arch.xen_hvm_config.flags) 4246 goto out; 4247 r = 0; 4248 break; 4249 } 4250 case KVM_SET_CLOCK: { 4251 struct kvm_clock_data user_ns; 4252 u64 now_ns; 4253 4254 r = -EFAULT; 4255 if (copy_from_user(&user_ns, argp, sizeof(user_ns))) 4256 goto out; 4257 4258 r = -EINVAL; 4259 if (user_ns.flags) 4260 goto out; 4261 4262 r = 0; 4263 /* 4264 * TODO: userspace has to take care of races with VCPU_RUN, so 4265 * kvm_gen_update_masterclock() can be cut down to locked 4266 * pvclock_update_vm_gtod_copy(). 4267 */ 4268 kvm_gen_update_masterclock(kvm); 4269 now_ns = get_kvmclock_ns(kvm); 4270 kvm->arch.kvmclock_offset += user_ns.clock - now_ns; 4271 kvm_make_all_cpus_request(kvm, KVM_REQ_CLOCK_UPDATE); 4272 break; 4273 } 4274 case KVM_GET_CLOCK: { 4275 struct kvm_clock_data user_ns; 4276 u64 now_ns; 4277 4278 now_ns = get_kvmclock_ns(kvm); 4279 user_ns.clock = now_ns; 4280 user_ns.flags = kvm->arch.use_master_clock ? KVM_CLOCK_TSC_STABLE : 0; 4281 memset(&user_ns.pad, 0, sizeof(user_ns.pad)); 4282 4283 r = -EFAULT; 4284 if (copy_to_user(argp, &user_ns, sizeof(user_ns))) 4285 goto out; 4286 r = 0; 4287 break; 4288 } 4289 case KVM_ENABLE_CAP: { 4290 struct kvm_enable_cap cap; 4291 4292 r = -EFAULT; 4293 if (copy_from_user(&cap, argp, sizeof(cap))) 4294 goto out; 4295 r = kvm_vm_ioctl_enable_cap(kvm, &cap); 4296 break; 4297 } 4298 default: 4299 r = -ENOTTY; 4300 } 4301 out: 4302 return r; 4303 } 4304 4305 static void kvm_init_msr_list(void) 4306 { 4307 u32 dummy[2]; 4308 unsigned i, j; 4309 4310 for (i = j = 0; i < ARRAY_SIZE(msrs_to_save); i++) { 4311 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0) 4312 continue; 4313 4314 /* 4315 * Even MSRs that are valid in the host may not be exposed 4316 * to the guests in some cases. 4317 */ 4318 switch (msrs_to_save[i]) { 4319 case MSR_IA32_BNDCFGS: 4320 if (!kvm_x86_ops->mpx_supported()) 4321 continue; 4322 break; 4323 case MSR_TSC_AUX: 4324 if (!kvm_x86_ops->rdtscp_supported()) 4325 continue; 4326 break; 4327 default: 4328 break; 4329 } 4330 4331 if (j < i) 4332 msrs_to_save[j] = msrs_to_save[i]; 4333 j++; 4334 } 4335 num_msrs_to_save = j; 4336 4337 for (i = j = 0; i < ARRAY_SIZE(emulated_msrs); i++) { 4338 switch (emulated_msrs[i]) { 4339 case MSR_IA32_SMBASE: 4340 if (!kvm_x86_ops->cpu_has_high_real_mode_segbase()) 4341 continue; 4342 break; 4343 default: 4344 break; 4345 } 4346 4347 if (j < i) 4348 emulated_msrs[j] = emulated_msrs[i]; 4349 j++; 4350 } 4351 num_emulated_msrs = j; 4352 } 4353 4354 static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len, 4355 const void *v) 4356 { 4357 int handled = 0; 4358 int n; 4359 4360 do { 4361 n = min(len, 8); 4362 if (!(lapic_in_kernel(vcpu) && 4363 !kvm_iodevice_write(vcpu, &vcpu->arch.apic->dev, addr, n, v)) 4364 && kvm_io_bus_write(vcpu, KVM_MMIO_BUS, addr, n, v)) 4365 break; 4366 handled += n; 4367 addr += n; 4368 len -= n; 4369 v += n; 4370 } while (len); 4371 4372 return handled; 4373 } 4374 4375 static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v) 4376 { 4377 int handled = 0; 4378 int n; 4379 4380 do { 4381 n = min(len, 8); 4382 if (!(lapic_in_kernel(vcpu) && 4383 !kvm_iodevice_read(vcpu, &vcpu->arch.apic->dev, 4384 addr, n, v)) 4385 && kvm_io_bus_read(vcpu, KVM_MMIO_BUS, addr, n, v)) 4386 break; 4387 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, *(u64 *)v); 4388 handled += n; 4389 addr += n; 4390 len -= n; 4391 v += n; 4392 } while (len); 4393 4394 return handled; 4395 } 4396 4397 static void kvm_set_segment(struct kvm_vcpu *vcpu, 4398 struct kvm_segment *var, int seg) 4399 { 4400 kvm_x86_ops->set_segment(vcpu, var, seg); 4401 } 4402 4403 void kvm_get_segment(struct kvm_vcpu *vcpu, 4404 struct kvm_segment *var, int seg) 4405 { 4406 kvm_x86_ops->get_segment(vcpu, var, seg); 4407 } 4408 4409 gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access, 4410 struct x86_exception *exception) 4411 { 4412 gpa_t t_gpa; 4413 4414 BUG_ON(!mmu_is_nested(vcpu)); 4415 4416 /* NPT walks are always user-walks */ 4417 access |= PFERR_USER_MASK; 4418 t_gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, exception); 4419 4420 return t_gpa; 4421 } 4422 4423 gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva, 4424 struct x86_exception *exception) 4425 { 4426 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0; 4427 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception); 4428 } 4429 4430 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva, 4431 struct x86_exception *exception) 4432 { 4433 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0; 4434 access |= PFERR_FETCH_MASK; 4435 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception); 4436 } 4437 4438 gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva, 4439 struct x86_exception *exception) 4440 { 4441 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0; 4442 access |= PFERR_WRITE_MASK; 4443 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception); 4444 } 4445 4446 /* uses this to access any guest's mapped memory without checking CPL */ 4447 gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva, 4448 struct x86_exception *exception) 4449 { 4450 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception); 4451 } 4452 4453 static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes, 4454 struct kvm_vcpu *vcpu, u32 access, 4455 struct x86_exception *exception) 4456 { 4457 void *data = val; 4458 int r = X86EMUL_CONTINUE; 4459 4460 while (bytes) { 4461 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access, 4462 exception); 4463 unsigned offset = addr & (PAGE_SIZE-1); 4464 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset); 4465 int ret; 4466 4467 if (gpa == UNMAPPED_GVA) 4468 return X86EMUL_PROPAGATE_FAULT; 4469 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, data, 4470 offset, toread); 4471 if (ret < 0) { 4472 r = X86EMUL_IO_NEEDED; 4473 goto out; 4474 } 4475 4476 bytes -= toread; 4477 data += toread; 4478 addr += toread; 4479 } 4480 out: 4481 return r; 4482 } 4483 4484 /* used for instruction fetching */ 4485 static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt, 4486 gva_t addr, void *val, unsigned int bytes, 4487 struct x86_exception *exception) 4488 { 4489 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 4490 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0; 4491 unsigned offset; 4492 int ret; 4493 4494 /* Inline kvm_read_guest_virt_helper for speed. */ 4495 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access|PFERR_FETCH_MASK, 4496 exception); 4497 if (unlikely(gpa == UNMAPPED_GVA)) 4498 return X86EMUL_PROPAGATE_FAULT; 4499 4500 offset = addr & (PAGE_SIZE-1); 4501 if (WARN_ON(offset + bytes > PAGE_SIZE)) 4502 bytes = (unsigned)PAGE_SIZE - offset; 4503 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, val, 4504 offset, bytes); 4505 if (unlikely(ret < 0)) 4506 return X86EMUL_IO_NEEDED; 4507 4508 return X86EMUL_CONTINUE; 4509 } 4510 4511 int kvm_read_guest_virt(struct x86_emulate_ctxt *ctxt, 4512 gva_t addr, void *val, unsigned int bytes, 4513 struct x86_exception *exception) 4514 { 4515 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 4516 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0; 4517 4518 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access, 4519 exception); 4520 } 4521 EXPORT_SYMBOL_GPL(kvm_read_guest_virt); 4522 4523 static int kvm_read_guest_virt_system(struct x86_emulate_ctxt *ctxt, 4524 gva_t addr, void *val, unsigned int bytes, 4525 struct x86_exception *exception) 4526 { 4527 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 4528 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, exception); 4529 } 4530 4531 static int kvm_read_guest_phys_system(struct x86_emulate_ctxt *ctxt, 4532 unsigned long addr, void *val, unsigned int bytes) 4533 { 4534 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 4535 int r = kvm_vcpu_read_guest(vcpu, addr, val, bytes); 4536 4537 return r < 0 ? X86EMUL_IO_NEEDED : X86EMUL_CONTINUE; 4538 } 4539 4540 int kvm_write_guest_virt_system(struct x86_emulate_ctxt *ctxt, 4541 gva_t addr, void *val, 4542 unsigned int bytes, 4543 struct x86_exception *exception) 4544 { 4545 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 4546 void *data = val; 4547 int r = X86EMUL_CONTINUE; 4548 4549 while (bytes) { 4550 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, 4551 PFERR_WRITE_MASK, 4552 exception); 4553 unsigned offset = addr & (PAGE_SIZE-1); 4554 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset); 4555 int ret; 4556 4557 if (gpa == UNMAPPED_GVA) 4558 return X86EMUL_PROPAGATE_FAULT; 4559 ret = kvm_vcpu_write_guest(vcpu, gpa, data, towrite); 4560 if (ret < 0) { 4561 r = X86EMUL_IO_NEEDED; 4562 goto out; 4563 } 4564 4565 bytes -= towrite; 4566 data += towrite; 4567 addr += towrite; 4568 } 4569 out: 4570 return r; 4571 } 4572 EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system); 4573 4574 static int vcpu_is_mmio_gpa(struct kvm_vcpu *vcpu, unsigned long gva, 4575 gpa_t gpa, bool write) 4576 { 4577 /* For APIC access vmexit */ 4578 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE) 4579 return 1; 4580 4581 if (vcpu_match_mmio_gpa(vcpu, gpa)) { 4582 trace_vcpu_match_mmio(gva, gpa, write, true); 4583 return 1; 4584 } 4585 4586 return 0; 4587 } 4588 4589 static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva, 4590 gpa_t *gpa, struct x86_exception *exception, 4591 bool write) 4592 { 4593 u32 access = ((kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0) 4594 | (write ? PFERR_WRITE_MASK : 0); 4595 4596 /* 4597 * currently PKRU is only applied to ept enabled guest so 4598 * there is no pkey in EPT page table for L1 guest or EPT 4599 * shadow page table for L2 guest. 4600 */ 4601 if (vcpu_match_mmio_gva(vcpu, gva) 4602 && !permission_fault(vcpu, vcpu->arch.walk_mmu, 4603 vcpu->arch.access, 0, access)) { 4604 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT | 4605 (gva & (PAGE_SIZE - 1)); 4606 trace_vcpu_match_mmio(gva, *gpa, write, false); 4607 return 1; 4608 } 4609 4610 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception); 4611 4612 if (*gpa == UNMAPPED_GVA) 4613 return -1; 4614 4615 return vcpu_is_mmio_gpa(vcpu, gva, *gpa, write); 4616 } 4617 4618 int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa, 4619 const void *val, int bytes) 4620 { 4621 int ret; 4622 4623 ret = kvm_vcpu_write_guest(vcpu, gpa, val, bytes); 4624 if (ret < 0) 4625 return 0; 4626 kvm_page_track_write(vcpu, gpa, val, bytes); 4627 return 1; 4628 } 4629 4630 struct read_write_emulator_ops { 4631 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val, 4632 int bytes); 4633 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa, 4634 void *val, int bytes); 4635 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa, 4636 int bytes, void *val); 4637 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa, 4638 void *val, int bytes); 4639 bool write; 4640 }; 4641 4642 static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes) 4643 { 4644 if (vcpu->mmio_read_completed) { 4645 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes, 4646 vcpu->mmio_fragments[0].gpa, *(u64 *)val); 4647 vcpu->mmio_read_completed = 0; 4648 return 1; 4649 } 4650 4651 return 0; 4652 } 4653 4654 static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa, 4655 void *val, int bytes) 4656 { 4657 return !kvm_vcpu_read_guest(vcpu, gpa, val, bytes); 4658 } 4659 4660 static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa, 4661 void *val, int bytes) 4662 { 4663 return emulator_write_phys(vcpu, gpa, val, bytes); 4664 } 4665 4666 static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val) 4667 { 4668 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val); 4669 return vcpu_mmio_write(vcpu, gpa, bytes, val); 4670 } 4671 4672 static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, 4673 void *val, int bytes) 4674 { 4675 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0); 4676 return X86EMUL_IO_NEEDED; 4677 } 4678 4679 static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, 4680 void *val, int bytes) 4681 { 4682 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0]; 4683 4684 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len)); 4685 return X86EMUL_CONTINUE; 4686 } 4687 4688 static const struct read_write_emulator_ops read_emultor = { 4689 .read_write_prepare = read_prepare, 4690 .read_write_emulate = read_emulate, 4691 .read_write_mmio = vcpu_mmio_read, 4692 .read_write_exit_mmio = read_exit_mmio, 4693 }; 4694 4695 static const struct read_write_emulator_ops write_emultor = { 4696 .read_write_emulate = write_emulate, 4697 .read_write_mmio = write_mmio, 4698 .read_write_exit_mmio = write_exit_mmio, 4699 .write = true, 4700 }; 4701 4702 static int emulator_read_write_onepage(unsigned long addr, void *val, 4703 unsigned int bytes, 4704 struct x86_exception *exception, 4705 struct kvm_vcpu *vcpu, 4706 const struct read_write_emulator_ops *ops) 4707 { 4708 gpa_t gpa; 4709 int handled, ret; 4710 bool write = ops->write; 4711 struct kvm_mmio_fragment *frag; 4712 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt; 4713 4714 /* 4715 * If the exit was due to a NPF we may already have a GPA. 4716 * If the GPA is present, use it to avoid the GVA to GPA table walk. 4717 * Note, this cannot be used on string operations since string 4718 * operation using rep will only have the initial GPA from the NPF 4719 * occurred. 4720 */ 4721 if (vcpu->arch.gpa_available && 4722 emulator_can_use_gpa(ctxt) && 4723 (addr & ~PAGE_MASK) == (vcpu->arch.gpa_val & ~PAGE_MASK)) { 4724 gpa = vcpu->arch.gpa_val; 4725 ret = vcpu_is_mmio_gpa(vcpu, addr, gpa, write); 4726 } else { 4727 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write); 4728 if (ret < 0) 4729 return X86EMUL_PROPAGATE_FAULT; 4730 } 4731 4732 if (!ret && ops->read_write_emulate(vcpu, gpa, val, bytes)) 4733 return X86EMUL_CONTINUE; 4734 4735 /* 4736 * Is this MMIO handled locally? 4737 */ 4738 handled = ops->read_write_mmio(vcpu, gpa, bytes, val); 4739 if (handled == bytes) 4740 return X86EMUL_CONTINUE; 4741 4742 gpa += handled; 4743 bytes -= handled; 4744 val += handled; 4745 4746 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS); 4747 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++]; 4748 frag->gpa = gpa; 4749 frag->data = val; 4750 frag->len = bytes; 4751 return X86EMUL_CONTINUE; 4752 } 4753 4754 static int emulator_read_write(struct x86_emulate_ctxt *ctxt, 4755 unsigned long addr, 4756 void *val, unsigned int bytes, 4757 struct x86_exception *exception, 4758 const struct read_write_emulator_ops *ops) 4759 { 4760 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 4761 gpa_t gpa; 4762 int rc; 4763 4764 if (ops->read_write_prepare && 4765 ops->read_write_prepare(vcpu, val, bytes)) 4766 return X86EMUL_CONTINUE; 4767 4768 vcpu->mmio_nr_fragments = 0; 4769 4770 /* Crossing a page boundary? */ 4771 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) { 4772 int now; 4773 4774 now = -addr & ~PAGE_MASK; 4775 rc = emulator_read_write_onepage(addr, val, now, exception, 4776 vcpu, ops); 4777 4778 if (rc != X86EMUL_CONTINUE) 4779 return rc; 4780 addr += now; 4781 if (ctxt->mode != X86EMUL_MODE_PROT64) 4782 addr = (u32)addr; 4783 val += now; 4784 bytes -= now; 4785 } 4786 4787 rc = emulator_read_write_onepage(addr, val, bytes, exception, 4788 vcpu, ops); 4789 if (rc != X86EMUL_CONTINUE) 4790 return rc; 4791 4792 if (!vcpu->mmio_nr_fragments) 4793 return rc; 4794 4795 gpa = vcpu->mmio_fragments[0].gpa; 4796 4797 vcpu->mmio_needed = 1; 4798 vcpu->mmio_cur_fragment = 0; 4799 4800 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len); 4801 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write; 4802 vcpu->run->exit_reason = KVM_EXIT_MMIO; 4803 vcpu->run->mmio.phys_addr = gpa; 4804 4805 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes); 4806 } 4807 4808 static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt, 4809 unsigned long addr, 4810 void *val, 4811 unsigned int bytes, 4812 struct x86_exception *exception) 4813 { 4814 return emulator_read_write(ctxt, addr, val, bytes, 4815 exception, &read_emultor); 4816 } 4817 4818 static int emulator_write_emulated(struct x86_emulate_ctxt *ctxt, 4819 unsigned long addr, 4820 const void *val, 4821 unsigned int bytes, 4822 struct x86_exception *exception) 4823 { 4824 return emulator_read_write(ctxt, addr, (void *)val, bytes, 4825 exception, &write_emultor); 4826 } 4827 4828 #define CMPXCHG_TYPE(t, ptr, old, new) \ 4829 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old)) 4830 4831 #ifdef CONFIG_X86_64 4832 # define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new) 4833 #else 4834 # define CMPXCHG64(ptr, old, new) \ 4835 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old)) 4836 #endif 4837 4838 static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt, 4839 unsigned long addr, 4840 const void *old, 4841 const void *new, 4842 unsigned int bytes, 4843 struct x86_exception *exception) 4844 { 4845 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 4846 gpa_t gpa; 4847 struct page *page; 4848 char *kaddr; 4849 bool exchanged; 4850 4851 /* guests cmpxchg8b have to be emulated atomically */ 4852 if (bytes > 8 || (bytes & (bytes - 1))) 4853 goto emul_write; 4854 4855 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL); 4856 4857 if (gpa == UNMAPPED_GVA || 4858 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE) 4859 goto emul_write; 4860 4861 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK)) 4862 goto emul_write; 4863 4864 page = kvm_vcpu_gfn_to_page(vcpu, gpa >> PAGE_SHIFT); 4865 if (is_error_page(page)) 4866 goto emul_write; 4867 4868 kaddr = kmap_atomic(page); 4869 kaddr += offset_in_page(gpa); 4870 switch (bytes) { 4871 case 1: 4872 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new); 4873 break; 4874 case 2: 4875 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new); 4876 break; 4877 case 4: 4878 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new); 4879 break; 4880 case 8: 4881 exchanged = CMPXCHG64(kaddr, old, new); 4882 break; 4883 default: 4884 BUG(); 4885 } 4886 kunmap_atomic(kaddr); 4887 kvm_release_page_dirty(page); 4888 4889 if (!exchanged) 4890 return X86EMUL_CMPXCHG_FAILED; 4891 4892 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT); 4893 kvm_page_track_write(vcpu, gpa, new, bytes); 4894 4895 return X86EMUL_CONTINUE; 4896 4897 emul_write: 4898 printk_once(KERN_WARNING "kvm: emulating exchange as write\n"); 4899 4900 return emulator_write_emulated(ctxt, addr, new, bytes, exception); 4901 } 4902 4903 static int kernel_pio(struct kvm_vcpu *vcpu, void *pd) 4904 { 4905 int r = 0, i; 4906 4907 for (i = 0; i < vcpu->arch.pio.count; i++) { 4908 if (vcpu->arch.pio.in) 4909 r = kvm_io_bus_read(vcpu, KVM_PIO_BUS, vcpu->arch.pio.port, 4910 vcpu->arch.pio.size, pd); 4911 else 4912 r = kvm_io_bus_write(vcpu, KVM_PIO_BUS, 4913 vcpu->arch.pio.port, vcpu->arch.pio.size, 4914 pd); 4915 if (r) 4916 break; 4917 pd += vcpu->arch.pio.size; 4918 } 4919 return r; 4920 } 4921 4922 static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size, 4923 unsigned short port, void *val, 4924 unsigned int count, bool in) 4925 { 4926 vcpu->arch.pio.port = port; 4927 vcpu->arch.pio.in = in; 4928 vcpu->arch.pio.count = count; 4929 vcpu->arch.pio.size = size; 4930 4931 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) { 4932 vcpu->arch.pio.count = 0; 4933 return 1; 4934 } 4935 4936 vcpu->run->exit_reason = KVM_EXIT_IO; 4937 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT; 4938 vcpu->run->io.size = size; 4939 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE; 4940 vcpu->run->io.count = count; 4941 vcpu->run->io.port = port; 4942 4943 return 0; 4944 } 4945 4946 static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt, 4947 int size, unsigned short port, void *val, 4948 unsigned int count) 4949 { 4950 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 4951 int ret; 4952 4953 if (vcpu->arch.pio.count) 4954 goto data_avail; 4955 4956 memset(vcpu->arch.pio_data, 0, size * count); 4957 4958 ret = emulator_pio_in_out(vcpu, size, port, val, count, true); 4959 if (ret) { 4960 data_avail: 4961 memcpy(val, vcpu->arch.pio_data, size * count); 4962 trace_kvm_pio(KVM_PIO_IN, port, size, count, vcpu->arch.pio_data); 4963 vcpu->arch.pio.count = 0; 4964 return 1; 4965 } 4966 4967 return 0; 4968 } 4969 4970 static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt, 4971 int size, unsigned short port, 4972 const void *val, unsigned int count) 4973 { 4974 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 4975 4976 memcpy(vcpu->arch.pio_data, val, size * count); 4977 trace_kvm_pio(KVM_PIO_OUT, port, size, count, vcpu->arch.pio_data); 4978 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false); 4979 } 4980 4981 static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg) 4982 { 4983 return kvm_x86_ops->get_segment_base(vcpu, seg); 4984 } 4985 4986 static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address) 4987 { 4988 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address); 4989 } 4990 4991 static int kvm_emulate_wbinvd_noskip(struct kvm_vcpu *vcpu) 4992 { 4993 if (!need_emulate_wbinvd(vcpu)) 4994 return X86EMUL_CONTINUE; 4995 4996 if (kvm_x86_ops->has_wbinvd_exit()) { 4997 int cpu = get_cpu(); 4998 4999 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask); 5000 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask, 5001 wbinvd_ipi, NULL, 1); 5002 put_cpu(); 5003 cpumask_clear(vcpu->arch.wbinvd_dirty_mask); 5004 } else 5005 wbinvd(); 5006 return X86EMUL_CONTINUE; 5007 } 5008 5009 int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu) 5010 { 5011 kvm_emulate_wbinvd_noskip(vcpu); 5012 return kvm_skip_emulated_instruction(vcpu); 5013 } 5014 EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd); 5015 5016 5017 5018 static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt) 5019 { 5020 kvm_emulate_wbinvd_noskip(emul_to_vcpu(ctxt)); 5021 } 5022 5023 static int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr, 5024 unsigned long *dest) 5025 { 5026 return kvm_get_dr(emul_to_vcpu(ctxt), dr, dest); 5027 } 5028 5029 static int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr, 5030 unsigned long value) 5031 { 5032 5033 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value); 5034 } 5035 5036 static u64 mk_cr_64(u64 curr_cr, u32 new_val) 5037 { 5038 return (curr_cr & ~((1ULL << 32) - 1)) | new_val; 5039 } 5040 5041 static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr) 5042 { 5043 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 5044 unsigned long value; 5045 5046 switch (cr) { 5047 case 0: 5048 value = kvm_read_cr0(vcpu); 5049 break; 5050 case 2: 5051 value = vcpu->arch.cr2; 5052 break; 5053 case 3: 5054 value = kvm_read_cr3(vcpu); 5055 break; 5056 case 4: 5057 value = kvm_read_cr4(vcpu); 5058 break; 5059 case 8: 5060 value = kvm_get_cr8(vcpu); 5061 break; 5062 default: 5063 kvm_err("%s: unexpected cr %u\n", __func__, cr); 5064 return 0; 5065 } 5066 5067 return value; 5068 } 5069 5070 static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val) 5071 { 5072 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 5073 int res = 0; 5074 5075 switch (cr) { 5076 case 0: 5077 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val)); 5078 break; 5079 case 2: 5080 vcpu->arch.cr2 = val; 5081 break; 5082 case 3: 5083 res = kvm_set_cr3(vcpu, val); 5084 break; 5085 case 4: 5086 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val)); 5087 break; 5088 case 8: 5089 res = kvm_set_cr8(vcpu, val); 5090 break; 5091 default: 5092 kvm_err("%s: unexpected cr %u\n", __func__, cr); 5093 res = -1; 5094 } 5095 5096 return res; 5097 } 5098 5099 static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt) 5100 { 5101 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt)); 5102 } 5103 5104 static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt) 5105 { 5106 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt); 5107 } 5108 5109 static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt) 5110 { 5111 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt); 5112 } 5113 5114 static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt) 5115 { 5116 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt); 5117 } 5118 5119 static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt) 5120 { 5121 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt); 5122 } 5123 5124 static unsigned long emulator_get_cached_segment_base( 5125 struct x86_emulate_ctxt *ctxt, int seg) 5126 { 5127 return get_segment_base(emul_to_vcpu(ctxt), seg); 5128 } 5129 5130 static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector, 5131 struct desc_struct *desc, u32 *base3, 5132 int seg) 5133 { 5134 struct kvm_segment var; 5135 5136 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg); 5137 *selector = var.selector; 5138 5139 if (var.unusable) { 5140 memset(desc, 0, sizeof(*desc)); 5141 if (base3) 5142 *base3 = 0; 5143 return false; 5144 } 5145 5146 if (var.g) 5147 var.limit >>= 12; 5148 set_desc_limit(desc, var.limit); 5149 set_desc_base(desc, (unsigned long)var.base); 5150 #ifdef CONFIG_X86_64 5151 if (base3) 5152 *base3 = var.base >> 32; 5153 #endif 5154 desc->type = var.type; 5155 desc->s = var.s; 5156 desc->dpl = var.dpl; 5157 desc->p = var.present; 5158 desc->avl = var.avl; 5159 desc->l = var.l; 5160 desc->d = var.db; 5161 desc->g = var.g; 5162 5163 return true; 5164 } 5165 5166 static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector, 5167 struct desc_struct *desc, u32 base3, 5168 int seg) 5169 { 5170 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 5171 struct kvm_segment var; 5172 5173 var.selector = selector; 5174 var.base = get_desc_base(desc); 5175 #ifdef CONFIG_X86_64 5176 var.base |= ((u64)base3) << 32; 5177 #endif 5178 var.limit = get_desc_limit(desc); 5179 if (desc->g) 5180 var.limit = (var.limit << 12) | 0xfff; 5181 var.type = desc->type; 5182 var.dpl = desc->dpl; 5183 var.db = desc->d; 5184 var.s = desc->s; 5185 var.l = desc->l; 5186 var.g = desc->g; 5187 var.avl = desc->avl; 5188 var.present = desc->p; 5189 var.unusable = !var.present; 5190 var.padding = 0; 5191 5192 kvm_set_segment(vcpu, &var, seg); 5193 return; 5194 } 5195 5196 static int emulator_get_msr(struct x86_emulate_ctxt *ctxt, 5197 u32 msr_index, u64 *pdata) 5198 { 5199 struct msr_data msr; 5200 int r; 5201 5202 msr.index = msr_index; 5203 msr.host_initiated = false; 5204 r = kvm_get_msr(emul_to_vcpu(ctxt), &msr); 5205 if (r) 5206 return r; 5207 5208 *pdata = msr.data; 5209 return 0; 5210 } 5211 5212 static int emulator_set_msr(struct x86_emulate_ctxt *ctxt, 5213 u32 msr_index, u64 data) 5214 { 5215 struct msr_data msr; 5216 5217 msr.data = data; 5218 msr.index = msr_index; 5219 msr.host_initiated = false; 5220 return kvm_set_msr(emul_to_vcpu(ctxt), &msr); 5221 } 5222 5223 static u64 emulator_get_smbase(struct x86_emulate_ctxt *ctxt) 5224 { 5225 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 5226 5227 return vcpu->arch.smbase; 5228 } 5229 5230 static void emulator_set_smbase(struct x86_emulate_ctxt *ctxt, u64 smbase) 5231 { 5232 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 5233 5234 vcpu->arch.smbase = smbase; 5235 } 5236 5237 static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt, 5238 u32 pmc) 5239 { 5240 return kvm_pmu_is_valid_msr_idx(emul_to_vcpu(ctxt), pmc); 5241 } 5242 5243 static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt, 5244 u32 pmc, u64 *pdata) 5245 { 5246 return kvm_pmu_rdpmc(emul_to_vcpu(ctxt), pmc, pdata); 5247 } 5248 5249 static void emulator_halt(struct x86_emulate_ctxt *ctxt) 5250 { 5251 emul_to_vcpu(ctxt)->arch.halt_request = 1; 5252 } 5253 5254 static int emulator_intercept(struct x86_emulate_ctxt *ctxt, 5255 struct x86_instruction_info *info, 5256 enum x86_intercept_stage stage) 5257 { 5258 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage); 5259 } 5260 5261 static bool emulator_get_cpuid(struct x86_emulate_ctxt *ctxt, 5262 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx, bool check_limit) 5263 { 5264 return kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx, check_limit); 5265 } 5266 5267 static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg) 5268 { 5269 return kvm_register_read(emul_to_vcpu(ctxt), reg); 5270 } 5271 5272 static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val) 5273 { 5274 kvm_register_write(emul_to_vcpu(ctxt), reg, val); 5275 } 5276 5277 static void emulator_set_nmi_mask(struct x86_emulate_ctxt *ctxt, bool masked) 5278 { 5279 kvm_x86_ops->set_nmi_mask(emul_to_vcpu(ctxt), masked); 5280 } 5281 5282 static unsigned emulator_get_hflags(struct x86_emulate_ctxt *ctxt) 5283 { 5284 return emul_to_vcpu(ctxt)->arch.hflags; 5285 } 5286 5287 static void emulator_set_hflags(struct x86_emulate_ctxt *ctxt, unsigned emul_flags) 5288 { 5289 kvm_set_hflags(emul_to_vcpu(ctxt), emul_flags); 5290 } 5291 5292 static int emulator_pre_leave_smm(struct x86_emulate_ctxt *ctxt, u64 smbase) 5293 { 5294 return kvm_x86_ops->pre_leave_smm(emul_to_vcpu(ctxt), smbase); 5295 } 5296 5297 static const struct x86_emulate_ops emulate_ops = { 5298 .read_gpr = emulator_read_gpr, 5299 .write_gpr = emulator_write_gpr, 5300 .read_std = kvm_read_guest_virt_system, 5301 .write_std = kvm_write_guest_virt_system, 5302 .read_phys = kvm_read_guest_phys_system, 5303 .fetch = kvm_fetch_guest_virt, 5304 .read_emulated = emulator_read_emulated, 5305 .write_emulated = emulator_write_emulated, 5306 .cmpxchg_emulated = emulator_cmpxchg_emulated, 5307 .invlpg = emulator_invlpg, 5308 .pio_in_emulated = emulator_pio_in_emulated, 5309 .pio_out_emulated = emulator_pio_out_emulated, 5310 .get_segment = emulator_get_segment, 5311 .set_segment = emulator_set_segment, 5312 .get_cached_segment_base = emulator_get_cached_segment_base, 5313 .get_gdt = emulator_get_gdt, 5314 .get_idt = emulator_get_idt, 5315 .set_gdt = emulator_set_gdt, 5316 .set_idt = emulator_set_idt, 5317 .get_cr = emulator_get_cr, 5318 .set_cr = emulator_set_cr, 5319 .cpl = emulator_get_cpl, 5320 .get_dr = emulator_get_dr, 5321 .set_dr = emulator_set_dr, 5322 .get_smbase = emulator_get_smbase, 5323 .set_smbase = emulator_set_smbase, 5324 .set_msr = emulator_set_msr, 5325 .get_msr = emulator_get_msr, 5326 .check_pmc = emulator_check_pmc, 5327 .read_pmc = emulator_read_pmc, 5328 .halt = emulator_halt, 5329 .wbinvd = emulator_wbinvd, 5330 .fix_hypercall = emulator_fix_hypercall, 5331 .intercept = emulator_intercept, 5332 .get_cpuid = emulator_get_cpuid, 5333 .set_nmi_mask = emulator_set_nmi_mask, 5334 .get_hflags = emulator_get_hflags, 5335 .set_hflags = emulator_set_hflags, 5336 .pre_leave_smm = emulator_pre_leave_smm, 5337 }; 5338 5339 static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask) 5340 { 5341 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu); 5342 /* 5343 * an sti; sti; sequence only disable interrupts for the first 5344 * instruction. So, if the last instruction, be it emulated or 5345 * not, left the system with the INT_STI flag enabled, it 5346 * means that the last instruction is an sti. We should not 5347 * leave the flag on in this case. The same goes for mov ss 5348 */ 5349 if (int_shadow & mask) 5350 mask = 0; 5351 if (unlikely(int_shadow || mask)) { 5352 kvm_x86_ops->set_interrupt_shadow(vcpu, mask); 5353 if (!mask) 5354 kvm_make_request(KVM_REQ_EVENT, vcpu); 5355 } 5356 } 5357 5358 static bool inject_emulated_exception(struct kvm_vcpu *vcpu) 5359 { 5360 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt; 5361 if (ctxt->exception.vector == PF_VECTOR) 5362 return kvm_propagate_fault(vcpu, &ctxt->exception); 5363 5364 if (ctxt->exception.error_code_valid) 5365 kvm_queue_exception_e(vcpu, ctxt->exception.vector, 5366 ctxt->exception.error_code); 5367 else 5368 kvm_queue_exception(vcpu, ctxt->exception.vector); 5369 return false; 5370 } 5371 5372 static void init_emulate_ctxt(struct kvm_vcpu *vcpu) 5373 { 5374 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt; 5375 int cs_db, cs_l; 5376 5377 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l); 5378 5379 ctxt->eflags = kvm_get_rflags(vcpu); 5380 ctxt->tf = (ctxt->eflags & X86_EFLAGS_TF) != 0; 5381 5382 ctxt->eip = kvm_rip_read(vcpu); 5383 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL : 5384 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 : 5385 (cs_l && is_long_mode(vcpu)) ? X86EMUL_MODE_PROT64 : 5386 cs_db ? X86EMUL_MODE_PROT32 : 5387 X86EMUL_MODE_PROT16; 5388 BUILD_BUG_ON(HF_GUEST_MASK != X86EMUL_GUEST_MASK); 5389 BUILD_BUG_ON(HF_SMM_MASK != X86EMUL_SMM_MASK); 5390 BUILD_BUG_ON(HF_SMM_INSIDE_NMI_MASK != X86EMUL_SMM_INSIDE_NMI_MASK); 5391 5392 init_decode_cache(ctxt); 5393 vcpu->arch.emulate_regs_need_sync_from_vcpu = false; 5394 } 5395 5396 int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip) 5397 { 5398 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt; 5399 int ret; 5400 5401 init_emulate_ctxt(vcpu); 5402 5403 ctxt->op_bytes = 2; 5404 ctxt->ad_bytes = 2; 5405 ctxt->_eip = ctxt->eip + inc_eip; 5406 ret = emulate_int_real(ctxt, irq); 5407 5408 if (ret != X86EMUL_CONTINUE) 5409 return EMULATE_FAIL; 5410 5411 ctxt->eip = ctxt->_eip; 5412 kvm_rip_write(vcpu, ctxt->eip); 5413 kvm_set_rflags(vcpu, ctxt->eflags); 5414 5415 if (irq == NMI_VECTOR) 5416 vcpu->arch.nmi_pending = 0; 5417 else 5418 vcpu->arch.interrupt.pending = false; 5419 5420 return EMULATE_DONE; 5421 } 5422 EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt); 5423 5424 static int handle_emulation_failure(struct kvm_vcpu *vcpu) 5425 { 5426 int r = EMULATE_DONE; 5427 5428 ++vcpu->stat.insn_emulation_fail; 5429 trace_kvm_emulate_insn_failed(vcpu); 5430 if (!is_guest_mode(vcpu) && kvm_x86_ops->get_cpl(vcpu) == 0) { 5431 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR; 5432 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION; 5433 vcpu->run->internal.ndata = 0; 5434 r = EMULATE_USER_EXIT; 5435 } 5436 kvm_queue_exception(vcpu, UD_VECTOR); 5437 5438 return r; 5439 } 5440 5441 static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t cr2, 5442 bool write_fault_to_shadow_pgtable, 5443 int emulation_type) 5444 { 5445 gpa_t gpa = cr2; 5446 kvm_pfn_t pfn; 5447 5448 if (emulation_type & EMULTYPE_NO_REEXECUTE) 5449 return false; 5450 5451 if (!vcpu->arch.mmu.direct_map) { 5452 /* 5453 * Write permission should be allowed since only 5454 * write access need to be emulated. 5455 */ 5456 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL); 5457 5458 /* 5459 * If the mapping is invalid in guest, let cpu retry 5460 * it to generate fault. 5461 */ 5462 if (gpa == UNMAPPED_GVA) 5463 return true; 5464 } 5465 5466 /* 5467 * Do not retry the unhandleable instruction if it faults on the 5468 * readonly host memory, otherwise it will goto a infinite loop: 5469 * retry instruction -> write #PF -> emulation fail -> retry 5470 * instruction -> ... 5471 */ 5472 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa)); 5473 5474 /* 5475 * If the instruction failed on the error pfn, it can not be fixed, 5476 * report the error to userspace. 5477 */ 5478 if (is_error_noslot_pfn(pfn)) 5479 return false; 5480 5481 kvm_release_pfn_clean(pfn); 5482 5483 /* The instructions are well-emulated on direct mmu. */ 5484 if (vcpu->arch.mmu.direct_map) { 5485 unsigned int indirect_shadow_pages; 5486 5487 spin_lock(&vcpu->kvm->mmu_lock); 5488 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages; 5489 spin_unlock(&vcpu->kvm->mmu_lock); 5490 5491 if (indirect_shadow_pages) 5492 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa)); 5493 5494 return true; 5495 } 5496 5497 /* 5498 * if emulation was due to access to shadowed page table 5499 * and it failed try to unshadow page and re-enter the 5500 * guest to let CPU execute the instruction. 5501 */ 5502 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa)); 5503 5504 /* 5505 * If the access faults on its page table, it can not 5506 * be fixed by unprotecting shadow page and it should 5507 * be reported to userspace. 5508 */ 5509 return !write_fault_to_shadow_pgtable; 5510 } 5511 5512 static bool retry_instruction(struct x86_emulate_ctxt *ctxt, 5513 unsigned long cr2, int emulation_type) 5514 { 5515 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 5516 unsigned long last_retry_eip, last_retry_addr, gpa = cr2; 5517 5518 last_retry_eip = vcpu->arch.last_retry_eip; 5519 last_retry_addr = vcpu->arch.last_retry_addr; 5520 5521 /* 5522 * If the emulation is caused by #PF and it is non-page_table 5523 * writing instruction, it means the VM-EXIT is caused by shadow 5524 * page protected, we can zap the shadow page and retry this 5525 * instruction directly. 5526 * 5527 * Note: if the guest uses a non-page-table modifying instruction 5528 * on the PDE that points to the instruction, then we will unmap 5529 * the instruction and go to an infinite loop. So, we cache the 5530 * last retried eip and the last fault address, if we meet the eip 5531 * and the address again, we can break out of the potential infinite 5532 * loop. 5533 */ 5534 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0; 5535 5536 if (!(emulation_type & EMULTYPE_RETRY)) 5537 return false; 5538 5539 if (x86_page_table_writing_insn(ctxt)) 5540 return false; 5541 5542 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2) 5543 return false; 5544 5545 vcpu->arch.last_retry_eip = ctxt->eip; 5546 vcpu->arch.last_retry_addr = cr2; 5547 5548 if (!vcpu->arch.mmu.direct_map) 5549 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL); 5550 5551 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa)); 5552 5553 return true; 5554 } 5555 5556 static int complete_emulated_mmio(struct kvm_vcpu *vcpu); 5557 static int complete_emulated_pio(struct kvm_vcpu *vcpu); 5558 5559 static void kvm_smm_changed(struct kvm_vcpu *vcpu) 5560 { 5561 if (!(vcpu->arch.hflags & HF_SMM_MASK)) { 5562 /* This is a good place to trace that we are exiting SMM. */ 5563 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, false); 5564 5565 /* Process a latched INIT or SMI, if any. */ 5566 kvm_make_request(KVM_REQ_EVENT, vcpu); 5567 } 5568 5569 kvm_mmu_reset_context(vcpu); 5570 } 5571 5572 static void kvm_set_hflags(struct kvm_vcpu *vcpu, unsigned emul_flags) 5573 { 5574 unsigned changed = vcpu->arch.hflags ^ emul_flags; 5575 5576 vcpu->arch.hflags = emul_flags; 5577 5578 if (changed & HF_SMM_MASK) 5579 kvm_smm_changed(vcpu); 5580 } 5581 5582 static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7, 5583 unsigned long *db) 5584 { 5585 u32 dr6 = 0; 5586 int i; 5587 u32 enable, rwlen; 5588 5589 enable = dr7; 5590 rwlen = dr7 >> 16; 5591 for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4) 5592 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr) 5593 dr6 |= (1 << i); 5594 return dr6; 5595 } 5596 5597 static void kvm_vcpu_do_singlestep(struct kvm_vcpu *vcpu, int *r) 5598 { 5599 struct kvm_run *kvm_run = vcpu->run; 5600 5601 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) { 5602 kvm_run->debug.arch.dr6 = DR6_BS | DR6_FIXED_1 | DR6_RTM; 5603 kvm_run->debug.arch.pc = vcpu->arch.singlestep_rip; 5604 kvm_run->debug.arch.exception = DB_VECTOR; 5605 kvm_run->exit_reason = KVM_EXIT_DEBUG; 5606 *r = EMULATE_USER_EXIT; 5607 } else { 5608 /* 5609 * "Certain debug exceptions may clear bit 0-3. The 5610 * remaining contents of the DR6 register are never 5611 * cleared by the processor". 5612 */ 5613 vcpu->arch.dr6 &= ~15; 5614 vcpu->arch.dr6 |= DR6_BS | DR6_RTM; 5615 kvm_queue_exception(vcpu, DB_VECTOR); 5616 } 5617 } 5618 5619 int kvm_skip_emulated_instruction(struct kvm_vcpu *vcpu) 5620 { 5621 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu); 5622 int r = EMULATE_DONE; 5623 5624 kvm_x86_ops->skip_emulated_instruction(vcpu); 5625 5626 /* 5627 * rflags is the old, "raw" value of the flags. The new value has 5628 * not been saved yet. 5629 * 5630 * This is correct even for TF set by the guest, because "the 5631 * processor will not generate this exception after the instruction 5632 * that sets the TF flag". 5633 */ 5634 if (unlikely(rflags & X86_EFLAGS_TF)) 5635 kvm_vcpu_do_singlestep(vcpu, &r); 5636 return r == EMULATE_DONE; 5637 } 5638 EXPORT_SYMBOL_GPL(kvm_skip_emulated_instruction); 5639 5640 static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r) 5641 { 5642 if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) && 5643 (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) { 5644 struct kvm_run *kvm_run = vcpu->run; 5645 unsigned long eip = kvm_get_linear_rip(vcpu); 5646 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0, 5647 vcpu->arch.guest_debug_dr7, 5648 vcpu->arch.eff_db); 5649 5650 if (dr6 != 0) { 5651 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1 | DR6_RTM; 5652 kvm_run->debug.arch.pc = eip; 5653 kvm_run->debug.arch.exception = DB_VECTOR; 5654 kvm_run->exit_reason = KVM_EXIT_DEBUG; 5655 *r = EMULATE_USER_EXIT; 5656 return true; 5657 } 5658 } 5659 5660 if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) && 5661 !(kvm_get_rflags(vcpu) & X86_EFLAGS_RF)) { 5662 unsigned long eip = kvm_get_linear_rip(vcpu); 5663 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0, 5664 vcpu->arch.dr7, 5665 vcpu->arch.db); 5666 5667 if (dr6 != 0) { 5668 vcpu->arch.dr6 &= ~15; 5669 vcpu->arch.dr6 |= dr6 | DR6_RTM; 5670 kvm_queue_exception(vcpu, DB_VECTOR); 5671 *r = EMULATE_DONE; 5672 return true; 5673 } 5674 } 5675 5676 return false; 5677 } 5678 5679 int x86_emulate_instruction(struct kvm_vcpu *vcpu, 5680 unsigned long cr2, 5681 int emulation_type, 5682 void *insn, 5683 int insn_len) 5684 { 5685 int r; 5686 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt; 5687 bool writeback = true; 5688 bool write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable; 5689 5690 /* 5691 * Clear write_fault_to_shadow_pgtable here to ensure it is 5692 * never reused. 5693 */ 5694 vcpu->arch.write_fault_to_shadow_pgtable = false; 5695 kvm_clear_exception_queue(vcpu); 5696 5697 if (!(emulation_type & EMULTYPE_NO_DECODE)) { 5698 init_emulate_ctxt(vcpu); 5699 5700 /* 5701 * We will reenter on the same instruction since 5702 * we do not set complete_userspace_io. This does not 5703 * handle watchpoints yet, those would be handled in 5704 * the emulate_ops. 5705 */ 5706 if (kvm_vcpu_check_breakpoint(vcpu, &r)) 5707 return r; 5708 5709 ctxt->interruptibility = 0; 5710 ctxt->have_exception = false; 5711 ctxt->exception.vector = -1; 5712 ctxt->perm_ok = false; 5713 5714 ctxt->ud = emulation_type & EMULTYPE_TRAP_UD; 5715 5716 r = x86_decode_insn(ctxt, insn, insn_len); 5717 5718 trace_kvm_emulate_insn_start(vcpu); 5719 ++vcpu->stat.insn_emulation; 5720 if (r != EMULATION_OK) { 5721 if (emulation_type & EMULTYPE_TRAP_UD) 5722 return EMULATE_FAIL; 5723 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt, 5724 emulation_type)) 5725 return EMULATE_DONE; 5726 if (ctxt->have_exception && inject_emulated_exception(vcpu)) 5727 return EMULATE_DONE; 5728 if (emulation_type & EMULTYPE_SKIP) 5729 return EMULATE_FAIL; 5730 return handle_emulation_failure(vcpu); 5731 } 5732 } 5733 5734 if (emulation_type & EMULTYPE_SKIP) { 5735 kvm_rip_write(vcpu, ctxt->_eip); 5736 if (ctxt->eflags & X86_EFLAGS_RF) 5737 kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF); 5738 return EMULATE_DONE; 5739 } 5740 5741 if (retry_instruction(ctxt, cr2, emulation_type)) 5742 return EMULATE_DONE; 5743 5744 /* this is needed for vmware backdoor interface to work since it 5745 changes registers values during IO operation */ 5746 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) { 5747 vcpu->arch.emulate_regs_need_sync_from_vcpu = false; 5748 emulator_invalidate_register_cache(ctxt); 5749 } 5750 5751 restart: 5752 /* Save the faulting GPA (cr2) in the address field */ 5753 ctxt->exception.address = cr2; 5754 5755 r = x86_emulate_insn(ctxt); 5756 5757 if (r == EMULATION_INTERCEPTED) 5758 return EMULATE_DONE; 5759 5760 if (r == EMULATION_FAILED) { 5761 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt, 5762 emulation_type)) 5763 return EMULATE_DONE; 5764 5765 return handle_emulation_failure(vcpu); 5766 } 5767 5768 if (ctxt->have_exception) { 5769 r = EMULATE_DONE; 5770 if (inject_emulated_exception(vcpu)) 5771 return r; 5772 } else if (vcpu->arch.pio.count) { 5773 if (!vcpu->arch.pio.in) { 5774 /* FIXME: return into emulator if single-stepping. */ 5775 vcpu->arch.pio.count = 0; 5776 } else { 5777 writeback = false; 5778 vcpu->arch.complete_userspace_io = complete_emulated_pio; 5779 } 5780 r = EMULATE_USER_EXIT; 5781 } else if (vcpu->mmio_needed) { 5782 if (!vcpu->mmio_is_write) 5783 writeback = false; 5784 r = EMULATE_USER_EXIT; 5785 vcpu->arch.complete_userspace_io = complete_emulated_mmio; 5786 } else if (r == EMULATION_RESTART) 5787 goto restart; 5788 else 5789 r = EMULATE_DONE; 5790 5791 if (writeback) { 5792 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu); 5793 toggle_interruptibility(vcpu, ctxt->interruptibility); 5794 vcpu->arch.emulate_regs_need_sync_to_vcpu = false; 5795 kvm_rip_write(vcpu, ctxt->eip); 5796 if (r == EMULATE_DONE && 5797 (ctxt->tf || (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP))) 5798 kvm_vcpu_do_singlestep(vcpu, &r); 5799 if (!ctxt->have_exception || 5800 exception_type(ctxt->exception.vector) == EXCPT_TRAP) 5801 __kvm_set_rflags(vcpu, ctxt->eflags); 5802 5803 /* 5804 * For STI, interrupts are shadowed; so KVM_REQ_EVENT will 5805 * do nothing, and it will be requested again as soon as 5806 * the shadow expires. But we still need to check here, 5807 * because POPF has no interrupt shadow. 5808 */ 5809 if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF)) 5810 kvm_make_request(KVM_REQ_EVENT, vcpu); 5811 } else 5812 vcpu->arch.emulate_regs_need_sync_to_vcpu = true; 5813 5814 return r; 5815 } 5816 EXPORT_SYMBOL_GPL(x86_emulate_instruction); 5817 5818 int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port) 5819 { 5820 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX); 5821 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt, 5822 size, port, &val, 1); 5823 /* do not return to emulator after return from userspace */ 5824 vcpu->arch.pio.count = 0; 5825 return ret; 5826 } 5827 EXPORT_SYMBOL_GPL(kvm_fast_pio_out); 5828 5829 static int complete_fast_pio_in(struct kvm_vcpu *vcpu) 5830 { 5831 unsigned long val; 5832 5833 /* We should only ever be called with arch.pio.count equal to 1 */ 5834 BUG_ON(vcpu->arch.pio.count != 1); 5835 5836 /* For size less than 4 we merge, else we zero extend */ 5837 val = (vcpu->arch.pio.size < 4) ? kvm_register_read(vcpu, VCPU_REGS_RAX) 5838 : 0; 5839 5840 /* 5841 * Since vcpu->arch.pio.count == 1 let emulator_pio_in_emulated perform 5842 * the copy and tracing 5843 */ 5844 emulator_pio_in_emulated(&vcpu->arch.emulate_ctxt, vcpu->arch.pio.size, 5845 vcpu->arch.pio.port, &val, 1); 5846 kvm_register_write(vcpu, VCPU_REGS_RAX, val); 5847 5848 return 1; 5849 } 5850 5851 int kvm_fast_pio_in(struct kvm_vcpu *vcpu, int size, unsigned short port) 5852 { 5853 unsigned long val; 5854 int ret; 5855 5856 /* For size less than 4 we merge, else we zero extend */ 5857 val = (size < 4) ? kvm_register_read(vcpu, VCPU_REGS_RAX) : 0; 5858 5859 ret = emulator_pio_in_emulated(&vcpu->arch.emulate_ctxt, size, port, 5860 &val, 1); 5861 if (ret) { 5862 kvm_register_write(vcpu, VCPU_REGS_RAX, val); 5863 return ret; 5864 } 5865 5866 vcpu->arch.complete_userspace_io = complete_fast_pio_in; 5867 5868 return 0; 5869 } 5870 EXPORT_SYMBOL_GPL(kvm_fast_pio_in); 5871 5872 static int kvmclock_cpu_down_prep(unsigned int cpu) 5873 { 5874 __this_cpu_write(cpu_tsc_khz, 0); 5875 return 0; 5876 } 5877 5878 static void tsc_khz_changed(void *data) 5879 { 5880 struct cpufreq_freqs *freq = data; 5881 unsigned long khz = 0; 5882 5883 if (data) 5884 khz = freq->new; 5885 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) 5886 khz = cpufreq_quick_get(raw_smp_processor_id()); 5887 if (!khz) 5888 khz = tsc_khz; 5889 __this_cpu_write(cpu_tsc_khz, khz); 5890 } 5891 5892 static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val, 5893 void *data) 5894 { 5895 struct cpufreq_freqs *freq = data; 5896 struct kvm *kvm; 5897 struct kvm_vcpu *vcpu; 5898 int i, send_ipi = 0; 5899 5900 /* 5901 * We allow guests to temporarily run on slowing clocks, 5902 * provided we notify them after, or to run on accelerating 5903 * clocks, provided we notify them before. Thus time never 5904 * goes backwards. 5905 * 5906 * However, we have a problem. We can't atomically update 5907 * the frequency of a given CPU from this function; it is 5908 * merely a notifier, which can be called from any CPU. 5909 * Changing the TSC frequency at arbitrary points in time 5910 * requires a recomputation of local variables related to 5911 * the TSC for each VCPU. We must flag these local variables 5912 * to be updated and be sure the update takes place with the 5913 * new frequency before any guests proceed. 5914 * 5915 * Unfortunately, the combination of hotplug CPU and frequency 5916 * change creates an intractable locking scenario; the order 5917 * of when these callouts happen is undefined with respect to 5918 * CPU hotplug, and they can race with each other. As such, 5919 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is 5920 * undefined; you can actually have a CPU frequency change take 5921 * place in between the computation of X and the setting of the 5922 * variable. To protect against this problem, all updates of 5923 * the per_cpu tsc_khz variable are done in an interrupt 5924 * protected IPI, and all callers wishing to update the value 5925 * must wait for a synchronous IPI to complete (which is trivial 5926 * if the caller is on the CPU already). This establishes the 5927 * necessary total order on variable updates. 5928 * 5929 * Note that because a guest time update may take place 5930 * anytime after the setting of the VCPU's request bit, the 5931 * correct TSC value must be set before the request. However, 5932 * to ensure the update actually makes it to any guest which 5933 * starts running in hardware virtualization between the set 5934 * and the acquisition of the spinlock, we must also ping the 5935 * CPU after setting the request bit. 5936 * 5937 */ 5938 5939 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new) 5940 return 0; 5941 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new) 5942 return 0; 5943 5944 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1); 5945 5946 spin_lock(&kvm_lock); 5947 list_for_each_entry(kvm, &vm_list, vm_list) { 5948 kvm_for_each_vcpu(i, vcpu, kvm) { 5949 if (vcpu->cpu != freq->cpu) 5950 continue; 5951 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 5952 if (vcpu->cpu != smp_processor_id()) 5953 send_ipi = 1; 5954 } 5955 } 5956 spin_unlock(&kvm_lock); 5957 5958 if (freq->old < freq->new && send_ipi) { 5959 /* 5960 * We upscale the frequency. Must make the guest 5961 * doesn't see old kvmclock values while running with 5962 * the new frequency, otherwise we risk the guest sees 5963 * time go backwards. 5964 * 5965 * In case we update the frequency for another cpu 5966 * (which might be in guest context) send an interrupt 5967 * to kick the cpu out of guest context. Next time 5968 * guest context is entered kvmclock will be updated, 5969 * so the guest will not see stale values. 5970 */ 5971 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1); 5972 } 5973 return 0; 5974 } 5975 5976 static struct notifier_block kvmclock_cpufreq_notifier_block = { 5977 .notifier_call = kvmclock_cpufreq_notifier 5978 }; 5979 5980 static int kvmclock_cpu_online(unsigned int cpu) 5981 { 5982 tsc_khz_changed(NULL); 5983 return 0; 5984 } 5985 5986 static void kvm_timer_init(void) 5987 { 5988 max_tsc_khz = tsc_khz; 5989 5990 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) { 5991 #ifdef CONFIG_CPU_FREQ 5992 struct cpufreq_policy policy; 5993 int cpu; 5994 5995 memset(&policy, 0, sizeof(policy)); 5996 cpu = get_cpu(); 5997 cpufreq_get_policy(&policy, cpu); 5998 if (policy.cpuinfo.max_freq) 5999 max_tsc_khz = policy.cpuinfo.max_freq; 6000 put_cpu(); 6001 #endif 6002 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block, 6003 CPUFREQ_TRANSITION_NOTIFIER); 6004 } 6005 pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz); 6006 6007 cpuhp_setup_state(CPUHP_AP_X86_KVM_CLK_ONLINE, "x86/kvm/clk:online", 6008 kvmclock_cpu_online, kvmclock_cpu_down_prep); 6009 } 6010 6011 static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu); 6012 6013 int kvm_is_in_guest(void) 6014 { 6015 return __this_cpu_read(current_vcpu) != NULL; 6016 } 6017 6018 static int kvm_is_user_mode(void) 6019 { 6020 int user_mode = 3; 6021 6022 if (__this_cpu_read(current_vcpu)) 6023 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu)); 6024 6025 return user_mode != 0; 6026 } 6027 6028 static unsigned long kvm_get_guest_ip(void) 6029 { 6030 unsigned long ip = 0; 6031 6032 if (__this_cpu_read(current_vcpu)) 6033 ip = kvm_rip_read(__this_cpu_read(current_vcpu)); 6034 6035 return ip; 6036 } 6037 6038 static struct perf_guest_info_callbacks kvm_guest_cbs = { 6039 .is_in_guest = kvm_is_in_guest, 6040 .is_user_mode = kvm_is_user_mode, 6041 .get_guest_ip = kvm_get_guest_ip, 6042 }; 6043 6044 void kvm_before_handle_nmi(struct kvm_vcpu *vcpu) 6045 { 6046 __this_cpu_write(current_vcpu, vcpu); 6047 } 6048 EXPORT_SYMBOL_GPL(kvm_before_handle_nmi); 6049 6050 void kvm_after_handle_nmi(struct kvm_vcpu *vcpu) 6051 { 6052 __this_cpu_write(current_vcpu, NULL); 6053 } 6054 EXPORT_SYMBOL_GPL(kvm_after_handle_nmi); 6055 6056 static void kvm_set_mmio_spte_mask(void) 6057 { 6058 u64 mask; 6059 int maxphyaddr = boot_cpu_data.x86_phys_bits; 6060 6061 /* 6062 * Set the reserved bits and the present bit of an paging-structure 6063 * entry to generate page fault with PFER.RSV = 1. 6064 */ 6065 /* Mask the reserved physical address bits. */ 6066 mask = rsvd_bits(maxphyaddr, 51); 6067 6068 /* Set the present bit. */ 6069 mask |= 1ull; 6070 6071 #ifdef CONFIG_X86_64 6072 /* 6073 * If reserved bit is not supported, clear the present bit to disable 6074 * mmio page fault. 6075 */ 6076 if (maxphyaddr == 52) 6077 mask &= ~1ull; 6078 #endif 6079 6080 kvm_mmu_set_mmio_spte_mask(mask, mask); 6081 } 6082 6083 #ifdef CONFIG_X86_64 6084 static void pvclock_gtod_update_fn(struct work_struct *work) 6085 { 6086 struct kvm *kvm; 6087 6088 struct kvm_vcpu *vcpu; 6089 int i; 6090 6091 spin_lock(&kvm_lock); 6092 list_for_each_entry(kvm, &vm_list, vm_list) 6093 kvm_for_each_vcpu(i, vcpu, kvm) 6094 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu); 6095 atomic_set(&kvm_guest_has_master_clock, 0); 6096 spin_unlock(&kvm_lock); 6097 } 6098 6099 static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn); 6100 6101 /* 6102 * Notification about pvclock gtod data update. 6103 */ 6104 static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused, 6105 void *priv) 6106 { 6107 struct pvclock_gtod_data *gtod = &pvclock_gtod_data; 6108 struct timekeeper *tk = priv; 6109 6110 update_pvclock_gtod(tk); 6111 6112 /* disable master clock if host does not trust, or does not 6113 * use, TSC clocksource 6114 */ 6115 if (gtod->clock.vclock_mode != VCLOCK_TSC && 6116 atomic_read(&kvm_guest_has_master_clock) != 0) 6117 queue_work(system_long_wq, &pvclock_gtod_work); 6118 6119 return 0; 6120 } 6121 6122 static struct notifier_block pvclock_gtod_notifier = { 6123 .notifier_call = pvclock_gtod_notify, 6124 }; 6125 #endif 6126 6127 int kvm_arch_init(void *opaque) 6128 { 6129 int r; 6130 struct kvm_x86_ops *ops = opaque; 6131 6132 if (kvm_x86_ops) { 6133 printk(KERN_ERR "kvm: already loaded the other module\n"); 6134 r = -EEXIST; 6135 goto out; 6136 } 6137 6138 if (!ops->cpu_has_kvm_support()) { 6139 printk(KERN_ERR "kvm: no hardware support\n"); 6140 r = -EOPNOTSUPP; 6141 goto out; 6142 } 6143 if (ops->disabled_by_bios()) { 6144 printk(KERN_ERR "kvm: disabled by bios\n"); 6145 r = -EOPNOTSUPP; 6146 goto out; 6147 } 6148 6149 r = -ENOMEM; 6150 shared_msrs = alloc_percpu(struct kvm_shared_msrs); 6151 if (!shared_msrs) { 6152 printk(KERN_ERR "kvm: failed to allocate percpu kvm_shared_msrs\n"); 6153 goto out; 6154 } 6155 6156 r = kvm_mmu_module_init(); 6157 if (r) 6158 goto out_free_percpu; 6159 6160 kvm_set_mmio_spte_mask(); 6161 6162 kvm_x86_ops = ops; 6163 6164 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK, 6165 PT_DIRTY_MASK, PT64_NX_MASK, 0, 6166 PT_PRESENT_MASK, 0, sme_me_mask); 6167 kvm_timer_init(); 6168 6169 perf_register_guest_info_callbacks(&kvm_guest_cbs); 6170 6171 if (boot_cpu_has(X86_FEATURE_XSAVE)) 6172 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK); 6173 6174 kvm_lapic_init(); 6175 #ifdef CONFIG_X86_64 6176 pvclock_gtod_register_notifier(&pvclock_gtod_notifier); 6177 #endif 6178 6179 return 0; 6180 6181 out_free_percpu: 6182 free_percpu(shared_msrs); 6183 out: 6184 return r; 6185 } 6186 6187 void kvm_arch_exit(void) 6188 { 6189 kvm_lapic_exit(); 6190 perf_unregister_guest_info_callbacks(&kvm_guest_cbs); 6191 6192 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) 6193 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block, 6194 CPUFREQ_TRANSITION_NOTIFIER); 6195 cpuhp_remove_state_nocalls(CPUHP_AP_X86_KVM_CLK_ONLINE); 6196 #ifdef CONFIG_X86_64 6197 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier); 6198 #endif 6199 kvm_x86_ops = NULL; 6200 kvm_mmu_module_exit(); 6201 free_percpu(shared_msrs); 6202 } 6203 6204 int kvm_vcpu_halt(struct kvm_vcpu *vcpu) 6205 { 6206 ++vcpu->stat.halt_exits; 6207 if (lapic_in_kernel(vcpu)) { 6208 vcpu->arch.mp_state = KVM_MP_STATE_HALTED; 6209 return 1; 6210 } else { 6211 vcpu->run->exit_reason = KVM_EXIT_HLT; 6212 return 0; 6213 } 6214 } 6215 EXPORT_SYMBOL_GPL(kvm_vcpu_halt); 6216 6217 int kvm_emulate_halt(struct kvm_vcpu *vcpu) 6218 { 6219 int ret = kvm_skip_emulated_instruction(vcpu); 6220 /* 6221 * TODO: we might be squashing a GUESTDBG_SINGLESTEP-triggered 6222 * KVM_EXIT_DEBUG here. 6223 */ 6224 return kvm_vcpu_halt(vcpu) && ret; 6225 } 6226 EXPORT_SYMBOL_GPL(kvm_emulate_halt); 6227 6228 #ifdef CONFIG_X86_64 6229 static int kvm_pv_clock_pairing(struct kvm_vcpu *vcpu, gpa_t paddr, 6230 unsigned long clock_type) 6231 { 6232 struct kvm_clock_pairing clock_pairing; 6233 struct timespec ts; 6234 u64 cycle; 6235 int ret; 6236 6237 if (clock_type != KVM_CLOCK_PAIRING_WALLCLOCK) 6238 return -KVM_EOPNOTSUPP; 6239 6240 if (kvm_get_walltime_and_clockread(&ts, &cycle) == false) 6241 return -KVM_EOPNOTSUPP; 6242 6243 clock_pairing.sec = ts.tv_sec; 6244 clock_pairing.nsec = ts.tv_nsec; 6245 clock_pairing.tsc = kvm_read_l1_tsc(vcpu, cycle); 6246 clock_pairing.flags = 0; 6247 6248 ret = 0; 6249 if (kvm_write_guest(vcpu->kvm, paddr, &clock_pairing, 6250 sizeof(struct kvm_clock_pairing))) 6251 ret = -KVM_EFAULT; 6252 6253 return ret; 6254 } 6255 #endif 6256 6257 /* 6258 * kvm_pv_kick_cpu_op: Kick a vcpu. 6259 * 6260 * @apicid - apicid of vcpu to be kicked. 6261 */ 6262 static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid) 6263 { 6264 struct kvm_lapic_irq lapic_irq; 6265 6266 lapic_irq.shorthand = 0; 6267 lapic_irq.dest_mode = 0; 6268 lapic_irq.level = 0; 6269 lapic_irq.dest_id = apicid; 6270 lapic_irq.msi_redir_hint = false; 6271 6272 lapic_irq.delivery_mode = APIC_DM_REMRD; 6273 kvm_irq_delivery_to_apic(kvm, NULL, &lapic_irq, NULL); 6274 } 6275 6276 void kvm_vcpu_deactivate_apicv(struct kvm_vcpu *vcpu) 6277 { 6278 vcpu->arch.apicv_active = false; 6279 kvm_x86_ops->refresh_apicv_exec_ctrl(vcpu); 6280 } 6281 6282 int kvm_emulate_hypercall(struct kvm_vcpu *vcpu) 6283 { 6284 unsigned long nr, a0, a1, a2, a3, ret; 6285 int op_64_bit, r; 6286 6287 r = kvm_skip_emulated_instruction(vcpu); 6288 6289 if (kvm_hv_hypercall_enabled(vcpu->kvm)) 6290 return kvm_hv_hypercall(vcpu); 6291 6292 nr = kvm_register_read(vcpu, VCPU_REGS_RAX); 6293 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX); 6294 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX); 6295 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX); 6296 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI); 6297 6298 trace_kvm_hypercall(nr, a0, a1, a2, a3); 6299 6300 op_64_bit = is_64_bit_mode(vcpu); 6301 if (!op_64_bit) { 6302 nr &= 0xFFFFFFFF; 6303 a0 &= 0xFFFFFFFF; 6304 a1 &= 0xFFFFFFFF; 6305 a2 &= 0xFFFFFFFF; 6306 a3 &= 0xFFFFFFFF; 6307 } 6308 6309 if (kvm_x86_ops->get_cpl(vcpu) != 0) { 6310 ret = -KVM_EPERM; 6311 goto out; 6312 } 6313 6314 switch (nr) { 6315 case KVM_HC_VAPIC_POLL_IRQ: 6316 ret = 0; 6317 break; 6318 case KVM_HC_KICK_CPU: 6319 kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1); 6320 ret = 0; 6321 break; 6322 #ifdef CONFIG_X86_64 6323 case KVM_HC_CLOCK_PAIRING: 6324 ret = kvm_pv_clock_pairing(vcpu, a0, a1); 6325 break; 6326 #endif 6327 default: 6328 ret = -KVM_ENOSYS; 6329 break; 6330 } 6331 out: 6332 if (!op_64_bit) 6333 ret = (u32)ret; 6334 kvm_register_write(vcpu, VCPU_REGS_RAX, ret); 6335 ++vcpu->stat.hypercalls; 6336 return r; 6337 } 6338 EXPORT_SYMBOL_GPL(kvm_emulate_hypercall); 6339 6340 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt) 6341 { 6342 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 6343 char instruction[3]; 6344 unsigned long rip = kvm_rip_read(vcpu); 6345 6346 kvm_x86_ops->patch_hypercall(vcpu, instruction); 6347 6348 return emulator_write_emulated(ctxt, rip, instruction, 3, 6349 &ctxt->exception); 6350 } 6351 6352 static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu) 6353 { 6354 return vcpu->run->request_interrupt_window && 6355 likely(!pic_in_kernel(vcpu->kvm)); 6356 } 6357 6358 static void post_kvm_run_save(struct kvm_vcpu *vcpu) 6359 { 6360 struct kvm_run *kvm_run = vcpu->run; 6361 6362 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0; 6363 kvm_run->flags = is_smm(vcpu) ? KVM_RUN_X86_SMM : 0; 6364 kvm_run->cr8 = kvm_get_cr8(vcpu); 6365 kvm_run->apic_base = kvm_get_apic_base(vcpu); 6366 kvm_run->ready_for_interrupt_injection = 6367 pic_in_kernel(vcpu->kvm) || 6368 kvm_vcpu_ready_for_interrupt_injection(vcpu); 6369 } 6370 6371 static void update_cr8_intercept(struct kvm_vcpu *vcpu) 6372 { 6373 int max_irr, tpr; 6374 6375 if (!kvm_x86_ops->update_cr8_intercept) 6376 return; 6377 6378 if (!lapic_in_kernel(vcpu)) 6379 return; 6380 6381 if (vcpu->arch.apicv_active) 6382 return; 6383 6384 if (!vcpu->arch.apic->vapic_addr) 6385 max_irr = kvm_lapic_find_highest_irr(vcpu); 6386 else 6387 max_irr = -1; 6388 6389 if (max_irr != -1) 6390 max_irr >>= 4; 6391 6392 tpr = kvm_lapic_get_cr8(vcpu); 6393 6394 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr); 6395 } 6396 6397 static int inject_pending_event(struct kvm_vcpu *vcpu, bool req_int_win) 6398 { 6399 int r; 6400 6401 /* try to reinject previous events if any */ 6402 if (vcpu->arch.exception.injected) { 6403 kvm_x86_ops->queue_exception(vcpu); 6404 return 0; 6405 } 6406 6407 /* 6408 * Exceptions must be injected immediately, or the exception 6409 * frame will have the address of the NMI or interrupt handler. 6410 */ 6411 if (!vcpu->arch.exception.pending) { 6412 if (vcpu->arch.nmi_injected) { 6413 kvm_x86_ops->set_nmi(vcpu); 6414 return 0; 6415 } 6416 6417 if (vcpu->arch.interrupt.pending) { 6418 kvm_x86_ops->set_irq(vcpu); 6419 return 0; 6420 } 6421 } 6422 6423 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) { 6424 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win); 6425 if (r != 0) 6426 return r; 6427 } 6428 6429 /* try to inject new event if pending */ 6430 if (vcpu->arch.exception.pending) { 6431 trace_kvm_inj_exception(vcpu->arch.exception.nr, 6432 vcpu->arch.exception.has_error_code, 6433 vcpu->arch.exception.error_code); 6434 6435 vcpu->arch.exception.pending = false; 6436 vcpu->arch.exception.injected = true; 6437 6438 if (exception_type(vcpu->arch.exception.nr) == EXCPT_FAULT) 6439 __kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) | 6440 X86_EFLAGS_RF); 6441 6442 if (vcpu->arch.exception.nr == DB_VECTOR && 6443 (vcpu->arch.dr7 & DR7_GD)) { 6444 vcpu->arch.dr7 &= ~DR7_GD; 6445 kvm_update_dr7(vcpu); 6446 } 6447 6448 kvm_x86_ops->queue_exception(vcpu); 6449 } else if (vcpu->arch.smi_pending && !is_smm(vcpu) && kvm_x86_ops->smi_allowed(vcpu)) { 6450 vcpu->arch.smi_pending = false; 6451 enter_smm(vcpu); 6452 } else if (vcpu->arch.nmi_pending && kvm_x86_ops->nmi_allowed(vcpu)) { 6453 --vcpu->arch.nmi_pending; 6454 vcpu->arch.nmi_injected = true; 6455 kvm_x86_ops->set_nmi(vcpu); 6456 } else if (kvm_cpu_has_injectable_intr(vcpu)) { 6457 /* 6458 * Because interrupts can be injected asynchronously, we are 6459 * calling check_nested_events again here to avoid a race condition. 6460 * See https://lkml.org/lkml/2014/7/2/60 for discussion about this 6461 * proposal and current concerns. Perhaps we should be setting 6462 * KVM_REQ_EVENT only on certain events and not unconditionally? 6463 */ 6464 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) { 6465 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win); 6466 if (r != 0) 6467 return r; 6468 } 6469 if (kvm_x86_ops->interrupt_allowed(vcpu)) { 6470 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu), 6471 false); 6472 kvm_x86_ops->set_irq(vcpu); 6473 } 6474 } 6475 6476 return 0; 6477 } 6478 6479 static void process_nmi(struct kvm_vcpu *vcpu) 6480 { 6481 unsigned limit = 2; 6482 6483 /* 6484 * x86 is limited to one NMI running, and one NMI pending after it. 6485 * If an NMI is already in progress, limit further NMIs to just one. 6486 * Otherwise, allow two (and we'll inject the first one immediately). 6487 */ 6488 if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected) 6489 limit = 1; 6490 6491 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0); 6492 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit); 6493 kvm_make_request(KVM_REQ_EVENT, vcpu); 6494 } 6495 6496 static u32 enter_smm_get_segment_flags(struct kvm_segment *seg) 6497 { 6498 u32 flags = 0; 6499 flags |= seg->g << 23; 6500 flags |= seg->db << 22; 6501 flags |= seg->l << 21; 6502 flags |= seg->avl << 20; 6503 flags |= seg->present << 15; 6504 flags |= seg->dpl << 13; 6505 flags |= seg->s << 12; 6506 flags |= seg->type << 8; 6507 return flags; 6508 } 6509 6510 static void enter_smm_save_seg_32(struct kvm_vcpu *vcpu, char *buf, int n) 6511 { 6512 struct kvm_segment seg; 6513 int offset; 6514 6515 kvm_get_segment(vcpu, &seg, n); 6516 put_smstate(u32, buf, 0x7fa8 + n * 4, seg.selector); 6517 6518 if (n < 3) 6519 offset = 0x7f84 + n * 12; 6520 else 6521 offset = 0x7f2c + (n - 3) * 12; 6522 6523 put_smstate(u32, buf, offset + 8, seg.base); 6524 put_smstate(u32, buf, offset + 4, seg.limit); 6525 put_smstate(u32, buf, offset, enter_smm_get_segment_flags(&seg)); 6526 } 6527 6528 #ifdef CONFIG_X86_64 6529 static void enter_smm_save_seg_64(struct kvm_vcpu *vcpu, char *buf, int n) 6530 { 6531 struct kvm_segment seg; 6532 int offset; 6533 u16 flags; 6534 6535 kvm_get_segment(vcpu, &seg, n); 6536 offset = 0x7e00 + n * 16; 6537 6538 flags = enter_smm_get_segment_flags(&seg) >> 8; 6539 put_smstate(u16, buf, offset, seg.selector); 6540 put_smstate(u16, buf, offset + 2, flags); 6541 put_smstate(u32, buf, offset + 4, seg.limit); 6542 put_smstate(u64, buf, offset + 8, seg.base); 6543 } 6544 #endif 6545 6546 static void enter_smm_save_state_32(struct kvm_vcpu *vcpu, char *buf) 6547 { 6548 struct desc_ptr dt; 6549 struct kvm_segment seg; 6550 unsigned long val; 6551 int i; 6552 6553 put_smstate(u32, buf, 0x7ffc, kvm_read_cr0(vcpu)); 6554 put_smstate(u32, buf, 0x7ff8, kvm_read_cr3(vcpu)); 6555 put_smstate(u32, buf, 0x7ff4, kvm_get_rflags(vcpu)); 6556 put_smstate(u32, buf, 0x7ff0, kvm_rip_read(vcpu)); 6557 6558 for (i = 0; i < 8; i++) 6559 put_smstate(u32, buf, 0x7fd0 + i * 4, kvm_register_read(vcpu, i)); 6560 6561 kvm_get_dr(vcpu, 6, &val); 6562 put_smstate(u32, buf, 0x7fcc, (u32)val); 6563 kvm_get_dr(vcpu, 7, &val); 6564 put_smstate(u32, buf, 0x7fc8, (u32)val); 6565 6566 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR); 6567 put_smstate(u32, buf, 0x7fc4, seg.selector); 6568 put_smstate(u32, buf, 0x7f64, seg.base); 6569 put_smstate(u32, buf, 0x7f60, seg.limit); 6570 put_smstate(u32, buf, 0x7f5c, enter_smm_get_segment_flags(&seg)); 6571 6572 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR); 6573 put_smstate(u32, buf, 0x7fc0, seg.selector); 6574 put_smstate(u32, buf, 0x7f80, seg.base); 6575 put_smstate(u32, buf, 0x7f7c, seg.limit); 6576 put_smstate(u32, buf, 0x7f78, enter_smm_get_segment_flags(&seg)); 6577 6578 kvm_x86_ops->get_gdt(vcpu, &dt); 6579 put_smstate(u32, buf, 0x7f74, dt.address); 6580 put_smstate(u32, buf, 0x7f70, dt.size); 6581 6582 kvm_x86_ops->get_idt(vcpu, &dt); 6583 put_smstate(u32, buf, 0x7f58, dt.address); 6584 put_smstate(u32, buf, 0x7f54, dt.size); 6585 6586 for (i = 0; i < 6; i++) 6587 enter_smm_save_seg_32(vcpu, buf, i); 6588 6589 put_smstate(u32, buf, 0x7f14, kvm_read_cr4(vcpu)); 6590 6591 /* revision id */ 6592 put_smstate(u32, buf, 0x7efc, 0x00020000); 6593 put_smstate(u32, buf, 0x7ef8, vcpu->arch.smbase); 6594 } 6595 6596 static void enter_smm_save_state_64(struct kvm_vcpu *vcpu, char *buf) 6597 { 6598 #ifdef CONFIG_X86_64 6599 struct desc_ptr dt; 6600 struct kvm_segment seg; 6601 unsigned long val; 6602 int i; 6603 6604 for (i = 0; i < 16; i++) 6605 put_smstate(u64, buf, 0x7ff8 - i * 8, kvm_register_read(vcpu, i)); 6606 6607 put_smstate(u64, buf, 0x7f78, kvm_rip_read(vcpu)); 6608 put_smstate(u32, buf, 0x7f70, kvm_get_rflags(vcpu)); 6609 6610 kvm_get_dr(vcpu, 6, &val); 6611 put_smstate(u64, buf, 0x7f68, val); 6612 kvm_get_dr(vcpu, 7, &val); 6613 put_smstate(u64, buf, 0x7f60, val); 6614 6615 put_smstate(u64, buf, 0x7f58, kvm_read_cr0(vcpu)); 6616 put_smstate(u64, buf, 0x7f50, kvm_read_cr3(vcpu)); 6617 put_smstate(u64, buf, 0x7f48, kvm_read_cr4(vcpu)); 6618 6619 put_smstate(u32, buf, 0x7f00, vcpu->arch.smbase); 6620 6621 /* revision id */ 6622 put_smstate(u32, buf, 0x7efc, 0x00020064); 6623 6624 put_smstate(u64, buf, 0x7ed0, vcpu->arch.efer); 6625 6626 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR); 6627 put_smstate(u16, buf, 0x7e90, seg.selector); 6628 put_smstate(u16, buf, 0x7e92, enter_smm_get_segment_flags(&seg) >> 8); 6629 put_smstate(u32, buf, 0x7e94, seg.limit); 6630 put_smstate(u64, buf, 0x7e98, seg.base); 6631 6632 kvm_x86_ops->get_idt(vcpu, &dt); 6633 put_smstate(u32, buf, 0x7e84, dt.size); 6634 put_smstate(u64, buf, 0x7e88, dt.address); 6635 6636 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR); 6637 put_smstate(u16, buf, 0x7e70, seg.selector); 6638 put_smstate(u16, buf, 0x7e72, enter_smm_get_segment_flags(&seg) >> 8); 6639 put_smstate(u32, buf, 0x7e74, seg.limit); 6640 put_smstate(u64, buf, 0x7e78, seg.base); 6641 6642 kvm_x86_ops->get_gdt(vcpu, &dt); 6643 put_smstate(u32, buf, 0x7e64, dt.size); 6644 put_smstate(u64, buf, 0x7e68, dt.address); 6645 6646 for (i = 0; i < 6; i++) 6647 enter_smm_save_seg_64(vcpu, buf, i); 6648 #else 6649 WARN_ON_ONCE(1); 6650 #endif 6651 } 6652 6653 static void enter_smm(struct kvm_vcpu *vcpu) 6654 { 6655 struct kvm_segment cs, ds; 6656 struct desc_ptr dt; 6657 char buf[512]; 6658 u32 cr0; 6659 6660 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, true); 6661 memset(buf, 0, 512); 6662 if (guest_cpuid_has(vcpu, X86_FEATURE_LM)) 6663 enter_smm_save_state_64(vcpu, buf); 6664 else 6665 enter_smm_save_state_32(vcpu, buf); 6666 6667 /* 6668 * Give pre_enter_smm() a chance to make ISA-specific changes to the 6669 * vCPU state (e.g. leave guest mode) after we've saved the state into 6670 * the SMM state-save area. 6671 */ 6672 kvm_x86_ops->pre_enter_smm(vcpu, buf); 6673 6674 vcpu->arch.hflags |= HF_SMM_MASK; 6675 kvm_vcpu_write_guest(vcpu, vcpu->arch.smbase + 0xfe00, buf, sizeof(buf)); 6676 6677 if (kvm_x86_ops->get_nmi_mask(vcpu)) 6678 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK; 6679 else 6680 kvm_x86_ops->set_nmi_mask(vcpu, true); 6681 6682 kvm_set_rflags(vcpu, X86_EFLAGS_FIXED); 6683 kvm_rip_write(vcpu, 0x8000); 6684 6685 cr0 = vcpu->arch.cr0 & ~(X86_CR0_PE | X86_CR0_EM | X86_CR0_TS | X86_CR0_PG); 6686 kvm_x86_ops->set_cr0(vcpu, cr0); 6687 vcpu->arch.cr0 = cr0; 6688 6689 kvm_x86_ops->set_cr4(vcpu, 0); 6690 6691 /* Undocumented: IDT limit is set to zero on entry to SMM. */ 6692 dt.address = dt.size = 0; 6693 kvm_x86_ops->set_idt(vcpu, &dt); 6694 6695 __kvm_set_dr(vcpu, 7, DR7_FIXED_1); 6696 6697 cs.selector = (vcpu->arch.smbase >> 4) & 0xffff; 6698 cs.base = vcpu->arch.smbase; 6699 6700 ds.selector = 0; 6701 ds.base = 0; 6702 6703 cs.limit = ds.limit = 0xffffffff; 6704 cs.type = ds.type = 0x3; 6705 cs.dpl = ds.dpl = 0; 6706 cs.db = ds.db = 0; 6707 cs.s = ds.s = 1; 6708 cs.l = ds.l = 0; 6709 cs.g = ds.g = 1; 6710 cs.avl = ds.avl = 0; 6711 cs.present = ds.present = 1; 6712 cs.unusable = ds.unusable = 0; 6713 cs.padding = ds.padding = 0; 6714 6715 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS); 6716 kvm_set_segment(vcpu, &ds, VCPU_SREG_DS); 6717 kvm_set_segment(vcpu, &ds, VCPU_SREG_ES); 6718 kvm_set_segment(vcpu, &ds, VCPU_SREG_FS); 6719 kvm_set_segment(vcpu, &ds, VCPU_SREG_GS); 6720 kvm_set_segment(vcpu, &ds, VCPU_SREG_SS); 6721 6722 if (guest_cpuid_has(vcpu, X86_FEATURE_LM)) 6723 kvm_x86_ops->set_efer(vcpu, 0); 6724 6725 kvm_update_cpuid(vcpu); 6726 kvm_mmu_reset_context(vcpu); 6727 } 6728 6729 static void process_smi(struct kvm_vcpu *vcpu) 6730 { 6731 vcpu->arch.smi_pending = true; 6732 kvm_make_request(KVM_REQ_EVENT, vcpu); 6733 } 6734 6735 void kvm_make_scan_ioapic_request(struct kvm *kvm) 6736 { 6737 kvm_make_all_cpus_request(kvm, KVM_REQ_SCAN_IOAPIC); 6738 } 6739 6740 static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu) 6741 { 6742 u64 eoi_exit_bitmap[4]; 6743 6744 if (!kvm_apic_hw_enabled(vcpu->arch.apic)) 6745 return; 6746 6747 bitmap_zero(vcpu->arch.ioapic_handled_vectors, 256); 6748 6749 if (irqchip_split(vcpu->kvm)) 6750 kvm_scan_ioapic_routes(vcpu, vcpu->arch.ioapic_handled_vectors); 6751 else { 6752 if (kvm_x86_ops->sync_pir_to_irr && vcpu->arch.apicv_active) 6753 kvm_x86_ops->sync_pir_to_irr(vcpu); 6754 kvm_ioapic_scan_entry(vcpu, vcpu->arch.ioapic_handled_vectors); 6755 } 6756 bitmap_or((ulong *)eoi_exit_bitmap, vcpu->arch.ioapic_handled_vectors, 6757 vcpu_to_synic(vcpu)->vec_bitmap, 256); 6758 kvm_x86_ops->load_eoi_exitmap(vcpu, eoi_exit_bitmap); 6759 } 6760 6761 static void kvm_vcpu_flush_tlb(struct kvm_vcpu *vcpu) 6762 { 6763 ++vcpu->stat.tlb_flush; 6764 kvm_x86_ops->tlb_flush(vcpu); 6765 } 6766 6767 void kvm_arch_mmu_notifier_invalidate_range(struct kvm *kvm, 6768 unsigned long start, unsigned long end) 6769 { 6770 unsigned long apic_address; 6771 6772 /* 6773 * The physical address of apic access page is stored in the VMCS. 6774 * Update it when it becomes invalid. 6775 */ 6776 apic_address = gfn_to_hva(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT); 6777 if (start <= apic_address && apic_address < end) 6778 kvm_make_all_cpus_request(kvm, KVM_REQ_APIC_PAGE_RELOAD); 6779 } 6780 6781 void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu) 6782 { 6783 struct page *page = NULL; 6784 6785 if (!lapic_in_kernel(vcpu)) 6786 return; 6787 6788 if (!kvm_x86_ops->set_apic_access_page_addr) 6789 return; 6790 6791 page = gfn_to_page(vcpu->kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT); 6792 if (is_error_page(page)) 6793 return; 6794 kvm_x86_ops->set_apic_access_page_addr(vcpu, page_to_phys(page)); 6795 6796 /* 6797 * Do not pin apic access page in memory, the MMU notifier 6798 * will call us again if it is migrated or swapped out. 6799 */ 6800 put_page(page); 6801 } 6802 EXPORT_SYMBOL_GPL(kvm_vcpu_reload_apic_access_page); 6803 6804 /* 6805 * Returns 1 to let vcpu_run() continue the guest execution loop without 6806 * exiting to the userspace. Otherwise, the value will be returned to the 6807 * userspace. 6808 */ 6809 static int vcpu_enter_guest(struct kvm_vcpu *vcpu) 6810 { 6811 int r; 6812 bool req_int_win = 6813 dm_request_for_irq_injection(vcpu) && 6814 kvm_cpu_accept_dm_intr(vcpu); 6815 6816 bool req_immediate_exit = false; 6817 6818 if (kvm_request_pending(vcpu)) { 6819 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu)) 6820 kvm_mmu_unload(vcpu); 6821 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu)) 6822 __kvm_migrate_timers(vcpu); 6823 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu)) 6824 kvm_gen_update_masterclock(vcpu->kvm); 6825 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu)) 6826 kvm_gen_kvmclock_update(vcpu); 6827 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) { 6828 r = kvm_guest_time_update(vcpu); 6829 if (unlikely(r)) 6830 goto out; 6831 } 6832 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu)) 6833 kvm_mmu_sync_roots(vcpu); 6834 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu)) 6835 kvm_vcpu_flush_tlb(vcpu); 6836 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) { 6837 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS; 6838 r = 0; 6839 goto out; 6840 } 6841 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) { 6842 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN; 6843 vcpu->mmio_needed = 0; 6844 r = 0; 6845 goto out; 6846 } 6847 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) { 6848 /* Page is swapped out. Do synthetic halt */ 6849 vcpu->arch.apf.halted = true; 6850 r = 1; 6851 goto out; 6852 } 6853 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu)) 6854 record_steal_time(vcpu); 6855 if (kvm_check_request(KVM_REQ_SMI, vcpu)) 6856 process_smi(vcpu); 6857 if (kvm_check_request(KVM_REQ_NMI, vcpu)) 6858 process_nmi(vcpu); 6859 if (kvm_check_request(KVM_REQ_PMU, vcpu)) 6860 kvm_pmu_handle_event(vcpu); 6861 if (kvm_check_request(KVM_REQ_PMI, vcpu)) 6862 kvm_pmu_deliver_pmi(vcpu); 6863 if (kvm_check_request(KVM_REQ_IOAPIC_EOI_EXIT, vcpu)) { 6864 BUG_ON(vcpu->arch.pending_ioapic_eoi > 255); 6865 if (test_bit(vcpu->arch.pending_ioapic_eoi, 6866 vcpu->arch.ioapic_handled_vectors)) { 6867 vcpu->run->exit_reason = KVM_EXIT_IOAPIC_EOI; 6868 vcpu->run->eoi.vector = 6869 vcpu->arch.pending_ioapic_eoi; 6870 r = 0; 6871 goto out; 6872 } 6873 } 6874 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu)) 6875 vcpu_scan_ioapic(vcpu); 6876 if (kvm_check_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu)) 6877 kvm_vcpu_reload_apic_access_page(vcpu); 6878 if (kvm_check_request(KVM_REQ_HV_CRASH, vcpu)) { 6879 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT; 6880 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_CRASH; 6881 r = 0; 6882 goto out; 6883 } 6884 if (kvm_check_request(KVM_REQ_HV_RESET, vcpu)) { 6885 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT; 6886 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_RESET; 6887 r = 0; 6888 goto out; 6889 } 6890 if (kvm_check_request(KVM_REQ_HV_EXIT, vcpu)) { 6891 vcpu->run->exit_reason = KVM_EXIT_HYPERV; 6892 vcpu->run->hyperv = vcpu->arch.hyperv.exit; 6893 r = 0; 6894 goto out; 6895 } 6896 6897 /* 6898 * KVM_REQ_HV_STIMER has to be processed after 6899 * KVM_REQ_CLOCK_UPDATE, because Hyper-V SynIC timers 6900 * depend on the guest clock being up-to-date 6901 */ 6902 if (kvm_check_request(KVM_REQ_HV_STIMER, vcpu)) 6903 kvm_hv_process_stimers(vcpu); 6904 } 6905 6906 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) { 6907 ++vcpu->stat.req_event; 6908 kvm_apic_accept_events(vcpu); 6909 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) { 6910 r = 1; 6911 goto out; 6912 } 6913 6914 if (inject_pending_event(vcpu, req_int_win) != 0) 6915 req_immediate_exit = true; 6916 else { 6917 /* Enable SMI/NMI/IRQ window open exits if needed. 6918 * 6919 * SMIs have three cases: 6920 * 1) They can be nested, and then there is nothing to 6921 * do here because RSM will cause a vmexit anyway. 6922 * 2) There is an ISA-specific reason why SMI cannot be 6923 * injected, and the moment when this changes can be 6924 * intercepted. 6925 * 3) Or the SMI can be pending because 6926 * inject_pending_event has completed the injection 6927 * of an IRQ or NMI from the previous vmexit, and 6928 * then we request an immediate exit to inject the 6929 * SMI. 6930 */ 6931 if (vcpu->arch.smi_pending && !is_smm(vcpu)) 6932 if (!kvm_x86_ops->enable_smi_window(vcpu)) 6933 req_immediate_exit = true; 6934 if (vcpu->arch.nmi_pending) 6935 kvm_x86_ops->enable_nmi_window(vcpu); 6936 if (kvm_cpu_has_injectable_intr(vcpu) || req_int_win) 6937 kvm_x86_ops->enable_irq_window(vcpu); 6938 WARN_ON(vcpu->arch.exception.pending); 6939 } 6940 6941 if (kvm_lapic_enabled(vcpu)) { 6942 update_cr8_intercept(vcpu); 6943 kvm_lapic_sync_to_vapic(vcpu); 6944 } 6945 } 6946 6947 r = kvm_mmu_reload(vcpu); 6948 if (unlikely(r)) { 6949 goto cancel_injection; 6950 } 6951 6952 preempt_disable(); 6953 6954 kvm_x86_ops->prepare_guest_switch(vcpu); 6955 6956 /* 6957 * Disable IRQs before setting IN_GUEST_MODE. Posted interrupt 6958 * IPI are then delayed after guest entry, which ensures that they 6959 * result in virtual interrupt delivery. 6960 */ 6961 local_irq_disable(); 6962 vcpu->mode = IN_GUEST_MODE; 6963 6964 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx); 6965 6966 /* 6967 * 1) We should set ->mode before checking ->requests. Please see 6968 * the comment in kvm_vcpu_exiting_guest_mode(). 6969 * 6970 * 2) For APICv, we should set ->mode before checking PIR.ON. This 6971 * pairs with the memory barrier implicit in pi_test_and_set_on 6972 * (see vmx_deliver_posted_interrupt). 6973 * 6974 * 3) This also orders the write to mode from any reads to the page 6975 * tables done while the VCPU is running. Please see the comment 6976 * in kvm_flush_remote_tlbs. 6977 */ 6978 smp_mb__after_srcu_read_unlock(); 6979 6980 /* 6981 * This handles the case where a posted interrupt was 6982 * notified with kvm_vcpu_kick. 6983 */ 6984 if (kvm_lapic_enabled(vcpu)) { 6985 if (kvm_x86_ops->sync_pir_to_irr && vcpu->arch.apicv_active) 6986 kvm_x86_ops->sync_pir_to_irr(vcpu); 6987 } 6988 6989 if (vcpu->mode == EXITING_GUEST_MODE || kvm_request_pending(vcpu) 6990 || need_resched() || signal_pending(current)) { 6991 vcpu->mode = OUTSIDE_GUEST_MODE; 6992 smp_wmb(); 6993 local_irq_enable(); 6994 preempt_enable(); 6995 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu); 6996 r = 1; 6997 goto cancel_injection; 6998 } 6999 7000 kvm_load_guest_xcr0(vcpu); 7001 7002 if (req_immediate_exit) { 7003 kvm_make_request(KVM_REQ_EVENT, vcpu); 7004 smp_send_reschedule(vcpu->cpu); 7005 } 7006 7007 trace_kvm_entry(vcpu->vcpu_id); 7008 wait_lapic_expire(vcpu); 7009 guest_enter_irqoff(); 7010 7011 if (unlikely(vcpu->arch.switch_db_regs)) { 7012 set_debugreg(0, 7); 7013 set_debugreg(vcpu->arch.eff_db[0], 0); 7014 set_debugreg(vcpu->arch.eff_db[1], 1); 7015 set_debugreg(vcpu->arch.eff_db[2], 2); 7016 set_debugreg(vcpu->arch.eff_db[3], 3); 7017 set_debugreg(vcpu->arch.dr6, 6); 7018 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD; 7019 } 7020 7021 kvm_x86_ops->run(vcpu); 7022 7023 /* 7024 * Do this here before restoring debug registers on the host. And 7025 * since we do this before handling the vmexit, a DR access vmexit 7026 * can (a) read the correct value of the debug registers, (b) set 7027 * KVM_DEBUGREG_WONT_EXIT again. 7028 */ 7029 if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) { 7030 WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP); 7031 kvm_x86_ops->sync_dirty_debug_regs(vcpu); 7032 kvm_update_dr0123(vcpu); 7033 kvm_update_dr6(vcpu); 7034 kvm_update_dr7(vcpu); 7035 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD; 7036 } 7037 7038 /* 7039 * If the guest has used debug registers, at least dr7 7040 * will be disabled while returning to the host. 7041 * If we don't have active breakpoints in the host, we don't 7042 * care about the messed up debug address registers. But if 7043 * we have some of them active, restore the old state. 7044 */ 7045 if (hw_breakpoint_active()) 7046 hw_breakpoint_restore(); 7047 7048 vcpu->arch.last_guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc()); 7049 7050 vcpu->mode = OUTSIDE_GUEST_MODE; 7051 smp_wmb(); 7052 7053 kvm_put_guest_xcr0(vcpu); 7054 7055 kvm_x86_ops->handle_external_intr(vcpu); 7056 7057 ++vcpu->stat.exits; 7058 7059 guest_exit_irqoff(); 7060 7061 local_irq_enable(); 7062 preempt_enable(); 7063 7064 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu); 7065 7066 /* 7067 * Profile KVM exit RIPs: 7068 */ 7069 if (unlikely(prof_on == KVM_PROFILING)) { 7070 unsigned long rip = kvm_rip_read(vcpu); 7071 profile_hit(KVM_PROFILING, (void *)rip); 7072 } 7073 7074 if (unlikely(vcpu->arch.tsc_always_catchup)) 7075 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 7076 7077 if (vcpu->arch.apic_attention) 7078 kvm_lapic_sync_from_vapic(vcpu); 7079 7080 vcpu->arch.gpa_available = false; 7081 r = kvm_x86_ops->handle_exit(vcpu); 7082 return r; 7083 7084 cancel_injection: 7085 kvm_x86_ops->cancel_injection(vcpu); 7086 if (unlikely(vcpu->arch.apic_attention)) 7087 kvm_lapic_sync_from_vapic(vcpu); 7088 out: 7089 return r; 7090 } 7091 7092 static inline int vcpu_block(struct kvm *kvm, struct kvm_vcpu *vcpu) 7093 { 7094 if (!kvm_arch_vcpu_runnable(vcpu) && 7095 (!kvm_x86_ops->pre_block || kvm_x86_ops->pre_block(vcpu) == 0)) { 7096 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx); 7097 kvm_vcpu_block(vcpu); 7098 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu); 7099 7100 if (kvm_x86_ops->post_block) 7101 kvm_x86_ops->post_block(vcpu); 7102 7103 if (!kvm_check_request(KVM_REQ_UNHALT, vcpu)) 7104 return 1; 7105 } 7106 7107 kvm_apic_accept_events(vcpu); 7108 switch(vcpu->arch.mp_state) { 7109 case KVM_MP_STATE_HALTED: 7110 vcpu->arch.pv.pv_unhalted = false; 7111 vcpu->arch.mp_state = 7112 KVM_MP_STATE_RUNNABLE; 7113 case KVM_MP_STATE_RUNNABLE: 7114 vcpu->arch.apf.halted = false; 7115 break; 7116 case KVM_MP_STATE_INIT_RECEIVED: 7117 break; 7118 default: 7119 return -EINTR; 7120 break; 7121 } 7122 return 1; 7123 } 7124 7125 static inline bool kvm_vcpu_running(struct kvm_vcpu *vcpu) 7126 { 7127 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) 7128 kvm_x86_ops->check_nested_events(vcpu, false); 7129 7130 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE && 7131 !vcpu->arch.apf.halted); 7132 } 7133 7134 static int vcpu_run(struct kvm_vcpu *vcpu) 7135 { 7136 int r; 7137 struct kvm *kvm = vcpu->kvm; 7138 7139 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu); 7140 7141 for (;;) { 7142 if (kvm_vcpu_running(vcpu)) { 7143 r = vcpu_enter_guest(vcpu); 7144 } else { 7145 r = vcpu_block(kvm, vcpu); 7146 } 7147 7148 if (r <= 0) 7149 break; 7150 7151 kvm_clear_request(KVM_REQ_PENDING_TIMER, vcpu); 7152 if (kvm_cpu_has_pending_timer(vcpu)) 7153 kvm_inject_pending_timer_irqs(vcpu); 7154 7155 if (dm_request_for_irq_injection(vcpu) && 7156 kvm_vcpu_ready_for_interrupt_injection(vcpu)) { 7157 r = 0; 7158 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN; 7159 ++vcpu->stat.request_irq_exits; 7160 break; 7161 } 7162 7163 kvm_check_async_pf_completion(vcpu); 7164 7165 if (signal_pending(current)) { 7166 r = -EINTR; 7167 vcpu->run->exit_reason = KVM_EXIT_INTR; 7168 ++vcpu->stat.signal_exits; 7169 break; 7170 } 7171 if (need_resched()) { 7172 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx); 7173 cond_resched(); 7174 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu); 7175 } 7176 } 7177 7178 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx); 7179 7180 return r; 7181 } 7182 7183 static inline int complete_emulated_io(struct kvm_vcpu *vcpu) 7184 { 7185 int r; 7186 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu); 7187 r = emulate_instruction(vcpu, EMULTYPE_NO_DECODE); 7188 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx); 7189 if (r != EMULATE_DONE) 7190 return 0; 7191 return 1; 7192 } 7193 7194 static int complete_emulated_pio(struct kvm_vcpu *vcpu) 7195 { 7196 BUG_ON(!vcpu->arch.pio.count); 7197 7198 return complete_emulated_io(vcpu); 7199 } 7200 7201 /* 7202 * Implements the following, as a state machine: 7203 * 7204 * read: 7205 * for each fragment 7206 * for each mmio piece in the fragment 7207 * write gpa, len 7208 * exit 7209 * copy data 7210 * execute insn 7211 * 7212 * write: 7213 * for each fragment 7214 * for each mmio piece in the fragment 7215 * write gpa, len 7216 * copy data 7217 * exit 7218 */ 7219 static int complete_emulated_mmio(struct kvm_vcpu *vcpu) 7220 { 7221 struct kvm_run *run = vcpu->run; 7222 struct kvm_mmio_fragment *frag; 7223 unsigned len; 7224 7225 BUG_ON(!vcpu->mmio_needed); 7226 7227 /* Complete previous fragment */ 7228 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment]; 7229 len = min(8u, frag->len); 7230 if (!vcpu->mmio_is_write) 7231 memcpy(frag->data, run->mmio.data, len); 7232 7233 if (frag->len <= 8) { 7234 /* Switch to the next fragment. */ 7235 frag++; 7236 vcpu->mmio_cur_fragment++; 7237 } else { 7238 /* Go forward to the next mmio piece. */ 7239 frag->data += len; 7240 frag->gpa += len; 7241 frag->len -= len; 7242 } 7243 7244 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) { 7245 vcpu->mmio_needed = 0; 7246 7247 /* FIXME: return into emulator if single-stepping. */ 7248 if (vcpu->mmio_is_write) 7249 return 1; 7250 vcpu->mmio_read_completed = 1; 7251 return complete_emulated_io(vcpu); 7252 } 7253 7254 run->exit_reason = KVM_EXIT_MMIO; 7255 run->mmio.phys_addr = frag->gpa; 7256 if (vcpu->mmio_is_write) 7257 memcpy(run->mmio.data, frag->data, min(8u, frag->len)); 7258 run->mmio.len = min(8u, frag->len); 7259 run->mmio.is_write = vcpu->mmio_is_write; 7260 vcpu->arch.complete_userspace_io = complete_emulated_mmio; 7261 return 0; 7262 } 7263 7264 7265 int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) 7266 { 7267 struct fpu *fpu = ¤t->thread.fpu; 7268 int r; 7269 7270 fpu__initialize(fpu); 7271 7272 kvm_sigset_activate(vcpu); 7273 7274 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) { 7275 if (kvm_run->immediate_exit) { 7276 r = -EINTR; 7277 goto out; 7278 } 7279 kvm_vcpu_block(vcpu); 7280 kvm_apic_accept_events(vcpu); 7281 kvm_clear_request(KVM_REQ_UNHALT, vcpu); 7282 r = -EAGAIN; 7283 if (signal_pending(current)) { 7284 r = -EINTR; 7285 vcpu->run->exit_reason = KVM_EXIT_INTR; 7286 ++vcpu->stat.signal_exits; 7287 } 7288 goto out; 7289 } 7290 7291 /* re-sync apic's tpr */ 7292 if (!lapic_in_kernel(vcpu)) { 7293 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) { 7294 r = -EINVAL; 7295 goto out; 7296 } 7297 } 7298 7299 kvm_load_guest_fpu(vcpu); 7300 7301 if (unlikely(vcpu->arch.complete_userspace_io)) { 7302 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io; 7303 vcpu->arch.complete_userspace_io = NULL; 7304 r = cui(vcpu); 7305 if (r <= 0) 7306 goto out_fpu; 7307 } else 7308 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed); 7309 7310 if (kvm_run->immediate_exit) 7311 r = -EINTR; 7312 else 7313 r = vcpu_run(vcpu); 7314 7315 out_fpu: 7316 kvm_put_guest_fpu(vcpu); 7317 out: 7318 post_kvm_run_save(vcpu); 7319 kvm_sigset_deactivate(vcpu); 7320 7321 return r; 7322 } 7323 7324 int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) 7325 { 7326 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) { 7327 /* 7328 * We are here if userspace calls get_regs() in the middle of 7329 * instruction emulation. Registers state needs to be copied 7330 * back from emulation context to vcpu. Userspace shouldn't do 7331 * that usually, but some bad designed PV devices (vmware 7332 * backdoor interface) need this to work 7333 */ 7334 emulator_writeback_register_cache(&vcpu->arch.emulate_ctxt); 7335 vcpu->arch.emulate_regs_need_sync_to_vcpu = false; 7336 } 7337 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX); 7338 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX); 7339 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX); 7340 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX); 7341 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI); 7342 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI); 7343 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP); 7344 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP); 7345 #ifdef CONFIG_X86_64 7346 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8); 7347 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9); 7348 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10); 7349 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11); 7350 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12); 7351 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13); 7352 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14); 7353 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15); 7354 #endif 7355 7356 regs->rip = kvm_rip_read(vcpu); 7357 regs->rflags = kvm_get_rflags(vcpu); 7358 7359 return 0; 7360 } 7361 7362 int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) 7363 { 7364 vcpu->arch.emulate_regs_need_sync_from_vcpu = true; 7365 vcpu->arch.emulate_regs_need_sync_to_vcpu = false; 7366 7367 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax); 7368 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx); 7369 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx); 7370 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx); 7371 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi); 7372 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi); 7373 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp); 7374 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp); 7375 #ifdef CONFIG_X86_64 7376 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8); 7377 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9); 7378 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10); 7379 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11); 7380 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12); 7381 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13); 7382 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14); 7383 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15); 7384 #endif 7385 7386 kvm_rip_write(vcpu, regs->rip); 7387 kvm_set_rflags(vcpu, regs->rflags); 7388 7389 vcpu->arch.exception.pending = false; 7390 7391 kvm_make_request(KVM_REQ_EVENT, vcpu); 7392 7393 return 0; 7394 } 7395 7396 void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l) 7397 { 7398 struct kvm_segment cs; 7399 7400 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS); 7401 *db = cs.db; 7402 *l = cs.l; 7403 } 7404 EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits); 7405 7406 int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu, 7407 struct kvm_sregs *sregs) 7408 { 7409 struct desc_ptr dt; 7410 7411 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS); 7412 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS); 7413 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES); 7414 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS); 7415 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS); 7416 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS); 7417 7418 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR); 7419 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR); 7420 7421 kvm_x86_ops->get_idt(vcpu, &dt); 7422 sregs->idt.limit = dt.size; 7423 sregs->idt.base = dt.address; 7424 kvm_x86_ops->get_gdt(vcpu, &dt); 7425 sregs->gdt.limit = dt.size; 7426 sregs->gdt.base = dt.address; 7427 7428 sregs->cr0 = kvm_read_cr0(vcpu); 7429 sregs->cr2 = vcpu->arch.cr2; 7430 sregs->cr3 = kvm_read_cr3(vcpu); 7431 sregs->cr4 = kvm_read_cr4(vcpu); 7432 sregs->cr8 = kvm_get_cr8(vcpu); 7433 sregs->efer = vcpu->arch.efer; 7434 sregs->apic_base = kvm_get_apic_base(vcpu); 7435 7436 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap); 7437 7438 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft) 7439 set_bit(vcpu->arch.interrupt.nr, 7440 (unsigned long *)sregs->interrupt_bitmap); 7441 7442 return 0; 7443 } 7444 7445 int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu, 7446 struct kvm_mp_state *mp_state) 7447 { 7448 kvm_apic_accept_events(vcpu); 7449 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED && 7450 vcpu->arch.pv.pv_unhalted) 7451 mp_state->mp_state = KVM_MP_STATE_RUNNABLE; 7452 else 7453 mp_state->mp_state = vcpu->arch.mp_state; 7454 7455 return 0; 7456 } 7457 7458 int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu, 7459 struct kvm_mp_state *mp_state) 7460 { 7461 if (!lapic_in_kernel(vcpu) && 7462 mp_state->mp_state != KVM_MP_STATE_RUNNABLE) 7463 return -EINVAL; 7464 7465 /* INITs are latched while in SMM */ 7466 if ((is_smm(vcpu) || vcpu->arch.smi_pending) && 7467 (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED || 7468 mp_state->mp_state == KVM_MP_STATE_INIT_RECEIVED)) 7469 return -EINVAL; 7470 7471 if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) { 7472 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED; 7473 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events); 7474 } else 7475 vcpu->arch.mp_state = mp_state->mp_state; 7476 kvm_make_request(KVM_REQ_EVENT, vcpu); 7477 return 0; 7478 } 7479 7480 int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index, 7481 int reason, bool has_error_code, u32 error_code) 7482 { 7483 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt; 7484 int ret; 7485 7486 init_emulate_ctxt(vcpu); 7487 7488 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason, 7489 has_error_code, error_code); 7490 7491 if (ret) 7492 return EMULATE_FAIL; 7493 7494 kvm_rip_write(vcpu, ctxt->eip); 7495 kvm_set_rflags(vcpu, ctxt->eflags); 7496 kvm_make_request(KVM_REQ_EVENT, vcpu); 7497 return EMULATE_DONE; 7498 } 7499 EXPORT_SYMBOL_GPL(kvm_task_switch); 7500 7501 int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu, 7502 struct kvm_sregs *sregs) 7503 { 7504 struct msr_data apic_base_msr; 7505 int mmu_reset_needed = 0; 7506 int pending_vec, max_bits, idx; 7507 struct desc_ptr dt; 7508 7509 if (!guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) && 7510 (sregs->cr4 & X86_CR4_OSXSAVE)) 7511 return -EINVAL; 7512 7513 apic_base_msr.data = sregs->apic_base; 7514 apic_base_msr.host_initiated = true; 7515 if (kvm_set_apic_base(vcpu, &apic_base_msr)) 7516 return -EINVAL; 7517 7518 dt.size = sregs->idt.limit; 7519 dt.address = sregs->idt.base; 7520 kvm_x86_ops->set_idt(vcpu, &dt); 7521 dt.size = sregs->gdt.limit; 7522 dt.address = sregs->gdt.base; 7523 kvm_x86_ops->set_gdt(vcpu, &dt); 7524 7525 vcpu->arch.cr2 = sregs->cr2; 7526 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3; 7527 vcpu->arch.cr3 = sregs->cr3; 7528 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail); 7529 7530 kvm_set_cr8(vcpu, sregs->cr8); 7531 7532 mmu_reset_needed |= vcpu->arch.efer != sregs->efer; 7533 kvm_x86_ops->set_efer(vcpu, sregs->efer); 7534 7535 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0; 7536 kvm_x86_ops->set_cr0(vcpu, sregs->cr0); 7537 vcpu->arch.cr0 = sregs->cr0; 7538 7539 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4; 7540 kvm_x86_ops->set_cr4(vcpu, sregs->cr4); 7541 if (sregs->cr4 & (X86_CR4_OSXSAVE | X86_CR4_PKE)) 7542 kvm_update_cpuid(vcpu); 7543 7544 idx = srcu_read_lock(&vcpu->kvm->srcu); 7545 if (!is_long_mode(vcpu) && is_pae(vcpu)) { 7546 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu)); 7547 mmu_reset_needed = 1; 7548 } 7549 srcu_read_unlock(&vcpu->kvm->srcu, idx); 7550 7551 if (mmu_reset_needed) 7552 kvm_mmu_reset_context(vcpu); 7553 7554 max_bits = KVM_NR_INTERRUPTS; 7555 pending_vec = find_first_bit( 7556 (const unsigned long *)sregs->interrupt_bitmap, max_bits); 7557 if (pending_vec < max_bits) { 7558 kvm_queue_interrupt(vcpu, pending_vec, false); 7559 pr_debug("Set back pending irq %d\n", pending_vec); 7560 } 7561 7562 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS); 7563 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS); 7564 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES); 7565 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS); 7566 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS); 7567 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS); 7568 7569 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR); 7570 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR); 7571 7572 update_cr8_intercept(vcpu); 7573 7574 /* Older userspace won't unhalt the vcpu on reset. */ 7575 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 && 7576 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 && 7577 !is_protmode(vcpu)) 7578 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; 7579 7580 kvm_make_request(KVM_REQ_EVENT, vcpu); 7581 7582 return 0; 7583 } 7584 7585 int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu, 7586 struct kvm_guest_debug *dbg) 7587 { 7588 unsigned long rflags; 7589 int i, r; 7590 7591 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) { 7592 r = -EBUSY; 7593 if (vcpu->arch.exception.pending) 7594 goto out; 7595 if (dbg->control & KVM_GUESTDBG_INJECT_DB) 7596 kvm_queue_exception(vcpu, DB_VECTOR); 7597 else 7598 kvm_queue_exception(vcpu, BP_VECTOR); 7599 } 7600 7601 /* 7602 * Read rflags as long as potentially injected trace flags are still 7603 * filtered out. 7604 */ 7605 rflags = kvm_get_rflags(vcpu); 7606 7607 vcpu->guest_debug = dbg->control; 7608 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE)) 7609 vcpu->guest_debug = 0; 7610 7611 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) { 7612 for (i = 0; i < KVM_NR_DB_REGS; ++i) 7613 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i]; 7614 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7]; 7615 } else { 7616 for (i = 0; i < KVM_NR_DB_REGS; i++) 7617 vcpu->arch.eff_db[i] = vcpu->arch.db[i]; 7618 } 7619 kvm_update_dr7(vcpu); 7620 7621 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) 7622 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) + 7623 get_segment_base(vcpu, VCPU_SREG_CS); 7624 7625 /* 7626 * Trigger an rflags update that will inject or remove the trace 7627 * flags. 7628 */ 7629 kvm_set_rflags(vcpu, rflags); 7630 7631 kvm_x86_ops->update_bp_intercept(vcpu); 7632 7633 r = 0; 7634 7635 out: 7636 7637 return r; 7638 } 7639 7640 /* 7641 * Translate a guest virtual address to a guest physical address. 7642 */ 7643 int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu, 7644 struct kvm_translation *tr) 7645 { 7646 unsigned long vaddr = tr->linear_address; 7647 gpa_t gpa; 7648 int idx; 7649 7650 idx = srcu_read_lock(&vcpu->kvm->srcu); 7651 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL); 7652 srcu_read_unlock(&vcpu->kvm->srcu, idx); 7653 tr->physical_address = gpa; 7654 tr->valid = gpa != UNMAPPED_GVA; 7655 tr->writeable = 1; 7656 tr->usermode = 0; 7657 7658 return 0; 7659 } 7660 7661 int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu) 7662 { 7663 struct fxregs_state *fxsave = 7664 &vcpu->arch.guest_fpu.state.fxsave; 7665 7666 memcpy(fpu->fpr, fxsave->st_space, 128); 7667 fpu->fcw = fxsave->cwd; 7668 fpu->fsw = fxsave->swd; 7669 fpu->ftwx = fxsave->twd; 7670 fpu->last_opcode = fxsave->fop; 7671 fpu->last_ip = fxsave->rip; 7672 fpu->last_dp = fxsave->rdp; 7673 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space); 7674 7675 return 0; 7676 } 7677 7678 int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu) 7679 { 7680 struct fxregs_state *fxsave = 7681 &vcpu->arch.guest_fpu.state.fxsave; 7682 7683 memcpy(fxsave->st_space, fpu->fpr, 128); 7684 fxsave->cwd = fpu->fcw; 7685 fxsave->swd = fpu->fsw; 7686 fxsave->twd = fpu->ftwx; 7687 fxsave->fop = fpu->last_opcode; 7688 fxsave->rip = fpu->last_ip; 7689 fxsave->rdp = fpu->last_dp; 7690 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space); 7691 7692 return 0; 7693 } 7694 7695 static void fx_init(struct kvm_vcpu *vcpu) 7696 { 7697 fpstate_init(&vcpu->arch.guest_fpu.state); 7698 if (boot_cpu_has(X86_FEATURE_XSAVES)) 7699 vcpu->arch.guest_fpu.state.xsave.header.xcomp_bv = 7700 host_xcr0 | XSTATE_COMPACTION_ENABLED; 7701 7702 /* 7703 * Ensure guest xcr0 is valid for loading 7704 */ 7705 vcpu->arch.xcr0 = XFEATURE_MASK_FP; 7706 7707 vcpu->arch.cr0 |= X86_CR0_ET; 7708 } 7709 7710 /* Swap (qemu) user FPU context for the guest FPU context. */ 7711 void kvm_load_guest_fpu(struct kvm_vcpu *vcpu) 7712 { 7713 preempt_disable(); 7714 copy_fpregs_to_fpstate(&vcpu->arch.user_fpu); 7715 /* PKRU is separately restored in kvm_x86_ops->run. */ 7716 __copy_kernel_to_fpregs(&vcpu->arch.guest_fpu.state, 7717 ~XFEATURE_MASK_PKRU); 7718 preempt_enable(); 7719 trace_kvm_fpu(1); 7720 } 7721 7722 /* When vcpu_run ends, restore user space FPU context. */ 7723 void kvm_put_guest_fpu(struct kvm_vcpu *vcpu) 7724 { 7725 preempt_disable(); 7726 copy_fpregs_to_fpstate(&vcpu->arch.guest_fpu); 7727 copy_kernel_to_fpregs(&vcpu->arch.user_fpu.state); 7728 preempt_enable(); 7729 ++vcpu->stat.fpu_reload; 7730 trace_kvm_fpu(0); 7731 } 7732 7733 void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu) 7734 { 7735 void *wbinvd_dirty_mask = vcpu->arch.wbinvd_dirty_mask; 7736 7737 kvmclock_reset(vcpu); 7738 7739 kvm_x86_ops->vcpu_free(vcpu); 7740 free_cpumask_var(wbinvd_dirty_mask); 7741 } 7742 7743 struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm, 7744 unsigned int id) 7745 { 7746 struct kvm_vcpu *vcpu; 7747 7748 if (check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0) 7749 printk_once(KERN_WARNING 7750 "kvm: SMP vm created on host with unstable TSC; " 7751 "guest TSC will not be reliable\n"); 7752 7753 vcpu = kvm_x86_ops->vcpu_create(kvm, id); 7754 7755 return vcpu; 7756 } 7757 7758 int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu) 7759 { 7760 int r; 7761 7762 kvm_vcpu_mtrr_init(vcpu); 7763 r = vcpu_load(vcpu); 7764 if (r) 7765 return r; 7766 kvm_vcpu_reset(vcpu, false); 7767 kvm_mmu_setup(vcpu); 7768 vcpu_put(vcpu); 7769 return r; 7770 } 7771 7772 void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu) 7773 { 7774 struct msr_data msr; 7775 struct kvm *kvm = vcpu->kvm; 7776 7777 kvm_hv_vcpu_postcreate(vcpu); 7778 7779 if (vcpu_load(vcpu)) 7780 return; 7781 msr.data = 0x0; 7782 msr.index = MSR_IA32_TSC; 7783 msr.host_initiated = true; 7784 kvm_write_tsc(vcpu, &msr); 7785 vcpu_put(vcpu); 7786 7787 if (!kvmclock_periodic_sync) 7788 return; 7789 7790 schedule_delayed_work(&kvm->arch.kvmclock_sync_work, 7791 KVMCLOCK_SYNC_PERIOD); 7792 } 7793 7794 void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu) 7795 { 7796 int r; 7797 vcpu->arch.apf.msr_val = 0; 7798 7799 r = vcpu_load(vcpu); 7800 BUG_ON(r); 7801 kvm_mmu_unload(vcpu); 7802 vcpu_put(vcpu); 7803 7804 kvm_x86_ops->vcpu_free(vcpu); 7805 } 7806 7807 void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event) 7808 { 7809 vcpu->arch.hflags = 0; 7810 7811 vcpu->arch.smi_pending = 0; 7812 atomic_set(&vcpu->arch.nmi_queued, 0); 7813 vcpu->arch.nmi_pending = 0; 7814 vcpu->arch.nmi_injected = false; 7815 kvm_clear_interrupt_queue(vcpu); 7816 kvm_clear_exception_queue(vcpu); 7817 vcpu->arch.exception.pending = false; 7818 7819 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db)); 7820 kvm_update_dr0123(vcpu); 7821 vcpu->arch.dr6 = DR6_INIT; 7822 kvm_update_dr6(vcpu); 7823 vcpu->arch.dr7 = DR7_FIXED_1; 7824 kvm_update_dr7(vcpu); 7825 7826 vcpu->arch.cr2 = 0; 7827 7828 kvm_make_request(KVM_REQ_EVENT, vcpu); 7829 vcpu->arch.apf.msr_val = 0; 7830 vcpu->arch.st.msr_val = 0; 7831 7832 kvmclock_reset(vcpu); 7833 7834 kvm_clear_async_pf_completion_queue(vcpu); 7835 kvm_async_pf_hash_reset(vcpu); 7836 vcpu->arch.apf.halted = false; 7837 7838 if (kvm_mpx_supported()) { 7839 void *mpx_state_buffer; 7840 7841 /* 7842 * To avoid have the INIT path from kvm_apic_has_events() that be 7843 * called with loaded FPU and does not let userspace fix the state. 7844 */ 7845 if (init_event) 7846 kvm_put_guest_fpu(vcpu); 7847 mpx_state_buffer = get_xsave_addr(&vcpu->arch.guest_fpu.state.xsave, 7848 XFEATURE_MASK_BNDREGS); 7849 if (mpx_state_buffer) 7850 memset(mpx_state_buffer, 0, sizeof(struct mpx_bndreg_state)); 7851 mpx_state_buffer = get_xsave_addr(&vcpu->arch.guest_fpu.state.xsave, 7852 XFEATURE_MASK_BNDCSR); 7853 if (mpx_state_buffer) 7854 memset(mpx_state_buffer, 0, sizeof(struct mpx_bndcsr)); 7855 if (init_event) 7856 kvm_load_guest_fpu(vcpu); 7857 } 7858 7859 if (!init_event) { 7860 kvm_pmu_reset(vcpu); 7861 vcpu->arch.smbase = 0x30000; 7862 7863 vcpu->arch.msr_platform_info = MSR_PLATFORM_INFO_CPUID_FAULT; 7864 vcpu->arch.msr_misc_features_enables = 0; 7865 7866 vcpu->arch.xcr0 = XFEATURE_MASK_FP; 7867 } 7868 7869 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs)); 7870 vcpu->arch.regs_avail = ~0; 7871 vcpu->arch.regs_dirty = ~0; 7872 7873 vcpu->arch.ia32_xss = 0; 7874 7875 kvm_x86_ops->vcpu_reset(vcpu, init_event); 7876 } 7877 7878 void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector) 7879 { 7880 struct kvm_segment cs; 7881 7882 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS); 7883 cs.selector = vector << 8; 7884 cs.base = vector << 12; 7885 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS); 7886 kvm_rip_write(vcpu, 0); 7887 } 7888 7889 int kvm_arch_hardware_enable(void) 7890 { 7891 struct kvm *kvm; 7892 struct kvm_vcpu *vcpu; 7893 int i; 7894 int ret; 7895 u64 local_tsc; 7896 u64 max_tsc = 0; 7897 bool stable, backwards_tsc = false; 7898 7899 kvm_shared_msr_cpu_online(); 7900 ret = kvm_x86_ops->hardware_enable(); 7901 if (ret != 0) 7902 return ret; 7903 7904 local_tsc = rdtsc(); 7905 stable = !check_tsc_unstable(); 7906 list_for_each_entry(kvm, &vm_list, vm_list) { 7907 kvm_for_each_vcpu(i, vcpu, kvm) { 7908 if (!stable && vcpu->cpu == smp_processor_id()) 7909 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 7910 if (stable && vcpu->arch.last_host_tsc > local_tsc) { 7911 backwards_tsc = true; 7912 if (vcpu->arch.last_host_tsc > max_tsc) 7913 max_tsc = vcpu->arch.last_host_tsc; 7914 } 7915 } 7916 } 7917 7918 /* 7919 * Sometimes, even reliable TSCs go backwards. This happens on 7920 * platforms that reset TSC during suspend or hibernate actions, but 7921 * maintain synchronization. We must compensate. Fortunately, we can 7922 * detect that condition here, which happens early in CPU bringup, 7923 * before any KVM threads can be running. Unfortunately, we can't 7924 * bring the TSCs fully up to date with real time, as we aren't yet far 7925 * enough into CPU bringup that we know how much real time has actually 7926 * elapsed; our helper function, ktime_get_boot_ns() will be using boot 7927 * variables that haven't been updated yet. 7928 * 7929 * So we simply find the maximum observed TSC above, then record the 7930 * adjustment to TSC in each VCPU. When the VCPU later gets loaded, 7931 * the adjustment will be applied. Note that we accumulate 7932 * adjustments, in case multiple suspend cycles happen before some VCPU 7933 * gets a chance to run again. In the event that no KVM threads get a 7934 * chance to run, we will miss the entire elapsed period, as we'll have 7935 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may 7936 * loose cycle time. This isn't too big a deal, since the loss will be 7937 * uniform across all VCPUs (not to mention the scenario is extremely 7938 * unlikely). It is possible that a second hibernate recovery happens 7939 * much faster than a first, causing the observed TSC here to be 7940 * smaller; this would require additional padding adjustment, which is 7941 * why we set last_host_tsc to the local tsc observed here. 7942 * 7943 * N.B. - this code below runs only on platforms with reliable TSC, 7944 * as that is the only way backwards_tsc is set above. Also note 7945 * that this runs for ALL vcpus, which is not a bug; all VCPUs should 7946 * have the same delta_cyc adjustment applied if backwards_tsc 7947 * is detected. Note further, this adjustment is only done once, 7948 * as we reset last_host_tsc on all VCPUs to stop this from being 7949 * called multiple times (one for each physical CPU bringup). 7950 * 7951 * Platforms with unreliable TSCs don't have to deal with this, they 7952 * will be compensated by the logic in vcpu_load, which sets the TSC to 7953 * catchup mode. This will catchup all VCPUs to real time, but cannot 7954 * guarantee that they stay in perfect synchronization. 7955 */ 7956 if (backwards_tsc) { 7957 u64 delta_cyc = max_tsc - local_tsc; 7958 list_for_each_entry(kvm, &vm_list, vm_list) { 7959 kvm->arch.backwards_tsc_observed = true; 7960 kvm_for_each_vcpu(i, vcpu, kvm) { 7961 vcpu->arch.tsc_offset_adjustment += delta_cyc; 7962 vcpu->arch.last_host_tsc = local_tsc; 7963 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu); 7964 } 7965 7966 /* 7967 * We have to disable TSC offset matching.. if you were 7968 * booting a VM while issuing an S4 host suspend.... 7969 * you may have some problem. Solving this issue is 7970 * left as an exercise to the reader. 7971 */ 7972 kvm->arch.last_tsc_nsec = 0; 7973 kvm->arch.last_tsc_write = 0; 7974 } 7975 7976 } 7977 return 0; 7978 } 7979 7980 void kvm_arch_hardware_disable(void) 7981 { 7982 kvm_x86_ops->hardware_disable(); 7983 drop_user_return_notifiers(); 7984 } 7985 7986 int kvm_arch_hardware_setup(void) 7987 { 7988 int r; 7989 7990 r = kvm_x86_ops->hardware_setup(); 7991 if (r != 0) 7992 return r; 7993 7994 if (kvm_has_tsc_control) { 7995 /* 7996 * Make sure the user can only configure tsc_khz values that 7997 * fit into a signed integer. 7998 * A min value is not calculated needed because it will always 7999 * be 1 on all machines. 8000 */ 8001 u64 max = min(0x7fffffffULL, 8002 __scale_tsc(kvm_max_tsc_scaling_ratio, tsc_khz)); 8003 kvm_max_guest_tsc_khz = max; 8004 8005 kvm_default_tsc_scaling_ratio = 1ULL << kvm_tsc_scaling_ratio_frac_bits; 8006 } 8007 8008 kvm_init_msr_list(); 8009 return 0; 8010 } 8011 8012 void kvm_arch_hardware_unsetup(void) 8013 { 8014 kvm_x86_ops->hardware_unsetup(); 8015 } 8016 8017 void kvm_arch_check_processor_compat(void *rtn) 8018 { 8019 kvm_x86_ops->check_processor_compatibility(rtn); 8020 } 8021 8022 bool kvm_vcpu_is_reset_bsp(struct kvm_vcpu *vcpu) 8023 { 8024 return vcpu->kvm->arch.bsp_vcpu_id == vcpu->vcpu_id; 8025 } 8026 EXPORT_SYMBOL_GPL(kvm_vcpu_is_reset_bsp); 8027 8028 bool kvm_vcpu_is_bsp(struct kvm_vcpu *vcpu) 8029 { 8030 return (vcpu->arch.apic_base & MSR_IA32_APICBASE_BSP) != 0; 8031 } 8032 8033 struct static_key kvm_no_apic_vcpu __read_mostly; 8034 EXPORT_SYMBOL_GPL(kvm_no_apic_vcpu); 8035 8036 int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu) 8037 { 8038 struct page *page; 8039 int r; 8040 8041 vcpu->arch.apicv_active = kvm_x86_ops->get_enable_apicv(vcpu); 8042 vcpu->arch.emulate_ctxt.ops = &emulate_ops; 8043 if (!irqchip_in_kernel(vcpu->kvm) || kvm_vcpu_is_reset_bsp(vcpu)) 8044 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; 8045 else 8046 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED; 8047 8048 page = alloc_page(GFP_KERNEL | __GFP_ZERO); 8049 if (!page) { 8050 r = -ENOMEM; 8051 goto fail; 8052 } 8053 vcpu->arch.pio_data = page_address(page); 8054 8055 kvm_set_tsc_khz(vcpu, max_tsc_khz); 8056 8057 r = kvm_mmu_create(vcpu); 8058 if (r < 0) 8059 goto fail_free_pio_data; 8060 8061 if (irqchip_in_kernel(vcpu->kvm)) { 8062 r = kvm_create_lapic(vcpu); 8063 if (r < 0) 8064 goto fail_mmu_destroy; 8065 } else 8066 static_key_slow_inc(&kvm_no_apic_vcpu); 8067 8068 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4, 8069 GFP_KERNEL); 8070 if (!vcpu->arch.mce_banks) { 8071 r = -ENOMEM; 8072 goto fail_free_lapic; 8073 } 8074 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS; 8075 8076 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL)) { 8077 r = -ENOMEM; 8078 goto fail_free_mce_banks; 8079 } 8080 8081 fx_init(vcpu); 8082 8083 vcpu->arch.guest_xstate_size = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET; 8084 8085 vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu); 8086 8087 vcpu->arch.pat = MSR_IA32_CR_PAT_DEFAULT; 8088 8089 kvm_async_pf_hash_reset(vcpu); 8090 kvm_pmu_init(vcpu); 8091 8092 vcpu->arch.pending_external_vector = -1; 8093 vcpu->arch.preempted_in_kernel = false; 8094 8095 kvm_hv_vcpu_init(vcpu); 8096 8097 return 0; 8098 8099 fail_free_mce_banks: 8100 kfree(vcpu->arch.mce_banks); 8101 fail_free_lapic: 8102 kvm_free_lapic(vcpu); 8103 fail_mmu_destroy: 8104 kvm_mmu_destroy(vcpu); 8105 fail_free_pio_data: 8106 free_page((unsigned long)vcpu->arch.pio_data); 8107 fail: 8108 return r; 8109 } 8110 8111 void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu) 8112 { 8113 int idx; 8114 8115 kvm_hv_vcpu_uninit(vcpu); 8116 kvm_pmu_destroy(vcpu); 8117 kfree(vcpu->arch.mce_banks); 8118 kvm_free_lapic(vcpu); 8119 idx = srcu_read_lock(&vcpu->kvm->srcu); 8120 kvm_mmu_destroy(vcpu); 8121 srcu_read_unlock(&vcpu->kvm->srcu, idx); 8122 free_page((unsigned long)vcpu->arch.pio_data); 8123 if (!lapic_in_kernel(vcpu)) 8124 static_key_slow_dec(&kvm_no_apic_vcpu); 8125 } 8126 8127 void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu) 8128 { 8129 kvm_x86_ops->sched_in(vcpu, cpu); 8130 } 8131 8132 int kvm_arch_init_vm(struct kvm *kvm, unsigned long type) 8133 { 8134 if (type) 8135 return -EINVAL; 8136 8137 INIT_HLIST_HEAD(&kvm->arch.mask_notifier_list); 8138 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages); 8139 INIT_LIST_HEAD(&kvm->arch.zapped_obsolete_pages); 8140 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head); 8141 atomic_set(&kvm->arch.noncoherent_dma_count, 0); 8142 8143 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */ 8144 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap); 8145 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */ 8146 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID, 8147 &kvm->arch.irq_sources_bitmap); 8148 8149 raw_spin_lock_init(&kvm->arch.tsc_write_lock); 8150 mutex_init(&kvm->arch.apic_map_lock); 8151 mutex_init(&kvm->arch.hyperv.hv_lock); 8152 spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock); 8153 8154 kvm->arch.kvmclock_offset = -ktime_get_boot_ns(); 8155 pvclock_update_vm_gtod_copy(kvm); 8156 8157 INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn); 8158 INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn); 8159 8160 kvm_page_track_init(kvm); 8161 kvm_mmu_init_vm(kvm); 8162 8163 if (kvm_x86_ops->vm_init) 8164 return kvm_x86_ops->vm_init(kvm); 8165 8166 return 0; 8167 } 8168 8169 static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu) 8170 { 8171 int r; 8172 r = vcpu_load(vcpu); 8173 BUG_ON(r); 8174 kvm_mmu_unload(vcpu); 8175 vcpu_put(vcpu); 8176 } 8177 8178 static void kvm_free_vcpus(struct kvm *kvm) 8179 { 8180 unsigned int i; 8181 struct kvm_vcpu *vcpu; 8182 8183 /* 8184 * Unpin any mmu pages first. 8185 */ 8186 kvm_for_each_vcpu(i, vcpu, kvm) { 8187 kvm_clear_async_pf_completion_queue(vcpu); 8188 kvm_unload_vcpu_mmu(vcpu); 8189 } 8190 kvm_for_each_vcpu(i, vcpu, kvm) 8191 kvm_arch_vcpu_free(vcpu); 8192 8193 mutex_lock(&kvm->lock); 8194 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++) 8195 kvm->vcpus[i] = NULL; 8196 8197 atomic_set(&kvm->online_vcpus, 0); 8198 mutex_unlock(&kvm->lock); 8199 } 8200 8201 void kvm_arch_sync_events(struct kvm *kvm) 8202 { 8203 cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work); 8204 cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work); 8205 kvm_free_pit(kvm); 8206 } 8207 8208 int __x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size) 8209 { 8210 int i, r; 8211 unsigned long hva; 8212 struct kvm_memslots *slots = kvm_memslots(kvm); 8213 struct kvm_memory_slot *slot, old; 8214 8215 /* Called with kvm->slots_lock held. */ 8216 if (WARN_ON(id >= KVM_MEM_SLOTS_NUM)) 8217 return -EINVAL; 8218 8219 slot = id_to_memslot(slots, id); 8220 if (size) { 8221 if (slot->npages) 8222 return -EEXIST; 8223 8224 /* 8225 * MAP_SHARED to prevent internal slot pages from being moved 8226 * by fork()/COW. 8227 */ 8228 hva = vm_mmap(NULL, 0, size, PROT_READ | PROT_WRITE, 8229 MAP_SHARED | MAP_ANONYMOUS, 0); 8230 if (IS_ERR((void *)hva)) 8231 return PTR_ERR((void *)hva); 8232 } else { 8233 if (!slot->npages) 8234 return 0; 8235 8236 hva = 0; 8237 } 8238 8239 old = *slot; 8240 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) { 8241 struct kvm_userspace_memory_region m; 8242 8243 m.slot = id | (i << 16); 8244 m.flags = 0; 8245 m.guest_phys_addr = gpa; 8246 m.userspace_addr = hva; 8247 m.memory_size = size; 8248 r = __kvm_set_memory_region(kvm, &m); 8249 if (r < 0) 8250 return r; 8251 } 8252 8253 if (!size) { 8254 r = vm_munmap(old.userspace_addr, old.npages * PAGE_SIZE); 8255 WARN_ON(r < 0); 8256 } 8257 8258 return 0; 8259 } 8260 EXPORT_SYMBOL_GPL(__x86_set_memory_region); 8261 8262 int x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size) 8263 { 8264 int r; 8265 8266 mutex_lock(&kvm->slots_lock); 8267 r = __x86_set_memory_region(kvm, id, gpa, size); 8268 mutex_unlock(&kvm->slots_lock); 8269 8270 return r; 8271 } 8272 EXPORT_SYMBOL_GPL(x86_set_memory_region); 8273 8274 void kvm_arch_destroy_vm(struct kvm *kvm) 8275 { 8276 if (current->mm == kvm->mm) { 8277 /* 8278 * Free memory regions allocated on behalf of userspace, 8279 * unless the the memory map has changed due to process exit 8280 * or fd copying. 8281 */ 8282 x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT, 0, 0); 8283 x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT, 0, 0); 8284 x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, 0, 0); 8285 } 8286 if (kvm_x86_ops->vm_destroy) 8287 kvm_x86_ops->vm_destroy(kvm); 8288 kvm_pic_destroy(kvm); 8289 kvm_ioapic_destroy(kvm); 8290 kvm_free_vcpus(kvm); 8291 kvfree(rcu_dereference_check(kvm->arch.apic_map, 1)); 8292 kvm_mmu_uninit_vm(kvm); 8293 kvm_page_track_cleanup(kvm); 8294 } 8295 8296 void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *free, 8297 struct kvm_memory_slot *dont) 8298 { 8299 int i; 8300 8301 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) { 8302 if (!dont || free->arch.rmap[i] != dont->arch.rmap[i]) { 8303 kvfree(free->arch.rmap[i]); 8304 free->arch.rmap[i] = NULL; 8305 } 8306 if (i == 0) 8307 continue; 8308 8309 if (!dont || free->arch.lpage_info[i - 1] != 8310 dont->arch.lpage_info[i - 1]) { 8311 kvfree(free->arch.lpage_info[i - 1]); 8312 free->arch.lpage_info[i - 1] = NULL; 8313 } 8314 } 8315 8316 kvm_page_track_free_memslot(free, dont); 8317 } 8318 8319 int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot, 8320 unsigned long npages) 8321 { 8322 int i; 8323 8324 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) { 8325 struct kvm_lpage_info *linfo; 8326 unsigned long ugfn; 8327 int lpages; 8328 int level = i + 1; 8329 8330 lpages = gfn_to_index(slot->base_gfn + npages - 1, 8331 slot->base_gfn, level) + 1; 8332 8333 slot->arch.rmap[i] = 8334 kvzalloc(lpages * sizeof(*slot->arch.rmap[i]), GFP_KERNEL); 8335 if (!slot->arch.rmap[i]) 8336 goto out_free; 8337 if (i == 0) 8338 continue; 8339 8340 linfo = kvzalloc(lpages * sizeof(*linfo), GFP_KERNEL); 8341 if (!linfo) 8342 goto out_free; 8343 8344 slot->arch.lpage_info[i - 1] = linfo; 8345 8346 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1)) 8347 linfo[0].disallow_lpage = 1; 8348 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1)) 8349 linfo[lpages - 1].disallow_lpage = 1; 8350 ugfn = slot->userspace_addr >> PAGE_SHIFT; 8351 /* 8352 * If the gfn and userspace address are not aligned wrt each 8353 * other, or if explicitly asked to, disable large page 8354 * support for this slot 8355 */ 8356 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) || 8357 !kvm_largepages_enabled()) { 8358 unsigned long j; 8359 8360 for (j = 0; j < lpages; ++j) 8361 linfo[j].disallow_lpage = 1; 8362 } 8363 } 8364 8365 if (kvm_page_track_create_memslot(slot, npages)) 8366 goto out_free; 8367 8368 return 0; 8369 8370 out_free: 8371 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) { 8372 kvfree(slot->arch.rmap[i]); 8373 slot->arch.rmap[i] = NULL; 8374 if (i == 0) 8375 continue; 8376 8377 kvfree(slot->arch.lpage_info[i - 1]); 8378 slot->arch.lpage_info[i - 1] = NULL; 8379 } 8380 return -ENOMEM; 8381 } 8382 8383 void kvm_arch_memslots_updated(struct kvm *kvm, struct kvm_memslots *slots) 8384 { 8385 /* 8386 * memslots->generation has been incremented. 8387 * mmio generation may have reached its maximum value. 8388 */ 8389 kvm_mmu_invalidate_mmio_sptes(kvm, slots); 8390 } 8391 8392 int kvm_arch_prepare_memory_region(struct kvm *kvm, 8393 struct kvm_memory_slot *memslot, 8394 const struct kvm_userspace_memory_region *mem, 8395 enum kvm_mr_change change) 8396 { 8397 return 0; 8398 } 8399 8400 static void kvm_mmu_slot_apply_flags(struct kvm *kvm, 8401 struct kvm_memory_slot *new) 8402 { 8403 /* Still write protect RO slot */ 8404 if (new->flags & KVM_MEM_READONLY) { 8405 kvm_mmu_slot_remove_write_access(kvm, new); 8406 return; 8407 } 8408 8409 /* 8410 * Call kvm_x86_ops dirty logging hooks when they are valid. 8411 * 8412 * kvm_x86_ops->slot_disable_log_dirty is called when: 8413 * 8414 * - KVM_MR_CREATE with dirty logging is disabled 8415 * - KVM_MR_FLAGS_ONLY with dirty logging is disabled in new flag 8416 * 8417 * The reason is, in case of PML, we need to set D-bit for any slots 8418 * with dirty logging disabled in order to eliminate unnecessary GPA 8419 * logging in PML buffer (and potential PML buffer full VMEXT). This 8420 * guarantees leaving PML enabled during guest's lifetime won't have 8421 * any additonal overhead from PML when guest is running with dirty 8422 * logging disabled for memory slots. 8423 * 8424 * kvm_x86_ops->slot_enable_log_dirty is called when switching new slot 8425 * to dirty logging mode. 8426 * 8427 * If kvm_x86_ops dirty logging hooks are invalid, use write protect. 8428 * 8429 * In case of write protect: 8430 * 8431 * Write protect all pages for dirty logging. 8432 * 8433 * All the sptes including the large sptes which point to this 8434 * slot are set to readonly. We can not create any new large 8435 * spte on this slot until the end of the logging. 8436 * 8437 * See the comments in fast_page_fault(). 8438 */ 8439 if (new->flags & KVM_MEM_LOG_DIRTY_PAGES) { 8440 if (kvm_x86_ops->slot_enable_log_dirty) 8441 kvm_x86_ops->slot_enable_log_dirty(kvm, new); 8442 else 8443 kvm_mmu_slot_remove_write_access(kvm, new); 8444 } else { 8445 if (kvm_x86_ops->slot_disable_log_dirty) 8446 kvm_x86_ops->slot_disable_log_dirty(kvm, new); 8447 } 8448 } 8449 8450 void kvm_arch_commit_memory_region(struct kvm *kvm, 8451 const struct kvm_userspace_memory_region *mem, 8452 const struct kvm_memory_slot *old, 8453 const struct kvm_memory_slot *new, 8454 enum kvm_mr_change change) 8455 { 8456 int nr_mmu_pages = 0; 8457 8458 if (!kvm->arch.n_requested_mmu_pages) 8459 nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm); 8460 8461 if (nr_mmu_pages) 8462 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages); 8463 8464 /* 8465 * Dirty logging tracks sptes in 4k granularity, meaning that large 8466 * sptes have to be split. If live migration is successful, the guest 8467 * in the source machine will be destroyed and large sptes will be 8468 * created in the destination. However, if the guest continues to run 8469 * in the source machine (for example if live migration fails), small 8470 * sptes will remain around and cause bad performance. 8471 * 8472 * Scan sptes if dirty logging has been stopped, dropping those 8473 * which can be collapsed into a single large-page spte. Later 8474 * page faults will create the large-page sptes. 8475 */ 8476 if ((change != KVM_MR_DELETE) && 8477 (old->flags & KVM_MEM_LOG_DIRTY_PAGES) && 8478 !(new->flags & KVM_MEM_LOG_DIRTY_PAGES)) 8479 kvm_mmu_zap_collapsible_sptes(kvm, new); 8480 8481 /* 8482 * Set up write protection and/or dirty logging for the new slot. 8483 * 8484 * For KVM_MR_DELETE and KVM_MR_MOVE, the shadow pages of old slot have 8485 * been zapped so no dirty logging staff is needed for old slot. For 8486 * KVM_MR_FLAGS_ONLY, the old slot is essentially the same one as the 8487 * new and it's also covered when dealing with the new slot. 8488 * 8489 * FIXME: const-ify all uses of struct kvm_memory_slot. 8490 */ 8491 if (change != KVM_MR_DELETE) 8492 kvm_mmu_slot_apply_flags(kvm, (struct kvm_memory_slot *) new); 8493 } 8494 8495 void kvm_arch_flush_shadow_all(struct kvm *kvm) 8496 { 8497 kvm_mmu_invalidate_zap_all_pages(kvm); 8498 } 8499 8500 void kvm_arch_flush_shadow_memslot(struct kvm *kvm, 8501 struct kvm_memory_slot *slot) 8502 { 8503 kvm_page_track_flush_slot(kvm, slot); 8504 } 8505 8506 static inline bool kvm_vcpu_has_events(struct kvm_vcpu *vcpu) 8507 { 8508 if (!list_empty_careful(&vcpu->async_pf.done)) 8509 return true; 8510 8511 if (kvm_apic_has_events(vcpu)) 8512 return true; 8513 8514 if (vcpu->arch.pv.pv_unhalted) 8515 return true; 8516 8517 if (vcpu->arch.exception.pending) 8518 return true; 8519 8520 if (kvm_test_request(KVM_REQ_NMI, vcpu) || 8521 (vcpu->arch.nmi_pending && 8522 kvm_x86_ops->nmi_allowed(vcpu))) 8523 return true; 8524 8525 if (kvm_test_request(KVM_REQ_SMI, vcpu) || 8526 (vcpu->arch.smi_pending && !is_smm(vcpu))) 8527 return true; 8528 8529 if (kvm_arch_interrupt_allowed(vcpu) && 8530 kvm_cpu_has_interrupt(vcpu)) 8531 return true; 8532 8533 if (kvm_hv_has_stimer_pending(vcpu)) 8534 return true; 8535 8536 return false; 8537 } 8538 8539 int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu) 8540 { 8541 return kvm_vcpu_running(vcpu) || kvm_vcpu_has_events(vcpu); 8542 } 8543 8544 bool kvm_arch_vcpu_in_kernel(struct kvm_vcpu *vcpu) 8545 { 8546 return vcpu->arch.preempted_in_kernel; 8547 } 8548 8549 int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu) 8550 { 8551 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE; 8552 } 8553 8554 int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu) 8555 { 8556 return kvm_x86_ops->interrupt_allowed(vcpu); 8557 } 8558 8559 unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu) 8560 { 8561 if (is_64_bit_mode(vcpu)) 8562 return kvm_rip_read(vcpu); 8563 return (u32)(get_segment_base(vcpu, VCPU_SREG_CS) + 8564 kvm_rip_read(vcpu)); 8565 } 8566 EXPORT_SYMBOL_GPL(kvm_get_linear_rip); 8567 8568 bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip) 8569 { 8570 return kvm_get_linear_rip(vcpu) == linear_rip; 8571 } 8572 EXPORT_SYMBOL_GPL(kvm_is_linear_rip); 8573 8574 unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu) 8575 { 8576 unsigned long rflags; 8577 8578 rflags = kvm_x86_ops->get_rflags(vcpu); 8579 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) 8580 rflags &= ~X86_EFLAGS_TF; 8581 return rflags; 8582 } 8583 EXPORT_SYMBOL_GPL(kvm_get_rflags); 8584 8585 static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags) 8586 { 8587 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP && 8588 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip)) 8589 rflags |= X86_EFLAGS_TF; 8590 kvm_x86_ops->set_rflags(vcpu, rflags); 8591 } 8592 8593 void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags) 8594 { 8595 __kvm_set_rflags(vcpu, rflags); 8596 kvm_make_request(KVM_REQ_EVENT, vcpu); 8597 } 8598 EXPORT_SYMBOL_GPL(kvm_set_rflags); 8599 8600 void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work) 8601 { 8602 int r; 8603 8604 if ((vcpu->arch.mmu.direct_map != work->arch.direct_map) || 8605 work->wakeup_all) 8606 return; 8607 8608 r = kvm_mmu_reload(vcpu); 8609 if (unlikely(r)) 8610 return; 8611 8612 if (!vcpu->arch.mmu.direct_map && 8613 work->arch.cr3 != vcpu->arch.mmu.get_cr3(vcpu)) 8614 return; 8615 8616 vcpu->arch.mmu.page_fault(vcpu, work->gva, 0, true); 8617 } 8618 8619 static inline u32 kvm_async_pf_hash_fn(gfn_t gfn) 8620 { 8621 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU)); 8622 } 8623 8624 static inline u32 kvm_async_pf_next_probe(u32 key) 8625 { 8626 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1); 8627 } 8628 8629 static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn) 8630 { 8631 u32 key = kvm_async_pf_hash_fn(gfn); 8632 8633 while (vcpu->arch.apf.gfns[key] != ~0) 8634 key = kvm_async_pf_next_probe(key); 8635 8636 vcpu->arch.apf.gfns[key] = gfn; 8637 } 8638 8639 static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn) 8640 { 8641 int i; 8642 u32 key = kvm_async_pf_hash_fn(gfn); 8643 8644 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) && 8645 (vcpu->arch.apf.gfns[key] != gfn && 8646 vcpu->arch.apf.gfns[key] != ~0); i++) 8647 key = kvm_async_pf_next_probe(key); 8648 8649 return key; 8650 } 8651 8652 bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn) 8653 { 8654 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn; 8655 } 8656 8657 static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn) 8658 { 8659 u32 i, j, k; 8660 8661 i = j = kvm_async_pf_gfn_slot(vcpu, gfn); 8662 while (true) { 8663 vcpu->arch.apf.gfns[i] = ~0; 8664 do { 8665 j = kvm_async_pf_next_probe(j); 8666 if (vcpu->arch.apf.gfns[j] == ~0) 8667 return; 8668 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]); 8669 /* 8670 * k lies cyclically in ]i,j] 8671 * | i.k.j | 8672 * |....j i.k.| or |.k..j i...| 8673 */ 8674 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j)); 8675 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j]; 8676 i = j; 8677 } 8678 } 8679 8680 static int apf_put_user(struct kvm_vcpu *vcpu, u32 val) 8681 { 8682 8683 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val, 8684 sizeof(val)); 8685 } 8686 8687 static int apf_get_user(struct kvm_vcpu *vcpu, u32 *val) 8688 { 8689 8690 return kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, val, 8691 sizeof(u32)); 8692 } 8693 8694 void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu, 8695 struct kvm_async_pf *work) 8696 { 8697 struct x86_exception fault; 8698 8699 trace_kvm_async_pf_not_present(work->arch.token, work->gva); 8700 kvm_add_async_pf_gfn(vcpu, work->arch.gfn); 8701 8702 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) || 8703 (vcpu->arch.apf.send_user_only && 8704 kvm_x86_ops->get_cpl(vcpu) == 0)) 8705 kvm_make_request(KVM_REQ_APF_HALT, vcpu); 8706 else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) { 8707 fault.vector = PF_VECTOR; 8708 fault.error_code_valid = true; 8709 fault.error_code = 0; 8710 fault.nested_page_fault = false; 8711 fault.address = work->arch.token; 8712 fault.async_page_fault = true; 8713 kvm_inject_page_fault(vcpu, &fault); 8714 } 8715 } 8716 8717 void kvm_arch_async_page_present(struct kvm_vcpu *vcpu, 8718 struct kvm_async_pf *work) 8719 { 8720 struct x86_exception fault; 8721 u32 val; 8722 8723 if (work->wakeup_all) 8724 work->arch.token = ~0; /* broadcast wakeup */ 8725 else 8726 kvm_del_async_pf_gfn(vcpu, work->arch.gfn); 8727 trace_kvm_async_pf_ready(work->arch.token, work->gva); 8728 8729 if (vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED && 8730 !apf_get_user(vcpu, &val)) { 8731 if (val == KVM_PV_REASON_PAGE_NOT_PRESENT && 8732 vcpu->arch.exception.pending && 8733 vcpu->arch.exception.nr == PF_VECTOR && 8734 !apf_put_user(vcpu, 0)) { 8735 vcpu->arch.exception.injected = false; 8736 vcpu->arch.exception.pending = false; 8737 vcpu->arch.exception.nr = 0; 8738 vcpu->arch.exception.has_error_code = false; 8739 vcpu->arch.exception.error_code = 0; 8740 } else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) { 8741 fault.vector = PF_VECTOR; 8742 fault.error_code_valid = true; 8743 fault.error_code = 0; 8744 fault.nested_page_fault = false; 8745 fault.address = work->arch.token; 8746 fault.async_page_fault = true; 8747 kvm_inject_page_fault(vcpu, &fault); 8748 } 8749 } 8750 vcpu->arch.apf.halted = false; 8751 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; 8752 } 8753 8754 bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu) 8755 { 8756 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED)) 8757 return true; 8758 else 8759 return kvm_can_do_async_pf(vcpu); 8760 } 8761 8762 void kvm_arch_start_assignment(struct kvm *kvm) 8763 { 8764 atomic_inc(&kvm->arch.assigned_device_count); 8765 } 8766 EXPORT_SYMBOL_GPL(kvm_arch_start_assignment); 8767 8768 void kvm_arch_end_assignment(struct kvm *kvm) 8769 { 8770 atomic_dec(&kvm->arch.assigned_device_count); 8771 } 8772 EXPORT_SYMBOL_GPL(kvm_arch_end_assignment); 8773 8774 bool kvm_arch_has_assigned_device(struct kvm *kvm) 8775 { 8776 return atomic_read(&kvm->arch.assigned_device_count); 8777 } 8778 EXPORT_SYMBOL_GPL(kvm_arch_has_assigned_device); 8779 8780 void kvm_arch_register_noncoherent_dma(struct kvm *kvm) 8781 { 8782 atomic_inc(&kvm->arch.noncoherent_dma_count); 8783 } 8784 EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma); 8785 8786 void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm) 8787 { 8788 atomic_dec(&kvm->arch.noncoherent_dma_count); 8789 } 8790 EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma); 8791 8792 bool kvm_arch_has_noncoherent_dma(struct kvm *kvm) 8793 { 8794 return atomic_read(&kvm->arch.noncoherent_dma_count); 8795 } 8796 EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma); 8797 8798 bool kvm_arch_has_irq_bypass(void) 8799 { 8800 return kvm_x86_ops->update_pi_irte != NULL; 8801 } 8802 8803 int kvm_arch_irq_bypass_add_producer(struct irq_bypass_consumer *cons, 8804 struct irq_bypass_producer *prod) 8805 { 8806 struct kvm_kernel_irqfd *irqfd = 8807 container_of(cons, struct kvm_kernel_irqfd, consumer); 8808 8809 irqfd->producer = prod; 8810 8811 return kvm_x86_ops->update_pi_irte(irqfd->kvm, 8812 prod->irq, irqfd->gsi, 1); 8813 } 8814 8815 void kvm_arch_irq_bypass_del_producer(struct irq_bypass_consumer *cons, 8816 struct irq_bypass_producer *prod) 8817 { 8818 int ret; 8819 struct kvm_kernel_irqfd *irqfd = 8820 container_of(cons, struct kvm_kernel_irqfd, consumer); 8821 8822 WARN_ON(irqfd->producer != prod); 8823 irqfd->producer = NULL; 8824 8825 /* 8826 * When producer of consumer is unregistered, we change back to 8827 * remapped mode, so we can re-use the current implementation 8828 * when the irq is masked/disabled or the consumer side (KVM 8829 * int this case doesn't want to receive the interrupts. 8830 */ 8831 ret = kvm_x86_ops->update_pi_irte(irqfd->kvm, prod->irq, irqfd->gsi, 0); 8832 if (ret) 8833 printk(KERN_INFO "irq bypass consumer (token %p) unregistration" 8834 " fails: %d\n", irqfd->consumer.token, ret); 8835 } 8836 8837 int kvm_arch_update_irqfd_routing(struct kvm *kvm, unsigned int host_irq, 8838 uint32_t guest_irq, bool set) 8839 { 8840 if (!kvm_x86_ops->update_pi_irte) 8841 return -EINVAL; 8842 8843 return kvm_x86_ops->update_pi_irte(kvm, host_irq, guest_irq, set); 8844 } 8845 8846 bool kvm_vector_hashing_enabled(void) 8847 { 8848 return vector_hashing; 8849 } 8850 EXPORT_SYMBOL_GPL(kvm_vector_hashing_enabled); 8851 8852 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit); 8853 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_fast_mmio); 8854 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq); 8855 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault); 8856 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr); 8857 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr); 8858 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun); 8859 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit); 8860 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject); 8861 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit); 8862 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga); 8863 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit); 8864 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts); 8865 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset); 8866 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_ple_window); 8867 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pml_full); 8868 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pi_irte_update); 8869 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_unaccelerated_access); 8870 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_incomplete_ipi); 8871