1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Kernel-based Virtual Machine driver for Linux 4 * 5 * derived from drivers/kvm/kvm_main.c 6 * 7 * Copyright (C) 2006 Qumranet, Inc. 8 * Copyright (C) 2008 Qumranet, Inc. 9 * Copyright IBM Corporation, 2008 10 * Copyright 2010 Red Hat, Inc. and/or its affiliates. 11 * 12 * Authors: 13 * Avi Kivity <avi@qumranet.com> 14 * Yaniv Kamay <yaniv@qumranet.com> 15 * Amit Shah <amit.shah@qumranet.com> 16 * Ben-Ami Yassour <benami@il.ibm.com> 17 */ 18 19 #include <linux/kvm_host.h> 20 #include "irq.h" 21 #include "ioapic.h" 22 #include "mmu.h" 23 #include "i8254.h" 24 #include "tss.h" 25 #include "kvm_cache_regs.h" 26 #include "kvm_emulate.h" 27 #include "x86.h" 28 #include "cpuid.h" 29 #include "pmu.h" 30 #include "hyperv.h" 31 #include "lapic.h" 32 #include "xen.h" 33 34 #include <linux/clocksource.h> 35 #include <linux/interrupt.h> 36 #include <linux/kvm.h> 37 #include <linux/fs.h> 38 #include <linux/vmalloc.h> 39 #include <linux/export.h> 40 #include <linux/moduleparam.h> 41 #include <linux/mman.h> 42 #include <linux/highmem.h> 43 #include <linux/iommu.h> 44 #include <linux/cpufreq.h> 45 #include <linux/user-return-notifier.h> 46 #include <linux/srcu.h> 47 #include <linux/slab.h> 48 #include <linux/perf_event.h> 49 #include <linux/uaccess.h> 50 #include <linux/hash.h> 51 #include <linux/pci.h> 52 #include <linux/timekeeper_internal.h> 53 #include <linux/pvclock_gtod.h> 54 #include <linux/kvm_irqfd.h> 55 #include <linux/irqbypass.h> 56 #include <linux/sched/stat.h> 57 #include <linux/sched/isolation.h> 58 #include <linux/mem_encrypt.h> 59 #include <linux/entry-kvm.h> 60 #include <linux/suspend.h> 61 62 #include <trace/events/kvm.h> 63 64 #include <asm/debugreg.h> 65 #include <asm/msr.h> 66 #include <asm/desc.h> 67 #include <asm/mce.h> 68 #include <asm/pkru.h> 69 #include <linux/kernel_stat.h> 70 #include <asm/fpu/api.h> 71 #include <asm/fpu/xcr.h> 72 #include <asm/fpu/xstate.h> 73 #include <asm/pvclock.h> 74 #include <asm/div64.h> 75 #include <asm/irq_remapping.h> 76 #include <asm/mshyperv.h> 77 #include <asm/hypervisor.h> 78 #include <asm/tlbflush.h> 79 #include <asm/intel_pt.h> 80 #include <asm/emulate_prefix.h> 81 #include <asm/sgx.h> 82 #include <clocksource/hyperv_timer.h> 83 84 #define CREATE_TRACE_POINTS 85 #include "trace.h" 86 87 #define MAX_IO_MSRS 256 88 #define KVM_MAX_MCE_BANKS 32 89 90 struct kvm_caps kvm_caps __read_mostly = { 91 .supported_mce_cap = MCG_CTL_P | MCG_SER_P, 92 }; 93 EXPORT_SYMBOL_GPL(kvm_caps); 94 95 #define ERR_PTR_USR(e) ((void __user *)ERR_PTR(e)) 96 97 #define emul_to_vcpu(ctxt) \ 98 ((struct kvm_vcpu *)(ctxt)->vcpu) 99 100 /* EFER defaults: 101 * - enable syscall per default because its emulated by KVM 102 * - enable LME and LMA per default on 64 bit KVM 103 */ 104 #ifdef CONFIG_X86_64 105 static 106 u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA)); 107 #else 108 static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE); 109 #endif 110 111 static u64 __read_mostly cr4_reserved_bits = CR4_RESERVED_BITS; 112 113 #define KVM_EXIT_HYPERCALL_VALID_MASK (1 << KVM_HC_MAP_GPA_RANGE) 114 115 #define KVM_CAP_PMU_VALID_MASK KVM_PMU_CAP_DISABLE 116 117 #define KVM_X2APIC_API_VALID_FLAGS (KVM_X2APIC_API_USE_32BIT_IDS | \ 118 KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK) 119 120 static void update_cr8_intercept(struct kvm_vcpu *vcpu); 121 static void process_nmi(struct kvm_vcpu *vcpu); 122 static void process_smi(struct kvm_vcpu *vcpu); 123 static void enter_smm(struct kvm_vcpu *vcpu); 124 static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags); 125 static void store_regs(struct kvm_vcpu *vcpu); 126 static int sync_regs(struct kvm_vcpu *vcpu); 127 static int kvm_vcpu_do_singlestep(struct kvm_vcpu *vcpu); 128 129 static int __set_sregs2(struct kvm_vcpu *vcpu, struct kvm_sregs2 *sregs2); 130 static void __get_sregs2(struct kvm_vcpu *vcpu, struct kvm_sregs2 *sregs2); 131 132 struct kvm_x86_ops kvm_x86_ops __read_mostly; 133 134 #define KVM_X86_OP(func) \ 135 DEFINE_STATIC_CALL_NULL(kvm_x86_##func, \ 136 *(((struct kvm_x86_ops *)0)->func)); 137 #define KVM_X86_OP_OPTIONAL KVM_X86_OP 138 #define KVM_X86_OP_OPTIONAL_RET0 KVM_X86_OP 139 #include <asm/kvm-x86-ops.h> 140 EXPORT_STATIC_CALL_GPL(kvm_x86_get_cs_db_l_bits); 141 EXPORT_STATIC_CALL_GPL(kvm_x86_cache_reg); 142 143 static bool __read_mostly ignore_msrs = 0; 144 module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR); 145 146 bool __read_mostly report_ignored_msrs = true; 147 module_param(report_ignored_msrs, bool, S_IRUGO | S_IWUSR); 148 EXPORT_SYMBOL_GPL(report_ignored_msrs); 149 150 unsigned int min_timer_period_us = 200; 151 module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR); 152 153 static bool __read_mostly kvmclock_periodic_sync = true; 154 module_param(kvmclock_periodic_sync, bool, S_IRUGO); 155 156 /* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */ 157 static u32 __read_mostly tsc_tolerance_ppm = 250; 158 module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR); 159 160 /* 161 * lapic timer advance (tscdeadline mode only) in nanoseconds. '-1' enables 162 * adaptive tuning starting from default advancement of 1000ns. '0' disables 163 * advancement entirely. Any other value is used as-is and disables adaptive 164 * tuning, i.e. allows privileged userspace to set an exact advancement time. 165 */ 166 static int __read_mostly lapic_timer_advance_ns = -1; 167 module_param(lapic_timer_advance_ns, int, S_IRUGO | S_IWUSR); 168 169 static bool __read_mostly vector_hashing = true; 170 module_param(vector_hashing, bool, S_IRUGO); 171 172 bool __read_mostly enable_vmware_backdoor = false; 173 module_param(enable_vmware_backdoor, bool, S_IRUGO); 174 EXPORT_SYMBOL_GPL(enable_vmware_backdoor); 175 176 static bool __read_mostly force_emulation_prefix = false; 177 module_param(force_emulation_prefix, bool, S_IRUGO); 178 179 int __read_mostly pi_inject_timer = -1; 180 module_param(pi_inject_timer, bint, S_IRUGO | S_IWUSR); 181 182 /* Enable/disable PMU virtualization */ 183 bool __read_mostly enable_pmu = true; 184 EXPORT_SYMBOL_GPL(enable_pmu); 185 module_param(enable_pmu, bool, 0444); 186 187 bool __read_mostly eager_page_split = true; 188 module_param(eager_page_split, bool, 0644); 189 190 /* 191 * Restoring the host value for MSRs that are only consumed when running in 192 * usermode, e.g. SYSCALL MSRs and TSC_AUX, can be deferred until the CPU 193 * returns to userspace, i.e. the kernel can run with the guest's value. 194 */ 195 #define KVM_MAX_NR_USER_RETURN_MSRS 16 196 197 struct kvm_user_return_msrs { 198 struct user_return_notifier urn; 199 bool registered; 200 struct kvm_user_return_msr_values { 201 u64 host; 202 u64 curr; 203 } values[KVM_MAX_NR_USER_RETURN_MSRS]; 204 }; 205 206 u32 __read_mostly kvm_nr_uret_msrs; 207 EXPORT_SYMBOL_GPL(kvm_nr_uret_msrs); 208 static u32 __read_mostly kvm_uret_msrs_list[KVM_MAX_NR_USER_RETURN_MSRS]; 209 static struct kvm_user_return_msrs __percpu *user_return_msrs; 210 211 #define KVM_SUPPORTED_XCR0 (XFEATURE_MASK_FP | XFEATURE_MASK_SSE \ 212 | XFEATURE_MASK_YMM | XFEATURE_MASK_BNDREGS \ 213 | XFEATURE_MASK_BNDCSR | XFEATURE_MASK_AVX512 \ 214 | XFEATURE_MASK_PKRU | XFEATURE_MASK_XTILE) 215 216 u64 __read_mostly host_efer; 217 EXPORT_SYMBOL_GPL(host_efer); 218 219 bool __read_mostly allow_smaller_maxphyaddr = 0; 220 EXPORT_SYMBOL_GPL(allow_smaller_maxphyaddr); 221 222 bool __read_mostly enable_apicv = true; 223 EXPORT_SYMBOL_GPL(enable_apicv); 224 225 u64 __read_mostly host_xss; 226 EXPORT_SYMBOL_GPL(host_xss); 227 228 const struct _kvm_stats_desc kvm_vm_stats_desc[] = { 229 KVM_GENERIC_VM_STATS(), 230 STATS_DESC_COUNTER(VM, mmu_shadow_zapped), 231 STATS_DESC_COUNTER(VM, mmu_pte_write), 232 STATS_DESC_COUNTER(VM, mmu_pde_zapped), 233 STATS_DESC_COUNTER(VM, mmu_flooded), 234 STATS_DESC_COUNTER(VM, mmu_recycled), 235 STATS_DESC_COUNTER(VM, mmu_cache_miss), 236 STATS_DESC_ICOUNTER(VM, mmu_unsync), 237 STATS_DESC_ICOUNTER(VM, pages_4k), 238 STATS_DESC_ICOUNTER(VM, pages_2m), 239 STATS_DESC_ICOUNTER(VM, pages_1g), 240 STATS_DESC_ICOUNTER(VM, nx_lpage_splits), 241 STATS_DESC_PCOUNTER(VM, max_mmu_rmap_size), 242 STATS_DESC_PCOUNTER(VM, max_mmu_page_hash_collisions) 243 }; 244 245 const struct kvm_stats_header kvm_vm_stats_header = { 246 .name_size = KVM_STATS_NAME_SIZE, 247 .num_desc = ARRAY_SIZE(kvm_vm_stats_desc), 248 .id_offset = sizeof(struct kvm_stats_header), 249 .desc_offset = sizeof(struct kvm_stats_header) + KVM_STATS_NAME_SIZE, 250 .data_offset = sizeof(struct kvm_stats_header) + KVM_STATS_NAME_SIZE + 251 sizeof(kvm_vm_stats_desc), 252 }; 253 254 const struct _kvm_stats_desc kvm_vcpu_stats_desc[] = { 255 KVM_GENERIC_VCPU_STATS(), 256 STATS_DESC_COUNTER(VCPU, pf_taken), 257 STATS_DESC_COUNTER(VCPU, pf_fixed), 258 STATS_DESC_COUNTER(VCPU, pf_emulate), 259 STATS_DESC_COUNTER(VCPU, pf_spurious), 260 STATS_DESC_COUNTER(VCPU, pf_fast), 261 STATS_DESC_COUNTER(VCPU, pf_mmio_spte_created), 262 STATS_DESC_COUNTER(VCPU, pf_guest), 263 STATS_DESC_COUNTER(VCPU, tlb_flush), 264 STATS_DESC_COUNTER(VCPU, invlpg), 265 STATS_DESC_COUNTER(VCPU, exits), 266 STATS_DESC_COUNTER(VCPU, io_exits), 267 STATS_DESC_COUNTER(VCPU, mmio_exits), 268 STATS_DESC_COUNTER(VCPU, signal_exits), 269 STATS_DESC_COUNTER(VCPU, irq_window_exits), 270 STATS_DESC_COUNTER(VCPU, nmi_window_exits), 271 STATS_DESC_COUNTER(VCPU, l1d_flush), 272 STATS_DESC_COUNTER(VCPU, halt_exits), 273 STATS_DESC_COUNTER(VCPU, request_irq_exits), 274 STATS_DESC_COUNTER(VCPU, irq_exits), 275 STATS_DESC_COUNTER(VCPU, host_state_reload), 276 STATS_DESC_COUNTER(VCPU, fpu_reload), 277 STATS_DESC_COUNTER(VCPU, insn_emulation), 278 STATS_DESC_COUNTER(VCPU, insn_emulation_fail), 279 STATS_DESC_COUNTER(VCPU, hypercalls), 280 STATS_DESC_COUNTER(VCPU, irq_injections), 281 STATS_DESC_COUNTER(VCPU, nmi_injections), 282 STATS_DESC_COUNTER(VCPU, req_event), 283 STATS_DESC_COUNTER(VCPU, nested_run), 284 STATS_DESC_COUNTER(VCPU, directed_yield_attempted), 285 STATS_DESC_COUNTER(VCPU, directed_yield_successful), 286 STATS_DESC_COUNTER(VCPU, preemption_reported), 287 STATS_DESC_COUNTER(VCPU, preemption_other), 288 STATS_DESC_IBOOLEAN(VCPU, guest_mode), 289 STATS_DESC_COUNTER(VCPU, notify_window_exits), 290 }; 291 292 const struct kvm_stats_header kvm_vcpu_stats_header = { 293 .name_size = KVM_STATS_NAME_SIZE, 294 .num_desc = ARRAY_SIZE(kvm_vcpu_stats_desc), 295 .id_offset = sizeof(struct kvm_stats_header), 296 .desc_offset = sizeof(struct kvm_stats_header) + KVM_STATS_NAME_SIZE, 297 .data_offset = sizeof(struct kvm_stats_header) + KVM_STATS_NAME_SIZE + 298 sizeof(kvm_vcpu_stats_desc), 299 }; 300 301 u64 __read_mostly host_xcr0; 302 303 static struct kmem_cache *x86_emulator_cache; 304 305 /* 306 * When called, it means the previous get/set msr reached an invalid msr. 307 * Return true if we want to ignore/silent this failed msr access. 308 */ 309 static bool kvm_msr_ignored_check(u32 msr, u64 data, bool write) 310 { 311 const char *op = write ? "wrmsr" : "rdmsr"; 312 313 if (ignore_msrs) { 314 if (report_ignored_msrs) 315 kvm_pr_unimpl("ignored %s: 0x%x data 0x%llx\n", 316 op, msr, data); 317 /* Mask the error */ 318 return true; 319 } else { 320 kvm_debug_ratelimited("unhandled %s: 0x%x data 0x%llx\n", 321 op, msr, data); 322 return false; 323 } 324 } 325 326 static struct kmem_cache *kvm_alloc_emulator_cache(void) 327 { 328 unsigned int useroffset = offsetof(struct x86_emulate_ctxt, src); 329 unsigned int size = sizeof(struct x86_emulate_ctxt); 330 331 return kmem_cache_create_usercopy("x86_emulator", size, 332 __alignof__(struct x86_emulate_ctxt), 333 SLAB_ACCOUNT, useroffset, 334 size - useroffset, NULL); 335 } 336 337 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt); 338 339 static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu) 340 { 341 int i; 342 for (i = 0; i < ASYNC_PF_PER_VCPU; i++) 343 vcpu->arch.apf.gfns[i] = ~0; 344 } 345 346 static void kvm_on_user_return(struct user_return_notifier *urn) 347 { 348 unsigned slot; 349 struct kvm_user_return_msrs *msrs 350 = container_of(urn, struct kvm_user_return_msrs, urn); 351 struct kvm_user_return_msr_values *values; 352 unsigned long flags; 353 354 /* 355 * Disabling irqs at this point since the following code could be 356 * interrupted and executed through kvm_arch_hardware_disable() 357 */ 358 local_irq_save(flags); 359 if (msrs->registered) { 360 msrs->registered = false; 361 user_return_notifier_unregister(urn); 362 } 363 local_irq_restore(flags); 364 for (slot = 0; slot < kvm_nr_uret_msrs; ++slot) { 365 values = &msrs->values[slot]; 366 if (values->host != values->curr) { 367 wrmsrl(kvm_uret_msrs_list[slot], values->host); 368 values->curr = values->host; 369 } 370 } 371 } 372 373 static int kvm_probe_user_return_msr(u32 msr) 374 { 375 u64 val; 376 int ret; 377 378 preempt_disable(); 379 ret = rdmsrl_safe(msr, &val); 380 if (ret) 381 goto out; 382 ret = wrmsrl_safe(msr, val); 383 out: 384 preempt_enable(); 385 return ret; 386 } 387 388 int kvm_add_user_return_msr(u32 msr) 389 { 390 BUG_ON(kvm_nr_uret_msrs >= KVM_MAX_NR_USER_RETURN_MSRS); 391 392 if (kvm_probe_user_return_msr(msr)) 393 return -1; 394 395 kvm_uret_msrs_list[kvm_nr_uret_msrs] = msr; 396 return kvm_nr_uret_msrs++; 397 } 398 EXPORT_SYMBOL_GPL(kvm_add_user_return_msr); 399 400 int kvm_find_user_return_msr(u32 msr) 401 { 402 int i; 403 404 for (i = 0; i < kvm_nr_uret_msrs; ++i) { 405 if (kvm_uret_msrs_list[i] == msr) 406 return i; 407 } 408 return -1; 409 } 410 EXPORT_SYMBOL_GPL(kvm_find_user_return_msr); 411 412 static void kvm_user_return_msr_cpu_online(void) 413 { 414 unsigned int cpu = smp_processor_id(); 415 struct kvm_user_return_msrs *msrs = per_cpu_ptr(user_return_msrs, cpu); 416 u64 value; 417 int i; 418 419 for (i = 0; i < kvm_nr_uret_msrs; ++i) { 420 rdmsrl_safe(kvm_uret_msrs_list[i], &value); 421 msrs->values[i].host = value; 422 msrs->values[i].curr = value; 423 } 424 } 425 426 int kvm_set_user_return_msr(unsigned slot, u64 value, u64 mask) 427 { 428 unsigned int cpu = smp_processor_id(); 429 struct kvm_user_return_msrs *msrs = per_cpu_ptr(user_return_msrs, cpu); 430 int err; 431 432 value = (value & mask) | (msrs->values[slot].host & ~mask); 433 if (value == msrs->values[slot].curr) 434 return 0; 435 err = wrmsrl_safe(kvm_uret_msrs_list[slot], value); 436 if (err) 437 return 1; 438 439 msrs->values[slot].curr = value; 440 if (!msrs->registered) { 441 msrs->urn.on_user_return = kvm_on_user_return; 442 user_return_notifier_register(&msrs->urn); 443 msrs->registered = true; 444 } 445 return 0; 446 } 447 EXPORT_SYMBOL_GPL(kvm_set_user_return_msr); 448 449 static void drop_user_return_notifiers(void) 450 { 451 unsigned int cpu = smp_processor_id(); 452 struct kvm_user_return_msrs *msrs = per_cpu_ptr(user_return_msrs, cpu); 453 454 if (msrs->registered) 455 kvm_on_user_return(&msrs->urn); 456 } 457 458 u64 kvm_get_apic_base(struct kvm_vcpu *vcpu) 459 { 460 return vcpu->arch.apic_base; 461 } 462 EXPORT_SYMBOL_GPL(kvm_get_apic_base); 463 464 enum lapic_mode kvm_get_apic_mode(struct kvm_vcpu *vcpu) 465 { 466 return kvm_apic_mode(kvm_get_apic_base(vcpu)); 467 } 468 EXPORT_SYMBOL_GPL(kvm_get_apic_mode); 469 470 int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info) 471 { 472 enum lapic_mode old_mode = kvm_get_apic_mode(vcpu); 473 enum lapic_mode new_mode = kvm_apic_mode(msr_info->data); 474 u64 reserved_bits = kvm_vcpu_reserved_gpa_bits_raw(vcpu) | 0x2ff | 475 (guest_cpuid_has(vcpu, X86_FEATURE_X2APIC) ? 0 : X2APIC_ENABLE); 476 477 if ((msr_info->data & reserved_bits) != 0 || new_mode == LAPIC_MODE_INVALID) 478 return 1; 479 if (!msr_info->host_initiated) { 480 if (old_mode == LAPIC_MODE_X2APIC && new_mode == LAPIC_MODE_XAPIC) 481 return 1; 482 if (old_mode == LAPIC_MODE_DISABLED && new_mode == LAPIC_MODE_X2APIC) 483 return 1; 484 } 485 486 kvm_lapic_set_base(vcpu, msr_info->data); 487 kvm_recalculate_apic_map(vcpu->kvm); 488 return 0; 489 } 490 EXPORT_SYMBOL_GPL(kvm_set_apic_base); 491 492 /* 493 * Handle a fault on a hardware virtualization (VMX or SVM) instruction. 494 * 495 * Hardware virtualization extension instructions may fault if a reboot turns 496 * off virtualization while processes are running. Usually after catching the 497 * fault we just panic; during reboot instead the instruction is ignored. 498 */ 499 noinstr void kvm_spurious_fault(void) 500 { 501 /* Fault while not rebooting. We want the trace. */ 502 BUG_ON(!kvm_rebooting); 503 } 504 EXPORT_SYMBOL_GPL(kvm_spurious_fault); 505 506 #define EXCPT_BENIGN 0 507 #define EXCPT_CONTRIBUTORY 1 508 #define EXCPT_PF 2 509 510 static int exception_class(int vector) 511 { 512 switch (vector) { 513 case PF_VECTOR: 514 return EXCPT_PF; 515 case DE_VECTOR: 516 case TS_VECTOR: 517 case NP_VECTOR: 518 case SS_VECTOR: 519 case GP_VECTOR: 520 return EXCPT_CONTRIBUTORY; 521 default: 522 break; 523 } 524 return EXCPT_BENIGN; 525 } 526 527 #define EXCPT_FAULT 0 528 #define EXCPT_TRAP 1 529 #define EXCPT_ABORT 2 530 #define EXCPT_INTERRUPT 3 531 532 static int exception_type(int vector) 533 { 534 unsigned int mask; 535 536 if (WARN_ON(vector > 31 || vector == NMI_VECTOR)) 537 return EXCPT_INTERRUPT; 538 539 mask = 1 << vector; 540 541 /* #DB is trap, as instruction watchpoints are handled elsewhere */ 542 if (mask & ((1 << DB_VECTOR) | (1 << BP_VECTOR) | (1 << OF_VECTOR))) 543 return EXCPT_TRAP; 544 545 if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR))) 546 return EXCPT_ABORT; 547 548 /* Reserved exceptions will result in fault */ 549 return EXCPT_FAULT; 550 } 551 552 void kvm_deliver_exception_payload(struct kvm_vcpu *vcpu) 553 { 554 unsigned nr = vcpu->arch.exception.nr; 555 bool has_payload = vcpu->arch.exception.has_payload; 556 unsigned long payload = vcpu->arch.exception.payload; 557 558 if (!has_payload) 559 return; 560 561 switch (nr) { 562 case DB_VECTOR: 563 /* 564 * "Certain debug exceptions may clear bit 0-3. The 565 * remaining contents of the DR6 register are never 566 * cleared by the processor". 567 */ 568 vcpu->arch.dr6 &= ~DR_TRAP_BITS; 569 /* 570 * In order to reflect the #DB exception payload in guest 571 * dr6, three components need to be considered: active low 572 * bit, FIXED_1 bits and active high bits (e.g. DR6_BD, 573 * DR6_BS and DR6_BT) 574 * DR6_ACTIVE_LOW contains the FIXED_1 and active low bits. 575 * In the target guest dr6: 576 * FIXED_1 bits should always be set. 577 * Active low bits should be cleared if 1-setting in payload. 578 * Active high bits should be set if 1-setting in payload. 579 * 580 * Note, the payload is compatible with the pending debug 581 * exceptions/exit qualification under VMX, that active_low bits 582 * are active high in payload. 583 * So they need to be flipped for DR6. 584 */ 585 vcpu->arch.dr6 |= DR6_ACTIVE_LOW; 586 vcpu->arch.dr6 |= payload; 587 vcpu->arch.dr6 ^= payload & DR6_ACTIVE_LOW; 588 589 /* 590 * The #DB payload is defined as compatible with the 'pending 591 * debug exceptions' field under VMX, not DR6. While bit 12 is 592 * defined in the 'pending debug exceptions' field (enabled 593 * breakpoint), it is reserved and must be zero in DR6. 594 */ 595 vcpu->arch.dr6 &= ~BIT(12); 596 break; 597 case PF_VECTOR: 598 vcpu->arch.cr2 = payload; 599 break; 600 } 601 602 vcpu->arch.exception.has_payload = false; 603 vcpu->arch.exception.payload = 0; 604 } 605 EXPORT_SYMBOL_GPL(kvm_deliver_exception_payload); 606 607 static void kvm_multiple_exception(struct kvm_vcpu *vcpu, 608 unsigned nr, bool has_error, u32 error_code, 609 bool has_payload, unsigned long payload, bool reinject) 610 { 611 u32 prev_nr; 612 int class1, class2; 613 614 kvm_make_request(KVM_REQ_EVENT, vcpu); 615 616 if (!vcpu->arch.exception.pending && !vcpu->arch.exception.injected) { 617 queue: 618 if (reinject) { 619 /* 620 * On vmentry, vcpu->arch.exception.pending is only 621 * true if an event injection was blocked by 622 * nested_run_pending. In that case, however, 623 * vcpu_enter_guest requests an immediate exit, 624 * and the guest shouldn't proceed far enough to 625 * need reinjection. 626 */ 627 WARN_ON_ONCE(vcpu->arch.exception.pending); 628 vcpu->arch.exception.injected = true; 629 if (WARN_ON_ONCE(has_payload)) { 630 /* 631 * A reinjected event has already 632 * delivered its payload. 633 */ 634 has_payload = false; 635 payload = 0; 636 } 637 } else { 638 vcpu->arch.exception.pending = true; 639 vcpu->arch.exception.injected = false; 640 } 641 vcpu->arch.exception.has_error_code = has_error; 642 vcpu->arch.exception.nr = nr; 643 vcpu->arch.exception.error_code = error_code; 644 vcpu->arch.exception.has_payload = has_payload; 645 vcpu->arch.exception.payload = payload; 646 if (!is_guest_mode(vcpu)) 647 kvm_deliver_exception_payload(vcpu); 648 return; 649 } 650 651 /* to check exception */ 652 prev_nr = vcpu->arch.exception.nr; 653 if (prev_nr == DF_VECTOR) { 654 /* triple fault -> shutdown */ 655 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); 656 return; 657 } 658 class1 = exception_class(prev_nr); 659 class2 = exception_class(nr); 660 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY) 661 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) { 662 /* 663 * Generate double fault per SDM Table 5-5. Set 664 * exception.pending = true so that the double fault 665 * can trigger a nested vmexit. 666 */ 667 vcpu->arch.exception.pending = true; 668 vcpu->arch.exception.injected = false; 669 vcpu->arch.exception.has_error_code = true; 670 vcpu->arch.exception.nr = DF_VECTOR; 671 vcpu->arch.exception.error_code = 0; 672 vcpu->arch.exception.has_payload = false; 673 vcpu->arch.exception.payload = 0; 674 } else 675 /* replace previous exception with a new one in a hope 676 that instruction re-execution will regenerate lost 677 exception */ 678 goto queue; 679 } 680 681 void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr) 682 { 683 kvm_multiple_exception(vcpu, nr, false, 0, false, 0, false); 684 } 685 EXPORT_SYMBOL_GPL(kvm_queue_exception); 686 687 void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr) 688 { 689 kvm_multiple_exception(vcpu, nr, false, 0, false, 0, true); 690 } 691 EXPORT_SYMBOL_GPL(kvm_requeue_exception); 692 693 void kvm_queue_exception_p(struct kvm_vcpu *vcpu, unsigned nr, 694 unsigned long payload) 695 { 696 kvm_multiple_exception(vcpu, nr, false, 0, true, payload, false); 697 } 698 EXPORT_SYMBOL_GPL(kvm_queue_exception_p); 699 700 static void kvm_queue_exception_e_p(struct kvm_vcpu *vcpu, unsigned nr, 701 u32 error_code, unsigned long payload) 702 { 703 kvm_multiple_exception(vcpu, nr, true, error_code, 704 true, payload, false); 705 } 706 707 int kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err) 708 { 709 if (err) 710 kvm_inject_gp(vcpu, 0); 711 else 712 return kvm_skip_emulated_instruction(vcpu); 713 714 return 1; 715 } 716 EXPORT_SYMBOL_GPL(kvm_complete_insn_gp); 717 718 static int complete_emulated_insn_gp(struct kvm_vcpu *vcpu, int err) 719 { 720 if (err) { 721 kvm_inject_gp(vcpu, 0); 722 return 1; 723 } 724 725 return kvm_emulate_instruction(vcpu, EMULTYPE_NO_DECODE | EMULTYPE_SKIP | 726 EMULTYPE_COMPLETE_USER_EXIT); 727 } 728 729 void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault) 730 { 731 ++vcpu->stat.pf_guest; 732 vcpu->arch.exception.nested_apf = 733 is_guest_mode(vcpu) && fault->async_page_fault; 734 if (vcpu->arch.exception.nested_apf) { 735 vcpu->arch.apf.nested_apf_token = fault->address; 736 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code); 737 } else { 738 kvm_queue_exception_e_p(vcpu, PF_VECTOR, fault->error_code, 739 fault->address); 740 } 741 } 742 EXPORT_SYMBOL_GPL(kvm_inject_page_fault); 743 744 /* Returns true if the page fault was immediately morphed into a VM-Exit. */ 745 bool kvm_inject_emulated_page_fault(struct kvm_vcpu *vcpu, 746 struct x86_exception *fault) 747 { 748 struct kvm_mmu *fault_mmu; 749 WARN_ON_ONCE(fault->vector != PF_VECTOR); 750 751 fault_mmu = fault->nested_page_fault ? vcpu->arch.mmu : 752 vcpu->arch.walk_mmu; 753 754 /* 755 * Invalidate the TLB entry for the faulting address, if it exists, 756 * else the access will fault indefinitely (and to emulate hardware). 757 */ 758 if ((fault->error_code & PFERR_PRESENT_MASK) && 759 !(fault->error_code & PFERR_RSVD_MASK)) 760 kvm_mmu_invalidate_gva(vcpu, fault_mmu, fault->address, 761 fault_mmu->root.hpa); 762 763 /* 764 * A workaround for KVM's bad exception handling. If KVM injected an 765 * exception into L2, and L2 encountered a #PF while vectoring the 766 * injected exception, manually check to see if L1 wants to intercept 767 * #PF, otherwise queuing the #PF will lead to #DF or a lost exception. 768 * In all other cases, defer the check to nested_ops->check_events(), 769 * which will correctly handle priority (this does not). Note, other 770 * exceptions, e.g. #GP, are theoretically affected, #PF is simply the 771 * most problematic, e.g. when L0 and L1 are both intercepting #PF for 772 * shadow paging. 773 * 774 * TODO: Rewrite exception handling to track injected and pending 775 * (VM-Exit) exceptions separately. 776 */ 777 if (unlikely(vcpu->arch.exception.injected && is_guest_mode(vcpu)) && 778 kvm_x86_ops.nested_ops->handle_page_fault_workaround(vcpu, fault)) 779 return true; 780 781 fault_mmu->inject_page_fault(vcpu, fault); 782 return false; 783 } 784 EXPORT_SYMBOL_GPL(kvm_inject_emulated_page_fault); 785 786 void kvm_inject_nmi(struct kvm_vcpu *vcpu) 787 { 788 atomic_inc(&vcpu->arch.nmi_queued); 789 kvm_make_request(KVM_REQ_NMI, vcpu); 790 } 791 EXPORT_SYMBOL_GPL(kvm_inject_nmi); 792 793 void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code) 794 { 795 kvm_multiple_exception(vcpu, nr, true, error_code, false, 0, false); 796 } 797 EXPORT_SYMBOL_GPL(kvm_queue_exception_e); 798 799 void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code) 800 { 801 kvm_multiple_exception(vcpu, nr, true, error_code, false, 0, true); 802 } 803 EXPORT_SYMBOL_GPL(kvm_requeue_exception_e); 804 805 /* 806 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue 807 * a #GP and return false. 808 */ 809 bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl) 810 { 811 if (static_call(kvm_x86_get_cpl)(vcpu) <= required_cpl) 812 return true; 813 kvm_queue_exception_e(vcpu, GP_VECTOR, 0); 814 return false; 815 } 816 EXPORT_SYMBOL_GPL(kvm_require_cpl); 817 818 bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr) 819 { 820 if ((dr != 4 && dr != 5) || !kvm_read_cr4_bits(vcpu, X86_CR4_DE)) 821 return true; 822 823 kvm_queue_exception(vcpu, UD_VECTOR); 824 return false; 825 } 826 EXPORT_SYMBOL_GPL(kvm_require_dr); 827 828 static inline u64 pdptr_rsvd_bits(struct kvm_vcpu *vcpu) 829 { 830 return vcpu->arch.reserved_gpa_bits | rsvd_bits(5, 8) | rsvd_bits(1, 2); 831 } 832 833 /* 834 * Load the pae pdptrs. Return 1 if they are all valid, 0 otherwise. 835 */ 836 int load_pdptrs(struct kvm_vcpu *vcpu, unsigned long cr3) 837 { 838 struct kvm_mmu *mmu = vcpu->arch.walk_mmu; 839 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT; 840 gpa_t real_gpa; 841 int i; 842 int ret; 843 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)]; 844 845 /* 846 * If the MMU is nested, CR3 holds an L2 GPA and needs to be translated 847 * to an L1 GPA. 848 */ 849 real_gpa = kvm_translate_gpa(vcpu, mmu, gfn_to_gpa(pdpt_gfn), 850 PFERR_USER_MASK | PFERR_WRITE_MASK, NULL); 851 if (real_gpa == INVALID_GPA) 852 return 0; 853 854 /* Note the offset, PDPTRs are 32 byte aligned when using PAE paging. */ 855 ret = kvm_vcpu_read_guest_page(vcpu, gpa_to_gfn(real_gpa), pdpte, 856 cr3 & GENMASK(11, 5), sizeof(pdpte)); 857 if (ret < 0) 858 return 0; 859 860 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) { 861 if ((pdpte[i] & PT_PRESENT_MASK) && 862 (pdpte[i] & pdptr_rsvd_bits(vcpu))) { 863 return 0; 864 } 865 } 866 867 /* 868 * Marking VCPU_EXREG_PDPTR dirty doesn't work for !tdp_enabled. 869 * Shadow page roots need to be reconstructed instead. 870 */ 871 if (!tdp_enabled && memcmp(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs))) 872 kvm_mmu_free_roots(vcpu->kvm, mmu, KVM_MMU_ROOT_CURRENT); 873 874 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs)); 875 kvm_register_mark_dirty(vcpu, VCPU_EXREG_PDPTR); 876 kvm_make_request(KVM_REQ_LOAD_MMU_PGD, vcpu); 877 vcpu->arch.pdptrs_from_userspace = false; 878 879 return 1; 880 } 881 EXPORT_SYMBOL_GPL(load_pdptrs); 882 883 void kvm_post_set_cr0(struct kvm_vcpu *vcpu, unsigned long old_cr0, unsigned long cr0) 884 { 885 if ((cr0 ^ old_cr0) & X86_CR0_PG) { 886 kvm_clear_async_pf_completion_queue(vcpu); 887 kvm_async_pf_hash_reset(vcpu); 888 889 /* 890 * Clearing CR0.PG is defined to flush the TLB from the guest's 891 * perspective. 892 */ 893 if (!(cr0 & X86_CR0_PG)) 894 kvm_make_request(KVM_REQ_TLB_FLUSH_GUEST, vcpu); 895 } 896 897 if ((cr0 ^ old_cr0) & KVM_MMU_CR0_ROLE_BITS) 898 kvm_mmu_reset_context(vcpu); 899 900 if (((cr0 ^ old_cr0) & X86_CR0_CD) && 901 kvm_arch_has_noncoherent_dma(vcpu->kvm) && 902 !kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED)) 903 kvm_zap_gfn_range(vcpu->kvm, 0, ~0ULL); 904 } 905 EXPORT_SYMBOL_GPL(kvm_post_set_cr0); 906 907 int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0) 908 { 909 unsigned long old_cr0 = kvm_read_cr0(vcpu); 910 911 cr0 |= X86_CR0_ET; 912 913 #ifdef CONFIG_X86_64 914 if (cr0 & 0xffffffff00000000UL) 915 return 1; 916 #endif 917 918 cr0 &= ~CR0_RESERVED_BITS; 919 920 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD)) 921 return 1; 922 923 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE)) 924 return 1; 925 926 #ifdef CONFIG_X86_64 927 if ((vcpu->arch.efer & EFER_LME) && !is_paging(vcpu) && 928 (cr0 & X86_CR0_PG)) { 929 int cs_db, cs_l; 930 931 if (!is_pae(vcpu)) 932 return 1; 933 static_call(kvm_x86_get_cs_db_l_bits)(vcpu, &cs_db, &cs_l); 934 if (cs_l) 935 return 1; 936 } 937 #endif 938 if (!(vcpu->arch.efer & EFER_LME) && (cr0 & X86_CR0_PG) && 939 is_pae(vcpu) && ((cr0 ^ old_cr0) & X86_CR0_PDPTR_BITS) && 940 !load_pdptrs(vcpu, kvm_read_cr3(vcpu))) 941 return 1; 942 943 if (!(cr0 & X86_CR0_PG) && 944 (is_64_bit_mode(vcpu) || kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))) 945 return 1; 946 947 static_call(kvm_x86_set_cr0)(vcpu, cr0); 948 949 kvm_post_set_cr0(vcpu, old_cr0, cr0); 950 951 return 0; 952 } 953 EXPORT_SYMBOL_GPL(kvm_set_cr0); 954 955 void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw) 956 { 957 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f)); 958 } 959 EXPORT_SYMBOL_GPL(kvm_lmsw); 960 961 void kvm_load_guest_xsave_state(struct kvm_vcpu *vcpu) 962 { 963 if (vcpu->arch.guest_state_protected) 964 return; 965 966 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE)) { 967 968 if (vcpu->arch.xcr0 != host_xcr0) 969 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0); 970 971 if (vcpu->arch.xsaves_enabled && 972 vcpu->arch.ia32_xss != host_xss) 973 wrmsrl(MSR_IA32_XSS, vcpu->arch.ia32_xss); 974 } 975 976 #ifdef CONFIG_X86_INTEL_MEMORY_PROTECTION_KEYS 977 if (static_cpu_has(X86_FEATURE_PKU) && 978 vcpu->arch.pkru != vcpu->arch.host_pkru && 979 ((vcpu->arch.xcr0 & XFEATURE_MASK_PKRU) || 980 kvm_read_cr4_bits(vcpu, X86_CR4_PKE))) 981 write_pkru(vcpu->arch.pkru); 982 #endif /* CONFIG_X86_INTEL_MEMORY_PROTECTION_KEYS */ 983 } 984 EXPORT_SYMBOL_GPL(kvm_load_guest_xsave_state); 985 986 void kvm_load_host_xsave_state(struct kvm_vcpu *vcpu) 987 { 988 if (vcpu->arch.guest_state_protected) 989 return; 990 991 #ifdef CONFIG_X86_INTEL_MEMORY_PROTECTION_KEYS 992 if (static_cpu_has(X86_FEATURE_PKU) && 993 ((vcpu->arch.xcr0 & XFEATURE_MASK_PKRU) || 994 kvm_read_cr4_bits(vcpu, X86_CR4_PKE))) { 995 vcpu->arch.pkru = rdpkru(); 996 if (vcpu->arch.pkru != vcpu->arch.host_pkru) 997 write_pkru(vcpu->arch.host_pkru); 998 } 999 #endif /* CONFIG_X86_INTEL_MEMORY_PROTECTION_KEYS */ 1000 1001 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE)) { 1002 1003 if (vcpu->arch.xcr0 != host_xcr0) 1004 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0); 1005 1006 if (vcpu->arch.xsaves_enabled && 1007 vcpu->arch.ia32_xss != host_xss) 1008 wrmsrl(MSR_IA32_XSS, host_xss); 1009 } 1010 1011 } 1012 EXPORT_SYMBOL_GPL(kvm_load_host_xsave_state); 1013 1014 static inline u64 kvm_guest_supported_xcr0(struct kvm_vcpu *vcpu) 1015 { 1016 return vcpu->arch.guest_fpu.fpstate->user_xfeatures; 1017 } 1018 1019 #ifdef CONFIG_X86_64 1020 static inline u64 kvm_guest_supported_xfd(struct kvm_vcpu *vcpu) 1021 { 1022 return kvm_guest_supported_xcr0(vcpu) & XFEATURE_MASK_USER_DYNAMIC; 1023 } 1024 #endif 1025 1026 static int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr) 1027 { 1028 u64 xcr0 = xcr; 1029 u64 old_xcr0 = vcpu->arch.xcr0; 1030 u64 valid_bits; 1031 1032 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */ 1033 if (index != XCR_XFEATURE_ENABLED_MASK) 1034 return 1; 1035 if (!(xcr0 & XFEATURE_MASK_FP)) 1036 return 1; 1037 if ((xcr0 & XFEATURE_MASK_YMM) && !(xcr0 & XFEATURE_MASK_SSE)) 1038 return 1; 1039 1040 /* 1041 * Do not allow the guest to set bits that we do not support 1042 * saving. However, xcr0 bit 0 is always set, even if the 1043 * emulated CPU does not support XSAVE (see kvm_vcpu_reset()). 1044 */ 1045 valid_bits = kvm_guest_supported_xcr0(vcpu) | XFEATURE_MASK_FP; 1046 if (xcr0 & ~valid_bits) 1047 return 1; 1048 1049 if ((!(xcr0 & XFEATURE_MASK_BNDREGS)) != 1050 (!(xcr0 & XFEATURE_MASK_BNDCSR))) 1051 return 1; 1052 1053 if (xcr0 & XFEATURE_MASK_AVX512) { 1054 if (!(xcr0 & XFEATURE_MASK_YMM)) 1055 return 1; 1056 if ((xcr0 & XFEATURE_MASK_AVX512) != XFEATURE_MASK_AVX512) 1057 return 1; 1058 } 1059 1060 if ((xcr0 & XFEATURE_MASK_XTILE) && 1061 ((xcr0 & XFEATURE_MASK_XTILE) != XFEATURE_MASK_XTILE)) 1062 return 1; 1063 1064 vcpu->arch.xcr0 = xcr0; 1065 1066 if ((xcr0 ^ old_xcr0) & XFEATURE_MASK_EXTEND) 1067 kvm_update_cpuid_runtime(vcpu); 1068 return 0; 1069 } 1070 1071 int kvm_emulate_xsetbv(struct kvm_vcpu *vcpu) 1072 { 1073 if (static_call(kvm_x86_get_cpl)(vcpu) != 0 || 1074 __kvm_set_xcr(vcpu, kvm_rcx_read(vcpu), kvm_read_edx_eax(vcpu))) { 1075 kvm_inject_gp(vcpu, 0); 1076 return 1; 1077 } 1078 1079 return kvm_skip_emulated_instruction(vcpu); 1080 } 1081 EXPORT_SYMBOL_GPL(kvm_emulate_xsetbv); 1082 1083 bool __kvm_is_valid_cr4(struct kvm_vcpu *vcpu, unsigned long cr4) 1084 { 1085 if (cr4 & cr4_reserved_bits) 1086 return false; 1087 1088 if (cr4 & vcpu->arch.cr4_guest_rsvd_bits) 1089 return false; 1090 1091 return true; 1092 } 1093 EXPORT_SYMBOL_GPL(__kvm_is_valid_cr4); 1094 1095 static bool kvm_is_valid_cr4(struct kvm_vcpu *vcpu, unsigned long cr4) 1096 { 1097 return __kvm_is_valid_cr4(vcpu, cr4) && 1098 static_call(kvm_x86_is_valid_cr4)(vcpu, cr4); 1099 } 1100 1101 void kvm_post_set_cr4(struct kvm_vcpu *vcpu, unsigned long old_cr4, unsigned long cr4) 1102 { 1103 if ((cr4 ^ old_cr4) & KVM_MMU_CR4_ROLE_BITS) 1104 kvm_mmu_reset_context(vcpu); 1105 1106 /* 1107 * If CR4.PCIDE is changed 0 -> 1, there is no need to flush the TLB 1108 * according to the SDM; however, stale prev_roots could be reused 1109 * incorrectly in the future after a MOV to CR3 with NOFLUSH=1, so we 1110 * free them all. This is *not* a superset of KVM_REQ_TLB_FLUSH_GUEST 1111 * or KVM_REQ_TLB_FLUSH_CURRENT, because the hardware TLB is not flushed, 1112 * so fall through. 1113 */ 1114 if (!tdp_enabled && 1115 (cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) 1116 kvm_mmu_unload(vcpu); 1117 1118 /* 1119 * The TLB has to be flushed for all PCIDs if any of the following 1120 * (architecturally required) changes happen: 1121 * - CR4.PCIDE is changed from 1 to 0 1122 * - CR4.PGE is toggled 1123 * 1124 * This is a superset of KVM_REQ_TLB_FLUSH_CURRENT. 1125 */ 1126 if (((cr4 ^ old_cr4) & X86_CR4_PGE) || 1127 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE))) 1128 kvm_make_request(KVM_REQ_TLB_FLUSH_GUEST, vcpu); 1129 1130 /* 1131 * The TLB has to be flushed for the current PCID if any of the 1132 * following (architecturally required) changes happen: 1133 * - CR4.SMEP is changed from 0 to 1 1134 * - CR4.PAE is toggled 1135 */ 1136 else if (((cr4 ^ old_cr4) & X86_CR4_PAE) || 1137 ((cr4 & X86_CR4_SMEP) && !(old_cr4 & X86_CR4_SMEP))) 1138 kvm_make_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu); 1139 1140 } 1141 EXPORT_SYMBOL_GPL(kvm_post_set_cr4); 1142 1143 int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4) 1144 { 1145 unsigned long old_cr4 = kvm_read_cr4(vcpu); 1146 1147 if (!kvm_is_valid_cr4(vcpu, cr4)) 1148 return 1; 1149 1150 if (is_long_mode(vcpu)) { 1151 if (!(cr4 & X86_CR4_PAE)) 1152 return 1; 1153 if ((cr4 ^ old_cr4) & X86_CR4_LA57) 1154 return 1; 1155 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE) 1156 && ((cr4 ^ old_cr4) & X86_CR4_PDPTR_BITS) 1157 && !load_pdptrs(vcpu, kvm_read_cr3(vcpu))) 1158 return 1; 1159 1160 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) { 1161 if (!guest_cpuid_has(vcpu, X86_FEATURE_PCID)) 1162 return 1; 1163 1164 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */ 1165 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu)) 1166 return 1; 1167 } 1168 1169 static_call(kvm_x86_set_cr4)(vcpu, cr4); 1170 1171 kvm_post_set_cr4(vcpu, old_cr4, cr4); 1172 1173 return 0; 1174 } 1175 EXPORT_SYMBOL_GPL(kvm_set_cr4); 1176 1177 static void kvm_invalidate_pcid(struct kvm_vcpu *vcpu, unsigned long pcid) 1178 { 1179 struct kvm_mmu *mmu = vcpu->arch.mmu; 1180 unsigned long roots_to_free = 0; 1181 int i; 1182 1183 /* 1184 * MOV CR3 and INVPCID are usually not intercepted when using TDP, but 1185 * this is reachable when running EPT=1 and unrestricted_guest=0, and 1186 * also via the emulator. KVM's TDP page tables are not in the scope of 1187 * the invalidation, but the guest's TLB entries need to be flushed as 1188 * the CPU may have cached entries in its TLB for the target PCID. 1189 */ 1190 if (unlikely(tdp_enabled)) { 1191 kvm_make_request(KVM_REQ_TLB_FLUSH_GUEST, vcpu); 1192 return; 1193 } 1194 1195 /* 1196 * If neither the current CR3 nor any of the prev_roots use the given 1197 * PCID, then nothing needs to be done here because a resync will 1198 * happen anyway before switching to any other CR3. 1199 */ 1200 if (kvm_get_active_pcid(vcpu) == pcid) { 1201 kvm_make_request(KVM_REQ_MMU_SYNC, vcpu); 1202 kvm_make_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu); 1203 } 1204 1205 /* 1206 * If PCID is disabled, there is no need to free prev_roots even if the 1207 * PCIDs for them are also 0, because MOV to CR3 always flushes the TLB 1208 * with PCIDE=0. 1209 */ 1210 if (!kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE)) 1211 return; 1212 1213 for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++) 1214 if (kvm_get_pcid(vcpu, mmu->prev_roots[i].pgd) == pcid) 1215 roots_to_free |= KVM_MMU_ROOT_PREVIOUS(i); 1216 1217 kvm_mmu_free_roots(vcpu->kvm, mmu, roots_to_free); 1218 } 1219 1220 int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3) 1221 { 1222 bool skip_tlb_flush = false; 1223 unsigned long pcid = 0; 1224 #ifdef CONFIG_X86_64 1225 bool pcid_enabled = kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE); 1226 1227 if (pcid_enabled) { 1228 skip_tlb_flush = cr3 & X86_CR3_PCID_NOFLUSH; 1229 cr3 &= ~X86_CR3_PCID_NOFLUSH; 1230 pcid = cr3 & X86_CR3_PCID_MASK; 1231 } 1232 #endif 1233 1234 /* PDPTRs are always reloaded for PAE paging. */ 1235 if (cr3 == kvm_read_cr3(vcpu) && !is_pae_paging(vcpu)) 1236 goto handle_tlb_flush; 1237 1238 /* 1239 * Do not condition the GPA check on long mode, this helper is used to 1240 * stuff CR3, e.g. for RSM emulation, and there is no guarantee that 1241 * the current vCPU mode is accurate. 1242 */ 1243 if (kvm_vcpu_is_illegal_gpa(vcpu, cr3)) 1244 return 1; 1245 1246 if (is_pae_paging(vcpu) && !load_pdptrs(vcpu, cr3)) 1247 return 1; 1248 1249 if (cr3 != kvm_read_cr3(vcpu)) 1250 kvm_mmu_new_pgd(vcpu, cr3); 1251 1252 vcpu->arch.cr3 = cr3; 1253 kvm_register_mark_dirty(vcpu, VCPU_EXREG_CR3); 1254 /* Do not call post_set_cr3, we do not get here for confidential guests. */ 1255 1256 handle_tlb_flush: 1257 /* 1258 * A load of CR3 that flushes the TLB flushes only the current PCID, 1259 * even if PCID is disabled, in which case PCID=0 is flushed. It's a 1260 * moot point in the end because _disabling_ PCID will flush all PCIDs, 1261 * and it's impossible to use a non-zero PCID when PCID is disabled, 1262 * i.e. only PCID=0 can be relevant. 1263 */ 1264 if (!skip_tlb_flush) 1265 kvm_invalidate_pcid(vcpu, pcid); 1266 1267 return 0; 1268 } 1269 EXPORT_SYMBOL_GPL(kvm_set_cr3); 1270 1271 int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8) 1272 { 1273 if (cr8 & CR8_RESERVED_BITS) 1274 return 1; 1275 if (lapic_in_kernel(vcpu)) 1276 kvm_lapic_set_tpr(vcpu, cr8); 1277 else 1278 vcpu->arch.cr8 = cr8; 1279 return 0; 1280 } 1281 EXPORT_SYMBOL_GPL(kvm_set_cr8); 1282 1283 unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu) 1284 { 1285 if (lapic_in_kernel(vcpu)) 1286 return kvm_lapic_get_cr8(vcpu); 1287 else 1288 return vcpu->arch.cr8; 1289 } 1290 EXPORT_SYMBOL_GPL(kvm_get_cr8); 1291 1292 static void kvm_update_dr0123(struct kvm_vcpu *vcpu) 1293 { 1294 int i; 1295 1296 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) { 1297 for (i = 0; i < KVM_NR_DB_REGS; i++) 1298 vcpu->arch.eff_db[i] = vcpu->arch.db[i]; 1299 } 1300 } 1301 1302 void kvm_update_dr7(struct kvm_vcpu *vcpu) 1303 { 1304 unsigned long dr7; 1305 1306 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) 1307 dr7 = vcpu->arch.guest_debug_dr7; 1308 else 1309 dr7 = vcpu->arch.dr7; 1310 static_call(kvm_x86_set_dr7)(vcpu, dr7); 1311 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED; 1312 if (dr7 & DR7_BP_EN_MASK) 1313 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED; 1314 } 1315 EXPORT_SYMBOL_GPL(kvm_update_dr7); 1316 1317 static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu) 1318 { 1319 u64 fixed = DR6_FIXED_1; 1320 1321 if (!guest_cpuid_has(vcpu, X86_FEATURE_RTM)) 1322 fixed |= DR6_RTM; 1323 1324 if (!guest_cpuid_has(vcpu, X86_FEATURE_BUS_LOCK_DETECT)) 1325 fixed |= DR6_BUS_LOCK; 1326 return fixed; 1327 } 1328 1329 int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val) 1330 { 1331 size_t size = ARRAY_SIZE(vcpu->arch.db); 1332 1333 switch (dr) { 1334 case 0 ... 3: 1335 vcpu->arch.db[array_index_nospec(dr, size)] = val; 1336 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) 1337 vcpu->arch.eff_db[dr] = val; 1338 break; 1339 case 4: 1340 case 6: 1341 if (!kvm_dr6_valid(val)) 1342 return 1; /* #GP */ 1343 vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu); 1344 break; 1345 case 5: 1346 default: /* 7 */ 1347 if (!kvm_dr7_valid(val)) 1348 return 1; /* #GP */ 1349 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1; 1350 kvm_update_dr7(vcpu); 1351 break; 1352 } 1353 1354 return 0; 1355 } 1356 EXPORT_SYMBOL_GPL(kvm_set_dr); 1357 1358 void kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val) 1359 { 1360 size_t size = ARRAY_SIZE(vcpu->arch.db); 1361 1362 switch (dr) { 1363 case 0 ... 3: 1364 *val = vcpu->arch.db[array_index_nospec(dr, size)]; 1365 break; 1366 case 4: 1367 case 6: 1368 *val = vcpu->arch.dr6; 1369 break; 1370 case 5: 1371 default: /* 7 */ 1372 *val = vcpu->arch.dr7; 1373 break; 1374 } 1375 } 1376 EXPORT_SYMBOL_GPL(kvm_get_dr); 1377 1378 int kvm_emulate_rdpmc(struct kvm_vcpu *vcpu) 1379 { 1380 u32 ecx = kvm_rcx_read(vcpu); 1381 u64 data; 1382 1383 if (kvm_pmu_rdpmc(vcpu, ecx, &data)) { 1384 kvm_inject_gp(vcpu, 0); 1385 return 1; 1386 } 1387 1388 kvm_rax_write(vcpu, (u32)data); 1389 kvm_rdx_write(vcpu, data >> 32); 1390 return kvm_skip_emulated_instruction(vcpu); 1391 } 1392 EXPORT_SYMBOL_GPL(kvm_emulate_rdpmc); 1393 1394 /* 1395 * List of msr numbers which we expose to userspace through KVM_GET_MSRS 1396 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST. 1397 * 1398 * The three MSR lists(msrs_to_save, emulated_msrs, msr_based_features) 1399 * extract the supported MSRs from the related const lists. 1400 * msrs_to_save is selected from the msrs_to_save_all to reflect the 1401 * capabilities of the host cpu. This capabilities test skips MSRs that are 1402 * kvm-specific. Those are put in emulated_msrs_all; filtering of emulated_msrs 1403 * may depend on host virtualization features rather than host cpu features. 1404 */ 1405 1406 static const u32 msrs_to_save_all[] = { 1407 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP, 1408 MSR_STAR, 1409 #ifdef CONFIG_X86_64 1410 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR, 1411 #endif 1412 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA, 1413 MSR_IA32_FEAT_CTL, MSR_IA32_BNDCFGS, MSR_TSC_AUX, 1414 MSR_IA32_SPEC_CTRL, 1415 MSR_IA32_RTIT_CTL, MSR_IA32_RTIT_STATUS, MSR_IA32_RTIT_CR3_MATCH, 1416 MSR_IA32_RTIT_OUTPUT_BASE, MSR_IA32_RTIT_OUTPUT_MASK, 1417 MSR_IA32_RTIT_ADDR0_A, MSR_IA32_RTIT_ADDR0_B, 1418 MSR_IA32_RTIT_ADDR1_A, MSR_IA32_RTIT_ADDR1_B, 1419 MSR_IA32_RTIT_ADDR2_A, MSR_IA32_RTIT_ADDR2_B, 1420 MSR_IA32_RTIT_ADDR3_A, MSR_IA32_RTIT_ADDR3_B, 1421 MSR_IA32_UMWAIT_CONTROL, 1422 1423 MSR_ARCH_PERFMON_FIXED_CTR0, MSR_ARCH_PERFMON_FIXED_CTR1, 1424 MSR_ARCH_PERFMON_FIXED_CTR0 + 2, 1425 MSR_CORE_PERF_FIXED_CTR_CTRL, MSR_CORE_PERF_GLOBAL_STATUS, 1426 MSR_CORE_PERF_GLOBAL_CTRL, MSR_CORE_PERF_GLOBAL_OVF_CTRL, 1427 MSR_ARCH_PERFMON_PERFCTR0, MSR_ARCH_PERFMON_PERFCTR1, 1428 MSR_ARCH_PERFMON_PERFCTR0 + 2, MSR_ARCH_PERFMON_PERFCTR0 + 3, 1429 MSR_ARCH_PERFMON_PERFCTR0 + 4, MSR_ARCH_PERFMON_PERFCTR0 + 5, 1430 MSR_ARCH_PERFMON_PERFCTR0 + 6, MSR_ARCH_PERFMON_PERFCTR0 + 7, 1431 MSR_ARCH_PERFMON_PERFCTR0 + 8, MSR_ARCH_PERFMON_PERFCTR0 + 9, 1432 MSR_ARCH_PERFMON_PERFCTR0 + 10, MSR_ARCH_PERFMON_PERFCTR0 + 11, 1433 MSR_ARCH_PERFMON_PERFCTR0 + 12, MSR_ARCH_PERFMON_PERFCTR0 + 13, 1434 MSR_ARCH_PERFMON_PERFCTR0 + 14, MSR_ARCH_PERFMON_PERFCTR0 + 15, 1435 MSR_ARCH_PERFMON_PERFCTR0 + 16, MSR_ARCH_PERFMON_PERFCTR0 + 17, 1436 MSR_ARCH_PERFMON_EVENTSEL0, MSR_ARCH_PERFMON_EVENTSEL1, 1437 MSR_ARCH_PERFMON_EVENTSEL0 + 2, MSR_ARCH_PERFMON_EVENTSEL0 + 3, 1438 MSR_ARCH_PERFMON_EVENTSEL0 + 4, MSR_ARCH_PERFMON_EVENTSEL0 + 5, 1439 MSR_ARCH_PERFMON_EVENTSEL0 + 6, MSR_ARCH_PERFMON_EVENTSEL0 + 7, 1440 MSR_ARCH_PERFMON_EVENTSEL0 + 8, MSR_ARCH_PERFMON_EVENTSEL0 + 9, 1441 MSR_ARCH_PERFMON_EVENTSEL0 + 10, MSR_ARCH_PERFMON_EVENTSEL0 + 11, 1442 MSR_ARCH_PERFMON_EVENTSEL0 + 12, MSR_ARCH_PERFMON_EVENTSEL0 + 13, 1443 MSR_ARCH_PERFMON_EVENTSEL0 + 14, MSR_ARCH_PERFMON_EVENTSEL0 + 15, 1444 MSR_ARCH_PERFMON_EVENTSEL0 + 16, MSR_ARCH_PERFMON_EVENTSEL0 + 17, 1445 MSR_IA32_PEBS_ENABLE, MSR_IA32_DS_AREA, MSR_PEBS_DATA_CFG, 1446 1447 MSR_K7_EVNTSEL0, MSR_K7_EVNTSEL1, MSR_K7_EVNTSEL2, MSR_K7_EVNTSEL3, 1448 MSR_K7_PERFCTR0, MSR_K7_PERFCTR1, MSR_K7_PERFCTR2, MSR_K7_PERFCTR3, 1449 MSR_F15H_PERF_CTL0, MSR_F15H_PERF_CTL1, MSR_F15H_PERF_CTL2, 1450 MSR_F15H_PERF_CTL3, MSR_F15H_PERF_CTL4, MSR_F15H_PERF_CTL5, 1451 MSR_F15H_PERF_CTR0, MSR_F15H_PERF_CTR1, MSR_F15H_PERF_CTR2, 1452 MSR_F15H_PERF_CTR3, MSR_F15H_PERF_CTR4, MSR_F15H_PERF_CTR5, 1453 MSR_IA32_XFD, MSR_IA32_XFD_ERR, 1454 }; 1455 1456 static u32 msrs_to_save[ARRAY_SIZE(msrs_to_save_all)]; 1457 static unsigned num_msrs_to_save; 1458 1459 static const u32 emulated_msrs_all[] = { 1460 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK, 1461 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW, 1462 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL, 1463 HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC, 1464 HV_X64_MSR_TSC_FREQUENCY, HV_X64_MSR_APIC_FREQUENCY, 1465 HV_X64_MSR_CRASH_P0, HV_X64_MSR_CRASH_P1, HV_X64_MSR_CRASH_P2, 1466 HV_X64_MSR_CRASH_P3, HV_X64_MSR_CRASH_P4, HV_X64_MSR_CRASH_CTL, 1467 HV_X64_MSR_RESET, 1468 HV_X64_MSR_VP_INDEX, 1469 HV_X64_MSR_VP_RUNTIME, 1470 HV_X64_MSR_SCONTROL, 1471 HV_X64_MSR_STIMER0_CONFIG, 1472 HV_X64_MSR_VP_ASSIST_PAGE, 1473 HV_X64_MSR_REENLIGHTENMENT_CONTROL, HV_X64_MSR_TSC_EMULATION_CONTROL, 1474 HV_X64_MSR_TSC_EMULATION_STATUS, 1475 HV_X64_MSR_SYNDBG_OPTIONS, 1476 HV_X64_MSR_SYNDBG_CONTROL, HV_X64_MSR_SYNDBG_STATUS, 1477 HV_X64_MSR_SYNDBG_SEND_BUFFER, HV_X64_MSR_SYNDBG_RECV_BUFFER, 1478 HV_X64_MSR_SYNDBG_PENDING_BUFFER, 1479 1480 MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME, 1481 MSR_KVM_PV_EOI_EN, MSR_KVM_ASYNC_PF_INT, MSR_KVM_ASYNC_PF_ACK, 1482 1483 MSR_IA32_TSC_ADJUST, 1484 MSR_IA32_TSC_DEADLINE, 1485 MSR_IA32_ARCH_CAPABILITIES, 1486 MSR_IA32_PERF_CAPABILITIES, 1487 MSR_IA32_MISC_ENABLE, 1488 MSR_IA32_MCG_STATUS, 1489 MSR_IA32_MCG_CTL, 1490 MSR_IA32_MCG_EXT_CTL, 1491 MSR_IA32_SMBASE, 1492 MSR_SMI_COUNT, 1493 MSR_PLATFORM_INFO, 1494 MSR_MISC_FEATURES_ENABLES, 1495 MSR_AMD64_VIRT_SPEC_CTRL, 1496 MSR_AMD64_TSC_RATIO, 1497 MSR_IA32_POWER_CTL, 1498 MSR_IA32_UCODE_REV, 1499 1500 /* 1501 * The following list leaves out MSRs whose values are determined 1502 * by arch/x86/kvm/vmx/nested.c based on CPUID or other MSRs. 1503 * We always support the "true" VMX control MSRs, even if the host 1504 * processor does not, so I am putting these registers here rather 1505 * than in msrs_to_save_all. 1506 */ 1507 MSR_IA32_VMX_BASIC, 1508 MSR_IA32_VMX_TRUE_PINBASED_CTLS, 1509 MSR_IA32_VMX_TRUE_PROCBASED_CTLS, 1510 MSR_IA32_VMX_TRUE_EXIT_CTLS, 1511 MSR_IA32_VMX_TRUE_ENTRY_CTLS, 1512 MSR_IA32_VMX_MISC, 1513 MSR_IA32_VMX_CR0_FIXED0, 1514 MSR_IA32_VMX_CR4_FIXED0, 1515 MSR_IA32_VMX_VMCS_ENUM, 1516 MSR_IA32_VMX_PROCBASED_CTLS2, 1517 MSR_IA32_VMX_EPT_VPID_CAP, 1518 MSR_IA32_VMX_VMFUNC, 1519 1520 MSR_K7_HWCR, 1521 MSR_KVM_POLL_CONTROL, 1522 }; 1523 1524 static u32 emulated_msrs[ARRAY_SIZE(emulated_msrs_all)]; 1525 static unsigned num_emulated_msrs; 1526 1527 /* 1528 * List of msr numbers which are used to expose MSR-based features that 1529 * can be used by a hypervisor to validate requested CPU features. 1530 */ 1531 static const u32 msr_based_features_all[] = { 1532 MSR_IA32_VMX_BASIC, 1533 MSR_IA32_VMX_TRUE_PINBASED_CTLS, 1534 MSR_IA32_VMX_PINBASED_CTLS, 1535 MSR_IA32_VMX_TRUE_PROCBASED_CTLS, 1536 MSR_IA32_VMX_PROCBASED_CTLS, 1537 MSR_IA32_VMX_TRUE_EXIT_CTLS, 1538 MSR_IA32_VMX_EXIT_CTLS, 1539 MSR_IA32_VMX_TRUE_ENTRY_CTLS, 1540 MSR_IA32_VMX_ENTRY_CTLS, 1541 MSR_IA32_VMX_MISC, 1542 MSR_IA32_VMX_CR0_FIXED0, 1543 MSR_IA32_VMX_CR0_FIXED1, 1544 MSR_IA32_VMX_CR4_FIXED0, 1545 MSR_IA32_VMX_CR4_FIXED1, 1546 MSR_IA32_VMX_VMCS_ENUM, 1547 MSR_IA32_VMX_PROCBASED_CTLS2, 1548 MSR_IA32_VMX_EPT_VPID_CAP, 1549 MSR_IA32_VMX_VMFUNC, 1550 1551 MSR_F10H_DECFG, 1552 MSR_IA32_UCODE_REV, 1553 MSR_IA32_ARCH_CAPABILITIES, 1554 MSR_IA32_PERF_CAPABILITIES, 1555 }; 1556 1557 static u32 msr_based_features[ARRAY_SIZE(msr_based_features_all)]; 1558 static unsigned int num_msr_based_features; 1559 1560 /* 1561 * Some IA32_ARCH_CAPABILITIES bits have dependencies on MSRs that KVM 1562 * does not yet virtualize. These include: 1563 * 10 - MISC_PACKAGE_CTRLS 1564 * 11 - ENERGY_FILTERING_CTL 1565 * 12 - DOITM 1566 * 18 - FB_CLEAR_CTRL 1567 * 21 - XAPIC_DISABLE_STATUS 1568 * 23 - OVERCLOCKING_STATUS 1569 */ 1570 1571 #define KVM_SUPPORTED_ARCH_CAP \ 1572 (ARCH_CAP_RDCL_NO | ARCH_CAP_IBRS_ALL | ARCH_CAP_RSBA | \ 1573 ARCH_CAP_SKIP_VMENTRY_L1DFLUSH | ARCH_CAP_SSB_NO | ARCH_CAP_MDS_NO | \ 1574 ARCH_CAP_PSCHANGE_MC_NO | ARCH_CAP_TSX_CTRL_MSR | ARCH_CAP_TAA_NO | \ 1575 ARCH_CAP_SBDR_SSDP_NO | ARCH_CAP_FBSDP_NO | ARCH_CAP_PSDP_NO | \ 1576 ARCH_CAP_FB_CLEAR | ARCH_CAP_RRSBA | ARCH_CAP_PBRSB_NO) 1577 1578 static u64 kvm_get_arch_capabilities(void) 1579 { 1580 u64 data = 0; 1581 1582 if (boot_cpu_has(X86_FEATURE_ARCH_CAPABILITIES)) { 1583 rdmsrl(MSR_IA32_ARCH_CAPABILITIES, data); 1584 data &= KVM_SUPPORTED_ARCH_CAP; 1585 } 1586 1587 /* 1588 * If nx_huge_pages is enabled, KVM's shadow paging will ensure that 1589 * the nested hypervisor runs with NX huge pages. If it is not, 1590 * L1 is anyway vulnerable to ITLB_MULTIHIT exploits from other 1591 * L1 guests, so it need not worry about its own (L2) guests. 1592 */ 1593 data |= ARCH_CAP_PSCHANGE_MC_NO; 1594 1595 /* 1596 * If we're doing cache flushes (either "always" or "cond") 1597 * we will do one whenever the guest does a vmlaunch/vmresume. 1598 * If an outer hypervisor is doing the cache flush for us 1599 * (VMENTER_L1D_FLUSH_NESTED_VM), we can safely pass that 1600 * capability to the guest too, and if EPT is disabled we're not 1601 * vulnerable. Overall, only VMENTER_L1D_FLUSH_NEVER will 1602 * require a nested hypervisor to do a flush of its own. 1603 */ 1604 if (l1tf_vmx_mitigation != VMENTER_L1D_FLUSH_NEVER) 1605 data |= ARCH_CAP_SKIP_VMENTRY_L1DFLUSH; 1606 1607 if (!boot_cpu_has_bug(X86_BUG_CPU_MELTDOWN)) 1608 data |= ARCH_CAP_RDCL_NO; 1609 if (!boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS)) 1610 data |= ARCH_CAP_SSB_NO; 1611 if (!boot_cpu_has_bug(X86_BUG_MDS)) 1612 data |= ARCH_CAP_MDS_NO; 1613 1614 if (!boot_cpu_has(X86_FEATURE_RTM)) { 1615 /* 1616 * If RTM=0 because the kernel has disabled TSX, the host might 1617 * have TAA_NO or TSX_CTRL. Clear TAA_NO (the guest sees RTM=0 1618 * and therefore knows that there cannot be TAA) but keep 1619 * TSX_CTRL: some buggy userspaces leave it set on tsx=on hosts, 1620 * and we want to allow migrating those guests to tsx=off hosts. 1621 */ 1622 data &= ~ARCH_CAP_TAA_NO; 1623 } else if (!boot_cpu_has_bug(X86_BUG_TAA)) { 1624 data |= ARCH_CAP_TAA_NO; 1625 } else { 1626 /* 1627 * Nothing to do here; we emulate TSX_CTRL if present on the 1628 * host so the guest can choose between disabling TSX or 1629 * using VERW to clear CPU buffers. 1630 */ 1631 } 1632 1633 return data; 1634 } 1635 1636 static int kvm_get_msr_feature(struct kvm_msr_entry *msr) 1637 { 1638 switch (msr->index) { 1639 case MSR_IA32_ARCH_CAPABILITIES: 1640 msr->data = kvm_get_arch_capabilities(); 1641 break; 1642 case MSR_IA32_UCODE_REV: 1643 rdmsrl_safe(msr->index, &msr->data); 1644 break; 1645 default: 1646 return static_call(kvm_x86_get_msr_feature)(msr); 1647 } 1648 return 0; 1649 } 1650 1651 static int do_get_msr_feature(struct kvm_vcpu *vcpu, unsigned index, u64 *data) 1652 { 1653 struct kvm_msr_entry msr; 1654 int r; 1655 1656 msr.index = index; 1657 r = kvm_get_msr_feature(&msr); 1658 1659 if (r == KVM_MSR_RET_INVALID) { 1660 /* Unconditionally clear the output for simplicity */ 1661 *data = 0; 1662 if (kvm_msr_ignored_check(index, 0, false)) 1663 r = 0; 1664 } 1665 1666 if (r) 1667 return r; 1668 1669 *data = msr.data; 1670 1671 return 0; 1672 } 1673 1674 static bool __kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer) 1675 { 1676 if (efer & EFER_FFXSR && !guest_cpuid_has(vcpu, X86_FEATURE_FXSR_OPT)) 1677 return false; 1678 1679 if (efer & EFER_SVME && !guest_cpuid_has(vcpu, X86_FEATURE_SVM)) 1680 return false; 1681 1682 if (efer & (EFER_LME | EFER_LMA) && 1683 !guest_cpuid_has(vcpu, X86_FEATURE_LM)) 1684 return false; 1685 1686 if (efer & EFER_NX && !guest_cpuid_has(vcpu, X86_FEATURE_NX)) 1687 return false; 1688 1689 return true; 1690 1691 } 1692 bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer) 1693 { 1694 if (efer & efer_reserved_bits) 1695 return false; 1696 1697 return __kvm_valid_efer(vcpu, efer); 1698 } 1699 EXPORT_SYMBOL_GPL(kvm_valid_efer); 1700 1701 static int set_efer(struct kvm_vcpu *vcpu, struct msr_data *msr_info) 1702 { 1703 u64 old_efer = vcpu->arch.efer; 1704 u64 efer = msr_info->data; 1705 int r; 1706 1707 if (efer & efer_reserved_bits) 1708 return 1; 1709 1710 if (!msr_info->host_initiated) { 1711 if (!__kvm_valid_efer(vcpu, efer)) 1712 return 1; 1713 1714 if (is_paging(vcpu) && 1715 (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME)) 1716 return 1; 1717 } 1718 1719 efer &= ~EFER_LMA; 1720 efer |= vcpu->arch.efer & EFER_LMA; 1721 1722 r = static_call(kvm_x86_set_efer)(vcpu, efer); 1723 if (r) { 1724 WARN_ON(r > 0); 1725 return r; 1726 } 1727 1728 if ((efer ^ old_efer) & KVM_MMU_EFER_ROLE_BITS) 1729 kvm_mmu_reset_context(vcpu); 1730 1731 return 0; 1732 } 1733 1734 void kvm_enable_efer_bits(u64 mask) 1735 { 1736 efer_reserved_bits &= ~mask; 1737 } 1738 EXPORT_SYMBOL_GPL(kvm_enable_efer_bits); 1739 1740 bool kvm_msr_allowed(struct kvm_vcpu *vcpu, u32 index, u32 type) 1741 { 1742 struct kvm_x86_msr_filter *msr_filter; 1743 struct msr_bitmap_range *ranges; 1744 struct kvm *kvm = vcpu->kvm; 1745 bool allowed; 1746 int idx; 1747 u32 i; 1748 1749 /* x2APIC MSRs do not support filtering. */ 1750 if (index >= 0x800 && index <= 0x8ff) 1751 return true; 1752 1753 idx = srcu_read_lock(&kvm->srcu); 1754 1755 msr_filter = srcu_dereference(kvm->arch.msr_filter, &kvm->srcu); 1756 if (!msr_filter) { 1757 allowed = true; 1758 goto out; 1759 } 1760 1761 allowed = msr_filter->default_allow; 1762 ranges = msr_filter->ranges; 1763 1764 for (i = 0; i < msr_filter->count; i++) { 1765 u32 start = ranges[i].base; 1766 u32 end = start + ranges[i].nmsrs; 1767 u32 flags = ranges[i].flags; 1768 unsigned long *bitmap = ranges[i].bitmap; 1769 1770 if ((index >= start) && (index < end) && (flags & type)) { 1771 allowed = !!test_bit(index - start, bitmap); 1772 break; 1773 } 1774 } 1775 1776 out: 1777 srcu_read_unlock(&kvm->srcu, idx); 1778 1779 return allowed; 1780 } 1781 EXPORT_SYMBOL_GPL(kvm_msr_allowed); 1782 1783 /* 1784 * Write @data into the MSR specified by @index. Select MSR specific fault 1785 * checks are bypassed if @host_initiated is %true. 1786 * Returns 0 on success, non-0 otherwise. 1787 * Assumes vcpu_load() was already called. 1788 */ 1789 static int __kvm_set_msr(struct kvm_vcpu *vcpu, u32 index, u64 data, 1790 bool host_initiated) 1791 { 1792 struct msr_data msr; 1793 1794 switch (index) { 1795 case MSR_FS_BASE: 1796 case MSR_GS_BASE: 1797 case MSR_KERNEL_GS_BASE: 1798 case MSR_CSTAR: 1799 case MSR_LSTAR: 1800 if (is_noncanonical_address(data, vcpu)) 1801 return 1; 1802 break; 1803 case MSR_IA32_SYSENTER_EIP: 1804 case MSR_IA32_SYSENTER_ESP: 1805 /* 1806 * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if 1807 * non-canonical address is written on Intel but not on 1808 * AMD (which ignores the top 32-bits, because it does 1809 * not implement 64-bit SYSENTER). 1810 * 1811 * 64-bit code should hence be able to write a non-canonical 1812 * value on AMD. Making the address canonical ensures that 1813 * vmentry does not fail on Intel after writing a non-canonical 1814 * value, and that something deterministic happens if the guest 1815 * invokes 64-bit SYSENTER. 1816 */ 1817 data = __canonical_address(data, vcpu_virt_addr_bits(vcpu)); 1818 break; 1819 case MSR_TSC_AUX: 1820 if (!kvm_is_supported_user_return_msr(MSR_TSC_AUX)) 1821 return 1; 1822 1823 if (!host_initiated && 1824 !guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP) && 1825 !guest_cpuid_has(vcpu, X86_FEATURE_RDPID)) 1826 return 1; 1827 1828 /* 1829 * Per Intel's SDM, bits 63:32 are reserved, but AMD's APM has 1830 * incomplete and conflicting architectural behavior. Current 1831 * AMD CPUs completely ignore bits 63:32, i.e. they aren't 1832 * reserved and always read as zeros. Enforce Intel's reserved 1833 * bits check if and only if the guest CPU is Intel, and clear 1834 * the bits in all other cases. This ensures cross-vendor 1835 * migration will provide consistent behavior for the guest. 1836 */ 1837 if (guest_cpuid_is_intel(vcpu) && (data >> 32) != 0) 1838 return 1; 1839 1840 data = (u32)data; 1841 break; 1842 } 1843 1844 msr.data = data; 1845 msr.index = index; 1846 msr.host_initiated = host_initiated; 1847 1848 return static_call(kvm_x86_set_msr)(vcpu, &msr); 1849 } 1850 1851 static int kvm_set_msr_ignored_check(struct kvm_vcpu *vcpu, 1852 u32 index, u64 data, bool host_initiated) 1853 { 1854 int ret = __kvm_set_msr(vcpu, index, data, host_initiated); 1855 1856 if (ret == KVM_MSR_RET_INVALID) 1857 if (kvm_msr_ignored_check(index, data, true)) 1858 ret = 0; 1859 1860 return ret; 1861 } 1862 1863 /* 1864 * Read the MSR specified by @index into @data. Select MSR specific fault 1865 * checks are bypassed if @host_initiated is %true. 1866 * Returns 0 on success, non-0 otherwise. 1867 * Assumes vcpu_load() was already called. 1868 */ 1869 int __kvm_get_msr(struct kvm_vcpu *vcpu, u32 index, u64 *data, 1870 bool host_initiated) 1871 { 1872 struct msr_data msr; 1873 int ret; 1874 1875 switch (index) { 1876 case MSR_TSC_AUX: 1877 if (!kvm_is_supported_user_return_msr(MSR_TSC_AUX)) 1878 return 1; 1879 1880 if (!host_initiated && 1881 !guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP) && 1882 !guest_cpuid_has(vcpu, X86_FEATURE_RDPID)) 1883 return 1; 1884 break; 1885 } 1886 1887 msr.index = index; 1888 msr.host_initiated = host_initiated; 1889 1890 ret = static_call(kvm_x86_get_msr)(vcpu, &msr); 1891 if (!ret) 1892 *data = msr.data; 1893 return ret; 1894 } 1895 1896 static int kvm_get_msr_ignored_check(struct kvm_vcpu *vcpu, 1897 u32 index, u64 *data, bool host_initiated) 1898 { 1899 int ret = __kvm_get_msr(vcpu, index, data, host_initiated); 1900 1901 if (ret == KVM_MSR_RET_INVALID) { 1902 /* Unconditionally clear *data for simplicity */ 1903 *data = 0; 1904 if (kvm_msr_ignored_check(index, 0, false)) 1905 ret = 0; 1906 } 1907 1908 return ret; 1909 } 1910 1911 static int kvm_get_msr_with_filter(struct kvm_vcpu *vcpu, u32 index, u64 *data) 1912 { 1913 if (!kvm_msr_allowed(vcpu, index, KVM_MSR_FILTER_READ)) 1914 return KVM_MSR_RET_FILTERED; 1915 return kvm_get_msr_ignored_check(vcpu, index, data, false); 1916 } 1917 1918 static int kvm_set_msr_with_filter(struct kvm_vcpu *vcpu, u32 index, u64 data) 1919 { 1920 if (!kvm_msr_allowed(vcpu, index, KVM_MSR_FILTER_WRITE)) 1921 return KVM_MSR_RET_FILTERED; 1922 return kvm_set_msr_ignored_check(vcpu, index, data, false); 1923 } 1924 1925 int kvm_get_msr(struct kvm_vcpu *vcpu, u32 index, u64 *data) 1926 { 1927 return kvm_get_msr_ignored_check(vcpu, index, data, false); 1928 } 1929 EXPORT_SYMBOL_GPL(kvm_get_msr); 1930 1931 int kvm_set_msr(struct kvm_vcpu *vcpu, u32 index, u64 data) 1932 { 1933 return kvm_set_msr_ignored_check(vcpu, index, data, false); 1934 } 1935 EXPORT_SYMBOL_GPL(kvm_set_msr); 1936 1937 static void complete_userspace_rdmsr(struct kvm_vcpu *vcpu) 1938 { 1939 if (!vcpu->run->msr.error) { 1940 kvm_rax_write(vcpu, (u32)vcpu->run->msr.data); 1941 kvm_rdx_write(vcpu, vcpu->run->msr.data >> 32); 1942 } 1943 } 1944 1945 static int complete_emulated_msr_access(struct kvm_vcpu *vcpu) 1946 { 1947 return complete_emulated_insn_gp(vcpu, vcpu->run->msr.error); 1948 } 1949 1950 static int complete_emulated_rdmsr(struct kvm_vcpu *vcpu) 1951 { 1952 complete_userspace_rdmsr(vcpu); 1953 return complete_emulated_msr_access(vcpu); 1954 } 1955 1956 static int complete_fast_msr_access(struct kvm_vcpu *vcpu) 1957 { 1958 return static_call(kvm_x86_complete_emulated_msr)(vcpu, vcpu->run->msr.error); 1959 } 1960 1961 static int complete_fast_rdmsr(struct kvm_vcpu *vcpu) 1962 { 1963 complete_userspace_rdmsr(vcpu); 1964 return complete_fast_msr_access(vcpu); 1965 } 1966 1967 static u64 kvm_msr_reason(int r) 1968 { 1969 switch (r) { 1970 case KVM_MSR_RET_INVALID: 1971 return KVM_MSR_EXIT_REASON_UNKNOWN; 1972 case KVM_MSR_RET_FILTERED: 1973 return KVM_MSR_EXIT_REASON_FILTER; 1974 default: 1975 return KVM_MSR_EXIT_REASON_INVAL; 1976 } 1977 } 1978 1979 static int kvm_msr_user_space(struct kvm_vcpu *vcpu, u32 index, 1980 u32 exit_reason, u64 data, 1981 int (*completion)(struct kvm_vcpu *vcpu), 1982 int r) 1983 { 1984 u64 msr_reason = kvm_msr_reason(r); 1985 1986 /* Check if the user wanted to know about this MSR fault */ 1987 if (!(vcpu->kvm->arch.user_space_msr_mask & msr_reason)) 1988 return 0; 1989 1990 vcpu->run->exit_reason = exit_reason; 1991 vcpu->run->msr.error = 0; 1992 memset(vcpu->run->msr.pad, 0, sizeof(vcpu->run->msr.pad)); 1993 vcpu->run->msr.reason = msr_reason; 1994 vcpu->run->msr.index = index; 1995 vcpu->run->msr.data = data; 1996 vcpu->arch.complete_userspace_io = completion; 1997 1998 return 1; 1999 } 2000 2001 int kvm_emulate_rdmsr(struct kvm_vcpu *vcpu) 2002 { 2003 u32 ecx = kvm_rcx_read(vcpu); 2004 u64 data; 2005 int r; 2006 2007 r = kvm_get_msr_with_filter(vcpu, ecx, &data); 2008 2009 if (!r) { 2010 trace_kvm_msr_read(ecx, data); 2011 2012 kvm_rax_write(vcpu, data & -1u); 2013 kvm_rdx_write(vcpu, (data >> 32) & -1u); 2014 } else { 2015 /* MSR read failed? See if we should ask user space */ 2016 if (kvm_msr_user_space(vcpu, ecx, KVM_EXIT_X86_RDMSR, 0, 2017 complete_fast_rdmsr, r)) 2018 return 0; 2019 trace_kvm_msr_read_ex(ecx); 2020 } 2021 2022 return static_call(kvm_x86_complete_emulated_msr)(vcpu, r); 2023 } 2024 EXPORT_SYMBOL_GPL(kvm_emulate_rdmsr); 2025 2026 int kvm_emulate_wrmsr(struct kvm_vcpu *vcpu) 2027 { 2028 u32 ecx = kvm_rcx_read(vcpu); 2029 u64 data = kvm_read_edx_eax(vcpu); 2030 int r; 2031 2032 r = kvm_set_msr_with_filter(vcpu, ecx, data); 2033 2034 if (!r) { 2035 trace_kvm_msr_write(ecx, data); 2036 } else { 2037 /* MSR write failed? See if we should ask user space */ 2038 if (kvm_msr_user_space(vcpu, ecx, KVM_EXIT_X86_WRMSR, data, 2039 complete_fast_msr_access, r)) 2040 return 0; 2041 /* Signal all other negative errors to userspace */ 2042 if (r < 0) 2043 return r; 2044 trace_kvm_msr_write_ex(ecx, data); 2045 } 2046 2047 return static_call(kvm_x86_complete_emulated_msr)(vcpu, r); 2048 } 2049 EXPORT_SYMBOL_GPL(kvm_emulate_wrmsr); 2050 2051 int kvm_emulate_as_nop(struct kvm_vcpu *vcpu) 2052 { 2053 return kvm_skip_emulated_instruction(vcpu); 2054 } 2055 EXPORT_SYMBOL_GPL(kvm_emulate_as_nop); 2056 2057 int kvm_emulate_invd(struct kvm_vcpu *vcpu) 2058 { 2059 /* Treat an INVD instruction as a NOP and just skip it. */ 2060 return kvm_emulate_as_nop(vcpu); 2061 } 2062 EXPORT_SYMBOL_GPL(kvm_emulate_invd); 2063 2064 int kvm_handle_invalid_op(struct kvm_vcpu *vcpu) 2065 { 2066 kvm_queue_exception(vcpu, UD_VECTOR); 2067 return 1; 2068 } 2069 EXPORT_SYMBOL_GPL(kvm_handle_invalid_op); 2070 2071 2072 static int kvm_emulate_monitor_mwait(struct kvm_vcpu *vcpu, const char *insn) 2073 { 2074 if (!kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_MWAIT_NEVER_UD_FAULTS) && 2075 !guest_cpuid_has(vcpu, X86_FEATURE_MWAIT)) 2076 return kvm_handle_invalid_op(vcpu); 2077 2078 pr_warn_once("kvm: %s instruction emulated as NOP!\n", insn); 2079 return kvm_emulate_as_nop(vcpu); 2080 } 2081 int kvm_emulate_mwait(struct kvm_vcpu *vcpu) 2082 { 2083 return kvm_emulate_monitor_mwait(vcpu, "MWAIT"); 2084 } 2085 EXPORT_SYMBOL_GPL(kvm_emulate_mwait); 2086 2087 int kvm_emulate_monitor(struct kvm_vcpu *vcpu) 2088 { 2089 return kvm_emulate_monitor_mwait(vcpu, "MONITOR"); 2090 } 2091 EXPORT_SYMBOL_GPL(kvm_emulate_monitor); 2092 2093 static inline bool kvm_vcpu_exit_request(struct kvm_vcpu *vcpu) 2094 { 2095 xfer_to_guest_mode_prepare(); 2096 return vcpu->mode == EXITING_GUEST_MODE || kvm_request_pending(vcpu) || 2097 xfer_to_guest_mode_work_pending(); 2098 } 2099 2100 /* 2101 * The fast path for frequent and performance sensitive wrmsr emulation, 2102 * i.e. the sending of IPI, sending IPI early in the VM-Exit flow reduces 2103 * the latency of virtual IPI by avoiding the expensive bits of transitioning 2104 * from guest to host, e.g. reacquiring KVM's SRCU lock. In contrast to the 2105 * other cases which must be called after interrupts are enabled on the host. 2106 */ 2107 static int handle_fastpath_set_x2apic_icr_irqoff(struct kvm_vcpu *vcpu, u64 data) 2108 { 2109 if (!lapic_in_kernel(vcpu) || !apic_x2apic_mode(vcpu->arch.apic)) 2110 return 1; 2111 2112 if (((data & APIC_SHORT_MASK) == APIC_DEST_NOSHORT) && 2113 ((data & APIC_DEST_MASK) == APIC_DEST_PHYSICAL) && 2114 ((data & APIC_MODE_MASK) == APIC_DM_FIXED) && 2115 ((u32)(data >> 32) != X2APIC_BROADCAST)) 2116 return kvm_x2apic_icr_write(vcpu->arch.apic, data); 2117 2118 return 1; 2119 } 2120 2121 static int handle_fastpath_set_tscdeadline(struct kvm_vcpu *vcpu, u64 data) 2122 { 2123 if (!kvm_can_use_hv_timer(vcpu)) 2124 return 1; 2125 2126 kvm_set_lapic_tscdeadline_msr(vcpu, data); 2127 return 0; 2128 } 2129 2130 fastpath_t handle_fastpath_set_msr_irqoff(struct kvm_vcpu *vcpu) 2131 { 2132 u32 msr = kvm_rcx_read(vcpu); 2133 u64 data; 2134 fastpath_t ret = EXIT_FASTPATH_NONE; 2135 2136 switch (msr) { 2137 case APIC_BASE_MSR + (APIC_ICR >> 4): 2138 data = kvm_read_edx_eax(vcpu); 2139 if (!handle_fastpath_set_x2apic_icr_irqoff(vcpu, data)) { 2140 kvm_skip_emulated_instruction(vcpu); 2141 ret = EXIT_FASTPATH_EXIT_HANDLED; 2142 } 2143 break; 2144 case MSR_IA32_TSC_DEADLINE: 2145 data = kvm_read_edx_eax(vcpu); 2146 if (!handle_fastpath_set_tscdeadline(vcpu, data)) { 2147 kvm_skip_emulated_instruction(vcpu); 2148 ret = EXIT_FASTPATH_REENTER_GUEST; 2149 } 2150 break; 2151 default: 2152 break; 2153 } 2154 2155 if (ret != EXIT_FASTPATH_NONE) 2156 trace_kvm_msr_write(msr, data); 2157 2158 return ret; 2159 } 2160 EXPORT_SYMBOL_GPL(handle_fastpath_set_msr_irqoff); 2161 2162 /* 2163 * Adapt set_msr() to msr_io()'s calling convention 2164 */ 2165 static int do_get_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data) 2166 { 2167 return kvm_get_msr_ignored_check(vcpu, index, data, true); 2168 } 2169 2170 static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data) 2171 { 2172 return kvm_set_msr_ignored_check(vcpu, index, *data, true); 2173 } 2174 2175 #ifdef CONFIG_X86_64 2176 struct pvclock_clock { 2177 int vclock_mode; 2178 u64 cycle_last; 2179 u64 mask; 2180 u32 mult; 2181 u32 shift; 2182 u64 base_cycles; 2183 u64 offset; 2184 }; 2185 2186 struct pvclock_gtod_data { 2187 seqcount_t seq; 2188 2189 struct pvclock_clock clock; /* extract of a clocksource struct */ 2190 struct pvclock_clock raw_clock; /* extract of a clocksource struct */ 2191 2192 ktime_t offs_boot; 2193 u64 wall_time_sec; 2194 }; 2195 2196 static struct pvclock_gtod_data pvclock_gtod_data; 2197 2198 static void update_pvclock_gtod(struct timekeeper *tk) 2199 { 2200 struct pvclock_gtod_data *vdata = &pvclock_gtod_data; 2201 2202 write_seqcount_begin(&vdata->seq); 2203 2204 /* copy pvclock gtod data */ 2205 vdata->clock.vclock_mode = tk->tkr_mono.clock->vdso_clock_mode; 2206 vdata->clock.cycle_last = tk->tkr_mono.cycle_last; 2207 vdata->clock.mask = tk->tkr_mono.mask; 2208 vdata->clock.mult = tk->tkr_mono.mult; 2209 vdata->clock.shift = tk->tkr_mono.shift; 2210 vdata->clock.base_cycles = tk->tkr_mono.xtime_nsec; 2211 vdata->clock.offset = tk->tkr_mono.base; 2212 2213 vdata->raw_clock.vclock_mode = tk->tkr_raw.clock->vdso_clock_mode; 2214 vdata->raw_clock.cycle_last = tk->tkr_raw.cycle_last; 2215 vdata->raw_clock.mask = tk->tkr_raw.mask; 2216 vdata->raw_clock.mult = tk->tkr_raw.mult; 2217 vdata->raw_clock.shift = tk->tkr_raw.shift; 2218 vdata->raw_clock.base_cycles = tk->tkr_raw.xtime_nsec; 2219 vdata->raw_clock.offset = tk->tkr_raw.base; 2220 2221 vdata->wall_time_sec = tk->xtime_sec; 2222 2223 vdata->offs_boot = tk->offs_boot; 2224 2225 write_seqcount_end(&vdata->seq); 2226 } 2227 2228 static s64 get_kvmclock_base_ns(void) 2229 { 2230 /* Count up from boot time, but with the frequency of the raw clock. */ 2231 return ktime_to_ns(ktime_add(ktime_get_raw(), pvclock_gtod_data.offs_boot)); 2232 } 2233 #else 2234 static s64 get_kvmclock_base_ns(void) 2235 { 2236 /* Master clock not used, so we can just use CLOCK_BOOTTIME. */ 2237 return ktime_get_boottime_ns(); 2238 } 2239 #endif 2240 2241 static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock, int sec_hi_ofs) 2242 { 2243 int version; 2244 int r; 2245 struct pvclock_wall_clock wc; 2246 u32 wc_sec_hi; 2247 u64 wall_nsec; 2248 2249 if (!wall_clock) 2250 return; 2251 2252 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version)); 2253 if (r) 2254 return; 2255 2256 if (version & 1) 2257 ++version; /* first time write, random junk */ 2258 2259 ++version; 2260 2261 if (kvm_write_guest(kvm, wall_clock, &version, sizeof(version))) 2262 return; 2263 2264 /* 2265 * The guest calculates current wall clock time by adding 2266 * system time (updated by kvm_guest_time_update below) to the 2267 * wall clock specified here. We do the reverse here. 2268 */ 2269 wall_nsec = ktime_get_real_ns() - get_kvmclock_ns(kvm); 2270 2271 wc.nsec = do_div(wall_nsec, 1000000000); 2272 wc.sec = (u32)wall_nsec; /* overflow in 2106 guest time */ 2273 wc.version = version; 2274 2275 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc)); 2276 2277 if (sec_hi_ofs) { 2278 wc_sec_hi = wall_nsec >> 32; 2279 kvm_write_guest(kvm, wall_clock + sec_hi_ofs, 2280 &wc_sec_hi, sizeof(wc_sec_hi)); 2281 } 2282 2283 version++; 2284 kvm_write_guest(kvm, wall_clock, &version, sizeof(version)); 2285 } 2286 2287 static void kvm_write_system_time(struct kvm_vcpu *vcpu, gpa_t system_time, 2288 bool old_msr, bool host_initiated) 2289 { 2290 struct kvm_arch *ka = &vcpu->kvm->arch; 2291 2292 if (vcpu->vcpu_id == 0 && !host_initiated) { 2293 if (ka->boot_vcpu_runs_old_kvmclock != old_msr) 2294 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu); 2295 2296 ka->boot_vcpu_runs_old_kvmclock = old_msr; 2297 } 2298 2299 vcpu->arch.time = system_time; 2300 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu); 2301 2302 /* we verify if the enable bit is set... */ 2303 if (system_time & 1) { 2304 kvm_gfn_to_pfn_cache_init(vcpu->kvm, &vcpu->arch.pv_time, vcpu, 2305 KVM_HOST_USES_PFN, system_time & ~1ULL, 2306 sizeof(struct pvclock_vcpu_time_info)); 2307 } else { 2308 kvm_gfn_to_pfn_cache_destroy(vcpu->kvm, &vcpu->arch.pv_time); 2309 } 2310 2311 return; 2312 } 2313 2314 static uint32_t div_frac(uint32_t dividend, uint32_t divisor) 2315 { 2316 do_shl32_div32(dividend, divisor); 2317 return dividend; 2318 } 2319 2320 static void kvm_get_time_scale(uint64_t scaled_hz, uint64_t base_hz, 2321 s8 *pshift, u32 *pmultiplier) 2322 { 2323 uint64_t scaled64; 2324 int32_t shift = 0; 2325 uint64_t tps64; 2326 uint32_t tps32; 2327 2328 tps64 = base_hz; 2329 scaled64 = scaled_hz; 2330 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) { 2331 tps64 >>= 1; 2332 shift--; 2333 } 2334 2335 tps32 = (uint32_t)tps64; 2336 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) { 2337 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000) 2338 scaled64 >>= 1; 2339 else 2340 tps32 <<= 1; 2341 shift++; 2342 } 2343 2344 *pshift = shift; 2345 *pmultiplier = div_frac(scaled64, tps32); 2346 } 2347 2348 #ifdef CONFIG_X86_64 2349 static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0); 2350 #endif 2351 2352 static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz); 2353 static unsigned long max_tsc_khz; 2354 2355 static u32 adjust_tsc_khz(u32 khz, s32 ppm) 2356 { 2357 u64 v = (u64)khz * (1000000 + ppm); 2358 do_div(v, 1000000); 2359 return v; 2360 } 2361 2362 static void kvm_vcpu_write_tsc_multiplier(struct kvm_vcpu *vcpu, u64 l1_multiplier); 2363 2364 static int set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale) 2365 { 2366 u64 ratio; 2367 2368 /* Guest TSC same frequency as host TSC? */ 2369 if (!scale) { 2370 kvm_vcpu_write_tsc_multiplier(vcpu, kvm_caps.default_tsc_scaling_ratio); 2371 return 0; 2372 } 2373 2374 /* TSC scaling supported? */ 2375 if (!kvm_caps.has_tsc_control) { 2376 if (user_tsc_khz > tsc_khz) { 2377 vcpu->arch.tsc_catchup = 1; 2378 vcpu->arch.tsc_always_catchup = 1; 2379 return 0; 2380 } else { 2381 pr_warn_ratelimited("user requested TSC rate below hardware speed\n"); 2382 return -1; 2383 } 2384 } 2385 2386 /* TSC scaling required - calculate ratio */ 2387 ratio = mul_u64_u32_div(1ULL << kvm_caps.tsc_scaling_ratio_frac_bits, 2388 user_tsc_khz, tsc_khz); 2389 2390 if (ratio == 0 || ratio >= kvm_caps.max_tsc_scaling_ratio) { 2391 pr_warn_ratelimited("Invalid TSC scaling ratio - virtual-tsc-khz=%u\n", 2392 user_tsc_khz); 2393 return -1; 2394 } 2395 2396 kvm_vcpu_write_tsc_multiplier(vcpu, ratio); 2397 return 0; 2398 } 2399 2400 static int kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz) 2401 { 2402 u32 thresh_lo, thresh_hi; 2403 int use_scaling = 0; 2404 2405 /* tsc_khz can be zero if TSC calibration fails */ 2406 if (user_tsc_khz == 0) { 2407 /* set tsc_scaling_ratio to a safe value */ 2408 kvm_vcpu_write_tsc_multiplier(vcpu, kvm_caps.default_tsc_scaling_ratio); 2409 return -1; 2410 } 2411 2412 /* Compute a scale to convert nanoseconds in TSC cycles */ 2413 kvm_get_time_scale(user_tsc_khz * 1000LL, NSEC_PER_SEC, 2414 &vcpu->arch.virtual_tsc_shift, 2415 &vcpu->arch.virtual_tsc_mult); 2416 vcpu->arch.virtual_tsc_khz = user_tsc_khz; 2417 2418 /* 2419 * Compute the variation in TSC rate which is acceptable 2420 * within the range of tolerance and decide if the 2421 * rate being applied is within that bounds of the hardware 2422 * rate. If so, no scaling or compensation need be done. 2423 */ 2424 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm); 2425 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm); 2426 if (user_tsc_khz < thresh_lo || user_tsc_khz > thresh_hi) { 2427 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", user_tsc_khz, thresh_lo, thresh_hi); 2428 use_scaling = 1; 2429 } 2430 return set_tsc_khz(vcpu, user_tsc_khz, use_scaling); 2431 } 2432 2433 static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns) 2434 { 2435 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec, 2436 vcpu->arch.virtual_tsc_mult, 2437 vcpu->arch.virtual_tsc_shift); 2438 tsc += vcpu->arch.this_tsc_write; 2439 return tsc; 2440 } 2441 2442 #ifdef CONFIG_X86_64 2443 static inline int gtod_is_based_on_tsc(int mode) 2444 { 2445 return mode == VDSO_CLOCKMODE_TSC || mode == VDSO_CLOCKMODE_HVCLOCK; 2446 } 2447 #endif 2448 2449 static void kvm_track_tsc_matching(struct kvm_vcpu *vcpu) 2450 { 2451 #ifdef CONFIG_X86_64 2452 bool vcpus_matched; 2453 struct kvm_arch *ka = &vcpu->kvm->arch; 2454 struct pvclock_gtod_data *gtod = &pvclock_gtod_data; 2455 2456 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 == 2457 atomic_read(&vcpu->kvm->online_vcpus)); 2458 2459 /* 2460 * Once the masterclock is enabled, always perform request in 2461 * order to update it. 2462 * 2463 * In order to enable masterclock, the host clocksource must be TSC 2464 * and the vcpus need to have matched TSCs. When that happens, 2465 * perform request to enable masterclock. 2466 */ 2467 if (ka->use_master_clock || 2468 (gtod_is_based_on_tsc(gtod->clock.vclock_mode) && vcpus_matched)) 2469 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu); 2470 2471 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc, 2472 atomic_read(&vcpu->kvm->online_vcpus), 2473 ka->use_master_clock, gtod->clock.vclock_mode); 2474 #endif 2475 } 2476 2477 /* 2478 * Multiply tsc by a fixed point number represented by ratio. 2479 * 2480 * The most significant 64-N bits (mult) of ratio represent the 2481 * integral part of the fixed point number; the remaining N bits 2482 * (frac) represent the fractional part, ie. ratio represents a fixed 2483 * point number (mult + frac * 2^(-N)). 2484 * 2485 * N equals to kvm_caps.tsc_scaling_ratio_frac_bits. 2486 */ 2487 static inline u64 __scale_tsc(u64 ratio, u64 tsc) 2488 { 2489 return mul_u64_u64_shr(tsc, ratio, kvm_caps.tsc_scaling_ratio_frac_bits); 2490 } 2491 2492 u64 kvm_scale_tsc(u64 tsc, u64 ratio) 2493 { 2494 u64 _tsc = tsc; 2495 2496 if (ratio != kvm_caps.default_tsc_scaling_ratio) 2497 _tsc = __scale_tsc(ratio, tsc); 2498 2499 return _tsc; 2500 } 2501 EXPORT_SYMBOL_GPL(kvm_scale_tsc); 2502 2503 static u64 kvm_compute_l1_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc) 2504 { 2505 u64 tsc; 2506 2507 tsc = kvm_scale_tsc(rdtsc(), vcpu->arch.l1_tsc_scaling_ratio); 2508 2509 return target_tsc - tsc; 2510 } 2511 2512 u64 kvm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc) 2513 { 2514 return vcpu->arch.l1_tsc_offset + 2515 kvm_scale_tsc(host_tsc, vcpu->arch.l1_tsc_scaling_ratio); 2516 } 2517 EXPORT_SYMBOL_GPL(kvm_read_l1_tsc); 2518 2519 u64 kvm_calc_nested_tsc_offset(u64 l1_offset, u64 l2_offset, u64 l2_multiplier) 2520 { 2521 u64 nested_offset; 2522 2523 if (l2_multiplier == kvm_caps.default_tsc_scaling_ratio) 2524 nested_offset = l1_offset; 2525 else 2526 nested_offset = mul_s64_u64_shr((s64) l1_offset, l2_multiplier, 2527 kvm_caps.tsc_scaling_ratio_frac_bits); 2528 2529 nested_offset += l2_offset; 2530 return nested_offset; 2531 } 2532 EXPORT_SYMBOL_GPL(kvm_calc_nested_tsc_offset); 2533 2534 u64 kvm_calc_nested_tsc_multiplier(u64 l1_multiplier, u64 l2_multiplier) 2535 { 2536 if (l2_multiplier != kvm_caps.default_tsc_scaling_ratio) 2537 return mul_u64_u64_shr(l1_multiplier, l2_multiplier, 2538 kvm_caps.tsc_scaling_ratio_frac_bits); 2539 2540 return l1_multiplier; 2541 } 2542 EXPORT_SYMBOL_GPL(kvm_calc_nested_tsc_multiplier); 2543 2544 static void kvm_vcpu_write_tsc_offset(struct kvm_vcpu *vcpu, u64 l1_offset) 2545 { 2546 trace_kvm_write_tsc_offset(vcpu->vcpu_id, 2547 vcpu->arch.l1_tsc_offset, 2548 l1_offset); 2549 2550 vcpu->arch.l1_tsc_offset = l1_offset; 2551 2552 /* 2553 * If we are here because L1 chose not to trap WRMSR to TSC then 2554 * according to the spec this should set L1's TSC (as opposed to 2555 * setting L1's offset for L2). 2556 */ 2557 if (is_guest_mode(vcpu)) 2558 vcpu->arch.tsc_offset = kvm_calc_nested_tsc_offset( 2559 l1_offset, 2560 static_call(kvm_x86_get_l2_tsc_offset)(vcpu), 2561 static_call(kvm_x86_get_l2_tsc_multiplier)(vcpu)); 2562 else 2563 vcpu->arch.tsc_offset = l1_offset; 2564 2565 static_call(kvm_x86_write_tsc_offset)(vcpu, vcpu->arch.tsc_offset); 2566 } 2567 2568 static void kvm_vcpu_write_tsc_multiplier(struct kvm_vcpu *vcpu, u64 l1_multiplier) 2569 { 2570 vcpu->arch.l1_tsc_scaling_ratio = l1_multiplier; 2571 2572 /* Userspace is changing the multiplier while L2 is active */ 2573 if (is_guest_mode(vcpu)) 2574 vcpu->arch.tsc_scaling_ratio = kvm_calc_nested_tsc_multiplier( 2575 l1_multiplier, 2576 static_call(kvm_x86_get_l2_tsc_multiplier)(vcpu)); 2577 else 2578 vcpu->arch.tsc_scaling_ratio = l1_multiplier; 2579 2580 if (kvm_caps.has_tsc_control) 2581 static_call(kvm_x86_write_tsc_multiplier)( 2582 vcpu, vcpu->arch.tsc_scaling_ratio); 2583 } 2584 2585 static inline bool kvm_check_tsc_unstable(void) 2586 { 2587 #ifdef CONFIG_X86_64 2588 /* 2589 * TSC is marked unstable when we're running on Hyper-V, 2590 * 'TSC page' clocksource is good. 2591 */ 2592 if (pvclock_gtod_data.clock.vclock_mode == VDSO_CLOCKMODE_HVCLOCK) 2593 return false; 2594 #endif 2595 return check_tsc_unstable(); 2596 } 2597 2598 /* 2599 * Infers attempts to synchronize the guest's tsc from host writes. Sets the 2600 * offset for the vcpu and tracks the TSC matching generation that the vcpu 2601 * participates in. 2602 */ 2603 static void __kvm_synchronize_tsc(struct kvm_vcpu *vcpu, u64 offset, u64 tsc, 2604 u64 ns, bool matched) 2605 { 2606 struct kvm *kvm = vcpu->kvm; 2607 2608 lockdep_assert_held(&kvm->arch.tsc_write_lock); 2609 2610 /* 2611 * We also track th most recent recorded KHZ, write and time to 2612 * allow the matching interval to be extended at each write. 2613 */ 2614 kvm->arch.last_tsc_nsec = ns; 2615 kvm->arch.last_tsc_write = tsc; 2616 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz; 2617 kvm->arch.last_tsc_offset = offset; 2618 2619 vcpu->arch.last_guest_tsc = tsc; 2620 2621 kvm_vcpu_write_tsc_offset(vcpu, offset); 2622 2623 if (!matched) { 2624 /* 2625 * We split periods of matched TSC writes into generations. 2626 * For each generation, we track the original measured 2627 * nanosecond time, offset, and write, so if TSCs are in 2628 * sync, we can match exact offset, and if not, we can match 2629 * exact software computation in compute_guest_tsc() 2630 * 2631 * These values are tracked in kvm->arch.cur_xxx variables. 2632 */ 2633 kvm->arch.cur_tsc_generation++; 2634 kvm->arch.cur_tsc_nsec = ns; 2635 kvm->arch.cur_tsc_write = tsc; 2636 kvm->arch.cur_tsc_offset = offset; 2637 kvm->arch.nr_vcpus_matched_tsc = 0; 2638 } else if (vcpu->arch.this_tsc_generation != kvm->arch.cur_tsc_generation) { 2639 kvm->arch.nr_vcpus_matched_tsc++; 2640 } 2641 2642 /* Keep track of which generation this VCPU has synchronized to */ 2643 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation; 2644 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec; 2645 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write; 2646 2647 kvm_track_tsc_matching(vcpu); 2648 } 2649 2650 static void kvm_synchronize_tsc(struct kvm_vcpu *vcpu, u64 data) 2651 { 2652 struct kvm *kvm = vcpu->kvm; 2653 u64 offset, ns, elapsed; 2654 unsigned long flags; 2655 bool matched = false; 2656 bool synchronizing = false; 2657 2658 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags); 2659 offset = kvm_compute_l1_tsc_offset(vcpu, data); 2660 ns = get_kvmclock_base_ns(); 2661 elapsed = ns - kvm->arch.last_tsc_nsec; 2662 2663 if (vcpu->arch.virtual_tsc_khz) { 2664 if (data == 0) { 2665 /* 2666 * detection of vcpu initialization -- need to sync 2667 * with other vCPUs. This particularly helps to keep 2668 * kvm_clock stable after CPU hotplug 2669 */ 2670 synchronizing = true; 2671 } else { 2672 u64 tsc_exp = kvm->arch.last_tsc_write + 2673 nsec_to_cycles(vcpu, elapsed); 2674 u64 tsc_hz = vcpu->arch.virtual_tsc_khz * 1000LL; 2675 /* 2676 * Special case: TSC write with a small delta (1 second) 2677 * of virtual cycle time against real time is 2678 * interpreted as an attempt to synchronize the CPU. 2679 */ 2680 synchronizing = data < tsc_exp + tsc_hz && 2681 data + tsc_hz > tsc_exp; 2682 } 2683 } 2684 2685 /* 2686 * For a reliable TSC, we can match TSC offsets, and for an unstable 2687 * TSC, we add elapsed time in this computation. We could let the 2688 * compensation code attempt to catch up if we fall behind, but 2689 * it's better to try to match offsets from the beginning. 2690 */ 2691 if (synchronizing && 2692 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) { 2693 if (!kvm_check_tsc_unstable()) { 2694 offset = kvm->arch.cur_tsc_offset; 2695 } else { 2696 u64 delta = nsec_to_cycles(vcpu, elapsed); 2697 data += delta; 2698 offset = kvm_compute_l1_tsc_offset(vcpu, data); 2699 } 2700 matched = true; 2701 } 2702 2703 __kvm_synchronize_tsc(vcpu, offset, data, ns, matched); 2704 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags); 2705 } 2706 2707 static inline void adjust_tsc_offset_guest(struct kvm_vcpu *vcpu, 2708 s64 adjustment) 2709 { 2710 u64 tsc_offset = vcpu->arch.l1_tsc_offset; 2711 kvm_vcpu_write_tsc_offset(vcpu, tsc_offset + adjustment); 2712 } 2713 2714 static inline void adjust_tsc_offset_host(struct kvm_vcpu *vcpu, s64 adjustment) 2715 { 2716 if (vcpu->arch.l1_tsc_scaling_ratio != kvm_caps.default_tsc_scaling_ratio) 2717 WARN_ON(adjustment < 0); 2718 adjustment = kvm_scale_tsc((u64) adjustment, 2719 vcpu->arch.l1_tsc_scaling_ratio); 2720 adjust_tsc_offset_guest(vcpu, adjustment); 2721 } 2722 2723 #ifdef CONFIG_X86_64 2724 2725 static u64 read_tsc(void) 2726 { 2727 u64 ret = (u64)rdtsc_ordered(); 2728 u64 last = pvclock_gtod_data.clock.cycle_last; 2729 2730 if (likely(ret >= last)) 2731 return ret; 2732 2733 /* 2734 * GCC likes to generate cmov here, but this branch is extremely 2735 * predictable (it's just a function of time and the likely is 2736 * very likely) and there's a data dependence, so force GCC 2737 * to generate a branch instead. I don't barrier() because 2738 * we don't actually need a barrier, and if this function 2739 * ever gets inlined it will generate worse code. 2740 */ 2741 asm volatile (""); 2742 return last; 2743 } 2744 2745 static inline u64 vgettsc(struct pvclock_clock *clock, u64 *tsc_timestamp, 2746 int *mode) 2747 { 2748 long v; 2749 u64 tsc_pg_val; 2750 2751 switch (clock->vclock_mode) { 2752 case VDSO_CLOCKMODE_HVCLOCK: 2753 tsc_pg_val = hv_read_tsc_page_tsc(hv_get_tsc_page(), 2754 tsc_timestamp); 2755 if (tsc_pg_val != U64_MAX) { 2756 /* TSC page valid */ 2757 *mode = VDSO_CLOCKMODE_HVCLOCK; 2758 v = (tsc_pg_val - clock->cycle_last) & 2759 clock->mask; 2760 } else { 2761 /* TSC page invalid */ 2762 *mode = VDSO_CLOCKMODE_NONE; 2763 } 2764 break; 2765 case VDSO_CLOCKMODE_TSC: 2766 *mode = VDSO_CLOCKMODE_TSC; 2767 *tsc_timestamp = read_tsc(); 2768 v = (*tsc_timestamp - clock->cycle_last) & 2769 clock->mask; 2770 break; 2771 default: 2772 *mode = VDSO_CLOCKMODE_NONE; 2773 } 2774 2775 if (*mode == VDSO_CLOCKMODE_NONE) 2776 *tsc_timestamp = v = 0; 2777 2778 return v * clock->mult; 2779 } 2780 2781 static int do_monotonic_raw(s64 *t, u64 *tsc_timestamp) 2782 { 2783 struct pvclock_gtod_data *gtod = &pvclock_gtod_data; 2784 unsigned long seq; 2785 int mode; 2786 u64 ns; 2787 2788 do { 2789 seq = read_seqcount_begin(>od->seq); 2790 ns = gtod->raw_clock.base_cycles; 2791 ns += vgettsc(>od->raw_clock, tsc_timestamp, &mode); 2792 ns >>= gtod->raw_clock.shift; 2793 ns += ktime_to_ns(ktime_add(gtod->raw_clock.offset, gtod->offs_boot)); 2794 } while (unlikely(read_seqcount_retry(>od->seq, seq))); 2795 *t = ns; 2796 2797 return mode; 2798 } 2799 2800 static int do_realtime(struct timespec64 *ts, u64 *tsc_timestamp) 2801 { 2802 struct pvclock_gtod_data *gtod = &pvclock_gtod_data; 2803 unsigned long seq; 2804 int mode; 2805 u64 ns; 2806 2807 do { 2808 seq = read_seqcount_begin(>od->seq); 2809 ts->tv_sec = gtod->wall_time_sec; 2810 ns = gtod->clock.base_cycles; 2811 ns += vgettsc(>od->clock, tsc_timestamp, &mode); 2812 ns >>= gtod->clock.shift; 2813 } while (unlikely(read_seqcount_retry(>od->seq, seq))); 2814 2815 ts->tv_sec += __iter_div_u64_rem(ns, NSEC_PER_SEC, &ns); 2816 ts->tv_nsec = ns; 2817 2818 return mode; 2819 } 2820 2821 /* returns true if host is using TSC based clocksource */ 2822 static bool kvm_get_time_and_clockread(s64 *kernel_ns, u64 *tsc_timestamp) 2823 { 2824 /* checked again under seqlock below */ 2825 if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode)) 2826 return false; 2827 2828 return gtod_is_based_on_tsc(do_monotonic_raw(kernel_ns, 2829 tsc_timestamp)); 2830 } 2831 2832 /* returns true if host is using TSC based clocksource */ 2833 static bool kvm_get_walltime_and_clockread(struct timespec64 *ts, 2834 u64 *tsc_timestamp) 2835 { 2836 /* checked again under seqlock below */ 2837 if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode)) 2838 return false; 2839 2840 return gtod_is_based_on_tsc(do_realtime(ts, tsc_timestamp)); 2841 } 2842 #endif 2843 2844 /* 2845 * 2846 * Assuming a stable TSC across physical CPUS, and a stable TSC 2847 * across virtual CPUs, the following condition is possible. 2848 * Each numbered line represents an event visible to both 2849 * CPUs at the next numbered event. 2850 * 2851 * "timespecX" represents host monotonic time. "tscX" represents 2852 * RDTSC value. 2853 * 2854 * VCPU0 on CPU0 | VCPU1 on CPU1 2855 * 2856 * 1. read timespec0,tsc0 2857 * 2. | timespec1 = timespec0 + N 2858 * | tsc1 = tsc0 + M 2859 * 3. transition to guest | transition to guest 2860 * 4. ret0 = timespec0 + (rdtsc - tsc0) | 2861 * 5. | ret1 = timespec1 + (rdtsc - tsc1) 2862 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M)) 2863 * 2864 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity: 2865 * 2866 * - ret0 < ret1 2867 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M)) 2868 * ... 2869 * - 0 < N - M => M < N 2870 * 2871 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not 2872 * always the case (the difference between two distinct xtime instances 2873 * might be smaller then the difference between corresponding TSC reads, 2874 * when updating guest vcpus pvclock areas). 2875 * 2876 * To avoid that problem, do not allow visibility of distinct 2877 * system_timestamp/tsc_timestamp values simultaneously: use a master 2878 * copy of host monotonic time values. Update that master copy 2879 * in lockstep. 2880 * 2881 * Rely on synchronization of host TSCs and guest TSCs for monotonicity. 2882 * 2883 */ 2884 2885 static void pvclock_update_vm_gtod_copy(struct kvm *kvm) 2886 { 2887 #ifdef CONFIG_X86_64 2888 struct kvm_arch *ka = &kvm->arch; 2889 int vclock_mode; 2890 bool host_tsc_clocksource, vcpus_matched; 2891 2892 lockdep_assert_held(&kvm->arch.tsc_write_lock); 2893 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 == 2894 atomic_read(&kvm->online_vcpus)); 2895 2896 /* 2897 * If the host uses TSC clock, then passthrough TSC as stable 2898 * to the guest. 2899 */ 2900 host_tsc_clocksource = kvm_get_time_and_clockread( 2901 &ka->master_kernel_ns, 2902 &ka->master_cycle_now); 2903 2904 ka->use_master_clock = host_tsc_clocksource && vcpus_matched 2905 && !ka->backwards_tsc_observed 2906 && !ka->boot_vcpu_runs_old_kvmclock; 2907 2908 if (ka->use_master_clock) 2909 atomic_set(&kvm_guest_has_master_clock, 1); 2910 2911 vclock_mode = pvclock_gtod_data.clock.vclock_mode; 2912 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode, 2913 vcpus_matched); 2914 #endif 2915 } 2916 2917 static void kvm_make_mclock_inprogress_request(struct kvm *kvm) 2918 { 2919 kvm_make_all_cpus_request(kvm, KVM_REQ_MCLOCK_INPROGRESS); 2920 } 2921 2922 static void __kvm_start_pvclock_update(struct kvm *kvm) 2923 { 2924 raw_spin_lock_irq(&kvm->arch.tsc_write_lock); 2925 write_seqcount_begin(&kvm->arch.pvclock_sc); 2926 } 2927 2928 static void kvm_start_pvclock_update(struct kvm *kvm) 2929 { 2930 kvm_make_mclock_inprogress_request(kvm); 2931 2932 /* no guest entries from this point */ 2933 __kvm_start_pvclock_update(kvm); 2934 } 2935 2936 static void kvm_end_pvclock_update(struct kvm *kvm) 2937 { 2938 struct kvm_arch *ka = &kvm->arch; 2939 struct kvm_vcpu *vcpu; 2940 unsigned long i; 2941 2942 write_seqcount_end(&ka->pvclock_sc); 2943 raw_spin_unlock_irq(&ka->tsc_write_lock); 2944 kvm_for_each_vcpu(i, vcpu, kvm) 2945 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 2946 2947 /* guest entries allowed */ 2948 kvm_for_each_vcpu(i, vcpu, kvm) 2949 kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu); 2950 } 2951 2952 static void kvm_update_masterclock(struct kvm *kvm) 2953 { 2954 kvm_hv_request_tsc_page_update(kvm); 2955 kvm_start_pvclock_update(kvm); 2956 pvclock_update_vm_gtod_copy(kvm); 2957 kvm_end_pvclock_update(kvm); 2958 } 2959 2960 /* Called within read_seqcount_begin/retry for kvm->pvclock_sc. */ 2961 static void __get_kvmclock(struct kvm *kvm, struct kvm_clock_data *data) 2962 { 2963 struct kvm_arch *ka = &kvm->arch; 2964 struct pvclock_vcpu_time_info hv_clock; 2965 2966 /* both __this_cpu_read() and rdtsc() should be on the same cpu */ 2967 get_cpu(); 2968 2969 data->flags = 0; 2970 if (ka->use_master_clock && __this_cpu_read(cpu_tsc_khz)) { 2971 #ifdef CONFIG_X86_64 2972 struct timespec64 ts; 2973 2974 if (kvm_get_walltime_and_clockread(&ts, &data->host_tsc)) { 2975 data->realtime = ts.tv_nsec + NSEC_PER_SEC * ts.tv_sec; 2976 data->flags |= KVM_CLOCK_REALTIME | KVM_CLOCK_HOST_TSC; 2977 } else 2978 #endif 2979 data->host_tsc = rdtsc(); 2980 2981 data->flags |= KVM_CLOCK_TSC_STABLE; 2982 hv_clock.tsc_timestamp = ka->master_cycle_now; 2983 hv_clock.system_time = ka->master_kernel_ns + ka->kvmclock_offset; 2984 kvm_get_time_scale(NSEC_PER_SEC, __this_cpu_read(cpu_tsc_khz) * 1000LL, 2985 &hv_clock.tsc_shift, 2986 &hv_clock.tsc_to_system_mul); 2987 data->clock = __pvclock_read_cycles(&hv_clock, data->host_tsc); 2988 } else { 2989 data->clock = get_kvmclock_base_ns() + ka->kvmclock_offset; 2990 } 2991 2992 put_cpu(); 2993 } 2994 2995 static void get_kvmclock(struct kvm *kvm, struct kvm_clock_data *data) 2996 { 2997 struct kvm_arch *ka = &kvm->arch; 2998 unsigned seq; 2999 3000 do { 3001 seq = read_seqcount_begin(&ka->pvclock_sc); 3002 __get_kvmclock(kvm, data); 3003 } while (read_seqcount_retry(&ka->pvclock_sc, seq)); 3004 } 3005 3006 u64 get_kvmclock_ns(struct kvm *kvm) 3007 { 3008 struct kvm_clock_data data; 3009 3010 get_kvmclock(kvm, &data); 3011 return data.clock; 3012 } 3013 3014 static void kvm_setup_guest_pvclock(struct kvm_vcpu *v, 3015 struct gfn_to_pfn_cache *gpc, 3016 unsigned int offset) 3017 { 3018 struct kvm_vcpu_arch *vcpu = &v->arch; 3019 struct pvclock_vcpu_time_info *guest_hv_clock; 3020 unsigned long flags; 3021 3022 read_lock_irqsave(&gpc->lock, flags); 3023 while (!kvm_gfn_to_pfn_cache_check(v->kvm, gpc, gpc->gpa, 3024 offset + sizeof(*guest_hv_clock))) { 3025 read_unlock_irqrestore(&gpc->lock, flags); 3026 3027 if (kvm_gfn_to_pfn_cache_refresh(v->kvm, gpc, gpc->gpa, 3028 offset + sizeof(*guest_hv_clock))) 3029 return; 3030 3031 read_lock_irqsave(&gpc->lock, flags); 3032 } 3033 3034 guest_hv_clock = (void *)(gpc->khva + offset); 3035 3036 /* 3037 * This VCPU is paused, but it's legal for a guest to read another 3038 * VCPU's kvmclock, so we really have to follow the specification where 3039 * it says that version is odd if data is being modified, and even after 3040 * it is consistent. 3041 */ 3042 3043 guest_hv_clock->version = vcpu->hv_clock.version = (guest_hv_clock->version + 1) | 1; 3044 smp_wmb(); 3045 3046 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */ 3047 vcpu->hv_clock.flags |= (guest_hv_clock->flags & PVCLOCK_GUEST_STOPPED); 3048 3049 if (vcpu->pvclock_set_guest_stopped_request) { 3050 vcpu->hv_clock.flags |= PVCLOCK_GUEST_STOPPED; 3051 vcpu->pvclock_set_guest_stopped_request = false; 3052 } 3053 3054 memcpy(guest_hv_clock, &vcpu->hv_clock, sizeof(*guest_hv_clock)); 3055 smp_wmb(); 3056 3057 guest_hv_clock->version = ++vcpu->hv_clock.version; 3058 3059 mark_page_dirty_in_slot(v->kvm, gpc->memslot, gpc->gpa >> PAGE_SHIFT); 3060 read_unlock_irqrestore(&gpc->lock, flags); 3061 3062 trace_kvm_pvclock_update(v->vcpu_id, &vcpu->hv_clock); 3063 } 3064 3065 static int kvm_guest_time_update(struct kvm_vcpu *v) 3066 { 3067 unsigned long flags, tgt_tsc_khz; 3068 unsigned seq; 3069 struct kvm_vcpu_arch *vcpu = &v->arch; 3070 struct kvm_arch *ka = &v->kvm->arch; 3071 s64 kernel_ns; 3072 u64 tsc_timestamp, host_tsc; 3073 u8 pvclock_flags; 3074 bool use_master_clock; 3075 3076 kernel_ns = 0; 3077 host_tsc = 0; 3078 3079 /* 3080 * If the host uses TSC clock, then passthrough TSC as stable 3081 * to the guest. 3082 */ 3083 do { 3084 seq = read_seqcount_begin(&ka->pvclock_sc); 3085 use_master_clock = ka->use_master_clock; 3086 if (use_master_clock) { 3087 host_tsc = ka->master_cycle_now; 3088 kernel_ns = ka->master_kernel_ns; 3089 } 3090 } while (read_seqcount_retry(&ka->pvclock_sc, seq)); 3091 3092 /* Keep irq disabled to prevent changes to the clock */ 3093 local_irq_save(flags); 3094 tgt_tsc_khz = __this_cpu_read(cpu_tsc_khz); 3095 if (unlikely(tgt_tsc_khz == 0)) { 3096 local_irq_restore(flags); 3097 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v); 3098 return 1; 3099 } 3100 if (!use_master_clock) { 3101 host_tsc = rdtsc(); 3102 kernel_ns = get_kvmclock_base_ns(); 3103 } 3104 3105 tsc_timestamp = kvm_read_l1_tsc(v, host_tsc); 3106 3107 /* 3108 * We may have to catch up the TSC to match elapsed wall clock 3109 * time for two reasons, even if kvmclock is used. 3110 * 1) CPU could have been running below the maximum TSC rate 3111 * 2) Broken TSC compensation resets the base at each VCPU 3112 * entry to avoid unknown leaps of TSC even when running 3113 * again on the same CPU. This may cause apparent elapsed 3114 * time to disappear, and the guest to stand still or run 3115 * very slowly. 3116 */ 3117 if (vcpu->tsc_catchup) { 3118 u64 tsc = compute_guest_tsc(v, kernel_ns); 3119 if (tsc > tsc_timestamp) { 3120 adjust_tsc_offset_guest(v, tsc - tsc_timestamp); 3121 tsc_timestamp = tsc; 3122 } 3123 } 3124 3125 local_irq_restore(flags); 3126 3127 /* With all the info we got, fill in the values */ 3128 3129 if (kvm_caps.has_tsc_control) 3130 tgt_tsc_khz = kvm_scale_tsc(tgt_tsc_khz, 3131 v->arch.l1_tsc_scaling_ratio); 3132 3133 if (unlikely(vcpu->hw_tsc_khz != tgt_tsc_khz)) { 3134 kvm_get_time_scale(NSEC_PER_SEC, tgt_tsc_khz * 1000LL, 3135 &vcpu->hv_clock.tsc_shift, 3136 &vcpu->hv_clock.tsc_to_system_mul); 3137 vcpu->hw_tsc_khz = tgt_tsc_khz; 3138 } 3139 3140 vcpu->hv_clock.tsc_timestamp = tsc_timestamp; 3141 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset; 3142 vcpu->last_guest_tsc = tsc_timestamp; 3143 3144 /* If the host uses TSC clocksource, then it is stable */ 3145 pvclock_flags = 0; 3146 if (use_master_clock) 3147 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT; 3148 3149 vcpu->hv_clock.flags = pvclock_flags; 3150 3151 if (vcpu->pv_time.active) 3152 kvm_setup_guest_pvclock(v, &vcpu->pv_time, 0); 3153 if (vcpu->xen.vcpu_info_cache.active) 3154 kvm_setup_guest_pvclock(v, &vcpu->xen.vcpu_info_cache, 3155 offsetof(struct compat_vcpu_info, time)); 3156 if (vcpu->xen.vcpu_time_info_cache.active) 3157 kvm_setup_guest_pvclock(v, &vcpu->xen.vcpu_time_info_cache, 0); 3158 kvm_hv_setup_tsc_page(v->kvm, &vcpu->hv_clock); 3159 return 0; 3160 } 3161 3162 /* 3163 * kvmclock updates which are isolated to a given vcpu, such as 3164 * vcpu->cpu migration, should not allow system_timestamp from 3165 * the rest of the vcpus to remain static. Otherwise ntp frequency 3166 * correction applies to one vcpu's system_timestamp but not 3167 * the others. 3168 * 3169 * So in those cases, request a kvmclock update for all vcpus. 3170 * We need to rate-limit these requests though, as they can 3171 * considerably slow guests that have a large number of vcpus. 3172 * The time for a remote vcpu to update its kvmclock is bound 3173 * by the delay we use to rate-limit the updates. 3174 */ 3175 3176 #define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100) 3177 3178 static void kvmclock_update_fn(struct work_struct *work) 3179 { 3180 unsigned long i; 3181 struct delayed_work *dwork = to_delayed_work(work); 3182 struct kvm_arch *ka = container_of(dwork, struct kvm_arch, 3183 kvmclock_update_work); 3184 struct kvm *kvm = container_of(ka, struct kvm, arch); 3185 struct kvm_vcpu *vcpu; 3186 3187 kvm_for_each_vcpu(i, vcpu, kvm) { 3188 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 3189 kvm_vcpu_kick(vcpu); 3190 } 3191 } 3192 3193 static void kvm_gen_kvmclock_update(struct kvm_vcpu *v) 3194 { 3195 struct kvm *kvm = v->kvm; 3196 3197 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v); 3198 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 3199 KVMCLOCK_UPDATE_DELAY); 3200 } 3201 3202 #define KVMCLOCK_SYNC_PERIOD (300 * HZ) 3203 3204 static void kvmclock_sync_fn(struct work_struct *work) 3205 { 3206 struct delayed_work *dwork = to_delayed_work(work); 3207 struct kvm_arch *ka = container_of(dwork, struct kvm_arch, 3208 kvmclock_sync_work); 3209 struct kvm *kvm = container_of(ka, struct kvm, arch); 3210 3211 if (!kvmclock_periodic_sync) 3212 return; 3213 3214 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0); 3215 schedule_delayed_work(&kvm->arch.kvmclock_sync_work, 3216 KVMCLOCK_SYNC_PERIOD); 3217 } 3218 3219 /* These helpers are safe iff @msr is known to be an MCx bank MSR. */ 3220 static bool is_mci_control_msr(u32 msr) 3221 { 3222 return (msr & 3) == 0; 3223 } 3224 static bool is_mci_status_msr(u32 msr) 3225 { 3226 return (msr & 3) == 1; 3227 } 3228 3229 /* 3230 * On AMD, HWCR[McStatusWrEn] controls whether setting MCi_STATUS results in #GP. 3231 */ 3232 static bool can_set_mci_status(struct kvm_vcpu *vcpu) 3233 { 3234 /* McStatusWrEn enabled? */ 3235 if (guest_cpuid_is_amd_or_hygon(vcpu)) 3236 return !!(vcpu->arch.msr_hwcr & BIT_ULL(18)); 3237 3238 return false; 3239 } 3240 3241 static int set_msr_mce(struct kvm_vcpu *vcpu, struct msr_data *msr_info) 3242 { 3243 u64 mcg_cap = vcpu->arch.mcg_cap; 3244 unsigned bank_num = mcg_cap & 0xff; 3245 u32 msr = msr_info->index; 3246 u64 data = msr_info->data; 3247 u32 offset, last_msr; 3248 3249 switch (msr) { 3250 case MSR_IA32_MCG_STATUS: 3251 vcpu->arch.mcg_status = data; 3252 break; 3253 case MSR_IA32_MCG_CTL: 3254 if (!(mcg_cap & MCG_CTL_P) && 3255 (data || !msr_info->host_initiated)) 3256 return 1; 3257 if (data != 0 && data != ~(u64)0) 3258 return 1; 3259 vcpu->arch.mcg_ctl = data; 3260 break; 3261 case MSR_IA32_MC0_CTL2 ... MSR_IA32_MCx_CTL2(KVM_MAX_MCE_BANKS) - 1: 3262 last_msr = MSR_IA32_MCx_CTL2(bank_num) - 1; 3263 if (msr > last_msr) 3264 return 1; 3265 3266 if (!(mcg_cap & MCG_CMCI_P) && (data || !msr_info->host_initiated)) 3267 return 1; 3268 /* An attempt to write a 1 to a reserved bit raises #GP */ 3269 if (data & ~(MCI_CTL2_CMCI_EN | MCI_CTL2_CMCI_THRESHOLD_MASK)) 3270 return 1; 3271 offset = array_index_nospec(msr - MSR_IA32_MC0_CTL2, 3272 last_msr + 1 - MSR_IA32_MC0_CTL2); 3273 vcpu->arch.mci_ctl2_banks[offset] = data; 3274 break; 3275 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1: 3276 last_msr = MSR_IA32_MCx_CTL(bank_num) - 1; 3277 if (msr > last_msr) 3278 return 1; 3279 3280 /* 3281 * Only 0 or all 1s can be written to IA32_MCi_CTL, all other 3282 * values are architecturally undefined. But, some Linux 3283 * kernels clear bit 10 in bank 4 to workaround a BIOS/GART TLB 3284 * issue on AMD K8s, allow bit 10 to be clear when setting all 3285 * other bits in order to avoid an uncaught #GP in the guest. 3286 * 3287 * UNIXWARE clears bit 0 of MC1_CTL to ignore correctable, 3288 * single-bit ECC data errors. 3289 */ 3290 if (is_mci_control_msr(msr) && 3291 data != 0 && (data | (1 << 10) | 1) != ~(u64)0) 3292 return 1; 3293 3294 /* 3295 * All CPUs allow writing 0 to MCi_STATUS MSRs to clear the MSR. 3296 * AMD-based CPUs allow non-zero values, but if and only if 3297 * HWCR[McStatusWrEn] is set. 3298 */ 3299 if (!msr_info->host_initiated && is_mci_status_msr(msr) && 3300 data != 0 && !can_set_mci_status(vcpu)) 3301 return 1; 3302 3303 offset = array_index_nospec(msr - MSR_IA32_MC0_CTL, 3304 last_msr + 1 - MSR_IA32_MC0_CTL); 3305 vcpu->arch.mce_banks[offset] = data; 3306 break; 3307 default: 3308 return 1; 3309 } 3310 return 0; 3311 } 3312 3313 static inline bool kvm_pv_async_pf_enabled(struct kvm_vcpu *vcpu) 3314 { 3315 u64 mask = KVM_ASYNC_PF_ENABLED | KVM_ASYNC_PF_DELIVERY_AS_INT; 3316 3317 return (vcpu->arch.apf.msr_en_val & mask) == mask; 3318 } 3319 3320 static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data) 3321 { 3322 gpa_t gpa = data & ~0x3f; 3323 3324 /* Bits 4:5 are reserved, Should be zero */ 3325 if (data & 0x30) 3326 return 1; 3327 3328 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_VMEXIT) && 3329 (data & KVM_ASYNC_PF_DELIVERY_AS_PF_VMEXIT)) 3330 return 1; 3331 3332 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_INT) && 3333 (data & KVM_ASYNC_PF_DELIVERY_AS_INT)) 3334 return 1; 3335 3336 if (!lapic_in_kernel(vcpu)) 3337 return data ? 1 : 0; 3338 3339 vcpu->arch.apf.msr_en_val = data; 3340 3341 if (!kvm_pv_async_pf_enabled(vcpu)) { 3342 kvm_clear_async_pf_completion_queue(vcpu); 3343 kvm_async_pf_hash_reset(vcpu); 3344 return 0; 3345 } 3346 3347 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa, 3348 sizeof(u64))) 3349 return 1; 3350 3351 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS); 3352 vcpu->arch.apf.delivery_as_pf_vmexit = data & KVM_ASYNC_PF_DELIVERY_AS_PF_VMEXIT; 3353 3354 kvm_async_pf_wakeup_all(vcpu); 3355 3356 return 0; 3357 } 3358 3359 static int kvm_pv_enable_async_pf_int(struct kvm_vcpu *vcpu, u64 data) 3360 { 3361 /* Bits 8-63 are reserved */ 3362 if (data >> 8) 3363 return 1; 3364 3365 if (!lapic_in_kernel(vcpu)) 3366 return 1; 3367 3368 vcpu->arch.apf.msr_int_val = data; 3369 3370 vcpu->arch.apf.vec = data & KVM_ASYNC_PF_VEC_MASK; 3371 3372 return 0; 3373 } 3374 3375 static void kvmclock_reset(struct kvm_vcpu *vcpu) 3376 { 3377 kvm_gfn_to_pfn_cache_destroy(vcpu->kvm, &vcpu->arch.pv_time); 3378 vcpu->arch.time = 0; 3379 } 3380 3381 static void kvm_vcpu_flush_tlb_all(struct kvm_vcpu *vcpu) 3382 { 3383 ++vcpu->stat.tlb_flush; 3384 static_call(kvm_x86_flush_tlb_all)(vcpu); 3385 } 3386 3387 static void kvm_vcpu_flush_tlb_guest(struct kvm_vcpu *vcpu) 3388 { 3389 ++vcpu->stat.tlb_flush; 3390 3391 if (!tdp_enabled) { 3392 /* 3393 * A TLB flush on behalf of the guest is equivalent to 3394 * INVPCID(all), toggling CR4.PGE, etc., which requires 3395 * a forced sync of the shadow page tables. Ensure all the 3396 * roots are synced and the guest TLB in hardware is clean. 3397 */ 3398 kvm_mmu_sync_roots(vcpu); 3399 kvm_mmu_sync_prev_roots(vcpu); 3400 } 3401 3402 static_call(kvm_x86_flush_tlb_guest)(vcpu); 3403 } 3404 3405 3406 static inline void kvm_vcpu_flush_tlb_current(struct kvm_vcpu *vcpu) 3407 { 3408 ++vcpu->stat.tlb_flush; 3409 static_call(kvm_x86_flush_tlb_current)(vcpu); 3410 } 3411 3412 /* 3413 * Service "local" TLB flush requests, which are specific to the current MMU 3414 * context. In addition to the generic event handling in vcpu_enter_guest(), 3415 * TLB flushes that are targeted at an MMU context also need to be serviced 3416 * prior before nested VM-Enter/VM-Exit. 3417 */ 3418 void kvm_service_local_tlb_flush_requests(struct kvm_vcpu *vcpu) 3419 { 3420 if (kvm_check_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu)) 3421 kvm_vcpu_flush_tlb_current(vcpu); 3422 3423 if (kvm_check_request(KVM_REQ_TLB_FLUSH_GUEST, vcpu)) 3424 kvm_vcpu_flush_tlb_guest(vcpu); 3425 } 3426 EXPORT_SYMBOL_GPL(kvm_service_local_tlb_flush_requests); 3427 3428 static void record_steal_time(struct kvm_vcpu *vcpu) 3429 { 3430 struct gfn_to_hva_cache *ghc = &vcpu->arch.st.cache; 3431 struct kvm_steal_time __user *st; 3432 struct kvm_memslots *slots; 3433 gpa_t gpa = vcpu->arch.st.msr_val & KVM_STEAL_VALID_BITS; 3434 u64 steal; 3435 u32 version; 3436 3437 if (kvm_xen_msr_enabled(vcpu->kvm)) { 3438 kvm_xen_runstate_set_running(vcpu); 3439 return; 3440 } 3441 3442 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED)) 3443 return; 3444 3445 if (WARN_ON_ONCE(current->mm != vcpu->kvm->mm)) 3446 return; 3447 3448 slots = kvm_memslots(vcpu->kvm); 3449 3450 if (unlikely(slots->generation != ghc->generation || 3451 gpa != ghc->gpa || 3452 kvm_is_error_hva(ghc->hva) || !ghc->memslot)) { 3453 /* We rely on the fact that it fits in a single page. */ 3454 BUILD_BUG_ON((sizeof(*st) - 1) & KVM_STEAL_VALID_BITS); 3455 3456 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, ghc, gpa, sizeof(*st)) || 3457 kvm_is_error_hva(ghc->hva) || !ghc->memslot) 3458 return; 3459 } 3460 3461 st = (struct kvm_steal_time __user *)ghc->hva; 3462 /* 3463 * Doing a TLB flush here, on the guest's behalf, can avoid 3464 * expensive IPIs. 3465 */ 3466 if (guest_pv_has(vcpu, KVM_FEATURE_PV_TLB_FLUSH)) { 3467 u8 st_preempted = 0; 3468 int err = -EFAULT; 3469 3470 if (!user_access_begin(st, sizeof(*st))) 3471 return; 3472 3473 asm volatile("1: xchgb %0, %2\n" 3474 "xor %1, %1\n" 3475 "2:\n" 3476 _ASM_EXTABLE_UA(1b, 2b) 3477 : "+q" (st_preempted), 3478 "+&r" (err), 3479 "+m" (st->preempted)); 3480 if (err) 3481 goto out; 3482 3483 user_access_end(); 3484 3485 vcpu->arch.st.preempted = 0; 3486 3487 trace_kvm_pv_tlb_flush(vcpu->vcpu_id, 3488 st_preempted & KVM_VCPU_FLUSH_TLB); 3489 if (st_preempted & KVM_VCPU_FLUSH_TLB) 3490 kvm_vcpu_flush_tlb_guest(vcpu); 3491 3492 if (!user_access_begin(st, sizeof(*st))) 3493 goto dirty; 3494 } else { 3495 if (!user_access_begin(st, sizeof(*st))) 3496 return; 3497 3498 unsafe_put_user(0, &st->preempted, out); 3499 vcpu->arch.st.preempted = 0; 3500 } 3501 3502 unsafe_get_user(version, &st->version, out); 3503 if (version & 1) 3504 version += 1; /* first time write, random junk */ 3505 3506 version += 1; 3507 unsafe_put_user(version, &st->version, out); 3508 3509 smp_wmb(); 3510 3511 unsafe_get_user(steal, &st->steal, out); 3512 steal += current->sched_info.run_delay - 3513 vcpu->arch.st.last_steal; 3514 vcpu->arch.st.last_steal = current->sched_info.run_delay; 3515 unsafe_put_user(steal, &st->steal, out); 3516 3517 version += 1; 3518 unsafe_put_user(version, &st->version, out); 3519 3520 out: 3521 user_access_end(); 3522 dirty: 3523 mark_page_dirty_in_slot(vcpu->kvm, ghc->memslot, gpa_to_gfn(ghc->gpa)); 3524 } 3525 3526 int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info) 3527 { 3528 bool pr = false; 3529 u32 msr = msr_info->index; 3530 u64 data = msr_info->data; 3531 3532 if (msr && msr == vcpu->kvm->arch.xen_hvm_config.msr) 3533 return kvm_xen_write_hypercall_page(vcpu, data); 3534 3535 switch (msr) { 3536 case MSR_AMD64_NB_CFG: 3537 case MSR_IA32_UCODE_WRITE: 3538 case MSR_VM_HSAVE_PA: 3539 case MSR_AMD64_PATCH_LOADER: 3540 case MSR_AMD64_BU_CFG2: 3541 case MSR_AMD64_DC_CFG: 3542 case MSR_F15H_EX_CFG: 3543 break; 3544 3545 case MSR_IA32_UCODE_REV: 3546 if (msr_info->host_initiated) 3547 vcpu->arch.microcode_version = data; 3548 break; 3549 case MSR_IA32_ARCH_CAPABILITIES: 3550 if (!msr_info->host_initiated) 3551 return 1; 3552 vcpu->arch.arch_capabilities = data; 3553 break; 3554 case MSR_IA32_PERF_CAPABILITIES: { 3555 struct kvm_msr_entry msr_ent = {.index = msr, .data = 0}; 3556 3557 if (!msr_info->host_initiated) 3558 return 1; 3559 if (kvm_get_msr_feature(&msr_ent)) 3560 return 1; 3561 if (data & ~msr_ent.data) 3562 return 1; 3563 3564 vcpu->arch.perf_capabilities = data; 3565 kvm_pmu_refresh(vcpu); 3566 return 0; 3567 } 3568 case MSR_EFER: 3569 return set_efer(vcpu, msr_info); 3570 case MSR_K7_HWCR: 3571 data &= ~(u64)0x40; /* ignore flush filter disable */ 3572 data &= ~(u64)0x100; /* ignore ignne emulation enable */ 3573 data &= ~(u64)0x8; /* ignore TLB cache disable */ 3574 3575 /* Handle McStatusWrEn */ 3576 if (data == BIT_ULL(18)) { 3577 vcpu->arch.msr_hwcr = data; 3578 } else if (data != 0) { 3579 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n", 3580 data); 3581 return 1; 3582 } 3583 break; 3584 case MSR_FAM10H_MMIO_CONF_BASE: 3585 if (data != 0) { 3586 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: " 3587 "0x%llx\n", data); 3588 return 1; 3589 } 3590 break; 3591 case 0x200 ... MSR_IA32_MC0_CTL2 - 1: 3592 case MSR_IA32_MCx_CTL2(KVM_MAX_MCE_BANKS) ... 0x2ff: 3593 return kvm_mtrr_set_msr(vcpu, msr, data); 3594 case MSR_IA32_APICBASE: 3595 return kvm_set_apic_base(vcpu, msr_info); 3596 case APIC_BASE_MSR ... APIC_BASE_MSR + 0xff: 3597 return kvm_x2apic_msr_write(vcpu, msr, data); 3598 case MSR_IA32_TSC_DEADLINE: 3599 kvm_set_lapic_tscdeadline_msr(vcpu, data); 3600 break; 3601 case MSR_IA32_TSC_ADJUST: 3602 if (guest_cpuid_has(vcpu, X86_FEATURE_TSC_ADJUST)) { 3603 if (!msr_info->host_initiated) { 3604 s64 adj = data - vcpu->arch.ia32_tsc_adjust_msr; 3605 adjust_tsc_offset_guest(vcpu, adj); 3606 /* Before back to guest, tsc_timestamp must be adjusted 3607 * as well, otherwise guest's percpu pvclock time could jump. 3608 */ 3609 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 3610 } 3611 vcpu->arch.ia32_tsc_adjust_msr = data; 3612 } 3613 break; 3614 case MSR_IA32_MISC_ENABLE: { 3615 u64 old_val = vcpu->arch.ia32_misc_enable_msr; 3616 3617 if (!msr_info->host_initiated) { 3618 /* RO bits */ 3619 if ((old_val ^ data) & MSR_IA32_MISC_ENABLE_PMU_RO_MASK) 3620 return 1; 3621 3622 /* R bits, i.e. writes are ignored, but don't fault. */ 3623 data = data & ~MSR_IA32_MISC_ENABLE_EMON; 3624 data |= old_val & MSR_IA32_MISC_ENABLE_EMON; 3625 } 3626 3627 if (!kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_MISC_ENABLE_NO_MWAIT) && 3628 ((old_val ^ data) & MSR_IA32_MISC_ENABLE_MWAIT)) { 3629 if (!guest_cpuid_has(vcpu, X86_FEATURE_XMM3)) 3630 return 1; 3631 vcpu->arch.ia32_misc_enable_msr = data; 3632 kvm_update_cpuid_runtime(vcpu); 3633 } else { 3634 vcpu->arch.ia32_misc_enable_msr = data; 3635 } 3636 break; 3637 } 3638 case MSR_IA32_SMBASE: 3639 if (!msr_info->host_initiated) 3640 return 1; 3641 vcpu->arch.smbase = data; 3642 break; 3643 case MSR_IA32_POWER_CTL: 3644 vcpu->arch.msr_ia32_power_ctl = data; 3645 break; 3646 case MSR_IA32_TSC: 3647 if (msr_info->host_initiated) { 3648 kvm_synchronize_tsc(vcpu, data); 3649 } else { 3650 u64 adj = kvm_compute_l1_tsc_offset(vcpu, data) - vcpu->arch.l1_tsc_offset; 3651 adjust_tsc_offset_guest(vcpu, adj); 3652 vcpu->arch.ia32_tsc_adjust_msr += adj; 3653 } 3654 break; 3655 case MSR_IA32_XSS: 3656 if (!msr_info->host_initiated && 3657 !guest_cpuid_has(vcpu, X86_FEATURE_XSAVES)) 3658 return 1; 3659 /* 3660 * KVM supports exposing PT to the guest, but does not support 3661 * IA32_XSS[bit 8]. Guests have to use RDMSR/WRMSR rather than 3662 * XSAVES/XRSTORS to save/restore PT MSRs. 3663 */ 3664 if (data & ~kvm_caps.supported_xss) 3665 return 1; 3666 vcpu->arch.ia32_xss = data; 3667 kvm_update_cpuid_runtime(vcpu); 3668 break; 3669 case MSR_SMI_COUNT: 3670 if (!msr_info->host_initiated) 3671 return 1; 3672 vcpu->arch.smi_count = data; 3673 break; 3674 case MSR_KVM_WALL_CLOCK_NEW: 3675 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE2)) 3676 return 1; 3677 3678 vcpu->kvm->arch.wall_clock = data; 3679 kvm_write_wall_clock(vcpu->kvm, data, 0); 3680 break; 3681 case MSR_KVM_WALL_CLOCK: 3682 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE)) 3683 return 1; 3684 3685 vcpu->kvm->arch.wall_clock = data; 3686 kvm_write_wall_clock(vcpu->kvm, data, 0); 3687 break; 3688 case MSR_KVM_SYSTEM_TIME_NEW: 3689 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE2)) 3690 return 1; 3691 3692 kvm_write_system_time(vcpu, data, false, msr_info->host_initiated); 3693 break; 3694 case MSR_KVM_SYSTEM_TIME: 3695 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE)) 3696 return 1; 3697 3698 kvm_write_system_time(vcpu, data, true, msr_info->host_initiated); 3699 break; 3700 case MSR_KVM_ASYNC_PF_EN: 3701 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF)) 3702 return 1; 3703 3704 if (kvm_pv_enable_async_pf(vcpu, data)) 3705 return 1; 3706 break; 3707 case MSR_KVM_ASYNC_PF_INT: 3708 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_INT)) 3709 return 1; 3710 3711 if (kvm_pv_enable_async_pf_int(vcpu, data)) 3712 return 1; 3713 break; 3714 case MSR_KVM_ASYNC_PF_ACK: 3715 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_INT)) 3716 return 1; 3717 if (data & 0x1) { 3718 vcpu->arch.apf.pageready_pending = false; 3719 kvm_check_async_pf_completion(vcpu); 3720 } 3721 break; 3722 case MSR_KVM_STEAL_TIME: 3723 if (!guest_pv_has(vcpu, KVM_FEATURE_STEAL_TIME)) 3724 return 1; 3725 3726 if (unlikely(!sched_info_on())) 3727 return 1; 3728 3729 if (data & KVM_STEAL_RESERVED_MASK) 3730 return 1; 3731 3732 vcpu->arch.st.msr_val = data; 3733 3734 if (!(data & KVM_MSR_ENABLED)) 3735 break; 3736 3737 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu); 3738 3739 break; 3740 case MSR_KVM_PV_EOI_EN: 3741 if (!guest_pv_has(vcpu, KVM_FEATURE_PV_EOI)) 3742 return 1; 3743 3744 if (kvm_lapic_set_pv_eoi(vcpu, data, sizeof(u8))) 3745 return 1; 3746 break; 3747 3748 case MSR_KVM_POLL_CONTROL: 3749 if (!guest_pv_has(vcpu, KVM_FEATURE_POLL_CONTROL)) 3750 return 1; 3751 3752 /* only enable bit supported */ 3753 if (data & (-1ULL << 1)) 3754 return 1; 3755 3756 vcpu->arch.msr_kvm_poll_control = data; 3757 break; 3758 3759 case MSR_IA32_MCG_CTL: 3760 case MSR_IA32_MCG_STATUS: 3761 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1: 3762 case MSR_IA32_MC0_CTL2 ... MSR_IA32_MCx_CTL2(KVM_MAX_MCE_BANKS) - 1: 3763 return set_msr_mce(vcpu, msr_info); 3764 3765 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3: 3766 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1: 3767 pr = true; 3768 fallthrough; 3769 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3: 3770 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1: 3771 if (kvm_pmu_is_valid_msr(vcpu, msr)) 3772 return kvm_pmu_set_msr(vcpu, msr_info); 3773 3774 if (pr || data != 0) 3775 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: " 3776 "0x%x data 0x%llx\n", msr, data); 3777 break; 3778 case MSR_K7_CLK_CTL: 3779 /* 3780 * Ignore all writes to this no longer documented MSR. 3781 * Writes are only relevant for old K7 processors, 3782 * all pre-dating SVM, but a recommended workaround from 3783 * AMD for these chips. It is possible to specify the 3784 * affected processor models on the command line, hence 3785 * the need to ignore the workaround. 3786 */ 3787 break; 3788 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15: 3789 case HV_X64_MSR_SYNDBG_CONTROL ... HV_X64_MSR_SYNDBG_PENDING_BUFFER: 3790 case HV_X64_MSR_SYNDBG_OPTIONS: 3791 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4: 3792 case HV_X64_MSR_CRASH_CTL: 3793 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT: 3794 case HV_X64_MSR_REENLIGHTENMENT_CONTROL: 3795 case HV_X64_MSR_TSC_EMULATION_CONTROL: 3796 case HV_X64_MSR_TSC_EMULATION_STATUS: 3797 return kvm_hv_set_msr_common(vcpu, msr, data, 3798 msr_info->host_initiated); 3799 case MSR_IA32_BBL_CR_CTL3: 3800 /* Drop writes to this legacy MSR -- see rdmsr 3801 * counterpart for further detail. 3802 */ 3803 if (report_ignored_msrs) 3804 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data 0x%llx\n", 3805 msr, data); 3806 break; 3807 case MSR_AMD64_OSVW_ID_LENGTH: 3808 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW)) 3809 return 1; 3810 vcpu->arch.osvw.length = data; 3811 break; 3812 case MSR_AMD64_OSVW_STATUS: 3813 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW)) 3814 return 1; 3815 vcpu->arch.osvw.status = data; 3816 break; 3817 case MSR_PLATFORM_INFO: 3818 if (!msr_info->host_initiated || 3819 (!(data & MSR_PLATFORM_INFO_CPUID_FAULT) && 3820 cpuid_fault_enabled(vcpu))) 3821 return 1; 3822 vcpu->arch.msr_platform_info = data; 3823 break; 3824 case MSR_MISC_FEATURES_ENABLES: 3825 if (data & ~MSR_MISC_FEATURES_ENABLES_CPUID_FAULT || 3826 (data & MSR_MISC_FEATURES_ENABLES_CPUID_FAULT && 3827 !supports_cpuid_fault(vcpu))) 3828 return 1; 3829 vcpu->arch.msr_misc_features_enables = data; 3830 break; 3831 #ifdef CONFIG_X86_64 3832 case MSR_IA32_XFD: 3833 if (!msr_info->host_initiated && 3834 !guest_cpuid_has(vcpu, X86_FEATURE_XFD)) 3835 return 1; 3836 3837 if (data & ~kvm_guest_supported_xfd(vcpu)) 3838 return 1; 3839 3840 fpu_update_guest_xfd(&vcpu->arch.guest_fpu, data); 3841 break; 3842 case MSR_IA32_XFD_ERR: 3843 if (!msr_info->host_initiated && 3844 !guest_cpuid_has(vcpu, X86_FEATURE_XFD)) 3845 return 1; 3846 3847 if (data & ~kvm_guest_supported_xfd(vcpu)) 3848 return 1; 3849 3850 vcpu->arch.guest_fpu.xfd_err = data; 3851 break; 3852 #endif 3853 case MSR_IA32_PEBS_ENABLE: 3854 case MSR_IA32_DS_AREA: 3855 case MSR_PEBS_DATA_CFG: 3856 case MSR_F15H_PERF_CTL0 ... MSR_F15H_PERF_CTR5: 3857 if (kvm_pmu_is_valid_msr(vcpu, msr)) 3858 return kvm_pmu_set_msr(vcpu, msr_info); 3859 /* 3860 * Userspace is allowed to write '0' to MSRs that KVM reports 3861 * as to-be-saved, even if an MSRs isn't fully supported. 3862 */ 3863 return !msr_info->host_initiated || data; 3864 default: 3865 if (kvm_pmu_is_valid_msr(vcpu, msr)) 3866 return kvm_pmu_set_msr(vcpu, msr_info); 3867 return KVM_MSR_RET_INVALID; 3868 } 3869 return 0; 3870 } 3871 EXPORT_SYMBOL_GPL(kvm_set_msr_common); 3872 3873 static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata, bool host) 3874 { 3875 u64 data; 3876 u64 mcg_cap = vcpu->arch.mcg_cap; 3877 unsigned bank_num = mcg_cap & 0xff; 3878 u32 offset, last_msr; 3879 3880 switch (msr) { 3881 case MSR_IA32_P5_MC_ADDR: 3882 case MSR_IA32_P5_MC_TYPE: 3883 data = 0; 3884 break; 3885 case MSR_IA32_MCG_CAP: 3886 data = vcpu->arch.mcg_cap; 3887 break; 3888 case MSR_IA32_MCG_CTL: 3889 if (!(mcg_cap & MCG_CTL_P) && !host) 3890 return 1; 3891 data = vcpu->arch.mcg_ctl; 3892 break; 3893 case MSR_IA32_MCG_STATUS: 3894 data = vcpu->arch.mcg_status; 3895 break; 3896 case MSR_IA32_MC0_CTL2 ... MSR_IA32_MCx_CTL2(KVM_MAX_MCE_BANKS) - 1: 3897 last_msr = MSR_IA32_MCx_CTL2(bank_num) - 1; 3898 if (msr > last_msr) 3899 return 1; 3900 3901 if (!(mcg_cap & MCG_CMCI_P) && !host) 3902 return 1; 3903 offset = array_index_nospec(msr - MSR_IA32_MC0_CTL2, 3904 last_msr + 1 - MSR_IA32_MC0_CTL2); 3905 data = vcpu->arch.mci_ctl2_banks[offset]; 3906 break; 3907 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1: 3908 last_msr = MSR_IA32_MCx_CTL(bank_num) - 1; 3909 if (msr > last_msr) 3910 return 1; 3911 3912 offset = array_index_nospec(msr - MSR_IA32_MC0_CTL, 3913 last_msr + 1 - MSR_IA32_MC0_CTL); 3914 data = vcpu->arch.mce_banks[offset]; 3915 break; 3916 default: 3917 return 1; 3918 } 3919 *pdata = data; 3920 return 0; 3921 } 3922 3923 int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info) 3924 { 3925 switch (msr_info->index) { 3926 case MSR_IA32_PLATFORM_ID: 3927 case MSR_IA32_EBL_CR_POWERON: 3928 case MSR_IA32_LASTBRANCHFROMIP: 3929 case MSR_IA32_LASTBRANCHTOIP: 3930 case MSR_IA32_LASTINTFROMIP: 3931 case MSR_IA32_LASTINTTOIP: 3932 case MSR_AMD64_SYSCFG: 3933 case MSR_K8_TSEG_ADDR: 3934 case MSR_K8_TSEG_MASK: 3935 case MSR_VM_HSAVE_PA: 3936 case MSR_K8_INT_PENDING_MSG: 3937 case MSR_AMD64_NB_CFG: 3938 case MSR_FAM10H_MMIO_CONF_BASE: 3939 case MSR_AMD64_BU_CFG2: 3940 case MSR_IA32_PERF_CTL: 3941 case MSR_AMD64_DC_CFG: 3942 case MSR_F15H_EX_CFG: 3943 /* 3944 * Intel Sandy Bridge CPUs must support the RAPL (running average power 3945 * limit) MSRs. Just return 0, as we do not want to expose the host 3946 * data here. Do not conditionalize this on CPUID, as KVM does not do 3947 * so for existing CPU-specific MSRs. 3948 */ 3949 case MSR_RAPL_POWER_UNIT: 3950 case MSR_PP0_ENERGY_STATUS: /* Power plane 0 (core) */ 3951 case MSR_PP1_ENERGY_STATUS: /* Power plane 1 (graphics uncore) */ 3952 case MSR_PKG_ENERGY_STATUS: /* Total package */ 3953 case MSR_DRAM_ENERGY_STATUS: /* DRAM controller */ 3954 msr_info->data = 0; 3955 break; 3956 case MSR_IA32_PEBS_ENABLE: 3957 case MSR_IA32_DS_AREA: 3958 case MSR_PEBS_DATA_CFG: 3959 case MSR_F15H_PERF_CTL0 ... MSR_F15H_PERF_CTR5: 3960 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index)) 3961 return kvm_pmu_get_msr(vcpu, msr_info); 3962 /* 3963 * Userspace is allowed to read MSRs that KVM reports as 3964 * to-be-saved, even if an MSR isn't fully supported. 3965 */ 3966 if (!msr_info->host_initiated) 3967 return 1; 3968 msr_info->data = 0; 3969 break; 3970 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3: 3971 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3: 3972 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1: 3973 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1: 3974 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index)) 3975 return kvm_pmu_get_msr(vcpu, msr_info); 3976 msr_info->data = 0; 3977 break; 3978 case MSR_IA32_UCODE_REV: 3979 msr_info->data = vcpu->arch.microcode_version; 3980 break; 3981 case MSR_IA32_ARCH_CAPABILITIES: 3982 if (!msr_info->host_initiated && 3983 !guest_cpuid_has(vcpu, X86_FEATURE_ARCH_CAPABILITIES)) 3984 return 1; 3985 msr_info->data = vcpu->arch.arch_capabilities; 3986 break; 3987 case MSR_IA32_PERF_CAPABILITIES: 3988 if (!msr_info->host_initiated && 3989 !guest_cpuid_has(vcpu, X86_FEATURE_PDCM)) 3990 return 1; 3991 msr_info->data = vcpu->arch.perf_capabilities; 3992 break; 3993 case MSR_IA32_POWER_CTL: 3994 msr_info->data = vcpu->arch.msr_ia32_power_ctl; 3995 break; 3996 case MSR_IA32_TSC: { 3997 /* 3998 * Intel SDM states that MSR_IA32_TSC read adds the TSC offset 3999 * even when not intercepted. AMD manual doesn't explicitly 4000 * state this but appears to behave the same. 4001 * 4002 * On userspace reads and writes, however, we unconditionally 4003 * return L1's TSC value to ensure backwards-compatible 4004 * behavior for migration. 4005 */ 4006 u64 offset, ratio; 4007 4008 if (msr_info->host_initiated) { 4009 offset = vcpu->arch.l1_tsc_offset; 4010 ratio = vcpu->arch.l1_tsc_scaling_ratio; 4011 } else { 4012 offset = vcpu->arch.tsc_offset; 4013 ratio = vcpu->arch.tsc_scaling_ratio; 4014 } 4015 4016 msr_info->data = kvm_scale_tsc(rdtsc(), ratio) + offset; 4017 break; 4018 } 4019 case MSR_MTRRcap: 4020 case 0x200 ... MSR_IA32_MC0_CTL2 - 1: 4021 case MSR_IA32_MCx_CTL2(KVM_MAX_MCE_BANKS) ... 0x2ff: 4022 return kvm_mtrr_get_msr(vcpu, msr_info->index, &msr_info->data); 4023 case 0xcd: /* fsb frequency */ 4024 msr_info->data = 3; 4025 break; 4026 /* 4027 * MSR_EBC_FREQUENCY_ID 4028 * Conservative value valid for even the basic CPU models. 4029 * Models 0,1: 000 in bits 23:21 indicating a bus speed of 4030 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz, 4031 * and 266MHz for model 3, or 4. Set Core Clock 4032 * Frequency to System Bus Frequency Ratio to 1 (bits 4033 * 31:24) even though these are only valid for CPU 4034 * models > 2, however guests may end up dividing or 4035 * multiplying by zero otherwise. 4036 */ 4037 case MSR_EBC_FREQUENCY_ID: 4038 msr_info->data = 1 << 24; 4039 break; 4040 case MSR_IA32_APICBASE: 4041 msr_info->data = kvm_get_apic_base(vcpu); 4042 break; 4043 case APIC_BASE_MSR ... APIC_BASE_MSR + 0xff: 4044 return kvm_x2apic_msr_read(vcpu, msr_info->index, &msr_info->data); 4045 case MSR_IA32_TSC_DEADLINE: 4046 msr_info->data = kvm_get_lapic_tscdeadline_msr(vcpu); 4047 break; 4048 case MSR_IA32_TSC_ADJUST: 4049 msr_info->data = (u64)vcpu->arch.ia32_tsc_adjust_msr; 4050 break; 4051 case MSR_IA32_MISC_ENABLE: 4052 msr_info->data = vcpu->arch.ia32_misc_enable_msr; 4053 break; 4054 case MSR_IA32_SMBASE: 4055 if (!msr_info->host_initiated) 4056 return 1; 4057 msr_info->data = vcpu->arch.smbase; 4058 break; 4059 case MSR_SMI_COUNT: 4060 msr_info->data = vcpu->arch.smi_count; 4061 break; 4062 case MSR_IA32_PERF_STATUS: 4063 /* TSC increment by tick */ 4064 msr_info->data = 1000ULL; 4065 /* CPU multiplier */ 4066 msr_info->data |= (((uint64_t)4ULL) << 40); 4067 break; 4068 case MSR_EFER: 4069 msr_info->data = vcpu->arch.efer; 4070 break; 4071 case MSR_KVM_WALL_CLOCK: 4072 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE)) 4073 return 1; 4074 4075 msr_info->data = vcpu->kvm->arch.wall_clock; 4076 break; 4077 case MSR_KVM_WALL_CLOCK_NEW: 4078 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE2)) 4079 return 1; 4080 4081 msr_info->data = vcpu->kvm->arch.wall_clock; 4082 break; 4083 case MSR_KVM_SYSTEM_TIME: 4084 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE)) 4085 return 1; 4086 4087 msr_info->data = vcpu->arch.time; 4088 break; 4089 case MSR_KVM_SYSTEM_TIME_NEW: 4090 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE2)) 4091 return 1; 4092 4093 msr_info->data = vcpu->arch.time; 4094 break; 4095 case MSR_KVM_ASYNC_PF_EN: 4096 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF)) 4097 return 1; 4098 4099 msr_info->data = vcpu->arch.apf.msr_en_val; 4100 break; 4101 case MSR_KVM_ASYNC_PF_INT: 4102 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_INT)) 4103 return 1; 4104 4105 msr_info->data = vcpu->arch.apf.msr_int_val; 4106 break; 4107 case MSR_KVM_ASYNC_PF_ACK: 4108 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_INT)) 4109 return 1; 4110 4111 msr_info->data = 0; 4112 break; 4113 case MSR_KVM_STEAL_TIME: 4114 if (!guest_pv_has(vcpu, KVM_FEATURE_STEAL_TIME)) 4115 return 1; 4116 4117 msr_info->data = vcpu->arch.st.msr_val; 4118 break; 4119 case MSR_KVM_PV_EOI_EN: 4120 if (!guest_pv_has(vcpu, KVM_FEATURE_PV_EOI)) 4121 return 1; 4122 4123 msr_info->data = vcpu->arch.pv_eoi.msr_val; 4124 break; 4125 case MSR_KVM_POLL_CONTROL: 4126 if (!guest_pv_has(vcpu, KVM_FEATURE_POLL_CONTROL)) 4127 return 1; 4128 4129 msr_info->data = vcpu->arch.msr_kvm_poll_control; 4130 break; 4131 case MSR_IA32_P5_MC_ADDR: 4132 case MSR_IA32_P5_MC_TYPE: 4133 case MSR_IA32_MCG_CAP: 4134 case MSR_IA32_MCG_CTL: 4135 case MSR_IA32_MCG_STATUS: 4136 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1: 4137 case MSR_IA32_MC0_CTL2 ... MSR_IA32_MCx_CTL2(KVM_MAX_MCE_BANKS) - 1: 4138 return get_msr_mce(vcpu, msr_info->index, &msr_info->data, 4139 msr_info->host_initiated); 4140 case MSR_IA32_XSS: 4141 if (!msr_info->host_initiated && 4142 !guest_cpuid_has(vcpu, X86_FEATURE_XSAVES)) 4143 return 1; 4144 msr_info->data = vcpu->arch.ia32_xss; 4145 break; 4146 case MSR_K7_CLK_CTL: 4147 /* 4148 * Provide expected ramp-up count for K7. All other 4149 * are set to zero, indicating minimum divisors for 4150 * every field. 4151 * 4152 * This prevents guest kernels on AMD host with CPU 4153 * type 6, model 8 and higher from exploding due to 4154 * the rdmsr failing. 4155 */ 4156 msr_info->data = 0x20000000; 4157 break; 4158 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15: 4159 case HV_X64_MSR_SYNDBG_CONTROL ... HV_X64_MSR_SYNDBG_PENDING_BUFFER: 4160 case HV_X64_MSR_SYNDBG_OPTIONS: 4161 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4: 4162 case HV_X64_MSR_CRASH_CTL: 4163 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT: 4164 case HV_X64_MSR_REENLIGHTENMENT_CONTROL: 4165 case HV_X64_MSR_TSC_EMULATION_CONTROL: 4166 case HV_X64_MSR_TSC_EMULATION_STATUS: 4167 return kvm_hv_get_msr_common(vcpu, 4168 msr_info->index, &msr_info->data, 4169 msr_info->host_initiated); 4170 case MSR_IA32_BBL_CR_CTL3: 4171 /* This legacy MSR exists but isn't fully documented in current 4172 * silicon. It is however accessed by winxp in very narrow 4173 * scenarios where it sets bit #19, itself documented as 4174 * a "reserved" bit. Best effort attempt to source coherent 4175 * read data here should the balance of the register be 4176 * interpreted by the guest: 4177 * 4178 * L2 cache control register 3: 64GB range, 256KB size, 4179 * enabled, latency 0x1, configured 4180 */ 4181 msr_info->data = 0xbe702111; 4182 break; 4183 case MSR_AMD64_OSVW_ID_LENGTH: 4184 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW)) 4185 return 1; 4186 msr_info->data = vcpu->arch.osvw.length; 4187 break; 4188 case MSR_AMD64_OSVW_STATUS: 4189 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW)) 4190 return 1; 4191 msr_info->data = vcpu->arch.osvw.status; 4192 break; 4193 case MSR_PLATFORM_INFO: 4194 if (!msr_info->host_initiated && 4195 !vcpu->kvm->arch.guest_can_read_msr_platform_info) 4196 return 1; 4197 msr_info->data = vcpu->arch.msr_platform_info; 4198 break; 4199 case MSR_MISC_FEATURES_ENABLES: 4200 msr_info->data = vcpu->arch.msr_misc_features_enables; 4201 break; 4202 case MSR_K7_HWCR: 4203 msr_info->data = vcpu->arch.msr_hwcr; 4204 break; 4205 #ifdef CONFIG_X86_64 4206 case MSR_IA32_XFD: 4207 if (!msr_info->host_initiated && 4208 !guest_cpuid_has(vcpu, X86_FEATURE_XFD)) 4209 return 1; 4210 4211 msr_info->data = vcpu->arch.guest_fpu.fpstate->xfd; 4212 break; 4213 case MSR_IA32_XFD_ERR: 4214 if (!msr_info->host_initiated && 4215 !guest_cpuid_has(vcpu, X86_FEATURE_XFD)) 4216 return 1; 4217 4218 msr_info->data = vcpu->arch.guest_fpu.xfd_err; 4219 break; 4220 #endif 4221 default: 4222 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index)) 4223 return kvm_pmu_get_msr(vcpu, msr_info); 4224 return KVM_MSR_RET_INVALID; 4225 } 4226 return 0; 4227 } 4228 EXPORT_SYMBOL_GPL(kvm_get_msr_common); 4229 4230 /* 4231 * Read or write a bunch of msrs. All parameters are kernel addresses. 4232 * 4233 * @return number of msrs set successfully. 4234 */ 4235 static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs, 4236 struct kvm_msr_entry *entries, 4237 int (*do_msr)(struct kvm_vcpu *vcpu, 4238 unsigned index, u64 *data)) 4239 { 4240 int i; 4241 4242 for (i = 0; i < msrs->nmsrs; ++i) 4243 if (do_msr(vcpu, entries[i].index, &entries[i].data)) 4244 break; 4245 4246 return i; 4247 } 4248 4249 /* 4250 * Read or write a bunch of msrs. Parameters are user addresses. 4251 * 4252 * @return number of msrs set successfully. 4253 */ 4254 static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs, 4255 int (*do_msr)(struct kvm_vcpu *vcpu, 4256 unsigned index, u64 *data), 4257 int writeback) 4258 { 4259 struct kvm_msrs msrs; 4260 struct kvm_msr_entry *entries; 4261 int r, n; 4262 unsigned size; 4263 4264 r = -EFAULT; 4265 if (copy_from_user(&msrs, user_msrs, sizeof(msrs))) 4266 goto out; 4267 4268 r = -E2BIG; 4269 if (msrs.nmsrs >= MAX_IO_MSRS) 4270 goto out; 4271 4272 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs; 4273 entries = memdup_user(user_msrs->entries, size); 4274 if (IS_ERR(entries)) { 4275 r = PTR_ERR(entries); 4276 goto out; 4277 } 4278 4279 r = n = __msr_io(vcpu, &msrs, entries, do_msr); 4280 if (r < 0) 4281 goto out_free; 4282 4283 r = -EFAULT; 4284 if (writeback && copy_to_user(user_msrs->entries, entries, size)) 4285 goto out_free; 4286 4287 r = n; 4288 4289 out_free: 4290 kfree(entries); 4291 out: 4292 return r; 4293 } 4294 4295 static inline bool kvm_can_mwait_in_guest(void) 4296 { 4297 return boot_cpu_has(X86_FEATURE_MWAIT) && 4298 !boot_cpu_has_bug(X86_BUG_MONITOR) && 4299 boot_cpu_has(X86_FEATURE_ARAT); 4300 } 4301 4302 static int kvm_ioctl_get_supported_hv_cpuid(struct kvm_vcpu *vcpu, 4303 struct kvm_cpuid2 __user *cpuid_arg) 4304 { 4305 struct kvm_cpuid2 cpuid; 4306 int r; 4307 4308 r = -EFAULT; 4309 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid))) 4310 return r; 4311 4312 r = kvm_get_hv_cpuid(vcpu, &cpuid, cpuid_arg->entries); 4313 if (r) 4314 return r; 4315 4316 r = -EFAULT; 4317 if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid))) 4318 return r; 4319 4320 return 0; 4321 } 4322 4323 int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext) 4324 { 4325 int r = 0; 4326 4327 switch (ext) { 4328 case KVM_CAP_IRQCHIP: 4329 case KVM_CAP_HLT: 4330 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL: 4331 case KVM_CAP_SET_TSS_ADDR: 4332 case KVM_CAP_EXT_CPUID: 4333 case KVM_CAP_EXT_EMUL_CPUID: 4334 case KVM_CAP_CLOCKSOURCE: 4335 case KVM_CAP_PIT: 4336 case KVM_CAP_NOP_IO_DELAY: 4337 case KVM_CAP_MP_STATE: 4338 case KVM_CAP_SYNC_MMU: 4339 case KVM_CAP_USER_NMI: 4340 case KVM_CAP_REINJECT_CONTROL: 4341 case KVM_CAP_IRQ_INJECT_STATUS: 4342 case KVM_CAP_IOEVENTFD: 4343 case KVM_CAP_IOEVENTFD_NO_LENGTH: 4344 case KVM_CAP_PIT2: 4345 case KVM_CAP_PIT_STATE2: 4346 case KVM_CAP_SET_IDENTITY_MAP_ADDR: 4347 case KVM_CAP_VCPU_EVENTS: 4348 case KVM_CAP_HYPERV: 4349 case KVM_CAP_HYPERV_VAPIC: 4350 case KVM_CAP_HYPERV_SPIN: 4351 case KVM_CAP_HYPERV_SYNIC: 4352 case KVM_CAP_HYPERV_SYNIC2: 4353 case KVM_CAP_HYPERV_VP_INDEX: 4354 case KVM_CAP_HYPERV_EVENTFD: 4355 case KVM_CAP_HYPERV_TLBFLUSH: 4356 case KVM_CAP_HYPERV_SEND_IPI: 4357 case KVM_CAP_HYPERV_CPUID: 4358 case KVM_CAP_HYPERV_ENFORCE_CPUID: 4359 case KVM_CAP_SYS_HYPERV_CPUID: 4360 case KVM_CAP_PCI_SEGMENT: 4361 case KVM_CAP_DEBUGREGS: 4362 case KVM_CAP_X86_ROBUST_SINGLESTEP: 4363 case KVM_CAP_XSAVE: 4364 case KVM_CAP_ASYNC_PF: 4365 case KVM_CAP_ASYNC_PF_INT: 4366 case KVM_CAP_GET_TSC_KHZ: 4367 case KVM_CAP_KVMCLOCK_CTRL: 4368 case KVM_CAP_READONLY_MEM: 4369 case KVM_CAP_HYPERV_TIME: 4370 case KVM_CAP_IOAPIC_POLARITY_IGNORED: 4371 case KVM_CAP_TSC_DEADLINE_TIMER: 4372 case KVM_CAP_DISABLE_QUIRKS: 4373 case KVM_CAP_SET_BOOT_CPU_ID: 4374 case KVM_CAP_SPLIT_IRQCHIP: 4375 case KVM_CAP_IMMEDIATE_EXIT: 4376 case KVM_CAP_PMU_EVENT_FILTER: 4377 case KVM_CAP_GET_MSR_FEATURES: 4378 case KVM_CAP_MSR_PLATFORM_INFO: 4379 case KVM_CAP_EXCEPTION_PAYLOAD: 4380 case KVM_CAP_X86_TRIPLE_FAULT_EVENT: 4381 case KVM_CAP_SET_GUEST_DEBUG: 4382 case KVM_CAP_LAST_CPU: 4383 case KVM_CAP_X86_USER_SPACE_MSR: 4384 case KVM_CAP_X86_MSR_FILTER: 4385 case KVM_CAP_ENFORCE_PV_FEATURE_CPUID: 4386 #ifdef CONFIG_X86_SGX_KVM 4387 case KVM_CAP_SGX_ATTRIBUTE: 4388 #endif 4389 case KVM_CAP_VM_COPY_ENC_CONTEXT_FROM: 4390 case KVM_CAP_VM_MOVE_ENC_CONTEXT_FROM: 4391 case KVM_CAP_SREGS2: 4392 case KVM_CAP_EXIT_ON_EMULATION_FAILURE: 4393 case KVM_CAP_VCPU_ATTRIBUTES: 4394 case KVM_CAP_SYS_ATTRIBUTES: 4395 case KVM_CAP_VAPIC: 4396 case KVM_CAP_ENABLE_CAP: 4397 case KVM_CAP_VM_DISABLE_NX_HUGE_PAGES: 4398 r = 1; 4399 break; 4400 case KVM_CAP_EXIT_HYPERCALL: 4401 r = KVM_EXIT_HYPERCALL_VALID_MASK; 4402 break; 4403 case KVM_CAP_SET_GUEST_DEBUG2: 4404 return KVM_GUESTDBG_VALID_MASK; 4405 #ifdef CONFIG_KVM_XEN 4406 case KVM_CAP_XEN_HVM: 4407 r = KVM_XEN_HVM_CONFIG_HYPERCALL_MSR | 4408 KVM_XEN_HVM_CONFIG_INTERCEPT_HCALL | 4409 KVM_XEN_HVM_CONFIG_SHARED_INFO | 4410 KVM_XEN_HVM_CONFIG_EVTCHN_2LEVEL | 4411 KVM_XEN_HVM_CONFIG_EVTCHN_SEND; 4412 if (sched_info_on()) 4413 r |= KVM_XEN_HVM_CONFIG_RUNSTATE; 4414 break; 4415 #endif 4416 case KVM_CAP_SYNC_REGS: 4417 r = KVM_SYNC_X86_VALID_FIELDS; 4418 break; 4419 case KVM_CAP_ADJUST_CLOCK: 4420 r = KVM_CLOCK_VALID_FLAGS; 4421 break; 4422 case KVM_CAP_X86_DISABLE_EXITS: 4423 r |= KVM_X86_DISABLE_EXITS_HLT | KVM_X86_DISABLE_EXITS_PAUSE | 4424 KVM_X86_DISABLE_EXITS_CSTATE; 4425 if(kvm_can_mwait_in_guest()) 4426 r |= KVM_X86_DISABLE_EXITS_MWAIT; 4427 break; 4428 case KVM_CAP_X86_SMM: 4429 /* SMBASE is usually relocated above 1M on modern chipsets, 4430 * and SMM handlers might indeed rely on 4G segment limits, 4431 * so do not report SMM to be available if real mode is 4432 * emulated via vm86 mode. Still, do not go to great lengths 4433 * to avoid userspace's usage of the feature, because it is a 4434 * fringe case that is not enabled except via specific settings 4435 * of the module parameters. 4436 */ 4437 r = static_call(kvm_x86_has_emulated_msr)(kvm, MSR_IA32_SMBASE); 4438 break; 4439 case KVM_CAP_NR_VCPUS: 4440 r = min_t(unsigned int, num_online_cpus(), KVM_MAX_VCPUS); 4441 break; 4442 case KVM_CAP_MAX_VCPUS: 4443 r = KVM_MAX_VCPUS; 4444 break; 4445 case KVM_CAP_MAX_VCPU_ID: 4446 r = KVM_MAX_VCPU_IDS; 4447 break; 4448 case KVM_CAP_PV_MMU: /* obsolete */ 4449 r = 0; 4450 break; 4451 case KVM_CAP_MCE: 4452 r = KVM_MAX_MCE_BANKS; 4453 break; 4454 case KVM_CAP_XCRS: 4455 r = boot_cpu_has(X86_FEATURE_XSAVE); 4456 break; 4457 case KVM_CAP_TSC_CONTROL: 4458 case KVM_CAP_VM_TSC_CONTROL: 4459 r = kvm_caps.has_tsc_control; 4460 break; 4461 case KVM_CAP_X2APIC_API: 4462 r = KVM_X2APIC_API_VALID_FLAGS; 4463 break; 4464 case KVM_CAP_NESTED_STATE: 4465 r = kvm_x86_ops.nested_ops->get_state ? 4466 kvm_x86_ops.nested_ops->get_state(NULL, NULL, 0) : 0; 4467 break; 4468 case KVM_CAP_HYPERV_DIRECT_TLBFLUSH: 4469 r = kvm_x86_ops.enable_direct_tlbflush != NULL; 4470 break; 4471 case KVM_CAP_HYPERV_ENLIGHTENED_VMCS: 4472 r = kvm_x86_ops.nested_ops->enable_evmcs != NULL; 4473 break; 4474 case KVM_CAP_SMALLER_MAXPHYADDR: 4475 r = (int) allow_smaller_maxphyaddr; 4476 break; 4477 case KVM_CAP_STEAL_TIME: 4478 r = sched_info_on(); 4479 break; 4480 case KVM_CAP_X86_BUS_LOCK_EXIT: 4481 if (kvm_caps.has_bus_lock_exit) 4482 r = KVM_BUS_LOCK_DETECTION_OFF | 4483 KVM_BUS_LOCK_DETECTION_EXIT; 4484 else 4485 r = 0; 4486 break; 4487 case KVM_CAP_XSAVE2: { 4488 u64 guest_perm = xstate_get_guest_group_perm(); 4489 4490 r = xstate_required_size(kvm_caps.supported_xcr0 & guest_perm, false); 4491 if (r < sizeof(struct kvm_xsave)) 4492 r = sizeof(struct kvm_xsave); 4493 break; 4494 } 4495 case KVM_CAP_PMU_CAPABILITY: 4496 r = enable_pmu ? KVM_CAP_PMU_VALID_MASK : 0; 4497 break; 4498 case KVM_CAP_DISABLE_QUIRKS2: 4499 r = KVM_X86_VALID_QUIRKS; 4500 break; 4501 case KVM_CAP_X86_NOTIFY_VMEXIT: 4502 r = kvm_caps.has_notify_vmexit; 4503 break; 4504 default: 4505 break; 4506 } 4507 return r; 4508 } 4509 4510 static inline void __user *kvm_get_attr_addr(struct kvm_device_attr *attr) 4511 { 4512 void __user *uaddr = (void __user*)(unsigned long)attr->addr; 4513 4514 if ((u64)(unsigned long)uaddr != attr->addr) 4515 return ERR_PTR_USR(-EFAULT); 4516 return uaddr; 4517 } 4518 4519 static int kvm_x86_dev_get_attr(struct kvm_device_attr *attr) 4520 { 4521 u64 __user *uaddr = kvm_get_attr_addr(attr); 4522 4523 if (attr->group) 4524 return -ENXIO; 4525 4526 if (IS_ERR(uaddr)) 4527 return PTR_ERR(uaddr); 4528 4529 switch (attr->attr) { 4530 case KVM_X86_XCOMP_GUEST_SUPP: 4531 if (put_user(kvm_caps.supported_xcr0, uaddr)) 4532 return -EFAULT; 4533 return 0; 4534 default: 4535 return -ENXIO; 4536 break; 4537 } 4538 } 4539 4540 static int kvm_x86_dev_has_attr(struct kvm_device_attr *attr) 4541 { 4542 if (attr->group) 4543 return -ENXIO; 4544 4545 switch (attr->attr) { 4546 case KVM_X86_XCOMP_GUEST_SUPP: 4547 return 0; 4548 default: 4549 return -ENXIO; 4550 } 4551 } 4552 4553 long kvm_arch_dev_ioctl(struct file *filp, 4554 unsigned int ioctl, unsigned long arg) 4555 { 4556 void __user *argp = (void __user *)arg; 4557 long r; 4558 4559 switch (ioctl) { 4560 case KVM_GET_MSR_INDEX_LIST: { 4561 struct kvm_msr_list __user *user_msr_list = argp; 4562 struct kvm_msr_list msr_list; 4563 unsigned n; 4564 4565 r = -EFAULT; 4566 if (copy_from_user(&msr_list, user_msr_list, sizeof(msr_list))) 4567 goto out; 4568 n = msr_list.nmsrs; 4569 msr_list.nmsrs = num_msrs_to_save + num_emulated_msrs; 4570 if (copy_to_user(user_msr_list, &msr_list, sizeof(msr_list))) 4571 goto out; 4572 r = -E2BIG; 4573 if (n < msr_list.nmsrs) 4574 goto out; 4575 r = -EFAULT; 4576 if (copy_to_user(user_msr_list->indices, &msrs_to_save, 4577 num_msrs_to_save * sizeof(u32))) 4578 goto out; 4579 if (copy_to_user(user_msr_list->indices + num_msrs_to_save, 4580 &emulated_msrs, 4581 num_emulated_msrs * sizeof(u32))) 4582 goto out; 4583 r = 0; 4584 break; 4585 } 4586 case KVM_GET_SUPPORTED_CPUID: 4587 case KVM_GET_EMULATED_CPUID: { 4588 struct kvm_cpuid2 __user *cpuid_arg = argp; 4589 struct kvm_cpuid2 cpuid; 4590 4591 r = -EFAULT; 4592 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid))) 4593 goto out; 4594 4595 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries, 4596 ioctl); 4597 if (r) 4598 goto out; 4599 4600 r = -EFAULT; 4601 if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid))) 4602 goto out; 4603 r = 0; 4604 break; 4605 } 4606 case KVM_X86_GET_MCE_CAP_SUPPORTED: 4607 r = -EFAULT; 4608 if (copy_to_user(argp, &kvm_caps.supported_mce_cap, 4609 sizeof(kvm_caps.supported_mce_cap))) 4610 goto out; 4611 r = 0; 4612 break; 4613 case KVM_GET_MSR_FEATURE_INDEX_LIST: { 4614 struct kvm_msr_list __user *user_msr_list = argp; 4615 struct kvm_msr_list msr_list; 4616 unsigned int n; 4617 4618 r = -EFAULT; 4619 if (copy_from_user(&msr_list, user_msr_list, sizeof(msr_list))) 4620 goto out; 4621 n = msr_list.nmsrs; 4622 msr_list.nmsrs = num_msr_based_features; 4623 if (copy_to_user(user_msr_list, &msr_list, sizeof(msr_list))) 4624 goto out; 4625 r = -E2BIG; 4626 if (n < msr_list.nmsrs) 4627 goto out; 4628 r = -EFAULT; 4629 if (copy_to_user(user_msr_list->indices, &msr_based_features, 4630 num_msr_based_features * sizeof(u32))) 4631 goto out; 4632 r = 0; 4633 break; 4634 } 4635 case KVM_GET_MSRS: 4636 r = msr_io(NULL, argp, do_get_msr_feature, 1); 4637 break; 4638 case KVM_GET_SUPPORTED_HV_CPUID: 4639 r = kvm_ioctl_get_supported_hv_cpuid(NULL, argp); 4640 break; 4641 case KVM_GET_DEVICE_ATTR: { 4642 struct kvm_device_attr attr; 4643 r = -EFAULT; 4644 if (copy_from_user(&attr, (void __user *)arg, sizeof(attr))) 4645 break; 4646 r = kvm_x86_dev_get_attr(&attr); 4647 break; 4648 } 4649 case KVM_HAS_DEVICE_ATTR: { 4650 struct kvm_device_attr attr; 4651 r = -EFAULT; 4652 if (copy_from_user(&attr, (void __user *)arg, sizeof(attr))) 4653 break; 4654 r = kvm_x86_dev_has_attr(&attr); 4655 break; 4656 } 4657 default: 4658 r = -EINVAL; 4659 break; 4660 } 4661 out: 4662 return r; 4663 } 4664 4665 static void wbinvd_ipi(void *garbage) 4666 { 4667 wbinvd(); 4668 } 4669 4670 static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu) 4671 { 4672 return kvm_arch_has_noncoherent_dma(vcpu->kvm); 4673 } 4674 4675 void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu) 4676 { 4677 /* Address WBINVD may be executed by guest */ 4678 if (need_emulate_wbinvd(vcpu)) { 4679 if (static_call(kvm_x86_has_wbinvd_exit)()) 4680 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask); 4681 else if (vcpu->cpu != -1 && vcpu->cpu != cpu) 4682 smp_call_function_single(vcpu->cpu, 4683 wbinvd_ipi, NULL, 1); 4684 } 4685 4686 static_call(kvm_x86_vcpu_load)(vcpu, cpu); 4687 4688 /* Save host pkru register if supported */ 4689 vcpu->arch.host_pkru = read_pkru(); 4690 4691 /* Apply any externally detected TSC adjustments (due to suspend) */ 4692 if (unlikely(vcpu->arch.tsc_offset_adjustment)) { 4693 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment); 4694 vcpu->arch.tsc_offset_adjustment = 0; 4695 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 4696 } 4697 4698 if (unlikely(vcpu->cpu != cpu) || kvm_check_tsc_unstable()) { 4699 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 : 4700 rdtsc() - vcpu->arch.last_host_tsc; 4701 if (tsc_delta < 0) 4702 mark_tsc_unstable("KVM discovered backwards TSC"); 4703 4704 if (kvm_check_tsc_unstable()) { 4705 u64 offset = kvm_compute_l1_tsc_offset(vcpu, 4706 vcpu->arch.last_guest_tsc); 4707 kvm_vcpu_write_tsc_offset(vcpu, offset); 4708 vcpu->arch.tsc_catchup = 1; 4709 } 4710 4711 if (kvm_lapic_hv_timer_in_use(vcpu)) 4712 kvm_lapic_restart_hv_timer(vcpu); 4713 4714 /* 4715 * On a host with synchronized TSC, there is no need to update 4716 * kvmclock on vcpu->cpu migration 4717 */ 4718 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1) 4719 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu); 4720 if (vcpu->cpu != cpu) 4721 kvm_make_request(KVM_REQ_MIGRATE_TIMER, vcpu); 4722 vcpu->cpu = cpu; 4723 } 4724 4725 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu); 4726 } 4727 4728 static void kvm_steal_time_set_preempted(struct kvm_vcpu *vcpu) 4729 { 4730 struct gfn_to_hva_cache *ghc = &vcpu->arch.st.cache; 4731 struct kvm_steal_time __user *st; 4732 struct kvm_memslots *slots; 4733 static const u8 preempted = KVM_VCPU_PREEMPTED; 4734 gpa_t gpa = vcpu->arch.st.msr_val & KVM_STEAL_VALID_BITS; 4735 4736 /* 4737 * The vCPU can be marked preempted if and only if the VM-Exit was on 4738 * an instruction boundary and will not trigger guest emulation of any 4739 * kind (see vcpu_run). Vendor specific code controls (conservatively) 4740 * when this is true, for example allowing the vCPU to be marked 4741 * preempted if and only if the VM-Exit was due to a host interrupt. 4742 */ 4743 if (!vcpu->arch.at_instruction_boundary) { 4744 vcpu->stat.preemption_other++; 4745 return; 4746 } 4747 4748 vcpu->stat.preemption_reported++; 4749 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED)) 4750 return; 4751 4752 if (vcpu->arch.st.preempted) 4753 return; 4754 4755 /* This happens on process exit */ 4756 if (unlikely(current->mm != vcpu->kvm->mm)) 4757 return; 4758 4759 slots = kvm_memslots(vcpu->kvm); 4760 4761 if (unlikely(slots->generation != ghc->generation || 4762 gpa != ghc->gpa || 4763 kvm_is_error_hva(ghc->hva) || !ghc->memslot)) 4764 return; 4765 4766 st = (struct kvm_steal_time __user *)ghc->hva; 4767 BUILD_BUG_ON(sizeof(st->preempted) != sizeof(preempted)); 4768 4769 if (!copy_to_user_nofault(&st->preempted, &preempted, sizeof(preempted))) 4770 vcpu->arch.st.preempted = KVM_VCPU_PREEMPTED; 4771 4772 mark_page_dirty_in_slot(vcpu->kvm, ghc->memslot, gpa_to_gfn(ghc->gpa)); 4773 } 4774 4775 void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu) 4776 { 4777 int idx; 4778 4779 if (vcpu->preempted) { 4780 if (!vcpu->arch.guest_state_protected) 4781 vcpu->arch.preempted_in_kernel = !static_call(kvm_x86_get_cpl)(vcpu); 4782 4783 /* 4784 * Take the srcu lock as memslots will be accessed to check the gfn 4785 * cache generation against the memslots generation. 4786 */ 4787 idx = srcu_read_lock(&vcpu->kvm->srcu); 4788 if (kvm_xen_msr_enabled(vcpu->kvm)) 4789 kvm_xen_runstate_set_preempted(vcpu); 4790 else 4791 kvm_steal_time_set_preempted(vcpu); 4792 srcu_read_unlock(&vcpu->kvm->srcu, idx); 4793 } 4794 4795 static_call(kvm_x86_vcpu_put)(vcpu); 4796 vcpu->arch.last_host_tsc = rdtsc(); 4797 } 4798 4799 static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu, 4800 struct kvm_lapic_state *s) 4801 { 4802 static_call_cond(kvm_x86_sync_pir_to_irr)(vcpu); 4803 4804 return kvm_apic_get_state(vcpu, s); 4805 } 4806 4807 static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu, 4808 struct kvm_lapic_state *s) 4809 { 4810 int r; 4811 4812 r = kvm_apic_set_state(vcpu, s); 4813 if (r) 4814 return r; 4815 update_cr8_intercept(vcpu); 4816 4817 return 0; 4818 } 4819 4820 static int kvm_cpu_accept_dm_intr(struct kvm_vcpu *vcpu) 4821 { 4822 /* 4823 * We can accept userspace's request for interrupt injection 4824 * as long as we have a place to store the interrupt number. 4825 * The actual injection will happen when the CPU is able to 4826 * deliver the interrupt. 4827 */ 4828 if (kvm_cpu_has_extint(vcpu)) 4829 return false; 4830 4831 /* Acknowledging ExtINT does not happen if LINT0 is masked. */ 4832 return (!lapic_in_kernel(vcpu) || 4833 kvm_apic_accept_pic_intr(vcpu)); 4834 } 4835 4836 static int kvm_vcpu_ready_for_interrupt_injection(struct kvm_vcpu *vcpu) 4837 { 4838 /* 4839 * Do not cause an interrupt window exit if an exception 4840 * is pending or an event needs reinjection; userspace 4841 * might want to inject the interrupt manually using KVM_SET_REGS 4842 * or KVM_SET_SREGS. For that to work, we must be at an 4843 * instruction boundary and with no events half-injected. 4844 */ 4845 return (kvm_arch_interrupt_allowed(vcpu) && 4846 kvm_cpu_accept_dm_intr(vcpu) && 4847 !kvm_event_needs_reinjection(vcpu) && 4848 !vcpu->arch.exception.pending); 4849 } 4850 4851 static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu, 4852 struct kvm_interrupt *irq) 4853 { 4854 if (irq->irq >= KVM_NR_INTERRUPTS) 4855 return -EINVAL; 4856 4857 if (!irqchip_in_kernel(vcpu->kvm)) { 4858 kvm_queue_interrupt(vcpu, irq->irq, false); 4859 kvm_make_request(KVM_REQ_EVENT, vcpu); 4860 return 0; 4861 } 4862 4863 /* 4864 * With in-kernel LAPIC, we only use this to inject EXTINT, so 4865 * fail for in-kernel 8259. 4866 */ 4867 if (pic_in_kernel(vcpu->kvm)) 4868 return -ENXIO; 4869 4870 if (vcpu->arch.pending_external_vector != -1) 4871 return -EEXIST; 4872 4873 vcpu->arch.pending_external_vector = irq->irq; 4874 kvm_make_request(KVM_REQ_EVENT, vcpu); 4875 return 0; 4876 } 4877 4878 static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu) 4879 { 4880 kvm_inject_nmi(vcpu); 4881 4882 return 0; 4883 } 4884 4885 static int kvm_vcpu_ioctl_smi(struct kvm_vcpu *vcpu) 4886 { 4887 kvm_make_request(KVM_REQ_SMI, vcpu); 4888 4889 return 0; 4890 } 4891 4892 static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu, 4893 struct kvm_tpr_access_ctl *tac) 4894 { 4895 if (tac->flags) 4896 return -EINVAL; 4897 vcpu->arch.tpr_access_reporting = !!tac->enabled; 4898 return 0; 4899 } 4900 4901 static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu, 4902 u64 mcg_cap) 4903 { 4904 int r; 4905 unsigned bank_num = mcg_cap & 0xff, bank; 4906 4907 r = -EINVAL; 4908 if (!bank_num || bank_num > KVM_MAX_MCE_BANKS) 4909 goto out; 4910 if (mcg_cap & ~(kvm_caps.supported_mce_cap | 0xff | 0xff0000)) 4911 goto out; 4912 r = 0; 4913 vcpu->arch.mcg_cap = mcg_cap; 4914 /* Init IA32_MCG_CTL to all 1s */ 4915 if (mcg_cap & MCG_CTL_P) 4916 vcpu->arch.mcg_ctl = ~(u64)0; 4917 /* Init IA32_MCi_CTL to all 1s, IA32_MCi_CTL2 to all 0s */ 4918 for (bank = 0; bank < bank_num; bank++) { 4919 vcpu->arch.mce_banks[bank*4] = ~(u64)0; 4920 if (mcg_cap & MCG_CMCI_P) 4921 vcpu->arch.mci_ctl2_banks[bank] = 0; 4922 } 4923 4924 kvm_apic_after_set_mcg_cap(vcpu); 4925 4926 static_call(kvm_x86_setup_mce)(vcpu); 4927 out: 4928 return r; 4929 } 4930 4931 /* 4932 * Validate this is an UCNA (uncorrectable no action) error by checking the 4933 * MCG_STATUS and MCi_STATUS registers: 4934 * - none of the bits for Machine Check Exceptions are set 4935 * - both the VAL (valid) and UC (uncorrectable) bits are set 4936 * MCI_STATUS_PCC - Processor Context Corrupted 4937 * MCI_STATUS_S - Signaled as a Machine Check Exception 4938 * MCI_STATUS_AR - Software recoverable Action Required 4939 */ 4940 static bool is_ucna(struct kvm_x86_mce *mce) 4941 { 4942 return !mce->mcg_status && 4943 !(mce->status & (MCI_STATUS_PCC | MCI_STATUS_S | MCI_STATUS_AR)) && 4944 (mce->status & MCI_STATUS_VAL) && 4945 (mce->status & MCI_STATUS_UC); 4946 } 4947 4948 static int kvm_vcpu_x86_set_ucna(struct kvm_vcpu *vcpu, struct kvm_x86_mce *mce, u64* banks) 4949 { 4950 u64 mcg_cap = vcpu->arch.mcg_cap; 4951 4952 banks[1] = mce->status; 4953 banks[2] = mce->addr; 4954 banks[3] = mce->misc; 4955 vcpu->arch.mcg_status = mce->mcg_status; 4956 4957 if (!(mcg_cap & MCG_CMCI_P) || 4958 !(vcpu->arch.mci_ctl2_banks[mce->bank] & MCI_CTL2_CMCI_EN)) 4959 return 0; 4960 4961 if (lapic_in_kernel(vcpu)) 4962 kvm_apic_local_deliver(vcpu->arch.apic, APIC_LVTCMCI); 4963 4964 return 0; 4965 } 4966 4967 static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu, 4968 struct kvm_x86_mce *mce) 4969 { 4970 u64 mcg_cap = vcpu->arch.mcg_cap; 4971 unsigned bank_num = mcg_cap & 0xff; 4972 u64 *banks = vcpu->arch.mce_banks; 4973 4974 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL)) 4975 return -EINVAL; 4976 4977 banks += array_index_nospec(4 * mce->bank, 4 * bank_num); 4978 4979 if (is_ucna(mce)) 4980 return kvm_vcpu_x86_set_ucna(vcpu, mce, banks); 4981 4982 /* 4983 * if IA32_MCG_CTL is not all 1s, the uncorrected error 4984 * reporting is disabled 4985 */ 4986 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) && 4987 vcpu->arch.mcg_ctl != ~(u64)0) 4988 return 0; 4989 /* 4990 * if IA32_MCi_CTL is not all 1s, the uncorrected error 4991 * reporting is disabled for the bank 4992 */ 4993 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0) 4994 return 0; 4995 if (mce->status & MCI_STATUS_UC) { 4996 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) || 4997 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) { 4998 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); 4999 return 0; 5000 } 5001 if (banks[1] & MCI_STATUS_VAL) 5002 mce->status |= MCI_STATUS_OVER; 5003 banks[2] = mce->addr; 5004 banks[3] = mce->misc; 5005 vcpu->arch.mcg_status = mce->mcg_status; 5006 banks[1] = mce->status; 5007 kvm_queue_exception(vcpu, MC_VECTOR); 5008 } else if (!(banks[1] & MCI_STATUS_VAL) 5009 || !(banks[1] & MCI_STATUS_UC)) { 5010 if (banks[1] & MCI_STATUS_VAL) 5011 mce->status |= MCI_STATUS_OVER; 5012 banks[2] = mce->addr; 5013 banks[3] = mce->misc; 5014 banks[1] = mce->status; 5015 } else 5016 banks[1] |= MCI_STATUS_OVER; 5017 return 0; 5018 } 5019 5020 static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu, 5021 struct kvm_vcpu_events *events) 5022 { 5023 process_nmi(vcpu); 5024 5025 if (kvm_check_request(KVM_REQ_SMI, vcpu)) 5026 process_smi(vcpu); 5027 5028 /* 5029 * In guest mode, payload delivery should be deferred, 5030 * so that the L1 hypervisor can intercept #PF before 5031 * CR2 is modified (or intercept #DB before DR6 is 5032 * modified under nVMX). Unless the per-VM capability, 5033 * KVM_CAP_EXCEPTION_PAYLOAD, is set, we may not defer the delivery of 5034 * an exception payload and handle after a KVM_GET_VCPU_EVENTS. Since we 5035 * opportunistically defer the exception payload, deliver it if the 5036 * capability hasn't been requested before processing a 5037 * KVM_GET_VCPU_EVENTS. 5038 */ 5039 if (!vcpu->kvm->arch.exception_payload_enabled && 5040 vcpu->arch.exception.pending && vcpu->arch.exception.has_payload) 5041 kvm_deliver_exception_payload(vcpu); 5042 5043 /* 5044 * The API doesn't provide the instruction length for software 5045 * exceptions, so don't report them. As long as the guest RIP 5046 * isn't advanced, we should expect to encounter the exception 5047 * again. 5048 */ 5049 if (kvm_exception_is_soft(vcpu->arch.exception.nr)) { 5050 events->exception.injected = 0; 5051 events->exception.pending = 0; 5052 } else { 5053 events->exception.injected = vcpu->arch.exception.injected; 5054 events->exception.pending = vcpu->arch.exception.pending; 5055 /* 5056 * For ABI compatibility, deliberately conflate 5057 * pending and injected exceptions when 5058 * KVM_CAP_EXCEPTION_PAYLOAD isn't enabled. 5059 */ 5060 if (!vcpu->kvm->arch.exception_payload_enabled) 5061 events->exception.injected |= 5062 vcpu->arch.exception.pending; 5063 } 5064 events->exception.nr = vcpu->arch.exception.nr; 5065 events->exception.has_error_code = vcpu->arch.exception.has_error_code; 5066 events->exception.error_code = vcpu->arch.exception.error_code; 5067 events->exception_has_payload = vcpu->arch.exception.has_payload; 5068 events->exception_payload = vcpu->arch.exception.payload; 5069 5070 events->interrupt.injected = 5071 vcpu->arch.interrupt.injected && !vcpu->arch.interrupt.soft; 5072 events->interrupt.nr = vcpu->arch.interrupt.nr; 5073 events->interrupt.soft = 0; 5074 events->interrupt.shadow = static_call(kvm_x86_get_interrupt_shadow)(vcpu); 5075 5076 events->nmi.injected = vcpu->arch.nmi_injected; 5077 events->nmi.pending = vcpu->arch.nmi_pending != 0; 5078 events->nmi.masked = static_call(kvm_x86_get_nmi_mask)(vcpu); 5079 events->nmi.pad = 0; 5080 5081 events->sipi_vector = 0; /* never valid when reporting to user space */ 5082 5083 events->smi.smm = is_smm(vcpu); 5084 events->smi.pending = vcpu->arch.smi_pending; 5085 events->smi.smm_inside_nmi = 5086 !!(vcpu->arch.hflags & HF_SMM_INSIDE_NMI_MASK); 5087 events->smi.latched_init = kvm_lapic_latched_init(vcpu); 5088 5089 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING 5090 | KVM_VCPUEVENT_VALID_SHADOW 5091 | KVM_VCPUEVENT_VALID_SMM); 5092 if (vcpu->kvm->arch.exception_payload_enabled) 5093 events->flags |= KVM_VCPUEVENT_VALID_PAYLOAD; 5094 if (vcpu->kvm->arch.triple_fault_event) { 5095 events->triple_fault.pending = kvm_test_request(KVM_REQ_TRIPLE_FAULT, vcpu); 5096 events->flags |= KVM_VCPUEVENT_VALID_TRIPLE_FAULT; 5097 } 5098 5099 memset(&events->reserved, 0, sizeof(events->reserved)); 5100 } 5101 5102 static void kvm_smm_changed(struct kvm_vcpu *vcpu, bool entering_smm); 5103 5104 static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu, 5105 struct kvm_vcpu_events *events) 5106 { 5107 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING 5108 | KVM_VCPUEVENT_VALID_SIPI_VECTOR 5109 | KVM_VCPUEVENT_VALID_SHADOW 5110 | KVM_VCPUEVENT_VALID_SMM 5111 | KVM_VCPUEVENT_VALID_PAYLOAD 5112 | KVM_VCPUEVENT_VALID_TRIPLE_FAULT)) 5113 return -EINVAL; 5114 5115 if (events->flags & KVM_VCPUEVENT_VALID_PAYLOAD) { 5116 if (!vcpu->kvm->arch.exception_payload_enabled) 5117 return -EINVAL; 5118 if (events->exception.pending) 5119 events->exception.injected = 0; 5120 else 5121 events->exception_has_payload = 0; 5122 } else { 5123 events->exception.pending = 0; 5124 events->exception_has_payload = 0; 5125 } 5126 5127 if ((events->exception.injected || events->exception.pending) && 5128 (events->exception.nr > 31 || events->exception.nr == NMI_VECTOR)) 5129 return -EINVAL; 5130 5131 /* INITs are latched while in SMM */ 5132 if (events->flags & KVM_VCPUEVENT_VALID_SMM && 5133 (events->smi.smm || events->smi.pending) && 5134 vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) 5135 return -EINVAL; 5136 5137 process_nmi(vcpu); 5138 vcpu->arch.exception.injected = events->exception.injected; 5139 vcpu->arch.exception.pending = events->exception.pending; 5140 vcpu->arch.exception.nr = events->exception.nr; 5141 vcpu->arch.exception.has_error_code = events->exception.has_error_code; 5142 vcpu->arch.exception.error_code = events->exception.error_code; 5143 vcpu->arch.exception.has_payload = events->exception_has_payload; 5144 vcpu->arch.exception.payload = events->exception_payload; 5145 5146 vcpu->arch.interrupt.injected = events->interrupt.injected; 5147 vcpu->arch.interrupt.nr = events->interrupt.nr; 5148 vcpu->arch.interrupt.soft = events->interrupt.soft; 5149 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW) 5150 static_call(kvm_x86_set_interrupt_shadow)(vcpu, 5151 events->interrupt.shadow); 5152 5153 vcpu->arch.nmi_injected = events->nmi.injected; 5154 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING) 5155 vcpu->arch.nmi_pending = events->nmi.pending; 5156 static_call(kvm_x86_set_nmi_mask)(vcpu, events->nmi.masked); 5157 5158 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR && 5159 lapic_in_kernel(vcpu)) 5160 vcpu->arch.apic->sipi_vector = events->sipi_vector; 5161 5162 if (events->flags & KVM_VCPUEVENT_VALID_SMM) { 5163 if (!!(vcpu->arch.hflags & HF_SMM_MASK) != events->smi.smm) { 5164 kvm_x86_ops.nested_ops->leave_nested(vcpu); 5165 kvm_smm_changed(vcpu, events->smi.smm); 5166 } 5167 5168 vcpu->arch.smi_pending = events->smi.pending; 5169 5170 if (events->smi.smm) { 5171 if (events->smi.smm_inside_nmi) 5172 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK; 5173 else 5174 vcpu->arch.hflags &= ~HF_SMM_INSIDE_NMI_MASK; 5175 } 5176 5177 if (lapic_in_kernel(vcpu)) { 5178 if (events->smi.latched_init) 5179 set_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events); 5180 else 5181 clear_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events); 5182 } 5183 } 5184 5185 if (events->flags & KVM_VCPUEVENT_VALID_TRIPLE_FAULT) { 5186 if (!vcpu->kvm->arch.triple_fault_event) 5187 return -EINVAL; 5188 if (events->triple_fault.pending) 5189 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); 5190 else 5191 kvm_clear_request(KVM_REQ_TRIPLE_FAULT, vcpu); 5192 } 5193 5194 kvm_make_request(KVM_REQ_EVENT, vcpu); 5195 5196 return 0; 5197 } 5198 5199 static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu, 5200 struct kvm_debugregs *dbgregs) 5201 { 5202 unsigned long val; 5203 5204 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db)); 5205 kvm_get_dr(vcpu, 6, &val); 5206 dbgregs->dr6 = val; 5207 dbgregs->dr7 = vcpu->arch.dr7; 5208 dbgregs->flags = 0; 5209 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved)); 5210 } 5211 5212 static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu, 5213 struct kvm_debugregs *dbgregs) 5214 { 5215 if (dbgregs->flags) 5216 return -EINVAL; 5217 5218 if (!kvm_dr6_valid(dbgregs->dr6)) 5219 return -EINVAL; 5220 if (!kvm_dr7_valid(dbgregs->dr7)) 5221 return -EINVAL; 5222 5223 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db)); 5224 kvm_update_dr0123(vcpu); 5225 vcpu->arch.dr6 = dbgregs->dr6; 5226 vcpu->arch.dr7 = dbgregs->dr7; 5227 kvm_update_dr7(vcpu); 5228 5229 return 0; 5230 } 5231 5232 static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu, 5233 struct kvm_xsave *guest_xsave) 5234 { 5235 if (fpstate_is_confidential(&vcpu->arch.guest_fpu)) 5236 return; 5237 5238 fpu_copy_guest_fpstate_to_uabi(&vcpu->arch.guest_fpu, 5239 guest_xsave->region, 5240 sizeof(guest_xsave->region), 5241 vcpu->arch.pkru); 5242 } 5243 5244 static void kvm_vcpu_ioctl_x86_get_xsave2(struct kvm_vcpu *vcpu, 5245 u8 *state, unsigned int size) 5246 { 5247 if (fpstate_is_confidential(&vcpu->arch.guest_fpu)) 5248 return; 5249 5250 fpu_copy_guest_fpstate_to_uabi(&vcpu->arch.guest_fpu, 5251 state, size, vcpu->arch.pkru); 5252 } 5253 5254 static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu, 5255 struct kvm_xsave *guest_xsave) 5256 { 5257 if (fpstate_is_confidential(&vcpu->arch.guest_fpu)) 5258 return 0; 5259 5260 return fpu_copy_uabi_to_guest_fpstate(&vcpu->arch.guest_fpu, 5261 guest_xsave->region, 5262 kvm_caps.supported_xcr0, 5263 &vcpu->arch.pkru); 5264 } 5265 5266 static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu, 5267 struct kvm_xcrs *guest_xcrs) 5268 { 5269 if (!boot_cpu_has(X86_FEATURE_XSAVE)) { 5270 guest_xcrs->nr_xcrs = 0; 5271 return; 5272 } 5273 5274 guest_xcrs->nr_xcrs = 1; 5275 guest_xcrs->flags = 0; 5276 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK; 5277 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0; 5278 } 5279 5280 static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu, 5281 struct kvm_xcrs *guest_xcrs) 5282 { 5283 int i, r = 0; 5284 5285 if (!boot_cpu_has(X86_FEATURE_XSAVE)) 5286 return -EINVAL; 5287 5288 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags) 5289 return -EINVAL; 5290 5291 for (i = 0; i < guest_xcrs->nr_xcrs; i++) 5292 /* Only support XCR0 currently */ 5293 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) { 5294 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK, 5295 guest_xcrs->xcrs[i].value); 5296 break; 5297 } 5298 if (r) 5299 r = -EINVAL; 5300 return r; 5301 } 5302 5303 /* 5304 * kvm_set_guest_paused() indicates to the guest kernel that it has been 5305 * stopped by the hypervisor. This function will be called from the host only. 5306 * EINVAL is returned when the host attempts to set the flag for a guest that 5307 * does not support pv clocks. 5308 */ 5309 static int kvm_set_guest_paused(struct kvm_vcpu *vcpu) 5310 { 5311 if (!vcpu->arch.pv_time.active) 5312 return -EINVAL; 5313 vcpu->arch.pvclock_set_guest_stopped_request = true; 5314 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 5315 return 0; 5316 } 5317 5318 static int kvm_arch_tsc_has_attr(struct kvm_vcpu *vcpu, 5319 struct kvm_device_attr *attr) 5320 { 5321 int r; 5322 5323 switch (attr->attr) { 5324 case KVM_VCPU_TSC_OFFSET: 5325 r = 0; 5326 break; 5327 default: 5328 r = -ENXIO; 5329 } 5330 5331 return r; 5332 } 5333 5334 static int kvm_arch_tsc_get_attr(struct kvm_vcpu *vcpu, 5335 struct kvm_device_attr *attr) 5336 { 5337 u64 __user *uaddr = kvm_get_attr_addr(attr); 5338 int r; 5339 5340 if (IS_ERR(uaddr)) 5341 return PTR_ERR(uaddr); 5342 5343 switch (attr->attr) { 5344 case KVM_VCPU_TSC_OFFSET: 5345 r = -EFAULT; 5346 if (put_user(vcpu->arch.l1_tsc_offset, uaddr)) 5347 break; 5348 r = 0; 5349 break; 5350 default: 5351 r = -ENXIO; 5352 } 5353 5354 return r; 5355 } 5356 5357 static int kvm_arch_tsc_set_attr(struct kvm_vcpu *vcpu, 5358 struct kvm_device_attr *attr) 5359 { 5360 u64 __user *uaddr = kvm_get_attr_addr(attr); 5361 struct kvm *kvm = vcpu->kvm; 5362 int r; 5363 5364 if (IS_ERR(uaddr)) 5365 return PTR_ERR(uaddr); 5366 5367 switch (attr->attr) { 5368 case KVM_VCPU_TSC_OFFSET: { 5369 u64 offset, tsc, ns; 5370 unsigned long flags; 5371 bool matched; 5372 5373 r = -EFAULT; 5374 if (get_user(offset, uaddr)) 5375 break; 5376 5377 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags); 5378 5379 matched = (vcpu->arch.virtual_tsc_khz && 5380 kvm->arch.last_tsc_khz == vcpu->arch.virtual_tsc_khz && 5381 kvm->arch.last_tsc_offset == offset); 5382 5383 tsc = kvm_scale_tsc(rdtsc(), vcpu->arch.l1_tsc_scaling_ratio) + offset; 5384 ns = get_kvmclock_base_ns(); 5385 5386 __kvm_synchronize_tsc(vcpu, offset, tsc, ns, matched); 5387 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags); 5388 5389 r = 0; 5390 break; 5391 } 5392 default: 5393 r = -ENXIO; 5394 } 5395 5396 return r; 5397 } 5398 5399 static int kvm_vcpu_ioctl_device_attr(struct kvm_vcpu *vcpu, 5400 unsigned int ioctl, 5401 void __user *argp) 5402 { 5403 struct kvm_device_attr attr; 5404 int r; 5405 5406 if (copy_from_user(&attr, argp, sizeof(attr))) 5407 return -EFAULT; 5408 5409 if (attr.group != KVM_VCPU_TSC_CTRL) 5410 return -ENXIO; 5411 5412 switch (ioctl) { 5413 case KVM_HAS_DEVICE_ATTR: 5414 r = kvm_arch_tsc_has_attr(vcpu, &attr); 5415 break; 5416 case KVM_GET_DEVICE_ATTR: 5417 r = kvm_arch_tsc_get_attr(vcpu, &attr); 5418 break; 5419 case KVM_SET_DEVICE_ATTR: 5420 r = kvm_arch_tsc_set_attr(vcpu, &attr); 5421 break; 5422 } 5423 5424 return r; 5425 } 5426 5427 static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu, 5428 struct kvm_enable_cap *cap) 5429 { 5430 int r; 5431 uint16_t vmcs_version; 5432 void __user *user_ptr; 5433 5434 if (cap->flags) 5435 return -EINVAL; 5436 5437 switch (cap->cap) { 5438 case KVM_CAP_HYPERV_SYNIC2: 5439 if (cap->args[0]) 5440 return -EINVAL; 5441 fallthrough; 5442 5443 case KVM_CAP_HYPERV_SYNIC: 5444 if (!irqchip_in_kernel(vcpu->kvm)) 5445 return -EINVAL; 5446 return kvm_hv_activate_synic(vcpu, cap->cap == 5447 KVM_CAP_HYPERV_SYNIC2); 5448 case KVM_CAP_HYPERV_ENLIGHTENED_VMCS: 5449 if (!kvm_x86_ops.nested_ops->enable_evmcs) 5450 return -ENOTTY; 5451 r = kvm_x86_ops.nested_ops->enable_evmcs(vcpu, &vmcs_version); 5452 if (!r) { 5453 user_ptr = (void __user *)(uintptr_t)cap->args[0]; 5454 if (copy_to_user(user_ptr, &vmcs_version, 5455 sizeof(vmcs_version))) 5456 r = -EFAULT; 5457 } 5458 return r; 5459 case KVM_CAP_HYPERV_DIRECT_TLBFLUSH: 5460 if (!kvm_x86_ops.enable_direct_tlbflush) 5461 return -ENOTTY; 5462 5463 return static_call(kvm_x86_enable_direct_tlbflush)(vcpu); 5464 5465 case KVM_CAP_HYPERV_ENFORCE_CPUID: 5466 return kvm_hv_set_enforce_cpuid(vcpu, cap->args[0]); 5467 5468 case KVM_CAP_ENFORCE_PV_FEATURE_CPUID: 5469 vcpu->arch.pv_cpuid.enforce = cap->args[0]; 5470 if (vcpu->arch.pv_cpuid.enforce) 5471 kvm_update_pv_runtime(vcpu); 5472 5473 return 0; 5474 default: 5475 return -EINVAL; 5476 } 5477 } 5478 5479 long kvm_arch_vcpu_ioctl(struct file *filp, 5480 unsigned int ioctl, unsigned long arg) 5481 { 5482 struct kvm_vcpu *vcpu = filp->private_data; 5483 void __user *argp = (void __user *)arg; 5484 int r; 5485 union { 5486 struct kvm_sregs2 *sregs2; 5487 struct kvm_lapic_state *lapic; 5488 struct kvm_xsave *xsave; 5489 struct kvm_xcrs *xcrs; 5490 void *buffer; 5491 } u; 5492 5493 vcpu_load(vcpu); 5494 5495 u.buffer = NULL; 5496 switch (ioctl) { 5497 case KVM_GET_LAPIC: { 5498 r = -EINVAL; 5499 if (!lapic_in_kernel(vcpu)) 5500 goto out; 5501 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), 5502 GFP_KERNEL_ACCOUNT); 5503 5504 r = -ENOMEM; 5505 if (!u.lapic) 5506 goto out; 5507 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic); 5508 if (r) 5509 goto out; 5510 r = -EFAULT; 5511 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state))) 5512 goto out; 5513 r = 0; 5514 break; 5515 } 5516 case KVM_SET_LAPIC: { 5517 r = -EINVAL; 5518 if (!lapic_in_kernel(vcpu)) 5519 goto out; 5520 u.lapic = memdup_user(argp, sizeof(*u.lapic)); 5521 if (IS_ERR(u.lapic)) { 5522 r = PTR_ERR(u.lapic); 5523 goto out_nofree; 5524 } 5525 5526 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic); 5527 break; 5528 } 5529 case KVM_INTERRUPT: { 5530 struct kvm_interrupt irq; 5531 5532 r = -EFAULT; 5533 if (copy_from_user(&irq, argp, sizeof(irq))) 5534 goto out; 5535 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq); 5536 break; 5537 } 5538 case KVM_NMI: { 5539 r = kvm_vcpu_ioctl_nmi(vcpu); 5540 break; 5541 } 5542 case KVM_SMI: { 5543 r = kvm_vcpu_ioctl_smi(vcpu); 5544 break; 5545 } 5546 case KVM_SET_CPUID: { 5547 struct kvm_cpuid __user *cpuid_arg = argp; 5548 struct kvm_cpuid cpuid; 5549 5550 r = -EFAULT; 5551 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid))) 5552 goto out; 5553 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries); 5554 break; 5555 } 5556 case KVM_SET_CPUID2: { 5557 struct kvm_cpuid2 __user *cpuid_arg = argp; 5558 struct kvm_cpuid2 cpuid; 5559 5560 r = -EFAULT; 5561 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid))) 5562 goto out; 5563 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid, 5564 cpuid_arg->entries); 5565 break; 5566 } 5567 case KVM_GET_CPUID2: { 5568 struct kvm_cpuid2 __user *cpuid_arg = argp; 5569 struct kvm_cpuid2 cpuid; 5570 5571 r = -EFAULT; 5572 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid))) 5573 goto out; 5574 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid, 5575 cpuid_arg->entries); 5576 if (r) 5577 goto out; 5578 r = -EFAULT; 5579 if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid))) 5580 goto out; 5581 r = 0; 5582 break; 5583 } 5584 case KVM_GET_MSRS: { 5585 int idx = srcu_read_lock(&vcpu->kvm->srcu); 5586 r = msr_io(vcpu, argp, do_get_msr, 1); 5587 srcu_read_unlock(&vcpu->kvm->srcu, idx); 5588 break; 5589 } 5590 case KVM_SET_MSRS: { 5591 int idx = srcu_read_lock(&vcpu->kvm->srcu); 5592 r = msr_io(vcpu, argp, do_set_msr, 0); 5593 srcu_read_unlock(&vcpu->kvm->srcu, idx); 5594 break; 5595 } 5596 case KVM_TPR_ACCESS_REPORTING: { 5597 struct kvm_tpr_access_ctl tac; 5598 5599 r = -EFAULT; 5600 if (copy_from_user(&tac, argp, sizeof(tac))) 5601 goto out; 5602 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac); 5603 if (r) 5604 goto out; 5605 r = -EFAULT; 5606 if (copy_to_user(argp, &tac, sizeof(tac))) 5607 goto out; 5608 r = 0; 5609 break; 5610 }; 5611 case KVM_SET_VAPIC_ADDR: { 5612 struct kvm_vapic_addr va; 5613 int idx; 5614 5615 r = -EINVAL; 5616 if (!lapic_in_kernel(vcpu)) 5617 goto out; 5618 r = -EFAULT; 5619 if (copy_from_user(&va, argp, sizeof(va))) 5620 goto out; 5621 idx = srcu_read_lock(&vcpu->kvm->srcu); 5622 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr); 5623 srcu_read_unlock(&vcpu->kvm->srcu, idx); 5624 break; 5625 } 5626 case KVM_X86_SETUP_MCE: { 5627 u64 mcg_cap; 5628 5629 r = -EFAULT; 5630 if (copy_from_user(&mcg_cap, argp, sizeof(mcg_cap))) 5631 goto out; 5632 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap); 5633 break; 5634 } 5635 case KVM_X86_SET_MCE: { 5636 struct kvm_x86_mce mce; 5637 5638 r = -EFAULT; 5639 if (copy_from_user(&mce, argp, sizeof(mce))) 5640 goto out; 5641 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce); 5642 break; 5643 } 5644 case KVM_GET_VCPU_EVENTS: { 5645 struct kvm_vcpu_events events; 5646 5647 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events); 5648 5649 r = -EFAULT; 5650 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events))) 5651 break; 5652 r = 0; 5653 break; 5654 } 5655 case KVM_SET_VCPU_EVENTS: { 5656 struct kvm_vcpu_events events; 5657 5658 r = -EFAULT; 5659 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events))) 5660 break; 5661 5662 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events); 5663 break; 5664 } 5665 case KVM_GET_DEBUGREGS: { 5666 struct kvm_debugregs dbgregs; 5667 5668 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs); 5669 5670 r = -EFAULT; 5671 if (copy_to_user(argp, &dbgregs, 5672 sizeof(struct kvm_debugregs))) 5673 break; 5674 r = 0; 5675 break; 5676 } 5677 case KVM_SET_DEBUGREGS: { 5678 struct kvm_debugregs dbgregs; 5679 5680 r = -EFAULT; 5681 if (copy_from_user(&dbgregs, argp, 5682 sizeof(struct kvm_debugregs))) 5683 break; 5684 5685 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs); 5686 break; 5687 } 5688 case KVM_GET_XSAVE: { 5689 r = -EINVAL; 5690 if (vcpu->arch.guest_fpu.uabi_size > sizeof(struct kvm_xsave)) 5691 break; 5692 5693 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL_ACCOUNT); 5694 r = -ENOMEM; 5695 if (!u.xsave) 5696 break; 5697 5698 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave); 5699 5700 r = -EFAULT; 5701 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave))) 5702 break; 5703 r = 0; 5704 break; 5705 } 5706 case KVM_SET_XSAVE: { 5707 int size = vcpu->arch.guest_fpu.uabi_size; 5708 5709 u.xsave = memdup_user(argp, size); 5710 if (IS_ERR(u.xsave)) { 5711 r = PTR_ERR(u.xsave); 5712 goto out_nofree; 5713 } 5714 5715 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave); 5716 break; 5717 } 5718 5719 case KVM_GET_XSAVE2: { 5720 int size = vcpu->arch.guest_fpu.uabi_size; 5721 5722 u.xsave = kzalloc(size, GFP_KERNEL_ACCOUNT); 5723 r = -ENOMEM; 5724 if (!u.xsave) 5725 break; 5726 5727 kvm_vcpu_ioctl_x86_get_xsave2(vcpu, u.buffer, size); 5728 5729 r = -EFAULT; 5730 if (copy_to_user(argp, u.xsave, size)) 5731 break; 5732 5733 r = 0; 5734 break; 5735 } 5736 5737 case KVM_GET_XCRS: { 5738 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL_ACCOUNT); 5739 r = -ENOMEM; 5740 if (!u.xcrs) 5741 break; 5742 5743 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs); 5744 5745 r = -EFAULT; 5746 if (copy_to_user(argp, u.xcrs, 5747 sizeof(struct kvm_xcrs))) 5748 break; 5749 r = 0; 5750 break; 5751 } 5752 case KVM_SET_XCRS: { 5753 u.xcrs = memdup_user(argp, sizeof(*u.xcrs)); 5754 if (IS_ERR(u.xcrs)) { 5755 r = PTR_ERR(u.xcrs); 5756 goto out_nofree; 5757 } 5758 5759 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs); 5760 break; 5761 } 5762 case KVM_SET_TSC_KHZ: { 5763 u32 user_tsc_khz; 5764 5765 r = -EINVAL; 5766 user_tsc_khz = (u32)arg; 5767 5768 if (kvm_caps.has_tsc_control && 5769 user_tsc_khz >= kvm_caps.max_guest_tsc_khz) 5770 goto out; 5771 5772 if (user_tsc_khz == 0) 5773 user_tsc_khz = tsc_khz; 5774 5775 if (!kvm_set_tsc_khz(vcpu, user_tsc_khz)) 5776 r = 0; 5777 5778 goto out; 5779 } 5780 case KVM_GET_TSC_KHZ: { 5781 r = vcpu->arch.virtual_tsc_khz; 5782 goto out; 5783 } 5784 case KVM_KVMCLOCK_CTRL: { 5785 r = kvm_set_guest_paused(vcpu); 5786 goto out; 5787 } 5788 case KVM_ENABLE_CAP: { 5789 struct kvm_enable_cap cap; 5790 5791 r = -EFAULT; 5792 if (copy_from_user(&cap, argp, sizeof(cap))) 5793 goto out; 5794 r = kvm_vcpu_ioctl_enable_cap(vcpu, &cap); 5795 break; 5796 } 5797 case KVM_GET_NESTED_STATE: { 5798 struct kvm_nested_state __user *user_kvm_nested_state = argp; 5799 u32 user_data_size; 5800 5801 r = -EINVAL; 5802 if (!kvm_x86_ops.nested_ops->get_state) 5803 break; 5804 5805 BUILD_BUG_ON(sizeof(user_data_size) != sizeof(user_kvm_nested_state->size)); 5806 r = -EFAULT; 5807 if (get_user(user_data_size, &user_kvm_nested_state->size)) 5808 break; 5809 5810 r = kvm_x86_ops.nested_ops->get_state(vcpu, user_kvm_nested_state, 5811 user_data_size); 5812 if (r < 0) 5813 break; 5814 5815 if (r > user_data_size) { 5816 if (put_user(r, &user_kvm_nested_state->size)) 5817 r = -EFAULT; 5818 else 5819 r = -E2BIG; 5820 break; 5821 } 5822 5823 r = 0; 5824 break; 5825 } 5826 case KVM_SET_NESTED_STATE: { 5827 struct kvm_nested_state __user *user_kvm_nested_state = argp; 5828 struct kvm_nested_state kvm_state; 5829 int idx; 5830 5831 r = -EINVAL; 5832 if (!kvm_x86_ops.nested_ops->set_state) 5833 break; 5834 5835 r = -EFAULT; 5836 if (copy_from_user(&kvm_state, user_kvm_nested_state, sizeof(kvm_state))) 5837 break; 5838 5839 r = -EINVAL; 5840 if (kvm_state.size < sizeof(kvm_state)) 5841 break; 5842 5843 if (kvm_state.flags & 5844 ~(KVM_STATE_NESTED_RUN_PENDING | KVM_STATE_NESTED_GUEST_MODE 5845 | KVM_STATE_NESTED_EVMCS | KVM_STATE_NESTED_MTF_PENDING 5846 | KVM_STATE_NESTED_GIF_SET)) 5847 break; 5848 5849 /* nested_run_pending implies guest_mode. */ 5850 if ((kvm_state.flags & KVM_STATE_NESTED_RUN_PENDING) 5851 && !(kvm_state.flags & KVM_STATE_NESTED_GUEST_MODE)) 5852 break; 5853 5854 idx = srcu_read_lock(&vcpu->kvm->srcu); 5855 r = kvm_x86_ops.nested_ops->set_state(vcpu, user_kvm_nested_state, &kvm_state); 5856 srcu_read_unlock(&vcpu->kvm->srcu, idx); 5857 break; 5858 } 5859 case KVM_GET_SUPPORTED_HV_CPUID: 5860 r = kvm_ioctl_get_supported_hv_cpuid(vcpu, argp); 5861 break; 5862 #ifdef CONFIG_KVM_XEN 5863 case KVM_XEN_VCPU_GET_ATTR: { 5864 struct kvm_xen_vcpu_attr xva; 5865 5866 r = -EFAULT; 5867 if (copy_from_user(&xva, argp, sizeof(xva))) 5868 goto out; 5869 r = kvm_xen_vcpu_get_attr(vcpu, &xva); 5870 if (!r && copy_to_user(argp, &xva, sizeof(xva))) 5871 r = -EFAULT; 5872 break; 5873 } 5874 case KVM_XEN_VCPU_SET_ATTR: { 5875 struct kvm_xen_vcpu_attr xva; 5876 5877 r = -EFAULT; 5878 if (copy_from_user(&xva, argp, sizeof(xva))) 5879 goto out; 5880 r = kvm_xen_vcpu_set_attr(vcpu, &xva); 5881 break; 5882 } 5883 #endif 5884 case KVM_GET_SREGS2: { 5885 u.sregs2 = kzalloc(sizeof(struct kvm_sregs2), GFP_KERNEL); 5886 r = -ENOMEM; 5887 if (!u.sregs2) 5888 goto out; 5889 __get_sregs2(vcpu, u.sregs2); 5890 r = -EFAULT; 5891 if (copy_to_user(argp, u.sregs2, sizeof(struct kvm_sregs2))) 5892 goto out; 5893 r = 0; 5894 break; 5895 } 5896 case KVM_SET_SREGS2: { 5897 u.sregs2 = memdup_user(argp, sizeof(struct kvm_sregs2)); 5898 if (IS_ERR(u.sregs2)) { 5899 r = PTR_ERR(u.sregs2); 5900 u.sregs2 = NULL; 5901 goto out; 5902 } 5903 r = __set_sregs2(vcpu, u.sregs2); 5904 break; 5905 } 5906 case KVM_HAS_DEVICE_ATTR: 5907 case KVM_GET_DEVICE_ATTR: 5908 case KVM_SET_DEVICE_ATTR: 5909 r = kvm_vcpu_ioctl_device_attr(vcpu, ioctl, argp); 5910 break; 5911 default: 5912 r = -EINVAL; 5913 } 5914 out: 5915 kfree(u.buffer); 5916 out_nofree: 5917 vcpu_put(vcpu); 5918 return r; 5919 } 5920 5921 vm_fault_t kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf) 5922 { 5923 return VM_FAULT_SIGBUS; 5924 } 5925 5926 static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr) 5927 { 5928 int ret; 5929 5930 if (addr > (unsigned int)(-3 * PAGE_SIZE)) 5931 return -EINVAL; 5932 ret = static_call(kvm_x86_set_tss_addr)(kvm, addr); 5933 return ret; 5934 } 5935 5936 static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm, 5937 u64 ident_addr) 5938 { 5939 return static_call(kvm_x86_set_identity_map_addr)(kvm, ident_addr); 5940 } 5941 5942 static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm, 5943 unsigned long kvm_nr_mmu_pages) 5944 { 5945 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES) 5946 return -EINVAL; 5947 5948 mutex_lock(&kvm->slots_lock); 5949 5950 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages); 5951 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages; 5952 5953 mutex_unlock(&kvm->slots_lock); 5954 return 0; 5955 } 5956 5957 static unsigned long kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm) 5958 { 5959 return kvm->arch.n_max_mmu_pages; 5960 } 5961 5962 static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip) 5963 { 5964 struct kvm_pic *pic = kvm->arch.vpic; 5965 int r; 5966 5967 r = 0; 5968 switch (chip->chip_id) { 5969 case KVM_IRQCHIP_PIC_MASTER: 5970 memcpy(&chip->chip.pic, &pic->pics[0], 5971 sizeof(struct kvm_pic_state)); 5972 break; 5973 case KVM_IRQCHIP_PIC_SLAVE: 5974 memcpy(&chip->chip.pic, &pic->pics[1], 5975 sizeof(struct kvm_pic_state)); 5976 break; 5977 case KVM_IRQCHIP_IOAPIC: 5978 kvm_get_ioapic(kvm, &chip->chip.ioapic); 5979 break; 5980 default: 5981 r = -EINVAL; 5982 break; 5983 } 5984 return r; 5985 } 5986 5987 static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip) 5988 { 5989 struct kvm_pic *pic = kvm->arch.vpic; 5990 int r; 5991 5992 r = 0; 5993 switch (chip->chip_id) { 5994 case KVM_IRQCHIP_PIC_MASTER: 5995 spin_lock(&pic->lock); 5996 memcpy(&pic->pics[0], &chip->chip.pic, 5997 sizeof(struct kvm_pic_state)); 5998 spin_unlock(&pic->lock); 5999 break; 6000 case KVM_IRQCHIP_PIC_SLAVE: 6001 spin_lock(&pic->lock); 6002 memcpy(&pic->pics[1], &chip->chip.pic, 6003 sizeof(struct kvm_pic_state)); 6004 spin_unlock(&pic->lock); 6005 break; 6006 case KVM_IRQCHIP_IOAPIC: 6007 kvm_set_ioapic(kvm, &chip->chip.ioapic); 6008 break; 6009 default: 6010 r = -EINVAL; 6011 break; 6012 } 6013 kvm_pic_update_irq(pic); 6014 return r; 6015 } 6016 6017 static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps) 6018 { 6019 struct kvm_kpit_state *kps = &kvm->arch.vpit->pit_state; 6020 6021 BUILD_BUG_ON(sizeof(*ps) != sizeof(kps->channels)); 6022 6023 mutex_lock(&kps->lock); 6024 memcpy(ps, &kps->channels, sizeof(*ps)); 6025 mutex_unlock(&kps->lock); 6026 return 0; 6027 } 6028 6029 static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps) 6030 { 6031 int i; 6032 struct kvm_pit *pit = kvm->arch.vpit; 6033 6034 mutex_lock(&pit->pit_state.lock); 6035 memcpy(&pit->pit_state.channels, ps, sizeof(*ps)); 6036 for (i = 0; i < 3; i++) 6037 kvm_pit_load_count(pit, i, ps->channels[i].count, 0); 6038 mutex_unlock(&pit->pit_state.lock); 6039 return 0; 6040 } 6041 6042 static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps) 6043 { 6044 mutex_lock(&kvm->arch.vpit->pit_state.lock); 6045 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels, 6046 sizeof(ps->channels)); 6047 ps->flags = kvm->arch.vpit->pit_state.flags; 6048 mutex_unlock(&kvm->arch.vpit->pit_state.lock); 6049 memset(&ps->reserved, 0, sizeof(ps->reserved)); 6050 return 0; 6051 } 6052 6053 static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps) 6054 { 6055 int start = 0; 6056 int i; 6057 u32 prev_legacy, cur_legacy; 6058 struct kvm_pit *pit = kvm->arch.vpit; 6059 6060 mutex_lock(&pit->pit_state.lock); 6061 prev_legacy = pit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY; 6062 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY; 6063 if (!prev_legacy && cur_legacy) 6064 start = 1; 6065 memcpy(&pit->pit_state.channels, &ps->channels, 6066 sizeof(pit->pit_state.channels)); 6067 pit->pit_state.flags = ps->flags; 6068 for (i = 0; i < 3; i++) 6069 kvm_pit_load_count(pit, i, pit->pit_state.channels[i].count, 6070 start && i == 0); 6071 mutex_unlock(&pit->pit_state.lock); 6072 return 0; 6073 } 6074 6075 static int kvm_vm_ioctl_reinject(struct kvm *kvm, 6076 struct kvm_reinject_control *control) 6077 { 6078 struct kvm_pit *pit = kvm->arch.vpit; 6079 6080 /* pit->pit_state.lock was overloaded to prevent userspace from getting 6081 * an inconsistent state after running multiple KVM_REINJECT_CONTROL 6082 * ioctls in parallel. Use a separate lock if that ioctl isn't rare. 6083 */ 6084 mutex_lock(&pit->pit_state.lock); 6085 kvm_pit_set_reinject(pit, control->pit_reinject); 6086 mutex_unlock(&pit->pit_state.lock); 6087 6088 return 0; 6089 } 6090 6091 void kvm_arch_sync_dirty_log(struct kvm *kvm, struct kvm_memory_slot *memslot) 6092 { 6093 6094 /* 6095 * Flush all CPUs' dirty log buffers to the dirty_bitmap. Called 6096 * before reporting dirty_bitmap to userspace. KVM flushes the buffers 6097 * on all VM-Exits, thus we only need to kick running vCPUs to force a 6098 * VM-Exit. 6099 */ 6100 struct kvm_vcpu *vcpu; 6101 unsigned long i; 6102 6103 kvm_for_each_vcpu(i, vcpu, kvm) 6104 kvm_vcpu_kick(vcpu); 6105 } 6106 6107 int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event, 6108 bool line_status) 6109 { 6110 if (!irqchip_in_kernel(kvm)) 6111 return -ENXIO; 6112 6113 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID, 6114 irq_event->irq, irq_event->level, 6115 line_status); 6116 return 0; 6117 } 6118 6119 int kvm_vm_ioctl_enable_cap(struct kvm *kvm, 6120 struct kvm_enable_cap *cap) 6121 { 6122 int r; 6123 6124 if (cap->flags) 6125 return -EINVAL; 6126 6127 switch (cap->cap) { 6128 case KVM_CAP_DISABLE_QUIRKS2: 6129 r = -EINVAL; 6130 if (cap->args[0] & ~KVM_X86_VALID_QUIRKS) 6131 break; 6132 fallthrough; 6133 case KVM_CAP_DISABLE_QUIRKS: 6134 kvm->arch.disabled_quirks = cap->args[0]; 6135 r = 0; 6136 break; 6137 case KVM_CAP_SPLIT_IRQCHIP: { 6138 mutex_lock(&kvm->lock); 6139 r = -EINVAL; 6140 if (cap->args[0] > MAX_NR_RESERVED_IOAPIC_PINS) 6141 goto split_irqchip_unlock; 6142 r = -EEXIST; 6143 if (irqchip_in_kernel(kvm)) 6144 goto split_irqchip_unlock; 6145 if (kvm->created_vcpus) 6146 goto split_irqchip_unlock; 6147 r = kvm_setup_empty_irq_routing(kvm); 6148 if (r) 6149 goto split_irqchip_unlock; 6150 /* Pairs with irqchip_in_kernel. */ 6151 smp_wmb(); 6152 kvm->arch.irqchip_mode = KVM_IRQCHIP_SPLIT; 6153 kvm->arch.nr_reserved_ioapic_pins = cap->args[0]; 6154 kvm_clear_apicv_inhibit(kvm, APICV_INHIBIT_REASON_ABSENT); 6155 r = 0; 6156 split_irqchip_unlock: 6157 mutex_unlock(&kvm->lock); 6158 break; 6159 } 6160 case KVM_CAP_X2APIC_API: 6161 r = -EINVAL; 6162 if (cap->args[0] & ~KVM_X2APIC_API_VALID_FLAGS) 6163 break; 6164 6165 if (cap->args[0] & KVM_X2APIC_API_USE_32BIT_IDS) 6166 kvm->arch.x2apic_format = true; 6167 if (cap->args[0] & KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK) 6168 kvm->arch.x2apic_broadcast_quirk_disabled = true; 6169 6170 r = 0; 6171 break; 6172 case KVM_CAP_X86_DISABLE_EXITS: 6173 r = -EINVAL; 6174 if (cap->args[0] & ~KVM_X86_DISABLE_VALID_EXITS) 6175 break; 6176 6177 if ((cap->args[0] & KVM_X86_DISABLE_EXITS_MWAIT) && 6178 kvm_can_mwait_in_guest()) 6179 kvm->arch.mwait_in_guest = true; 6180 if (cap->args[0] & KVM_X86_DISABLE_EXITS_HLT) 6181 kvm->arch.hlt_in_guest = true; 6182 if (cap->args[0] & KVM_X86_DISABLE_EXITS_PAUSE) 6183 kvm->arch.pause_in_guest = true; 6184 if (cap->args[0] & KVM_X86_DISABLE_EXITS_CSTATE) 6185 kvm->arch.cstate_in_guest = true; 6186 r = 0; 6187 break; 6188 case KVM_CAP_MSR_PLATFORM_INFO: 6189 kvm->arch.guest_can_read_msr_platform_info = cap->args[0]; 6190 r = 0; 6191 break; 6192 case KVM_CAP_EXCEPTION_PAYLOAD: 6193 kvm->arch.exception_payload_enabled = cap->args[0]; 6194 r = 0; 6195 break; 6196 case KVM_CAP_X86_TRIPLE_FAULT_EVENT: 6197 kvm->arch.triple_fault_event = cap->args[0]; 6198 r = 0; 6199 break; 6200 case KVM_CAP_X86_USER_SPACE_MSR: 6201 r = -EINVAL; 6202 if (cap->args[0] & ~(KVM_MSR_EXIT_REASON_INVAL | 6203 KVM_MSR_EXIT_REASON_UNKNOWN | 6204 KVM_MSR_EXIT_REASON_FILTER)) 6205 break; 6206 kvm->arch.user_space_msr_mask = cap->args[0]; 6207 r = 0; 6208 break; 6209 case KVM_CAP_X86_BUS_LOCK_EXIT: 6210 r = -EINVAL; 6211 if (cap->args[0] & ~KVM_BUS_LOCK_DETECTION_VALID_MODE) 6212 break; 6213 6214 if ((cap->args[0] & KVM_BUS_LOCK_DETECTION_OFF) && 6215 (cap->args[0] & KVM_BUS_LOCK_DETECTION_EXIT)) 6216 break; 6217 6218 if (kvm_caps.has_bus_lock_exit && 6219 cap->args[0] & KVM_BUS_LOCK_DETECTION_EXIT) 6220 kvm->arch.bus_lock_detection_enabled = true; 6221 r = 0; 6222 break; 6223 #ifdef CONFIG_X86_SGX_KVM 6224 case KVM_CAP_SGX_ATTRIBUTE: { 6225 unsigned long allowed_attributes = 0; 6226 6227 r = sgx_set_attribute(&allowed_attributes, cap->args[0]); 6228 if (r) 6229 break; 6230 6231 /* KVM only supports the PROVISIONKEY privileged attribute. */ 6232 if ((allowed_attributes & SGX_ATTR_PROVISIONKEY) && 6233 !(allowed_attributes & ~SGX_ATTR_PROVISIONKEY)) 6234 kvm->arch.sgx_provisioning_allowed = true; 6235 else 6236 r = -EINVAL; 6237 break; 6238 } 6239 #endif 6240 case KVM_CAP_VM_COPY_ENC_CONTEXT_FROM: 6241 r = -EINVAL; 6242 if (!kvm_x86_ops.vm_copy_enc_context_from) 6243 break; 6244 6245 r = static_call(kvm_x86_vm_copy_enc_context_from)(kvm, cap->args[0]); 6246 break; 6247 case KVM_CAP_VM_MOVE_ENC_CONTEXT_FROM: 6248 r = -EINVAL; 6249 if (!kvm_x86_ops.vm_move_enc_context_from) 6250 break; 6251 6252 r = static_call(kvm_x86_vm_move_enc_context_from)(kvm, cap->args[0]); 6253 break; 6254 case KVM_CAP_EXIT_HYPERCALL: 6255 if (cap->args[0] & ~KVM_EXIT_HYPERCALL_VALID_MASK) { 6256 r = -EINVAL; 6257 break; 6258 } 6259 kvm->arch.hypercall_exit_enabled = cap->args[0]; 6260 r = 0; 6261 break; 6262 case KVM_CAP_EXIT_ON_EMULATION_FAILURE: 6263 r = -EINVAL; 6264 if (cap->args[0] & ~1) 6265 break; 6266 kvm->arch.exit_on_emulation_error = cap->args[0]; 6267 r = 0; 6268 break; 6269 case KVM_CAP_PMU_CAPABILITY: 6270 r = -EINVAL; 6271 if (!enable_pmu || (cap->args[0] & ~KVM_CAP_PMU_VALID_MASK)) 6272 break; 6273 6274 mutex_lock(&kvm->lock); 6275 if (!kvm->created_vcpus) { 6276 kvm->arch.enable_pmu = !(cap->args[0] & KVM_PMU_CAP_DISABLE); 6277 r = 0; 6278 } 6279 mutex_unlock(&kvm->lock); 6280 break; 6281 case KVM_CAP_MAX_VCPU_ID: 6282 r = -EINVAL; 6283 if (cap->args[0] > KVM_MAX_VCPU_IDS) 6284 break; 6285 6286 mutex_lock(&kvm->lock); 6287 if (kvm->arch.max_vcpu_ids == cap->args[0]) { 6288 r = 0; 6289 } else if (!kvm->arch.max_vcpu_ids) { 6290 kvm->arch.max_vcpu_ids = cap->args[0]; 6291 r = 0; 6292 } 6293 mutex_unlock(&kvm->lock); 6294 break; 6295 case KVM_CAP_X86_NOTIFY_VMEXIT: 6296 r = -EINVAL; 6297 if ((u32)cap->args[0] & ~KVM_X86_NOTIFY_VMEXIT_VALID_BITS) 6298 break; 6299 if (!kvm_caps.has_notify_vmexit) 6300 break; 6301 if (!((u32)cap->args[0] & KVM_X86_NOTIFY_VMEXIT_ENABLED)) 6302 break; 6303 mutex_lock(&kvm->lock); 6304 if (!kvm->created_vcpus) { 6305 kvm->arch.notify_window = cap->args[0] >> 32; 6306 kvm->arch.notify_vmexit_flags = (u32)cap->args[0]; 6307 r = 0; 6308 } 6309 mutex_unlock(&kvm->lock); 6310 break; 6311 case KVM_CAP_VM_DISABLE_NX_HUGE_PAGES: 6312 r = -EINVAL; 6313 6314 /* 6315 * Since the risk of disabling NX hugepages is a guest crashing 6316 * the system, ensure the userspace process has permission to 6317 * reboot the system. 6318 * 6319 * Note that unlike the reboot() syscall, the process must have 6320 * this capability in the root namespace because exposing 6321 * /dev/kvm into a container does not limit the scope of the 6322 * iTLB multihit bug to that container. In other words, 6323 * this must use capable(), not ns_capable(). 6324 */ 6325 if (!capable(CAP_SYS_BOOT)) { 6326 r = -EPERM; 6327 break; 6328 } 6329 6330 if (cap->args[0]) 6331 break; 6332 6333 mutex_lock(&kvm->lock); 6334 if (!kvm->created_vcpus) { 6335 kvm->arch.disable_nx_huge_pages = true; 6336 r = 0; 6337 } 6338 mutex_unlock(&kvm->lock); 6339 break; 6340 default: 6341 r = -EINVAL; 6342 break; 6343 } 6344 return r; 6345 } 6346 6347 static struct kvm_x86_msr_filter *kvm_alloc_msr_filter(bool default_allow) 6348 { 6349 struct kvm_x86_msr_filter *msr_filter; 6350 6351 msr_filter = kzalloc(sizeof(*msr_filter), GFP_KERNEL_ACCOUNT); 6352 if (!msr_filter) 6353 return NULL; 6354 6355 msr_filter->default_allow = default_allow; 6356 return msr_filter; 6357 } 6358 6359 static void kvm_free_msr_filter(struct kvm_x86_msr_filter *msr_filter) 6360 { 6361 u32 i; 6362 6363 if (!msr_filter) 6364 return; 6365 6366 for (i = 0; i < msr_filter->count; i++) 6367 kfree(msr_filter->ranges[i].bitmap); 6368 6369 kfree(msr_filter); 6370 } 6371 6372 static int kvm_add_msr_filter(struct kvm_x86_msr_filter *msr_filter, 6373 struct kvm_msr_filter_range *user_range) 6374 { 6375 unsigned long *bitmap = NULL; 6376 size_t bitmap_size; 6377 6378 if (!user_range->nmsrs) 6379 return 0; 6380 6381 if (user_range->flags & ~(KVM_MSR_FILTER_READ | KVM_MSR_FILTER_WRITE)) 6382 return -EINVAL; 6383 6384 if (!user_range->flags) 6385 return -EINVAL; 6386 6387 bitmap_size = BITS_TO_LONGS(user_range->nmsrs) * sizeof(long); 6388 if (!bitmap_size || bitmap_size > KVM_MSR_FILTER_MAX_BITMAP_SIZE) 6389 return -EINVAL; 6390 6391 bitmap = memdup_user((__user u8*)user_range->bitmap, bitmap_size); 6392 if (IS_ERR(bitmap)) 6393 return PTR_ERR(bitmap); 6394 6395 msr_filter->ranges[msr_filter->count] = (struct msr_bitmap_range) { 6396 .flags = user_range->flags, 6397 .base = user_range->base, 6398 .nmsrs = user_range->nmsrs, 6399 .bitmap = bitmap, 6400 }; 6401 6402 msr_filter->count++; 6403 return 0; 6404 } 6405 6406 static int kvm_vm_ioctl_set_msr_filter(struct kvm *kvm, void __user *argp) 6407 { 6408 struct kvm_msr_filter __user *user_msr_filter = argp; 6409 struct kvm_x86_msr_filter *new_filter, *old_filter; 6410 struct kvm_msr_filter filter; 6411 bool default_allow; 6412 bool empty = true; 6413 int r = 0; 6414 u32 i; 6415 6416 if (copy_from_user(&filter, user_msr_filter, sizeof(filter))) 6417 return -EFAULT; 6418 6419 if (filter.flags & ~KVM_MSR_FILTER_DEFAULT_DENY) 6420 return -EINVAL; 6421 6422 for (i = 0; i < ARRAY_SIZE(filter.ranges); i++) 6423 empty &= !filter.ranges[i].nmsrs; 6424 6425 default_allow = !(filter.flags & KVM_MSR_FILTER_DEFAULT_DENY); 6426 if (empty && !default_allow) 6427 return -EINVAL; 6428 6429 new_filter = kvm_alloc_msr_filter(default_allow); 6430 if (!new_filter) 6431 return -ENOMEM; 6432 6433 for (i = 0; i < ARRAY_SIZE(filter.ranges); i++) { 6434 r = kvm_add_msr_filter(new_filter, &filter.ranges[i]); 6435 if (r) { 6436 kvm_free_msr_filter(new_filter); 6437 return r; 6438 } 6439 } 6440 6441 mutex_lock(&kvm->lock); 6442 6443 /* The per-VM filter is protected by kvm->lock... */ 6444 old_filter = srcu_dereference_check(kvm->arch.msr_filter, &kvm->srcu, 1); 6445 6446 rcu_assign_pointer(kvm->arch.msr_filter, new_filter); 6447 synchronize_srcu(&kvm->srcu); 6448 6449 kvm_free_msr_filter(old_filter); 6450 6451 kvm_make_all_cpus_request(kvm, KVM_REQ_MSR_FILTER_CHANGED); 6452 mutex_unlock(&kvm->lock); 6453 6454 return 0; 6455 } 6456 6457 #ifdef CONFIG_HAVE_KVM_PM_NOTIFIER 6458 static int kvm_arch_suspend_notifier(struct kvm *kvm) 6459 { 6460 struct kvm_vcpu *vcpu; 6461 unsigned long i; 6462 int ret = 0; 6463 6464 mutex_lock(&kvm->lock); 6465 kvm_for_each_vcpu(i, vcpu, kvm) { 6466 if (!vcpu->arch.pv_time.active) 6467 continue; 6468 6469 ret = kvm_set_guest_paused(vcpu); 6470 if (ret) { 6471 kvm_err("Failed to pause guest VCPU%d: %d\n", 6472 vcpu->vcpu_id, ret); 6473 break; 6474 } 6475 } 6476 mutex_unlock(&kvm->lock); 6477 6478 return ret ? NOTIFY_BAD : NOTIFY_DONE; 6479 } 6480 6481 int kvm_arch_pm_notifier(struct kvm *kvm, unsigned long state) 6482 { 6483 switch (state) { 6484 case PM_HIBERNATION_PREPARE: 6485 case PM_SUSPEND_PREPARE: 6486 return kvm_arch_suspend_notifier(kvm); 6487 } 6488 6489 return NOTIFY_DONE; 6490 } 6491 #endif /* CONFIG_HAVE_KVM_PM_NOTIFIER */ 6492 6493 static int kvm_vm_ioctl_get_clock(struct kvm *kvm, void __user *argp) 6494 { 6495 struct kvm_clock_data data = { 0 }; 6496 6497 get_kvmclock(kvm, &data); 6498 if (copy_to_user(argp, &data, sizeof(data))) 6499 return -EFAULT; 6500 6501 return 0; 6502 } 6503 6504 static int kvm_vm_ioctl_set_clock(struct kvm *kvm, void __user *argp) 6505 { 6506 struct kvm_arch *ka = &kvm->arch; 6507 struct kvm_clock_data data; 6508 u64 now_raw_ns; 6509 6510 if (copy_from_user(&data, argp, sizeof(data))) 6511 return -EFAULT; 6512 6513 /* 6514 * Only KVM_CLOCK_REALTIME is used, but allow passing the 6515 * result of KVM_GET_CLOCK back to KVM_SET_CLOCK. 6516 */ 6517 if (data.flags & ~KVM_CLOCK_VALID_FLAGS) 6518 return -EINVAL; 6519 6520 kvm_hv_request_tsc_page_update(kvm); 6521 kvm_start_pvclock_update(kvm); 6522 pvclock_update_vm_gtod_copy(kvm); 6523 6524 /* 6525 * This pairs with kvm_guest_time_update(): when masterclock is 6526 * in use, we use master_kernel_ns + kvmclock_offset to set 6527 * unsigned 'system_time' so if we use get_kvmclock_ns() (which 6528 * is slightly ahead) here we risk going negative on unsigned 6529 * 'system_time' when 'data.clock' is very small. 6530 */ 6531 if (data.flags & KVM_CLOCK_REALTIME) { 6532 u64 now_real_ns = ktime_get_real_ns(); 6533 6534 /* 6535 * Avoid stepping the kvmclock backwards. 6536 */ 6537 if (now_real_ns > data.realtime) 6538 data.clock += now_real_ns - data.realtime; 6539 } 6540 6541 if (ka->use_master_clock) 6542 now_raw_ns = ka->master_kernel_ns; 6543 else 6544 now_raw_ns = get_kvmclock_base_ns(); 6545 ka->kvmclock_offset = data.clock - now_raw_ns; 6546 kvm_end_pvclock_update(kvm); 6547 return 0; 6548 } 6549 6550 long kvm_arch_vm_ioctl(struct file *filp, 6551 unsigned int ioctl, unsigned long arg) 6552 { 6553 struct kvm *kvm = filp->private_data; 6554 void __user *argp = (void __user *)arg; 6555 int r = -ENOTTY; 6556 /* 6557 * This union makes it completely explicit to gcc-3.x 6558 * that these two variables' stack usage should be 6559 * combined, not added together. 6560 */ 6561 union { 6562 struct kvm_pit_state ps; 6563 struct kvm_pit_state2 ps2; 6564 struct kvm_pit_config pit_config; 6565 } u; 6566 6567 switch (ioctl) { 6568 case KVM_SET_TSS_ADDR: 6569 r = kvm_vm_ioctl_set_tss_addr(kvm, arg); 6570 break; 6571 case KVM_SET_IDENTITY_MAP_ADDR: { 6572 u64 ident_addr; 6573 6574 mutex_lock(&kvm->lock); 6575 r = -EINVAL; 6576 if (kvm->created_vcpus) 6577 goto set_identity_unlock; 6578 r = -EFAULT; 6579 if (copy_from_user(&ident_addr, argp, sizeof(ident_addr))) 6580 goto set_identity_unlock; 6581 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr); 6582 set_identity_unlock: 6583 mutex_unlock(&kvm->lock); 6584 break; 6585 } 6586 case KVM_SET_NR_MMU_PAGES: 6587 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg); 6588 break; 6589 case KVM_GET_NR_MMU_PAGES: 6590 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm); 6591 break; 6592 case KVM_CREATE_IRQCHIP: { 6593 mutex_lock(&kvm->lock); 6594 6595 r = -EEXIST; 6596 if (irqchip_in_kernel(kvm)) 6597 goto create_irqchip_unlock; 6598 6599 r = -EINVAL; 6600 if (kvm->created_vcpus) 6601 goto create_irqchip_unlock; 6602 6603 r = kvm_pic_init(kvm); 6604 if (r) 6605 goto create_irqchip_unlock; 6606 6607 r = kvm_ioapic_init(kvm); 6608 if (r) { 6609 kvm_pic_destroy(kvm); 6610 goto create_irqchip_unlock; 6611 } 6612 6613 r = kvm_setup_default_irq_routing(kvm); 6614 if (r) { 6615 kvm_ioapic_destroy(kvm); 6616 kvm_pic_destroy(kvm); 6617 goto create_irqchip_unlock; 6618 } 6619 /* Write kvm->irq_routing before enabling irqchip_in_kernel. */ 6620 smp_wmb(); 6621 kvm->arch.irqchip_mode = KVM_IRQCHIP_KERNEL; 6622 kvm_clear_apicv_inhibit(kvm, APICV_INHIBIT_REASON_ABSENT); 6623 create_irqchip_unlock: 6624 mutex_unlock(&kvm->lock); 6625 break; 6626 } 6627 case KVM_CREATE_PIT: 6628 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY; 6629 goto create_pit; 6630 case KVM_CREATE_PIT2: 6631 r = -EFAULT; 6632 if (copy_from_user(&u.pit_config, argp, 6633 sizeof(struct kvm_pit_config))) 6634 goto out; 6635 create_pit: 6636 mutex_lock(&kvm->lock); 6637 r = -EEXIST; 6638 if (kvm->arch.vpit) 6639 goto create_pit_unlock; 6640 r = -ENOMEM; 6641 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags); 6642 if (kvm->arch.vpit) 6643 r = 0; 6644 create_pit_unlock: 6645 mutex_unlock(&kvm->lock); 6646 break; 6647 case KVM_GET_IRQCHIP: { 6648 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */ 6649 struct kvm_irqchip *chip; 6650 6651 chip = memdup_user(argp, sizeof(*chip)); 6652 if (IS_ERR(chip)) { 6653 r = PTR_ERR(chip); 6654 goto out; 6655 } 6656 6657 r = -ENXIO; 6658 if (!irqchip_kernel(kvm)) 6659 goto get_irqchip_out; 6660 r = kvm_vm_ioctl_get_irqchip(kvm, chip); 6661 if (r) 6662 goto get_irqchip_out; 6663 r = -EFAULT; 6664 if (copy_to_user(argp, chip, sizeof(*chip))) 6665 goto get_irqchip_out; 6666 r = 0; 6667 get_irqchip_out: 6668 kfree(chip); 6669 break; 6670 } 6671 case KVM_SET_IRQCHIP: { 6672 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */ 6673 struct kvm_irqchip *chip; 6674 6675 chip = memdup_user(argp, sizeof(*chip)); 6676 if (IS_ERR(chip)) { 6677 r = PTR_ERR(chip); 6678 goto out; 6679 } 6680 6681 r = -ENXIO; 6682 if (!irqchip_kernel(kvm)) 6683 goto set_irqchip_out; 6684 r = kvm_vm_ioctl_set_irqchip(kvm, chip); 6685 set_irqchip_out: 6686 kfree(chip); 6687 break; 6688 } 6689 case KVM_GET_PIT: { 6690 r = -EFAULT; 6691 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state))) 6692 goto out; 6693 r = -ENXIO; 6694 if (!kvm->arch.vpit) 6695 goto out; 6696 r = kvm_vm_ioctl_get_pit(kvm, &u.ps); 6697 if (r) 6698 goto out; 6699 r = -EFAULT; 6700 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state))) 6701 goto out; 6702 r = 0; 6703 break; 6704 } 6705 case KVM_SET_PIT: { 6706 r = -EFAULT; 6707 if (copy_from_user(&u.ps, argp, sizeof(u.ps))) 6708 goto out; 6709 mutex_lock(&kvm->lock); 6710 r = -ENXIO; 6711 if (!kvm->arch.vpit) 6712 goto set_pit_out; 6713 r = kvm_vm_ioctl_set_pit(kvm, &u.ps); 6714 set_pit_out: 6715 mutex_unlock(&kvm->lock); 6716 break; 6717 } 6718 case KVM_GET_PIT2: { 6719 r = -ENXIO; 6720 if (!kvm->arch.vpit) 6721 goto out; 6722 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2); 6723 if (r) 6724 goto out; 6725 r = -EFAULT; 6726 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2))) 6727 goto out; 6728 r = 0; 6729 break; 6730 } 6731 case KVM_SET_PIT2: { 6732 r = -EFAULT; 6733 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2))) 6734 goto out; 6735 mutex_lock(&kvm->lock); 6736 r = -ENXIO; 6737 if (!kvm->arch.vpit) 6738 goto set_pit2_out; 6739 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2); 6740 set_pit2_out: 6741 mutex_unlock(&kvm->lock); 6742 break; 6743 } 6744 case KVM_REINJECT_CONTROL: { 6745 struct kvm_reinject_control control; 6746 r = -EFAULT; 6747 if (copy_from_user(&control, argp, sizeof(control))) 6748 goto out; 6749 r = -ENXIO; 6750 if (!kvm->arch.vpit) 6751 goto out; 6752 r = kvm_vm_ioctl_reinject(kvm, &control); 6753 break; 6754 } 6755 case KVM_SET_BOOT_CPU_ID: 6756 r = 0; 6757 mutex_lock(&kvm->lock); 6758 if (kvm->created_vcpus) 6759 r = -EBUSY; 6760 else 6761 kvm->arch.bsp_vcpu_id = arg; 6762 mutex_unlock(&kvm->lock); 6763 break; 6764 #ifdef CONFIG_KVM_XEN 6765 case KVM_XEN_HVM_CONFIG: { 6766 struct kvm_xen_hvm_config xhc; 6767 r = -EFAULT; 6768 if (copy_from_user(&xhc, argp, sizeof(xhc))) 6769 goto out; 6770 r = kvm_xen_hvm_config(kvm, &xhc); 6771 break; 6772 } 6773 case KVM_XEN_HVM_GET_ATTR: { 6774 struct kvm_xen_hvm_attr xha; 6775 6776 r = -EFAULT; 6777 if (copy_from_user(&xha, argp, sizeof(xha))) 6778 goto out; 6779 r = kvm_xen_hvm_get_attr(kvm, &xha); 6780 if (!r && copy_to_user(argp, &xha, sizeof(xha))) 6781 r = -EFAULT; 6782 break; 6783 } 6784 case KVM_XEN_HVM_SET_ATTR: { 6785 struct kvm_xen_hvm_attr xha; 6786 6787 r = -EFAULT; 6788 if (copy_from_user(&xha, argp, sizeof(xha))) 6789 goto out; 6790 r = kvm_xen_hvm_set_attr(kvm, &xha); 6791 break; 6792 } 6793 case KVM_XEN_HVM_EVTCHN_SEND: { 6794 struct kvm_irq_routing_xen_evtchn uxe; 6795 6796 r = -EFAULT; 6797 if (copy_from_user(&uxe, argp, sizeof(uxe))) 6798 goto out; 6799 r = kvm_xen_hvm_evtchn_send(kvm, &uxe); 6800 break; 6801 } 6802 #endif 6803 case KVM_SET_CLOCK: 6804 r = kvm_vm_ioctl_set_clock(kvm, argp); 6805 break; 6806 case KVM_GET_CLOCK: 6807 r = kvm_vm_ioctl_get_clock(kvm, argp); 6808 break; 6809 case KVM_SET_TSC_KHZ: { 6810 u32 user_tsc_khz; 6811 6812 r = -EINVAL; 6813 user_tsc_khz = (u32)arg; 6814 6815 if (kvm_caps.has_tsc_control && 6816 user_tsc_khz >= kvm_caps.max_guest_tsc_khz) 6817 goto out; 6818 6819 if (user_tsc_khz == 0) 6820 user_tsc_khz = tsc_khz; 6821 6822 WRITE_ONCE(kvm->arch.default_tsc_khz, user_tsc_khz); 6823 r = 0; 6824 6825 goto out; 6826 } 6827 case KVM_GET_TSC_KHZ: { 6828 r = READ_ONCE(kvm->arch.default_tsc_khz); 6829 goto out; 6830 } 6831 case KVM_MEMORY_ENCRYPT_OP: { 6832 r = -ENOTTY; 6833 if (!kvm_x86_ops.mem_enc_ioctl) 6834 goto out; 6835 6836 r = static_call(kvm_x86_mem_enc_ioctl)(kvm, argp); 6837 break; 6838 } 6839 case KVM_MEMORY_ENCRYPT_REG_REGION: { 6840 struct kvm_enc_region region; 6841 6842 r = -EFAULT; 6843 if (copy_from_user(®ion, argp, sizeof(region))) 6844 goto out; 6845 6846 r = -ENOTTY; 6847 if (!kvm_x86_ops.mem_enc_register_region) 6848 goto out; 6849 6850 r = static_call(kvm_x86_mem_enc_register_region)(kvm, ®ion); 6851 break; 6852 } 6853 case KVM_MEMORY_ENCRYPT_UNREG_REGION: { 6854 struct kvm_enc_region region; 6855 6856 r = -EFAULT; 6857 if (copy_from_user(®ion, argp, sizeof(region))) 6858 goto out; 6859 6860 r = -ENOTTY; 6861 if (!kvm_x86_ops.mem_enc_unregister_region) 6862 goto out; 6863 6864 r = static_call(kvm_x86_mem_enc_unregister_region)(kvm, ®ion); 6865 break; 6866 } 6867 case KVM_HYPERV_EVENTFD: { 6868 struct kvm_hyperv_eventfd hvevfd; 6869 6870 r = -EFAULT; 6871 if (copy_from_user(&hvevfd, argp, sizeof(hvevfd))) 6872 goto out; 6873 r = kvm_vm_ioctl_hv_eventfd(kvm, &hvevfd); 6874 break; 6875 } 6876 case KVM_SET_PMU_EVENT_FILTER: 6877 r = kvm_vm_ioctl_set_pmu_event_filter(kvm, argp); 6878 break; 6879 case KVM_X86_SET_MSR_FILTER: 6880 r = kvm_vm_ioctl_set_msr_filter(kvm, argp); 6881 break; 6882 default: 6883 r = -ENOTTY; 6884 } 6885 out: 6886 return r; 6887 } 6888 6889 static void kvm_init_msr_list(void) 6890 { 6891 u32 dummy[2]; 6892 unsigned i; 6893 6894 BUILD_BUG_ON_MSG(KVM_PMC_MAX_FIXED != 3, 6895 "Please update the fixed PMCs in msrs_to_saved_all[]"); 6896 6897 num_msrs_to_save = 0; 6898 num_emulated_msrs = 0; 6899 num_msr_based_features = 0; 6900 6901 for (i = 0; i < ARRAY_SIZE(msrs_to_save_all); i++) { 6902 if (rdmsr_safe(msrs_to_save_all[i], &dummy[0], &dummy[1]) < 0) 6903 continue; 6904 6905 /* 6906 * Even MSRs that are valid in the host may not be exposed 6907 * to the guests in some cases. 6908 */ 6909 switch (msrs_to_save_all[i]) { 6910 case MSR_IA32_BNDCFGS: 6911 if (!kvm_mpx_supported()) 6912 continue; 6913 break; 6914 case MSR_TSC_AUX: 6915 if (!kvm_cpu_cap_has(X86_FEATURE_RDTSCP) && 6916 !kvm_cpu_cap_has(X86_FEATURE_RDPID)) 6917 continue; 6918 break; 6919 case MSR_IA32_UMWAIT_CONTROL: 6920 if (!kvm_cpu_cap_has(X86_FEATURE_WAITPKG)) 6921 continue; 6922 break; 6923 case MSR_IA32_RTIT_CTL: 6924 case MSR_IA32_RTIT_STATUS: 6925 if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT)) 6926 continue; 6927 break; 6928 case MSR_IA32_RTIT_CR3_MATCH: 6929 if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT) || 6930 !intel_pt_validate_hw_cap(PT_CAP_cr3_filtering)) 6931 continue; 6932 break; 6933 case MSR_IA32_RTIT_OUTPUT_BASE: 6934 case MSR_IA32_RTIT_OUTPUT_MASK: 6935 if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT) || 6936 (!intel_pt_validate_hw_cap(PT_CAP_topa_output) && 6937 !intel_pt_validate_hw_cap(PT_CAP_single_range_output))) 6938 continue; 6939 break; 6940 case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B: 6941 if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT) || 6942 msrs_to_save_all[i] - MSR_IA32_RTIT_ADDR0_A >= 6943 intel_pt_validate_hw_cap(PT_CAP_num_address_ranges) * 2) 6944 continue; 6945 break; 6946 case MSR_ARCH_PERFMON_PERFCTR0 ... MSR_ARCH_PERFMON_PERFCTR0 + 17: 6947 if (msrs_to_save_all[i] - MSR_ARCH_PERFMON_PERFCTR0 >= 6948 min(INTEL_PMC_MAX_GENERIC, kvm_pmu_cap.num_counters_gp)) 6949 continue; 6950 break; 6951 case MSR_ARCH_PERFMON_EVENTSEL0 ... MSR_ARCH_PERFMON_EVENTSEL0 + 17: 6952 if (msrs_to_save_all[i] - MSR_ARCH_PERFMON_EVENTSEL0 >= 6953 min(INTEL_PMC_MAX_GENERIC, kvm_pmu_cap.num_counters_gp)) 6954 continue; 6955 break; 6956 case MSR_IA32_XFD: 6957 case MSR_IA32_XFD_ERR: 6958 if (!kvm_cpu_cap_has(X86_FEATURE_XFD)) 6959 continue; 6960 break; 6961 default: 6962 break; 6963 } 6964 6965 msrs_to_save[num_msrs_to_save++] = msrs_to_save_all[i]; 6966 } 6967 6968 for (i = 0; i < ARRAY_SIZE(emulated_msrs_all); i++) { 6969 if (!static_call(kvm_x86_has_emulated_msr)(NULL, emulated_msrs_all[i])) 6970 continue; 6971 6972 emulated_msrs[num_emulated_msrs++] = emulated_msrs_all[i]; 6973 } 6974 6975 for (i = 0; i < ARRAY_SIZE(msr_based_features_all); i++) { 6976 struct kvm_msr_entry msr; 6977 6978 msr.index = msr_based_features_all[i]; 6979 if (kvm_get_msr_feature(&msr)) 6980 continue; 6981 6982 msr_based_features[num_msr_based_features++] = msr_based_features_all[i]; 6983 } 6984 } 6985 6986 static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len, 6987 const void *v) 6988 { 6989 int handled = 0; 6990 int n; 6991 6992 do { 6993 n = min(len, 8); 6994 if (!(lapic_in_kernel(vcpu) && 6995 !kvm_iodevice_write(vcpu, &vcpu->arch.apic->dev, addr, n, v)) 6996 && kvm_io_bus_write(vcpu, KVM_MMIO_BUS, addr, n, v)) 6997 break; 6998 handled += n; 6999 addr += n; 7000 len -= n; 7001 v += n; 7002 } while (len); 7003 7004 return handled; 7005 } 7006 7007 static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v) 7008 { 7009 int handled = 0; 7010 int n; 7011 7012 do { 7013 n = min(len, 8); 7014 if (!(lapic_in_kernel(vcpu) && 7015 !kvm_iodevice_read(vcpu, &vcpu->arch.apic->dev, 7016 addr, n, v)) 7017 && kvm_io_bus_read(vcpu, KVM_MMIO_BUS, addr, n, v)) 7018 break; 7019 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, v); 7020 handled += n; 7021 addr += n; 7022 len -= n; 7023 v += n; 7024 } while (len); 7025 7026 return handled; 7027 } 7028 7029 static void kvm_set_segment(struct kvm_vcpu *vcpu, 7030 struct kvm_segment *var, int seg) 7031 { 7032 static_call(kvm_x86_set_segment)(vcpu, var, seg); 7033 } 7034 7035 void kvm_get_segment(struct kvm_vcpu *vcpu, 7036 struct kvm_segment *var, int seg) 7037 { 7038 static_call(kvm_x86_get_segment)(vcpu, var, seg); 7039 } 7040 7041 gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u64 access, 7042 struct x86_exception *exception) 7043 { 7044 struct kvm_mmu *mmu = vcpu->arch.mmu; 7045 gpa_t t_gpa; 7046 7047 BUG_ON(!mmu_is_nested(vcpu)); 7048 7049 /* NPT walks are always user-walks */ 7050 access |= PFERR_USER_MASK; 7051 t_gpa = mmu->gva_to_gpa(vcpu, mmu, gpa, access, exception); 7052 7053 return t_gpa; 7054 } 7055 7056 gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva, 7057 struct x86_exception *exception) 7058 { 7059 struct kvm_mmu *mmu = vcpu->arch.walk_mmu; 7060 7061 u64 access = (static_call(kvm_x86_get_cpl)(vcpu) == 3) ? PFERR_USER_MASK : 0; 7062 return mmu->gva_to_gpa(vcpu, mmu, gva, access, exception); 7063 } 7064 EXPORT_SYMBOL_GPL(kvm_mmu_gva_to_gpa_read); 7065 7066 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva, 7067 struct x86_exception *exception) 7068 { 7069 struct kvm_mmu *mmu = vcpu->arch.walk_mmu; 7070 7071 u64 access = (static_call(kvm_x86_get_cpl)(vcpu) == 3) ? PFERR_USER_MASK : 0; 7072 access |= PFERR_FETCH_MASK; 7073 return mmu->gva_to_gpa(vcpu, mmu, gva, access, exception); 7074 } 7075 7076 gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva, 7077 struct x86_exception *exception) 7078 { 7079 struct kvm_mmu *mmu = vcpu->arch.walk_mmu; 7080 7081 u64 access = (static_call(kvm_x86_get_cpl)(vcpu) == 3) ? PFERR_USER_MASK : 0; 7082 access |= PFERR_WRITE_MASK; 7083 return mmu->gva_to_gpa(vcpu, mmu, gva, access, exception); 7084 } 7085 EXPORT_SYMBOL_GPL(kvm_mmu_gva_to_gpa_write); 7086 7087 /* uses this to access any guest's mapped memory without checking CPL */ 7088 gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva, 7089 struct x86_exception *exception) 7090 { 7091 struct kvm_mmu *mmu = vcpu->arch.walk_mmu; 7092 7093 return mmu->gva_to_gpa(vcpu, mmu, gva, 0, exception); 7094 } 7095 7096 static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes, 7097 struct kvm_vcpu *vcpu, u64 access, 7098 struct x86_exception *exception) 7099 { 7100 struct kvm_mmu *mmu = vcpu->arch.walk_mmu; 7101 void *data = val; 7102 int r = X86EMUL_CONTINUE; 7103 7104 while (bytes) { 7105 gpa_t gpa = mmu->gva_to_gpa(vcpu, mmu, addr, access, exception); 7106 unsigned offset = addr & (PAGE_SIZE-1); 7107 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset); 7108 int ret; 7109 7110 if (gpa == INVALID_GPA) 7111 return X86EMUL_PROPAGATE_FAULT; 7112 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, data, 7113 offset, toread); 7114 if (ret < 0) { 7115 r = X86EMUL_IO_NEEDED; 7116 goto out; 7117 } 7118 7119 bytes -= toread; 7120 data += toread; 7121 addr += toread; 7122 } 7123 out: 7124 return r; 7125 } 7126 7127 /* used for instruction fetching */ 7128 static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt, 7129 gva_t addr, void *val, unsigned int bytes, 7130 struct x86_exception *exception) 7131 { 7132 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 7133 struct kvm_mmu *mmu = vcpu->arch.walk_mmu; 7134 u64 access = (static_call(kvm_x86_get_cpl)(vcpu) == 3) ? PFERR_USER_MASK : 0; 7135 unsigned offset; 7136 int ret; 7137 7138 /* Inline kvm_read_guest_virt_helper for speed. */ 7139 gpa_t gpa = mmu->gva_to_gpa(vcpu, mmu, addr, access|PFERR_FETCH_MASK, 7140 exception); 7141 if (unlikely(gpa == INVALID_GPA)) 7142 return X86EMUL_PROPAGATE_FAULT; 7143 7144 offset = addr & (PAGE_SIZE-1); 7145 if (WARN_ON(offset + bytes > PAGE_SIZE)) 7146 bytes = (unsigned)PAGE_SIZE - offset; 7147 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, val, 7148 offset, bytes); 7149 if (unlikely(ret < 0)) 7150 return X86EMUL_IO_NEEDED; 7151 7152 return X86EMUL_CONTINUE; 7153 } 7154 7155 int kvm_read_guest_virt(struct kvm_vcpu *vcpu, 7156 gva_t addr, void *val, unsigned int bytes, 7157 struct x86_exception *exception) 7158 { 7159 u64 access = (static_call(kvm_x86_get_cpl)(vcpu) == 3) ? PFERR_USER_MASK : 0; 7160 7161 /* 7162 * FIXME: this should call handle_emulation_failure if X86EMUL_IO_NEEDED 7163 * is returned, but our callers are not ready for that and they blindly 7164 * call kvm_inject_page_fault. Ensure that they at least do not leak 7165 * uninitialized kernel stack memory into cr2 and error code. 7166 */ 7167 memset(exception, 0, sizeof(*exception)); 7168 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access, 7169 exception); 7170 } 7171 EXPORT_SYMBOL_GPL(kvm_read_guest_virt); 7172 7173 static int emulator_read_std(struct x86_emulate_ctxt *ctxt, 7174 gva_t addr, void *val, unsigned int bytes, 7175 struct x86_exception *exception, bool system) 7176 { 7177 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 7178 u64 access = 0; 7179 7180 if (system) 7181 access |= PFERR_IMPLICIT_ACCESS; 7182 else if (static_call(kvm_x86_get_cpl)(vcpu) == 3) 7183 access |= PFERR_USER_MASK; 7184 7185 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access, exception); 7186 } 7187 7188 static int kvm_read_guest_phys_system(struct x86_emulate_ctxt *ctxt, 7189 unsigned long addr, void *val, unsigned int bytes) 7190 { 7191 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 7192 int r = kvm_vcpu_read_guest(vcpu, addr, val, bytes); 7193 7194 return r < 0 ? X86EMUL_IO_NEEDED : X86EMUL_CONTINUE; 7195 } 7196 7197 static int kvm_write_guest_virt_helper(gva_t addr, void *val, unsigned int bytes, 7198 struct kvm_vcpu *vcpu, u64 access, 7199 struct x86_exception *exception) 7200 { 7201 struct kvm_mmu *mmu = vcpu->arch.walk_mmu; 7202 void *data = val; 7203 int r = X86EMUL_CONTINUE; 7204 7205 while (bytes) { 7206 gpa_t gpa = mmu->gva_to_gpa(vcpu, mmu, addr, access, exception); 7207 unsigned offset = addr & (PAGE_SIZE-1); 7208 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset); 7209 int ret; 7210 7211 if (gpa == INVALID_GPA) 7212 return X86EMUL_PROPAGATE_FAULT; 7213 ret = kvm_vcpu_write_guest(vcpu, gpa, data, towrite); 7214 if (ret < 0) { 7215 r = X86EMUL_IO_NEEDED; 7216 goto out; 7217 } 7218 7219 bytes -= towrite; 7220 data += towrite; 7221 addr += towrite; 7222 } 7223 out: 7224 return r; 7225 } 7226 7227 static int emulator_write_std(struct x86_emulate_ctxt *ctxt, gva_t addr, void *val, 7228 unsigned int bytes, struct x86_exception *exception, 7229 bool system) 7230 { 7231 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 7232 u64 access = PFERR_WRITE_MASK; 7233 7234 if (system) 7235 access |= PFERR_IMPLICIT_ACCESS; 7236 else if (static_call(kvm_x86_get_cpl)(vcpu) == 3) 7237 access |= PFERR_USER_MASK; 7238 7239 return kvm_write_guest_virt_helper(addr, val, bytes, vcpu, 7240 access, exception); 7241 } 7242 7243 int kvm_write_guest_virt_system(struct kvm_vcpu *vcpu, gva_t addr, void *val, 7244 unsigned int bytes, struct x86_exception *exception) 7245 { 7246 /* kvm_write_guest_virt_system can pull in tons of pages. */ 7247 vcpu->arch.l1tf_flush_l1d = true; 7248 7249 return kvm_write_guest_virt_helper(addr, val, bytes, vcpu, 7250 PFERR_WRITE_MASK, exception); 7251 } 7252 EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system); 7253 7254 static int kvm_can_emulate_insn(struct kvm_vcpu *vcpu, int emul_type, 7255 void *insn, int insn_len) 7256 { 7257 return static_call(kvm_x86_can_emulate_instruction)(vcpu, emul_type, 7258 insn, insn_len); 7259 } 7260 7261 int handle_ud(struct kvm_vcpu *vcpu) 7262 { 7263 static const char kvm_emulate_prefix[] = { __KVM_EMULATE_PREFIX }; 7264 int emul_type = EMULTYPE_TRAP_UD; 7265 char sig[5]; /* ud2; .ascii "kvm" */ 7266 struct x86_exception e; 7267 7268 if (unlikely(!kvm_can_emulate_insn(vcpu, emul_type, NULL, 0))) 7269 return 1; 7270 7271 if (force_emulation_prefix && 7272 kvm_read_guest_virt(vcpu, kvm_get_linear_rip(vcpu), 7273 sig, sizeof(sig), &e) == 0 && 7274 memcmp(sig, kvm_emulate_prefix, sizeof(sig)) == 0) { 7275 kvm_rip_write(vcpu, kvm_rip_read(vcpu) + sizeof(sig)); 7276 emul_type = EMULTYPE_TRAP_UD_FORCED; 7277 } 7278 7279 return kvm_emulate_instruction(vcpu, emul_type); 7280 } 7281 EXPORT_SYMBOL_GPL(handle_ud); 7282 7283 static int vcpu_is_mmio_gpa(struct kvm_vcpu *vcpu, unsigned long gva, 7284 gpa_t gpa, bool write) 7285 { 7286 /* For APIC access vmexit */ 7287 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE) 7288 return 1; 7289 7290 if (vcpu_match_mmio_gpa(vcpu, gpa)) { 7291 trace_vcpu_match_mmio(gva, gpa, write, true); 7292 return 1; 7293 } 7294 7295 return 0; 7296 } 7297 7298 static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva, 7299 gpa_t *gpa, struct x86_exception *exception, 7300 bool write) 7301 { 7302 struct kvm_mmu *mmu = vcpu->arch.walk_mmu; 7303 u64 access = ((static_call(kvm_x86_get_cpl)(vcpu) == 3) ? PFERR_USER_MASK : 0) 7304 | (write ? PFERR_WRITE_MASK : 0); 7305 7306 /* 7307 * currently PKRU is only applied to ept enabled guest so 7308 * there is no pkey in EPT page table for L1 guest or EPT 7309 * shadow page table for L2 guest. 7310 */ 7311 if (vcpu_match_mmio_gva(vcpu, gva) && (!is_paging(vcpu) || 7312 !permission_fault(vcpu, vcpu->arch.walk_mmu, 7313 vcpu->arch.mmio_access, 0, access))) { 7314 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT | 7315 (gva & (PAGE_SIZE - 1)); 7316 trace_vcpu_match_mmio(gva, *gpa, write, false); 7317 return 1; 7318 } 7319 7320 *gpa = mmu->gva_to_gpa(vcpu, mmu, gva, access, exception); 7321 7322 if (*gpa == INVALID_GPA) 7323 return -1; 7324 7325 return vcpu_is_mmio_gpa(vcpu, gva, *gpa, write); 7326 } 7327 7328 int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa, 7329 const void *val, int bytes) 7330 { 7331 int ret; 7332 7333 ret = kvm_vcpu_write_guest(vcpu, gpa, val, bytes); 7334 if (ret < 0) 7335 return 0; 7336 kvm_page_track_write(vcpu, gpa, val, bytes); 7337 return 1; 7338 } 7339 7340 struct read_write_emulator_ops { 7341 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val, 7342 int bytes); 7343 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa, 7344 void *val, int bytes); 7345 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa, 7346 int bytes, void *val); 7347 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa, 7348 void *val, int bytes); 7349 bool write; 7350 }; 7351 7352 static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes) 7353 { 7354 if (vcpu->mmio_read_completed) { 7355 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes, 7356 vcpu->mmio_fragments[0].gpa, val); 7357 vcpu->mmio_read_completed = 0; 7358 return 1; 7359 } 7360 7361 return 0; 7362 } 7363 7364 static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa, 7365 void *val, int bytes) 7366 { 7367 return !kvm_vcpu_read_guest(vcpu, gpa, val, bytes); 7368 } 7369 7370 static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa, 7371 void *val, int bytes) 7372 { 7373 return emulator_write_phys(vcpu, gpa, val, bytes); 7374 } 7375 7376 static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val) 7377 { 7378 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, val); 7379 return vcpu_mmio_write(vcpu, gpa, bytes, val); 7380 } 7381 7382 static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, 7383 void *val, int bytes) 7384 { 7385 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, NULL); 7386 return X86EMUL_IO_NEEDED; 7387 } 7388 7389 static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, 7390 void *val, int bytes) 7391 { 7392 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0]; 7393 7394 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len)); 7395 return X86EMUL_CONTINUE; 7396 } 7397 7398 static const struct read_write_emulator_ops read_emultor = { 7399 .read_write_prepare = read_prepare, 7400 .read_write_emulate = read_emulate, 7401 .read_write_mmio = vcpu_mmio_read, 7402 .read_write_exit_mmio = read_exit_mmio, 7403 }; 7404 7405 static const struct read_write_emulator_ops write_emultor = { 7406 .read_write_emulate = write_emulate, 7407 .read_write_mmio = write_mmio, 7408 .read_write_exit_mmio = write_exit_mmio, 7409 .write = true, 7410 }; 7411 7412 static int emulator_read_write_onepage(unsigned long addr, void *val, 7413 unsigned int bytes, 7414 struct x86_exception *exception, 7415 struct kvm_vcpu *vcpu, 7416 const struct read_write_emulator_ops *ops) 7417 { 7418 gpa_t gpa; 7419 int handled, ret; 7420 bool write = ops->write; 7421 struct kvm_mmio_fragment *frag; 7422 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt; 7423 7424 /* 7425 * If the exit was due to a NPF we may already have a GPA. 7426 * If the GPA is present, use it to avoid the GVA to GPA table walk. 7427 * Note, this cannot be used on string operations since string 7428 * operation using rep will only have the initial GPA from the NPF 7429 * occurred. 7430 */ 7431 if (ctxt->gpa_available && emulator_can_use_gpa(ctxt) && 7432 (addr & ~PAGE_MASK) == (ctxt->gpa_val & ~PAGE_MASK)) { 7433 gpa = ctxt->gpa_val; 7434 ret = vcpu_is_mmio_gpa(vcpu, addr, gpa, write); 7435 } else { 7436 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write); 7437 if (ret < 0) 7438 return X86EMUL_PROPAGATE_FAULT; 7439 } 7440 7441 if (!ret && ops->read_write_emulate(vcpu, gpa, val, bytes)) 7442 return X86EMUL_CONTINUE; 7443 7444 /* 7445 * Is this MMIO handled locally? 7446 */ 7447 handled = ops->read_write_mmio(vcpu, gpa, bytes, val); 7448 if (handled == bytes) 7449 return X86EMUL_CONTINUE; 7450 7451 gpa += handled; 7452 bytes -= handled; 7453 val += handled; 7454 7455 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS); 7456 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++]; 7457 frag->gpa = gpa; 7458 frag->data = val; 7459 frag->len = bytes; 7460 return X86EMUL_CONTINUE; 7461 } 7462 7463 static int emulator_read_write(struct x86_emulate_ctxt *ctxt, 7464 unsigned long addr, 7465 void *val, unsigned int bytes, 7466 struct x86_exception *exception, 7467 const struct read_write_emulator_ops *ops) 7468 { 7469 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 7470 gpa_t gpa; 7471 int rc; 7472 7473 if (ops->read_write_prepare && 7474 ops->read_write_prepare(vcpu, val, bytes)) 7475 return X86EMUL_CONTINUE; 7476 7477 vcpu->mmio_nr_fragments = 0; 7478 7479 /* Crossing a page boundary? */ 7480 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) { 7481 int now; 7482 7483 now = -addr & ~PAGE_MASK; 7484 rc = emulator_read_write_onepage(addr, val, now, exception, 7485 vcpu, ops); 7486 7487 if (rc != X86EMUL_CONTINUE) 7488 return rc; 7489 addr += now; 7490 if (ctxt->mode != X86EMUL_MODE_PROT64) 7491 addr = (u32)addr; 7492 val += now; 7493 bytes -= now; 7494 } 7495 7496 rc = emulator_read_write_onepage(addr, val, bytes, exception, 7497 vcpu, ops); 7498 if (rc != X86EMUL_CONTINUE) 7499 return rc; 7500 7501 if (!vcpu->mmio_nr_fragments) 7502 return rc; 7503 7504 gpa = vcpu->mmio_fragments[0].gpa; 7505 7506 vcpu->mmio_needed = 1; 7507 vcpu->mmio_cur_fragment = 0; 7508 7509 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len); 7510 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write; 7511 vcpu->run->exit_reason = KVM_EXIT_MMIO; 7512 vcpu->run->mmio.phys_addr = gpa; 7513 7514 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes); 7515 } 7516 7517 static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt, 7518 unsigned long addr, 7519 void *val, 7520 unsigned int bytes, 7521 struct x86_exception *exception) 7522 { 7523 return emulator_read_write(ctxt, addr, val, bytes, 7524 exception, &read_emultor); 7525 } 7526 7527 static int emulator_write_emulated(struct x86_emulate_ctxt *ctxt, 7528 unsigned long addr, 7529 const void *val, 7530 unsigned int bytes, 7531 struct x86_exception *exception) 7532 { 7533 return emulator_read_write(ctxt, addr, (void *)val, bytes, 7534 exception, &write_emultor); 7535 } 7536 7537 #define emulator_try_cmpxchg_user(t, ptr, old, new) \ 7538 (__try_cmpxchg_user((t __user *)(ptr), (t *)(old), *(t *)(new), efault ## t)) 7539 7540 static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt, 7541 unsigned long addr, 7542 const void *old, 7543 const void *new, 7544 unsigned int bytes, 7545 struct x86_exception *exception) 7546 { 7547 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 7548 u64 page_line_mask; 7549 unsigned long hva; 7550 gpa_t gpa; 7551 int r; 7552 7553 /* guests cmpxchg8b have to be emulated atomically */ 7554 if (bytes > 8 || (bytes & (bytes - 1))) 7555 goto emul_write; 7556 7557 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL); 7558 7559 if (gpa == INVALID_GPA || 7560 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE) 7561 goto emul_write; 7562 7563 /* 7564 * Emulate the atomic as a straight write to avoid #AC if SLD is 7565 * enabled in the host and the access splits a cache line. 7566 */ 7567 if (boot_cpu_has(X86_FEATURE_SPLIT_LOCK_DETECT)) 7568 page_line_mask = ~(cache_line_size() - 1); 7569 else 7570 page_line_mask = PAGE_MASK; 7571 7572 if (((gpa + bytes - 1) & page_line_mask) != (gpa & page_line_mask)) 7573 goto emul_write; 7574 7575 hva = kvm_vcpu_gfn_to_hva(vcpu, gpa_to_gfn(gpa)); 7576 if (kvm_is_error_hva(hva)) 7577 goto emul_write; 7578 7579 hva += offset_in_page(gpa); 7580 7581 switch (bytes) { 7582 case 1: 7583 r = emulator_try_cmpxchg_user(u8, hva, old, new); 7584 break; 7585 case 2: 7586 r = emulator_try_cmpxchg_user(u16, hva, old, new); 7587 break; 7588 case 4: 7589 r = emulator_try_cmpxchg_user(u32, hva, old, new); 7590 break; 7591 case 8: 7592 r = emulator_try_cmpxchg_user(u64, hva, old, new); 7593 break; 7594 default: 7595 BUG(); 7596 } 7597 7598 if (r < 0) 7599 return X86EMUL_UNHANDLEABLE; 7600 if (r) 7601 return X86EMUL_CMPXCHG_FAILED; 7602 7603 kvm_page_track_write(vcpu, gpa, new, bytes); 7604 7605 return X86EMUL_CONTINUE; 7606 7607 emul_write: 7608 printk_once(KERN_WARNING "kvm: emulating exchange as write\n"); 7609 7610 return emulator_write_emulated(ctxt, addr, new, bytes, exception); 7611 } 7612 7613 static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size, 7614 unsigned short port, void *data, 7615 unsigned int count, bool in) 7616 { 7617 unsigned i; 7618 int r; 7619 7620 WARN_ON_ONCE(vcpu->arch.pio.count); 7621 for (i = 0; i < count; i++) { 7622 if (in) 7623 r = kvm_io_bus_read(vcpu, KVM_PIO_BUS, port, size, data); 7624 else 7625 r = kvm_io_bus_write(vcpu, KVM_PIO_BUS, port, size, data); 7626 7627 if (r) { 7628 if (i == 0) 7629 goto userspace_io; 7630 7631 /* 7632 * Userspace must have unregistered the device while PIO 7633 * was running. Drop writes / read as 0. 7634 */ 7635 if (in) 7636 memset(data, 0, size * (count - i)); 7637 break; 7638 } 7639 7640 data += size; 7641 } 7642 return 1; 7643 7644 userspace_io: 7645 vcpu->arch.pio.port = port; 7646 vcpu->arch.pio.in = in; 7647 vcpu->arch.pio.count = count; 7648 vcpu->arch.pio.size = size; 7649 7650 if (in) 7651 memset(vcpu->arch.pio_data, 0, size * count); 7652 else 7653 memcpy(vcpu->arch.pio_data, data, size * count); 7654 7655 vcpu->run->exit_reason = KVM_EXIT_IO; 7656 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT; 7657 vcpu->run->io.size = size; 7658 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE; 7659 vcpu->run->io.count = count; 7660 vcpu->run->io.port = port; 7661 return 0; 7662 } 7663 7664 static int emulator_pio_in(struct kvm_vcpu *vcpu, int size, 7665 unsigned short port, void *val, unsigned int count) 7666 { 7667 int r = emulator_pio_in_out(vcpu, size, port, val, count, true); 7668 if (r) 7669 trace_kvm_pio(KVM_PIO_IN, port, size, count, val); 7670 7671 return r; 7672 } 7673 7674 static void complete_emulator_pio_in(struct kvm_vcpu *vcpu, void *val) 7675 { 7676 int size = vcpu->arch.pio.size; 7677 unsigned int count = vcpu->arch.pio.count; 7678 memcpy(val, vcpu->arch.pio_data, size * count); 7679 trace_kvm_pio(KVM_PIO_IN, vcpu->arch.pio.port, size, count, vcpu->arch.pio_data); 7680 vcpu->arch.pio.count = 0; 7681 } 7682 7683 static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt, 7684 int size, unsigned short port, void *val, 7685 unsigned int count) 7686 { 7687 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 7688 if (vcpu->arch.pio.count) { 7689 /* 7690 * Complete a previous iteration that required userspace I/O. 7691 * Note, @count isn't guaranteed to match pio.count as userspace 7692 * can modify ECX before rerunning the vCPU. Ignore any such 7693 * shenanigans as KVM doesn't support modifying the rep count, 7694 * and the emulator ensures @count doesn't overflow the buffer. 7695 */ 7696 complete_emulator_pio_in(vcpu, val); 7697 return 1; 7698 } 7699 7700 return emulator_pio_in(vcpu, size, port, val, count); 7701 } 7702 7703 static int emulator_pio_out(struct kvm_vcpu *vcpu, int size, 7704 unsigned short port, const void *val, 7705 unsigned int count) 7706 { 7707 trace_kvm_pio(KVM_PIO_OUT, port, size, count, val); 7708 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false); 7709 } 7710 7711 static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt, 7712 int size, unsigned short port, 7713 const void *val, unsigned int count) 7714 { 7715 return emulator_pio_out(emul_to_vcpu(ctxt), size, port, val, count); 7716 } 7717 7718 static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg) 7719 { 7720 return static_call(kvm_x86_get_segment_base)(vcpu, seg); 7721 } 7722 7723 static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address) 7724 { 7725 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address); 7726 } 7727 7728 static int kvm_emulate_wbinvd_noskip(struct kvm_vcpu *vcpu) 7729 { 7730 if (!need_emulate_wbinvd(vcpu)) 7731 return X86EMUL_CONTINUE; 7732 7733 if (static_call(kvm_x86_has_wbinvd_exit)()) { 7734 int cpu = get_cpu(); 7735 7736 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask); 7737 on_each_cpu_mask(vcpu->arch.wbinvd_dirty_mask, 7738 wbinvd_ipi, NULL, 1); 7739 put_cpu(); 7740 cpumask_clear(vcpu->arch.wbinvd_dirty_mask); 7741 } else 7742 wbinvd(); 7743 return X86EMUL_CONTINUE; 7744 } 7745 7746 int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu) 7747 { 7748 kvm_emulate_wbinvd_noskip(vcpu); 7749 return kvm_skip_emulated_instruction(vcpu); 7750 } 7751 EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd); 7752 7753 7754 7755 static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt) 7756 { 7757 kvm_emulate_wbinvd_noskip(emul_to_vcpu(ctxt)); 7758 } 7759 7760 static void emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr, 7761 unsigned long *dest) 7762 { 7763 kvm_get_dr(emul_to_vcpu(ctxt), dr, dest); 7764 } 7765 7766 static int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr, 7767 unsigned long value) 7768 { 7769 7770 return kvm_set_dr(emul_to_vcpu(ctxt), dr, value); 7771 } 7772 7773 static u64 mk_cr_64(u64 curr_cr, u32 new_val) 7774 { 7775 return (curr_cr & ~((1ULL << 32) - 1)) | new_val; 7776 } 7777 7778 static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr) 7779 { 7780 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 7781 unsigned long value; 7782 7783 switch (cr) { 7784 case 0: 7785 value = kvm_read_cr0(vcpu); 7786 break; 7787 case 2: 7788 value = vcpu->arch.cr2; 7789 break; 7790 case 3: 7791 value = kvm_read_cr3(vcpu); 7792 break; 7793 case 4: 7794 value = kvm_read_cr4(vcpu); 7795 break; 7796 case 8: 7797 value = kvm_get_cr8(vcpu); 7798 break; 7799 default: 7800 kvm_err("%s: unexpected cr %u\n", __func__, cr); 7801 return 0; 7802 } 7803 7804 return value; 7805 } 7806 7807 static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val) 7808 { 7809 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 7810 int res = 0; 7811 7812 switch (cr) { 7813 case 0: 7814 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val)); 7815 break; 7816 case 2: 7817 vcpu->arch.cr2 = val; 7818 break; 7819 case 3: 7820 res = kvm_set_cr3(vcpu, val); 7821 break; 7822 case 4: 7823 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val)); 7824 break; 7825 case 8: 7826 res = kvm_set_cr8(vcpu, val); 7827 break; 7828 default: 7829 kvm_err("%s: unexpected cr %u\n", __func__, cr); 7830 res = -1; 7831 } 7832 7833 return res; 7834 } 7835 7836 static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt) 7837 { 7838 return static_call(kvm_x86_get_cpl)(emul_to_vcpu(ctxt)); 7839 } 7840 7841 static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt) 7842 { 7843 static_call(kvm_x86_get_gdt)(emul_to_vcpu(ctxt), dt); 7844 } 7845 7846 static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt) 7847 { 7848 static_call(kvm_x86_get_idt)(emul_to_vcpu(ctxt), dt); 7849 } 7850 7851 static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt) 7852 { 7853 static_call(kvm_x86_set_gdt)(emul_to_vcpu(ctxt), dt); 7854 } 7855 7856 static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt) 7857 { 7858 static_call(kvm_x86_set_idt)(emul_to_vcpu(ctxt), dt); 7859 } 7860 7861 static unsigned long emulator_get_cached_segment_base( 7862 struct x86_emulate_ctxt *ctxt, int seg) 7863 { 7864 return get_segment_base(emul_to_vcpu(ctxt), seg); 7865 } 7866 7867 static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector, 7868 struct desc_struct *desc, u32 *base3, 7869 int seg) 7870 { 7871 struct kvm_segment var; 7872 7873 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg); 7874 *selector = var.selector; 7875 7876 if (var.unusable) { 7877 memset(desc, 0, sizeof(*desc)); 7878 if (base3) 7879 *base3 = 0; 7880 return false; 7881 } 7882 7883 if (var.g) 7884 var.limit >>= 12; 7885 set_desc_limit(desc, var.limit); 7886 set_desc_base(desc, (unsigned long)var.base); 7887 #ifdef CONFIG_X86_64 7888 if (base3) 7889 *base3 = var.base >> 32; 7890 #endif 7891 desc->type = var.type; 7892 desc->s = var.s; 7893 desc->dpl = var.dpl; 7894 desc->p = var.present; 7895 desc->avl = var.avl; 7896 desc->l = var.l; 7897 desc->d = var.db; 7898 desc->g = var.g; 7899 7900 return true; 7901 } 7902 7903 static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector, 7904 struct desc_struct *desc, u32 base3, 7905 int seg) 7906 { 7907 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 7908 struct kvm_segment var; 7909 7910 var.selector = selector; 7911 var.base = get_desc_base(desc); 7912 #ifdef CONFIG_X86_64 7913 var.base |= ((u64)base3) << 32; 7914 #endif 7915 var.limit = get_desc_limit(desc); 7916 if (desc->g) 7917 var.limit = (var.limit << 12) | 0xfff; 7918 var.type = desc->type; 7919 var.dpl = desc->dpl; 7920 var.db = desc->d; 7921 var.s = desc->s; 7922 var.l = desc->l; 7923 var.g = desc->g; 7924 var.avl = desc->avl; 7925 var.present = desc->p; 7926 var.unusable = !var.present; 7927 var.padding = 0; 7928 7929 kvm_set_segment(vcpu, &var, seg); 7930 return; 7931 } 7932 7933 static int emulator_get_msr_with_filter(struct x86_emulate_ctxt *ctxt, 7934 u32 msr_index, u64 *pdata) 7935 { 7936 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 7937 int r; 7938 7939 r = kvm_get_msr_with_filter(vcpu, msr_index, pdata); 7940 7941 if (r && kvm_msr_user_space(vcpu, msr_index, KVM_EXIT_X86_RDMSR, 0, 7942 complete_emulated_rdmsr, r)) { 7943 /* Bounce to user space */ 7944 return X86EMUL_IO_NEEDED; 7945 } 7946 7947 return r; 7948 } 7949 7950 static int emulator_set_msr_with_filter(struct x86_emulate_ctxt *ctxt, 7951 u32 msr_index, u64 data) 7952 { 7953 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 7954 int r; 7955 7956 r = kvm_set_msr_with_filter(vcpu, msr_index, data); 7957 7958 if (r && kvm_msr_user_space(vcpu, msr_index, KVM_EXIT_X86_WRMSR, data, 7959 complete_emulated_msr_access, r)) { 7960 /* Bounce to user space */ 7961 return X86EMUL_IO_NEEDED; 7962 } 7963 7964 return r; 7965 } 7966 7967 static int emulator_get_msr(struct x86_emulate_ctxt *ctxt, 7968 u32 msr_index, u64 *pdata) 7969 { 7970 return kvm_get_msr(emul_to_vcpu(ctxt), msr_index, pdata); 7971 } 7972 7973 static int emulator_set_msr(struct x86_emulate_ctxt *ctxt, 7974 u32 msr_index, u64 data) 7975 { 7976 return kvm_set_msr(emul_to_vcpu(ctxt), msr_index, data); 7977 } 7978 7979 static u64 emulator_get_smbase(struct x86_emulate_ctxt *ctxt) 7980 { 7981 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 7982 7983 return vcpu->arch.smbase; 7984 } 7985 7986 static void emulator_set_smbase(struct x86_emulate_ctxt *ctxt, u64 smbase) 7987 { 7988 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 7989 7990 vcpu->arch.smbase = smbase; 7991 } 7992 7993 static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt, 7994 u32 pmc) 7995 { 7996 if (kvm_pmu_is_valid_rdpmc_ecx(emul_to_vcpu(ctxt), pmc)) 7997 return 0; 7998 return -EINVAL; 7999 } 8000 8001 static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt, 8002 u32 pmc, u64 *pdata) 8003 { 8004 return kvm_pmu_rdpmc(emul_to_vcpu(ctxt), pmc, pdata); 8005 } 8006 8007 static void emulator_halt(struct x86_emulate_ctxt *ctxt) 8008 { 8009 emul_to_vcpu(ctxt)->arch.halt_request = 1; 8010 } 8011 8012 static int emulator_intercept(struct x86_emulate_ctxt *ctxt, 8013 struct x86_instruction_info *info, 8014 enum x86_intercept_stage stage) 8015 { 8016 return static_call(kvm_x86_check_intercept)(emul_to_vcpu(ctxt), info, stage, 8017 &ctxt->exception); 8018 } 8019 8020 static bool emulator_get_cpuid(struct x86_emulate_ctxt *ctxt, 8021 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx, 8022 bool exact_only) 8023 { 8024 return kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx, exact_only); 8025 } 8026 8027 static bool emulator_guest_has_long_mode(struct x86_emulate_ctxt *ctxt) 8028 { 8029 return guest_cpuid_has(emul_to_vcpu(ctxt), X86_FEATURE_LM); 8030 } 8031 8032 static bool emulator_guest_has_movbe(struct x86_emulate_ctxt *ctxt) 8033 { 8034 return guest_cpuid_has(emul_to_vcpu(ctxt), X86_FEATURE_MOVBE); 8035 } 8036 8037 static bool emulator_guest_has_fxsr(struct x86_emulate_ctxt *ctxt) 8038 { 8039 return guest_cpuid_has(emul_to_vcpu(ctxt), X86_FEATURE_FXSR); 8040 } 8041 8042 static bool emulator_guest_has_rdpid(struct x86_emulate_ctxt *ctxt) 8043 { 8044 return guest_cpuid_has(emul_to_vcpu(ctxt), X86_FEATURE_RDPID); 8045 } 8046 8047 static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg) 8048 { 8049 return kvm_register_read_raw(emul_to_vcpu(ctxt), reg); 8050 } 8051 8052 static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val) 8053 { 8054 kvm_register_write_raw(emul_to_vcpu(ctxt), reg, val); 8055 } 8056 8057 static void emulator_set_nmi_mask(struct x86_emulate_ctxt *ctxt, bool masked) 8058 { 8059 static_call(kvm_x86_set_nmi_mask)(emul_to_vcpu(ctxt), masked); 8060 } 8061 8062 static unsigned emulator_get_hflags(struct x86_emulate_ctxt *ctxt) 8063 { 8064 return emul_to_vcpu(ctxt)->arch.hflags; 8065 } 8066 8067 static void emulator_exiting_smm(struct x86_emulate_ctxt *ctxt) 8068 { 8069 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 8070 8071 kvm_smm_changed(vcpu, false); 8072 } 8073 8074 static int emulator_leave_smm(struct x86_emulate_ctxt *ctxt, 8075 const char *smstate) 8076 { 8077 return static_call(kvm_x86_leave_smm)(emul_to_vcpu(ctxt), smstate); 8078 } 8079 8080 static void emulator_triple_fault(struct x86_emulate_ctxt *ctxt) 8081 { 8082 kvm_make_request(KVM_REQ_TRIPLE_FAULT, emul_to_vcpu(ctxt)); 8083 } 8084 8085 static int emulator_set_xcr(struct x86_emulate_ctxt *ctxt, u32 index, u64 xcr) 8086 { 8087 return __kvm_set_xcr(emul_to_vcpu(ctxt), index, xcr); 8088 } 8089 8090 static void emulator_vm_bugged(struct x86_emulate_ctxt *ctxt) 8091 { 8092 struct kvm *kvm = emul_to_vcpu(ctxt)->kvm; 8093 8094 if (!kvm->vm_bugged) 8095 kvm_vm_bugged(kvm); 8096 } 8097 8098 static const struct x86_emulate_ops emulate_ops = { 8099 .vm_bugged = emulator_vm_bugged, 8100 .read_gpr = emulator_read_gpr, 8101 .write_gpr = emulator_write_gpr, 8102 .read_std = emulator_read_std, 8103 .write_std = emulator_write_std, 8104 .read_phys = kvm_read_guest_phys_system, 8105 .fetch = kvm_fetch_guest_virt, 8106 .read_emulated = emulator_read_emulated, 8107 .write_emulated = emulator_write_emulated, 8108 .cmpxchg_emulated = emulator_cmpxchg_emulated, 8109 .invlpg = emulator_invlpg, 8110 .pio_in_emulated = emulator_pio_in_emulated, 8111 .pio_out_emulated = emulator_pio_out_emulated, 8112 .get_segment = emulator_get_segment, 8113 .set_segment = emulator_set_segment, 8114 .get_cached_segment_base = emulator_get_cached_segment_base, 8115 .get_gdt = emulator_get_gdt, 8116 .get_idt = emulator_get_idt, 8117 .set_gdt = emulator_set_gdt, 8118 .set_idt = emulator_set_idt, 8119 .get_cr = emulator_get_cr, 8120 .set_cr = emulator_set_cr, 8121 .cpl = emulator_get_cpl, 8122 .get_dr = emulator_get_dr, 8123 .set_dr = emulator_set_dr, 8124 .get_smbase = emulator_get_smbase, 8125 .set_smbase = emulator_set_smbase, 8126 .set_msr_with_filter = emulator_set_msr_with_filter, 8127 .get_msr_with_filter = emulator_get_msr_with_filter, 8128 .set_msr = emulator_set_msr, 8129 .get_msr = emulator_get_msr, 8130 .check_pmc = emulator_check_pmc, 8131 .read_pmc = emulator_read_pmc, 8132 .halt = emulator_halt, 8133 .wbinvd = emulator_wbinvd, 8134 .fix_hypercall = emulator_fix_hypercall, 8135 .intercept = emulator_intercept, 8136 .get_cpuid = emulator_get_cpuid, 8137 .guest_has_long_mode = emulator_guest_has_long_mode, 8138 .guest_has_movbe = emulator_guest_has_movbe, 8139 .guest_has_fxsr = emulator_guest_has_fxsr, 8140 .guest_has_rdpid = emulator_guest_has_rdpid, 8141 .set_nmi_mask = emulator_set_nmi_mask, 8142 .get_hflags = emulator_get_hflags, 8143 .exiting_smm = emulator_exiting_smm, 8144 .leave_smm = emulator_leave_smm, 8145 .triple_fault = emulator_triple_fault, 8146 .set_xcr = emulator_set_xcr, 8147 }; 8148 8149 static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask) 8150 { 8151 u32 int_shadow = static_call(kvm_x86_get_interrupt_shadow)(vcpu); 8152 /* 8153 * an sti; sti; sequence only disable interrupts for the first 8154 * instruction. So, if the last instruction, be it emulated or 8155 * not, left the system with the INT_STI flag enabled, it 8156 * means that the last instruction is an sti. We should not 8157 * leave the flag on in this case. The same goes for mov ss 8158 */ 8159 if (int_shadow & mask) 8160 mask = 0; 8161 if (unlikely(int_shadow || mask)) { 8162 static_call(kvm_x86_set_interrupt_shadow)(vcpu, mask); 8163 if (!mask) 8164 kvm_make_request(KVM_REQ_EVENT, vcpu); 8165 } 8166 } 8167 8168 static bool inject_emulated_exception(struct kvm_vcpu *vcpu) 8169 { 8170 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt; 8171 if (ctxt->exception.vector == PF_VECTOR) 8172 return kvm_inject_emulated_page_fault(vcpu, &ctxt->exception); 8173 8174 if (ctxt->exception.error_code_valid) 8175 kvm_queue_exception_e(vcpu, ctxt->exception.vector, 8176 ctxt->exception.error_code); 8177 else 8178 kvm_queue_exception(vcpu, ctxt->exception.vector); 8179 return false; 8180 } 8181 8182 static struct x86_emulate_ctxt *alloc_emulate_ctxt(struct kvm_vcpu *vcpu) 8183 { 8184 struct x86_emulate_ctxt *ctxt; 8185 8186 ctxt = kmem_cache_zalloc(x86_emulator_cache, GFP_KERNEL_ACCOUNT); 8187 if (!ctxt) { 8188 pr_err("kvm: failed to allocate vcpu's emulator\n"); 8189 return NULL; 8190 } 8191 8192 ctxt->vcpu = vcpu; 8193 ctxt->ops = &emulate_ops; 8194 vcpu->arch.emulate_ctxt = ctxt; 8195 8196 return ctxt; 8197 } 8198 8199 static void init_emulate_ctxt(struct kvm_vcpu *vcpu) 8200 { 8201 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt; 8202 int cs_db, cs_l; 8203 8204 static_call(kvm_x86_get_cs_db_l_bits)(vcpu, &cs_db, &cs_l); 8205 8206 ctxt->gpa_available = false; 8207 ctxt->eflags = kvm_get_rflags(vcpu); 8208 ctxt->tf = (ctxt->eflags & X86_EFLAGS_TF) != 0; 8209 8210 ctxt->eip = kvm_rip_read(vcpu); 8211 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL : 8212 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 : 8213 (cs_l && is_long_mode(vcpu)) ? X86EMUL_MODE_PROT64 : 8214 cs_db ? X86EMUL_MODE_PROT32 : 8215 X86EMUL_MODE_PROT16; 8216 BUILD_BUG_ON(HF_GUEST_MASK != X86EMUL_GUEST_MASK); 8217 BUILD_BUG_ON(HF_SMM_MASK != X86EMUL_SMM_MASK); 8218 BUILD_BUG_ON(HF_SMM_INSIDE_NMI_MASK != X86EMUL_SMM_INSIDE_NMI_MASK); 8219 8220 ctxt->interruptibility = 0; 8221 ctxt->have_exception = false; 8222 ctxt->exception.vector = -1; 8223 ctxt->perm_ok = false; 8224 8225 init_decode_cache(ctxt); 8226 vcpu->arch.emulate_regs_need_sync_from_vcpu = false; 8227 } 8228 8229 void kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip) 8230 { 8231 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt; 8232 int ret; 8233 8234 init_emulate_ctxt(vcpu); 8235 8236 ctxt->op_bytes = 2; 8237 ctxt->ad_bytes = 2; 8238 ctxt->_eip = ctxt->eip + inc_eip; 8239 ret = emulate_int_real(ctxt, irq); 8240 8241 if (ret != X86EMUL_CONTINUE) { 8242 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); 8243 } else { 8244 ctxt->eip = ctxt->_eip; 8245 kvm_rip_write(vcpu, ctxt->eip); 8246 kvm_set_rflags(vcpu, ctxt->eflags); 8247 } 8248 } 8249 EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt); 8250 8251 static void prepare_emulation_failure_exit(struct kvm_vcpu *vcpu, u64 *data, 8252 u8 ndata, u8 *insn_bytes, u8 insn_size) 8253 { 8254 struct kvm_run *run = vcpu->run; 8255 u64 info[5]; 8256 u8 info_start; 8257 8258 /* 8259 * Zero the whole array used to retrieve the exit info, as casting to 8260 * u32 for select entries will leave some chunks uninitialized. 8261 */ 8262 memset(&info, 0, sizeof(info)); 8263 8264 static_call(kvm_x86_get_exit_info)(vcpu, (u32 *)&info[0], &info[1], 8265 &info[2], (u32 *)&info[3], 8266 (u32 *)&info[4]); 8267 8268 run->exit_reason = KVM_EXIT_INTERNAL_ERROR; 8269 run->emulation_failure.suberror = KVM_INTERNAL_ERROR_EMULATION; 8270 8271 /* 8272 * There's currently space for 13 entries, but 5 are used for the exit 8273 * reason and info. Restrict to 4 to reduce the maintenance burden 8274 * when expanding kvm_run.emulation_failure in the future. 8275 */ 8276 if (WARN_ON_ONCE(ndata > 4)) 8277 ndata = 4; 8278 8279 /* Always include the flags as a 'data' entry. */ 8280 info_start = 1; 8281 run->emulation_failure.flags = 0; 8282 8283 if (insn_size) { 8284 BUILD_BUG_ON((sizeof(run->emulation_failure.insn_size) + 8285 sizeof(run->emulation_failure.insn_bytes) != 16)); 8286 info_start += 2; 8287 run->emulation_failure.flags |= 8288 KVM_INTERNAL_ERROR_EMULATION_FLAG_INSTRUCTION_BYTES; 8289 run->emulation_failure.insn_size = insn_size; 8290 memset(run->emulation_failure.insn_bytes, 0x90, 8291 sizeof(run->emulation_failure.insn_bytes)); 8292 memcpy(run->emulation_failure.insn_bytes, insn_bytes, insn_size); 8293 } 8294 8295 memcpy(&run->internal.data[info_start], info, sizeof(info)); 8296 memcpy(&run->internal.data[info_start + ARRAY_SIZE(info)], data, 8297 ndata * sizeof(data[0])); 8298 8299 run->emulation_failure.ndata = info_start + ARRAY_SIZE(info) + ndata; 8300 } 8301 8302 static void prepare_emulation_ctxt_failure_exit(struct kvm_vcpu *vcpu) 8303 { 8304 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt; 8305 8306 prepare_emulation_failure_exit(vcpu, NULL, 0, ctxt->fetch.data, 8307 ctxt->fetch.end - ctxt->fetch.data); 8308 } 8309 8310 void __kvm_prepare_emulation_failure_exit(struct kvm_vcpu *vcpu, u64 *data, 8311 u8 ndata) 8312 { 8313 prepare_emulation_failure_exit(vcpu, data, ndata, NULL, 0); 8314 } 8315 EXPORT_SYMBOL_GPL(__kvm_prepare_emulation_failure_exit); 8316 8317 void kvm_prepare_emulation_failure_exit(struct kvm_vcpu *vcpu) 8318 { 8319 __kvm_prepare_emulation_failure_exit(vcpu, NULL, 0); 8320 } 8321 EXPORT_SYMBOL_GPL(kvm_prepare_emulation_failure_exit); 8322 8323 static int handle_emulation_failure(struct kvm_vcpu *vcpu, int emulation_type) 8324 { 8325 struct kvm *kvm = vcpu->kvm; 8326 8327 ++vcpu->stat.insn_emulation_fail; 8328 trace_kvm_emulate_insn_failed(vcpu); 8329 8330 if (emulation_type & EMULTYPE_VMWARE_GP) { 8331 kvm_queue_exception_e(vcpu, GP_VECTOR, 0); 8332 return 1; 8333 } 8334 8335 if (kvm->arch.exit_on_emulation_error || 8336 (emulation_type & EMULTYPE_SKIP)) { 8337 prepare_emulation_ctxt_failure_exit(vcpu); 8338 return 0; 8339 } 8340 8341 kvm_queue_exception(vcpu, UD_VECTOR); 8342 8343 if (!is_guest_mode(vcpu) && static_call(kvm_x86_get_cpl)(vcpu) == 0) { 8344 prepare_emulation_ctxt_failure_exit(vcpu); 8345 return 0; 8346 } 8347 8348 return 1; 8349 } 8350 8351 static bool reexecute_instruction(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa, 8352 bool write_fault_to_shadow_pgtable, 8353 int emulation_type) 8354 { 8355 gpa_t gpa = cr2_or_gpa; 8356 kvm_pfn_t pfn; 8357 8358 if (!(emulation_type & EMULTYPE_ALLOW_RETRY_PF)) 8359 return false; 8360 8361 if (WARN_ON_ONCE(is_guest_mode(vcpu)) || 8362 WARN_ON_ONCE(!(emulation_type & EMULTYPE_PF))) 8363 return false; 8364 8365 if (!vcpu->arch.mmu->root_role.direct) { 8366 /* 8367 * Write permission should be allowed since only 8368 * write access need to be emulated. 8369 */ 8370 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2_or_gpa, NULL); 8371 8372 /* 8373 * If the mapping is invalid in guest, let cpu retry 8374 * it to generate fault. 8375 */ 8376 if (gpa == INVALID_GPA) 8377 return true; 8378 } 8379 8380 /* 8381 * Do not retry the unhandleable instruction if it faults on the 8382 * readonly host memory, otherwise it will goto a infinite loop: 8383 * retry instruction -> write #PF -> emulation fail -> retry 8384 * instruction -> ... 8385 */ 8386 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa)); 8387 8388 /* 8389 * If the instruction failed on the error pfn, it can not be fixed, 8390 * report the error to userspace. 8391 */ 8392 if (is_error_noslot_pfn(pfn)) 8393 return false; 8394 8395 kvm_release_pfn_clean(pfn); 8396 8397 /* The instructions are well-emulated on direct mmu. */ 8398 if (vcpu->arch.mmu->root_role.direct) { 8399 unsigned int indirect_shadow_pages; 8400 8401 write_lock(&vcpu->kvm->mmu_lock); 8402 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages; 8403 write_unlock(&vcpu->kvm->mmu_lock); 8404 8405 if (indirect_shadow_pages) 8406 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa)); 8407 8408 return true; 8409 } 8410 8411 /* 8412 * if emulation was due to access to shadowed page table 8413 * and it failed try to unshadow page and re-enter the 8414 * guest to let CPU execute the instruction. 8415 */ 8416 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa)); 8417 8418 /* 8419 * If the access faults on its page table, it can not 8420 * be fixed by unprotecting shadow page and it should 8421 * be reported to userspace. 8422 */ 8423 return !write_fault_to_shadow_pgtable; 8424 } 8425 8426 static bool retry_instruction(struct x86_emulate_ctxt *ctxt, 8427 gpa_t cr2_or_gpa, int emulation_type) 8428 { 8429 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 8430 unsigned long last_retry_eip, last_retry_addr, gpa = cr2_or_gpa; 8431 8432 last_retry_eip = vcpu->arch.last_retry_eip; 8433 last_retry_addr = vcpu->arch.last_retry_addr; 8434 8435 /* 8436 * If the emulation is caused by #PF and it is non-page_table 8437 * writing instruction, it means the VM-EXIT is caused by shadow 8438 * page protected, we can zap the shadow page and retry this 8439 * instruction directly. 8440 * 8441 * Note: if the guest uses a non-page-table modifying instruction 8442 * on the PDE that points to the instruction, then we will unmap 8443 * the instruction and go to an infinite loop. So, we cache the 8444 * last retried eip and the last fault address, if we meet the eip 8445 * and the address again, we can break out of the potential infinite 8446 * loop. 8447 */ 8448 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0; 8449 8450 if (!(emulation_type & EMULTYPE_ALLOW_RETRY_PF)) 8451 return false; 8452 8453 if (WARN_ON_ONCE(is_guest_mode(vcpu)) || 8454 WARN_ON_ONCE(!(emulation_type & EMULTYPE_PF))) 8455 return false; 8456 8457 if (x86_page_table_writing_insn(ctxt)) 8458 return false; 8459 8460 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2_or_gpa) 8461 return false; 8462 8463 vcpu->arch.last_retry_eip = ctxt->eip; 8464 vcpu->arch.last_retry_addr = cr2_or_gpa; 8465 8466 if (!vcpu->arch.mmu->root_role.direct) 8467 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2_or_gpa, NULL); 8468 8469 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa)); 8470 8471 return true; 8472 } 8473 8474 static int complete_emulated_mmio(struct kvm_vcpu *vcpu); 8475 static int complete_emulated_pio(struct kvm_vcpu *vcpu); 8476 8477 static void kvm_smm_changed(struct kvm_vcpu *vcpu, bool entering_smm) 8478 { 8479 trace_kvm_smm_transition(vcpu->vcpu_id, vcpu->arch.smbase, entering_smm); 8480 8481 if (entering_smm) { 8482 vcpu->arch.hflags |= HF_SMM_MASK; 8483 } else { 8484 vcpu->arch.hflags &= ~(HF_SMM_MASK | HF_SMM_INSIDE_NMI_MASK); 8485 8486 /* Process a latched INIT or SMI, if any. */ 8487 kvm_make_request(KVM_REQ_EVENT, vcpu); 8488 8489 /* 8490 * Even if KVM_SET_SREGS2 loaded PDPTRs out of band, 8491 * on SMM exit we still need to reload them from 8492 * guest memory 8493 */ 8494 vcpu->arch.pdptrs_from_userspace = false; 8495 } 8496 8497 kvm_mmu_reset_context(vcpu); 8498 } 8499 8500 static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7, 8501 unsigned long *db) 8502 { 8503 u32 dr6 = 0; 8504 int i; 8505 u32 enable, rwlen; 8506 8507 enable = dr7; 8508 rwlen = dr7 >> 16; 8509 for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4) 8510 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr) 8511 dr6 |= (1 << i); 8512 return dr6; 8513 } 8514 8515 static int kvm_vcpu_do_singlestep(struct kvm_vcpu *vcpu) 8516 { 8517 struct kvm_run *kvm_run = vcpu->run; 8518 8519 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) { 8520 kvm_run->debug.arch.dr6 = DR6_BS | DR6_ACTIVE_LOW; 8521 kvm_run->debug.arch.pc = kvm_get_linear_rip(vcpu); 8522 kvm_run->debug.arch.exception = DB_VECTOR; 8523 kvm_run->exit_reason = KVM_EXIT_DEBUG; 8524 return 0; 8525 } 8526 kvm_queue_exception_p(vcpu, DB_VECTOR, DR6_BS); 8527 return 1; 8528 } 8529 8530 int kvm_skip_emulated_instruction(struct kvm_vcpu *vcpu) 8531 { 8532 unsigned long rflags = static_call(kvm_x86_get_rflags)(vcpu); 8533 int r; 8534 8535 r = static_call(kvm_x86_skip_emulated_instruction)(vcpu); 8536 if (unlikely(!r)) 8537 return 0; 8538 8539 kvm_pmu_trigger_event(vcpu, PERF_COUNT_HW_INSTRUCTIONS); 8540 8541 /* 8542 * rflags is the old, "raw" value of the flags. The new value has 8543 * not been saved yet. 8544 * 8545 * This is correct even for TF set by the guest, because "the 8546 * processor will not generate this exception after the instruction 8547 * that sets the TF flag". 8548 */ 8549 if (unlikely(rflags & X86_EFLAGS_TF)) 8550 r = kvm_vcpu_do_singlestep(vcpu); 8551 return r; 8552 } 8553 EXPORT_SYMBOL_GPL(kvm_skip_emulated_instruction); 8554 8555 static bool kvm_vcpu_check_code_breakpoint(struct kvm_vcpu *vcpu, int *r) 8556 { 8557 if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) && 8558 (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) { 8559 struct kvm_run *kvm_run = vcpu->run; 8560 unsigned long eip = kvm_get_linear_rip(vcpu); 8561 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0, 8562 vcpu->arch.guest_debug_dr7, 8563 vcpu->arch.eff_db); 8564 8565 if (dr6 != 0) { 8566 kvm_run->debug.arch.dr6 = dr6 | DR6_ACTIVE_LOW; 8567 kvm_run->debug.arch.pc = eip; 8568 kvm_run->debug.arch.exception = DB_VECTOR; 8569 kvm_run->exit_reason = KVM_EXIT_DEBUG; 8570 *r = 0; 8571 return true; 8572 } 8573 } 8574 8575 if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) && 8576 !(kvm_get_rflags(vcpu) & X86_EFLAGS_RF)) { 8577 unsigned long eip = kvm_get_linear_rip(vcpu); 8578 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0, 8579 vcpu->arch.dr7, 8580 vcpu->arch.db); 8581 8582 if (dr6 != 0) { 8583 kvm_queue_exception_p(vcpu, DB_VECTOR, dr6); 8584 *r = 1; 8585 return true; 8586 } 8587 } 8588 8589 return false; 8590 } 8591 8592 static bool is_vmware_backdoor_opcode(struct x86_emulate_ctxt *ctxt) 8593 { 8594 switch (ctxt->opcode_len) { 8595 case 1: 8596 switch (ctxt->b) { 8597 case 0xe4: /* IN */ 8598 case 0xe5: 8599 case 0xec: 8600 case 0xed: 8601 case 0xe6: /* OUT */ 8602 case 0xe7: 8603 case 0xee: 8604 case 0xef: 8605 case 0x6c: /* INS */ 8606 case 0x6d: 8607 case 0x6e: /* OUTS */ 8608 case 0x6f: 8609 return true; 8610 } 8611 break; 8612 case 2: 8613 switch (ctxt->b) { 8614 case 0x33: /* RDPMC */ 8615 return true; 8616 } 8617 break; 8618 } 8619 8620 return false; 8621 } 8622 8623 /* 8624 * Decode an instruction for emulation. The caller is responsible for handling 8625 * code breakpoints. Note, manually detecting code breakpoints is unnecessary 8626 * (and wrong) when emulating on an intercepted fault-like exception[*], as 8627 * code breakpoints have higher priority and thus have already been done by 8628 * hardware. 8629 * 8630 * [*] Except #MC, which is higher priority, but KVM should never emulate in 8631 * response to a machine check. 8632 */ 8633 int x86_decode_emulated_instruction(struct kvm_vcpu *vcpu, int emulation_type, 8634 void *insn, int insn_len) 8635 { 8636 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt; 8637 int r; 8638 8639 init_emulate_ctxt(vcpu); 8640 8641 r = x86_decode_insn(ctxt, insn, insn_len, emulation_type); 8642 8643 trace_kvm_emulate_insn_start(vcpu); 8644 ++vcpu->stat.insn_emulation; 8645 8646 return r; 8647 } 8648 EXPORT_SYMBOL_GPL(x86_decode_emulated_instruction); 8649 8650 int x86_emulate_instruction(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa, 8651 int emulation_type, void *insn, int insn_len) 8652 { 8653 int r; 8654 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt; 8655 bool writeback = true; 8656 bool write_fault_to_spt; 8657 8658 if (unlikely(!kvm_can_emulate_insn(vcpu, emulation_type, insn, insn_len))) 8659 return 1; 8660 8661 vcpu->arch.l1tf_flush_l1d = true; 8662 8663 /* 8664 * Clear write_fault_to_shadow_pgtable here to ensure it is 8665 * never reused. 8666 */ 8667 write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable; 8668 vcpu->arch.write_fault_to_shadow_pgtable = false; 8669 8670 if (!(emulation_type & EMULTYPE_NO_DECODE)) { 8671 kvm_clear_exception_queue(vcpu); 8672 8673 /* 8674 * Return immediately if RIP hits a code breakpoint, such #DBs 8675 * are fault-like and are higher priority than any faults on 8676 * the code fetch itself. 8677 */ 8678 if (!(emulation_type & EMULTYPE_SKIP) && 8679 kvm_vcpu_check_code_breakpoint(vcpu, &r)) 8680 return r; 8681 8682 r = x86_decode_emulated_instruction(vcpu, emulation_type, 8683 insn, insn_len); 8684 if (r != EMULATION_OK) { 8685 if ((emulation_type & EMULTYPE_TRAP_UD) || 8686 (emulation_type & EMULTYPE_TRAP_UD_FORCED)) { 8687 kvm_queue_exception(vcpu, UD_VECTOR); 8688 return 1; 8689 } 8690 if (reexecute_instruction(vcpu, cr2_or_gpa, 8691 write_fault_to_spt, 8692 emulation_type)) 8693 return 1; 8694 if (ctxt->have_exception) { 8695 /* 8696 * #UD should result in just EMULATION_FAILED, and trap-like 8697 * exception should not be encountered during decode. 8698 */ 8699 WARN_ON_ONCE(ctxt->exception.vector == UD_VECTOR || 8700 exception_type(ctxt->exception.vector) == EXCPT_TRAP); 8701 inject_emulated_exception(vcpu); 8702 return 1; 8703 } 8704 return handle_emulation_failure(vcpu, emulation_type); 8705 } 8706 } 8707 8708 if ((emulation_type & EMULTYPE_VMWARE_GP) && 8709 !is_vmware_backdoor_opcode(ctxt)) { 8710 kvm_queue_exception_e(vcpu, GP_VECTOR, 0); 8711 return 1; 8712 } 8713 8714 /* 8715 * EMULTYPE_SKIP without EMULTYPE_COMPLETE_USER_EXIT is intended for 8716 * use *only* by vendor callbacks for kvm_skip_emulated_instruction(). 8717 * The caller is responsible for updating interruptibility state and 8718 * injecting single-step #DBs. 8719 */ 8720 if (emulation_type & EMULTYPE_SKIP) { 8721 if (ctxt->mode != X86EMUL_MODE_PROT64) 8722 ctxt->eip = (u32)ctxt->_eip; 8723 else 8724 ctxt->eip = ctxt->_eip; 8725 8726 if (emulation_type & EMULTYPE_COMPLETE_USER_EXIT) { 8727 r = 1; 8728 goto writeback; 8729 } 8730 8731 kvm_rip_write(vcpu, ctxt->eip); 8732 if (ctxt->eflags & X86_EFLAGS_RF) 8733 kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF); 8734 return 1; 8735 } 8736 8737 if (retry_instruction(ctxt, cr2_or_gpa, emulation_type)) 8738 return 1; 8739 8740 /* this is needed for vmware backdoor interface to work since it 8741 changes registers values during IO operation */ 8742 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) { 8743 vcpu->arch.emulate_regs_need_sync_from_vcpu = false; 8744 emulator_invalidate_register_cache(ctxt); 8745 } 8746 8747 restart: 8748 if (emulation_type & EMULTYPE_PF) { 8749 /* Save the faulting GPA (cr2) in the address field */ 8750 ctxt->exception.address = cr2_or_gpa; 8751 8752 /* With shadow page tables, cr2 contains a GVA or nGPA. */ 8753 if (vcpu->arch.mmu->root_role.direct) { 8754 ctxt->gpa_available = true; 8755 ctxt->gpa_val = cr2_or_gpa; 8756 } 8757 } else { 8758 /* Sanitize the address out of an abundance of paranoia. */ 8759 ctxt->exception.address = 0; 8760 } 8761 8762 r = x86_emulate_insn(ctxt); 8763 8764 if (r == EMULATION_INTERCEPTED) 8765 return 1; 8766 8767 if (r == EMULATION_FAILED) { 8768 if (reexecute_instruction(vcpu, cr2_or_gpa, write_fault_to_spt, 8769 emulation_type)) 8770 return 1; 8771 8772 return handle_emulation_failure(vcpu, emulation_type); 8773 } 8774 8775 if (ctxt->have_exception) { 8776 r = 1; 8777 if (inject_emulated_exception(vcpu)) 8778 return r; 8779 } else if (vcpu->arch.pio.count) { 8780 if (!vcpu->arch.pio.in) { 8781 /* FIXME: return into emulator if single-stepping. */ 8782 vcpu->arch.pio.count = 0; 8783 } else { 8784 writeback = false; 8785 vcpu->arch.complete_userspace_io = complete_emulated_pio; 8786 } 8787 r = 0; 8788 } else if (vcpu->mmio_needed) { 8789 ++vcpu->stat.mmio_exits; 8790 8791 if (!vcpu->mmio_is_write) 8792 writeback = false; 8793 r = 0; 8794 vcpu->arch.complete_userspace_io = complete_emulated_mmio; 8795 } else if (vcpu->arch.complete_userspace_io) { 8796 writeback = false; 8797 r = 0; 8798 } else if (r == EMULATION_RESTART) 8799 goto restart; 8800 else 8801 r = 1; 8802 8803 writeback: 8804 if (writeback) { 8805 unsigned long rflags = static_call(kvm_x86_get_rflags)(vcpu); 8806 toggle_interruptibility(vcpu, ctxt->interruptibility); 8807 vcpu->arch.emulate_regs_need_sync_to_vcpu = false; 8808 if (!ctxt->have_exception || 8809 exception_type(ctxt->exception.vector) == EXCPT_TRAP) { 8810 kvm_pmu_trigger_event(vcpu, PERF_COUNT_HW_INSTRUCTIONS); 8811 if (ctxt->is_branch) 8812 kvm_pmu_trigger_event(vcpu, PERF_COUNT_HW_BRANCH_INSTRUCTIONS); 8813 kvm_rip_write(vcpu, ctxt->eip); 8814 if (r && (ctxt->tf || (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP))) 8815 r = kvm_vcpu_do_singlestep(vcpu); 8816 static_call_cond(kvm_x86_update_emulated_instruction)(vcpu); 8817 __kvm_set_rflags(vcpu, ctxt->eflags); 8818 } 8819 8820 /* 8821 * For STI, interrupts are shadowed; so KVM_REQ_EVENT will 8822 * do nothing, and it will be requested again as soon as 8823 * the shadow expires. But we still need to check here, 8824 * because POPF has no interrupt shadow. 8825 */ 8826 if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF)) 8827 kvm_make_request(KVM_REQ_EVENT, vcpu); 8828 } else 8829 vcpu->arch.emulate_regs_need_sync_to_vcpu = true; 8830 8831 return r; 8832 } 8833 8834 int kvm_emulate_instruction(struct kvm_vcpu *vcpu, int emulation_type) 8835 { 8836 return x86_emulate_instruction(vcpu, 0, emulation_type, NULL, 0); 8837 } 8838 EXPORT_SYMBOL_GPL(kvm_emulate_instruction); 8839 8840 int kvm_emulate_instruction_from_buffer(struct kvm_vcpu *vcpu, 8841 void *insn, int insn_len) 8842 { 8843 return x86_emulate_instruction(vcpu, 0, 0, insn, insn_len); 8844 } 8845 EXPORT_SYMBOL_GPL(kvm_emulate_instruction_from_buffer); 8846 8847 static int complete_fast_pio_out_port_0x7e(struct kvm_vcpu *vcpu) 8848 { 8849 vcpu->arch.pio.count = 0; 8850 return 1; 8851 } 8852 8853 static int complete_fast_pio_out(struct kvm_vcpu *vcpu) 8854 { 8855 vcpu->arch.pio.count = 0; 8856 8857 if (unlikely(!kvm_is_linear_rip(vcpu, vcpu->arch.pio.linear_rip))) 8858 return 1; 8859 8860 return kvm_skip_emulated_instruction(vcpu); 8861 } 8862 8863 static int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, 8864 unsigned short port) 8865 { 8866 unsigned long val = kvm_rax_read(vcpu); 8867 int ret = emulator_pio_out(vcpu, size, port, &val, 1); 8868 8869 if (ret) 8870 return ret; 8871 8872 /* 8873 * Workaround userspace that relies on old KVM behavior of %rip being 8874 * incremented prior to exiting to userspace to handle "OUT 0x7e". 8875 */ 8876 if (port == 0x7e && 8877 kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_OUT_7E_INC_RIP)) { 8878 vcpu->arch.complete_userspace_io = 8879 complete_fast_pio_out_port_0x7e; 8880 kvm_skip_emulated_instruction(vcpu); 8881 } else { 8882 vcpu->arch.pio.linear_rip = kvm_get_linear_rip(vcpu); 8883 vcpu->arch.complete_userspace_io = complete_fast_pio_out; 8884 } 8885 return 0; 8886 } 8887 8888 static int complete_fast_pio_in(struct kvm_vcpu *vcpu) 8889 { 8890 unsigned long val; 8891 8892 /* We should only ever be called with arch.pio.count equal to 1 */ 8893 BUG_ON(vcpu->arch.pio.count != 1); 8894 8895 if (unlikely(!kvm_is_linear_rip(vcpu, vcpu->arch.pio.linear_rip))) { 8896 vcpu->arch.pio.count = 0; 8897 return 1; 8898 } 8899 8900 /* For size less than 4 we merge, else we zero extend */ 8901 val = (vcpu->arch.pio.size < 4) ? kvm_rax_read(vcpu) : 0; 8902 8903 complete_emulator_pio_in(vcpu, &val); 8904 kvm_rax_write(vcpu, val); 8905 8906 return kvm_skip_emulated_instruction(vcpu); 8907 } 8908 8909 static int kvm_fast_pio_in(struct kvm_vcpu *vcpu, int size, 8910 unsigned short port) 8911 { 8912 unsigned long val; 8913 int ret; 8914 8915 /* For size less than 4 we merge, else we zero extend */ 8916 val = (size < 4) ? kvm_rax_read(vcpu) : 0; 8917 8918 ret = emulator_pio_in(vcpu, size, port, &val, 1); 8919 if (ret) { 8920 kvm_rax_write(vcpu, val); 8921 return ret; 8922 } 8923 8924 vcpu->arch.pio.linear_rip = kvm_get_linear_rip(vcpu); 8925 vcpu->arch.complete_userspace_io = complete_fast_pio_in; 8926 8927 return 0; 8928 } 8929 8930 int kvm_fast_pio(struct kvm_vcpu *vcpu, int size, unsigned short port, int in) 8931 { 8932 int ret; 8933 8934 if (in) 8935 ret = kvm_fast_pio_in(vcpu, size, port); 8936 else 8937 ret = kvm_fast_pio_out(vcpu, size, port); 8938 return ret && kvm_skip_emulated_instruction(vcpu); 8939 } 8940 EXPORT_SYMBOL_GPL(kvm_fast_pio); 8941 8942 static int kvmclock_cpu_down_prep(unsigned int cpu) 8943 { 8944 __this_cpu_write(cpu_tsc_khz, 0); 8945 return 0; 8946 } 8947 8948 static void tsc_khz_changed(void *data) 8949 { 8950 struct cpufreq_freqs *freq = data; 8951 unsigned long khz = 0; 8952 8953 if (data) 8954 khz = freq->new; 8955 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) 8956 khz = cpufreq_quick_get(raw_smp_processor_id()); 8957 if (!khz) 8958 khz = tsc_khz; 8959 __this_cpu_write(cpu_tsc_khz, khz); 8960 } 8961 8962 #ifdef CONFIG_X86_64 8963 static void kvm_hyperv_tsc_notifier(void) 8964 { 8965 struct kvm *kvm; 8966 int cpu; 8967 8968 mutex_lock(&kvm_lock); 8969 list_for_each_entry(kvm, &vm_list, vm_list) 8970 kvm_make_mclock_inprogress_request(kvm); 8971 8972 /* no guest entries from this point */ 8973 hyperv_stop_tsc_emulation(); 8974 8975 /* TSC frequency always matches when on Hyper-V */ 8976 for_each_present_cpu(cpu) 8977 per_cpu(cpu_tsc_khz, cpu) = tsc_khz; 8978 kvm_caps.max_guest_tsc_khz = tsc_khz; 8979 8980 list_for_each_entry(kvm, &vm_list, vm_list) { 8981 __kvm_start_pvclock_update(kvm); 8982 pvclock_update_vm_gtod_copy(kvm); 8983 kvm_end_pvclock_update(kvm); 8984 } 8985 8986 mutex_unlock(&kvm_lock); 8987 } 8988 #endif 8989 8990 static void __kvmclock_cpufreq_notifier(struct cpufreq_freqs *freq, int cpu) 8991 { 8992 struct kvm *kvm; 8993 struct kvm_vcpu *vcpu; 8994 int send_ipi = 0; 8995 unsigned long i; 8996 8997 /* 8998 * We allow guests to temporarily run on slowing clocks, 8999 * provided we notify them after, or to run on accelerating 9000 * clocks, provided we notify them before. Thus time never 9001 * goes backwards. 9002 * 9003 * However, we have a problem. We can't atomically update 9004 * the frequency of a given CPU from this function; it is 9005 * merely a notifier, which can be called from any CPU. 9006 * Changing the TSC frequency at arbitrary points in time 9007 * requires a recomputation of local variables related to 9008 * the TSC for each VCPU. We must flag these local variables 9009 * to be updated and be sure the update takes place with the 9010 * new frequency before any guests proceed. 9011 * 9012 * Unfortunately, the combination of hotplug CPU and frequency 9013 * change creates an intractable locking scenario; the order 9014 * of when these callouts happen is undefined with respect to 9015 * CPU hotplug, and they can race with each other. As such, 9016 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is 9017 * undefined; you can actually have a CPU frequency change take 9018 * place in between the computation of X and the setting of the 9019 * variable. To protect against this problem, all updates of 9020 * the per_cpu tsc_khz variable are done in an interrupt 9021 * protected IPI, and all callers wishing to update the value 9022 * must wait for a synchronous IPI to complete (which is trivial 9023 * if the caller is on the CPU already). This establishes the 9024 * necessary total order on variable updates. 9025 * 9026 * Note that because a guest time update may take place 9027 * anytime after the setting of the VCPU's request bit, the 9028 * correct TSC value must be set before the request. However, 9029 * to ensure the update actually makes it to any guest which 9030 * starts running in hardware virtualization between the set 9031 * and the acquisition of the spinlock, we must also ping the 9032 * CPU after setting the request bit. 9033 * 9034 */ 9035 9036 smp_call_function_single(cpu, tsc_khz_changed, freq, 1); 9037 9038 mutex_lock(&kvm_lock); 9039 list_for_each_entry(kvm, &vm_list, vm_list) { 9040 kvm_for_each_vcpu(i, vcpu, kvm) { 9041 if (vcpu->cpu != cpu) 9042 continue; 9043 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 9044 if (vcpu->cpu != raw_smp_processor_id()) 9045 send_ipi = 1; 9046 } 9047 } 9048 mutex_unlock(&kvm_lock); 9049 9050 if (freq->old < freq->new && send_ipi) { 9051 /* 9052 * We upscale the frequency. Must make the guest 9053 * doesn't see old kvmclock values while running with 9054 * the new frequency, otherwise we risk the guest sees 9055 * time go backwards. 9056 * 9057 * In case we update the frequency for another cpu 9058 * (which might be in guest context) send an interrupt 9059 * to kick the cpu out of guest context. Next time 9060 * guest context is entered kvmclock will be updated, 9061 * so the guest will not see stale values. 9062 */ 9063 smp_call_function_single(cpu, tsc_khz_changed, freq, 1); 9064 } 9065 } 9066 9067 static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val, 9068 void *data) 9069 { 9070 struct cpufreq_freqs *freq = data; 9071 int cpu; 9072 9073 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new) 9074 return 0; 9075 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new) 9076 return 0; 9077 9078 for_each_cpu(cpu, freq->policy->cpus) 9079 __kvmclock_cpufreq_notifier(freq, cpu); 9080 9081 return 0; 9082 } 9083 9084 static struct notifier_block kvmclock_cpufreq_notifier_block = { 9085 .notifier_call = kvmclock_cpufreq_notifier 9086 }; 9087 9088 static int kvmclock_cpu_online(unsigned int cpu) 9089 { 9090 tsc_khz_changed(NULL); 9091 return 0; 9092 } 9093 9094 static void kvm_timer_init(void) 9095 { 9096 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) { 9097 max_tsc_khz = tsc_khz; 9098 9099 if (IS_ENABLED(CONFIG_CPU_FREQ)) { 9100 struct cpufreq_policy *policy; 9101 int cpu; 9102 9103 cpu = get_cpu(); 9104 policy = cpufreq_cpu_get(cpu); 9105 if (policy) { 9106 if (policy->cpuinfo.max_freq) 9107 max_tsc_khz = policy->cpuinfo.max_freq; 9108 cpufreq_cpu_put(policy); 9109 } 9110 put_cpu(); 9111 } 9112 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block, 9113 CPUFREQ_TRANSITION_NOTIFIER); 9114 } 9115 9116 cpuhp_setup_state(CPUHP_AP_X86_KVM_CLK_ONLINE, "x86/kvm/clk:online", 9117 kvmclock_cpu_online, kvmclock_cpu_down_prep); 9118 } 9119 9120 #ifdef CONFIG_X86_64 9121 static void pvclock_gtod_update_fn(struct work_struct *work) 9122 { 9123 struct kvm *kvm; 9124 struct kvm_vcpu *vcpu; 9125 unsigned long i; 9126 9127 mutex_lock(&kvm_lock); 9128 list_for_each_entry(kvm, &vm_list, vm_list) 9129 kvm_for_each_vcpu(i, vcpu, kvm) 9130 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu); 9131 atomic_set(&kvm_guest_has_master_clock, 0); 9132 mutex_unlock(&kvm_lock); 9133 } 9134 9135 static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn); 9136 9137 /* 9138 * Indirection to move queue_work() out of the tk_core.seq write held 9139 * region to prevent possible deadlocks against time accessors which 9140 * are invoked with work related locks held. 9141 */ 9142 static void pvclock_irq_work_fn(struct irq_work *w) 9143 { 9144 queue_work(system_long_wq, &pvclock_gtod_work); 9145 } 9146 9147 static DEFINE_IRQ_WORK(pvclock_irq_work, pvclock_irq_work_fn); 9148 9149 /* 9150 * Notification about pvclock gtod data update. 9151 */ 9152 static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused, 9153 void *priv) 9154 { 9155 struct pvclock_gtod_data *gtod = &pvclock_gtod_data; 9156 struct timekeeper *tk = priv; 9157 9158 update_pvclock_gtod(tk); 9159 9160 /* 9161 * Disable master clock if host does not trust, or does not use, 9162 * TSC based clocksource. Delegate queue_work() to irq_work as 9163 * this is invoked with tk_core.seq write held. 9164 */ 9165 if (!gtod_is_based_on_tsc(gtod->clock.vclock_mode) && 9166 atomic_read(&kvm_guest_has_master_clock) != 0) 9167 irq_work_queue(&pvclock_irq_work); 9168 return 0; 9169 } 9170 9171 static struct notifier_block pvclock_gtod_notifier = { 9172 .notifier_call = pvclock_gtod_notify, 9173 }; 9174 #endif 9175 9176 int kvm_arch_init(void *opaque) 9177 { 9178 struct kvm_x86_init_ops *ops = opaque; 9179 u64 host_pat; 9180 int r; 9181 9182 if (kvm_x86_ops.hardware_enable) { 9183 pr_err("kvm: already loaded vendor module '%s'\n", kvm_x86_ops.name); 9184 return -EEXIST; 9185 } 9186 9187 if (!ops->cpu_has_kvm_support()) { 9188 pr_err_ratelimited("kvm: no hardware support for '%s'\n", 9189 ops->runtime_ops->name); 9190 return -EOPNOTSUPP; 9191 } 9192 if (ops->disabled_by_bios()) { 9193 pr_err_ratelimited("kvm: support for '%s' disabled by bios\n", 9194 ops->runtime_ops->name); 9195 return -EOPNOTSUPP; 9196 } 9197 9198 /* 9199 * KVM explicitly assumes that the guest has an FPU and 9200 * FXSAVE/FXRSTOR. For example, the KVM_GET_FPU explicitly casts the 9201 * vCPU's FPU state as a fxregs_state struct. 9202 */ 9203 if (!boot_cpu_has(X86_FEATURE_FPU) || !boot_cpu_has(X86_FEATURE_FXSR)) { 9204 printk(KERN_ERR "kvm: inadequate fpu\n"); 9205 return -EOPNOTSUPP; 9206 } 9207 9208 if (IS_ENABLED(CONFIG_PREEMPT_RT) && !boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) { 9209 pr_err("RT requires X86_FEATURE_CONSTANT_TSC\n"); 9210 return -EOPNOTSUPP; 9211 } 9212 9213 /* 9214 * KVM assumes that PAT entry '0' encodes WB memtype and simply zeroes 9215 * the PAT bits in SPTEs. Bail if PAT[0] is programmed to something 9216 * other than WB. Note, EPT doesn't utilize the PAT, but don't bother 9217 * with an exception. PAT[0] is set to WB on RESET and also by the 9218 * kernel, i.e. failure indicates a kernel bug or broken firmware. 9219 */ 9220 if (rdmsrl_safe(MSR_IA32_CR_PAT, &host_pat) || 9221 (host_pat & GENMASK(2, 0)) != 6) { 9222 pr_err("kvm: host PAT[0] is not WB\n"); 9223 return -EIO; 9224 } 9225 9226 x86_emulator_cache = kvm_alloc_emulator_cache(); 9227 if (!x86_emulator_cache) { 9228 pr_err("kvm: failed to allocate cache for x86 emulator\n"); 9229 return -ENOMEM; 9230 } 9231 9232 user_return_msrs = alloc_percpu(struct kvm_user_return_msrs); 9233 if (!user_return_msrs) { 9234 printk(KERN_ERR "kvm: failed to allocate percpu kvm_user_return_msrs\n"); 9235 r = -ENOMEM; 9236 goto out_free_x86_emulator_cache; 9237 } 9238 kvm_nr_uret_msrs = 0; 9239 9240 r = kvm_mmu_vendor_module_init(); 9241 if (r) 9242 goto out_free_percpu; 9243 9244 kvm_timer_init(); 9245 9246 if (boot_cpu_has(X86_FEATURE_XSAVE)) { 9247 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK); 9248 kvm_caps.supported_xcr0 = host_xcr0 & KVM_SUPPORTED_XCR0; 9249 } 9250 9251 if (pi_inject_timer == -1) 9252 pi_inject_timer = housekeeping_enabled(HK_TYPE_TIMER); 9253 #ifdef CONFIG_X86_64 9254 pvclock_gtod_register_notifier(&pvclock_gtod_notifier); 9255 9256 if (hypervisor_is_type(X86_HYPER_MS_HYPERV)) 9257 set_hv_tscchange_cb(kvm_hyperv_tsc_notifier); 9258 #endif 9259 9260 return 0; 9261 9262 out_free_percpu: 9263 free_percpu(user_return_msrs); 9264 out_free_x86_emulator_cache: 9265 kmem_cache_destroy(x86_emulator_cache); 9266 return r; 9267 } 9268 9269 void kvm_arch_exit(void) 9270 { 9271 #ifdef CONFIG_X86_64 9272 if (hypervisor_is_type(X86_HYPER_MS_HYPERV)) 9273 clear_hv_tscchange_cb(); 9274 #endif 9275 kvm_lapic_exit(); 9276 9277 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) 9278 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block, 9279 CPUFREQ_TRANSITION_NOTIFIER); 9280 cpuhp_remove_state_nocalls(CPUHP_AP_X86_KVM_CLK_ONLINE); 9281 #ifdef CONFIG_X86_64 9282 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier); 9283 irq_work_sync(&pvclock_irq_work); 9284 cancel_work_sync(&pvclock_gtod_work); 9285 #endif 9286 kvm_x86_ops.hardware_enable = NULL; 9287 kvm_mmu_vendor_module_exit(); 9288 free_percpu(user_return_msrs); 9289 kmem_cache_destroy(x86_emulator_cache); 9290 #ifdef CONFIG_KVM_XEN 9291 static_key_deferred_flush(&kvm_xen_enabled); 9292 WARN_ON(static_branch_unlikely(&kvm_xen_enabled.key)); 9293 #endif 9294 } 9295 9296 static int __kvm_emulate_halt(struct kvm_vcpu *vcpu, int state, int reason) 9297 { 9298 /* 9299 * The vCPU has halted, e.g. executed HLT. Update the run state if the 9300 * local APIC is in-kernel, the run loop will detect the non-runnable 9301 * state and halt the vCPU. Exit to userspace if the local APIC is 9302 * managed by userspace, in which case userspace is responsible for 9303 * handling wake events. 9304 */ 9305 ++vcpu->stat.halt_exits; 9306 if (lapic_in_kernel(vcpu)) { 9307 vcpu->arch.mp_state = state; 9308 return 1; 9309 } else { 9310 vcpu->run->exit_reason = reason; 9311 return 0; 9312 } 9313 } 9314 9315 int kvm_emulate_halt_noskip(struct kvm_vcpu *vcpu) 9316 { 9317 return __kvm_emulate_halt(vcpu, KVM_MP_STATE_HALTED, KVM_EXIT_HLT); 9318 } 9319 EXPORT_SYMBOL_GPL(kvm_emulate_halt_noskip); 9320 9321 int kvm_emulate_halt(struct kvm_vcpu *vcpu) 9322 { 9323 int ret = kvm_skip_emulated_instruction(vcpu); 9324 /* 9325 * TODO: we might be squashing a GUESTDBG_SINGLESTEP-triggered 9326 * KVM_EXIT_DEBUG here. 9327 */ 9328 return kvm_emulate_halt_noskip(vcpu) && ret; 9329 } 9330 EXPORT_SYMBOL_GPL(kvm_emulate_halt); 9331 9332 int kvm_emulate_ap_reset_hold(struct kvm_vcpu *vcpu) 9333 { 9334 int ret = kvm_skip_emulated_instruction(vcpu); 9335 9336 return __kvm_emulate_halt(vcpu, KVM_MP_STATE_AP_RESET_HOLD, 9337 KVM_EXIT_AP_RESET_HOLD) && ret; 9338 } 9339 EXPORT_SYMBOL_GPL(kvm_emulate_ap_reset_hold); 9340 9341 #ifdef CONFIG_X86_64 9342 static int kvm_pv_clock_pairing(struct kvm_vcpu *vcpu, gpa_t paddr, 9343 unsigned long clock_type) 9344 { 9345 struct kvm_clock_pairing clock_pairing; 9346 struct timespec64 ts; 9347 u64 cycle; 9348 int ret; 9349 9350 if (clock_type != KVM_CLOCK_PAIRING_WALLCLOCK) 9351 return -KVM_EOPNOTSUPP; 9352 9353 /* 9354 * When tsc is in permanent catchup mode guests won't be able to use 9355 * pvclock_read_retry loop to get consistent view of pvclock 9356 */ 9357 if (vcpu->arch.tsc_always_catchup) 9358 return -KVM_EOPNOTSUPP; 9359 9360 if (!kvm_get_walltime_and_clockread(&ts, &cycle)) 9361 return -KVM_EOPNOTSUPP; 9362 9363 clock_pairing.sec = ts.tv_sec; 9364 clock_pairing.nsec = ts.tv_nsec; 9365 clock_pairing.tsc = kvm_read_l1_tsc(vcpu, cycle); 9366 clock_pairing.flags = 0; 9367 memset(&clock_pairing.pad, 0, sizeof(clock_pairing.pad)); 9368 9369 ret = 0; 9370 if (kvm_write_guest(vcpu->kvm, paddr, &clock_pairing, 9371 sizeof(struct kvm_clock_pairing))) 9372 ret = -KVM_EFAULT; 9373 9374 return ret; 9375 } 9376 #endif 9377 9378 /* 9379 * kvm_pv_kick_cpu_op: Kick a vcpu. 9380 * 9381 * @apicid - apicid of vcpu to be kicked. 9382 */ 9383 static void kvm_pv_kick_cpu_op(struct kvm *kvm, int apicid) 9384 { 9385 /* 9386 * All other fields are unused for APIC_DM_REMRD, but may be consumed by 9387 * common code, e.g. for tracing. Defer initialization to the compiler. 9388 */ 9389 struct kvm_lapic_irq lapic_irq = { 9390 .delivery_mode = APIC_DM_REMRD, 9391 .dest_mode = APIC_DEST_PHYSICAL, 9392 .shorthand = APIC_DEST_NOSHORT, 9393 .dest_id = apicid, 9394 }; 9395 9396 kvm_irq_delivery_to_apic(kvm, NULL, &lapic_irq, NULL); 9397 } 9398 9399 bool kvm_apicv_activated(struct kvm *kvm) 9400 { 9401 return (READ_ONCE(kvm->arch.apicv_inhibit_reasons) == 0); 9402 } 9403 EXPORT_SYMBOL_GPL(kvm_apicv_activated); 9404 9405 bool kvm_vcpu_apicv_activated(struct kvm_vcpu *vcpu) 9406 { 9407 ulong vm_reasons = READ_ONCE(vcpu->kvm->arch.apicv_inhibit_reasons); 9408 ulong vcpu_reasons = static_call(kvm_x86_vcpu_get_apicv_inhibit_reasons)(vcpu); 9409 9410 return (vm_reasons | vcpu_reasons) == 0; 9411 } 9412 EXPORT_SYMBOL_GPL(kvm_vcpu_apicv_activated); 9413 9414 static void set_or_clear_apicv_inhibit(unsigned long *inhibits, 9415 enum kvm_apicv_inhibit reason, bool set) 9416 { 9417 if (set) 9418 __set_bit(reason, inhibits); 9419 else 9420 __clear_bit(reason, inhibits); 9421 9422 trace_kvm_apicv_inhibit_changed(reason, set, *inhibits); 9423 } 9424 9425 static void kvm_apicv_init(struct kvm *kvm) 9426 { 9427 unsigned long *inhibits = &kvm->arch.apicv_inhibit_reasons; 9428 9429 init_rwsem(&kvm->arch.apicv_update_lock); 9430 9431 set_or_clear_apicv_inhibit(inhibits, APICV_INHIBIT_REASON_ABSENT, true); 9432 9433 if (!enable_apicv) 9434 set_or_clear_apicv_inhibit(inhibits, 9435 APICV_INHIBIT_REASON_DISABLE, true); 9436 } 9437 9438 static void kvm_sched_yield(struct kvm_vcpu *vcpu, unsigned long dest_id) 9439 { 9440 struct kvm_vcpu *target = NULL; 9441 struct kvm_apic_map *map; 9442 9443 vcpu->stat.directed_yield_attempted++; 9444 9445 if (single_task_running()) 9446 goto no_yield; 9447 9448 rcu_read_lock(); 9449 map = rcu_dereference(vcpu->kvm->arch.apic_map); 9450 9451 if (likely(map) && dest_id <= map->max_apic_id && map->phys_map[dest_id]) 9452 target = map->phys_map[dest_id]->vcpu; 9453 9454 rcu_read_unlock(); 9455 9456 if (!target || !READ_ONCE(target->ready)) 9457 goto no_yield; 9458 9459 /* Ignore requests to yield to self */ 9460 if (vcpu == target) 9461 goto no_yield; 9462 9463 if (kvm_vcpu_yield_to(target) <= 0) 9464 goto no_yield; 9465 9466 vcpu->stat.directed_yield_successful++; 9467 9468 no_yield: 9469 return; 9470 } 9471 9472 static int complete_hypercall_exit(struct kvm_vcpu *vcpu) 9473 { 9474 u64 ret = vcpu->run->hypercall.ret; 9475 9476 if (!is_64_bit_mode(vcpu)) 9477 ret = (u32)ret; 9478 kvm_rax_write(vcpu, ret); 9479 ++vcpu->stat.hypercalls; 9480 return kvm_skip_emulated_instruction(vcpu); 9481 } 9482 9483 int kvm_emulate_hypercall(struct kvm_vcpu *vcpu) 9484 { 9485 unsigned long nr, a0, a1, a2, a3, ret; 9486 int op_64_bit; 9487 9488 if (kvm_xen_hypercall_enabled(vcpu->kvm)) 9489 return kvm_xen_hypercall(vcpu); 9490 9491 if (kvm_hv_hypercall_enabled(vcpu)) 9492 return kvm_hv_hypercall(vcpu); 9493 9494 nr = kvm_rax_read(vcpu); 9495 a0 = kvm_rbx_read(vcpu); 9496 a1 = kvm_rcx_read(vcpu); 9497 a2 = kvm_rdx_read(vcpu); 9498 a3 = kvm_rsi_read(vcpu); 9499 9500 trace_kvm_hypercall(nr, a0, a1, a2, a3); 9501 9502 op_64_bit = is_64_bit_hypercall(vcpu); 9503 if (!op_64_bit) { 9504 nr &= 0xFFFFFFFF; 9505 a0 &= 0xFFFFFFFF; 9506 a1 &= 0xFFFFFFFF; 9507 a2 &= 0xFFFFFFFF; 9508 a3 &= 0xFFFFFFFF; 9509 } 9510 9511 if (static_call(kvm_x86_get_cpl)(vcpu) != 0) { 9512 ret = -KVM_EPERM; 9513 goto out; 9514 } 9515 9516 ret = -KVM_ENOSYS; 9517 9518 switch (nr) { 9519 case KVM_HC_VAPIC_POLL_IRQ: 9520 ret = 0; 9521 break; 9522 case KVM_HC_KICK_CPU: 9523 if (!guest_pv_has(vcpu, KVM_FEATURE_PV_UNHALT)) 9524 break; 9525 9526 kvm_pv_kick_cpu_op(vcpu->kvm, a1); 9527 kvm_sched_yield(vcpu, a1); 9528 ret = 0; 9529 break; 9530 #ifdef CONFIG_X86_64 9531 case KVM_HC_CLOCK_PAIRING: 9532 ret = kvm_pv_clock_pairing(vcpu, a0, a1); 9533 break; 9534 #endif 9535 case KVM_HC_SEND_IPI: 9536 if (!guest_pv_has(vcpu, KVM_FEATURE_PV_SEND_IPI)) 9537 break; 9538 9539 ret = kvm_pv_send_ipi(vcpu->kvm, a0, a1, a2, a3, op_64_bit); 9540 break; 9541 case KVM_HC_SCHED_YIELD: 9542 if (!guest_pv_has(vcpu, KVM_FEATURE_PV_SCHED_YIELD)) 9543 break; 9544 9545 kvm_sched_yield(vcpu, a0); 9546 ret = 0; 9547 break; 9548 case KVM_HC_MAP_GPA_RANGE: { 9549 u64 gpa = a0, npages = a1, attrs = a2; 9550 9551 ret = -KVM_ENOSYS; 9552 if (!(vcpu->kvm->arch.hypercall_exit_enabled & (1 << KVM_HC_MAP_GPA_RANGE))) 9553 break; 9554 9555 if (!PAGE_ALIGNED(gpa) || !npages || 9556 gpa_to_gfn(gpa) + npages <= gpa_to_gfn(gpa)) { 9557 ret = -KVM_EINVAL; 9558 break; 9559 } 9560 9561 vcpu->run->exit_reason = KVM_EXIT_HYPERCALL; 9562 vcpu->run->hypercall.nr = KVM_HC_MAP_GPA_RANGE; 9563 vcpu->run->hypercall.args[0] = gpa; 9564 vcpu->run->hypercall.args[1] = npages; 9565 vcpu->run->hypercall.args[2] = attrs; 9566 vcpu->run->hypercall.longmode = op_64_bit; 9567 vcpu->arch.complete_userspace_io = complete_hypercall_exit; 9568 return 0; 9569 } 9570 default: 9571 ret = -KVM_ENOSYS; 9572 break; 9573 } 9574 out: 9575 if (!op_64_bit) 9576 ret = (u32)ret; 9577 kvm_rax_write(vcpu, ret); 9578 9579 ++vcpu->stat.hypercalls; 9580 return kvm_skip_emulated_instruction(vcpu); 9581 } 9582 EXPORT_SYMBOL_GPL(kvm_emulate_hypercall); 9583 9584 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt) 9585 { 9586 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 9587 char instruction[3]; 9588 unsigned long rip = kvm_rip_read(vcpu); 9589 9590 /* 9591 * If the quirk is disabled, synthesize a #UD and let the guest pick up 9592 * the pieces. 9593 */ 9594 if (!kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_FIX_HYPERCALL_INSN)) { 9595 ctxt->exception.error_code_valid = false; 9596 ctxt->exception.vector = UD_VECTOR; 9597 ctxt->have_exception = true; 9598 return X86EMUL_PROPAGATE_FAULT; 9599 } 9600 9601 static_call(kvm_x86_patch_hypercall)(vcpu, instruction); 9602 9603 return emulator_write_emulated(ctxt, rip, instruction, 3, 9604 &ctxt->exception); 9605 } 9606 9607 static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu) 9608 { 9609 return vcpu->run->request_interrupt_window && 9610 likely(!pic_in_kernel(vcpu->kvm)); 9611 } 9612 9613 /* Called within kvm->srcu read side. */ 9614 static void post_kvm_run_save(struct kvm_vcpu *vcpu) 9615 { 9616 struct kvm_run *kvm_run = vcpu->run; 9617 9618 kvm_run->if_flag = static_call(kvm_x86_get_if_flag)(vcpu); 9619 kvm_run->cr8 = kvm_get_cr8(vcpu); 9620 kvm_run->apic_base = kvm_get_apic_base(vcpu); 9621 9622 kvm_run->ready_for_interrupt_injection = 9623 pic_in_kernel(vcpu->kvm) || 9624 kvm_vcpu_ready_for_interrupt_injection(vcpu); 9625 9626 if (is_smm(vcpu)) 9627 kvm_run->flags |= KVM_RUN_X86_SMM; 9628 } 9629 9630 static void update_cr8_intercept(struct kvm_vcpu *vcpu) 9631 { 9632 int max_irr, tpr; 9633 9634 if (!kvm_x86_ops.update_cr8_intercept) 9635 return; 9636 9637 if (!lapic_in_kernel(vcpu)) 9638 return; 9639 9640 if (vcpu->arch.apic->apicv_active) 9641 return; 9642 9643 if (!vcpu->arch.apic->vapic_addr) 9644 max_irr = kvm_lapic_find_highest_irr(vcpu); 9645 else 9646 max_irr = -1; 9647 9648 if (max_irr != -1) 9649 max_irr >>= 4; 9650 9651 tpr = kvm_lapic_get_cr8(vcpu); 9652 9653 static_call(kvm_x86_update_cr8_intercept)(vcpu, tpr, max_irr); 9654 } 9655 9656 9657 int kvm_check_nested_events(struct kvm_vcpu *vcpu) 9658 { 9659 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) { 9660 kvm_x86_ops.nested_ops->triple_fault(vcpu); 9661 return 1; 9662 } 9663 9664 return kvm_x86_ops.nested_ops->check_events(vcpu); 9665 } 9666 9667 static void kvm_inject_exception(struct kvm_vcpu *vcpu) 9668 { 9669 trace_kvm_inj_exception(vcpu->arch.exception.nr, 9670 vcpu->arch.exception.has_error_code, 9671 vcpu->arch.exception.error_code, 9672 vcpu->arch.exception.injected); 9673 9674 if (vcpu->arch.exception.error_code && !is_protmode(vcpu)) 9675 vcpu->arch.exception.error_code = false; 9676 static_call(kvm_x86_queue_exception)(vcpu); 9677 } 9678 9679 static int inject_pending_event(struct kvm_vcpu *vcpu, bool *req_immediate_exit) 9680 { 9681 int r; 9682 bool can_inject = true; 9683 9684 /* try to reinject previous events if any */ 9685 9686 if (vcpu->arch.exception.injected) { 9687 kvm_inject_exception(vcpu); 9688 can_inject = false; 9689 } 9690 /* 9691 * Do not inject an NMI or interrupt if there is a pending 9692 * exception. Exceptions and interrupts are recognized at 9693 * instruction boundaries, i.e. the start of an instruction. 9694 * Trap-like exceptions, e.g. #DB, have higher priority than 9695 * NMIs and interrupts, i.e. traps are recognized before an 9696 * NMI/interrupt that's pending on the same instruction. 9697 * Fault-like exceptions, e.g. #GP and #PF, are the lowest 9698 * priority, but are only generated (pended) during instruction 9699 * execution, i.e. a pending fault-like exception means the 9700 * fault occurred on the *previous* instruction and must be 9701 * serviced prior to recognizing any new events in order to 9702 * fully complete the previous instruction. 9703 */ 9704 else if (!vcpu->arch.exception.pending) { 9705 if (vcpu->arch.nmi_injected) { 9706 static_call(kvm_x86_inject_nmi)(vcpu); 9707 can_inject = false; 9708 } else if (vcpu->arch.interrupt.injected) { 9709 static_call(kvm_x86_inject_irq)(vcpu, true); 9710 can_inject = false; 9711 } 9712 } 9713 9714 WARN_ON_ONCE(vcpu->arch.exception.injected && 9715 vcpu->arch.exception.pending); 9716 9717 /* 9718 * Call check_nested_events() even if we reinjected a previous event 9719 * in order for caller to determine if it should require immediate-exit 9720 * from L2 to L1 due to pending L1 events which require exit 9721 * from L2 to L1. 9722 */ 9723 if (is_guest_mode(vcpu)) { 9724 r = kvm_check_nested_events(vcpu); 9725 if (r < 0) 9726 goto out; 9727 } 9728 9729 /* try to inject new event if pending */ 9730 if (vcpu->arch.exception.pending) { 9731 if (exception_type(vcpu->arch.exception.nr) == EXCPT_FAULT) 9732 __kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) | 9733 X86_EFLAGS_RF); 9734 9735 if (vcpu->arch.exception.nr == DB_VECTOR) { 9736 kvm_deliver_exception_payload(vcpu); 9737 if (vcpu->arch.dr7 & DR7_GD) { 9738 vcpu->arch.dr7 &= ~DR7_GD; 9739 kvm_update_dr7(vcpu); 9740 } 9741 } 9742 9743 kvm_inject_exception(vcpu); 9744 9745 vcpu->arch.exception.pending = false; 9746 vcpu->arch.exception.injected = true; 9747 9748 can_inject = false; 9749 } 9750 9751 /* Don't inject interrupts if the user asked to avoid doing so */ 9752 if (vcpu->guest_debug & KVM_GUESTDBG_BLOCKIRQ) 9753 return 0; 9754 9755 /* 9756 * Finally, inject interrupt events. If an event cannot be injected 9757 * due to architectural conditions (e.g. IF=0) a window-open exit 9758 * will re-request KVM_REQ_EVENT. Sometimes however an event is pending 9759 * and can architecturally be injected, but we cannot do it right now: 9760 * an interrupt could have arrived just now and we have to inject it 9761 * as a vmexit, or there could already an event in the queue, which is 9762 * indicated by can_inject. In that case we request an immediate exit 9763 * in order to make progress and get back here for another iteration. 9764 * The kvm_x86_ops hooks communicate this by returning -EBUSY. 9765 */ 9766 if (vcpu->arch.smi_pending) { 9767 r = can_inject ? static_call(kvm_x86_smi_allowed)(vcpu, true) : -EBUSY; 9768 if (r < 0) 9769 goto out; 9770 if (r) { 9771 vcpu->arch.smi_pending = false; 9772 ++vcpu->arch.smi_count; 9773 enter_smm(vcpu); 9774 can_inject = false; 9775 } else 9776 static_call(kvm_x86_enable_smi_window)(vcpu); 9777 } 9778 9779 if (vcpu->arch.nmi_pending) { 9780 r = can_inject ? static_call(kvm_x86_nmi_allowed)(vcpu, true) : -EBUSY; 9781 if (r < 0) 9782 goto out; 9783 if (r) { 9784 --vcpu->arch.nmi_pending; 9785 vcpu->arch.nmi_injected = true; 9786 static_call(kvm_x86_inject_nmi)(vcpu); 9787 can_inject = false; 9788 WARN_ON(static_call(kvm_x86_nmi_allowed)(vcpu, true) < 0); 9789 } 9790 if (vcpu->arch.nmi_pending) 9791 static_call(kvm_x86_enable_nmi_window)(vcpu); 9792 } 9793 9794 if (kvm_cpu_has_injectable_intr(vcpu)) { 9795 r = can_inject ? static_call(kvm_x86_interrupt_allowed)(vcpu, true) : -EBUSY; 9796 if (r < 0) 9797 goto out; 9798 if (r) { 9799 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu), false); 9800 static_call(kvm_x86_inject_irq)(vcpu, false); 9801 WARN_ON(static_call(kvm_x86_interrupt_allowed)(vcpu, true) < 0); 9802 } 9803 if (kvm_cpu_has_injectable_intr(vcpu)) 9804 static_call(kvm_x86_enable_irq_window)(vcpu); 9805 } 9806 9807 if (is_guest_mode(vcpu) && 9808 kvm_x86_ops.nested_ops->hv_timer_pending && 9809 kvm_x86_ops.nested_ops->hv_timer_pending(vcpu)) 9810 *req_immediate_exit = true; 9811 9812 WARN_ON(vcpu->arch.exception.pending); 9813 return 0; 9814 9815 out: 9816 if (r == -EBUSY) { 9817 *req_immediate_exit = true; 9818 r = 0; 9819 } 9820 return r; 9821 } 9822 9823 static void process_nmi(struct kvm_vcpu *vcpu) 9824 { 9825 unsigned limit = 2; 9826 9827 /* 9828 * x86 is limited to one NMI running, and one NMI pending after it. 9829 * If an NMI is already in progress, limit further NMIs to just one. 9830 * Otherwise, allow two (and we'll inject the first one immediately). 9831 */ 9832 if (static_call(kvm_x86_get_nmi_mask)(vcpu) || vcpu->arch.nmi_injected) 9833 limit = 1; 9834 9835 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0); 9836 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit); 9837 kvm_make_request(KVM_REQ_EVENT, vcpu); 9838 } 9839 9840 static u32 enter_smm_get_segment_flags(struct kvm_segment *seg) 9841 { 9842 u32 flags = 0; 9843 flags |= seg->g << 23; 9844 flags |= seg->db << 22; 9845 flags |= seg->l << 21; 9846 flags |= seg->avl << 20; 9847 flags |= seg->present << 15; 9848 flags |= seg->dpl << 13; 9849 flags |= seg->s << 12; 9850 flags |= seg->type << 8; 9851 return flags; 9852 } 9853 9854 static void enter_smm_save_seg_32(struct kvm_vcpu *vcpu, char *buf, int n) 9855 { 9856 struct kvm_segment seg; 9857 int offset; 9858 9859 kvm_get_segment(vcpu, &seg, n); 9860 put_smstate(u32, buf, 0x7fa8 + n * 4, seg.selector); 9861 9862 if (n < 3) 9863 offset = 0x7f84 + n * 12; 9864 else 9865 offset = 0x7f2c + (n - 3) * 12; 9866 9867 put_smstate(u32, buf, offset + 8, seg.base); 9868 put_smstate(u32, buf, offset + 4, seg.limit); 9869 put_smstate(u32, buf, offset, enter_smm_get_segment_flags(&seg)); 9870 } 9871 9872 #ifdef CONFIG_X86_64 9873 static void enter_smm_save_seg_64(struct kvm_vcpu *vcpu, char *buf, int n) 9874 { 9875 struct kvm_segment seg; 9876 int offset; 9877 u16 flags; 9878 9879 kvm_get_segment(vcpu, &seg, n); 9880 offset = 0x7e00 + n * 16; 9881 9882 flags = enter_smm_get_segment_flags(&seg) >> 8; 9883 put_smstate(u16, buf, offset, seg.selector); 9884 put_smstate(u16, buf, offset + 2, flags); 9885 put_smstate(u32, buf, offset + 4, seg.limit); 9886 put_smstate(u64, buf, offset + 8, seg.base); 9887 } 9888 #endif 9889 9890 static void enter_smm_save_state_32(struct kvm_vcpu *vcpu, char *buf) 9891 { 9892 struct desc_ptr dt; 9893 struct kvm_segment seg; 9894 unsigned long val; 9895 int i; 9896 9897 put_smstate(u32, buf, 0x7ffc, kvm_read_cr0(vcpu)); 9898 put_smstate(u32, buf, 0x7ff8, kvm_read_cr3(vcpu)); 9899 put_smstate(u32, buf, 0x7ff4, kvm_get_rflags(vcpu)); 9900 put_smstate(u32, buf, 0x7ff0, kvm_rip_read(vcpu)); 9901 9902 for (i = 0; i < 8; i++) 9903 put_smstate(u32, buf, 0x7fd0 + i * 4, kvm_register_read_raw(vcpu, i)); 9904 9905 kvm_get_dr(vcpu, 6, &val); 9906 put_smstate(u32, buf, 0x7fcc, (u32)val); 9907 kvm_get_dr(vcpu, 7, &val); 9908 put_smstate(u32, buf, 0x7fc8, (u32)val); 9909 9910 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR); 9911 put_smstate(u32, buf, 0x7fc4, seg.selector); 9912 put_smstate(u32, buf, 0x7f64, seg.base); 9913 put_smstate(u32, buf, 0x7f60, seg.limit); 9914 put_smstate(u32, buf, 0x7f5c, enter_smm_get_segment_flags(&seg)); 9915 9916 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR); 9917 put_smstate(u32, buf, 0x7fc0, seg.selector); 9918 put_smstate(u32, buf, 0x7f80, seg.base); 9919 put_smstate(u32, buf, 0x7f7c, seg.limit); 9920 put_smstate(u32, buf, 0x7f78, enter_smm_get_segment_flags(&seg)); 9921 9922 static_call(kvm_x86_get_gdt)(vcpu, &dt); 9923 put_smstate(u32, buf, 0x7f74, dt.address); 9924 put_smstate(u32, buf, 0x7f70, dt.size); 9925 9926 static_call(kvm_x86_get_idt)(vcpu, &dt); 9927 put_smstate(u32, buf, 0x7f58, dt.address); 9928 put_smstate(u32, buf, 0x7f54, dt.size); 9929 9930 for (i = 0; i < 6; i++) 9931 enter_smm_save_seg_32(vcpu, buf, i); 9932 9933 put_smstate(u32, buf, 0x7f14, kvm_read_cr4(vcpu)); 9934 9935 /* revision id */ 9936 put_smstate(u32, buf, 0x7efc, 0x00020000); 9937 put_smstate(u32, buf, 0x7ef8, vcpu->arch.smbase); 9938 } 9939 9940 #ifdef CONFIG_X86_64 9941 static void enter_smm_save_state_64(struct kvm_vcpu *vcpu, char *buf) 9942 { 9943 struct desc_ptr dt; 9944 struct kvm_segment seg; 9945 unsigned long val; 9946 int i; 9947 9948 for (i = 0; i < 16; i++) 9949 put_smstate(u64, buf, 0x7ff8 - i * 8, kvm_register_read_raw(vcpu, i)); 9950 9951 put_smstate(u64, buf, 0x7f78, kvm_rip_read(vcpu)); 9952 put_smstate(u32, buf, 0x7f70, kvm_get_rflags(vcpu)); 9953 9954 kvm_get_dr(vcpu, 6, &val); 9955 put_smstate(u64, buf, 0x7f68, val); 9956 kvm_get_dr(vcpu, 7, &val); 9957 put_smstate(u64, buf, 0x7f60, val); 9958 9959 put_smstate(u64, buf, 0x7f58, kvm_read_cr0(vcpu)); 9960 put_smstate(u64, buf, 0x7f50, kvm_read_cr3(vcpu)); 9961 put_smstate(u64, buf, 0x7f48, kvm_read_cr4(vcpu)); 9962 9963 put_smstate(u32, buf, 0x7f00, vcpu->arch.smbase); 9964 9965 /* revision id */ 9966 put_smstate(u32, buf, 0x7efc, 0x00020064); 9967 9968 put_smstate(u64, buf, 0x7ed0, vcpu->arch.efer); 9969 9970 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR); 9971 put_smstate(u16, buf, 0x7e90, seg.selector); 9972 put_smstate(u16, buf, 0x7e92, enter_smm_get_segment_flags(&seg) >> 8); 9973 put_smstate(u32, buf, 0x7e94, seg.limit); 9974 put_smstate(u64, buf, 0x7e98, seg.base); 9975 9976 static_call(kvm_x86_get_idt)(vcpu, &dt); 9977 put_smstate(u32, buf, 0x7e84, dt.size); 9978 put_smstate(u64, buf, 0x7e88, dt.address); 9979 9980 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR); 9981 put_smstate(u16, buf, 0x7e70, seg.selector); 9982 put_smstate(u16, buf, 0x7e72, enter_smm_get_segment_flags(&seg) >> 8); 9983 put_smstate(u32, buf, 0x7e74, seg.limit); 9984 put_smstate(u64, buf, 0x7e78, seg.base); 9985 9986 static_call(kvm_x86_get_gdt)(vcpu, &dt); 9987 put_smstate(u32, buf, 0x7e64, dt.size); 9988 put_smstate(u64, buf, 0x7e68, dt.address); 9989 9990 for (i = 0; i < 6; i++) 9991 enter_smm_save_seg_64(vcpu, buf, i); 9992 } 9993 #endif 9994 9995 static void enter_smm(struct kvm_vcpu *vcpu) 9996 { 9997 struct kvm_segment cs, ds; 9998 struct desc_ptr dt; 9999 unsigned long cr0; 10000 char buf[512]; 10001 10002 memset(buf, 0, 512); 10003 #ifdef CONFIG_X86_64 10004 if (guest_cpuid_has(vcpu, X86_FEATURE_LM)) 10005 enter_smm_save_state_64(vcpu, buf); 10006 else 10007 #endif 10008 enter_smm_save_state_32(vcpu, buf); 10009 10010 /* 10011 * Give enter_smm() a chance to make ISA-specific changes to the vCPU 10012 * state (e.g. leave guest mode) after we've saved the state into the 10013 * SMM state-save area. 10014 */ 10015 static_call(kvm_x86_enter_smm)(vcpu, buf); 10016 10017 kvm_smm_changed(vcpu, true); 10018 kvm_vcpu_write_guest(vcpu, vcpu->arch.smbase + 0xfe00, buf, sizeof(buf)); 10019 10020 if (static_call(kvm_x86_get_nmi_mask)(vcpu)) 10021 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK; 10022 else 10023 static_call(kvm_x86_set_nmi_mask)(vcpu, true); 10024 10025 kvm_set_rflags(vcpu, X86_EFLAGS_FIXED); 10026 kvm_rip_write(vcpu, 0x8000); 10027 10028 cr0 = vcpu->arch.cr0 & ~(X86_CR0_PE | X86_CR0_EM | X86_CR0_TS | X86_CR0_PG); 10029 static_call(kvm_x86_set_cr0)(vcpu, cr0); 10030 vcpu->arch.cr0 = cr0; 10031 10032 static_call(kvm_x86_set_cr4)(vcpu, 0); 10033 10034 /* Undocumented: IDT limit is set to zero on entry to SMM. */ 10035 dt.address = dt.size = 0; 10036 static_call(kvm_x86_set_idt)(vcpu, &dt); 10037 10038 kvm_set_dr(vcpu, 7, DR7_FIXED_1); 10039 10040 cs.selector = (vcpu->arch.smbase >> 4) & 0xffff; 10041 cs.base = vcpu->arch.smbase; 10042 10043 ds.selector = 0; 10044 ds.base = 0; 10045 10046 cs.limit = ds.limit = 0xffffffff; 10047 cs.type = ds.type = 0x3; 10048 cs.dpl = ds.dpl = 0; 10049 cs.db = ds.db = 0; 10050 cs.s = ds.s = 1; 10051 cs.l = ds.l = 0; 10052 cs.g = ds.g = 1; 10053 cs.avl = ds.avl = 0; 10054 cs.present = ds.present = 1; 10055 cs.unusable = ds.unusable = 0; 10056 cs.padding = ds.padding = 0; 10057 10058 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS); 10059 kvm_set_segment(vcpu, &ds, VCPU_SREG_DS); 10060 kvm_set_segment(vcpu, &ds, VCPU_SREG_ES); 10061 kvm_set_segment(vcpu, &ds, VCPU_SREG_FS); 10062 kvm_set_segment(vcpu, &ds, VCPU_SREG_GS); 10063 kvm_set_segment(vcpu, &ds, VCPU_SREG_SS); 10064 10065 #ifdef CONFIG_X86_64 10066 if (guest_cpuid_has(vcpu, X86_FEATURE_LM)) 10067 static_call(kvm_x86_set_efer)(vcpu, 0); 10068 #endif 10069 10070 kvm_update_cpuid_runtime(vcpu); 10071 kvm_mmu_reset_context(vcpu); 10072 } 10073 10074 static void process_smi(struct kvm_vcpu *vcpu) 10075 { 10076 vcpu->arch.smi_pending = true; 10077 kvm_make_request(KVM_REQ_EVENT, vcpu); 10078 } 10079 10080 void kvm_make_scan_ioapic_request_mask(struct kvm *kvm, 10081 unsigned long *vcpu_bitmap) 10082 { 10083 kvm_make_vcpus_request_mask(kvm, KVM_REQ_SCAN_IOAPIC, vcpu_bitmap); 10084 } 10085 10086 void kvm_make_scan_ioapic_request(struct kvm *kvm) 10087 { 10088 kvm_make_all_cpus_request(kvm, KVM_REQ_SCAN_IOAPIC); 10089 } 10090 10091 void kvm_vcpu_update_apicv(struct kvm_vcpu *vcpu) 10092 { 10093 struct kvm_lapic *apic = vcpu->arch.apic; 10094 bool activate; 10095 10096 if (!lapic_in_kernel(vcpu)) 10097 return; 10098 10099 down_read(&vcpu->kvm->arch.apicv_update_lock); 10100 preempt_disable(); 10101 10102 /* Do not activate APICV when APIC is disabled */ 10103 activate = kvm_vcpu_apicv_activated(vcpu) && 10104 (kvm_get_apic_mode(vcpu) != LAPIC_MODE_DISABLED); 10105 10106 if (apic->apicv_active == activate) 10107 goto out; 10108 10109 apic->apicv_active = activate; 10110 kvm_apic_update_apicv(vcpu); 10111 static_call(kvm_x86_refresh_apicv_exec_ctrl)(vcpu); 10112 10113 /* 10114 * When APICv gets disabled, we may still have injected interrupts 10115 * pending. At the same time, KVM_REQ_EVENT may not be set as APICv was 10116 * still active when the interrupt got accepted. Make sure 10117 * inject_pending_event() is called to check for that. 10118 */ 10119 if (!apic->apicv_active) 10120 kvm_make_request(KVM_REQ_EVENT, vcpu); 10121 10122 out: 10123 preempt_enable(); 10124 up_read(&vcpu->kvm->arch.apicv_update_lock); 10125 } 10126 EXPORT_SYMBOL_GPL(kvm_vcpu_update_apicv); 10127 10128 void __kvm_set_or_clear_apicv_inhibit(struct kvm *kvm, 10129 enum kvm_apicv_inhibit reason, bool set) 10130 { 10131 unsigned long old, new; 10132 10133 lockdep_assert_held_write(&kvm->arch.apicv_update_lock); 10134 10135 if (!static_call(kvm_x86_check_apicv_inhibit_reasons)(reason)) 10136 return; 10137 10138 old = new = kvm->arch.apicv_inhibit_reasons; 10139 10140 set_or_clear_apicv_inhibit(&new, reason, set); 10141 10142 if (!!old != !!new) { 10143 /* 10144 * Kick all vCPUs before setting apicv_inhibit_reasons to avoid 10145 * false positives in the sanity check WARN in svm_vcpu_run(). 10146 * This task will wait for all vCPUs to ack the kick IRQ before 10147 * updating apicv_inhibit_reasons, and all other vCPUs will 10148 * block on acquiring apicv_update_lock so that vCPUs can't 10149 * redo svm_vcpu_run() without seeing the new inhibit state. 10150 * 10151 * Note, holding apicv_update_lock and taking it in the read 10152 * side (handling the request) also prevents other vCPUs from 10153 * servicing the request with a stale apicv_inhibit_reasons. 10154 */ 10155 kvm_make_all_cpus_request(kvm, KVM_REQ_APICV_UPDATE); 10156 kvm->arch.apicv_inhibit_reasons = new; 10157 if (new) { 10158 unsigned long gfn = gpa_to_gfn(APIC_DEFAULT_PHYS_BASE); 10159 kvm_zap_gfn_range(kvm, gfn, gfn+1); 10160 } 10161 } else { 10162 kvm->arch.apicv_inhibit_reasons = new; 10163 } 10164 } 10165 10166 void kvm_set_or_clear_apicv_inhibit(struct kvm *kvm, 10167 enum kvm_apicv_inhibit reason, bool set) 10168 { 10169 if (!enable_apicv) 10170 return; 10171 10172 down_write(&kvm->arch.apicv_update_lock); 10173 __kvm_set_or_clear_apicv_inhibit(kvm, reason, set); 10174 up_write(&kvm->arch.apicv_update_lock); 10175 } 10176 EXPORT_SYMBOL_GPL(kvm_set_or_clear_apicv_inhibit); 10177 10178 static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu) 10179 { 10180 if (!kvm_apic_present(vcpu)) 10181 return; 10182 10183 bitmap_zero(vcpu->arch.ioapic_handled_vectors, 256); 10184 10185 if (irqchip_split(vcpu->kvm)) 10186 kvm_scan_ioapic_routes(vcpu, vcpu->arch.ioapic_handled_vectors); 10187 else { 10188 static_call_cond(kvm_x86_sync_pir_to_irr)(vcpu); 10189 if (ioapic_in_kernel(vcpu->kvm)) 10190 kvm_ioapic_scan_entry(vcpu, vcpu->arch.ioapic_handled_vectors); 10191 } 10192 10193 if (is_guest_mode(vcpu)) 10194 vcpu->arch.load_eoi_exitmap_pending = true; 10195 else 10196 kvm_make_request(KVM_REQ_LOAD_EOI_EXITMAP, vcpu); 10197 } 10198 10199 static void vcpu_load_eoi_exitmap(struct kvm_vcpu *vcpu) 10200 { 10201 u64 eoi_exit_bitmap[4]; 10202 10203 if (!kvm_apic_hw_enabled(vcpu->arch.apic)) 10204 return; 10205 10206 if (to_hv_vcpu(vcpu)) { 10207 bitmap_or((ulong *)eoi_exit_bitmap, 10208 vcpu->arch.ioapic_handled_vectors, 10209 to_hv_synic(vcpu)->vec_bitmap, 256); 10210 static_call_cond(kvm_x86_load_eoi_exitmap)(vcpu, eoi_exit_bitmap); 10211 return; 10212 } 10213 10214 static_call_cond(kvm_x86_load_eoi_exitmap)( 10215 vcpu, (u64 *)vcpu->arch.ioapic_handled_vectors); 10216 } 10217 10218 void kvm_arch_mmu_notifier_invalidate_range(struct kvm *kvm, 10219 unsigned long start, unsigned long end) 10220 { 10221 unsigned long apic_address; 10222 10223 /* 10224 * The physical address of apic access page is stored in the VMCS. 10225 * Update it when it becomes invalid. 10226 */ 10227 apic_address = gfn_to_hva(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT); 10228 if (start <= apic_address && apic_address < end) 10229 kvm_make_all_cpus_request(kvm, KVM_REQ_APIC_PAGE_RELOAD); 10230 } 10231 10232 void kvm_arch_guest_memory_reclaimed(struct kvm *kvm) 10233 { 10234 static_call_cond(kvm_x86_guest_memory_reclaimed)(kvm); 10235 } 10236 10237 static void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu) 10238 { 10239 if (!lapic_in_kernel(vcpu)) 10240 return; 10241 10242 static_call_cond(kvm_x86_set_apic_access_page_addr)(vcpu); 10243 } 10244 10245 void __kvm_request_immediate_exit(struct kvm_vcpu *vcpu) 10246 { 10247 smp_send_reschedule(vcpu->cpu); 10248 } 10249 EXPORT_SYMBOL_GPL(__kvm_request_immediate_exit); 10250 10251 /* 10252 * Called within kvm->srcu read side. 10253 * Returns 1 to let vcpu_run() continue the guest execution loop without 10254 * exiting to the userspace. Otherwise, the value will be returned to the 10255 * userspace. 10256 */ 10257 static int vcpu_enter_guest(struct kvm_vcpu *vcpu) 10258 { 10259 int r; 10260 bool req_int_win = 10261 dm_request_for_irq_injection(vcpu) && 10262 kvm_cpu_accept_dm_intr(vcpu); 10263 fastpath_t exit_fastpath; 10264 10265 bool req_immediate_exit = false; 10266 10267 /* Forbid vmenter if vcpu dirty ring is soft-full */ 10268 if (unlikely(vcpu->kvm->dirty_ring_size && 10269 kvm_dirty_ring_soft_full(&vcpu->dirty_ring))) { 10270 vcpu->run->exit_reason = KVM_EXIT_DIRTY_RING_FULL; 10271 trace_kvm_dirty_ring_exit(vcpu); 10272 r = 0; 10273 goto out; 10274 } 10275 10276 if (kvm_request_pending(vcpu)) { 10277 if (kvm_check_request(KVM_REQ_VM_DEAD, vcpu)) { 10278 r = -EIO; 10279 goto out; 10280 } 10281 if (kvm_check_request(KVM_REQ_GET_NESTED_STATE_PAGES, vcpu)) { 10282 if (unlikely(!kvm_x86_ops.nested_ops->get_nested_state_pages(vcpu))) { 10283 r = 0; 10284 goto out; 10285 } 10286 } 10287 if (kvm_check_request(KVM_REQ_MMU_FREE_OBSOLETE_ROOTS, vcpu)) 10288 kvm_mmu_free_obsolete_roots(vcpu); 10289 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu)) 10290 __kvm_migrate_timers(vcpu); 10291 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu)) 10292 kvm_update_masterclock(vcpu->kvm); 10293 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu)) 10294 kvm_gen_kvmclock_update(vcpu); 10295 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) { 10296 r = kvm_guest_time_update(vcpu); 10297 if (unlikely(r)) 10298 goto out; 10299 } 10300 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu)) 10301 kvm_mmu_sync_roots(vcpu); 10302 if (kvm_check_request(KVM_REQ_LOAD_MMU_PGD, vcpu)) 10303 kvm_mmu_load_pgd(vcpu); 10304 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu)) { 10305 kvm_vcpu_flush_tlb_all(vcpu); 10306 10307 /* Flushing all ASIDs flushes the current ASID... */ 10308 kvm_clear_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu); 10309 } 10310 kvm_service_local_tlb_flush_requests(vcpu); 10311 10312 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) { 10313 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS; 10314 r = 0; 10315 goto out; 10316 } 10317 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) { 10318 if (is_guest_mode(vcpu)) { 10319 kvm_x86_ops.nested_ops->triple_fault(vcpu); 10320 } else { 10321 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN; 10322 vcpu->mmio_needed = 0; 10323 r = 0; 10324 goto out; 10325 } 10326 } 10327 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) { 10328 /* Page is swapped out. Do synthetic halt */ 10329 vcpu->arch.apf.halted = true; 10330 r = 1; 10331 goto out; 10332 } 10333 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu)) 10334 record_steal_time(vcpu); 10335 if (kvm_check_request(KVM_REQ_SMI, vcpu)) 10336 process_smi(vcpu); 10337 if (kvm_check_request(KVM_REQ_NMI, vcpu)) 10338 process_nmi(vcpu); 10339 if (kvm_check_request(KVM_REQ_PMU, vcpu)) 10340 kvm_pmu_handle_event(vcpu); 10341 if (kvm_check_request(KVM_REQ_PMI, vcpu)) 10342 kvm_pmu_deliver_pmi(vcpu); 10343 if (kvm_check_request(KVM_REQ_IOAPIC_EOI_EXIT, vcpu)) { 10344 BUG_ON(vcpu->arch.pending_ioapic_eoi > 255); 10345 if (test_bit(vcpu->arch.pending_ioapic_eoi, 10346 vcpu->arch.ioapic_handled_vectors)) { 10347 vcpu->run->exit_reason = KVM_EXIT_IOAPIC_EOI; 10348 vcpu->run->eoi.vector = 10349 vcpu->arch.pending_ioapic_eoi; 10350 r = 0; 10351 goto out; 10352 } 10353 } 10354 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu)) 10355 vcpu_scan_ioapic(vcpu); 10356 if (kvm_check_request(KVM_REQ_LOAD_EOI_EXITMAP, vcpu)) 10357 vcpu_load_eoi_exitmap(vcpu); 10358 if (kvm_check_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu)) 10359 kvm_vcpu_reload_apic_access_page(vcpu); 10360 if (kvm_check_request(KVM_REQ_HV_CRASH, vcpu)) { 10361 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT; 10362 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_CRASH; 10363 vcpu->run->system_event.ndata = 0; 10364 r = 0; 10365 goto out; 10366 } 10367 if (kvm_check_request(KVM_REQ_HV_RESET, vcpu)) { 10368 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT; 10369 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_RESET; 10370 vcpu->run->system_event.ndata = 0; 10371 r = 0; 10372 goto out; 10373 } 10374 if (kvm_check_request(KVM_REQ_HV_EXIT, vcpu)) { 10375 struct kvm_vcpu_hv *hv_vcpu = to_hv_vcpu(vcpu); 10376 10377 vcpu->run->exit_reason = KVM_EXIT_HYPERV; 10378 vcpu->run->hyperv = hv_vcpu->exit; 10379 r = 0; 10380 goto out; 10381 } 10382 10383 /* 10384 * KVM_REQ_HV_STIMER has to be processed after 10385 * KVM_REQ_CLOCK_UPDATE, because Hyper-V SynIC timers 10386 * depend on the guest clock being up-to-date 10387 */ 10388 if (kvm_check_request(KVM_REQ_HV_STIMER, vcpu)) 10389 kvm_hv_process_stimers(vcpu); 10390 if (kvm_check_request(KVM_REQ_APICV_UPDATE, vcpu)) 10391 kvm_vcpu_update_apicv(vcpu); 10392 if (kvm_check_request(KVM_REQ_APF_READY, vcpu)) 10393 kvm_check_async_pf_completion(vcpu); 10394 if (kvm_check_request(KVM_REQ_MSR_FILTER_CHANGED, vcpu)) 10395 static_call(kvm_x86_msr_filter_changed)(vcpu); 10396 10397 if (kvm_check_request(KVM_REQ_UPDATE_CPU_DIRTY_LOGGING, vcpu)) 10398 static_call(kvm_x86_update_cpu_dirty_logging)(vcpu); 10399 } 10400 10401 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win || 10402 kvm_xen_has_interrupt(vcpu)) { 10403 ++vcpu->stat.req_event; 10404 r = kvm_apic_accept_events(vcpu); 10405 if (r < 0) { 10406 r = 0; 10407 goto out; 10408 } 10409 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) { 10410 r = 1; 10411 goto out; 10412 } 10413 10414 r = inject_pending_event(vcpu, &req_immediate_exit); 10415 if (r < 0) { 10416 r = 0; 10417 goto out; 10418 } 10419 if (req_int_win) 10420 static_call(kvm_x86_enable_irq_window)(vcpu); 10421 10422 if (kvm_lapic_enabled(vcpu)) { 10423 update_cr8_intercept(vcpu); 10424 kvm_lapic_sync_to_vapic(vcpu); 10425 } 10426 } 10427 10428 r = kvm_mmu_reload(vcpu); 10429 if (unlikely(r)) { 10430 goto cancel_injection; 10431 } 10432 10433 preempt_disable(); 10434 10435 static_call(kvm_x86_prepare_switch_to_guest)(vcpu); 10436 10437 /* 10438 * Disable IRQs before setting IN_GUEST_MODE. Posted interrupt 10439 * IPI are then delayed after guest entry, which ensures that they 10440 * result in virtual interrupt delivery. 10441 */ 10442 local_irq_disable(); 10443 10444 /* Store vcpu->apicv_active before vcpu->mode. */ 10445 smp_store_release(&vcpu->mode, IN_GUEST_MODE); 10446 10447 kvm_vcpu_srcu_read_unlock(vcpu); 10448 10449 /* 10450 * 1) We should set ->mode before checking ->requests. Please see 10451 * the comment in kvm_vcpu_exiting_guest_mode(). 10452 * 10453 * 2) For APICv, we should set ->mode before checking PID.ON. This 10454 * pairs with the memory barrier implicit in pi_test_and_set_on 10455 * (see vmx_deliver_posted_interrupt). 10456 * 10457 * 3) This also orders the write to mode from any reads to the page 10458 * tables done while the VCPU is running. Please see the comment 10459 * in kvm_flush_remote_tlbs. 10460 */ 10461 smp_mb__after_srcu_read_unlock(); 10462 10463 /* 10464 * Process pending posted interrupts to handle the case where the 10465 * notification IRQ arrived in the host, or was never sent (because the 10466 * target vCPU wasn't running). Do this regardless of the vCPU's APICv 10467 * status, KVM doesn't update assigned devices when APICv is inhibited, 10468 * i.e. they can post interrupts even if APICv is temporarily disabled. 10469 */ 10470 if (kvm_lapic_enabled(vcpu)) 10471 static_call_cond(kvm_x86_sync_pir_to_irr)(vcpu); 10472 10473 if (kvm_vcpu_exit_request(vcpu)) { 10474 vcpu->mode = OUTSIDE_GUEST_MODE; 10475 smp_wmb(); 10476 local_irq_enable(); 10477 preempt_enable(); 10478 kvm_vcpu_srcu_read_lock(vcpu); 10479 r = 1; 10480 goto cancel_injection; 10481 } 10482 10483 if (req_immediate_exit) { 10484 kvm_make_request(KVM_REQ_EVENT, vcpu); 10485 static_call(kvm_x86_request_immediate_exit)(vcpu); 10486 } 10487 10488 fpregs_assert_state_consistent(); 10489 if (test_thread_flag(TIF_NEED_FPU_LOAD)) 10490 switch_fpu_return(); 10491 10492 if (vcpu->arch.guest_fpu.xfd_err) 10493 wrmsrl(MSR_IA32_XFD_ERR, vcpu->arch.guest_fpu.xfd_err); 10494 10495 if (unlikely(vcpu->arch.switch_db_regs)) { 10496 set_debugreg(0, 7); 10497 set_debugreg(vcpu->arch.eff_db[0], 0); 10498 set_debugreg(vcpu->arch.eff_db[1], 1); 10499 set_debugreg(vcpu->arch.eff_db[2], 2); 10500 set_debugreg(vcpu->arch.eff_db[3], 3); 10501 } else if (unlikely(hw_breakpoint_active())) { 10502 set_debugreg(0, 7); 10503 } 10504 10505 guest_timing_enter_irqoff(); 10506 10507 for (;;) { 10508 /* 10509 * Assert that vCPU vs. VM APICv state is consistent. An APICv 10510 * update must kick and wait for all vCPUs before toggling the 10511 * per-VM state, and responsing vCPUs must wait for the update 10512 * to complete before servicing KVM_REQ_APICV_UPDATE. 10513 */ 10514 WARN_ON_ONCE((kvm_vcpu_apicv_activated(vcpu) != kvm_vcpu_apicv_active(vcpu)) && 10515 (kvm_get_apic_mode(vcpu) != LAPIC_MODE_DISABLED)); 10516 10517 exit_fastpath = static_call(kvm_x86_vcpu_run)(vcpu); 10518 if (likely(exit_fastpath != EXIT_FASTPATH_REENTER_GUEST)) 10519 break; 10520 10521 if (kvm_lapic_enabled(vcpu)) 10522 static_call_cond(kvm_x86_sync_pir_to_irr)(vcpu); 10523 10524 if (unlikely(kvm_vcpu_exit_request(vcpu))) { 10525 exit_fastpath = EXIT_FASTPATH_EXIT_HANDLED; 10526 break; 10527 } 10528 } 10529 10530 /* 10531 * Do this here before restoring debug registers on the host. And 10532 * since we do this before handling the vmexit, a DR access vmexit 10533 * can (a) read the correct value of the debug registers, (b) set 10534 * KVM_DEBUGREG_WONT_EXIT again. 10535 */ 10536 if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) { 10537 WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP); 10538 static_call(kvm_x86_sync_dirty_debug_regs)(vcpu); 10539 kvm_update_dr0123(vcpu); 10540 kvm_update_dr7(vcpu); 10541 } 10542 10543 /* 10544 * If the guest has used debug registers, at least dr7 10545 * will be disabled while returning to the host. 10546 * If we don't have active breakpoints in the host, we don't 10547 * care about the messed up debug address registers. But if 10548 * we have some of them active, restore the old state. 10549 */ 10550 if (hw_breakpoint_active()) 10551 hw_breakpoint_restore(); 10552 10553 vcpu->arch.last_vmentry_cpu = vcpu->cpu; 10554 vcpu->arch.last_guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc()); 10555 10556 vcpu->mode = OUTSIDE_GUEST_MODE; 10557 smp_wmb(); 10558 10559 /* 10560 * Sync xfd before calling handle_exit_irqoff() which may 10561 * rely on the fact that guest_fpu::xfd is up-to-date (e.g. 10562 * in #NM irqoff handler). 10563 */ 10564 if (vcpu->arch.xfd_no_write_intercept) 10565 fpu_sync_guest_vmexit_xfd_state(); 10566 10567 static_call(kvm_x86_handle_exit_irqoff)(vcpu); 10568 10569 if (vcpu->arch.guest_fpu.xfd_err) 10570 wrmsrl(MSR_IA32_XFD_ERR, 0); 10571 10572 /* 10573 * Consume any pending interrupts, including the possible source of 10574 * VM-Exit on SVM and any ticks that occur between VM-Exit and now. 10575 * An instruction is required after local_irq_enable() to fully unblock 10576 * interrupts on processors that implement an interrupt shadow, the 10577 * stat.exits increment will do nicely. 10578 */ 10579 kvm_before_interrupt(vcpu, KVM_HANDLING_IRQ); 10580 local_irq_enable(); 10581 ++vcpu->stat.exits; 10582 local_irq_disable(); 10583 kvm_after_interrupt(vcpu); 10584 10585 /* 10586 * Wait until after servicing IRQs to account guest time so that any 10587 * ticks that occurred while running the guest are properly accounted 10588 * to the guest. Waiting until IRQs are enabled degrades the accuracy 10589 * of accounting via context tracking, but the loss of accuracy is 10590 * acceptable for all known use cases. 10591 */ 10592 guest_timing_exit_irqoff(); 10593 10594 local_irq_enable(); 10595 preempt_enable(); 10596 10597 kvm_vcpu_srcu_read_lock(vcpu); 10598 10599 /* 10600 * Profile KVM exit RIPs: 10601 */ 10602 if (unlikely(prof_on == KVM_PROFILING)) { 10603 unsigned long rip = kvm_rip_read(vcpu); 10604 profile_hit(KVM_PROFILING, (void *)rip); 10605 } 10606 10607 if (unlikely(vcpu->arch.tsc_always_catchup)) 10608 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 10609 10610 if (vcpu->arch.apic_attention) 10611 kvm_lapic_sync_from_vapic(vcpu); 10612 10613 r = static_call(kvm_x86_handle_exit)(vcpu, exit_fastpath); 10614 return r; 10615 10616 cancel_injection: 10617 if (req_immediate_exit) 10618 kvm_make_request(KVM_REQ_EVENT, vcpu); 10619 static_call(kvm_x86_cancel_injection)(vcpu); 10620 if (unlikely(vcpu->arch.apic_attention)) 10621 kvm_lapic_sync_from_vapic(vcpu); 10622 out: 10623 return r; 10624 } 10625 10626 /* Called within kvm->srcu read side. */ 10627 static inline int vcpu_block(struct kvm_vcpu *vcpu) 10628 { 10629 bool hv_timer; 10630 10631 if (!kvm_arch_vcpu_runnable(vcpu)) { 10632 /* 10633 * Switch to the software timer before halt-polling/blocking as 10634 * the guest's timer may be a break event for the vCPU, and the 10635 * hypervisor timer runs only when the CPU is in guest mode. 10636 * Switch before halt-polling so that KVM recognizes an expired 10637 * timer before blocking. 10638 */ 10639 hv_timer = kvm_lapic_hv_timer_in_use(vcpu); 10640 if (hv_timer) 10641 kvm_lapic_switch_to_sw_timer(vcpu); 10642 10643 kvm_vcpu_srcu_read_unlock(vcpu); 10644 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED) 10645 kvm_vcpu_halt(vcpu); 10646 else 10647 kvm_vcpu_block(vcpu); 10648 kvm_vcpu_srcu_read_lock(vcpu); 10649 10650 if (hv_timer) 10651 kvm_lapic_switch_to_hv_timer(vcpu); 10652 10653 if (!kvm_check_request(KVM_REQ_UNHALT, vcpu)) 10654 return 1; 10655 } 10656 10657 if (kvm_apic_accept_events(vcpu) < 0) 10658 return 0; 10659 switch(vcpu->arch.mp_state) { 10660 case KVM_MP_STATE_HALTED: 10661 case KVM_MP_STATE_AP_RESET_HOLD: 10662 vcpu->arch.pv.pv_unhalted = false; 10663 vcpu->arch.mp_state = 10664 KVM_MP_STATE_RUNNABLE; 10665 fallthrough; 10666 case KVM_MP_STATE_RUNNABLE: 10667 vcpu->arch.apf.halted = false; 10668 break; 10669 case KVM_MP_STATE_INIT_RECEIVED: 10670 break; 10671 default: 10672 WARN_ON_ONCE(1); 10673 break; 10674 } 10675 return 1; 10676 } 10677 10678 static inline bool kvm_vcpu_running(struct kvm_vcpu *vcpu) 10679 { 10680 if (is_guest_mode(vcpu)) 10681 kvm_check_nested_events(vcpu); 10682 10683 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE && 10684 !vcpu->arch.apf.halted); 10685 } 10686 10687 /* Called within kvm->srcu read side. */ 10688 static int vcpu_run(struct kvm_vcpu *vcpu) 10689 { 10690 int r; 10691 10692 vcpu->arch.l1tf_flush_l1d = true; 10693 10694 for (;;) { 10695 /* 10696 * If another guest vCPU requests a PV TLB flush in the middle 10697 * of instruction emulation, the rest of the emulation could 10698 * use a stale page translation. Assume that any code after 10699 * this point can start executing an instruction. 10700 */ 10701 vcpu->arch.at_instruction_boundary = false; 10702 if (kvm_vcpu_running(vcpu)) { 10703 r = vcpu_enter_guest(vcpu); 10704 } else { 10705 r = vcpu_block(vcpu); 10706 } 10707 10708 if (r <= 0) 10709 break; 10710 10711 kvm_clear_request(KVM_REQ_UNBLOCK, vcpu); 10712 if (kvm_xen_has_pending_events(vcpu)) 10713 kvm_xen_inject_pending_events(vcpu); 10714 10715 if (kvm_cpu_has_pending_timer(vcpu)) 10716 kvm_inject_pending_timer_irqs(vcpu); 10717 10718 if (dm_request_for_irq_injection(vcpu) && 10719 kvm_vcpu_ready_for_interrupt_injection(vcpu)) { 10720 r = 0; 10721 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN; 10722 ++vcpu->stat.request_irq_exits; 10723 break; 10724 } 10725 10726 if (__xfer_to_guest_mode_work_pending()) { 10727 kvm_vcpu_srcu_read_unlock(vcpu); 10728 r = xfer_to_guest_mode_handle_work(vcpu); 10729 kvm_vcpu_srcu_read_lock(vcpu); 10730 if (r) 10731 return r; 10732 } 10733 } 10734 10735 return r; 10736 } 10737 10738 static inline int complete_emulated_io(struct kvm_vcpu *vcpu) 10739 { 10740 return kvm_emulate_instruction(vcpu, EMULTYPE_NO_DECODE); 10741 } 10742 10743 static int complete_emulated_pio(struct kvm_vcpu *vcpu) 10744 { 10745 BUG_ON(!vcpu->arch.pio.count); 10746 10747 return complete_emulated_io(vcpu); 10748 } 10749 10750 /* 10751 * Implements the following, as a state machine: 10752 * 10753 * read: 10754 * for each fragment 10755 * for each mmio piece in the fragment 10756 * write gpa, len 10757 * exit 10758 * copy data 10759 * execute insn 10760 * 10761 * write: 10762 * for each fragment 10763 * for each mmio piece in the fragment 10764 * write gpa, len 10765 * copy data 10766 * exit 10767 */ 10768 static int complete_emulated_mmio(struct kvm_vcpu *vcpu) 10769 { 10770 struct kvm_run *run = vcpu->run; 10771 struct kvm_mmio_fragment *frag; 10772 unsigned len; 10773 10774 BUG_ON(!vcpu->mmio_needed); 10775 10776 /* Complete previous fragment */ 10777 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment]; 10778 len = min(8u, frag->len); 10779 if (!vcpu->mmio_is_write) 10780 memcpy(frag->data, run->mmio.data, len); 10781 10782 if (frag->len <= 8) { 10783 /* Switch to the next fragment. */ 10784 frag++; 10785 vcpu->mmio_cur_fragment++; 10786 } else { 10787 /* Go forward to the next mmio piece. */ 10788 frag->data += len; 10789 frag->gpa += len; 10790 frag->len -= len; 10791 } 10792 10793 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) { 10794 vcpu->mmio_needed = 0; 10795 10796 /* FIXME: return into emulator if single-stepping. */ 10797 if (vcpu->mmio_is_write) 10798 return 1; 10799 vcpu->mmio_read_completed = 1; 10800 return complete_emulated_io(vcpu); 10801 } 10802 10803 run->exit_reason = KVM_EXIT_MMIO; 10804 run->mmio.phys_addr = frag->gpa; 10805 if (vcpu->mmio_is_write) 10806 memcpy(run->mmio.data, frag->data, min(8u, frag->len)); 10807 run->mmio.len = min(8u, frag->len); 10808 run->mmio.is_write = vcpu->mmio_is_write; 10809 vcpu->arch.complete_userspace_io = complete_emulated_mmio; 10810 return 0; 10811 } 10812 10813 /* Swap (qemu) user FPU context for the guest FPU context. */ 10814 static void kvm_load_guest_fpu(struct kvm_vcpu *vcpu) 10815 { 10816 /* Exclude PKRU, it's restored separately immediately after VM-Exit. */ 10817 fpu_swap_kvm_fpstate(&vcpu->arch.guest_fpu, true); 10818 trace_kvm_fpu(1); 10819 } 10820 10821 /* When vcpu_run ends, restore user space FPU context. */ 10822 static void kvm_put_guest_fpu(struct kvm_vcpu *vcpu) 10823 { 10824 fpu_swap_kvm_fpstate(&vcpu->arch.guest_fpu, false); 10825 ++vcpu->stat.fpu_reload; 10826 trace_kvm_fpu(0); 10827 } 10828 10829 int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu) 10830 { 10831 struct kvm_run *kvm_run = vcpu->run; 10832 int r; 10833 10834 vcpu_load(vcpu); 10835 kvm_sigset_activate(vcpu); 10836 kvm_run->flags = 0; 10837 kvm_load_guest_fpu(vcpu); 10838 10839 kvm_vcpu_srcu_read_lock(vcpu); 10840 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) { 10841 if (kvm_run->immediate_exit) { 10842 r = -EINTR; 10843 goto out; 10844 } 10845 /* 10846 * It should be impossible for the hypervisor timer to be in 10847 * use before KVM has ever run the vCPU. 10848 */ 10849 WARN_ON_ONCE(kvm_lapic_hv_timer_in_use(vcpu)); 10850 10851 kvm_vcpu_srcu_read_unlock(vcpu); 10852 kvm_vcpu_block(vcpu); 10853 kvm_vcpu_srcu_read_lock(vcpu); 10854 10855 if (kvm_apic_accept_events(vcpu) < 0) { 10856 r = 0; 10857 goto out; 10858 } 10859 kvm_clear_request(KVM_REQ_UNHALT, vcpu); 10860 r = -EAGAIN; 10861 if (signal_pending(current)) { 10862 r = -EINTR; 10863 kvm_run->exit_reason = KVM_EXIT_INTR; 10864 ++vcpu->stat.signal_exits; 10865 } 10866 goto out; 10867 } 10868 10869 if ((kvm_run->kvm_valid_regs & ~KVM_SYNC_X86_VALID_FIELDS) || 10870 (kvm_run->kvm_dirty_regs & ~KVM_SYNC_X86_VALID_FIELDS)) { 10871 r = -EINVAL; 10872 goto out; 10873 } 10874 10875 if (kvm_run->kvm_dirty_regs) { 10876 r = sync_regs(vcpu); 10877 if (r != 0) 10878 goto out; 10879 } 10880 10881 /* re-sync apic's tpr */ 10882 if (!lapic_in_kernel(vcpu)) { 10883 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) { 10884 r = -EINVAL; 10885 goto out; 10886 } 10887 } 10888 10889 if (unlikely(vcpu->arch.complete_userspace_io)) { 10890 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io; 10891 vcpu->arch.complete_userspace_io = NULL; 10892 r = cui(vcpu); 10893 if (r <= 0) 10894 goto out; 10895 } else { 10896 WARN_ON_ONCE(vcpu->arch.pio.count); 10897 WARN_ON_ONCE(vcpu->mmio_needed); 10898 } 10899 10900 if (kvm_run->immediate_exit) { 10901 r = -EINTR; 10902 goto out; 10903 } 10904 10905 r = static_call(kvm_x86_vcpu_pre_run)(vcpu); 10906 if (r <= 0) 10907 goto out; 10908 10909 r = vcpu_run(vcpu); 10910 10911 out: 10912 kvm_put_guest_fpu(vcpu); 10913 if (kvm_run->kvm_valid_regs) 10914 store_regs(vcpu); 10915 post_kvm_run_save(vcpu); 10916 kvm_vcpu_srcu_read_unlock(vcpu); 10917 10918 kvm_sigset_deactivate(vcpu); 10919 vcpu_put(vcpu); 10920 return r; 10921 } 10922 10923 static void __get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) 10924 { 10925 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) { 10926 /* 10927 * We are here if userspace calls get_regs() in the middle of 10928 * instruction emulation. Registers state needs to be copied 10929 * back from emulation context to vcpu. Userspace shouldn't do 10930 * that usually, but some bad designed PV devices (vmware 10931 * backdoor interface) need this to work 10932 */ 10933 emulator_writeback_register_cache(vcpu->arch.emulate_ctxt); 10934 vcpu->arch.emulate_regs_need_sync_to_vcpu = false; 10935 } 10936 regs->rax = kvm_rax_read(vcpu); 10937 regs->rbx = kvm_rbx_read(vcpu); 10938 regs->rcx = kvm_rcx_read(vcpu); 10939 regs->rdx = kvm_rdx_read(vcpu); 10940 regs->rsi = kvm_rsi_read(vcpu); 10941 regs->rdi = kvm_rdi_read(vcpu); 10942 regs->rsp = kvm_rsp_read(vcpu); 10943 regs->rbp = kvm_rbp_read(vcpu); 10944 #ifdef CONFIG_X86_64 10945 regs->r8 = kvm_r8_read(vcpu); 10946 regs->r9 = kvm_r9_read(vcpu); 10947 regs->r10 = kvm_r10_read(vcpu); 10948 regs->r11 = kvm_r11_read(vcpu); 10949 regs->r12 = kvm_r12_read(vcpu); 10950 regs->r13 = kvm_r13_read(vcpu); 10951 regs->r14 = kvm_r14_read(vcpu); 10952 regs->r15 = kvm_r15_read(vcpu); 10953 #endif 10954 10955 regs->rip = kvm_rip_read(vcpu); 10956 regs->rflags = kvm_get_rflags(vcpu); 10957 } 10958 10959 int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) 10960 { 10961 vcpu_load(vcpu); 10962 __get_regs(vcpu, regs); 10963 vcpu_put(vcpu); 10964 return 0; 10965 } 10966 10967 static void __set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) 10968 { 10969 vcpu->arch.emulate_regs_need_sync_from_vcpu = true; 10970 vcpu->arch.emulate_regs_need_sync_to_vcpu = false; 10971 10972 kvm_rax_write(vcpu, regs->rax); 10973 kvm_rbx_write(vcpu, regs->rbx); 10974 kvm_rcx_write(vcpu, regs->rcx); 10975 kvm_rdx_write(vcpu, regs->rdx); 10976 kvm_rsi_write(vcpu, regs->rsi); 10977 kvm_rdi_write(vcpu, regs->rdi); 10978 kvm_rsp_write(vcpu, regs->rsp); 10979 kvm_rbp_write(vcpu, regs->rbp); 10980 #ifdef CONFIG_X86_64 10981 kvm_r8_write(vcpu, regs->r8); 10982 kvm_r9_write(vcpu, regs->r9); 10983 kvm_r10_write(vcpu, regs->r10); 10984 kvm_r11_write(vcpu, regs->r11); 10985 kvm_r12_write(vcpu, regs->r12); 10986 kvm_r13_write(vcpu, regs->r13); 10987 kvm_r14_write(vcpu, regs->r14); 10988 kvm_r15_write(vcpu, regs->r15); 10989 #endif 10990 10991 kvm_rip_write(vcpu, regs->rip); 10992 kvm_set_rflags(vcpu, regs->rflags | X86_EFLAGS_FIXED); 10993 10994 vcpu->arch.exception.pending = false; 10995 10996 kvm_make_request(KVM_REQ_EVENT, vcpu); 10997 } 10998 10999 int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) 11000 { 11001 vcpu_load(vcpu); 11002 __set_regs(vcpu, regs); 11003 vcpu_put(vcpu); 11004 return 0; 11005 } 11006 11007 static void __get_sregs_common(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs) 11008 { 11009 struct desc_ptr dt; 11010 11011 if (vcpu->arch.guest_state_protected) 11012 goto skip_protected_regs; 11013 11014 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS); 11015 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS); 11016 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES); 11017 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS); 11018 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS); 11019 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS); 11020 11021 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR); 11022 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR); 11023 11024 static_call(kvm_x86_get_idt)(vcpu, &dt); 11025 sregs->idt.limit = dt.size; 11026 sregs->idt.base = dt.address; 11027 static_call(kvm_x86_get_gdt)(vcpu, &dt); 11028 sregs->gdt.limit = dt.size; 11029 sregs->gdt.base = dt.address; 11030 11031 sregs->cr2 = vcpu->arch.cr2; 11032 sregs->cr3 = kvm_read_cr3(vcpu); 11033 11034 skip_protected_regs: 11035 sregs->cr0 = kvm_read_cr0(vcpu); 11036 sregs->cr4 = kvm_read_cr4(vcpu); 11037 sregs->cr8 = kvm_get_cr8(vcpu); 11038 sregs->efer = vcpu->arch.efer; 11039 sregs->apic_base = kvm_get_apic_base(vcpu); 11040 } 11041 11042 static void __get_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs) 11043 { 11044 __get_sregs_common(vcpu, sregs); 11045 11046 if (vcpu->arch.guest_state_protected) 11047 return; 11048 11049 if (vcpu->arch.interrupt.injected && !vcpu->arch.interrupt.soft) 11050 set_bit(vcpu->arch.interrupt.nr, 11051 (unsigned long *)sregs->interrupt_bitmap); 11052 } 11053 11054 static void __get_sregs2(struct kvm_vcpu *vcpu, struct kvm_sregs2 *sregs2) 11055 { 11056 int i; 11057 11058 __get_sregs_common(vcpu, (struct kvm_sregs *)sregs2); 11059 11060 if (vcpu->arch.guest_state_protected) 11061 return; 11062 11063 if (is_pae_paging(vcpu)) { 11064 for (i = 0 ; i < 4 ; i++) 11065 sregs2->pdptrs[i] = kvm_pdptr_read(vcpu, i); 11066 sregs2->flags |= KVM_SREGS2_FLAGS_PDPTRS_VALID; 11067 } 11068 } 11069 11070 int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu, 11071 struct kvm_sregs *sregs) 11072 { 11073 vcpu_load(vcpu); 11074 __get_sregs(vcpu, sregs); 11075 vcpu_put(vcpu); 11076 return 0; 11077 } 11078 11079 int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu, 11080 struct kvm_mp_state *mp_state) 11081 { 11082 int r; 11083 11084 vcpu_load(vcpu); 11085 if (kvm_mpx_supported()) 11086 kvm_load_guest_fpu(vcpu); 11087 11088 r = kvm_apic_accept_events(vcpu); 11089 if (r < 0) 11090 goto out; 11091 r = 0; 11092 11093 if ((vcpu->arch.mp_state == KVM_MP_STATE_HALTED || 11094 vcpu->arch.mp_state == KVM_MP_STATE_AP_RESET_HOLD) && 11095 vcpu->arch.pv.pv_unhalted) 11096 mp_state->mp_state = KVM_MP_STATE_RUNNABLE; 11097 else 11098 mp_state->mp_state = vcpu->arch.mp_state; 11099 11100 out: 11101 if (kvm_mpx_supported()) 11102 kvm_put_guest_fpu(vcpu); 11103 vcpu_put(vcpu); 11104 return r; 11105 } 11106 11107 int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu, 11108 struct kvm_mp_state *mp_state) 11109 { 11110 int ret = -EINVAL; 11111 11112 vcpu_load(vcpu); 11113 11114 switch (mp_state->mp_state) { 11115 case KVM_MP_STATE_UNINITIALIZED: 11116 case KVM_MP_STATE_HALTED: 11117 case KVM_MP_STATE_AP_RESET_HOLD: 11118 case KVM_MP_STATE_INIT_RECEIVED: 11119 case KVM_MP_STATE_SIPI_RECEIVED: 11120 if (!lapic_in_kernel(vcpu)) 11121 goto out; 11122 break; 11123 11124 case KVM_MP_STATE_RUNNABLE: 11125 break; 11126 11127 default: 11128 goto out; 11129 } 11130 11131 /* 11132 * KVM_MP_STATE_INIT_RECEIVED means the processor is in 11133 * INIT state; latched init should be reported using 11134 * KVM_SET_VCPU_EVENTS, so reject it here. 11135 */ 11136 if ((kvm_vcpu_latch_init(vcpu) || vcpu->arch.smi_pending) && 11137 (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED || 11138 mp_state->mp_state == KVM_MP_STATE_INIT_RECEIVED)) 11139 goto out; 11140 11141 if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) { 11142 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED; 11143 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events); 11144 } else 11145 vcpu->arch.mp_state = mp_state->mp_state; 11146 kvm_make_request(KVM_REQ_EVENT, vcpu); 11147 11148 ret = 0; 11149 out: 11150 vcpu_put(vcpu); 11151 return ret; 11152 } 11153 11154 int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index, 11155 int reason, bool has_error_code, u32 error_code) 11156 { 11157 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt; 11158 int ret; 11159 11160 init_emulate_ctxt(vcpu); 11161 11162 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason, 11163 has_error_code, error_code); 11164 if (ret) { 11165 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR; 11166 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION; 11167 vcpu->run->internal.ndata = 0; 11168 return 0; 11169 } 11170 11171 kvm_rip_write(vcpu, ctxt->eip); 11172 kvm_set_rflags(vcpu, ctxt->eflags); 11173 return 1; 11174 } 11175 EXPORT_SYMBOL_GPL(kvm_task_switch); 11176 11177 static bool kvm_is_valid_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs) 11178 { 11179 if ((sregs->efer & EFER_LME) && (sregs->cr0 & X86_CR0_PG)) { 11180 /* 11181 * When EFER.LME and CR0.PG are set, the processor is in 11182 * 64-bit mode (though maybe in a 32-bit code segment). 11183 * CR4.PAE and EFER.LMA must be set. 11184 */ 11185 if (!(sregs->cr4 & X86_CR4_PAE) || !(sregs->efer & EFER_LMA)) 11186 return false; 11187 if (kvm_vcpu_is_illegal_gpa(vcpu, sregs->cr3)) 11188 return false; 11189 } else { 11190 /* 11191 * Not in 64-bit mode: EFER.LMA is clear and the code 11192 * segment cannot be 64-bit. 11193 */ 11194 if (sregs->efer & EFER_LMA || sregs->cs.l) 11195 return false; 11196 } 11197 11198 return kvm_is_valid_cr4(vcpu, sregs->cr4); 11199 } 11200 11201 static int __set_sregs_common(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs, 11202 int *mmu_reset_needed, bool update_pdptrs) 11203 { 11204 struct msr_data apic_base_msr; 11205 int idx; 11206 struct desc_ptr dt; 11207 11208 if (!kvm_is_valid_sregs(vcpu, sregs)) 11209 return -EINVAL; 11210 11211 apic_base_msr.data = sregs->apic_base; 11212 apic_base_msr.host_initiated = true; 11213 if (kvm_set_apic_base(vcpu, &apic_base_msr)) 11214 return -EINVAL; 11215 11216 if (vcpu->arch.guest_state_protected) 11217 return 0; 11218 11219 dt.size = sregs->idt.limit; 11220 dt.address = sregs->idt.base; 11221 static_call(kvm_x86_set_idt)(vcpu, &dt); 11222 dt.size = sregs->gdt.limit; 11223 dt.address = sregs->gdt.base; 11224 static_call(kvm_x86_set_gdt)(vcpu, &dt); 11225 11226 vcpu->arch.cr2 = sregs->cr2; 11227 *mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3; 11228 vcpu->arch.cr3 = sregs->cr3; 11229 kvm_register_mark_dirty(vcpu, VCPU_EXREG_CR3); 11230 static_call_cond(kvm_x86_post_set_cr3)(vcpu, sregs->cr3); 11231 11232 kvm_set_cr8(vcpu, sregs->cr8); 11233 11234 *mmu_reset_needed |= vcpu->arch.efer != sregs->efer; 11235 static_call(kvm_x86_set_efer)(vcpu, sregs->efer); 11236 11237 *mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0; 11238 static_call(kvm_x86_set_cr0)(vcpu, sregs->cr0); 11239 vcpu->arch.cr0 = sregs->cr0; 11240 11241 *mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4; 11242 static_call(kvm_x86_set_cr4)(vcpu, sregs->cr4); 11243 11244 if (update_pdptrs) { 11245 idx = srcu_read_lock(&vcpu->kvm->srcu); 11246 if (is_pae_paging(vcpu)) { 11247 load_pdptrs(vcpu, kvm_read_cr3(vcpu)); 11248 *mmu_reset_needed = 1; 11249 } 11250 srcu_read_unlock(&vcpu->kvm->srcu, idx); 11251 } 11252 11253 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS); 11254 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS); 11255 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES); 11256 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS); 11257 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS); 11258 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS); 11259 11260 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR); 11261 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR); 11262 11263 update_cr8_intercept(vcpu); 11264 11265 /* Older userspace won't unhalt the vcpu on reset. */ 11266 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 && 11267 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 && 11268 !is_protmode(vcpu)) 11269 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; 11270 11271 return 0; 11272 } 11273 11274 static int __set_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs) 11275 { 11276 int pending_vec, max_bits; 11277 int mmu_reset_needed = 0; 11278 int ret = __set_sregs_common(vcpu, sregs, &mmu_reset_needed, true); 11279 11280 if (ret) 11281 return ret; 11282 11283 if (mmu_reset_needed) 11284 kvm_mmu_reset_context(vcpu); 11285 11286 max_bits = KVM_NR_INTERRUPTS; 11287 pending_vec = find_first_bit( 11288 (const unsigned long *)sregs->interrupt_bitmap, max_bits); 11289 11290 if (pending_vec < max_bits) { 11291 kvm_queue_interrupt(vcpu, pending_vec, false); 11292 pr_debug("Set back pending irq %d\n", pending_vec); 11293 kvm_make_request(KVM_REQ_EVENT, vcpu); 11294 } 11295 return 0; 11296 } 11297 11298 static int __set_sregs2(struct kvm_vcpu *vcpu, struct kvm_sregs2 *sregs2) 11299 { 11300 int mmu_reset_needed = 0; 11301 bool valid_pdptrs = sregs2->flags & KVM_SREGS2_FLAGS_PDPTRS_VALID; 11302 bool pae = (sregs2->cr0 & X86_CR0_PG) && (sregs2->cr4 & X86_CR4_PAE) && 11303 !(sregs2->efer & EFER_LMA); 11304 int i, ret; 11305 11306 if (sregs2->flags & ~KVM_SREGS2_FLAGS_PDPTRS_VALID) 11307 return -EINVAL; 11308 11309 if (valid_pdptrs && (!pae || vcpu->arch.guest_state_protected)) 11310 return -EINVAL; 11311 11312 ret = __set_sregs_common(vcpu, (struct kvm_sregs *)sregs2, 11313 &mmu_reset_needed, !valid_pdptrs); 11314 if (ret) 11315 return ret; 11316 11317 if (valid_pdptrs) { 11318 for (i = 0; i < 4 ; i++) 11319 kvm_pdptr_write(vcpu, i, sregs2->pdptrs[i]); 11320 11321 kvm_register_mark_dirty(vcpu, VCPU_EXREG_PDPTR); 11322 mmu_reset_needed = 1; 11323 vcpu->arch.pdptrs_from_userspace = true; 11324 } 11325 if (mmu_reset_needed) 11326 kvm_mmu_reset_context(vcpu); 11327 return 0; 11328 } 11329 11330 int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu, 11331 struct kvm_sregs *sregs) 11332 { 11333 int ret; 11334 11335 vcpu_load(vcpu); 11336 ret = __set_sregs(vcpu, sregs); 11337 vcpu_put(vcpu); 11338 return ret; 11339 } 11340 11341 static void kvm_arch_vcpu_guestdbg_update_apicv_inhibit(struct kvm *kvm) 11342 { 11343 bool set = false; 11344 struct kvm_vcpu *vcpu; 11345 unsigned long i; 11346 11347 if (!enable_apicv) 11348 return; 11349 11350 down_write(&kvm->arch.apicv_update_lock); 11351 11352 kvm_for_each_vcpu(i, vcpu, kvm) { 11353 if (vcpu->guest_debug & KVM_GUESTDBG_BLOCKIRQ) { 11354 set = true; 11355 break; 11356 } 11357 } 11358 __kvm_set_or_clear_apicv_inhibit(kvm, APICV_INHIBIT_REASON_BLOCKIRQ, set); 11359 up_write(&kvm->arch.apicv_update_lock); 11360 } 11361 11362 int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu, 11363 struct kvm_guest_debug *dbg) 11364 { 11365 unsigned long rflags; 11366 int i, r; 11367 11368 if (vcpu->arch.guest_state_protected) 11369 return -EINVAL; 11370 11371 vcpu_load(vcpu); 11372 11373 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) { 11374 r = -EBUSY; 11375 if (vcpu->arch.exception.pending) 11376 goto out; 11377 if (dbg->control & KVM_GUESTDBG_INJECT_DB) 11378 kvm_queue_exception(vcpu, DB_VECTOR); 11379 else 11380 kvm_queue_exception(vcpu, BP_VECTOR); 11381 } 11382 11383 /* 11384 * Read rflags as long as potentially injected trace flags are still 11385 * filtered out. 11386 */ 11387 rflags = kvm_get_rflags(vcpu); 11388 11389 vcpu->guest_debug = dbg->control; 11390 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE)) 11391 vcpu->guest_debug = 0; 11392 11393 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) { 11394 for (i = 0; i < KVM_NR_DB_REGS; ++i) 11395 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i]; 11396 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7]; 11397 } else { 11398 for (i = 0; i < KVM_NR_DB_REGS; i++) 11399 vcpu->arch.eff_db[i] = vcpu->arch.db[i]; 11400 } 11401 kvm_update_dr7(vcpu); 11402 11403 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) 11404 vcpu->arch.singlestep_rip = kvm_get_linear_rip(vcpu); 11405 11406 /* 11407 * Trigger an rflags update that will inject or remove the trace 11408 * flags. 11409 */ 11410 kvm_set_rflags(vcpu, rflags); 11411 11412 static_call(kvm_x86_update_exception_bitmap)(vcpu); 11413 11414 kvm_arch_vcpu_guestdbg_update_apicv_inhibit(vcpu->kvm); 11415 11416 r = 0; 11417 11418 out: 11419 vcpu_put(vcpu); 11420 return r; 11421 } 11422 11423 /* 11424 * Translate a guest virtual address to a guest physical address. 11425 */ 11426 int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu, 11427 struct kvm_translation *tr) 11428 { 11429 unsigned long vaddr = tr->linear_address; 11430 gpa_t gpa; 11431 int idx; 11432 11433 vcpu_load(vcpu); 11434 11435 idx = srcu_read_lock(&vcpu->kvm->srcu); 11436 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL); 11437 srcu_read_unlock(&vcpu->kvm->srcu, idx); 11438 tr->physical_address = gpa; 11439 tr->valid = gpa != INVALID_GPA; 11440 tr->writeable = 1; 11441 tr->usermode = 0; 11442 11443 vcpu_put(vcpu); 11444 return 0; 11445 } 11446 11447 int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu) 11448 { 11449 struct fxregs_state *fxsave; 11450 11451 if (fpstate_is_confidential(&vcpu->arch.guest_fpu)) 11452 return 0; 11453 11454 vcpu_load(vcpu); 11455 11456 fxsave = &vcpu->arch.guest_fpu.fpstate->regs.fxsave; 11457 memcpy(fpu->fpr, fxsave->st_space, 128); 11458 fpu->fcw = fxsave->cwd; 11459 fpu->fsw = fxsave->swd; 11460 fpu->ftwx = fxsave->twd; 11461 fpu->last_opcode = fxsave->fop; 11462 fpu->last_ip = fxsave->rip; 11463 fpu->last_dp = fxsave->rdp; 11464 memcpy(fpu->xmm, fxsave->xmm_space, sizeof(fxsave->xmm_space)); 11465 11466 vcpu_put(vcpu); 11467 return 0; 11468 } 11469 11470 int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu) 11471 { 11472 struct fxregs_state *fxsave; 11473 11474 if (fpstate_is_confidential(&vcpu->arch.guest_fpu)) 11475 return 0; 11476 11477 vcpu_load(vcpu); 11478 11479 fxsave = &vcpu->arch.guest_fpu.fpstate->regs.fxsave; 11480 11481 memcpy(fxsave->st_space, fpu->fpr, 128); 11482 fxsave->cwd = fpu->fcw; 11483 fxsave->swd = fpu->fsw; 11484 fxsave->twd = fpu->ftwx; 11485 fxsave->fop = fpu->last_opcode; 11486 fxsave->rip = fpu->last_ip; 11487 fxsave->rdp = fpu->last_dp; 11488 memcpy(fxsave->xmm_space, fpu->xmm, sizeof(fxsave->xmm_space)); 11489 11490 vcpu_put(vcpu); 11491 return 0; 11492 } 11493 11494 static void store_regs(struct kvm_vcpu *vcpu) 11495 { 11496 BUILD_BUG_ON(sizeof(struct kvm_sync_regs) > SYNC_REGS_SIZE_BYTES); 11497 11498 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_REGS) 11499 __get_regs(vcpu, &vcpu->run->s.regs.regs); 11500 11501 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_SREGS) 11502 __get_sregs(vcpu, &vcpu->run->s.regs.sregs); 11503 11504 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_EVENTS) 11505 kvm_vcpu_ioctl_x86_get_vcpu_events( 11506 vcpu, &vcpu->run->s.regs.events); 11507 } 11508 11509 static int sync_regs(struct kvm_vcpu *vcpu) 11510 { 11511 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_REGS) { 11512 __set_regs(vcpu, &vcpu->run->s.regs.regs); 11513 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_REGS; 11514 } 11515 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_SREGS) { 11516 if (__set_sregs(vcpu, &vcpu->run->s.regs.sregs)) 11517 return -EINVAL; 11518 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_SREGS; 11519 } 11520 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_EVENTS) { 11521 if (kvm_vcpu_ioctl_x86_set_vcpu_events( 11522 vcpu, &vcpu->run->s.regs.events)) 11523 return -EINVAL; 11524 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_EVENTS; 11525 } 11526 11527 return 0; 11528 } 11529 11530 int kvm_arch_vcpu_precreate(struct kvm *kvm, unsigned int id) 11531 { 11532 if (kvm_check_tsc_unstable() && kvm->created_vcpus) 11533 pr_warn_once("kvm: SMP vm created on host with unstable TSC; " 11534 "guest TSC will not be reliable\n"); 11535 11536 if (!kvm->arch.max_vcpu_ids) 11537 kvm->arch.max_vcpu_ids = KVM_MAX_VCPU_IDS; 11538 11539 if (id >= kvm->arch.max_vcpu_ids) 11540 return -EINVAL; 11541 11542 return static_call(kvm_x86_vcpu_precreate)(kvm); 11543 } 11544 11545 int kvm_arch_vcpu_create(struct kvm_vcpu *vcpu) 11546 { 11547 struct page *page; 11548 int r; 11549 11550 vcpu->arch.last_vmentry_cpu = -1; 11551 vcpu->arch.regs_avail = ~0; 11552 vcpu->arch.regs_dirty = ~0; 11553 11554 if (!irqchip_in_kernel(vcpu->kvm) || kvm_vcpu_is_reset_bsp(vcpu)) 11555 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; 11556 else 11557 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED; 11558 11559 r = kvm_mmu_create(vcpu); 11560 if (r < 0) 11561 return r; 11562 11563 if (irqchip_in_kernel(vcpu->kvm)) { 11564 r = kvm_create_lapic(vcpu, lapic_timer_advance_ns); 11565 if (r < 0) 11566 goto fail_mmu_destroy; 11567 11568 /* 11569 * Defer evaluating inhibits until the vCPU is first run, as 11570 * this vCPU will not get notified of any changes until this 11571 * vCPU is visible to other vCPUs (marked online and added to 11572 * the set of vCPUs). Opportunistically mark APICv active as 11573 * VMX in particularly is highly unlikely to have inhibits. 11574 * Ignore the current per-VM APICv state so that vCPU creation 11575 * is guaranteed to run with a deterministic value, the request 11576 * will ensure the vCPU gets the correct state before VM-Entry. 11577 */ 11578 if (enable_apicv) { 11579 vcpu->arch.apic->apicv_active = true; 11580 kvm_make_request(KVM_REQ_APICV_UPDATE, vcpu); 11581 } 11582 } else 11583 static_branch_inc(&kvm_has_noapic_vcpu); 11584 11585 r = -ENOMEM; 11586 11587 page = alloc_page(GFP_KERNEL_ACCOUNT | __GFP_ZERO); 11588 if (!page) 11589 goto fail_free_lapic; 11590 vcpu->arch.pio_data = page_address(page); 11591 11592 vcpu->arch.mce_banks = kcalloc(KVM_MAX_MCE_BANKS * 4, sizeof(u64), 11593 GFP_KERNEL_ACCOUNT); 11594 vcpu->arch.mci_ctl2_banks = kcalloc(KVM_MAX_MCE_BANKS, sizeof(u64), 11595 GFP_KERNEL_ACCOUNT); 11596 if (!vcpu->arch.mce_banks || !vcpu->arch.mci_ctl2_banks) 11597 goto fail_free_mce_banks; 11598 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS; 11599 11600 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, 11601 GFP_KERNEL_ACCOUNT)) 11602 goto fail_free_mce_banks; 11603 11604 if (!alloc_emulate_ctxt(vcpu)) 11605 goto free_wbinvd_dirty_mask; 11606 11607 if (!fpu_alloc_guest_fpstate(&vcpu->arch.guest_fpu)) { 11608 pr_err("kvm: failed to allocate vcpu's fpu\n"); 11609 goto free_emulate_ctxt; 11610 } 11611 11612 vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu); 11613 vcpu->arch.reserved_gpa_bits = kvm_vcpu_reserved_gpa_bits_raw(vcpu); 11614 11615 vcpu->arch.pat = MSR_IA32_CR_PAT_DEFAULT; 11616 11617 kvm_async_pf_hash_reset(vcpu); 11618 kvm_pmu_init(vcpu); 11619 11620 vcpu->arch.pending_external_vector = -1; 11621 vcpu->arch.preempted_in_kernel = false; 11622 11623 #if IS_ENABLED(CONFIG_HYPERV) 11624 vcpu->arch.hv_root_tdp = INVALID_PAGE; 11625 #endif 11626 11627 r = static_call(kvm_x86_vcpu_create)(vcpu); 11628 if (r) 11629 goto free_guest_fpu; 11630 11631 vcpu->arch.arch_capabilities = kvm_get_arch_capabilities(); 11632 vcpu->arch.msr_platform_info = MSR_PLATFORM_INFO_CPUID_FAULT; 11633 kvm_xen_init_vcpu(vcpu); 11634 kvm_vcpu_mtrr_init(vcpu); 11635 vcpu_load(vcpu); 11636 kvm_set_tsc_khz(vcpu, vcpu->kvm->arch.default_tsc_khz); 11637 kvm_vcpu_reset(vcpu, false); 11638 kvm_init_mmu(vcpu); 11639 vcpu_put(vcpu); 11640 return 0; 11641 11642 free_guest_fpu: 11643 fpu_free_guest_fpstate(&vcpu->arch.guest_fpu); 11644 free_emulate_ctxt: 11645 kmem_cache_free(x86_emulator_cache, vcpu->arch.emulate_ctxt); 11646 free_wbinvd_dirty_mask: 11647 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask); 11648 fail_free_mce_banks: 11649 kfree(vcpu->arch.mce_banks); 11650 kfree(vcpu->arch.mci_ctl2_banks); 11651 free_page((unsigned long)vcpu->arch.pio_data); 11652 fail_free_lapic: 11653 kvm_free_lapic(vcpu); 11654 fail_mmu_destroy: 11655 kvm_mmu_destroy(vcpu); 11656 return r; 11657 } 11658 11659 void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu) 11660 { 11661 struct kvm *kvm = vcpu->kvm; 11662 11663 if (mutex_lock_killable(&vcpu->mutex)) 11664 return; 11665 vcpu_load(vcpu); 11666 kvm_synchronize_tsc(vcpu, 0); 11667 vcpu_put(vcpu); 11668 11669 /* poll control enabled by default */ 11670 vcpu->arch.msr_kvm_poll_control = 1; 11671 11672 mutex_unlock(&vcpu->mutex); 11673 11674 if (kvmclock_periodic_sync && vcpu->vcpu_idx == 0) 11675 schedule_delayed_work(&kvm->arch.kvmclock_sync_work, 11676 KVMCLOCK_SYNC_PERIOD); 11677 } 11678 11679 void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu) 11680 { 11681 int idx; 11682 11683 kvmclock_reset(vcpu); 11684 11685 static_call(kvm_x86_vcpu_free)(vcpu); 11686 11687 kmem_cache_free(x86_emulator_cache, vcpu->arch.emulate_ctxt); 11688 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask); 11689 fpu_free_guest_fpstate(&vcpu->arch.guest_fpu); 11690 11691 kvm_xen_destroy_vcpu(vcpu); 11692 kvm_hv_vcpu_uninit(vcpu); 11693 kvm_pmu_destroy(vcpu); 11694 kfree(vcpu->arch.mce_banks); 11695 kfree(vcpu->arch.mci_ctl2_banks); 11696 kvm_free_lapic(vcpu); 11697 idx = srcu_read_lock(&vcpu->kvm->srcu); 11698 kvm_mmu_destroy(vcpu); 11699 srcu_read_unlock(&vcpu->kvm->srcu, idx); 11700 free_page((unsigned long)vcpu->arch.pio_data); 11701 kvfree(vcpu->arch.cpuid_entries); 11702 if (!lapic_in_kernel(vcpu)) 11703 static_branch_dec(&kvm_has_noapic_vcpu); 11704 } 11705 11706 void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event) 11707 { 11708 struct kvm_cpuid_entry2 *cpuid_0x1; 11709 unsigned long old_cr0 = kvm_read_cr0(vcpu); 11710 unsigned long new_cr0; 11711 11712 /* 11713 * Several of the "set" flows, e.g. ->set_cr0(), read other registers 11714 * to handle side effects. RESET emulation hits those flows and relies 11715 * on emulated/virtualized registers, including those that are loaded 11716 * into hardware, to be zeroed at vCPU creation. Use CRs as a sentinel 11717 * to detect improper or missing initialization. 11718 */ 11719 WARN_ON_ONCE(!init_event && 11720 (old_cr0 || kvm_read_cr3(vcpu) || kvm_read_cr4(vcpu))); 11721 11722 kvm_lapic_reset(vcpu, init_event); 11723 11724 vcpu->arch.hflags = 0; 11725 11726 vcpu->arch.smi_pending = 0; 11727 vcpu->arch.smi_count = 0; 11728 atomic_set(&vcpu->arch.nmi_queued, 0); 11729 vcpu->arch.nmi_pending = 0; 11730 vcpu->arch.nmi_injected = false; 11731 kvm_clear_interrupt_queue(vcpu); 11732 kvm_clear_exception_queue(vcpu); 11733 11734 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db)); 11735 kvm_update_dr0123(vcpu); 11736 vcpu->arch.dr6 = DR6_ACTIVE_LOW; 11737 vcpu->arch.dr7 = DR7_FIXED_1; 11738 kvm_update_dr7(vcpu); 11739 11740 vcpu->arch.cr2 = 0; 11741 11742 kvm_make_request(KVM_REQ_EVENT, vcpu); 11743 vcpu->arch.apf.msr_en_val = 0; 11744 vcpu->arch.apf.msr_int_val = 0; 11745 vcpu->arch.st.msr_val = 0; 11746 11747 kvmclock_reset(vcpu); 11748 11749 kvm_clear_async_pf_completion_queue(vcpu); 11750 kvm_async_pf_hash_reset(vcpu); 11751 vcpu->arch.apf.halted = false; 11752 11753 if (vcpu->arch.guest_fpu.fpstate && kvm_mpx_supported()) { 11754 struct fpstate *fpstate = vcpu->arch.guest_fpu.fpstate; 11755 11756 /* 11757 * To avoid have the INIT path from kvm_apic_has_events() that be 11758 * called with loaded FPU and does not let userspace fix the state. 11759 */ 11760 if (init_event) 11761 kvm_put_guest_fpu(vcpu); 11762 11763 fpstate_clear_xstate_component(fpstate, XFEATURE_BNDREGS); 11764 fpstate_clear_xstate_component(fpstate, XFEATURE_BNDCSR); 11765 11766 if (init_event) 11767 kvm_load_guest_fpu(vcpu); 11768 } 11769 11770 if (!init_event) { 11771 kvm_pmu_reset(vcpu); 11772 vcpu->arch.smbase = 0x30000; 11773 11774 vcpu->arch.msr_misc_features_enables = 0; 11775 vcpu->arch.ia32_misc_enable_msr = MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL | 11776 MSR_IA32_MISC_ENABLE_BTS_UNAVAIL; 11777 11778 __kvm_set_xcr(vcpu, 0, XFEATURE_MASK_FP); 11779 __kvm_set_msr(vcpu, MSR_IA32_XSS, 0, true); 11780 } 11781 11782 /* All GPRs except RDX (handled below) are zeroed on RESET/INIT. */ 11783 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs)); 11784 kvm_register_mark_dirty(vcpu, VCPU_REGS_RSP); 11785 11786 /* 11787 * Fall back to KVM's default Family/Model/Stepping of 0x600 (P6/Athlon) 11788 * if no CPUID match is found. Note, it's impossible to get a match at 11789 * RESET since KVM emulates RESET before exposing the vCPU to userspace, 11790 * i.e. it's impossible for kvm_find_cpuid_entry() to find a valid entry 11791 * on RESET. But, go through the motions in case that's ever remedied. 11792 */ 11793 cpuid_0x1 = kvm_find_cpuid_entry(vcpu, 1); 11794 kvm_rdx_write(vcpu, cpuid_0x1 ? cpuid_0x1->eax : 0x600); 11795 11796 static_call(kvm_x86_vcpu_reset)(vcpu, init_event); 11797 11798 kvm_set_rflags(vcpu, X86_EFLAGS_FIXED); 11799 kvm_rip_write(vcpu, 0xfff0); 11800 11801 vcpu->arch.cr3 = 0; 11802 kvm_register_mark_dirty(vcpu, VCPU_EXREG_CR3); 11803 11804 /* 11805 * CR0.CD/NW are set on RESET, preserved on INIT. Note, some versions 11806 * of Intel's SDM list CD/NW as being set on INIT, but they contradict 11807 * (or qualify) that with a footnote stating that CD/NW are preserved. 11808 */ 11809 new_cr0 = X86_CR0_ET; 11810 if (init_event) 11811 new_cr0 |= (old_cr0 & (X86_CR0_NW | X86_CR0_CD)); 11812 else 11813 new_cr0 |= X86_CR0_NW | X86_CR0_CD; 11814 11815 static_call(kvm_x86_set_cr0)(vcpu, new_cr0); 11816 static_call(kvm_x86_set_cr4)(vcpu, 0); 11817 static_call(kvm_x86_set_efer)(vcpu, 0); 11818 static_call(kvm_x86_update_exception_bitmap)(vcpu); 11819 11820 /* 11821 * On the standard CR0/CR4/EFER modification paths, there are several 11822 * complex conditions determining whether the MMU has to be reset and/or 11823 * which PCIDs have to be flushed. However, CR0.WP and the paging-related 11824 * bits in CR4 and EFER are irrelevant if CR0.PG was '0'; and a reset+flush 11825 * is needed anyway if CR0.PG was '1' (which can only happen for INIT, as 11826 * CR0 will be '0' prior to RESET). So we only need to check CR0.PG here. 11827 */ 11828 if (old_cr0 & X86_CR0_PG) { 11829 kvm_make_request(KVM_REQ_TLB_FLUSH_GUEST, vcpu); 11830 kvm_mmu_reset_context(vcpu); 11831 } 11832 11833 /* 11834 * Intel's SDM states that all TLB entries are flushed on INIT. AMD's 11835 * APM states the TLBs are untouched by INIT, but it also states that 11836 * the TLBs are flushed on "External initialization of the processor." 11837 * Flush the guest TLB regardless of vendor, there is no meaningful 11838 * benefit in relying on the guest to flush the TLB immediately after 11839 * INIT. A spurious TLB flush is benign and likely negligible from a 11840 * performance perspective. 11841 */ 11842 if (init_event) 11843 kvm_make_request(KVM_REQ_TLB_FLUSH_GUEST, vcpu); 11844 } 11845 EXPORT_SYMBOL_GPL(kvm_vcpu_reset); 11846 11847 void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector) 11848 { 11849 struct kvm_segment cs; 11850 11851 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS); 11852 cs.selector = vector << 8; 11853 cs.base = vector << 12; 11854 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS); 11855 kvm_rip_write(vcpu, 0); 11856 } 11857 EXPORT_SYMBOL_GPL(kvm_vcpu_deliver_sipi_vector); 11858 11859 int kvm_arch_hardware_enable(void) 11860 { 11861 struct kvm *kvm; 11862 struct kvm_vcpu *vcpu; 11863 unsigned long i; 11864 int ret; 11865 u64 local_tsc; 11866 u64 max_tsc = 0; 11867 bool stable, backwards_tsc = false; 11868 11869 kvm_user_return_msr_cpu_online(); 11870 ret = static_call(kvm_x86_hardware_enable)(); 11871 if (ret != 0) 11872 return ret; 11873 11874 local_tsc = rdtsc(); 11875 stable = !kvm_check_tsc_unstable(); 11876 list_for_each_entry(kvm, &vm_list, vm_list) { 11877 kvm_for_each_vcpu(i, vcpu, kvm) { 11878 if (!stable && vcpu->cpu == smp_processor_id()) 11879 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 11880 if (stable && vcpu->arch.last_host_tsc > local_tsc) { 11881 backwards_tsc = true; 11882 if (vcpu->arch.last_host_tsc > max_tsc) 11883 max_tsc = vcpu->arch.last_host_tsc; 11884 } 11885 } 11886 } 11887 11888 /* 11889 * Sometimes, even reliable TSCs go backwards. This happens on 11890 * platforms that reset TSC during suspend or hibernate actions, but 11891 * maintain synchronization. We must compensate. Fortunately, we can 11892 * detect that condition here, which happens early in CPU bringup, 11893 * before any KVM threads can be running. Unfortunately, we can't 11894 * bring the TSCs fully up to date with real time, as we aren't yet far 11895 * enough into CPU bringup that we know how much real time has actually 11896 * elapsed; our helper function, ktime_get_boottime_ns() will be using boot 11897 * variables that haven't been updated yet. 11898 * 11899 * So we simply find the maximum observed TSC above, then record the 11900 * adjustment to TSC in each VCPU. When the VCPU later gets loaded, 11901 * the adjustment will be applied. Note that we accumulate 11902 * adjustments, in case multiple suspend cycles happen before some VCPU 11903 * gets a chance to run again. In the event that no KVM threads get a 11904 * chance to run, we will miss the entire elapsed period, as we'll have 11905 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may 11906 * loose cycle time. This isn't too big a deal, since the loss will be 11907 * uniform across all VCPUs (not to mention the scenario is extremely 11908 * unlikely). It is possible that a second hibernate recovery happens 11909 * much faster than a first, causing the observed TSC here to be 11910 * smaller; this would require additional padding adjustment, which is 11911 * why we set last_host_tsc to the local tsc observed here. 11912 * 11913 * N.B. - this code below runs only on platforms with reliable TSC, 11914 * as that is the only way backwards_tsc is set above. Also note 11915 * that this runs for ALL vcpus, which is not a bug; all VCPUs should 11916 * have the same delta_cyc adjustment applied if backwards_tsc 11917 * is detected. Note further, this adjustment is only done once, 11918 * as we reset last_host_tsc on all VCPUs to stop this from being 11919 * called multiple times (one for each physical CPU bringup). 11920 * 11921 * Platforms with unreliable TSCs don't have to deal with this, they 11922 * will be compensated by the logic in vcpu_load, which sets the TSC to 11923 * catchup mode. This will catchup all VCPUs to real time, but cannot 11924 * guarantee that they stay in perfect synchronization. 11925 */ 11926 if (backwards_tsc) { 11927 u64 delta_cyc = max_tsc - local_tsc; 11928 list_for_each_entry(kvm, &vm_list, vm_list) { 11929 kvm->arch.backwards_tsc_observed = true; 11930 kvm_for_each_vcpu(i, vcpu, kvm) { 11931 vcpu->arch.tsc_offset_adjustment += delta_cyc; 11932 vcpu->arch.last_host_tsc = local_tsc; 11933 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu); 11934 } 11935 11936 /* 11937 * We have to disable TSC offset matching.. if you were 11938 * booting a VM while issuing an S4 host suspend.... 11939 * you may have some problem. Solving this issue is 11940 * left as an exercise to the reader. 11941 */ 11942 kvm->arch.last_tsc_nsec = 0; 11943 kvm->arch.last_tsc_write = 0; 11944 } 11945 11946 } 11947 return 0; 11948 } 11949 11950 void kvm_arch_hardware_disable(void) 11951 { 11952 static_call(kvm_x86_hardware_disable)(); 11953 drop_user_return_notifiers(); 11954 } 11955 11956 static inline void kvm_ops_update(struct kvm_x86_init_ops *ops) 11957 { 11958 memcpy(&kvm_x86_ops, ops->runtime_ops, sizeof(kvm_x86_ops)); 11959 11960 #define __KVM_X86_OP(func) \ 11961 static_call_update(kvm_x86_##func, kvm_x86_ops.func); 11962 #define KVM_X86_OP(func) \ 11963 WARN_ON(!kvm_x86_ops.func); __KVM_X86_OP(func) 11964 #define KVM_X86_OP_OPTIONAL __KVM_X86_OP 11965 #define KVM_X86_OP_OPTIONAL_RET0(func) \ 11966 static_call_update(kvm_x86_##func, (void *)kvm_x86_ops.func ? : \ 11967 (void *)__static_call_return0); 11968 #include <asm/kvm-x86-ops.h> 11969 #undef __KVM_X86_OP 11970 11971 kvm_pmu_ops_update(ops->pmu_ops); 11972 } 11973 11974 int kvm_arch_hardware_setup(void *opaque) 11975 { 11976 struct kvm_x86_init_ops *ops = opaque; 11977 int r; 11978 11979 rdmsrl_safe(MSR_EFER, &host_efer); 11980 11981 if (boot_cpu_has(X86_FEATURE_XSAVES)) 11982 rdmsrl(MSR_IA32_XSS, host_xss); 11983 11984 kvm_init_pmu_capability(); 11985 11986 r = ops->hardware_setup(); 11987 if (r != 0) 11988 return r; 11989 11990 kvm_ops_update(ops); 11991 11992 kvm_register_perf_callbacks(ops->handle_intel_pt_intr); 11993 11994 if (!kvm_cpu_cap_has(X86_FEATURE_XSAVES)) 11995 kvm_caps.supported_xss = 0; 11996 11997 #define __kvm_cpu_cap_has(UNUSED_, f) kvm_cpu_cap_has(f) 11998 cr4_reserved_bits = __cr4_reserved_bits(__kvm_cpu_cap_has, UNUSED_); 11999 #undef __kvm_cpu_cap_has 12000 12001 if (kvm_caps.has_tsc_control) { 12002 /* 12003 * Make sure the user can only configure tsc_khz values that 12004 * fit into a signed integer. 12005 * A min value is not calculated because it will always 12006 * be 1 on all machines. 12007 */ 12008 u64 max = min(0x7fffffffULL, 12009 __scale_tsc(kvm_caps.max_tsc_scaling_ratio, tsc_khz)); 12010 kvm_caps.max_guest_tsc_khz = max; 12011 } 12012 kvm_caps.default_tsc_scaling_ratio = 1ULL << kvm_caps.tsc_scaling_ratio_frac_bits; 12013 kvm_init_msr_list(); 12014 return 0; 12015 } 12016 12017 void kvm_arch_hardware_unsetup(void) 12018 { 12019 kvm_unregister_perf_callbacks(); 12020 12021 static_call(kvm_x86_hardware_unsetup)(); 12022 } 12023 12024 int kvm_arch_check_processor_compat(void *opaque) 12025 { 12026 struct cpuinfo_x86 *c = &cpu_data(smp_processor_id()); 12027 struct kvm_x86_init_ops *ops = opaque; 12028 12029 WARN_ON(!irqs_disabled()); 12030 12031 if (__cr4_reserved_bits(cpu_has, c) != 12032 __cr4_reserved_bits(cpu_has, &boot_cpu_data)) 12033 return -EIO; 12034 12035 return ops->check_processor_compatibility(); 12036 } 12037 12038 bool kvm_vcpu_is_reset_bsp(struct kvm_vcpu *vcpu) 12039 { 12040 return vcpu->kvm->arch.bsp_vcpu_id == vcpu->vcpu_id; 12041 } 12042 EXPORT_SYMBOL_GPL(kvm_vcpu_is_reset_bsp); 12043 12044 bool kvm_vcpu_is_bsp(struct kvm_vcpu *vcpu) 12045 { 12046 return (vcpu->arch.apic_base & MSR_IA32_APICBASE_BSP) != 0; 12047 } 12048 12049 __read_mostly DEFINE_STATIC_KEY_FALSE(kvm_has_noapic_vcpu); 12050 EXPORT_SYMBOL_GPL(kvm_has_noapic_vcpu); 12051 12052 void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu) 12053 { 12054 struct kvm_pmu *pmu = vcpu_to_pmu(vcpu); 12055 12056 vcpu->arch.l1tf_flush_l1d = true; 12057 if (pmu->version && unlikely(pmu->event_count)) { 12058 pmu->need_cleanup = true; 12059 kvm_make_request(KVM_REQ_PMU, vcpu); 12060 } 12061 static_call(kvm_x86_sched_in)(vcpu, cpu); 12062 } 12063 12064 void kvm_arch_free_vm(struct kvm *kvm) 12065 { 12066 kfree(to_kvm_hv(kvm)->hv_pa_pg); 12067 __kvm_arch_free_vm(kvm); 12068 } 12069 12070 12071 int kvm_arch_init_vm(struct kvm *kvm, unsigned long type) 12072 { 12073 int ret; 12074 unsigned long flags; 12075 12076 if (type) 12077 return -EINVAL; 12078 12079 ret = kvm_page_track_init(kvm); 12080 if (ret) 12081 goto out; 12082 12083 ret = kvm_mmu_init_vm(kvm); 12084 if (ret) 12085 goto out_page_track; 12086 12087 INIT_HLIST_HEAD(&kvm->arch.mask_notifier_list); 12088 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head); 12089 atomic_set(&kvm->arch.noncoherent_dma_count, 0); 12090 12091 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */ 12092 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap); 12093 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */ 12094 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID, 12095 &kvm->arch.irq_sources_bitmap); 12096 12097 raw_spin_lock_init(&kvm->arch.tsc_write_lock); 12098 mutex_init(&kvm->arch.apic_map_lock); 12099 seqcount_raw_spinlock_init(&kvm->arch.pvclock_sc, &kvm->arch.tsc_write_lock); 12100 kvm->arch.kvmclock_offset = -get_kvmclock_base_ns(); 12101 12102 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags); 12103 pvclock_update_vm_gtod_copy(kvm); 12104 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags); 12105 12106 kvm->arch.default_tsc_khz = max_tsc_khz ? : tsc_khz; 12107 kvm->arch.guest_can_read_msr_platform_info = true; 12108 kvm->arch.enable_pmu = enable_pmu; 12109 12110 #if IS_ENABLED(CONFIG_HYPERV) 12111 spin_lock_init(&kvm->arch.hv_root_tdp_lock); 12112 kvm->arch.hv_root_tdp = INVALID_PAGE; 12113 #endif 12114 12115 INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn); 12116 INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn); 12117 12118 kvm_apicv_init(kvm); 12119 kvm_hv_init_vm(kvm); 12120 kvm_xen_init_vm(kvm); 12121 12122 return static_call(kvm_x86_vm_init)(kvm); 12123 12124 out_page_track: 12125 kvm_page_track_cleanup(kvm); 12126 out: 12127 return ret; 12128 } 12129 12130 int kvm_arch_post_init_vm(struct kvm *kvm) 12131 { 12132 return kvm_mmu_post_init_vm(kvm); 12133 } 12134 12135 static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu) 12136 { 12137 vcpu_load(vcpu); 12138 kvm_mmu_unload(vcpu); 12139 vcpu_put(vcpu); 12140 } 12141 12142 static void kvm_unload_vcpu_mmus(struct kvm *kvm) 12143 { 12144 unsigned long i; 12145 struct kvm_vcpu *vcpu; 12146 12147 kvm_for_each_vcpu(i, vcpu, kvm) { 12148 kvm_clear_async_pf_completion_queue(vcpu); 12149 kvm_unload_vcpu_mmu(vcpu); 12150 } 12151 } 12152 12153 void kvm_arch_sync_events(struct kvm *kvm) 12154 { 12155 cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work); 12156 cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work); 12157 kvm_free_pit(kvm); 12158 } 12159 12160 /** 12161 * __x86_set_memory_region: Setup KVM internal memory slot 12162 * 12163 * @kvm: the kvm pointer to the VM. 12164 * @id: the slot ID to setup. 12165 * @gpa: the GPA to install the slot (unused when @size == 0). 12166 * @size: the size of the slot. Set to zero to uninstall a slot. 12167 * 12168 * This function helps to setup a KVM internal memory slot. Specify 12169 * @size > 0 to install a new slot, while @size == 0 to uninstall a 12170 * slot. The return code can be one of the following: 12171 * 12172 * HVA: on success (uninstall will return a bogus HVA) 12173 * -errno: on error 12174 * 12175 * The caller should always use IS_ERR() to check the return value 12176 * before use. Note, the KVM internal memory slots are guaranteed to 12177 * remain valid and unchanged until the VM is destroyed, i.e., the 12178 * GPA->HVA translation will not change. However, the HVA is a user 12179 * address, i.e. its accessibility is not guaranteed, and must be 12180 * accessed via __copy_{to,from}_user(). 12181 */ 12182 void __user * __x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, 12183 u32 size) 12184 { 12185 int i, r; 12186 unsigned long hva, old_npages; 12187 struct kvm_memslots *slots = kvm_memslots(kvm); 12188 struct kvm_memory_slot *slot; 12189 12190 /* Called with kvm->slots_lock held. */ 12191 if (WARN_ON(id >= KVM_MEM_SLOTS_NUM)) 12192 return ERR_PTR_USR(-EINVAL); 12193 12194 slot = id_to_memslot(slots, id); 12195 if (size) { 12196 if (slot && slot->npages) 12197 return ERR_PTR_USR(-EEXIST); 12198 12199 /* 12200 * MAP_SHARED to prevent internal slot pages from being moved 12201 * by fork()/COW. 12202 */ 12203 hva = vm_mmap(NULL, 0, size, PROT_READ | PROT_WRITE, 12204 MAP_SHARED | MAP_ANONYMOUS, 0); 12205 if (IS_ERR((void *)hva)) 12206 return (void __user *)hva; 12207 } else { 12208 if (!slot || !slot->npages) 12209 return NULL; 12210 12211 old_npages = slot->npages; 12212 hva = slot->userspace_addr; 12213 } 12214 12215 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) { 12216 struct kvm_userspace_memory_region m; 12217 12218 m.slot = id | (i << 16); 12219 m.flags = 0; 12220 m.guest_phys_addr = gpa; 12221 m.userspace_addr = hva; 12222 m.memory_size = size; 12223 r = __kvm_set_memory_region(kvm, &m); 12224 if (r < 0) 12225 return ERR_PTR_USR(r); 12226 } 12227 12228 if (!size) 12229 vm_munmap(hva, old_npages * PAGE_SIZE); 12230 12231 return (void __user *)hva; 12232 } 12233 EXPORT_SYMBOL_GPL(__x86_set_memory_region); 12234 12235 void kvm_arch_pre_destroy_vm(struct kvm *kvm) 12236 { 12237 kvm_mmu_pre_destroy_vm(kvm); 12238 } 12239 12240 void kvm_arch_destroy_vm(struct kvm *kvm) 12241 { 12242 if (current->mm == kvm->mm) { 12243 /* 12244 * Free memory regions allocated on behalf of userspace, 12245 * unless the memory map has changed due to process exit 12246 * or fd copying. 12247 */ 12248 mutex_lock(&kvm->slots_lock); 12249 __x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT, 12250 0, 0); 12251 __x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT, 12252 0, 0); 12253 __x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, 0, 0); 12254 mutex_unlock(&kvm->slots_lock); 12255 } 12256 kvm_unload_vcpu_mmus(kvm); 12257 static_call_cond(kvm_x86_vm_destroy)(kvm); 12258 kvm_free_msr_filter(srcu_dereference_check(kvm->arch.msr_filter, &kvm->srcu, 1)); 12259 kvm_pic_destroy(kvm); 12260 kvm_ioapic_destroy(kvm); 12261 kvm_destroy_vcpus(kvm); 12262 kvfree(rcu_dereference_check(kvm->arch.apic_map, 1)); 12263 kfree(srcu_dereference_check(kvm->arch.pmu_event_filter, &kvm->srcu, 1)); 12264 kvm_mmu_uninit_vm(kvm); 12265 kvm_page_track_cleanup(kvm); 12266 kvm_xen_destroy_vm(kvm); 12267 kvm_hv_destroy_vm(kvm); 12268 } 12269 12270 static void memslot_rmap_free(struct kvm_memory_slot *slot) 12271 { 12272 int i; 12273 12274 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) { 12275 kvfree(slot->arch.rmap[i]); 12276 slot->arch.rmap[i] = NULL; 12277 } 12278 } 12279 12280 void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *slot) 12281 { 12282 int i; 12283 12284 memslot_rmap_free(slot); 12285 12286 for (i = 1; i < KVM_NR_PAGE_SIZES; ++i) { 12287 kvfree(slot->arch.lpage_info[i - 1]); 12288 slot->arch.lpage_info[i - 1] = NULL; 12289 } 12290 12291 kvm_page_track_free_memslot(slot); 12292 } 12293 12294 int memslot_rmap_alloc(struct kvm_memory_slot *slot, unsigned long npages) 12295 { 12296 const int sz = sizeof(*slot->arch.rmap[0]); 12297 int i; 12298 12299 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) { 12300 int level = i + 1; 12301 int lpages = __kvm_mmu_slot_lpages(slot, npages, level); 12302 12303 if (slot->arch.rmap[i]) 12304 continue; 12305 12306 slot->arch.rmap[i] = __vcalloc(lpages, sz, GFP_KERNEL_ACCOUNT); 12307 if (!slot->arch.rmap[i]) { 12308 memslot_rmap_free(slot); 12309 return -ENOMEM; 12310 } 12311 } 12312 12313 return 0; 12314 } 12315 12316 static int kvm_alloc_memslot_metadata(struct kvm *kvm, 12317 struct kvm_memory_slot *slot) 12318 { 12319 unsigned long npages = slot->npages; 12320 int i, r; 12321 12322 /* 12323 * Clear out the previous array pointers for the KVM_MR_MOVE case. The 12324 * old arrays will be freed by __kvm_set_memory_region() if installing 12325 * the new memslot is successful. 12326 */ 12327 memset(&slot->arch, 0, sizeof(slot->arch)); 12328 12329 if (kvm_memslots_have_rmaps(kvm)) { 12330 r = memslot_rmap_alloc(slot, npages); 12331 if (r) 12332 return r; 12333 } 12334 12335 for (i = 1; i < KVM_NR_PAGE_SIZES; ++i) { 12336 struct kvm_lpage_info *linfo; 12337 unsigned long ugfn; 12338 int lpages; 12339 int level = i + 1; 12340 12341 lpages = __kvm_mmu_slot_lpages(slot, npages, level); 12342 12343 linfo = __vcalloc(lpages, sizeof(*linfo), GFP_KERNEL_ACCOUNT); 12344 if (!linfo) 12345 goto out_free; 12346 12347 slot->arch.lpage_info[i - 1] = linfo; 12348 12349 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1)) 12350 linfo[0].disallow_lpage = 1; 12351 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1)) 12352 linfo[lpages - 1].disallow_lpage = 1; 12353 ugfn = slot->userspace_addr >> PAGE_SHIFT; 12354 /* 12355 * If the gfn and userspace address are not aligned wrt each 12356 * other, disable large page support for this slot. 12357 */ 12358 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1)) { 12359 unsigned long j; 12360 12361 for (j = 0; j < lpages; ++j) 12362 linfo[j].disallow_lpage = 1; 12363 } 12364 } 12365 12366 if (kvm_page_track_create_memslot(kvm, slot, npages)) 12367 goto out_free; 12368 12369 return 0; 12370 12371 out_free: 12372 memslot_rmap_free(slot); 12373 12374 for (i = 1; i < KVM_NR_PAGE_SIZES; ++i) { 12375 kvfree(slot->arch.lpage_info[i - 1]); 12376 slot->arch.lpage_info[i - 1] = NULL; 12377 } 12378 return -ENOMEM; 12379 } 12380 12381 void kvm_arch_memslots_updated(struct kvm *kvm, u64 gen) 12382 { 12383 struct kvm_vcpu *vcpu; 12384 unsigned long i; 12385 12386 /* 12387 * memslots->generation has been incremented. 12388 * mmio generation may have reached its maximum value. 12389 */ 12390 kvm_mmu_invalidate_mmio_sptes(kvm, gen); 12391 12392 /* Force re-initialization of steal_time cache */ 12393 kvm_for_each_vcpu(i, vcpu, kvm) 12394 kvm_vcpu_kick(vcpu); 12395 } 12396 12397 int kvm_arch_prepare_memory_region(struct kvm *kvm, 12398 const struct kvm_memory_slot *old, 12399 struct kvm_memory_slot *new, 12400 enum kvm_mr_change change) 12401 { 12402 if (change == KVM_MR_CREATE || change == KVM_MR_MOVE) { 12403 if ((new->base_gfn + new->npages - 1) > kvm_mmu_max_gfn()) 12404 return -EINVAL; 12405 12406 return kvm_alloc_memslot_metadata(kvm, new); 12407 } 12408 12409 if (change == KVM_MR_FLAGS_ONLY) 12410 memcpy(&new->arch, &old->arch, sizeof(old->arch)); 12411 else if (WARN_ON_ONCE(change != KVM_MR_DELETE)) 12412 return -EIO; 12413 12414 return 0; 12415 } 12416 12417 12418 static void kvm_mmu_update_cpu_dirty_logging(struct kvm *kvm, bool enable) 12419 { 12420 struct kvm_arch *ka = &kvm->arch; 12421 12422 if (!kvm_x86_ops.cpu_dirty_log_size) 12423 return; 12424 12425 if ((enable && ++ka->cpu_dirty_logging_count == 1) || 12426 (!enable && --ka->cpu_dirty_logging_count == 0)) 12427 kvm_make_all_cpus_request(kvm, KVM_REQ_UPDATE_CPU_DIRTY_LOGGING); 12428 12429 WARN_ON_ONCE(ka->cpu_dirty_logging_count < 0); 12430 } 12431 12432 static void kvm_mmu_slot_apply_flags(struct kvm *kvm, 12433 struct kvm_memory_slot *old, 12434 const struct kvm_memory_slot *new, 12435 enum kvm_mr_change change) 12436 { 12437 u32 old_flags = old ? old->flags : 0; 12438 u32 new_flags = new ? new->flags : 0; 12439 bool log_dirty_pages = new_flags & KVM_MEM_LOG_DIRTY_PAGES; 12440 12441 /* 12442 * Update CPU dirty logging if dirty logging is being toggled. This 12443 * applies to all operations. 12444 */ 12445 if ((old_flags ^ new_flags) & KVM_MEM_LOG_DIRTY_PAGES) 12446 kvm_mmu_update_cpu_dirty_logging(kvm, log_dirty_pages); 12447 12448 /* 12449 * Nothing more to do for RO slots (which can't be dirtied and can't be 12450 * made writable) or CREATE/MOVE/DELETE of a slot. 12451 * 12452 * For a memslot with dirty logging disabled: 12453 * CREATE: No dirty mappings will already exist. 12454 * MOVE/DELETE: The old mappings will already have been cleaned up by 12455 * kvm_arch_flush_shadow_memslot() 12456 * 12457 * For a memslot with dirty logging enabled: 12458 * CREATE: No shadow pages exist, thus nothing to write-protect 12459 * and no dirty bits to clear. 12460 * MOVE/DELETE: The old mappings will already have been cleaned up by 12461 * kvm_arch_flush_shadow_memslot(). 12462 */ 12463 if ((change != KVM_MR_FLAGS_ONLY) || (new_flags & KVM_MEM_READONLY)) 12464 return; 12465 12466 /* 12467 * READONLY and non-flags changes were filtered out above, and the only 12468 * other flag is LOG_DIRTY_PAGES, i.e. something is wrong if dirty 12469 * logging isn't being toggled on or off. 12470 */ 12471 if (WARN_ON_ONCE(!((old_flags ^ new_flags) & KVM_MEM_LOG_DIRTY_PAGES))) 12472 return; 12473 12474 if (!log_dirty_pages) { 12475 /* 12476 * Dirty logging tracks sptes in 4k granularity, meaning that 12477 * large sptes have to be split. If live migration succeeds, 12478 * the guest in the source machine will be destroyed and large 12479 * sptes will be created in the destination. However, if the 12480 * guest continues to run in the source machine (for example if 12481 * live migration fails), small sptes will remain around and 12482 * cause bad performance. 12483 * 12484 * Scan sptes if dirty logging has been stopped, dropping those 12485 * which can be collapsed into a single large-page spte. Later 12486 * page faults will create the large-page sptes. 12487 */ 12488 kvm_mmu_zap_collapsible_sptes(kvm, new); 12489 } else { 12490 /* 12491 * Initially-all-set does not require write protecting any page, 12492 * because they're all assumed to be dirty. 12493 */ 12494 if (kvm_dirty_log_manual_protect_and_init_set(kvm)) 12495 return; 12496 12497 if (READ_ONCE(eager_page_split)) 12498 kvm_mmu_slot_try_split_huge_pages(kvm, new, PG_LEVEL_4K); 12499 12500 if (kvm_x86_ops.cpu_dirty_log_size) { 12501 kvm_mmu_slot_leaf_clear_dirty(kvm, new); 12502 kvm_mmu_slot_remove_write_access(kvm, new, PG_LEVEL_2M); 12503 } else { 12504 kvm_mmu_slot_remove_write_access(kvm, new, PG_LEVEL_4K); 12505 } 12506 12507 /* 12508 * Unconditionally flush the TLBs after enabling dirty logging. 12509 * A flush is almost always going to be necessary (see below), 12510 * and unconditionally flushing allows the helpers to omit 12511 * the subtly complex checks when removing write access. 12512 * 12513 * Do the flush outside of mmu_lock to reduce the amount of 12514 * time mmu_lock is held. Flushing after dropping mmu_lock is 12515 * safe as KVM only needs to guarantee the slot is fully 12516 * write-protected before returning to userspace, i.e. before 12517 * userspace can consume the dirty status. 12518 * 12519 * Flushing outside of mmu_lock requires KVM to be careful when 12520 * making decisions based on writable status of an SPTE, e.g. a 12521 * !writable SPTE doesn't guarantee a CPU can't perform writes. 12522 * 12523 * Specifically, KVM also write-protects guest page tables to 12524 * monitor changes when using shadow paging, and must guarantee 12525 * no CPUs can write to those page before mmu_lock is dropped. 12526 * Because CPUs may have stale TLB entries at this point, a 12527 * !writable SPTE doesn't guarantee CPUs can't perform writes. 12528 * 12529 * KVM also allows making SPTES writable outside of mmu_lock, 12530 * e.g. to allow dirty logging without taking mmu_lock. 12531 * 12532 * To handle these scenarios, KVM uses a separate software-only 12533 * bit (MMU-writable) to track if a SPTE is !writable due to 12534 * a guest page table being write-protected (KVM clears the 12535 * MMU-writable flag when write-protecting for shadow paging). 12536 * 12537 * The use of MMU-writable is also the primary motivation for 12538 * the unconditional flush. Because KVM must guarantee that a 12539 * CPU doesn't contain stale, writable TLB entries for a 12540 * !MMU-writable SPTE, KVM must flush if it encounters any 12541 * MMU-writable SPTE regardless of whether the actual hardware 12542 * writable bit was set. I.e. KVM is almost guaranteed to need 12543 * to flush, while unconditionally flushing allows the "remove 12544 * write access" helpers to ignore MMU-writable entirely. 12545 * 12546 * See is_writable_pte() for more details (the case involving 12547 * access-tracked SPTEs is particularly relevant). 12548 */ 12549 kvm_arch_flush_remote_tlbs_memslot(kvm, new); 12550 } 12551 } 12552 12553 void kvm_arch_commit_memory_region(struct kvm *kvm, 12554 struct kvm_memory_slot *old, 12555 const struct kvm_memory_slot *new, 12556 enum kvm_mr_change change) 12557 { 12558 if (!kvm->arch.n_requested_mmu_pages && 12559 (change == KVM_MR_CREATE || change == KVM_MR_DELETE)) { 12560 unsigned long nr_mmu_pages; 12561 12562 nr_mmu_pages = kvm->nr_memslot_pages / KVM_MEMSLOT_PAGES_TO_MMU_PAGES_RATIO; 12563 nr_mmu_pages = max(nr_mmu_pages, KVM_MIN_ALLOC_MMU_PAGES); 12564 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages); 12565 } 12566 12567 kvm_mmu_slot_apply_flags(kvm, old, new, change); 12568 12569 /* Free the arrays associated with the old memslot. */ 12570 if (change == KVM_MR_MOVE) 12571 kvm_arch_free_memslot(kvm, old); 12572 } 12573 12574 void kvm_arch_flush_shadow_all(struct kvm *kvm) 12575 { 12576 kvm_mmu_zap_all(kvm); 12577 } 12578 12579 void kvm_arch_flush_shadow_memslot(struct kvm *kvm, 12580 struct kvm_memory_slot *slot) 12581 { 12582 kvm_page_track_flush_slot(kvm, slot); 12583 } 12584 12585 static inline bool kvm_guest_apic_has_interrupt(struct kvm_vcpu *vcpu) 12586 { 12587 return (is_guest_mode(vcpu) && 12588 static_call(kvm_x86_guest_apic_has_interrupt)(vcpu)); 12589 } 12590 12591 static inline bool kvm_vcpu_has_events(struct kvm_vcpu *vcpu) 12592 { 12593 if (!list_empty_careful(&vcpu->async_pf.done)) 12594 return true; 12595 12596 if (kvm_apic_has_events(vcpu)) 12597 return true; 12598 12599 if (vcpu->arch.pv.pv_unhalted) 12600 return true; 12601 12602 if (vcpu->arch.exception.pending) 12603 return true; 12604 12605 if (kvm_test_request(KVM_REQ_NMI, vcpu) || 12606 (vcpu->arch.nmi_pending && 12607 static_call(kvm_x86_nmi_allowed)(vcpu, false))) 12608 return true; 12609 12610 if (kvm_test_request(KVM_REQ_SMI, vcpu) || 12611 (vcpu->arch.smi_pending && 12612 static_call(kvm_x86_smi_allowed)(vcpu, false))) 12613 return true; 12614 12615 if (kvm_arch_interrupt_allowed(vcpu) && 12616 (kvm_cpu_has_interrupt(vcpu) || 12617 kvm_guest_apic_has_interrupt(vcpu))) 12618 return true; 12619 12620 if (kvm_hv_has_stimer_pending(vcpu)) 12621 return true; 12622 12623 if (is_guest_mode(vcpu) && 12624 kvm_x86_ops.nested_ops->hv_timer_pending && 12625 kvm_x86_ops.nested_ops->hv_timer_pending(vcpu)) 12626 return true; 12627 12628 if (kvm_xen_has_pending_events(vcpu)) 12629 return true; 12630 12631 if (kvm_test_request(KVM_REQ_TRIPLE_FAULT, vcpu)) 12632 return true; 12633 12634 return false; 12635 } 12636 12637 int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu) 12638 { 12639 return kvm_vcpu_running(vcpu) || kvm_vcpu_has_events(vcpu); 12640 } 12641 12642 bool kvm_arch_dy_has_pending_interrupt(struct kvm_vcpu *vcpu) 12643 { 12644 if (kvm_vcpu_apicv_active(vcpu) && 12645 static_call(kvm_x86_dy_apicv_has_pending_interrupt)(vcpu)) 12646 return true; 12647 12648 return false; 12649 } 12650 12651 bool kvm_arch_dy_runnable(struct kvm_vcpu *vcpu) 12652 { 12653 if (READ_ONCE(vcpu->arch.pv.pv_unhalted)) 12654 return true; 12655 12656 if (kvm_test_request(KVM_REQ_NMI, vcpu) || 12657 kvm_test_request(KVM_REQ_SMI, vcpu) || 12658 kvm_test_request(KVM_REQ_EVENT, vcpu)) 12659 return true; 12660 12661 return kvm_arch_dy_has_pending_interrupt(vcpu); 12662 } 12663 12664 bool kvm_arch_vcpu_in_kernel(struct kvm_vcpu *vcpu) 12665 { 12666 if (vcpu->arch.guest_state_protected) 12667 return true; 12668 12669 return vcpu->arch.preempted_in_kernel; 12670 } 12671 12672 unsigned long kvm_arch_vcpu_get_ip(struct kvm_vcpu *vcpu) 12673 { 12674 return kvm_rip_read(vcpu); 12675 } 12676 12677 int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu) 12678 { 12679 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE; 12680 } 12681 12682 int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu) 12683 { 12684 return static_call(kvm_x86_interrupt_allowed)(vcpu, false); 12685 } 12686 12687 unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu) 12688 { 12689 /* Can't read the RIP when guest state is protected, just return 0 */ 12690 if (vcpu->arch.guest_state_protected) 12691 return 0; 12692 12693 if (is_64_bit_mode(vcpu)) 12694 return kvm_rip_read(vcpu); 12695 return (u32)(get_segment_base(vcpu, VCPU_SREG_CS) + 12696 kvm_rip_read(vcpu)); 12697 } 12698 EXPORT_SYMBOL_GPL(kvm_get_linear_rip); 12699 12700 bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip) 12701 { 12702 return kvm_get_linear_rip(vcpu) == linear_rip; 12703 } 12704 EXPORT_SYMBOL_GPL(kvm_is_linear_rip); 12705 12706 unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu) 12707 { 12708 unsigned long rflags; 12709 12710 rflags = static_call(kvm_x86_get_rflags)(vcpu); 12711 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) 12712 rflags &= ~X86_EFLAGS_TF; 12713 return rflags; 12714 } 12715 EXPORT_SYMBOL_GPL(kvm_get_rflags); 12716 12717 static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags) 12718 { 12719 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP && 12720 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip)) 12721 rflags |= X86_EFLAGS_TF; 12722 static_call(kvm_x86_set_rflags)(vcpu, rflags); 12723 } 12724 12725 void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags) 12726 { 12727 __kvm_set_rflags(vcpu, rflags); 12728 kvm_make_request(KVM_REQ_EVENT, vcpu); 12729 } 12730 EXPORT_SYMBOL_GPL(kvm_set_rflags); 12731 12732 static inline u32 kvm_async_pf_hash_fn(gfn_t gfn) 12733 { 12734 BUILD_BUG_ON(!is_power_of_2(ASYNC_PF_PER_VCPU)); 12735 12736 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU)); 12737 } 12738 12739 static inline u32 kvm_async_pf_next_probe(u32 key) 12740 { 12741 return (key + 1) & (ASYNC_PF_PER_VCPU - 1); 12742 } 12743 12744 static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn) 12745 { 12746 u32 key = kvm_async_pf_hash_fn(gfn); 12747 12748 while (vcpu->arch.apf.gfns[key] != ~0) 12749 key = kvm_async_pf_next_probe(key); 12750 12751 vcpu->arch.apf.gfns[key] = gfn; 12752 } 12753 12754 static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn) 12755 { 12756 int i; 12757 u32 key = kvm_async_pf_hash_fn(gfn); 12758 12759 for (i = 0; i < ASYNC_PF_PER_VCPU && 12760 (vcpu->arch.apf.gfns[key] != gfn && 12761 vcpu->arch.apf.gfns[key] != ~0); i++) 12762 key = kvm_async_pf_next_probe(key); 12763 12764 return key; 12765 } 12766 12767 bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn) 12768 { 12769 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn; 12770 } 12771 12772 static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn) 12773 { 12774 u32 i, j, k; 12775 12776 i = j = kvm_async_pf_gfn_slot(vcpu, gfn); 12777 12778 if (WARN_ON_ONCE(vcpu->arch.apf.gfns[i] != gfn)) 12779 return; 12780 12781 while (true) { 12782 vcpu->arch.apf.gfns[i] = ~0; 12783 do { 12784 j = kvm_async_pf_next_probe(j); 12785 if (vcpu->arch.apf.gfns[j] == ~0) 12786 return; 12787 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]); 12788 /* 12789 * k lies cyclically in ]i,j] 12790 * | i.k.j | 12791 * |....j i.k.| or |.k..j i...| 12792 */ 12793 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j)); 12794 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j]; 12795 i = j; 12796 } 12797 } 12798 12799 static inline int apf_put_user_notpresent(struct kvm_vcpu *vcpu) 12800 { 12801 u32 reason = KVM_PV_REASON_PAGE_NOT_PRESENT; 12802 12803 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &reason, 12804 sizeof(reason)); 12805 } 12806 12807 static inline int apf_put_user_ready(struct kvm_vcpu *vcpu, u32 token) 12808 { 12809 unsigned int offset = offsetof(struct kvm_vcpu_pv_apf_data, token); 12810 12811 return kvm_write_guest_offset_cached(vcpu->kvm, &vcpu->arch.apf.data, 12812 &token, offset, sizeof(token)); 12813 } 12814 12815 static inline bool apf_pageready_slot_free(struct kvm_vcpu *vcpu) 12816 { 12817 unsigned int offset = offsetof(struct kvm_vcpu_pv_apf_data, token); 12818 u32 val; 12819 12820 if (kvm_read_guest_offset_cached(vcpu->kvm, &vcpu->arch.apf.data, 12821 &val, offset, sizeof(val))) 12822 return false; 12823 12824 return !val; 12825 } 12826 12827 static bool kvm_can_deliver_async_pf(struct kvm_vcpu *vcpu) 12828 { 12829 12830 if (!kvm_pv_async_pf_enabled(vcpu)) 12831 return false; 12832 12833 if (vcpu->arch.apf.send_user_only && 12834 static_call(kvm_x86_get_cpl)(vcpu) == 0) 12835 return false; 12836 12837 if (is_guest_mode(vcpu)) { 12838 /* 12839 * L1 needs to opt into the special #PF vmexits that are 12840 * used to deliver async page faults. 12841 */ 12842 return vcpu->arch.apf.delivery_as_pf_vmexit; 12843 } else { 12844 /* 12845 * Play it safe in case the guest temporarily disables paging. 12846 * The real mode IDT in particular is unlikely to have a #PF 12847 * exception setup. 12848 */ 12849 return is_paging(vcpu); 12850 } 12851 } 12852 12853 bool kvm_can_do_async_pf(struct kvm_vcpu *vcpu) 12854 { 12855 if (unlikely(!lapic_in_kernel(vcpu) || 12856 kvm_event_needs_reinjection(vcpu) || 12857 vcpu->arch.exception.pending)) 12858 return false; 12859 12860 if (kvm_hlt_in_guest(vcpu->kvm) && !kvm_can_deliver_async_pf(vcpu)) 12861 return false; 12862 12863 /* 12864 * If interrupts are off we cannot even use an artificial 12865 * halt state. 12866 */ 12867 return kvm_arch_interrupt_allowed(vcpu); 12868 } 12869 12870 bool kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu, 12871 struct kvm_async_pf *work) 12872 { 12873 struct x86_exception fault; 12874 12875 trace_kvm_async_pf_not_present(work->arch.token, work->cr2_or_gpa); 12876 kvm_add_async_pf_gfn(vcpu, work->arch.gfn); 12877 12878 if (kvm_can_deliver_async_pf(vcpu) && 12879 !apf_put_user_notpresent(vcpu)) { 12880 fault.vector = PF_VECTOR; 12881 fault.error_code_valid = true; 12882 fault.error_code = 0; 12883 fault.nested_page_fault = false; 12884 fault.address = work->arch.token; 12885 fault.async_page_fault = true; 12886 kvm_inject_page_fault(vcpu, &fault); 12887 return true; 12888 } else { 12889 /* 12890 * It is not possible to deliver a paravirtualized asynchronous 12891 * page fault, but putting the guest in an artificial halt state 12892 * can be beneficial nevertheless: if an interrupt arrives, we 12893 * can deliver it timely and perhaps the guest will schedule 12894 * another process. When the instruction that triggered a page 12895 * fault is retried, hopefully the page will be ready in the host. 12896 */ 12897 kvm_make_request(KVM_REQ_APF_HALT, vcpu); 12898 return false; 12899 } 12900 } 12901 12902 void kvm_arch_async_page_present(struct kvm_vcpu *vcpu, 12903 struct kvm_async_pf *work) 12904 { 12905 struct kvm_lapic_irq irq = { 12906 .delivery_mode = APIC_DM_FIXED, 12907 .vector = vcpu->arch.apf.vec 12908 }; 12909 12910 if (work->wakeup_all) 12911 work->arch.token = ~0; /* broadcast wakeup */ 12912 else 12913 kvm_del_async_pf_gfn(vcpu, work->arch.gfn); 12914 trace_kvm_async_pf_ready(work->arch.token, work->cr2_or_gpa); 12915 12916 if ((work->wakeup_all || work->notpresent_injected) && 12917 kvm_pv_async_pf_enabled(vcpu) && 12918 !apf_put_user_ready(vcpu, work->arch.token)) { 12919 vcpu->arch.apf.pageready_pending = true; 12920 kvm_apic_set_irq(vcpu, &irq, NULL); 12921 } 12922 12923 vcpu->arch.apf.halted = false; 12924 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; 12925 } 12926 12927 void kvm_arch_async_page_present_queued(struct kvm_vcpu *vcpu) 12928 { 12929 kvm_make_request(KVM_REQ_APF_READY, vcpu); 12930 if (!vcpu->arch.apf.pageready_pending) 12931 kvm_vcpu_kick(vcpu); 12932 } 12933 12934 bool kvm_arch_can_dequeue_async_page_present(struct kvm_vcpu *vcpu) 12935 { 12936 if (!kvm_pv_async_pf_enabled(vcpu)) 12937 return true; 12938 else 12939 return kvm_lapic_enabled(vcpu) && apf_pageready_slot_free(vcpu); 12940 } 12941 12942 void kvm_arch_start_assignment(struct kvm *kvm) 12943 { 12944 if (atomic_inc_return(&kvm->arch.assigned_device_count) == 1) 12945 static_call_cond(kvm_x86_pi_start_assignment)(kvm); 12946 } 12947 EXPORT_SYMBOL_GPL(kvm_arch_start_assignment); 12948 12949 void kvm_arch_end_assignment(struct kvm *kvm) 12950 { 12951 atomic_dec(&kvm->arch.assigned_device_count); 12952 } 12953 EXPORT_SYMBOL_GPL(kvm_arch_end_assignment); 12954 12955 bool noinstr kvm_arch_has_assigned_device(struct kvm *kvm) 12956 { 12957 return arch_atomic_read(&kvm->arch.assigned_device_count); 12958 } 12959 EXPORT_SYMBOL_GPL(kvm_arch_has_assigned_device); 12960 12961 void kvm_arch_register_noncoherent_dma(struct kvm *kvm) 12962 { 12963 atomic_inc(&kvm->arch.noncoherent_dma_count); 12964 } 12965 EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma); 12966 12967 void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm) 12968 { 12969 atomic_dec(&kvm->arch.noncoherent_dma_count); 12970 } 12971 EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma); 12972 12973 bool kvm_arch_has_noncoherent_dma(struct kvm *kvm) 12974 { 12975 return atomic_read(&kvm->arch.noncoherent_dma_count); 12976 } 12977 EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma); 12978 12979 bool kvm_arch_has_irq_bypass(void) 12980 { 12981 return true; 12982 } 12983 12984 int kvm_arch_irq_bypass_add_producer(struct irq_bypass_consumer *cons, 12985 struct irq_bypass_producer *prod) 12986 { 12987 struct kvm_kernel_irqfd *irqfd = 12988 container_of(cons, struct kvm_kernel_irqfd, consumer); 12989 int ret; 12990 12991 irqfd->producer = prod; 12992 kvm_arch_start_assignment(irqfd->kvm); 12993 ret = static_call(kvm_x86_pi_update_irte)(irqfd->kvm, 12994 prod->irq, irqfd->gsi, 1); 12995 12996 if (ret) 12997 kvm_arch_end_assignment(irqfd->kvm); 12998 12999 return ret; 13000 } 13001 13002 void kvm_arch_irq_bypass_del_producer(struct irq_bypass_consumer *cons, 13003 struct irq_bypass_producer *prod) 13004 { 13005 int ret; 13006 struct kvm_kernel_irqfd *irqfd = 13007 container_of(cons, struct kvm_kernel_irqfd, consumer); 13008 13009 WARN_ON(irqfd->producer != prod); 13010 irqfd->producer = NULL; 13011 13012 /* 13013 * When producer of consumer is unregistered, we change back to 13014 * remapped mode, so we can re-use the current implementation 13015 * when the irq is masked/disabled or the consumer side (KVM 13016 * int this case doesn't want to receive the interrupts. 13017 */ 13018 ret = static_call(kvm_x86_pi_update_irte)(irqfd->kvm, prod->irq, irqfd->gsi, 0); 13019 if (ret) 13020 printk(KERN_INFO "irq bypass consumer (token %p) unregistration" 13021 " fails: %d\n", irqfd->consumer.token, ret); 13022 13023 kvm_arch_end_assignment(irqfd->kvm); 13024 } 13025 13026 int kvm_arch_update_irqfd_routing(struct kvm *kvm, unsigned int host_irq, 13027 uint32_t guest_irq, bool set) 13028 { 13029 return static_call(kvm_x86_pi_update_irte)(kvm, host_irq, guest_irq, set); 13030 } 13031 13032 bool kvm_arch_irqfd_route_changed(struct kvm_kernel_irq_routing_entry *old, 13033 struct kvm_kernel_irq_routing_entry *new) 13034 { 13035 if (new->type != KVM_IRQ_ROUTING_MSI) 13036 return true; 13037 13038 return !!memcmp(&old->msi, &new->msi, sizeof(new->msi)); 13039 } 13040 13041 bool kvm_vector_hashing_enabled(void) 13042 { 13043 return vector_hashing; 13044 } 13045 13046 bool kvm_arch_no_poll(struct kvm_vcpu *vcpu) 13047 { 13048 return (vcpu->arch.msr_kvm_poll_control & 1) == 0; 13049 } 13050 EXPORT_SYMBOL_GPL(kvm_arch_no_poll); 13051 13052 13053 int kvm_spec_ctrl_test_value(u64 value) 13054 { 13055 /* 13056 * test that setting IA32_SPEC_CTRL to given value 13057 * is allowed by the host processor 13058 */ 13059 13060 u64 saved_value; 13061 unsigned long flags; 13062 int ret = 0; 13063 13064 local_irq_save(flags); 13065 13066 if (rdmsrl_safe(MSR_IA32_SPEC_CTRL, &saved_value)) 13067 ret = 1; 13068 else if (wrmsrl_safe(MSR_IA32_SPEC_CTRL, value)) 13069 ret = 1; 13070 else 13071 wrmsrl(MSR_IA32_SPEC_CTRL, saved_value); 13072 13073 local_irq_restore(flags); 13074 13075 return ret; 13076 } 13077 EXPORT_SYMBOL_GPL(kvm_spec_ctrl_test_value); 13078 13079 void kvm_fixup_and_inject_pf_error(struct kvm_vcpu *vcpu, gva_t gva, u16 error_code) 13080 { 13081 struct kvm_mmu *mmu = vcpu->arch.walk_mmu; 13082 struct x86_exception fault; 13083 u64 access = error_code & 13084 (PFERR_WRITE_MASK | PFERR_FETCH_MASK | PFERR_USER_MASK); 13085 13086 if (!(error_code & PFERR_PRESENT_MASK) || 13087 mmu->gva_to_gpa(vcpu, mmu, gva, access, &fault) != INVALID_GPA) { 13088 /* 13089 * If vcpu->arch.walk_mmu->gva_to_gpa succeeded, the page 13090 * tables probably do not match the TLB. Just proceed 13091 * with the error code that the processor gave. 13092 */ 13093 fault.vector = PF_VECTOR; 13094 fault.error_code_valid = true; 13095 fault.error_code = error_code; 13096 fault.nested_page_fault = false; 13097 fault.address = gva; 13098 fault.async_page_fault = false; 13099 } 13100 vcpu->arch.walk_mmu->inject_page_fault(vcpu, &fault); 13101 } 13102 EXPORT_SYMBOL_GPL(kvm_fixup_and_inject_pf_error); 13103 13104 /* 13105 * Handles kvm_read/write_guest_virt*() result and either injects #PF or returns 13106 * KVM_EXIT_INTERNAL_ERROR for cases not currently handled by KVM. Return value 13107 * indicates whether exit to userspace is needed. 13108 */ 13109 int kvm_handle_memory_failure(struct kvm_vcpu *vcpu, int r, 13110 struct x86_exception *e) 13111 { 13112 if (r == X86EMUL_PROPAGATE_FAULT) { 13113 kvm_inject_emulated_page_fault(vcpu, e); 13114 return 1; 13115 } 13116 13117 /* 13118 * In case kvm_read/write_guest_virt*() failed with X86EMUL_IO_NEEDED 13119 * while handling a VMX instruction KVM could've handled the request 13120 * correctly by exiting to userspace and performing I/O but there 13121 * doesn't seem to be a real use-case behind such requests, just return 13122 * KVM_EXIT_INTERNAL_ERROR for now. 13123 */ 13124 kvm_prepare_emulation_failure_exit(vcpu); 13125 13126 return 0; 13127 } 13128 EXPORT_SYMBOL_GPL(kvm_handle_memory_failure); 13129 13130 int kvm_handle_invpcid(struct kvm_vcpu *vcpu, unsigned long type, gva_t gva) 13131 { 13132 bool pcid_enabled; 13133 struct x86_exception e; 13134 struct { 13135 u64 pcid; 13136 u64 gla; 13137 } operand; 13138 int r; 13139 13140 r = kvm_read_guest_virt(vcpu, gva, &operand, sizeof(operand), &e); 13141 if (r != X86EMUL_CONTINUE) 13142 return kvm_handle_memory_failure(vcpu, r, &e); 13143 13144 if (operand.pcid >> 12 != 0) { 13145 kvm_inject_gp(vcpu, 0); 13146 return 1; 13147 } 13148 13149 pcid_enabled = kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE); 13150 13151 switch (type) { 13152 case INVPCID_TYPE_INDIV_ADDR: 13153 if ((!pcid_enabled && (operand.pcid != 0)) || 13154 is_noncanonical_address(operand.gla, vcpu)) { 13155 kvm_inject_gp(vcpu, 0); 13156 return 1; 13157 } 13158 kvm_mmu_invpcid_gva(vcpu, operand.gla, operand.pcid); 13159 return kvm_skip_emulated_instruction(vcpu); 13160 13161 case INVPCID_TYPE_SINGLE_CTXT: 13162 if (!pcid_enabled && (operand.pcid != 0)) { 13163 kvm_inject_gp(vcpu, 0); 13164 return 1; 13165 } 13166 13167 kvm_invalidate_pcid(vcpu, operand.pcid); 13168 return kvm_skip_emulated_instruction(vcpu); 13169 13170 case INVPCID_TYPE_ALL_NON_GLOBAL: 13171 /* 13172 * Currently, KVM doesn't mark global entries in the shadow 13173 * page tables, so a non-global flush just degenerates to a 13174 * global flush. If needed, we could optimize this later by 13175 * keeping track of global entries in shadow page tables. 13176 */ 13177 13178 fallthrough; 13179 case INVPCID_TYPE_ALL_INCL_GLOBAL: 13180 kvm_make_request(KVM_REQ_TLB_FLUSH_GUEST, vcpu); 13181 return kvm_skip_emulated_instruction(vcpu); 13182 13183 default: 13184 kvm_inject_gp(vcpu, 0); 13185 return 1; 13186 } 13187 } 13188 EXPORT_SYMBOL_GPL(kvm_handle_invpcid); 13189 13190 static int complete_sev_es_emulated_mmio(struct kvm_vcpu *vcpu) 13191 { 13192 struct kvm_run *run = vcpu->run; 13193 struct kvm_mmio_fragment *frag; 13194 unsigned int len; 13195 13196 BUG_ON(!vcpu->mmio_needed); 13197 13198 /* Complete previous fragment */ 13199 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment]; 13200 len = min(8u, frag->len); 13201 if (!vcpu->mmio_is_write) 13202 memcpy(frag->data, run->mmio.data, len); 13203 13204 if (frag->len <= 8) { 13205 /* Switch to the next fragment. */ 13206 frag++; 13207 vcpu->mmio_cur_fragment++; 13208 } else { 13209 /* Go forward to the next mmio piece. */ 13210 frag->data += len; 13211 frag->gpa += len; 13212 frag->len -= len; 13213 } 13214 13215 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) { 13216 vcpu->mmio_needed = 0; 13217 13218 // VMG change, at this point, we're always done 13219 // RIP has already been advanced 13220 return 1; 13221 } 13222 13223 // More MMIO is needed 13224 run->mmio.phys_addr = frag->gpa; 13225 run->mmio.len = min(8u, frag->len); 13226 run->mmio.is_write = vcpu->mmio_is_write; 13227 if (run->mmio.is_write) 13228 memcpy(run->mmio.data, frag->data, min(8u, frag->len)); 13229 run->exit_reason = KVM_EXIT_MMIO; 13230 13231 vcpu->arch.complete_userspace_io = complete_sev_es_emulated_mmio; 13232 13233 return 0; 13234 } 13235 13236 int kvm_sev_es_mmio_write(struct kvm_vcpu *vcpu, gpa_t gpa, unsigned int bytes, 13237 void *data) 13238 { 13239 int handled; 13240 struct kvm_mmio_fragment *frag; 13241 13242 if (!data) 13243 return -EINVAL; 13244 13245 handled = write_emultor.read_write_mmio(vcpu, gpa, bytes, data); 13246 if (handled == bytes) 13247 return 1; 13248 13249 bytes -= handled; 13250 gpa += handled; 13251 data += handled; 13252 13253 /*TODO: Check if need to increment number of frags */ 13254 frag = vcpu->mmio_fragments; 13255 vcpu->mmio_nr_fragments = 1; 13256 frag->len = bytes; 13257 frag->gpa = gpa; 13258 frag->data = data; 13259 13260 vcpu->mmio_needed = 1; 13261 vcpu->mmio_cur_fragment = 0; 13262 13263 vcpu->run->mmio.phys_addr = gpa; 13264 vcpu->run->mmio.len = min(8u, frag->len); 13265 vcpu->run->mmio.is_write = 1; 13266 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len)); 13267 vcpu->run->exit_reason = KVM_EXIT_MMIO; 13268 13269 vcpu->arch.complete_userspace_io = complete_sev_es_emulated_mmio; 13270 13271 return 0; 13272 } 13273 EXPORT_SYMBOL_GPL(kvm_sev_es_mmio_write); 13274 13275 int kvm_sev_es_mmio_read(struct kvm_vcpu *vcpu, gpa_t gpa, unsigned int bytes, 13276 void *data) 13277 { 13278 int handled; 13279 struct kvm_mmio_fragment *frag; 13280 13281 if (!data) 13282 return -EINVAL; 13283 13284 handled = read_emultor.read_write_mmio(vcpu, gpa, bytes, data); 13285 if (handled == bytes) 13286 return 1; 13287 13288 bytes -= handled; 13289 gpa += handled; 13290 data += handled; 13291 13292 /*TODO: Check if need to increment number of frags */ 13293 frag = vcpu->mmio_fragments; 13294 vcpu->mmio_nr_fragments = 1; 13295 frag->len = bytes; 13296 frag->gpa = gpa; 13297 frag->data = data; 13298 13299 vcpu->mmio_needed = 1; 13300 vcpu->mmio_cur_fragment = 0; 13301 13302 vcpu->run->mmio.phys_addr = gpa; 13303 vcpu->run->mmio.len = min(8u, frag->len); 13304 vcpu->run->mmio.is_write = 0; 13305 vcpu->run->exit_reason = KVM_EXIT_MMIO; 13306 13307 vcpu->arch.complete_userspace_io = complete_sev_es_emulated_mmio; 13308 13309 return 0; 13310 } 13311 EXPORT_SYMBOL_GPL(kvm_sev_es_mmio_read); 13312 13313 static void advance_sev_es_emulated_pio(struct kvm_vcpu *vcpu, unsigned count, int size) 13314 { 13315 vcpu->arch.sev_pio_count -= count; 13316 vcpu->arch.sev_pio_data += count * size; 13317 } 13318 13319 static int kvm_sev_es_outs(struct kvm_vcpu *vcpu, unsigned int size, 13320 unsigned int port); 13321 13322 static int complete_sev_es_emulated_outs(struct kvm_vcpu *vcpu) 13323 { 13324 int size = vcpu->arch.pio.size; 13325 int port = vcpu->arch.pio.port; 13326 13327 vcpu->arch.pio.count = 0; 13328 if (vcpu->arch.sev_pio_count) 13329 return kvm_sev_es_outs(vcpu, size, port); 13330 return 1; 13331 } 13332 13333 static int kvm_sev_es_outs(struct kvm_vcpu *vcpu, unsigned int size, 13334 unsigned int port) 13335 { 13336 for (;;) { 13337 unsigned int count = 13338 min_t(unsigned int, PAGE_SIZE / size, vcpu->arch.sev_pio_count); 13339 int ret = emulator_pio_out(vcpu, size, port, vcpu->arch.sev_pio_data, count); 13340 13341 /* memcpy done already by emulator_pio_out. */ 13342 advance_sev_es_emulated_pio(vcpu, count, size); 13343 if (!ret) 13344 break; 13345 13346 /* Emulation done by the kernel. */ 13347 if (!vcpu->arch.sev_pio_count) 13348 return 1; 13349 } 13350 13351 vcpu->arch.complete_userspace_io = complete_sev_es_emulated_outs; 13352 return 0; 13353 } 13354 13355 static int kvm_sev_es_ins(struct kvm_vcpu *vcpu, unsigned int size, 13356 unsigned int port); 13357 13358 static int complete_sev_es_emulated_ins(struct kvm_vcpu *vcpu) 13359 { 13360 unsigned count = vcpu->arch.pio.count; 13361 int size = vcpu->arch.pio.size; 13362 int port = vcpu->arch.pio.port; 13363 13364 complete_emulator_pio_in(vcpu, vcpu->arch.sev_pio_data); 13365 advance_sev_es_emulated_pio(vcpu, count, size); 13366 if (vcpu->arch.sev_pio_count) 13367 return kvm_sev_es_ins(vcpu, size, port); 13368 return 1; 13369 } 13370 13371 static int kvm_sev_es_ins(struct kvm_vcpu *vcpu, unsigned int size, 13372 unsigned int port) 13373 { 13374 for (;;) { 13375 unsigned int count = 13376 min_t(unsigned int, PAGE_SIZE / size, vcpu->arch.sev_pio_count); 13377 if (!emulator_pio_in(vcpu, size, port, vcpu->arch.sev_pio_data, count)) 13378 break; 13379 13380 /* Emulation done by the kernel. */ 13381 advance_sev_es_emulated_pio(vcpu, count, size); 13382 if (!vcpu->arch.sev_pio_count) 13383 return 1; 13384 } 13385 13386 vcpu->arch.complete_userspace_io = complete_sev_es_emulated_ins; 13387 return 0; 13388 } 13389 13390 int kvm_sev_es_string_io(struct kvm_vcpu *vcpu, unsigned int size, 13391 unsigned int port, void *data, unsigned int count, 13392 int in) 13393 { 13394 vcpu->arch.sev_pio_data = data; 13395 vcpu->arch.sev_pio_count = count; 13396 return in ? kvm_sev_es_ins(vcpu, size, port) 13397 : kvm_sev_es_outs(vcpu, size, port); 13398 } 13399 EXPORT_SYMBOL_GPL(kvm_sev_es_string_io); 13400 13401 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_entry); 13402 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit); 13403 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_fast_mmio); 13404 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq); 13405 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault); 13406 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr); 13407 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr); 13408 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun); 13409 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit); 13410 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject); 13411 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit); 13412 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmenter_failed); 13413 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga); 13414 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit); 13415 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts); 13416 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset); 13417 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_ple_window_update); 13418 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pml_full); 13419 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pi_irte_update); 13420 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_unaccelerated_access); 13421 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_incomplete_ipi); 13422 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_ga_log); 13423 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_kick_vcpu_slowpath); 13424 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_doorbell); 13425 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_apicv_accept_irq); 13426 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_vmgexit_enter); 13427 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_vmgexit_exit); 13428 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_vmgexit_msr_protocol_enter); 13429 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_vmgexit_msr_protocol_exit); 13430 13431 static int __init kvm_x86_init(void) 13432 { 13433 kvm_mmu_x86_module_init(); 13434 return 0; 13435 } 13436 module_init(kvm_x86_init); 13437 13438 static void __exit kvm_x86_exit(void) 13439 { 13440 /* 13441 * If module_init() is implemented, module_exit() must also be 13442 * implemented to allow module unload. 13443 */ 13444 } 13445 module_exit(kvm_x86_exit); 13446