xref: /linux/arch/x86/kvm/x86.c (revision d163d60258c755845cbc9cfe0e45fca71e649488)
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * Kernel-based Virtual Machine driver for Linux
4  *
5  * derived from drivers/kvm/kvm_main.c
6  *
7  * Copyright (C) 2006 Qumranet, Inc.
8  * Copyright (C) 2008 Qumranet, Inc.
9  * Copyright IBM Corporation, 2008
10  * Copyright 2010 Red Hat, Inc. and/or its affiliates.
11  *
12  * Authors:
13  *   Avi Kivity   <avi@qumranet.com>
14  *   Yaniv Kamay  <yaniv@qumranet.com>
15  *   Amit Shah    <amit.shah@qumranet.com>
16  *   Ben-Ami Yassour <benami@il.ibm.com>
17  */
18 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
19 
20 #include <linux/kvm_host.h>
21 #include "irq.h"
22 #include "ioapic.h"
23 #include "mmu.h"
24 #include "i8254.h"
25 #include "tss.h"
26 #include "kvm_cache_regs.h"
27 #include "kvm_emulate.h"
28 #include "mmu/page_track.h"
29 #include "x86.h"
30 #include "cpuid.h"
31 #include "pmu.h"
32 #include "hyperv.h"
33 #include "lapic.h"
34 #include "xen.h"
35 #include "smm.h"
36 
37 #include <linux/clocksource.h>
38 #include <linux/interrupt.h>
39 #include <linux/kvm.h>
40 #include <linux/fs.h>
41 #include <linux/vmalloc.h>
42 #include <linux/export.h>
43 #include <linux/moduleparam.h>
44 #include <linux/mman.h>
45 #include <linux/highmem.h>
46 #include <linux/iommu.h>
47 #include <linux/cpufreq.h>
48 #include <linux/user-return-notifier.h>
49 #include <linux/srcu.h>
50 #include <linux/slab.h>
51 #include <linux/perf_event.h>
52 #include <linux/uaccess.h>
53 #include <linux/hash.h>
54 #include <linux/pci.h>
55 #include <linux/timekeeper_internal.h>
56 #include <linux/pvclock_gtod.h>
57 #include <linux/kvm_irqfd.h>
58 #include <linux/irqbypass.h>
59 #include <linux/sched/stat.h>
60 #include <linux/sched/isolation.h>
61 #include <linux/mem_encrypt.h>
62 #include <linux/entry-kvm.h>
63 #include <linux/suspend.h>
64 #include <linux/smp.h>
65 
66 #include <trace/events/ipi.h>
67 #include <trace/events/kvm.h>
68 
69 #include <asm/debugreg.h>
70 #include <asm/msr.h>
71 #include <asm/desc.h>
72 #include <asm/mce.h>
73 #include <asm/pkru.h>
74 #include <linux/kernel_stat.h>
75 #include <asm/fpu/api.h>
76 #include <asm/fpu/xcr.h>
77 #include <asm/fpu/xstate.h>
78 #include <asm/pvclock.h>
79 #include <asm/div64.h>
80 #include <asm/irq_remapping.h>
81 #include <asm/mshyperv.h>
82 #include <asm/hypervisor.h>
83 #include <asm/tlbflush.h>
84 #include <asm/intel_pt.h>
85 #include <asm/emulate_prefix.h>
86 #include <asm/sgx.h>
87 #include <clocksource/hyperv_timer.h>
88 
89 #define CREATE_TRACE_POINTS
90 #include "trace.h"
91 
92 #define MAX_IO_MSRS 256
93 #define KVM_MAX_MCE_BANKS 32
94 
95 /*
96  * Note, kvm_caps fields should *never* have default values, all fields must be
97  * recomputed from scratch during vendor module load, e.g. to account for a
98  * vendor module being reloaded with different module parameters.
99  */
100 struct kvm_caps kvm_caps __read_mostly;
101 EXPORT_SYMBOL_GPL(kvm_caps);
102 
103 #define  ERR_PTR_USR(e)  ((void __user *)ERR_PTR(e))
104 
105 #define emul_to_vcpu(ctxt) \
106 	((struct kvm_vcpu *)(ctxt)->vcpu)
107 
108 /* EFER defaults:
109  * - enable syscall per default because its emulated by KVM
110  * - enable LME and LMA per default on 64 bit KVM
111  */
112 #ifdef CONFIG_X86_64
113 static
114 u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
115 #else
116 static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
117 #endif
118 
119 static u64 __read_mostly cr4_reserved_bits = CR4_RESERVED_BITS;
120 
121 #define KVM_EXIT_HYPERCALL_VALID_MASK (1 << KVM_HC_MAP_GPA_RANGE)
122 
123 #define KVM_CAP_PMU_VALID_MASK KVM_PMU_CAP_DISABLE
124 
125 #define KVM_X2APIC_API_VALID_FLAGS (KVM_X2APIC_API_USE_32BIT_IDS | \
126                                     KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
127 
128 static void update_cr8_intercept(struct kvm_vcpu *vcpu);
129 static void process_nmi(struct kvm_vcpu *vcpu);
130 static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags);
131 static void store_regs(struct kvm_vcpu *vcpu);
132 static int sync_regs(struct kvm_vcpu *vcpu);
133 static int kvm_vcpu_do_singlestep(struct kvm_vcpu *vcpu);
134 
135 static int __set_sregs2(struct kvm_vcpu *vcpu, struct kvm_sregs2 *sregs2);
136 static void __get_sregs2(struct kvm_vcpu *vcpu, struct kvm_sregs2 *sregs2);
137 
138 static DEFINE_MUTEX(vendor_module_lock);
139 struct kvm_x86_ops kvm_x86_ops __read_mostly;
140 
141 #define KVM_X86_OP(func)					     \
142 	DEFINE_STATIC_CALL_NULL(kvm_x86_##func,			     \
143 				*(((struct kvm_x86_ops *)0)->func));
144 #define KVM_X86_OP_OPTIONAL KVM_X86_OP
145 #define KVM_X86_OP_OPTIONAL_RET0 KVM_X86_OP
146 #include <asm/kvm-x86-ops.h>
147 EXPORT_STATIC_CALL_GPL(kvm_x86_get_cs_db_l_bits);
148 EXPORT_STATIC_CALL_GPL(kvm_x86_cache_reg);
149 
150 static bool __read_mostly ignore_msrs = 0;
151 module_param(ignore_msrs, bool, 0644);
152 
153 bool __read_mostly report_ignored_msrs = true;
154 module_param(report_ignored_msrs, bool, 0644);
155 EXPORT_SYMBOL_GPL(report_ignored_msrs);
156 
157 unsigned int min_timer_period_us = 200;
158 module_param(min_timer_period_us, uint, 0644);
159 
160 static bool __read_mostly kvmclock_periodic_sync = true;
161 module_param(kvmclock_periodic_sync, bool, 0444);
162 
163 /* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
164 static u32 __read_mostly tsc_tolerance_ppm = 250;
165 module_param(tsc_tolerance_ppm, uint, 0644);
166 
167 /*
168  * lapic timer advance (tscdeadline mode only) in nanoseconds.  '-1' enables
169  * adaptive tuning starting from default advancement of 1000ns.  '0' disables
170  * advancement entirely.  Any other value is used as-is and disables adaptive
171  * tuning, i.e. allows privileged userspace to set an exact advancement time.
172  */
173 static int __read_mostly lapic_timer_advance_ns = -1;
174 module_param(lapic_timer_advance_ns, int, 0644);
175 
176 static bool __read_mostly vector_hashing = true;
177 module_param(vector_hashing, bool, 0444);
178 
179 bool __read_mostly enable_vmware_backdoor = false;
180 module_param(enable_vmware_backdoor, bool, 0444);
181 EXPORT_SYMBOL_GPL(enable_vmware_backdoor);
182 
183 /*
184  * Flags to manipulate forced emulation behavior (any non-zero value will
185  * enable forced emulation).
186  */
187 #define KVM_FEP_CLEAR_RFLAGS_RF	BIT(1)
188 static int __read_mostly force_emulation_prefix;
189 module_param(force_emulation_prefix, int, 0644);
190 
191 int __read_mostly pi_inject_timer = -1;
192 module_param(pi_inject_timer, bint, 0644);
193 
194 /* Enable/disable PMU virtualization */
195 bool __read_mostly enable_pmu = true;
196 EXPORT_SYMBOL_GPL(enable_pmu);
197 module_param(enable_pmu, bool, 0444);
198 
199 bool __read_mostly eager_page_split = true;
200 module_param(eager_page_split, bool, 0644);
201 
202 /* Enable/disable SMT_RSB bug mitigation */
203 static bool __read_mostly mitigate_smt_rsb;
204 module_param(mitigate_smt_rsb, bool, 0444);
205 
206 /*
207  * Restoring the host value for MSRs that are only consumed when running in
208  * usermode, e.g. SYSCALL MSRs and TSC_AUX, can be deferred until the CPU
209  * returns to userspace, i.e. the kernel can run with the guest's value.
210  */
211 #define KVM_MAX_NR_USER_RETURN_MSRS 16
212 
213 struct kvm_user_return_msrs {
214 	struct user_return_notifier urn;
215 	bool registered;
216 	struct kvm_user_return_msr_values {
217 		u64 host;
218 		u64 curr;
219 	} values[KVM_MAX_NR_USER_RETURN_MSRS];
220 };
221 
222 u32 __read_mostly kvm_nr_uret_msrs;
223 EXPORT_SYMBOL_GPL(kvm_nr_uret_msrs);
224 static u32 __read_mostly kvm_uret_msrs_list[KVM_MAX_NR_USER_RETURN_MSRS];
225 static struct kvm_user_return_msrs __percpu *user_return_msrs;
226 
227 #define KVM_SUPPORTED_XCR0     (XFEATURE_MASK_FP | XFEATURE_MASK_SSE \
228 				| XFEATURE_MASK_YMM | XFEATURE_MASK_BNDREGS \
229 				| XFEATURE_MASK_BNDCSR | XFEATURE_MASK_AVX512 \
230 				| XFEATURE_MASK_PKRU | XFEATURE_MASK_XTILE)
231 
232 u64 __read_mostly host_efer;
233 EXPORT_SYMBOL_GPL(host_efer);
234 
235 bool __read_mostly allow_smaller_maxphyaddr = 0;
236 EXPORT_SYMBOL_GPL(allow_smaller_maxphyaddr);
237 
238 bool __read_mostly enable_apicv = true;
239 EXPORT_SYMBOL_GPL(enable_apicv);
240 
241 u64 __read_mostly host_xss;
242 EXPORT_SYMBOL_GPL(host_xss);
243 
244 u64 __read_mostly host_arch_capabilities;
245 EXPORT_SYMBOL_GPL(host_arch_capabilities);
246 
247 const struct _kvm_stats_desc kvm_vm_stats_desc[] = {
248 	KVM_GENERIC_VM_STATS(),
249 	STATS_DESC_COUNTER(VM, mmu_shadow_zapped),
250 	STATS_DESC_COUNTER(VM, mmu_pte_write),
251 	STATS_DESC_COUNTER(VM, mmu_pde_zapped),
252 	STATS_DESC_COUNTER(VM, mmu_flooded),
253 	STATS_DESC_COUNTER(VM, mmu_recycled),
254 	STATS_DESC_COUNTER(VM, mmu_cache_miss),
255 	STATS_DESC_ICOUNTER(VM, mmu_unsync),
256 	STATS_DESC_ICOUNTER(VM, pages_4k),
257 	STATS_DESC_ICOUNTER(VM, pages_2m),
258 	STATS_DESC_ICOUNTER(VM, pages_1g),
259 	STATS_DESC_ICOUNTER(VM, nx_lpage_splits),
260 	STATS_DESC_PCOUNTER(VM, max_mmu_rmap_size),
261 	STATS_DESC_PCOUNTER(VM, max_mmu_page_hash_collisions)
262 };
263 
264 const struct kvm_stats_header kvm_vm_stats_header = {
265 	.name_size = KVM_STATS_NAME_SIZE,
266 	.num_desc = ARRAY_SIZE(kvm_vm_stats_desc),
267 	.id_offset = sizeof(struct kvm_stats_header),
268 	.desc_offset = sizeof(struct kvm_stats_header) + KVM_STATS_NAME_SIZE,
269 	.data_offset = sizeof(struct kvm_stats_header) + KVM_STATS_NAME_SIZE +
270 		       sizeof(kvm_vm_stats_desc),
271 };
272 
273 const struct _kvm_stats_desc kvm_vcpu_stats_desc[] = {
274 	KVM_GENERIC_VCPU_STATS(),
275 	STATS_DESC_COUNTER(VCPU, pf_taken),
276 	STATS_DESC_COUNTER(VCPU, pf_fixed),
277 	STATS_DESC_COUNTER(VCPU, pf_emulate),
278 	STATS_DESC_COUNTER(VCPU, pf_spurious),
279 	STATS_DESC_COUNTER(VCPU, pf_fast),
280 	STATS_DESC_COUNTER(VCPU, pf_mmio_spte_created),
281 	STATS_DESC_COUNTER(VCPU, pf_guest),
282 	STATS_DESC_COUNTER(VCPU, tlb_flush),
283 	STATS_DESC_COUNTER(VCPU, invlpg),
284 	STATS_DESC_COUNTER(VCPU, exits),
285 	STATS_DESC_COUNTER(VCPU, io_exits),
286 	STATS_DESC_COUNTER(VCPU, mmio_exits),
287 	STATS_DESC_COUNTER(VCPU, signal_exits),
288 	STATS_DESC_COUNTER(VCPU, irq_window_exits),
289 	STATS_DESC_COUNTER(VCPU, nmi_window_exits),
290 	STATS_DESC_COUNTER(VCPU, l1d_flush),
291 	STATS_DESC_COUNTER(VCPU, halt_exits),
292 	STATS_DESC_COUNTER(VCPU, request_irq_exits),
293 	STATS_DESC_COUNTER(VCPU, irq_exits),
294 	STATS_DESC_COUNTER(VCPU, host_state_reload),
295 	STATS_DESC_COUNTER(VCPU, fpu_reload),
296 	STATS_DESC_COUNTER(VCPU, insn_emulation),
297 	STATS_DESC_COUNTER(VCPU, insn_emulation_fail),
298 	STATS_DESC_COUNTER(VCPU, hypercalls),
299 	STATS_DESC_COUNTER(VCPU, irq_injections),
300 	STATS_DESC_COUNTER(VCPU, nmi_injections),
301 	STATS_DESC_COUNTER(VCPU, req_event),
302 	STATS_DESC_COUNTER(VCPU, nested_run),
303 	STATS_DESC_COUNTER(VCPU, directed_yield_attempted),
304 	STATS_DESC_COUNTER(VCPU, directed_yield_successful),
305 	STATS_DESC_COUNTER(VCPU, preemption_reported),
306 	STATS_DESC_COUNTER(VCPU, preemption_other),
307 	STATS_DESC_IBOOLEAN(VCPU, guest_mode),
308 	STATS_DESC_COUNTER(VCPU, notify_window_exits),
309 };
310 
311 const struct kvm_stats_header kvm_vcpu_stats_header = {
312 	.name_size = KVM_STATS_NAME_SIZE,
313 	.num_desc = ARRAY_SIZE(kvm_vcpu_stats_desc),
314 	.id_offset = sizeof(struct kvm_stats_header),
315 	.desc_offset = sizeof(struct kvm_stats_header) + KVM_STATS_NAME_SIZE,
316 	.data_offset = sizeof(struct kvm_stats_header) + KVM_STATS_NAME_SIZE +
317 		       sizeof(kvm_vcpu_stats_desc),
318 };
319 
320 u64 __read_mostly host_xcr0;
321 
322 static struct kmem_cache *x86_emulator_cache;
323 
324 /*
325  * When called, it means the previous get/set msr reached an invalid msr.
326  * Return true if we want to ignore/silent this failed msr access.
327  */
328 static bool kvm_msr_ignored_check(u32 msr, u64 data, bool write)
329 {
330 	const char *op = write ? "wrmsr" : "rdmsr";
331 
332 	if (ignore_msrs) {
333 		if (report_ignored_msrs)
334 			kvm_pr_unimpl("ignored %s: 0x%x data 0x%llx\n",
335 				      op, msr, data);
336 		/* Mask the error */
337 		return true;
338 	} else {
339 		kvm_debug_ratelimited("unhandled %s: 0x%x data 0x%llx\n",
340 				      op, msr, data);
341 		return false;
342 	}
343 }
344 
345 static struct kmem_cache *kvm_alloc_emulator_cache(void)
346 {
347 	unsigned int useroffset = offsetof(struct x86_emulate_ctxt, src);
348 	unsigned int size = sizeof(struct x86_emulate_ctxt);
349 
350 	return kmem_cache_create_usercopy("x86_emulator", size,
351 					  __alignof__(struct x86_emulate_ctxt),
352 					  SLAB_ACCOUNT, useroffset,
353 					  size - useroffset, NULL);
354 }
355 
356 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
357 
358 static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
359 {
360 	int i;
361 	for (i = 0; i < ASYNC_PF_PER_VCPU; i++)
362 		vcpu->arch.apf.gfns[i] = ~0;
363 }
364 
365 static void kvm_on_user_return(struct user_return_notifier *urn)
366 {
367 	unsigned slot;
368 	struct kvm_user_return_msrs *msrs
369 		= container_of(urn, struct kvm_user_return_msrs, urn);
370 	struct kvm_user_return_msr_values *values;
371 	unsigned long flags;
372 
373 	/*
374 	 * Disabling irqs at this point since the following code could be
375 	 * interrupted and executed through kvm_arch_hardware_disable()
376 	 */
377 	local_irq_save(flags);
378 	if (msrs->registered) {
379 		msrs->registered = false;
380 		user_return_notifier_unregister(urn);
381 	}
382 	local_irq_restore(flags);
383 	for (slot = 0; slot < kvm_nr_uret_msrs; ++slot) {
384 		values = &msrs->values[slot];
385 		if (values->host != values->curr) {
386 			wrmsrl(kvm_uret_msrs_list[slot], values->host);
387 			values->curr = values->host;
388 		}
389 	}
390 }
391 
392 static int kvm_probe_user_return_msr(u32 msr)
393 {
394 	u64 val;
395 	int ret;
396 
397 	preempt_disable();
398 	ret = rdmsrl_safe(msr, &val);
399 	if (ret)
400 		goto out;
401 	ret = wrmsrl_safe(msr, val);
402 out:
403 	preempt_enable();
404 	return ret;
405 }
406 
407 int kvm_add_user_return_msr(u32 msr)
408 {
409 	BUG_ON(kvm_nr_uret_msrs >= KVM_MAX_NR_USER_RETURN_MSRS);
410 
411 	if (kvm_probe_user_return_msr(msr))
412 		return -1;
413 
414 	kvm_uret_msrs_list[kvm_nr_uret_msrs] = msr;
415 	return kvm_nr_uret_msrs++;
416 }
417 EXPORT_SYMBOL_GPL(kvm_add_user_return_msr);
418 
419 int kvm_find_user_return_msr(u32 msr)
420 {
421 	int i;
422 
423 	for (i = 0; i < kvm_nr_uret_msrs; ++i) {
424 		if (kvm_uret_msrs_list[i] == msr)
425 			return i;
426 	}
427 	return -1;
428 }
429 EXPORT_SYMBOL_GPL(kvm_find_user_return_msr);
430 
431 static void kvm_user_return_msr_cpu_online(void)
432 {
433 	unsigned int cpu = smp_processor_id();
434 	struct kvm_user_return_msrs *msrs = per_cpu_ptr(user_return_msrs, cpu);
435 	u64 value;
436 	int i;
437 
438 	for (i = 0; i < kvm_nr_uret_msrs; ++i) {
439 		rdmsrl_safe(kvm_uret_msrs_list[i], &value);
440 		msrs->values[i].host = value;
441 		msrs->values[i].curr = value;
442 	}
443 }
444 
445 int kvm_set_user_return_msr(unsigned slot, u64 value, u64 mask)
446 {
447 	unsigned int cpu = smp_processor_id();
448 	struct kvm_user_return_msrs *msrs = per_cpu_ptr(user_return_msrs, cpu);
449 	int err;
450 
451 	value = (value & mask) | (msrs->values[slot].host & ~mask);
452 	if (value == msrs->values[slot].curr)
453 		return 0;
454 	err = wrmsrl_safe(kvm_uret_msrs_list[slot], value);
455 	if (err)
456 		return 1;
457 
458 	msrs->values[slot].curr = value;
459 	if (!msrs->registered) {
460 		msrs->urn.on_user_return = kvm_on_user_return;
461 		user_return_notifier_register(&msrs->urn);
462 		msrs->registered = true;
463 	}
464 	return 0;
465 }
466 EXPORT_SYMBOL_GPL(kvm_set_user_return_msr);
467 
468 static void drop_user_return_notifiers(void)
469 {
470 	unsigned int cpu = smp_processor_id();
471 	struct kvm_user_return_msrs *msrs = per_cpu_ptr(user_return_msrs, cpu);
472 
473 	if (msrs->registered)
474 		kvm_on_user_return(&msrs->urn);
475 }
476 
477 u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
478 {
479 	return vcpu->arch.apic_base;
480 }
481 
482 enum lapic_mode kvm_get_apic_mode(struct kvm_vcpu *vcpu)
483 {
484 	return kvm_apic_mode(kvm_get_apic_base(vcpu));
485 }
486 EXPORT_SYMBOL_GPL(kvm_get_apic_mode);
487 
488 int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
489 {
490 	enum lapic_mode old_mode = kvm_get_apic_mode(vcpu);
491 	enum lapic_mode new_mode = kvm_apic_mode(msr_info->data);
492 	u64 reserved_bits = kvm_vcpu_reserved_gpa_bits_raw(vcpu) | 0x2ff |
493 		(guest_cpuid_has(vcpu, X86_FEATURE_X2APIC) ? 0 : X2APIC_ENABLE);
494 
495 	if ((msr_info->data & reserved_bits) != 0 || new_mode == LAPIC_MODE_INVALID)
496 		return 1;
497 	if (!msr_info->host_initiated) {
498 		if (old_mode == LAPIC_MODE_X2APIC && new_mode == LAPIC_MODE_XAPIC)
499 			return 1;
500 		if (old_mode == LAPIC_MODE_DISABLED && new_mode == LAPIC_MODE_X2APIC)
501 			return 1;
502 	}
503 
504 	kvm_lapic_set_base(vcpu, msr_info->data);
505 	kvm_recalculate_apic_map(vcpu->kvm);
506 	return 0;
507 }
508 
509 /*
510  * Handle a fault on a hardware virtualization (VMX or SVM) instruction.
511  *
512  * Hardware virtualization extension instructions may fault if a reboot turns
513  * off virtualization while processes are running.  Usually after catching the
514  * fault we just panic; during reboot instead the instruction is ignored.
515  */
516 noinstr void kvm_spurious_fault(void)
517 {
518 	/* Fault while not rebooting.  We want the trace. */
519 	BUG_ON(!kvm_rebooting);
520 }
521 EXPORT_SYMBOL_GPL(kvm_spurious_fault);
522 
523 #define EXCPT_BENIGN		0
524 #define EXCPT_CONTRIBUTORY	1
525 #define EXCPT_PF		2
526 
527 static int exception_class(int vector)
528 {
529 	switch (vector) {
530 	case PF_VECTOR:
531 		return EXCPT_PF;
532 	case DE_VECTOR:
533 	case TS_VECTOR:
534 	case NP_VECTOR:
535 	case SS_VECTOR:
536 	case GP_VECTOR:
537 		return EXCPT_CONTRIBUTORY;
538 	default:
539 		break;
540 	}
541 	return EXCPT_BENIGN;
542 }
543 
544 #define EXCPT_FAULT		0
545 #define EXCPT_TRAP		1
546 #define EXCPT_ABORT		2
547 #define EXCPT_INTERRUPT		3
548 #define EXCPT_DB		4
549 
550 static int exception_type(int vector)
551 {
552 	unsigned int mask;
553 
554 	if (WARN_ON(vector > 31 || vector == NMI_VECTOR))
555 		return EXCPT_INTERRUPT;
556 
557 	mask = 1 << vector;
558 
559 	/*
560 	 * #DBs can be trap-like or fault-like, the caller must check other CPU
561 	 * state, e.g. DR6, to determine whether a #DB is a trap or fault.
562 	 */
563 	if (mask & (1 << DB_VECTOR))
564 		return EXCPT_DB;
565 
566 	if (mask & ((1 << BP_VECTOR) | (1 << OF_VECTOR)))
567 		return EXCPT_TRAP;
568 
569 	if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR)))
570 		return EXCPT_ABORT;
571 
572 	/* Reserved exceptions will result in fault */
573 	return EXCPT_FAULT;
574 }
575 
576 void kvm_deliver_exception_payload(struct kvm_vcpu *vcpu,
577 				   struct kvm_queued_exception *ex)
578 {
579 	if (!ex->has_payload)
580 		return;
581 
582 	switch (ex->vector) {
583 	case DB_VECTOR:
584 		/*
585 		 * "Certain debug exceptions may clear bit 0-3.  The
586 		 * remaining contents of the DR6 register are never
587 		 * cleared by the processor".
588 		 */
589 		vcpu->arch.dr6 &= ~DR_TRAP_BITS;
590 		/*
591 		 * In order to reflect the #DB exception payload in guest
592 		 * dr6, three components need to be considered: active low
593 		 * bit, FIXED_1 bits and active high bits (e.g. DR6_BD,
594 		 * DR6_BS and DR6_BT)
595 		 * DR6_ACTIVE_LOW contains the FIXED_1 and active low bits.
596 		 * In the target guest dr6:
597 		 * FIXED_1 bits should always be set.
598 		 * Active low bits should be cleared if 1-setting in payload.
599 		 * Active high bits should be set if 1-setting in payload.
600 		 *
601 		 * Note, the payload is compatible with the pending debug
602 		 * exceptions/exit qualification under VMX, that active_low bits
603 		 * are active high in payload.
604 		 * So they need to be flipped for DR6.
605 		 */
606 		vcpu->arch.dr6 |= DR6_ACTIVE_LOW;
607 		vcpu->arch.dr6 |= ex->payload;
608 		vcpu->arch.dr6 ^= ex->payload & DR6_ACTIVE_LOW;
609 
610 		/*
611 		 * The #DB payload is defined as compatible with the 'pending
612 		 * debug exceptions' field under VMX, not DR6. While bit 12 is
613 		 * defined in the 'pending debug exceptions' field (enabled
614 		 * breakpoint), it is reserved and must be zero in DR6.
615 		 */
616 		vcpu->arch.dr6 &= ~BIT(12);
617 		break;
618 	case PF_VECTOR:
619 		vcpu->arch.cr2 = ex->payload;
620 		break;
621 	}
622 
623 	ex->has_payload = false;
624 	ex->payload = 0;
625 }
626 EXPORT_SYMBOL_GPL(kvm_deliver_exception_payload);
627 
628 static void kvm_queue_exception_vmexit(struct kvm_vcpu *vcpu, unsigned int vector,
629 				       bool has_error_code, u32 error_code,
630 				       bool has_payload, unsigned long payload)
631 {
632 	struct kvm_queued_exception *ex = &vcpu->arch.exception_vmexit;
633 
634 	ex->vector = vector;
635 	ex->injected = false;
636 	ex->pending = true;
637 	ex->has_error_code = has_error_code;
638 	ex->error_code = error_code;
639 	ex->has_payload = has_payload;
640 	ex->payload = payload;
641 }
642 
643 /* Forcibly leave the nested mode in cases like a vCPU reset */
644 static void kvm_leave_nested(struct kvm_vcpu *vcpu)
645 {
646 	kvm_x86_ops.nested_ops->leave_nested(vcpu);
647 }
648 
649 static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
650 		unsigned nr, bool has_error, u32 error_code,
651 	        bool has_payload, unsigned long payload, bool reinject)
652 {
653 	u32 prev_nr;
654 	int class1, class2;
655 
656 	kvm_make_request(KVM_REQ_EVENT, vcpu);
657 
658 	/*
659 	 * If the exception is destined for L2 and isn't being reinjected,
660 	 * morph it to a VM-Exit if L1 wants to intercept the exception.  A
661 	 * previously injected exception is not checked because it was checked
662 	 * when it was original queued, and re-checking is incorrect if _L1_
663 	 * injected the exception, in which case it's exempt from interception.
664 	 */
665 	if (!reinject && is_guest_mode(vcpu) &&
666 	    kvm_x86_ops.nested_ops->is_exception_vmexit(vcpu, nr, error_code)) {
667 		kvm_queue_exception_vmexit(vcpu, nr, has_error, error_code,
668 					   has_payload, payload);
669 		return;
670 	}
671 
672 	if (!vcpu->arch.exception.pending && !vcpu->arch.exception.injected) {
673 	queue:
674 		if (reinject) {
675 			/*
676 			 * On VM-Entry, an exception can be pending if and only
677 			 * if event injection was blocked by nested_run_pending.
678 			 * In that case, however, vcpu_enter_guest() requests an
679 			 * immediate exit, and the guest shouldn't proceed far
680 			 * enough to need reinjection.
681 			 */
682 			WARN_ON_ONCE(kvm_is_exception_pending(vcpu));
683 			vcpu->arch.exception.injected = true;
684 			if (WARN_ON_ONCE(has_payload)) {
685 				/*
686 				 * A reinjected event has already
687 				 * delivered its payload.
688 				 */
689 				has_payload = false;
690 				payload = 0;
691 			}
692 		} else {
693 			vcpu->arch.exception.pending = true;
694 			vcpu->arch.exception.injected = false;
695 		}
696 		vcpu->arch.exception.has_error_code = has_error;
697 		vcpu->arch.exception.vector = nr;
698 		vcpu->arch.exception.error_code = error_code;
699 		vcpu->arch.exception.has_payload = has_payload;
700 		vcpu->arch.exception.payload = payload;
701 		if (!is_guest_mode(vcpu))
702 			kvm_deliver_exception_payload(vcpu,
703 						      &vcpu->arch.exception);
704 		return;
705 	}
706 
707 	/* to check exception */
708 	prev_nr = vcpu->arch.exception.vector;
709 	if (prev_nr == DF_VECTOR) {
710 		/* triple fault -> shutdown */
711 		kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
712 		return;
713 	}
714 	class1 = exception_class(prev_nr);
715 	class2 = exception_class(nr);
716 	if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY) ||
717 	    (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
718 		/*
719 		 * Synthesize #DF.  Clear the previously injected or pending
720 		 * exception so as not to incorrectly trigger shutdown.
721 		 */
722 		vcpu->arch.exception.injected = false;
723 		vcpu->arch.exception.pending = false;
724 
725 		kvm_queue_exception_e(vcpu, DF_VECTOR, 0);
726 	} else {
727 		/* replace previous exception with a new one in a hope
728 		   that instruction re-execution will regenerate lost
729 		   exception */
730 		goto queue;
731 	}
732 }
733 
734 void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
735 {
736 	kvm_multiple_exception(vcpu, nr, false, 0, false, 0, false);
737 }
738 EXPORT_SYMBOL_GPL(kvm_queue_exception);
739 
740 void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
741 {
742 	kvm_multiple_exception(vcpu, nr, false, 0, false, 0, true);
743 }
744 EXPORT_SYMBOL_GPL(kvm_requeue_exception);
745 
746 void kvm_queue_exception_p(struct kvm_vcpu *vcpu, unsigned nr,
747 			   unsigned long payload)
748 {
749 	kvm_multiple_exception(vcpu, nr, false, 0, true, payload, false);
750 }
751 EXPORT_SYMBOL_GPL(kvm_queue_exception_p);
752 
753 static void kvm_queue_exception_e_p(struct kvm_vcpu *vcpu, unsigned nr,
754 				    u32 error_code, unsigned long payload)
755 {
756 	kvm_multiple_exception(vcpu, nr, true, error_code,
757 			       true, payload, false);
758 }
759 
760 int kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
761 {
762 	if (err)
763 		kvm_inject_gp(vcpu, 0);
764 	else
765 		return kvm_skip_emulated_instruction(vcpu);
766 
767 	return 1;
768 }
769 EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
770 
771 static int complete_emulated_insn_gp(struct kvm_vcpu *vcpu, int err)
772 {
773 	if (err) {
774 		kvm_inject_gp(vcpu, 0);
775 		return 1;
776 	}
777 
778 	return kvm_emulate_instruction(vcpu, EMULTYPE_NO_DECODE | EMULTYPE_SKIP |
779 				       EMULTYPE_COMPLETE_USER_EXIT);
780 }
781 
782 void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
783 {
784 	++vcpu->stat.pf_guest;
785 
786 	/*
787 	 * Async #PF in L2 is always forwarded to L1 as a VM-Exit regardless of
788 	 * whether or not L1 wants to intercept "regular" #PF.
789 	 */
790 	if (is_guest_mode(vcpu) && fault->async_page_fault)
791 		kvm_queue_exception_vmexit(vcpu, PF_VECTOR,
792 					   true, fault->error_code,
793 					   true, fault->address);
794 	else
795 		kvm_queue_exception_e_p(vcpu, PF_VECTOR, fault->error_code,
796 					fault->address);
797 }
798 
799 void kvm_inject_emulated_page_fault(struct kvm_vcpu *vcpu,
800 				    struct x86_exception *fault)
801 {
802 	struct kvm_mmu *fault_mmu;
803 	WARN_ON_ONCE(fault->vector != PF_VECTOR);
804 
805 	fault_mmu = fault->nested_page_fault ? vcpu->arch.mmu :
806 					       vcpu->arch.walk_mmu;
807 
808 	/*
809 	 * Invalidate the TLB entry for the faulting address, if it exists,
810 	 * else the access will fault indefinitely (and to emulate hardware).
811 	 */
812 	if ((fault->error_code & PFERR_PRESENT_MASK) &&
813 	    !(fault->error_code & PFERR_RSVD_MASK))
814 		kvm_mmu_invalidate_addr(vcpu, fault_mmu, fault->address,
815 					KVM_MMU_ROOT_CURRENT);
816 
817 	fault_mmu->inject_page_fault(vcpu, fault);
818 }
819 EXPORT_SYMBOL_GPL(kvm_inject_emulated_page_fault);
820 
821 void kvm_inject_nmi(struct kvm_vcpu *vcpu)
822 {
823 	atomic_inc(&vcpu->arch.nmi_queued);
824 	kvm_make_request(KVM_REQ_NMI, vcpu);
825 }
826 
827 void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
828 {
829 	kvm_multiple_exception(vcpu, nr, true, error_code, false, 0, false);
830 }
831 EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
832 
833 void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
834 {
835 	kvm_multiple_exception(vcpu, nr, true, error_code, false, 0, true);
836 }
837 EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
838 
839 /*
840  * Checks if cpl <= required_cpl; if true, return true.  Otherwise queue
841  * a #GP and return false.
842  */
843 bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
844 {
845 	if (static_call(kvm_x86_get_cpl)(vcpu) <= required_cpl)
846 		return true;
847 	kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
848 	return false;
849 }
850 
851 bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr)
852 {
853 	if ((dr != 4 && dr != 5) || !kvm_is_cr4_bit_set(vcpu, X86_CR4_DE))
854 		return true;
855 
856 	kvm_queue_exception(vcpu, UD_VECTOR);
857 	return false;
858 }
859 EXPORT_SYMBOL_GPL(kvm_require_dr);
860 
861 static inline u64 pdptr_rsvd_bits(struct kvm_vcpu *vcpu)
862 {
863 	return vcpu->arch.reserved_gpa_bits | rsvd_bits(5, 8) | rsvd_bits(1, 2);
864 }
865 
866 /*
867  * Load the pae pdptrs.  Return 1 if they are all valid, 0 otherwise.
868  */
869 int load_pdptrs(struct kvm_vcpu *vcpu, unsigned long cr3)
870 {
871 	struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
872 	gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
873 	gpa_t real_gpa;
874 	int i;
875 	int ret;
876 	u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
877 
878 	/*
879 	 * If the MMU is nested, CR3 holds an L2 GPA and needs to be translated
880 	 * to an L1 GPA.
881 	 */
882 	real_gpa = kvm_translate_gpa(vcpu, mmu, gfn_to_gpa(pdpt_gfn),
883 				     PFERR_USER_MASK | PFERR_WRITE_MASK, NULL);
884 	if (real_gpa == INVALID_GPA)
885 		return 0;
886 
887 	/* Note the offset, PDPTRs are 32 byte aligned when using PAE paging. */
888 	ret = kvm_vcpu_read_guest_page(vcpu, gpa_to_gfn(real_gpa), pdpte,
889 				       cr3 & GENMASK(11, 5), sizeof(pdpte));
890 	if (ret < 0)
891 		return 0;
892 
893 	for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
894 		if ((pdpte[i] & PT_PRESENT_MASK) &&
895 		    (pdpte[i] & pdptr_rsvd_bits(vcpu))) {
896 			return 0;
897 		}
898 	}
899 
900 	/*
901 	 * Marking VCPU_EXREG_PDPTR dirty doesn't work for !tdp_enabled.
902 	 * Shadow page roots need to be reconstructed instead.
903 	 */
904 	if (!tdp_enabled && memcmp(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs)))
905 		kvm_mmu_free_roots(vcpu->kvm, mmu, KVM_MMU_ROOT_CURRENT);
906 
907 	memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
908 	kvm_register_mark_dirty(vcpu, VCPU_EXREG_PDPTR);
909 	kvm_make_request(KVM_REQ_LOAD_MMU_PGD, vcpu);
910 	vcpu->arch.pdptrs_from_userspace = false;
911 
912 	return 1;
913 }
914 EXPORT_SYMBOL_GPL(load_pdptrs);
915 
916 static bool kvm_is_valid_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
917 {
918 #ifdef CONFIG_X86_64
919 	if (cr0 & 0xffffffff00000000UL)
920 		return false;
921 #endif
922 
923 	if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
924 		return false;
925 
926 	if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
927 		return false;
928 
929 	return static_call(kvm_x86_is_valid_cr0)(vcpu, cr0);
930 }
931 
932 void kvm_post_set_cr0(struct kvm_vcpu *vcpu, unsigned long old_cr0, unsigned long cr0)
933 {
934 	/*
935 	 * CR0.WP is incorporated into the MMU role, but only for non-nested,
936 	 * indirect shadow MMUs.  If paging is disabled, no updates are needed
937 	 * as there are no permission bits to emulate.  If TDP is enabled, the
938 	 * MMU's metadata needs to be updated, e.g. so that emulating guest
939 	 * translations does the right thing, but there's no need to unload the
940 	 * root as CR0.WP doesn't affect SPTEs.
941 	 */
942 	if ((cr0 ^ old_cr0) == X86_CR0_WP) {
943 		if (!(cr0 & X86_CR0_PG))
944 			return;
945 
946 		if (tdp_enabled) {
947 			kvm_init_mmu(vcpu);
948 			return;
949 		}
950 	}
951 
952 	if ((cr0 ^ old_cr0) & X86_CR0_PG) {
953 		kvm_clear_async_pf_completion_queue(vcpu);
954 		kvm_async_pf_hash_reset(vcpu);
955 
956 		/*
957 		 * Clearing CR0.PG is defined to flush the TLB from the guest's
958 		 * perspective.
959 		 */
960 		if (!(cr0 & X86_CR0_PG))
961 			kvm_make_request(KVM_REQ_TLB_FLUSH_GUEST, vcpu);
962 	}
963 
964 	if ((cr0 ^ old_cr0) & KVM_MMU_CR0_ROLE_BITS)
965 		kvm_mmu_reset_context(vcpu);
966 
967 	if (((cr0 ^ old_cr0) & X86_CR0_CD) &&
968 	    kvm_mmu_honors_guest_mtrrs(vcpu->kvm) &&
969 	    !kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
970 		kvm_zap_gfn_range(vcpu->kvm, 0, ~0ULL);
971 }
972 EXPORT_SYMBOL_GPL(kvm_post_set_cr0);
973 
974 int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
975 {
976 	unsigned long old_cr0 = kvm_read_cr0(vcpu);
977 
978 	if (!kvm_is_valid_cr0(vcpu, cr0))
979 		return 1;
980 
981 	cr0 |= X86_CR0_ET;
982 
983 	/* Write to CR0 reserved bits are ignored, even on Intel. */
984 	cr0 &= ~CR0_RESERVED_BITS;
985 
986 #ifdef CONFIG_X86_64
987 	if ((vcpu->arch.efer & EFER_LME) && !is_paging(vcpu) &&
988 	    (cr0 & X86_CR0_PG)) {
989 		int cs_db, cs_l;
990 
991 		if (!is_pae(vcpu))
992 			return 1;
993 		static_call(kvm_x86_get_cs_db_l_bits)(vcpu, &cs_db, &cs_l);
994 		if (cs_l)
995 			return 1;
996 	}
997 #endif
998 	if (!(vcpu->arch.efer & EFER_LME) && (cr0 & X86_CR0_PG) &&
999 	    is_pae(vcpu) && ((cr0 ^ old_cr0) & X86_CR0_PDPTR_BITS) &&
1000 	    !load_pdptrs(vcpu, kvm_read_cr3(vcpu)))
1001 		return 1;
1002 
1003 	if (!(cr0 & X86_CR0_PG) &&
1004 	    (is_64_bit_mode(vcpu) || kvm_is_cr4_bit_set(vcpu, X86_CR4_PCIDE)))
1005 		return 1;
1006 
1007 	static_call(kvm_x86_set_cr0)(vcpu, cr0);
1008 
1009 	kvm_post_set_cr0(vcpu, old_cr0, cr0);
1010 
1011 	return 0;
1012 }
1013 EXPORT_SYMBOL_GPL(kvm_set_cr0);
1014 
1015 void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
1016 {
1017 	(void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
1018 }
1019 EXPORT_SYMBOL_GPL(kvm_lmsw);
1020 
1021 void kvm_load_guest_xsave_state(struct kvm_vcpu *vcpu)
1022 {
1023 	if (vcpu->arch.guest_state_protected)
1024 		return;
1025 
1026 	if (kvm_is_cr4_bit_set(vcpu, X86_CR4_OSXSAVE)) {
1027 
1028 		if (vcpu->arch.xcr0 != host_xcr0)
1029 			xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
1030 
1031 		if (guest_can_use(vcpu, X86_FEATURE_XSAVES) &&
1032 		    vcpu->arch.ia32_xss != host_xss)
1033 			wrmsrl(MSR_IA32_XSS, vcpu->arch.ia32_xss);
1034 	}
1035 
1036 	if (cpu_feature_enabled(X86_FEATURE_PKU) &&
1037 	    vcpu->arch.pkru != vcpu->arch.host_pkru &&
1038 	    ((vcpu->arch.xcr0 & XFEATURE_MASK_PKRU) ||
1039 	     kvm_is_cr4_bit_set(vcpu, X86_CR4_PKE)))
1040 		write_pkru(vcpu->arch.pkru);
1041 }
1042 EXPORT_SYMBOL_GPL(kvm_load_guest_xsave_state);
1043 
1044 void kvm_load_host_xsave_state(struct kvm_vcpu *vcpu)
1045 {
1046 	if (vcpu->arch.guest_state_protected)
1047 		return;
1048 
1049 	if (cpu_feature_enabled(X86_FEATURE_PKU) &&
1050 	    ((vcpu->arch.xcr0 & XFEATURE_MASK_PKRU) ||
1051 	     kvm_is_cr4_bit_set(vcpu, X86_CR4_PKE))) {
1052 		vcpu->arch.pkru = rdpkru();
1053 		if (vcpu->arch.pkru != vcpu->arch.host_pkru)
1054 			write_pkru(vcpu->arch.host_pkru);
1055 	}
1056 
1057 	if (kvm_is_cr4_bit_set(vcpu, X86_CR4_OSXSAVE)) {
1058 
1059 		if (vcpu->arch.xcr0 != host_xcr0)
1060 			xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
1061 
1062 		if (guest_can_use(vcpu, X86_FEATURE_XSAVES) &&
1063 		    vcpu->arch.ia32_xss != host_xss)
1064 			wrmsrl(MSR_IA32_XSS, host_xss);
1065 	}
1066 
1067 }
1068 EXPORT_SYMBOL_GPL(kvm_load_host_xsave_state);
1069 
1070 #ifdef CONFIG_X86_64
1071 static inline u64 kvm_guest_supported_xfd(struct kvm_vcpu *vcpu)
1072 {
1073 	return vcpu->arch.guest_supported_xcr0 & XFEATURE_MASK_USER_DYNAMIC;
1074 }
1075 #endif
1076 
1077 static int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
1078 {
1079 	u64 xcr0 = xcr;
1080 	u64 old_xcr0 = vcpu->arch.xcr0;
1081 	u64 valid_bits;
1082 
1083 	/* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now  */
1084 	if (index != XCR_XFEATURE_ENABLED_MASK)
1085 		return 1;
1086 	if (!(xcr0 & XFEATURE_MASK_FP))
1087 		return 1;
1088 	if ((xcr0 & XFEATURE_MASK_YMM) && !(xcr0 & XFEATURE_MASK_SSE))
1089 		return 1;
1090 
1091 	/*
1092 	 * Do not allow the guest to set bits that we do not support
1093 	 * saving.  However, xcr0 bit 0 is always set, even if the
1094 	 * emulated CPU does not support XSAVE (see kvm_vcpu_reset()).
1095 	 */
1096 	valid_bits = vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FP;
1097 	if (xcr0 & ~valid_bits)
1098 		return 1;
1099 
1100 	if ((!(xcr0 & XFEATURE_MASK_BNDREGS)) !=
1101 	    (!(xcr0 & XFEATURE_MASK_BNDCSR)))
1102 		return 1;
1103 
1104 	if (xcr0 & XFEATURE_MASK_AVX512) {
1105 		if (!(xcr0 & XFEATURE_MASK_YMM))
1106 			return 1;
1107 		if ((xcr0 & XFEATURE_MASK_AVX512) != XFEATURE_MASK_AVX512)
1108 			return 1;
1109 	}
1110 
1111 	if ((xcr0 & XFEATURE_MASK_XTILE) &&
1112 	    ((xcr0 & XFEATURE_MASK_XTILE) != XFEATURE_MASK_XTILE))
1113 		return 1;
1114 
1115 	vcpu->arch.xcr0 = xcr0;
1116 
1117 	if ((xcr0 ^ old_xcr0) & XFEATURE_MASK_EXTEND)
1118 		kvm_update_cpuid_runtime(vcpu);
1119 	return 0;
1120 }
1121 
1122 int kvm_emulate_xsetbv(struct kvm_vcpu *vcpu)
1123 {
1124 	/* Note, #UD due to CR4.OSXSAVE=0 has priority over the intercept. */
1125 	if (static_call(kvm_x86_get_cpl)(vcpu) != 0 ||
1126 	    __kvm_set_xcr(vcpu, kvm_rcx_read(vcpu), kvm_read_edx_eax(vcpu))) {
1127 		kvm_inject_gp(vcpu, 0);
1128 		return 1;
1129 	}
1130 
1131 	return kvm_skip_emulated_instruction(vcpu);
1132 }
1133 EXPORT_SYMBOL_GPL(kvm_emulate_xsetbv);
1134 
1135 bool __kvm_is_valid_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1136 {
1137 	if (cr4 & cr4_reserved_bits)
1138 		return false;
1139 
1140 	if (cr4 & vcpu->arch.cr4_guest_rsvd_bits)
1141 		return false;
1142 
1143 	return true;
1144 }
1145 EXPORT_SYMBOL_GPL(__kvm_is_valid_cr4);
1146 
1147 static bool kvm_is_valid_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1148 {
1149 	return __kvm_is_valid_cr4(vcpu, cr4) &&
1150 	       static_call(kvm_x86_is_valid_cr4)(vcpu, cr4);
1151 }
1152 
1153 void kvm_post_set_cr4(struct kvm_vcpu *vcpu, unsigned long old_cr4, unsigned long cr4)
1154 {
1155 	if ((cr4 ^ old_cr4) & KVM_MMU_CR4_ROLE_BITS)
1156 		kvm_mmu_reset_context(vcpu);
1157 
1158 	/*
1159 	 * If CR4.PCIDE is changed 0 -> 1, there is no need to flush the TLB
1160 	 * according to the SDM; however, stale prev_roots could be reused
1161 	 * incorrectly in the future after a MOV to CR3 with NOFLUSH=1, so we
1162 	 * free them all.  This is *not* a superset of KVM_REQ_TLB_FLUSH_GUEST
1163 	 * or KVM_REQ_TLB_FLUSH_CURRENT, because the hardware TLB is not flushed,
1164 	 * so fall through.
1165 	 */
1166 	if (!tdp_enabled &&
1167 	    (cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE))
1168 		kvm_mmu_unload(vcpu);
1169 
1170 	/*
1171 	 * The TLB has to be flushed for all PCIDs if any of the following
1172 	 * (architecturally required) changes happen:
1173 	 * - CR4.PCIDE is changed from 1 to 0
1174 	 * - CR4.PGE is toggled
1175 	 *
1176 	 * This is a superset of KVM_REQ_TLB_FLUSH_CURRENT.
1177 	 */
1178 	if (((cr4 ^ old_cr4) & X86_CR4_PGE) ||
1179 	    (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
1180 		kvm_make_request(KVM_REQ_TLB_FLUSH_GUEST, vcpu);
1181 
1182 	/*
1183 	 * The TLB has to be flushed for the current PCID if any of the
1184 	 * following (architecturally required) changes happen:
1185 	 * - CR4.SMEP is changed from 0 to 1
1186 	 * - CR4.PAE is toggled
1187 	 */
1188 	else if (((cr4 ^ old_cr4) & X86_CR4_PAE) ||
1189 		 ((cr4 & X86_CR4_SMEP) && !(old_cr4 & X86_CR4_SMEP)))
1190 		kvm_make_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu);
1191 
1192 }
1193 EXPORT_SYMBOL_GPL(kvm_post_set_cr4);
1194 
1195 int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1196 {
1197 	unsigned long old_cr4 = kvm_read_cr4(vcpu);
1198 
1199 	if (!kvm_is_valid_cr4(vcpu, cr4))
1200 		return 1;
1201 
1202 	if (is_long_mode(vcpu)) {
1203 		if (!(cr4 & X86_CR4_PAE))
1204 			return 1;
1205 		if ((cr4 ^ old_cr4) & X86_CR4_LA57)
1206 			return 1;
1207 	} else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
1208 		   && ((cr4 ^ old_cr4) & X86_CR4_PDPTR_BITS)
1209 		   && !load_pdptrs(vcpu, kvm_read_cr3(vcpu)))
1210 		return 1;
1211 
1212 	if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
1213 		/* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
1214 		if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
1215 			return 1;
1216 	}
1217 
1218 	static_call(kvm_x86_set_cr4)(vcpu, cr4);
1219 
1220 	kvm_post_set_cr4(vcpu, old_cr4, cr4);
1221 
1222 	return 0;
1223 }
1224 EXPORT_SYMBOL_GPL(kvm_set_cr4);
1225 
1226 static void kvm_invalidate_pcid(struct kvm_vcpu *vcpu, unsigned long pcid)
1227 {
1228 	struct kvm_mmu *mmu = vcpu->arch.mmu;
1229 	unsigned long roots_to_free = 0;
1230 	int i;
1231 
1232 	/*
1233 	 * MOV CR3 and INVPCID are usually not intercepted when using TDP, but
1234 	 * this is reachable when running EPT=1 and unrestricted_guest=0,  and
1235 	 * also via the emulator.  KVM's TDP page tables are not in the scope of
1236 	 * the invalidation, but the guest's TLB entries need to be flushed as
1237 	 * the CPU may have cached entries in its TLB for the target PCID.
1238 	 */
1239 	if (unlikely(tdp_enabled)) {
1240 		kvm_make_request(KVM_REQ_TLB_FLUSH_GUEST, vcpu);
1241 		return;
1242 	}
1243 
1244 	/*
1245 	 * If neither the current CR3 nor any of the prev_roots use the given
1246 	 * PCID, then nothing needs to be done here because a resync will
1247 	 * happen anyway before switching to any other CR3.
1248 	 */
1249 	if (kvm_get_active_pcid(vcpu) == pcid) {
1250 		kvm_make_request(KVM_REQ_MMU_SYNC, vcpu);
1251 		kvm_make_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu);
1252 	}
1253 
1254 	/*
1255 	 * If PCID is disabled, there is no need to free prev_roots even if the
1256 	 * PCIDs for them are also 0, because MOV to CR3 always flushes the TLB
1257 	 * with PCIDE=0.
1258 	 */
1259 	if (!kvm_is_cr4_bit_set(vcpu, X86_CR4_PCIDE))
1260 		return;
1261 
1262 	for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++)
1263 		if (kvm_get_pcid(vcpu, mmu->prev_roots[i].pgd) == pcid)
1264 			roots_to_free |= KVM_MMU_ROOT_PREVIOUS(i);
1265 
1266 	kvm_mmu_free_roots(vcpu->kvm, mmu, roots_to_free);
1267 }
1268 
1269 int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
1270 {
1271 	bool skip_tlb_flush = false;
1272 	unsigned long pcid = 0;
1273 #ifdef CONFIG_X86_64
1274 	if (kvm_is_cr4_bit_set(vcpu, X86_CR4_PCIDE)) {
1275 		skip_tlb_flush = cr3 & X86_CR3_PCID_NOFLUSH;
1276 		cr3 &= ~X86_CR3_PCID_NOFLUSH;
1277 		pcid = cr3 & X86_CR3_PCID_MASK;
1278 	}
1279 #endif
1280 
1281 	/* PDPTRs are always reloaded for PAE paging. */
1282 	if (cr3 == kvm_read_cr3(vcpu) && !is_pae_paging(vcpu))
1283 		goto handle_tlb_flush;
1284 
1285 	/*
1286 	 * Do not condition the GPA check on long mode, this helper is used to
1287 	 * stuff CR3, e.g. for RSM emulation, and there is no guarantee that
1288 	 * the current vCPU mode is accurate.
1289 	 */
1290 	if (!kvm_vcpu_is_legal_cr3(vcpu, cr3))
1291 		return 1;
1292 
1293 	if (is_pae_paging(vcpu) && !load_pdptrs(vcpu, cr3))
1294 		return 1;
1295 
1296 	if (cr3 != kvm_read_cr3(vcpu))
1297 		kvm_mmu_new_pgd(vcpu, cr3);
1298 
1299 	vcpu->arch.cr3 = cr3;
1300 	kvm_register_mark_dirty(vcpu, VCPU_EXREG_CR3);
1301 	/* Do not call post_set_cr3, we do not get here for confidential guests.  */
1302 
1303 handle_tlb_flush:
1304 	/*
1305 	 * A load of CR3 that flushes the TLB flushes only the current PCID,
1306 	 * even if PCID is disabled, in which case PCID=0 is flushed.  It's a
1307 	 * moot point in the end because _disabling_ PCID will flush all PCIDs,
1308 	 * and it's impossible to use a non-zero PCID when PCID is disabled,
1309 	 * i.e. only PCID=0 can be relevant.
1310 	 */
1311 	if (!skip_tlb_flush)
1312 		kvm_invalidate_pcid(vcpu, pcid);
1313 
1314 	return 0;
1315 }
1316 EXPORT_SYMBOL_GPL(kvm_set_cr3);
1317 
1318 int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
1319 {
1320 	if (cr8 & CR8_RESERVED_BITS)
1321 		return 1;
1322 	if (lapic_in_kernel(vcpu))
1323 		kvm_lapic_set_tpr(vcpu, cr8);
1324 	else
1325 		vcpu->arch.cr8 = cr8;
1326 	return 0;
1327 }
1328 EXPORT_SYMBOL_GPL(kvm_set_cr8);
1329 
1330 unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
1331 {
1332 	if (lapic_in_kernel(vcpu))
1333 		return kvm_lapic_get_cr8(vcpu);
1334 	else
1335 		return vcpu->arch.cr8;
1336 }
1337 EXPORT_SYMBOL_GPL(kvm_get_cr8);
1338 
1339 static void kvm_update_dr0123(struct kvm_vcpu *vcpu)
1340 {
1341 	int i;
1342 
1343 	if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
1344 		for (i = 0; i < KVM_NR_DB_REGS; i++)
1345 			vcpu->arch.eff_db[i] = vcpu->arch.db[i];
1346 	}
1347 }
1348 
1349 void kvm_update_dr7(struct kvm_vcpu *vcpu)
1350 {
1351 	unsigned long dr7;
1352 
1353 	if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1354 		dr7 = vcpu->arch.guest_debug_dr7;
1355 	else
1356 		dr7 = vcpu->arch.dr7;
1357 	static_call(kvm_x86_set_dr7)(vcpu, dr7);
1358 	vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED;
1359 	if (dr7 & DR7_BP_EN_MASK)
1360 		vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED;
1361 }
1362 EXPORT_SYMBOL_GPL(kvm_update_dr7);
1363 
1364 static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu)
1365 {
1366 	u64 fixed = DR6_FIXED_1;
1367 
1368 	if (!guest_cpuid_has(vcpu, X86_FEATURE_RTM))
1369 		fixed |= DR6_RTM;
1370 
1371 	if (!guest_cpuid_has(vcpu, X86_FEATURE_BUS_LOCK_DETECT))
1372 		fixed |= DR6_BUS_LOCK;
1373 	return fixed;
1374 }
1375 
1376 int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
1377 {
1378 	size_t size = ARRAY_SIZE(vcpu->arch.db);
1379 
1380 	switch (dr) {
1381 	case 0 ... 3:
1382 		vcpu->arch.db[array_index_nospec(dr, size)] = val;
1383 		if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
1384 			vcpu->arch.eff_db[dr] = val;
1385 		break;
1386 	case 4:
1387 	case 6:
1388 		if (!kvm_dr6_valid(val))
1389 			return 1; /* #GP */
1390 		vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu);
1391 		break;
1392 	case 5:
1393 	default: /* 7 */
1394 		if (!kvm_dr7_valid(val))
1395 			return 1; /* #GP */
1396 		vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
1397 		kvm_update_dr7(vcpu);
1398 		break;
1399 	}
1400 
1401 	return 0;
1402 }
1403 EXPORT_SYMBOL_GPL(kvm_set_dr);
1404 
1405 unsigned long kvm_get_dr(struct kvm_vcpu *vcpu, int dr)
1406 {
1407 	size_t size = ARRAY_SIZE(vcpu->arch.db);
1408 
1409 	switch (dr) {
1410 	case 0 ... 3:
1411 		return vcpu->arch.db[array_index_nospec(dr, size)];
1412 	case 4:
1413 	case 6:
1414 		return vcpu->arch.dr6;
1415 	case 5:
1416 	default: /* 7 */
1417 		return vcpu->arch.dr7;
1418 	}
1419 }
1420 EXPORT_SYMBOL_GPL(kvm_get_dr);
1421 
1422 int kvm_emulate_rdpmc(struct kvm_vcpu *vcpu)
1423 {
1424 	u32 ecx = kvm_rcx_read(vcpu);
1425 	u64 data;
1426 
1427 	if (kvm_pmu_rdpmc(vcpu, ecx, &data)) {
1428 		kvm_inject_gp(vcpu, 0);
1429 		return 1;
1430 	}
1431 
1432 	kvm_rax_write(vcpu, (u32)data);
1433 	kvm_rdx_write(vcpu, data >> 32);
1434 	return kvm_skip_emulated_instruction(vcpu);
1435 }
1436 EXPORT_SYMBOL_GPL(kvm_emulate_rdpmc);
1437 
1438 /*
1439  * The three MSR lists(msrs_to_save, emulated_msrs, msr_based_features) track
1440  * the set of MSRs that KVM exposes to userspace through KVM_GET_MSRS,
1441  * KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.  msrs_to_save holds MSRs that
1442  * require host support, i.e. should be probed via RDMSR.  emulated_msrs holds
1443  * MSRs that KVM emulates without strictly requiring host support.
1444  * msr_based_features holds MSRs that enumerate features, i.e. are effectively
1445  * CPUID leafs.  Note, msr_based_features isn't mutually exclusive with
1446  * msrs_to_save and emulated_msrs.
1447  */
1448 
1449 static const u32 msrs_to_save_base[] = {
1450 	MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
1451 	MSR_STAR,
1452 #ifdef CONFIG_X86_64
1453 	MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
1454 #endif
1455 	MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA,
1456 	MSR_IA32_FEAT_CTL, MSR_IA32_BNDCFGS, MSR_TSC_AUX,
1457 	MSR_IA32_SPEC_CTRL, MSR_IA32_TSX_CTRL,
1458 	MSR_IA32_RTIT_CTL, MSR_IA32_RTIT_STATUS, MSR_IA32_RTIT_CR3_MATCH,
1459 	MSR_IA32_RTIT_OUTPUT_BASE, MSR_IA32_RTIT_OUTPUT_MASK,
1460 	MSR_IA32_RTIT_ADDR0_A, MSR_IA32_RTIT_ADDR0_B,
1461 	MSR_IA32_RTIT_ADDR1_A, MSR_IA32_RTIT_ADDR1_B,
1462 	MSR_IA32_RTIT_ADDR2_A, MSR_IA32_RTIT_ADDR2_B,
1463 	MSR_IA32_RTIT_ADDR3_A, MSR_IA32_RTIT_ADDR3_B,
1464 	MSR_IA32_UMWAIT_CONTROL,
1465 
1466 	MSR_IA32_XFD, MSR_IA32_XFD_ERR,
1467 };
1468 
1469 static const u32 msrs_to_save_pmu[] = {
1470 	MSR_ARCH_PERFMON_FIXED_CTR0, MSR_ARCH_PERFMON_FIXED_CTR1,
1471 	MSR_ARCH_PERFMON_FIXED_CTR0 + 2,
1472 	MSR_CORE_PERF_FIXED_CTR_CTRL, MSR_CORE_PERF_GLOBAL_STATUS,
1473 	MSR_CORE_PERF_GLOBAL_CTRL, MSR_CORE_PERF_GLOBAL_OVF_CTRL,
1474 	MSR_IA32_PEBS_ENABLE, MSR_IA32_DS_AREA, MSR_PEBS_DATA_CFG,
1475 
1476 	/* This part of MSRs should match KVM_INTEL_PMC_MAX_GENERIC. */
1477 	MSR_ARCH_PERFMON_PERFCTR0, MSR_ARCH_PERFMON_PERFCTR1,
1478 	MSR_ARCH_PERFMON_PERFCTR0 + 2, MSR_ARCH_PERFMON_PERFCTR0 + 3,
1479 	MSR_ARCH_PERFMON_PERFCTR0 + 4, MSR_ARCH_PERFMON_PERFCTR0 + 5,
1480 	MSR_ARCH_PERFMON_PERFCTR0 + 6, MSR_ARCH_PERFMON_PERFCTR0 + 7,
1481 	MSR_ARCH_PERFMON_EVENTSEL0, MSR_ARCH_PERFMON_EVENTSEL1,
1482 	MSR_ARCH_PERFMON_EVENTSEL0 + 2, MSR_ARCH_PERFMON_EVENTSEL0 + 3,
1483 	MSR_ARCH_PERFMON_EVENTSEL0 + 4, MSR_ARCH_PERFMON_EVENTSEL0 + 5,
1484 	MSR_ARCH_PERFMON_EVENTSEL0 + 6, MSR_ARCH_PERFMON_EVENTSEL0 + 7,
1485 
1486 	MSR_K7_EVNTSEL0, MSR_K7_EVNTSEL1, MSR_K7_EVNTSEL2, MSR_K7_EVNTSEL3,
1487 	MSR_K7_PERFCTR0, MSR_K7_PERFCTR1, MSR_K7_PERFCTR2, MSR_K7_PERFCTR3,
1488 
1489 	/* This part of MSRs should match KVM_AMD_PMC_MAX_GENERIC. */
1490 	MSR_F15H_PERF_CTL0, MSR_F15H_PERF_CTL1, MSR_F15H_PERF_CTL2,
1491 	MSR_F15H_PERF_CTL3, MSR_F15H_PERF_CTL4, MSR_F15H_PERF_CTL5,
1492 	MSR_F15H_PERF_CTR0, MSR_F15H_PERF_CTR1, MSR_F15H_PERF_CTR2,
1493 	MSR_F15H_PERF_CTR3, MSR_F15H_PERF_CTR4, MSR_F15H_PERF_CTR5,
1494 
1495 	MSR_AMD64_PERF_CNTR_GLOBAL_CTL,
1496 	MSR_AMD64_PERF_CNTR_GLOBAL_STATUS,
1497 	MSR_AMD64_PERF_CNTR_GLOBAL_STATUS_CLR,
1498 };
1499 
1500 static u32 msrs_to_save[ARRAY_SIZE(msrs_to_save_base) +
1501 			ARRAY_SIZE(msrs_to_save_pmu)];
1502 static unsigned num_msrs_to_save;
1503 
1504 static const u32 emulated_msrs_all[] = {
1505 	MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
1506 	MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
1507 
1508 #ifdef CONFIG_KVM_HYPERV
1509 	HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
1510 	HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC,
1511 	HV_X64_MSR_TSC_FREQUENCY, HV_X64_MSR_APIC_FREQUENCY,
1512 	HV_X64_MSR_CRASH_P0, HV_X64_MSR_CRASH_P1, HV_X64_MSR_CRASH_P2,
1513 	HV_X64_MSR_CRASH_P3, HV_X64_MSR_CRASH_P4, HV_X64_MSR_CRASH_CTL,
1514 	HV_X64_MSR_RESET,
1515 	HV_X64_MSR_VP_INDEX,
1516 	HV_X64_MSR_VP_RUNTIME,
1517 	HV_X64_MSR_SCONTROL,
1518 	HV_X64_MSR_STIMER0_CONFIG,
1519 	HV_X64_MSR_VP_ASSIST_PAGE,
1520 	HV_X64_MSR_REENLIGHTENMENT_CONTROL, HV_X64_MSR_TSC_EMULATION_CONTROL,
1521 	HV_X64_MSR_TSC_EMULATION_STATUS, HV_X64_MSR_TSC_INVARIANT_CONTROL,
1522 	HV_X64_MSR_SYNDBG_OPTIONS,
1523 	HV_X64_MSR_SYNDBG_CONTROL, HV_X64_MSR_SYNDBG_STATUS,
1524 	HV_X64_MSR_SYNDBG_SEND_BUFFER, HV_X64_MSR_SYNDBG_RECV_BUFFER,
1525 	HV_X64_MSR_SYNDBG_PENDING_BUFFER,
1526 #endif
1527 
1528 	MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
1529 	MSR_KVM_PV_EOI_EN, MSR_KVM_ASYNC_PF_INT, MSR_KVM_ASYNC_PF_ACK,
1530 
1531 	MSR_IA32_TSC_ADJUST,
1532 	MSR_IA32_TSC_DEADLINE,
1533 	MSR_IA32_ARCH_CAPABILITIES,
1534 	MSR_IA32_PERF_CAPABILITIES,
1535 	MSR_IA32_MISC_ENABLE,
1536 	MSR_IA32_MCG_STATUS,
1537 	MSR_IA32_MCG_CTL,
1538 	MSR_IA32_MCG_EXT_CTL,
1539 	MSR_IA32_SMBASE,
1540 	MSR_SMI_COUNT,
1541 	MSR_PLATFORM_INFO,
1542 	MSR_MISC_FEATURES_ENABLES,
1543 	MSR_AMD64_VIRT_SPEC_CTRL,
1544 	MSR_AMD64_TSC_RATIO,
1545 	MSR_IA32_POWER_CTL,
1546 	MSR_IA32_UCODE_REV,
1547 
1548 	/*
1549 	 * KVM always supports the "true" VMX control MSRs, even if the host
1550 	 * does not.  The VMX MSRs as a whole are considered "emulated" as KVM
1551 	 * doesn't strictly require them to exist in the host (ignoring that
1552 	 * KVM would refuse to load in the first place if the core set of MSRs
1553 	 * aren't supported).
1554 	 */
1555 	MSR_IA32_VMX_BASIC,
1556 	MSR_IA32_VMX_TRUE_PINBASED_CTLS,
1557 	MSR_IA32_VMX_TRUE_PROCBASED_CTLS,
1558 	MSR_IA32_VMX_TRUE_EXIT_CTLS,
1559 	MSR_IA32_VMX_TRUE_ENTRY_CTLS,
1560 	MSR_IA32_VMX_MISC,
1561 	MSR_IA32_VMX_CR0_FIXED0,
1562 	MSR_IA32_VMX_CR4_FIXED0,
1563 	MSR_IA32_VMX_VMCS_ENUM,
1564 	MSR_IA32_VMX_PROCBASED_CTLS2,
1565 	MSR_IA32_VMX_EPT_VPID_CAP,
1566 	MSR_IA32_VMX_VMFUNC,
1567 
1568 	MSR_K7_HWCR,
1569 	MSR_KVM_POLL_CONTROL,
1570 };
1571 
1572 static u32 emulated_msrs[ARRAY_SIZE(emulated_msrs_all)];
1573 static unsigned num_emulated_msrs;
1574 
1575 /*
1576  * List of MSRs that control the existence of MSR-based features, i.e. MSRs
1577  * that are effectively CPUID leafs.  VMX MSRs are also included in the set of
1578  * feature MSRs, but are handled separately to allow expedited lookups.
1579  */
1580 static const u32 msr_based_features_all_except_vmx[] = {
1581 	MSR_AMD64_DE_CFG,
1582 	MSR_IA32_UCODE_REV,
1583 	MSR_IA32_ARCH_CAPABILITIES,
1584 	MSR_IA32_PERF_CAPABILITIES,
1585 };
1586 
1587 static u32 msr_based_features[ARRAY_SIZE(msr_based_features_all_except_vmx) +
1588 			      (KVM_LAST_EMULATED_VMX_MSR - KVM_FIRST_EMULATED_VMX_MSR + 1)];
1589 static unsigned int num_msr_based_features;
1590 
1591 /*
1592  * All feature MSRs except uCode revID, which tracks the currently loaded uCode
1593  * patch, are immutable once the vCPU model is defined.
1594  */
1595 static bool kvm_is_immutable_feature_msr(u32 msr)
1596 {
1597 	int i;
1598 
1599 	if (msr >= KVM_FIRST_EMULATED_VMX_MSR && msr <= KVM_LAST_EMULATED_VMX_MSR)
1600 		return true;
1601 
1602 	for (i = 0; i < ARRAY_SIZE(msr_based_features_all_except_vmx); i++) {
1603 		if (msr == msr_based_features_all_except_vmx[i])
1604 			return msr != MSR_IA32_UCODE_REV;
1605 	}
1606 
1607 	return false;
1608 }
1609 
1610 /*
1611  * Some IA32_ARCH_CAPABILITIES bits have dependencies on MSRs that KVM
1612  * does not yet virtualize. These include:
1613  *   10 - MISC_PACKAGE_CTRLS
1614  *   11 - ENERGY_FILTERING_CTL
1615  *   12 - DOITM
1616  *   18 - FB_CLEAR_CTRL
1617  *   21 - XAPIC_DISABLE_STATUS
1618  *   23 - OVERCLOCKING_STATUS
1619  */
1620 
1621 #define KVM_SUPPORTED_ARCH_CAP \
1622 	(ARCH_CAP_RDCL_NO | ARCH_CAP_IBRS_ALL | ARCH_CAP_RSBA | \
1623 	 ARCH_CAP_SKIP_VMENTRY_L1DFLUSH | ARCH_CAP_SSB_NO | ARCH_CAP_MDS_NO | \
1624 	 ARCH_CAP_PSCHANGE_MC_NO | ARCH_CAP_TSX_CTRL_MSR | ARCH_CAP_TAA_NO | \
1625 	 ARCH_CAP_SBDR_SSDP_NO | ARCH_CAP_FBSDP_NO | ARCH_CAP_PSDP_NO | \
1626 	 ARCH_CAP_FB_CLEAR | ARCH_CAP_RRSBA | ARCH_CAP_PBRSB_NO | ARCH_CAP_GDS_NO | \
1627 	 ARCH_CAP_RFDS_NO | ARCH_CAP_RFDS_CLEAR | ARCH_CAP_BHI_NO)
1628 
1629 static u64 kvm_get_arch_capabilities(void)
1630 {
1631 	u64 data = host_arch_capabilities & KVM_SUPPORTED_ARCH_CAP;
1632 
1633 	/*
1634 	 * If nx_huge_pages is enabled, KVM's shadow paging will ensure that
1635 	 * the nested hypervisor runs with NX huge pages.  If it is not,
1636 	 * L1 is anyway vulnerable to ITLB_MULTIHIT exploits from other
1637 	 * L1 guests, so it need not worry about its own (L2) guests.
1638 	 */
1639 	data |= ARCH_CAP_PSCHANGE_MC_NO;
1640 
1641 	/*
1642 	 * If we're doing cache flushes (either "always" or "cond")
1643 	 * we will do one whenever the guest does a vmlaunch/vmresume.
1644 	 * If an outer hypervisor is doing the cache flush for us
1645 	 * (ARCH_CAP_SKIP_VMENTRY_L1DFLUSH), we can safely pass that
1646 	 * capability to the guest too, and if EPT is disabled we're not
1647 	 * vulnerable.  Overall, only VMENTER_L1D_FLUSH_NEVER will
1648 	 * require a nested hypervisor to do a flush of its own.
1649 	 */
1650 	if (l1tf_vmx_mitigation != VMENTER_L1D_FLUSH_NEVER)
1651 		data |= ARCH_CAP_SKIP_VMENTRY_L1DFLUSH;
1652 
1653 	if (!boot_cpu_has_bug(X86_BUG_CPU_MELTDOWN))
1654 		data |= ARCH_CAP_RDCL_NO;
1655 	if (!boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS))
1656 		data |= ARCH_CAP_SSB_NO;
1657 	if (!boot_cpu_has_bug(X86_BUG_MDS))
1658 		data |= ARCH_CAP_MDS_NO;
1659 	if (!boot_cpu_has_bug(X86_BUG_RFDS))
1660 		data |= ARCH_CAP_RFDS_NO;
1661 
1662 	if (!boot_cpu_has(X86_FEATURE_RTM)) {
1663 		/*
1664 		 * If RTM=0 because the kernel has disabled TSX, the host might
1665 		 * have TAA_NO or TSX_CTRL.  Clear TAA_NO (the guest sees RTM=0
1666 		 * and therefore knows that there cannot be TAA) but keep
1667 		 * TSX_CTRL: some buggy userspaces leave it set on tsx=on hosts,
1668 		 * and we want to allow migrating those guests to tsx=off hosts.
1669 		 */
1670 		data &= ~ARCH_CAP_TAA_NO;
1671 	} else if (!boot_cpu_has_bug(X86_BUG_TAA)) {
1672 		data |= ARCH_CAP_TAA_NO;
1673 	} else {
1674 		/*
1675 		 * Nothing to do here; we emulate TSX_CTRL if present on the
1676 		 * host so the guest can choose between disabling TSX or
1677 		 * using VERW to clear CPU buffers.
1678 		 */
1679 	}
1680 
1681 	if (!boot_cpu_has_bug(X86_BUG_GDS) || gds_ucode_mitigated())
1682 		data |= ARCH_CAP_GDS_NO;
1683 
1684 	return data;
1685 }
1686 
1687 static int kvm_get_msr_feature(struct kvm_msr_entry *msr)
1688 {
1689 	switch (msr->index) {
1690 	case MSR_IA32_ARCH_CAPABILITIES:
1691 		msr->data = kvm_get_arch_capabilities();
1692 		break;
1693 	case MSR_IA32_PERF_CAPABILITIES:
1694 		msr->data = kvm_caps.supported_perf_cap;
1695 		break;
1696 	case MSR_IA32_UCODE_REV:
1697 		rdmsrl_safe(msr->index, &msr->data);
1698 		break;
1699 	default:
1700 		return static_call(kvm_x86_get_msr_feature)(msr);
1701 	}
1702 	return 0;
1703 }
1704 
1705 static int do_get_msr_feature(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1706 {
1707 	struct kvm_msr_entry msr;
1708 	int r;
1709 
1710 	/* Unconditionally clear the output for simplicity */
1711 	msr.data = 0;
1712 	msr.index = index;
1713 	r = kvm_get_msr_feature(&msr);
1714 
1715 	if (r == KVM_MSR_RET_INVALID && kvm_msr_ignored_check(index, 0, false))
1716 		r = 0;
1717 
1718 	*data = msr.data;
1719 
1720 	return r;
1721 }
1722 
1723 static bool __kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
1724 {
1725 	if (efer & EFER_AUTOIBRS && !guest_cpuid_has(vcpu, X86_FEATURE_AUTOIBRS))
1726 		return false;
1727 
1728 	if (efer & EFER_FFXSR && !guest_cpuid_has(vcpu, X86_FEATURE_FXSR_OPT))
1729 		return false;
1730 
1731 	if (efer & EFER_SVME && !guest_cpuid_has(vcpu, X86_FEATURE_SVM))
1732 		return false;
1733 
1734 	if (efer & (EFER_LME | EFER_LMA) &&
1735 	    !guest_cpuid_has(vcpu, X86_FEATURE_LM))
1736 		return false;
1737 
1738 	if (efer & EFER_NX && !guest_cpuid_has(vcpu, X86_FEATURE_NX))
1739 		return false;
1740 
1741 	return true;
1742 
1743 }
1744 bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
1745 {
1746 	if (efer & efer_reserved_bits)
1747 		return false;
1748 
1749 	return __kvm_valid_efer(vcpu, efer);
1750 }
1751 EXPORT_SYMBOL_GPL(kvm_valid_efer);
1752 
1753 static int set_efer(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
1754 {
1755 	u64 old_efer = vcpu->arch.efer;
1756 	u64 efer = msr_info->data;
1757 	int r;
1758 
1759 	if (efer & efer_reserved_bits)
1760 		return 1;
1761 
1762 	if (!msr_info->host_initiated) {
1763 		if (!__kvm_valid_efer(vcpu, efer))
1764 			return 1;
1765 
1766 		if (is_paging(vcpu) &&
1767 		    (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
1768 			return 1;
1769 	}
1770 
1771 	efer &= ~EFER_LMA;
1772 	efer |= vcpu->arch.efer & EFER_LMA;
1773 
1774 	r = static_call(kvm_x86_set_efer)(vcpu, efer);
1775 	if (r) {
1776 		WARN_ON(r > 0);
1777 		return r;
1778 	}
1779 
1780 	if ((efer ^ old_efer) & KVM_MMU_EFER_ROLE_BITS)
1781 		kvm_mmu_reset_context(vcpu);
1782 
1783 	if (!static_cpu_has(X86_FEATURE_XSAVES) &&
1784 	    (efer & EFER_SVME))
1785 		kvm_hv_xsaves_xsavec_maybe_warn(vcpu);
1786 
1787 	return 0;
1788 }
1789 
1790 void kvm_enable_efer_bits(u64 mask)
1791 {
1792        efer_reserved_bits &= ~mask;
1793 }
1794 EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
1795 
1796 bool kvm_msr_allowed(struct kvm_vcpu *vcpu, u32 index, u32 type)
1797 {
1798 	struct kvm_x86_msr_filter *msr_filter;
1799 	struct msr_bitmap_range *ranges;
1800 	struct kvm *kvm = vcpu->kvm;
1801 	bool allowed;
1802 	int idx;
1803 	u32 i;
1804 
1805 	/* x2APIC MSRs do not support filtering. */
1806 	if (index >= 0x800 && index <= 0x8ff)
1807 		return true;
1808 
1809 	idx = srcu_read_lock(&kvm->srcu);
1810 
1811 	msr_filter = srcu_dereference(kvm->arch.msr_filter, &kvm->srcu);
1812 	if (!msr_filter) {
1813 		allowed = true;
1814 		goto out;
1815 	}
1816 
1817 	allowed = msr_filter->default_allow;
1818 	ranges = msr_filter->ranges;
1819 
1820 	for (i = 0; i < msr_filter->count; i++) {
1821 		u32 start = ranges[i].base;
1822 		u32 end = start + ranges[i].nmsrs;
1823 		u32 flags = ranges[i].flags;
1824 		unsigned long *bitmap = ranges[i].bitmap;
1825 
1826 		if ((index >= start) && (index < end) && (flags & type)) {
1827 			allowed = test_bit(index - start, bitmap);
1828 			break;
1829 		}
1830 	}
1831 
1832 out:
1833 	srcu_read_unlock(&kvm->srcu, idx);
1834 
1835 	return allowed;
1836 }
1837 EXPORT_SYMBOL_GPL(kvm_msr_allowed);
1838 
1839 /*
1840  * Write @data into the MSR specified by @index.  Select MSR specific fault
1841  * checks are bypassed if @host_initiated is %true.
1842  * Returns 0 on success, non-0 otherwise.
1843  * Assumes vcpu_load() was already called.
1844  */
1845 static int __kvm_set_msr(struct kvm_vcpu *vcpu, u32 index, u64 data,
1846 			 bool host_initiated)
1847 {
1848 	struct msr_data msr;
1849 
1850 	switch (index) {
1851 	case MSR_FS_BASE:
1852 	case MSR_GS_BASE:
1853 	case MSR_KERNEL_GS_BASE:
1854 	case MSR_CSTAR:
1855 	case MSR_LSTAR:
1856 		if (is_noncanonical_address(data, vcpu))
1857 			return 1;
1858 		break;
1859 	case MSR_IA32_SYSENTER_EIP:
1860 	case MSR_IA32_SYSENTER_ESP:
1861 		/*
1862 		 * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if
1863 		 * non-canonical address is written on Intel but not on
1864 		 * AMD (which ignores the top 32-bits, because it does
1865 		 * not implement 64-bit SYSENTER).
1866 		 *
1867 		 * 64-bit code should hence be able to write a non-canonical
1868 		 * value on AMD.  Making the address canonical ensures that
1869 		 * vmentry does not fail on Intel after writing a non-canonical
1870 		 * value, and that something deterministic happens if the guest
1871 		 * invokes 64-bit SYSENTER.
1872 		 */
1873 		data = __canonical_address(data, vcpu_virt_addr_bits(vcpu));
1874 		break;
1875 	case MSR_TSC_AUX:
1876 		if (!kvm_is_supported_user_return_msr(MSR_TSC_AUX))
1877 			return 1;
1878 
1879 		if (!host_initiated &&
1880 		    !guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP) &&
1881 		    !guest_cpuid_has(vcpu, X86_FEATURE_RDPID))
1882 			return 1;
1883 
1884 		/*
1885 		 * Per Intel's SDM, bits 63:32 are reserved, but AMD's APM has
1886 		 * incomplete and conflicting architectural behavior.  Current
1887 		 * AMD CPUs completely ignore bits 63:32, i.e. they aren't
1888 		 * reserved and always read as zeros.  Enforce Intel's reserved
1889 		 * bits check if and only if the guest CPU is Intel, and clear
1890 		 * the bits in all other cases.  This ensures cross-vendor
1891 		 * migration will provide consistent behavior for the guest.
1892 		 */
1893 		if (guest_cpuid_is_intel(vcpu) && (data >> 32) != 0)
1894 			return 1;
1895 
1896 		data = (u32)data;
1897 		break;
1898 	}
1899 
1900 	msr.data = data;
1901 	msr.index = index;
1902 	msr.host_initiated = host_initiated;
1903 
1904 	return static_call(kvm_x86_set_msr)(vcpu, &msr);
1905 }
1906 
1907 static int kvm_set_msr_ignored_check(struct kvm_vcpu *vcpu,
1908 				     u32 index, u64 data, bool host_initiated)
1909 {
1910 	int ret = __kvm_set_msr(vcpu, index, data, host_initiated);
1911 
1912 	if (ret == KVM_MSR_RET_INVALID)
1913 		if (kvm_msr_ignored_check(index, data, true))
1914 			ret = 0;
1915 
1916 	return ret;
1917 }
1918 
1919 /*
1920  * Read the MSR specified by @index into @data.  Select MSR specific fault
1921  * checks are bypassed if @host_initiated is %true.
1922  * Returns 0 on success, non-0 otherwise.
1923  * Assumes vcpu_load() was already called.
1924  */
1925 int __kvm_get_msr(struct kvm_vcpu *vcpu, u32 index, u64 *data,
1926 		  bool host_initiated)
1927 {
1928 	struct msr_data msr;
1929 	int ret;
1930 
1931 	switch (index) {
1932 	case MSR_TSC_AUX:
1933 		if (!kvm_is_supported_user_return_msr(MSR_TSC_AUX))
1934 			return 1;
1935 
1936 		if (!host_initiated &&
1937 		    !guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP) &&
1938 		    !guest_cpuid_has(vcpu, X86_FEATURE_RDPID))
1939 			return 1;
1940 		break;
1941 	}
1942 
1943 	msr.index = index;
1944 	msr.host_initiated = host_initiated;
1945 
1946 	ret = static_call(kvm_x86_get_msr)(vcpu, &msr);
1947 	if (!ret)
1948 		*data = msr.data;
1949 	return ret;
1950 }
1951 
1952 static int kvm_get_msr_ignored_check(struct kvm_vcpu *vcpu,
1953 				     u32 index, u64 *data, bool host_initiated)
1954 {
1955 	int ret = __kvm_get_msr(vcpu, index, data, host_initiated);
1956 
1957 	if (ret == KVM_MSR_RET_INVALID) {
1958 		/* Unconditionally clear *data for simplicity */
1959 		*data = 0;
1960 		if (kvm_msr_ignored_check(index, 0, false))
1961 			ret = 0;
1962 	}
1963 
1964 	return ret;
1965 }
1966 
1967 static int kvm_get_msr_with_filter(struct kvm_vcpu *vcpu, u32 index, u64 *data)
1968 {
1969 	if (!kvm_msr_allowed(vcpu, index, KVM_MSR_FILTER_READ))
1970 		return KVM_MSR_RET_FILTERED;
1971 	return kvm_get_msr_ignored_check(vcpu, index, data, false);
1972 }
1973 
1974 static int kvm_set_msr_with_filter(struct kvm_vcpu *vcpu, u32 index, u64 data)
1975 {
1976 	if (!kvm_msr_allowed(vcpu, index, KVM_MSR_FILTER_WRITE))
1977 		return KVM_MSR_RET_FILTERED;
1978 	return kvm_set_msr_ignored_check(vcpu, index, data, false);
1979 }
1980 
1981 int kvm_get_msr(struct kvm_vcpu *vcpu, u32 index, u64 *data)
1982 {
1983 	return kvm_get_msr_ignored_check(vcpu, index, data, false);
1984 }
1985 EXPORT_SYMBOL_GPL(kvm_get_msr);
1986 
1987 int kvm_set_msr(struct kvm_vcpu *vcpu, u32 index, u64 data)
1988 {
1989 	return kvm_set_msr_ignored_check(vcpu, index, data, false);
1990 }
1991 EXPORT_SYMBOL_GPL(kvm_set_msr);
1992 
1993 static void complete_userspace_rdmsr(struct kvm_vcpu *vcpu)
1994 {
1995 	if (!vcpu->run->msr.error) {
1996 		kvm_rax_write(vcpu, (u32)vcpu->run->msr.data);
1997 		kvm_rdx_write(vcpu, vcpu->run->msr.data >> 32);
1998 	}
1999 }
2000 
2001 static int complete_emulated_msr_access(struct kvm_vcpu *vcpu)
2002 {
2003 	return complete_emulated_insn_gp(vcpu, vcpu->run->msr.error);
2004 }
2005 
2006 static int complete_emulated_rdmsr(struct kvm_vcpu *vcpu)
2007 {
2008 	complete_userspace_rdmsr(vcpu);
2009 	return complete_emulated_msr_access(vcpu);
2010 }
2011 
2012 static int complete_fast_msr_access(struct kvm_vcpu *vcpu)
2013 {
2014 	return static_call(kvm_x86_complete_emulated_msr)(vcpu, vcpu->run->msr.error);
2015 }
2016 
2017 static int complete_fast_rdmsr(struct kvm_vcpu *vcpu)
2018 {
2019 	complete_userspace_rdmsr(vcpu);
2020 	return complete_fast_msr_access(vcpu);
2021 }
2022 
2023 static u64 kvm_msr_reason(int r)
2024 {
2025 	switch (r) {
2026 	case KVM_MSR_RET_INVALID:
2027 		return KVM_MSR_EXIT_REASON_UNKNOWN;
2028 	case KVM_MSR_RET_FILTERED:
2029 		return KVM_MSR_EXIT_REASON_FILTER;
2030 	default:
2031 		return KVM_MSR_EXIT_REASON_INVAL;
2032 	}
2033 }
2034 
2035 static int kvm_msr_user_space(struct kvm_vcpu *vcpu, u32 index,
2036 			      u32 exit_reason, u64 data,
2037 			      int (*completion)(struct kvm_vcpu *vcpu),
2038 			      int r)
2039 {
2040 	u64 msr_reason = kvm_msr_reason(r);
2041 
2042 	/* Check if the user wanted to know about this MSR fault */
2043 	if (!(vcpu->kvm->arch.user_space_msr_mask & msr_reason))
2044 		return 0;
2045 
2046 	vcpu->run->exit_reason = exit_reason;
2047 	vcpu->run->msr.error = 0;
2048 	memset(vcpu->run->msr.pad, 0, sizeof(vcpu->run->msr.pad));
2049 	vcpu->run->msr.reason = msr_reason;
2050 	vcpu->run->msr.index = index;
2051 	vcpu->run->msr.data = data;
2052 	vcpu->arch.complete_userspace_io = completion;
2053 
2054 	return 1;
2055 }
2056 
2057 int kvm_emulate_rdmsr(struct kvm_vcpu *vcpu)
2058 {
2059 	u32 ecx = kvm_rcx_read(vcpu);
2060 	u64 data;
2061 	int r;
2062 
2063 	r = kvm_get_msr_with_filter(vcpu, ecx, &data);
2064 
2065 	if (!r) {
2066 		trace_kvm_msr_read(ecx, data);
2067 
2068 		kvm_rax_write(vcpu, data & -1u);
2069 		kvm_rdx_write(vcpu, (data >> 32) & -1u);
2070 	} else {
2071 		/* MSR read failed? See if we should ask user space */
2072 		if (kvm_msr_user_space(vcpu, ecx, KVM_EXIT_X86_RDMSR, 0,
2073 				       complete_fast_rdmsr, r))
2074 			return 0;
2075 		trace_kvm_msr_read_ex(ecx);
2076 	}
2077 
2078 	return static_call(kvm_x86_complete_emulated_msr)(vcpu, r);
2079 }
2080 EXPORT_SYMBOL_GPL(kvm_emulate_rdmsr);
2081 
2082 int kvm_emulate_wrmsr(struct kvm_vcpu *vcpu)
2083 {
2084 	u32 ecx = kvm_rcx_read(vcpu);
2085 	u64 data = kvm_read_edx_eax(vcpu);
2086 	int r;
2087 
2088 	r = kvm_set_msr_with_filter(vcpu, ecx, data);
2089 
2090 	if (!r) {
2091 		trace_kvm_msr_write(ecx, data);
2092 	} else {
2093 		/* MSR write failed? See if we should ask user space */
2094 		if (kvm_msr_user_space(vcpu, ecx, KVM_EXIT_X86_WRMSR, data,
2095 				       complete_fast_msr_access, r))
2096 			return 0;
2097 		/* Signal all other negative errors to userspace */
2098 		if (r < 0)
2099 			return r;
2100 		trace_kvm_msr_write_ex(ecx, data);
2101 	}
2102 
2103 	return static_call(kvm_x86_complete_emulated_msr)(vcpu, r);
2104 }
2105 EXPORT_SYMBOL_GPL(kvm_emulate_wrmsr);
2106 
2107 int kvm_emulate_as_nop(struct kvm_vcpu *vcpu)
2108 {
2109 	return kvm_skip_emulated_instruction(vcpu);
2110 }
2111 
2112 int kvm_emulate_invd(struct kvm_vcpu *vcpu)
2113 {
2114 	/* Treat an INVD instruction as a NOP and just skip it. */
2115 	return kvm_emulate_as_nop(vcpu);
2116 }
2117 EXPORT_SYMBOL_GPL(kvm_emulate_invd);
2118 
2119 int kvm_handle_invalid_op(struct kvm_vcpu *vcpu)
2120 {
2121 	kvm_queue_exception(vcpu, UD_VECTOR);
2122 	return 1;
2123 }
2124 EXPORT_SYMBOL_GPL(kvm_handle_invalid_op);
2125 
2126 
2127 static int kvm_emulate_monitor_mwait(struct kvm_vcpu *vcpu, const char *insn)
2128 {
2129 	if (!kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_MWAIT_NEVER_UD_FAULTS) &&
2130 	    !guest_cpuid_has(vcpu, X86_FEATURE_MWAIT))
2131 		return kvm_handle_invalid_op(vcpu);
2132 
2133 	pr_warn_once("%s instruction emulated as NOP!\n", insn);
2134 	return kvm_emulate_as_nop(vcpu);
2135 }
2136 int kvm_emulate_mwait(struct kvm_vcpu *vcpu)
2137 {
2138 	return kvm_emulate_monitor_mwait(vcpu, "MWAIT");
2139 }
2140 EXPORT_SYMBOL_GPL(kvm_emulate_mwait);
2141 
2142 int kvm_emulate_monitor(struct kvm_vcpu *vcpu)
2143 {
2144 	return kvm_emulate_monitor_mwait(vcpu, "MONITOR");
2145 }
2146 EXPORT_SYMBOL_GPL(kvm_emulate_monitor);
2147 
2148 static inline bool kvm_vcpu_exit_request(struct kvm_vcpu *vcpu)
2149 {
2150 	xfer_to_guest_mode_prepare();
2151 	return vcpu->mode == EXITING_GUEST_MODE || kvm_request_pending(vcpu) ||
2152 		xfer_to_guest_mode_work_pending();
2153 }
2154 
2155 /*
2156  * The fast path for frequent and performance sensitive wrmsr emulation,
2157  * i.e. the sending of IPI, sending IPI early in the VM-Exit flow reduces
2158  * the latency of virtual IPI by avoiding the expensive bits of transitioning
2159  * from guest to host, e.g. reacquiring KVM's SRCU lock. In contrast to the
2160  * other cases which must be called after interrupts are enabled on the host.
2161  */
2162 static int handle_fastpath_set_x2apic_icr_irqoff(struct kvm_vcpu *vcpu, u64 data)
2163 {
2164 	if (!lapic_in_kernel(vcpu) || !apic_x2apic_mode(vcpu->arch.apic))
2165 		return 1;
2166 
2167 	if (((data & APIC_SHORT_MASK) == APIC_DEST_NOSHORT) &&
2168 	    ((data & APIC_DEST_MASK) == APIC_DEST_PHYSICAL) &&
2169 	    ((data & APIC_MODE_MASK) == APIC_DM_FIXED) &&
2170 	    ((u32)(data >> 32) != X2APIC_BROADCAST))
2171 		return kvm_x2apic_icr_write(vcpu->arch.apic, data);
2172 
2173 	return 1;
2174 }
2175 
2176 static int handle_fastpath_set_tscdeadline(struct kvm_vcpu *vcpu, u64 data)
2177 {
2178 	if (!kvm_can_use_hv_timer(vcpu))
2179 		return 1;
2180 
2181 	kvm_set_lapic_tscdeadline_msr(vcpu, data);
2182 	return 0;
2183 }
2184 
2185 fastpath_t handle_fastpath_set_msr_irqoff(struct kvm_vcpu *vcpu)
2186 {
2187 	u32 msr = kvm_rcx_read(vcpu);
2188 	u64 data;
2189 	fastpath_t ret = EXIT_FASTPATH_NONE;
2190 
2191 	kvm_vcpu_srcu_read_lock(vcpu);
2192 
2193 	switch (msr) {
2194 	case APIC_BASE_MSR + (APIC_ICR >> 4):
2195 		data = kvm_read_edx_eax(vcpu);
2196 		if (!handle_fastpath_set_x2apic_icr_irqoff(vcpu, data)) {
2197 			kvm_skip_emulated_instruction(vcpu);
2198 			ret = EXIT_FASTPATH_EXIT_HANDLED;
2199 		}
2200 		break;
2201 	case MSR_IA32_TSC_DEADLINE:
2202 		data = kvm_read_edx_eax(vcpu);
2203 		if (!handle_fastpath_set_tscdeadline(vcpu, data)) {
2204 			kvm_skip_emulated_instruction(vcpu);
2205 			ret = EXIT_FASTPATH_REENTER_GUEST;
2206 		}
2207 		break;
2208 	default:
2209 		break;
2210 	}
2211 
2212 	if (ret != EXIT_FASTPATH_NONE)
2213 		trace_kvm_msr_write(msr, data);
2214 
2215 	kvm_vcpu_srcu_read_unlock(vcpu);
2216 
2217 	return ret;
2218 }
2219 EXPORT_SYMBOL_GPL(handle_fastpath_set_msr_irqoff);
2220 
2221 /*
2222  * Adapt set_msr() to msr_io()'s calling convention
2223  */
2224 static int do_get_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
2225 {
2226 	return kvm_get_msr_ignored_check(vcpu, index, data, true);
2227 }
2228 
2229 static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
2230 {
2231 	u64 val;
2232 
2233 	/*
2234 	 * Disallow writes to immutable feature MSRs after KVM_RUN.  KVM does
2235 	 * not support modifying the guest vCPU model on the fly, e.g. changing
2236 	 * the nVMX capabilities while L2 is running is nonsensical.  Allow
2237 	 * writes of the same value, e.g. to allow userspace to blindly stuff
2238 	 * all MSRs when emulating RESET.
2239 	 */
2240 	if (kvm_vcpu_has_run(vcpu) && kvm_is_immutable_feature_msr(index) &&
2241 	    (do_get_msr(vcpu, index, &val) || *data != val))
2242 		return -EINVAL;
2243 
2244 	return kvm_set_msr_ignored_check(vcpu, index, *data, true);
2245 }
2246 
2247 #ifdef CONFIG_X86_64
2248 struct pvclock_clock {
2249 	int vclock_mode;
2250 	u64 cycle_last;
2251 	u64 mask;
2252 	u32 mult;
2253 	u32 shift;
2254 	u64 base_cycles;
2255 	u64 offset;
2256 };
2257 
2258 struct pvclock_gtod_data {
2259 	seqcount_t	seq;
2260 
2261 	struct pvclock_clock clock; /* extract of a clocksource struct */
2262 	struct pvclock_clock raw_clock; /* extract of a clocksource struct */
2263 
2264 	ktime_t		offs_boot;
2265 	u64		wall_time_sec;
2266 };
2267 
2268 static struct pvclock_gtod_data pvclock_gtod_data;
2269 
2270 static void update_pvclock_gtod(struct timekeeper *tk)
2271 {
2272 	struct pvclock_gtod_data *vdata = &pvclock_gtod_data;
2273 
2274 	write_seqcount_begin(&vdata->seq);
2275 
2276 	/* copy pvclock gtod data */
2277 	vdata->clock.vclock_mode	= tk->tkr_mono.clock->vdso_clock_mode;
2278 	vdata->clock.cycle_last		= tk->tkr_mono.cycle_last;
2279 	vdata->clock.mask		= tk->tkr_mono.mask;
2280 	vdata->clock.mult		= tk->tkr_mono.mult;
2281 	vdata->clock.shift		= tk->tkr_mono.shift;
2282 	vdata->clock.base_cycles	= tk->tkr_mono.xtime_nsec;
2283 	vdata->clock.offset		= tk->tkr_mono.base;
2284 
2285 	vdata->raw_clock.vclock_mode	= tk->tkr_raw.clock->vdso_clock_mode;
2286 	vdata->raw_clock.cycle_last	= tk->tkr_raw.cycle_last;
2287 	vdata->raw_clock.mask		= tk->tkr_raw.mask;
2288 	vdata->raw_clock.mult		= tk->tkr_raw.mult;
2289 	vdata->raw_clock.shift		= tk->tkr_raw.shift;
2290 	vdata->raw_clock.base_cycles	= tk->tkr_raw.xtime_nsec;
2291 	vdata->raw_clock.offset		= tk->tkr_raw.base;
2292 
2293 	vdata->wall_time_sec            = tk->xtime_sec;
2294 
2295 	vdata->offs_boot		= tk->offs_boot;
2296 
2297 	write_seqcount_end(&vdata->seq);
2298 }
2299 
2300 static s64 get_kvmclock_base_ns(void)
2301 {
2302 	/* Count up from boot time, but with the frequency of the raw clock.  */
2303 	return ktime_to_ns(ktime_add(ktime_get_raw(), pvclock_gtod_data.offs_boot));
2304 }
2305 #else
2306 static s64 get_kvmclock_base_ns(void)
2307 {
2308 	/* Master clock not used, so we can just use CLOCK_BOOTTIME.  */
2309 	return ktime_get_boottime_ns();
2310 }
2311 #endif
2312 
2313 static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock, int sec_hi_ofs)
2314 {
2315 	int version;
2316 	int r;
2317 	struct pvclock_wall_clock wc;
2318 	u32 wc_sec_hi;
2319 	u64 wall_nsec;
2320 
2321 	if (!wall_clock)
2322 		return;
2323 
2324 	r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
2325 	if (r)
2326 		return;
2327 
2328 	if (version & 1)
2329 		++version;  /* first time write, random junk */
2330 
2331 	++version;
2332 
2333 	if (kvm_write_guest(kvm, wall_clock, &version, sizeof(version)))
2334 		return;
2335 
2336 	wall_nsec = kvm_get_wall_clock_epoch(kvm);
2337 
2338 	wc.nsec = do_div(wall_nsec, NSEC_PER_SEC);
2339 	wc.sec = (u32)wall_nsec; /* overflow in 2106 guest time */
2340 	wc.version = version;
2341 
2342 	kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
2343 
2344 	if (sec_hi_ofs) {
2345 		wc_sec_hi = wall_nsec >> 32;
2346 		kvm_write_guest(kvm, wall_clock + sec_hi_ofs,
2347 				&wc_sec_hi, sizeof(wc_sec_hi));
2348 	}
2349 
2350 	version++;
2351 	kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
2352 }
2353 
2354 static void kvm_write_system_time(struct kvm_vcpu *vcpu, gpa_t system_time,
2355 				  bool old_msr, bool host_initiated)
2356 {
2357 	struct kvm_arch *ka = &vcpu->kvm->arch;
2358 
2359 	if (vcpu->vcpu_id == 0 && !host_initiated) {
2360 		if (ka->boot_vcpu_runs_old_kvmclock != old_msr)
2361 			kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
2362 
2363 		ka->boot_vcpu_runs_old_kvmclock = old_msr;
2364 	}
2365 
2366 	vcpu->arch.time = system_time;
2367 	kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
2368 
2369 	/* we verify if the enable bit is set... */
2370 	if (system_time & 1)
2371 		kvm_gpc_activate(&vcpu->arch.pv_time, system_time & ~1ULL,
2372 				 sizeof(struct pvclock_vcpu_time_info));
2373 	else
2374 		kvm_gpc_deactivate(&vcpu->arch.pv_time);
2375 
2376 	return;
2377 }
2378 
2379 static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
2380 {
2381 	do_shl32_div32(dividend, divisor);
2382 	return dividend;
2383 }
2384 
2385 static void kvm_get_time_scale(uint64_t scaled_hz, uint64_t base_hz,
2386 			       s8 *pshift, u32 *pmultiplier)
2387 {
2388 	uint64_t scaled64;
2389 	int32_t  shift = 0;
2390 	uint64_t tps64;
2391 	uint32_t tps32;
2392 
2393 	tps64 = base_hz;
2394 	scaled64 = scaled_hz;
2395 	while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
2396 		tps64 >>= 1;
2397 		shift--;
2398 	}
2399 
2400 	tps32 = (uint32_t)tps64;
2401 	while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
2402 		if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
2403 			scaled64 >>= 1;
2404 		else
2405 			tps32 <<= 1;
2406 		shift++;
2407 	}
2408 
2409 	*pshift = shift;
2410 	*pmultiplier = div_frac(scaled64, tps32);
2411 }
2412 
2413 #ifdef CONFIG_X86_64
2414 static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0);
2415 #endif
2416 
2417 static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
2418 static unsigned long max_tsc_khz;
2419 
2420 static u32 adjust_tsc_khz(u32 khz, s32 ppm)
2421 {
2422 	u64 v = (u64)khz * (1000000 + ppm);
2423 	do_div(v, 1000000);
2424 	return v;
2425 }
2426 
2427 static void kvm_vcpu_write_tsc_multiplier(struct kvm_vcpu *vcpu, u64 l1_multiplier);
2428 
2429 static int set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
2430 {
2431 	u64 ratio;
2432 
2433 	/* Guest TSC same frequency as host TSC? */
2434 	if (!scale) {
2435 		kvm_vcpu_write_tsc_multiplier(vcpu, kvm_caps.default_tsc_scaling_ratio);
2436 		return 0;
2437 	}
2438 
2439 	/* TSC scaling supported? */
2440 	if (!kvm_caps.has_tsc_control) {
2441 		if (user_tsc_khz > tsc_khz) {
2442 			vcpu->arch.tsc_catchup = 1;
2443 			vcpu->arch.tsc_always_catchup = 1;
2444 			return 0;
2445 		} else {
2446 			pr_warn_ratelimited("user requested TSC rate below hardware speed\n");
2447 			return -1;
2448 		}
2449 	}
2450 
2451 	/* TSC scaling required  - calculate ratio */
2452 	ratio = mul_u64_u32_div(1ULL << kvm_caps.tsc_scaling_ratio_frac_bits,
2453 				user_tsc_khz, tsc_khz);
2454 
2455 	if (ratio == 0 || ratio >= kvm_caps.max_tsc_scaling_ratio) {
2456 		pr_warn_ratelimited("Invalid TSC scaling ratio - virtual-tsc-khz=%u\n",
2457 			            user_tsc_khz);
2458 		return -1;
2459 	}
2460 
2461 	kvm_vcpu_write_tsc_multiplier(vcpu, ratio);
2462 	return 0;
2463 }
2464 
2465 static int kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz)
2466 {
2467 	u32 thresh_lo, thresh_hi;
2468 	int use_scaling = 0;
2469 
2470 	/* tsc_khz can be zero if TSC calibration fails */
2471 	if (user_tsc_khz == 0) {
2472 		/* set tsc_scaling_ratio to a safe value */
2473 		kvm_vcpu_write_tsc_multiplier(vcpu, kvm_caps.default_tsc_scaling_ratio);
2474 		return -1;
2475 	}
2476 
2477 	/* Compute a scale to convert nanoseconds in TSC cycles */
2478 	kvm_get_time_scale(user_tsc_khz * 1000LL, NSEC_PER_SEC,
2479 			   &vcpu->arch.virtual_tsc_shift,
2480 			   &vcpu->arch.virtual_tsc_mult);
2481 	vcpu->arch.virtual_tsc_khz = user_tsc_khz;
2482 
2483 	/*
2484 	 * Compute the variation in TSC rate which is acceptable
2485 	 * within the range of tolerance and decide if the
2486 	 * rate being applied is within that bounds of the hardware
2487 	 * rate.  If so, no scaling or compensation need be done.
2488 	 */
2489 	thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
2490 	thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
2491 	if (user_tsc_khz < thresh_lo || user_tsc_khz > thresh_hi) {
2492 		pr_debug("requested TSC rate %u falls outside tolerance [%u,%u]\n",
2493 			 user_tsc_khz, thresh_lo, thresh_hi);
2494 		use_scaling = 1;
2495 	}
2496 	return set_tsc_khz(vcpu, user_tsc_khz, use_scaling);
2497 }
2498 
2499 static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
2500 {
2501 	u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
2502 				      vcpu->arch.virtual_tsc_mult,
2503 				      vcpu->arch.virtual_tsc_shift);
2504 	tsc += vcpu->arch.this_tsc_write;
2505 	return tsc;
2506 }
2507 
2508 #ifdef CONFIG_X86_64
2509 static inline bool gtod_is_based_on_tsc(int mode)
2510 {
2511 	return mode == VDSO_CLOCKMODE_TSC || mode == VDSO_CLOCKMODE_HVCLOCK;
2512 }
2513 #endif
2514 
2515 static void kvm_track_tsc_matching(struct kvm_vcpu *vcpu, bool new_generation)
2516 {
2517 #ifdef CONFIG_X86_64
2518 	struct kvm_arch *ka = &vcpu->kvm->arch;
2519 	struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
2520 
2521 	/*
2522 	 * To use the masterclock, the host clocksource must be based on TSC
2523 	 * and all vCPUs must have matching TSCs.  Note, the count for matching
2524 	 * vCPUs doesn't include the reference vCPU, hence "+1".
2525 	 */
2526 	bool use_master_clock = (ka->nr_vcpus_matched_tsc + 1 ==
2527 				 atomic_read(&vcpu->kvm->online_vcpus)) &&
2528 				gtod_is_based_on_tsc(gtod->clock.vclock_mode);
2529 
2530 	/*
2531 	 * Request a masterclock update if the masterclock needs to be toggled
2532 	 * on/off, or when starting a new generation and the masterclock is
2533 	 * enabled (compute_guest_tsc() requires the masterclock snapshot to be
2534 	 * taken _after_ the new generation is created).
2535 	 */
2536 	if ((ka->use_master_clock && new_generation) ||
2537 	    (ka->use_master_clock != use_master_clock))
2538 		kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
2539 
2540 	trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc,
2541 			    atomic_read(&vcpu->kvm->online_vcpus),
2542 		            ka->use_master_clock, gtod->clock.vclock_mode);
2543 #endif
2544 }
2545 
2546 /*
2547  * Multiply tsc by a fixed point number represented by ratio.
2548  *
2549  * The most significant 64-N bits (mult) of ratio represent the
2550  * integral part of the fixed point number; the remaining N bits
2551  * (frac) represent the fractional part, ie. ratio represents a fixed
2552  * point number (mult + frac * 2^(-N)).
2553  *
2554  * N equals to kvm_caps.tsc_scaling_ratio_frac_bits.
2555  */
2556 static inline u64 __scale_tsc(u64 ratio, u64 tsc)
2557 {
2558 	return mul_u64_u64_shr(tsc, ratio, kvm_caps.tsc_scaling_ratio_frac_bits);
2559 }
2560 
2561 u64 kvm_scale_tsc(u64 tsc, u64 ratio)
2562 {
2563 	u64 _tsc = tsc;
2564 
2565 	if (ratio != kvm_caps.default_tsc_scaling_ratio)
2566 		_tsc = __scale_tsc(ratio, tsc);
2567 
2568 	return _tsc;
2569 }
2570 
2571 static u64 kvm_compute_l1_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
2572 {
2573 	u64 tsc;
2574 
2575 	tsc = kvm_scale_tsc(rdtsc(), vcpu->arch.l1_tsc_scaling_ratio);
2576 
2577 	return target_tsc - tsc;
2578 }
2579 
2580 u64 kvm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
2581 {
2582 	return vcpu->arch.l1_tsc_offset +
2583 		kvm_scale_tsc(host_tsc, vcpu->arch.l1_tsc_scaling_ratio);
2584 }
2585 EXPORT_SYMBOL_GPL(kvm_read_l1_tsc);
2586 
2587 u64 kvm_calc_nested_tsc_offset(u64 l1_offset, u64 l2_offset, u64 l2_multiplier)
2588 {
2589 	u64 nested_offset;
2590 
2591 	if (l2_multiplier == kvm_caps.default_tsc_scaling_ratio)
2592 		nested_offset = l1_offset;
2593 	else
2594 		nested_offset = mul_s64_u64_shr((s64) l1_offset, l2_multiplier,
2595 						kvm_caps.tsc_scaling_ratio_frac_bits);
2596 
2597 	nested_offset += l2_offset;
2598 	return nested_offset;
2599 }
2600 EXPORT_SYMBOL_GPL(kvm_calc_nested_tsc_offset);
2601 
2602 u64 kvm_calc_nested_tsc_multiplier(u64 l1_multiplier, u64 l2_multiplier)
2603 {
2604 	if (l2_multiplier != kvm_caps.default_tsc_scaling_ratio)
2605 		return mul_u64_u64_shr(l1_multiplier, l2_multiplier,
2606 				       kvm_caps.tsc_scaling_ratio_frac_bits);
2607 
2608 	return l1_multiplier;
2609 }
2610 EXPORT_SYMBOL_GPL(kvm_calc_nested_tsc_multiplier);
2611 
2612 static void kvm_vcpu_write_tsc_offset(struct kvm_vcpu *vcpu, u64 l1_offset)
2613 {
2614 	trace_kvm_write_tsc_offset(vcpu->vcpu_id,
2615 				   vcpu->arch.l1_tsc_offset,
2616 				   l1_offset);
2617 
2618 	vcpu->arch.l1_tsc_offset = l1_offset;
2619 
2620 	/*
2621 	 * If we are here because L1 chose not to trap WRMSR to TSC then
2622 	 * according to the spec this should set L1's TSC (as opposed to
2623 	 * setting L1's offset for L2).
2624 	 */
2625 	if (is_guest_mode(vcpu))
2626 		vcpu->arch.tsc_offset = kvm_calc_nested_tsc_offset(
2627 			l1_offset,
2628 			static_call(kvm_x86_get_l2_tsc_offset)(vcpu),
2629 			static_call(kvm_x86_get_l2_tsc_multiplier)(vcpu));
2630 	else
2631 		vcpu->arch.tsc_offset = l1_offset;
2632 
2633 	static_call(kvm_x86_write_tsc_offset)(vcpu);
2634 }
2635 
2636 static void kvm_vcpu_write_tsc_multiplier(struct kvm_vcpu *vcpu, u64 l1_multiplier)
2637 {
2638 	vcpu->arch.l1_tsc_scaling_ratio = l1_multiplier;
2639 
2640 	/* Userspace is changing the multiplier while L2 is active */
2641 	if (is_guest_mode(vcpu))
2642 		vcpu->arch.tsc_scaling_ratio = kvm_calc_nested_tsc_multiplier(
2643 			l1_multiplier,
2644 			static_call(kvm_x86_get_l2_tsc_multiplier)(vcpu));
2645 	else
2646 		vcpu->arch.tsc_scaling_ratio = l1_multiplier;
2647 
2648 	if (kvm_caps.has_tsc_control)
2649 		static_call(kvm_x86_write_tsc_multiplier)(vcpu);
2650 }
2651 
2652 static inline bool kvm_check_tsc_unstable(void)
2653 {
2654 #ifdef CONFIG_X86_64
2655 	/*
2656 	 * TSC is marked unstable when we're running on Hyper-V,
2657 	 * 'TSC page' clocksource is good.
2658 	 */
2659 	if (pvclock_gtod_data.clock.vclock_mode == VDSO_CLOCKMODE_HVCLOCK)
2660 		return false;
2661 #endif
2662 	return check_tsc_unstable();
2663 }
2664 
2665 /*
2666  * Infers attempts to synchronize the guest's tsc from host writes. Sets the
2667  * offset for the vcpu and tracks the TSC matching generation that the vcpu
2668  * participates in.
2669  */
2670 static void __kvm_synchronize_tsc(struct kvm_vcpu *vcpu, u64 offset, u64 tsc,
2671 				  u64 ns, bool matched)
2672 {
2673 	struct kvm *kvm = vcpu->kvm;
2674 
2675 	lockdep_assert_held(&kvm->arch.tsc_write_lock);
2676 
2677 	/*
2678 	 * We also track th most recent recorded KHZ, write and time to
2679 	 * allow the matching interval to be extended at each write.
2680 	 */
2681 	kvm->arch.last_tsc_nsec = ns;
2682 	kvm->arch.last_tsc_write = tsc;
2683 	kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
2684 	kvm->arch.last_tsc_offset = offset;
2685 
2686 	vcpu->arch.last_guest_tsc = tsc;
2687 
2688 	kvm_vcpu_write_tsc_offset(vcpu, offset);
2689 
2690 	if (!matched) {
2691 		/*
2692 		 * We split periods of matched TSC writes into generations.
2693 		 * For each generation, we track the original measured
2694 		 * nanosecond time, offset, and write, so if TSCs are in
2695 		 * sync, we can match exact offset, and if not, we can match
2696 		 * exact software computation in compute_guest_tsc()
2697 		 *
2698 		 * These values are tracked in kvm->arch.cur_xxx variables.
2699 		 */
2700 		kvm->arch.cur_tsc_generation++;
2701 		kvm->arch.cur_tsc_nsec = ns;
2702 		kvm->arch.cur_tsc_write = tsc;
2703 		kvm->arch.cur_tsc_offset = offset;
2704 		kvm->arch.nr_vcpus_matched_tsc = 0;
2705 	} else if (vcpu->arch.this_tsc_generation != kvm->arch.cur_tsc_generation) {
2706 		kvm->arch.nr_vcpus_matched_tsc++;
2707 	}
2708 
2709 	/* Keep track of which generation this VCPU has synchronized to */
2710 	vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
2711 	vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
2712 	vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
2713 
2714 	kvm_track_tsc_matching(vcpu, !matched);
2715 }
2716 
2717 static void kvm_synchronize_tsc(struct kvm_vcpu *vcpu, u64 *user_value)
2718 {
2719 	u64 data = user_value ? *user_value : 0;
2720 	struct kvm *kvm = vcpu->kvm;
2721 	u64 offset, ns, elapsed;
2722 	unsigned long flags;
2723 	bool matched = false;
2724 	bool synchronizing = false;
2725 
2726 	raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
2727 	offset = kvm_compute_l1_tsc_offset(vcpu, data);
2728 	ns = get_kvmclock_base_ns();
2729 	elapsed = ns - kvm->arch.last_tsc_nsec;
2730 
2731 	if (vcpu->arch.virtual_tsc_khz) {
2732 		if (data == 0) {
2733 			/*
2734 			 * Force synchronization when creating a vCPU, or when
2735 			 * userspace explicitly writes a zero value.
2736 			 */
2737 			synchronizing = true;
2738 		} else if (kvm->arch.user_set_tsc) {
2739 			u64 tsc_exp = kvm->arch.last_tsc_write +
2740 						nsec_to_cycles(vcpu, elapsed);
2741 			u64 tsc_hz = vcpu->arch.virtual_tsc_khz * 1000LL;
2742 			/*
2743 			 * Here lies UAPI baggage: when a user-initiated TSC write has
2744 			 * a small delta (1 second) of virtual cycle time against the
2745 			 * previously set vCPU, we assume that they were intended to be
2746 			 * in sync and the delta was only due to the racy nature of the
2747 			 * legacy API.
2748 			 *
2749 			 * This trick falls down when restoring a guest which genuinely
2750 			 * has been running for less time than the 1 second of imprecision
2751 			 * which we allow for in the legacy API. In this case, the first
2752 			 * value written by userspace (on any vCPU) should not be subject
2753 			 * to this 'correction' to make it sync up with values that only
2754 			 * come from the kernel's default vCPU creation. Make the 1-second
2755 			 * slop hack only trigger if the user_set_tsc flag is already set.
2756 			 */
2757 			synchronizing = data < tsc_exp + tsc_hz &&
2758 					data + tsc_hz > tsc_exp;
2759 		}
2760 	}
2761 
2762 	if (user_value)
2763 		kvm->arch.user_set_tsc = true;
2764 
2765 	/*
2766 	 * For a reliable TSC, we can match TSC offsets, and for an unstable
2767 	 * TSC, we add elapsed time in this computation.  We could let the
2768 	 * compensation code attempt to catch up if we fall behind, but
2769 	 * it's better to try to match offsets from the beginning.
2770          */
2771 	if (synchronizing &&
2772 	    vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
2773 		if (!kvm_check_tsc_unstable()) {
2774 			offset = kvm->arch.cur_tsc_offset;
2775 		} else {
2776 			u64 delta = nsec_to_cycles(vcpu, elapsed);
2777 			data += delta;
2778 			offset = kvm_compute_l1_tsc_offset(vcpu, data);
2779 		}
2780 		matched = true;
2781 	}
2782 
2783 	__kvm_synchronize_tsc(vcpu, offset, data, ns, matched);
2784 	raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
2785 }
2786 
2787 static inline void adjust_tsc_offset_guest(struct kvm_vcpu *vcpu,
2788 					   s64 adjustment)
2789 {
2790 	u64 tsc_offset = vcpu->arch.l1_tsc_offset;
2791 	kvm_vcpu_write_tsc_offset(vcpu, tsc_offset + adjustment);
2792 }
2793 
2794 static inline void adjust_tsc_offset_host(struct kvm_vcpu *vcpu, s64 adjustment)
2795 {
2796 	if (vcpu->arch.l1_tsc_scaling_ratio != kvm_caps.default_tsc_scaling_ratio)
2797 		WARN_ON(adjustment < 0);
2798 	adjustment = kvm_scale_tsc((u64) adjustment,
2799 				   vcpu->arch.l1_tsc_scaling_ratio);
2800 	adjust_tsc_offset_guest(vcpu, adjustment);
2801 }
2802 
2803 #ifdef CONFIG_X86_64
2804 
2805 static u64 read_tsc(void)
2806 {
2807 	u64 ret = (u64)rdtsc_ordered();
2808 	u64 last = pvclock_gtod_data.clock.cycle_last;
2809 
2810 	if (likely(ret >= last))
2811 		return ret;
2812 
2813 	/*
2814 	 * GCC likes to generate cmov here, but this branch is extremely
2815 	 * predictable (it's just a function of time and the likely is
2816 	 * very likely) and there's a data dependence, so force GCC
2817 	 * to generate a branch instead.  I don't barrier() because
2818 	 * we don't actually need a barrier, and if this function
2819 	 * ever gets inlined it will generate worse code.
2820 	 */
2821 	asm volatile ("");
2822 	return last;
2823 }
2824 
2825 static inline u64 vgettsc(struct pvclock_clock *clock, u64 *tsc_timestamp,
2826 			  int *mode)
2827 {
2828 	u64 tsc_pg_val;
2829 	long v;
2830 
2831 	switch (clock->vclock_mode) {
2832 	case VDSO_CLOCKMODE_HVCLOCK:
2833 		if (hv_read_tsc_page_tsc(hv_get_tsc_page(),
2834 					 tsc_timestamp, &tsc_pg_val)) {
2835 			/* TSC page valid */
2836 			*mode = VDSO_CLOCKMODE_HVCLOCK;
2837 			v = (tsc_pg_val - clock->cycle_last) &
2838 				clock->mask;
2839 		} else {
2840 			/* TSC page invalid */
2841 			*mode = VDSO_CLOCKMODE_NONE;
2842 		}
2843 		break;
2844 	case VDSO_CLOCKMODE_TSC:
2845 		*mode = VDSO_CLOCKMODE_TSC;
2846 		*tsc_timestamp = read_tsc();
2847 		v = (*tsc_timestamp - clock->cycle_last) &
2848 			clock->mask;
2849 		break;
2850 	default:
2851 		*mode = VDSO_CLOCKMODE_NONE;
2852 	}
2853 
2854 	if (*mode == VDSO_CLOCKMODE_NONE)
2855 		*tsc_timestamp = v = 0;
2856 
2857 	return v * clock->mult;
2858 }
2859 
2860 /*
2861  * As with get_kvmclock_base_ns(), this counts from boot time, at the
2862  * frequency of CLOCK_MONOTONIC_RAW (hence adding gtos->offs_boot).
2863  */
2864 static int do_kvmclock_base(s64 *t, u64 *tsc_timestamp)
2865 {
2866 	struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
2867 	unsigned long seq;
2868 	int mode;
2869 	u64 ns;
2870 
2871 	do {
2872 		seq = read_seqcount_begin(&gtod->seq);
2873 		ns = gtod->raw_clock.base_cycles;
2874 		ns += vgettsc(&gtod->raw_clock, tsc_timestamp, &mode);
2875 		ns >>= gtod->raw_clock.shift;
2876 		ns += ktime_to_ns(ktime_add(gtod->raw_clock.offset, gtod->offs_boot));
2877 	} while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
2878 	*t = ns;
2879 
2880 	return mode;
2881 }
2882 
2883 /*
2884  * This calculates CLOCK_MONOTONIC at the time of the TSC snapshot, with
2885  * no boot time offset.
2886  */
2887 static int do_monotonic(s64 *t, u64 *tsc_timestamp)
2888 {
2889 	struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
2890 	unsigned long seq;
2891 	int mode;
2892 	u64 ns;
2893 
2894 	do {
2895 		seq = read_seqcount_begin(&gtod->seq);
2896 		ns = gtod->clock.base_cycles;
2897 		ns += vgettsc(&gtod->clock, tsc_timestamp, &mode);
2898 		ns >>= gtod->clock.shift;
2899 		ns += ktime_to_ns(gtod->clock.offset);
2900 	} while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
2901 	*t = ns;
2902 
2903 	return mode;
2904 }
2905 
2906 static int do_realtime(struct timespec64 *ts, u64 *tsc_timestamp)
2907 {
2908 	struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
2909 	unsigned long seq;
2910 	int mode;
2911 	u64 ns;
2912 
2913 	do {
2914 		seq = read_seqcount_begin(&gtod->seq);
2915 		ts->tv_sec = gtod->wall_time_sec;
2916 		ns = gtod->clock.base_cycles;
2917 		ns += vgettsc(&gtod->clock, tsc_timestamp, &mode);
2918 		ns >>= gtod->clock.shift;
2919 	} while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
2920 
2921 	ts->tv_sec += __iter_div_u64_rem(ns, NSEC_PER_SEC, &ns);
2922 	ts->tv_nsec = ns;
2923 
2924 	return mode;
2925 }
2926 
2927 /*
2928  * Calculates the kvmclock_base_ns (CLOCK_MONOTONIC_RAW + boot time) and
2929  * reports the TSC value from which it do so. Returns true if host is
2930  * using TSC based clocksource.
2931  */
2932 static bool kvm_get_time_and_clockread(s64 *kernel_ns, u64 *tsc_timestamp)
2933 {
2934 	/* checked again under seqlock below */
2935 	if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode))
2936 		return false;
2937 
2938 	return gtod_is_based_on_tsc(do_kvmclock_base(kernel_ns,
2939 						     tsc_timestamp));
2940 }
2941 
2942 /*
2943  * Calculates CLOCK_MONOTONIC and reports the TSC value from which it did
2944  * so. Returns true if host is using TSC based clocksource.
2945  */
2946 bool kvm_get_monotonic_and_clockread(s64 *kernel_ns, u64 *tsc_timestamp)
2947 {
2948 	/* checked again under seqlock below */
2949 	if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode))
2950 		return false;
2951 
2952 	return gtod_is_based_on_tsc(do_monotonic(kernel_ns,
2953 						 tsc_timestamp));
2954 }
2955 
2956 /*
2957  * Calculates CLOCK_REALTIME and reports the TSC value from which it did
2958  * so. Returns true if host is using TSC based clocksource.
2959  *
2960  * DO NOT USE this for anything related to migration. You want CLOCK_TAI
2961  * for that.
2962  */
2963 static bool kvm_get_walltime_and_clockread(struct timespec64 *ts,
2964 					   u64 *tsc_timestamp)
2965 {
2966 	/* checked again under seqlock below */
2967 	if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode))
2968 		return false;
2969 
2970 	return gtod_is_based_on_tsc(do_realtime(ts, tsc_timestamp));
2971 }
2972 #endif
2973 
2974 /*
2975  *
2976  * Assuming a stable TSC across physical CPUS, and a stable TSC
2977  * across virtual CPUs, the following condition is possible.
2978  * Each numbered line represents an event visible to both
2979  * CPUs at the next numbered event.
2980  *
2981  * "timespecX" represents host monotonic time. "tscX" represents
2982  * RDTSC value.
2983  *
2984  * 		VCPU0 on CPU0		|	VCPU1 on CPU1
2985  *
2986  * 1.  read timespec0,tsc0
2987  * 2.					| timespec1 = timespec0 + N
2988  * 					| tsc1 = tsc0 + M
2989  * 3. transition to guest		| transition to guest
2990  * 4. ret0 = timespec0 + (rdtsc - tsc0) |
2991  * 5.				        | ret1 = timespec1 + (rdtsc - tsc1)
2992  * 				        | ret1 = timespec0 + N + (rdtsc - (tsc0 + M))
2993  *
2994  * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity:
2995  *
2996  * 	- ret0 < ret1
2997  *	- timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M))
2998  *		...
2999  *	- 0 < N - M => M < N
3000  *
3001  * That is, when timespec0 != timespec1, M < N. Unfortunately that is not
3002  * always the case (the difference between two distinct xtime instances
3003  * might be smaller then the difference between corresponding TSC reads,
3004  * when updating guest vcpus pvclock areas).
3005  *
3006  * To avoid that problem, do not allow visibility of distinct
3007  * system_timestamp/tsc_timestamp values simultaneously: use a master
3008  * copy of host monotonic time values. Update that master copy
3009  * in lockstep.
3010  *
3011  * Rely on synchronization of host TSCs and guest TSCs for monotonicity.
3012  *
3013  */
3014 
3015 static void pvclock_update_vm_gtod_copy(struct kvm *kvm)
3016 {
3017 #ifdef CONFIG_X86_64
3018 	struct kvm_arch *ka = &kvm->arch;
3019 	int vclock_mode;
3020 	bool host_tsc_clocksource, vcpus_matched;
3021 
3022 	lockdep_assert_held(&kvm->arch.tsc_write_lock);
3023 	vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
3024 			atomic_read(&kvm->online_vcpus));
3025 
3026 	/*
3027 	 * If the host uses TSC clock, then passthrough TSC as stable
3028 	 * to the guest.
3029 	 */
3030 	host_tsc_clocksource = kvm_get_time_and_clockread(
3031 					&ka->master_kernel_ns,
3032 					&ka->master_cycle_now);
3033 
3034 	ka->use_master_clock = host_tsc_clocksource && vcpus_matched
3035 				&& !ka->backwards_tsc_observed
3036 				&& !ka->boot_vcpu_runs_old_kvmclock;
3037 
3038 	if (ka->use_master_clock)
3039 		atomic_set(&kvm_guest_has_master_clock, 1);
3040 
3041 	vclock_mode = pvclock_gtod_data.clock.vclock_mode;
3042 	trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode,
3043 					vcpus_matched);
3044 #endif
3045 }
3046 
3047 static void kvm_make_mclock_inprogress_request(struct kvm *kvm)
3048 {
3049 	kvm_make_all_cpus_request(kvm, KVM_REQ_MCLOCK_INPROGRESS);
3050 }
3051 
3052 static void __kvm_start_pvclock_update(struct kvm *kvm)
3053 {
3054 	raw_spin_lock_irq(&kvm->arch.tsc_write_lock);
3055 	write_seqcount_begin(&kvm->arch.pvclock_sc);
3056 }
3057 
3058 static void kvm_start_pvclock_update(struct kvm *kvm)
3059 {
3060 	kvm_make_mclock_inprogress_request(kvm);
3061 
3062 	/* no guest entries from this point */
3063 	__kvm_start_pvclock_update(kvm);
3064 }
3065 
3066 static void kvm_end_pvclock_update(struct kvm *kvm)
3067 {
3068 	struct kvm_arch *ka = &kvm->arch;
3069 	struct kvm_vcpu *vcpu;
3070 	unsigned long i;
3071 
3072 	write_seqcount_end(&ka->pvclock_sc);
3073 	raw_spin_unlock_irq(&ka->tsc_write_lock);
3074 	kvm_for_each_vcpu(i, vcpu, kvm)
3075 		kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3076 
3077 	/* guest entries allowed */
3078 	kvm_for_each_vcpu(i, vcpu, kvm)
3079 		kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu);
3080 }
3081 
3082 static void kvm_update_masterclock(struct kvm *kvm)
3083 {
3084 	kvm_hv_request_tsc_page_update(kvm);
3085 	kvm_start_pvclock_update(kvm);
3086 	pvclock_update_vm_gtod_copy(kvm);
3087 	kvm_end_pvclock_update(kvm);
3088 }
3089 
3090 /*
3091  * Use the kernel's tsc_khz directly if the TSC is constant, otherwise use KVM's
3092  * per-CPU value (which may be zero if a CPU is going offline).  Note, tsc_khz
3093  * can change during boot even if the TSC is constant, as it's possible for KVM
3094  * to be loaded before TSC calibration completes.  Ideally, KVM would get a
3095  * notification when calibration completes, but practically speaking calibration
3096  * will complete before userspace is alive enough to create VMs.
3097  */
3098 static unsigned long get_cpu_tsc_khz(void)
3099 {
3100 	if (static_cpu_has(X86_FEATURE_CONSTANT_TSC))
3101 		return tsc_khz;
3102 	else
3103 		return __this_cpu_read(cpu_tsc_khz);
3104 }
3105 
3106 /* Called within read_seqcount_begin/retry for kvm->pvclock_sc.  */
3107 static void __get_kvmclock(struct kvm *kvm, struct kvm_clock_data *data)
3108 {
3109 	struct kvm_arch *ka = &kvm->arch;
3110 	struct pvclock_vcpu_time_info hv_clock;
3111 
3112 	/* both __this_cpu_read() and rdtsc() should be on the same cpu */
3113 	get_cpu();
3114 
3115 	data->flags = 0;
3116 	if (ka->use_master_clock &&
3117 	    (static_cpu_has(X86_FEATURE_CONSTANT_TSC) || __this_cpu_read(cpu_tsc_khz))) {
3118 #ifdef CONFIG_X86_64
3119 		struct timespec64 ts;
3120 
3121 		if (kvm_get_walltime_and_clockread(&ts, &data->host_tsc)) {
3122 			data->realtime = ts.tv_nsec + NSEC_PER_SEC * ts.tv_sec;
3123 			data->flags |= KVM_CLOCK_REALTIME | KVM_CLOCK_HOST_TSC;
3124 		} else
3125 #endif
3126 		data->host_tsc = rdtsc();
3127 
3128 		data->flags |= KVM_CLOCK_TSC_STABLE;
3129 		hv_clock.tsc_timestamp = ka->master_cycle_now;
3130 		hv_clock.system_time = ka->master_kernel_ns + ka->kvmclock_offset;
3131 		kvm_get_time_scale(NSEC_PER_SEC, get_cpu_tsc_khz() * 1000LL,
3132 				   &hv_clock.tsc_shift,
3133 				   &hv_clock.tsc_to_system_mul);
3134 		data->clock = __pvclock_read_cycles(&hv_clock, data->host_tsc);
3135 	} else {
3136 		data->clock = get_kvmclock_base_ns() + ka->kvmclock_offset;
3137 	}
3138 
3139 	put_cpu();
3140 }
3141 
3142 static void get_kvmclock(struct kvm *kvm, struct kvm_clock_data *data)
3143 {
3144 	struct kvm_arch *ka = &kvm->arch;
3145 	unsigned seq;
3146 
3147 	do {
3148 		seq = read_seqcount_begin(&ka->pvclock_sc);
3149 		__get_kvmclock(kvm, data);
3150 	} while (read_seqcount_retry(&ka->pvclock_sc, seq));
3151 }
3152 
3153 u64 get_kvmclock_ns(struct kvm *kvm)
3154 {
3155 	struct kvm_clock_data data;
3156 
3157 	get_kvmclock(kvm, &data);
3158 	return data.clock;
3159 }
3160 
3161 static void kvm_setup_guest_pvclock(struct kvm_vcpu *v,
3162 				    struct gfn_to_pfn_cache *gpc,
3163 				    unsigned int offset,
3164 				    bool force_tsc_unstable)
3165 {
3166 	struct kvm_vcpu_arch *vcpu = &v->arch;
3167 	struct pvclock_vcpu_time_info *guest_hv_clock;
3168 	unsigned long flags;
3169 
3170 	read_lock_irqsave(&gpc->lock, flags);
3171 	while (!kvm_gpc_check(gpc, offset + sizeof(*guest_hv_clock))) {
3172 		read_unlock_irqrestore(&gpc->lock, flags);
3173 
3174 		if (kvm_gpc_refresh(gpc, offset + sizeof(*guest_hv_clock)))
3175 			return;
3176 
3177 		read_lock_irqsave(&gpc->lock, flags);
3178 	}
3179 
3180 	guest_hv_clock = (void *)(gpc->khva + offset);
3181 
3182 	/*
3183 	 * This VCPU is paused, but it's legal for a guest to read another
3184 	 * VCPU's kvmclock, so we really have to follow the specification where
3185 	 * it says that version is odd if data is being modified, and even after
3186 	 * it is consistent.
3187 	 */
3188 
3189 	guest_hv_clock->version = vcpu->hv_clock.version = (guest_hv_clock->version + 1) | 1;
3190 	smp_wmb();
3191 
3192 	/* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
3193 	vcpu->hv_clock.flags |= (guest_hv_clock->flags & PVCLOCK_GUEST_STOPPED);
3194 
3195 	if (vcpu->pvclock_set_guest_stopped_request) {
3196 		vcpu->hv_clock.flags |= PVCLOCK_GUEST_STOPPED;
3197 		vcpu->pvclock_set_guest_stopped_request = false;
3198 	}
3199 
3200 	memcpy(guest_hv_clock, &vcpu->hv_clock, sizeof(*guest_hv_clock));
3201 
3202 	if (force_tsc_unstable)
3203 		guest_hv_clock->flags &= ~PVCLOCK_TSC_STABLE_BIT;
3204 
3205 	smp_wmb();
3206 
3207 	guest_hv_clock->version = ++vcpu->hv_clock.version;
3208 
3209 	kvm_gpc_mark_dirty_in_slot(gpc);
3210 	read_unlock_irqrestore(&gpc->lock, flags);
3211 
3212 	trace_kvm_pvclock_update(v->vcpu_id, &vcpu->hv_clock);
3213 }
3214 
3215 static int kvm_guest_time_update(struct kvm_vcpu *v)
3216 {
3217 	unsigned long flags, tgt_tsc_khz;
3218 	unsigned seq;
3219 	struct kvm_vcpu_arch *vcpu = &v->arch;
3220 	struct kvm_arch *ka = &v->kvm->arch;
3221 	s64 kernel_ns;
3222 	u64 tsc_timestamp, host_tsc;
3223 	u8 pvclock_flags;
3224 	bool use_master_clock;
3225 #ifdef CONFIG_KVM_XEN
3226 	/*
3227 	 * For Xen guests we may need to override PVCLOCK_TSC_STABLE_BIT as unless
3228 	 * explicitly told to use TSC as its clocksource Xen will not set this bit.
3229 	 * This default behaviour led to bugs in some guest kernels which cause
3230 	 * problems if they observe PVCLOCK_TSC_STABLE_BIT in the pvclock flags.
3231 	 */
3232 	bool xen_pvclock_tsc_unstable =
3233 		ka->xen_hvm_config.flags & KVM_XEN_HVM_CONFIG_PVCLOCK_TSC_UNSTABLE;
3234 #endif
3235 
3236 	kernel_ns = 0;
3237 	host_tsc = 0;
3238 
3239 	/*
3240 	 * If the host uses TSC clock, then passthrough TSC as stable
3241 	 * to the guest.
3242 	 */
3243 	do {
3244 		seq = read_seqcount_begin(&ka->pvclock_sc);
3245 		use_master_clock = ka->use_master_clock;
3246 		if (use_master_clock) {
3247 			host_tsc = ka->master_cycle_now;
3248 			kernel_ns = ka->master_kernel_ns;
3249 		}
3250 	} while (read_seqcount_retry(&ka->pvclock_sc, seq));
3251 
3252 	/* Keep irq disabled to prevent changes to the clock */
3253 	local_irq_save(flags);
3254 	tgt_tsc_khz = get_cpu_tsc_khz();
3255 	if (unlikely(tgt_tsc_khz == 0)) {
3256 		local_irq_restore(flags);
3257 		kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
3258 		return 1;
3259 	}
3260 	if (!use_master_clock) {
3261 		host_tsc = rdtsc();
3262 		kernel_ns = get_kvmclock_base_ns();
3263 	}
3264 
3265 	tsc_timestamp = kvm_read_l1_tsc(v, host_tsc);
3266 
3267 	/*
3268 	 * We may have to catch up the TSC to match elapsed wall clock
3269 	 * time for two reasons, even if kvmclock is used.
3270 	 *   1) CPU could have been running below the maximum TSC rate
3271 	 *   2) Broken TSC compensation resets the base at each VCPU
3272 	 *      entry to avoid unknown leaps of TSC even when running
3273 	 *      again on the same CPU.  This may cause apparent elapsed
3274 	 *      time to disappear, and the guest to stand still or run
3275 	 *	very slowly.
3276 	 */
3277 	if (vcpu->tsc_catchup) {
3278 		u64 tsc = compute_guest_tsc(v, kernel_ns);
3279 		if (tsc > tsc_timestamp) {
3280 			adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
3281 			tsc_timestamp = tsc;
3282 		}
3283 	}
3284 
3285 	local_irq_restore(flags);
3286 
3287 	/* With all the info we got, fill in the values */
3288 
3289 	if (kvm_caps.has_tsc_control)
3290 		tgt_tsc_khz = kvm_scale_tsc(tgt_tsc_khz,
3291 					    v->arch.l1_tsc_scaling_ratio);
3292 
3293 	if (unlikely(vcpu->hw_tsc_khz != tgt_tsc_khz)) {
3294 		kvm_get_time_scale(NSEC_PER_SEC, tgt_tsc_khz * 1000LL,
3295 				   &vcpu->hv_clock.tsc_shift,
3296 				   &vcpu->hv_clock.tsc_to_system_mul);
3297 		vcpu->hw_tsc_khz = tgt_tsc_khz;
3298 		kvm_xen_update_tsc_info(v);
3299 	}
3300 
3301 	vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
3302 	vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
3303 	vcpu->last_guest_tsc = tsc_timestamp;
3304 
3305 	/* If the host uses TSC clocksource, then it is stable */
3306 	pvclock_flags = 0;
3307 	if (use_master_clock)
3308 		pvclock_flags |= PVCLOCK_TSC_STABLE_BIT;
3309 
3310 	vcpu->hv_clock.flags = pvclock_flags;
3311 
3312 	if (vcpu->pv_time.active)
3313 		kvm_setup_guest_pvclock(v, &vcpu->pv_time, 0, false);
3314 #ifdef CONFIG_KVM_XEN
3315 	if (vcpu->xen.vcpu_info_cache.active)
3316 		kvm_setup_guest_pvclock(v, &vcpu->xen.vcpu_info_cache,
3317 					offsetof(struct compat_vcpu_info, time),
3318 					xen_pvclock_tsc_unstable);
3319 	if (vcpu->xen.vcpu_time_info_cache.active)
3320 		kvm_setup_guest_pvclock(v, &vcpu->xen.vcpu_time_info_cache, 0,
3321 					xen_pvclock_tsc_unstable);
3322 #endif
3323 	kvm_hv_setup_tsc_page(v->kvm, &vcpu->hv_clock);
3324 	return 0;
3325 }
3326 
3327 /*
3328  * The pvclock_wall_clock ABI tells the guest the wall clock time at
3329  * which it started (i.e. its epoch, when its kvmclock was zero).
3330  *
3331  * In fact those clocks are subtly different; wall clock frequency is
3332  * adjusted by NTP and has leap seconds, while the kvmclock is a
3333  * simple function of the TSC without any such adjustment.
3334  *
3335  * Perhaps the ABI should have exposed CLOCK_TAI and a ratio between
3336  * that and kvmclock, but even that would be subject to change over
3337  * time.
3338  *
3339  * Attempt to calculate the epoch at a given moment using the *same*
3340  * TSC reading via kvm_get_walltime_and_clockread() to obtain both
3341  * wallclock and kvmclock times, and subtracting one from the other.
3342  *
3343  * Fall back to using their values at slightly different moments by
3344  * calling ktime_get_real_ns() and get_kvmclock_ns() separately.
3345  */
3346 uint64_t kvm_get_wall_clock_epoch(struct kvm *kvm)
3347 {
3348 #ifdef CONFIG_X86_64
3349 	struct pvclock_vcpu_time_info hv_clock;
3350 	struct kvm_arch *ka = &kvm->arch;
3351 	unsigned long seq, local_tsc_khz;
3352 	struct timespec64 ts;
3353 	uint64_t host_tsc;
3354 
3355 	do {
3356 		seq = read_seqcount_begin(&ka->pvclock_sc);
3357 
3358 		local_tsc_khz = 0;
3359 		if (!ka->use_master_clock)
3360 			break;
3361 
3362 		/*
3363 		 * The TSC read and the call to get_cpu_tsc_khz() must happen
3364 		 * on the same CPU.
3365 		 */
3366 		get_cpu();
3367 
3368 		local_tsc_khz = get_cpu_tsc_khz();
3369 
3370 		if (local_tsc_khz &&
3371 		    !kvm_get_walltime_and_clockread(&ts, &host_tsc))
3372 			local_tsc_khz = 0; /* Fall back to old method */
3373 
3374 		put_cpu();
3375 
3376 		/*
3377 		 * These values must be snapshotted within the seqcount loop.
3378 		 * After that, it's just mathematics which can happen on any
3379 		 * CPU at any time.
3380 		 */
3381 		hv_clock.tsc_timestamp = ka->master_cycle_now;
3382 		hv_clock.system_time = ka->master_kernel_ns + ka->kvmclock_offset;
3383 
3384 	} while (read_seqcount_retry(&ka->pvclock_sc, seq));
3385 
3386 	/*
3387 	 * If the conditions were right, and obtaining the wallclock+TSC was
3388 	 * successful, calculate the KVM clock at the corresponding time and
3389 	 * subtract one from the other to get the guest's epoch in nanoseconds
3390 	 * since 1970-01-01.
3391 	 */
3392 	if (local_tsc_khz) {
3393 		kvm_get_time_scale(NSEC_PER_SEC, local_tsc_khz * NSEC_PER_USEC,
3394 				   &hv_clock.tsc_shift,
3395 				   &hv_clock.tsc_to_system_mul);
3396 		return ts.tv_nsec + NSEC_PER_SEC * ts.tv_sec -
3397 			__pvclock_read_cycles(&hv_clock, host_tsc);
3398 	}
3399 #endif
3400 	return ktime_get_real_ns() - get_kvmclock_ns(kvm);
3401 }
3402 
3403 /*
3404  * kvmclock updates which are isolated to a given vcpu, such as
3405  * vcpu->cpu migration, should not allow system_timestamp from
3406  * the rest of the vcpus to remain static. Otherwise ntp frequency
3407  * correction applies to one vcpu's system_timestamp but not
3408  * the others.
3409  *
3410  * So in those cases, request a kvmclock update for all vcpus.
3411  * We need to rate-limit these requests though, as they can
3412  * considerably slow guests that have a large number of vcpus.
3413  * The time for a remote vcpu to update its kvmclock is bound
3414  * by the delay we use to rate-limit the updates.
3415  */
3416 
3417 #define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100)
3418 
3419 static void kvmclock_update_fn(struct work_struct *work)
3420 {
3421 	unsigned long i;
3422 	struct delayed_work *dwork = to_delayed_work(work);
3423 	struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
3424 					   kvmclock_update_work);
3425 	struct kvm *kvm = container_of(ka, struct kvm, arch);
3426 	struct kvm_vcpu *vcpu;
3427 
3428 	kvm_for_each_vcpu(i, vcpu, kvm) {
3429 		kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3430 		kvm_vcpu_kick(vcpu);
3431 	}
3432 }
3433 
3434 static void kvm_gen_kvmclock_update(struct kvm_vcpu *v)
3435 {
3436 	struct kvm *kvm = v->kvm;
3437 
3438 	kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
3439 	schedule_delayed_work(&kvm->arch.kvmclock_update_work,
3440 					KVMCLOCK_UPDATE_DELAY);
3441 }
3442 
3443 #define KVMCLOCK_SYNC_PERIOD (300 * HZ)
3444 
3445 static void kvmclock_sync_fn(struct work_struct *work)
3446 {
3447 	struct delayed_work *dwork = to_delayed_work(work);
3448 	struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
3449 					   kvmclock_sync_work);
3450 	struct kvm *kvm = container_of(ka, struct kvm, arch);
3451 
3452 	schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0);
3453 	schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
3454 					KVMCLOCK_SYNC_PERIOD);
3455 }
3456 
3457 /* These helpers are safe iff @msr is known to be an MCx bank MSR. */
3458 static bool is_mci_control_msr(u32 msr)
3459 {
3460 	return (msr & 3) == 0;
3461 }
3462 static bool is_mci_status_msr(u32 msr)
3463 {
3464 	return (msr & 3) == 1;
3465 }
3466 
3467 /*
3468  * On AMD, HWCR[McStatusWrEn] controls whether setting MCi_STATUS results in #GP.
3469  */
3470 static bool can_set_mci_status(struct kvm_vcpu *vcpu)
3471 {
3472 	/* McStatusWrEn enabled? */
3473 	if (guest_cpuid_is_amd_compatible(vcpu))
3474 		return !!(vcpu->arch.msr_hwcr & BIT_ULL(18));
3475 
3476 	return false;
3477 }
3478 
3479 static int set_msr_mce(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
3480 {
3481 	u64 mcg_cap = vcpu->arch.mcg_cap;
3482 	unsigned bank_num = mcg_cap & 0xff;
3483 	u32 msr = msr_info->index;
3484 	u64 data = msr_info->data;
3485 	u32 offset, last_msr;
3486 
3487 	switch (msr) {
3488 	case MSR_IA32_MCG_STATUS:
3489 		vcpu->arch.mcg_status = data;
3490 		break;
3491 	case MSR_IA32_MCG_CTL:
3492 		if (!(mcg_cap & MCG_CTL_P) &&
3493 		    (data || !msr_info->host_initiated))
3494 			return 1;
3495 		if (data != 0 && data != ~(u64)0)
3496 			return 1;
3497 		vcpu->arch.mcg_ctl = data;
3498 		break;
3499 	case MSR_IA32_MC0_CTL2 ... MSR_IA32_MCx_CTL2(KVM_MAX_MCE_BANKS) - 1:
3500 		last_msr = MSR_IA32_MCx_CTL2(bank_num) - 1;
3501 		if (msr > last_msr)
3502 			return 1;
3503 
3504 		if (!(mcg_cap & MCG_CMCI_P) && (data || !msr_info->host_initiated))
3505 			return 1;
3506 		/* An attempt to write a 1 to a reserved bit raises #GP */
3507 		if (data & ~(MCI_CTL2_CMCI_EN | MCI_CTL2_CMCI_THRESHOLD_MASK))
3508 			return 1;
3509 		offset = array_index_nospec(msr - MSR_IA32_MC0_CTL2,
3510 					    last_msr + 1 - MSR_IA32_MC0_CTL2);
3511 		vcpu->arch.mci_ctl2_banks[offset] = data;
3512 		break;
3513 	case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
3514 		last_msr = MSR_IA32_MCx_CTL(bank_num) - 1;
3515 		if (msr > last_msr)
3516 			return 1;
3517 
3518 		/*
3519 		 * Only 0 or all 1s can be written to IA32_MCi_CTL, all other
3520 		 * values are architecturally undefined.  But, some Linux
3521 		 * kernels clear bit 10 in bank 4 to workaround a BIOS/GART TLB
3522 		 * issue on AMD K8s, allow bit 10 to be clear when setting all
3523 		 * other bits in order to avoid an uncaught #GP in the guest.
3524 		 *
3525 		 * UNIXWARE clears bit 0 of MC1_CTL to ignore correctable,
3526 		 * single-bit ECC data errors.
3527 		 */
3528 		if (is_mci_control_msr(msr) &&
3529 		    data != 0 && (data | (1 << 10) | 1) != ~(u64)0)
3530 			return 1;
3531 
3532 		/*
3533 		 * All CPUs allow writing 0 to MCi_STATUS MSRs to clear the MSR.
3534 		 * AMD-based CPUs allow non-zero values, but if and only if
3535 		 * HWCR[McStatusWrEn] is set.
3536 		 */
3537 		if (!msr_info->host_initiated && is_mci_status_msr(msr) &&
3538 		    data != 0 && !can_set_mci_status(vcpu))
3539 			return 1;
3540 
3541 		offset = array_index_nospec(msr - MSR_IA32_MC0_CTL,
3542 					    last_msr + 1 - MSR_IA32_MC0_CTL);
3543 		vcpu->arch.mce_banks[offset] = data;
3544 		break;
3545 	default:
3546 		return 1;
3547 	}
3548 	return 0;
3549 }
3550 
3551 static inline bool kvm_pv_async_pf_enabled(struct kvm_vcpu *vcpu)
3552 {
3553 	u64 mask = KVM_ASYNC_PF_ENABLED | KVM_ASYNC_PF_DELIVERY_AS_INT;
3554 
3555 	return (vcpu->arch.apf.msr_en_val & mask) == mask;
3556 }
3557 
3558 static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
3559 {
3560 	gpa_t gpa = data & ~0x3f;
3561 
3562 	/* Bits 4:5 are reserved, Should be zero */
3563 	if (data & 0x30)
3564 		return 1;
3565 
3566 	if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_VMEXIT) &&
3567 	    (data & KVM_ASYNC_PF_DELIVERY_AS_PF_VMEXIT))
3568 		return 1;
3569 
3570 	if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_INT) &&
3571 	    (data & KVM_ASYNC_PF_DELIVERY_AS_INT))
3572 		return 1;
3573 
3574 	if (!lapic_in_kernel(vcpu))
3575 		return data ? 1 : 0;
3576 
3577 	vcpu->arch.apf.msr_en_val = data;
3578 
3579 	if (!kvm_pv_async_pf_enabled(vcpu)) {
3580 		kvm_clear_async_pf_completion_queue(vcpu);
3581 		kvm_async_pf_hash_reset(vcpu);
3582 		return 0;
3583 	}
3584 
3585 	if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa,
3586 					sizeof(u64)))
3587 		return 1;
3588 
3589 	vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
3590 	vcpu->arch.apf.delivery_as_pf_vmexit = data & KVM_ASYNC_PF_DELIVERY_AS_PF_VMEXIT;
3591 
3592 	kvm_async_pf_wakeup_all(vcpu);
3593 
3594 	return 0;
3595 }
3596 
3597 static int kvm_pv_enable_async_pf_int(struct kvm_vcpu *vcpu, u64 data)
3598 {
3599 	/* Bits 8-63 are reserved */
3600 	if (data >> 8)
3601 		return 1;
3602 
3603 	if (!lapic_in_kernel(vcpu))
3604 		return 1;
3605 
3606 	vcpu->arch.apf.msr_int_val = data;
3607 
3608 	vcpu->arch.apf.vec = data & KVM_ASYNC_PF_VEC_MASK;
3609 
3610 	return 0;
3611 }
3612 
3613 static void kvmclock_reset(struct kvm_vcpu *vcpu)
3614 {
3615 	kvm_gpc_deactivate(&vcpu->arch.pv_time);
3616 	vcpu->arch.time = 0;
3617 }
3618 
3619 static void kvm_vcpu_flush_tlb_all(struct kvm_vcpu *vcpu)
3620 {
3621 	++vcpu->stat.tlb_flush;
3622 	static_call(kvm_x86_flush_tlb_all)(vcpu);
3623 
3624 	/* Flushing all ASIDs flushes the current ASID... */
3625 	kvm_clear_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu);
3626 }
3627 
3628 static void kvm_vcpu_flush_tlb_guest(struct kvm_vcpu *vcpu)
3629 {
3630 	++vcpu->stat.tlb_flush;
3631 
3632 	if (!tdp_enabled) {
3633 		/*
3634 		 * A TLB flush on behalf of the guest is equivalent to
3635 		 * INVPCID(all), toggling CR4.PGE, etc., which requires
3636 		 * a forced sync of the shadow page tables.  Ensure all the
3637 		 * roots are synced and the guest TLB in hardware is clean.
3638 		 */
3639 		kvm_mmu_sync_roots(vcpu);
3640 		kvm_mmu_sync_prev_roots(vcpu);
3641 	}
3642 
3643 	static_call(kvm_x86_flush_tlb_guest)(vcpu);
3644 
3645 	/*
3646 	 * Flushing all "guest" TLB is always a superset of Hyper-V's fine
3647 	 * grained flushing.
3648 	 */
3649 	kvm_hv_vcpu_purge_flush_tlb(vcpu);
3650 }
3651 
3652 
3653 static inline void kvm_vcpu_flush_tlb_current(struct kvm_vcpu *vcpu)
3654 {
3655 	++vcpu->stat.tlb_flush;
3656 	static_call(kvm_x86_flush_tlb_current)(vcpu);
3657 }
3658 
3659 /*
3660  * Service "local" TLB flush requests, which are specific to the current MMU
3661  * context.  In addition to the generic event handling in vcpu_enter_guest(),
3662  * TLB flushes that are targeted at an MMU context also need to be serviced
3663  * prior before nested VM-Enter/VM-Exit.
3664  */
3665 void kvm_service_local_tlb_flush_requests(struct kvm_vcpu *vcpu)
3666 {
3667 	if (kvm_check_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu))
3668 		kvm_vcpu_flush_tlb_current(vcpu);
3669 
3670 	if (kvm_check_request(KVM_REQ_TLB_FLUSH_GUEST, vcpu))
3671 		kvm_vcpu_flush_tlb_guest(vcpu);
3672 }
3673 EXPORT_SYMBOL_GPL(kvm_service_local_tlb_flush_requests);
3674 
3675 static void record_steal_time(struct kvm_vcpu *vcpu)
3676 {
3677 	struct gfn_to_hva_cache *ghc = &vcpu->arch.st.cache;
3678 	struct kvm_steal_time __user *st;
3679 	struct kvm_memslots *slots;
3680 	gpa_t gpa = vcpu->arch.st.msr_val & KVM_STEAL_VALID_BITS;
3681 	u64 steal;
3682 	u32 version;
3683 
3684 	if (kvm_xen_msr_enabled(vcpu->kvm)) {
3685 		kvm_xen_runstate_set_running(vcpu);
3686 		return;
3687 	}
3688 
3689 	if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
3690 		return;
3691 
3692 	if (WARN_ON_ONCE(current->mm != vcpu->kvm->mm))
3693 		return;
3694 
3695 	slots = kvm_memslots(vcpu->kvm);
3696 
3697 	if (unlikely(slots->generation != ghc->generation ||
3698 		     gpa != ghc->gpa ||
3699 		     kvm_is_error_hva(ghc->hva) || !ghc->memslot)) {
3700 		/* We rely on the fact that it fits in a single page. */
3701 		BUILD_BUG_ON((sizeof(*st) - 1) & KVM_STEAL_VALID_BITS);
3702 
3703 		if (kvm_gfn_to_hva_cache_init(vcpu->kvm, ghc, gpa, sizeof(*st)) ||
3704 		    kvm_is_error_hva(ghc->hva) || !ghc->memslot)
3705 			return;
3706 	}
3707 
3708 	st = (struct kvm_steal_time __user *)ghc->hva;
3709 	/*
3710 	 * Doing a TLB flush here, on the guest's behalf, can avoid
3711 	 * expensive IPIs.
3712 	 */
3713 	if (guest_pv_has(vcpu, KVM_FEATURE_PV_TLB_FLUSH)) {
3714 		u8 st_preempted = 0;
3715 		int err = -EFAULT;
3716 
3717 		if (!user_access_begin(st, sizeof(*st)))
3718 			return;
3719 
3720 		asm volatile("1: xchgb %0, %2\n"
3721 			     "xor %1, %1\n"
3722 			     "2:\n"
3723 			     _ASM_EXTABLE_UA(1b, 2b)
3724 			     : "+q" (st_preempted),
3725 			       "+&r" (err),
3726 			       "+m" (st->preempted));
3727 		if (err)
3728 			goto out;
3729 
3730 		user_access_end();
3731 
3732 		vcpu->arch.st.preempted = 0;
3733 
3734 		trace_kvm_pv_tlb_flush(vcpu->vcpu_id,
3735 				       st_preempted & KVM_VCPU_FLUSH_TLB);
3736 		if (st_preempted & KVM_VCPU_FLUSH_TLB)
3737 			kvm_vcpu_flush_tlb_guest(vcpu);
3738 
3739 		if (!user_access_begin(st, sizeof(*st)))
3740 			goto dirty;
3741 	} else {
3742 		if (!user_access_begin(st, sizeof(*st)))
3743 			return;
3744 
3745 		unsafe_put_user(0, &st->preempted, out);
3746 		vcpu->arch.st.preempted = 0;
3747 	}
3748 
3749 	unsafe_get_user(version, &st->version, out);
3750 	if (version & 1)
3751 		version += 1;  /* first time write, random junk */
3752 
3753 	version += 1;
3754 	unsafe_put_user(version, &st->version, out);
3755 
3756 	smp_wmb();
3757 
3758 	unsafe_get_user(steal, &st->steal, out);
3759 	steal += current->sched_info.run_delay -
3760 		vcpu->arch.st.last_steal;
3761 	vcpu->arch.st.last_steal = current->sched_info.run_delay;
3762 	unsafe_put_user(steal, &st->steal, out);
3763 
3764 	version += 1;
3765 	unsafe_put_user(version, &st->version, out);
3766 
3767  out:
3768 	user_access_end();
3769  dirty:
3770 	mark_page_dirty_in_slot(vcpu->kvm, ghc->memslot, gpa_to_gfn(ghc->gpa));
3771 }
3772 
3773 static bool kvm_is_msr_to_save(u32 msr_index)
3774 {
3775 	unsigned int i;
3776 
3777 	for (i = 0; i < num_msrs_to_save; i++) {
3778 		if (msrs_to_save[i] == msr_index)
3779 			return true;
3780 	}
3781 
3782 	return false;
3783 }
3784 
3785 int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
3786 {
3787 	u32 msr = msr_info->index;
3788 	u64 data = msr_info->data;
3789 
3790 	if (msr && msr == vcpu->kvm->arch.xen_hvm_config.msr)
3791 		return kvm_xen_write_hypercall_page(vcpu, data);
3792 
3793 	switch (msr) {
3794 	case MSR_AMD64_NB_CFG:
3795 	case MSR_IA32_UCODE_WRITE:
3796 	case MSR_VM_HSAVE_PA:
3797 	case MSR_AMD64_PATCH_LOADER:
3798 	case MSR_AMD64_BU_CFG2:
3799 	case MSR_AMD64_DC_CFG:
3800 	case MSR_AMD64_TW_CFG:
3801 	case MSR_F15H_EX_CFG:
3802 		break;
3803 
3804 	case MSR_IA32_UCODE_REV:
3805 		if (msr_info->host_initiated)
3806 			vcpu->arch.microcode_version = data;
3807 		break;
3808 	case MSR_IA32_ARCH_CAPABILITIES:
3809 		if (!msr_info->host_initiated)
3810 			return 1;
3811 		vcpu->arch.arch_capabilities = data;
3812 		break;
3813 	case MSR_IA32_PERF_CAPABILITIES:
3814 		if (!msr_info->host_initiated)
3815 			return 1;
3816 		if (data & ~kvm_caps.supported_perf_cap)
3817 			return 1;
3818 
3819 		/*
3820 		 * Note, this is not just a performance optimization!  KVM
3821 		 * disallows changing feature MSRs after the vCPU has run; PMU
3822 		 * refresh will bug the VM if called after the vCPU has run.
3823 		 */
3824 		if (vcpu->arch.perf_capabilities == data)
3825 			break;
3826 
3827 		vcpu->arch.perf_capabilities = data;
3828 		kvm_pmu_refresh(vcpu);
3829 		break;
3830 	case MSR_IA32_PRED_CMD: {
3831 		u64 reserved_bits = ~(PRED_CMD_IBPB | PRED_CMD_SBPB);
3832 
3833 		if (!msr_info->host_initiated) {
3834 			if ((!guest_has_pred_cmd_msr(vcpu)))
3835 				return 1;
3836 
3837 			if (!guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL) &&
3838 			    !guest_cpuid_has(vcpu, X86_FEATURE_AMD_IBPB))
3839 				reserved_bits |= PRED_CMD_IBPB;
3840 
3841 			if (!guest_cpuid_has(vcpu, X86_FEATURE_SBPB))
3842 				reserved_bits |= PRED_CMD_SBPB;
3843 		}
3844 
3845 		if (!boot_cpu_has(X86_FEATURE_IBPB))
3846 			reserved_bits |= PRED_CMD_IBPB;
3847 
3848 		if (!boot_cpu_has(X86_FEATURE_SBPB))
3849 			reserved_bits |= PRED_CMD_SBPB;
3850 
3851 		if (data & reserved_bits)
3852 			return 1;
3853 
3854 		if (!data)
3855 			break;
3856 
3857 		wrmsrl(MSR_IA32_PRED_CMD, data);
3858 		break;
3859 	}
3860 	case MSR_IA32_FLUSH_CMD:
3861 		if (!msr_info->host_initiated &&
3862 		    !guest_cpuid_has(vcpu, X86_FEATURE_FLUSH_L1D))
3863 			return 1;
3864 
3865 		if (!boot_cpu_has(X86_FEATURE_FLUSH_L1D) || (data & ~L1D_FLUSH))
3866 			return 1;
3867 		if (!data)
3868 			break;
3869 
3870 		wrmsrl(MSR_IA32_FLUSH_CMD, L1D_FLUSH);
3871 		break;
3872 	case MSR_EFER:
3873 		return set_efer(vcpu, msr_info);
3874 	case MSR_K7_HWCR:
3875 		data &= ~(u64)0x40;	/* ignore flush filter disable */
3876 		data &= ~(u64)0x100;	/* ignore ignne emulation enable */
3877 		data &= ~(u64)0x8;	/* ignore TLB cache disable */
3878 
3879 		/*
3880 		 * Allow McStatusWrEn and TscFreqSel. (Linux guests from v3.2
3881 		 * through at least v6.6 whine if TscFreqSel is clear,
3882 		 * depending on F/M/S.
3883 		 */
3884 		if (data & ~(BIT_ULL(18) | BIT_ULL(24))) {
3885 			kvm_pr_unimpl_wrmsr(vcpu, msr, data);
3886 			return 1;
3887 		}
3888 		vcpu->arch.msr_hwcr = data;
3889 		break;
3890 	case MSR_FAM10H_MMIO_CONF_BASE:
3891 		if (data != 0) {
3892 			kvm_pr_unimpl_wrmsr(vcpu, msr, data);
3893 			return 1;
3894 		}
3895 		break;
3896 	case MSR_IA32_CR_PAT:
3897 		if (!kvm_pat_valid(data))
3898 			return 1;
3899 
3900 		vcpu->arch.pat = data;
3901 		break;
3902 	case MTRRphysBase_MSR(0) ... MSR_MTRRfix4K_F8000:
3903 	case MSR_MTRRdefType:
3904 		return kvm_mtrr_set_msr(vcpu, msr, data);
3905 	case MSR_IA32_APICBASE:
3906 		return kvm_set_apic_base(vcpu, msr_info);
3907 	case APIC_BASE_MSR ... APIC_BASE_MSR + 0xff:
3908 		return kvm_x2apic_msr_write(vcpu, msr, data);
3909 	case MSR_IA32_TSC_DEADLINE:
3910 		kvm_set_lapic_tscdeadline_msr(vcpu, data);
3911 		break;
3912 	case MSR_IA32_TSC_ADJUST:
3913 		if (guest_cpuid_has(vcpu, X86_FEATURE_TSC_ADJUST)) {
3914 			if (!msr_info->host_initiated) {
3915 				s64 adj = data - vcpu->arch.ia32_tsc_adjust_msr;
3916 				adjust_tsc_offset_guest(vcpu, adj);
3917 				/* Before back to guest, tsc_timestamp must be adjusted
3918 				 * as well, otherwise guest's percpu pvclock time could jump.
3919 				 */
3920 				kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3921 			}
3922 			vcpu->arch.ia32_tsc_adjust_msr = data;
3923 		}
3924 		break;
3925 	case MSR_IA32_MISC_ENABLE: {
3926 		u64 old_val = vcpu->arch.ia32_misc_enable_msr;
3927 
3928 		if (!msr_info->host_initiated) {
3929 			/* RO bits */
3930 			if ((old_val ^ data) & MSR_IA32_MISC_ENABLE_PMU_RO_MASK)
3931 				return 1;
3932 
3933 			/* R bits, i.e. writes are ignored, but don't fault. */
3934 			data = data & ~MSR_IA32_MISC_ENABLE_EMON;
3935 			data |= old_val & MSR_IA32_MISC_ENABLE_EMON;
3936 		}
3937 
3938 		if (!kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_MISC_ENABLE_NO_MWAIT) &&
3939 		    ((old_val ^ data)  & MSR_IA32_MISC_ENABLE_MWAIT)) {
3940 			if (!guest_cpuid_has(vcpu, X86_FEATURE_XMM3))
3941 				return 1;
3942 			vcpu->arch.ia32_misc_enable_msr = data;
3943 			kvm_update_cpuid_runtime(vcpu);
3944 		} else {
3945 			vcpu->arch.ia32_misc_enable_msr = data;
3946 		}
3947 		break;
3948 	}
3949 	case MSR_IA32_SMBASE:
3950 		if (!IS_ENABLED(CONFIG_KVM_SMM) || !msr_info->host_initiated)
3951 			return 1;
3952 		vcpu->arch.smbase = data;
3953 		break;
3954 	case MSR_IA32_POWER_CTL:
3955 		vcpu->arch.msr_ia32_power_ctl = data;
3956 		break;
3957 	case MSR_IA32_TSC:
3958 		if (msr_info->host_initiated) {
3959 			kvm_synchronize_tsc(vcpu, &data);
3960 		} else {
3961 			u64 adj = kvm_compute_l1_tsc_offset(vcpu, data) - vcpu->arch.l1_tsc_offset;
3962 			adjust_tsc_offset_guest(vcpu, adj);
3963 			vcpu->arch.ia32_tsc_adjust_msr += adj;
3964 		}
3965 		break;
3966 	case MSR_IA32_XSS:
3967 		if (!msr_info->host_initiated &&
3968 		    !guest_cpuid_has(vcpu, X86_FEATURE_XSAVES))
3969 			return 1;
3970 		/*
3971 		 * KVM supports exposing PT to the guest, but does not support
3972 		 * IA32_XSS[bit 8]. Guests have to use RDMSR/WRMSR rather than
3973 		 * XSAVES/XRSTORS to save/restore PT MSRs.
3974 		 */
3975 		if (data & ~kvm_caps.supported_xss)
3976 			return 1;
3977 		vcpu->arch.ia32_xss = data;
3978 		kvm_update_cpuid_runtime(vcpu);
3979 		break;
3980 	case MSR_SMI_COUNT:
3981 		if (!msr_info->host_initiated)
3982 			return 1;
3983 		vcpu->arch.smi_count = data;
3984 		break;
3985 	case MSR_KVM_WALL_CLOCK_NEW:
3986 		if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE2))
3987 			return 1;
3988 
3989 		vcpu->kvm->arch.wall_clock = data;
3990 		kvm_write_wall_clock(vcpu->kvm, data, 0);
3991 		break;
3992 	case MSR_KVM_WALL_CLOCK:
3993 		if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE))
3994 			return 1;
3995 
3996 		vcpu->kvm->arch.wall_clock = data;
3997 		kvm_write_wall_clock(vcpu->kvm, data, 0);
3998 		break;
3999 	case MSR_KVM_SYSTEM_TIME_NEW:
4000 		if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE2))
4001 			return 1;
4002 
4003 		kvm_write_system_time(vcpu, data, false, msr_info->host_initiated);
4004 		break;
4005 	case MSR_KVM_SYSTEM_TIME:
4006 		if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE))
4007 			return 1;
4008 
4009 		kvm_write_system_time(vcpu, data, true,  msr_info->host_initiated);
4010 		break;
4011 	case MSR_KVM_ASYNC_PF_EN:
4012 		if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF))
4013 			return 1;
4014 
4015 		if (kvm_pv_enable_async_pf(vcpu, data))
4016 			return 1;
4017 		break;
4018 	case MSR_KVM_ASYNC_PF_INT:
4019 		if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_INT))
4020 			return 1;
4021 
4022 		if (kvm_pv_enable_async_pf_int(vcpu, data))
4023 			return 1;
4024 		break;
4025 	case MSR_KVM_ASYNC_PF_ACK:
4026 		if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_INT))
4027 			return 1;
4028 		if (data & 0x1) {
4029 			vcpu->arch.apf.pageready_pending = false;
4030 			kvm_check_async_pf_completion(vcpu);
4031 		}
4032 		break;
4033 	case MSR_KVM_STEAL_TIME:
4034 		if (!guest_pv_has(vcpu, KVM_FEATURE_STEAL_TIME))
4035 			return 1;
4036 
4037 		if (unlikely(!sched_info_on()))
4038 			return 1;
4039 
4040 		if (data & KVM_STEAL_RESERVED_MASK)
4041 			return 1;
4042 
4043 		vcpu->arch.st.msr_val = data;
4044 
4045 		if (!(data & KVM_MSR_ENABLED))
4046 			break;
4047 
4048 		kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
4049 
4050 		break;
4051 	case MSR_KVM_PV_EOI_EN:
4052 		if (!guest_pv_has(vcpu, KVM_FEATURE_PV_EOI))
4053 			return 1;
4054 
4055 		if (kvm_lapic_set_pv_eoi(vcpu, data, sizeof(u8)))
4056 			return 1;
4057 		break;
4058 
4059 	case MSR_KVM_POLL_CONTROL:
4060 		if (!guest_pv_has(vcpu, KVM_FEATURE_POLL_CONTROL))
4061 			return 1;
4062 
4063 		/* only enable bit supported */
4064 		if (data & (-1ULL << 1))
4065 			return 1;
4066 
4067 		vcpu->arch.msr_kvm_poll_control = data;
4068 		break;
4069 
4070 	case MSR_IA32_MCG_CTL:
4071 	case MSR_IA32_MCG_STATUS:
4072 	case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
4073 	case MSR_IA32_MC0_CTL2 ... MSR_IA32_MCx_CTL2(KVM_MAX_MCE_BANKS) - 1:
4074 		return set_msr_mce(vcpu, msr_info);
4075 
4076 	case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
4077 	case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
4078 	case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
4079 	case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
4080 		if (kvm_pmu_is_valid_msr(vcpu, msr))
4081 			return kvm_pmu_set_msr(vcpu, msr_info);
4082 
4083 		if (data)
4084 			kvm_pr_unimpl_wrmsr(vcpu, msr, data);
4085 		break;
4086 	case MSR_K7_CLK_CTL:
4087 		/*
4088 		 * Ignore all writes to this no longer documented MSR.
4089 		 * Writes are only relevant for old K7 processors,
4090 		 * all pre-dating SVM, but a recommended workaround from
4091 		 * AMD for these chips. It is possible to specify the
4092 		 * affected processor models on the command line, hence
4093 		 * the need to ignore the workaround.
4094 		 */
4095 		break;
4096 #ifdef CONFIG_KVM_HYPERV
4097 	case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
4098 	case HV_X64_MSR_SYNDBG_CONTROL ... HV_X64_MSR_SYNDBG_PENDING_BUFFER:
4099 	case HV_X64_MSR_SYNDBG_OPTIONS:
4100 	case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
4101 	case HV_X64_MSR_CRASH_CTL:
4102 	case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
4103 	case HV_X64_MSR_REENLIGHTENMENT_CONTROL:
4104 	case HV_X64_MSR_TSC_EMULATION_CONTROL:
4105 	case HV_X64_MSR_TSC_EMULATION_STATUS:
4106 	case HV_X64_MSR_TSC_INVARIANT_CONTROL:
4107 		return kvm_hv_set_msr_common(vcpu, msr, data,
4108 					     msr_info->host_initiated);
4109 #endif
4110 	case MSR_IA32_BBL_CR_CTL3:
4111 		/* Drop writes to this legacy MSR -- see rdmsr
4112 		 * counterpart for further detail.
4113 		 */
4114 		kvm_pr_unimpl_wrmsr(vcpu, msr, data);
4115 		break;
4116 	case MSR_AMD64_OSVW_ID_LENGTH:
4117 		if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
4118 			return 1;
4119 		vcpu->arch.osvw.length = data;
4120 		break;
4121 	case MSR_AMD64_OSVW_STATUS:
4122 		if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
4123 			return 1;
4124 		vcpu->arch.osvw.status = data;
4125 		break;
4126 	case MSR_PLATFORM_INFO:
4127 		if (!msr_info->host_initiated ||
4128 		    (!(data & MSR_PLATFORM_INFO_CPUID_FAULT) &&
4129 		     cpuid_fault_enabled(vcpu)))
4130 			return 1;
4131 		vcpu->arch.msr_platform_info = data;
4132 		break;
4133 	case MSR_MISC_FEATURES_ENABLES:
4134 		if (data & ~MSR_MISC_FEATURES_ENABLES_CPUID_FAULT ||
4135 		    (data & MSR_MISC_FEATURES_ENABLES_CPUID_FAULT &&
4136 		     !supports_cpuid_fault(vcpu)))
4137 			return 1;
4138 		vcpu->arch.msr_misc_features_enables = data;
4139 		break;
4140 #ifdef CONFIG_X86_64
4141 	case MSR_IA32_XFD:
4142 		if (!msr_info->host_initiated &&
4143 		    !guest_cpuid_has(vcpu, X86_FEATURE_XFD))
4144 			return 1;
4145 
4146 		if (data & ~kvm_guest_supported_xfd(vcpu))
4147 			return 1;
4148 
4149 		fpu_update_guest_xfd(&vcpu->arch.guest_fpu, data);
4150 		break;
4151 	case MSR_IA32_XFD_ERR:
4152 		if (!msr_info->host_initiated &&
4153 		    !guest_cpuid_has(vcpu, X86_FEATURE_XFD))
4154 			return 1;
4155 
4156 		if (data & ~kvm_guest_supported_xfd(vcpu))
4157 			return 1;
4158 
4159 		vcpu->arch.guest_fpu.xfd_err = data;
4160 		break;
4161 #endif
4162 	default:
4163 		if (kvm_pmu_is_valid_msr(vcpu, msr))
4164 			return kvm_pmu_set_msr(vcpu, msr_info);
4165 
4166 		/*
4167 		 * Userspace is allowed to write '0' to MSRs that KVM reports
4168 		 * as to-be-saved, even if an MSRs isn't fully supported.
4169 		 */
4170 		if (msr_info->host_initiated && !data &&
4171 		    kvm_is_msr_to_save(msr))
4172 			break;
4173 
4174 		return KVM_MSR_RET_INVALID;
4175 	}
4176 	return 0;
4177 }
4178 EXPORT_SYMBOL_GPL(kvm_set_msr_common);
4179 
4180 static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata, bool host)
4181 {
4182 	u64 data;
4183 	u64 mcg_cap = vcpu->arch.mcg_cap;
4184 	unsigned bank_num = mcg_cap & 0xff;
4185 	u32 offset, last_msr;
4186 
4187 	switch (msr) {
4188 	case MSR_IA32_P5_MC_ADDR:
4189 	case MSR_IA32_P5_MC_TYPE:
4190 		data = 0;
4191 		break;
4192 	case MSR_IA32_MCG_CAP:
4193 		data = vcpu->arch.mcg_cap;
4194 		break;
4195 	case MSR_IA32_MCG_CTL:
4196 		if (!(mcg_cap & MCG_CTL_P) && !host)
4197 			return 1;
4198 		data = vcpu->arch.mcg_ctl;
4199 		break;
4200 	case MSR_IA32_MCG_STATUS:
4201 		data = vcpu->arch.mcg_status;
4202 		break;
4203 	case MSR_IA32_MC0_CTL2 ... MSR_IA32_MCx_CTL2(KVM_MAX_MCE_BANKS) - 1:
4204 		last_msr = MSR_IA32_MCx_CTL2(bank_num) - 1;
4205 		if (msr > last_msr)
4206 			return 1;
4207 
4208 		if (!(mcg_cap & MCG_CMCI_P) && !host)
4209 			return 1;
4210 		offset = array_index_nospec(msr - MSR_IA32_MC0_CTL2,
4211 					    last_msr + 1 - MSR_IA32_MC0_CTL2);
4212 		data = vcpu->arch.mci_ctl2_banks[offset];
4213 		break;
4214 	case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
4215 		last_msr = MSR_IA32_MCx_CTL(bank_num) - 1;
4216 		if (msr > last_msr)
4217 			return 1;
4218 
4219 		offset = array_index_nospec(msr - MSR_IA32_MC0_CTL,
4220 					    last_msr + 1 - MSR_IA32_MC0_CTL);
4221 		data = vcpu->arch.mce_banks[offset];
4222 		break;
4223 	default:
4224 		return 1;
4225 	}
4226 	*pdata = data;
4227 	return 0;
4228 }
4229 
4230 int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
4231 {
4232 	switch (msr_info->index) {
4233 	case MSR_IA32_PLATFORM_ID:
4234 	case MSR_IA32_EBL_CR_POWERON:
4235 	case MSR_IA32_LASTBRANCHFROMIP:
4236 	case MSR_IA32_LASTBRANCHTOIP:
4237 	case MSR_IA32_LASTINTFROMIP:
4238 	case MSR_IA32_LASTINTTOIP:
4239 	case MSR_AMD64_SYSCFG:
4240 	case MSR_K8_TSEG_ADDR:
4241 	case MSR_K8_TSEG_MASK:
4242 	case MSR_VM_HSAVE_PA:
4243 	case MSR_K8_INT_PENDING_MSG:
4244 	case MSR_AMD64_NB_CFG:
4245 	case MSR_FAM10H_MMIO_CONF_BASE:
4246 	case MSR_AMD64_BU_CFG2:
4247 	case MSR_IA32_PERF_CTL:
4248 	case MSR_AMD64_DC_CFG:
4249 	case MSR_AMD64_TW_CFG:
4250 	case MSR_F15H_EX_CFG:
4251 	/*
4252 	 * Intel Sandy Bridge CPUs must support the RAPL (running average power
4253 	 * limit) MSRs. Just return 0, as we do not want to expose the host
4254 	 * data here. Do not conditionalize this on CPUID, as KVM does not do
4255 	 * so for existing CPU-specific MSRs.
4256 	 */
4257 	case MSR_RAPL_POWER_UNIT:
4258 	case MSR_PP0_ENERGY_STATUS:	/* Power plane 0 (core) */
4259 	case MSR_PP1_ENERGY_STATUS:	/* Power plane 1 (graphics uncore) */
4260 	case MSR_PKG_ENERGY_STATUS:	/* Total package */
4261 	case MSR_DRAM_ENERGY_STATUS:	/* DRAM controller */
4262 		msr_info->data = 0;
4263 		break;
4264 	case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
4265 	case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
4266 	case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
4267 	case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
4268 		if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
4269 			return kvm_pmu_get_msr(vcpu, msr_info);
4270 		msr_info->data = 0;
4271 		break;
4272 	case MSR_IA32_UCODE_REV:
4273 		msr_info->data = vcpu->arch.microcode_version;
4274 		break;
4275 	case MSR_IA32_ARCH_CAPABILITIES:
4276 		if (!msr_info->host_initiated &&
4277 		    !guest_cpuid_has(vcpu, X86_FEATURE_ARCH_CAPABILITIES))
4278 			return 1;
4279 		msr_info->data = vcpu->arch.arch_capabilities;
4280 		break;
4281 	case MSR_IA32_PERF_CAPABILITIES:
4282 		if (!msr_info->host_initiated &&
4283 		    !guest_cpuid_has(vcpu, X86_FEATURE_PDCM))
4284 			return 1;
4285 		msr_info->data = vcpu->arch.perf_capabilities;
4286 		break;
4287 	case MSR_IA32_POWER_CTL:
4288 		msr_info->data = vcpu->arch.msr_ia32_power_ctl;
4289 		break;
4290 	case MSR_IA32_TSC: {
4291 		/*
4292 		 * Intel SDM states that MSR_IA32_TSC read adds the TSC offset
4293 		 * even when not intercepted. AMD manual doesn't explicitly
4294 		 * state this but appears to behave the same.
4295 		 *
4296 		 * On userspace reads and writes, however, we unconditionally
4297 		 * return L1's TSC value to ensure backwards-compatible
4298 		 * behavior for migration.
4299 		 */
4300 		u64 offset, ratio;
4301 
4302 		if (msr_info->host_initiated) {
4303 			offset = vcpu->arch.l1_tsc_offset;
4304 			ratio = vcpu->arch.l1_tsc_scaling_ratio;
4305 		} else {
4306 			offset = vcpu->arch.tsc_offset;
4307 			ratio = vcpu->arch.tsc_scaling_ratio;
4308 		}
4309 
4310 		msr_info->data = kvm_scale_tsc(rdtsc(), ratio) + offset;
4311 		break;
4312 	}
4313 	case MSR_IA32_CR_PAT:
4314 		msr_info->data = vcpu->arch.pat;
4315 		break;
4316 	case MSR_MTRRcap:
4317 	case MTRRphysBase_MSR(0) ... MSR_MTRRfix4K_F8000:
4318 	case MSR_MTRRdefType:
4319 		return kvm_mtrr_get_msr(vcpu, msr_info->index, &msr_info->data);
4320 	case 0xcd: /* fsb frequency */
4321 		msr_info->data = 3;
4322 		break;
4323 		/*
4324 		 * MSR_EBC_FREQUENCY_ID
4325 		 * Conservative value valid for even the basic CPU models.
4326 		 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
4327 		 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
4328 		 * and 266MHz for model 3, or 4. Set Core Clock
4329 		 * Frequency to System Bus Frequency Ratio to 1 (bits
4330 		 * 31:24) even though these are only valid for CPU
4331 		 * models > 2, however guests may end up dividing or
4332 		 * multiplying by zero otherwise.
4333 		 */
4334 	case MSR_EBC_FREQUENCY_ID:
4335 		msr_info->data = 1 << 24;
4336 		break;
4337 	case MSR_IA32_APICBASE:
4338 		msr_info->data = kvm_get_apic_base(vcpu);
4339 		break;
4340 	case APIC_BASE_MSR ... APIC_BASE_MSR + 0xff:
4341 		return kvm_x2apic_msr_read(vcpu, msr_info->index, &msr_info->data);
4342 	case MSR_IA32_TSC_DEADLINE:
4343 		msr_info->data = kvm_get_lapic_tscdeadline_msr(vcpu);
4344 		break;
4345 	case MSR_IA32_TSC_ADJUST:
4346 		msr_info->data = (u64)vcpu->arch.ia32_tsc_adjust_msr;
4347 		break;
4348 	case MSR_IA32_MISC_ENABLE:
4349 		msr_info->data = vcpu->arch.ia32_misc_enable_msr;
4350 		break;
4351 	case MSR_IA32_SMBASE:
4352 		if (!IS_ENABLED(CONFIG_KVM_SMM) || !msr_info->host_initiated)
4353 			return 1;
4354 		msr_info->data = vcpu->arch.smbase;
4355 		break;
4356 	case MSR_SMI_COUNT:
4357 		msr_info->data = vcpu->arch.smi_count;
4358 		break;
4359 	case MSR_IA32_PERF_STATUS:
4360 		/* TSC increment by tick */
4361 		msr_info->data = 1000ULL;
4362 		/* CPU multiplier */
4363 		msr_info->data |= (((uint64_t)4ULL) << 40);
4364 		break;
4365 	case MSR_EFER:
4366 		msr_info->data = vcpu->arch.efer;
4367 		break;
4368 	case MSR_KVM_WALL_CLOCK:
4369 		if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE))
4370 			return 1;
4371 
4372 		msr_info->data = vcpu->kvm->arch.wall_clock;
4373 		break;
4374 	case MSR_KVM_WALL_CLOCK_NEW:
4375 		if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE2))
4376 			return 1;
4377 
4378 		msr_info->data = vcpu->kvm->arch.wall_clock;
4379 		break;
4380 	case MSR_KVM_SYSTEM_TIME:
4381 		if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE))
4382 			return 1;
4383 
4384 		msr_info->data = vcpu->arch.time;
4385 		break;
4386 	case MSR_KVM_SYSTEM_TIME_NEW:
4387 		if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE2))
4388 			return 1;
4389 
4390 		msr_info->data = vcpu->arch.time;
4391 		break;
4392 	case MSR_KVM_ASYNC_PF_EN:
4393 		if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF))
4394 			return 1;
4395 
4396 		msr_info->data = vcpu->arch.apf.msr_en_val;
4397 		break;
4398 	case MSR_KVM_ASYNC_PF_INT:
4399 		if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_INT))
4400 			return 1;
4401 
4402 		msr_info->data = vcpu->arch.apf.msr_int_val;
4403 		break;
4404 	case MSR_KVM_ASYNC_PF_ACK:
4405 		if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_INT))
4406 			return 1;
4407 
4408 		msr_info->data = 0;
4409 		break;
4410 	case MSR_KVM_STEAL_TIME:
4411 		if (!guest_pv_has(vcpu, KVM_FEATURE_STEAL_TIME))
4412 			return 1;
4413 
4414 		msr_info->data = vcpu->arch.st.msr_val;
4415 		break;
4416 	case MSR_KVM_PV_EOI_EN:
4417 		if (!guest_pv_has(vcpu, KVM_FEATURE_PV_EOI))
4418 			return 1;
4419 
4420 		msr_info->data = vcpu->arch.pv_eoi.msr_val;
4421 		break;
4422 	case MSR_KVM_POLL_CONTROL:
4423 		if (!guest_pv_has(vcpu, KVM_FEATURE_POLL_CONTROL))
4424 			return 1;
4425 
4426 		msr_info->data = vcpu->arch.msr_kvm_poll_control;
4427 		break;
4428 	case MSR_IA32_P5_MC_ADDR:
4429 	case MSR_IA32_P5_MC_TYPE:
4430 	case MSR_IA32_MCG_CAP:
4431 	case MSR_IA32_MCG_CTL:
4432 	case MSR_IA32_MCG_STATUS:
4433 	case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
4434 	case MSR_IA32_MC0_CTL2 ... MSR_IA32_MCx_CTL2(KVM_MAX_MCE_BANKS) - 1:
4435 		return get_msr_mce(vcpu, msr_info->index, &msr_info->data,
4436 				   msr_info->host_initiated);
4437 	case MSR_IA32_XSS:
4438 		if (!msr_info->host_initiated &&
4439 		    !guest_cpuid_has(vcpu, X86_FEATURE_XSAVES))
4440 			return 1;
4441 		msr_info->data = vcpu->arch.ia32_xss;
4442 		break;
4443 	case MSR_K7_CLK_CTL:
4444 		/*
4445 		 * Provide expected ramp-up count for K7. All other
4446 		 * are set to zero, indicating minimum divisors for
4447 		 * every field.
4448 		 *
4449 		 * This prevents guest kernels on AMD host with CPU
4450 		 * type 6, model 8 and higher from exploding due to
4451 		 * the rdmsr failing.
4452 		 */
4453 		msr_info->data = 0x20000000;
4454 		break;
4455 #ifdef CONFIG_KVM_HYPERV
4456 	case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
4457 	case HV_X64_MSR_SYNDBG_CONTROL ... HV_X64_MSR_SYNDBG_PENDING_BUFFER:
4458 	case HV_X64_MSR_SYNDBG_OPTIONS:
4459 	case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
4460 	case HV_X64_MSR_CRASH_CTL:
4461 	case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
4462 	case HV_X64_MSR_REENLIGHTENMENT_CONTROL:
4463 	case HV_X64_MSR_TSC_EMULATION_CONTROL:
4464 	case HV_X64_MSR_TSC_EMULATION_STATUS:
4465 	case HV_X64_MSR_TSC_INVARIANT_CONTROL:
4466 		return kvm_hv_get_msr_common(vcpu,
4467 					     msr_info->index, &msr_info->data,
4468 					     msr_info->host_initiated);
4469 #endif
4470 	case MSR_IA32_BBL_CR_CTL3:
4471 		/* This legacy MSR exists but isn't fully documented in current
4472 		 * silicon.  It is however accessed by winxp in very narrow
4473 		 * scenarios where it sets bit #19, itself documented as
4474 		 * a "reserved" bit.  Best effort attempt to source coherent
4475 		 * read data here should the balance of the register be
4476 		 * interpreted by the guest:
4477 		 *
4478 		 * L2 cache control register 3: 64GB range, 256KB size,
4479 		 * enabled, latency 0x1, configured
4480 		 */
4481 		msr_info->data = 0xbe702111;
4482 		break;
4483 	case MSR_AMD64_OSVW_ID_LENGTH:
4484 		if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
4485 			return 1;
4486 		msr_info->data = vcpu->arch.osvw.length;
4487 		break;
4488 	case MSR_AMD64_OSVW_STATUS:
4489 		if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
4490 			return 1;
4491 		msr_info->data = vcpu->arch.osvw.status;
4492 		break;
4493 	case MSR_PLATFORM_INFO:
4494 		if (!msr_info->host_initiated &&
4495 		    !vcpu->kvm->arch.guest_can_read_msr_platform_info)
4496 			return 1;
4497 		msr_info->data = vcpu->arch.msr_platform_info;
4498 		break;
4499 	case MSR_MISC_FEATURES_ENABLES:
4500 		msr_info->data = vcpu->arch.msr_misc_features_enables;
4501 		break;
4502 	case MSR_K7_HWCR:
4503 		msr_info->data = vcpu->arch.msr_hwcr;
4504 		break;
4505 #ifdef CONFIG_X86_64
4506 	case MSR_IA32_XFD:
4507 		if (!msr_info->host_initiated &&
4508 		    !guest_cpuid_has(vcpu, X86_FEATURE_XFD))
4509 			return 1;
4510 
4511 		msr_info->data = vcpu->arch.guest_fpu.fpstate->xfd;
4512 		break;
4513 	case MSR_IA32_XFD_ERR:
4514 		if (!msr_info->host_initiated &&
4515 		    !guest_cpuid_has(vcpu, X86_FEATURE_XFD))
4516 			return 1;
4517 
4518 		msr_info->data = vcpu->arch.guest_fpu.xfd_err;
4519 		break;
4520 #endif
4521 	default:
4522 		if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
4523 			return kvm_pmu_get_msr(vcpu, msr_info);
4524 
4525 		/*
4526 		 * Userspace is allowed to read MSRs that KVM reports as
4527 		 * to-be-saved, even if an MSR isn't fully supported.
4528 		 */
4529 		if (msr_info->host_initiated &&
4530 		    kvm_is_msr_to_save(msr_info->index)) {
4531 			msr_info->data = 0;
4532 			break;
4533 		}
4534 
4535 		return KVM_MSR_RET_INVALID;
4536 	}
4537 	return 0;
4538 }
4539 EXPORT_SYMBOL_GPL(kvm_get_msr_common);
4540 
4541 /*
4542  * Read or write a bunch of msrs. All parameters are kernel addresses.
4543  *
4544  * @return number of msrs set successfully.
4545  */
4546 static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
4547 		    struct kvm_msr_entry *entries,
4548 		    int (*do_msr)(struct kvm_vcpu *vcpu,
4549 				  unsigned index, u64 *data))
4550 {
4551 	int i;
4552 
4553 	for (i = 0; i < msrs->nmsrs; ++i)
4554 		if (do_msr(vcpu, entries[i].index, &entries[i].data))
4555 			break;
4556 
4557 	return i;
4558 }
4559 
4560 /*
4561  * Read or write a bunch of msrs. Parameters are user addresses.
4562  *
4563  * @return number of msrs set successfully.
4564  */
4565 static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
4566 		  int (*do_msr)(struct kvm_vcpu *vcpu,
4567 				unsigned index, u64 *data),
4568 		  int writeback)
4569 {
4570 	struct kvm_msrs msrs;
4571 	struct kvm_msr_entry *entries;
4572 	unsigned size;
4573 	int r;
4574 
4575 	r = -EFAULT;
4576 	if (copy_from_user(&msrs, user_msrs, sizeof(msrs)))
4577 		goto out;
4578 
4579 	r = -E2BIG;
4580 	if (msrs.nmsrs >= MAX_IO_MSRS)
4581 		goto out;
4582 
4583 	size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
4584 	entries = memdup_user(user_msrs->entries, size);
4585 	if (IS_ERR(entries)) {
4586 		r = PTR_ERR(entries);
4587 		goto out;
4588 	}
4589 
4590 	r = __msr_io(vcpu, &msrs, entries, do_msr);
4591 
4592 	if (writeback && copy_to_user(user_msrs->entries, entries, size))
4593 		r = -EFAULT;
4594 
4595 	kfree(entries);
4596 out:
4597 	return r;
4598 }
4599 
4600 static inline bool kvm_can_mwait_in_guest(void)
4601 {
4602 	return boot_cpu_has(X86_FEATURE_MWAIT) &&
4603 		!boot_cpu_has_bug(X86_BUG_MONITOR) &&
4604 		boot_cpu_has(X86_FEATURE_ARAT);
4605 }
4606 
4607 #ifdef CONFIG_KVM_HYPERV
4608 static int kvm_ioctl_get_supported_hv_cpuid(struct kvm_vcpu *vcpu,
4609 					    struct kvm_cpuid2 __user *cpuid_arg)
4610 {
4611 	struct kvm_cpuid2 cpuid;
4612 	int r;
4613 
4614 	r = -EFAULT;
4615 	if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
4616 		return r;
4617 
4618 	r = kvm_get_hv_cpuid(vcpu, &cpuid, cpuid_arg->entries);
4619 	if (r)
4620 		return r;
4621 
4622 	r = -EFAULT;
4623 	if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid)))
4624 		return r;
4625 
4626 	return 0;
4627 }
4628 #endif
4629 
4630 static bool kvm_is_vm_type_supported(unsigned long type)
4631 {
4632 	return type < 32 && (kvm_caps.supported_vm_types & BIT(type));
4633 }
4634 
4635 int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
4636 {
4637 	int r = 0;
4638 
4639 	switch (ext) {
4640 	case KVM_CAP_IRQCHIP:
4641 	case KVM_CAP_HLT:
4642 	case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
4643 	case KVM_CAP_SET_TSS_ADDR:
4644 	case KVM_CAP_EXT_CPUID:
4645 	case KVM_CAP_EXT_EMUL_CPUID:
4646 	case KVM_CAP_CLOCKSOURCE:
4647 	case KVM_CAP_PIT:
4648 	case KVM_CAP_NOP_IO_DELAY:
4649 	case KVM_CAP_MP_STATE:
4650 	case KVM_CAP_SYNC_MMU:
4651 	case KVM_CAP_USER_NMI:
4652 	case KVM_CAP_REINJECT_CONTROL:
4653 	case KVM_CAP_IRQ_INJECT_STATUS:
4654 	case KVM_CAP_IOEVENTFD:
4655 	case KVM_CAP_IOEVENTFD_NO_LENGTH:
4656 	case KVM_CAP_PIT2:
4657 	case KVM_CAP_PIT_STATE2:
4658 	case KVM_CAP_SET_IDENTITY_MAP_ADDR:
4659 	case KVM_CAP_VCPU_EVENTS:
4660 #ifdef CONFIG_KVM_HYPERV
4661 	case KVM_CAP_HYPERV:
4662 	case KVM_CAP_HYPERV_VAPIC:
4663 	case KVM_CAP_HYPERV_SPIN:
4664 	case KVM_CAP_HYPERV_TIME:
4665 	case KVM_CAP_HYPERV_SYNIC:
4666 	case KVM_CAP_HYPERV_SYNIC2:
4667 	case KVM_CAP_HYPERV_VP_INDEX:
4668 	case KVM_CAP_HYPERV_EVENTFD:
4669 	case KVM_CAP_HYPERV_TLBFLUSH:
4670 	case KVM_CAP_HYPERV_SEND_IPI:
4671 	case KVM_CAP_HYPERV_CPUID:
4672 	case KVM_CAP_HYPERV_ENFORCE_CPUID:
4673 	case KVM_CAP_SYS_HYPERV_CPUID:
4674 #endif
4675 	case KVM_CAP_PCI_SEGMENT:
4676 	case KVM_CAP_DEBUGREGS:
4677 	case KVM_CAP_X86_ROBUST_SINGLESTEP:
4678 	case KVM_CAP_XSAVE:
4679 	case KVM_CAP_ASYNC_PF:
4680 	case KVM_CAP_ASYNC_PF_INT:
4681 	case KVM_CAP_GET_TSC_KHZ:
4682 	case KVM_CAP_KVMCLOCK_CTRL:
4683 	case KVM_CAP_READONLY_MEM:
4684 	case KVM_CAP_IOAPIC_POLARITY_IGNORED:
4685 	case KVM_CAP_TSC_DEADLINE_TIMER:
4686 	case KVM_CAP_DISABLE_QUIRKS:
4687 	case KVM_CAP_SET_BOOT_CPU_ID:
4688  	case KVM_CAP_SPLIT_IRQCHIP:
4689 	case KVM_CAP_IMMEDIATE_EXIT:
4690 	case KVM_CAP_PMU_EVENT_FILTER:
4691 	case KVM_CAP_PMU_EVENT_MASKED_EVENTS:
4692 	case KVM_CAP_GET_MSR_FEATURES:
4693 	case KVM_CAP_MSR_PLATFORM_INFO:
4694 	case KVM_CAP_EXCEPTION_PAYLOAD:
4695 	case KVM_CAP_X86_TRIPLE_FAULT_EVENT:
4696 	case KVM_CAP_SET_GUEST_DEBUG:
4697 	case KVM_CAP_LAST_CPU:
4698 	case KVM_CAP_X86_USER_SPACE_MSR:
4699 	case KVM_CAP_X86_MSR_FILTER:
4700 	case KVM_CAP_ENFORCE_PV_FEATURE_CPUID:
4701 #ifdef CONFIG_X86_SGX_KVM
4702 	case KVM_CAP_SGX_ATTRIBUTE:
4703 #endif
4704 	case KVM_CAP_VM_COPY_ENC_CONTEXT_FROM:
4705 	case KVM_CAP_VM_MOVE_ENC_CONTEXT_FROM:
4706 	case KVM_CAP_SREGS2:
4707 	case KVM_CAP_EXIT_ON_EMULATION_FAILURE:
4708 	case KVM_CAP_VCPU_ATTRIBUTES:
4709 	case KVM_CAP_SYS_ATTRIBUTES:
4710 	case KVM_CAP_VAPIC:
4711 	case KVM_CAP_ENABLE_CAP:
4712 	case KVM_CAP_VM_DISABLE_NX_HUGE_PAGES:
4713 	case KVM_CAP_IRQFD_RESAMPLE:
4714 	case KVM_CAP_MEMORY_FAULT_INFO:
4715 		r = 1;
4716 		break;
4717 	case KVM_CAP_EXIT_HYPERCALL:
4718 		r = KVM_EXIT_HYPERCALL_VALID_MASK;
4719 		break;
4720 	case KVM_CAP_SET_GUEST_DEBUG2:
4721 		return KVM_GUESTDBG_VALID_MASK;
4722 #ifdef CONFIG_KVM_XEN
4723 	case KVM_CAP_XEN_HVM:
4724 		r = KVM_XEN_HVM_CONFIG_HYPERCALL_MSR |
4725 		    KVM_XEN_HVM_CONFIG_INTERCEPT_HCALL |
4726 		    KVM_XEN_HVM_CONFIG_SHARED_INFO |
4727 		    KVM_XEN_HVM_CONFIG_EVTCHN_2LEVEL |
4728 		    KVM_XEN_HVM_CONFIG_EVTCHN_SEND |
4729 		    KVM_XEN_HVM_CONFIG_PVCLOCK_TSC_UNSTABLE |
4730 		    KVM_XEN_HVM_CONFIG_SHARED_INFO_HVA;
4731 		if (sched_info_on())
4732 			r |= KVM_XEN_HVM_CONFIG_RUNSTATE |
4733 			     KVM_XEN_HVM_CONFIG_RUNSTATE_UPDATE_FLAG;
4734 		break;
4735 #endif
4736 	case KVM_CAP_SYNC_REGS:
4737 		r = KVM_SYNC_X86_VALID_FIELDS;
4738 		break;
4739 	case KVM_CAP_ADJUST_CLOCK:
4740 		r = KVM_CLOCK_VALID_FLAGS;
4741 		break;
4742 	case KVM_CAP_X86_DISABLE_EXITS:
4743 		r = KVM_X86_DISABLE_EXITS_PAUSE;
4744 
4745 		if (!mitigate_smt_rsb) {
4746 			r |= KVM_X86_DISABLE_EXITS_HLT |
4747 			     KVM_X86_DISABLE_EXITS_CSTATE;
4748 
4749 			if (kvm_can_mwait_in_guest())
4750 				r |= KVM_X86_DISABLE_EXITS_MWAIT;
4751 		}
4752 		break;
4753 	case KVM_CAP_X86_SMM:
4754 		if (!IS_ENABLED(CONFIG_KVM_SMM))
4755 			break;
4756 
4757 		/* SMBASE is usually relocated above 1M on modern chipsets,
4758 		 * and SMM handlers might indeed rely on 4G segment limits,
4759 		 * so do not report SMM to be available if real mode is
4760 		 * emulated via vm86 mode.  Still, do not go to great lengths
4761 		 * to avoid userspace's usage of the feature, because it is a
4762 		 * fringe case that is not enabled except via specific settings
4763 		 * of the module parameters.
4764 		 */
4765 		r = static_call(kvm_x86_has_emulated_msr)(kvm, MSR_IA32_SMBASE);
4766 		break;
4767 	case KVM_CAP_NR_VCPUS:
4768 		r = min_t(unsigned int, num_online_cpus(), KVM_MAX_VCPUS);
4769 		break;
4770 	case KVM_CAP_MAX_VCPUS:
4771 		r = KVM_MAX_VCPUS;
4772 		break;
4773 	case KVM_CAP_MAX_VCPU_ID:
4774 		r = KVM_MAX_VCPU_IDS;
4775 		break;
4776 	case KVM_CAP_PV_MMU:	/* obsolete */
4777 		r = 0;
4778 		break;
4779 	case KVM_CAP_MCE:
4780 		r = KVM_MAX_MCE_BANKS;
4781 		break;
4782 	case KVM_CAP_XCRS:
4783 		r = boot_cpu_has(X86_FEATURE_XSAVE);
4784 		break;
4785 	case KVM_CAP_TSC_CONTROL:
4786 	case KVM_CAP_VM_TSC_CONTROL:
4787 		r = kvm_caps.has_tsc_control;
4788 		break;
4789 	case KVM_CAP_X2APIC_API:
4790 		r = KVM_X2APIC_API_VALID_FLAGS;
4791 		break;
4792 	case KVM_CAP_NESTED_STATE:
4793 		r = kvm_x86_ops.nested_ops->get_state ?
4794 			kvm_x86_ops.nested_ops->get_state(NULL, NULL, 0) : 0;
4795 		break;
4796 #ifdef CONFIG_KVM_HYPERV
4797 	case KVM_CAP_HYPERV_DIRECT_TLBFLUSH:
4798 		r = kvm_x86_ops.enable_l2_tlb_flush != NULL;
4799 		break;
4800 	case KVM_CAP_HYPERV_ENLIGHTENED_VMCS:
4801 		r = kvm_x86_ops.nested_ops->enable_evmcs != NULL;
4802 		break;
4803 #endif
4804 	case KVM_CAP_SMALLER_MAXPHYADDR:
4805 		r = (int) allow_smaller_maxphyaddr;
4806 		break;
4807 	case KVM_CAP_STEAL_TIME:
4808 		r = sched_info_on();
4809 		break;
4810 	case KVM_CAP_X86_BUS_LOCK_EXIT:
4811 		if (kvm_caps.has_bus_lock_exit)
4812 			r = KVM_BUS_LOCK_DETECTION_OFF |
4813 			    KVM_BUS_LOCK_DETECTION_EXIT;
4814 		else
4815 			r = 0;
4816 		break;
4817 	case KVM_CAP_XSAVE2: {
4818 		r = xstate_required_size(kvm_get_filtered_xcr0(), false);
4819 		if (r < sizeof(struct kvm_xsave))
4820 			r = sizeof(struct kvm_xsave);
4821 		break;
4822 	}
4823 	case KVM_CAP_PMU_CAPABILITY:
4824 		r = enable_pmu ? KVM_CAP_PMU_VALID_MASK : 0;
4825 		break;
4826 	case KVM_CAP_DISABLE_QUIRKS2:
4827 		r = KVM_X86_VALID_QUIRKS;
4828 		break;
4829 	case KVM_CAP_X86_NOTIFY_VMEXIT:
4830 		r = kvm_caps.has_notify_vmexit;
4831 		break;
4832 	case KVM_CAP_VM_TYPES:
4833 		r = kvm_caps.supported_vm_types;
4834 		break;
4835 	default:
4836 		break;
4837 	}
4838 	return r;
4839 }
4840 
4841 static int __kvm_x86_dev_get_attr(struct kvm_device_attr *attr, u64 *val)
4842 {
4843 	if (attr->group) {
4844 		if (kvm_x86_ops.dev_get_attr)
4845 			return static_call(kvm_x86_dev_get_attr)(attr->group, attr->attr, val);
4846 		return -ENXIO;
4847 	}
4848 
4849 	switch (attr->attr) {
4850 	case KVM_X86_XCOMP_GUEST_SUPP:
4851 		*val = kvm_caps.supported_xcr0;
4852 		return 0;
4853 	default:
4854 		return -ENXIO;
4855 	}
4856 }
4857 
4858 static int kvm_x86_dev_get_attr(struct kvm_device_attr *attr)
4859 {
4860 	u64 __user *uaddr = u64_to_user_ptr(attr->addr);
4861 	int r;
4862 	u64 val;
4863 
4864 	r = __kvm_x86_dev_get_attr(attr, &val);
4865 	if (r < 0)
4866 		return r;
4867 
4868 	if (put_user(val, uaddr))
4869 		return -EFAULT;
4870 
4871 	return 0;
4872 }
4873 
4874 static int kvm_x86_dev_has_attr(struct kvm_device_attr *attr)
4875 {
4876 	u64 val;
4877 
4878 	return __kvm_x86_dev_get_attr(attr, &val);
4879 }
4880 
4881 long kvm_arch_dev_ioctl(struct file *filp,
4882 			unsigned int ioctl, unsigned long arg)
4883 {
4884 	void __user *argp = (void __user *)arg;
4885 	long r;
4886 
4887 	switch (ioctl) {
4888 	case KVM_GET_MSR_INDEX_LIST: {
4889 		struct kvm_msr_list __user *user_msr_list = argp;
4890 		struct kvm_msr_list msr_list;
4891 		unsigned n;
4892 
4893 		r = -EFAULT;
4894 		if (copy_from_user(&msr_list, user_msr_list, sizeof(msr_list)))
4895 			goto out;
4896 		n = msr_list.nmsrs;
4897 		msr_list.nmsrs = num_msrs_to_save + num_emulated_msrs;
4898 		if (copy_to_user(user_msr_list, &msr_list, sizeof(msr_list)))
4899 			goto out;
4900 		r = -E2BIG;
4901 		if (n < msr_list.nmsrs)
4902 			goto out;
4903 		r = -EFAULT;
4904 		if (copy_to_user(user_msr_list->indices, &msrs_to_save,
4905 				 num_msrs_to_save * sizeof(u32)))
4906 			goto out;
4907 		if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
4908 				 &emulated_msrs,
4909 				 num_emulated_msrs * sizeof(u32)))
4910 			goto out;
4911 		r = 0;
4912 		break;
4913 	}
4914 	case KVM_GET_SUPPORTED_CPUID:
4915 	case KVM_GET_EMULATED_CPUID: {
4916 		struct kvm_cpuid2 __user *cpuid_arg = argp;
4917 		struct kvm_cpuid2 cpuid;
4918 
4919 		r = -EFAULT;
4920 		if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
4921 			goto out;
4922 
4923 		r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries,
4924 					    ioctl);
4925 		if (r)
4926 			goto out;
4927 
4928 		r = -EFAULT;
4929 		if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid)))
4930 			goto out;
4931 		r = 0;
4932 		break;
4933 	}
4934 	case KVM_X86_GET_MCE_CAP_SUPPORTED:
4935 		r = -EFAULT;
4936 		if (copy_to_user(argp, &kvm_caps.supported_mce_cap,
4937 				 sizeof(kvm_caps.supported_mce_cap)))
4938 			goto out;
4939 		r = 0;
4940 		break;
4941 	case KVM_GET_MSR_FEATURE_INDEX_LIST: {
4942 		struct kvm_msr_list __user *user_msr_list = argp;
4943 		struct kvm_msr_list msr_list;
4944 		unsigned int n;
4945 
4946 		r = -EFAULT;
4947 		if (copy_from_user(&msr_list, user_msr_list, sizeof(msr_list)))
4948 			goto out;
4949 		n = msr_list.nmsrs;
4950 		msr_list.nmsrs = num_msr_based_features;
4951 		if (copy_to_user(user_msr_list, &msr_list, sizeof(msr_list)))
4952 			goto out;
4953 		r = -E2BIG;
4954 		if (n < msr_list.nmsrs)
4955 			goto out;
4956 		r = -EFAULT;
4957 		if (copy_to_user(user_msr_list->indices, &msr_based_features,
4958 				 num_msr_based_features * sizeof(u32)))
4959 			goto out;
4960 		r = 0;
4961 		break;
4962 	}
4963 	case KVM_GET_MSRS:
4964 		r = msr_io(NULL, argp, do_get_msr_feature, 1);
4965 		break;
4966 #ifdef CONFIG_KVM_HYPERV
4967 	case KVM_GET_SUPPORTED_HV_CPUID:
4968 		r = kvm_ioctl_get_supported_hv_cpuid(NULL, argp);
4969 		break;
4970 #endif
4971 	case KVM_GET_DEVICE_ATTR: {
4972 		struct kvm_device_attr attr;
4973 		r = -EFAULT;
4974 		if (copy_from_user(&attr, (void __user *)arg, sizeof(attr)))
4975 			break;
4976 		r = kvm_x86_dev_get_attr(&attr);
4977 		break;
4978 	}
4979 	case KVM_HAS_DEVICE_ATTR: {
4980 		struct kvm_device_attr attr;
4981 		r = -EFAULT;
4982 		if (copy_from_user(&attr, (void __user *)arg, sizeof(attr)))
4983 			break;
4984 		r = kvm_x86_dev_has_attr(&attr);
4985 		break;
4986 	}
4987 	default:
4988 		r = -EINVAL;
4989 		break;
4990 	}
4991 out:
4992 	return r;
4993 }
4994 
4995 static void wbinvd_ipi(void *garbage)
4996 {
4997 	wbinvd();
4998 }
4999 
5000 static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
5001 {
5002 	return kvm_arch_has_noncoherent_dma(vcpu->kvm);
5003 }
5004 
5005 void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
5006 {
5007 	/* Address WBINVD may be executed by guest */
5008 	if (need_emulate_wbinvd(vcpu)) {
5009 		if (static_call(kvm_x86_has_wbinvd_exit)())
5010 			cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
5011 		else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
5012 			smp_call_function_single(vcpu->cpu,
5013 					wbinvd_ipi, NULL, 1);
5014 	}
5015 
5016 	static_call(kvm_x86_vcpu_load)(vcpu, cpu);
5017 
5018 	/* Save host pkru register if supported */
5019 	vcpu->arch.host_pkru = read_pkru();
5020 
5021 	/* Apply any externally detected TSC adjustments (due to suspend) */
5022 	if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
5023 		adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
5024 		vcpu->arch.tsc_offset_adjustment = 0;
5025 		kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
5026 	}
5027 
5028 	if (unlikely(vcpu->cpu != cpu) || kvm_check_tsc_unstable()) {
5029 		s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
5030 				rdtsc() - vcpu->arch.last_host_tsc;
5031 		if (tsc_delta < 0)
5032 			mark_tsc_unstable("KVM discovered backwards TSC");
5033 
5034 		if (kvm_check_tsc_unstable()) {
5035 			u64 offset = kvm_compute_l1_tsc_offset(vcpu,
5036 						vcpu->arch.last_guest_tsc);
5037 			kvm_vcpu_write_tsc_offset(vcpu, offset);
5038 			vcpu->arch.tsc_catchup = 1;
5039 		}
5040 
5041 		if (kvm_lapic_hv_timer_in_use(vcpu))
5042 			kvm_lapic_restart_hv_timer(vcpu);
5043 
5044 		/*
5045 		 * On a host with synchronized TSC, there is no need to update
5046 		 * kvmclock on vcpu->cpu migration
5047 		 */
5048 		if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1)
5049 			kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
5050 		if (vcpu->cpu != cpu)
5051 			kvm_make_request(KVM_REQ_MIGRATE_TIMER, vcpu);
5052 		vcpu->cpu = cpu;
5053 	}
5054 
5055 	kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
5056 }
5057 
5058 static void kvm_steal_time_set_preempted(struct kvm_vcpu *vcpu)
5059 {
5060 	struct gfn_to_hva_cache *ghc = &vcpu->arch.st.cache;
5061 	struct kvm_steal_time __user *st;
5062 	struct kvm_memslots *slots;
5063 	static const u8 preempted = KVM_VCPU_PREEMPTED;
5064 	gpa_t gpa = vcpu->arch.st.msr_val & KVM_STEAL_VALID_BITS;
5065 
5066 	/*
5067 	 * The vCPU can be marked preempted if and only if the VM-Exit was on
5068 	 * an instruction boundary and will not trigger guest emulation of any
5069 	 * kind (see vcpu_run).  Vendor specific code controls (conservatively)
5070 	 * when this is true, for example allowing the vCPU to be marked
5071 	 * preempted if and only if the VM-Exit was due to a host interrupt.
5072 	 */
5073 	if (!vcpu->arch.at_instruction_boundary) {
5074 		vcpu->stat.preemption_other++;
5075 		return;
5076 	}
5077 
5078 	vcpu->stat.preemption_reported++;
5079 	if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
5080 		return;
5081 
5082 	if (vcpu->arch.st.preempted)
5083 		return;
5084 
5085 	/* This happens on process exit */
5086 	if (unlikely(current->mm != vcpu->kvm->mm))
5087 		return;
5088 
5089 	slots = kvm_memslots(vcpu->kvm);
5090 
5091 	if (unlikely(slots->generation != ghc->generation ||
5092 		     gpa != ghc->gpa ||
5093 		     kvm_is_error_hva(ghc->hva) || !ghc->memslot))
5094 		return;
5095 
5096 	st = (struct kvm_steal_time __user *)ghc->hva;
5097 	BUILD_BUG_ON(sizeof(st->preempted) != sizeof(preempted));
5098 
5099 	if (!copy_to_user_nofault(&st->preempted, &preempted, sizeof(preempted)))
5100 		vcpu->arch.st.preempted = KVM_VCPU_PREEMPTED;
5101 
5102 	mark_page_dirty_in_slot(vcpu->kvm, ghc->memslot, gpa_to_gfn(ghc->gpa));
5103 }
5104 
5105 void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
5106 {
5107 	int idx;
5108 
5109 	if (vcpu->preempted) {
5110 		vcpu->arch.preempted_in_kernel = kvm_arch_vcpu_in_kernel(vcpu);
5111 
5112 		/*
5113 		 * Take the srcu lock as memslots will be accessed to check the gfn
5114 		 * cache generation against the memslots generation.
5115 		 */
5116 		idx = srcu_read_lock(&vcpu->kvm->srcu);
5117 		if (kvm_xen_msr_enabled(vcpu->kvm))
5118 			kvm_xen_runstate_set_preempted(vcpu);
5119 		else
5120 			kvm_steal_time_set_preempted(vcpu);
5121 		srcu_read_unlock(&vcpu->kvm->srcu, idx);
5122 	}
5123 
5124 	static_call(kvm_x86_vcpu_put)(vcpu);
5125 	vcpu->arch.last_host_tsc = rdtsc();
5126 }
5127 
5128 static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
5129 				    struct kvm_lapic_state *s)
5130 {
5131 	static_call_cond(kvm_x86_sync_pir_to_irr)(vcpu);
5132 
5133 	return kvm_apic_get_state(vcpu, s);
5134 }
5135 
5136 static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
5137 				    struct kvm_lapic_state *s)
5138 {
5139 	int r;
5140 
5141 	r = kvm_apic_set_state(vcpu, s);
5142 	if (r)
5143 		return r;
5144 	update_cr8_intercept(vcpu);
5145 
5146 	return 0;
5147 }
5148 
5149 static int kvm_cpu_accept_dm_intr(struct kvm_vcpu *vcpu)
5150 {
5151 	/*
5152 	 * We can accept userspace's request for interrupt injection
5153 	 * as long as we have a place to store the interrupt number.
5154 	 * The actual injection will happen when the CPU is able to
5155 	 * deliver the interrupt.
5156 	 */
5157 	if (kvm_cpu_has_extint(vcpu))
5158 		return false;
5159 
5160 	/* Acknowledging ExtINT does not happen if LINT0 is masked.  */
5161 	return (!lapic_in_kernel(vcpu) ||
5162 		kvm_apic_accept_pic_intr(vcpu));
5163 }
5164 
5165 static int kvm_vcpu_ready_for_interrupt_injection(struct kvm_vcpu *vcpu)
5166 {
5167 	/*
5168 	 * Do not cause an interrupt window exit if an exception
5169 	 * is pending or an event needs reinjection; userspace
5170 	 * might want to inject the interrupt manually using KVM_SET_REGS
5171 	 * or KVM_SET_SREGS.  For that to work, we must be at an
5172 	 * instruction boundary and with no events half-injected.
5173 	 */
5174 	return (kvm_arch_interrupt_allowed(vcpu) &&
5175 		kvm_cpu_accept_dm_intr(vcpu) &&
5176 		!kvm_event_needs_reinjection(vcpu) &&
5177 		!kvm_is_exception_pending(vcpu));
5178 }
5179 
5180 static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
5181 				    struct kvm_interrupt *irq)
5182 {
5183 	if (irq->irq >= KVM_NR_INTERRUPTS)
5184 		return -EINVAL;
5185 
5186 	if (!irqchip_in_kernel(vcpu->kvm)) {
5187 		kvm_queue_interrupt(vcpu, irq->irq, false);
5188 		kvm_make_request(KVM_REQ_EVENT, vcpu);
5189 		return 0;
5190 	}
5191 
5192 	/*
5193 	 * With in-kernel LAPIC, we only use this to inject EXTINT, so
5194 	 * fail for in-kernel 8259.
5195 	 */
5196 	if (pic_in_kernel(vcpu->kvm))
5197 		return -ENXIO;
5198 
5199 	if (vcpu->arch.pending_external_vector != -1)
5200 		return -EEXIST;
5201 
5202 	vcpu->arch.pending_external_vector = irq->irq;
5203 	kvm_make_request(KVM_REQ_EVENT, vcpu);
5204 	return 0;
5205 }
5206 
5207 static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
5208 {
5209 	kvm_inject_nmi(vcpu);
5210 
5211 	return 0;
5212 }
5213 
5214 static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
5215 					   struct kvm_tpr_access_ctl *tac)
5216 {
5217 	if (tac->flags)
5218 		return -EINVAL;
5219 	vcpu->arch.tpr_access_reporting = !!tac->enabled;
5220 	return 0;
5221 }
5222 
5223 static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
5224 					u64 mcg_cap)
5225 {
5226 	int r;
5227 	unsigned bank_num = mcg_cap & 0xff, bank;
5228 
5229 	r = -EINVAL;
5230 	if (!bank_num || bank_num > KVM_MAX_MCE_BANKS)
5231 		goto out;
5232 	if (mcg_cap & ~(kvm_caps.supported_mce_cap | 0xff | 0xff0000))
5233 		goto out;
5234 	r = 0;
5235 	vcpu->arch.mcg_cap = mcg_cap;
5236 	/* Init IA32_MCG_CTL to all 1s */
5237 	if (mcg_cap & MCG_CTL_P)
5238 		vcpu->arch.mcg_ctl = ~(u64)0;
5239 	/* Init IA32_MCi_CTL to all 1s, IA32_MCi_CTL2 to all 0s */
5240 	for (bank = 0; bank < bank_num; bank++) {
5241 		vcpu->arch.mce_banks[bank*4] = ~(u64)0;
5242 		if (mcg_cap & MCG_CMCI_P)
5243 			vcpu->arch.mci_ctl2_banks[bank] = 0;
5244 	}
5245 
5246 	kvm_apic_after_set_mcg_cap(vcpu);
5247 
5248 	static_call(kvm_x86_setup_mce)(vcpu);
5249 out:
5250 	return r;
5251 }
5252 
5253 /*
5254  * Validate this is an UCNA (uncorrectable no action) error by checking the
5255  * MCG_STATUS and MCi_STATUS registers:
5256  * - none of the bits for Machine Check Exceptions are set
5257  * - both the VAL (valid) and UC (uncorrectable) bits are set
5258  * MCI_STATUS_PCC - Processor Context Corrupted
5259  * MCI_STATUS_S - Signaled as a Machine Check Exception
5260  * MCI_STATUS_AR - Software recoverable Action Required
5261  */
5262 static bool is_ucna(struct kvm_x86_mce *mce)
5263 {
5264 	return	!mce->mcg_status &&
5265 		!(mce->status & (MCI_STATUS_PCC | MCI_STATUS_S | MCI_STATUS_AR)) &&
5266 		(mce->status & MCI_STATUS_VAL) &&
5267 		(mce->status & MCI_STATUS_UC);
5268 }
5269 
5270 static int kvm_vcpu_x86_set_ucna(struct kvm_vcpu *vcpu, struct kvm_x86_mce *mce, u64* banks)
5271 {
5272 	u64 mcg_cap = vcpu->arch.mcg_cap;
5273 
5274 	banks[1] = mce->status;
5275 	banks[2] = mce->addr;
5276 	banks[3] = mce->misc;
5277 	vcpu->arch.mcg_status = mce->mcg_status;
5278 
5279 	if (!(mcg_cap & MCG_CMCI_P) ||
5280 	    !(vcpu->arch.mci_ctl2_banks[mce->bank] & MCI_CTL2_CMCI_EN))
5281 		return 0;
5282 
5283 	if (lapic_in_kernel(vcpu))
5284 		kvm_apic_local_deliver(vcpu->arch.apic, APIC_LVTCMCI);
5285 
5286 	return 0;
5287 }
5288 
5289 static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
5290 				      struct kvm_x86_mce *mce)
5291 {
5292 	u64 mcg_cap = vcpu->arch.mcg_cap;
5293 	unsigned bank_num = mcg_cap & 0xff;
5294 	u64 *banks = vcpu->arch.mce_banks;
5295 
5296 	if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
5297 		return -EINVAL;
5298 
5299 	banks += array_index_nospec(4 * mce->bank, 4 * bank_num);
5300 
5301 	if (is_ucna(mce))
5302 		return kvm_vcpu_x86_set_ucna(vcpu, mce, banks);
5303 
5304 	/*
5305 	 * if IA32_MCG_CTL is not all 1s, the uncorrected error
5306 	 * reporting is disabled
5307 	 */
5308 	if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
5309 	    vcpu->arch.mcg_ctl != ~(u64)0)
5310 		return 0;
5311 	/*
5312 	 * if IA32_MCi_CTL is not all 1s, the uncorrected error
5313 	 * reporting is disabled for the bank
5314 	 */
5315 	if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
5316 		return 0;
5317 	if (mce->status & MCI_STATUS_UC) {
5318 		if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
5319 		    !kvm_is_cr4_bit_set(vcpu, X86_CR4_MCE)) {
5320 			kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
5321 			return 0;
5322 		}
5323 		if (banks[1] & MCI_STATUS_VAL)
5324 			mce->status |= MCI_STATUS_OVER;
5325 		banks[2] = mce->addr;
5326 		banks[3] = mce->misc;
5327 		vcpu->arch.mcg_status = mce->mcg_status;
5328 		banks[1] = mce->status;
5329 		kvm_queue_exception(vcpu, MC_VECTOR);
5330 	} else if (!(banks[1] & MCI_STATUS_VAL)
5331 		   || !(banks[1] & MCI_STATUS_UC)) {
5332 		if (banks[1] & MCI_STATUS_VAL)
5333 			mce->status |= MCI_STATUS_OVER;
5334 		banks[2] = mce->addr;
5335 		banks[3] = mce->misc;
5336 		banks[1] = mce->status;
5337 	} else
5338 		banks[1] |= MCI_STATUS_OVER;
5339 	return 0;
5340 }
5341 
5342 static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
5343 					       struct kvm_vcpu_events *events)
5344 {
5345 	struct kvm_queued_exception *ex;
5346 
5347 	process_nmi(vcpu);
5348 
5349 #ifdef CONFIG_KVM_SMM
5350 	if (kvm_check_request(KVM_REQ_SMI, vcpu))
5351 		process_smi(vcpu);
5352 #endif
5353 
5354 	/*
5355 	 * KVM's ABI only allows for one exception to be migrated.  Luckily,
5356 	 * the only time there can be two queued exceptions is if there's a
5357 	 * non-exiting _injected_ exception, and a pending exiting exception.
5358 	 * In that case, ignore the VM-Exiting exception as it's an extension
5359 	 * of the injected exception.
5360 	 */
5361 	if (vcpu->arch.exception_vmexit.pending &&
5362 	    !vcpu->arch.exception.pending &&
5363 	    !vcpu->arch.exception.injected)
5364 		ex = &vcpu->arch.exception_vmexit;
5365 	else
5366 		ex = &vcpu->arch.exception;
5367 
5368 	/*
5369 	 * In guest mode, payload delivery should be deferred if the exception
5370 	 * will be intercepted by L1, e.g. KVM should not modifying CR2 if L1
5371 	 * intercepts #PF, ditto for DR6 and #DBs.  If the per-VM capability,
5372 	 * KVM_CAP_EXCEPTION_PAYLOAD, is not set, userspace may or may not
5373 	 * propagate the payload and so it cannot be safely deferred.  Deliver
5374 	 * the payload if the capability hasn't been requested.
5375 	 */
5376 	if (!vcpu->kvm->arch.exception_payload_enabled &&
5377 	    ex->pending && ex->has_payload)
5378 		kvm_deliver_exception_payload(vcpu, ex);
5379 
5380 	memset(events, 0, sizeof(*events));
5381 
5382 	/*
5383 	 * The API doesn't provide the instruction length for software
5384 	 * exceptions, so don't report them. As long as the guest RIP
5385 	 * isn't advanced, we should expect to encounter the exception
5386 	 * again.
5387 	 */
5388 	if (!kvm_exception_is_soft(ex->vector)) {
5389 		events->exception.injected = ex->injected;
5390 		events->exception.pending = ex->pending;
5391 		/*
5392 		 * For ABI compatibility, deliberately conflate
5393 		 * pending and injected exceptions when
5394 		 * KVM_CAP_EXCEPTION_PAYLOAD isn't enabled.
5395 		 */
5396 		if (!vcpu->kvm->arch.exception_payload_enabled)
5397 			events->exception.injected |= ex->pending;
5398 	}
5399 	events->exception.nr = ex->vector;
5400 	events->exception.has_error_code = ex->has_error_code;
5401 	events->exception.error_code = ex->error_code;
5402 	events->exception_has_payload = ex->has_payload;
5403 	events->exception_payload = ex->payload;
5404 
5405 	events->interrupt.injected =
5406 		vcpu->arch.interrupt.injected && !vcpu->arch.interrupt.soft;
5407 	events->interrupt.nr = vcpu->arch.interrupt.nr;
5408 	events->interrupt.shadow = static_call(kvm_x86_get_interrupt_shadow)(vcpu);
5409 
5410 	events->nmi.injected = vcpu->arch.nmi_injected;
5411 	events->nmi.pending = kvm_get_nr_pending_nmis(vcpu);
5412 	events->nmi.masked = static_call(kvm_x86_get_nmi_mask)(vcpu);
5413 
5414 	/* events->sipi_vector is never valid when reporting to user space */
5415 
5416 #ifdef CONFIG_KVM_SMM
5417 	events->smi.smm = is_smm(vcpu);
5418 	events->smi.pending = vcpu->arch.smi_pending;
5419 	events->smi.smm_inside_nmi =
5420 		!!(vcpu->arch.hflags & HF_SMM_INSIDE_NMI_MASK);
5421 #endif
5422 	events->smi.latched_init = kvm_lapic_latched_init(vcpu);
5423 
5424 	events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
5425 			 | KVM_VCPUEVENT_VALID_SHADOW
5426 			 | KVM_VCPUEVENT_VALID_SMM);
5427 	if (vcpu->kvm->arch.exception_payload_enabled)
5428 		events->flags |= KVM_VCPUEVENT_VALID_PAYLOAD;
5429 	if (vcpu->kvm->arch.triple_fault_event) {
5430 		events->triple_fault.pending = kvm_test_request(KVM_REQ_TRIPLE_FAULT, vcpu);
5431 		events->flags |= KVM_VCPUEVENT_VALID_TRIPLE_FAULT;
5432 	}
5433 }
5434 
5435 static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
5436 					      struct kvm_vcpu_events *events)
5437 {
5438 	if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
5439 			      | KVM_VCPUEVENT_VALID_SIPI_VECTOR
5440 			      | KVM_VCPUEVENT_VALID_SHADOW
5441 			      | KVM_VCPUEVENT_VALID_SMM
5442 			      | KVM_VCPUEVENT_VALID_PAYLOAD
5443 			      | KVM_VCPUEVENT_VALID_TRIPLE_FAULT))
5444 		return -EINVAL;
5445 
5446 	if (events->flags & KVM_VCPUEVENT_VALID_PAYLOAD) {
5447 		if (!vcpu->kvm->arch.exception_payload_enabled)
5448 			return -EINVAL;
5449 		if (events->exception.pending)
5450 			events->exception.injected = 0;
5451 		else
5452 			events->exception_has_payload = 0;
5453 	} else {
5454 		events->exception.pending = 0;
5455 		events->exception_has_payload = 0;
5456 	}
5457 
5458 	if ((events->exception.injected || events->exception.pending) &&
5459 	    (events->exception.nr > 31 || events->exception.nr == NMI_VECTOR))
5460 		return -EINVAL;
5461 
5462 	/* INITs are latched while in SMM */
5463 	if (events->flags & KVM_VCPUEVENT_VALID_SMM &&
5464 	    (events->smi.smm || events->smi.pending) &&
5465 	    vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED)
5466 		return -EINVAL;
5467 
5468 	process_nmi(vcpu);
5469 
5470 	/*
5471 	 * Flag that userspace is stuffing an exception, the next KVM_RUN will
5472 	 * morph the exception to a VM-Exit if appropriate.  Do this only for
5473 	 * pending exceptions, already-injected exceptions are not subject to
5474 	 * intercpetion.  Note, userspace that conflates pending and injected
5475 	 * is hosed, and will incorrectly convert an injected exception into a
5476 	 * pending exception, which in turn may cause a spurious VM-Exit.
5477 	 */
5478 	vcpu->arch.exception_from_userspace = events->exception.pending;
5479 
5480 	vcpu->arch.exception_vmexit.pending = false;
5481 
5482 	vcpu->arch.exception.injected = events->exception.injected;
5483 	vcpu->arch.exception.pending = events->exception.pending;
5484 	vcpu->arch.exception.vector = events->exception.nr;
5485 	vcpu->arch.exception.has_error_code = events->exception.has_error_code;
5486 	vcpu->arch.exception.error_code = events->exception.error_code;
5487 	vcpu->arch.exception.has_payload = events->exception_has_payload;
5488 	vcpu->arch.exception.payload = events->exception_payload;
5489 
5490 	vcpu->arch.interrupt.injected = events->interrupt.injected;
5491 	vcpu->arch.interrupt.nr = events->interrupt.nr;
5492 	vcpu->arch.interrupt.soft = events->interrupt.soft;
5493 	if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
5494 		static_call(kvm_x86_set_interrupt_shadow)(vcpu,
5495 						events->interrupt.shadow);
5496 
5497 	vcpu->arch.nmi_injected = events->nmi.injected;
5498 	if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING) {
5499 		vcpu->arch.nmi_pending = 0;
5500 		atomic_set(&vcpu->arch.nmi_queued, events->nmi.pending);
5501 		if (events->nmi.pending)
5502 			kvm_make_request(KVM_REQ_NMI, vcpu);
5503 	}
5504 	static_call(kvm_x86_set_nmi_mask)(vcpu, events->nmi.masked);
5505 
5506 	if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR &&
5507 	    lapic_in_kernel(vcpu))
5508 		vcpu->arch.apic->sipi_vector = events->sipi_vector;
5509 
5510 	if (events->flags & KVM_VCPUEVENT_VALID_SMM) {
5511 #ifdef CONFIG_KVM_SMM
5512 		if (!!(vcpu->arch.hflags & HF_SMM_MASK) != events->smi.smm) {
5513 			kvm_leave_nested(vcpu);
5514 			kvm_smm_changed(vcpu, events->smi.smm);
5515 		}
5516 
5517 		vcpu->arch.smi_pending = events->smi.pending;
5518 
5519 		if (events->smi.smm) {
5520 			if (events->smi.smm_inside_nmi)
5521 				vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
5522 			else
5523 				vcpu->arch.hflags &= ~HF_SMM_INSIDE_NMI_MASK;
5524 		}
5525 
5526 #else
5527 		if (events->smi.smm || events->smi.pending ||
5528 		    events->smi.smm_inside_nmi)
5529 			return -EINVAL;
5530 #endif
5531 
5532 		if (lapic_in_kernel(vcpu)) {
5533 			if (events->smi.latched_init)
5534 				set_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
5535 			else
5536 				clear_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
5537 		}
5538 	}
5539 
5540 	if (events->flags & KVM_VCPUEVENT_VALID_TRIPLE_FAULT) {
5541 		if (!vcpu->kvm->arch.triple_fault_event)
5542 			return -EINVAL;
5543 		if (events->triple_fault.pending)
5544 			kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
5545 		else
5546 			kvm_clear_request(KVM_REQ_TRIPLE_FAULT, vcpu);
5547 	}
5548 
5549 	kvm_make_request(KVM_REQ_EVENT, vcpu);
5550 
5551 	return 0;
5552 }
5553 
5554 static int kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
5555 					    struct kvm_debugregs *dbgregs)
5556 {
5557 	unsigned int i;
5558 
5559 	if (vcpu->kvm->arch.has_protected_state &&
5560 	    vcpu->arch.guest_state_protected)
5561 		return -EINVAL;
5562 
5563 	memset(dbgregs, 0, sizeof(*dbgregs));
5564 
5565 	BUILD_BUG_ON(ARRAY_SIZE(vcpu->arch.db) != ARRAY_SIZE(dbgregs->db));
5566 	for (i = 0; i < ARRAY_SIZE(vcpu->arch.db); i++)
5567 		dbgregs->db[i] = vcpu->arch.db[i];
5568 
5569 	dbgregs->dr6 = vcpu->arch.dr6;
5570 	dbgregs->dr7 = vcpu->arch.dr7;
5571 	return 0;
5572 }
5573 
5574 static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
5575 					    struct kvm_debugregs *dbgregs)
5576 {
5577 	unsigned int i;
5578 
5579 	if (vcpu->kvm->arch.has_protected_state &&
5580 	    vcpu->arch.guest_state_protected)
5581 		return -EINVAL;
5582 
5583 	if (dbgregs->flags)
5584 		return -EINVAL;
5585 
5586 	if (!kvm_dr6_valid(dbgregs->dr6))
5587 		return -EINVAL;
5588 	if (!kvm_dr7_valid(dbgregs->dr7))
5589 		return -EINVAL;
5590 
5591 	for (i = 0; i < ARRAY_SIZE(vcpu->arch.db); i++)
5592 		vcpu->arch.db[i] = dbgregs->db[i];
5593 
5594 	kvm_update_dr0123(vcpu);
5595 	vcpu->arch.dr6 = dbgregs->dr6;
5596 	vcpu->arch.dr7 = dbgregs->dr7;
5597 	kvm_update_dr7(vcpu);
5598 
5599 	return 0;
5600 }
5601 
5602 
5603 static int kvm_vcpu_ioctl_x86_get_xsave2(struct kvm_vcpu *vcpu,
5604 					 u8 *state, unsigned int size)
5605 {
5606 	/*
5607 	 * Only copy state for features that are enabled for the guest.  The
5608 	 * state itself isn't problematic, but setting bits in the header for
5609 	 * features that are supported in *this* host but not exposed to the
5610 	 * guest can result in KVM_SET_XSAVE failing when live migrating to a
5611 	 * compatible host without the features that are NOT exposed to the
5612 	 * guest.
5613 	 *
5614 	 * FP+SSE can always be saved/restored via KVM_{G,S}ET_XSAVE, even if
5615 	 * XSAVE/XCRO are not exposed to the guest, and even if XSAVE isn't
5616 	 * supported by the host.
5617 	 */
5618 	u64 supported_xcr0 = vcpu->arch.guest_supported_xcr0 |
5619 			     XFEATURE_MASK_FPSSE;
5620 
5621 	if (fpstate_is_confidential(&vcpu->arch.guest_fpu))
5622 		return vcpu->kvm->arch.has_protected_state ? -EINVAL : 0;
5623 
5624 	fpu_copy_guest_fpstate_to_uabi(&vcpu->arch.guest_fpu, state, size,
5625 				       supported_xcr0, vcpu->arch.pkru);
5626 	return 0;
5627 }
5628 
5629 static int kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
5630 					struct kvm_xsave *guest_xsave)
5631 {
5632 	return kvm_vcpu_ioctl_x86_get_xsave2(vcpu, (void *)guest_xsave->region,
5633 					     sizeof(guest_xsave->region));
5634 }
5635 
5636 static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
5637 					struct kvm_xsave *guest_xsave)
5638 {
5639 	if (fpstate_is_confidential(&vcpu->arch.guest_fpu))
5640 		return vcpu->kvm->arch.has_protected_state ? -EINVAL : 0;
5641 
5642 	return fpu_copy_uabi_to_guest_fpstate(&vcpu->arch.guest_fpu,
5643 					      guest_xsave->region,
5644 					      kvm_caps.supported_xcr0,
5645 					      &vcpu->arch.pkru);
5646 }
5647 
5648 static int kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
5649 				       struct kvm_xcrs *guest_xcrs)
5650 {
5651 	if (vcpu->kvm->arch.has_protected_state &&
5652 	    vcpu->arch.guest_state_protected)
5653 		return -EINVAL;
5654 
5655 	if (!boot_cpu_has(X86_FEATURE_XSAVE)) {
5656 		guest_xcrs->nr_xcrs = 0;
5657 		return 0;
5658 	}
5659 
5660 	guest_xcrs->nr_xcrs = 1;
5661 	guest_xcrs->flags = 0;
5662 	guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
5663 	guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
5664 	return 0;
5665 }
5666 
5667 static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
5668 				       struct kvm_xcrs *guest_xcrs)
5669 {
5670 	int i, r = 0;
5671 
5672 	if (vcpu->kvm->arch.has_protected_state &&
5673 	    vcpu->arch.guest_state_protected)
5674 		return -EINVAL;
5675 
5676 	if (!boot_cpu_has(X86_FEATURE_XSAVE))
5677 		return -EINVAL;
5678 
5679 	if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
5680 		return -EINVAL;
5681 
5682 	for (i = 0; i < guest_xcrs->nr_xcrs; i++)
5683 		/* Only support XCR0 currently */
5684 		if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) {
5685 			r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
5686 				guest_xcrs->xcrs[i].value);
5687 			break;
5688 		}
5689 	if (r)
5690 		r = -EINVAL;
5691 	return r;
5692 }
5693 
5694 /*
5695  * kvm_set_guest_paused() indicates to the guest kernel that it has been
5696  * stopped by the hypervisor.  This function will be called from the host only.
5697  * EINVAL is returned when the host attempts to set the flag for a guest that
5698  * does not support pv clocks.
5699  */
5700 static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
5701 {
5702 	if (!vcpu->arch.pv_time.active)
5703 		return -EINVAL;
5704 	vcpu->arch.pvclock_set_guest_stopped_request = true;
5705 	kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
5706 	return 0;
5707 }
5708 
5709 static int kvm_arch_tsc_has_attr(struct kvm_vcpu *vcpu,
5710 				 struct kvm_device_attr *attr)
5711 {
5712 	int r;
5713 
5714 	switch (attr->attr) {
5715 	case KVM_VCPU_TSC_OFFSET:
5716 		r = 0;
5717 		break;
5718 	default:
5719 		r = -ENXIO;
5720 	}
5721 
5722 	return r;
5723 }
5724 
5725 static int kvm_arch_tsc_get_attr(struct kvm_vcpu *vcpu,
5726 				 struct kvm_device_attr *attr)
5727 {
5728 	u64 __user *uaddr = u64_to_user_ptr(attr->addr);
5729 	int r;
5730 
5731 	switch (attr->attr) {
5732 	case KVM_VCPU_TSC_OFFSET:
5733 		r = -EFAULT;
5734 		if (put_user(vcpu->arch.l1_tsc_offset, uaddr))
5735 			break;
5736 		r = 0;
5737 		break;
5738 	default:
5739 		r = -ENXIO;
5740 	}
5741 
5742 	return r;
5743 }
5744 
5745 static int kvm_arch_tsc_set_attr(struct kvm_vcpu *vcpu,
5746 				 struct kvm_device_attr *attr)
5747 {
5748 	u64 __user *uaddr = u64_to_user_ptr(attr->addr);
5749 	struct kvm *kvm = vcpu->kvm;
5750 	int r;
5751 
5752 	switch (attr->attr) {
5753 	case KVM_VCPU_TSC_OFFSET: {
5754 		u64 offset, tsc, ns;
5755 		unsigned long flags;
5756 		bool matched;
5757 
5758 		r = -EFAULT;
5759 		if (get_user(offset, uaddr))
5760 			break;
5761 
5762 		raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
5763 
5764 		matched = (vcpu->arch.virtual_tsc_khz &&
5765 			   kvm->arch.last_tsc_khz == vcpu->arch.virtual_tsc_khz &&
5766 			   kvm->arch.last_tsc_offset == offset);
5767 
5768 		tsc = kvm_scale_tsc(rdtsc(), vcpu->arch.l1_tsc_scaling_ratio) + offset;
5769 		ns = get_kvmclock_base_ns();
5770 
5771 		kvm->arch.user_set_tsc = true;
5772 		__kvm_synchronize_tsc(vcpu, offset, tsc, ns, matched);
5773 		raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
5774 
5775 		r = 0;
5776 		break;
5777 	}
5778 	default:
5779 		r = -ENXIO;
5780 	}
5781 
5782 	return r;
5783 }
5784 
5785 static int kvm_vcpu_ioctl_device_attr(struct kvm_vcpu *vcpu,
5786 				      unsigned int ioctl,
5787 				      void __user *argp)
5788 {
5789 	struct kvm_device_attr attr;
5790 	int r;
5791 
5792 	if (copy_from_user(&attr, argp, sizeof(attr)))
5793 		return -EFAULT;
5794 
5795 	if (attr.group != KVM_VCPU_TSC_CTRL)
5796 		return -ENXIO;
5797 
5798 	switch (ioctl) {
5799 	case KVM_HAS_DEVICE_ATTR:
5800 		r = kvm_arch_tsc_has_attr(vcpu, &attr);
5801 		break;
5802 	case KVM_GET_DEVICE_ATTR:
5803 		r = kvm_arch_tsc_get_attr(vcpu, &attr);
5804 		break;
5805 	case KVM_SET_DEVICE_ATTR:
5806 		r = kvm_arch_tsc_set_attr(vcpu, &attr);
5807 		break;
5808 	}
5809 
5810 	return r;
5811 }
5812 
5813 static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu,
5814 				     struct kvm_enable_cap *cap)
5815 {
5816 	if (cap->flags)
5817 		return -EINVAL;
5818 
5819 	switch (cap->cap) {
5820 #ifdef CONFIG_KVM_HYPERV
5821 	case KVM_CAP_HYPERV_SYNIC2:
5822 		if (cap->args[0])
5823 			return -EINVAL;
5824 		fallthrough;
5825 
5826 	case KVM_CAP_HYPERV_SYNIC:
5827 		if (!irqchip_in_kernel(vcpu->kvm))
5828 			return -EINVAL;
5829 		return kvm_hv_activate_synic(vcpu, cap->cap ==
5830 					     KVM_CAP_HYPERV_SYNIC2);
5831 	case KVM_CAP_HYPERV_ENLIGHTENED_VMCS:
5832 		{
5833 			int r;
5834 			uint16_t vmcs_version;
5835 			void __user *user_ptr;
5836 
5837 			if (!kvm_x86_ops.nested_ops->enable_evmcs)
5838 				return -ENOTTY;
5839 			r = kvm_x86_ops.nested_ops->enable_evmcs(vcpu, &vmcs_version);
5840 			if (!r) {
5841 				user_ptr = (void __user *)(uintptr_t)cap->args[0];
5842 				if (copy_to_user(user_ptr, &vmcs_version,
5843 						 sizeof(vmcs_version)))
5844 					r = -EFAULT;
5845 			}
5846 			return r;
5847 		}
5848 	case KVM_CAP_HYPERV_DIRECT_TLBFLUSH:
5849 		if (!kvm_x86_ops.enable_l2_tlb_flush)
5850 			return -ENOTTY;
5851 
5852 		return static_call(kvm_x86_enable_l2_tlb_flush)(vcpu);
5853 
5854 	case KVM_CAP_HYPERV_ENFORCE_CPUID:
5855 		return kvm_hv_set_enforce_cpuid(vcpu, cap->args[0]);
5856 #endif
5857 
5858 	case KVM_CAP_ENFORCE_PV_FEATURE_CPUID:
5859 		vcpu->arch.pv_cpuid.enforce = cap->args[0];
5860 		if (vcpu->arch.pv_cpuid.enforce)
5861 			kvm_update_pv_runtime(vcpu);
5862 
5863 		return 0;
5864 	default:
5865 		return -EINVAL;
5866 	}
5867 }
5868 
5869 long kvm_arch_vcpu_ioctl(struct file *filp,
5870 			 unsigned int ioctl, unsigned long arg)
5871 {
5872 	struct kvm_vcpu *vcpu = filp->private_data;
5873 	void __user *argp = (void __user *)arg;
5874 	int r;
5875 	union {
5876 		struct kvm_sregs2 *sregs2;
5877 		struct kvm_lapic_state *lapic;
5878 		struct kvm_xsave *xsave;
5879 		struct kvm_xcrs *xcrs;
5880 		void *buffer;
5881 	} u;
5882 
5883 	vcpu_load(vcpu);
5884 
5885 	u.buffer = NULL;
5886 	switch (ioctl) {
5887 	case KVM_GET_LAPIC: {
5888 		r = -EINVAL;
5889 		if (!lapic_in_kernel(vcpu))
5890 			goto out;
5891 		u.lapic = kzalloc(sizeof(struct kvm_lapic_state),
5892 				GFP_KERNEL_ACCOUNT);
5893 
5894 		r = -ENOMEM;
5895 		if (!u.lapic)
5896 			goto out;
5897 		r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
5898 		if (r)
5899 			goto out;
5900 		r = -EFAULT;
5901 		if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
5902 			goto out;
5903 		r = 0;
5904 		break;
5905 	}
5906 	case KVM_SET_LAPIC: {
5907 		r = -EINVAL;
5908 		if (!lapic_in_kernel(vcpu))
5909 			goto out;
5910 		u.lapic = memdup_user(argp, sizeof(*u.lapic));
5911 		if (IS_ERR(u.lapic)) {
5912 			r = PTR_ERR(u.lapic);
5913 			goto out_nofree;
5914 		}
5915 
5916 		r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
5917 		break;
5918 	}
5919 	case KVM_INTERRUPT: {
5920 		struct kvm_interrupt irq;
5921 
5922 		r = -EFAULT;
5923 		if (copy_from_user(&irq, argp, sizeof(irq)))
5924 			goto out;
5925 		r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
5926 		break;
5927 	}
5928 	case KVM_NMI: {
5929 		r = kvm_vcpu_ioctl_nmi(vcpu);
5930 		break;
5931 	}
5932 	case KVM_SMI: {
5933 		r = kvm_inject_smi(vcpu);
5934 		break;
5935 	}
5936 	case KVM_SET_CPUID: {
5937 		struct kvm_cpuid __user *cpuid_arg = argp;
5938 		struct kvm_cpuid cpuid;
5939 
5940 		r = -EFAULT;
5941 		if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
5942 			goto out;
5943 		r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
5944 		break;
5945 	}
5946 	case KVM_SET_CPUID2: {
5947 		struct kvm_cpuid2 __user *cpuid_arg = argp;
5948 		struct kvm_cpuid2 cpuid;
5949 
5950 		r = -EFAULT;
5951 		if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
5952 			goto out;
5953 		r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
5954 					      cpuid_arg->entries);
5955 		break;
5956 	}
5957 	case KVM_GET_CPUID2: {
5958 		struct kvm_cpuid2 __user *cpuid_arg = argp;
5959 		struct kvm_cpuid2 cpuid;
5960 
5961 		r = -EFAULT;
5962 		if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
5963 			goto out;
5964 		r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
5965 					      cpuid_arg->entries);
5966 		if (r)
5967 			goto out;
5968 		r = -EFAULT;
5969 		if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid)))
5970 			goto out;
5971 		r = 0;
5972 		break;
5973 	}
5974 	case KVM_GET_MSRS: {
5975 		int idx = srcu_read_lock(&vcpu->kvm->srcu);
5976 		r = msr_io(vcpu, argp, do_get_msr, 1);
5977 		srcu_read_unlock(&vcpu->kvm->srcu, idx);
5978 		break;
5979 	}
5980 	case KVM_SET_MSRS: {
5981 		int idx = srcu_read_lock(&vcpu->kvm->srcu);
5982 		r = msr_io(vcpu, argp, do_set_msr, 0);
5983 		srcu_read_unlock(&vcpu->kvm->srcu, idx);
5984 		break;
5985 	}
5986 	case KVM_TPR_ACCESS_REPORTING: {
5987 		struct kvm_tpr_access_ctl tac;
5988 
5989 		r = -EFAULT;
5990 		if (copy_from_user(&tac, argp, sizeof(tac)))
5991 			goto out;
5992 		r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
5993 		if (r)
5994 			goto out;
5995 		r = -EFAULT;
5996 		if (copy_to_user(argp, &tac, sizeof(tac)))
5997 			goto out;
5998 		r = 0;
5999 		break;
6000 	};
6001 	case KVM_SET_VAPIC_ADDR: {
6002 		struct kvm_vapic_addr va;
6003 		int idx;
6004 
6005 		r = -EINVAL;
6006 		if (!lapic_in_kernel(vcpu))
6007 			goto out;
6008 		r = -EFAULT;
6009 		if (copy_from_user(&va, argp, sizeof(va)))
6010 			goto out;
6011 		idx = srcu_read_lock(&vcpu->kvm->srcu);
6012 		r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
6013 		srcu_read_unlock(&vcpu->kvm->srcu, idx);
6014 		break;
6015 	}
6016 	case KVM_X86_SETUP_MCE: {
6017 		u64 mcg_cap;
6018 
6019 		r = -EFAULT;
6020 		if (copy_from_user(&mcg_cap, argp, sizeof(mcg_cap)))
6021 			goto out;
6022 		r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
6023 		break;
6024 	}
6025 	case KVM_X86_SET_MCE: {
6026 		struct kvm_x86_mce mce;
6027 
6028 		r = -EFAULT;
6029 		if (copy_from_user(&mce, argp, sizeof(mce)))
6030 			goto out;
6031 		r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
6032 		break;
6033 	}
6034 	case KVM_GET_VCPU_EVENTS: {
6035 		struct kvm_vcpu_events events;
6036 
6037 		kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
6038 
6039 		r = -EFAULT;
6040 		if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
6041 			break;
6042 		r = 0;
6043 		break;
6044 	}
6045 	case KVM_SET_VCPU_EVENTS: {
6046 		struct kvm_vcpu_events events;
6047 
6048 		r = -EFAULT;
6049 		if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
6050 			break;
6051 
6052 		r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
6053 		break;
6054 	}
6055 	case KVM_GET_DEBUGREGS: {
6056 		struct kvm_debugregs dbgregs;
6057 
6058 		r = kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
6059 		if (r < 0)
6060 			break;
6061 
6062 		r = -EFAULT;
6063 		if (copy_to_user(argp, &dbgregs,
6064 				 sizeof(struct kvm_debugregs)))
6065 			break;
6066 		r = 0;
6067 		break;
6068 	}
6069 	case KVM_SET_DEBUGREGS: {
6070 		struct kvm_debugregs dbgregs;
6071 
6072 		r = -EFAULT;
6073 		if (copy_from_user(&dbgregs, argp,
6074 				   sizeof(struct kvm_debugregs)))
6075 			break;
6076 
6077 		r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
6078 		break;
6079 	}
6080 	case KVM_GET_XSAVE: {
6081 		r = -EINVAL;
6082 		if (vcpu->arch.guest_fpu.uabi_size > sizeof(struct kvm_xsave))
6083 			break;
6084 
6085 		u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL_ACCOUNT);
6086 		r = -ENOMEM;
6087 		if (!u.xsave)
6088 			break;
6089 
6090 		r = kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
6091 		if (r < 0)
6092 			break;
6093 
6094 		r = -EFAULT;
6095 		if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
6096 			break;
6097 		r = 0;
6098 		break;
6099 	}
6100 	case KVM_SET_XSAVE: {
6101 		int size = vcpu->arch.guest_fpu.uabi_size;
6102 
6103 		u.xsave = memdup_user(argp, size);
6104 		if (IS_ERR(u.xsave)) {
6105 			r = PTR_ERR(u.xsave);
6106 			goto out_nofree;
6107 		}
6108 
6109 		r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
6110 		break;
6111 	}
6112 
6113 	case KVM_GET_XSAVE2: {
6114 		int size = vcpu->arch.guest_fpu.uabi_size;
6115 
6116 		u.xsave = kzalloc(size, GFP_KERNEL_ACCOUNT);
6117 		r = -ENOMEM;
6118 		if (!u.xsave)
6119 			break;
6120 
6121 		r = kvm_vcpu_ioctl_x86_get_xsave2(vcpu, u.buffer, size);
6122 		if (r < 0)
6123 			break;
6124 
6125 		r = -EFAULT;
6126 		if (copy_to_user(argp, u.xsave, size))
6127 			break;
6128 
6129 		r = 0;
6130 		break;
6131 	}
6132 
6133 	case KVM_GET_XCRS: {
6134 		u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL_ACCOUNT);
6135 		r = -ENOMEM;
6136 		if (!u.xcrs)
6137 			break;
6138 
6139 		r = kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
6140 		if (r < 0)
6141 			break;
6142 
6143 		r = -EFAULT;
6144 		if (copy_to_user(argp, u.xcrs,
6145 				 sizeof(struct kvm_xcrs)))
6146 			break;
6147 		r = 0;
6148 		break;
6149 	}
6150 	case KVM_SET_XCRS: {
6151 		u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
6152 		if (IS_ERR(u.xcrs)) {
6153 			r = PTR_ERR(u.xcrs);
6154 			goto out_nofree;
6155 		}
6156 
6157 		r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
6158 		break;
6159 	}
6160 	case KVM_SET_TSC_KHZ: {
6161 		u32 user_tsc_khz;
6162 
6163 		r = -EINVAL;
6164 		user_tsc_khz = (u32)arg;
6165 
6166 		if (kvm_caps.has_tsc_control &&
6167 		    user_tsc_khz >= kvm_caps.max_guest_tsc_khz)
6168 			goto out;
6169 
6170 		if (user_tsc_khz == 0)
6171 			user_tsc_khz = tsc_khz;
6172 
6173 		if (!kvm_set_tsc_khz(vcpu, user_tsc_khz))
6174 			r = 0;
6175 
6176 		goto out;
6177 	}
6178 	case KVM_GET_TSC_KHZ: {
6179 		r = vcpu->arch.virtual_tsc_khz;
6180 		goto out;
6181 	}
6182 	case KVM_KVMCLOCK_CTRL: {
6183 		r = kvm_set_guest_paused(vcpu);
6184 		goto out;
6185 	}
6186 	case KVM_ENABLE_CAP: {
6187 		struct kvm_enable_cap cap;
6188 
6189 		r = -EFAULT;
6190 		if (copy_from_user(&cap, argp, sizeof(cap)))
6191 			goto out;
6192 		r = kvm_vcpu_ioctl_enable_cap(vcpu, &cap);
6193 		break;
6194 	}
6195 	case KVM_GET_NESTED_STATE: {
6196 		struct kvm_nested_state __user *user_kvm_nested_state = argp;
6197 		u32 user_data_size;
6198 
6199 		r = -EINVAL;
6200 		if (!kvm_x86_ops.nested_ops->get_state)
6201 			break;
6202 
6203 		BUILD_BUG_ON(sizeof(user_data_size) != sizeof(user_kvm_nested_state->size));
6204 		r = -EFAULT;
6205 		if (get_user(user_data_size, &user_kvm_nested_state->size))
6206 			break;
6207 
6208 		r = kvm_x86_ops.nested_ops->get_state(vcpu, user_kvm_nested_state,
6209 						     user_data_size);
6210 		if (r < 0)
6211 			break;
6212 
6213 		if (r > user_data_size) {
6214 			if (put_user(r, &user_kvm_nested_state->size))
6215 				r = -EFAULT;
6216 			else
6217 				r = -E2BIG;
6218 			break;
6219 		}
6220 
6221 		r = 0;
6222 		break;
6223 	}
6224 	case KVM_SET_NESTED_STATE: {
6225 		struct kvm_nested_state __user *user_kvm_nested_state = argp;
6226 		struct kvm_nested_state kvm_state;
6227 		int idx;
6228 
6229 		r = -EINVAL;
6230 		if (!kvm_x86_ops.nested_ops->set_state)
6231 			break;
6232 
6233 		r = -EFAULT;
6234 		if (copy_from_user(&kvm_state, user_kvm_nested_state, sizeof(kvm_state)))
6235 			break;
6236 
6237 		r = -EINVAL;
6238 		if (kvm_state.size < sizeof(kvm_state))
6239 			break;
6240 
6241 		if (kvm_state.flags &
6242 		    ~(KVM_STATE_NESTED_RUN_PENDING | KVM_STATE_NESTED_GUEST_MODE
6243 		      | KVM_STATE_NESTED_EVMCS | KVM_STATE_NESTED_MTF_PENDING
6244 		      | KVM_STATE_NESTED_GIF_SET))
6245 			break;
6246 
6247 		/* nested_run_pending implies guest_mode.  */
6248 		if ((kvm_state.flags & KVM_STATE_NESTED_RUN_PENDING)
6249 		    && !(kvm_state.flags & KVM_STATE_NESTED_GUEST_MODE))
6250 			break;
6251 
6252 		idx = srcu_read_lock(&vcpu->kvm->srcu);
6253 		r = kvm_x86_ops.nested_ops->set_state(vcpu, user_kvm_nested_state, &kvm_state);
6254 		srcu_read_unlock(&vcpu->kvm->srcu, idx);
6255 		break;
6256 	}
6257 #ifdef CONFIG_KVM_HYPERV
6258 	case KVM_GET_SUPPORTED_HV_CPUID:
6259 		r = kvm_ioctl_get_supported_hv_cpuid(vcpu, argp);
6260 		break;
6261 #endif
6262 #ifdef CONFIG_KVM_XEN
6263 	case KVM_XEN_VCPU_GET_ATTR: {
6264 		struct kvm_xen_vcpu_attr xva;
6265 
6266 		r = -EFAULT;
6267 		if (copy_from_user(&xva, argp, sizeof(xva)))
6268 			goto out;
6269 		r = kvm_xen_vcpu_get_attr(vcpu, &xva);
6270 		if (!r && copy_to_user(argp, &xva, sizeof(xva)))
6271 			r = -EFAULT;
6272 		break;
6273 	}
6274 	case KVM_XEN_VCPU_SET_ATTR: {
6275 		struct kvm_xen_vcpu_attr xva;
6276 
6277 		r = -EFAULT;
6278 		if (copy_from_user(&xva, argp, sizeof(xva)))
6279 			goto out;
6280 		r = kvm_xen_vcpu_set_attr(vcpu, &xva);
6281 		break;
6282 	}
6283 #endif
6284 	case KVM_GET_SREGS2: {
6285 		r = -EINVAL;
6286 		if (vcpu->kvm->arch.has_protected_state &&
6287 		    vcpu->arch.guest_state_protected)
6288 			goto out;
6289 
6290 		u.sregs2 = kzalloc(sizeof(struct kvm_sregs2), GFP_KERNEL);
6291 		r = -ENOMEM;
6292 		if (!u.sregs2)
6293 			goto out;
6294 		__get_sregs2(vcpu, u.sregs2);
6295 		r = -EFAULT;
6296 		if (copy_to_user(argp, u.sregs2, sizeof(struct kvm_sregs2)))
6297 			goto out;
6298 		r = 0;
6299 		break;
6300 	}
6301 	case KVM_SET_SREGS2: {
6302 		r = -EINVAL;
6303 		if (vcpu->kvm->arch.has_protected_state &&
6304 		    vcpu->arch.guest_state_protected)
6305 			goto out;
6306 
6307 		u.sregs2 = memdup_user(argp, sizeof(struct kvm_sregs2));
6308 		if (IS_ERR(u.sregs2)) {
6309 			r = PTR_ERR(u.sregs2);
6310 			u.sregs2 = NULL;
6311 			goto out;
6312 		}
6313 		r = __set_sregs2(vcpu, u.sregs2);
6314 		break;
6315 	}
6316 	case KVM_HAS_DEVICE_ATTR:
6317 	case KVM_GET_DEVICE_ATTR:
6318 	case KVM_SET_DEVICE_ATTR:
6319 		r = kvm_vcpu_ioctl_device_attr(vcpu, ioctl, argp);
6320 		break;
6321 	default:
6322 		r = -EINVAL;
6323 	}
6324 out:
6325 	kfree(u.buffer);
6326 out_nofree:
6327 	vcpu_put(vcpu);
6328 	return r;
6329 }
6330 
6331 vm_fault_t kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
6332 {
6333 	return VM_FAULT_SIGBUS;
6334 }
6335 
6336 static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
6337 {
6338 	int ret;
6339 
6340 	if (addr > (unsigned int)(-3 * PAGE_SIZE))
6341 		return -EINVAL;
6342 	ret = static_call(kvm_x86_set_tss_addr)(kvm, addr);
6343 	return ret;
6344 }
6345 
6346 static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
6347 					      u64 ident_addr)
6348 {
6349 	return static_call(kvm_x86_set_identity_map_addr)(kvm, ident_addr);
6350 }
6351 
6352 static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
6353 					 unsigned long kvm_nr_mmu_pages)
6354 {
6355 	if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
6356 		return -EINVAL;
6357 
6358 	mutex_lock(&kvm->slots_lock);
6359 
6360 	kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
6361 	kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
6362 
6363 	mutex_unlock(&kvm->slots_lock);
6364 	return 0;
6365 }
6366 
6367 static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
6368 {
6369 	struct kvm_pic *pic = kvm->arch.vpic;
6370 	int r;
6371 
6372 	r = 0;
6373 	switch (chip->chip_id) {
6374 	case KVM_IRQCHIP_PIC_MASTER:
6375 		memcpy(&chip->chip.pic, &pic->pics[0],
6376 			sizeof(struct kvm_pic_state));
6377 		break;
6378 	case KVM_IRQCHIP_PIC_SLAVE:
6379 		memcpy(&chip->chip.pic, &pic->pics[1],
6380 			sizeof(struct kvm_pic_state));
6381 		break;
6382 	case KVM_IRQCHIP_IOAPIC:
6383 		kvm_get_ioapic(kvm, &chip->chip.ioapic);
6384 		break;
6385 	default:
6386 		r = -EINVAL;
6387 		break;
6388 	}
6389 	return r;
6390 }
6391 
6392 static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
6393 {
6394 	struct kvm_pic *pic = kvm->arch.vpic;
6395 	int r;
6396 
6397 	r = 0;
6398 	switch (chip->chip_id) {
6399 	case KVM_IRQCHIP_PIC_MASTER:
6400 		spin_lock(&pic->lock);
6401 		memcpy(&pic->pics[0], &chip->chip.pic,
6402 			sizeof(struct kvm_pic_state));
6403 		spin_unlock(&pic->lock);
6404 		break;
6405 	case KVM_IRQCHIP_PIC_SLAVE:
6406 		spin_lock(&pic->lock);
6407 		memcpy(&pic->pics[1], &chip->chip.pic,
6408 			sizeof(struct kvm_pic_state));
6409 		spin_unlock(&pic->lock);
6410 		break;
6411 	case KVM_IRQCHIP_IOAPIC:
6412 		kvm_set_ioapic(kvm, &chip->chip.ioapic);
6413 		break;
6414 	default:
6415 		r = -EINVAL;
6416 		break;
6417 	}
6418 	kvm_pic_update_irq(pic);
6419 	return r;
6420 }
6421 
6422 static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
6423 {
6424 	struct kvm_kpit_state *kps = &kvm->arch.vpit->pit_state;
6425 
6426 	BUILD_BUG_ON(sizeof(*ps) != sizeof(kps->channels));
6427 
6428 	mutex_lock(&kps->lock);
6429 	memcpy(ps, &kps->channels, sizeof(*ps));
6430 	mutex_unlock(&kps->lock);
6431 	return 0;
6432 }
6433 
6434 static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
6435 {
6436 	int i;
6437 	struct kvm_pit *pit = kvm->arch.vpit;
6438 
6439 	mutex_lock(&pit->pit_state.lock);
6440 	memcpy(&pit->pit_state.channels, ps, sizeof(*ps));
6441 	for (i = 0; i < 3; i++)
6442 		kvm_pit_load_count(pit, i, ps->channels[i].count, 0);
6443 	mutex_unlock(&pit->pit_state.lock);
6444 	return 0;
6445 }
6446 
6447 static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
6448 {
6449 	mutex_lock(&kvm->arch.vpit->pit_state.lock);
6450 	memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
6451 		sizeof(ps->channels));
6452 	ps->flags = kvm->arch.vpit->pit_state.flags;
6453 	mutex_unlock(&kvm->arch.vpit->pit_state.lock);
6454 	memset(&ps->reserved, 0, sizeof(ps->reserved));
6455 	return 0;
6456 }
6457 
6458 static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
6459 {
6460 	int start = 0;
6461 	int i;
6462 	u32 prev_legacy, cur_legacy;
6463 	struct kvm_pit *pit = kvm->arch.vpit;
6464 
6465 	mutex_lock(&pit->pit_state.lock);
6466 	prev_legacy = pit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
6467 	cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
6468 	if (!prev_legacy && cur_legacy)
6469 		start = 1;
6470 	memcpy(&pit->pit_state.channels, &ps->channels,
6471 	       sizeof(pit->pit_state.channels));
6472 	pit->pit_state.flags = ps->flags;
6473 	for (i = 0; i < 3; i++)
6474 		kvm_pit_load_count(pit, i, pit->pit_state.channels[i].count,
6475 				   start && i == 0);
6476 	mutex_unlock(&pit->pit_state.lock);
6477 	return 0;
6478 }
6479 
6480 static int kvm_vm_ioctl_reinject(struct kvm *kvm,
6481 				 struct kvm_reinject_control *control)
6482 {
6483 	struct kvm_pit *pit = kvm->arch.vpit;
6484 
6485 	/* pit->pit_state.lock was overloaded to prevent userspace from getting
6486 	 * an inconsistent state after running multiple KVM_REINJECT_CONTROL
6487 	 * ioctls in parallel.  Use a separate lock if that ioctl isn't rare.
6488 	 */
6489 	mutex_lock(&pit->pit_state.lock);
6490 	kvm_pit_set_reinject(pit, control->pit_reinject);
6491 	mutex_unlock(&pit->pit_state.lock);
6492 
6493 	return 0;
6494 }
6495 
6496 void kvm_arch_sync_dirty_log(struct kvm *kvm, struct kvm_memory_slot *memslot)
6497 {
6498 
6499 	/*
6500 	 * Flush all CPUs' dirty log buffers to the  dirty_bitmap.  Called
6501 	 * before reporting dirty_bitmap to userspace.  KVM flushes the buffers
6502 	 * on all VM-Exits, thus we only need to kick running vCPUs to force a
6503 	 * VM-Exit.
6504 	 */
6505 	struct kvm_vcpu *vcpu;
6506 	unsigned long i;
6507 
6508 	if (!kvm_x86_ops.cpu_dirty_log_size)
6509 		return;
6510 
6511 	kvm_for_each_vcpu(i, vcpu, kvm)
6512 		kvm_vcpu_kick(vcpu);
6513 }
6514 
6515 int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event,
6516 			bool line_status)
6517 {
6518 	if (!irqchip_in_kernel(kvm))
6519 		return -ENXIO;
6520 
6521 	irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
6522 					irq_event->irq, irq_event->level,
6523 					line_status);
6524 	return 0;
6525 }
6526 
6527 int kvm_vm_ioctl_enable_cap(struct kvm *kvm,
6528 			    struct kvm_enable_cap *cap)
6529 {
6530 	int r;
6531 
6532 	if (cap->flags)
6533 		return -EINVAL;
6534 
6535 	switch (cap->cap) {
6536 	case KVM_CAP_DISABLE_QUIRKS2:
6537 		r = -EINVAL;
6538 		if (cap->args[0] & ~KVM_X86_VALID_QUIRKS)
6539 			break;
6540 		fallthrough;
6541 	case KVM_CAP_DISABLE_QUIRKS:
6542 		kvm->arch.disabled_quirks = cap->args[0];
6543 		r = 0;
6544 		break;
6545 	case KVM_CAP_SPLIT_IRQCHIP: {
6546 		mutex_lock(&kvm->lock);
6547 		r = -EINVAL;
6548 		if (cap->args[0] > MAX_NR_RESERVED_IOAPIC_PINS)
6549 			goto split_irqchip_unlock;
6550 		r = -EEXIST;
6551 		if (irqchip_in_kernel(kvm))
6552 			goto split_irqchip_unlock;
6553 		if (kvm->created_vcpus)
6554 			goto split_irqchip_unlock;
6555 		r = kvm_setup_empty_irq_routing(kvm);
6556 		if (r)
6557 			goto split_irqchip_unlock;
6558 		/* Pairs with irqchip_in_kernel. */
6559 		smp_wmb();
6560 		kvm->arch.irqchip_mode = KVM_IRQCHIP_SPLIT;
6561 		kvm->arch.nr_reserved_ioapic_pins = cap->args[0];
6562 		kvm_clear_apicv_inhibit(kvm, APICV_INHIBIT_REASON_ABSENT);
6563 		r = 0;
6564 split_irqchip_unlock:
6565 		mutex_unlock(&kvm->lock);
6566 		break;
6567 	}
6568 	case KVM_CAP_X2APIC_API:
6569 		r = -EINVAL;
6570 		if (cap->args[0] & ~KVM_X2APIC_API_VALID_FLAGS)
6571 			break;
6572 
6573 		if (cap->args[0] & KVM_X2APIC_API_USE_32BIT_IDS)
6574 			kvm->arch.x2apic_format = true;
6575 		if (cap->args[0] & KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
6576 			kvm->arch.x2apic_broadcast_quirk_disabled = true;
6577 
6578 		r = 0;
6579 		break;
6580 	case KVM_CAP_X86_DISABLE_EXITS:
6581 		r = -EINVAL;
6582 		if (cap->args[0] & ~KVM_X86_DISABLE_VALID_EXITS)
6583 			break;
6584 
6585 		if (cap->args[0] & KVM_X86_DISABLE_EXITS_PAUSE)
6586 			kvm->arch.pause_in_guest = true;
6587 
6588 #define SMT_RSB_MSG "This processor is affected by the Cross-Thread Return Predictions vulnerability. " \
6589 		    "KVM_CAP_X86_DISABLE_EXITS should only be used with SMT disabled or trusted guests."
6590 
6591 		if (!mitigate_smt_rsb) {
6592 			if (boot_cpu_has_bug(X86_BUG_SMT_RSB) && cpu_smt_possible() &&
6593 			    (cap->args[0] & ~KVM_X86_DISABLE_EXITS_PAUSE))
6594 				pr_warn_once(SMT_RSB_MSG);
6595 
6596 			if ((cap->args[0] & KVM_X86_DISABLE_EXITS_MWAIT) &&
6597 			    kvm_can_mwait_in_guest())
6598 				kvm->arch.mwait_in_guest = true;
6599 			if (cap->args[0] & KVM_X86_DISABLE_EXITS_HLT)
6600 				kvm->arch.hlt_in_guest = true;
6601 			if (cap->args[0] & KVM_X86_DISABLE_EXITS_CSTATE)
6602 				kvm->arch.cstate_in_guest = true;
6603 		}
6604 
6605 		r = 0;
6606 		break;
6607 	case KVM_CAP_MSR_PLATFORM_INFO:
6608 		kvm->arch.guest_can_read_msr_platform_info = cap->args[0];
6609 		r = 0;
6610 		break;
6611 	case KVM_CAP_EXCEPTION_PAYLOAD:
6612 		kvm->arch.exception_payload_enabled = cap->args[0];
6613 		r = 0;
6614 		break;
6615 	case KVM_CAP_X86_TRIPLE_FAULT_EVENT:
6616 		kvm->arch.triple_fault_event = cap->args[0];
6617 		r = 0;
6618 		break;
6619 	case KVM_CAP_X86_USER_SPACE_MSR:
6620 		r = -EINVAL;
6621 		if (cap->args[0] & ~KVM_MSR_EXIT_REASON_VALID_MASK)
6622 			break;
6623 		kvm->arch.user_space_msr_mask = cap->args[0];
6624 		r = 0;
6625 		break;
6626 	case KVM_CAP_X86_BUS_LOCK_EXIT:
6627 		r = -EINVAL;
6628 		if (cap->args[0] & ~KVM_BUS_LOCK_DETECTION_VALID_MODE)
6629 			break;
6630 
6631 		if ((cap->args[0] & KVM_BUS_LOCK_DETECTION_OFF) &&
6632 		    (cap->args[0] & KVM_BUS_LOCK_DETECTION_EXIT))
6633 			break;
6634 
6635 		if (kvm_caps.has_bus_lock_exit &&
6636 		    cap->args[0] & KVM_BUS_LOCK_DETECTION_EXIT)
6637 			kvm->arch.bus_lock_detection_enabled = true;
6638 		r = 0;
6639 		break;
6640 #ifdef CONFIG_X86_SGX_KVM
6641 	case KVM_CAP_SGX_ATTRIBUTE: {
6642 		unsigned long allowed_attributes = 0;
6643 
6644 		r = sgx_set_attribute(&allowed_attributes, cap->args[0]);
6645 		if (r)
6646 			break;
6647 
6648 		/* KVM only supports the PROVISIONKEY privileged attribute. */
6649 		if ((allowed_attributes & SGX_ATTR_PROVISIONKEY) &&
6650 		    !(allowed_attributes & ~SGX_ATTR_PROVISIONKEY))
6651 			kvm->arch.sgx_provisioning_allowed = true;
6652 		else
6653 			r = -EINVAL;
6654 		break;
6655 	}
6656 #endif
6657 	case KVM_CAP_VM_COPY_ENC_CONTEXT_FROM:
6658 		r = -EINVAL;
6659 		if (!kvm_x86_ops.vm_copy_enc_context_from)
6660 			break;
6661 
6662 		r = static_call(kvm_x86_vm_copy_enc_context_from)(kvm, cap->args[0]);
6663 		break;
6664 	case KVM_CAP_VM_MOVE_ENC_CONTEXT_FROM:
6665 		r = -EINVAL;
6666 		if (!kvm_x86_ops.vm_move_enc_context_from)
6667 			break;
6668 
6669 		r = static_call(kvm_x86_vm_move_enc_context_from)(kvm, cap->args[0]);
6670 		break;
6671 	case KVM_CAP_EXIT_HYPERCALL:
6672 		if (cap->args[0] & ~KVM_EXIT_HYPERCALL_VALID_MASK) {
6673 			r = -EINVAL;
6674 			break;
6675 		}
6676 		kvm->arch.hypercall_exit_enabled = cap->args[0];
6677 		r = 0;
6678 		break;
6679 	case KVM_CAP_EXIT_ON_EMULATION_FAILURE:
6680 		r = -EINVAL;
6681 		if (cap->args[0] & ~1)
6682 			break;
6683 		kvm->arch.exit_on_emulation_error = cap->args[0];
6684 		r = 0;
6685 		break;
6686 	case KVM_CAP_PMU_CAPABILITY:
6687 		r = -EINVAL;
6688 		if (!enable_pmu || (cap->args[0] & ~KVM_CAP_PMU_VALID_MASK))
6689 			break;
6690 
6691 		mutex_lock(&kvm->lock);
6692 		if (!kvm->created_vcpus) {
6693 			kvm->arch.enable_pmu = !(cap->args[0] & KVM_PMU_CAP_DISABLE);
6694 			r = 0;
6695 		}
6696 		mutex_unlock(&kvm->lock);
6697 		break;
6698 	case KVM_CAP_MAX_VCPU_ID:
6699 		r = -EINVAL;
6700 		if (cap->args[0] > KVM_MAX_VCPU_IDS)
6701 			break;
6702 
6703 		mutex_lock(&kvm->lock);
6704 		if (kvm->arch.max_vcpu_ids == cap->args[0]) {
6705 			r = 0;
6706 		} else if (!kvm->arch.max_vcpu_ids) {
6707 			kvm->arch.max_vcpu_ids = cap->args[0];
6708 			r = 0;
6709 		}
6710 		mutex_unlock(&kvm->lock);
6711 		break;
6712 	case KVM_CAP_X86_NOTIFY_VMEXIT:
6713 		r = -EINVAL;
6714 		if ((u32)cap->args[0] & ~KVM_X86_NOTIFY_VMEXIT_VALID_BITS)
6715 			break;
6716 		if (!kvm_caps.has_notify_vmexit)
6717 			break;
6718 		if (!((u32)cap->args[0] & KVM_X86_NOTIFY_VMEXIT_ENABLED))
6719 			break;
6720 		mutex_lock(&kvm->lock);
6721 		if (!kvm->created_vcpus) {
6722 			kvm->arch.notify_window = cap->args[0] >> 32;
6723 			kvm->arch.notify_vmexit_flags = (u32)cap->args[0];
6724 			r = 0;
6725 		}
6726 		mutex_unlock(&kvm->lock);
6727 		break;
6728 	case KVM_CAP_VM_DISABLE_NX_HUGE_PAGES:
6729 		r = -EINVAL;
6730 
6731 		/*
6732 		 * Since the risk of disabling NX hugepages is a guest crashing
6733 		 * the system, ensure the userspace process has permission to
6734 		 * reboot the system.
6735 		 *
6736 		 * Note that unlike the reboot() syscall, the process must have
6737 		 * this capability in the root namespace because exposing
6738 		 * /dev/kvm into a container does not limit the scope of the
6739 		 * iTLB multihit bug to that container. In other words,
6740 		 * this must use capable(), not ns_capable().
6741 		 */
6742 		if (!capable(CAP_SYS_BOOT)) {
6743 			r = -EPERM;
6744 			break;
6745 		}
6746 
6747 		if (cap->args[0])
6748 			break;
6749 
6750 		mutex_lock(&kvm->lock);
6751 		if (!kvm->created_vcpus) {
6752 			kvm->arch.disable_nx_huge_pages = true;
6753 			r = 0;
6754 		}
6755 		mutex_unlock(&kvm->lock);
6756 		break;
6757 	default:
6758 		r = -EINVAL;
6759 		break;
6760 	}
6761 	return r;
6762 }
6763 
6764 static struct kvm_x86_msr_filter *kvm_alloc_msr_filter(bool default_allow)
6765 {
6766 	struct kvm_x86_msr_filter *msr_filter;
6767 
6768 	msr_filter = kzalloc(sizeof(*msr_filter), GFP_KERNEL_ACCOUNT);
6769 	if (!msr_filter)
6770 		return NULL;
6771 
6772 	msr_filter->default_allow = default_allow;
6773 	return msr_filter;
6774 }
6775 
6776 static void kvm_free_msr_filter(struct kvm_x86_msr_filter *msr_filter)
6777 {
6778 	u32 i;
6779 
6780 	if (!msr_filter)
6781 		return;
6782 
6783 	for (i = 0; i < msr_filter->count; i++)
6784 		kfree(msr_filter->ranges[i].bitmap);
6785 
6786 	kfree(msr_filter);
6787 }
6788 
6789 static int kvm_add_msr_filter(struct kvm_x86_msr_filter *msr_filter,
6790 			      struct kvm_msr_filter_range *user_range)
6791 {
6792 	unsigned long *bitmap;
6793 	size_t bitmap_size;
6794 
6795 	if (!user_range->nmsrs)
6796 		return 0;
6797 
6798 	if (user_range->flags & ~KVM_MSR_FILTER_RANGE_VALID_MASK)
6799 		return -EINVAL;
6800 
6801 	if (!user_range->flags)
6802 		return -EINVAL;
6803 
6804 	bitmap_size = BITS_TO_LONGS(user_range->nmsrs) * sizeof(long);
6805 	if (!bitmap_size || bitmap_size > KVM_MSR_FILTER_MAX_BITMAP_SIZE)
6806 		return -EINVAL;
6807 
6808 	bitmap = memdup_user((__user u8*)user_range->bitmap, bitmap_size);
6809 	if (IS_ERR(bitmap))
6810 		return PTR_ERR(bitmap);
6811 
6812 	msr_filter->ranges[msr_filter->count] = (struct msr_bitmap_range) {
6813 		.flags = user_range->flags,
6814 		.base = user_range->base,
6815 		.nmsrs = user_range->nmsrs,
6816 		.bitmap = bitmap,
6817 	};
6818 
6819 	msr_filter->count++;
6820 	return 0;
6821 }
6822 
6823 static int kvm_vm_ioctl_set_msr_filter(struct kvm *kvm,
6824 				       struct kvm_msr_filter *filter)
6825 {
6826 	struct kvm_x86_msr_filter *new_filter, *old_filter;
6827 	bool default_allow;
6828 	bool empty = true;
6829 	int r;
6830 	u32 i;
6831 
6832 	if (filter->flags & ~KVM_MSR_FILTER_VALID_MASK)
6833 		return -EINVAL;
6834 
6835 	for (i = 0; i < ARRAY_SIZE(filter->ranges); i++)
6836 		empty &= !filter->ranges[i].nmsrs;
6837 
6838 	default_allow = !(filter->flags & KVM_MSR_FILTER_DEFAULT_DENY);
6839 	if (empty && !default_allow)
6840 		return -EINVAL;
6841 
6842 	new_filter = kvm_alloc_msr_filter(default_allow);
6843 	if (!new_filter)
6844 		return -ENOMEM;
6845 
6846 	for (i = 0; i < ARRAY_SIZE(filter->ranges); i++) {
6847 		r = kvm_add_msr_filter(new_filter, &filter->ranges[i]);
6848 		if (r) {
6849 			kvm_free_msr_filter(new_filter);
6850 			return r;
6851 		}
6852 	}
6853 
6854 	mutex_lock(&kvm->lock);
6855 	old_filter = rcu_replace_pointer(kvm->arch.msr_filter, new_filter,
6856 					 mutex_is_locked(&kvm->lock));
6857 	mutex_unlock(&kvm->lock);
6858 	synchronize_srcu(&kvm->srcu);
6859 
6860 	kvm_free_msr_filter(old_filter);
6861 
6862 	kvm_make_all_cpus_request(kvm, KVM_REQ_MSR_FILTER_CHANGED);
6863 
6864 	return 0;
6865 }
6866 
6867 #ifdef CONFIG_KVM_COMPAT
6868 /* for KVM_X86_SET_MSR_FILTER */
6869 struct kvm_msr_filter_range_compat {
6870 	__u32 flags;
6871 	__u32 nmsrs;
6872 	__u32 base;
6873 	__u32 bitmap;
6874 };
6875 
6876 struct kvm_msr_filter_compat {
6877 	__u32 flags;
6878 	struct kvm_msr_filter_range_compat ranges[KVM_MSR_FILTER_MAX_RANGES];
6879 };
6880 
6881 #define KVM_X86_SET_MSR_FILTER_COMPAT _IOW(KVMIO, 0xc6, struct kvm_msr_filter_compat)
6882 
6883 long kvm_arch_vm_compat_ioctl(struct file *filp, unsigned int ioctl,
6884 			      unsigned long arg)
6885 {
6886 	void __user *argp = (void __user *)arg;
6887 	struct kvm *kvm = filp->private_data;
6888 	long r = -ENOTTY;
6889 
6890 	switch (ioctl) {
6891 	case KVM_X86_SET_MSR_FILTER_COMPAT: {
6892 		struct kvm_msr_filter __user *user_msr_filter = argp;
6893 		struct kvm_msr_filter_compat filter_compat;
6894 		struct kvm_msr_filter filter;
6895 		int i;
6896 
6897 		if (copy_from_user(&filter_compat, user_msr_filter,
6898 				   sizeof(filter_compat)))
6899 			return -EFAULT;
6900 
6901 		filter.flags = filter_compat.flags;
6902 		for (i = 0; i < ARRAY_SIZE(filter.ranges); i++) {
6903 			struct kvm_msr_filter_range_compat *cr;
6904 
6905 			cr = &filter_compat.ranges[i];
6906 			filter.ranges[i] = (struct kvm_msr_filter_range) {
6907 				.flags = cr->flags,
6908 				.nmsrs = cr->nmsrs,
6909 				.base = cr->base,
6910 				.bitmap = (__u8 *)(ulong)cr->bitmap,
6911 			};
6912 		}
6913 
6914 		r = kvm_vm_ioctl_set_msr_filter(kvm, &filter);
6915 		break;
6916 	}
6917 	}
6918 
6919 	return r;
6920 }
6921 #endif
6922 
6923 #ifdef CONFIG_HAVE_KVM_PM_NOTIFIER
6924 static int kvm_arch_suspend_notifier(struct kvm *kvm)
6925 {
6926 	struct kvm_vcpu *vcpu;
6927 	unsigned long i;
6928 	int ret = 0;
6929 
6930 	mutex_lock(&kvm->lock);
6931 	kvm_for_each_vcpu(i, vcpu, kvm) {
6932 		if (!vcpu->arch.pv_time.active)
6933 			continue;
6934 
6935 		ret = kvm_set_guest_paused(vcpu);
6936 		if (ret) {
6937 			kvm_err("Failed to pause guest VCPU%d: %d\n",
6938 				vcpu->vcpu_id, ret);
6939 			break;
6940 		}
6941 	}
6942 	mutex_unlock(&kvm->lock);
6943 
6944 	return ret ? NOTIFY_BAD : NOTIFY_DONE;
6945 }
6946 
6947 int kvm_arch_pm_notifier(struct kvm *kvm, unsigned long state)
6948 {
6949 	switch (state) {
6950 	case PM_HIBERNATION_PREPARE:
6951 	case PM_SUSPEND_PREPARE:
6952 		return kvm_arch_suspend_notifier(kvm);
6953 	}
6954 
6955 	return NOTIFY_DONE;
6956 }
6957 #endif /* CONFIG_HAVE_KVM_PM_NOTIFIER */
6958 
6959 static int kvm_vm_ioctl_get_clock(struct kvm *kvm, void __user *argp)
6960 {
6961 	struct kvm_clock_data data = { 0 };
6962 
6963 	get_kvmclock(kvm, &data);
6964 	if (copy_to_user(argp, &data, sizeof(data)))
6965 		return -EFAULT;
6966 
6967 	return 0;
6968 }
6969 
6970 static int kvm_vm_ioctl_set_clock(struct kvm *kvm, void __user *argp)
6971 {
6972 	struct kvm_arch *ka = &kvm->arch;
6973 	struct kvm_clock_data data;
6974 	u64 now_raw_ns;
6975 
6976 	if (copy_from_user(&data, argp, sizeof(data)))
6977 		return -EFAULT;
6978 
6979 	/*
6980 	 * Only KVM_CLOCK_REALTIME is used, but allow passing the
6981 	 * result of KVM_GET_CLOCK back to KVM_SET_CLOCK.
6982 	 */
6983 	if (data.flags & ~KVM_CLOCK_VALID_FLAGS)
6984 		return -EINVAL;
6985 
6986 	kvm_hv_request_tsc_page_update(kvm);
6987 	kvm_start_pvclock_update(kvm);
6988 	pvclock_update_vm_gtod_copy(kvm);
6989 
6990 	/*
6991 	 * This pairs with kvm_guest_time_update(): when masterclock is
6992 	 * in use, we use master_kernel_ns + kvmclock_offset to set
6993 	 * unsigned 'system_time' so if we use get_kvmclock_ns() (which
6994 	 * is slightly ahead) here we risk going negative on unsigned
6995 	 * 'system_time' when 'data.clock' is very small.
6996 	 */
6997 	if (data.flags & KVM_CLOCK_REALTIME) {
6998 		u64 now_real_ns = ktime_get_real_ns();
6999 
7000 		/*
7001 		 * Avoid stepping the kvmclock backwards.
7002 		 */
7003 		if (now_real_ns > data.realtime)
7004 			data.clock += now_real_ns - data.realtime;
7005 	}
7006 
7007 	if (ka->use_master_clock)
7008 		now_raw_ns = ka->master_kernel_ns;
7009 	else
7010 		now_raw_ns = get_kvmclock_base_ns();
7011 	ka->kvmclock_offset = data.clock - now_raw_ns;
7012 	kvm_end_pvclock_update(kvm);
7013 	return 0;
7014 }
7015 
7016 int kvm_arch_vm_ioctl(struct file *filp, unsigned int ioctl, unsigned long arg)
7017 {
7018 	struct kvm *kvm = filp->private_data;
7019 	void __user *argp = (void __user *)arg;
7020 	int r = -ENOTTY;
7021 	/*
7022 	 * This union makes it completely explicit to gcc-3.x
7023 	 * that these two variables' stack usage should be
7024 	 * combined, not added together.
7025 	 */
7026 	union {
7027 		struct kvm_pit_state ps;
7028 		struct kvm_pit_state2 ps2;
7029 		struct kvm_pit_config pit_config;
7030 	} u;
7031 
7032 	switch (ioctl) {
7033 	case KVM_SET_TSS_ADDR:
7034 		r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
7035 		break;
7036 	case KVM_SET_IDENTITY_MAP_ADDR: {
7037 		u64 ident_addr;
7038 
7039 		mutex_lock(&kvm->lock);
7040 		r = -EINVAL;
7041 		if (kvm->created_vcpus)
7042 			goto set_identity_unlock;
7043 		r = -EFAULT;
7044 		if (copy_from_user(&ident_addr, argp, sizeof(ident_addr)))
7045 			goto set_identity_unlock;
7046 		r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
7047 set_identity_unlock:
7048 		mutex_unlock(&kvm->lock);
7049 		break;
7050 	}
7051 	case KVM_SET_NR_MMU_PAGES:
7052 		r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
7053 		break;
7054 	case KVM_CREATE_IRQCHIP: {
7055 		mutex_lock(&kvm->lock);
7056 
7057 		r = -EEXIST;
7058 		if (irqchip_in_kernel(kvm))
7059 			goto create_irqchip_unlock;
7060 
7061 		r = -EINVAL;
7062 		if (kvm->created_vcpus)
7063 			goto create_irqchip_unlock;
7064 
7065 		r = kvm_pic_init(kvm);
7066 		if (r)
7067 			goto create_irqchip_unlock;
7068 
7069 		r = kvm_ioapic_init(kvm);
7070 		if (r) {
7071 			kvm_pic_destroy(kvm);
7072 			goto create_irqchip_unlock;
7073 		}
7074 
7075 		r = kvm_setup_default_irq_routing(kvm);
7076 		if (r) {
7077 			kvm_ioapic_destroy(kvm);
7078 			kvm_pic_destroy(kvm);
7079 			goto create_irqchip_unlock;
7080 		}
7081 		/* Write kvm->irq_routing before enabling irqchip_in_kernel. */
7082 		smp_wmb();
7083 		kvm->arch.irqchip_mode = KVM_IRQCHIP_KERNEL;
7084 		kvm_clear_apicv_inhibit(kvm, APICV_INHIBIT_REASON_ABSENT);
7085 	create_irqchip_unlock:
7086 		mutex_unlock(&kvm->lock);
7087 		break;
7088 	}
7089 	case KVM_CREATE_PIT:
7090 		u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
7091 		goto create_pit;
7092 	case KVM_CREATE_PIT2:
7093 		r = -EFAULT;
7094 		if (copy_from_user(&u.pit_config, argp,
7095 				   sizeof(struct kvm_pit_config)))
7096 			goto out;
7097 	create_pit:
7098 		mutex_lock(&kvm->lock);
7099 		r = -EEXIST;
7100 		if (kvm->arch.vpit)
7101 			goto create_pit_unlock;
7102 		r = -ENOENT;
7103 		if (!pic_in_kernel(kvm))
7104 			goto create_pit_unlock;
7105 		r = -ENOMEM;
7106 		kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
7107 		if (kvm->arch.vpit)
7108 			r = 0;
7109 	create_pit_unlock:
7110 		mutex_unlock(&kvm->lock);
7111 		break;
7112 	case KVM_GET_IRQCHIP: {
7113 		/* 0: PIC master, 1: PIC slave, 2: IOAPIC */
7114 		struct kvm_irqchip *chip;
7115 
7116 		chip = memdup_user(argp, sizeof(*chip));
7117 		if (IS_ERR(chip)) {
7118 			r = PTR_ERR(chip);
7119 			goto out;
7120 		}
7121 
7122 		r = -ENXIO;
7123 		if (!irqchip_kernel(kvm))
7124 			goto get_irqchip_out;
7125 		r = kvm_vm_ioctl_get_irqchip(kvm, chip);
7126 		if (r)
7127 			goto get_irqchip_out;
7128 		r = -EFAULT;
7129 		if (copy_to_user(argp, chip, sizeof(*chip)))
7130 			goto get_irqchip_out;
7131 		r = 0;
7132 	get_irqchip_out:
7133 		kfree(chip);
7134 		break;
7135 	}
7136 	case KVM_SET_IRQCHIP: {
7137 		/* 0: PIC master, 1: PIC slave, 2: IOAPIC */
7138 		struct kvm_irqchip *chip;
7139 
7140 		chip = memdup_user(argp, sizeof(*chip));
7141 		if (IS_ERR(chip)) {
7142 			r = PTR_ERR(chip);
7143 			goto out;
7144 		}
7145 
7146 		r = -ENXIO;
7147 		if (!irqchip_kernel(kvm))
7148 			goto set_irqchip_out;
7149 		r = kvm_vm_ioctl_set_irqchip(kvm, chip);
7150 	set_irqchip_out:
7151 		kfree(chip);
7152 		break;
7153 	}
7154 	case KVM_GET_PIT: {
7155 		r = -EFAULT;
7156 		if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
7157 			goto out;
7158 		r = -ENXIO;
7159 		if (!kvm->arch.vpit)
7160 			goto out;
7161 		r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
7162 		if (r)
7163 			goto out;
7164 		r = -EFAULT;
7165 		if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
7166 			goto out;
7167 		r = 0;
7168 		break;
7169 	}
7170 	case KVM_SET_PIT: {
7171 		r = -EFAULT;
7172 		if (copy_from_user(&u.ps, argp, sizeof(u.ps)))
7173 			goto out;
7174 		mutex_lock(&kvm->lock);
7175 		r = -ENXIO;
7176 		if (!kvm->arch.vpit)
7177 			goto set_pit_out;
7178 		r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
7179 set_pit_out:
7180 		mutex_unlock(&kvm->lock);
7181 		break;
7182 	}
7183 	case KVM_GET_PIT2: {
7184 		r = -ENXIO;
7185 		if (!kvm->arch.vpit)
7186 			goto out;
7187 		r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
7188 		if (r)
7189 			goto out;
7190 		r = -EFAULT;
7191 		if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
7192 			goto out;
7193 		r = 0;
7194 		break;
7195 	}
7196 	case KVM_SET_PIT2: {
7197 		r = -EFAULT;
7198 		if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
7199 			goto out;
7200 		mutex_lock(&kvm->lock);
7201 		r = -ENXIO;
7202 		if (!kvm->arch.vpit)
7203 			goto set_pit2_out;
7204 		r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
7205 set_pit2_out:
7206 		mutex_unlock(&kvm->lock);
7207 		break;
7208 	}
7209 	case KVM_REINJECT_CONTROL: {
7210 		struct kvm_reinject_control control;
7211 		r =  -EFAULT;
7212 		if (copy_from_user(&control, argp, sizeof(control)))
7213 			goto out;
7214 		r = -ENXIO;
7215 		if (!kvm->arch.vpit)
7216 			goto out;
7217 		r = kvm_vm_ioctl_reinject(kvm, &control);
7218 		break;
7219 	}
7220 	case KVM_SET_BOOT_CPU_ID:
7221 		r = 0;
7222 		mutex_lock(&kvm->lock);
7223 		if (kvm->created_vcpus)
7224 			r = -EBUSY;
7225 		else
7226 			kvm->arch.bsp_vcpu_id = arg;
7227 		mutex_unlock(&kvm->lock);
7228 		break;
7229 #ifdef CONFIG_KVM_XEN
7230 	case KVM_XEN_HVM_CONFIG: {
7231 		struct kvm_xen_hvm_config xhc;
7232 		r = -EFAULT;
7233 		if (copy_from_user(&xhc, argp, sizeof(xhc)))
7234 			goto out;
7235 		r = kvm_xen_hvm_config(kvm, &xhc);
7236 		break;
7237 	}
7238 	case KVM_XEN_HVM_GET_ATTR: {
7239 		struct kvm_xen_hvm_attr xha;
7240 
7241 		r = -EFAULT;
7242 		if (copy_from_user(&xha, argp, sizeof(xha)))
7243 			goto out;
7244 		r = kvm_xen_hvm_get_attr(kvm, &xha);
7245 		if (!r && copy_to_user(argp, &xha, sizeof(xha)))
7246 			r = -EFAULT;
7247 		break;
7248 	}
7249 	case KVM_XEN_HVM_SET_ATTR: {
7250 		struct kvm_xen_hvm_attr xha;
7251 
7252 		r = -EFAULT;
7253 		if (copy_from_user(&xha, argp, sizeof(xha)))
7254 			goto out;
7255 		r = kvm_xen_hvm_set_attr(kvm, &xha);
7256 		break;
7257 	}
7258 	case KVM_XEN_HVM_EVTCHN_SEND: {
7259 		struct kvm_irq_routing_xen_evtchn uxe;
7260 
7261 		r = -EFAULT;
7262 		if (copy_from_user(&uxe, argp, sizeof(uxe)))
7263 			goto out;
7264 		r = kvm_xen_hvm_evtchn_send(kvm, &uxe);
7265 		break;
7266 	}
7267 #endif
7268 	case KVM_SET_CLOCK:
7269 		r = kvm_vm_ioctl_set_clock(kvm, argp);
7270 		break;
7271 	case KVM_GET_CLOCK:
7272 		r = kvm_vm_ioctl_get_clock(kvm, argp);
7273 		break;
7274 	case KVM_SET_TSC_KHZ: {
7275 		u32 user_tsc_khz;
7276 
7277 		r = -EINVAL;
7278 		user_tsc_khz = (u32)arg;
7279 
7280 		if (kvm_caps.has_tsc_control &&
7281 		    user_tsc_khz >= kvm_caps.max_guest_tsc_khz)
7282 			goto out;
7283 
7284 		if (user_tsc_khz == 0)
7285 			user_tsc_khz = tsc_khz;
7286 
7287 		WRITE_ONCE(kvm->arch.default_tsc_khz, user_tsc_khz);
7288 		r = 0;
7289 
7290 		goto out;
7291 	}
7292 	case KVM_GET_TSC_KHZ: {
7293 		r = READ_ONCE(kvm->arch.default_tsc_khz);
7294 		goto out;
7295 	}
7296 	case KVM_MEMORY_ENCRYPT_OP: {
7297 		r = -ENOTTY;
7298 		if (!kvm_x86_ops.mem_enc_ioctl)
7299 			goto out;
7300 
7301 		r = static_call(kvm_x86_mem_enc_ioctl)(kvm, argp);
7302 		break;
7303 	}
7304 	case KVM_MEMORY_ENCRYPT_REG_REGION: {
7305 		struct kvm_enc_region region;
7306 
7307 		r = -EFAULT;
7308 		if (copy_from_user(&region, argp, sizeof(region)))
7309 			goto out;
7310 
7311 		r = -ENOTTY;
7312 		if (!kvm_x86_ops.mem_enc_register_region)
7313 			goto out;
7314 
7315 		r = static_call(kvm_x86_mem_enc_register_region)(kvm, &region);
7316 		break;
7317 	}
7318 	case KVM_MEMORY_ENCRYPT_UNREG_REGION: {
7319 		struct kvm_enc_region region;
7320 
7321 		r = -EFAULT;
7322 		if (copy_from_user(&region, argp, sizeof(region)))
7323 			goto out;
7324 
7325 		r = -ENOTTY;
7326 		if (!kvm_x86_ops.mem_enc_unregister_region)
7327 			goto out;
7328 
7329 		r = static_call(kvm_x86_mem_enc_unregister_region)(kvm, &region);
7330 		break;
7331 	}
7332 #ifdef CONFIG_KVM_HYPERV
7333 	case KVM_HYPERV_EVENTFD: {
7334 		struct kvm_hyperv_eventfd hvevfd;
7335 
7336 		r = -EFAULT;
7337 		if (copy_from_user(&hvevfd, argp, sizeof(hvevfd)))
7338 			goto out;
7339 		r = kvm_vm_ioctl_hv_eventfd(kvm, &hvevfd);
7340 		break;
7341 	}
7342 #endif
7343 	case KVM_SET_PMU_EVENT_FILTER:
7344 		r = kvm_vm_ioctl_set_pmu_event_filter(kvm, argp);
7345 		break;
7346 	case KVM_X86_SET_MSR_FILTER: {
7347 		struct kvm_msr_filter __user *user_msr_filter = argp;
7348 		struct kvm_msr_filter filter;
7349 
7350 		if (copy_from_user(&filter, user_msr_filter, sizeof(filter)))
7351 			return -EFAULT;
7352 
7353 		r = kvm_vm_ioctl_set_msr_filter(kvm, &filter);
7354 		break;
7355 	}
7356 	default:
7357 		r = -ENOTTY;
7358 	}
7359 out:
7360 	return r;
7361 }
7362 
7363 static void kvm_probe_feature_msr(u32 msr_index)
7364 {
7365 	struct kvm_msr_entry msr = {
7366 		.index = msr_index,
7367 	};
7368 
7369 	if (kvm_get_msr_feature(&msr))
7370 		return;
7371 
7372 	msr_based_features[num_msr_based_features++] = msr_index;
7373 }
7374 
7375 static void kvm_probe_msr_to_save(u32 msr_index)
7376 {
7377 	u32 dummy[2];
7378 
7379 	if (rdmsr_safe(msr_index, &dummy[0], &dummy[1]))
7380 		return;
7381 
7382 	/*
7383 	 * Even MSRs that are valid in the host may not be exposed to guests in
7384 	 * some cases.
7385 	 */
7386 	switch (msr_index) {
7387 	case MSR_IA32_BNDCFGS:
7388 		if (!kvm_mpx_supported())
7389 			return;
7390 		break;
7391 	case MSR_TSC_AUX:
7392 		if (!kvm_cpu_cap_has(X86_FEATURE_RDTSCP) &&
7393 		    !kvm_cpu_cap_has(X86_FEATURE_RDPID))
7394 			return;
7395 		break;
7396 	case MSR_IA32_UMWAIT_CONTROL:
7397 		if (!kvm_cpu_cap_has(X86_FEATURE_WAITPKG))
7398 			return;
7399 		break;
7400 	case MSR_IA32_RTIT_CTL:
7401 	case MSR_IA32_RTIT_STATUS:
7402 		if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT))
7403 			return;
7404 		break;
7405 	case MSR_IA32_RTIT_CR3_MATCH:
7406 		if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT) ||
7407 		    !intel_pt_validate_hw_cap(PT_CAP_cr3_filtering))
7408 			return;
7409 		break;
7410 	case MSR_IA32_RTIT_OUTPUT_BASE:
7411 	case MSR_IA32_RTIT_OUTPUT_MASK:
7412 		if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT) ||
7413 		    (!intel_pt_validate_hw_cap(PT_CAP_topa_output) &&
7414 		     !intel_pt_validate_hw_cap(PT_CAP_single_range_output)))
7415 			return;
7416 		break;
7417 	case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B:
7418 		if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT) ||
7419 		    (msr_index - MSR_IA32_RTIT_ADDR0_A >=
7420 		     intel_pt_validate_hw_cap(PT_CAP_num_address_ranges) * 2))
7421 			return;
7422 		break;
7423 	case MSR_ARCH_PERFMON_PERFCTR0 ... MSR_ARCH_PERFMON_PERFCTR_MAX:
7424 		if (msr_index - MSR_ARCH_PERFMON_PERFCTR0 >=
7425 		    kvm_pmu_cap.num_counters_gp)
7426 			return;
7427 		break;
7428 	case MSR_ARCH_PERFMON_EVENTSEL0 ... MSR_ARCH_PERFMON_EVENTSEL_MAX:
7429 		if (msr_index - MSR_ARCH_PERFMON_EVENTSEL0 >=
7430 		    kvm_pmu_cap.num_counters_gp)
7431 			return;
7432 		break;
7433 	case MSR_ARCH_PERFMON_FIXED_CTR0 ... MSR_ARCH_PERFMON_FIXED_CTR_MAX:
7434 		if (msr_index - MSR_ARCH_PERFMON_FIXED_CTR0 >=
7435 		    kvm_pmu_cap.num_counters_fixed)
7436 			return;
7437 		break;
7438 	case MSR_AMD64_PERF_CNTR_GLOBAL_CTL:
7439 	case MSR_AMD64_PERF_CNTR_GLOBAL_STATUS:
7440 	case MSR_AMD64_PERF_CNTR_GLOBAL_STATUS_CLR:
7441 		if (!kvm_cpu_cap_has(X86_FEATURE_PERFMON_V2))
7442 			return;
7443 		break;
7444 	case MSR_IA32_XFD:
7445 	case MSR_IA32_XFD_ERR:
7446 		if (!kvm_cpu_cap_has(X86_FEATURE_XFD))
7447 			return;
7448 		break;
7449 	case MSR_IA32_TSX_CTRL:
7450 		if (!(kvm_get_arch_capabilities() & ARCH_CAP_TSX_CTRL_MSR))
7451 			return;
7452 		break;
7453 	default:
7454 		break;
7455 	}
7456 
7457 	msrs_to_save[num_msrs_to_save++] = msr_index;
7458 }
7459 
7460 static void kvm_init_msr_lists(void)
7461 {
7462 	unsigned i;
7463 
7464 	BUILD_BUG_ON_MSG(KVM_PMC_MAX_FIXED != 3,
7465 			 "Please update the fixed PMCs in msrs_to_save_pmu[]");
7466 
7467 	num_msrs_to_save = 0;
7468 	num_emulated_msrs = 0;
7469 	num_msr_based_features = 0;
7470 
7471 	for (i = 0; i < ARRAY_SIZE(msrs_to_save_base); i++)
7472 		kvm_probe_msr_to_save(msrs_to_save_base[i]);
7473 
7474 	if (enable_pmu) {
7475 		for (i = 0; i < ARRAY_SIZE(msrs_to_save_pmu); i++)
7476 			kvm_probe_msr_to_save(msrs_to_save_pmu[i]);
7477 	}
7478 
7479 	for (i = 0; i < ARRAY_SIZE(emulated_msrs_all); i++) {
7480 		if (!static_call(kvm_x86_has_emulated_msr)(NULL, emulated_msrs_all[i]))
7481 			continue;
7482 
7483 		emulated_msrs[num_emulated_msrs++] = emulated_msrs_all[i];
7484 	}
7485 
7486 	for (i = KVM_FIRST_EMULATED_VMX_MSR; i <= KVM_LAST_EMULATED_VMX_MSR; i++)
7487 		kvm_probe_feature_msr(i);
7488 
7489 	for (i = 0; i < ARRAY_SIZE(msr_based_features_all_except_vmx); i++)
7490 		kvm_probe_feature_msr(msr_based_features_all_except_vmx[i]);
7491 }
7492 
7493 static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
7494 			   const void *v)
7495 {
7496 	int handled = 0;
7497 	int n;
7498 
7499 	do {
7500 		n = min(len, 8);
7501 		if (!(lapic_in_kernel(vcpu) &&
7502 		      !kvm_iodevice_write(vcpu, &vcpu->arch.apic->dev, addr, n, v))
7503 		    && kvm_io_bus_write(vcpu, KVM_MMIO_BUS, addr, n, v))
7504 			break;
7505 		handled += n;
7506 		addr += n;
7507 		len -= n;
7508 		v += n;
7509 	} while (len);
7510 
7511 	return handled;
7512 }
7513 
7514 static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
7515 {
7516 	int handled = 0;
7517 	int n;
7518 
7519 	do {
7520 		n = min(len, 8);
7521 		if (!(lapic_in_kernel(vcpu) &&
7522 		      !kvm_iodevice_read(vcpu, &vcpu->arch.apic->dev,
7523 					 addr, n, v))
7524 		    && kvm_io_bus_read(vcpu, KVM_MMIO_BUS, addr, n, v))
7525 			break;
7526 		trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, v);
7527 		handled += n;
7528 		addr += n;
7529 		len -= n;
7530 		v += n;
7531 	} while (len);
7532 
7533 	return handled;
7534 }
7535 
7536 void kvm_set_segment(struct kvm_vcpu *vcpu,
7537 		     struct kvm_segment *var, int seg)
7538 {
7539 	static_call(kvm_x86_set_segment)(vcpu, var, seg);
7540 }
7541 
7542 void kvm_get_segment(struct kvm_vcpu *vcpu,
7543 		     struct kvm_segment *var, int seg)
7544 {
7545 	static_call(kvm_x86_get_segment)(vcpu, var, seg);
7546 }
7547 
7548 gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u64 access,
7549 			   struct x86_exception *exception)
7550 {
7551 	struct kvm_mmu *mmu = vcpu->arch.mmu;
7552 	gpa_t t_gpa;
7553 
7554 	BUG_ON(!mmu_is_nested(vcpu));
7555 
7556 	/* NPT walks are always user-walks */
7557 	access |= PFERR_USER_MASK;
7558 	t_gpa  = mmu->gva_to_gpa(vcpu, mmu, gpa, access, exception);
7559 
7560 	return t_gpa;
7561 }
7562 
7563 gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
7564 			      struct x86_exception *exception)
7565 {
7566 	struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
7567 
7568 	u64 access = (static_call(kvm_x86_get_cpl)(vcpu) == 3) ? PFERR_USER_MASK : 0;
7569 	return mmu->gva_to_gpa(vcpu, mmu, gva, access, exception);
7570 }
7571 EXPORT_SYMBOL_GPL(kvm_mmu_gva_to_gpa_read);
7572 
7573 gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
7574 			       struct x86_exception *exception)
7575 {
7576 	struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
7577 
7578 	u64 access = (static_call(kvm_x86_get_cpl)(vcpu) == 3) ? PFERR_USER_MASK : 0;
7579 	access |= PFERR_WRITE_MASK;
7580 	return mmu->gva_to_gpa(vcpu, mmu, gva, access, exception);
7581 }
7582 EXPORT_SYMBOL_GPL(kvm_mmu_gva_to_gpa_write);
7583 
7584 /* uses this to access any guest's mapped memory without checking CPL */
7585 gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
7586 				struct x86_exception *exception)
7587 {
7588 	struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
7589 
7590 	return mmu->gva_to_gpa(vcpu, mmu, gva, 0, exception);
7591 }
7592 
7593 static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
7594 				      struct kvm_vcpu *vcpu, u64 access,
7595 				      struct x86_exception *exception)
7596 {
7597 	struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
7598 	void *data = val;
7599 	int r = X86EMUL_CONTINUE;
7600 
7601 	while (bytes) {
7602 		gpa_t gpa = mmu->gva_to_gpa(vcpu, mmu, addr, access, exception);
7603 		unsigned offset = addr & (PAGE_SIZE-1);
7604 		unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
7605 		int ret;
7606 
7607 		if (gpa == INVALID_GPA)
7608 			return X86EMUL_PROPAGATE_FAULT;
7609 		ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, data,
7610 					       offset, toread);
7611 		if (ret < 0) {
7612 			r = X86EMUL_IO_NEEDED;
7613 			goto out;
7614 		}
7615 
7616 		bytes -= toread;
7617 		data += toread;
7618 		addr += toread;
7619 	}
7620 out:
7621 	return r;
7622 }
7623 
7624 /* used for instruction fetching */
7625 static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
7626 				gva_t addr, void *val, unsigned int bytes,
7627 				struct x86_exception *exception)
7628 {
7629 	struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
7630 	struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
7631 	u64 access = (static_call(kvm_x86_get_cpl)(vcpu) == 3) ? PFERR_USER_MASK : 0;
7632 	unsigned offset;
7633 	int ret;
7634 
7635 	/* Inline kvm_read_guest_virt_helper for speed.  */
7636 	gpa_t gpa = mmu->gva_to_gpa(vcpu, mmu, addr, access|PFERR_FETCH_MASK,
7637 				    exception);
7638 	if (unlikely(gpa == INVALID_GPA))
7639 		return X86EMUL_PROPAGATE_FAULT;
7640 
7641 	offset = addr & (PAGE_SIZE-1);
7642 	if (WARN_ON(offset + bytes > PAGE_SIZE))
7643 		bytes = (unsigned)PAGE_SIZE - offset;
7644 	ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, val,
7645 				       offset, bytes);
7646 	if (unlikely(ret < 0))
7647 		return X86EMUL_IO_NEEDED;
7648 
7649 	return X86EMUL_CONTINUE;
7650 }
7651 
7652 int kvm_read_guest_virt(struct kvm_vcpu *vcpu,
7653 			       gva_t addr, void *val, unsigned int bytes,
7654 			       struct x86_exception *exception)
7655 {
7656 	u64 access = (static_call(kvm_x86_get_cpl)(vcpu) == 3) ? PFERR_USER_MASK : 0;
7657 
7658 	/*
7659 	 * FIXME: this should call handle_emulation_failure if X86EMUL_IO_NEEDED
7660 	 * is returned, but our callers are not ready for that and they blindly
7661 	 * call kvm_inject_page_fault.  Ensure that they at least do not leak
7662 	 * uninitialized kernel stack memory into cr2 and error code.
7663 	 */
7664 	memset(exception, 0, sizeof(*exception));
7665 	return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
7666 					  exception);
7667 }
7668 EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
7669 
7670 static int emulator_read_std(struct x86_emulate_ctxt *ctxt,
7671 			     gva_t addr, void *val, unsigned int bytes,
7672 			     struct x86_exception *exception, bool system)
7673 {
7674 	struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
7675 	u64 access = 0;
7676 
7677 	if (system)
7678 		access |= PFERR_IMPLICIT_ACCESS;
7679 	else if (static_call(kvm_x86_get_cpl)(vcpu) == 3)
7680 		access |= PFERR_USER_MASK;
7681 
7682 	return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access, exception);
7683 }
7684 
7685 static int kvm_write_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
7686 				      struct kvm_vcpu *vcpu, u64 access,
7687 				      struct x86_exception *exception)
7688 {
7689 	struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
7690 	void *data = val;
7691 	int r = X86EMUL_CONTINUE;
7692 
7693 	while (bytes) {
7694 		gpa_t gpa = mmu->gva_to_gpa(vcpu, mmu, addr, access, exception);
7695 		unsigned offset = addr & (PAGE_SIZE-1);
7696 		unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
7697 		int ret;
7698 
7699 		if (gpa == INVALID_GPA)
7700 			return X86EMUL_PROPAGATE_FAULT;
7701 		ret = kvm_vcpu_write_guest(vcpu, gpa, data, towrite);
7702 		if (ret < 0) {
7703 			r = X86EMUL_IO_NEEDED;
7704 			goto out;
7705 		}
7706 
7707 		bytes -= towrite;
7708 		data += towrite;
7709 		addr += towrite;
7710 	}
7711 out:
7712 	return r;
7713 }
7714 
7715 static int emulator_write_std(struct x86_emulate_ctxt *ctxt, gva_t addr, void *val,
7716 			      unsigned int bytes, struct x86_exception *exception,
7717 			      bool system)
7718 {
7719 	struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
7720 	u64 access = PFERR_WRITE_MASK;
7721 
7722 	if (system)
7723 		access |= PFERR_IMPLICIT_ACCESS;
7724 	else if (static_call(kvm_x86_get_cpl)(vcpu) == 3)
7725 		access |= PFERR_USER_MASK;
7726 
7727 	return kvm_write_guest_virt_helper(addr, val, bytes, vcpu,
7728 					   access, exception);
7729 }
7730 
7731 int kvm_write_guest_virt_system(struct kvm_vcpu *vcpu, gva_t addr, void *val,
7732 				unsigned int bytes, struct x86_exception *exception)
7733 {
7734 	/* kvm_write_guest_virt_system can pull in tons of pages. */
7735 	vcpu->arch.l1tf_flush_l1d = true;
7736 
7737 	return kvm_write_guest_virt_helper(addr, val, bytes, vcpu,
7738 					   PFERR_WRITE_MASK, exception);
7739 }
7740 EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
7741 
7742 static int kvm_check_emulate_insn(struct kvm_vcpu *vcpu, int emul_type,
7743 				  void *insn, int insn_len)
7744 {
7745 	return static_call(kvm_x86_check_emulate_instruction)(vcpu, emul_type,
7746 							      insn, insn_len);
7747 }
7748 
7749 int handle_ud(struct kvm_vcpu *vcpu)
7750 {
7751 	static const char kvm_emulate_prefix[] = { __KVM_EMULATE_PREFIX };
7752 	int fep_flags = READ_ONCE(force_emulation_prefix);
7753 	int emul_type = EMULTYPE_TRAP_UD;
7754 	char sig[5]; /* ud2; .ascii "kvm" */
7755 	struct x86_exception e;
7756 	int r;
7757 
7758 	r = kvm_check_emulate_insn(vcpu, emul_type, NULL, 0);
7759 	if (r != X86EMUL_CONTINUE)
7760 		return 1;
7761 
7762 	if (fep_flags &&
7763 	    kvm_read_guest_virt(vcpu, kvm_get_linear_rip(vcpu),
7764 				sig, sizeof(sig), &e) == 0 &&
7765 	    memcmp(sig, kvm_emulate_prefix, sizeof(sig)) == 0) {
7766 		if (fep_flags & KVM_FEP_CLEAR_RFLAGS_RF)
7767 			kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) & ~X86_EFLAGS_RF);
7768 		kvm_rip_write(vcpu, kvm_rip_read(vcpu) + sizeof(sig));
7769 		emul_type = EMULTYPE_TRAP_UD_FORCED;
7770 	}
7771 
7772 	return kvm_emulate_instruction(vcpu, emul_type);
7773 }
7774 EXPORT_SYMBOL_GPL(handle_ud);
7775 
7776 static int vcpu_is_mmio_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
7777 			    gpa_t gpa, bool write)
7778 {
7779 	/* For APIC access vmexit */
7780 	if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
7781 		return 1;
7782 
7783 	if (vcpu_match_mmio_gpa(vcpu, gpa)) {
7784 		trace_vcpu_match_mmio(gva, gpa, write, true);
7785 		return 1;
7786 	}
7787 
7788 	return 0;
7789 }
7790 
7791 static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
7792 				gpa_t *gpa, struct x86_exception *exception,
7793 				bool write)
7794 {
7795 	struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
7796 	u64 access = ((static_call(kvm_x86_get_cpl)(vcpu) == 3) ? PFERR_USER_MASK : 0)
7797 		| (write ? PFERR_WRITE_MASK : 0);
7798 
7799 	/*
7800 	 * currently PKRU is only applied to ept enabled guest so
7801 	 * there is no pkey in EPT page table for L1 guest or EPT
7802 	 * shadow page table for L2 guest.
7803 	 */
7804 	if (vcpu_match_mmio_gva(vcpu, gva) && (!is_paging(vcpu) ||
7805 	    !permission_fault(vcpu, vcpu->arch.walk_mmu,
7806 			      vcpu->arch.mmio_access, 0, access))) {
7807 		*gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
7808 					(gva & (PAGE_SIZE - 1));
7809 		trace_vcpu_match_mmio(gva, *gpa, write, false);
7810 		return 1;
7811 	}
7812 
7813 	*gpa = mmu->gva_to_gpa(vcpu, mmu, gva, access, exception);
7814 
7815 	if (*gpa == INVALID_GPA)
7816 		return -1;
7817 
7818 	return vcpu_is_mmio_gpa(vcpu, gva, *gpa, write);
7819 }
7820 
7821 int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
7822 			const void *val, int bytes)
7823 {
7824 	int ret;
7825 
7826 	ret = kvm_vcpu_write_guest(vcpu, gpa, val, bytes);
7827 	if (ret < 0)
7828 		return 0;
7829 	kvm_page_track_write(vcpu, gpa, val, bytes);
7830 	return 1;
7831 }
7832 
7833 struct read_write_emulator_ops {
7834 	int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
7835 				  int bytes);
7836 	int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
7837 				  void *val, int bytes);
7838 	int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
7839 			       int bytes, void *val);
7840 	int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
7841 				    void *val, int bytes);
7842 	bool write;
7843 };
7844 
7845 static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
7846 {
7847 	if (vcpu->mmio_read_completed) {
7848 		trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
7849 			       vcpu->mmio_fragments[0].gpa, val);
7850 		vcpu->mmio_read_completed = 0;
7851 		return 1;
7852 	}
7853 
7854 	return 0;
7855 }
7856 
7857 static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
7858 			void *val, int bytes)
7859 {
7860 	return !kvm_vcpu_read_guest(vcpu, gpa, val, bytes);
7861 }
7862 
7863 static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
7864 			 void *val, int bytes)
7865 {
7866 	return emulator_write_phys(vcpu, gpa, val, bytes);
7867 }
7868 
7869 static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
7870 {
7871 	trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, val);
7872 	return vcpu_mmio_write(vcpu, gpa, bytes, val);
7873 }
7874 
7875 static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
7876 			  void *val, int bytes)
7877 {
7878 	trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, NULL);
7879 	return X86EMUL_IO_NEEDED;
7880 }
7881 
7882 static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
7883 			   void *val, int bytes)
7884 {
7885 	struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
7886 
7887 	memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
7888 	return X86EMUL_CONTINUE;
7889 }
7890 
7891 static const struct read_write_emulator_ops read_emultor = {
7892 	.read_write_prepare = read_prepare,
7893 	.read_write_emulate = read_emulate,
7894 	.read_write_mmio = vcpu_mmio_read,
7895 	.read_write_exit_mmio = read_exit_mmio,
7896 };
7897 
7898 static const struct read_write_emulator_ops write_emultor = {
7899 	.read_write_emulate = write_emulate,
7900 	.read_write_mmio = write_mmio,
7901 	.read_write_exit_mmio = write_exit_mmio,
7902 	.write = true,
7903 };
7904 
7905 static int emulator_read_write_onepage(unsigned long addr, void *val,
7906 				       unsigned int bytes,
7907 				       struct x86_exception *exception,
7908 				       struct kvm_vcpu *vcpu,
7909 				       const struct read_write_emulator_ops *ops)
7910 {
7911 	gpa_t gpa;
7912 	int handled, ret;
7913 	bool write = ops->write;
7914 	struct kvm_mmio_fragment *frag;
7915 	struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt;
7916 
7917 	/*
7918 	 * If the exit was due to a NPF we may already have a GPA.
7919 	 * If the GPA is present, use it to avoid the GVA to GPA table walk.
7920 	 * Note, this cannot be used on string operations since string
7921 	 * operation using rep will only have the initial GPA from the NPF
7922 	 * occurred.
7923 	 */
7924 	if (ctxt->gpa_available && emulator_can_use_gpa(ctxt) &&
7925 	    (addr & ~PAGE_MASK) == (ctxt->gpa_val & ~PAGE_MASK)) {
7926 		gpa = ctxt->gpa_val;
7927 		ret = vcpu_is_mmio_gpa(vcpu, addr, gpa, write);
7928 	} else {
7929 		ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
7930 		if (ret < 0)
7931 			return X86EMUL_PROPAGATE_FAULT;
7932 	}
7933 
7934 	if (!ret && ops->read_write_emulate(vcpu, gpa, val, bytes))
7935 		return X86EMUL_CONTINUE;
7936 
7937 	/*
7938 	 * Is this MMIO handled locally?
7939 	 */
7940 	handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
7941 	if (handled == bytes)
7942 		return X86EMUL_CONTINUE;
7943 
7944 	gpa += handled;
7945 	bytes -= handled;
7946 	val += handled;
7947 
7948 	WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS);
7949 	frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
7950 	frag->gpa = gpa;
7951 	frag->data = val;
7952 	frag->len = bytes;
7953 	return X86EMUL_CONTINUE;
7954 }
7955 
7956 static int emulator_read_write(struct x86_emulate_ctxt *ctxt,
7957 			unsigned long addr,
7958 			void *val, unsigned int bytes,
7959 			struct x86_exception *exception,
7960 			const struct read_write_emulator_ops *ops)
7961 {
7962 	struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
7963 	gpa_t gpa;
7964 	int rc;
7965 
7966 	if (ops->read_write_prepare &&
7967 		  ops->read_write_prepare(vcpu, val, bytes))
7968 		return X86EMUL_CONTINUE;
7969 
7970 	vcpu->mmio_nr_fragments = 0;
7971 
7972 	/* Crossing a page boundary? */
7973 	if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
7974 		int now;
7975 
7976 		now = -addr & ~PAGE_MASK;
7977 		rc = emulator_read_write_onepage(addr, val, now, exception,
7978 						 vcpu, ops);
7979 
7980 		if (rc != X86EMUL_CONTINUE)
7981 			return rc;
7982 		addr += now;
7983 		if (ctxt->mode != X86EMUL_MODE_PROT64)
7984 			addr = (u32)addr;
7985 		val += now;
7986 		bytes -= now;
7987 	}
7988 
7989 	rc = emulator_read_write_onepage(addr, val, bytes, exception,
7990 					 vcpu, ops);
7991 	if (rc != X86EMUL_CONTINUE)
7992 		return rc;
7993 
7994 	if (!vcpu->mmio_nr_fragments)
7995 		return rc;
7996 
7997 	gpa = vcpu->mmio_fragments[0].gpa;
7998 
7999 	vcpu->mmio_needed = 1;
8000 	vcpu->mmio_cur_fragment = 0;
8001 
8002 	vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len);
8003 	vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
8004 	vcpu->run->exit_reason = KVM_EXIT_MMIO;
8005 	vcpu->run->mmio.phys_addr = gpa;
8006 
8007 	return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
8008 }
8009 
8010 static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
8011 				  unsigned long addr,
8012 				  void *val,
8013 				  unsigned int bytes,
8014 				  struct x86_exception *exception)
8015 {
8016 	return emulator_read_write(ctxt, addr, val, bytes,
8017 				   exception, &read_emultor);
8018 }
8019 
8020 static int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
8021 			    unsigned long addr,
8022 			    const void *val,
8023 			    unsigned int bytes,
8024 			    struct x86_exception *exception)
8025 {
8026 	return emulator_read_write(ctxt, addr, (void *)val, bytes,
8027 				   exception, &write_emultor);
8028 }
8029 
8030 #define emulator_try_cmpxchg_user(t, ptr, old, new) \
8031 	(__try_cmpxchg_user((t __user *)(ptr), (t *)(old), *(t *)(new), efault ## t))
8032 
8033 static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
8034 				     unsigned long addr,
8035 				     const void *old,
8036 				     const void *new,
8037 				     unsigned int bytes,
8038 				     struct x86_exception *exception)
8039 {
8040 	struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
8041 	u64 page_line_mask;
8042 	unsigned long hva;
8043 	gpa_t gpa;
8044 	int r;
8045 
8046 	/* guests cmpxchg8b have to be emulated atomically */
8047 	if (bytes > 8 || (bytes & (bytes - 1)))
8048 		goto emul_write;
8049 
8050 	gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
8051 
8052 	if (gpa == INVALID_GPA ||
8053 	    (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
8054 		goto emul_write;
8055 
8056 	/*
8057 	 * Emulate the atomic as a straight write to avoid #AC if SLD is
8058 	 * enabled in the host and the access splits a cache line.
8059 	 */
8060 	if (boot_cpu_has(X86_FEATURE_SPLIT_LOCK_DETECT))
8061 		page_line_mask = ~(cache_line_size() - 1);
8062 	else
8063 		page_line_mask = PAGE_MASK;
8064 
8065 	if (((gpa + bytes - 1) & page_line_mask) != (gpa & page_line_mask))
8066 		goto emul_write;
8067 
8068 	hva = kvm_vcpu_gfn_to_hva(vcpu, gpa_to_gfn(gpa));
8069 	if (kvm_is_error_hva(hva))
8070 		goto emul_write;
8071 
8072 	hva += offset_in_page(gpa);
8073 
8074 	switch (bytes) {
8075 	case 1:
8076 		r = emulator_try_cmpxchg_user(u8, hva, old, new);
8077 		break;
8078 	case 2:
8079 		r = emulator_try_cmpxchg_user(u16, hva, old, new);
8080 		break;
8081 	case 4:
8082 		r = emulator_try_cmpxchg_user(u32, hva, old, new);
8083 		break;
8084 	case 8:
8085 		r = emulator_try_cmpxchg_user(u64, hva, old, new);
8086 		break;
8087 	default:
8088 		BUG();
8089 	}
8090 
8091 	if (r < 0)
8092 		return X86EMUL_UNHANDLEABLE;
8093 
8094 	/*
8095 	 * Mark the page dirty _before_ checking whether or not the CMPXCHG was
8096 	 * successful, as the old value is written back on failure.  Note, for
8097 	 * live migration, this is unnecessarily conservative as CMPXCHG writes
8098 	 * back the original value and the access is atomic, but KVM's ABI is
8099 	 * that all writes are dirty logged, regardless of the value written.
8100 	 */
8101 	kvm_vcpu_mark_page_dirty(vcpu, gpa_to_gfn(gpa));
8102 
8103 	if (r)
8104 		return X86EMUL_CMPXCHG_FAILED;
8105 
8106 	kvm_page_track_write(vcpu, gpa, new, bytes);
8107 
8108 	return X86EMUL_CONTINUE;
8109 
8110 emul_write:
8111 	pr_warn_once("emulating exchange as write\n");
8112 
8113 	return emulator_write_emulated(ctxt, addr, new, bytes, exception);
8114 }
8115 
8116 static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
8117 			       unsigned short port, void *data,
8118 			       unsigned int count, bool in)
8119 {
8120 	unsigned i;
8121 	int r;
8122 
8123 	WARN_ON_ONCE(vcpu->arch.pio.count);
8124 	for (i = 0; i < count; i++) {
8125 		if (in)
8126 			r = kvm_io_bus_read(vcpu, KVM_PIO_BUS, port, size, data);
8127 		else
8128 			r = kvm_io_bus_write(vcpu, KVM_PIO_BUS, port, size, data);
8129 
8130 		if (r) {
8131 			if (i == 0)
8132 				goto userspace_io;
8133 
8134 			/*
8135 			 * Userspace must have unregistered the device while PIO
8136 			 * was running.  Drop writes / read as 0.
8137 			 */
8138 			if (in)
8139 				memset(data, 0, size * (count - i));
8140 			break;
8141 		}
8142 
8143 		data += size;
8144 	}
8145 	return 1;
8146 
8147 userspace_io:
8148 	vcpu->arch.pio.port = port;
8149 	vcpu->arch.pio.in = in;
8150 	vcpu->arch.pio.count = count;
8151 	vcpu->arch.pio.size = size;
8152 
8153 	if (in)
8154 		memset(vcpu->arch.pio_data, 0, size * count);
8155 	else
8156 		memcpy(vcpu->arch.pio_data, data, size * count);
8157 
8158 	vcpu->run->exit_reason = KVM_EXIT_IO;
8159 	vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
8160 	vcpu->run->io.size = size;
8161 	vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
8162 	vcpu->run->io.count = count;
8163 	vcpu->run->io.port = port;
8164 	return 0;
8165 }
8166 
8167 static int emulator_pio_in(struct kvm_vcpu *vcpu, int size,
8168       			   unsigned short port, void *val, unsigned int count)
8169 {
8170 	int r = emulator_pio_in_out(vcpu, size, port, val, count, true);
8171 	if (r)
8172 		trace_kvm_pio(KVM_PIO_IN, port, size, count, val);
8173 
8174 	return r;
8175 }
8176 
8177 static void complete_emulator_pio_in(struct kvm_vcpu *vcpu, void *val)
8178 {
8179 	int size = vcpu->arch.pio.size;
8180 	unsigned int count = vcpu->arch.pio.count;
8181 	memcpy(val, vcpu->arch.pio_data, size * count);
8182 	trace_kvm_pio(KVM_PIO_IN, vcpu->arch.pio.port, size, count, vcpu->arch.pio_data);
8183 	vcpu->arch.pio.count = 0;
8184 }
8185 
8186 static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
8187 				    int size, unsigned short port, void *val,
8188 				    unsigned int count)
8189 {
8190 	struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
8191 	if (vcpu->arch.pio.count) {
8192 		/*
8193 		 * Complete a previous iteration that required userspace I/O.
8194 		 * Note, @count isn't guaranteed to match pio.count as userspace
8195 		 * can modify ECX before rerunning the vCPU.  Ignore any such
8196 		 * shenanigans as KVM doesn't support modifying the rep count,
8197 		 * and the emulator ensures @count doesn't overflow the buffer.
8198 		 */
8199 		complete_emulator_pio_in(vcpu, val);
8200 		return 1;
8201 	}
8202 
8203 	return emulator_pio_in(vcpu, size, port, val, count);
8204 }
8205 
8206 static int emulator_pio_out(struct kvm_vcpu *vcpu, int size,
8207 			    unsigned short port, const void *val,
8208 			    unsigned int count)
8209 {
8210 	trace_kvm_pio(KVM_PIO_OUT, port, size, count, val);
8211 	return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
8212 }
8213 
8214 static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
8215 				     int size, unsigned short port,
8216 				     const void *val, unsigned int count)
8217 {
8218 	return emulator_pio_out(emul_to_vcpu(ctxt), size, port, val, count);
8219 }
8220 
8221 static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
8222 {
8223 	return static_call(kvm_x86_get_segment_base)(vcpu, seg);
8224 }
8225 
8226 static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
8227 {
8228 	kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
8229 }
8230 
8231 static int kvm_emulate_wbinvd_noskip(struct kvm_vcpu *vcpu)
8232 {
8233 	if (!need_emulate_wbinvd(vcpu))
8234 		return X86EMUL_CONTINUE;
8235 
8236 	if (static_call(kvm_x86_has_wbinvd_exit)()) {
8237 		int cpu = get_cpu();
8238 
8239 		cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
8240 		on_each_cpu_mask(vcpu->arch.wbinvd_dirty_mask,
8241 				wbinvd_ipi, NULL, 1);
8242 		put_cpu();
8243 		cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
8244 	} else
8245 		wbinvd();
8246 	return X86EMUL_CONTINUE;
8247 }
8248 
8249 int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
8250 {
8251 	kvm_emulate_wbinvd_noskip(vcpu);
8252 	return kvm_skip_emulated_instruction(vcpu);
8253 }
8254 EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
8255 
8256 
8257 
8258 static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
8259 {
8260 	kvm_emulate_wbinvd_noskip(emul_to_vcpu(ctxt));
8261 }
8262 
8263 static unsigned long emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr)
8264 {
8265 	return kvm_get_dr(emul_to_vcpu(ctxt), dr);
8266 }
8267 
8268 static int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr,
8269 			   unsigned long value)
8270 {
8271 
8272 	return kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
8273 }
8274 
8275 static u64 mk_cr_64(u64 curr_cr, u32 new_val)
8276 {
8277 	return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
8278 }
8279 
8280 static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
8281 {
8282 	struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
8283 	unsigned long value;
8284 
8285 	switch (cr) {
8286 	case 0:
8287 		value = kvm_read_cr0(vcpu);
8288 		break;
8289 	case 2:
8290 		value = vcpu->arch.cr2;
8291 		break;
8292 	case 3:
8293 		value = kvm_read_cr3(vcpu);
8294 		break;
8295 	case 4:
8296 		value = kvm_read_cr4(vcpu);
8297 		break;
8298 	case 8:
8299 		value = kvm_get_cr8(vcpu);
8300 		break;
8301 	default:
8302 		kvm_err("%s: unexpected cr %u\n", __func__, cr);
8303 		return 0;
8304 	}
8305 
8306 	return value;
8307 }
8308 
8309 static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
8310 {
8311 	struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
8312 	int res = 0;
8313 
8314 	switch (cr) {
8315 	case 0:
8316 		res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
8317 		break;
8318 	case 2:
8319 		vcpu->arch.cr2 = val;
8320 		break;
8321 	case 3:
8322 		res = kvm_set_cr3(vcpu, val);
8323 		break;
8324 	case 4:
8325 		res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
8326 		break;
8327 	case 8:
8328 		res = kvm_set_cr8(vcpu, val);
8329 		break;
8330 	default:
8331 		kvm_err("%s: unexpected cr %u\n", __func__, cr);
8332 		res = -1;
8333 	}
8334 
8335 	return res;
8336 }
8337 
8338 static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
8339 {
8340 	return static_call(kvm_x86_get_cpl)(emul_to_vcpu(ctxt));
8341 }
8342 
8343 static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
8344 {
8345 	static_call(kvm_x86_get_gdt)(emul_to_vcpu(ctxt), dt);
8346 }
8347 
8348 static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
8349 {
8350 	static_call(kvm_x86_get_idt)(emul_to_vcpu(ctxt), dt);
8351 }
8352 
8353 static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
8354 {
8355 	static_call(kvm_x86_set_gdt)(emul_to_vcpu(ctxt), dt);
8356 }
8357 
8358 static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
8359 {
8360 	static_call(kvm_x86_set_idt)(emul_to_vcpu(ctxt), dt);
8361 }
8362 
8363 static unsigned long emulator_get_cached_segment_base(
8364 	struct x86_emulate_ctxt *ctxt, int seg)
8365 {
8366 	return get_segment_base(emul_to_vcpu(ctxt), seg);
8367 }
8368 
8369 static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
8370 				 struct desc_struct *desc, u32 *base3,
8371 				 int seg)
8372 {
8373 	struct kvm_segment var;
8374 
8375 	kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
8376 	*selector = var.selector;
8377 
8378 	if (var.unusable) {
8379 		memset(desc, 0, sizeof(*desc));
8380 		if (base3)
8381 			*base3 = 0;
8382 		return false;
8383 	}
8384 
8385 	if (var.g)
8386 		var.limit >>= 12;
8387 	set_desc_limit(desc, var.limit);
8388 	set_desc_base(desc, (unsigned long)var.base);
8389 #ifdef CONFIG_X86_64
8390 	if (base3)
8391 		*base3 = var.base >> 32;
8392 #endif
8393 	desc->type = var.type;
8394 	desc->s = var.s;
8395 	desc->dpl = var.dpl;
8396 	desc->p = var.present;
8397 	desc->avl = var.avl;
8398 	desc->l = var.l;
8399 	desc->d = var.db;
8400 	desc->g = var.g;
8401 
8402 	return true;
8403 }
8404 
8405 static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
8406 				 struct desc_struct *desc, u32 base3,
8407 				 int seg)
8408 {
8409 	struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
8410 	struct kvm_segment var;
8411 
8412 	var.selector = selector;
8413 	var.base = get_desc_base(desc);
8414 #ifdef CONFIG_X86_64
8415 	var.base |= ((u64)base3) << 32;
8416 #endif
8417 	var.limit = get_desc_limit(desc);
8418 	if (desc->g)
8419 		var.limit = (var.limit << 12) | 0xfff;
8420 	var.type = desc->type;
8421 	var.dpl = desc->dpl;
8422 	var.db = desc->d;
8423 	var.s = desc->s;
8424 	var.l = desc->l;
8425 	var.g = desc->g;
8426 	var.avl = desc->avl;
8427 	var.present = desc->p;
8428 	var.unusable = !var.present;
8429 	var.padding = 0;
8430 
8431 	kvm_set_segment(vcpu, &var, seg);
8432 	return;
8433 }
8434 
8435 static int emulator_get_msr_with_filter(struct x86_emulate_ctxt *ctxt,
8436 					u32 msr_index, u64 *pdata)
8437 {
8438 	struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
8439 	int r;
8440 
8441 	r = kvm_get_msr_with_filter(vcpu, msr_index, pdata);
8442 	if (r < 0)
8443 		return X86EMUL_UNHANDLEABLE;
8444 
8445 	if (r) {
8446 		if (kvm_msr_user_space(vcpu, msr_index, KVM_EXIT_X86_RDMSR, 0,
8447 				       complete_emulated_rdmsr, r))
8448 			return X86EMUL_IO_NEEDED;
8449 
8450 		trace_kvm_msr_read_ex(msr_index);
8451 		return X86EMUL_PROPAGATE_FAULT;
8452 	}
8453 
8454 	trace_kvm_msr_read(msr_index, *pdata);
8455 	return X86EMUL_CONTINUE;
8456 }
8457 
8458 static int emulator_set_msr_with_filter(struct x86_emulate_ctxt *ctxt,
8459 					u32 msr_index, u64 data)
8460 {
8461 	struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
8462 	int r;
8463 
8464 	r = kvm_set_msr_with_filter(vcpu, msr_index, data);
8465 	if (r < 0)
8466 		return X86EMUL_UNHANDLEABLE;
8467 
8468 	if (r) {
8469 		if (kvm_msr_user_space(vcpu, msr_index, KVM_EXIT_X86_WRMSR, data,
8470 				       complete_emulated_msr_access, r))
8471 			return X86EMUL_IO_NEEDED;
8472 
8473 		trace_kvm_msr_write_ex(msr_index, data);
8474 		return X86EMUL_PROPAGATE_FAULT;
8475 	}
8476 
8477 	trace_kvm_msr_write(msr_index, data);
8478 	return X86EMUL_CONTINUE;
8479 }
8480 
8481 static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
8482 			    u32 msr_index, u64 *pdata)
8483 {
8484 	return kvm_get_msr(emul_to_vcpu(ctxt), msr_index, pdata);
8485 }
8486 
8487 static int emulator_check_rdpmc_early(struct x86_emulate_ctxt *ctxt, u32 pmc)
8488 {
8489 	return kvm_pmu_check_rdpmc_early(emul_to_vcpu(ctxt), pmc);
8490 }
8491 
8492 static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
8493 			     u32 pmc, u64 *pdata)
8494 {
8495 	return kvm_pmu_rdpmc(emul_to_vcpu(ctxt), pmc, pdata);
8496 }
8497 
8498 static void emulator_halt(struct x86_emulate_ctxt *ctxt)
8499 {
8500 	emul_to_vcpu(ctxt)->arch.halt_request = 1;
8501 }
8502 
8503 static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
8504 			      struct x86_instruction_info *info,
8505 			      enum x86_intercept_stage stage)
8506 {
8507 	return static_call(kvm_x86_check_intercept)(emul_to_vcpu(ctxt), info, stage,
8508 					    &ctxt->exception);
8509 }
8510 
8511 static bool emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
8512 			      u32 *eax, u32 *ebx, u32 *ecx, u32 *edx,
8513 			      bool exact_only)
8514 {
8515 	return kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx, exact_only);
8516 }
8517 
8518 static bool emulator_guest_has_movbe(struct x86_emulate_ctxt *ctxt)
8519 {
8520 	return guest_cpuid_has(emul_to_vcpu(ctxt), X86_FEATURE_MOVBE);
8521 }
8522 
8523 static bool emulator_guest_has_fxsr(struct x86_emulate_ctxt *ctxt)
8524 {
8525 	return guest_cpuid_has(emul_to_vcpu(ctxt), X86_FEATURE_FXSR);
8526 }
8527 
8528 static bool emulator_guest_has_rdpid(struct x86_emulate_ctxt *ctxt)
8529 {
8530 	return guest_cpuid_has(emul_to_vcpu(ctxt), X86_FEATURE_RDPID);
8531 }
8532 
8533 static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg)
8534 {
8535 	return kvm_register_read_raw(emul_to_vcpu(ctxt), reg);
8536 }
8537 
8538 static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val)
8539 {
8540 	kvm_register_write_raw(emul_to_vcpu(ctxt), reg, val);
8541 }
8542 
8543 static void emulator_set_nmi_mask(struct x86_emulate_ctxt *ctxt, bool masked)
8544 {
8545 	static_call(kvm_x86_set_nmi_mask)(emul_to_vcpu(ctxt), masked);
8546 }
8547 
8548 static bool emulator_is_smm(struct x86_emulate_ctxt *ctxt)
8549 {
8550 	return is_smm(emul_to_vcpu(ctxt));
8551 }
8552 
8553 static bool emulator_is_guest_mode(struct x86_emulate_ctxt *ctxt)
8554 {
8555 	return is_guest_mode(emul_to_vcpu(ctxt));
8556 }
8557 
8558 #ifndef CONFIG_KVM_SMM
8559 static int emulator_leave_smm(struct x86_emulate_ctxt *ctxt)
8560 {
8561 	WARN_ON_ONCE(1);
8562 	return X86EMUL_UNHANDLEABLE;
8563 }
8564 #endif
8565 
8566 static void emulator_triple_fault(struct x86_emulate_ctxt *ctxt)
8567 {
8568 	kvm_make_request(KVM_REQ_TRIPLE_FAULT, emul_to_vcpu(ctxt));
8569 }
8570 
8571 static int emulator_set_xcr(struct x86_emulate_ctxt *ctxt, u32 index, u64 xcr)
8572 {
8573 	return __kvm_set_xcr(emul_to_vcpu(ctxt), index, xcr);
8574 }
8575 
8576 static void emulator_vm_bugged(struct x86_emulate_ctxt *ctxt)
8577 {
8578 	struct kvm *kvm = emul_to_vcpu(ctxt)->kvm;
8579 
8580 	if (!kvm->vm_bugged)
8581 		kvm_vm_bugged(kvm);
8582 }
8583 
8584 static gva_t emulator_get_untagged_addr(struct x86_emulate_ctxt *ctxt,
8585 					gva_t addr, unsigned int flags)
8586 {
8587 	if (!kvm_x86_ops.get_untagged_addr)
8588 		return addr;
8589 
8590 	return static_call(kvm_x86_get_untagged_addr)(emul_to_vcpu(ctxt), addr, flags);
8591 }
8592 
8593 static const struct x86_emulate_ops emulate_ops = {
8594 	.vm_bugged           = emulator_vm_bugged,
8595 	.read_gpr            = emulator_read_gpr,
8596 	.write_gpr           = emulator_write_gpr,
8597 	.read_std            = emulator_read_std,
8598 	.write_std           = emulator_write_std,
8599 	.fetch               = kvm_fetch_guest_virt,
8600 	.read_emulated       = emulator_read_emulated,
8601 	.write_emulated      = emulator_write_emulated,
8602 	.cmpxchg_emulated    = emulator_cmpxchg_emulated,
8603 	.invlpg              = emulator_invlpg,
8604 	.pio_in_emulated     = emulator_pio_in_emulated,
8605 	.pio_out_emulated    = emulator_pio_out_emulated,
8606 	.get_segment         = emulator_get_segment,
8607 	.set_segment         = emulator_set_segment,
8608 	.get_cached_segment_base = emulator_get_cached_segment_base,
8609 	.get_gdt             = emulator_get_gdt,
8610 	.get_idt	     = emulator_get_idt,
8611 	.set_gdt             = emulator_set_gdt,
8612 	.set_idt	     = emulator_set_idt,
8613 	.get_cr              = emulator_get_cr,
8614 	.set_cr              = emulator_set_cr,
8615 	.cpl                 = emulator_get_cpl,
8616 	.get_dr              = emulator_get_dr,
8617 	.set_dr              = emulator_set_dr,
8618 	.set_msr_with_filter = emulator_set_msr_with_filter,
8619 	.get_msr_with_filter = emulator_get_msr_with_filter,
8620 	.get_msr             = emulator_get_msr,
8621 	.check_rdpmc_early   = emulator_check_rdpmc_early,
8622 	.read_pmc            = emulator_read_pmc,
8623 	.halt                = emulator_halt,
8624 	.wbinvd              = emulator_wbinvd,
8625 	.fix_hypercall       = emulator_fix_hypercall,
8626 	.intercept           = emulator_intercept,
8627 	.get_cpuid           = emulator_get_cpuid,
8628 	.guest_has_movbe     = emulator_guest_has_movbe,
8629 	.guest_has_fxsr      = emulator_guest_has_fxsr,
8630 	.guest_has_rdpid     = emulator_guest_has_rdpid,
8631 	.set_nmi_mask        = emulator_set_nmi_mask,
8632 	.is_smm              = emulator_is_smm,
8633 	.is_guest_mode       = emulator_is_guest_mode,
8634 	.leave_smm           = emulator_leave_smm,
8635 	.triple_fault        = emulator_triple_fault,
8636 	.set_xcr             = emulator_set_xcr,
8637 	.get_untagged_addr   = emulator_get_untagged_addr,
8638 };
8639 
8640 static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
8641 {
8642 	u32 int_shadow = static_call(kvm_x86_get_interrupt_shadow)(vcpu);
8643 	/*
8644 	 * an sti; sti; sequence only disable interrupts for the first
8645 	 * instruction. So, if the last instruction, be it emulated or
8646 	 * not, left the system with the INT_STI flag enabled, it
8647 	 * means that the last instruction is an sti. We should not
8648 	 * leave the flag on in this case. The same goes for mov ss
8649 	 */
8650 	if (int_shadow & mask)
8651 		mask = 0;
8652 	if (unlikely(int_shadow || mask)) {
8653 		static_call(kvm_x86_set_interrupt_shadow)(vcpu, mask);
8654 		if (!mask)
8655 			kvm_make_request(KVM_REQ_EVENT, vcpu);
8656 	}
8657 }
8658 
8659 static void inject_emulated_exception(struct kvm_vcpu *vcpu)
8660 {
8661 	struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt;
8662 
8663 	if (ctxt->exception.vector == PF_VECTOR)
8664 		kvm_inject_emulated_page_fault(vcpu, &ctxt->exception);
8665 	else if (ctxt->exception.error_code_valid)
8666 		kvm_queue_exception_e(vcpu, ctxt->exception.vector,
8667 				      ctxt->exception.error_code);
8668 	else
8669 		kvm_queue_exception(vcpu, ctxt->exception.vector);
8670 }
8671 
8672 static struct x86_emulate_ctxt *alloc_emulate_ctxt(struct kvm_vcpu *vcpu)
8673 {
8674 	struct x86_emulate_ctxt *ctxt;
8675 
8676 	ctxt = kmem_cache_zalloc(x86_emulator_cache, GFP_KERNEL_ACCOUNT);
8677 	if (!ctxt) {
8678 		pr_err("failed to allocate vcpu's emulator\n");
8679 		return NULL;
8680 	}
8681 
8682 	ctxt->vcpu = vcpu;
8683 	ctxt->ops = &emulate_ops;
8684 	vcpu->arch.emulate_ctxt = ctxt;
8685 
8686 	return ctxt;
8687 }
8688 
8689 static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
8690 {
8691 	struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt;
8692 	int cs_db, cs_l;
8693 
8694 	static_call(kvm_x86_get_cs_db_l_bits)(vcpu, &cs_db, &cs_l);
8695 
8696 	ctxt->gpa_available = false;
8697 	ctxt->eflags = kvm_get_rflags(vcpu);
8698 	ctxt->tf = (ctxt->eflags & X86_EFLAGS_TF) != 0;
8699 
8700 	ctxt->eip = kvm_rip_read(vcpu);
8701 	ctxt->mode = (!is_protmode(vcpu))		? X86EMUL_MODE_REAL :
8702 		     (ctxt->eflags & X86_EFLAGS_VM)	? X86EMUL_MODE_VM86 :
8703 		     (cs_l && is_long_mode(vcpu))	? X86EMUL_MODE_PROT64 :
8704 		     cs_db				? X86EMUL_MODE_PROT32 :
8705 							  X86EMUL_MODE_PROT16;
8706 	ctxt->interruptibility = 0;
8707 	ctxt->have_exception = false;
8708 	ctxt->exception.vector = -1;
8709 	ctxt->perm_ok = false;
8710 
8711 	init_decode_cache(ctxt);
8712 	vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
8713 }
8714 
8715 void kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
8716 {
8717 	struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt;
8718 	int ret;
8719 
8720 	init_emulate_ctxt(vcpu);
8721 
8722 	ctxt->op_bytes = 2;
8723 	ctxt->ad_bytes = 2;
8724 	ctxt->_eip = ctxt->eip + inc_eip;
8725 	ret = emulate_int_real(ctxt, irq);
8726 
8727 	if (ret != X86EMUL_CONTINUE) {
8728 		kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
8729 	} else {
8730 		ctxt->eip = ctxt->_eip;
8731 		kvm_rip_write(vcpu, ctxt->eip);
8732 		kvm_set_rflags(vcpu, ctxt->eflags);
8733 	}
8734 }
8735 EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
8736 
8737 static void prepare_emulation_failure_exit(struct kvm_vcpu *vcpu, u64 *data,
8738 					   u8 ndata, u8 *insn_bytes, u8 insn_size)
8739 {
8740 	struct kvm_run *run = vcpu->run;
8741 	u64 info[5];
8742 	u8 info_start;
8743 
8744 	/*
8745 	 * Zero the whole array used to retrieve the exit info, as casting to
8746 	 * u32 for select entries will leave some chunks uninitialized.
8747 	 */
8748 	memset(&info, 0, sizeof(info));
8749 
8750 	static_call(kvm_x86_get_exit_info)(vcpu, (u32 *)&info[0], &info[1],
8751 					   &info[2], (u32 *)&info[3],
8752 					   (u32 *)&info[4]);
8753 
8754 	run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
8755 	run->emulation_failure.suberror = KVM_INTERNAL_ERROR_EMULATION;
8756 
8757 	/*
8758 	 * There's currently space for 13 entries, but 5 are used for the exit
8759 	 * reason and info.  Restrict to 4 to reduce the maintenance burden
8760 	 * when expanding kvm_run.emulation_failure in the future.
8761 	 */
8762 	if (WARN_ON_ONCE(ndata > 4))
8763 		ndata = 4;
8764 
8765 	/* Always include the flags as a 'data' entry. */
8766 	info_start = 1;
8767 	run->emulation_failure.flags = 0;
8768 
8769 	if (insn_size) {
8770 		BUILD_BUG_ON((sizeof(run->emulation_failure.insn_size) +
8771 			      sizeof(run->emulation_failure.insn_bytes) != 16));
8772 		info_start += 2;
8773 		run->emulation_failure.flags |=
8774 			KVM_INTERNAL_ERROR_EMULATION_FLAG_INSTRUCTION_BYTES;
8775 		run->emulation_failure.insn_size = insn_size;
8776 		memset(run->emulation_failure.insn_bytes, 0x90,
8777 		       sizeof(run->emulation_failure.insn_bytes));
8778 		memcpy(run->emulation_failure.insn_bytes, insn_bytes, insn_size);
8779 	}
8780 
8781 	memcpy(&run->internal.data[info_start], info, sizeof(info));
8782 	memcpy(&run->internal.data[info_start + ARRAY_SIZE(info)], data,
8783 	       ndata * sizeof(data[0]));
8784 
8785 	run->emulation_failure.ndata = info_start + ARRAY_SIZE(info) + ndata;
8786 }
8787 
8788 static void prepare_emulation_ctxt_failure_exit(struct kvm_vcpu *vcpu)
8789 {
8790 	struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt;
8791 
8792 	prepare_emulation_failure_exit(vcpu, NULL, 0, ctxt->fetch.data,
8793 				       ctxt->fetch.end - ctxt->fetch.data);
8794 }
8795 
8796 void __kvm_prepare_emulation_failure_exit(struct kvm_vcpu *vcpu, u64 *data,
8797 					  u8 ndata)
8798 {
8799 	prepare_emulation_failure_exit(vcpu, data, ndata, NULL, 0);
8800 }
8801 EXPORT_SYMBOL_GPL(__kvm_prepare_emulation_failure_exit);
8802 
8803 void kvm_prepare_emulation_failure_exit(struct kvm_vcpu *vcpu)
8804 {
8805 	__kvm_prepare_emulation_failure_exit(vcpu, NULL, 0);
8806 }
8807 EXPORT_SYMBOL_GPL(kvm_prepare_emulation_failure_exit);
8808 
8809 static int handle_emulation_failure(struct kvm_vcpu *vcpu, int emulation_type)
8810 {
8811 	struct kvm *kvm = vcpu->kvm;
8812 
8813 	++vcpu->stat.insn_emulation_fail;
8814 	trace_kvm_emulate_insn_failed(vcpu);
8815 
8816 	if (emulation_type & EMULTYPE_VMWARE_GP) {
8817 		kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
8818 		return 1;
8819 	}
8820 
8821 	if (kvm->arch.exit_on_emulation_error ||
8822 	    (emulation_type & EMULTYPE_SKIP)) {
8823 		prepare_emulation_ctxt_failure_exit(vcpu);
8824 		return 0;
8825 	}
8826 
8827 	kvm_queue_exception(vcpu, UD_VECTOR);
8828 
8829 	if (!is_guest_mode(vcpu) && static_call(kvm_x86_get_cpl)(vcpu) == 0) {
8830 		prepare_emulation_ctxt_failure_exit(vcpu);
8831 		return 0;
8832 	}
8833 
8834 	return 1;
8835 }
8836 
8837 static bool reexecute_instruction(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa,
8838 				  int emulation_type)
8839 {
8840 	gpa_t gpa = cr2_or_gpa;
8841 	kvm_pfn_t pfn;
8842 
8843 	if (!(emulation_type & EMULTYPE_ALLOW_RETRY_PF))
8844 		return false;
8845 
8846 	if (WARN_ON_ONCE(is_guest_mode(vcpu)) ||
8847 	    WARN_ON_ONCE(!(emulation_type & EMULTYPE_PF)))
8848 		return false;
8849 
8850 	if (!vcpu->arch.mmu->root_role.direct) {
8851 		/*
8852 		 * Write permission should be allowed since only
8853 		 * write access need to be emulated.
8854 		 */
8855 		gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2_or_gpa, NULL);
8856 
8857 		/*
8858 		 * If the mapping is invalid in guest, let cpu retry
8859 		 * it to generate fault.
8860 		 */
8861 		if (gpa == INVALID_GPA)
8862 			return true;
8863 	}
8864 
8865 	/*
8866 	 * Do not retry the unhandleable instruction if it faults on the
8867 	 * readonly host memory, otherwise it will goto a infinite loop:
8868 	 * retry instruction -> write #PF -> emulation fail -> retry
8869 	 * instruction -> ...
8870 	 */
8871 	pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa));
8872 
8873 	/*
8874 	 * If the instruction failed on the error pfn, it can not be fixed,
8875 	 * report the error to userspace.
8876 	 */
8877 	if (is_error_noslot_pfn(pfn))
8878 		return false;
8879 
8880 	kvm_release_pfn_clean(pfn);
8881 
8882 	/*
8883 	 * If emulation may have been triggered by a write to a shadowed page
8884 	 * table, unprotect the gfn (zap any relevant SPTEs) and re-enter the
8885 	 * guest to let the CPU re-execute the instruction in the hope that the
8886 	 * CPU can cleanly execute the instruction that KVM failed to emulate.
8887 	 */
8888 	if (vcpu->kvm->arch.indirect_shadow_pages)
8889 		kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
8890 
8891 	/*
8892 	 * If the failed instruction faulted on an access to page tables that
8893 	 * are used to translate any part of the instruction, KVM can't resolve
8894 	 * the issue by unprotecting the gfn, as zapping the shadow page will
8895 	 * result in the instruction taking a !PRESENT page fault and thus put
8896 	 * the vCPU into an infinite loop of page faults.  E.g. KVM will create
8897 	 * a SPTE and write-protect the gfn to resolve the !PRESENT fault, and
8898 	 * then zap the SPTE to unprotect the gfn, and then do it all over
8899 	 * again.  Report the error to userspace.
8900 	 */
8901 	return !(emulation_type & EMULTYPE_WRITE_PF_TO_SP);
8902 }
8903 
8904 static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
8905 			      gpa_t cr2_or_gpa,  int emulation_type)
8906 {
8907 	struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
8908 	unsigned long last_retry_eip, last_retry_addr, gpa = cr2_or_gpa;
8909 
8910 	last_retry_eip = vcpu->arch.last_retry_eip;
8911 	last_retry_addr = vcpu->arch.last_retry_addr;
8912 
8913 	/*
8914 	 * If the emulation is caused by #PF and it is non-page_table
8915 	 * writing instruction, it means the VM-EXIT is caused by shadow
8916 	 * page protected, we can zap the shadow page and retry this
8917 	 * instruction directly.
8918 	 *
8919 	 * Note: if the guest uses a non-page-table modifying instruction
8920 	 * on the PDE that points to the instruction, then we will unmap
8921 	 * the instruction and go to an infinite loop. So, we cache the
8922 	 * last retried eip and the last fault address, if we meet the eip
8923 	 * and the address again, we can break out of the potential infinite
8924 	 * loop.
8925 	 */
8926 	vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
8927 
8928 	if (!(emulation_type & EMULTYPE_ALLOW_RETRY_PF))
8929 		return false;
8930 
8931 	if (WARN_ON_ONCE(is_guest_mode(vcpu)) ||
8932 	    WARN_ON_ONCE(!(emulation_type & EMULTYPE_PF)))
8933 		return false;
8934 
8935 	if (x86_page_table_writing_insn(ctxt))
8936 		return false;
8937 
8938 	if (ctxt->eip == last_retry_eip && last_retry_addr == cr2_or_gpa)
8939 		return false;
8940 
8941 	vcpu->arch.last_retry_eip = ctxt->eip;
8942 	vcpu->arch.last_retry_addr = cr2_or_gpa;
8943 
8944 	if (!vcpu->arch.mmu->root_role.direct)
8945 		gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2_or_gpa, NULL);
8946 
8947 	kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
8948 
8949 	return true;
8950 }
8951 
8952 static int complete_emulated_mmio(struct kvm_vcpu *vcpu);
8953 static int complete_emulated_pio(struct kvm_vcpu *vcpu);
8954 
8955 static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7,
8956 				unsigned long *db)
8957 {
8958 	u32 dr6 = 0;
8959 	int i;
8960 	u32 enable, rwlen;
8961 
8962 	enable = dr7;
8963 	rwlen = dr7 >> 16;
8964 	for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4)
8965 		if ((enable & 3) && (rwlen & 15) == type && db[i] == addr)
8966 			dr6 |= (1 << i);
8967 	return dr6;
8968 }
8969 
8970 static int kvm_vcpu_do_singlestep(struct kvm_vcpu *vcpu)
8971 {
8972 	struct kvm_run *kvm_run = vcpu->run;
8973 
8974 	if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) {
8975 		kvm_run->debug.arch.dr6 = DR6_BS | DR6_ACTIVE_LOW;
8976 		kvm_run->debug.arch.pc = kvm_get_linear_rip(vcpu);
8977 		kvm_run->debug.arch.exception = DB_VECTOR;
8978 		kvm_run->exit_reason = KVM_EXIT_DEBUG;
8979 		return 0;
8980 	}
8981 	kvm_queue_exception_p(vcpu, DB_VECTOR, DR6_BS);
8982 	return 1;
8983 }
8984 
8985 int kvm_skip_emulated_instruction(struct kvm_vcpu *vcpu)
8986 {
8987 	unsigned long rflags = static_call(kvm_x86_get_rflags)(vcpu);
8988 	int r;
8989 
8990 	r = static_call(kvm_x86_skip_emulated_instruction)(vcpu);
8991 	if (unlikely(!r))
8992 		return 0;
8993 
8994 	kvm_pmu_trigger_event(vcpu, kvm_pmu_eventsel.INSTRUCTIONS_RETIRED);
8995 
8996 	/*
8997 	 * rflags is the old, "raw" value of the flags.  The new value has
8998 	 * not been saved yet.
8999 	 *
9000 	 * This is correct even for TF set by the guest, because "the
9001 	 * processor will not generate this exception after the instruction
9002 	 * that sets the TF flag".
9003 	 */
9004 	if (unlikely(rflags & X86_EFLAGS_TF))
9005 		r = kvm_vcpu_do_singlestep(vcpu);
9006 	return r;
9007 }
9008 EXPORT_SYMBOL_GPL(kvm_skip_emulated_instruction);
9009 
9010 static bool kvm_is_code_breakpoint_inhibited(struct kvm_vcpu *vcpu)
9011 {
9012 	u32 shadow;
9013 
9014 	if (kvm_get_rflags(vcpu) & X86_EFLAGS_RF)
9015 		return true;
9016 
9017 	/*
9018 	 * Intel CPUs inhibit code #DBs when MOV/POP SS blocking is active,
9019 	 * but AMD CPUs do not.  MOV/POP SS blocking is rare, check that first
9020 	 * to avoid the relatively expensive CPUID lookup.
9021 	 */
9022 	shadow = static_call(kvm_x86_get_interrupt_shadow)(vcpu);
9023 	return (shadow & KVM_X86_SHADOW_INT_MOV_SS) &&
9024 	       guest_cpuid_is_intel(vcpu);
9025 }
9026 
9027 static bool kvm_vcpu_check_code_breakpoint(struct kvm_vcpu *vcpu,
9028 					   int emulation_type, int *r)
9029 {
9030 	WARN_ON_ONCE(emulation_type & EMULTYPE_NO_DECODE);
9031 
9032 	/*
9033 	 * Do not check for code breakpoints if hardware has already done the
9034 	 * checks, as inferred from the emulation type.  On NO_DECODE and SKIP,
9035 	 * the instruction has passed all exception checks, and all intercepted
9036 	 * exceptions that trigger emulation have lower priority than code
9037 	 * breakpoints, i.e. the fact that the intercepted exception occurred
9038 	 * means any code breakpoints have already been serviced.
9039 	 *
9040 	 * Note, KVM needs to check for code #DBs on EMULTYPE_TRAP_UD_FORCED as
9041 	 * hardware has checked the RIP of the magic prefix, but not the RIP of
9042 	 * the instruction being emulated.  The intent of forced emulation is
9043 	 * to behave as if KVM intercepted the instruction without an exception
9044 	 * and without a prefix.
9045 	 */
9046 	if (emulation_type & (EMULTYPE_NO_DECODE | EMULTYPE_SKIP |
9047 			      EMULTYPE_TRAP_UD | EMULTYPE_VMWARE_GP | EMULTYPE_PF))
9048 		return false;
9049 
9050 	if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) &&
9051 	    (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) {
9052 		struct kvm_run *kvm_run = vcpu->run;
9053 		unsigned long eip = kvm_get_linear_rip(vcpu);
9054 		u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
9055 					   vcpu->arch.guest_debug_dr7,
9056 					   vcpu->arch.eff_db);
9057 
9058 		if (dr6 != 0) {
9059 			kvm_run->debug.arch.dr6 = dr6 | DR6_ACTIVE_LOW;
9060 			kvm_run->debug.arch.pc = eip;
9061 			kvm_run->debug.arch.exception = DB_VECTOR;
9062 			kvm_run->exit_reason = KVM_EXIT_DEBUG;
9063 			*r = 0;
9064 			return true;
9065 		}
9066 	}
9067 
9068 	if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) &&
9069 	    !kvm_is_code_breakpoint_inhibited(vcpu)) {
9070 		unsigned long eip = kvm_get_linear_rip(vcpu);
9071 		u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
9072 					   vcpu->arch.dr7,
9073 					   vcpu->arch.db);
9074 
9075 		if (dr6 != 0) {
9076 			kvm_queue_exception_p(vcpu, DB_VECTOR, dr6);
9077 			*r = 1;
9078 			return true;
9079 		}
9080 	}
9081 
9082 	return false;
9083 }
9084 
9085 static bool is_vmware_backdoor_opcode(struct x86_emulate_ctxt *ctxt)
9086 {
9087 	switch (ctxt->opcode_len) {
9088 	case 1:
9089 		switch (ctxt->b) {
9090 		case 0xe4:	/* IN */
9091 		case 0xe5:
9092 		case 0xec:
9093 		case 0xed:
9094 		case 0xe6:	/* OUT */
9095 		case 0xe7:
9096 		case 0xee:
9097 		case 0xef:
9098 		case 0x6c:	/* INS */
9099 		case 0x6d:
9100 		case 0x6e:	/* OUTS */
9101 		case 0x6f:
9102 			return true;
9103 		}
9104 		break;
9105 	case 2:
9106 		switch (ctxt->b) {
9107 		case 0x33:	/* RDPMC */
9108 			return true;
9109 		}
9110 		break;
9111 	}
9112 
9113 	return false;
9114 }
9115 
9116 /*
9117  * Decode an instruction for emulation.  The caller is responsible for handling
9118  * code breakpoints.  Note, manually detecting code breakpoints is unnecessary
9119  * (and wrong) when emulating on an intercepted fault-like exception[*], as
9120  * code breakpoints have higher priority and thus have already been done by
9121  * hardware.
9122  *
9123  * [*] Except #MC, which is higher priority, but KVM should never emulate in
9124  *     response to a machine check.
9125  */
9126 int x86_decode_emulated_instruction(struct kvm_vcpu *vcpu, int emulation_type,
9127 				    void *insn, int insn_len)
9128 {
9129 	struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt;
9130 	int r;
9131 
9132 	init_emulate_ctxt(vcpu);
9133 
9134 	r = x86_decode_insn(ctxt, insn, insn_len, emulation_type);
9135 
9136 	trace_kvm_emulate_insn_start(vcpu);
9137 	++vcpu->stat.insn_emulation;
9138 
9139 	return r;
9140 }
9141 EXPORT_SYMBOL_GPL(x86_decode_emulated_instruction);
9142 
9143 int x86_emulate_instruction(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa,
9144 			    int emulation_type, void *insn, int insn_len)
9145 {
9146 	int r;
9147 	struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt;
9148 	bool writeback = true;
9149 
9150 	r = kvm_check_emulate_insn(vcpu, emulation_type, insn, insn_len);
9151 	if (r != X86EMUL_CONTINUE) {
9152 		if (r == X86EMUL_RETRY_INSTR || r == X86EMUL_PROPAGATE_FAULT)
9153 			return 1;
9154 
9155 		WARN_ON_ONCE(r != X86EMUL_UNHANDLEABLE);
9156 		return handle_emulation_failure(vcpu, emulation_type);
9157 	}
9158 
9159 	vcpu->arch.l1tf_flush_l1d = true;
9160 
9161 	if (!(emulation_type & EMULTYPE_NO_DECODE)) {
9162 		kvm_clear_exception_queue(vcpu);
9163 
9164 		/*
9165 		 * Return immediately if RIP hits a code breakpoint, such #DBs
9166 		 * are fault-like and are higher priority than any faults on
9167 		 * the code fetch itself.
9168 		 */
9169 		if (kvm_vcpu_check_code_breakpoint(vcpu, emulation_type, &r))
9170 			return r;
9171 
9172 		r = x86_decode_emulated_instruction(vcpu, emulation_type,
9173 						    insn, insn_len);
9174 		if (r != EMULATION_OK)  {
9175 			if ((emulation_type & EMULTYPE_TRAP_UD) ||
9176 			    (emulation_type & EMULTYPE_TRAP_UD_FORCED)) {
9177 				kvm_queue_exception(vcpu, UD_VECTOR);
9178 				return 1;
9179 			}
9180 			if (reexecute_instruction(vcpu, cr2_or_gpa,
9181 						  emulation_type))
9182 				return 1;
9183 
9184 			if (ctxt->have_exception &&
9185 			    !(emulation_type & EMULTYPE_SKIP)) {
9186 				/*
9187 				 * #UD should result in just EMULATION_FAILED, and trap-like
9188 				 * exception should not be encountered during decode.
9189 				 */
9190 				WARN_ON_ONCE(ctxt->exception.vector == UD_VECTOR ||
9191 					     exception_type(ctxt->exception.vector) == EXCPT_TRAP);
9192 				inject_emulated_exception(vcpu);
9193 				return 1;
9194 			}
9195 			return handle_emulation_failure(vcpu, emulation_type);
9196 		}
9197 	}
9198 
9199 	if ((emulation_type & EMULTYPE_VMWARE_GP) &&
9200 	    !is_vmware_backdoor_opcode(ctxt)) {
9201 		kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
9202 		return 1;
9203 	}
9204 
9205 	/*
9206 	 * EMULTYPE_SKIP without EMULTYPE_COMPLETE_USER_EXIT is intended for
9207 	 * use *only* by vendor callbacks for kvm_skip_emulated_instruction().
9208 	 * The caller is responsible for updating interruptibility state and
9209 	 * injecting single-step #DBs.
9210 	 */
9211 	if (emulation_type & EMULTYPE_SKIP) {
9212 		if (ctxt->mode != X86EMUL_MODE_PROT64)
9213 			ctxt->eip = (u32)ctxt->_eip;
9214 		else
9215 			ctxt->eip = ctxt->_eip;
9216 
9217 		if (emulation_type & EMULTYPE_COMPLETE_USER_EXIT) {
9218 			r = 1;
9219 			goto writeback;
9220 		}
9221 
9222 		kvm_rip_write(vcpu, ctxt->eip);
9223 		if (ctxt->eflags & X86_EFLAGS_RF)
9224 			kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF);
9225 		return 1;
9226 	}
9227 
9228 	if (retry_instruction(ctxt, cr2_or_gpa, emulation_type))
9229 		return 1;
9230 
9231 	/* this is needed for vmware backdoor interface to work since it
9232 	   changes registers values  during IO operation */
9233 	if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
9234 		vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
9235 		emulator_invalidate_register_cache(ctxt);
9236 	}
9237 
9238 restart:
9239 	if (emulation_type & EMULTYPE_PF) {
9240 		/* Save the faulting GPA (cr2) in the address field */
9241 		ctxt->exception.address = cr2_or_gpa;
9242 
9243 		/* With shadow page tables, cr2 contains a GVA or nGPA. */
9244 		if (vcpu->arch.mmu->root_role.direct) {
9245 			ctxt->gpa_available = true;
9246 			ctxt->gpa_val = cr2_or_gpa;
9247 		}
9248 	} else {
9249 		/* Sanitize the address out of an abundance of paranoia. */
9250 		ctxt->exception.address = 0;
9251 	}
9252 
9253 	r = x86_emulate_insn(ctxt);
9254 
9255 	if (r == EMULATION_INTERCEPTED)
9256 		return 1;
9257 
9258 	if (r == EMULATION_FAILED) {
9259 		if (reexecute_instruction(vcpu, cr2_or_gpa, emulation_type))
9260 			return 1;
9261 
9262 		return handle_emulation_failure(vcpu, emulation_type);
9263 	}
9264 
9265 	if (ctxt->have_exception) {
9266 		WARN_ON_ONCE(vcpu->mmio_needed && !vcpu->mmio_is_write);
9267 		vcpu->mmio_needed = false;
9268 		r = 1;
9269 		inject_emulated_exception(vcpu);
9270 	} else if (vcpu->arch.pio.count) {
9271 		if (!vcpu->arch.pio.in) {
9272 			/* FIXME: return into emulator if single-stepping.  */
9273 			vcpu->arch.pio.count = 0;
9274 		} else {
9275 			writeback = false;
9276 			vcpu->arch.complete_userspace_io = complete_emulated_pio;
9277 		}
9278 		r = 0;
9279 	} else if (vcpu->mmio_needed) {
9280 		++vcpu->stat.mmio_exits;
9281 
9282 		if (!vcpu->mmio_is_write)
9283 			writeback = false;
9284 		r = 0;
9285 		vcpu->arch.complete_userspace_io = complete_emulated_mmio;
9286 	} else if (vcpu->arch.complete_userspace_io) {
9287 		writeback = false;
9288 		r = 0;
9289 	} else if (r == EMULATION_RESTART)
9290 		goto restart;
9291 	else
9292 		r = 1;
9293 
9294 writeback:
9295 	if (writeback) {
9296 		unsigned long rflags = static_call(kvm_x86_get_rflags)(vcpu);
9297 		toggle_interruptibility(vcpu, ctxt->interruptibility);
9298 		vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
9299 
9300 		/*
9301 		 * Note, EXCPT_DB is assumed to be fault-like as the emulator
9302 		 * only supports code breakpoints and general detect #DB, both
9303 		 * of which are fault-like.
9304 		 */
9305 		if (!ctxt->have_exception ||
9306 		    exception_type(ctxt->exception.vector) == EXCPT_TRAP) {
9307 			kvm_pmu_trigger_event(vcpu, kvm_pmu_eventsel.INSTRUCTIONS_RETIRED);
9308 			if (ctxt->is_branch)
9309 				kvm_pmu_trigger_event(vcpu, kvm_pmu_eventsel.BRANCH_INSTRUCTIONS_RETIRED);
9310 			kvm_rip_write(vcpu, ctxt->eip);
9311 			if (r && (ctxt->tf || (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)))
9312 				r = kvm_vcpu_do_singlestep(vcpu);
9313 			static_call_cond(kvm_x86_update_emulated_instruction)(vcpu);
9314 			__kvm_set_rflags(vcpu, ctxt->eflags);
9315 		}
9316 
9317 		/*
9318 		 * For STI, interrupts are shadowed; so KVM_REQ_EVENT will
9319 		 * do nothing, and it will be requested again as soon as
9320 		 * the shadow expires.  But we still need to check here,
9321 		 * because POPF has no interrupt shadow.
9322 		 */
9323 		if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF))
9324 			kvm_make_request(KVM_REQ_EVENT, vcpu);
9325 	} else
9326 		vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
9327 
9328 	return r;
9329 }
9330 
9331 int kvm_emulate_instruction(struct kvm_vcpu *vcpu, int emulation_type)
9332 {
9333 	return x86_emulate_instruction(vcpu, 0, emulation_type, NULL, 0);
9334 }
9335 EXPORT_SYMBOL_GPL(kvm_emulate_instruction);
9336 
9337 int kvm_emulate_instruction_from_buffer(struct kvm_vcpu *vcpu,
9338 					void *insn, int insn_len)
9339 {
9340 	return x86_emulate_instruction(vcpu, 0, 0, insn, insn_len);
9341 }
9342 EXPORT_SYMBOL_GPL(kvm_emulate_instruction_from_buffer);
9343 
9344 static int complete_fast_pio_out_port_0x7e(struct kvm_vcpu *vcpu)
9345 {
9346 	vcpu->arch.pio.count = 0;
9347 	return 1;
9348 }
9349 
9350 static int complete_fast_pio_out(struct kvm_vcpu *vcpu)
9351 {
9352 	vcpu->arch.pio.count = 0;
9353 
9354 	if (unlikely(!kvm_is_linear_rip(vcpu, vcpu->arch.pio.linear_rip)))
9355 		return 1;
9356 
9357 	return kvm_skip_emulated_instruction(vcpu);
9358 }
9359 
9360 static int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size,
9361 			    unsigned short port)
9362 {
9363 	unsigned long val = kvm_rax_read(vcpu);
9364 	int ret = emulator_pio_out(vcpu, size, port, &val, 1);
9365 
9366 	if (ret)
9367 		return ret;
9368 
9369 	/*
9370 	 * Workaround userspace that relies on old KVM behavior of %rip being
9371 	 * incremented prior to exiting to userspace to handle "OUT 0x7e".
9372 	 */
9373 	if (port == 0x7e &&
9374 	    kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_OUT_7E_INC_RIP)) {
9375 		vcpu->arch.complete_userspace_io =
9376 			complete_fast_pio_out_port_0x7e;
9377 		kvm_skip_emulated_instruction(vcpu);
9378 	} else {
9379 		vcpu->arch.pio.linear_rip = kvm_get_linear_rip(vcpu);
9380 		vcpu->arch.complete_userspace_io = complete_fast_pio_out;
9381 	}
9382 	return 0;
9383 }
9384 
9385 static int complete_fast_pio_in(struct kvm_vcpu *vcpu)
9386 {
9387 	unsigned long val;
9388 
9389 	/* We should only ever be called with arch.pio.count equal to 1 */
9390 	BUG_ON(vcpu->arch.pio.count != 1);
9391 
9392 	if (unlikely(!kvm_is_linear_rip(vcpu, vcpu->arch.pio.linear_rip))) {
9393 		vcpu->arch.pio.count = 0;
9394 		return 1;
9395 	}
9396 
9397 	/* For size less than 4 we merge, else we zero extend */
9398 	val = (vcpu->arch.pio.size < 4) ? kvm_rax_read(vcpu) : 0;
9399 
9400 	complete_emulator_pio_in(vcpu, &val);
9401 	kvm_rax_write(vcpu, val);
9402 
9403 	return kvm_skip_emulated_instruction(vcpu);
9404 }
9405 
9406 static int kvm_fast_pio_in(struct kvm_vcpu *vcpu, int size,
9407 			   unsigned short port)
9408 {
9409 	unsigned long val;
9410 	int ret;
9411 
9412 	/* For size less than 4 we merge, else we zero extend */
9413 	val = (size < 4) ? kvm_rax_read(vcpu) : 0;
9414 
9415 	ret = emulator_pio_in(vcpu, size, port, &val, 1);
9416 	if (ret) {
9417 		kvm_rax_write(vcpu, val);
9418 		return ret;
9419 	}
9420 
9421 	vcpu->arch.pio.linear_rip = kvm_get_linear_rip(vcpu);
9422 	vcpu->arch.complete_userspace_io = complete_fast_pio_in;
9423 
9424 	return 0;
9425 }
9426 
9427 int kvm_fast_pio(struct kvm_vcpu *vcpu, int size, unsigned short port, int in)
9428 {
9429 	int ret;
9430 
9431 	if (in)
9432 		ret = kvm_fast_pio_in(vcpu, size, port);
9433 	else
9434 		ret = kvm_fast_pio_out(vcpu, size, port);
9435 	return ret && kvm_skip_emulated_instruction(vcpu);
9436 }
9437 EXPORT_SYMBOL_GPL(kvm_fast_pio);
9438 
9439 static int kvmclock_cpu_down_prep(unsigned int cpu)
9440 {
9441 	__this_cpu_write(cpu_tsc_khz, 0);
9442 	return 0;
9443 }
9444 
9445 static void tsc_khz_changed(void *data)
9446 {
9447 	struct cpufreq_freqs *freq = data;
9448 	unsigned long khz;
9449 
9450 	WARN_ON_ONCE(boot_cpu_has(X86_FEATURE_CONSTANT_TSC));
9451 
9452 	if (data)
9453 		khz = freq->new;
9454 	else
9455 		khz = cpufreq_quick_get(raw_smp_processor_id());
9456 	if (!khz)
9457 		khz = tsc_khz;
9458 	__this_cpu_write(cpu_tsc_khz, khz);
9459 }
9460 
9461 #ifdef CONFIG_X86_64
9462 static void kvm_hyperv_tsc_notifier(void)
9463 {
9464 	struct kvm *kvm;
9465 	int cpu;
9466 
9467 	mutex_lock(&kvm_lock);
9468 	list_for_each_entry(kvm, &vm_list, vm_list)
9469 		kvm_make_mclock_inprogress_request(kvm);
9470 
9471 	/* no guest entries from this point */
9472 	hyperv_stop_tsc_emulation();
9473 
9474 	/* TSC frequency always matches when on Hyper-V */
9475 	if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
9476 		for_each_present_cpu(cpu)
9477 			per_cpu(cpu_tsc_khz, cpu) = tsc_khz;
9478 	}
9479 	kvm_caps.max_guest_tsc_khz = tsc_khz;
9480 
9481 	list_for_each_entry(kvm, &vm_list, vm_list) {
9482 		__kvm_start_pvclock_update(kvm);
9483 		pvclock_update_vm_gtod_copy(kvm);
9484 		kvm_end_pvclock_update(kvm);
9485 	}
9486 
9487 	mutex_unlock(&kvm_lock);
9488 }
9489 #endif
9490 
9491 static void __kvmclock_cpufreq_notifier(struct cpufreq_freqs *freq, int cpu)
9492 {
9493 	struct kvm *kvm;
9494 	struct kvm_vcpu *vcpu;
9495 	int send_ipi = 0;
9496 	unsigned long i;
9497 
9498 	/*
9499 	 * We allow guests to temporarily run on slowing clocks,
9500 	 * provided we notify them after, or to run on accelerating
9501 	 * clocks, provided we notify them before.  Thus time never
9502 	 * goes backwards.
9503 	 *
9504 	 * However, we have a problem.  We can't atomically update
9505 	 * the frequency of a given CPU from this function; it is
9506 	 * merely a notifier, which can be called from any CPU.
9507 	 * Changing the TSC frequency at arbitrary points in time
9508 	 * requires a recomputation of local variables related to
9509 	 * the TSC for each VCPU.  We must flag these local variables
9510 	 * to be updated and be sure the update takes place with the
9511 	 * new frequency before any guests proceed.
9512 	 *
9513 	 * Unfortunately, the combination of hotplug CPU and frequency
9514 	 * change creates an intractable locking scenario; the order
9515 	 * of when these callouts happen is undefined with respect to
9516 	 * CPU hotplug, and they can race with each other.  As such,
9517 	 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
9518 	 * undefined; you can actually have a CPU frequency change take
9519 	 * place in between the computation of X and the setting of the
9520 	 * variable.  To protect against this problem, all updates of
9521 	 * the per_cpu tsc_khz variable are done in an interrupt
9522 	 * protected IPI, and all callers wishing to update the value
9523 	 * must wait for a synchronous IPI to complete (which is trivial
9524 	 * if the caller is on the CPU already).  This establishes the
9525 	 * necessary total order on variable updates.
9526 	 *
9527 	 * Note that because a guest time update may take place
9528 	 * anytime after the setting of the VCPU's request bit, the
9529 	 * correct TSC value must be set before the request.  However,
9530 	 * to ensure the update actually makes it to any guest which
9531 	 * starts running in hardware virtualization between the set
9532 	 * and the acquisition of the spinlock, we must also ping the
9533 	 * CPU after setting the request bit.
9534 	 *
9535 	 */
9536 
9537 	smp_call_function_single(cpu, tsc_khz_changed, freq, 1);
9538 
9539 	mutex_lock(&kvm_lock);
9540 	list_for_each_entry(kvm, &vm_list, vm_list) {
9541 		kvm_for_each_vcpu(i, vcpu, kvm) {
9542 			if (vcpu->cpu != cpu)
9543 				continue;
9544 			kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
9545 			if (vcpu->cpu != raw_smp_processor_id())
9546 				send_ipi = 1;
9547 		}
9548 	}
9549 	mutex_unlock(&kvm_lock);
9550 
9551 	if (freq->old < freq->new && send_ipi) {
9552 		/*
9553 		 * We upscale the frequency.  Must make the guest
9554 		 * doesn't see old kvmclock values while running with
9555 		 * the new frequency, otherwise we risk the guest sees
9556 		 * time go backwards.
9557 		 *
9558 		 * In case we update the frequency for another cpu
9559 		 * (which might be in guest context) send an interrupt
9560 		 * to kick the cpu out of guest context.  Next time
9561 		 * guest context is entered kvmclock will be updated,
9562 		 * so the guest will not see stale values.
9563 		 */
9564 		smp_call_function_single(cpu, tsc_khz_changed, freq, 1);
9565 	}
9566 }
9567 
9568 static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
9569 				     void *data)
9570 {
9571 	struct cpufreq_freqs *freq = data;
9572 	int cpu;
9573 
9574 	if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
9575 		return 0;
9576 	if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
9577 		return 0;
9578 
9579 	for_each_cpu(cpu, freq->policy->cpus)
9580 		__kvmclock_cpufreq_notifier(freq, cpu);
9581 
9582 	return 0;
9583 }
9584 
9585 static struct notifier_block kvmclock_cpufreq_notifier_block = {
9586 	.notifier_call  = kvmclock_cpufreq_notifier
9587 };
9588 
9589 static int kvmclock_cpu_online(unsigned int cpu)
9590 {
9591 	tsc_khz_changed(NULL);
9592 	return 0;
9593 }
9594 
9595 static void kvm_timer_init(void)
9596 {
9597 	if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
9598 		max_tsc_khz = tsc_khz;
9599 
9600 		if (IS_ENABLED(CONFIG_CPU_FREQ)) {
9601 			struct cpufreq_policy *policy;
9602 			int cpu;
9603 
9604 			cpu = get_cpu();
9605 			policy = cpufreq_cpu_get(cpu);
9606 			if (policy) {
9607 				if (policy->cpuinfo.max_freq)
9608 					max_tsc_khz = policy->cpuinfo.max_freq;
9609 				cpufreq_cpu_put(policy);
9610 			}
9611 			put_cpu();
9612 		}
9613 		cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
9614 					  CPUFREQ_TRANSITION_NOTIFIER);
9615 
9616 		cpuhp_setup_state(CPUHP_AP_X86_KVM_CLK_ONLINE, "x86/kvm/clk:online",
9617 				  kvmclock_cpu_online, kvmclock_cpu_down_prep);
9618 	}
9619 }
9620 
9621 #ifdef CONFIG_X86_64
9622 static void pvclock_gtod_update_fn(struct work_struct *work)
9623 {
9624 	struct kvm *kvm;
9625 	struct kvm_vcpu *vcpu;
9626 	unsigned long i;
9627 
9628 	mutex_lock(&kvm_lock);
9629 	list_for_each_entry(kvm, &vm_list, vm_list)
9630 		kvm_for_each_vcpu(i, vcpu, kvm)
9631 			kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
9632 	atomic_set(&kvm_guest_has_master_clock, 0);
9633 	mutex_unlock(&kvm_lock);
9634 }
9635 
9636 static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn);
9637 
9638 /*
9639  * Indirection to move queue_work() out of the tk_core.seq write held
9640  * region to prevent possible deadlocks against time accessors which
9641  * are invoked with work related locks held.
9642  */
9643 static void pvclock_irq_work_fn(struct irq_work *w)
9644 {
9645 	queue_work(system_long_wq, &pvclock_gtod_work);
9646 }
9647 
9648 static DEFINE_IRQ_WORK(pvclock_irq_work, pvclock_irq_work_fn);
9649 
9650 /*
9651  * Notification about pvclock gtod data update.
9652  */
9653 static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused,
9654 			       void *priv)
9655 {
9656 	struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
9657 	struct timekeeper *tk = priv;
9658 
9659 	update_pvclock_gtod(tk);
9660 
9661 	/*
9662 	 * Disable master clock if host does not trust, or does not use,
9663 	 * TSC based clocksource. Delegate queue_work() to irq_work as
9664 	 * this is invoked with tk_core.seq write held.
9665 	 */
9666 	if (!gtod_is_based_on_tsc(gtod->clock.vclock_mode) &&
9667 	    atomic_read(&kvm_guest_has_master_clock) != 0)
9668 		irq_work_queue(&pvclock_irq_work);
9669 	return 0;
9670 }
9671 
9672 static struct notifier_block pvclock_gtod_notifier = {
9673 	.notifier_call = pvclock_gtod_notify,
9674 };
9675 #endif
9676 
9677 static inline void kvm_ops_update(struct kvm_x86_init_ops *ops)
9678 {
9679 	memcpy(&kvm_x86_ops, ops->runtime_ops, sizeof(kvm_x86_ops));
9680 
9681 #define __KVM_X86_OP(func) \
9682 	static_call_update(kvm_x86_##func, kvm_x86_ops.func);
9683 #define KVM_X86_OP(func) \
9684 	WARN_ON(!kvm_x86_ops.func); __KVM_X86_OP(func)
9685 #define KVM_X86_OP_OPTIONAL __KVM_X86_OP
9686 #define KVM_X86_OP_OPTIONAL_RET0(func) \
9687 	static_call_update(kvm_x86_##func, (void *)kvm_x86_ops.func ? : \
9688 					   (void *)__static_call_return0);
9689 #include <asm/kvm-x86-ops.h>
9690 #undef __KVM_X86_OP
9691 
9692 	kvm_pmu_ops_update(ops->pmu_ops);
9693 }
9694 
9695 static int kvm_x86_check_processor_compatibility(void)
9696 {
9697 	int cpu = smp_processor_id();
9698 	struct cpuinfo_x86 *c = &cpu_data(cpu);
9699 
9700 	/*
9701 	 * Compatibility checks are done when loading KVM and when enabling
9702 	 * hardware, e.g. during CPU hotplug, to ensure all online CPUs are
9703 	 * compatible, i.e. KVM should never perform a compatibility check on
9704 	 * an offline CPU.
9705 	 */
9706 	WARN_ON(!cpu_online(cpu));
9707 
9708 	if (__cr4_reserved_bits(cpu_has, c) !=
9709 	    __cr4_reserved_bits(cpu_has, &boot_cpu_data))
9710 		return -EIO;
9711 
9712 	return static_call(kvm_x86_check_processor_compatibility)();
9713 }
9714 
9715 static void kvm_x86_check_cpu_compat(void *ret)
9716 {
9717 	*(int *)ret = kvm_x86_check_processor_compatibility();
9718 }
9719 
9720 int kvm_x86_vendor_init(struct kvm_x86_init_ops *ops)
9721 {
9722 	u64 host_pat;
9723 	int r, cpu;
9724 
9725 	guard(mutex)(&vendor_module_lock);
9726 
9727 	if (kvm_x86_ops.hardware_enable) {
9728 		pr_err("already loaded vendor module '%s'\n", kvm_x86_ops.name);
9729 		return -EEXIST;
9730 	}
9731 
9732 	/*
9733 	 * KVM explicitly assumes that the guest has an FPU and
9734 	 * FXSAVE/FXRSTOR. For example, the KVM_GET_FPU explicitly casts the
9735 	 * vCPU's FPU state as a fxregs_state struct.
9736 	 */
9737 	if (!boot_cpu_has(X86_FEATURE_FPU) || !boot_cpu_has(X86_FEATURE_FXSR)) {
9738 		pr_err("inadequate fpu\n");
9739 		return -EOPNOTSUPP;
9740 	}
9741 
9742 	if (IS_ENABLED(CONFIG_PREEMPT_RT) && !boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
9743 		pr_err("RT requires X86_FEATURE_CONSTANT_TSC\n");
9744 		return -EOPNOTSUPP;
9745 	}
9746 
9747 	/*
9748 	 * KVM assumes that PAT entry '0' encodes WB memtype and simply zeroes
9749 	 * the PAT bits in SPTEs.  Bail if PAT[0] is programmed to something
9750 	 * other than WB.  Note, EPT doesn't utilize the PAT, but don't bother
9751 	 * with an exception.  PAT[0] is set to WB on RESET and also by the
9752 	 * kernel, i.e. failure indicates a kernel bug or broken firmware.
9753 	 */
9754 	if (rdmsrl_safe(MSR_IA32_CR_PAT, &host_pat) ||
9755 	    (host_pat & GENMASK(2, 0)) != 6) {
9756 		pr_err("host PAT[0] is not WB\n");
9757 		return -EIO;
9758 	}
9759 
9760 	memset(&kvm_caps, 0, sizeof(kvm_caps));
9761 
9762 	x86_emulator_cache = kvm_alloc_emulator_cache();
9763 	if (!x86_emulator_cache) {
9764 		pr_err("failed to allocate cache for x86 emulator\n");
9765 		return -ENOMEM;
9766 	}
9767 
9768 	user_return_msrs = alloc_percpu(struct kvm_user_return_msrs);
9769 	if (!user_return_msrs) {
9770 		pr_err("failed to allocate percpu kvm_user_return_msrs\n");
9771 		r = -ENOMEM;
9772 		goto out_free_x86_emulator_cache;
9773 	}
9774 	kvm_nr_uret_msrs = 0;
9775 
9776 	r = kvm_mmu_vendor_module_init();
9777 	if (r)
9778 		goto out_free_percpu;
9779 
9780 	kvm_caps.supported_vm_types = BIT(KVM_X86_DEFAULT_VM);
9781 	kvm_caps.supported_mce_cap = MCG_CTL_P | MCG_SER_P;
9782 
9783 	if (boot_cpu_has(X86_FEATURE_XSAVE)) {
9784 		host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
9785 		kvm_caps.supported_xcr0 = host_xcr0 & KVM_SUPPORTED_XCR0;
9786 	}
9787 
9788 	rdmsrl_safe(MSR_EFER, &host_efer);
9789 
9790 	if (boot_cpu_has(X86_FEATURE_XSAVES))
9791 		rdmsrl(MSR_IA32_XSS, host_xss);
9792 
9793 	kvm_init_pmu_capability(ops->pmu_ops);
9794 
9795 	if (boot_cpu_has(X86_FEATURE_ARCH_CAPABILITIES))
9796 		rdmsrl(MSR_IA32_ARCH_CAPABILITIES, host_arch_capabilities);
9797 
9798 	r = ops->hardware_setup();
9799 	if (r != 0)
9800 		goto out_mmu_exit;
9801 
9802 	kvm_ops_update(ops);
9803 
9804 	for_each_online_cpu(cpu) {
9805 		smp_call_function_single(cpu, kvm_x86_check_cpu_compat, &r, 1);
9806 		if (r < 0)
9807 			goto out_unwind_ops;
9808 	}
9809 
9810 	/*
9811 	 * Point of no return!  DO NOT add error paths below this point unless
9812 	 * absolutely necessary, as most operations from this point forward
9813 	 * require unwinding.
9814 	 */
9815 	kvm_timer_init();
9816 
9817 	if (pi_inject_timer == -1)
9818 		pi_inject_timer = housekeeping_enabled(HK_TYPE_TIMER);
9819 #ifdef CONFIG_X86_64
9820 	pvclock_gtod_register_notifier(&pvclock_gtod_notifier);
9821 
9822 	if (hypervisor_is_type(X86_HYPER_MS_HYPERV))
9823 		set_hv_tscchange_cb(kvm_hyperv_tsc_notifier);
9824 #endif
9825 
9826 	kvm_register_perf_callbacks(ops->handle_intel_pt_intr);
9827 
9828 	if (IS_ENABLED(CONFIG_KVM_SW_PROTECTED_VM) && tdp_mmu_enabled)
9829 		kvm_caps.supported_vm_types |= BIT(KVM_X86_SW_PROTECTED_VM);
9830 
9831 	if (!kvm_cpu_cap_has(X86_FEATURE_XSAVES))
9832 		kvm_caps.supported_xss = 0;
9833 
9834 #define __kvm_cpu_cap_has(UNUSED_, f) kvm_cpu_cap_has(f)
9835 	cr4_reserved_bits = __cr4_reserved_bits(__kvm_cpu_cap_has, UNUSED_);
9836 #undef __kvm_cpu_cap_has
9837 
9838 	if (kvm_caps.has_tsc_control) {
9839 		/*
9840 		 * Make sure the user can only configure tsc_khz values that
9841 		 * fit into a signed integer.
9842 		 * A min value is not calculated because it will always
9843 		 * be 1 on all machines.
9844 		 */
9845 		u64 max = min(0x7fffffffULL,
9846 			      __scale_tsc(kvm_caps.max_tsc_scaling_ratio, tsc_khz));
9847 		kvm_caps.max_guest_tsc_khz = max;
9848 	}
9849 	kvm_caps.default_tsc_scaling_ratio = 1ULL << kvm_caps.tsc_scaling_ratio_frac_bits;
9850 	kvm_init_msr_lists();
9851 	return 0;
9852 
9853 out_unwind_ops:
9854 	kvm_x86_ops.hardware_enable = NULL;
9855 	static_call(kvm_x86_hardware_unsetup)();
9856 out_mmu_exit:
9857 	kvm_mmu_vendor_module_exit();
9858 out_free_percpu:
9859 	free_percpu(user_return_msrs);
9860 out_free_x86_emulator_cache:
9861 	kmem_cache_destroy(x86_emulator_cache);
9862 	return r;
9863 }
9864 EXPORT_SYMBOL_GPL(kvm_x86_vendor_init);
9865 
9866 void kvm_x86_vendor_exit(void)
9867 {
9868 	kvm_unregister_perf_callbacks();
9869 
9870 #ifdef CONFIG_X86_64
9871 	if (hypervisor_is_type(X86_HYPER_MS_HYPERV))
9872 		clear_hv_tscchange_cb();
9873 #endif
9874 	kvm_lapic_exit();
9875 
9876 	if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
9877 		cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
9878 					    CPUFREQ_TRANSITION_NOTIFIER);
9879 		cpuhp_remove_state_nocalls(CPUHP_AP_X86_KVM_CLK_ONLINE);
9880 	}
9881 #ifdef CONFIG_X86_64
9882 	pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier);
9883 	irq_work_sync(&pvclock_irq_work);
9884 	cancel_work_sync(&pvclock_gtod_work);
9885 #endif
9886 	static_call(kvm_x86_hardware_unsetup)();
9887 	kvm_mmu_vendor_module_exit();
9888 	free_percpu(user_return_msrs);
9889 	kmem_cache_destroy(x86_emulator_cache);
9890 #ifdef CONFIG_KVM_XEN
9891 	static_key_deferred_flush(&kvm_xen_enabled);
9892 	WARN_ON(static_branch_unlikely(&kvm_xen_enabled.key));
9893 #endif
9894 	mutex_lock(&vendor_module_lock);
9895 	kvm_x86_ops.hardware_enable = NULL;
9896 	mutex_unlock(&vendor_module_lock);
9897 }
9898 EXPORT_SYMBOL_GPL(kvm_x86_vendor_exit);
9899 
9900 static int __kvm_emulate_halt(struct kvm_vcpu *vcpu, int state, int reason)
9901 {
9902 	/*
9903 	 * The vCPU has halted, e.g. executed HLT.  Update the run state if the
9904 	 * local APIC is in-kernel, the run loop will detect the non-runnable
9905 	 * state and halt the vCPU.  Exit to userspace if the local APIC is
9906 	 * managed by userspace, in which case userspace is responsible for
9907 	 * handling wake events.
9908 	 */
9909 	++vcpu->stat.halt_exits;
9910 	if (lapic_in_kernel(vcpu)) {
9911 		vcpu->arch.mp_state = state;
9912 		return 1;
9913 	} else {
9914 		vcpu->run->exit_reason = reason;
9915 		return 0;
9916 	}
9917 }
9918 
9919 int kvm_emulate_halt_noskip(struct kvm_vcpu *vcpu)
9920 {
9921 	return __kvm_emulate_halt(vcpu, KVM_MP_STATE_HALTED, KVM_EXIT_HLT);
9922 }
9923 EXPORT_SYMBOL_GPL(kvm_emulate_halt_noskip);
9924 
9925 int kvm_emulate_halt(struct kvm_vcpu *vcpu)
9926 {
9927 	int ret = kvm_skip_emulated_instruction(vcpu);
9928 	/*
9929 	 * TODO: we might be squashing a GUESTDBG_SINGLESTEP-triggered
9930 	 * KVM_EXIT_DEBUG here.
9931 	 */
9932 	return kvm_emulate_halt_noskip(vcpu) && ret;
9933 }
9934 EXPORT_SYMBOL_GPL(kvm_emulate_halt);
9935 
9936 int kvm_emulate_ap_reset_hold(struct kvm_vcpu *vcpu)
9937 {
9938 	int ret = kvm_skip_emulated_instruction(vcpu);
9939 
9940 	return __kvm_emulate_halt(vcpu, KVM_MP_STATE_AP_RESET_HOLD,
9941 					KVM_EXIT_AP_RESET_HOLD) && ret;
9942 }
9943 EXPORT_SYMBOL_GPL(kvm_emulate_ap_reset_hold);
9944 
9945 #ifdef CONFIG_X86_64
9946 static int kvm_pv_clock_pairing(struct kvm_vcpu *vcpu, gpa_t paddr,
9947 			        unsigned long clock_type)
9948 {
9949 	struct kvm_clock_pairing clock_pairing;
9950 	struct timespec64 ts;
9951 	u64 cycle;
9952 	int ret;
9953 
9954 	if (clock_type != KVM_CLOCK_PAIRING_WALLCLOCK)
9955 		return -KVM_EOPNOTSUPP;
9956 
9957 	/*
9958 	 * When tsc is in permanent catchup mode guests won't be able to use
9959 	 * pvclock_read_retry loop to get consistent view of pvclock
9960 	 */
9961 	if (vcpu->arch.tsc_always_catchup)
9962 		return -KVM_EOPNOTSUPP;
9963 
9964 	if (!kvm_get_walltime_and_clockread(&ts, &cycle))
9965 		return -KVM_EOPNOTSUPP;
9966 
9967 	clock_pairing.sec = ts.tv_sec;
9968 	clock_pairing.nsec = ts.tv_nsec;
9969 	clock_pairing.tsc = kvm_read_l1_tsc(vcpu, cycle);
9970 	clock_pairing.flags = 0;
9971 	memset(&clock_pairing.pad, 0, sizeof(clock_pairing.pad));
9972 
9973 	ret = 0;
9974 	if (kvm_write_guest(vcpu->kvm, paddr, &clock_pairing,
9975 			    sizeof(struct kvm_clock_pairing)))
9976 		ret = -KVM_EFAULT;
9977 
9978 	return ret;
9979 }
9980 #endif
9981 
9982 /*
9983  * kvm_pv_kick_cpu_op:  Kick a vcpu.
9984  *
9985  * @apicid - apicid of vcpu to be kicked.
9986  */
9987 static void kvm_pv_kick_cpu_op(struct kvm *kvm, int apicid)
9988 {
9989 	/*
9990 	 * All other fields are unused for APIC_DM_REMRD, but may be consumed by
9991 	 * common code, e.g. for tracing. Defer initialization to the compiler.
9992 	 */
9993 	struct kvm_lapic_irq lapic_irq = {
9994 		.delivery_mode = APIC_DM_REMRD,
9995 		.dest_mode = APIC_DEST_PHYSICAL,
9996 		.shorthand = APIC_DEST_NOSHORT,
9997 		.dest_id = apicid,
9998 	};
9999 
10000 	kvm_irq_delivery_to_apic(kvm, NULL, &lapic_irq, NULL);
10001 }
10002 
10003 bool kvm_apicv_activated(struct kvm *kvm)
10004 {
10005 	return (READ_ONCE(kvm->arch.apicv_inhibit_reasons) == 0);
10006 }
10007 EXPORT_SYMBOL_GPL(kvm_apicv_activated);
10008 
10009 bool kvm_vcpu_apicv_activated(struct kvm_vcpu *vcpu)
10010 {
10011 	ulong vm_reasons = READ_ONCE(vcpu->kvm->arch.apicv_inhibit_reasons);
10012 	ulong vcpu_reasons = static_call(kvm_x86_vcpu_get_apicv_inhibit_reasons)(vcpu);
10013 
10014 	return (vm_reasons | vcpu_reasons) == 0;
10015 }
10016 EXPORT_SYMBOL_GPL(kvm_vcpu_apicv_activated);
10017 
10018 static void set_or_clear_apicv_inhibit(unsigned long *inhibits,
10019 				       enum kvm_apicv_inhibit reason, bool set)
10020 {
10021 	if (set)
10022 		__set_bit(reason, inhibits);
10023 	else
10024 		__clear_bit(reason, inhibits);
10025 
10026 	trace_kvm_apicv_inhibit_changed(reason, set, *inhibits);
10027 }
10028 
10029 static void kvm_apicv_init(struct kvm *kvm)
10030 {
10031 	enum kvm_apicv_inhibit reason = enable_apicv ? APICV_INHIBIT_REASON_ABSENT :
10032 						       APICV_INHIBIT_REASON_DISABLE;
10033 
10034 	set_or_clear_apicv_inhibit(&kvm->arch.apicv_inhibit_reasons, reason, true);
10035 
10036 	init_rwsem(&kvm->arch.apicv_update_lock);
10037 }
10038 
10039 static void kvm_sched_yield(struct kvm_vcpu *vcpu, unsigned long dest_id)
10040 {
10041 	struct kvm_vcpu *target = NULL;
10042 	struct kvm_apic_map *map;
10043 
10044 	vcpu->stat.directed_yield_attempted++;
10045 
10046 	if (single_task_running())
10047 		goto no_yield;
10048 
10049 	rcu_read_lock();
10050 	map = rcu_dereference(vcpu->kvm->arch.apic_map);
10051 
10052 	if (likely(map) && dest_id <= map->max_apic_id && map->phys_map[dest_id])
10053 		target = map->phys_map[dest_id]->vcpu;
10054 
10055 	rcu_read_unlock();
10056 
10057 	if (!target || !READ_ONCE(target->ready))
10058 		goto no_yield;
10059 
10060 	/* Ignore requests to yield to self */
10061 	if (vcpu == target)
10062 		goto no_yield;
10063 
10064 	if (kvm_vcpu_yield_to(target) <= 0)
10065 		goto no_yield;
10066 
10067 	vcpu->stat.directed_yield_successful++;
10068 
10069 no_yield:
10070 	return;
10071 }
10072 
10073 static int complete_hypercall_exit(struct kvm_vcpu *vcpu)
10074 {
10075 	u64 ret = vcpu->run->hypercall.ret;
10076 
10077 	if (!is_64_bit_mode(vcpu))
10078 		ret = (u32)ret;
10079 	kvm_rax_write(vcpu, ret);
10080 	++vcpu->stat.hypercalls;
10081 	return kvm_skip_emulated_instruction(vcpu);
10082 }
10083 
10084 unsigned long __kvm_emulate_hypercall(struct kvm_vcpu *vcpu, unsigned long nr,
10085 				      unsigned long a0, unsigned long a1,
10086 				      unsigned long a2, unsigned long a3,
10087 				      int op_64_bit, int cpl)
10088 {
10089 	unsigned long ret;
10090 
10091 	trace_kvm_hypercall(nr, a0, a1, a2, a3);
10092 
10093 	if (!op_64_bit) {
10094 		nr &= 0xFFFFFFFF;
10095 		a0 &= 0xFFFFFFFF;
10096 		a1 &= 0xFFFFFFFF;
10097 		a2 &= 0xFFFFFFFF;
10098 		a3 &= 0xFFFFFFFF;
10099 	}
10100 
10101 	if (cpl) {
10102 		ret = -KVM_EPERM;
10103 		goto out;
10104 	}
10105 
10106 	ret = -KVM_ENOSYS;
10107 
10108 	switch (nr) {
10109 	case KVM_HC_VAPIC_POLL_IRQ:
10110 		ret = 0;
10111 		break;
10112 	case KVM_HC_KICK_CPU:
10113 		if (!guest_pv_has(vcpu, KVM_FEATURE_PV_UNHALT))
10114 			break;
10115 
10116 		kvm_pv_kick_cpu_op(vcpu->kvm, a1);
10117 		kvm_sched_yield(vcpu, a1);
10118 		ret = 0;
10119 		break;
10120 #ifdef CONFIG_X86_64
10121 	case KVM_HC_CLOCK_PAIRING:
10122 		ret = kvm_pv_clock_pairing(vcpu, a0, a1);
10123 		break;
10124 #endif
10125 	case KVM_HC_SEND_IPI:
10126 		if (!guest_pv_has(vcpu, KVM_FEATURE_PV_SEND_IPI))
10127 			break;
10128 
10129 		ret = kvm_pv_send_ipi(vcpu->kvm, a0, a1, a2, a3, op_64_bit);
10130 		break;
10131 	case KVM_HC_SCHED_YIELD:
10132 		if (!guest_pv_has(vcpu, KVM_FEATURE_PV_SCHED_YIELD))
10133 			break;
10134 
10135 		kvm_sched_yield(vcpu, a0);
10136 		ret = 0;
10137 		break;
10138 	case KVM_HC_MAP_GPA_RANGE: {
10139 		u64 gpa = a0, npages = a1, attrs = a2;
10140 
10141 		ret = -KVM_ENOSYS;
10142 		if (!(vcpu->kvm->arch.hypercall_exit_enabled & (1 << KVM_HC_MAP_GPA_RANGE)))
10143 			break;
10144 
10145 		if (!PAGE_ALIGNED(gpa) || !npages ||
10146 		    gpa_to_gfn(gpa) + npages <= gpa_to_gfn(gpa)) {
10147 			ret = -KVM_EINVAL;
10148 			break;
10149 		}
10150 
10151 		vcpu->run->exit_reason        = KVM_EXIT_HYPERCALL;
10152 		vcpu->run->hypercall.nr       = KVM_HC_MAP_GPA_RANGE;
10153 		vcpu->run->hypercall.args[0]  = gpa;
10154 		vcpu->run->hypercall.args[1]  = npages;
10155 		vcpu->run->hypercall.args[2]  = attrs;
10156 		vcpu->run->hypercall.flags    = 0;
10157 		if (op_64_bit)
10158 			vcpu->run->hypercall.flags |= KVM_EXIT_HYPERCALL_LONG_MODE;
10159 
10160 		WARN_ON_ONCE(vcpu->run->hypercall.flags & KVM_EXIT_HYPERCALL_MBZ);
10161 		vcpu->arch.complete_userspace_io = complete_hypercall_exit;
10162 		/* stat is incremented on completion. */
10163 		return 0;
10164 	}
10165 	default:
10166 		ret = -KVM_ENOSYS;
10167 		break;
10168 	}
10169 
10170 out:
10171 	++vcpu->stat.hypercalls;
10172 	return ret;
10173 }
10174 EXPORT_SYMBOL_GPL(__kvm_emulate_hypercall);
10175 
10176 int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
10177 {
10178 	unsigned long nr, a0, a1, a2, a3, ret;
10179 	int op_64_bit;
10180 	int cpl;
10181 
10182 	if (kvm_xen_hypercall_enabled(vcpu->kvm))
10183 		return kvm_xen_hypercall(vcpu);
10184 
10185 	if (kvm_hv_hypercall_enabled(vcpu))
10186 		return kvm_hv_hypercall(vcpu);
10187 
10188 	nr = kvm_rax_read(vcpu);
10189 	a0 = kvm_rbx_read(vcpu);
10190 	a1 = kvm_rcx_read(vcpu);
10191 	a2 = kvm_rdx_read(vcpu);
10192 	a3 = kvm_rsi_read(vcpu);
10193 	op_64_bit = is_64_bit_hypercall(vcpu);
10194 	cpl = static_call(kvm_x86_get_cpl)(vcpu);
10195 
10196 	ret = __kvm_emulate_hypercall(vcpu, nr, a0, a1, a2, a3, op_64_bit, cpl);
10197 	if (nr == KVM_HC_MAP_GPA_RANGE && !ret)
10198 		/* MAP_GPA tosses the request to the user space. */
10199 		return 0;
10200 
10201 	if (!op_64_bit)
10202 		ret = (u32)ret;
10203 	kvm_rax_write(vcpu, ret);
10204 
10205 	return kvm_skip_emulated_instruction(vcpu);
10206 }
10207 EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
10208 
10209 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
10210 {
10211 	struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
10212 	char instruction[3];
10213 	unsigned long rip = kvm_rip_read(vcpu);
10214 
10215 	/*
10216 	 * If the quirk is disabled, synthesize a #UD and let the guest pick up
10217 	 * the pieces.
10218 	 */
10219 	if (!kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_FIX_HYPERCALL_INSN)) {
10220 		ctxt->exception.error_code_valid = false;
10221 		ctxt->exception.vector = UD_VECTOR;
10222 		ctxt->have_exception = true;
10223 		return X86EMUL_PROPAGATE_FAULT;
10224 	}
10225 
10226 	static_call(kvm_x86_patch_hypercall)(vcpu, instruction);
10227 
10228 	return emulator_write_emulated(ctxt, rip, instruction, 3,
10229 		&ctxt->exception);
10230 }
10231 
10232 static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
10233 {
10234 	return vcpu->run->request_interrupt_window &&
10235 		likely(!pic_in_kernel(vcpu->kvm));
10236 }
10237 
10238 /* Called within kvm->srcu read side.  */
10239 static void post_kvm_run_save(struct kvm_vcpu *vcpu)
10240 {
10241 	struct kvm_run *kvm_run = vcpu->run;
10242 
10243 	kvm_run->if_flag = static_call(kvm_x86_get_if_flag)(vcpu);
10244 	kvm_run->cr8 = kvm_get_cr8(vcpu);
10245 	kvm_run->apic_base = kvm_get_apic_base(vcpu);
10246 
10247 	kvm_run->ready_for_interrupt_injection =
10248 		pic_in_kernel(vcpu->kvm) ||
10249 		kvm_vcpu_ready_for_interrupt_injection(vcpu);
10250 
10251 	if (is_smm(vcpu))
10252 		kvm_run->flags |= KVM_RUN_X86_SMM;
10253 }
10254 
10255 static void update_cr8_intercept(struct kvm_vcpu *vcpu)
10256 {
10257 	int max_irr, tpr;
10258 
10259 	if (!kvm_x86_ops.update_cr8_intercept)
10260 		return;
10261 
10262 	if (!lapic_in_kernel(vcpu))
10263 		return;
10264 
10265 	if (vcpu->arch.apic->apicv_active)
10266 		return;
10267 
10268 	if (!vcpu->arch.apic->vapic_addr)
10269 		max_irr = kvm_lapic_find_highest_irr(vcpu);
10270 	else
10271 		max_irr = -1;
10272 
10273 	if (max_irr != -1)
10274 		max_irr >>= 4;
10275 
10276 	tpr = kvm_lapic_get_cr8(vcpu);
10277 
10278 	static_call(kvm_x86_update_cr8_intercept)(vcpu, tpr, max_irr);
10279 }
10280 
10281 
10282 int kvm_check_nested_events(struct kvm_vcpu *vcpu)
10283 {
10284 	if (kvm_test_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
10285 		kvm_x86_ops.nested_ops->triple_fault(vcpu);
10286 		return 1;
10287 	}
10288 
10289 	return kvm_x86_ops.nested_ops->check_events(vcpu);
10290 }
10291 
10292 static void kvm_inject_exception(struct kvm_vcpu *vcpu)
10293 {
10294 	/*
10295 	 * Suppress the error code if the vCPU is in Real Mode, as Real Mode
10296 	 * exceptions don't report error codes.  The presence of an error code
10297 	 * is carried with the exception and only stripped when the exception
10298 	 * is injected as intercepted #PF VM-Exits for AMD's Paged Real Mode do
10299 	 * report an error code despite the CPU being in Real Mode.
10300 	 */
10301 	vcpu->arch.exception.has_error_code &= is_protmode(vcpu);
10302 
10303 	trace_kvm_inj_exception(vcpu->arch.exception.vector,
10304 				vcpu->arch.exception.has_error_code,
10305 				vcpu->arch.exception.error_code,
10306 				vcpu->arch.exception.injected);
10307 
10308 	static_call(kvm_x86_inject_exception)(vcpu);
10309 }
10310 
10311 /*
10312  * Check for any event (interrupt or exception) that is ready to be injected,
10313  * and if there is at least one event, inject the event with the highest
10314  * priority.  This handles both "pending" events, i.e. events that have never
10315  * been injected into the guest, and "injected" events, i.e. events that were
10316  * injected as part of a previous VM-Enter, but weren't successfully delivered
10317  * and need to be re-injected.
10318  *
10319  * Note, this is not guaranteed to be invoked on a guest instruction boundary,
10320  * i.e. doesn't guarantee that there's an event window in the guest.  KVM must
10321  * be able to inject exceptions in the "middle" of an instruction, and so must
10322  * also be able to re-inject NMIs and IRQs in the middle of an instruction.
10323  * I.e. for exceptions and re-injected events, NOT invoking this on instruction
10324  * boundaries is necessary and correct.
10325  *
10326  * For simplicity, KVM uses a single path to inject all events (except events
10327  * that are injected directly from L1 to L2) and doesn't explicitly track
10328  * instruction boundaries for asynchronous events.  However, because VM-Exits
10329  * that can occur during instruction execution typically result in KVM skipping
10330  * the instruction or injecting an exception, e.g. instruction and exception
10331  * intercepts, and because pending exceptions have higher priority than pending
10332  * interrupts, KVM still honors instruction boundaries in most scenarios.
10333  *
10334  * But, if a VM-Exit occurs during instruction execution, and KVM does NOT skip
10335  * the instruction or inject an exception, then KVM can incorrecty inject a new
10336  * asynchronous event if the event became pending after the CPU fetched the
10337  * instruction (in the guest).  E.g. if a page fault (#PF, #NPF, EPT violation)
10338  * occurs and is resolved by KVM, a coincident NMI, SMI, IRQ, etc... can be
10339  * injected on the restarted instruction instead of being deferred until the
10340  * instruction completes.
10341  *
10342  * In practice, this virtualization hole is unlikely to be observed by the
10343  * guest, and even less likely to cause functional problems.  To detect the
10344  * hole, the guest would have to trigger an event on a side effect of an early
10345  * phase of instruction execution, e.g. on the instruction fetch from memory.
10346  * And for it to be a functional problem, the guest would need to depend on the
10347  * ordering between that side effect, the instruction completing, _and_ the
10348  * delivery of the asynchronous event.
10349  */
10350 static int kvm_check_and_inject_events(struct kvm_vcpu *vcpu,
10351 				       bool *req_immediate_exit)
10352 {
10353 	bool can_inject;
10354 	int r;
10355 
10356 	/*
10357 	 * Process nested events first, as nested VM-Exit supersedes event
10358 	 * re-injection.  If there's an event queued for re-injection, it will
10359 	 * be saved into the appropriate vmc{b,s}12 fields on nested VM-Exit.
10360 	 */
10361 	if (is_guest_mode(vcpu))
10362 		r = kvm_check_nested_events(vcpu);
10363 	else
10364 		r = 0;
10365 
10366 	/*
10367 	 * Re-inject exceptions and events *especially* if immediate entry+exit
10368 	 * to/from L2 is needed, as any event that has already been injected
10369 	 * into L2 needs to complete its lifecycle before injecting a new event.
10370 	 *
10371 	 * Don't re-inject an NMI or interrupt if there is a pending exception.
10372 	 * This collision arises if an exception occurred while vectoring the
10373 	 * injected event, KVM intercepted said exception, and KVM ultimately
10374 	 * determined the fault belongs to the guest and queues the exception
10375 	 * for injection back into the guest.
10376 	 *
10377 	 * "Injected" interrupts can also collide with pending exceptions if
10378 	 * userspace ignores the "ready for injection" flag and blindly queues
10379 	 * an interrupt.  In that case, prioritizing the exception is correct,
10380 	 * as the exception "occurred" before the exit to userspace.  Trap-like
10381 	 * exceptions, e.g. most #DBs, have higher priority than interrupts.
10382 	 * And while fault-like exceptions, e.g. #GP and #PF, are the lowest
10383 	 * priority, they're only generated (pended) during instruction
10384 	 * execution, and interrupts are recognized at instruction boundaries.
10385 	 * Thus a pending fault-like exception means the fault occurred on the
10386 	 * *previous* instruction and must be serviced prior to recognizing any
10387 	 * new events in order to fully complete the previous instruction.
10388 	 */
10389 	if (vcpu->arch.exception.injected)
10390 		kvm_inject_exception(vcpu);
10391 	else if (kvm_is_exception_pending(vcpu))
10392 		; /* see above */
10393 	else if (vcpu->arch.nmi_injected)
10394 		static_call(kvm_x86_inject_nmi)(vcpu);
10395 	else if (vcpu->arch.interrupt.injected)
10396 		static_call(kvm_x86_inject_irq)(vcpu, true);
10397 
10398 	/*
10399 	 * Exceptions that morph to VM-Exits are handled above, and pending
10400 	 * exceptions on top of injected exceptions that do not VM-Exit should
10401 	 * either morph to #DF or, sadly, override the injected exception.
10402 	 */
10403 	WARN_ON_ONCE(vcpu->arch.exception.injected &&
10404 		     vcpu->arch.exception.pending);
10405 
10406 	/*
10407 	 * Bail if immediate entry+exit to/from the guest is needed to complete
10408 	 * nested VM-Enter or event re-injection so that a different pending
10409 	 * event can be serviced (or if KVM needs to exit to userspace).
10410 	 *
10411 	 * Otherwise, continue processing events even if VM-Exit occurred.  The
10412 	 * VM-Exit will have cleared exceptions that were meant for L2, but
10413 	 * there may now be events that can be injected into L1.
10414 	 */
10415 	if (r < 0)
10416 		goto out;
10417 
10418 	/*
10419 	 * A pending exception VM-Exit should either result in nested VM-Exit
10420 	 * or force an immediate re-entry and exit to/from L2, and exception
10421 	 * VM-Exits cannot be injected (flag should _never_ be set).
10422 	 */
10423 	WARN_ON_ONCE(vcpu->arch.exception_vmexit.injected ||
10424 		     vcpu->arch.exception_vmexit.pending);
10425 
10426 	/*
10427 	 * New events, other than exceptions, cannot be injected if KVM needs
10428 	 * to re-inject a previous event.  See above comments on re-injecting
10429 	 * for why pending exceptions get priority.
10430 	 */
10431 	can_inject = !kvm_event_needs_reinjection(vcpu);
10432 
10433 	if (vcpu->arch.exception.pending) {
10434 		/*
10435 		 * Fault-class exceptions, except #DBs, set RF=1 in the RFLAGS
10436 		 * value pushed on the stack.  Trap-like exception and all #DBs
10437 		 * leave RF as-is (KVM follows Intel's behavior in this regard;
10438 		 * AMD states that code breakpoint #DBs excplitly clear RF=0).
10439 		 *
10440 		 * Note, most versions of Intel's SDM and AMD's APM incorrectly
10441 		 * describe the behavior of General Detect #DBs, which are
10442 		 * fault-like.  They do _not_ set RF, a la code breakpoints.
10443 		 */
10444 		if (exception_type(vcpu->arch.exception.vector) == EXCPT_FAULT)
10445 			__kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) |
10446 					     X86_EFLAGS_RF);
10447 
10448 		if (vcpu->arch.exception.vector == DB_VECTOR) {
10449 			kvm_deliver_exception_payload(vcpu, &vcpu->arch.exception);
10450 			if (vcpu->arch.dr7 & DR7_GD) {
10451 				vcpu->arch.dr7 &= ~DR7_GD;
10452 				kvm_update_dr7(vcpu);
10453 			}
10454 		}
10455 
10456 		kvm_inject_exception(vcpu);
10457 
10458 		vcpu->arch.exception.pending = false;
10459 		vcpu->arch.exception.injected = true;
10460 
10461 		can_inject = false;
10462 	}
10463 
10464 	/* Don't inject interrupts if the user asked to avoid doing so */
10465 	if (vcpu->guest_debug & KVM_GUESTDBG_BLOCKIRQ)
10466 		return 0;
10467 
10468 	/*
10469 	 * Finally, inject interrupt events.  If an event cannot be injected
10470 	 * due to architectural conditions (e.g. IF=0) a window-open exit
10471 	 * will re-request KVM_REQ_EVENT.  Sometimes however an event is pending
10472 	 * and can architecturally be injected, but we cannot do it right now:
10473 	 * an interrupt could have arrived just now and we have to inject it
10474 	 * as a vmexit, or there could already an event in the queue, which is
10475 	 * indicated by can_inject.  In that case we request an immediate exit
10476 	 * in order to make progress and get back here for another iteration.
10477 	 * The kvm_x86_ops hooks communicate this by returning -EBUSY.
10478 	 */
10479 #ifdef CONFIG_KVM_SMM
10480 	if (vcpu->arch.smi_pending) {
10481 		r = can_inject ? static_call(kvm_x86_smi_allowed)(vcpu, true) : -EBUSY;
10482 		if (r < 0)
10483 			goto out;
10484 		if (r) {
10485 			vcpu->arch.smi_pending = false;
10486 			++vcpu->arch.smi_count;
10487 			enter_smm(vcpu);
10488 			can_inject = false;
10489 		} else
10490 			static_call(kvm_x86_enable_smi_window)(vcpu);
10491 	}
10492 #endif
10493 
10494 	if (vcpu->arch.nmi_pending) {
10495 		r = can_inject ? static_call(kvm_x86_nmi_allowed)(vcpu, true) : -EBUSY;
10496 		if (r < 0)
10497 			goto out;
10498 		if (r) {
10499 			--vcpu->arch.nmi_pending;
10500 			vcpu->arch.nmi_injected = true;
10501 			static_call(kvm_x86_inject_nmi)(vcpu);
10502 			can_inject = false;
10503 			WARN_ON(static_call(kvm_x86_nmi_allowed)(vcpu, true) < 0);
10504 		}
10505 		if (vcpu->arch.nmi_pending)
10506 			static_call(kvm_x86_enable_nmi_window)(vcpu);
10507 	}
10508 
10509 	if (kvm_cpu_has_injectable_intr(vcpu)) {
10510 		r = can_inject ? static_call(kvm_x86_interrupt_allowed)(vcpu, true) : -EBUSY;
10511 		if (r < 0)
10512 			goto out;
10513 		if (r) {
10514 			int irq = kvm_cpu_get_interrupt(vcpu);
10515 
10516 			if (!WARN_ON_ONCE(irq == -1)) {
10517 				kvm_queue_interrupt(vcpu, irq, false);
10518 				static_call(kvm_x86_inject_irq)(vcpu, false);
10519 				WARN_ON(static_call(kvm_x86_interrupt_allowed)(vcpu, true) < 0);
10520 			}
10521 		}
10522 		if (kvm_cpu_has_injectable_intr(vcpu))
10523 			static_call(kvm_x86_enable_irq_window)(vcpu);
10524 	}
10525 
10526 	if (is_guest_mode(vcpu) &&
10527 	    kvm_x86_ops.nested_ops->has_events &&
10528 	    kvm_x86_ops.nested_ops->has_events(vcpu))
10529 		*req_immediate_exit = true;
10530 
10531 	/*
10532 	 * KVM must never queue a new exception while injecting an event; KVM
10533 	 * is done emulating and should only propagate the to-be-injected event
10534 	 * to the VMCS/VMCB.  Queueing a new exception can put the vCPU into an
10535 	 * infinite loop as KVM will bail from VM-Enter to inject the pending
10536 	 * exception and start the cycle all over.
10537 	 *
10538 	 * Exempt triple faults as they have special handling and won't put the
10539 	 * vCPU into an infinite loop.  Triple fault can be queued when running
10540 	 * VMX without unrestricted guest, as that requires KVM to emulate Real
10541 	 * Mode events (see kvm_inject_realmode_interrupt()).
10542 	 */
10543 	WARN_ON_ONCE(vcpu->arch.exception.pending ||
10544 		     vcpu->arch.exception_vmexit.pending);
10545 	return 0;
10546 
10547 out:
10548 	if (r == -EBUSY) {
10549 		*req_immediate_exit = true;
10550 		r = 0;
10551 	}
10552 	return r;
10553 }
10554 
10555 static void process_nmi(struct kvm_vcpu *vcpu)
10556 {
10557 	unsigned int limit;
10558 
10559 	/*
10560 	 * x86 is limited to one NMI pending, but because KVM can't react to
10561 	 * incoming NMIs as quickly as bare metal, e.g. if the vCPU is
10562 	 * scheduled out, KVM needs to play nice with two queued NMIs showing
10563 	 * up at the same time.  To handle this scenario, allow two NMIs to be
10564 	 * (temporarily) pending so long as NMIs are not blocked and KVM is not
10565 	 * waiting for a previous NMI injection to complete (which effectively
10566 	 * blocks NMIs).  KVM will immediately inject one of the two NMIs, and
10567 	 * will request an NMI window to handle the second NMI.
10568 	 */
10569 	if (static_call(kvm_x86_get_nmi_mask)(vcpu) || vcpu->arch.nmi_injected)
10570 		limit = 1;
10571 	else
10572 		limit = 2;
10573 
10574 	/*
10575 	 * Adjust the limit to account for pending virtual NMIs, which aren't
10576 	 * tracked in vcpu->arch.nmi_pending.
10577 	 */
10578 	if (static_call(kvm_x86_is_vnmi_pending)(vcpu))
10579 		limit--;
10580 
10581 	vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
10582 	vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
10583 
10584 	if (vcpu->arch.nmi_pending &&
10585 	    (static_call(kvm_x86_set_vnmi_pending)(vcpu)))
10586 		vcpu->arch.nmi_pending--;
10587 
10588 	if (vcpu->arch.nmi_pending)
10589 		kvm_make_request(KVM_REQ_EVENT, vcpu);
10590 }
10591 
10592 /* Return total number of NMIs pending injection to the VM */
10593 int kvm_get_nr_pending_nmis(struct kvm_vcpu *vcpu)
10594 {
10595 	return vcpu->arch.nmi_pending +
10596 	       static_call(kvm_x86_is_vnmi_pending)(vcpu);
10597 }
10598 
10599 void kvm_make_scan_ioapic_request_mask(struct kvm *kvm,
10600 				       unsigned long *vcpu_bitmap)
10601 {
10602 	kvm_make_vcpus_request_mask(kvm, KVM_REQ_SCAN_IOAPIC, vcpu_bitmap);
10603 }
10604 
10605 void kvm_make_scan_ioapic_request(struct kvm *kvm)
10606 {
10607 	kvm_make_all_cpus_request(kvm, KVM_REQ_SCAN_IOAPIC);
10608 }
10609 
10610 void __kvm_vcpu_update_apicv(struct kvm_vcpu *vcpu)
10611 {
10612 	struct kvm_lapic *apic = vcpu->arch.apic;
10613 	bool activate;
10614 
10615 	if (!lapic_in_kernel(vcpu))
10616 		return;
10617 
10618 	down_read(&vcpu->kvm->arch.apicv_update_lock);
10619 	preempt_disable();
10620 
10621 	/* Do not activate APICV when APIC is disabled */
10622 	activate = kvm_vcpu_apicv_activated(vcpu) &&
10623 		   (kvm_get_apic_mode(vcpu) != LAPIC_MODE_DISABLED);
10624 
10625 	if (apic->apicv_active == activate)
10626 		goto out;
10627 
10628 	apic->apicv_active = activate;
10629 	kvm_apic_update_apicv(vcpu);
10630 	static_call(kvm_x86_refresh_apicv_exec_ctrl)(vcpu);
10631 
10632 	/*
10633 	 * When APICv gets disabled, we may still have injected interrupts
10634 	 * pending. At the same time, KVM_REQ_EVENT may not be set as APICv was
10635 	 * still active when the interrupt got accepted. Make sure
10636 	 * kvm_check_and_inject_events() is called to check for that.
10637 	 */
10638 	if (!apic->apicv_active)
10639 		kvm_make_request(KVM_REQ_EVENT, vcpu);
10640 
10641 out:
10642 	preempt_enable();
10643 	up_read(&vcpu->kvm->arch.apicv_update_lock);
10644 }
10645 EXPORT_SYMBOL_GPL(__kvm_vcpu_update_apicv);
10646 
10647 static void kvm_vcpu_update_apicv(struct kvm_vcpu *vcpu)
10648 {
10649 	if (!lapic_in_kernel(vcpu))
10650 		return;
10651 
10652 	/*
10653 	 * Due to sharing page tables across vCPUs, the xAPIC memslot must be
10654 	 * deleted if any vCPU has xAPIC virtualization and x2APIC enabled, but
10655 	 * and hardware doesn't support x2APIC virtualization.  E.g. some AMD
10656 	 * CPUs support AVIC but not x2APIC.  KVM still allows enabling AVIC in
10657 	 * this case so that KVM can the AVIC doorbell to inject interrupts to
10658 	 * running vCPUs, but KVM must not create SPTEs for the APIC base as
10659 	 * the vCPU would incorrectly be able to access the vAPIC page via MMIO
10660 	 * despite being in x2APIC mode.  For simplicity, inhibiting the APIC
10661 	 * access page is sticky.
10662 	 */
10663 	if (apic_x2apic_mode(vcpu->arch.apic) &&
10664 	    kvm_x86_ops.allow_apicv_in_x2apic_without_x2apic_virtualization)
10665 		kvm_inhibit_apic_access_page(vcpu);
10666 
10667 	__kvm_vcpu_update_apicv(vcpu);
10668 }
10669 
10670 void __kvm_set_or_clear_apicv_inhibit(struct kvm *kvm,
10671 				      enum kvm_apicv_inhibit reason, bool set)
10672 {
10673 	unsigned long old, new;
10674 
10675 	lockdep_assert_held_write(&kvm->arch.apicv_update_lock);
10676 
10677 	if (!(kvm_x86_ops.required_apicv_inhibits & BIT(reason)))
10678 		return;
10679 
10680 	old = new = kvm->arch.apicv_inhibit_reasons;
10681 
10682 	set_or_clear_apicv_inhibit(&new, reason, set);
10683 
10684 	if (!!old != !!new) {
10685 		/*
10686 		 * Kick all vCPUs before setting apicv_inhibit_reasons to avoid
10687 		 * false positives in the sanity check WARN in svm_vcpu_run().
10688 		 * This task will wait for all vCPUs to ack the kick IRQ before
10689 		 * updating apicv_inhibit_reasons, and all other vCPUs will
10690 		 * block on acquiring apicv_update_lock so that vCPUs can't
10691 		 * redo svm_vcpu_run() without seeing the new inhibit state.
10692 		 *
10693 		 * Note, holding apicv_update_lock and taking it in the read
10694 		 * side (handling the request) also prevents other vCPUs from
10695 		 * servicing the request with a stale apicv_inhibit_reasons.
10696 		 */
10697 		kvm_make_all_cpus_request(kvm, KVM_REQ_APICV_UPDATE);
10698 		kvm->arch.apicv_inhibit_reasons = new;
10699 		if (new) {
10700 			unsigned long gfn = gpa_to_gfn(APIC_DEFAULT_PHYS_BASE);
10701 			int idx = srcu_read_lock(&kvm->srcu);
10702 
10703 			kvm_zap_gfn_range(kvm, gfn, gfn+1);
10704 			srcu_read_unlock(&kvm->srcu, idx);
10705 		}
10706 	} else {
10707 		kvm->arch.apicv_inhibit_reasons = new;
10708 	}
10709 }
10710 
10711 void kvm_set_or_clear_apicv_inhibit(struct kvm *kvm,
10712 				    enum kvm_apicv_inhibit reason, bool set)
10713 {
10714 	if (!enable_apicv)
10715 		return;
10716 
10717 	down_write(&kvm->arch.apicv_update_lock);
10718 	__kvm_set_or_clear_apicv_inhibit(kvm, reason, set);
10719 	up_write(&kvm->arch.apicv_update_lock);
10720 }
10721 EXPORT_SYMBOL_GPL(kvm_set_or_clear_apicv_inhibit);
10722 
10723 static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu)
10724 {
10725 	if (!kvm_apic_present(vcpu))
10726 		return;
10727 
10728 	bitmap_zero(vcpu->arch.ioapic_handled_vectors, 256);
10729 
10730 	if (irqchip_split(vcpu->kvm))
10731 		kvm_scan_ioapic_routes(vcpu, vcpu->arch.ioapic_handled_vectors);
10732 	else {
10733 		static_call_cond(kvm_x86_sync_pir_to_irr)(vcpu);
10734 		if (ioapic_in_kernel(vcpu->kvm))
10735 			kvm_ioapic_scan_entry(vcpu, vcpu->arch.ioapic_handled_vectors);
10736 	}
10737 
10738 	if (is_guest_mode(vcpu))
10739 		vcpu->arch.load_eoi_exitmap_pending = true;
10740 	else
10741 		kvm_make_request(KVM_REQ_LOAD_EOI_EXITMAP, vcpu);
10742 }
10743 
10744 static void vcpu_load_eoi_exitmap(struct kvm_vcpu *vcpu)
10745 {
10746 	if (!kvm_apic_hw_enabled(vcpu->arch.apic))
10747 		return;
10748 
10749 #ifdef CONFIG_KVM_HYPERV
10750 	if (to_hv_vcpu(vcpu)) {
10751 		u64 eoi_exit_bitmap[4];
10752 
10753 		bitmap_or((ulong *)eoi_exit_bitmap,
10754 			  vcpu->arch.ioapic_handled_vectors,
10755 			  to_hv_synic(vcpu)->vec_bitmap, 256);
10756 		static_call_cond(kvm_x86_load_eoi_exitmap)(vcpu, eoi_exit_bitmap);
10757 		return;
10758 	}
10759 #endif
10760 	static_call_cond(kvm_x86_load_eoi_exitmap)(
10761 		vcpu, (u64 *)vcpu->arch.ioapic_handled_vectors);
10762 }
10763 
10764 void kvm_arch_guest_memory_reclaimed(struct kvm *kvm)
10765 {
10766 	static_call_cond(kvm_x86_guest_memory_reclaimed)(kvm);
10767 }
10768 
10769 static void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu)
10770 {
10771 	if (!lapic_in_kernel(vcpu))
10772 		return;
10773 
10774 	static_call_cond(kvm_x86_set_apic_access_page_addr)(vcpu);
10775 }
10776 
10777 /*
10778  * Called within kvm->srcu read side.
10779  * Returns 1 to let vcpu_run() continue the guest execution loop without
10780  * exiting to the userspace.  Otherwise, the value will be returned to the
10781  * userspace.
10782  */
10783 static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
10784 {
10785 	int r;
10786 	bool req_int_win =
10787 		dm_request_for_irq_injection(vcpu) &&
10788 		kvm_cpu_accept_dm_intr(vcpu);
10789 	fastpath_t exit_fastpath;
10790 
10791 	bool req_immediate_exit = false;
10792 
10793 	if (kvm_request_pending(vcpu)) {
10794 		if (kvm_check_request(KVM_REQ_VM_DEAD, vcpu)) {
10795 			r = -EIO;
10796 			goto out;
10797 		}
10798 
10799 		if (kvm_dirty_ring_check_request(vcpu)) {
10800 			r = 0;
10801 			goto out;
10802 		}
10803 
10804 		if (kvm_check_request(KVM_REQ_GET_NESTED_STATE_PAGES, vcpu)) {
10805 			if (unlikely(!kvm_x86_ops.nested_ops->get_nested_state_pages(vcpu))) {
10806 				r = 0;
10807 				goto out;
10808 			}
10809 		}
10810 		if (kvm_check_request(KVM_REQ_MMU_FREE_OBSOLETE_ROOTS, vcpu))
10811 			kvm_mmu_free_obsolete_roots(vcpu);
10812 		if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
10813 			__kvm_migrate_timers(vcpu);
10814 		if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu))
10815 			kvm_update_masterclock(vcpu->kvm);
10816 		if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu))
10817 			kvm_gen_kvmclock_update(vcpu);
10818 		if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
10819 			r = kvm_guest_time_update(vcpu);
10820 			if (unlikely(r))
10821 				goto out;
10822 		}
10823 		if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
10824 			kvm_mmu_sync_roots(vcpu);
10825 		if (kvm_check_request(KVM_REQ_LOAD_MMU_PGD, vcpu))
10826 			kvm_mmu_load_pgd(vcpu);
10827 
10828 		/*
10829 		 * Note, the order matters here, as flushing "all" TLB entries
10830 		 * also flushes the "current" TLB entries, i.e. servicing the
10831 		 * flush "all" will clear any request to flush "current".
10832 		 */
10833 		if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
10834 			kvm_vcpu_flush_tlb_all(vcpu);
10835 
10836 		kvm_service_local_tlb_flush_requests(vcpu);
10837 
10838 		/*
10839 		 * Fall back to a "full" guest flush if Hyper-V's precise
10840 		 * flushing fails.  Note, Hyper-V's flushing is per-vCPU, but
10841 		 * the flushes are considered "remote" and not "local" because
10842 		 * the requests can be initiated from other vCPUs.
10843 		 */
10844 #ifdef CONFIG_KVM_HYPERV
10845 		if (kvm_check_request(KVM_REQ_HV_TLB_FLUSH, vcpu) &&
10846 		    kvm_hv_vcpu_flush_tlb(vcpu))
10847 			kvm_vcpu_flush_tlb_guest(vcpu);
10848 #endif
10849 
10850 		if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
10851 			vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
10852 			r = 0;
10853 			goto out;
10854 		}
10855 		if (kvm_test_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
10856 			if (is_guest_mode(vcpu))
10857 				kvm_x86_ops.nested_ops->triple_fault(vcpu);
10858 
10859 			if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
10860 				vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
10861 				vcpu->mmio_needed = 0;
10862 				r = 0;
10863 				goto out;
10864 			}
10865 		}
10866 		if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
10867 			/* Page is swapped out. Do synthetic halt */
10868 			vcpu->arch.apf.halted = true;
10869 			r = 1;
10870 			goto out;
10871 		}
10872 		if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
10873 			record_steal_time(vcpu);
10874 		if (kvm_check_request(KVM_REQ_PMU, vcpu))
10875 			kvm_pmu_handle_event(vcpu);
10876 		if (kvm_check_request(KVM_REQ_PMI, vcpu))
10877 			kvm_pmu_deliver_pmi(vcpu);
10878 #ifdef CONFIG_KVM_SMM
10879 		if (kvm_check_request(KVM_REQ_SMI, vcpu))
10880 			process_smi(vcpu);
10881 #endif
10882 		if (kvm_check_request(KVM_REQ_NMI, vcpu))
10883 			process_nmi(vcpu);
10884 		if (kvm_check_request(KVM_REQ_IOAPIC_EOI_EXIT, vcpu)) {
10885 			BUG_ON(vcpu->arch.pending_ioapic_eoi > 255);
10886 			if (test_bit(vcpu->arch.pending_ioapic_eoi,
10887 				     vcpu->arch.ioapic_handled_vectors)) {
10888 				vcpu->run->exit_reason = KVM_EXIT_IOAPIC_EOI;
10889 				vcpu->run->eoi.vector =
10890 						vcpu->arch.pending_ioapic_eoi;
10891 				r = 0;
10892 				goto out;
10893 			}
10894 		}
10895 		if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu))
10896 			vcpu_scan_ioapic(vcpu);
10897 		if (kvm_check_request(KVM_REQ_LOAD_EOI_EXITMAP, vcpu))
10898 			vcpu_load_eoi_exitmap(vcpu);
10899 		if (kvm_check_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu))
10900 			kvm_vcpu_reload_apic_access_page(vcpu);
10901 #ifdef CONFIG_KVM_HYPERV
10902 		if (kvm_check_request(KVM_REQ_HV_CRASH, vcpu)) {
10903 			vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
10904 			vcpu->run->system_event.type = KVM_SYSTEM_EVENT_CRASH;
10905 			vcpu->run->system_event.ndata = 0;
10906 			r = 0;
10907 			goto out;
10908 		}
10909 		if (kvm_check_request(KVM_REQ_HV_RESET, vcpu)) {
10910 			vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
10911 			vcpu->run->system_event.type = KVM_SYSTEM_EVENT_RESET;
10912 			vcpu->run->system_event.ndata = 0;
10913 			r = 0;
10914 			goto out;
10915 		}
10916 		if (kvm_check_request(KVM_REQ_HV_EXIT, vcpu)) {
10917 			struct kvm_vcpu_hv *hv_vcpu = to_hv_vcpu(vcpu);
10918 
10919 			vcpu->run->exit_reason = KVM_EXIT_HYPERV;
10920 			vcpu->run->hyperv = hv_vcpu->exit;
10921 			r = 0;
10922 			goto out;
10923 		}
10924 
10925 		/*
10926 		 * KVM_REQ_HV_STIMER has to be processed after
10927 		 * KVM_REQ_CLOCK_UPDATE, because Hyper-V SynIC timers
10928 		 * depend on the guest clock being up-to-date
10929 		 */
10930 		if (kvm_check_request(KVM_REQ_HV_STIMER, vcpu))
10931 			kvm_hv_process_stimers(vcpu);
10932 #endif
10933 		if (kvm_check_request(KVM_REQ_APICV_UPDATE, vcpu))
10934 			kvm_vcpu_update_apicv(vcpu);
10935 		if (kvm_check_request(KVM_REQ_APF_READY, vcpu))
10936 			kvm_check_async_pf_completion(vcpu);
10937 		if (kvm_check_request(KVM_REQ_MSR_FILTER_CHANGED, vcpu))
10938 			static_call(kvm_x86_msr_filter_changed)(vcpu);
10939 
10940 		if (kvm_check_request(KVM_REQ_UPDATE_CPU_DIRTY_LOGGING, vcpu))
10941 			static_call(kvm_x86_update_cpu_dirty_logging)(vcpu);
10942 	}
10943 
10944 	if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win ||
10945 	    kvm_xen_has_interrupt(vcpu)) {
10946 		++vcpu->stat.req_event;
10947 		r = kvm_apic_accept_events(vcpu);
10948 		if (r < 0) {
10949 			r = 0;
10950 			goto out;
10951 		}
10952 		if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
10953 			r = 1;
10954 			goto out;
10955 		}
10956 
10957 		r = kvm_check_and_inject_events(vcpu, &req_immediate_exit);
10958 		if (r < 0) {
10959 			r = 0;
10960 			goto out;
10961 		}
10962 		if (req_int_win)
10963 			static_call(kvm_x86_enable_irq_window)(vcpu);
10964 
10965 		if (kvm_lapic_enabled(vcpu)) {
10966 			update_cr8_intercept(vcpu);
10967 			kvm_lapic_sync_to_vapic(vcpu);
10968 		}
10969 	}
10970 
10971 	r = kvm_mmu_reload(vcpu);
10972 	if (unlikely(r)) {
10973 		goto cancel_injection;
10974 	}
10975 
10976 	preempt_disable();
10977 
10978 	static_call(kvm_x86_prepare_switch_to_guest)(vcpu);
10979 
10980 	/*
10981 	 * Disable IRQs before setting IN_GUEST_MODE.  Posted interrupt
10982 	 * IPI are then delayed after guest entry, which ensures that they
10983 	 * result in virtual interrupt delivery.
10984 	 */
10985 	local_irq_disable();
10986 
10987 	/* Store vcpu->apicv_active before vcpu->mode.  */
10988 	smp_store_release(&vcpu->mode, IN_GUEST_MODE);
10989 
10990 	kvm_vcpu_srcu_read_unlock(vcpu);
10991 
10992 	/*
10993 	 * 1) We should set ->mode before checking ->requests.  Please see
10994 	 * the comment in kvm_vcpu_exiting_guest_mode().
10995 	 *
10996 	 * 2) For APICv, we should set ->mode before checking PID.ON. This
10997 	 * pairs with the memory barrier implicit in pi_test_and_set_on
10998 	 * (see vmx_deliver_posted_interrupt).
10999 	 *
11000 	 * 3) This also orders the write to mode from any reads to the page
11001 	 * tables done while the VCPU is running.  Please see the comment
11002 	 * in kvm_flush_remote_tlbs.
11003 	 */
11004 	smp_mb__after_srcu_read_unlock();
11005 
11006 	/*
11007 	 * Process pending posted interrupts to handle the case where the
11008 	 * notification IRQ arrived in the host, or was never sent (because the
11009 	 * target vCPU wasn't running).  Do this regardless of the vCPU's APICv
11010 	 * status, KVM doesn't update assigned devices when APICv is inhibited,
11011 	 * i.e. they can post interrupts even if APICv is temporarily disabled.
11012 	 */
11013 	if (kvm_lapic_enabled(vcpu))
11014 		static_call_cond(kvm_x86_sync_pir_to_irr)(vcpu);
11015 
11016 	if (kvm_vcpu_exit_request(vcpu)) {
11017 		vcpu->mode = OUTSIDE_GUEST_MODE;
11018 		smp_wmb();
11019 		local_irq_enable();
11020 		preempt_enable();
11021 		kvm_vcpu_srcu_read_lock(vcpu);
11022 		r = 1;
11023 		goto cancel_injection;
11024 	}
11025 
11026 	if (req_immediate_exit)
11027 		kvm_make_request(KVM_REQ_EVENT, vcpu);
11028 
11029 	fpregs_assert_state_consistent();
11030 	if (test_thread_flag(TIF_NEED_FPU_LOAD))
11031 		switch_fpu_return();
11032 
11033 	if (vcpu->arch.guest_fpu.xfd_err)
11034 		wrmsrl(MSR_IA32_XFD_ERR, vcpu->arch.guest_fpu.xfd_err);
11035 
11036 	if (unlikely(vcpu->arch.switch_db_regs)) {
11037 		set_debugreg(0, 7);
11038 		set_debugreg(vcpu->arch.eff_db[0], 0);
11039 		set_debugreg(vcpu->arch.eff_db[1], 1);
11040 		set_debugreg(vcpu->arch.eff_db[2], 2);
11041 		set_debugreg(vcpu->arch.eff_db[3], 3);
11042 	} else if (unlikely(hw_breakpoint_active())) {
11043 		set_debugreg(0, 7);
11044 	}
11045 
11046 	guest_timing_enter_irqoff();
11047 
11048 	for (;;) {
11049 		/*
11050 		 * Assert that vCPU vs. VM APICv state is consistent.  An APICv
11051 		 * update must kick and wait for all vCPUs before toggling the
11052 		 * per-VM state, and responding vCPUs must wait for the update
11053 		 * to complete before servicing KVM_REQ_APICV_UPDATE.
11054 		 */
11055 		WARN_ON_ONCE((kvm_vcpu_apicv_activated(vcpu) != kvm_vcpu_apicv_active(vcpu)) &&
11056 			     (kvm_get_apic_mode(vcpu) != LAPIC_MODE_DISABLED));
11057 
11058 		exit_fastpath = static_call(kvm_x86_vcpu_run)(vcpu, req_immediate_exit);
11059 		if (likely(exit_fastpath != EXIT_FASTPATH_REENTER_GUEST))
11060 			break;
11061 
11062 		if (kvm_lapic_enabled(vcpu))
11063 			static_call_cond(kvm_x86_sync_pir_to_irr)(vcpu);
11064 
11065 		if (unlikely(kvm_vcpu_exit_request(vcpu))) {
11066 			exit_fastpath = EXIT_FASTPATH_EXIT_HANDLED;
11067 			break;
11068 		}
11069 
11070 		/* Note, VM-Exits that go down the "slow" path are accounted below. */
11071 		++vcpu->stat.exits;
11072 	}
11073 
11074 	/*
11075 	 * Do this here before restoring debug registers on the host.  And
11076 	 * since we do this before handling the vmexit, a DR access vmexit
11077 	 * can (a) read the correct value of the debug registers, (b) set
11078 	 * KVM_DEBUGREG_WONT_EXIT again.
11079 	 */
11080 	if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) {
11081 		WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP);
11082 		static_call(kvm_x86_sync_dirty_debug_regs)(vcpu);
11083 		kvm_update_dr0123(vcpu);
11084 		kvm_update_dr7(vcpu);
11085 	}
11086 
11087 	/*
11088 	 * If the guest has used debug registers, at least dr7
11089 	 * will be disabled while returning to the host.
11090 	 * If we don't have active breakpoints in the host, we don't
11091 	 * care about the messed up debug address registers. But if
11092 	 * we have some of them active, restore the old state.
11093 	 */
11094 	if (hw_breakpoint_active())
11095 		hw_breakpoint_restore();
11096 
11097 	vcpu->arch.last_vmentry_cpu = vcpu->cpu;
11098 	vcpu->arch.last_guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc());
11099 
11100 	vcpu->mode = OUTSIDE_GUEST_MODE;
11101 	smp_wmb();
11102 
11103 	/*
11104 	 * Sync xfd before calling handle_exit_irqoff() which may
11105 	 * rely on the fact that guest_fpu::xfd is up-to-date (e.g.
11106 	 * in #NM irqoff handler).
11107 	 */
11108 	if (vcpu->arch.xfd_no_write_intercept)
11109 		fpu_sync_guest_vmexit_xfd_state();
11110 
11111 	static_call(kvm_x86_handle_exit_irqoff)(vcpu);
11112 
11113 	if (vcpu->arch.guest_fpu.xfd_err)
11114 		wrmsrl(MSR_IA32_XFD_ERR, 0);
11115 
11116 	/*
11117 	 * Consume any pending interrupts, including the possible source of
11118 	 * VM-Exit on SVM and any ticks that occur between VM-Exit and now.
11119 	 * An instruction is required after local_irq_enable() to fully unblock
11120 	 * interrupts on processors that implement an interrupt shadow, the
11121 	 * stat.exits increment will do nicely.
11122 	 */
11123 	kvm_before_interrupt(vcpu, KVM_HANDLING_IRQ);
11124 	local_irq_enable();
11125 	++vcpu->stat.exits;
11126 	local_irq_disable();
11127 	kvm_after_interrupt(vcpu);
11128 
11129 	/*
11130 	 * Wait until after servicing IRQs to account guest time so that any
11131 	 * ticks that occurred while running the guest are properly accounted
11132 	 * to the guest.  Waiting until IRQs are enabled degrades the accuracy
11133 	 * of accounting via context tracking, but the loss of accuracy is
11134 	 * acceptable for all known use cases.
11135 	 */
11136 	guest_timing_exit_irqoff();
11137 
11138 	local_irq_enable();
11139 	preempt_enable();
11140 
11141 	kvm_vcpu_srcu_read_lock(vcpu);
11142 
11143 	/*
11144 	 * Profile KVM exit RIPs:
11145 	 */
11146 	if (unlikely(prof_on == KVM_PROFILING)) {
11147 		unsigned long rip = kvm_rip_read(vcpu);
11148 		profile_hit(KVM_PROFILING, (void *)rip);
11149 	}
11150 
11151 	if (unlikely(vcpu->arch.tsc_always_catchup))
11152 		kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
11153 
11154 	if (vcpu->arch.apic_attention)
11155 		kvm_lapic_sync_from_vapic(vcpu);
11156 
11157 	r = static_call(kvm_x86_handle_exit)(vcpu, exit_fastpath);
11158 	return r;
11159 
11160 cancel_injection:
11161 	if (req_immediate_exit)
11162 		kvm_make_request(KVM_REQ_EVENT, vcpu);
11163 	static_call(kvm_x86_cancel_injection)(vcpu);
11164 	if (unlikely(vcpu->arch.apic_attention))
11165 		kvm_lapic_sync_from_vapic(vcpu);
11166 out:
11167 	return r;
11168 }
11169 
11170 /* Called within kvm->srcu read side.  */
11171 static inline int vcpu_block(struct kvm_vcpu *vcpu)
11172 {
11173 	bool hv_timer;
11174 
11175 	if (!kvm_arch_vcpu_runnable(vcpu)) {
11176 		/*
11177 		 * Switch to the software timer before halt-polling/blocking as
11178 		 * the guest's timer may be a break event for the vCPU, and the
11179 		 * hypervisor timer runs only when the CPU is in guest mode.
11180 		 * Switch before halt-polling so that KVM recognizes an expired
11181 		 * timer before blocking.
11182 		 */
11183 		hv_timer = kvm_lapic_hv_timer_in_use(vcpu);
11184 		if (hv_timer)
11185 			kvm_lapic_switch_to_sw_timer(vcpu);
11186 
11187 		kvm_vcpu_srcu_read_unlock(vcpu);
11188 		if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED)
11189 			kvm_vcpu_halt(vcpu);
11190 		else
11191 			kvm_vcpu_block(vcpu);
11192 		kvm_vcpu_srcu_read_lock(vcpu);
11193 
11194 		if (hv_timer)
11195 			kvm_lapic_switch_to_hv_timer(vcpu);
11196 
11197 		/*
11198 		 * If the vCPU is not runnable, a signal or another host event
11199 		 * of some kind is pending; service it without changing the
11200 		 * vCPU's activity state.
11201 		 */
11202 		if (!kvm_arch_vcpu_runnable(vcpu))
11203 			return 1;
11204 	}
11205 
11206 	/*
11207 	 * Evaluate nested events before exiting the halted state.  This allows
11208 	 * the halt state to be recorded properly in the VMCS12's activity
11209 	 * state field (AMD does not have a similar field and a VM-Exit always
11210 	 * causes a spurious wakeup from HLT).
11211 	 */
11212 	if (is_guest_mode(vcpu)) {
11213 		if (kvm_check_nested_events(vcpu) < 0)
11214 			return 0;
11215 	}
11216 
11217 	if (kvm_apic_accept_events(vcpu) < 0)
11218 		return 0;
11219 	switch(vcpu->arch.mp_state) {
11220 	case KVM_MP_STATE_HALTED:
11221 	case KVM_MP_STATE_AP_RESET_HOLD:
11222 		vcpu->arch.pv.pv_unhalted = false;
11223 		vcpu->arch.mp_state =
11224 			KVM_MP_STATE_RUNNABLE;
11225 		fallthrough;
11226 	case KVM_MP_STATE_RUNNABLE:
11227 		vcpu->arch.apf.halted = false;
11228 		break;
11229 	case KVM_MP_STATE_INIT_RECEIVED:
11230 		break;
11231 	default:
11232 		WARN_ON_ONCE(1);
11233 		break;
11234 	}
11235 	return 1;
11236 }
11237 
11238 static inline bool kvm_vcpu_running(struct kvm_vcpu *vcpu)
11239 {
11240 	return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
11241 		!vcpu->arch.apf.halted);
11242 }
11243 
11244 /* Called within kvm->srcu read side.  */
11245 static int vcpu_run(struct kvm_vcpu *vcpu)
11246 {
11247 	int r;
11248 
11249 	vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
11250 	vcpu->arch.l1tf_flush_l1d = true;
11251 
11252 	for (;;) {
11253 		/*
11254 		 * If another guest vCPU requests a PV TLB flush in the middle
11255 		 * of instruction emulation, the rest of the emulation could
11256 		 * use a stale page translation. Assume that any code after
11257 		 * this point can start executing an instruction.
11258 		 */
11259 		vcpu->arch.at_instruction_boundary = false;
11260 		if (kvm_vcpu_running(vcpu)) {
11261 			r = vcpu_enter_guest(vcpu);
11262 		} else {
11263 			r = vcpu_block(vcpu);
11264 		}
11265 
11266 		if (r <= 0)
11267 			break;
11268 
11269 		kvm_clear_request(KVM_REQ_UNBLOCK, vcpu);
11270 		if (kvm_xen_has_pending_events(vcpu))
11271 			kvm_xen_inject_pending_events(vcpu);
11272 
11273 		if (kvm_cpu_has_pending_timer(vcpu))
11274 			kvm_inject_pending_timer_irqs(vcpu);
11275 
11276 		if (dm_request_for_irq_injection(vcpu) &&
11277 			kvm_vcpu_ready_for_interrupt_injection(vcpu)) {
11278 			r = 0;
11279 			vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
11280 			++vcpu->stat.request_irq_exits;
11281 			break;
11282 		}
11283 
11284 		if (__xfer_to_guest_mode_work_pending()) {
11285 			kvm_vcpu_srcu_read_unlock(vcpu);
11286 			r = xfer_to_guest_mode_handle_work(vcpu);
11287 			kvm_vcpu_srcu_read_lock(vcpu);
11288 			if (r)
11289 				return r;
11290 		}
11291 	}
11292 
11293 	return r;
11294 }
11295 
11296 static inline int complete_emulated_io(struct kvm_vcpu *vcpu)
11297 {
11298 	return kvm_emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
11299 }
11300 
11301 static int complete_emulated_pio(struct kvm_vcpu *vcpu)
11302 {
11303 	BUG_ON(!vcpu->arch.pio.count);
11304 
11305 	return complete_emulated_io(vcpu);
11306 }
11307 
11308 /*
11309  * Implements the following, as a state machine:
11310  *
11311  * read:
11312  *   for each fragment
11313  *     for each mmio piece in the fragment
11314  *       write gpa, len
11315  *       exit
11316  *       copy data
11317  *   execute insn
11318  *
11319  * write:
11320  *   for each fragment
11321  *     for each mmio piece in the fragment
11322  *       write gpa, len
11323  *       copy data
11324  *       exit
11325  */
11326 static int complete_emulated_mmio(struct kvm_vcpu *vcpu)
11327 {
11328 	struct kvm_run *run = vcpu->run;
11329 	struct kvm_mmio_fragment *frag;
11330 	unsigned len;
11331 
11332 	BUG_ON(!vcpu->mmio_needed);
11333 
11334 	/* Complete previous fragment */
11335 	frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
11336 	len = min(8u, frag->len);
11337 	if (!vcpu->mmio_is_write)
11338 		memcpy(frag->data, run->mmio.data, len);
11339 
11340 	if (frag->len <= 8) {
11341 		/* Switch to the next fragment. */
11342 		frag++;
11343 		vcpu->mmio_cur_fragment++;
11344 	} else {
11345 		/* Go forward to the next mmio piece. */
11346 		frag->data += len;
11347 		frag->gpa += len;
11348 		frag->len -= len;
11349 	}
11350 
11351 	if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) {
11352 		vcpu->mmio_needed = 0;
11353 
11354 		/* FIXME: return into emulator if single-stepping.  */
11355 		if (vcpu->mmio_is_write)
11356 			return 1;
11357 		vcpu->mmio_read_completed = 1;
11358 		return complete_emulated_io(vcpu);
11359 	}
11360 
11361 	run->exit_reason = KVM_EXIT_MMIO;
11362 	run->mmio.phys_addr = frag->gpa;
11363 	if (vcpu->mmio_is_write)
11364 		memcpy(run->mmio.data, frag->data, min(8u, frag->len));
11365 	run->mmio.len = min(8u, frag->len);
11366 	run->mmio.is_write = vcpu->mmio_is_write;
11367 	vcpu->arch.complete_userspace_io = complete_emulated_mmio;
11368 	return 0;
11369 }
11370 
11371 /* Swap (qemu) user FPU context for the guest FPU context. */
11372 static void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
11373 {
11374 	/* Exclude PKRU, it's restored separately immediately after VM-Exit. */
11375 	fpu_swap_kvm_fpstate(&vcpu->arch.guest_fpu, true);
11376 	trace_kvm_fpu(1);
11377 }
11378 
11379 /* When vcpu_run ends, restore user space FPU context. */
11380 static void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
11381 {
11382 	fpu_swap_kvm_fpstate(&vcpu->arch.guest_fpu, false);
11383 	++vcpu->stat.fpu_reload;
11384 	trace_kvm_fpu(0);
11385 }
11386 
11387 int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu)
11388 {
11389 	struct kvm_queued_exception *ex = &vcpu->arch.exception;
11390 	struct kvm_run *kvm_run = vcpu->run;
11391 	int r;
11392 
11393 	vcpu_load(vcpu);
11394 	kvm_sigset_activate(vcpu);
11395 	kvm_run->flags = 0;
11396 	kvm_load_guest_fpu(vcpu);
11397 
11398 	kvm_vcpu_srcu_read_lock(vcpu);
11399 	if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
11400 		if (kvm_run->immediate_exit) {
11401 			r = -EINTR;
11402 			goto out;
11403 		}
11404 
11405 		/*
11406 		 * Don't bother switching APIC timer emulation from the
11407 		 * hypervisor timer to the software timer, the only way for the
11408 		 * APIC timer to be active is if userspace stuffed vCPU state,
11409 		 * i.e. put the vCPU into a nonsensical state.  Only an INIT
11410 		 * will transition the vCPU out of UNINITIALIZED (without more
11411 		 * state stuffing from userspace), which will reset the local
11412 		 * APIC and thus cancel the timer or drop the IRQ (if the timer
11413 		 * already expired).
11414 		 */
11415 		kvm_vcpu_srcu_read_unlock(vcpu);
11416 		kvm_vcpu_block(vcpu);
11417 		kvm_vcpu_srcu_read_lock(vcpu);
11418 
11419 		if (kvm_apic_accept_events(vcpu) < 0) {
11420 			r = 0;
11421 			goto out;
11422 		}
11423 		r = -EAGAIN;
11424 		if (signal_pending(current)) {
11425 			r = -EINTR;
11426 			kvm_run->exit_reason = KVM_EXIT_INTR;
11427 			++vcpu->stat.signal_exits;
11428 		}
11429 		goto out;
11430 	}
11431 
11432 	if ((kvm_run->kvm_valid_regs & ~KVM_SYNC_X86_VALID_FIELDS) ||
11433 	    (kvm_run->kvm_dirty_regs & ~KVM_SYNC_X86_VALID_FIELDS)) {
11434 		r = -EINVAL;
11435 		goto out;
11436 	}
11437 
11438 	if (kvm_run->kvm_dirty_regs) {
11439 		r = sync_regs(vcpu);
11440 		if (r != 0)
11441 			goto out;
11442 	}
11443 
11444 	/* re-sync apic's tpr */
11445 	if (!lapic_in_kernel(vcpu)) {
11446 		if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
11447 			r = -EINVAL;
11448 			goto out;
11449 		}
11450 	}
11451 
11452 	/*
11453 	 * If userspace set a pending exception and L2 is active, convert it to
11454 	 * a pending VM-Exit if L1 wants to intercept the exception.
11455 	 */
11456 	if (vcpu->arch.exception_from_userspace && is_guest_mode(vcpu) &&
11457 	    kvm_x86_ops.nested_ops->is_exception_vmexit(vcpu, ex->vector,
11458 							ex->error_code)) {
11459 		kvm_queue_exception_vmexit(vcpu, ex->vector,
11460 					   ex->has_error_code, ex->error_code,
11461 					   ex->has_payload, ex->payload);
11462 		ex->injected = false;
11463 		ex->pending = false;
11464 	}
11465 	vcpu->arch.exception_from_userspace = false;
11466 
11467 	if (unlikely(vcpu->arch.complete_userspace_io)) {
11468 		int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io;
11469 		vcpu->arch.complete_userspace_io = NULL;
11470 		r = cui(vcpu);
11471 		if (r <= 0)
11472 			goto out;
11473 	} else {
11474 		WARN_ON_ONCE(vcpu->arch.pio.count);
11475 		WARN_ON_ONCE(vcpu->mmio_needed);
11476 	}
11477 
11478 	if (kvm_run->immediate_exit) {
11479 		r = -EINTR;
11480 		goto out;
11481 	}
11482 
11483 	r = static_call(kvm_x86_vcpu_pre_run)(vcpu);
11484 	if (r <= 0)
11485 		goto out;
11486 
11487 	r = vcpu_run(vcpu);
11488 
11489 out:
11490 	kvm_put_guest_fpu(vcpu);
11491 	if (kvm_run->kvm_valid_regs)
11492 		store_regs(vcpu);
11493 	post_kvm_run_save(vcpu);
11494 	kvm_vcpu_srcu_read_unlock(vcpu);
11495 
11496 	kvm_sigset_deactivate(vcpu);
11497 	vcpu_put(vcpu);
11498 	return r;
11499 }
11500 
11501 static void __get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
11502 {
11503 	if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
11504 		/*
11505 		 * We are here if userspace calls get_regs() in the middle of
11506 		 * instruction emulation. Registers state needs to be copied
11507 		 * back from emulation context to vcpu. Userspace shouldn't do
11508 		 * that usually, but some bad designed PV devices (vmware
11509 		 * backdoor interface) need this to work
11510 		 */
11511 		emulator_writeback_register_cache(vcpu->arch.emulate_ctxt);
11512 		vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
11513 	}
11514 	regs->rax = kvm_rax_read(vcpu);
11515 	regs->rbx = kvm_rbx_read(vcpu);
11516 	regs->rcx = kvm_rcx_read(vcpu);
11517 	regs->rdx = kvm_rdx_read(vcpu);
11518 	regs->rsi = kvm_rsi_read(vcpu);
11519 	regs->rdi = kvm_rdi_read(vcpu);
11520 	regs->rsp = kvm_rsp_read(vcpu);
11521 	regs->rbp = kvm_rbp_read(vcpu);
11522 #ifdef CONFIG_X86_64
11523 	regs->r8 = kvm_r8_read(vcpu);
11524 	regs->r9 = kvm_r9_read(vcpu);
11525 	regs->r10 = kvm_r10_read(vcpu);
11526 	regs->r11 = kvm_r11_read(vcpu);
11527 	regs->r12 = kvm_r12_read(vcpu);
11528 	regs->r13 = kvm_r13_read(vcpu);
11529 	regs->r14 = kvm_r14_read(vcpu);
11530 	regs->r15 = kvm_r15_read(vcpu);
11531 #endif
11532 
11533 	regs->rip = kvm_rip_read(vcpu);
11534 	regs->rflags = kvm_get_rflags(vcpu);
11535 }
11536 
11537 int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
11538 {
11539 	if (vcpu->kvm->arch.has_protected_state &&
11540 	    vcpu->arch.guest_state_protected)
11541 		return -EINVAL;
11542 
11543 	vcpu_load(vcpu);
11544 	__get_regs(vcpu, regs);
11545 	vcpu_put(vcpu);
11546 	return 0;
11547 }
11548 
11549 static void __set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
11550 {
11551 	vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
11552 	vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
11553 
11554 	kvm_rax_write(vcpu, regs->rax);
11555 	kvm_rbx_write(vcpu, regs->rbx);
11556 	kvm_rcx_write(vcpu, regs->rcx);
11557 	kvm_rdx_write(vcpu, regs->rdx);
11558 	kvm_rsi_write(vcpu, regs->rsi);
11559 	kvm_rdi_write(vcpu, regs->rdi);
11560 	kvm_rsp_write(vcpu, regs->rsp);
11561 	kvm_rbp_write(vcpu, regs->rbp);
11562 #ifdef CONFIG_X86_64
11563 	kvm_r8_write(vcpu, regs->r8);
11564 	kvm_r9_write(vcpu, regs->r9);
11565 	kvm_r10_write(vcpu, regs->r10);
11566 	kvm_r11_write(vcpu, regs->r11);
11567 	kvm_r12_write(vcpu, regs->r12);
11568 	kvm_r13_write(vcpu, regs->r13);
11569 	kvm_r14_write(vcpu, regs->r14);
11570 	kvm_r15_write(vcpu, regs->r15);
11571 #endif
11572 
11573 	kvm_rip_write(vcpu, regs->rip);
11574 	kvm_set_rflags(vcpu, regs->rflags | X86_EFLAGS_FIXED);
11575 
11576 	vcpu->arch.exception.pending = false;
11577 	vcpu->arch.exception_vmexit.pending = false;
11578 
11579 	kvm_make_request(KVM_REQ_EVENT, vcpu);
11580 }
11581 
11582 int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
11583 {
11584 	if (vcpu->kvm->arch.has_protected_state &&
11585 	    vcpu->arch.guest_state_protected)
11586 		return -EINVAL;
11587 
11588 	vcpu_load(vcpu);
11589 	__set_regs(vcpu, regs);
11590 	vcpu_put(vcpu);
11591 	return 0;
11592 }
11593 
11594 static void __get_sregs_common(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
11595 {
11596 	struct desc_ptr dt;
11597 
11598 	if (vcpu->arch.guest_state_protected)
11599 		goto skip_protected_regs;
11600 
11601 	kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
11602 	kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
11603 	kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
11604 	kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
11605 	kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
11606 	kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
11607 
11608 	kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
11609 	kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
11610 
11611 	static_call(kvm_x86_get_idt)(vcpu, &dt);
11612 	sregs->idt.limit = dt.size;
11613 	sregs->idt.base = dt.address;
11614 	static_call(kvm_x86_get_gdt)(vcpu, &dt);
11615 	sregs->gdt.limit = dt.size;
11616 	sregs->gdt.base = dt.address;
11617 
11618 	sregs->cr2 = vcpu->arch.cr2;
11619 	sregs->cr3 = kvm_read_cr3(vcpu);
11620 
11621 skip_protected_regs:
11622 	sregs->cr0 = kvm_read_cr0(vcpu);
11623 	sregs->cr4 = kvm_read_cr4(vcpu);
11624 	sregs->cr8 = kvm_get_cr8(vcpu);
11625 	sregs->efer = vcpu->arch.efer;
11626 	sregs->apic_base = kvm_get_apic_base(vcpu);
11627 }
11628 
11629 static void __get_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
11630 {
11631 	__get_sregs_common(vcpu, sregs);
11632 
11633 	if (vcpu->arch.guest_state_protected)
11634 		return;
11635 
11636 	if (vcpu->arch.interrupt.injected && !vcpu->arch.interrupt.soft)
11637 		set_bit(vcpu->arch.interrupt.nr,
11638 			(unsigned long *)sregs->interrupt_bitmap);
11639 }
11640 
11641 static void __get_sregs2(struct kvm_vcpu *vcpu, struct kvm_sregs2 *sregs2)
11642 {
11643 	int i;
11644 
11645 	__get_sregs_common(vcpu, (struct kvm_sregs *)sregs2);
11646 
11647 	if (vcpu->arch.guest_state_protected)
11648 		return;
11649 
11650 	if (is_pae_paging(vcpu)) {
11651 		for (i = 0 ; i < 4 ; i++)
11652 			sregs2->pdptrs[i] = kvm_pdptr_read(vcpu, i);
11653 		sregs2->flags |= KVM_SREGS2_FLAGS_PDPTRS_VALID;
11654 	}
11655 }
11656 
11657 int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
11658 				  struct kvm_sregs *sregs)
11659 {
11660 	if (vcpu->kvm->arch.has_protected_state &&
11661 	    vcpu->arch.guest_state_protected)
11662 		return -EINVAL;
11663 
11664 	vcpu_load(vcpu);
11665 	__get_sregs(vcpu, sregs);
11666 	vcpu_put(vcpu);
11667 	return 0;
11668 }
11669 
11670 int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
11671 				    struct kvm_mp_state *mp_state)
11672 {
11673 	int r;
11674 
11675 	vcpu_load(vcpu);
11676 	if (kvm_mpx_supported())
11677 		kvm_load_guest_fpu(vcpu);
11678 
11679 	r = kvm_apic_accept_events(vcpu);
11680 	if (r < 0)
11681 		goto out;
11682 	r = 0;
11683 
11684 	if ((vcpu->arch.mp_state == KVM_MP_STATE_HALTED ||
11685 	     vcpu->arch.mp_state == KVM_MP_STATE_AP_RESET_HOLD) &&
11686 	    vcpu->arch.pv.pv_unhalted)
11687 		mp_state->mp_state = KVM_MP_STATE_RUNNABLE;
11688 	else
11689 		mp_state->mp_state = vcpu->arch.mp_state;
11690 
11691 out:
11692 	if (kvm_mpx_supported())
11693 		kvm_put_guest_fpu(vcpu);
11694 	vcpu_put(vcpu);
11695 	return r;
11696 }
11697 
11698 int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
11699 				    struct kvm_mp_state *mp_state)
11700 {
11701 	int ret = -EINVAL;
11702 
11703 	vcpu_load(vcpu);
11704 
11705 	switch (mp_state->mp_state) {
11706 	case KVM_MP_STATE_UNINITIALIZED:
11707 	case KVM_MP_STATE_HALTED:
11708 	case KVM_MP_STATE_AP_RESET_HOLD:
11709 	case KVM_MP_STATE_INIT_RECEIVED:
11710 	case KVM_MP_STATE_SIPI_RECEIVED:
11711 		if (!lapic_in_kernel(vcpu))
11712 			goto out;
11713 		break;
11714 
11715 	case KVM_MP_STATE_RUNNABLE:
11716 		break;
11717 
11718 	default:
11719 		goto out;
11720 	}
11721 
11722 	/*
11723 	 * Pending INITs are reported using KVM_SET_VCPU_EVENTS, disallow
11724 	 * forcing the guest into INIT/SIPI if those events are supposed to be
11725 	 * blocked.  KVM prioritizes SMI over INIT, so reject INIT/SIPI state
11726 	 * if an SMI is pending as well.
11727 	 */
11728 	if ((!kvm_apic_init_sipi_allowed(vcpu) || vcpu->arch.smi_pending) &&
11729 	    (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED ||
11730 	     mp_state->mp_state == KVM_MP_STATE_INIT_RECEIVED))
11731 		goto out;
11732 
11733 	if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
11734 		vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
11735 		set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events);
11736 	} else
11737 		vcpu->arch.mp_state = mp_state->mp_state;
11738 	kvm_make_request(KVM_REQ_EVENT, vcpu);
11739 
11740 	ret = 0;
11741 out:
11742 	vcpu_put(vcpu);
11743 	return ret;
11744 }
11745 
11746 int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
11747 		    int reason, bool has_error_code, u32 error_code)
11748 {
11749 	struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt;
11750 	int ret;
11751 
11752 	init_emulate_ctxt(vcpu);
11753 
11754 	ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
11755 				   has_error_code, error_code);
11756 	if (ret) {
11757 		vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
11758 		vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
11759 		vcpu->run->internal.ndata = 0;
11760 		return 0;
11761 	}
11762 
11763 	kvm_rip_write(vcpu, ctxt->eip);
11764 	kvm_set_rflags(vcpu, ctxt->eflags);
11765 	return 1;
11766 }
11767 EXPORT_SYMBOL_GPL(kvm_task_switch);
11768 
11769 static bool kvm_is_valid_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
11770 {
11771 	if ((sregs->efer & EFER_LME) && (sregs->cr0 & X86_CR0_PG)) {
11772 		/*
11773 		 * When EFER.LME and CR0.PG are set, the processor is in
11774 		 * 64-bit mode (though maybe in a 32-bit code segment).
11775 		 * CR4.PAE and EFER.LMA must be set.
11776 		 */
11777 		if (!(sregs->cr4 & X86_CR4_PAE) || !(sregs->efer & EFER_LMA))
11778 			return false;
11779 		if (!kvm_vcpu_is_legal_cr3(vcpu, sregs->cr3))
11780 			return false;
11781 	} else {
11782 		/*
11783 		 * Not in 64-bit mode: EFER.LMA is clear and the code
11784 		 * segment cannot be 64-bit.
11785 		 */
11786 		if (sregs->efer & EFER_LMA || sregs->cs.l)
11787 			return false;
11788 	}
11789 
11790 	return kvm_is_valid_cr4(vcpu, sregs->cr4) &&
11791 	       kvm_is_valid_cr0(vcpu, sregs->cr0);
11792 }
11793 
11794 static int __set_sregs_common(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs,
11795 		int *mmu_reset_needed, bool update_pdptrs)
11796 {
11797 	struct msr_data apic_base_msr;
11798 	int idx;
11799 	struct desc_ptr dt;
11800 
11801 	if (!kvm_is_valid_sregs(vcpu, sregs))
11802 		return -EINVAL;
11803 
11804 	apic_base_msr.data = sregs->apic_base;
11805 	apic_base_msr.host_initiated = true;
11806 	if (kvm_set_apic_base(vcpu, &apic_base_msr))
11807 		return -EINVAL;
11808 
11809 	if (vcpu->arch.guest_state_protected)
11810 		return 0;
11811 
11812 	dt.size = sregs->idt.limit;
11813 	dt.address = sregs->idt.base;
11814 	static_call(kvm_x86_set_idt)(vcpu, &dt);
11815 	dt.size = sregs->gdt.limit;
11816 	dt.address = sregs->gdt.base;
11817 	static_call(kvm_x86_set_gdt)(vcpu, &dt);
11818 
11819 	vcpu->arch.cr2 = sregs->cr2;
11820 	*mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
11821 	vcpu->arch.cr3 = sregs->cr3;
11822 	kvm_register_mark_dirty(vcpu, VCPU_EXREG_CR3);
11823 	static_call_cond(kvm_x86_post_set_cr3)(vcpu, sregs->cr3);
11824 
11825 	kvm_set_cr8(vcpu, sregs->cr8);
11826 
11827 	*mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
11828 	static_call(kvm_x86_set_efer)(vcpu, sregs->efer);
11829 
11830 	*mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
11831 	static_call(kvm_x86_set_cr0)(vcpu, sregs->cr0);
11832 
11833 	*mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
11834 	static_call(kvm_x86_set_cr4)(vcpu, sregs->cr4);
11835 
11836 	if (update_pdptrs) {
11837 		idx = srcu_read_lock(&vcpu->kvm->srcu);
11838 		if (is_pae_paging(vcpu)) {
11839 			load_pdptrs(vcpu, kvm_read_cr3(vcpu));
11840 			*mmu_reset_needed = 1;
11841 		}
11842 		srcu_read_unlock(&vcpu->kvm->srcu, idx);
11843 	}
11844 
11845 	kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
11846 	kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
11847 	kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
11848 	kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
11849 	kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
11850 	kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
11851 
11852 	kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
11853 	kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
11854 
11855 	update_cr8_intercept(vcpu);
11856 
11857 	/* Older userspace won't unhalt the vcpu on reset. */
11858 	if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
11859 	    sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
11860 	    !is_protmode(vcpu))
11861 		vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
11862 
11863 	return 0;
11864 }
11865 
11866 static int __set_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
11867 {
11868 	int pending_vec, max_bits;
11869 	int mmu_reset_needed = 0;
11870 	int ret = __set_sregs_common(vcpu, sregs, &mmu_reset_needed, true);
11871 
11872 	if (ret)
11873 		return ret;
11874 
11875 	if (mmu_reset_needed) {
11876 		kvm_mmu_reset_context(vcpu);
11877 		kvm_make_request(KVM_REQ_TLB_FLUSH_GUEST, vcpu);
11878 	}
11879 
11880 	max_bits = KVM_NR_INTERRUPTS;
11881 	pending_vec = find_first_bit(
11882 		(const unsigned long *)sregs->interrupt_bitmap, max_bits);
11883 
11884 	if (pending_vec < max_bits) {
11885 		kvm_queue_interrupt(vcpu, pending_vec, false);
11886 		pr_debug("Set back pending irq %d\n", pending_vec);
11887 		kvm_make_request(KVM_REQ_EVENT, vcpu);
11888 	}
11889 	return 0;
11890 }
11891 
11892 static int __set_sregs2(struct kvm_vcpu *vcpu, struct kvm_sregs2 *sregs2)
11893 {
11894 	int mmu_reset_needed = 0;
11895 	bool valid_pdptrs = sregs2->flags & KVM_SREGS2_FLAGS_PDPTRS_VALID;
11896 	bool pae = (sregs2->cr0 & X86_CR0_PG) && (sregs2->cr4 & X86_CR4_PAE) &&
11897 		!(sregs2->efer & EFER_LMA);
11898 	int i, ret;
11899 
11900 	if (sregs2->flags & ~KVM_SREGS2_FLAGS_PDPTRS_VALID)
11901 		return -EINVAL;
11902 
11903 	if (valid_pdptrs && (!pae || vcpu->arch.guest_state_protected))
11904 		return -EINVAL;
11905 
11906 	ret = __set_sregs_common(vcpu, (struct kvm_sregs *)sregs2,
11907 				 &mmu_reset_needed, !valid_pdptrs);
11908 	if (ret)
11909 		return ret;
11910 
11911 	if (valid_pdptrs) {
11912 		for (i = 0; i < 4 ; i++)
11913 			kvm_pdptr_write(vcpu, i, sregs2->pdptrs[i]);
11914 
11915 		kvm_register_mark_dirty(vcpu, VCPU_EXREG_PDPTR);
11916 		mmu_reset_needed = 1;
11917 		vcpu->arch.pdptrs_from_userspace = true;
11918 	}
11919 	if (mmu_reset_needed) {
11920 		kvm_mmu_reset_context(vcpu);
11921 		kvm_make_request(KVM_REQ_TLB_FLUSH_GUEST, vcpu);
11922 	}
11923 	return 0;
11924 }
11925 
11926 int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
11927 				  struct kvm_sregs *sregs)
11928 {
11929 	int ret;
11930 
11931 	if (vcpu->kvm->arch.has_protected_state &&
11932 	    vcpu->arch.guest_state_protected)
11933 		return -EINVAL;
11934 
11935 	vcpu_load(vcpu);
11936 	ret = __set_sregs(vcpu, sregs);
11937 	vcpu_put(vcpu);
11938 	return ret;
11939 }
11940 
11941 static void kvm_arch_vcpu_guestdbg_update_apicv_inhibit(struct kvm *kvm)
11942 {
11943 	bool set = false;
11944 	struct kvm_vcpu *vcpu;
11945 	unsigned long i;
11946 
11947 	if (!enable_apicv)
11948 		return;
11949 
11950 	down_write(&kvm->arch.apicv_update_lock);
11951 
11952 	kvm_for_each_vcpu(i, vcpu, kvm) {
11953 		if (vcpu->guest_debug & KVM_GUESTDBG_BLOCKIRQ) {
11954 			set = true;
11955 			break;
11956 		}
11957 	}
11958 	__kvm_set_or_clear_apicv_inhibit(kvm, APICV_INHIBIT_REASON_BLOCKIRQ, set);
11959 	up_write(&kvm->arch.apicv_update_lock);
11960 }
11961 
11962 int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
11963 					struct kvm_guest_debug *dbg)
11964 {
11965 	unsigned long rflags;
11966 	int i, r;
11967 
11968 	if (vcpu->arch.guest_state_protected)
11969 		return -EINVAL;
11970 
11971 	vcpu_load(vcpu);
11972 
11973 	if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
11974 		r = -EBUSY;
11975 		if (kvm_is_exception_pending(vcpu))
11976 			goto out;
11977 		if (dbg->control & KVM_GUESTDBG_INJECT_DB)
11978 			kvm_queue_exception(vcpu, DB_VECTOR);
11979 		else
11980 			kvm_queue_exception(vcpu, BP_VECTOR);
11981 	}
11982 
11983 	/*
11984 	 * Read rflags as long as potentially injected trace flags are still
11985 	 * filtered out.
11986 	 */
11987 	rflags = kvm_get_rflags(vcpu);
11988 
11989 	vcpu->guest_debug = dbg->control;
11990 	if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
11991 		vcpu->guest_debug = 0;
11992 
11993 	if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
11994 		for (i = 0; i < KVM_NR_DB_REGS; ++i)
11995 			vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
11996 		vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7];
11997 	} else {
11998 		for (i = 0; i < KVM_NR_DB_REGS; i++)
11999 			vcpu->arch.eff_db[i] = vcpu->arch.db[i];
12000 	}
12001 	kvm_update_dr7(vcpu);
12002 
12003 	if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
12004 		vcpu->arch.singlestep_rip = kvm_get_linear_rip(vcpu);
12005 
12006 	/*
12007 	 * Trigger an rflags update that will inject or remove the trace
12008 	 * flags.
12009 	 */
12010 	kvm_set_rflags(vcpu, rflags);
12011 
12012 	static_call(kvm_x86_update_exception_bitmap)(vcpu);
12013 
12014 	kvm_arch_vcpu_guestdbg_update_apicv_inhibit(vcpu->kvm);
12015 
12016 	r = 0;
12017 
12018 out:
12019 	vcpu_put(vcpu);
12020 	return r;
12021 }
12022 
12023 /*
12024  * Translate a guest virtual address to a guest physical address.
12025  */
12026 int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
12027 				    struct kvm_translation *tr)
12028 {
12029 	unsigned long vaddr = tr->linear_address;
12030 	gpa_t gpa;
12031 	int idx;
12032 
12033 	vcpu_load(vcpu);
12034 
12035 	idx = srcu_read_lock(&vcpu->kvm->srcu);
12036 	gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
12037 	srcu_read_unlock(&vcpu->kvm->srcu, idx);
12038 	tr->physical_address = gpa;
12039 	tr->valid = gpa != INVALID_GPA;
12040 	tr->writeable = 1;
12041 	tr->usermode = 0;
12042 
12043 	vcpu_put(vcpu);
12044 	return 0;
12045 }
12046 
12047 int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
12048 {
12049 	struct fxregs_state *fxsave;
12050 
12051 	if (fpstate_is_confidential(&vcpu->arch.guest_fpu))
12052 		return vcpu->kvm->arch.has_protected_state ? -EINVAL : 0;
12053 
12054 	vcpu_load(vcpu);
12055 
12056 	fxsave = &vcpu->arch.guest_fpu.fpstate->regs.fxsave;
12057 	memcpy(fpu->fpr, fxsave->st_space, 128);
12058 	fpu->fcw = fxsave->cwd;
12059 	fpu->fsw = fxsave->swd;
12060 	fpu->ftwx = fxsave->twd;
12061 	fpu->last_opcode = fxsave->fop;
12062 	fpu->last_ip = fxsave->rip;
12063 	fpu->last_dp = fxsave->rdp;
12064 	memcpy(fpu->xmm, fxsave->xmm_space, sizeof(fxsave->xmm_space));
12065 
12066 	vcpu_put(vcpu);
12067 	return 0;
12068 }
12069 
12070 int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
12071 {
12072 	struct fxregs_state *fxsave;
12073 
12074 	if (fpstate_is_confidential(&vcpu->arch.guest_fpu))
12075 		return vcpu->kvm->arch.has_protected_state ? -EINVAL : 0;
12076 
12077 	vcpu_load(vcpu);
12078 
12079 	fxsave = &vcpu->arch.guest_fpu.fpstate->regs.fxsave;
12080 
12081 	memcpy(fxsave->st_space, fpu->fpr, 128);
12082 	fxsave->cwd = fpu->fcw;
12083 	fxsave->swd = fpu->fsw;
12084 	fxsave->twd = fpu->ftwx;
12085 	fxsave->fop = fpu->last_opcode;
12086 	fxsave->rip = fpu->last_ip;
12087 	fxsave->rdp = fpu->last_dp;
12088 	memcpy(fxsave->xmm_space, fpu->xmm, sizeof(fxsave->xmm_space));
12089 
12090 	vcpu_put(vcpu);
12091 	return 0;
12092 }
12093 
12094 static void store_regs(struct kvm_vcpu *vcpu)
12095 {
12096 	BUILD_BUG_ON(sizeof(struct kvm_sync_regs) > SYNC_REGS_SIZE_BYTES);
12097 
12098 	if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_REGS)
12099 		__get_regs(vcpu, &vcpu->run->s.regs.regs);
12100 
12101 	if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_SREGS)
12102 		__get_sregs(vcpu, &vcpu->run->s.regs.sregs);
12103 
12104 	if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_EVENTS)
12105 		kvm_vcpu_ioctl_x86_get_vcpu_events(
12106 				vcpu, &vcpu->run->s.regs.events);
12107 }
12108 
12109 static int sync_regs(struct kvm_vcpu *vcpu)
12110 {
12111 	if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_REGS) {
12112 		__set_regs(vcpu, &vcpu->run->s.regs.regs);
12113 		vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_REGS;
12114 	}
12115 
12116 	if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_SREGS) {
12117 		struct kvm_sregs sregs = vcpu->run->s.regs.sregs;
12118 
12119 		if (__set_sregs(vcpu, &sregs))
12120 			return -EINVAL;
12121 
12122 		vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_SREGS;
12123 	}
12124 
12125 	if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_EVENTS) {
12126 		struct kvm_vcpu_events events = vcpu->run->s.regs.events;
12127 
12128 		if (kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events))
12129 			return -EINVAL;
12130 
12131 		vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_EVENTS;
12132 	}
12133 
12134 	return 0;
12135 }
12136 
12137 int kvm_arch_vcpu_precreate(struct kvm *kvm, unsigned int id)
12138 {
12139 	if (kvm_check_tsc_unstable() && kvm->created_vcpus)
12140 		pr_warn_once("SMP vm created on host with unstable TSC; "
12141 			     "guest TSC will not be reliable\n");
12142 
12143 	if (!kvm->arch.max_vcpu_ids)
12144 		kvm->arch.max_vcpu_ids = KVM_MAX_VCPU_IDS;
12145 
12146 	if (id >= kvm->arch.max_vcpu_ids)
12147 		return -EINVAL;
12148 
12149 	return static_call(kvm_x86_vcpu_precreate)(kvm);
12150 }
12151 
12152 int kvm_arch_vcpu_create(struct kvm_vcpu *vcpu)
12153 {
12154 	struct page *page;
12155 	int r;
12156 
12157 	vcpu->arch.last_vmentry_cpu = -1;
12158 	vcpu->arch.regs_avail = ~0;
12159 	vcpu->arch.regs_dirty = ~0;
12160 
12161 	kvm_gpc_init(&vcpu->arch.pv_time, vcpu->kvm);
12162 
12163 	if (!irqchip_in_kernel(vcpu->kvm) || kvm_vcpu_is_reset_bsp(vcpu))
12164 		vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
12165 	else
12166 		vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
12167 
12168 	r = kvm_mmu_create(vcpu);
12169 	if (r < 0)
12170 		return r;
12171 
12172 	r = kvm_create_lapic(vcpu, lapic_timer_advance_ns);
12173 	if (r < 0)
12174 		goto fail_mmu_destroy;
12175 
12176 	r = -ENOMEM;
12177 
12178 	page = alloc_page(GFP_KERNEL_ACCOUNT | __GFP_ZERO);
12179 	if (!page)
12180 		goto fail_free_lapic;
12181 	vcpu->arch.pio_data = page_address(page);
12182 
12183 	vcpu->arch.mce_banks = kcalloc(KVM_MAX_MCE_BANKS * 4, sizeof(u64),
12184 				       GFP_KERNEL_ACCOUNT);
12185 	vcpu->arch.mci_ctl2_banks = kcalloc(KVM_MAX_MCE_BANKS, sizeof(u64),
12186 					    GFP_KERNEL_ACCOUNT);
12187 	if (!vcpu->arch.mce_banks || !vcpu->arch.mci_ctl2_banks)
12188 		goto fail_free_mce_banks;
12189 	vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
12190 
12191 	if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask,
12192 				GFP_KERNEL_ACCOUNT))
12193 		goto fail_free_mce_banks;
12194 
12195 	if (!alloc_emulate_ctxt(vcpu))
12196 		goto free_wbinvd_dirty_mask;
12197 
12198 	if (!fpu_alloc_guest_fpstate(&vcpu->arch.guest_fpu)) {
12199 		pr_err("failed to allocate vcpu's fpu\n");
12200 		goto free_emulate_ctxt;
12201 	}
12202 
12203 	vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu);
12204 	vcpu->arch.reserved_gpa_bits = kvm_vcpu_reserved_gpa_bits_raw(vcpu);
12205 
12206 	vcpu->arch.pat = MSR_IA32_CR_PAT_DEFAULT;
12207 
12208 	kvm_async_pf_hash_reset(vcpu);
12209 
12210 	vcpu->arch.perf_capabilities = kvm_caps.supported_perf_cap;
12211 	kvm_pmu_init(vcpu);
12212 
12213 	vcpu->arch.pending_external_vector = -1;
12214 	vcpu->arch.preempted_in_kernel = false;
12215 
12216 #if IS_ENABLED(CONFIG_HYPERV)
12217 	vcpu->arch.hv_root_tdp = INVALID_PAGE;
12218 #endif
12219 
12220 	r = static_call(kvm_x86_vcpu_create)(vcpu);
12221 	if (r)
12222 		goto free_guest_fpu;
12223 
12224 	vcpu->arch.arch_capabilities = kvm_get_arch_capabilities();
12225 	vcpu->arch.msr_platform_info = MSR_PLATFORM_INFO_CPUID_FAULT;
12226 	kvm_xen_init_vcpu(vcpu);
12227 	kvm_vcpu_mtrr_init(vcpu);
12228 	vcpu_load(vcpu);
12229 	kvm_set_tsc_khz(vcpu, vcpu->kvm->arch.default_tsc_khz);
12230 	kvm_vcpu_reset(vcpu, false);
12231 	kvm_init_mmu(vcpu);
12232 	vcpu_put(vcpu);
12233 	return 0;
12234 
12235 free_guest_fpu:
12236 	fpu_free_guest_fpstate(&vcpu->arch.guest_fpu);
12237 free_emulate_ctxt:
12238 	kmem_cache_free(x86_emulator_cache, vcpu->arch.emulate_ctxt);
12239 free_wbinvd_dirty_mask:
12240 	free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
12241 fail_free_mce_banks:
12242 	kfree(vcpu->arch.mce_banks);
12243 	kfree(vcpu->arch.mci_ctl2_banks);
12244 	free_page((unsigned long)vcpu->arch.pio_data);
12245 fail_free_lapic:
12246 	kvm_free_lapic(vcpu);
12247 fail_mmu_destroy:
12248 	kvm_mmu_destroy(vcpu);
12249 	return r;
12250 }
12251 
12252 void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
12253 {
12254 	struct kvm *kvm = vcpu->kvm;
12255 
12256 	if (mutex_lock_killable(&vcpu->mutex))
12257 		return;
12258 	vcpu_load(vcpu);
12259 	kvm_synchronize_tsc(vcpu, NULL);
12260 	vcpu_put(vcpu);
12261 
12262 	/* poll control enabled by default */
12263 	vcpu->arch.msr_kvm_poll_control = 1;
12264 
12265 	mutex_unlock(&vcpu->mutex);
12266 
12267 	if (kvmclock_periodic_sync && vcpu->vcpu_idx == 0)
12268 		schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
12269 						KVMCLOCK_SYNC_PERIOD);
12270 }
12271 
12272 void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
12273 {
12274 	int idx;
12275 
12276 	kvmclock_reset(vcpu);
12277 
12278 	static_call(kvm_x86_vcpu_free)(vcpu);
12279 
12280 	kmem_cache_free(x86_emulator_cache, vcpu->arch.emulate_ctxt);
12281 	free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
12282 	fpu_free_guest_fpstate(&vcpu->arch.guest_fpu);
12283 
12284 	kvm_xen_destroy_vcpu(vcpu);
12285 	kvm_hv_vcpu_uninit(vcpu);
12286 	kvm_pmu_destroy(vcpu);
12287 	kfree(vcpu->arch.mce_banks);
12288 	kfree(vcpu->arch.mci_ctl2_banks);
12289 	kvm_free_lapic(vcpu);
12290 	idx = srcu_read_lock(&vcpu->kvm->srcu);
12291 	kvm_mmu_destroy(vcpu);
12292 	srcu_read_unlock(&vcpu->kvm->srcu, idx);
12293 	free_page((unsigned long)vcpu->arch.pio_data);
12294 	kvfree(vcpu->arch.cpuid_entries);
12295 }
12296 
12297 void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
12298 {
12299 	struct kvm_cpuid_entry2 *cpuid_0x1;
12300 	unsigned long old_cr0 = kvm_read_cr0(vcpu);
12301 	unsigned long new_cr0;
12302 
12303 	/*
12304 	 * Several of the "set" flows, e.g. ->set_cr0(), read other registers
12305 	 * to handle side effects.  RESET emulation hits those flows and relies
12306 	 * on emulated/virtualized registers, including those that are loaded
12307 	 * into hardware, to be zeroed at vCPU creation.  Use CRs as a sentinel
12308 	 * to detect improper or missing initialization.
12309 	 */
12310 	WARN_ON_ONCE(!init_event &&
12311 		     (old_cr0 || kvm_read_cr3(vcpu) || kvm_read_cr4(vcpu)));
12312 
12313 	/*
12314 	 * SVM doesn't unconditionally VM-Exit on INIT and SHUTDOWN, thus it's
12315 	 * possible to INIT the vCPU while L2 is active.  Force the vCPU back
12316 	 * into L1 as EFER.SVME is cleared on INIT (along with all other EFER
12317 	 * bits), i.e. virtualization is disabled.
12318 	 */
12319 	if (is_guest_mode(vcpu))
12320 		kvm_leave_nested(vcpu);
12321 
12322 	kvm_lapic_reset(vcpu, init_event);
12323 
12324 	WARN_ON_ONCE(is_guest_mode(vcpu) || is_smm(vcpu));
12325 	vcpu->arch.hflags = 0;
12326 
12327 	vcpu->arch.smi_pending = 0;
12328 	vcpu->arch.smi_count = 0;
12329 	atomic_set(&vcpu->arch.nmi_queued, 0);
12330 	vcpu->arch.nmi_pending = 0;
12331 	vcpu->arch.nmi_injected = false;
12332 	kvm_clear_interrupt_queue(vcpu);
12333 	kvm_clear_exception_queue(vcpu);
12334 
12335 	memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
12336 	kvm_update_dr0123(vcpu);
12337 	vcpu->arch.dr6 = DR6_ACTIVE_LOW;
12338 	vcpu->arch.dr7 = DR7_FIXED_1;
12339 	kvm_update_dr7(vcpu);
12340 
12341 	vcpu->arch.cr2 = 0;
12342 
12343 	kvm_make_request(KVM_REQ_EVENT, vcpu);
12344 	vcpu->arch.apf.msr_en_val = 0;
12345 	vcpu->arch.apf.msr_int_val = 0;
12346 	vcpu->arch.st.msr_val = 0;
12347 
12348 	kvmclock_reset(vcpu);
12349 
12350 	kvm_clear_async_pf_completion_queue(vcpu);
12351 	kvm_async_pf_hash_reset(vcpu);
12352 	vcpu->arch.apf.halted = false;
12353 
12354 	if (vcpu->arch.guest_fpu.fpstate && kvm_mpx_supported()) {
12355 		struct fpstate *fpstate = vcpu->arch.guest_fpu.fpstate;
12356 
12357 		/*
12358 		 * All paths that lead to INIT are required to load the guest's
12359 		 * FPU state (because most paths are buried in KVM_RUN).
12360 		 */
12361 		if (init_event)
12362 			kvm_put_guest_fpu(vcpu);
12363 
12364 		fpstate_clear_xstate_component(fpstate, XFEATURE_BNDREGS);
12365 		fpstate_clear_xstate_component(fpstate, XFEATURE_BNDCSR);
12366 
12367 		if (init_event)
12368 			kvm_load_guest_fpu(vcpu);
12369 	}
12370 
12371 	if (!init_event) {
12372 		vcpu->arch.smbase = 0x30000;
12373 
12374 		vcpu->arch.msr_misc_features_enables = 0;
12375 		vcpu->arch.ia32_misc_enable_msr = MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL |
12376 						  MSR_IA32_MISC_ENABLE_BTS_UNAVAIL;
12377 
12378 		__kvm_set_xcr(vcpu, 0, XFEATURE_MASK_FP);
12379 		__kvm_set_msr(vcpu, MSR_IA32_XSS, 0, true);
12380 	}
12381 
12382 	/* All GPRs except RDX (handled below) are zeroed on RESET/INIT. */
12383 	memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs));
12384 	kvm_register_mark_dirty(vcpu, VCPU_REGS_RSP);
12385 
12386 	/*
12387 	 * Fall back to KVM's default Family/Model/Stepping of 0x600 (P6/Athlon)
12388 	 * if no CPUID match is found.  Note, it's impossible to get a match at
12389 	 * RESET since KVM emulates RESET before exposing the vCPU to userspace,
12390 	 * i.e. it's impossible for kvm_find_cpuid_entry() to find a valid entry
12391 	 * on RESET.  But, go through the motions in case that's ever remedied.
12392 	 */
12393 	cpuid_0x1 = kvm_find_cpuid_entry(vcpu, 1);
12394 	kvm_rdx_write(vcpu, cpuid_0x1 ? cpuid_0x1->eax : 0x600);
12395 
12396 	static_call(kvm_x86_vcpu_reset)(vcpu, init_event);
12397 
12398 	kvm_set_rflags(vcpu, X86_EFLAGS_FIXED);
12399 	kvm_rip_write(vcpu, 0xfff0);
12400 
12401 	vcpu->arch.cr3 = 0;
12402 	kvm_register_mark_dirty(vcpu, VCPU_EXREG_CR3);
12403 
12404 	/*
12405 	 * CR0.CD/NW are set on RESET, preserved on INIT.  Note, some versions
12406 	 * of Intel's SDM list CD/NW as being set on INIT, but they contradict
12407 	 * (or qualify) that with a footnote stating that CD/NW are preserved.
12408 	 */
12409 	new_cr0 = X86_CR0_ET;
12410 	if (init_event)
12411 		new_cr0 |= (old_cr0 & (X86_CR0_NW | X86_CR0_CD));
12412 	else
12413 		new_cr0 |= X86_CR0_NW | X86_CR0_CD;
12414 
12415 	static_call(kvm_x86_set_cr0)(vcpu, new_cr0);
12416 	static_call(kvm_x86_set_cr4)(vcpu, 0);
12417 	static_call(kvm_x86_set_efer)(vcpu, 0);
12418 	static_call(kvm_x86_update_exception_bitmap)(vcpu);
12419 
12420 	/*
12421 	 * On the standard CR0/CR4/EFER modification paths, there are several
12422 	 * complex conditions determining whether the MMU has to be reset and/or
12423 	 * which PCIDs have to be flushed.  However, CR0.WP and the paging-related
12424 	 * bits in CR4 and EFER are irrelevant if CR0.PG was '0'; and a reset+flush
12425 	 * is needed anyway if CR0.PG was '1' (which can only happen for INIT, as
12426 	 * CR0 will be '0' prior to RESET).  So we only need to check CR0.PG here.
12427 	 */
12428 	if (old_cr0 & X86_CR0_PG) {
12429 		kvm_make_request(KVM_REQ_TLB_FLUSH_GUEST, vcpu);
12430 		kvm_mmu_reset_context(vcpu);
12431 	}
12432 
12433 	/*
12434 	 * Intel's SDM states that all TLB entries are flushed on INIT.  AMD's
12435 	 * APM states the TLBs are untouched by INIT, but it also states that
12436 	 * the TLBs are flushed on "External initialization of the processor."
12437 	 * Flush the guest TLB regardless of vendor, there is no meaningful
12438 	 * benefit in relying on the guest to flush the TLB immediately after
12439 	 * INIT.  A spurious TLB flush is benign and likely negligible from a
12440 	 * performance perspective.
12441 	 */
12442 	if (init_event)
12443 		kvm_make_request(KVM_REQ_TLB_FLUSH_GUEST, vcpu);
12444 }
12445 EXPORT_SYMBOL_GPL(kvm_vcpu_reset);
12446 
12447 void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector)
12448 {
12449 	struct kvm_segment cs;
12450 
12451 	kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
12452 	cs.selector = vector << 8;
12453 	cs.base = vector << 12;
12454 	kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
12455 	kvm_rip_write(vcpu, 0);
12456 }
12457 EXPORT_SYMBOL_GPL(kvm_vcpu_deliver_sipi_vector);
12458 
12459 int kvm_arch_hardware_enable(void)
12460 {
12461 	struct kvm *kvm;
12462 	struct kvm_vcpu *vcpu;
12463 	unsigned long i;
12464 	int ret;
12465 	u64 local_tsc;
12466 	u64 max_tsc = 0;
12467 	bool stable, backwards_tsc = false;
12468 
12469 	kvm_user_return_msr_cpu_online();
12470 
12471 	ret = kvm_x86_check_processor_compatibility();
12472 	if (ret)
12473 		return ret;
12474 
12475 	ret = static_call(kvm_x86_hardware_enable)();
12476 	if (ret != 0)
12477 		return ret;
12478 
12479 	local_tsc = rdtsc();
12480 	stable = !kvm_check_tsc_unstable();
12481 	list_for_each_entry(kvm, &vm_list, vm_list) {
12482 		kvm_for_each_vcpu(i, vcpu, kvm) {
12483 			if (!stable && vcpu->cpu == smp_processor_id())
12484 				kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
12485 			if (stable && vcpu->arch.last_host_tsc > local_tsc) {
12486 				backwards_tsc = true;
12487 				if (vcpu->arch.last_host_tsc > max_tsc)
12488 					max_tsc = vcpu->arch.last_host_tsc;
12489 			}
12490 		}
12491 	}
12492 
12493 	/*
12494 	 * Sometimes, even reliable TSCs go backwards.  This happens on
12495 	 * platforms that reset TSC during suspend or hibernate actions, but
12496 	 * maintain synchronization.  We must compensate.  Fortunately, we can
12497 	 * detect that condition here, which happens early in CPU bringup,
12498 	 * before any KVM threads can be running.  Unfortunately, we can't
12499 	 * bring the TSCs fully up to date with real time, as we aren't yet far
12500 	 * enough into CPU bringup that we know how much real time has actually
12501 	 * elapsed; our helper function, ktime_get_boottime_ns() will be using boot
12502 	 * variables that haven't been updated yet.
12503 	 *
12504 	 * So we simply find the maximum observed TSC above, then record the
12505 	 * adjustment to TSC in each VCPU.  When the VCPU later gets loaded,
12506 	 * the adjustment will be applied.  Note that we accumulate
12507 	 * adjustments, in case multiple suspend cycles happen before some VCPU
12508 	 * gets a chance to run again.  In the event that no KVM threads get a
12509 	 * chance to run, we will miss the entire elapsed period, as we'll have
12510 	 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
12511 	 * loose cycle time.  This isn't too big a deal, since the loss will be
12512 	 * uniform across all VCPUs (not to mention the scenario is extremely
12513 	 * unlikely). It is possible that a second hibernate recovery happens
12514 	 * much faster than a first, causing the observed TSC here to be
12515 	 * smaller; this would require additional padding adjustment, which is
12516 	 * why we set last_host_tsc to the local tsc observed here.
12517 	 *
12518 	 * N.B. - this code below runs only on platforms with reliable TSC,
12519 	 * as that is the only way backwards_tsc is set above.  Also note
12520 	 * that this runs for ALL vcpus, which is not a bug; all VCPUs should
12521 	 * have the same delta_cyc adjustment applied if backwards_tsc
12522 	 * is detected.  Note further, this adjustment is only done once,
12523 	 * as we reset last_host_tsc on all VCPUs to stop this from being
12524 	 * called multiple times (one for each physical CPU bringup).
12525 	 *
12526 	 * Platforms with unreliable TSCs don't have to deal with this, they
12527 	 * will be compensated by the logic in vcpu_load, which sets the TSC to
12528 	 * catchup mode.  This will catchup all VCPUs to real time, but cannot
12529 	 * guarantee that they stay in perfect synchronization.
12530 	 */
12531 	if (backwards_tsc) {
12532 		u64 delta_cyc = max_tsc - local_tsc;
12533 		list_for_each_entry(kvm, &vm_list, vm_list) {
12534 			kvm->arch.backwards_tsc_observed = true;
12535 			kvm_for_each_vcpu(i, vcpu, kvm) {
12536 				vcpu->arch.tsc_offset_adjustment += delta_cyc;
12537 				vcpu->arch.last_host_tsc = local_tsc;
12538 				kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
12539 			}
12540 
12541 			/*
12542 			 * We have to disable TSC offset matching.. if you were
12543 			 * booting a VM while issuing an S4 host suspend....
12544 			 * you may have some problem.  Solving this issue is
12545 			 * left as an exercise to the reader.
12546 			 */
12547 			kvm->arch.last_tsc_nsec = 0;
12548 			kvm->arch.last_tsc_write = 0;
12549 		}
12550 
12551 	}
12552 	return 0;
12553 }
12554 
12555 void kvm_arch_hardware_disable(void)
12556 {
12557 	static_call(kvm_x86_hardware_disable)();
12558 	drop_user_return_notifiers();
12559 }
12560 
12561 bool kvm_vcpu_is_reset_bsp(struct kvm_vcpu *vcpu)
12562 {
12563 	return vcpu->kvm->arch.bsp_vcpu_id == vcpu->vcpu_id;
12564 }
12565 
12566 bool kvm_vcpu_is_bsp(struct kvm_vcpu *vcpu)
12567 {
12568 	return (vcpu->arch.apic_base & MSR_IA32_APICBASE_BSP) != 0;
12569 }
12570 
12571 void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu)
12572 {
12573 	struct kvm_pmu *pmu = vcpu_to_pmu(vcpu);
12574 
12575 	vcpu->arch.l1tf_flush_l1d = true;
12576 	if (pmu->version && unlikely(pmu->event_count)) {
12577 		pmu->need_cleanup = true;
12578 		kvm_make_request(KVM_REQ_PMU, vcpu);
12579 	}
12580 	static_call(kvm_x86_sched_in)(vcpu, cpu);
12581 }
12582 
12583 void kvm_arch_free_vm(struct kvm *kvm)
12584 {
12585 #if IS_ENABLED(CONFIG_HYPERV)
12586 	kfree(kvm->arch.hv_pa_pg);
12587 #endif
12588 	__kvm_arch_free_vm(kvm);
12589 }
12590 
12591 
12592 int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
12593 {
12594 	int ret;
12595 	unsigned long flags;
12596 
12597 	if (!kvm_is_vm_type_supported(type))
12598 		return -EINVAL;
12599 
12600 	kvm->arch.vm_type = type;
12601 	kvm->arch.has_private_mem =
12602 		(type == KVM_X86_SW_PROTECTED_VM);
12603 
12604 	ret = kvm_page_track_init(kvm);
12605 	if (ret)
12606 		goto out;
12607 
12608 	kvm_mmu_init_vm(kvm);
12609 
12610 	ret = static_call(kvm_x86_vm_init)(kvm);
12611 	if (ret)
12612 		goto out_uninit_mmu;
12613 
12614 	INIT_HLIST_HEAD(&kvm->arch.mask_notifier_list);
12615 	atomic_set(&kvm->arch.noncoherent_dma_count, 0);
12616 
12617 	/* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
12618 	set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
12619 	/* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */
12620 	set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID,
12621 		&kvm->arch.irq_sources_bitmap);
12622 
12623 	raw_spin_lock_init(&kvm->arch.tsc_write_lock);
12624 	mutex_init(&kvm->arch.apic_map_lock);
12625 	seqcount_raw_spinlock_init(&kvm->arch.pvclock_sc, &kvm->arch.tsc_write_lock);
12626 	kvm->arch.kvmclock_offset = -get_kvmclock_base_ns();
12627 
12628 	raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
12629 	pvclock_update_vm_gtod_copy(kvm);
12630 	raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
12631 
12632 	kvm->arch.default_tsc_khz = max_tsc_khz ? : tsc_khz;
12633 	kvm->arch.guest_can_read_msr_platform_info = true;
12634 	kvm->arch.enable_pmu = enable_pmu;
12635 
12636 #if IS_ENABLED(CONFIG_HYPERV)
12637 	spin_lock_init(&kvm->arch.hv_root_tdp_lock);
12638 	kvm->arch.hv_root_tdp = INVALID_PAGE;
12639 #endif
12640 
12641 	INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn);
12642 	INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn);
12643 
12644 	kvm_apicv_init(kvm);
12645 	kvm_hv_init_vm(kvm);
12646 	kvm_xen_init_vm(kvm);
12647 
12648 	return 0;
12649 
12650 out_uninit_mmu:
12651 	kvm_mmu_uninit_vm(kvm);
12652 	kvm_page_track_cleanup(kvm);
12653 out:
12654 	return ret;
12655 }
12656 
12657 int kvm_arch_post_init_vm(struct kvm *kvm)
12658 {
12659 	return kvm_mmu_post_init_vm(kvm);
12660 }
12661 
12662 static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
12663 {
12664 	vcpu_load(vcpu);
12665 	kvm_mmu_unload(vcpu);
12666 	vcpu_put(vcpu);
12667 }
12668 
12669 static void kvm_unload_vcpu_mmus(struct kvm *kvm)
12670 {
12671 	unsigned long i;
12672 	struct kvm_vcpu *vcpu;
12673 
12674 	kvm_for_each_vcpu(i, vcpu, kvm) {
12675 		kvm_clear_async_pf_completion_queue(vcpu);
12676 		kvm_unload_vcpu_mmu(vcpu);
12677 	}
12678 }
12679 
12680 void kvm_arch_sync_events(struct kvm *kvm)
12681 {
12682 	cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work);
12683 	cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work);
12684 	kvm_free_pit(kvm);
12685 }
12686 
12687 /**
12688  * __x86_set_memory_region: Setup KVM internal memory slot
12689  *
12690  * @kvm: the kvm pointer to the VM.
12691  * @id: the slot ID to setup.
12692  * @gpa: the GPA to install the slot (unused when @size == 0).
12693  * @size: the size of the slot. Set to zero to uninstall a slot.
12694  *
12695  * This function helps to setup a KVM internal memory slot.  Specify
12696  * @size > 0 to install a new slot, while @size == 0 to uninstall a
12697  * slot.  The return code can be one of the following:
12698  *
12699  *   HVA:           on success (uninstall will return a bogus HVA)
12700  *   -errno:        on error
12701  *
12702  * The caller should always use IS_ERR() to check the return value
12703  * before use.  Note, the KVM internal memory slots are guaranteed to
12704  * remain valid and unchanged until the VM is destroyed, i.e., the
12705  * GPA->HVA translation will not change.  However, the HVA is a user
12706  * address, i.e. its accessibility is not guaranteed, and must be
12707  * accessed via __copy_{to,from}_user().
12708  */
12709 void __user * __x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa,
12710 				      u32 size)
12711 {
12712 	int i, r;
12713 	unsigned long hva, old_npages;
12714 	struct kvm_memslots *slots = kvm_memslots(kvm);
12715 	struct kvm_memory_slot *slot;
12716 
12717 	/* Called with kvm->slots_lock held.  */
12718 	if (WARN_ON(id >= KVM_MEM_SLOTS_NUM))
12719 		return ERR_PTR_USR(-EINVAL);
12720 
12721 	slot = id_to_memslot(slots, id);
12722 	if (size) {
12723 		if (slot && slot->npages)
12724 			return ERR_PTR_USR(-EEXIST);
12725 
12726 		/*
12727 		 * MAP_SHARED to prevent internal slot pages from being moved
12728 		 * by fork()/COW.
12729 		 */
12730 		hva = vm_mmap(NULL, 0, size, PROT_READ | PROT_WRITE,
12731 			      MAP_SHARED | MAP_ANONYMOUS, 0);
12732 		if (IS_ERR_VALUE(hva))
12733 			return (void __user *)hva;
12734 	} else {
12735 		if (!slot || !slot->npages)
12736 			return NULL;
12737 
12738 		old_npages = slot->npages;
12739 		hva = slot->userspace_addr;
12740 	}
12741 
12742 	for (i = 0; i < kvm_arch_nr_memslot_as_ids(kvm); i++) {
12743 		struct kvm_userspace_memory_region2 m;
12744 
12745 		m.slot = id | (i << 16);
12746 		m.flags = 0;
12747 		m.guest_phys_addr = gpa;
12748 		m.userspace_addr = hva;
12749 		m.memory_size = size;
12750 		r = __kvm_set_memory_region(kvm, &m);
12751 		if (r < 0)
12752 			return ERR_PTR_USR(r);
12753 	}
12754 
12755 	if (!size)
12756 		vm_munmap(hva, old_npages * PAGE_SIZE);
12757 
12758 	return (void __user *)hva;
12759 }
12760 EXPORT_SYMBOL_GPL(__x86_set_memory_region);
12761 
12762 void kvm_arch_pre_destroy_vm(struct kvm *kvm)
12763 {
12764 	kvm_mmu_pre_destroy_vm(kvm);
12765 }
12766 
12767 void kvm_arch_destroy_vm(struct kvm *kvm)
12768 {
12769 	if (current->mm == kvm->mm) {
12770 		/*
12771 		 * Free memory regions allocated on behalf of userspace,
12772 		 * unless the memory map has changed due to process exit
12773 		 * or fd copying.
12774 		 */
12775 		mutex_lock(&kvm->slots_lock);
12776 		__x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT,
12777 					0, 0);
12778 		__x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT,
12779 					0, 0);
12780 		__x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, 0, 0);
12781 		mutex_unlock(&kvm->slots_lock);
12782 	}
12783 	kvm_unload_vcpu_mmus(kvm);
12784 	static_call_cond(kvm_x86_vm_destroy)(kvm);
12785 	kvm_free_msr_filter(srcu_dereference_check(kvm->arch.msr_filter, &kvm->srcu, 1));
12786 	kvm_pic_destroy(kvm);
12787 	kvm_ioapic_destroy(kvm);
12788 	kvm_destroy_vcpus(kvm);
12789 	kvfree(rcu_dereference_check(kvm->arch.apic_map, 1));
12790 	kfree(srcu_dereference_check(kvm->arch.pmu_event_filter, &kvm->srcu, 1));
12791 	kvm_mmu_uninit_vm(kvm);
12792 	kvm_page_track_cleanup(kvm);
12793 	kvm_xen_destroy_vm(kvm);
12794 	kvm_hv_destroy_vm(kvm);
12795 }
12796 
12797 static void memslot_rmap_free(struct kvm_memory_slot *slot)
12798 {
12799 	int i;
12800 
12801 	for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
12802 		vfree(slot->arch.rmap[i]);
12803 		slot->arch.rmap[i] = NULL;
12804 	}
12805 }
12806 
12807 void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *slot)
12808 {
12809 	int i;
12810 
12811 	memslot_rmap_free(slot);
12812 
12813 	for (i = 1; i < KVM_NR_PAGE_SIZES; ++i) {
12814 		vfree(slot->arch.lpage_info[i - 1]);
12815 		slot->arch.lpage_info[i - 1] = NULL;
12816 	}
12817 
12818 	kvm_page_track_free_memslot(slot);
12819 }
12820 
12821 int memslot_rmap_alloc(struct kvm_memory_slot *slot, unsigned long npages)
12822 {
12823 	const int sz = sizeof(*slot->arch.rmap[0]);
12824 	int i;
12825 
12826 	for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
12827 		int level = i + 1;
12828 		int lpages = __kvm_mmu_slot_lpages(slot, npages, level);
12829 
12830 		if (slot->arch.rmap[i])
12831 			continue;
12832 
12833 		slot->arch.rmap[i] = __vcalloc(lpages, sz, GFP_KERNEL_ACCOUNT);
12834 		if (!slot->arch.rmap[i]) {
12835 			memslot_rmap_free(slot);
12836 			return -ENOMEM;
12837 		}
12838 	}
12839 
12840 	return 0;
12841 }
12842 
12843 static int kvm_alloc_memslot_metadata(struct kvm *kvm,
12844 				      struct kvm_memory_slot *slot)
12845 {
12846 	unsigned long npages = slot->npages;
12847 	int i, r;
12848 
12849 	/*
12850 	 * Clear out the previous array pointers for the KVM_MR_MOVE case.  The
12851 	 * old arrays will be freed by __kvm_set_memory_region() if installing
12852 	 * the new memslot is successful.
12853 	 */
12854 	memset(&slot->arch, 0, sizeof(slot->arch));
12855 
12856 	if (kvm_memslots_have_rmaps(kvm)) {
12857 		r = memslot_rmap_alloc(slot, npages);
12858 		if (r)
12859 			return r;
12860 	}
12861 
12862 	for (i = 1; i < KVM_NR_PAGE_SIZES; ++i) {
12863 		struct kvm_lpage_info *linfo;
12864 		unsigned long ugfn;
12865 		int lpages;
12866 		int level = i + 1;
12867 
12868 		lpages = __kvm_mmu_slot_lpages(slot, npages, level);
12869 
12870 		linfo = __vcalloc(lpages, sizeof(*linfo), GFP_KERNEL_ACCOUNT);
12871 		if (!linfo)
12872 			goto out_free;
12873 
12874 		slot->arch.lpage_info[i - 1] = linfo;
12875 
12876 		if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
12877 			linfo[0].disallow_lpage = 1;
12878 		if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
12879 			linfo[lpages - 1].disallow_lpage = 1;
12880 		ugfn = slot->userspace_addr >> PAGE_SHIFT;
12881 		/*
12882 		 * If the gfn and userspace address are not aligned wrt each
12883 		 * other, disable large page support for this slot.
12884 		 */
12885 		if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1)) {
12886 			unsigned long j;
12887 
12888 			for (j = 0; j < lpages; ++j)
12889 				linfo[j].disallow_lpage = 1;
12890 		}
12891 	}
12892 
12893 #ifdef CONFIG_KVM_GENERIC_MEMORY_ATTRIBUTES
12894 	kvm_mmu_init_memslot_memory_attributes(kvm, slot);
12895 #endif
12896 
12897 	if (kvm_page_track_create_memslot(kvm, slot, npages))
12898 		goto out_free;
12899 
12900 	return 0;
12901 
12902 out_free:
12903 	memslot_rmap_free(slot);
12904 
12905 	for (i = 1; i < KVM_NR_PAGE_SIZES; ++i) {
12906 		vfree(slot->arch.lpage_info[i - 1]);
12907 		slot->arch.lpage_info[i - 1] = NULL;
12908 	}
12909 	return -ENOMEM;
12910 }
12911 
12912 void kvm_arch_memslots_updated(struct kvm *kvm, u64 gen)
12913 {
12914 	struct kvm_vcpu *vcpu;
12915 	unsigned long i;
12916 
12917 	/*
12918 	 * memslots->generation has been incremented.
12919 	 * mmio generation may have reached its maximum value.
12920 	 */
12921 	kvm_mmu_invalidate_mmio_sptes(kvm, gen);
12922 
12923 	/* Force re-initialization of steal_time cache */
12924 	kvm_for_each_vcpu(i, vcpu, kvm)
12925 		kvm_vcpu_kick(vcpu);
12926 }
12927 
12928 int kvm_arch_prepare_memory_region(struct kvm *kvm,
12929 				   const struct kvm_memory_slot *old,
12930 				   struct kvm_memory_slot *new,
12931 				   enum kvm_mr_change change)
12932 {
12933 	/*
12934 	 * KVM doesn't support moving memslots when there are external page
12935 	 * trackers attached to the VM, i.e. if KVMGT is in use.
12936 	 */
12937 	if (change == KVM_MR_MOVE && kvm_page_track_has_external_user(kvm))
12938 		return -EINVAL;
12939 
12940 	if (change == KVM_MR_CREATE || change == KVM_MR_MOVE) {
12941 		if ((new->base_gfn + new->npages - 1) > kvm_mmu_max_gfn())
12942 			return -EINVAL;
12943 
12944 		return kvm_alloc_memslot_metadata(kvm, new);
12945 	}
12946 
12947 	if (change == KVM_MR_FLAGS_ONLY)
12948 		memcpy(&new->arch, &old->arch, sizeof(old->arch));
12949 	else if (WARN_ON_ONCE(change != KVM_MR_DELETE))
12950 		return -EIO;
12951 
12952 	return 0;
12953 }
12954 
12955 
12956 static void kvm_mmu_update_cpu_dirty_logging(struct kvm *kvm, bool enable)
12957 {
12958 	int nr_slots;
12959 
12960 	if (!kvm_x86_ops.cpu_dirty_log_size)
12961 		return;
12962 
12963 	nr_slots = atomic_read(&kvm->nr_memslots_dirty_logging);
12964 	if ((enable && nr_slots == 1) || !nr_slots)
12965 		kvm_make_all_cpus_request(kvm, KVM_REQ_UPDATE_CPU_DIRTY_LOGGING);
12966 }
12967 
12968 static void kvm_mmu_slot_apply_flags(struct kvm *kvm,
12969 				     struct kvm_memory_slot *old,
12970 				     const struct kvm_memory_slot *new,
12971 				     enum kvm_mr_change change)
12972 {
12973 	u32 old_flags = old ? old->flags : 0;
12974 	u32 new_flags = new ? new->flags : 0;
12975 	bool log_dirty_pages = new_flags & KVM_MEM_LOG_DIRTY_PAGES;
12976 
12977 	/*
12978 	 * Update CPU dirty logging if dirty logging is being toggled.  This
12979 	 * applies to all operations.
12980 	 */
12981 	if ((old_flags ^ new_flags) & KVM_MEM_LOG_DIRTY_PAGES)
12982 		kvm_mmu_update_cpu_dirty_logging(kvm, log_dirty_pages);
12983 
12984 	/*
12985 	 * Nothing more to do for RO slots (which can't be dirtied and can't be
12986 	 * made writable) or CREATE/MOVE/DELETE of a slot.
12987 	 *
12988 	 * For a memslot with dirty logging disabled:
12989 	 * CREATE:      No dirty mappings will already exist.
12990 	 * MOVE/DELETE: The old mappings will already have been cleaned up by
12991 	 *		kvm_arch_flush_shadow_memslot()
12992 	 *
12993 	 * For a memslot with dirty logging enabled:
12994 	 * CREATE:      No shadow pages exist, thus nothing to write-protect
12995 	 *		and no dirty bits to clear.
12996 	 * MOVE/DELETE: The old mappings will already have been cleaned up by
12997 	 *		kvm_arch_flush_shadow_memslot().
12998 	 */
12999 	if ((change != KVM_MR_FLAGS_ONLY) || (new_flags & KVM_MEM_READONLY))
13000 		return;
13001 
13002 	/*
13003 	 * READONLY and non-flags changes were filtered out above, and the only
13004 	 * other flag is LOG_DIRTY_PAGES, i.e. something is wrong if dirty
13005 	 * logging isn't being toggled on or off.
13006 	 */
13007 	if (WARN_ON_ONCE(!((old_flags ^ new_flags) & KVM_MEM_LOG_DIRTY_PAGES)))
13008 		return;
13009 
13010 	if (!log_dirty_pages) {
13011 		/*
13012 		 * Dirty logging tracks sptes in 4k granularity, meaning that
13013 		 * large sptes have to be split.  If live migration succeeds,
13014 		 * the guest in the source machine will be destroyed and large
13015 		 * sptes will be created in the destination.  However, if the
13016 		 * guest continues to run in the source machine (for example if
13017 		 * live migration fails), small sptes will remain around and
13018 		 * cause bad performance.
13019 		 *
13020 		 * Scan sptes if dirty logging has been stopped, dropping those
13021 		 * which can be collapsed into a single large-page spte.  Later
13022 		 * page faults will create the large-page sptes.
13023 		 */
13024 		kvm_mmu_zap_collapsible_sptes(kvm, new);
13025 	} else {
13026 		/*
13027 		 * Initially-all-set does not require write protecting any page,
13028 		 * because they're all assumed to be dirty.
13029 		 */
13030 		if (kvm_dirty_log_manual_protect_and_init_set(kvm))
13031 			return;
13032 
13033 		if (READ_ONCE(eager_page_split))
13034 			kvm_mmu_slot_try_split_huge_pages(kvm, new, PG_LEVEL_4K);
13035 
13036 		if (kvm_x86_ops.cpu_dirty_log_size) {
13037 			kvm_mmu_slot_leaf_clear_dirty(kvm, new);
13038 			kvm_mmu_slot_remove_write_access(kvm, new, PG_LEVEL_2M);
13039 		} else {
13040 			kvm_mmu_slot_remove_write_access(kvm, new, PG_LEVEL_4K);
13041 		}
13042 
13043 		/*
13044 		 * Unconditionally flush the TLBs after enabling dirty logging.
13045 		 * A flush is almost always going to be necessary (see below),
13046 		 * and unconditionally flushing allows the helpers to omit
13047 		 * the subtly complex checks when removing write access.
13048 		 *
13049 		 * Do the flush outside of mmu_lock to reduce the amount of
13050 		 * time mmu_lock is held.  Flushing after dropping mmu_lock is
13051 		 * safe as KVM only needs to guarantee the slot is fully
13052 		 * write-protected before returning to userspace, i.e. before
13053 		 * userspace can consume the dirty status.
13054 		 *
13055 		 * Flushing outside of mmu_lock requires KVM to be careful when
13056 		 * making decisions based on writable status of an SPTE, e.g. a
13057 		 * !writable SPTE doesn't guarantee a CPU can't perform writes.
13058 		 *
13059 		 * Specifically, KVM also write-protects guest page tables to
13060 		 * monitor changes when using shadow paging, and must guarantee
13061 		 * no CPUs can write to those page before mmu_lock is dropped.
13062 		 * Because CPUs may have stale TLB entries at this point, a
13063 		 * !writable SPTE doesn't guarantee CPUs can't perform writes.
13064 		 *
13065 		 * KVM also allows making SPTES writable outside of mmu_lock,
13066 		 * e.g. to allow dirty logging without taking mmu_lock.
13067 		 *
13068 		 * To handle these scenarios, KVM uses a separate software-only
13069 		 * bit (MMU-writable) to track if a SPTE is !writable due to
13070 		 * a guest page table being write-protected (KVM clears the
13071 		 * MMU-writable flag when write-protecting for shadow paging).
13072 		 *
13073 		 * The use of MMU-writable is also the primary motivation for
13074 		 * the unconditional flush.  Because KVM must guarantee that a
13075 		 * CPU doesn't contain stale, writable TLB entries for a
13076 		 * !MMU-writable SPTE, KVM must flush if it encounters any
13077 		 * MMU-writable SPTE regardless of whether the actual hardware
13078 		 * writable bit was set.  I.e. KVM is almost guaranteed to need
13079 		 * to flush, while unconditionally flushing allows the "remove
13080 		 * write access" helpers to ignore MMU-writable entirely.
13081 		 *
13082 		 * See is_writable_pte() for more details (the case involving
13083 		 * access-tracked SPTEs is particularly relevant).
13084 		 */
13085 		kvm_flush_remote_tlbs_memslot(kvm, new);
13086 	}
13087 }
13088 
13089 void kvm_arch_commit_memory_region(struct kvm *kvm,
13090 				struct kvm_memory_slot *old,
13091 				const struct kvm_memory_slot *new,
13092 				enum kvm_mr_change change)
13093 {
13094 	if (change == KVM_MR_DELETE)
13095 		kvm_page_track_delete_slot(kvm, old);
13096 
13097 	if (!kvm->arch.n_requested_mmu_pages &&
13098 	    (change == KVM_MR_CREATE || change == KVM_MR_DELETE)) {
13099 		unsigned long nr_mmu_pages;
13100 
13101 		nr_mmu_pages = kvm->nr_memslot_pages / KVM_MEMSLOT_PAGES_TO_MMU_PAGES_RATIO;
13102 		nr_mmu_pages = max(nr_mmu_pages, KVM_MIN_ALLOC_MMU_PAGES);
13103 		kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
13104 	}
13105 
13106 	kvm_mmu_slot_apply_flags(kvm, old, new, change);
13107 
13108 	/* Free the arrays associated with the old memslot. */
13109 	if (change == KVM_MR_MOVE)
13110 		kvm_arch_free_memslot(kvm, old);
13111 }
13112 
13113 static inline bool kvm_guest_apic_has_interrupt(struct kvm_vcpu *vcpu)
13114 {
13115 	return (is_guest_mode(vcpu) &&
13116 		static_call(kvm_x86_guest_apic_has_interrupt)(vcpu));
13117 }
13118 
13119 static inline bool kvm_vcpu_has_events(struct kvm_vcpu *vcpu)
13120 {
13121 	if (!list_empty_careful(&vcpu->async_pf.done))
13122 		return true;
13123 
13124 	if (kvm_apic_has_pending_init_or_sipi(vcpu) &&
13125 	    kvm_apic_init_sipi_allowed(vcpu))
13126 		return true;
13127 
13128 	if (vcpu->arch.pv.pv_unhalted)
13129 		return true;
13130 
13131 	if (kvm_is_exception_pending(vcpu))
13132 		return true;
13133 
13134 	if (kvm_test_request(KVM_REQ_NMI, vcpu) ||
13135 	    (vcpu->arch.nmi_pending &&
13136 	     static_call(kvm_x86_nmi_allowed)(vcpu, false)))
13137 		return true;
13138 
13139 #ifdef CONFIG_KVM_SMM
13140 	if (kvm_test_request(KVM_REQ_SMI, vcpu) ||
13141 	    (vcpu->arch.smi_pending &&
13142 	     static_call(kvm_x86_smi_allowed)(vcpu, false)))
13143 		return true;
13144 #endif
13145 
13146 	if (kvm_test_request(KVM_REQ_PMI, vcpu))
13147 		return true;
13148 
13149 	if (kvm_arch_interrupt_allowed(vcpu) &&
13150 	    (kvm_cpu_has_interrupt(vcpu) ||
13151 	    kvm_guest_apic_has_interrupt(vcpu)))
13152 		return true;
13153 
13154 	if (kvm_hv_has_stimer_pending(vcpu))
13155 		return true;
13156 
13157 	if (is_guest_mode(vcpu) &&
13158 	    kvm_x86_ops.nested_ops->has_events &&
13159 	    kvm_x86_ops.nested_ops->has_events(vcpu))
13160 		return true;
13161 
13162 	if (kvm_xen_has_pending_events(vcpu))
13163 		return true;
13164 
13165 	return false;
13166 }
13167 
13168 int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
13169 {
13170 	return kvm_vcpu_running(vcpu) || kvm_vcpu_has_events(vcpu);
13171 }
13172 
13173 bool kvm_arch_dy_has_pending_interrupt(struct kvm_vcpu *vcpu)
13174 {
13175 	return kvm_vcpu_apicv_active(vcpu) &&
13176 	       static_call(kvm_x86_dy_apicv_has_pending_interrupt)(vcpu);
13177 }
13178 
13179 bool kvm_arch_vcpu_preempted_in_kernel(struct kvm_vcpu *vcpu)
13180 {
13181 	return vcpu->arch.preempted_in_kernel;
13182 }
13183 
13184 bool kvm_arch_dy_runnable(struct kvm_vcpu *vcpu)
13185 {
13186 	if (READ_ONCE(vcpu->arch.pv.pv_unhalted))
13187 		return true;
13188 
13189 	if (kvm_test_request(KVM_REQ_NMI, vcpu) ||
13190 #ifdef CONFIG_KVM_SMM
13191 		kvm_test_request(KVM_REQ_SMI, vcpu) ||
13192 #endif
13193 		 kvm_test_request(KVM_REQ_EVENT, vcpu))
13194 		return true;
13195 
13196 	return kvm_arch_dy_has_pending_interrupt(vcpu);
13197 }
13198 
13199 bool kvm_arch_vcpu_in_kernel(struct kvm_vcpu *vcpu)
13200 {
13201 	if (vcpu->arch.guest_state_protected)
13202 		return true;
13203 
13204 	return static_call(kvm_x86_get_cpl)(vcpu) == 0;
13205 }
13206 
13207 unsigned long kvm_arch_vcpu_get_ip(struct kvm_vcpu *vcpu)
13208 {
13209 	return kvm_rip_read(vcpu);
13210 }
13211 
13212 int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
13213 {
13214 	return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
13215 }
13216 
13217 int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
13218 {
13219 	return static_call(kvm_x86_interrupt_allowed)(vcpu, false);
13220 }
13221 
13222 unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu)
13223 {
13224 	/* Can't read the RIP when guest state is protected, just return 0 */
13225 	if (vcpu->arch.guest_state_protected)
13226 		return 0;
13227 
13228 	if (is_64_bit_mode(vcpu))
13229 		return kvm_rip_read(vcpu);
13230 	return (u32)(get_segment_base(vcpu, VCPU_SREG_CS) +
13231 		     kvm_rip_read(vcpu));
13232 }
13233 EXPORT_SYMBOL_GPL(kvm_get_linear_rip);
13234 
13235 bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
13236 {
13237 	return kvm_get_linear_rip(vcpu) == linear_rip;
13238 }
13239 EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
13240 
13241 unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
13242 {
13243 	unsigned long rflags;
13244 
13245 	rflags = static_call(kvm_x86_get_rflags)(vcpu);
13246 	if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
13247 		rflags &= ~X86_EFLAGS_TF;
13248 	return rflags;
13249 }
13250 EXPORT_SYMBOL_GPL(kvm_get_rflags);
13251 
13252 static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
13253 {
13254 	if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
13255 	    kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
13256 		rflags |= X86_EFLAGS_TF;
13257 	static_call(kvm_x86_set_rflags)(vcpu, rflags);
13258 }
13259 
13260 void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
13261 {
13262 	__kvm_set_rflags(vcpu, rflags);
13263 	kvm_make_request(KVM_REQ_EVENT, vcpu);
13264 }
13265 EXPORT_SYMBOL_GPL(kvm_set_rflags);
13266 
13267 static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
13268 {
13269 	BUILD_BUG_ON(!is_power_of_2(ASYNC_PF_PER_VCPU));
13270 
13271 	return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
13272 }
13273 
13274 static inline u32 kvm_async_pf_next_probe(u32 key)
13275 {
13276 	return (key + 1) & (ASYNC_PF_PER_VCPU - 1);
13277 }
13278 
13279 static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
13280 {
13281 	u32 key = kvm_async_pf_hash_fn(gfn);
13282 
13283 	while (vcpu->arch.apf.gfns[key] != ~0)
13284 		key = kvm_async_pf_next_probe(key);
13285 
13286 	vcpu->arch.apf.gfns[key] = gfn;
13287 }
13288 
13289 static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
13290 {
13291 	int i;
13292 	u32 key = kvm_async_pf_hash_fn(gfn);
13293 
13294 	for (i = 0; i < ASYNC_PF_PER_VCPU &&
13295 		     (vcpu->arch.apf.gfns[key] != gfn &&
13296 		      vcpu->arch.apf.gfns[key] != ~0); i++)
13297 		key = kvm_async_pf_next_probe(key);
13298 
13299 	return key;
13300 }
13301 
13302 bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
13303 {
13304 	return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
13305 }
13306 
13307 static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
13308 {
13309 	u32 i, j, k;
13310 
13311 	i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
13312 
13313 	if (WARN_ON_ONCE(vcpu->arch.apf.gfns[i] != gfn))
13314 		return;
13315 
13316 	while (true) {
13317 		vcpu->arch.apf.gfns[i] = ~0;
13318 		do {
13319 			j = kvm_async_pf_next_probe(j);
13320 			if (vcpu->arch.apf.gfns[j] == ~0)
13321 				return;
13322 			k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
13323 			/*
13324 			 * k lies cyclically in ]i,j]
13325 			 * |    i.k.j |
13326 			 * |....j i.k.| or  |.k..j i...|
13327 			 */
13328 		} while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
13329 		vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
13330 		i = j;
13331 	}
13332 }
13333 
13334 static inline int apf_put_user_notpresent(struct kvm_vcpu *vcpu)
13335 {
13336 	u32 reason = KVM_PV_REASON_PAGE_NOT_PRESENT;
13337 
13338 	return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &reason,
13339 				      sizeof(reason));
13340 }
13341 
13342 static inline int apf_put_user_ready(struct kvm_vcpu *vcpu, u32 token)
13343 {
13344 	unsigned int offset = offsetof(struct kvm_vcpu_pv_apf_data, token);
13345 
13346 	return kvm_write_guest_offset_cached(vcpu->kvm, &vcpu->arch.apf.data,
13347 					     &token, offset, sizeof(token));
13348 }
13349 
13350 static inline bool apf_pageready_slot_free(struct kvm_vcpu *vcpu)
13351 {
13352 	unsigned int offset = offsetof(struct kvm_vcpu_pv_apf_data, token);
13353 	u32 val;
13354 
13355 	if (kvm_read_guest_offset_cached(vcpu->kvm, &vcpu->arch.apf.data,
13356 					 &val, offset, sizeof(val)))
13357 		return false;
13358 
13359 	return !val;
13360 }
13361 
13362 static bool kvm_can_deliver_async_pf(struct kvm_vcpu *vcpu)
13363 {
13364 
13365 	if (!kvm_pv_async_pf_enabled(vcpu))
13366 		return false;
13367 
13368 	if (vcpu->arch.apf.send_user_only &&
13369 	    static_call(kvm_x86_get_cpl)(vcpu) == 0)
13370 		return false;
13371 
13372 	if (is_guest_mode(vcpu)) {
13373 		/*
13374 		 * L1 needs to opt into the special #PF vmexits that are
13375 		 * used to deliver async page faults.
13376 		 */
13377 		return vcpu->arch.apf.delivery_as_pf_vmexit;
13378 	} else {
13379 		/*
13380 		 * Play it safe in case the guest temporarily disables paging.
13381 		 * The real mode IDT in particular is unlikely to have a #PF
13382 		 * exception setup.
13383 		 */
13384 		return is_paging(vcpu);
13385 	}
13386 }
13387 
13388 bool kvm_can_do_async_pf(struct kvm_vcpu *vcpu)
13389 {
13390 	if (unlikely(!lapic_in_kernel(vcpu) ||
13391 		     kvm_event_needs_reinjection(vcpu) ||
13392 		     kvm_is_exception_pending(vcpu)))
13393 		return false;
13394 
13395 	if (kvm_hlt_in_guest(vcpu->kvm) && !kvm_can_deliver_async_pf(vcpu))
13396 		return false;
13397 
13398 	/*
13399 	 * If interrupts are off we cannot even use an artificial
13400 	 * halt state.
13401 	 */
13402 	return kvm_arch_interrupt_allowed(vcpu);
13403 }
13404 
13405 bool kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
13406 				     struct kvm_async_pf *work)
13407 {
13408 	struct x86_exception fault;
13409 
13410 	trace_kvm_async_pf_not_present(work->arch.token, work->cr2_or_gpa);
13411 	kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
13412 
13413 	if (kvm_can_deliver_async_pf(vcpu) &&
13414 	    !apf_put_user_notpresent(vcpu)) {
13415 		fault.vector = PF_VECTOR;
13416 		fault.error_code_valid = true;
13417 		fault.error_code = 0;
13418 		fault.nested_page_fault = false;
13419 		fault.address = work->arch.token;
13420 		fault.async_page_fault = true;
13421 		kvm_inject_page_fault(vcpu, &fault);
13422 		return true;
13423 	} else {
13424 		/*
13425 		 * It is not possible to deliver a paravirtualized asynchronous
13426 		 * page fault, but putting the guest in an artificial halt state
13427 		 * can be beneficial nevertheless: if an interrupt arrives, we
13428 		 * can deliver it timely and perhaps the guest will schedule
13429 		 * another process.  When the instruction that triggered a page
13430 		 * fault is retried, hopefully the page will be ready in the host.
13431 		 */
13432 		kvm_make_request(KVM_REQ_APF_HALT, vcpu);
13433 		return false;
13434 	}
13435 }
13436 
13437 void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
13438 				 struct kvm_async_pf *work)
13439 {
13440 	struct kvm_lapic_irq irq = {
13441 		.delivery_mode = APIC_DM_FIXED,
13442 		.vector = vcpu->arch.apf.vec
13443 	};
13444 
13445 	if (work->wakeup_all)
13446 		work->arch.token = ~0; /* broadcast wakeup */
13447 	else
13448 		kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
13449 	trace_kvm_async_pf_ready(work->arch.token, work->cr2_or_gpa);
13450 
13451 	if ((work->wakeup_all || work->notpresent_injected) &&
13452 	    kvm_pv_async_pf_enabled(vcpu) &&
13453 	    !apf_put_user_ready(vcpu, work->arch.token)) {
13454 		vcpu->arch.apf.pageready_pending = true;
13455 		kvm_apic_set_irq(vcpu, &irq, NULL);
13456 	}
13457 
13458 	vcpu->arch.apf.halted = false;
13459 	vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
13460 }
13461 
13462 void kvm_arch_async_page_present_queued(struct kvm_vcpu *vcpu)
13463 {
13464 	kvm_make_request(KVM_REQ_APF_READY, vcpu);
13465 	if (!vcpu->arch.apf.pageready_pending)
13466 		kvm_vcpu_kick(vcpu);
13467 }
13468 
13469 bool kvm_arch_can_dequeue_async_page_present(struct kvm_vcpu *vcpu)
13470 {
13471 	if (!kvm_pv_async_pf_enabled(vcpu))
13472 		return true;
13473 	else
13474 		return kvm_lapic_enabled(vcpu) && apf_pageready_slot_free(vcpu);
13475 }
13476 
13477 void kvm_arch_start_assignment(struct kvm *kvm)
13478 {
13479 	if (atomic_inc_return(&kvm->arch.assigned_device_count) == 1)
13480 		static_call_cond(kvm_x86_pi_start_assignment)(kvm);
13481 }
13482 EXPORT_SYMBOL_GPL(kvm_arch_start_assignment);
13483 
13484 void kvm_arch_end_assignment(struct kvm *kvm)
13485 {
13486 	atomic_dec(&kvm->arch.assigned_device_count);
13487 }
13488 EXPORT_SYMBOL_GPL(kvm_arch_end_assignment);
13489 
13490 bool noinstr kvm_arch_has_assigned_device(struct kvm *kvm)
13491 {
13492 	return raw_atomic_read(&kvm->arch.assigned_device_count);
13493 }
13494 EXPORT_SYMBOL_GPL(kvm_arch_has_assigned_device);
13495 
13496 static void kvm_noncoherent_dma_assignment_start_or_stop(struct kvm *kvm)
13497 {
13498 	/*
13499 	 * Non-coherent DMA assignment and de-assignment will affect
13500 	 * whether KVM honors guest MTRRs and cause changes in memtypes
13501 	 * in TDP.
13502 	 * So, pass %true unconditionally to indicate non-coherent DMA was,
13503 	 * or will be involved, and that zapping SPTEs might be necessary.
13504 	 */
13505 	if (__kvm_mmu_honors_guest_mtrrs(true))
13506 		kvm_zap_gfn_range(kvm, gpa_to_gfn(0), gpa_to_gfn(~0ULL));
13507 }
13508 
13509 void kvm_arch_register_noncoherent_dma(struct kvm *kvm)
13510 {
13511 	if (atomic_inc_return(&kvm->arch.noncoherent_dma_count) == 1)
13512 		kvm_noncoherent_dma_assignment_start_or_stop(kvm);
13513 }
13514 EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma);
13515 
13516 void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm)
13517 {
13518 	if (!atomic_dec_return(&kvm->arch.noncoherent_dma_count))
13519 		kvm_noncoherent_dma_assignment_start_or_stop(kvm);
13520 }
13521 EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma);
13522 
13523 bool kvm_arch_has_noncoherent_dma(struct kvm *kvm)
13524 {
13525 	return atomic_read(&kvm->arch.noncoherent_dma_count);
13526 }
13527 EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma);
13528 
13529 bool kvm_arch_has_irq_bypass(void)
13530 {
13531 	return enable_apicv && irq_remapping_cap(IRQ_POSTING_CAP);
13532 }
13533 
13534 int kvm_arch_irq_bypass_add_producer(struct irq_bypass_consumer *cons,
13535 				      struct irq_bypass_producer *prod)
13536 {
13537 	struct kvm_kernel_irqfd *irqfd =
13538 		container_of(cons, struct kvm_kernel_irqfd, consumer);
13539 	int ret;
13540 
13541 	irqfd->producer = prod;
13542 	kvm_arch_start_assignment(irqfd->kvm);
13543 	ret = static_call(kvm_x86_pi_update_irte)(irqfd->kvm,
13544 					 prod->irq, irqfd->gsi, 1);
13545 
13546 	if (ret)
13547 		kvm_arch_end_assignment(irqfd->kvm);
13548 
13549 	return ret;
13550 }
13551 
13552 void kvm_arch_irq_bypass_del_producer(struct irq_bypass_consumer *cons,
13553 				      struct irq_bypass_producer *prod)
13554 {
13555 	int ret;
13556 	struct kvm_kernel_irqfd *irqfd =
13557 		container_of(cons, struct kvm_kernel_irqfd, consumer);
13558 
13559 	WARN_ON(irqfd->producer != prod);
13560 	irqfd->producer = NULL;
13561 
13562 	/*
13563 	 * When producer of consumer is unregistered, we change back to
13564 	 * remapped mode, so we can re-use the current implementation
13565 	 * when the irq is masked/disabled or the consumer side (KVM
13566 	 * int this case doesn't want to receive the interrupts.
13567 	*/
13568 	ret = static_call(kvm_x86_pi_update_irte)(irqfd->kvm, prod->irq, irqfd->gsi, 0);
13569 	if (ret)
13570 		printk(KERN_INFO "irq bypass consumer (token %p) unregistration"
13571 		       " fails: %d\n", irqfd->consumer.token, ret);
13572 
13573 	kvm_arch_end_assignment(irqfd->kvm);
13574 }
13575 
13576 int kvm_arch_update_irqfd_routing(struct kvm *kvm, unsigned int host_irq,
13577 				   uint32_t guest_irq, bool set)
13578 {
13579 	return static_call(kvm_x86_pi_update_irte)(kvm, host_irq, guest_irq, set);
13580 }
13581 
13582 bool kvm_arch_irqfd_route_changed(struct kvm_kernel_irq_routing_entry *old,
13583 				  struct kvm_kernel_irq_routing_entry *new)
13584 {
13585 	if (new->type != KVM_IRQ_ROUTING_MSI)
13586 		return true;
13587 
13588 	return !!memcmp(&old->msi, &new->msi, sizeof(new->msi));
13589 }
13590 
13591 bool kvm_vector_hashing_enabled(void)
13592 {
13593 	return vector_hashing;
13594 }
13595 
13596 bool kvm_arch_no_poll(struct kvm_vcpu *vcpu)
13597 {
13598 	return (vcpu->arch.msr_kvm_poll_control & 1) == 0;
13599 }
13600 EXPORT_SYMBOL_GPL(kvm_arch_no_poll);
13601 
13602 
13603 int kvm_spec_ctrl_test_value(u64 value)
13604 {
13605 	/*
13606 	 * test that setting IA32_SPEC_CTRL to given value
13607 	 * is allowed by the host processor
13608 	 */
13609 
13610 	u64 saved_value;
13611 	unsigned long flags;
13612 	int ret = 0;
13613 
13614 	local_irq_save(flags);
13615 
13616 	if (rdmsrl_safe(MSR_IA32_SPEC_CTRL, &saved_value))
13617 		ret = 1;
13618 	else if (wrmsrl_safe(MSR_IA32_SPEC_CTRL, value))
13619 		ret = 1;
13620 	else
13621 		wrmsrl(MSR_IA32_SPEC_CTRL, saved_value);
13622 
13623 	local_irq_restore(flags);
13624 
13625 	return ret;
13626 }
13627 EXPORT_SYMBOL_GPL(kvm_spec_ctrl_test_value);
13628 
13629 void kvm_fixup_and_inject_pf_error(struct kvm_vcpu *vcpu, gva_t gva, u16 error_code)
13630 {
13631 	struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
13632 	struct x86_exception fault;
13633 	u64 access = error_code &
13634 		(PFERR_WRITE_MASK | PFERR_FETCH_MASK | PFERR_USER_MASK);
13635 
13636 	if (!(error_code & PFERR_PRESENT_MASK) ||
13637 	    mmu->gva_to_gpa(vcpu, mmu, gva, access, &fault) != INVALID_GPA) {
13638 		/*
13639 		 * If vcpu->arch.walk_mmu->gva_to_gpa succeeded, the page
13640 		 * tables probably do not match the TLB.  Just proceed
13641 		 * with the error code that the processor gave.
13642 		 */
13643 		fault.vector = PF_VECTOR;
13644 		fault.error_code_valid = true;
13645 		fault.error_code = error_code;
13646 		fault.nested_page_fault = false;
13647 		fault.address = gva;
13648 		fault.async_page_fault = false;
13649 	}
13650 	vcpu->arch.walk_mmu->inject_page_fault(vcpu, &fault);
13651 }
13652 EXPORT_SYMBOL_GPL(kvm_fixup_and_inject_pf_error);
13653 
13654 /*
13655  * Handles kvm_read/write_guest_virt*() result and either injects #PF or returns
13656  * KVM_EXIT_INTERNAL_ERROR for cases not currently handled by KVM. Return value
13657  * indicates whether exit to userspace is needed.
13658  */
13659 int kvm_handle_memory_failure(struct kvm_vcpu *vcpu, int r,
13660 			      struct x86_exception *e)
13661 {
13662 	if (r == X86EMUL_PROPAGATE_FAULT) {
13663 		if (KVM_BUG_ON(!e, vcpu->kvm))
13664 			return -EIO;
13665 
13666 		kvm_inject_emulated_page_fault(vcpu, e);
13667 		return 1;
13668 	}
13669 
13670 	/*
13671 	 * In case kvm_read/write_guest_virt*() failed with X86EMUL_IO_NEEDED
13672 	 * while handling a VMX instruction KVM could've handled the request
13673 	 * correctly by exiting to userspace and performing I/O but there
13674 	 * doesn't seem to be a real use-case behind such requests, just return
13675 	 * KVM_EXIT_INTERNAL_ERROR for now.
13676 	 */
13677 	kvm_prepare_emulation_failure_exit(vcpu);
13678 
13679 	return 0;
13680 }
13681 EXPORT_SYMBOL_GPL(kvm_handle_memory_failure);
13682 
13683 int kvm_handle_invpcid(struct kvm_vcpu *vcpu, unsigned long type, gva_t gva)
13684 {
13685 	bool pcid_enabled;
13686 	struct x86_exception e;
13687 	struct {
13688 		u64 pcid;
13689 		u64 gla;
13690 	} operand;
13691 	int r;
13692 
13693 	r = kvm_read_guest_virt(vcpu, gva, &operand, sizeof(operand), &e);
13694 	if (r != X86EMUL_CONTINUE)
13695 		return kvm_handle_memory_failure(vcpu, r, &e);
13696 
13697 	if (operand.pcid >> 12 != 0) {
13698 		kvm_inject_gp(vcpu, 0);
13699 		return 1;
13700 	}
13701 
13702 	pcid_enabled = kvm_is_cr4_bit_set(vcpu, X86_CR4_PCIDE);
13703 
13704 	switch (type) {
13705 	case INVPCID_TYPE_INDIV_ADDR:
13706 		/*
13707 		 * LAM doesn't apply to addresses that are inputs to TLB
13708 		 * invalidation.
13709 		 */
13710 		if ((!pcid_enabled && (operand.pcid != 0)) ||
13711 		    is_noncanonical_address(operand.gla, vcpu)) {
13712 			kvm_inject_gp(vcpu, 0);
13713 			return 1;
13714 		}
13715 		kvm_mmu_invpcid_gva(vcpu, operand.gla, operand.pcid);
13716 		return kvm_skip_emulated_instruction(vcpu);
13717 
13718 	case INVPCID_TYPE_SINGLE_CTXT:
13719 		if (!pcid_enabled && (operand.pcid != 0)) {
13720 			kvm_inject_gp(vcpu, 0);
13721 			return 1;
13722 		}
13723 
13724 		kvm_invalidate_pcid(vcpu, operand.pcid);
13725 		return kvm_skip_emulated_instruction(vcpu);
13726 
13727 	case INVPCID_TYPE_ALL_NON_GLOBAL:
13728 		/*
13729 		 * Currently, KVM doesn't mark global entries in the shadow
13730 		 * page tables, so a non-global flush just degenerates to a
13731 		 * global flush. If needed, we could optimize this later by
13732 		 * keeping track of global entries in shadow page tables.
13733 		 */
13734 
13735 		fallthrough;
13736 	case INVPCID_TYPE_ALL_INCL_GLOBAL:
13737 		kvm_make_request(KVM_REQ_TLB_FLUSH_GUEST, vcpu);
13738 		return kvm_skip_emulated_instruction(vcpu);
13739 
13740 	default:
13741 		kvm_inject_gp(vcpu, 0);
13742 		return 1;
13743 	}
13744 }
13745 EXPORT_SYMBOL_GPL(kvm_handle_invpcid);
13746 
13747 static int complete_sev_es_emulated_mmio(struct kvm_vcpu *vcpu)
13748 {
13749 	struct kvm_run *run = vcpu->run;
13750 	struct kvm_mmio_fragment *frag;
13751 	unsigned int len;
13752 
13753 	BUG_ON(!vcpu->mmio_needed);
13754 
13755 	/* Complete previous fragment */
13756 	frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
13757 	len = min(8u, frag->len);
13758 	if (!vcpu->mmio_is_write)
13759 		memcpy(frag->data, run->mmio.data, len);
13760 
13761 	if (frag->len <= 8) {
13762 		/* Switch to the next fragment. */
13763 		frag++;
13764 		vcpu->mmio_cur_fragment++;
13765 	} else {
13766 		/* Go forward to the next mmio piece. */
13767 		frag->data += len;
13768 		frag->gpa += len;
13769 		frag->len -= len;
13770 	}
13771 
13772 	if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) {
13773 		vcpu->mmio_needed = 0;
13774 
13775 		// VMG change, at this point, we're always done
13776 		// RIP has already been advanced
13777 		return 1;
13778 	}
13779 
13780 	// More MMIO is needed
13781 	run->mmio.phys_addr = frag->gpa;
13782 	run->mmio.len = min(8u, frag->len);
13783 	run->mmio.is_write = vcpu->mmio_is_write;
13784 	if (run->mmio.is_write)
13785 		memcpy(run->mmio.data, frag->data, min(8u, frag->len));
13786 	run->exit_reason = KVM_EXIT_MMIO;
13787 
13788 	vcpu->arch.complete_userspace_io = complete_sev_es_emulated_mmio;
13789 
13790 	return 0;
13791 }
13792 
13793 int kvm_sev_es_mmio_write(struct kvm_vcpu *vcpu, gpa_t gpa, unsigned int bytes,
13794 			  void *data)
13795 {
13796 	int handled;
13797 	struct kvm_mmio_fragment *frag;
13798 
13799 	if (!data)
13800 		return -EINVAL;
13801 
13802 	handled = write_emultor.read_write_mmio(vcpu, gpa, bytes, data);
13803 	if (handled == bytes)
13804 		return 1;
13805 
13806 	bytes -= handled;
13807 	gpa += handled;
13808 	data += handled;
13809 
13810 	/*TODO: Check if need to increment number of frags */
13811 	frag = vcpu->mmio_fragments;
13812 	vcpu->mmio_nr_fragments = 1;
13813 	frag->len = bytes;
13814 	frag->gpa = gpa;
13815 	frag->data = data;
13816 
13817 	vcpu->mmio_needed = 1;
13818 	vcpu->mmio_cur_fragment = 0;
13819 
13820 	vcpu->run->mmio.phys_addr = gpa;
13821 	vcpu->run->mmio.len = min(8u, frag->len);
13822 	vcpu->run->mmio.is_write = 1;
13823 	memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
13824 	vcpu->run->exit_reason = KVM_EXIT_MMIO;
13825 
13826 	vcpu->arch.complete_userspace_io = complete_sev_es_emulated_mmio;
13827 
13828 	return 0;
13829 }
13830 EXPORT_SYMBOL_GPL(kvm_sev_es_mmio_write);
13831 
13832 int kvm_sev_es_mmio_read(struct kvm_vcpu *vcpu, gpa_t gpa, unsigned int bytes,
13833 			 void *data)
13834 {
13835 	int handled;
13836 	struct kvm_mmio_fragment *frag;
13837 
13838 	if (!data)
13839 		return -EINVAL;
13840 
13841 	handled = read_emultor.read_write_mmio(vcpu, gpa, bytes, data);
13842 	if (handled == bytes)
13843 		return 1;
13844 
13845 	bytes -= handled;
13846 	gpa += handled;
13847 	data += handled;
13848 
13849 	/*TODO: Check if need to increment number of frags */
13850 	frag = vcpu->mmio_fragments;
13851 	vcpu->mmio_nr_fragments = 1;
13852 	frag->len = bytes;
13853 	frag->gpa = gpa;
13854 	frag->data = data;
13855 
13856 	vcpu->mmio_needed = 1;
13857 	vcpu->mmio_cur_fragment = 0;
13858 
13859 	vcpu->run->mmio.phys_addr = gpa;
13860 	vcpu->run->mmio.len = min(8u, frag->len);
13861 	vcpu->run->mmio.is_write = 0;
13862 	vcpu->run->exit_reason = KVM_EXIT_MMIO;
13863 
13864 	vcpu->arch.complete_userspace_io = complete_sev_es_emulated_mmio;
13865 
13866 	return 0;
13867 }
13868 EXPORT_SYMBOL_GPL(kvm_sev_es_mmio_read);
13869 
13870 static void advance_sev_es_emulated_pio(struct kvm_vcpu *vcpu, unsigned count, int size)
13871 {
13872 	vcpu->arch.sev_pio_count -= count;
13873 	vcpu->arch.sev_pio_data += count * size;
13874 }
13875 
13876 static int kvm_sev_es_outs(struct kvm_vcpu *vcpu, unsigned int size,
13877 			   unsigned int port);
13878 
13879 static int complete_sev_es_emulated_outs(struct kvm_vcpu *vcpu)
13880 {
13881 	int size = vcpu->arch.pio.size;
13882 	int port = vcpu->arch.pio.port;
13883 
13884 	vcpu->arch.pio.count = 0;
13885 	if (vcpu->arch.sev_pio_count)
13886 		return kvm_sev_es_outs(vcpu, size, port);
13887 	return 1;
13888 }
13889 
13890 static int kvm_sev_es_outs(struct kvm_vcpu *vcpu, unsigned int size,
13891 			   unsigned int port)
13892 {
13893 	for (;;) {
13894 		unsigned int count =
13895 			min_t(unsigned int, PAGE_SIZE / size, vcpu->arch.sev_pio_count);
13896 		int ret = emulator_pio_out(vcpu, size, port, vcpu->arch.sev_pio_data, count);
13897 
13898 		/* memcpy done already by emulator_pio_out.  */
13899 		advance_sev_es_emulated_pio(vcpu, count, size);
13900 		if (!ret)
13901 			break;
13902 
13903 		/* Emulation done by the kernel.  */
13904 		if (!vcpu->arch.sev_pio_count)
13905 			return 1;
13906 	}
13907 
13908 	vcpu->arch.complete_userspace_io = complete_sev_es_emulated_outs;
13909 	return 0;
13910 }
13911 
13912 static int kvm_sev_es_ins(struct kvm_vcpu *vcpu, unsigned int size,
13913 			  unsigned int port);
13914 
13915 static int complete_sev_es_emulated_ins(struct kvm_vcpu *vcpu)
13916 {
13917 	unsigned count = vcpu->arch.pio.count;
13918 	int size = vcpu->arch.pio.size;
13919 	int port = vcpu->arch.pio.port;
13920 
13921 	complete_emulator_pio_in(vcpu, vcpu->arch.sev_pio_data);
13922 	advance_sev_es_emulated_pio(vcpu, count, size);
13923 	if (vcpu->arch.sev_pio_count)
13924 		return kvm_sev_es_ins(vcpu, size, port);
13925 	return 1;
13926 }
13927 
13928 static int kvm_sev_es_ins(struct kvm_vcpu *vcpu, unsigned int size,
13929 			  unsigned int port)
13930 {
13931 	for (;;) {
13932 		unsigned int count =
13933 			min_t(unsigned int, PAGE_SIZE / size, vcpu->arch.sev_pio_count);
13934 		if (!emulator_pio_in(vcpu, size, port, vcpu->arch.sev_pio_data, count))
13935 			break;
13936 
13937 		/* Emulation done by the kernel.  */
13938 		advance_sev_es_emulated_pio(vcpu, count, size);
13939 		if (!vcpu->arch.sev_pio_count)
13940 			return 1;
13941 	}
13942 
13943 	vcpu->arch.complete_userspace_io = complete_sev_es_emulated_ins;
13944 	return 0;
13945 }
13946 
13947 int kvm_sev_es_string_io(struct kvm_vcpu *vcpu, unsigned int size,
13948 			 unsigned int port, void *data,  unsigned int count,
13949 			 int in)
13950 {
13951 	vcpu->arch.sev_pio_data = data;
13952 	vcpu->arch.sev_pio_count = count;
13953 	return in ? kvm_sev_es_ins(vcpu, size, port)
13954 		  : kvm_sev_es_outs(vcpu, size, port);
13955 }
13956 EXPORT_SYMBOL_GPL(kvm_sev_es_string_io);
13957 
13958 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_entry);
13959 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
13960 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_fast_mmio);
13961 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
13962 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
13963 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
13964 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
13965 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmenter);
13966 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
13967 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
13968 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
13969 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmenter_failed);
13970 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
13971 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
13972 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
13973 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset);
13974 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_ple_window_update);
13975 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pml_full);
13976 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pi_irte_update);
13977 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_unaccelerated_access);
13978 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_incomplete_ipi);
13979 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_ga_log);
13980 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_kick_vcpu_slowpath);
13981 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_doorbell);
13982 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_apicv_accept_irq);
13983 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_vmgexit_enter);
13984 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_vmgexit_exit);
13985 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_vmgexit_msr_protocol_enter);
13986 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_vmgexit_msr_protocol_exit);
13987 
13988 static int __init kvm_x86_init(void)
13989 {
13990 	kvm_mmu_x86_module_init();
13991 	mitigate_smt_rsb &= boot_cpu_has_bug(X86_BUG_SMT_RSB) && cpu_smt_possible();
13992 	return 0;
13993 }
13994 module_init(kvm_x86_init);
13995 
13996 static void __exit kvm_x86_exit(void)
13997 {
13998 	WARN_ON_ONCE(static_branch_unlikely(&kvm_has_noapic_vcpu));
13999 }
14000 module_exit(kvm_x86_exit);
14001