1 /* 2 * Kernel-based Virtual Machine driver for Linux 3 * 4 * derived from drivers/kvm/kvm_main.c 5 * 6 * Copyright (C) 2006 Qumranet, Inc. 7 * Copyright (C) 2008 Qumranet, Inc. 8 * Copyright IBM Corporation, 2008 9 * Copyright 2010 Red Hat, Inc. and/or its affiliates. 10 * 11 * Authors: 12 * Avi Kivity <avi@qumranet.com> 13 * Yaniv Kamay <yaniv@qumranet.com> 14 * Amit Shah <amit.shah@qumranet.com> 15 * Ben-Ami Yassour <benami@il.ibm.com> 16 * 17 * This work is licensed under the terms of the GNU GPL, version 2. See 18 * the COPYING file in the top-level directory. 19 * 20 */ 21 22 #include <linux/kvm_host.h> 23 #include "irq.h" 24 #include "mmu.h" 25 #include "i8254.h" 26 #include "tss.h" 27 #include "kvm_cache_regs.h" 28 #include "x86.h" 29 #include "cpuid.h" 30 #include "assigned-dev.h" 31 #include "pmu.h" 32 #include "hyperv.h" 33 34 #include <linux/clocksource.h> 35 #include <linux/interrupt.h> 36 #include <linux/kvm.h> 37 #include <linux/fs.h> 38 #include <linux/vmalloc.h> 39 #include <linux/module.h> 40 #include <linux/mman.h> 41 #include <linux/highmem.h> 42 #include <linux/iommu.h> 43 #include <linux/intel-iommu.h> 44 #include <linux/cpufreq.h> 45 #include <linux/user-return-notifier.h> 46 #include <linux/srcu.h> 47 #include <linux/slab.h> 48 #include <linux/perf_event.h> 49 #include <linux/uaccess.h> 50 #include <linux/hash.h> 51 #include <linux/pci.h> 52 #include <linux/timekeeper_internal.h> 53 #include <linux/pvclock_gtod.h> 54 #include <trace/events/kvm.h> 55 56 #define CREATE_TRACE_POINTS 57 #include "trace.h" 58 59 #include <asm/debugreg.h> 60 #include <asm/msr.h> 61 #include <asm/desc.h> 62 #include <asm/mce.h> 63 #include <linux/kernel_stat.h> 64 #include <asm/fpu/internal.h> /* Ugh! */ 65 #include <asm/pvclock.h> 66 #include <asm/div64.h> 67 68 #define MAX_IO_MSRS 256 69 #define KVM_MAX_MCE_BANKS 32 70 #define KVM_MCE_CAP_SUPPORTED (MCG_CTL_P | MCG_SER_P) 71 72 #define emul_to_vcpu(ctxt) \ 73 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt) 74 75 /* EFER defaults: 76 * - enable syscall per default because its emulated by KVM 77 * - enable LME and LMA per default on 64 bit KVM 78 */ 79 #ifdef CONFIG_X86_64 80 static 81 u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA)); 82 #else 83 static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE); 84 #endif 85 86 #define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM 87 #define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU 88 89 static void update_cr8_intercept(struct kvm_vcpu *vcpu); 90 static void process_nmi(struct kvm_vcpu *vcpu); 91 static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags); 92 93 struct kvm_x86_ops *kvm_x86_ops; 94 EXPORT_SYMBOL_GPL(kvm_x86_ops); 95 96 static bool ignore_msrs = 0; 97 module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR); 98 99 unsigned int min_timer_period_us = 500; 100 module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR); 101 102 static bool __read_mostly kvmclock_periodic_sync = true; 103 module_param(kvmclock_periodic_sync, bool, S_IRUGO); 104 105 bool kvm_has_tsc_control; 106 EXPORT_SYMBOL_GPL(kvm_has_tsc_control); 107 u32 kvm_max_guest_tsc_khz; 108 EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz); 109 110 /* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */ 111 static u32 tsc_tolerance_ppm = 250; 112 module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR); 113 114 /* lapic timer advance (tscdeadline mode only) in nanoseconds */ 115 unsigned int lapic_timer_advance_ns = 0; 116 module_param(lapic_timer_advance_ns, uint, S_IRUGO | S_IWUSR); 117 118 static bool backwards_tsc_observed = false; 119 120 #define KVM_NR_SHARED_MSRS 16 121 122 struct kvm_shared_msrs_global { 123 int nr; 124 u32 msrs[KVM_NR_SHARED_MSRS]; 125 }; 126 127 struct kvm_shared_msrs { 128 struct user_return_notifier urn; 129 bool registered; 130 struct kvm_shared_msr_values { 131 u64 host; 132 u64 curr; 133 } values[KVM_NR_SHARED_MSRS]; 134 }; 135 136 static struct kvm_shared_msrs_global __read_mostly shared_msrs_global; 137 static struct kvm_shared_msrs __percpu *shared_msrs; 138 139 struct kvm_stats_debugfs_item debugfs_entries[] = { 140 { "pf_fixed", VCPU_STAT(pf_fixed) }, 141 { "pf_guest", VCPU_STAT(pf_guest) }, 142 { "tlb_flush", VCPU_STAT(tlb_flush) }, 143 { "invlpg", VCPU_STAT(invlpg) }, 144 { "exits", VCPU_STAT(exits) }, 145 { "io_exits", VCPU_STAT(io_exits) }, 146 { "mmio_exits", VCPU_STAT(mmio_exits) }, 147 { "signal_exits", VCPU_STAT(signal_exits) }, 148 { "irq_window", VCPU_STAT(irq_window_exits) }, 149 { "nmi_window", VCPU_STAT(nmi_window_exits) }, 150 { "halt_exits", VCPU_STAT(halt_exits) }, 151 { "halt_successful_poll", VCPU_STAT(halt_successful_poll) }, 152 { "halt_attempted_poll", VCPU_STAT(halt_attempted_poll) }, 153 { "halt_wakeup", VCPU_STAT(halt_wakeup) }, 154 { "hypercalls", VCPU_STAT(hypercalls) }, 155 { "request_irq", VCPU_STAT(request_irq_exits) }, 156 { "irq_exits", VCPU_STAT(irq_exits) }, 157 { "host_state_reload", VCPU_STAT(host_state_reload) }, 158 { "efer_reload", VCPU_STAT(efer_reload) }, 159 { "fpu_reload", VCPU_STAT(fpu_reload) }, 160 { "insn_emulation", VCPU_STAT(insn_emulation) }, 161 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) }, 162 { "irq_injections", VCPU_STAT(irq_injections) }, 163 { "nmi_injections", VCPU_STAT(nmi_injections) }, 164 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) }, 165 { "mmu_pte_write", VM_STAT(mmu_pte_write) }, 166 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) }, 167 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) }, 168 { "mmu_flooded", VM_STAT(mmu_flooded) }, 169 { "mmu_recycled", VM_STAT(mmu_recycled) }, 170 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) }, 171 { "mmu_unsync", VM_STAT(mmu_unsync) }, 172 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) }, 173 { "largepages", VM_STAT(lpages) }, 174 { NULL } 175 }; 176 177 u64 __read_mostly host_xcr0; 178 179 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt); 180 181 static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu) 182 { 183 int i; 184 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++) 185 vcpu->arch.apf.gfns[i] = ~0; 186 } 187 188 static void kvm_on_user_return(struct user_return_notifier *urn) 189 { 190 unsigned slot; 191 struct kvm_shared_msrs *locals 192 = container_of(urn, struct kvm_shared_msrs, urn); 193 struct kvm_shared_msr_values *values; 194 195 for (slot = 0; slot < shared_msrs_global.nr; ++slot) { 196 values = &locals->values[slot]; 197 if (values->host != values->curr) { 198 wrmsrl(shared_msrs_global.msrs[slot], values->host); 199 values->curr = values->host; 200 } 201 } 202 locals->registered = false; 203 user_return_notifier_unregister(urn); 204 } 205 206 static void shared_msr_update(unsigned slot, u32 msr) 207 { 208 u64 value; 209 unsigned int cpu = smp_processor_id(); 210 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu); 211 212 /* only read, and nobody should modify it at this time, 213 * so don't need lock */ 214 if (slot >= shared_msrs_global.nr) { 215 printk(KERN_ERR "kvm: invalid MSR slot!"); 216 return; 217 } 218 rdmsrl_safe(msr, &value); 219 smsr->values[slot].host = value; 220 smsr->values[slot].curr = value; 221 } 222 223 void kvm_define_shared_msr(unsigned slot, u32 msr) 224 { 225 BUG_ON(slot >= KVM_NR_SHARED_MSRS); 226 shared_msrs_global.msrs[slot] = msr; 227 if (slot >= shared_msrs_global.nr) 228 shared_msrs_global.nr = slot + 1; 229 } 230 EXPORT_SYMBOL_GPL(kvm_define_shared_msr); 231 232 static void kvm_shared_msr_cpu_online(void) 233 { 234 unsigned i; 235 236 for (i = 0; i < shared_msrs_global.nr; ++i) 237 shared_msr_update(i, shared_msrs_global.msrs[i]); 238 } 239 240 int kvm_set_shared_msr(unsigned slot, u64 value, u64 mask) 241 { 242 unsigned int cpu = smp_processor_id(); 243 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu); 244 int err; 245 246 if (((value ^ smsr->values[slot].curr) & mask) == 0) 247 return 0; 248 smsr->values[slot].curr = value; 249 err = wrmsrl_safe(shared_msrs_global.msrs[slot], value); 250 if (err) 251 return 1; 252 253 if (!smsr->registered) { 254 smsr->urn.on_user_return = kvm_on_user_return; 255 user_return_notifier_register(&smsr->urn); 256 smsr->registered = true; 257 } 258 return 0; 259 } 260 EXPORT_SYMBOL_GPL(kvm_set_shared_msr); 261 262 static void drop_user_return_notifiers(void) 263 { 264 unsigned int cpu = smp_processor_id(); 265 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu); 266 267 if (smsr->registered) 268 kvm_on_user_return(&smsr->urn); 269 } 270 271 u64 kvm_get_apic_base(struct kvm_vcpu *vcpu) 272 { 273 return vcpu->arch.apic_base; 274 } 275 EXPORT_SYMBOL_GPL(kvm_get_apic_base); 276 277 int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info) 278 { 279 u64 old_state = vcpu->arch.apic_base & 280 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE); 281 u64 new_state = msr_info->data & 282 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE); 283 u64 reserved_bits = ((~0ULL) << cpuid_maxphyaddr(vcpu)) | 284 0x2ff | (guest_cpuid_has_x2apic(vcpu) ? 0 : X2APIC_ENABLE); 285 286 if (!msr_info->host_initiated && 287 ((msr_info->data & reserved_bits) != 0 || 288 new_state == X2APIC_ENABLE || 289 (new_state == MSR_IA32_APICBASE_ENABLE && 290 old_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE)) || 291 (new_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE) && 292 old_state == 0))) 293 return 1; 294 295 kvm_lapic_set_base(vcpu, msr_info->data); 296 return 0; 297 } 298 EXPORT_SYMBOL_GPL(kvm_set_apic_base); 299 300 asmlinkage __visible void kvm_spurious_fault(void) 301 { 302 /* Fault while not rebooting. We want the trace. */ 303 BUG(); 304 } 305 EXPORT_SYMBOL_GPL(kvm_spurious_fault); 306 307 #define EXCPT_BENIGN 0 308 #define EXCPT_CONTRIBUTORY 1 309 #define EXCPT_PF 2 310 311 static int exception_class(int vector) 312 { 313 switch (vector) { 314 case PF_VECTOR: 315 return EXCPT_PF; 316 case DE_VECTOR: 317 case TS_VECTOR: 318 case NP_VECTOR: 319 case SS_VECTOR: 320 case GP_VECTOR: 321 return EXCPT_CONTRIBUTORY; 322 default: 323 break; 324 } 325 return EXCPT_BENIGN; 326 } 327 328 #define EXCPT_FAULT 0 329 #define EXCPT_TRAP 1 330 #define EXCPT_ABORT 2 331 #define EXCPT_INTERRUPT 3 332 333 static int exception_type(int vector) 334 { 335 unsigned int mask; 336 337 if (WARN_ON(vector > 31 || vector == NMI_VECTOR)) 338 return EXCPT_INTERRUPT; 339 340 mask = 1 << vector; 341 342 /* #DB is trap, as instruction watchpoints are handled elsewhere */ 343 if (mask & ((1 << DB_VECTOR) | (1 << BP_VECTOR) | (1 << OF_VECTOR))) 344 return EXCPT_TRAP; 345 346 if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR))) 347 return EXCPT_ABORT; 348 349 /* Reserved exceptions will result in fault */ 350 return EXCPT_FAULT; 351 } 352 353 static void kvm_multiple_exception(struct kvm_vcpu *vcpu, 354 unsigned nr, bool has_error, u32 error_code, 355 bool reinject) 356 { 357 u32 prev_nr; 358 int class1, class2; 359 360 kvm_make_request(KVM_REQ_EVENT, vcpu); 361 362 if (!vcpu->arch.exception.pending) { 363 queue: 364 if (has_error && !is_protmode(vcpu)) 365 has_error = false; 366 vcpu->arch.exception.pending = true; 367 vcpu->arch.exception.has_error_code = has_error; 368 vcpu->arch.exception.nr = nr; 369 vcpu->arch.exception.error_code = error_code; 370 vcpu->arch.exception.reinject = reinject; 371 return; 372 } 373 374 /* to check exception */ 375 prev_nr = vcpu->arch.exception.nr; 376 if (prev_nr == DF_VECTOR) { 377 /* triple fault -> shutdown */ 378 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); 379 return; 380 } 381 class1 = exception_class(prev_nr); 382 class2 = exception_class(nr); 383 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY) 384 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) { 385 /* generate double fault per SDM Table 5-5 */ 386 vcpu->arch.exception.pending = true; 387 vcpu->arch.exception.has_error_code = true; 388 vcpu->arch.exception.nr = DF_VECTOR; 389 vcpu->arch.exception.error_code = 0; 390 } else 391 /* replace previous exception with a new one in a hope 392 that instruction re-execution will regenerate lost 393 exception */ 394 goto queue; 395 } 396 397 void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr) 398 { 399 kvm_multiple_exception(vcpu, nr, false, 0, false); 400 } 401 EXPORT_SYMBOL_GPL(kvm_queue_exception); 402 403 void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr) 404 { 405 kvm_multiple_exception(vcpu, nr, false, 0, true); 406 } 407 EXPORT_SYMBOL_GPL(kvm_requeue_exception); 408 409 void kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err) 410 { 411 if (err) 412 kvm_inject_gp(vcpu, 0); 413 else 414 kvm_x86_ops->skip_emulated_instruction(vcpu); 415 } 416 EXPORT_SYMBOL_GPL(kvm_complete_insn_gp); 417 418 void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault) 419 { 420 ++vcpu->stat.pf_guest; 421 vcpu->arch.cr2 = fault->address; 422 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code); 423 } 424 EXPORT_SYMBOL_GPL(kvm_inject_page_fault); 425 426 static bool kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault) 427 { 428 if (mmu_is_nested(vcpu) && !fault->nested_page_fault) 429 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault); 430 else 431 vcpu->arch.mmu.inject_page_fault(vcpu, fault); 432 433 return fault->nested_page_fault; 434 } 435 436 void kvm_inject_nmi(struct kvm_vcpu *vcpu) 437 { 438 atomic_inc(&vcpu->arch.nmi_queued); 439 kvm_make_request(KVM_REQ_NMI, vcpu); 440 } 441 EXPORT_SYMBOL_GPL(kvm_inject_nmi); 442 443 void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code) 444 { 445 kvm_multiple_exception(vcpu, nr, true, error_code, false); 446 } 447 EXPORT_SYMBOL_GPL(kvm_queue_exception_e); 448 449 void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code) 450 { 451 kvm_multiple_exception(vcpu, nr, true, error_code, true); 452 } 453 EXPORT_SYMBOL_GPL(kvm_requeue_exception_e); 454 455 /* 456 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue 457 * a #GP and return false. 458 */ 459 bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl) 460 { 461 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl) 462 return true; 463 kvm_queue_exception_e(vcpu, GP_VECTOR, 0); 464 return false; 465 } 466 EXPORT_SYMBOL_GPL(kvm_require_cpl); 467 468 bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr) 469 { 470 if ((dr != 4 && dr != 5) || !kvm_read_cr4_bits(vcpu, X86_CR4_DE)) 471 return true; 472 473 kvm_queue_exception(vcpu, UD_VECTOR); 474 return false; 475 } 476 EXPORT_SYMBOL_GPL(kvm_require_dr); 477 478 /* 479 * This function will be used to read from the physical memory of the currently 480 * running guest. The difference to kvm_vcpu_read_guest_page is that this function 481 * can read from guest physical or from the guest's guest physical memory. 482 */ 483 int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, 484 gfn_t ngfn, void *data, int offset, int len, 485 u32 access) 486 { 487 struct x86_exception exception; 488 gfn_t real_gfn; 489 gpa_t ngpa; 490 491 ngpa = gfn_to_gpa(ngfn); 492 real_gfn = mmu->translate_gpa(vcpu, ngpa, access, &exception); 493 if (real_gfn == UNMAPPED_GVA) 494 return -EFAULT; 495 496 real_gfn = gpa_to_gfn(real_gfn); 497 498 return kvm_vcpu_read_guest_page(vcpu, real_gfn, data, offset, len); 499 } 500 EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu); 501 502 static int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn, 503 void *data, int offset, int len, u32 access) 504 { 505 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn, 506 data, offset, len, access); 507 } 508 509 /* 510 * Load the pae pdptrs. Return true is they are all valid. 511 */ 512 int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3) 513 { 514 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT; 515 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2; 516 int i; 517 int ret; 518 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)]; 519 520 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte, 521 offset * sizeof(u64), sizeof(pdpte), 522 PFERR_USER_MASK|PFERR_WRITE_MASK); 523 if (ret < 0) { 524 ret = 0; 525 goto out; 526 } 527 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) { 528 if (is_present_gpte(pdpte[i]) && 529 (pdpte[i] & 530 vcpu->arch.mmu.guest_rsvd_check.rsvd_bits_mask[0][2])) { 531 ret = 0; 532 goto out; 533 } 534 } 535 ret = 1; 536 537 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs)); 538 __set_bit(VCPU_EXREG_PDPTR, 539 (unsigned long *)&vcpu->arch.regs_avail); 540 __set_bit(VCPU_EXREG_PDPTR, 541 (unsigned long *)&vcpu->arch.regs_dirty); 542 out: 543 544 return ret; 545 } 546 EXPORT_SYMBOL_GPL(load_pdptrs); 547 548 static bool pdptrs_changed(struct kvm_vcpu *vcpu) 549 { 550 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)]; 551 bool changed = true; 552 int offset; 553 gfn_t gfn; 554 int r; 555 556 if (is_long_mode(vcpu) || !is_pae(vcpu)) 557 return false; 558 559 if (!test_bit(VCPU_EXREG_PDPTR, 560 (unsigned long *)&vcpu->arch.regs_avail)) 561 return true; 562 563 gfn = (kvm_read_cr3(vcpu) & ~31u) >> PAGE_SHIFT; 564 offset = (kvm_read_cr3(vcpu) & ~31u) & (PAGE_SIZE - 1); 565 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte), 566 PFERR_USER_MASK | PFERR_WRITE_MASK); 567 if (r < 0) 568 goto out; 569 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0; 570 out: 571 572 return changed; 573 } 574 575 int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0) 576 { 577 unsigned long old_cr0 = kvm_read_cr0(vcpu); 578 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP; 579 580 cr0 |= X86_CR0_ET; 581 582 #ifdef CONFIG_X86_64 583 if (cr0 & 0xffffffff00000000UL) 584 return 1; 585 #endif 586 587 cr0 &= ~CR0_RESERVED_BITS; 588 589 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD)) 590 return 1; 591 592 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE)) 593 return 1; 594 595 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) { 596 #ifdef CONFIG_X86_64 597 if ((vcpu->arch.efer & EFER_LME)) { 598 int cs_db, cs_l; 599 600 if (!is_pae(vcpu)) 601 return 1; 602 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l); 603 if (cs_l) 604 return 1; 605 } else 606 #endif 607 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu, 608 kvm_read_cr3(vcpu))) 609 return 1; 610 } 611 612 if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE)) 613 return 1; 614 615 kvm_x86_ops->set_cr0(vcpu, cr0); 616 617 if ((cr0 ^ old_cr0) & X86_CR0_PG) { 618 kvm_clear_async_pf_completion_queue(vcpu); 619 kvm_async_pf_hash_reset(vcpu); 620 } 621 622 if ((cr0 ^ old_cr0) & update_bits) 623 kvm_mmu_reset_context(vcpu); 624 625 if ((cr0 ^ old_cr0) & X86_CR0_CD) 626 kvm_zap_gfn_range(vcpu->kvm, 0, ~0ULL); 627 628 return 0; 629 } 630 EXPORT_SYMBOL_GPL(kvm_set_cr0); 631 632 void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw) 633 { 634 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f)); 635 } 636 EXPORT_SYMBOL_GPL(kvm_lmsw); 637 638 static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu) 639 { 640 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) && 641 !vcpu->guest_xcr0_loaded) { 642 /* kvm_set_xcr() also depends on this */ 643 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0); 644 vcpu->guest_xcr0_loaded = 1; 645 } 646 } 647 648 static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu) 649 { 650 if (vcpu->guest_xcr0_loaded) { 651 if (vcpu->arch.xcr0 != host_xcr0) 652 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0); 653 vcpu->guest_xcr0_loaded = 0; 654 } 655 } 656 657 static int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr) 658 { 659 u64 xcr0 = xcr; 660 u64 old_xcr0 = vcpu->arch.xcr0; 661 u64 valid_bits; 662 663 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */ 664 if (index != XCR_XFEATURE_ENABLED_MASK) 665 return 1; 666 if (!(xcr0 & XSTATE_FP)) 667 return 1; 668 if ((xcr0 & XSTATE_YMM) && !(xcr0 & XSTATE_SSE)) 669 return 1; 670 671 /* 672 * Do not allow the guest to set bits that we do not support 673 * saving. However, xcr0 bit 0 is always set, even if the 674 * emulated CPU does not support XSAVE (see fx_init). 675 */ 676 valid_bits = vcpu->arch.guest_supported_xcr0 | XSTATE_FP; 677 if (xcr0 & ~valid_bits) 678 return 1; 679 680 if ((!(xcr0 & XSTATE_BNDREGS)) != (!(xcr0 & XSTATE_BNDCSR))) 681 return 1; 682 683 if (xcr0 & XSTATE_AVX512) { 684 if (!(xcr0 & XSTATE_YMM)) 685 return 1; 686 if ((xcr0 & XSTATE_AVX512) != XSTATE_AVX512) 687 return 1; 688 } 689 kvm_put_guest_xcr0(vcpu); 690 vcpu->arch.xcr0 = xcr0; 691 692 if ((xcr0 ^ old_xcr0) & XSTATE_EXTEND_MASK) 693 kvm_update_cpuid(vcpu); 694 return 0; 695 } 696 697 int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr) 698 { 699 if (kvm_x86_ops->get_cpl(vcpu) != 0 || 700 __kvm_set_xcr(vcpu, index, xcr)) { 701 kvm_inject_gp(vcpu, 0); 702 return 1; 703 } 704 return 0; 705 } 706 EXPORT_SYMBOL_GPL(kvm_set_xcr); 707 708 int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4) 709 { 710 unsigned long old_cr4 = kvm_read_cr4(vcpu); 711 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE | 712 X86_CR4_SMEP | X86_CR4_SMAP; 713 714 if (cr4 & CR4_RESERVED_BITS) 715 return 1; 716 717 if (!guest_cpuid_has_xsave(vcpu) && (cr4 & X86_CR4_OSXSAVE)) 718 return 1; 719 720 if (!guest_cpuid_has_smep(vcpu) && (cr4 & X86_CR4_SMEP)) 721 return 1; 722 723 if (!guest_cpuid_has_smap(vcpu) && (cr4 & X86_CR4_SMAP)) 724 return 1; 725 726 if (!guest_cpuid_has_fsgsbase(vcpu) && (cr4 & X86_CR4_FSGSBASE)) 727 return 1; 728 729 if (is_long_mode(vcpu)) { 730 if (!(cr4 & X86_CR4_PAE)) 731 return 1; 732 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE) 733 && ((cr4 ^ old_cr4) & pdptr_bits) 734 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu, 735 kvm_read_cr3(vcpu))) 736 return 1; 737 738 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) { 739 if (!guest_cpuid_has_pcid(vcpu)) 740 return 1; 741 742 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */ 743 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu)) 744 return 1; 745 } 746 747 if (kvm_x86_ops->set_cr4(vcpu, cr4)) 748 return 1; 749 750 if (((cr4 ^ old_cr4) & pdptr_bits) || 751 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE))) 752 kvm_mmu_reset_context(vcpu); 753 754 if ((cr4 ^ old_cr4) & X86_CR4_OSXSAVE) 755 kvm_update_cpuid(vcpu); 756 757 return 0; 758 } 759 EXPORT_SYMBOL_GPL(kvm_set_cr4); 760 761 int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3) 762 { 763 #ifdef CONFIG_X86_64 764 cr3 &= ~CR3_PCID_INVD; 765 #endif 766 767 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) { 768 kvm_mmu_sync_roots(vcpu); 769 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu); 770 return 0; 771 } 772 773 if (is_long_mode(vcpu)) { 774 if (cr3 & CR3_L_MODE_RESERVED_BITS) 775 return 1; 776 } else if (is_pae(vcpu) && is_paging(vcpu) && 777 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3)) 778 return 1; 779 780 vcpu->arch.cr3 = cr3; 781 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail); 782 kvm_mmu_new_cr3(vcpu); 783 return 0; 784 } 785 EXPORT_SYMBOL_GPL(kvm_set_cr3); 786 787 int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8) 788 { 789 if (cr8 & CR8_RESERVED_BITS) 790 return 1; 791 if (irqchip_in_kernel(vcpu->kvm)) 792 kvm_lapic_set_tpr(vcpu, cr8); 793 else 794 vcpu->arch.cr8 = cr8; 795 return 0; 796 } 797 EXPORT_SYMBOL_GPL(kvm_set_cr8); 798 799 unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu) 800 { 801 if (irqchip_in_kernel(vcpu->kvm)) 802 return kvm_lapic_get_cr8(vcpu); 803 else 804 return vcpu->arch.cr8; 805 } 806 EXPORT_SYMBOL_GPL(kvm_get_cr8); 807 808 static void kvm_update_dr0123(struct kvm_vcpu *vcpu) 809 { 810 int i; 811 812 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) { 813 for (i = 0; i < KVM_NR_DB_REGS; i++) 814 vcpu->arch.eff_db[i] = vcpu->arch.db[i]; 815 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_RELOAD; 816 } 817 } 818 819 static void kvm_update_dr6(struct kvm_vcpu *vcpu) 820 { 821 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) 822 kvm_x86_ops->set_dr6(vcpu, vcpu->arch.dr6); 823 } 824 825 static void kvm_update_dr7(struct kvm_vcpu *vcpu) 826 { 827 unsigned long dr7; 828 829 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) 830 dr7 = vcpu->arch.guest_debug_dr7; 831 else 832 dr7 = vcpu->arch.dr7; 833 kvm_x86_ops->set_dr7(vcpu, dr7); 834 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED; 835 if (dr7 & DR7_BP_EN_MASK) 836 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED; 837 } 838 839 static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu) 840 { 841 u64 fixed = DR6_FIXED_1; 842 843 if (!guest_cpuid_has_rtm(vcpu)) 844 fixed |= DR6_RTM; 845 return fixed; 846 } 847 848 static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val) 849 { 850 switch (dr) { 851 case 0 ... 3: 852 vcpu->arch.db[dr] = val; 853 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) 854 vcpu->arch.eff_db[dr] = val; 855 break; 856 case 4: 857 /* fall through */ 858 case 6: 859 if (val & 0xffffffff00000000ULL) 860 return -1; /* #GP */ 861 vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu); 862 kvm_update_dr6(vcpu); 863 break; 864 case 5: 865 /* fall through */ 866 default: /* 7 */ 867 if (val & 0xffffffff00000000ULL) 868 return -1; /* #GP */ 869 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1; 870 kvm_update_dr7(vcpu); 871 break; 872 } 873 874 return 0; 875 } 876 877 int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val) 878 { 879 if (__kvm_set_dr(vcpu, dr, val)) { 880 kvm_inject_gp(vcpu, 0); 881 return 1; 882 } 883 return 0; 884 } 885 EXPORT_SYMBOL_GPL(kvm_set_dr); 886 887 int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val) 888 { 889 switch (dr) { 890 case 0 ... 3: 891 *val = vcpu->arch.db[dr]; 892 break; 893 case 4: 894 /* fall through */ 895 case 6: 896 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) 897 *val = vcpu->arch.dr6; 898 else 899 *val = kvm_x86_ops->get_dr6(vcpu); 900 break; 901 case 5: 902 /* fall through */ 903 default: /* 7 */ 904 *val = vcpu->arch.dr7; 905 break; 906 } 907 return 0; 908 } 909 EXPORT_SYMBOL_GPL(kvm_get_dr); 910 911 bool kvm_rdpmc(struct kvm_vcpu *vcpu) 912 { 913 u32 ecx = kvm_register_read(vcpu, VCPU_REGS_RCX); 914 u64 data; 915 int err; 916 917 err = kvm_pmu_rdpmc(vcpu, ecx, &data); 918 if (err) 919 return err; 920 kvm_register_write(vcpu, VCPU_REGS_RAX, (u32)data); 921 kvm_register_write(vcpu, VCPU_REGS_RDX, data >> 32); 922 return err; 923 } 924 EXPORT_SYMBOL_GPL(kvm_rdpmc); 925 926 /* 927 * List of msr numbers which we expose to userspace through KVM_GET_MSRS 928 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST. 929 * 930 * This list is modified at module load time to reflect the 931 * capabilities of the host cpu. This capabilities test skips MSRs that are 932 * kvm-specific. Those are put in emulated_msrs; filtering of emulated_msrs 933 * may depend on host virtualization features rather than host cpu features. 934 */ 935 936 static u32 msrs_to_save[] = { 937 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP, 938 MSR_STAR, 939 #ifdef CONFIG_X86_64 940 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR, 941 #endif 942 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA, 943 MSR_IA32_FEATURE_CONTROL, MSR_IA32_BNDCFGS 944 }; 945 946 static unsigned num_msrs_to_save; 947 948 static u32 emulated_msrs[] = { 949 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK, 950 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW, 951 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL, 952 HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC, 953 HV_X64_MSR_CRASH_P0, HV_X64_MSR_CRASH_P1, HV_X64_MSR_CRASH_P2, 954 HV_X64_MSR_CRASH_P3, HV_X64_MSR_CRASH_P4, HV_X64_MSR_CRASH_CTL, 955 HV_X64_MSR_APIC_ASSIST_PAGE, MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME, 956 MSR_KVM_PV_EOI_EN, 957 958 MSR_IA32_TSC_ADJUST, 959 MSR_IA32_TSCDEADLINE, 960 MSR_IA32_MISC_ENABLE, 961 MSR_IA32_MCG_STATUS, 962 MSR_IA32_MCG_CTL, 963 MSR_IA32_SMBASE, 964 }; 965 966 static unsigned num_emulated_msrs; 967 968 bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer) 969 { 970 if (efer & efer_reserved_bits) 971 return false; 972 973 if (efer & EFER_FFXSR) { 974 struct kvm_cpuid_entry2 *feat; 975 976 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0); 977 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT))) 978 return false; 979 } 980 981 if (efer & EFER_SVME) { 982 struct kvm_cpuid_entry2 *feat; 983 984 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0); 985 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM))) 986 return false; 987 } 988 989 return true; 990 } 991 EXPORT_SYMBOL_GPL(kvm_valid_efer); 992 993 static int set_efer(struct kvm_vcpu *vcpu, u64 efer) 994 { 995 u64 old_efer = vcpu->arch.efer; 996 997 if (!kvm_valid_efer(vcpu, efer)) 998 return 1; 999 1000 if (is_paging(vcpu) 1001 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME)) 1002 return 1; 1003 1004 efer &= ~EFER_LMA; 1005 efer |= vcpu->arch.efer & EFER_LMA; 1006 1007 kvm_x86_ops->set_efer(vcpu, efer); 1008 1009 /* Update reserved bits */ 1010 if ((efer ^ old_efer) & EFER_NX) 1011 kvm_mmu_reset_context(vcpu); 1012 1013 return 0; 1014 } 1015 1016 void kvm_enable_efer_bits(u64 mask) 1017 { 1018 efer_reserved_bits &= ~mask; 1019 } 1020 EXPORT_SYMBOL_GPL(kvm_enable_efer_bits); 1021 1022 /* 1023 * Writes msr value into into the appropriate "register". 1024 * Returns 0 on success, non-0 otherwise. 1025 * Assumes vcpu_load() was already called. 1026 */ 1027 int kvm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr) 1028 { 1029 switch (msr->index) { 1030 case MSR_FS_BASE: 1031 case MSR_GS_BASE: 1032 case MSR_KERNEL_GS_BASE: 1033 case MSR_CSTAR: 1034 case MSR_LSTAR: 1035 if (is_noncanonical_address(msr->data)) 1036 return 1; 1037 break; 1038 case MSR_IA32_SYSENTER_EIP: 1039 case MSR_IA32_SYSENTER_ESP: 1040 /* 1041 * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if 1042 * non-canonical address is written on Intel but not on 1043 * AMD (which ignores the top 32-bits, because it does 1044 * not implement 64-bit SYSENTER). 1045 * 1046 * 64-bit code should hence be able to write a non-canonical 1047 * value on AMD. Making the address canonical ensures that 1048 * vmentry does not fail on Intel after writing a non-canonical 1049 * value, and that something deterministic happens if the guest 1050 * invokes 64-bit SYSENTER. 1051 */ 1052 msr->data = get_canonical(msr->data); 1053 } 1054 return kvm_x86_ops->set_msr(vcpu, msr); 1055 } 1056 EXPORT_SYMBOL_GPL(kvm_set_msr); 1057 1058 /* 1059 * Adapt set_msr() to msr_io()'s calling convention 1060 */ 1061 static int do_get_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data) 1062 { 1063 struct msr_data msr; 1064 int r; 1065 1066 msr.index = index; 1067 msr.host_initiated = true; 1068 r = kvm_get_msr(vcpu, &msr); 1069 if (r) 1070 return r; 1071 1072 *data = msr.data; 1073 return 0; 1074 } 1075 1076 static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data) 1077 { 1078 struct msr_data msr; 1079 1080 msr.data = *data; 1081 msr.index = index; 1082 msr.host_initiated = true; 1083 return kvm_set_msr(vcpu, &msr); 1084 } 1085 1086 #ifdef CONFIG_X86_64 1087 struct pvclock_gtod_data { 1088 seqcount_t seq; 1089 1090 struct { /* extract of a clocksource struct */ 1091 int vclock_mode; 1092 cycle_t cycle_last; 1093 cycle_t mask; 1094 u32 mult; 1095 u32 shift; 1096 } clock; 1097 1098 u64 boot_ns; 1099 u64 nsec_base; 1100 }; 1101 1102 static struct pvclock_gtod_data pvclock_gtod_data; 1103 1104 static void update_pvclock_gtod(struct timekeeper *tk) 1105 { 1106 struct pvclock_gtod_data *vdata = &pvclock_gtod_data; 1107 u64 boot_ns; 1108 1109 boot_ns = ktime_to_ns(ktime_add(tk->tkr_mono.base, tk->offs_boot)); 1110 1111 write_seqcount_begin(&vdata->seq); 1112 1113 /* copy pvclock gtod data */ 1114 vdata->clock.vclock_mode = tk->tkr_mono.clock->archdata.vclock_mode; 1115 vdata->clock.cycle_last = tk->tkr_mono.cycle_last; 1116 vdata->clock.mask = tk->tkr_mono.mask; 1117 vdata->clock.mult = tk->tkr_mono.mult; 1118 vdata->clock.shift = tk->tkr_mono.shift; 1119 1120 vdata->boot_ns = boot_ns; 1121 vdata->nsec_base = tk->tkr_mono.xtime_nsec; 1122 1123 write_seqcount_end(&vdata->seq); 1124 } 1125 #endif 1126 1127 void kvm_set_pending_timer(struct kvm_vcpu *vcpu) 1128 { 1129 /* 1130 * Note: KVM_REQ_PENDING_TIMER is implicitly checked in 1131 * vcpu_enter_guest. This function is only called from 1132 * the physical CPU that is running vcpu. 1133 */ 1134 kvm_make_request(KVM_REQ_PENDING_TIMER, vcpu); 1135 } 1136 1137 static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock) 1138 { 1139 int version; 1140 int r; 1141 struct pvclock_wall_clock wc; 1142 struct timespec boot; 1143 1144 if (!wall_clock) 1145 return; 1146 1147 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version)); 1148 if (r) 1149 return; 1150 1151 if (version & 1) 1152 ++version; /* first time write, random junk */ 1153 1154 ++version; 1155 1156 kvm_write_guest(kvm, wall_clock, &version, sizeof(version)); 1157 1158 /* 1159 * The guest calculates current wall clock time by adding 1160 * system time (updated by kvm_guest_time_update below) to the 1161 * wall clock specified here. guest system time equals host 1162 * system time for us, thus we must fill in host boot time here. 1163 */ 1164 getboottime(&boot); 1165 1166 if (kvm->arch.kvmclock_offset) { 1167 struct timespec ts = ns_to_timespec(kvm->arch.kvmclock_offset); 1168 boot = timespec_sub(boot, ts); 1169 } 1170 wc.sec = boot.tv_sec; 1171 wc.nsec = boot.tv_nsec; 1172 wc.version = version; 1173 1174 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc)); 1175 1176 version++; 1177 kvm_write_guest(kvm, wall_clock, &version, sizeof(version)); 1178 } 1179 1180 static uint32_t div_frac(uint32_t dividend, uint32_t divisor) 1181 { 1182 uint32_t quotient, remainder; 1183 1184 /* Don't try to replace with do_div(), this one calculates 1185 * "(dividend << 32) / divisor" */ 1186 __asm__ ( "divl %4" 1187 : "=a" (quotient), "=d" (remainder) 1188 : "0" (0), "1" (dividend), "r" (divisor) ); 1189 return quotient; 1190 } 1191 1192 static void kvm_get_time_scale(uint32_t scaled_khz, uint32_t base_khz, 1193 s8 *pshift, u32 *pmultiplier) 1194 { 1195 uint64_t scaled64; 1196 int32_t shift = 0; 1197 uint64_t tps64; 1198 uint32_t tps32; 1199 1200 tps64 = base_khz * 1000LL; 1201 scaled64 = scaled_khz * 1000LL; 1202 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) { 1203 tps64 >>= 1; 1204 shift--; 1205 } 1206 1207 tps32 = (uint32_t)tps64; 1208 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) { 1209 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000) 1210 scaled64 >>= 1; 1211 else 1212 tps32 <<= 1; 1213 shift++; 1214 } 1215 1216 *pshift = shift; 1217 *pmultiplier = div_frac(scaled64, tps32); 1218 1219 pr_debug("%s: base_khz %u => %u, shift %d, mul %u\n", 1220 __func__, base_khz, scaled_khz, shift, *pmultiplier); 1221 } 1222 1223 #ifdef CONFIG_X86_64 1224 static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0); 1225 #endif 1226 1227 static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz); 1228 static unsigned long max_tsc_khz; 1229 1230 static inline u64 nsec_to_cycles(struct kvm_vcpu *vcpu, u64 nsec) 1231 { 1232 return pvclock_scale_delta(nsec, vcpu->arch.virtual_tsc_mult, 1233 vcpu->arch.virtual_tsc_shift); 1234 } 1235 1236 static u32 adjust_tsc_khz(u32 khz, s32 ppm) 1237 { 1238 u64 v = (u64)khz * (1000000 + ppm); 1239 do_div(v, 1000000); 1240 return v; 1241 } 1242 1243 static void kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 this_tsc_khz) 1244 { 1245 u32 thresh_lo, thresh_hi; 1246 int use_scaling = 0; 1247 1248 /* tsc_khz can be zero if TSC calibration fails */ 1249 if (this_tsc_khz == 0) 1250 return; 1251 1252 /* Compute a scale to convert nanoseconds in TSC cycles */ 1253 kvm_get_time_scale(this_tsc_khz, NSEC_PER_SEC / 1000, 1254 &vcpu->arch.virtual_tsc_shift, 1255 &vcpu->arch.virtual_tsc_mult); 1256 vcpu->arch.virtual_tsc_khz = this_tsc_khz; 1257 1258 /* 1259 * Compute the variation in TSC rate which is acceptable 1260 * within the range of tolerance and decide if the 1261 * rate being applied is within that bounds of the hardware 1262 * rate. If so, no scaling or compensation need be done. 1263 */ 1264 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm); 1265 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm); 1266 if (this_tsc_khz < thresh_lo || this_tsc_khz > thresh_hi) { 1267 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", this_tsc_khz, thresh_lo, thresh_hi); 1268 use_scaling = 1; 1269 } 1270 kvm_x86_ops->set_tsc_khz(vcpu, this_tsc_khz, use_scaling); 1271 } 1272 1273 static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns) 1274 { 1275 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec, 1276 vcpu->arch.virtual_tsc_mult, 1277 vcpu->arch.virtual_tsc_shift); 1278 tsc += vcpu->arch.this_tsc_write; 1279 return tsc; 1280 } 1281 1282 static void kvm_track_tsc_matching(struct kvm_vcpu *vcpu) 1283 { 1284 #ifdef CONFIG_X86_64 1285 bool vcpus_matched; 1286 struct kvm_arch *ka = &vcpu->kvm->arch; 1287 struct pvclock_gtod_data *gtod = &pvclock_gtod_data; 1288 1289 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 == 1290 atomic_read(&vcpu->kvm->online_vcpus)); 1291 1292 /* 1293 * Once the masterclock is enabled, always perform request in 1294 * order to update it. 1295 * 1296 * In order to enable masterclock, the host clocksource must be TSC 1297 * and the vcpus need to have matched TSCs. When that happens, 1298 * perform request to enable masterclock. 1299 */ 1300 if (ka->use_master_clock || 1301 (gtod->clock.vclock_mode == VCLOCK_TSC && vcpus_matched)) 1302 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu); 1303 1304 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc, 1305 atomic_read(&vcpu->kvm->online_vcpus), 1306 ka->use_master_clock, gtod->clock.vclock_mode); 1307 #endif 1308 } 1309 1310 static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset) 1311 { 1312 u64 curr_offset = kvm_x86_ops->read_tsc_offset(vcpu); 1313 vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset; 1314 } 1315 1316 void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr) 1317 { 1318 struct kvm *kvm = vcpu->kvm; 1319 u64 offset, ns, elapsed; 1320 unsigned long flags; 1321 s64 usdiff; 1322 bool matched; 1323 bool already_matched; 1324 u64 data = msr->data; 1325 1326 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags); 1327 offset = kvm_x86_ops->compute_tsc_offset(vcpu, data); 1328 ns = get_kernel_ns(); 1329 elapsed = ns - kvm->arch.last_tsc_nsec; 1330 1331 if (vcpu->arch.virtual_tsc_khz) { 1332 int faulted = 0; 1333 1334 /* n.b - signed multiplication and division required */ 1335 usdiff = data - kvm->arch.last_tsc_write; 1336 #ifdef CONFIG_X86_64 1337 usdiff = (usdiff * 1000) / vcpu->arch.virtual_tsc_khz; 1338 #else 1339 /* do_div() only does unsigned */ 1340 asm("1: idivl %[divisor]\n" 1341 "2: xor %%edx, %%edx\n" 1342 " movl $0, %[faulted]\n" 1343 "3:\n" 1344 ".section .fixup,\"ax\"\n" 1345 "4: movl $1, %[faulted]\n" 1346 " jmp 3b\n" 1347 ".previous\n" 1348 1349 _ASM_EXTABLE(1b, 4b) 1350 1351 : "=A"(usdiff), [faulted] "=r" (faulted) 1352 : "A"(usdiff * 1000), [divisor] "rm"(vcpu->arch.virtual_tsc_khz)); 1353 1354 #endif 1355 do_div(elapsed, 1000); 1356 usdiff -= elapsed; 1357 if (usdiff < 0) 1358 usdiff = -usdiff; 1359 1360 /* idivl overflow => difference is larger than USEC_PER_SEC */ 1361 if (faulted) 1362 usdiff = USEC_PER_SEC; 1363 } else 1364 usdiff = USEC_PER_SEC; /* disable TSC match window below */ 1365 1366 /* 1367 * Special case: TSC write with a small delta (1 second) of virtual 1368 * cycle time against real time is interpreted as an attempt to 1369 * synchronize the CPU. 1370 * 1371 * For a reliable TSC, we can match TSC offsets, and for an unstable 1372 * TSC, we add elapsed time in this computation. We could let the 1373 * compensation code attempt to catch up if we fall behind, but 1374 * it's better to try to match offsets from the beginning. 1375 */ 1376 if (usdiff < USEC_PER_SEC && 1377 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) { 1378 if (!check_tsc_unstable()) { 1379 offset = kvm->arch.cur_tsc_offset; 1380 pr_debug("kvm: matched tsc offset for %llu\n", data); 1381 } else { 1382 u64 delta = nsec_to_cycles(vcpu, elapsed); 1383 data += delta; 1384 offset = kvm_x86_ops->compute_tsc_offset(vcpu, data); 1385 pr_debug("kvm: adjusted tsc offset by %llu\n", delta); 1386 } 1387 matched = true; 1388 already_matched = (vcpu->arch.this_tsc_generation == kvm->arch.cur_tsc_generation); 1389 } else { 1390 /* 1391 * We split periods of matched TSC writes into generations. 1392 * For each generation, we track the original measured 1393 * nanosecond time, offset, and write, so if TSCs are in 1394 * sync, we can match exact offset, and if not, we can match 1395 * exact software computation in compute_guest_tsc() 1396 * 1397 * These values are tracked in kvm->arch.cur_xxx variables. 1398 */ 1399 kvm->arch.cur_tsc_generation++; 1400 kvm->arch.cur_tsc_nsec = ns; 1401 kvm->arch.cur_tsc_write = data; 1402 kvm->arch.cur_tsc_offset = offset; 1403 matched = false; 1404 pr_debug("kvm: new tsc generation %llu, clock %llu\n", 1405 kvm->arch.cur_tsc_generation, data); 1406 } 1407 1408 /* 1409 * We also track th most recent recorded KHZ, write and time to 1410 * allow the matching interval to be extended at each write. 1411 */ 1412 kvm->arch.last_tsc_nsec = ns; 1413 kvm->arch.last_tsc_write = data; 1414 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz; 1415 1416 vcpu->arch.last_guest_tsc = data; 1417 1418 /* Keep track of which generation this VCPU has synchronized to */ 1419 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation; 1420 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec; 1421 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write; 1422 1423 if (guest_cpuid_has_tsc_adjust(vcpu) && !msr->host_initiated) 1424 update_ia32_tsc_adjust_msr(vcpu, offset); 1425 kvm_x86_ops->write_tsc_offset(vcpu, offset); 1426 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags); 1427 1428 spin_lock(&kvm->arch.pvclock_gtod_sync_lock); 1429 if (!matched) { 1430 kvm->arch.nr_vcpus_matched_tsc = 0; 1431 } else if (!already_matched) { 1432 kvm->arch.nr_vcpus_matched_tsc++; 1433 } 1434 1435 kvm_track_tsc_matching(vcpu); 1436 spin_unlock(&kvm->arch.pvclock_gtod_sync_lock); 1437 } 1438 1439 EXPORT_SYMBOL_GPL(kvm_write_tsc); 1440 1441 #ifdef CONFIG_X86_64 1442 1443 static cycle_t read_tsc(void) 1444 { 1445 cycle_t ret = (cycle_t)rdtsc_ordered(); 1446 u64 last = pvclock_gtod_data.clock.cycle_last; 1447 1448 if (likely(ret >= last)) 1449 return ret; 1450 1451 /* 1452 * GCC likes to generate cmov here, but this branch is extremely 1453 * predictable (it's just a funciton of time and the likely is 1454 * very likely) and there's a data dependence, so force GCC 1455 * to generate a branch instead. I don't barrier() because 1456 * we don't actually need a barrier, and if this function 1457 * ever gets inlined it will generate worse code. 1458 */ 1459 asm volatile (""); 1460 return last; 1461 } 1462 1463 static inline u64 vgettsc(cycle_t *cycle_now) 1464 { 1465 long v; 1466 struct pvclock_gtod_data *gtod = &pvclock_gtod_data; 1467 1468 *cycle_now = read_tsc(); 1469 1470 v = (*cycle_now - gtod->clock.cycle_last) & gtod->clock.mask; 1471 return v * gtod->clock.mult; 1472 } 1473 1474 static int do_monotonic_boot(s64 *t, cycle_t *cycle_now) 1475 { 1476 struct pvclock_gtod_data *gtod = &pvclock_gtod_data; 1477 unsigned long seq; 1478 int mode; 1479 u64 ns; 1480 1481 do { 1482 seq = read_seqcount_begin(>od->seq); 1483 mode = gtod->clock.vclock_mode; 1484 ns = gtod->nsec_base; 1485 ns += vgettsc(cycle_now); 1486 ns >>= gtod->clock.shift; 1487 ns += gtod->boot_ns; 1488 } while (unlikely(read_seqcount_retry(>od->seq, seq))); 1489 *t = ns; 1490 1491 return mode; 1492 } 1493 1494 /* returns true if host is using tsc clocksource */ 1495 static bool kvm_get_time_and_clockread(s64 *kernel_ns, cycle_t *cycle_now) 1496 { 1497 /* checked again under seqlock below */ 1498 if (pvclock_gtod_data.clock.vclock_mode != VCLOCK_TSC) 1499 return false; 1500 1501 return do_monotonic_boot(kernel_ns, cycle_now) == VCLOCK_TSC; 1502 } 1503 #endif 1504 1505 /* 1506 * 1507 * Assuming a stable TSC across physical CPUS, and a stable TSC 1508 * across virtual CPUs, the following condition is possible. 1509 * Each numbered line represents an event visible to both 1510 * CPUs at the next numbered event. 1511 * 1512 * "timespecX" represents host monotonic time. "tscX" represents 1513 * RDTSC value. 1514 * 1515 * VCPU0 on CPU0 | VCPU1 on CPU1 1516 * 1517 * 1. read timespec0,tsc0 1518 * 2. | timespec1 = timespec0 + N 1519 * | tsc1 = tsc0 + M 1520 * 3. transition to guest | transition to guest 1521 * 4. ret0 = timespec0 + (rdtsc - tsc0) | 1522 * 5. | ret1 = timespec1 + (rdtsc - tsc1) 1523 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M)) 1524 * 1525 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity: 1526 * 1527 * - ret0 < ret1 1528 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M)) 1529 * ... 1530 * - 0 < N - M => M < N 1531 * 1532 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not 1533 * always the case (the difference between two distinct xtime instances 1534 * might be smaller then the difference between corresponding TSC reads, 1535 * when updating guest vcpus pvclock areas). 1536 * 1537 * To avoid that problem, do not allow visibility of distinct 1538 * system_timestamp/tsc_timestamp values simultaneously: use a master 1539 * copy of host monotonic time values. Update that master copy 1540 * in lockstep. 1541 * 1542 * Rely on synchronization of host TSCs and guest TSCs for monotonicity. 1543 * 1544 */ 1545 1546 static void pvclock_update_vm_gtod_copy(struct kvm *kvm) 1547 { 1548 #ifdef CONFIG_X86_64 1549 struct kvm_arch *ka = &kvm->arch; 1550 int vclock_mode; 1551 bool host_tsc_clocksource, vcpus_matched; 1552 1553 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 == 1554 atomic_read(&kvm->online_vcpus)); 1555 1556 /* 1557 * If the host uses TSC clock, then passthrough TSC as stable 1558 * to the guest. 1559 */ 1560 host_tsc_clocksource = kvm_get_time_and_clockread( 1561 &ka->master_kernel_ns, 1562 &ka->master_cycle_now); 1563 1564 ka->use_master_clock = host_tsc_clocksource && vcpus_matched 1565 && !backwards_tsc_observed 1566 && !ka->boot_vcpu_runs_old_kvmclock; 1567 1568 if (ka->use_master_clock) 1569 atomic_set(&kvm_guest_has_master_clock, 1); 1570 1571 vclock_mode = pvclock_gtod_data.clock.vclock_mode; 1572 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode, 1573 vcpus_matched); 1574 #endif 1575 } 1576 1577 static void kvm_gen_update_masterclock(struct kvm *kvm) 1578 { 1579 #ifdef CONFIG_X86_64 1580 int i; 1581 struct kvm_vcpu *vcpu; 1582 struct kvm_arch *ka = &kvm->arch; 1583 1584 spin_lock(&ka->pvclock_gtod_sync_lock); 1585 kvm_make_mclock_inprogress_request(kvm); 1586 /* no guest entries from this point */ 1587 pvclock_update_vm_gtod_copy(kvm); 1588 1589 kvm_for_each_vcpu(i, vcpu, kvm) 1590 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 1591 1592 /* guest entries allowed */ 1593 kvm_for_each_vcpu(i, vcpu, kvm) 1594 clear_bit(KVM_REQ_MCLOCK_INPROGRESS, &vcpu->requests); 1595 1596 spin_unlock(&ka->pvclock_gtod_sync_lock); 1597 #endif 1598 } 1599 1600 static int kvm_guest_time_update(struct kvm_vcpu *v) 1601 { 1602 unsigned long flags, this_tsc_khz; 1603 struct kvm_vcpu_arch *vcpu = &v->arch; 1604 struct kvm_arch *ka = &v->kvm->arch; 1605 s64 kernel_ns; 1606 u64 tsc_timestamp, host_tsc; 1607 struct pvclock_vcpu_time_info guest_hv_clock; 1608 u8 pvclock_flags; 1609 bool use_master_clock; 1610 1611 kernel_ns = 0; 1612 host_tsc = 0; 1613 1614 /* 1615 * If the host uses TSC clock, then passthrough TSC as stable 1616 * to the guest. 1617 */ 1618 spin_lock(&ka->pvclock_gtod_sync_lock); 1619 use_master_clock = ka->use_master_clock; 1620 if (use_master_clock) { 1621 host_tsc = ka->master_cycle_now; 1622 kernel_ns = ka->master_kernel_ns; 1623 } 1624 spin_unlock(&ka->pvclock_gtod_sync_lock); 1625 1626 /* Keep irq disabled to prevent changes to the clock */ 1627 local_irq_save(flags); 1628 this_tsc_khz = __this_cpu_read(cpu_tsc_khz); 1629 if (unlikely(this_tsc_khz == 0)) { 1630 local_irq_restore(flags); 1631 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v); 1632 return 1; 1633 } 1634 if (!use_master_clock) { 1635 host_tsc = rdtsc(); 1636 kernel_ns = get_kernel_ns(); 1637 } 1638 1639 tsc_timestamp = kvm_x86_ops->read_l1_tsc(v, host_tsc); 1640 1641 /* 1642 * We may have to catch up the TSC to match elapsed wall clock 1643 * time for two reasons, even if kvmclock is used. 1644 * 1) CPU could have been running below the maximum TSC rate 1645 * 2) Broken TSC compensation resets the base at each VCPU 1646 * entry to avoid unknown leaps of TSC even when running 1647 * again on the same CPU. This may cause apparent elapsed 1648 * time to disappear, and the guest to stand still or run 1649 * very slowly. 1650 */ 1651 if (vcpu->tsc_catchup) { 1652 u64 tsc = compute_guest_tsc(v, kernel_ns); 1653 if (tsc > tsc_timestamp) { 1654 adjust_tsc_offset_guest(v, tsc - tsc_timestamp); 1655 tsc_timestamp = tsc; 1656 } 1657 } 1658 1659 local_irq_restore(flags); 1660 1661 if (!vcpu->pv_time_enabled) 1662 return 0; 1663 1664 if (unlikely(vcpu->hw_tsc_khz != this_tsc_khz)) { 1665 kvm_get_time_scale(NSEC_PER_SEC / 1000, this_tsc_khz, 1666 &vcpu->hv_clock.tsc_shift, 1667 &vcpu->hv_clock.tsc_to_system_mul); 1668 vcpu->hw_tsc_khz = this_tsc_khz; 1669 } 1670 1671 /* With all the info we got, fill in the values */ 1672 vcpu->hv_clock.tsc_timestamp = tsc_timestamp; 1673 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset; 1674 vcpu->last_guest_tsc = tsc_timestamp; 1675 1676 if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time, 1677 &guest_hv_clock, sizeof(guest_hv_clock)))) 1678 return 0; 1679 1680 /* This VCPU is paused, but it's legal for a guest to read another 1681 * VCPU's kvmclock, so we really have to follow the specification where 1682 * it says that version is odd if data is being modified, and even after 1683 * it is consistent. 1684 * 1685 * Version field updates must be kept separate. This is because 1686 * kvm_write_guest_cached might use a "rep movs" instruction, and 1687 * writes within a string instruction are weakly ordered. So there 1688 * are three writes overall. 1689 * 1690 * As a small optimization, only write the version field in the first 1691 * and third write. The vcpu->pv_time cache is still valid, because the 1692 * version field is the first in the struct. 1693 */ 1694 BUILD_BUG_ON(offsetof(struct pvclock_vcpu_time_info, version) != 0); 1695 1696 vcpu->hv_clock.version = guest_hv_clock.version + 1; 1697 kvm_write_guest_cached(v->kvm, &vcpu->pv_time, 1698 &vcpu->hv_clock, 1699 sizeof(vcpu->hv_clock.version)); 1700 1701 smp_wmb(); 1702 1703 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */ 1704 pvclock_flags = (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED); 1705 1706 if (vcpu->pvclock_set_guest_stopped_request) { 1707 pvclock_flags |= PVCLOCK_GUEST_STOPPED; 1708 vcpu->pvclock_set_guest_stopped_request = false; 1709 } 1710 1711 /* If the host uses TSC clocksource, then it is stable */ 1712 if (use_master_clock) 1713 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT; 1714 1715 vcpu->hv_clock.flags = pvclock_flags; 1716 1717 trace_kvm_pvclock_update(v->vcpu_id, &vcpu->hv_clock); 1718 1719 kvm_write_guest_cached(v->kvm, &vcpu->pv_time, 1720 &vcpu->hv_clock, 1721 sizeof(vcpu->hv_clock)); 1722 1723 smp_wmb(); 1724 1725 vcpu->hv_clock.version++; 1726 kvm_write_guest_cached(v->kvm, &vcpu->pv_time, 1727 &vcpu->hv_clock, 1728 sizeof(vcpu->hv_clock.version)); 1729 return 0; 1730 } 1731 1732 /* 1733 * kvmclock updates which are isolated to a given vcpu, such as 1734 * vcpu->cpu migration, should not allow system_timestamp from 1735 * the rest of the vcpus to remain static. Otherwise ntp frequency 1736 * correction applies to one vcpu's system_timestamp but not 1737 * the others. 1738 * 1739 * So in those cases, request a kvmclock update for all vcpus. 1740 * We need to rate-limit these requests though, as they can 1741 * considerably slow guests that have a large number of vcpus. 1742 * The time for a remote vcpu to update its kvmclock is bound 1743 * by the delay we use to rate-limit the updates. 1744 */ 1745 1746 #define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100) 1747 1748 static void kvmclock_update_fn(struct work_struct *work) 1749 { 1750 int i; 1751 struct delayed_work *dwork = to_delayed_work(work); 1752 struct kvm_arch *ka = container_of(dwork, struct kvm_arch, 1753 kvmclock_update_work); 1754 struct kvm *kvm = container_of(ka, struct kvm, arch); 1755 struct kvm_vcpu *vcpu; 1756 1757 kvm_for_each_vcpu(i, vcpu, kvm) { 1758 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 1759 kvm_vcpu_kick(vcpu); 1760 } 1761 } 1762 1763 static void kvm_gen_kvmclock_update(struct kvm_vcpu *v) 1764 { 1765 struct kvm *kvm = v->kvm; 1766 1767 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v); 1768 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 1769 KVMCLOCK_UPDATE_DELAY); 1770 } 1771 1772 #define KVMCLOCK_SYNC_PERIOD (300 * HZ) 1773 1774 static void kvmclock_sync_fn(struct work_struct *work) 1775 { 1776 struct delayed_work *dwork = to_delayed_work(work); 1777 struct kvm_arch *ka = container_of(dwork, struct kvm_arch, 1778 kvmclock_sync_work); 1779 struct kvm *kvm = container_of(ka, struct kvm, arch); 1780 1781 if (!kvmclock_periodic_sync) 1782 return; 1783 1784 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0); 1785 schedule_delayed_work(&kvm->arch.kvmclock_sync_work, 1786 KVMCLOCK_SYNC_PERIOD); 1787 } 1788 1789 static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data) 1790 { 1791 u64 mcg_cap = vcpu->arch.mcg_cap; 1792 unsigned bank_num = mcg_cap & 0xff; 1793 1794 switch (msr) { 1795 case MSR_IA32_MCG_STATUS: 1796 vcpu->arch.mcg_status = data; 1797 break; 1798 case MSR_IA32_MCG_CTL: 1799 if (!(mcg_cap & MCG_CTL_P)) 1800 return 1; 1801 if (data != 0 && data != ~(u64)0) 1802 return -1; 1803 vcpu->arch.mcg_ctl = data; 1804 break; 1805 default: 1806 if (msr >= MSR_IA32_MC0_CTL && 1807 msr < MSR_IA32_MCx_CTL(bank_num)) { 1808 u32 offset = msr - MSR_IA32_MC0_CTL; 1809 /* only 0 or all 1s can be written to IA32_MCi_CTL 1810 * some Linux kernels though clear bit 10 in bank 4 to 1811 * workaround a BIOS/GART TBL issue on AMD K8s, ignore 1812 * this to avoid an uncatched #GP in the guest 1813 */ 1814 if ((offset & 0x3) == 0 && 1815 data != 0 && (data | (1 << 10)) != ~(u64)0) 1816 return -1; 1817 vcpu->arch.mce_banks[offset] = data; 1818 break; 1819 } 1820 return 1; 1821 } 1822 return 0; 1823 } 1824 1825 static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data) 1826 { 1827 struct kvm *kvm = vcpu->kvm; 1828 int lm = is_long_mode(vcpu); 1829 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64 1830 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32; 1831 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64 1832 : kvm->arch.xen_hvm_config.blob_size_32; 1833 u32 page_num = data & ~PAGE_MASK; 1834 u64 page_addr = data & PAGE_MASK; 1835 u8 *page; 1836 int r; 1837 1838 r = -E2BIG; 1839 if (page_num >= blob_size) 1840 goto out; 1841 r = -ENOMEM; 1842 page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE); 1843 if (IS_ERR(page)) { 1844 r = PTR_ERR(page); 1845 goto out; 1846 } 1847 if (kvm_vcpu_write_guest(vcpu, page_addr, page, PAGE_SIZE)) 1848 goto out_free; 1849 r = 0; 1850 out_free: 1851 kfree(page); 1852 out: 1853 return r; 1854 } 1855 1856 static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data) 1857 { 1858 gpa_t gpa = data & ~0x3f; 1859 1860 /* Bits 2:5 are reserved, Should be zero */ 1861 if (data & 0x3c) 1862 return 1; 1863 1864 vcpu->arch.apf.msr_val = data; 1865 1866 if (!(data & KVM_ASYNC_PF_ENABLED)) { 1867 kvm_clear_async_pf_completion_queue(vcpu); 1868 kvm_async_pf_hash_reset(vcpu); 1869 return 0; 1870 } 1871 1872 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa, 1873 sizeof(u32))) 1874 return 1; 1875 1876 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS); 1877 kvm_async_pf_wakeup_all(vcpu); 1878 return 0; 1879 } 1880 1881 static void kvmclock_reset(struct kvm_vcpu *vcpu) 1882 { 1883 vcpu->arch.pv_time_enabled = false; 1884 } 1885 1886 static void accumulate_steal_time(struct kvm_vcpu *vcpu) 1887 { 1888 u64 delta; 1889 1890 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED)) 1891 return; 1892 1893 delta = current->sched_info.run_delay - vcpu->arch.st.last_steal; 1894 vcpu->arch.st.last_steal = current->sched_info.run_delay; 1895 vcpu->arch.st.accum_steal = delta; 1896 } 1897 1898 static void record_steal_time(struct kvm_vcpu *vcpu) 1899 { 1900 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED)) 1901 return; 1902 1903 if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime, 1904 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time)))) 1905 return; 1906 1907 vcpu->arch.st.steal.steal += vcpu->arch.st.accum_steal; 1908 vcpu->arch.st.steal.version += 2; 1909 vcpu->arch.st.accum_steal = 0; 1910 1911 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime, 1912 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time)); 1913 } 1914 1915 int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info) 1916 { 1917 bool pr = false; 1918 u32 msr = msr_info->index; 1919 u64 data = msr_info->data; 1920 1921 switch (msr) { 1922 case MSR_AMD64_NB_CFG: 1923 case MSR_IA32_UCODE_REV: 1924 case MSR_IA32_UCODE_WRITE: 1925 case MSR_VM_HSAVE_PA: 1926 case MSR_AMD64_PATCH_LOADER: 1927 case MSR_AMD64_BU_CFG2: 1928 break; 1929 1930 case MSR_EFER: 1931 return set_efer(vcpu, data); 1932 case MSR_K7_HWCR: 1933 data &= ~(u64)0x40; /* ignore flush filter disable */ 1934 data &= ~(u64)0x100; /* ignore ignne emulation enable */ 1935 data &= ~(u64)0x8; /* ignore TLB cache disable */ 1936 data &= ~(u64)0x40000; /* ignore Mc status write enable */ 1937 if (data != 0) { 1938 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n", 1939 data); 1940 return 1; 1941 } 1942 break; 1943 case MSR_FAM10H_MMIO_CONF_BASE: 1944 if (data != 0) { 1945 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: " 1946 "0x%llx\n", data); 1947 return 1; 1948 } 1949 break; 1950 case MSR_IA32_DEBUGCTLMSR: 1951 if (!data) { 1952 /* We support the non-activated case already */ 1953 break; 1954 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) { 1955 /* Values other than LBR and BTF are vendor-specific, 1956 thus reserved and should throw a #GP */ 1957 return 1; 1958 } 1959 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n", 1960 __func__, data); 1961 break; 1962 case 0x200 ... 0x2ff: 1963 return kvm_mtrr_set_msr(vcpu, msr, data); 1964 case MSR_IA32_APICBASE: 1965 return kvm_set_apic_base(vcpu, msr_info); 1966 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff: 1967 return kvm_x2apic_msr_write(vcpu, msr, data); 1968 case MSR_IA32_TSCDEADLINE: 1969 kvm_set_lapic_tscdeadline_msr(vcpu, data); 1970 break; 1971 case MSR_IA32_TSC_ADJUST: 1972 if (guest_cpuid_has_tsc_adjust(vcpu)) { 1973 if (!msr_info->host_initiated) { 1974 s64 adj = data - vcpu->arch.ia32_tsc_adjust_msr; 1975 adjust_tsc_offset_guest(vcpu, adj); 1976 } 1977 vcpu->arch.ia32_tsc_adjust_msr = data; 1978 } 1979 break; 1980 case MSR_IA32_MISC_ENABLE: 1981 vcpu->arch.ia32_misc_enable_msr = data; 1982 break; 1983 case MSR_IA32_SMBASE: 1984 if (!msr_info->host_initiated) 1985 return 1; 1986 vcpu->arch.smbase = data; 1987 break; 1988 case MSR_KVM_WALL_CLOCK_NEW: 1989 case MSR_KVM_WALL_CLOCK: 1990 vcpu->kvm->arch.wall_clock = data; 1991 kvm_write_wall_clock(vcpu->kvm, data); 1992 break; 1993 case MSR_KVM_SYSTEM_TIME_NEW: 1994 case MSR_KVM_SYSTEM_TIME: { 1995 u64 gpa_offset; 1996 struct kvm_arch *ka = &vcpu->kvm->arch; 1997 1998 kvmclock_reset(vcpu); 1999 2000 if (vcpu->vcpu_id == 0 && !msr_info->host_initiated) { 2001 bool tmp = (msr == MSR_KVM_SYSTEM_TIME); 2002 2003 if (ka->boot_vcpu_runs_old_kvmclock != tmp) 2004 set_bit(KVM_REQ_MASTERCLOCK_UPDATE, 2005 &vcpu->requests); 2006 2007 ka->boot_vcpu_runs_old_kvmclock = tmp; 2008 } 2009 2010 vcpu->arch.time = data; 2011 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu); 2012 2013 /* we verify if the enable bit is set... */ 2014 if (!(data & 1)) 2015 break; 2016 2017 gpa_offset = data & ~(PAGE_MASK | 1); 2018 2019 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, 2020 &vcpu->arch.pv_time, data & ~1ULL, 2021 sizeof(struct pvclock_vcpu_time_info))) 2022 vcpu->arch.pv_time_enabled = false; 2023 else 2024 vcpu->arch.pv_time_enabled = true; 2025 2026 break; 2027 } 2028 case MSR_KVM_ASYNC_PF_EN: 2029 if (kvm_pv_enable_async_pf(vcpu, data)) 2030 return 1; 2031 break; 2032 case MSR_KVM_STEAL_TIME: 2033 2034 if (unlikely(!sched_info_on())) 2035 return 1; 2036 2037 if (data & KVM_STEAL_RESERVED_MASK) 2038 return 1; 2039 2040 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime, 2041 data & KVM_STEAL_VALID_BITS, 2042 sizeof(struct kvm_steal_time))) 2043 return 1; 2044 2045 vcpu->arch.st.msr_val = data; 2046 2047 if (!(data & KVM_MSR_ENABLED)) 2048 break; 2049 2050 vcpu->arch.st.last_steal = current->sched_info.run_delay; 2051 2052 preempt_disable(); 2053 accumulate_steal_time(vcpu); 2054 preempt_enable(); 2055 2056 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu); 2057 2058 break; 2059 case MSR_KVM_PV_EOI_EN: 2060 if (kvm_lapic_enable_pv_eoi(vcpu, data)) 2061 return 1; 2062 break; 2063 2064 case MSR_IA32_MCG_CTL: 2065 case MSR_IA32_MCG_STATUS: 2066 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1: 2067 return set_msr_mce(vcpu, msr, data); 2068 2069 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3: 2070 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1: 2071 pr = true; /* fall through */ 2072 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3: 2073 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1: 2074 if (kvm_pmu_is_valid_msr(vcpu, msr)) 2075 return kvm_pmu_set_msr(vcpu, msr_info); 2076 2077 if (pr || data != 0) 2078 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: " 2079 "0x%x data 0x%llx\n", msr, data); 2080 break; 2081 case MSR_K7_CLK_CTL: 2082 /* 2083 * Ignore all writes to this no longer documented MSR. 2084 * Writes are only relevant for old K7 processors, 2085 * all pre-dating SVM, but a recommended workaround from 2086 * AMD for these chips. It is possible to specify the 2087 * affected processor models on the command line, hence 2088 * the need to ignore the workaround. 2089 */ 2090 break; 2091 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15: 2092 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4: 2093 case HV_X64_MSR_CRASH_CTL: 2094 return kvm_hv_set_msr_common(vcpu, msr, data, 2095 msr_info->host_initiated); 2096 case MSR_IA32_BBL_CR_CTL3: 2097 /* Drop writes to this legacy MSR -- see rdmsr 2098 * counterpart for further detail. 2099 */ 2100 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n", msr, data); 2101 break; 2102 case MSR_AMD64_OSVW_ID_LENGTH: 2103 if (!guest_cpuid_has_osvw(vcpu)) 2104 return 1; 2105 vcpu->arch.osvw.length = data; 2106 break; 2107 case MSR_AMD64_OSVW_STATUS: 2108 if (!guest_cpuid_has_osvw(vcpu)) 2109 return 1; 2110 vcpu->arch.osvw.status = data; 2111 break; 2112 default: 2113 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr)) 2114 return xen_hvm_config(vcpu, data); 2115 if (kvm_pmu_is_valid_msr(vcpu, msr)) 2116 return kvm_pmu_set_msr(vcpu, msr_info); 2117 if (!ignore_msrs) { 2118 vcpu_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n", 2119 msr, data); 2120 return 1; 2121 } else { 2122 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n", 2123 msr, data); 2124 break; 2125 } 2126 } 2127 return 0; 2128 } 2129 EXPORT_SYMBOL_GPL(kvm_set_msr_common); 2130 2131 2132 /* 2133 * Reads an msr value (of 'msr_index') into 'pdata'. 2134 * Returns 0 on success, non-0 otherwise. 2135 * Assumes vcpu_load() was already called. 2136 */ 2137 int kvm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr) 2138 { 2139 return kvm_x86_ops->get_msr(vcpu, msr); 2140 } 2141 EXPORT_SYMBOL_GPL(kvm_get_msr); 2142 2143 static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata) 2144 { 2145 u64 data; 2146 u64 mcg_cap = vcpu->arch.mcg_cap; 2147 unsigned bank_num = mcg_cap & 0xff; 2148 2149 switch (msr) { 2150 case MSR_IA32_P5_MC_ADDR: 2151 case MSR_IA32_P5_MC_TYPE: 2152 data = 0; 2153 break; 2154 case MSR_IA32_MCG_CAP: 2155 data = vcpu->arch.mcg_cap; 2156 break; 2157 case MSR_IA32_MCG_CTL: 2158 if (!(mcg_cap & MCG_CTL_P)) 2159 return 1; 2160 data = vcpu->arch.mcg_ctl; 2161 break; 2162 case MSR_IA32_MCG_STATUS: 2163 data = vcpu->arch.mcg_status; 2164 break; 2165 default: 2166 if (msr >= MSR_IA32_MC0_CTL && 2167 msr < MSR_IA32_MCx_CTL(bank_num)) { 2168 u32 offset = msr - MSR_IA32_MC0_CTL; 2169 data = vcpu->arch.mce_banks[offset]; 2170 break; 2171 } 2172 return 1; 2173 } 2174 *pdata = data; 2175 return 0; 2176 } 2177 2178 int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info) 2179 { 2180 switch (msr_info->index) { 2181 case MSR_IA32_PLATFORM_ID: 2182 case MSR_IA32_EBL_CR_POWERON: 2183 case MSR_IA32_DEBUGCTLMSR: 2184 case MSR_IA32_LASTBRANCHFROMIP: 2185 case MSR_IA32_LASTBRANCHTOIP: 2186 case MSR_IA32_LASTINTFROMIP: 2187 case MSR_IA32_LASTINTTOIP: 2188 case MSR_K8_SYSCFG: 2189 case MSR_K8_TSEG_ADDR: 2190 case MSR_K8_TSEG_MASK: 2191 case MSR_K7_HWCR: 2192 case MSR_VM_HSAVE_PA: 2193 case MSR_K8_INT_PENDING_MSG: 2194 case MSR_AMD64_NB_CFG: 2195 case MSR_FAM10H_MMIO_CONF_BASE: 2196 case MSR_AMD64_BU_CFG2: 2197 msr_info->data = 0; 2198 break; 2199 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3: 2200 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3: 2201 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1: 2202 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1: 2203 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index)) 2204 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data); 2205 msr_info->data = 0; 2206 break; 2207 case MSR_IA32_UCODE_REV: 2208 msr_info->data = 0x100000000ULL; 2209 break; 2210 case MSR_MTRRcap: 2211 case 0x200 ... 0x2ff: 2212 return kvm_mtrr_get_msr(vcpu, msr_info->index, &msr_info->data); 2213 case 0xcd: /* fsb frequency */ 2214 msr_info->data = 3; 2215 break; 2216 /* 2217 * MSR_EBC_FREQUENCY_ID 2218 * Conservative value valid for even the basic CPU models. 2219 * Models 0,1: 000 in bits 23:21 indicating a bus speed of 2220 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz, 2221 * and 266MHz for model 3, or 4. Set Core Clock 2222 * Frequency to System Bus Frequency Ratio to 1 (bits 2223 * 31:24) even though these are only valid for CPU 2224 * models > 2, however guests may end up dividing or 2225 * multiplying by zero otherwise. 2226 */ 2227 case MSR_EBC_FREQUENCY_ID: 2228 msr_info->data = 1 << 24; 2229 break; 2230 case MSR_IA32_APICBASE: 2231 msr_info->data = kvm_get_apic_base(vcpu); 2232 break; 2233 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff: 2234 return kvm_x2apic_msr_read(vcpu, msr_info->index, &msr_info->data); 2235 break; 2236 case MSR_IA32_TSCDEADLINE: 2237 msr_info->data = kvm_get_lapic_tscdeadline_msr(vcpu); 2238 break; 2239 case MSR_IA32_TSC_ADJUST: 2240 msr_info->data = (u64)vcpu->arch.ia32_tsc_adjust_msr; 2241 break; 2242 case MSR_IA32_MISC_ENABLE: 2243 msr_info->data = vcpu->arch.ia32_misc_enable_msr; 2244 break; 2245 case MSR_IA32_SMBASE: 2246 if (!msr_info->host_initiated) 2247 return 1; 2248 msr_info->data = vcpu->arch.smbase; 2249 break; 2250 case MSR_IA32_PERF_STATUS: 2251 /* TSC increment by tick */ 2252 msr_info->data = 1000ULL; 2253 /* CPU multiplier */ 2254 msr_info->data |= (((uint64_t)4ULL) << 40); 2255 break; 2256 case MSR_EFER: 2257 msr_info->data = vcpu->arch.efer; 2258 break; 2259 case MSR_KVM_WALL_CLOCK: 2260 case MSR_KVM_WALL_CLOCK_NEW: 2261 msr_info->data = vcpu->kvm->arch.wall_clock; 2262 break; 2263 case MSR_KVM_SYSTEM_TIME: 2264 case MSR_KVM_SYSTEM_TIME_NEW: 2265 msr_info->data = vcpu->arch.time; 2266 break; 2267 case MSR_KVM_ASYNC_PF_EN: 2268 msr_info->data = vcpu->arch.apf.msr_val; 2269 break; 2270 case MSR_KVM_STEAL_TIME: 2271 msr_info->data = vcpu->arch.st.msr_val; 2272 break; 2273 case MSR_KVM_PV_EOI_EN: 2274 msr_info->data = vcpu->arch.pv_eoi.msr_val; 2275 break; 2276 case MSR_IA32_P5_MC_ADDR: 2277 case MSR_IA32_P5_MC_TYPE: 2278 case MSR_IA32_MCG_CAP: 2279 case MSR_IA32_MCG_CTL: 2280 case MSR_IA32_MCG_STATUS: 2281 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1: 2282 return get_msr_mce(vcpu, msr_info->index, &msr_info->data); 2283 case MSR_K7_CLK_CTL: 2284 /* 2285 * Provide expected ramp-up count for K7. All other 2286 * are set to zero, indicating minimum divisors for 2287 * every field. 2288 * 2289 * This prevents guest kernels on AMD host with CPU 2290 * type 6, model 8 and higher from exploding due to 2291 * the rdmsr failing. 2292 */ 2293 msr_info->data = 0x20000000; 2294 break; 2295 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15: 2296 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4: 2297 case HV_X64_MSR_CRASH_CTL: 2298 return kvm_hv_get_msr_common(vcpu, 2299 msr_info->index, &msr_info->data); 2300 break; 2301 case MSR_IA32_BBL_CR_CTL3: 2302 /* This legacy MSR exists but isn't fully documented in current 2303 * silicon. It is however accessed by winxp in very narrow 2304 * scenarios where it sets bit #19, itself documented as 2305 * a "reserved" bit. Best effort attempt to source coherent 2306 * read data here should the balance of the register be 2307 * interpreted by the guest: 2308 * 2309 * L2 cache control register 3: 64GB range, 256KB size, 2310 * enabled, latency 0x1, configured 2311 */ 2312 msr_info->data = 0xbe702111; 2313 break; 2314 case MSR_AMD64_OSVW_ID_LENGTH: 2315 if (!guest_cpuid_has_osvw(vcpu)) 2316 return 1; 2317 msr_info->data = vcpu->arch.osvw.length; 2318 break; 2319 case MSR_AMD64_OSVW_STATUS: 2320 if (!guest_cpuid_has_osvw(vcpu)) 2321 return 1; 2322 msr_info->data = vcpu->arch.osvw.status; 2323 break; 2324 default: 2325 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index)) 2326 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data); 2327 if (!ignore_msrs) { 2328 vcpu_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr_info->index); 2329 return 1; 2330 } else { 2331 vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr_info->index); 2332 msr_info->data = 0; 2333 } 2334 break; 2335 } 2336 return 0; 2337 } 2338 EXPORT_SYMBOL_GPL(kvm_get_msr_common); 2339 2340 /* 2341 * Read or write a bunch of msrs. All parameters are kernel addresses. 2342 * 2343 * @return number of msrs set successfully. 2344 */ 2345 static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs, 2346 struct kvm_msr_entry *entries, 2347 int (*do_msr)(struct kvm_vcpu *vcpu, 2348 unsigned index, u64 *data)) 2349 { 2350 int i, idx; 2351 2352 idx = srcu_read_lock(&vcpu->kvm->srcu); 2353 for (i = 0; i < msrs->nmsrs; ++i) 2354 if (do_msr(vcpu, entries[i].index, &entries[i].data)) 2355 break; 2356 srcu_read_unlock(&vcpu->kvm->srcu, idx); 2357 2358 return i; 2359 } 2360 2361 /* 2362 * Read or write a bunch of msrs. Parameters are user addresses. 2363 * 2364 * @return number of msrs set successfully. 2365 */ 2366 static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs, 2367 int (*do_msr)(struct kvm_vcpu *vcpu, 2368 unsigned index, u64 *data), 2369 int writeback) 2370 { 2371 struct kvm_msrs msrs; 2372 struct kvm_msr_entry *entries; 2373 int r, n; 2374 unsigned size; 2375 2376 r = -EFAULT; 2377 if (copy_from_user(&msrs, user_msrs, sizeof msrs)) 2378 goto out; 2379 2380 r = -E2BIG; 2381 if (msrs.nmsrs >= MAX_IO_MSRS) 2382 goto out; 2383 2384 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs; 2385 entries = memdup_user(user_msrs->entries, size); 2386 if (IS_ERR(entries)) { 2387 r = PTR_ERR(entries); 2388 goto out; 2389 } 2390 2391 r = n = __msr_io(vcpu, &msrs, entries, do_msr); 2392 if (r < 0) 2393 goto out_free; 2394 2395 r = -EFAULT; 2396 if (writeback && copy_to_user(user_msrs->entries, entries, size)) 2397 goto out_free; 2398 2399 r = n; 2400 2401 out_free: 2402 kfree(entries); 2403 out: 2404 return r; 2405 } 2406 2407 int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext) 2408 { 2409 int r; 2410 2411 switch (ext) { 2412 case KVM_CAP_IRQCHIP: 2413 case KVM_CAP_HLT: 2414 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL: 2415 case KVM_CAP_SET_TSS_ADDR: 2416 case KVM_CAP_EXT_CPUID: 2417 case KVM_CAP_EXT_EMUL_CPUID: 2418 case KVM_CAP_CLOCKSOURCE: 2419 case KVM_CAP_PIT: 2420 case KVM_CAP_NOP_IO_DELAY: 2421 case KVM_CAP_MP_STATE: 2422 case KVM_CAP_SYNC_MMU: 2423 case KVM_CAP_USER_NMI: 2424 case KVM_CAP_REINJECT_CONTROL: 2425 case KVM_CAP_IRQ_INJECT_STATUS: 2426 case KVM_CAP_IOEVENTFD: 2427 case KVM_CAP_IOEVENTFD_NO_LENGTH: 2428 case KVM_CAP_PIT2: 2429 case KVM_CAP_PIT_STATE2: 2430 case KVM_CAP_SET_IDENTITY_MAP_ADDR: 2431 case KVM_CAP_XEN_HVM: 2432 case KVM_CAP_ADJUST_CLOCK: 2433 case KVM_CAP_VCPU_EVENTS: 2434 case KVM_CAP_HYPERV: 2435 case KVM_CAP_HYPERV_VAPIC: 2436 case KVM_CAP_HYPERV_SPIN: 2437 case KVM_CAP_PCI_SEGMENT: 2438 case KVM_CAP_DEBUGREGS: 2439 case KVM_CAP_X86_ROBUST_SINGLESTEP: 2440 case KVM_CAP_XSAVE: 2441 case KVM_CAP_ASYNC_PF: 2442 case KVM_CAP_GET_TSC_KHZ: 2443 case KVM_CAP_KVMCLOCK_CTRL: 2444 case KVM_CAP_READONLY_MEM: 2445 case KVM_CAP_HYPERV_TIME: 2446 case KVM_CAP_IOAPIC_POLARITY_IGNORED: 2447 case KVM_CAP_TSC_DEADLINE_TIMER: 2448 case KVM_CAP_ENABLE_CAP_VM: 2449 case KVM_CAP_DISABLE_QUIRKS: 2450 case KVM_CAP_SET_BOOT_CPU_ID: 2451 #ifdef CONFIG_KVM_DEVICE_ASSIGNMENT 2452 case KVM_CAP_ASSIGN_DEV_IRQ: 2453 case KVM_CAP_PCI_2_3: 2454 #endif 2455 r = 1; 2456 break; 2457 case KVM_CAP_X86_SMM: 2458 /* SMBASE is usually relocated above 1M on modern chipsets, 2459 * and SMM handlers might indeed rely on 4G segment limits, 2460 * so do not report SMM to be available if real mode is 2461 * emulated via vm86 mode. Still, do not go to great lengths 2462 * to avoid userspace's usage of the feature, because it is a 2463 * fringe case that is not enabled except via specific settings 2464 * of the module parameters. 2465 */ 2466 r = kvm_x86_ops->cpu_has_high_real_mode_segbase(); 2467 break; 2468 case KVM_CAP_COALESCED_MMIO: 2469 r = KVM_COALESCED_MMIO_PAGE_OFFSET; 2470 break; 2471 case KVM_CAP_VAPIC: 2472 r = !kvm_x86_ops->cpu_has_accelerated_tpr(); 2473 break; 2474 case KVM_CAP_NR_VCPUS: 2475 r = KVM_SOFT_MAX_VCPUS; 2476 break; 2477 case KVM_CAP_MAX_VCPUS: 2478 r = KVM_MAX_VCPUS; 2479 break; 2480 case KVM_CAP_NR_MEMSLOTS: 2481 r = KVM_USER_MEM_SLOTS; 2482 break; 2483 case KVM_CAP_PV_MMU: /* obsolete */ 2484 r = 0; 2485 break; 2486 #ifdef CONFIG_KVM_DEVICE_ASSIGNMENT 2487 case KVM_CAP_IOMMU: 2488 r = iommu_present(&pci_bus_type); 2489 break; 2490 #endif 2491 case KVM_CAP_MCE: 2492 r = KVM_MAX_MCE_BANKS; 2493 break; 2494 case KVM_CAP_XCRS: 2495 r = cpu_has_xsave; 2496 break; 2497 case KVM_CAP_TSC_CONTROL: 2498 r = kvm_has_tsc_control; 2499 break; 2500 default: 2501 r = 0; 2502 break; 2503 } 2504 return r; 2505 2506 } 2507 2508 long kvm_arch_dev_ioctl(struct file *filp, 2509 unsigned int ioctl, unsigned long arg) 2510 { 2511 void __user *argp = (void __user *)arg; 2512 long r; 2513 2514 switch (ioctl) { 2515 case KVM_GET_MSR_INDEX_LIST: { 2516 struct kvm_msr_list __user *user_msr_list = argp; 2517 struct kvm_msr_list msr_list; 2518 unsigned n; 2519 2520 r = -EFAULT; 2521 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list)) 2522 goto out; 2523 n = msr_list.nmsrs; 2524 msr_list.nmsrs = num_msrs_to_save + num_emulated_msrs; 2525 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list)) 2526 goto out; 2527 r = -E2BIG; 2528 if (n < msr_list.nmsrs) 2529 goto out; 2530 r = -EFAULT; 2531 if (copy_to_user(user_msr_list->indices, &msrs_to_save, 2532 num_msrs_to_save * sizeof(u32))) 2533 goto out; 2534 if (copy_to_user(user_msr_list->indices + num_msrs_to_save, 2535 &emulated_msrs, 2536 num_emulated_msrs * sizeof(u32))) 2537 goto out; 2538 r = 0; 2539 break; 2540 } 2541 case KVM_GET_SUPPORTED_CPUID: 2542 case KVM_GET_EMULATED_CPUID: { 2543 struct kvm_cpuid2 __user *cpuid_arg = argp; 2544 struct kvm_cpuid2 cpuid; 2545 2546 r = -EFAULT; 2547 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid)) 2548 goto out; 2549 2550 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries, 2551 ioctl); 2552 if (r) 2553 goto out; 2554 2555 r = -EFAULT; 2556 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid)) 2557 goto out; 2558 r = 0; 2559 break; 2560 } 2561 case KVM_X86_GET_MCE_CAP_SUPPORTED: { 2562 u64 mce_cap; 2563 2564 mce_cap = KVM_MCE_CAP_SUPPORTED; 2565 r = -EFAULT; 2566 if (copy_to_user(argp, &mce_cap, sizeof mce_cap)) 2567 goto out; 2568 r = 0; 2569 break; 2570 } 2571 default: 2572 r = -EINVAL; 2573 } 2574 out: 2575 return r; 2576 } 2577 2578 static void wbinvd_ipi(void *garbage) 2579 { 2580 wbinvd(); 2581 } 2582 2583 static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu) 2584 { 2585 return kvm_arch_has_noncoherent_dma(vcpu->kvm); 2586 } 2587 2588 void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu) 2589 { 2590 /* Address WBINVD may be executed by guest */ 2591 if (need_emulate_wbinvd(vcpu)) { 2592 if (kvm_x86_ops->has_wbinvd_exit()) 2593 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask); 2594 else if (vcpu->cpu != -1 && vcpu->cpu != cpu) 2595 smp_call_function_single(vcpu->cpu, 2596 wbinvd_ipi, NULL, 1); 2597 } 2598 2599 kvm_x86_ops->vcpu_load(vcpu, cpu); 2600 2601 /* Apply any externally detected TSC adjustments (due to suspend) */ 2602 if (unlikely(vcpu->arch.tsc_offset_adjustment)) { 2603 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment); 2604 vcpu->arch.tsc_offset_adjustment = 0; 2605 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 2606 } 2607 2608 if (unlikely(vcpu->cpu != cpu) || check_tsc_unstable()) { 2609 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 : 2610 rdtsc() - vcpu->arch.last_host_tsc; 2611 if (tsc_delta < 0) 2612 mark_tsc_unstable("KVM discovered backwards TSC"); 2613 if (check_tsc_unstable()) { 2614 u64 offset = kvm_x86_ops->compute_tsc_offset(vcpu, 2615 vcpu->arch.last_guest_tsc); 2616 kvm_x86_ops->write_tsc_offset(vcpu, offset); 2617 vcpu->arch.tsc_catchup = 1; 2618 } 2619 /* 2620 * On a host with synchronized TSC, there is no need to update 2621 * kvmclock on vcpu->cpu migration 2622 */ 2623 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1) 2624 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu); 2625 if (vcpu->cpu != cpu) 2626 kvm_migrate_timers(vcpu); 2627 vcpu->cpu = cpu; 2628 } 2629 2630 accumulate_steal_time(vcpu); 2631 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu); 2632 } 2633 2634 void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu) 2635 { 2636 kvm_x86_ops->vcpu_put(vcpu); 2637 kvm_put_guest_fpu(vcpu); 2638 vcpu->arch.last_host_tsc = rdtsc(); 2639 } 2640 2641 static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu, 2642 struct kvm_lapic_state *s) 2643 { 2644 kvm_x86_ops->sync_pir_to_irr(vcpu); 2645 memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s); 2646 2647 return 0; 2648 } 2649 2650 static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu, 2651 struct kvm_lapic_state *s) 2652 { 2653 kvm_apic_post_state_restore(vcpu, s); 2654 update_cr8_intercept(vcpu); 2655 2656 return 0; 2657 } 2658 2659 static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu, 2660 struct kvm_interrupt *irq) 2661 { 2662 if (irq->irq >= KVM_NR_INTERRUPTS) 2663 return -EINVAL; 2664 if (irqchip_in_kernel(vcpu->kvm)) 2665 return -ENXIO; 2666 2667 kvm_queue_interrupt(vcpu, irq->irq, false); 2668 kvm_make_request(KVM_REQ_EVENT, vcpu); 2669 2670 return 0; 2671 } 2672 2673 static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu) 2674 { 2675 kvm_inject_nmi(vcpu); 2676 2677 return 0; 2678 } 2679 2680 static int kvm_vcpu_ioctl_smi(struct kvm_vcpu *vcpu) 2681 { 2682 kvm_make_request(KVM_REQ_SMI, vcpu); 2683 2684 return 0; 2685 } 2686 2687 static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu, 2688 struct kvm_tpr_access_ctl *tac) 2689 { 2690 if (tac->flags) 2691 return -EINVAL; 2692 vcpu->arch.tpr_access_reporting = !!tac->enabled; 2693 return 0; 2694 } 2695 2696 static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu, 2697 u64 mcg_cap) 2698 { 2699 int r; 2700 unsigned bank_num = mcg_cap & 0xff, bank; 2701 2702 r = -EINVAL; 2703 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS) 2704 goto out; 2705 if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000)) 2706 goto out; 2707 r = 0; 2708 vcpu->arch.mcg_cap = mcg_cap; 2709 /* Init IA32_MCG_CTL to all 1s */ 2710 if (mcg_cap & MCG_CTL_P) 2711 vcpu->arch.mcg_ctl = ~(u64)0; 2712 /* Init IA32_MCi_CTL to all 1s */ 2713 for (bank = 0; bank < bank_num; bank++) 2714 vcpu->arch.mce_banks[bank*4] = ~(u64)0; 2715 out: 2716 return r; 2717 } 2718 2719 static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu, 2720 struct kvm_x86_mce *mce) 2721 { 2722 u64 mcg_cap = vcpu->arch.mcg_cap; 2723 unsigned bank_num = mcg_cap & 0xff; 2724 u64 *banks = vcpu->arch.mce_banks; 2725 2726 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL)) 2727 return -EINVAL; 2728 /* 2729 * if IA32_MCG_CTL is not all 1s, the uncorrected error 2730 * reporting is disabled 2731 */ 2732 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) && 2733 vcpu->arch.mcg_ctl != ~(u64)0) 2734 return 0; 2735 banks += 4 * mce->bank; 2736 /* 2737 * if IA32_MCi_CTL is not all 1s, the uncorrected error 2738 * reporting is disabled for the bank 2739 */ 2740 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0) 2741 return 0; 2742 if (mce->status & MCI_STATUS_UC) { 2743 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) || 2744 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) { 2745 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); 2746 return 0; 2747 } 2748 if (banks[1] & MCI_STATUS_VAL) 2749 mce->status |= MCI_STATUS_OVER; 2750 banks[2] = mce->addr; 2751 banks[3] = mce->misc; 2752 vcpu->arch.mcg_status = mce->mcg_status; 2753 banks[1] = mce->status; 2754 kvm_queue_exception(vcpu, MC_VECTOR); 2755 } else if (!(banks[1] & MCI_STATUS_VAL) 2756 || !(banks[1] & MCI_STATUS_UC)) { 2757 if (banks[1] & MCI_STATUS_VAL) 2758 mce->status |= MCI_STATUS_OVER; 2759 banks[2] = mce->addr; 2760 banks[3] = mce->misc; 2761 banks[1] = mce->status; 2762 } else 2763 banks[1] |= MCI_STATUS_OVER; 2764 return 0; 2765 } 2766 2767 static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu, 2768 struct kvm_vcpu_events *events) 2769 { 2770 process_nmi(vcpu); 2771 events->exception.injected = 2772 vcpu->arch.exception.pending && 2773 !kvm_exception_is_soft(vcpu->arch.exception.nr); 2774 events->exception.nr = vcpu->arch.exception.nr; 2775 events->exception.has_error_code = vcpu->arch.exception.has_error_code; 2776 events->exception.pad = 0; 2777 events->exception.error_code = vcpu->arch.exception.error_code; 2778 2779 events->interrupt.injected = 2780 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft; 2781 events->interrupt.nr = vcpu->arch.interrupt.nr; 2782 events->interrupt.soft = 0; 2783 events->interrupt.shadow = kvm_x86_ops->get_interrupt_shadow(vcpu); 2784 2785 events->nmi.injected = vcpu->arch.nmi_injected; 2786 events->nmi.pending = vcpu->arch.nmi_pending != 0; 2787 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu); 2788 events->nmi.pad = 0; 2789 2790 events->sipi_vector = 0; /* never valid when reporting to user space */ 2791 2792 events->smi.smm = is_smm(vcpu); 2793 events->smi.pending = vcpu->arch.smi_pending; 2794 events->smi.smm_inside_nmi = 2795 !!(vcpu->arch.hflags & HF_SMM_INSIDE_NMI_MASK); 2796 events->smi.latched_init = kvm_lapic_latched_init(vcpu); 2797 2798 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING 2799 | KVM_VCPUEVENT_VALID_SHADOW 2800 | KVM_VCPUEVENT_VALID_SMM); 2801 memset(&events->reserved, 0, sizeof(events->reserved)); 2802 } 2803 2804 static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu, 2805 struct kvm_vcpu_events *events) 2806 { 2807 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING 2808 | KVM_VCPUEVENT_VALID_SIPI_VECTOR 2809 | KVM_VCPUEVENT_VALID_SHADOW 2810 | KVM_VCPUEVENT_VALID_SMM)) 2811 return -EINVAL; 2812 2813 process_nmi(vcpu); 2814 vcpu->arch.exception.pending = events->exception.injected; 2815 vcpu->arch.exception.nr = events->exception.nr; 2816 vcpu->arch.exception.has_error_code = events->exception.has_error_code; 2817 vcpu->arch.exception.error_code = events->exception.error_code; 2818 2819 vcpu->arch.interrupt.pending = events->interrupt.injected; 2820 vcpu->arch.interrupt.nr = events->interrupt.nr; 2821 vcpu->arch.interrupt.soft = events->interrupt.soft; 2822 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW) 2823 kvm_x86_ops->set_interrupt_shadow(vcpu, 2824 events->interrupt.shadow); 2825 2826 vcpu->arch.nmi_injected = events->nmi.injected; 2827 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING) 2828 vcpu->arch.nmi_pending = events->nmi.pending; 2829 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked); 2830 2831 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR && 2832 kvm_vcpu_has_lapic(vcpu)) 2833 vcpu->arch.apic->sipi_vector = events->sipi_vector; 2834 2835 if (events->flags & KVM_VCPUEVENT_VALID_SMM) { 2836 if (events->smi.smm) 2837 vcpu->arch.hflags |= HF_SMM_MASK; 2838 else 2839 vcpu->arch.hflags &= ~HF_SMM_MASK; 2840 vcpu->arch.smi_pending = events->smi.pending; 2841 if (events->smi.smm_inside_nmi) 2842 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK; 2843 else 2844 vcpu->arch.hflags &= ~HF_SMM_INSIDE_NMI_MASK; 2845 if (kvm_vcpu_has_lapic(vcpu)) { 2846 if (events->smi.latched_init) 2847 set_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events); 2848 else 2849 clear_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events); 2850 } 2851 } 2852 2853 kvm_make_request(KVM_REQ_EVENT, vcpu); 2854 2855 return 0; 2856 } 2857 2858 static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu, 2859 struct kvm_debugregs *dbgregs) 2860 { 2861 unsigned long val; 2862 2863 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db)); 2864 kvm_get_dr(vcpu, 6, &val); 2865 dbgregs->dr6 = val; 2866 dbgregs->dr7 = vcpu->arch.dr7; 2867 dbgregs->flags = 0; 2868 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved)); 2869 } 2870 2871 static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu, 2872 struct kvm_debugregs *dbgregs) 2873 { 2874 if (dbgregs->flags) 2875 return -EINVAL; 2876 2877 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db)); 2878 kvm_update_dr0123(vcpu); 2879 vcpu->arch.dr6 = dbgregs->dr6; 2880 kvm_update_dr6(vcpu); 2881 vcpu->arch.dr7 = dbgregs->dr7; 2882 kvm_update_dr7(vcpu); 2883 2884 return 0; 2885 } 2886 2887 #define XSTATE_COMPACTION_ENABLED (1ULL << 63) 2888 2889 static void fill_xsave(u8 *dest, struct kvm_vcpu *vcpu) 2890 { 2891 struct xregs_state *xsave = &vcpu->arch.guest_fpu.state.xsave; 2892 u64 xstate_bv = xsave->header.xfeatures; 2893 u64 valid; 2894 2895 /* 2896 * Copy legacy XSAVE area, to avoid complications with CPUID 2897 * leaves 0 and 1 in the loop below. 2898 */ 2899 memcpy(dest, xsave, XSAVE_HDR_OFFSET); 2900 2901 /* Set XSTATE_BV */ 2902 *(u64 *)(dest + XSAVE_HDR_OFFSET) = xstate_bv; 2903 2904 /* 2905 * Copy each region from the possibly compacted offset to the 2906 * non-compacted offset. 2907 */ 2908 valid = xstate_bv & ~XSTATE_FPSSE; 2909 while (valid) { 2910 u64 feature = valid & -valid; 2911 int index = fls64(feature) - 1; 2912 void *src = get_xsave_addr(xsave, feature); 2913 2914 if (src) { 2915 u32 size, offset, ecx, edx; 2916 cpuid_count(XSTATE_CPUID, index, 2917 &size, &offset, &ecx, &edx); 2918 memcpy(dest + offset, src, size); 2919 } 2920 2921 valid -= feature; 2922 } 2923 } 2924 2925 static void load_xsave(struct kvm_vcpu *vcpu, u8 *src) 2926 { 2927 struct xregs_state *xsave = &vcpu->arch.guest_fpu.state.xsave; 2928 u64 xstate_bv = *(u64 *)(src + XSAVE_HDR_OFFSET); 2929 u64 valid; 2930 2931 /* 2932 * Copy legacy XSAVE area, to avoid complications with CPUID 2933 * leaves 0 and 1 in the loop below. 2934 */ 2935 memcpy(xsave, src, XSAVE_HDR_OFFSET); 2936 2937 /* Set XSTATE_BV and possibly XCOMP_BV. */ 2938 xsave->header.xfeatures = xstate_bv; 2939 if (cpu_has_xsaves) 2940 xsave->header.xcomp_bv = host_xcr0 | XSTATE_COMPACTION_ENABLED; 2941 2942 /* 2943 * Copy each region from the non-compacted offset to the 2944 * possibly compacted offset. 2945 */ 2946 valid = xstate_bv & ~XSTATE_FPSSE; 2947 while (valid) { 2948 u64 feature = valid & -valid; 2949 int index = fls64(feature) - 1; 2950 void *dest = get_xsave_addr(xsave, feature); 2951 2952 if (dest) { 2953 u32 size, offset, ecx, edx; 2954 cpuid_count(XSTATE_CPUID, index, 2955 &size, &offset, &ecx, &edx); 2956 memcpy(dest, src + offset, size); 2957 } 2958 2959 valid -= feature; 2960 } 2961 } 2962 2963 static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu, 2964 struct kvm_xsave *guest_xsave) 2965 { 2966 if (cpu_has_xsave) { 2967 memset(guest_xsave, 0, sizeof(struct kvm_xsave)); 2968 fill_xsave((u8 *) guest_xsave->region, vcpu); 2969 } else { 2970 memcpy(guest_xsave->region, 2971 &vcpu->arch.guest_fpu.state.fxsave, 2972 sizeof(struct fxregs_state)); 2973 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] = 2974 XSTATE_FPSSE; 2975 } 2976 } 2977 2978 static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu, 2979 struct kvm_xsave *guest_xsave) 2980 { 2981 u64 xstate_bv = 2982 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)]; 2983 2984 if (cpu_has_xsave) { 2985 /* 2986 * Here we allow setting states that are not present in 2987 * CPUID leaf 0xD, index 0, EDX:EAX. This is for compatibility 2988 * with old userspace. 2989 */ 2990 if (xstate_bv & ~kvm_supported_xcr0()) 2991 return -EINVAL; 2992 load_xsave(vcpu, (u8 *)guest_xsave->region); 2993 } else { 2994 if (xstate_bv & ~XSTATE_FPSSE) 2995 return -EINVAL; 2996 memcpy(&vcpu->arch.guest_fpu.state.fxsave, 2997 guest_xsave->region, sizeof(struct fxregs_state)); 2998 } 2999 return 0; 3000 } 3001 3002 static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu, 3003 struct kvm_xcrs *guest_xcrs) 3004 { 3005 if (!cpu_has_xsave) { 3006 guest_xcrs->nr_xcrs = 0; 3007 return; 3008 } 3009 3010 guest_xcrs->nr_xcrs = 1; 3011 guest_xcrs->flags = 0; 3012 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK; 3013 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0; 3014 } 3015 3016 static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu, 3017 struct kvm_xcrs *guest_xcrs) 3018 { 3019 int i, r = 0; 3020 3021 if (!cpu_has_xsave) 3022 return -EINVAL; 3023 3024 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags) 3025 return -EINVAL; 3026 3027 for (i = 0; i < guest_xcrs->nr_xcrs; i++) 3028 /* Only support XCR0 currently */ 3029 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) { 3030 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK, 3031 guest_xcrs->xcrs[i].value); 3032 break; 3033 } 3034 if (r) 3035 r = -EINVAL; 3036 return r; 3037 } 3038 3039 /* 3040 * kvm_set_guest_paused() indicates to the guest kernel that it has been 3041 * stopped by the hypervisor. This function will be called from the host only. 3042 * EINVAL is returned when the host attempts to set the flag for a guest that 3043 * does not support pv clocks. 3044 */ 3045 static int kvm_set_guest_paused(struct kvm_vcpu *vcpu) 3046 { 3047 if (!vcpu->arch.pv_time_enabled) 3048 return -EINVAL; 3049 vcpu->arch.pvclock_set_guest_stopped_request = true; 3050 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 3051 return 0; 3052 } 3053 3054 long kvm_arch_vcpu_ioctl(struct file *filp, 3055 unsigned int ioctl, unsigned long arg) 3056 { 3057 struct kvm_vcpu *vcpu = filp->private_data; 3058 void __user *argp = (void __user *)arg; 3059 int r; 3060 union { 3061 struct kvm_lapic_state *lapic; 3062 struct kvm_xsave *xsave; 3063 struct kvm_xcrs *xcrs; 3064 void *buffer; 3065 } u; 3066 3067 u.buffer = NULL; 3068 switch (ioctl) { 3069 case KVM_GET_LAPIC: { 3070 r = -EINVAL; 3071 if (!vcpu->arch.apic) 3072 goto out; 3073 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL); 3074 3075 r = -ENOMEM; 3076 if (!u.lapic) 3077 goto out; 3078 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic); 3079 if (r) 3080 goto out; 3081 r = -EFAULT; 3082 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state))) 3083 goto out; 3084 r = 0; 3085 break; 3086 } 3087 case KVM_SET_LAPIC: { 3088 r = -EINVAL; 3089 if (!vcpu->arch.apic) 3090 goto out; 3091 u.lapic = memdup_user(argp, sizeof(*u.lapic)); 3092 if (IS_ERR(u.lapic)) 3093 return PTR_ERR(u.lapic); 3094 3095 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic); 3096 break; 3097 } 3098 case KVM_INTERRUPT: { 3099 struct kvm_interrupt irq; 3100 3101 r = -EFAULT; 3102 if (copy_from_user(&irq, argp, sizeof irq)) 3103 goto out; 3104 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq); 3105 break; 3106 } 3107 case KVM_NMI: { 3108 r = kvm_vcpu_ioctl_nmi(vcpu); 3109 break; 3110 } 3111 case KVM_SMI: { 3112 r = kvm_vcpu_ioctl_smi(vcpu); 3113 break; 3114 } 3115 case KVM_SET_CPUID: { 3116 struct kvm_cpuid __user *cpuid_arg = argp; 3117 struct kvm_cpuid cpuid; 3118 3119 r = -EFAULT; 3120 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid)) 3121 goto out; 3122 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries); 3123 break; 3124 } 3125 case KVM_SET_CPUID2: { 3126 struct kvm_cpuid2 __user *cpuid_arg = argp; 3127 struct kvm_cpuid2 cpuid; 3128 3129 r = -EFAULT; 3130 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid)) 3131 goto out; 3132 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid, 3133 cpuid_arg->entries); 3134 break; 3135 } 3136 case KVM_GET_CPUID2: { 3137 struct kvm_cpuid2 __user *cpuid_arg = argp; 3138 struct kvm_cpuid2 cpuid; 3139 3140 r = -EFAULT; 3141 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid)) 3142 goto out; 3143 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid, 3144 cpuid_arg->entries); 3145 if (r) 3146 goto out; 3147 r = -EFAULT; 3148 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid)) 3149 goto out; 3150 r = 0; 3151 break; 3152 } 3153 case KVM_GET_MSRS: 3154 r = msr_io(vcpu, argp, do_get_msr, 1); 3155 break; 3156 case KVM_SET_MSRS: 3157 r = msr_io(vcpu, argp, do_set_msr, 0); 3158 break; 3159 case KVM_TPR_ACCESS_REPORTING: { 3160 struct kvm_tpr_access_ctl tac; 3161 3162 r = -EFAULT; 3163 if (copy_from_user(&tac, argp, sizeof tac)) 3164 goto out; 3165 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac); 3166 if (r) 3167 goto out; 3168 r = -EFAULT; 3169 if (copy_to_user(argp, &tac, sizeof tac)) 3170 goto out; 3171 r = 0; 3172 break; 3173 }; 3174 case KVM_SET_VAPIC_ADDR: { 3175 struct kvm_vapic_addr va; 3176 3177 r = -EINVAL; 3178 if (!irqchip_in_kernel(vcpu->kvm)) 3179 goto out; 3180 r = -EFAULT; 3181 if (copy_from_user(&va, argp, sizeof va)) 3182 goto out; 3183 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr); 3184 break; 3185 } 3186 case KVM_X86_SETUP_MCE: { 3187 u64 mcg_cap; 3188 3189 r = -EFAULT; 3190 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap)) 3191 goto out; 3192 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap); 3193 break; 3194 } 3195 case KVM_X86_SET_MCE: { 3196 struct kvm_x86_mce mce; 3197 3198 r = -EFAULT; 3199 if (copy_from_user(&mce, argp, sizeof mce)) 3200 goto out; 3201 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce); 3202 break; 3203 } 3204 case KVM_GET_VCPU_EVENTS: { 3205 struct kvm_vcpu_events events; 3206 3207 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events); 3208 3209 r = -EFAULT; 3210 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events))) 3211 break; 3212 r = 0; 3213 break; 3214 } 3215 case KVM_SET_VCPU_EVENTS: { 3216 struct kvm_vcpu_events events; 3217 3218 r = -EFAULT; 3219 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events))) 3220 break; 3221 3222 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events); 3223 break; 3224 } 3225 case KVM_GET_DEBUGREGS: { 3226 struct kvm_debugregs dbgregs; 3227 3228 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs); 3229 3230 r = -EFAULT; 3231 if (copy_to_user(argp, &dbgregs, 3232 sizeof(struct kvm_debugregs))) 3233 break; 3234 r = 0; 3235 break; 3236 } 3237 case KVM_SET_DEBUGREGS: { 3238 struct kvm_debugregs dbgregs; 3239 3240 r = -EFAULT; 3241 if (copy_from_user(&dbgregs, argp, 3242 sizeof(struct kvm_debugregs))) 3243 break; 3244 3245 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs); 3246 break; 3247 } 3248 case KVM_GET_XSAVE: { 3249 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL); 3250 r = -ENOMEM; 3251 if (!u.xsave) 3252 break; 3253 3254 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave); 3255 3256 r = -EFAULT; 3257 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave))) 3258 break; 3259 r = 0; 3260 break; 3261 } 3262 case KVM_SET_XSAVE: { 3263 u.xsave = memdup_user(argp, sizeof(*u.xsave)); 3264 if (IS_ERR(u.xsave)) 3265 return PTR_ERR(u.xsave); 3266 3267 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave); 3268 break; 3269 } 3270 case KVM_GET_XCRS: { 3271 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL); 3272 r = -ENOMEM; 3273 if (!u.xcrs) 3274 break; 3275 3276 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs); 3277 3278 r = -EFAULT; 3279 if (copy_to_user(argp, u.xcrs, 3280 sizeof(struct kvm_xcrs))) 3281 break; 3282 r = 0; 3283 break; 3284 } 3285 case KVM_SET_XCRS: { 3286 u.xcrs = memdup_user(argp, sizeof(*u.xcrs)); 3287 if (IS_ERR(u.xcrs)) 3288 return PTR_ERR(u.xcrs); 3289 3290 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs); 3291 break; 3292 } 3293 case KVM_SET_TSC_KHZ: { 3294 u32 user_tsc_khz; 3295 3296 r = -EINVAL; 3297 user_tsc_khz = (u32)arg; 3298 3299 if (user_tsc_khz >= kvm_max_guest_tsc_khz) 3300 goto out; 3301 3302 if (user_tsc_khz == 0) 3303 user_tsc_khz = tsc_khz; 3304 3305 kvm_set_tsc_khz(vcpu, user_tsc_khz); 3306 3307 r = 0; 3308 goto out; 3309 } 3310 case KVM_GET_TSC_KHZ: { 3311 r = vcpu->arch.virtual_tsc_khz; 3312 goto out; 3313 } 3314 case KVM_KVMCLOCK_CTRL: { 3315 r = kvm_set_guest_paused(vcpu); 3316 goto out; 3317 } 3318 default: 3319 r = -EINVAL; 3320 } 3321 out: 3322 kfree(u.buffer); 3323 return r; 3324 } 3325 3326 int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf) 3327 { 3328 return VM_FAULT_SIGBUS; 3329 } 3330 3331 static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr) 3332 { 3333 int ret; 3334 3335 if (addr > (unsigned int)(-3 * PAGE_SIZE)) 3336 return -EINVAL; 3337 ret = kvm_x86_ops->set_tss_addr(kvm, addr); 3338 return ret; 3339 } 3340 3341 static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm, 3342 u64 ident_addr) 3343 { 3344 kvm->arch.ept_identity_map_addr = ident_addr; 3345 return 0; 3346 } 3347 3348 static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm, 3349 u32 kvm_nr_mmu_pages) 3350 { 3351 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES) 3352 return -EINVAL; 3353 3354 mutex_lock(&kvm->slots_lock); 3355 3356 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages); 3357 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages; 3358 3359 mutex_unlock(&kvm->slots_lock); 3360 return 0; 3361 } 3362 3363 static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm) 3364 { 3365 return kvm->arch.n_max_mmu_pages; 3366 } 3367 3368 static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip) 3369 { 3370 int r; 3371 3372 r = 0; 3373 switch (chip->chip_id) { 3374 case KVM_IRQCHIP_PIC_MASTER: 3375 memcpy(&chip->chip.pic, 3376 &pic_irqchip(kvm)->pics[0], 3377 sizeof(struct kvm_pic_state)); 3378 break; 3379 case KVM_IRQCHIP_PIC_SLAVE: 3380 memcpy(&chip->chip.pic, 3381 &pic_irqchip(kvm)->pics[1], 3382 sizeof(struct kvm_pic_state)); 3383 break; 3384 case KVM_IRQCHIP_IOAPIC: 3385 r = kvm_get_ioapic(kvm, &chip->chip.ioapic); 3386 break; 3387 default: 3388 r = -EINVAL; 3389 break; 3390 } 3391 return r; 3392 } 3393 3394 static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip) 3395 { 3396 int r; 3397 3398 r = 0; 3399 switch (chip->chip_id) { 3400 case KVM_IRQCHIP_PIC_MASTER: 3401 spin_lock(&pic_irqchip(kvm)->lock); 3402 memcpy(&pic_irqchip(kvm)->pics[0], 3403 &chip->chip.pic, 3404 sizeof(struct kvm_pic_state)); 3405 spin_unlock(&pic_irqchip(kvm)->lock); 3406 break; 3407 case KVM_IRQCHIP_PIC_SLAVE: 3408 spin_lock(&pic_irqchip(kvm)->lock); 3409 memcpy(&pic_irqchip(kvm)->pics[1], 3410 &chip->chip.pic, 3411 sizeof(struct kvm_pic_state)); 3412 spin_unlock(&pic_irqchip(kvm)->lock); 3413 break; 3414 case KVM_IRQCHIP_IOAPIC: 3415 r = kvm_set_ioapic(kvm, &chip->chip.ioapic); 3416 break; 3417 default: 3418 r = -EINVAL; 3419 break; 3420 } 3421 kvm_pic_update_irq(pic_irqchip(kvm)); 3422 return r; 3423 } 3424 3425 static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps) 3426 { 3427 int r = 0; 3428 3429 mutex_lock(&kvm->arch.vpit->pit_state.lock); 3430 memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state)); 3431 mutex_unlock(&kvm->arch.vpit->pit_state.lock); 3432 return r; 3433 } 3434 3435 static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps) 3436 { 3437 int r = 0; 3438 3439 mutex_lock(&kvm->arch.vpit->pit_state.lock); 3440 memcpy(&kvm->arch.vpit->pit_state, ps, sizeof(struct kvm_pit_state)); 3441 kvm_pit_load_count(kvm, 0, ps->channels[0].count, 0); 3442 mutex_unlock(&kvm->arch.vpit->pit_state.lock); 3443 return r; 3444 } 3445 3446 static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps) 3447 { 3448 int r = 0; 3449 3450 mutex_lock(&kvm->arch.vpit->pit_state.lock); 3451 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels, 3452 sizeof(ps->channels)); 3453 ps->flags = kvm->arch.vpit->pit_state.flags; 3454 mutex_unlock(&kvm->arch.vpit->pit_state.lock); 3455 memset(&ps->reserved, 0, sizeof(ps->reserved)); 3456 return r; 3457 } 3458 3459 static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps) 3460 { 3461 int r = 0, start = 0; 3462 u32 prev_legacy, cur_legacy; 3463 mutex_lock(&kvm->arch.vpit->pit_state.lock); 3464 prev_legacy = kvm->arch.vpit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY; 3465 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY; 3466 if (!prev_legacy && cur_legacy) 3467 start = 1; 3468 memcpy(&kvm->arch.vpit->pit_state.channels, &ps->channels, 3469 sizeof(kvm->arch.vpit->pit_state.channels)); 3470 kvm->arch.vpit->pit_state.flags = ps->flags; 3471 kvm_pit_load_count(kvm, 0, kvm->arch.vpit->pit_state.channels[0].count, start); 3472 mutex_unlock(&kvm->arch.vpit->pit_state.lock); 3473 return r; 3474 } 3475 3476 static int kvm_vm_ioctl_reinject(struct kvm *kvm, 3477 struct kvm_reinject_control *control) 3478 { 3479 if (!kvm->arch.vpit) 3480 return -ENXIO; 3481 mutex_lock(&kvm->arch.vpit->pit_state.lock); 3482 kvm->arch.vpit->pit_state.reinject = control->pit_reinject; 3483 mutex_unlock(&kvm->arch.vpit->pit_state.lock); 3484 return 0; 3485 } 3486 3487 /** 3488 * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot 3489 * @kvm: kvm instance 3490 * @log: slot id and address to which we copy the log 3491 * 3492 * Steps 1-4 below provide general overview of dirty page logging. See 3493 * kvm_get_dirty_log_protect() function description for additional details. 3494 * 3495 * We call kvm_get_dirty_log_protect() to handle steps 1-3, upon return we 3496 * always flush the TLB (step 4) even if previous step failed and the dirty 3497 * bitmap may be corrupt. Regardless of previous outcome the KVM logging API 3498 * does not preclude user space subsequent dirty log read. Flushing TLB ensures 3499 * writes will be marked dirty for next log read. 3500 * 3501 * 1. Take a snapshot of the bit and clear it if needed. 3502 * 2. Write protect the corresponding page. 3503 * 3. Copy the snapshot to the userspace. 3504 * 4. Flush TLB's if needed. 3505 */ 3506 int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log) 3507 { 3508 bool is_dirty = false; 3509 int r; 3510 3511 mutex_lock(&kvm->slots_lock); 3512 3513 /* 3514 * Flush potentially hardware-cached dirty pages to dirty_bitmap. 3515 */ 3516 if (kvm_x86_ops->flush_log_dirty) 3517 kvm_x86_ops->flush_log_dirty(kvm); 3518 3519 r = kvm_get_dirty_log_protect(kvm, log, &is_dirty); 3520 3521 /* 3522 * All the TLBs can be flushed out of mmu lock, see the comments in 3523 * kvm_mmu_slot_remove_write_access(). 3524 */ 3525 lockdep_assert_held(&kvm->slots_lock); 3526 if (is_dirty) 3527 kvm_flush_remote_tlbs(kvm); 3528 3529 mutex_unlock(&kvm->slots_lock); 3530 return r; 3531 } 3532 3533 int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event, 3534 bool line_status) 3535 { 3536 if (!irqchip_in_kernel(kvm)) 3537 return -ENXIO; 3538 3539 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID, 3540 irq_event->irq, irq_event->level, 3541 line_status); 3542 return 0; 3543 } 3544 3545 static int kvm_vm_ioctl_enable_cap(struct kvm *kvm, 3546 struct kvm_enable_cap *cap) 3547 { 3548 int r; 3549 3550 if (cap->flags) 3551 return -EINVAL; 3552 3553 switch (cap->cap) { 3554 case KVM_CAP_DISABLE_QUIRKS: 3555 kvm->arch.disabled_quirks = cap->args[0]; 3556 r = 0; 3557 break; 3558 default: 3559 r = -EINVAL; 3560 break; 3561 } 3562 return r; 3563 } 3564 3565 long kvm_arch_vm_ioctl(struct file *filp, 3566 unsigned int ioctl, unsigned long arg) 3567 { 3568 struct kvm *kvm = filp->private_data; 3569 void __user *argp = (void __user *)arg; 3570 int r = -ENOTTY; 3571 /* 3572 * This union makes it completely explicit to gcc-3.x 3573 * that these two variables' stack usage should be 3574 * combined, not added together. 3575 */ 3576 union { 3577 struct kvm_pit_state ps; 3578 struct kvm_pit_state2 ps2; 3579 struct kvm_pit_config pit_config; 3580 } u; 3581 3582 switch (ioctl) { 3583 case KVM_SET_TSS_ADDR: 3584 r = kvm_vm_ioctl_set_tss_addr(kvm, arg); 3585 break; 3586 case KVM_SET_IDENTITY_MAP_ADDR: { 3587 u64 ident_addr; 3588 3589 r = -EFAULT; 3590 if (copy_from_user(&ident_addr, argp, sizeof ident_addr)) 3591 goto out; 3592 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr); 3593 break; 3594 } 3595 case KVM_SET_NR_MMU_PAGES: 3596 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg); 3597 break; 3598 case KVM_GET_NR_MMU_PAGES: 3599 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm); 3600 break; 3601 case KVM_CREATE_IRQCHIP: { 3602 struct kvm_pic *vpic; 3603 3604 mutex_lock(&kvm->lock); 3605 r = -EEXIST; 3606 if (kvm->arch.vpic) 3607 goto create_irqchip_unlock; 3608 r = -EINVAL; 3609 if (atomic_read(&kvm->online_vcpus)) 3610 goto create_irqchip_unlock; 3611 r = -ENOMEM; 3612 vpic = kvm_create_pic(kvm); 3613 if (vpic) { 3614 r = kvm_ioapic_init(kvm); 3615 if (r) { 3616 mutex_lock(&kvm->slots_lock); 3617 kvm_destroy_pic(vpic); 3618 mutex_unlock(&kvm->slots_lock); 3619 goto create_irqchip_unlock; 3620 } 3621 } else 3622 goto create_irqchip_unlock; 3623 r = kvm_setup_default_irq_routing(kvm); 3624 if (r) { 3625 mutex_lock(&kvm->slots_lock); 3626 mutex_lock(&kvm->irq_lock); 3627 kvm_ioapic_destroy(kvm); 3628 kvm_destroy_pic(vpic); 3629 mutex_unlock(&kvm->irq_lock); 3630 mutex_unlock(&kvm->slots_lock); 3631 goto create_irqchip_unlock; 3632 } 3633 /* Write kvm->irq_routing before kvm->arch.vpic. */ 3634 smp_wmb(); 3635 kvm->arch.vpic = vpic; 3636 create_irqchip_unlock: 3637 mutex_unlock(&kvm->lock); 3638 break; 3639 } 3640 case KVM_CREATE_PIT: 3641 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY; 3642 goto create_pit; 3643 case KVM_CREATE_PIT2: 3644 r = -EFAULT; 3645 if (copy_from_user(&u.pit_config, argp, 3646 sizeof(struct kvm_pit_config))) 3647 goto out; 3648 create_pit: 3649 mutex_lock(&kvm->slots_lock); 3650 r = -EEXIST; 3651 if (kvm->arch.vpit) 3652 goto create_pit_unlock; 3653 r = -ENOMEM; 3654 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags); 3655 if (kvm->arch.vpit) 3656 r = 0; 3657 create_pit_unlock: 3658 mutex_unlock(&kvm->slots_lock); 3659 break; 3660 case KVM_GET_IRQCHIP: { 3661 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */ 3662 struct kvm_irqchip *chip; 3663 3664 chip = memdup_user(argp, sizeof(*chip)); 3665 if (IS_ERR(chip)) { 3666 r = PTR_ERR(chip); 3667 goto out; 3668 } 3669 3670 r = -ENXIO; 3671 if (!irqchip_in_kernel(kvm)) 3672 goto get_irqchip_out; 3673 r = kvm_vm_ioctl_get_irqchip(kvm, chip); 3674 if (r) 3675 goto get_irqchip_out; 3676 r = -EFAULT; 3677 if (copy_to_user(argp, chip, sizeof *chip)) 3678 goto get_irqchip_out; 3679 r = 0; 3680 get_irqchip_out: 3681 kfree(chip); 3682 break; 3683 } 3684 case KVM_SET_IRQCHIP: { 3685 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */ 3686 struct kvm_irqchip *chip; 3687 3688 chip = memdup_user(argp, sizeof(*chip)); 3689 if (IS_ERR(chip)) { 3690 r = PTR_ERR(chip); 3691 goto out; 3692 } 3693 3694 r = -ENXIO; 3695 if (!irqchip_in_kernel(kvm)) 3696 goto set_irqchip_out; 3697 r = kvm_vm_ioctl_set_irqchip(kvm, chip); 3698 if (r) 3699 goto set_irqchip_out; 3700 r = 0; 3701 set_irqchip_out: 3702 kfree(chip); 3703 break; 3704 } 3705 case KVM_GET_PIT: { 3706 r = -EFAULT; 3707 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state))) 3708 goto out; 3709 r = -ENXIO; 3710 if (!kvm->arch.vpit) 3711 goto out; 3712 r = kvm_vm_ioctl_get_pit(kvm, &u.ps); 3713 if (r) 3714 goto out; 3715 r = -EFAULT; 3716 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state))) 3717 goto out; 3718 r = 0; 3719 break; 3720 } 3721 case KVM_SET_PIT: { 3722 r = -EFAULT; 3723 if (copy_from_user(&u.ps, argp, sizeof u.ps)) 3724 goto out; 3725 r = -ENXIO; 3726 if (!kvm->arch.vpit) 3727 goto out; 3728 r = kvm_vm_ioctl_set_pit(kvm, &u.ps); 3729 break; 3730 } 3731 case KVM_GET_PIT2: { 3732 r = -ENXIO; 3733 if (!kvm->arch.vpit) 3734 goto out; 3735 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2); 3736 if (r) 3737 goto out; 3738 r = -EFAULT; 3739 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2))) 3740 goto out; 3741 r = 0; 3742 break; 3743 } 3744 case KVM_SET_PIT2: { 3745 r = -EFAULT; 3746 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2))) 3747 goto out; 3748 r = -ENXIO; 3749 if (!kvm->arch.vpit) 3750 goto out; 3751 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2); 3752 break; 3753 } 3754 case KVM_REINJECT_CONTROL: { 3755 struct kvm_reinject_control control; 3756 r = -EFAULT; 3757 if (copy_from_user(&control, argp, sizeof(control))) 3758 goto out; 3759 r = kvm_vm_ioctl_reinject(kvm, &control); 3760 break; 3761 } 3762 case KVM_SET_BOOT_CPU_ID: 3763 r = 0; 3764 mutex_lock(&kvm->lock); 3765 if (atomic_read(&kvm->online_vcpus) != 0) 3766 r = -EBUSY; 3767 else 3768 kvm->arch.bsp_vcpu_id = arg; 3769 mutex_unlock(&kvm->lock); 3770 break; 3771 case KVM_XEN_HVM_CONFIG: { 3772 r = -EFAULT; 3773 if (copy_from_user(&kvm->arch.xen_hvm_config, argp, 3774 sizeof(struct kvm_xen_hvm_config))) 3775 goto out; 3776 r = -EINVAL; 3777 if (kvm->arch.xen_hvm_config.flags) 3778 goto out; 3779 r = 0; 3780 break; 3781 } 3782 case KVM_SET_CLOCK: { 3783 struct kvm_clock_data user_ns; 3784 u64 now_ns; 3785 s64 delta; 3786 3787 r = -EFAULT; 3788 if (copy_from_user(&user_ns, argp, sizeof(user_ns))) 3789 goto out; 3790 3791 r = -EINVAL; 3792 if (user_ns.flags) 3793 goto out; 3794 3795 r = 0; 3796 local_irq_disable(); 3797 now_ns = get_kernel_ns(); 3798 delta = user_ns.clock - now_ns; 3799 local_irq_enable(); 3800 kvm->arch.kvmclock_offset = delta; 3801 kvm_gen_update_masterclock(kvm); 3802 break; 3803 } 3804 case KVM_GET_CLOCK: { 3805 struct kvm_clock_data user_ns; 3806 u64 now_ns; 3807 3808 local_irq_disable(); 3809 now_ns = get_kernel_ns(); 3810 user_ns.clock = kvm->arch.kvmclock_offset + now_ns; 3811 local_irq_enable(); 3812 user_ns.flags = 0; 3813 memset(&user_ns.pad, 0, sizeof(user_ns.pad)); 3814 3815 r = -EFAULT; 3816 if (copy_to_user(argp, &user_ns, sizeof(user_ns))) 3817 goto out; 3818 r = 0; 3819 break; 3820 } 3821 case KVM_ENABLE_CAP: { 3822 struct kvm_enable_cap cap; 3823 3824 r = -EFAULT; 3825 if (copy_from_user(&cap, argp, sizeof(cap))) 3826 goto out; 3827 r = kvm_vm_ioctl_enable_cap(kvm, &cap); 3828 break; 3829 } 3830 default: 3831 r = kvm_vm_ioctl_assigned_device(kvm, ioctl, arg); 3832 } 3833 out: 3834 return r; 3835 } 3836 3837 static void kvm_init_msr_list(void) 3838 { 3839 u32 dummy[2]; 3840 unsigned i, j; 3841 3842 for (i = j = 0; i < ARRAY_SIZE(msrs_to_save); i++) { 3843 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0) 3844 continue; 3845 3846 /* 3847 * Even MSRs that are valid in the host may not be exposed 3848 * to the guests in some cases. We could work around this 3849 * in VMX with the generic MSR save/load machinery, but it 3850 * is not really worthwhile since it will really only 3851 * happen with nested virtualization. 3852 */ 3853 switch (msrs_to_save[i]) { 3854 case MSR_IA32_BNDCFGS: 3855 if (!kvm_x86_ops->mpx_supported()) 3856 continue; 3857 break; 3858 default: 3859 break; 3860 } 3861 3862 if (j < i) 3863 msrs_to_save[j] = msrs_to_save[i]; 3864 j++; 3865 } 3866 num_msrs_to_save = j; 3867 3868 for (i = j = 0; i < ARRAY_SIZE(emulated_msrs); i++) { 3869 switch (emulated_msrs[i]) { 3870 case MSR_IA32_SMBASE: 3871 if (!kvm_x86_ops->cpu_has_high_real_mode_segbase()) 3872 continue; 3873 break; 3874 default: 3875 break; 3876 } 3877 3878 if (j < i) 3879 emulated_msrs[j] = emulated_msrs[i]; 3880 j++; 3881 } 3882 num_emulated_msrs = j; 3883 } 3884 3885 static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len, 3886 const void *v) 3887 { 3888 int handled = 0; 3889 int n; 3890 3891 do { 3892 n = min(len, 8); 3893 if (!(vcpu->arch.apic && 3894 !kvm_iodevice_write(vcpu, &vcpu->arch.apic->dev, addr, n, v)) 3895 && kvm_io_bus_write(vcpu, KVM_MMIO_BUS, addr, n, v)) 3896 break; 3897 handled += n; 3898 addr += n; 3899 len -= n; 3900 v += n; 3901 } while (len); 3902 3903 return handled; 3904 } 3905 3906 static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v) 3907 { 3908 int handled = 0; 3909 int n; 3910 3911 do { 3912 n = min(len, 8); 3913 if (!(vcpu->arch.apic && 3914 !kvm_iodevice_read(vcpu, &vcpu->arch.apic->dev, 3915 addr, n, v)) 3916 && kvm_io_bus_read(vcpu, KVM_MMIO_BUS, addr, n, v)) 3917 break; 3918 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, *(u64 *)v); 3919 handled += n; 3920 addr += n; 3921 len -= n; 3922 v += n; 3923 } while (len); 3924 3925 return handled; 3926 } 3927 3928 static void kvm_set_segment(struct kvm_vcpu *vcpu, 3929 struct kvm_segment *var, int seg) 3930 { 3931 kvm_x86_ops->set_segment(vcpu, var, seg); 3932 } 3933 3934 void kvm_get_segment(struct kvm_vcpu *vcpu, 3935 struct kvm_segment *var, int seg) 3936 { 3937 kvm_x86_ops->get_segment(vcpu, var, seg); 3938 } 3939 3940 gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access, 3941 struct x86_exception *exception) 3942 { 3943 gpa_t t_gpa; 3944 3945 BUG_ON(!mmu_is_nested(vcpu)); 3946 3947 /* NPT walks are always user-walks */ 3948 access |= PFERR_USER_MASK; 3949 t_gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, exception); 3950 3951 return t_gpa; 3952 } 3953 3954 gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva, 3955 struct x86_exception *exception) 3956 { 3957 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0; 3958 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception); 3959 } 3960 3961 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva, 3962 struct x86_exception *exception) 3963 { 3964 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0; 3965 access |= PFERR_FETCH_MASK; 3966 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception); 3967 } 3968 3969 gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva, 3970 struct x86_exception *exception) 3971 { 3972 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0; 3973 access |= PFERR_WRITE_MASK; 3974 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception); 3975 } 3976 3977 /* uses this to access any guest's mapped memory without checking CPL */ 3978 gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva, 3979 struct x86_exception *exception) 3980 { 3981 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception); 3982 } 3983 3984 static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes, 3985 struct kvm_vcpu *vcpu, u32 access, 3986 struct x86_exception *exception) 3987 { 3988 void *data = val; 3989 int r = X86EMUL_CONTINUE; 3990 3991 while (bytes) { 3992 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access, 3993 exception); 3994 unsigned offset = addr & (PAGE_SIZE-1); 3995 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset); 3996 int ret; 3997 3998 if (gpa == UNMAPPED_GVA) 3999 return X86EMUL_PROPAGATE_FAULT; 4000 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, data, 4001 offset, toread); 4002 if (ret < 0) { 4003 r = X86EMUL_IO_NEEDED; 4004 goto out; 4005 } 4006 4007 bytes -= toread; 4008 data += toread; 4009 addr += toread; 4010 } 4011 out: 4012 return r; 4013 } 4014 4015 /* used for instruction fetching */ 4016 static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt, 4017 gva_t addr, void *val, unsigned int bytes, 4018 struct x86_exception *exception) 4019 { 4020 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 4021 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0; 4022 unsigned offset; 4023 int ret; 4024 4025 /* Inline kvm_read_guest_virt_helper for speed. */ 4026 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access|PFERR_FETCH_MASK, 4027 exception); 4028 if (unlikely(gpa == UNMAPPED_GVA)) 4029 return X86EMUL_PROPAGATE_FAULT; 4030 4031 offset = addr & (PAGE_SIZE-1); 4032 if (WARN_ON(offset + bytes > PAGE_SIZE)) 4033 bytes = (unsigned)PAGE_SIZE - offset; 4034 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, val, 4035 offset, bytes); 4036 if (unlikely(ret < 0)) 4037 return X86EMUL_IO_NEEDED; 4038 4039 return X86EMUL_CONTINUE; 4040 } 4041 4042 int kvm_read_guest_virt(struct x86_emulate_ctxt *ctxt, 4043 gva_t addr, void *val, unsigned int bytes, 4044 struct x86_exception *exception) 4045 { 4046 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 4047 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0; 4048 4049 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access, 4050 exception); 4051 } 4052 EXPORT_SYMBOL_GPL(kvm_read_guest_virt); 4053 4054 static int kvm_read_guest_virt_system(struct x86_emulate_ctxt *ctxt, 4055 gva_t addr, void *val, unsigned int bytes, 4056 struct x86_exception *exception) 4057 { 4058 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 4059 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, exception); 4060 } 4061 4062 int kvm_write_guest_virt_system(struct x86_emulate_ctxt *ctxt, 4063 gva_t addr, void *val, 4064 unsigned int bytes, 4065 struct x86_exception *exception) 4066 { 4067 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 4068 void *data = val; 4069 int r = X86EMUL_CONTINUE; 4070 4071 while (bytes) { 4072 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, 4073 PFERR_WRITE_MASK, 4074 exception); 4075 unsigned offset = addr & (PAGE_SIZE-1); 4076 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset); 4077 int ret; 4078 4079 if (gpa == UNMAPPED_GVA) 4080 return X86EMUL_PROPAGATE_FAULT; 4081 ret = kvm_vcpu_write_guest(vcpu, gpa, data, towrite); 4082 if (ret < 0) { 4083 r = X86EMUL_IO_NEEDED; 4084 goto out; 4085 } 4086 4087 bytes -= towrite; 4088 data += towrite; 4089 addr += towrite; 4090 } 4091 out: 4092 return r; 4093 } 4094 EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system); 4095 4096 static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva, 4097 gpa_t *gpa, struct x86_exception *exception, 4098 bool write) 4099 { 4100 u32 access = ((kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0) 4101 | (write ? PFERR_WRITE_MASK : 0); 4102 4103 if (vcpu_match_mmio_gva(vcpu, gva) 4104 && !permission_fault(vcpu, vcpu->arch.walk_mmu, 4105 vcpu->arch.access, access)) { 4106 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT | 4107 (gva & (PAGE_SIZE - 1)); 4108 trace_vcpu_match_mmio(gva, *gpa, write, false); 4109 return 1; 4110 } 4111 4112 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception); 4113 4114 if (*gpa == UNMAPPED_GVA) 4115 return -1; 4116 4117 /* For APIC access vmexit */ 4118 if ((*gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE) 4119 return 1; 4120 4121 if (vcpu_match_mmio_gpa(vcpu, *gpa)) { 4122 trace_vcpu_match_mmio(gva, *gpa, write, true); 4123 return 1; 4124 } 4125 4126 return 0; 4127 } 4128 4129 int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa, 4130 const void *val, int bytes) 4131 { 4132 int ret; 4133 4134 ret = kvm_vcpu_write_guest(vcpu, gpa, val, bytes); 4135 if (ret < 0) 4136 return 0; 4137 kvm_mmu_pte_write(vcpu, gpa, val, bytes); 4138 return 1; 4139 } 4140 4141 struct read_write_emulator_ops { 4142 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val, 4143 int bytes); 4144 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa, 4145 void *val, int bytes); 4146 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa, 4147 int bytes, void *val); 4148 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa, 4149 void *val, int bytes); 4150 bool write; 4151 }; 4152 4153 static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes) 4154 { 4155 if (vcpu->mmio_read_completed) { 4156 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes, 4157 vcpu->mmio_fragments[0].gpa, *(u64 *)val); 4158 vcpu->mmio_read_completed = 0; 4159 return 1; 4160 } 4161 4162 return 0; 4163 } 4164 4165 static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa, 4166 void *val, int bytes) 4167 { 4168 return !kvm_vcpu_read_guest(vcpu, gpa, val, bytes); 4169 } 4170 4171 static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa, 4172 void *val, int bytes) 4173 { 4174 return emulator_write_phys(vcpu, gpa, val, bytes); 4175 } 4176 4177 static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val) 4178 { 4179 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val); 4180 return vcpu_mmio_write(vcpu, gpa, bytes, val); 4181 } 4182 4183 static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, 4184 void *val, int bytes) 4185 { 4186 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0); 4187 return X86EMUL_IO_NEEDED; 4188 } 4189 4190 static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, 4191 void *val, int bytes) 4192 { 4193 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0]; 4194 4195 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len)); 4196 return X86EMUL_CONTINUE; 4197 } 4198 4199 static const struct read_write_emulator_ops read_emultor = { 4200 .read_write_prepare = read_prepare, 4201 .read_write_emulate = read_emulate, 4202 .read_write_mmio = vcpu_mmio_read, 4203 .read_write_exit_mmio = read_exit_mmio, 4204 }; 4205 4206 static const struct read_write_emulator_ops write_emultor = { 4207 .read_write_emulate = write_emulate, 4208 .read_write_mmio = write_mmio, 4209 .read_write_exit_mmio = write_exit_mmio, 4210 .write = true, 4211 }; 4212 4213 static int emulator_read_write_onepage(unsigned long addr, void *val, 4214 unsigned int bytes, 4215 struct x86_exception *exception, 4216 struct kvm_vcpu *vcpu, 4217 const struct read_write_emulator_ops *ops) 4218 { 4219 gpa_t gpa; 4220 int handled, ret; 4221 bool write = ops->write; 4222 struct kvm_mmio_fragment *frag; 4223 4224 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write); 4225 4226 if (ret < 0) 4227 return X86EMUL_PROPAGATE_FAULT; 4228 4229 /* For APIC access vmexit */ 4230 if (ret) 4231 goto mmio; 4232 4233 if (ops->read_write_emulate(vcpu, gpa, val, bytes)) 4234 return X86EMUL_CONTINUE; 4235 4236 mmio: 4237 /* 4238 * Is this MMIO handled locally? 4239 */ 4240 handled = ops->read_write_mmio(vcpu, gpa, bytes, val); 4241 if (handled == bytes) 4242 return X86EMUL_CONTINUE; 4243 4244 gpa += handled; 4245 bytes -= handled; 4246 val += handled; 4247 4248 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS); 4249 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++]; 4250 frag->gpa = gpa; 4251 frag->data = val; 4252 frag->len = bytes; 4253 return X86EMUL_CONTINUE; 4254 } 4255 4256 static int emulator_read_write(struct x86_emulate_ctxt *ctxt, 4257 unsigned long addr, 4258 void *val, unsigned int bytes, 4259 struct x86_exception *exception, 4260 const struct read_write_emulator_ops *ops) 4261 { 4262 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 4263 gpa_t gpa; 4264 int rc; 4265 4266 if (ops->read_write_prepare && 4267 ops->read_write_prepare(vcpu, val, bytes)) 4268 return X86EMUL_CONTINUE; 4269 4270 vcpu->mmio_nr_fragments = 0; 4271 4272 /* Crossing a page boundary? */ 4273 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) { 4274 int now; 4275 4276 now = -addr & ~PAGE_MASK; 4277 rc = emulator_read_write_onepage(addr, val, now, exception, 4278 vcpu, ops); 4279 4280 if (rc != X86EMUL_CONTINUE) 4281 return rc; 4282 addr += now; 4283 if (ctxt->mode != X86EMUL_MODE_PROT64) 4284 addr = (u32)addr; 4285 val += now; 4286 bytes -= now; 4287 } 4288 4289 rc = emulator_read_write_onepage(addr, val, bytes, exception, 4290 vcpu, ops); 4291 if (rc != X86EMUL_CONTINUE) 4292 return rc; 4293 4294 if (!vcpu->mmio_nr_fragments) 4295 return rc; 4296 4297 gpa = vcpu->mmio_fragments[0].gpa; 4298 4299 vcpu->mmio_needed = 1; 4300 vcpu->mmio_cur_fragment = 0; 4301 4302 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len); 4303 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write; 4304 vcpu->run->exit_reason = KVM_EXIT_MMIO; 4305 vcpu->run->mmio.phys_addr = gpa; 4306 4307 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes); 4308 } 4309 4310 static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt, 4311 unsigned long addr, 4312 void *val, 4313 unsigned int bytes, 4314 struct x86_exception *exception) 4315 { 4316 return emulator_read_write(ctxt, addr, val, bytes, 4317 exception, &read_emultor); 4318 } 4319 4320 static int emulator_write_emulated(struct x86_emulate_ctxt *ctxt, 4321 unsigned long addr, 4322 const void *val, 4323 unsigned int bytes, 4324 struct x86_exception *exception) 4325 { 4326 return emulator_read_write(ctxt, addr, (void *)val, bytes, 4327 exception, &write_emultor); 4328 } 4329 4330 #define CMPXCHG_TYPE(t, ptr, old, new) \ 4331 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old)) 4332 4333 #ifdef CONFIG_X86_64 4334 # define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new) 4335 #else 4336 # define CMPXCHG64(ptr, old, new) \ 4337 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old)) 4338 #endif 4339 4340 static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt, 4341 unsigned long addr, 4342 const void *old, 4343 const void *new, 4344 unsigned int bytes, 4345 struct x86_exception *exception) 4346 { 4347 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 4348 gpa_t gpa; 4349 struct page *page; 4350 char *kaddr; 4351 bool exchanged; 4352 4353 /* guests cmpxchg8b have to be emulated atomically */ 4354 if (bytes > 8 || (bytes & (bytes - 1))) 4355 goto emul_write; 4356 4357 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL); 4358 4359 if (gpa == UNMAPPED_GVA || 4360 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE) 4361 goto emul_write; 4362 4363 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK)) 4364 goto emul_write; 4365 4366 page = kvm_vcpu_gfn_to_page(vcpu, gpa >> PAGE_SHIFT); 4367 if (is_error_page(page)) 4368 goto emul_write; 4369 4370 kaddr = kmap_atomic(page); 4371 kaddr += offset_in_page(gpa); 4372 switch (bytes) { 4373 case 1: 4374 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new); 4375 break; 4376 case 2: 4377 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new); 4378 break; 4379 case 4: 4380 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new); 4381 break; 4382 case 8: 4383 exchanged = CMPXCHG64(kaddr, old, new); 4384 break; 4385 default: 4386 BUG(); 4387 } 4388 kunmap_atomic(kaddr); 4389 kvm_release_page_dirty(page); 4390 4391 if (!exchanged) 4392 return X86EMUL_CMPXCHG_FAILED; 4393 4394 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT); 4395 kvm_mmu_pte_write(vcpu, gpa, new, bytes); 4396 4397 return X86EMUL_CONTINUE; 4398 4399 emul_write: 4400 printk_once(KERN_WARNING "kvm: emulating exchange as write\n"); 4401 4402 return emulator_write_emulated(ctxt, addr, new, bytes, exception); 4403 } 4404 4405 static int kernel_pio(struct kvm_vcpu *vcpu, void *pd) 4406 { 4407 /* TODO: String I/O for in kernel device */ 4408 int r; 4409 4410 if (vcpu->arch.pio.in) 4411 r = kvm_io_bus_read(vcpu, KVM_PIO_BUS, vcpu->arch.pio.port, 4412 vcpu->arch.pio.size, pd); 4413 else 4414 r = kvm_io_bus_write(vcpu, KVM_PIO_BUS, 4415 vcpu->arch.pio.port, vcpu->arch.pio.size, 4416 pd); 4417 return r; 4418 } 4419 4420 static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size, 4421 unsigned short port, void *val, 4422 unsigned int count, bool in) 4423 { 4424 vcpu->arch.pio.port = port; 4425 vcpu->arch.pio.in = in; 4426 vcpu->arch.pio.count = count; 4427 vcpu->arch.pio.size = size; 4428 4429 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) { 4430 vcpu->arch.pio.count = 0; 4431 return 1; 4432 } 4433 4434 vcpu->run->exit_reason = KVM_EXIT_IO; 4435 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT; 4436 vcpu->run->io.size = size; 4437 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE; 4438 vcpu->run->io.count = count; 4439 vcpu->run->io.port = port; 4440 4441 return 0; 4442 } 4443 4444 static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt, 4445 int size, unsigned short port, void *val, 4446 unsigned int count) 4447 { 4448 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 4449 int ret; 4450 4451 if (vcpu->arch.pio.count) 4452 goto data_avail; 4453 4454 ret = emulator_pio_in_out(vcpu, size, port, val, count, true); 4455 if (ret) { 4456 data_avail: 4457 memcpy(val, vcpu->arch.pio_data, size * count); 4458 trace_kvm_pio(KVM_PIO_IN, port, size, count, vcpu->arch.pio_data); 4459 vcpu->arch.pio.count = 0; 4460 return 1; 4461 } 4462 4463 return 0; 4464 } 4465 4466 static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt, 4467 int size, unsigned short port, 4468 const void *val, unsigned int count) 4469 { 4470 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 4471 4472 memcpy(vcpu->arch.pio_data, val, size * count); 4473 trace_kvm_pio(KVM_PIO_OUT, port, size, count, vcpu->arch.pio_data); 4474 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false); 4475 } 4476 4477 static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg) 4478 { 4479 return kvm_x86_ops->get_segment_base(vcpu, seg); 4480 } 4481 4482 static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address) 4483 { 4484 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address); 4485 } 4486 4487 int kvm_emulate_wbinvd_noskip(struct kvm_vcpu *vcpu) 4488 { 4489 if (!need_emulate_wbinvd(vcpu)) 4490 return X86EMUL_CONTINUE; 4491 4492 if (kvm_x86_ops->has_wbinvd_exit()) { 4493 int cpu = get_cpu(); 4494 4495 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask); 4496 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask, 4497 wbinvd_ipi, NULL, 1); 4498 put_cpu(); 4499 cpumask_clear(vcpu->arch.wbinvd_dirty_mask); 4500 } else 4501 wbinvd(); 4502 return X86EMUL_CONTINUE; 4503 } 4504 4505 int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu) 4506 { 4507 kvm_x86_ops->skip_emulated_instruction(vcpu); 4508 return kvm_emulate_wbinvd_noskip(vcpu); 4509 } 4510 EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd); 4511 4512 4513 4514 static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt) 4515 { 4516 kvm_emulate_wbinvd_noskip(emul_to_vcpu(ctxt)); 4517 } 4518 4519 static int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr, 4520 unsigned long *dest) 4521 { 4522 return kvm_get_dr(emul_to_vcpu(ctxt), dr, dest); 4523 } 4524 4525 static int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr, 4526 unsigned long value) 4527 { 4528 4529 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value); 4530 } 4531 4532 static u64 mk_cr_64(u64 curr_cr, u32 new_val) 4533 { 4534 return (curr_cr & ~((1ULL << 32) - 1)) | new_val; 4535 } 4536 4537 static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr) 4538 { 4539 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 4540 unsigned long value; 4541 4542 switch (cr) { 4543 case 0: 4544 value = kvm_read_cr0(vcpu); 4545 break; 4546 case 2: 4547 value = vcpu->arch.cr2; 4548 break; 4549 case 3: 4550 value = kvm_read_cr3(vcpu); 4551 break; 4552 case 4: 4553 value = kvm_read_cr4(vcpu); 4554 break; 4555 case 8: 4556 value = kvm_get_cr8(vcpu); 4557 break; 4558 default: 4559 kvm_err("%s: unexpected cr %u\n", __func__, cr); 4560 return 0; 4561 } 4562 4563 return value; 4564 } 4565 4566 static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val) 4567 { 4568 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 4569 int res = 0; 4570 4571 switch (cr) { 4572 case 0: 4573 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val)); 4574 break; 4575 case 2: 4576 vcpu->arch.cr2 = val; 4577 break; 4578 case 3: 4579 res = kvm_set_cr3(vcpu, val); 4580 break; 4581 case 4: 4582 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val)); 4583 break; 4584 case 8: 4585 res = kvm_set_cr8(vcpu, val); 4586 break; 4587 default: 4588 kvm_err("%s: unexpected cr %u\n", __func__, cr); 4589 res = -1; 4590 } 4591 4592 return res; 4593 } 4594 4595 static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt) 4596 { 4597 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt)); 4598 } 4599 4600 static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt) 4601 { 4602 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt); 4603 } 4604 4605 static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt) 4606 { 4607 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt); 4608 } 4609 4610 static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt) 4611 { 4612 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt); 4613 } 4614 4615 static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt) 4616 { 4617 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt); 4618 } 4619 4620 static unsigned long emulator_get_cached_segment_base( 4621 struct x86_emulate_ctxt *ctxt, int seg) 4622 { 4623 return get_segment_base(emul_to_vcpu(ctxt), seg); 4624 } 4625 4626 static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector, 4627 struct desc_struct *desc, u32 *base3, 4628 int seg) 4629 { 4630 struct kvm_segment var; 4631 4632 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg); 4633 *selector = var.selector; 4634 4635 if (var.unusable) { 4636 memset(desc, 0, sizeof(*desc)); 4637 return false; 4638 } 4639 4640 if (var.g) 4641 var.limit >>= 12; 4642 set_desc_limit(desc, var.limit); 4643 set_desc_base(desc, (unsigned long)var.base); 4644 #ifdef CONFIG_X86_64 4645 if (base3) 4646 *base3 = var.base >> 32; 4647 #endif 4648 desc->type = var.type; 4649 desc->s = var.s; 4650 desc->dpl = var.dpl; 4651 desc->p = var.present; 4652 desc->avl = var.avl; 4653 desc->l = var.l; 4654 desc->d = var.db; 4655 desc->g = var.g; 4656 4657 return true; 4658 } 4659 4660 static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector, 4661 struct desc_struct *desc, u32 base3, 4662 int seg) 4663 { 4664 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 4665 struct kvm_segment var; 4666 4667 var.selector = selector; 4668 var.base = get_desc_base(desc); 4669 #ifdef CONFIG_X86_64 4670 var.base |= ((u64)base3) << 32; 4671 #endif 4672 var.limit = get_desc_limit(desc); 4673 if (desc->g) 4674 var.limit = (var.limit << 12) | 0xfff; 4675 var.type = desc->type; 4676 var.dpl = desc->dpl; 4677 var.db = desc->d; 4678 var.s = desc->s; 4679 var.l = desc->l; 4680 var.g = desc->g; 4681 var.avl = desc->avl; 4682 var.present = desc->p; 4683 var.unusable = !var.present; 4684 var.padding = 0; 4685 4686 kvm_set_segment(vcpu, &var, seg); 4687 return; 4688 } 4689 4690 static int emulator_get_msr(struct x86_emulate_ctxt *ctxt, 4691 u32 msr_index, u64 *pdata) 4692 { 4693 struct msr_data msr; 4694 int r; 4695 4696 msr.index = msr_index; 4697 msr.host_initiated = false; 4698 r = kvm_get_msr(emul_to_vcpu(ctxt), &msr); 4699 if (r) 4700 return r; 4701 4702 *pdata = msr.data; 4703 return 0; 4704 } 4705 4706 static int emulator_set_msr(struct x86_emulate_ctxt *ctxt, 4707 u32 msr_index, u64 data) 4708 { 4709 struct msr_data msr; 4710 4711 msr.data = data; 4712 msr.index = msr_index; 4713 msr.host_initiated = false; 4714 return kvm_set_msr(emul_to_vcpu(ctxt), &msr); 4715 } 4716 4717 static u64 emulator_get_smbase(struct x86_emulate_ctxt *ctxt) 4718 { 4719 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 4720 4721 return vcpu->arch.smbase; 4722 } 4723 4724 static void emulator_set_smbase(struct x86_emulate_ctxt *ctxt, u64 smbase) 4725 { 4726 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 4727 4728 vcpu->arch.smbase = smbase; 4729 } 4730 4731 static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt, 4732 u32 pmc) 4733 { 4734 return kvm_pmu_is_valid_msr_idx(emul_to_vcpu(ctxt), pmc); 4735 } 4736 4737 static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt, 4738 u32 pmc, u64 *pdata) 4739 { 4740 return kvm_pmu_rdpmc(emul_to_vcpu(ctxt), pmc, pdata); 4741 } 4742 4743 static void emulator_halt(struct x86_emulate_ctxt *ctxt) 4744 { 4745 emul_to_vcpu(ctxt)->arch.halt_request = 1; 4746 } 4747 4748 static void emulator_get_fpu(struct x86_emulate_ctxt *ctxt) 4749 { 4750 preempt_disable(); 4751 kvm_load_guest_fpu(emul_to_vcpu(ctxt)); 4752 /* 4753 * CR0.TS may reference the host fpu state, not the guest fpu state, 4754 * so it may be clear at this point. 4755 */ 4756 clts(); 4757 } 4758 4759 static void emulator_put_fpu(struct x86_emulate_ctxt *ctxt) 4760 { 4761 preempt_enable(); 4762 } 4763 4764 static int emulator_intercept(struct x86_emulate_ctxt *ctxt, 4765 struct x86_instruction_info *info, 4766 enum x86_intercept_stage stage) 4767 { 4768 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage); 4769 } 4770 4771 static void emulator_get_cpuid(struct x86_emulate_ctxt *ctxt, 4772 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx) 4773 { 4774 kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx); 4775 } 4776 4777 static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg) 4778 { 4779 return kvm_register_read(emul_to_vcpu(ctxt), reg); 4780 } 4781 4782 static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val) 4783 { 4784 kvm_register_write(emul_to_vcpu(ctxt), reg, val); 4785 } 4786 4787 static void emulator_set_nmi_mask(struct x86_emulate_ctxt *ctxt, bool masked) 4788 { 4789 kvm_x86_ops->set_nmi_mask(emul_to_vcpu(ctxt), masked); 4790 } 4791 4792 static const struct x86_emulate_ops emulate_ops = { 4793 .read_gpr = emulator_read_gpr, 4794 .write_gpr = emulator_write_gpr, 4795 .read_std = kvm_read_guest_virt_system, 4796 .write_std = kvm_write_guest_virt_system, 4797 .fetch = kvm_fetch_guest_virt, 4798 .read_emulated = emulator_read_emulated, 4799 .write_emulated = emulator_write_emulated, 4800 .cmpxchg_emulated = emulator_cmpxchg_emulated, 4801 .invlpg = emulator_invlpg, 4802 .pio_in_emulated = emulator_pio_in_emulated, 4803 .pio_out_emulated = emulator_pio_out_emulated, 4804 .get_segment = emulator_get_segment, 4805 .set_segment = emulator_set_segment, 4806 .get_cached_segment_base = emulator_get_cached_segment_base, 4807 .get_gdt = emulator_get_gdt, 4808 .get_idt = emulator_get_idt, 4809 .set_gdt = emulator_set_gdt, 4810 .set_idt = emulator_set_idt, 4811 .get_cr = emulator_get_cr, 4812 .set_cr = emulator_set_cr, 4813 .cpl = emulator_get_cpl, 4814 .get_dr = emulator_get_dr, 4815 .set_dr = emulator_set_dr, 4816 .get_smbase = emulator_get_smbase, 4817 .set_smbase = emulator_set_smbase, 4818 .set_msr = emulator_set_msr, 4819 .get_msr = emulator_get_msr, 4820 .check_pmc = emulator_check_pmc, 4821 .read_pmc = emulator_read_pmc, 4822 .halt = emulator_halt, 4823 .wbinvd = emulator_wbinvd, 4824 .fix_hypercall = emulator_fix_hypercall, 4825 .get_fpu = emulator_get_fpu, 4826 .put_fpu = emulator_put_fpu, 4827 .intercept = emulator_intercept, 4828 .get_cpuid = emulator_get_cpuid, 4829 .set_nmi_mask = emulator_set_nmi_mask, 4830 }; 4831 4832 static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask) 4833 { 4834 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu); 4835 /* 4836 * an sti; sti; sequence only disable interrupts for the first 4837 * instruction. So, if the last instruction, be it emulated or 4838 * not, left the system with the INT_STI flag enabled, it 4839 * means that the last instruction is an sti. We should not 4840 * leave the flag on in this case. The same goes for mov ss 4841 */ 4842 if (int_shadow & mask) 4843 mask = 0; 4844 if (unlikely(int_shadow || mask)) { 4845 kvm_x86_ops->set_interrupt_shadow(vcpu, mask); 4846 if (!mask) 4847 kvm_make_request(KVM_REQ_EVENT, vcpu); 4848 } 4849 } 4850 4851 static bool inject_emulated_exception(struct kvm_vcpu *vcpu) 4852 { 4853 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt; 4854 if (ctxt->exception.vector == PF_VECTOR) 4855 return kvm_propagate_fault(vcpu, &ctxt->exception); 4856 4857 if (ctxt->exception.error_code_valid) 4858 kvm_queue_exception_e(vcpu, ctxt->exception.vector, 4859 ctxt->exception.error_code); 4860 else 4861 kvm_queue_exception(vcpu, ctxt->exception.vector); 4862 return false; 4863 } 4864 4865 static void init_emulate_ctxt(struct kvm_vcpu *vcpu) 4866 { 4867 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt; 4868 int cs_db, cs_l; 4869 4870 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l); 4871 4872 ctxt->eflags = kvm_get_rflags(vcpu); 4873 ctxt->eip = kvm_rip_read(vcpu); 4874 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL : 4875 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 : 4876 (cs_l && is_long_mode(vcpu)) ? X86EMUL_MODE_PROT64 : 4877 cs_db ? X86EMUL_MODE_PROT32 : 4878 X86EMUL_MODE_PROT16; 4879 BUILD_BUG_ON(HF_GUEST_MASK != X86EMUL_GUEST_MASK); 4880 BUILD_BUG_ON(HF_SMM_MASK != X86EMUL_SMM_MASK); 4881 BUILD_BUG_ON(HF_SMM_INSIDE_NMI_MASK != X86EMUL_SMM_INSIDE_NMI_MASK); 4882 ctxt->emul_flags = vcpu->arch.hflags; 4883 4884 init_decode_cache(ctxt); 4885 vcpu->arch.emulate_regs_need_sync_from_vcpu = false; 4886 } 4887 4888 int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip) 4889 { 4890 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt; 4891 int ret; 4892 4893 init_emulate_ctxt(vcpu); 4894 4895 ctxt->op_bytes = 2; 4896 ctxt->ad_bytes = 2; 4897 ctxt->_eip = ctxt->eip + inc_eip; 4898 ret = emulate_int_real(ctxt, irq); 4899 4900 if (ret != X86EMUL_CONTINUE) 4901 return EMULATE_FAIL; 4902 4903 ctxt->eip = ctxt->_eip; 4904 kvm_rip_write(vcpu, ctxt->eip); 4905 kvm_set_rflags(vcpu, ctxt->eflags); 4906 4907 if (irq == NMI_VECTOR) 4908 vcpu->arch.nmi_pending = 0; 4909 else 4910 vcpu->arch.interrupt.pending = false; 4911 4912 return EMULATE_DONE; 4913 } 4914 EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt); 4915 4916 static int handle_emulation_failure(struct kvm_vcpu *vcpu) 4917 { 4918 int r = EMULATE_DONE; 4919 4920 ++vcpu->stat.insn_emulation_fail; 4921 trace_kvm_emulate_insn_failed(vcpu); 4922 if (!is_guest_mode(vcpu) && kvm_x86_ops->get_cpl(vcpu) == 0) { 4923 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR; 4924 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION; 4925 vcpu->run->internal.ndata = 0; 4926 r = EMULATE_FAIL; 4927 } 4928 kvm_queue_exception(vcpu, UD_VECTOR); 4929 4930 return r; 4931 } 4932 4933 static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t cr2, 4934 bool write_fault_to_shadow_pgtable, 4935 int emulation_type) 4936 { 4937 gpa_t gpa = cr2; 4938 pfn_t pfn; 4939 4940 if (emulation_type & EMULTYPE_NO_REEXECUTE) 4941 return false; 4942 4943 if (!vcpu->arch.mmu.direct_map) { 4944 /* 4945 * Write permission should be allowed since only 4946 * write access need to be emulated. 4947 */ 4948 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL); 4949 4950 /* 4951 * If the mapping is invalid in guest, let cpu retry 4952 * it to generate fault. 4953 */ 4954 if (gpa == UNMAPPED_GVA) 4955 return true; 4956 } 4957 4958 /* 4959 * Do not retry the unhandleable instruction if it faults on the 4960 * readonly host memory, otherwise it will goto a infinite loop: 4961 * retry instruction -> write #PF -> emulation fail -> retry 4962 * instruction -> ... 4963 */ 4964 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa)); 4965 4966 /* 4967 * If the instruction failed on the error pfn, it can not be fixed, 4968 * report the error to userspace. 4969 */ 4970 if (is_error_noslot_pfn(pfn)) 4971 return false; 4972 4973 kvm_release_pfn_clean(pfn); 4974 4975 /* The instructions are well-emulated on direct mmu. */ 4976 if (vcpu->arch.mmu.direct_map) { 4977 unsigned int indirect_shadow_pages; 4978 4979 spin_lock(&vcpu->kvm->mmu_lock); 4980 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages; 4981 spin_unlock(&vcpu->kvm->mmu_lock); 4982 4983 if (indirect_shadow_pages) 4984 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa)); 4985 4986 return true; 4987 } 4988 4989 /* 4990 * if emulation was due to access to shadowed page table 4991 * and it failed try to unshadow page and re-enter the 4992 * guest to let CPU execute the instruction. 4993 */ 4994 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa)); 4995 4996 /* 4997 * If the access faults on its page table, it can not 4998 * be fixed by unprotecting shadow page and it should 4999 * be reported to userspace. 5000 */ 5001 return !write_fault_to_shadow_pgtable; 5002 } 5003 5004 static bool retry_instruction(struct x86_emulate_ctxt *ctxt, 5005 unsigned long cr2, int emulation_type) 5006 { 5007 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 5008 unsigned long last_retry_eip, last_retry_addr, gpa = cr2; 5009 5010 last_retry_eip = vcpu->arch.last_retry_eip; 5011 last_retry_addr = vcpu->arch.last_retry_addr; 5012 5013 /* 5014 * If the emulation is caused by #PF and it is non-page_table 5015 * writing instruction, it means the VM-EXIT is caused by shadow 5016 * page protected, we can zap the shadow page and retry this 5017 * instruction directly. 5018 * 5019 * Note: if the guest uses a non-page-table modifying instruction 5020 * on the PDE that points to the instruction, then we will unmap 5021 * the instruction and go to an infinite loop. So, we cache the 5022 * last retried eip and the last fault address, if we meet the eip 5023 * and the address again, we can break out of the potential infinite 5024 * loop. 5025 */ 5026 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0; 5027 5028 if (!(emulation_type & EMULTYPE_RETRY)) 5029 return false; 5030 5031 if (x86_page_table_writing_insn(ctxt)) 5032 return false; 5033 5034 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2) 5035 return false; 5036 5037 vcpu->arch.last_retry_eip = ctxt->eip; 5038 vcpu->arch.last_retry_addr = cr2; 5039 5040 if (!vcpu->arch.mmu.direct_map) 5041 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL); 5042 5043 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa)); 5044 5045 return true; 5046 } 5047 5048 static int complete_emulated_mmio(struct kvm_vcpu *vcpu); 5049 static int complete_emulated_pio(struct kvm_vcpu *vcpu); 5050 5051 static void kvm_smm_changed(struct kvm_vcpu *vcpu) 5052 { 5053 if (!(vcpu->arch.hflags & HF_SMM_MASK)) { 5054 /* This is a good place to trace that we are exiting SMM. */ 5055 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, false); 5056 5057 if (unlikely(vcpu->arch.smi_pending)) { 5058 kvm_make_request(KVM_REQ_SMI, vcpu); 5059 vcpu->arch.smi_pending = 0; 5060 } else { 5061 /* Process a latched INIT, if any. */ 5062 kvm_make_request(KVM_REQ_EVENT, vcpu); 5063 } 5064 } 5065 5066 kvm_mmu_reset_context(vcpu); 5067 } 5068 5069 static void kvm_set_hflags(struct kvm_vcpu *vcpu, unsigned emul_flags) 5070 { 5071 unsigned changed = vcpu->arch.hflags ^ emul_flags; 5072 5073 vcpu->arch.hflags = emul_flags; 5074 5075 if (changed & HF_SMM_MASK) 5076 kvm_smm_changed(vcpu); 5077 } 5078 5079 static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7, 5080 unsigned long *db) 5081 { 5082 u32 dr6 = 0; 5083 int i; 5084 u32 enable, rwlen; 5085 5086 enable = dr7; 5087 rwlen = dr7 >> 16; 5088 for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4) 5089 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr) 5090 dr6 |= (1 << i); 5091 return dr6; 5092 } 5093 5094 static void kvm_vcpu_check_singlestep(struct kvm_vcpu *vcpu, unsigned long rflags, int *r) 5095 { 5096 struct kvm_run *kvm_run = vcpu->run; 5097 5098 /* 5099 * rflags is the old, "raw" value of the flags. The new value has 5100 * not been saved yet. 5101 * 5102 * This is correct even for TF set by the guest, because "the 5103 * processor will not generate this exception after the instruction 5104 * that sets the TF flag". 5105 */ 5106 if (unlikely(rflags & X86_EFLAGS_TF)) { 5107 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) { 5108 kvm_run->debug.arch.dr6 = DR6_BS | DR6_FIXED_1 | 5109 DR6_RTM; 5110 kvm_run->debug.arch.pc = vcpu->arch.singlestep_rip; 5111 kvm_run->debug.arch.exception = DB_VECTOR; 5112 kvm_run->exit_reason = KVM_EXIT_DEBUG; 5113 *r = EMULATE_USER_EXIT; 5114 } else { 5115 vcpu->arch.emulate_ctxt.eflags &= ~X86_EFLAGS_TF; 5116 /* 5117 * "Certain debug exceptions may clear bit 0-3. The 5118 * remaining contents of the DR6 register are never 5119 * cleared by the processor". 5120 */ 5121 vcpu->arch.dr6 &= ~15; 5122 vcpu->arch.dr6 |= DR6_BS | DR6_RTM; 5123 kvm_queue_exception(vcpu, DB_VECTOR); 5124 } 5125 } 5126 } 5127 5128 static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r) 5129 { 5130 if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) && 5131 (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) { 5132 struct kvm_run *kvm_run = vcpu->run; 5133 unsigned long eip = kvm_get_linear_rip(vcpu); 5134 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0, 5135 vcpu->arch.guest_debug_dr7, 5136 vcpu->arch.eff_db); 5137 5138 if (dr6 != 0) { 5139 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1 | DR6_RTM; 5140 kvm_run->debug.arch.pc = eip; 5141 kvm_run->debug.arch.exception = DB_VECTOR; 5142 kvm_run->exit_reason = KVM_EXIT_DEBUG; 5143 *r = EMULATE_USER_EXIT; 5144 return true; 5145 } 5146 } 5147 5148 if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) && 5149 !(kvm_get_rflags(vcpu) & X86_EFLAGS_RF)) { 5150 unsigned long eip = kvm_get_linear_rip(vcpu); 5151 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0, 5152 vcpu->arch.dr7, 5153 vcpu->arch.db); 5154 5155 if (dr6 != 0) { 5156 vcpu->arch.dr6 &= ~15; 5157 vcpu->arch.dr6 |= dr6 | DR6_RTM; 5158 kvm_queue_exception(vcpu, DB_VECTOR); 5159 *r = EMULATE_DONE; 5160 return true; 5161 } 5162 } 5163 5164 return false; 5165 } 5166 5167 int x86_emulate_instruction(struct kvm_vcpu *vcpu, 5168 unsigned long cr2, 5169 int emulation_type, 5170 void *insn, 5171 int insn_len) 5172 { 5173 int r; 5174 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt; 5175 bool writeback = true; 5176 bool write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable; 5177 5178 /* 5179 * Clear write_fault_to_shadow_pgtable here to ensure it is 5180 * never reused. 5181 */ 5182 vcpu->arch.write_fault_to_shadow_pgtable = false; 5183 kvm_clear_exception_queue(vcpu); 5184 5185 if (!(emulation_type & EMULTYPE_NO_DECODE)) { 5186 init_emulate_ctxt(vcpu); 5187 5188 /* 5189 * We will reenter on the same instruction since 5190 * we do not set complete_userspace_io. This does not 5191 * handle watchpoints yet, those would be handled in 5192 * the emulate_ops. 5193 */ 5194 if (kvm_vcpu_check_breakpoint(vcpu, &r)) 5195 return r; 5196 5197 ctxt->interruptibility = 0; 5198 ctxt->have_exception = false; 5199 ctxt->exception.vector = -1; 5200 ctxt->perm_ok = false; 5201 5202 ctxt->ud = emulation_type & EMULTYPE_TRAP_UD; 5203 5204 r = x86_decode_insn(ctxt, insn, insn_len); 5205 5206 trace_kvm_emulate_insn_start(vcpu); 5207 ++vcpu->stat.insn_emulation; 5208 if (r != EMULATION_OK) { 5209 if (emulation_type & EMULTYPE_TRAP_UD) 5210 return EMULATE_FAIL; 5211 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt, 5212 emulation_type)) 5213 return EMULATE_DONE; 5214 if (emulation_type & EMULTYPE_SKIP) 5215 return EMULATE_FAIL; 5216 return handle_emulation_failure(vcpu); 5217 } 5218 } 5219 5220 if (emulation_type & EMULTYPE_SKIP) { 5221 kvm_rip_write(vcpu, ctxt->_eip); 5222 if (ctxt->eflags & X86_EFLAGS_RF) 5223 kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF); 5224 return EMULATE_DONE; 5225 } 5226 5227 if (retry_instruction(ctxt, cr2, emulation_type)) 5228 return EMULATE_DONE; 5229 5230 /* this is needed for vmware backdoor interface to work since it 5231 changes registers values during IO operation */ 5232 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) { 5233 vcpu->arch.emulate_regs_need_sync_from_vcpu = false; 5234 emulator_invalidate_register_cache(ctxt); 5235 } 5236 5237 restart: 5238 r = x86_emulate_insn(ctxt); 5239 5240 if (r == EMULATION_INTERCEPTED) 5241 return EMULATE_DONE; 5242 5243 if (r == EMULATION_FAILED) { 5244 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt, 5245 emulation_type)) 5246 return EMULATE_DONE; 5247 5248 return handle_emulation_failure(vcpu); 5249 } 5250 5251 if (ctxt->have_exception) { 5252 r = EMULATE_DONE; 5253 if (inject_emulated_exception(vcpu)) 5254 return r; 5255 } else if (vcpu->arch.pio.count) { 5256 if (!vcpu->arch.pio.in) { 5257 /* FIXME: return into emulator if single-stepping. */ 5258 vcpu->arch.pio.count = 0; 5259 } else { 5260 writeback = false; 5261 vcpu->arch.complete_userspace_io = complete_emulated_pio; 5262 } 5263 r = EMULATE_USER_EXIT; 5264 } else if (vcpu->mmio_needed) { 5265 if (!vcpu->mmio_is_write) 5266 writeback = false; 5267 r = EMULATE_USER_EXIT; 5268 vcpu->arch.complete_userspace_io = complete_emulated_mmio; 5269 } else if (r == EMULATION_RESTART) 5270 goto restart; 5271 else 5272 r = EMULATE_DONE; 5273 5274 if (writeback) { 5275 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu); 5276 toggle_interruptibility(vcpu, ctxt->interruptibility); 5277 vcpu->arch.emulate_regs_need_sync_to_vcpu = false; 5278 if (vcpu->arch.hflags != ctxt->emul_flags) 5279 kvm_set_hflags(vcpu, ctxt->emul_flags); 5280 kvm_rip_write(vcpu, ctxt->eip); 5281 if (r == EMULATE_DONE) 5282 kvm_vcpu_check_singlestep(vcpu, rflags, &r); 5283 if (!ctxt->have_exception || 5284 exception_type(ctxt->exception.vector) == EXCPT_TRAP) 5285 __kvm_set_rflags(vcpu, ctxt->eflags); 5286 5287 /* 5288 * For STI, interrupts are shadowed; so KVM_REQ_EVENT will 5289 * do nothing, and it will be requested again as soon as 5290 * the shadow expires. But we still need to check here, 5291 * because POPF has no interrupt shadow. 5292 */ 5293 if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF)) 5294 kvm_make_request(KVM_REQ_EVENT, vcpu); 5295 } else 5296 vcpu->arch.emulate_regs_need_sync_to_vcpu = true; 5297 5298 return r; 5299 } 5300 EXPORT_SYMBOL_GPL(x86_emulate_instruction); 5301 5302 int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port) 5303 { 5304 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX); 5305 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt, 5306 size, port, &val, 1); 5307 /* do not return to emulator after return from userspace */ 5308 vcpu->arch.pio.count = 0; 5309 return ret; 5310 } 5311 EXPORT_SYMBOL_GPL(kvm_fast_pio_out); 5312 5313 static void tsc_bad(void *info) 5314 { 5315 __this_cpu_write(cpu_tsc_khz, 0); 5316 } 5317 5318 static void tsc_khz_changed(void *data) 5319 { 5320 struct cpufreq_freqs *freq = data; 5321 unsigned long khz = 0; 5322 5323 if (data) 5324 khz = freq->new; 5325 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) 5326 khz = cpufreq_quick_get(raw_smp_processor_id()); 5327 if (!khz) 5328 khz = tsc_khz; 5329 __this_cpu_write(cpu_tsc_khz, khz); 5330 } 5331 5332 static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val, 5333 void *data) 5334 { 5335 struct cpufreq_freqs *freq = data; 5336 struct kvm *kvm; 5337 struct kvm_vcpu *vcpu; 5338 int i, send_ipi = 0; 5339 5340 /* 5341 * We allow guests to temporarily run on slowing clocks, 5342 * provided we notify them after, or to run on accelerating 5343 * clocks, provided we notify them before. Thus time never 5344 * goes backwards. 5345 * 5346 * However, we have a problem. We can't atomically update 5347 * the frequency of a given CPU from this function; it is 5348 * merely a notifier, which can be called from any CPU. 5349 * Changing the TSC frequency at arbitrary points in time 5350 * requires a recomputation of local variables related to 5351 * the TSC for each VCPU. We must flag these local variables 5352 * to be updated and be sure the update takes place with the 5353 * new frequency before any guests proceed. 5354 * 5355 * Unfortunately, the combination of hotplug CPU and frequency 5356 * change creates an intractable locking scenario; the order 5357 * of when these callouts happen is undefined with respect to 5358 * CPU hotplug, and they can race with each other. As such, 5359 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is 5360 * undefined; you can actually have a CPU frequency change take 5361 * place in between the computation of X and the setting of the 5362 * variable. To protect against this problem, all updates of 5363 * the per_cpu tsc_khz variable are done in an interrupt 5364 * protected IPI, and all callers wishing to update the value 5365 * must wait for a synchronous IPI to complete (which is trivial 5366 * if the caller is on the CPU already). This establishes the 5367 * necessary total order on variable updates. 5368 * 5369 * Note that because a guest time update may take place 5370 * anytime after the setting of the VCPU's request bit, the 5371 * correct TSC value must be set before the request. However, 5372 * to ensure the update actually makes it to any guest which 5373 * starts running in hardware virtualization between the set 5374 * and the acquisition of the spinlock, we must also ping the 5375 * CPU after setting the request bit. 5376 * 5377 */ 5378 5379 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new) 5380 return 0; 5381 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new) 5382 return 0; 5383 5384 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1); 5385 5386 spin_lock(&kvm_lock); 5387 list_for_each_entry(kvm, &vm_list, vm_list) { 5388 kvm_for_each_vcpu(i, vcpu, kvm) { 5389 if (vcpu->cpu != freq->cpu) 5390 continue; 5391 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 5392 if (vcpu->cpu != smp_processor_id()) 5393 send_ipi = 1; 5394 } 5395 } 5396 spin_unlock(&kvm_lock); 5397 5398 if (freq->old < freq->new && send_ipi) { 5399 /* 5400 * We upscale the frequency. Must make the guest 5401 * doesn't see old kvmclock values while running with 5402 * the new frequency, otherwise we risk the guest sees 5403 * time go backwards. 5404 * 5405 * In case we update the frequency for another cpu 5406 * (which might be in guest context) send an interrupt 5407 * to kick the cpu out of guest context. Next time 5408 * guest context is entered kvmclock will be updated, 5409 * so the guest will not see stale values. 5410 */ 5411 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1); 5412 } 5413 return 0; 5414 } 5415 5416 static struct notifier_block kvmclock_cpufreq_notifier_block = { 5417 .notifier_call = kvmclock_cpufreq_notifier 5418 }; 5419 5420 static int kvmclock_cpu_notifier(struct notifier_block *nfb, 5421 unsigned long action, void *hcpu) 5422 { 5423 unsigned int cpu = (unsigned long)hcpu; 5424 5425 switch (action) { 5426 case CPU_ONLINE: 5427 case CPU_DOWN_FAILED: 5428 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1); 5429 break; 5430 case CPU_DOWN_PREPARE: 5431 smp_call_function_single(cpu, tsc_bad, NULL, 1); 5432 break; 5433 } 5434 return NOTIFY_OK; 5435 } 5436 5437 static struct notifier_block kvmclock_cpu_notifier_block = { 5438 .notifier_call = kvmclock_cpu_notifier, 5439 .priority = -INT_MAX 5440 }; 5441 5442 static void kvm_timer_init(void) 5443 { 5444 int cpu; 5445 5446 max_tsc_khz = tsc_khz; 5447 5448 cpu_notifier_register_begin(); 5449 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) { 5450 #ifdef CONFIG_CPU_FREQ 5451 struct cpufreq_policy policy; 5452 memset(&policy, 0, sizeof(policy)); 5453 cpu = get_cpu(); 5454 cpufreq_get_policy(&policy, cpu); 5455 if (policy.cpuinfo.max_freq) 5456 max_tsc_khz = policy.cpuinfo.max_freq; 5457 put_cpu(); 5458 #endif 5459 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block, 5460 CPUFREQ_TRANSITION_NOTIFIER); 5461 } 5462 pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz); 5463 for_each_online_cpu(cpu) 5464 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1); 5465 5466 __register_hotcpu_notifier(&kvmclock_cpu_notifier_block); 5467 cpu_notifier_register_done(); 5468 5469 } 5470 5471 static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu); 5472 5473 int kvm_is_in_guest(void) 5474 { 5475 return __this_cpu_read(current_vcpu) != NULL; 5476 } 5477 5478 static int kvm_is_user_mode(void) 5479 { 5480 int user_mode = 3; 5481 5482 if (__this_cpu_read(current_vcpu)) 5483 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu)); 5484 5485 return user_mode != 0; 5486 } 5487 5488 static unsigned long kvm_get_guest_ip(void) 5489 { 5490 unsigned long ip = 0; 5491 5492 if (__this_cpu_read(current_vcpu)) 5493 ip = kvm_rip_read(__this_cpu_read(current_vcpu)); 5494 5495 return ip; 5496 } 5497 5498 static struct perf_guest_info_callbacks kvm_guest_cbs = { 5499 .is_in_guest = kvm_is_in_guest, 5500 .is_user_mode = kvm_is_user_mode, 5501 .get_guest_ip = kvm_get_guest_ip, 5502 }; 5503 5504 void kvm_before_handle_nmi(struct kvm_vcpu *vcpu) 5505 { 5506 __this_cpu_write(current_vcpu, vcpu); 5507 } 5508 EXPORT_SYMBOL_GPL(kvm_before_handle_nmi); 5509 5510 void kvm_after_handle_nmi(struct kvm_vcpu *vcpu) 5511 { 5512 __this_cpu_write(current_vcpu, NULL); 5513 } 5514 EXPORT_SYMBOL_GPL(kvm_after_handle_nmi); 5515 5516 static void kvm_set_mmio_spte_mask(void) 5517 { 5518 u64 mask; 5519 int maxphyaddr = boot_cpu_data.x86_phys_bits; 5520 5521 /* 5522 * Set the reserved bits and the present bit of an paging-structure 5523 * entry to generate page fault with PFER.RSV = 1. 5524 */ 5525 /* Mask the reserved physical address bits. */ 5526 mask = rsvd_bits(maxphyaddr, 51); 5527 5528 /* Bit 62 is always reserved for 32bit host. */ 5529 mask |= 0x3ull << 62; 5530 5531 /* Set the present bit. */ 5532 mask |= 1ull; 5533 5534 #ifdef CONFIG_X86_64 5535 /* 5536 * If reserved bit is not supported, clear the present bit to disable 5537 * mmio page fault. 5538 */ 5539 if (maxphyaddr == 52) 5540 mask &= ~1ull; 5541 #endif 5542 5543 kvm_mmu_set_mmio_spte_mask(mask); 5544 } 5545 5546 #ifdef CONFIG_X86_64 5547 static void pvclock_gtod_update_fn(struct work_struct *work) 5548 { 5549 struct kvm *kvm; 5550 5551 struct kvm_vcpu *vcpu; 5552 int i; 5553 5554 spin_lock(&kvm_lock); 5555 list_for_each_entry(kvm, &vm_list, vm_list) 5556 kvm_for_each_vcpu(i, vcpu, kvm) 5557 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu); 5558 atomic_set(&kvm_guest_has_master_clock, 0); 5559 spin_unlock(&kvm_lock); 5560 } 5561 5562 static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn); 5563 5564 /* 5565 * Notification about pvclock gtod data update. 5566 */ 5567 static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused, 5568 void *priv) 5569 { 5570 struct pvclock_gtod_data *gtod = &pvclock_gtod_data; 5571 struct timekeeper *tk = priv; 5572 5573 update_pvclock_gtod(tk); 5574 5575 /* disable master clock if host does not trust, or does not 5576 * use, TSC clocksource 5577 */ 5578 if (gtod->clock.vclock_mode != VCLOCK_TSC && 5579 atomic_read(&kvm_guest_has_master_clock) != 0) 5580 queue_work(system_long_wq, &pvclock_gtod_work); 5581 5582 return 0; 5583 } 5584 5585 static struct notifier_block pvclock_gtod_notifier = { 5586 .notifier_call = pvclock_gtod_notify, 5587 }; 5588 #endif 5589 5590 int kvm_arch_init(void *opaque) 5591 { 5592 int r; 5593 struct kvm_x86_ops *ops = opaque; 5594 5595 if (kvm_x86_ops) { 5596 printk(KERN_ERR "kvm: already loaded the other module\n"); 5597 r = -EEXIST; 5598 goto out; 5599 } 5600 5601 if (!ops->cpu_has_kvm_support()) { 5602 printk(KERN_ERR "kvm: no hardware support\n"); 5603 r = -EOPNOTSUPP; 5604 goto out; 5605 } 5606 if (ops->disabled_by_bios()) { 5607 printk(KERN_ERR "kvm: disabled by bios\n"); 5608 r = -EOPNOTSUPP; 5609 goto out; 5610 } 5611 5612 r = -ENOMEM; 5613 shared_msrs = alloc_percpu(struct kvm_shared_msrs); 5614 if (!shared_msrs) { 5615 printk(KERN_ERR "kvm: failed to allocate percpu kvm_shared_msrs\n"); 5616 goto out; 5617 } 5618 5619 r = kvm_mmu_module_init(); 5620 if (r) 5621 goto out_free_percpu; 5622 5623 kvm_set_mmio_spte_mask(); 5624 5625 kvm_x86_ops = ops; 5626 5627 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK, 5628 PT_DIRTY_MASK, PT64_NX_MASK, 0); 5629 5630 kvm_timer_init(); 5631 5632 perf_register_guest_info_callbacks(&kvm_guest_cbs); 5633 5634 if (cpu_has_xsave) 5635 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK); 5636 5637 kvm_lapic_init(); 5638 #ifdef CONFIG_X86_64 5639 pvclock_gtod_register_notifier(&pvclock_gtod_notifier); 5640 #endif 5641 5642 return 0; 5643 5644 out_free_percpu: 5645 free_percpu(shared_msrs); 5646 out: 5647 return r; 5648 } 5649 5650 void kvm_arch_exit(void) 5651 { 5652 perf_unregister_guest_info_callbacks(&kvm_guest_cbs); 5653 5654 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) 5655 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block, 5656 CPUFREQ_TRANSITION_NOTIFIER); 5657 unregister_hotcpu_notifier(&kvmclock_cpu_notifier_block); 5658 #ifdef CONFIG_X86_64 5659 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier); 5660 #endif 5661 kvm_x86_ops = NULL; 5662 kvm_mmu_module_exit(); 5663 free_percpu(shared_msrs); 5664 } 5665 5666 int kvm_vcpu_halt(struct kvm_vcpu *vcpu) 5667 { 5668 ++vcpu->stat.halt_exits; 5669 if (irqchip_in_kernel(vcpu->kvm)) { 5670 vcpu->arch.mp_state = KVM_MP_STATE_HALTED; 5671 return 1; 5672 } else { 5673 vcpu->run->exit_reason = KVM_EXIT_HLT; 5674 return 0; 5675 } 5676 } 5677 EXPORT_SYMBOL_GPL(kvm_vcpu_halt); 5678 5679 int kvm_emulate_halt(struct kvm_vcpu *vcpu) 5680 { 5681 kvm_x86_ops->skip_emulated_instruction(vcpu); 5682 return kvm_vcpu_halt(vcpu); 5683 } 5684 EXPORT_SYMBOL_GPL(kvm_emulate_halt); 5685 5686 /* 5687 * kvm_pv_kick_cpu_op: Kick a vcpu. 5688 * 5689 * @apicid - apicid of vcpu to be kicked. 5690 */ 5691 static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid) 5692 { 5693 struct kvm_lapic_irq lapic_irq; 5694 5695 lapic_irq.shorthand = 0; 5696 lapic_irq.dest_mode = 0; 5697 lapic_irq.dest_id = apicid; 5698 lapic_irq.msi_redir_hint = false; 5699 5700 lapic_irq.delivery_mode = APIC_DM_REMRD; 5701 kvm_irq_delivery_to_apic(kvm, NULL, &lapic_irq, NULL); 5702 } 5703 5704 int kvm_emulate_hypercall(struct kvm_vcpu *vcpu) 5705 { 5706 unsigned long nr, a0, a1, a2, a3, ret; 5707 int op_64_bit, r = 1; 5708 5709 kvm_x86_ops->skip_emulated_instruction(vcpu); 5710 5711 if (kvm_hv_hypercall_enabled(vcpu->kvm)) 5712 return kvm_hv_hypercall(vcpu); 5713 5714 nr = kvm_register_read(vcpu, VCPU_REGS_RAX); 5715 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX); 5716 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX); 5717 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX); 5718 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI); 5719 5720 trace_kvm_hypercall(nr, a0, a1, a2, a3); 5721 5722 op_64_bit = is_64_bit_mode(vcpu); 5723 if (!op_64_bit) { 5724 nr &= 0xFFFFFFFF; 5725 a0 &= 0xFFFFFFFF; 5726 a1 &= 0xFFFFFFFF; 5727 a2 &= 0xFFFFFFFF; 5728 a3 &= 0xFFFFFFFF; 5729 } 5730 5731 if (kvm_x86_ops->get_cpl(vcpu) != 0) { 5732 ret = -KVM_EPERM; 5733 goto out; 5734 } 5735 5736 switch (nr) { 5737 case KVM_HC_VAPIC_POLL_IRQ: 5738 ret = 0; 5739 break; 5740 case KVM_HC_KICK_CPU: 5741 kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1); 5742 ret = 0; 5743 break; 5744 default: 5745 ret = -KVM_ENOSYS; 5746 break; 5747 } 5748 out: 5749 if (!op_64_bit) 5750 ret = (u32)ret; 5751 kvm_register_write(vcpu, VCPU_REGS_RAX, ret); 5752 ++vcpu->stat.hypercalls; 5753 return r; 5754 } 5755 EXPORT_SYMBOL_GPL(kvm_emulate_hypercall); 5756 5757 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt) 5758 { 5759 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 5760 char instruction[3]; 5761 unsigned long rip = kvm_rip_read(vcpu); 5762 5763 kvm_x86_ops->patch_hypercall(vcpu, instruction); 5764 5765 return emulator_write_emulated(ctxt, rip, instruction, 3, NULL); 5766 } 5767 5768 /* 5769 * Check if userspace requested an interrupt window, and that the 5770 * interrupt window is open. 5771 * 5772 * No need to exit to userspace if we already have an interrupt queued. 5773 */ 5774 static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu) 5775 { 5776 return (!irqchip_in_kernel(vcpu->kvm) && !kvm_cpu_has_interrupt(vcpu) && 5777 vcpu->run->request_interrupt_window && 5778 kvm_arch_interrupt_allowed(vcpu)); 5779 } 5780 5781 static void post_kvm_run_save(struct kvm_vcpu *vcpu) 5782 { 5783 struct kvm_run *kvm_run = vcpu->run; 5784 5785 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0; 5786 kvm_run->flags = is_smm(vcpu) ? KVM_RUN_X86_SMM : 0; 5787 kvm_run->cr8 = kvm_get_cr8(vcpu); 5788 kvm_run->apic_base = kvm_get_apic_base(vcpu); 5789 if (irqchip_in_kernel(vcpu->kvm)) 5790 kvm_run->ready_for_interrupt_injection = 1; 5791 else 5792 kvm_run->ready_for_interrupt_injection = 5793 kvm_arch_interrupt_allowed(vcpu) && 5794 !kvm_cpu_has_interrupt(vcpu) && 5795 !kvm_event_needs_reinjection(vcpu); 5796 } 5797 5798 static void update_cr8_intercept(struct kvm_vcpu *vcpu) 5799 { 5800 int max_irr, tpr; 5801 5802 if (!kvm_x86_ops->update_cr8_intercept) 5803 return; 5804 5805 if (!vcpu->arch.apic) 5806 return; 5807 5808 if (!vcpu->arch.apic->vapic_addr) 5809 max_irr = kvm_lapic_find_highest_irr(vcpu); 5810 else 5811 max_irr = -1; 5812 5813 if (max_irr != -1) 5814 max_irr >>= 4; 5815 5816 tpr = kvm_lapic_get_cr8(vcpu); 5817 5818 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr); 5819 } 5820 5821 static int inject_pending_event(struct kvm_vcpu *vcpu, bool req_int_win) 5822 { 5823 int r; 5824 5825 /* try to reinject previous events if any */ 5826 if (vcpu->arch.exception.pending) { 5827 trace_kvm_inj_exception(vcpu->arch.exception.nr, 5828 vcpu->arch.exception.has_error_code, 5829 vcpu->arch.exception.error_code); 5830 5831 if (exception_type(vcpu->arch.exception.nr) == EXCPT_FAULT) 5832 __kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) | 5833 X86_EFLAGS_RF); 5834 5835 if (vcpu->arch.exception.nr == DB_VECTOR && 5836 (vcpu->arch.dr7 & DR7_GD)) { 5837 vcpu->arch.dr7 &= ~DR7_GD; 5838 kvm_update_dr7(vcpu); 5839 } 5840 5841 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr, 5842 vcpu->arch.exception.has_error_code, 5843 vcpu->arch.exception.error_code, 5844 vcpu->arch.exception.reinject); 5845 return 0; 5846 } 5847 5848 if (vcpu->arch.nmi_injected) { 5849 kvm_x86_ops->set_nmi(vcpu); 5850 return 0; 5851 } 5852 5853 if (vcpu->arch.interrupt.pending) { 5854 kvm_x86_ops->set_irq(vcpu); 5855 return 0; 5856 } 5857 5858 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) { 5859 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win); 5860 if (r != 0) 5861 return r; 5862 } 5863 5864 /* try to inject new event if pending */ 5865 if (vcpu->arch.nmi_pending) { 5866 if (kvm_x86_ops->nmi_allowed(vcpu)) { 5867 --vcpu->arch.nmi_pending; 5868 vcpu->arch.nmi_injected = true; 5869 kvm_x86_ops->set_nmi(vcpu); 5870 } 5871 } else if (kvm_cpu_has_injectable_intr(vcpu)) { 5872 /* 5873 * Because interrupts can be injected asynchronously, we are 5874 * calling check_nested_events again here to avoid a race condition. 5875 * See https://lkml.org/lkml/2014/7/2/60 for discussion about this 5876 * proposal and current concerns. Perhaps we should be setting 5877 * KVM_REQ_EVENT only on certain events and not unconditionally? 5878 */ 5879 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) { 5880 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win); 5881 if (r != 0) 5882 return r; 5883 } 5884 if (kvm_x86_ops->interrupt_allowed(vcpu)) { 5885 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu), 5886 false); 5887 kvm_x86_ops->set_irq(vcpu); 5888 } 5889 } 5890 return 0; 5891 } 5892 5893 static void process_nmi(struct kvm_vcpu *vcpu) 5894 { 5895 unsigned limit = 2; 5896 5897 /* 5898 * x86 is limited to one NMI running, and one NMI pending after it. 5899 * If an NMI is already in progress, limit further NMIs to just one. 5900 * Otherwise, allow two (and we'll inject the first one immediately). 5901 */ 5902 if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected) 5903 limit = 1; 5904 5905 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0); 5906 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit); 5907 kvm_make_request(KVM_REQ_EVENT, vcpu); 5908 } 5909 5910 #define put_smstate(type, buf, offset, val) \ 5911 *(type *)((buf) + (offset) - 0x7e00) = val 5912 5913 static u32 process_smi_get_segment_flags(struct kvm_segment *seg) 5914 { 5915 u32 flags = 0; 5916 flags |= seg->g << 23; 5917 flags |= seg->db << 22; 5918 flags |= seg->l << 21; 5919 flags |= seg->avl << 20; 5920 flags |= seg->present << 15; 5921 flags |= seg->dpl << 13; 5922 flags |= seg->s << 12; 5923 flags |= seg->type << 8; 5924 return flags; 5925 } 5926 5927 static void process_smi_save_seg_32(struct kvm_vcpu *vcpu, char *buf, int n) 5928 { 5929 struct kvm_segment seg; 5930 int offset; 5931 5932 kvm_get_segment(vcpu, &seg, n); 5933 put_smstate(u32, buf, 0x7fa8 + n * 4, seg.selector); 5934 5935 if (n < 3) 5936 offset = 0x7f84 + n * 12; 5937 else 5938 offset = 0x7f2c + (n - 3) * 12; 5939 5940 put_smstate(u32, buf, offset + 8, seg.base); 5941 put_smstate(u32, buf, offset + 4, seg.limit); 5942 put_smstate(u32, buf, offset, process_smi_get_segment_flags(&seg)); 5943 } 5944 5945 #ifdef CONFIG_X86_64 5946 static void process_smi_save_seg_64(struct kvm_vcpu *vcpu, char *buf, int n) 5947 { 5948 struct kvm_segment seg; 5949 int offset; 5950 u16 flags; 5951 5952 kvm_get_segment(vcpu, &seg, n); 5953 offset = 0x7e00 + n * 16; 5954 5955 flags = process_smi_get_segment_flags(&seg) >> 8; 5956 put_smstate(u16, buf, offset, seg.selector); 5957 put_smstate(u16, buf, offset + 2, flags); 5958 put_smstate(u32, buf, offset + 4, seg.limit); 5959 put_smstate(u64, buf, offset + 8, seg.base); 5960 } 5961 #endif 5962 5963 static void process_smi_save_state_32(struct kvm_vcpu *vcpu, char *buf) 5964 { 5965 struct desc_ptr dt; 5966 struct kvm_segment seg; 5967 unsigned long val; 5968 int i; 5969 5970 put_smstate(u32, buf, 0x7ffc, kvm_read_cr0(vcpu)); 5971 put_smstate(u32, buf, 0x7ff8, kvm_read_cr3(vcpu)); 5972 put_smstate(u32, buf, 0x7ff4, kvm_get_rflags(vcpu)); 5973 put_smstate(u32, buf, 0x7ff0, kvm_rip_read(vcpu)); 5974 5975 for (i = 0; i < 8; i++) 5976 put_smstate(u32, buf, 0x7fd0 + i * 4, kvm_register_read(vcpu, i)); 5977 5978 kvm_get_dr(vcpu, 6, &val); 5979 put_smstate(u32, buf, 0x7fcc, (u32)val); 5980 kvm_get_dr(vcpu, 7, &val); 5981 put_smstate(u32, buf, 0x7fc8, (u32)val); 5982 5983 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR); 5984 put_smstate(u32, buf, 0x7fc4, seg.selector); 5985 put_smstate(u32, buf, 0x7f64, seg.base); 5986 put_smstate(u32, buf, 0x7f60, seg.limit); 5987 put_smstate(u32, buf, 0x7f5c, process_smi_get_segment_flags(&seg)); 5988 5989 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR); 5990 put_smstate(u32, buf, 0x7fc0, seg.selector); 5991 put_smstate(u32, buf, 0x7f80, seg.base); 5992 put_smstate(u32, buf, 0x7f7c, seg.limit); 5993 put_smstate(u32, buf, 0x7f78, process_smi_get_segment_flags(&seg)); 5994 5995 kvm_x86_ops->get_gdt(vcpu, &dt); 5996 put_smstate(u32, buf, 0x7f74, dt.address); 5997 put_smstate(u32, buf, 0x7f70, dt.size); 5998 5999 kvm_x86_ops->get_idt(vcpu, &dt); 6000 put_smstate(u32, buf, 0x7f58, dt.address); 6001 put_smstate(u32, buf, 0x7f54, dt.size); 6002 6003 for (i = 0; i < 6; i++) 6004 process_smi_save_seg_32(vcpu, buf, i); 6005 6006 put_smstate(u32, buf, 0x7f14, kvm_read_cr4(vcpu)); 6007 6008 /* revision id */ 6009 put_smstate(u32, buf, 0x7efc, 0x00020000); 6010 put_smstate(u32, buf, 0x7ef8, vcpu->arch.smbase); 6011 } 6012 6013 static void process_smi_save_state_64(struct kvm_vcpu *vcpu, char *buf) 6014 { 6015 #ifdef CONFIG_X86_64 6016 struct desc_ptr dt; 6017 struct kvm_segment seg; 6018 unsigned long val; 6019 int i; 6020 6021 for (i = 0; i < 16; i++) 6022 put_smstate(u64, buf, 0x7ff8 - i * 8, kvm_register_read(vcpu, i)); 6023 6024 put_smstate(u64, buf, 0x7f78, kvm_rip_read(vcpu)); 6025 put_smstate(u32, buf, 0x7f70, kvm_get_rflags(vcpu)); 6026 6027 kvm_get_dr(vcpu, 6, &val); 6028 put_smstate(u64, buf, 0x7f68, val); 6029 kvm_get_dr(vcpu, 7, &val); 6030 put_smstate(u64, buf, 0x7f60, val); 6031 6032 put_smstate(u64, buf, 0x7f58, kvm_read_cr0(vcpu)); 6033 put_smstate(u64, buf, 0x7f50, kvm_read_cr3(vcpu)); 6034 put_smstate(u64, buf, 0x7f48, kvm_read_cr4(vcpu)); 6035 6036 put_smstate(u32, buf, 0x7f00, vcpu->arch.smbase); 6037 6038 /* revision id */ 6039 put_smstate(u32, buf, 0x7efc, 0x00020064); 6040 6041 put_smstate(u64, buf, 0x7ed0, vcpu->arch.efer); 6042 6043 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR); 6044 put_smstate(u16, buf, 0x7e90, seg.selector); 6045 put_smstate(u16, buf, 0x7e92, process_smi_get_segment_flags(&seg) >> 8); 6046 put_smstate(u32, buf, 0x7e94, seg.limit); 6047 put_smstate(u64, buf, 0x7e98, seg.base); 6048 6049 kvm_x86_ops->get_idt(vcpu, &dt); 6050 put_smstate(u32, buf, 0x7e84, dt.size); 6051 put_smstate(u64, buf, 0x7e88, dt.address); 6052 6053 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR); 6054 put_smstate(u16, buf, 0x7e70, seg.selector); 6055 put_smstate(u16, buf, 0x7e72, process_smi_get_segment_flags(&seg) >> 8); 6056 put_smstate(u32, buf, 0x7e74, seg.limit); 6057 put_smstate(u64, buf, 0x7e78, seg.base); 6058 6059 kvm_x86_ops->get_gdt(vcpu, &dt); 6060 put_smstate(u32, buf, 0x7e64, dt.size); 6061 put_smstate(u64, buf, 0x7e68, dt.address); 6062 6063 for (i = 0; i < 6; i++) 6064 process_smi_save_seg_64(vcpu, buf, i); 6065 #else 6066 WARN_ON_ONCE(1); 6067 #endif 6068 } 6069 6070 static void process_smi(struct kvm_vcpu *vcpu) 6071 { 6072 struct kvm_segment cs, ds; 6073 struct desc_ptr dt; 6074 char buf[512]; 6075 u32 cr0; 6076 6077 if (is_smm(vcpu)) { 6078 vcpu->arch.smi_pending = true; 6079 return; 6080 } 6081 6082 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, true); 6083 vcpu->arch.hflags |= HF_SMM_MASK; 6084 memset(buf, 0, 512); 6085 if (guest_cpuid_has_longmode(vcpu)) 6086 process_smi_save_state_64(vcpu, buf); 6087 else 6088 process_smi_save_state_32(vcpu, buf); 6089 6090 kvm_vcpu_write_guest(vcpu, vcpu->arch.smbase + 0xfe00, buf, sizeof(buf)); 6091 6092 if (kvm_x86_ops->get_nmi_mask(vcpu)) 6093 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK; 6094 else 6095 kvm_x86_ops->set_nmi_mask(vcpu, true); 6096 6097 kvm_set_rflags(vcpu, X86_EFLAGS_FIXED); 6098 kvm_rip_write(vcpu, 0x8000); 6099 6100 cr0 = vcpu->arch.cr0 & ~(X86_CR0_PE | X86_CR0_EM | X86_CR0_TS | X86_CR0_PG); 6101 kvm_x86_ops->set_cr0(vcpu, cr0); 6102 vcpu->arch.cr0 = cr0; 6103 6104 kvm_x86_ops->set_cr4(vcpu, 0); 6105 6106 /* Undocumented: IDT limit is set to zero on entry to SMM. */ 6107 dt.address = dt.size = 0; 6108 kvm_x86_ops->set_idt(vcpu, &dt); 6109 6110 __kvm_set_dr(vcpu, 7, DR7_FIXED_1); 6111 6112 cs.selector = (vcpu->arch.smbase >> 4) & 0xffff; 6113 cs.base = vcpu->arch.smbase; 6114 6115 ds.selector = 0; 6116 ds.base = 0; 6117 6118 cs.limit = ds.limit = 0xffffffff; 6119 cs.type = ds.type = 0x3; 6120 cs.dpl = ds.dpl = 0; 6121 cs.db = ds.db = 0; 6122 cs.s = ds.s = 1; 6123 cs.l = ds.l = 0; 6124 cs.g = ds.g = 1; 6125 cs.avl = ds.avl = 0; 6126 cs.present = ds.present = 1; 6127 cs.unusable = ds.unusable = 0; 6128 cs.padding = ds.padding = 0; 6129 6130 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS); 6131 kvm_set_segment(vcpu, &ds, VCPU_SREG_DS); 6132 kvm_set_segment(vcpu, &ds, VCPU_SREG_ES); 6133 kvm_set_segment(vcpu, &ds, VCPU_SREG_FS); 6134 kvm_set_segment(vcpu, &ds, VCPU_SREG_GS); 6135 kvm_set_segment(vcpu, &ds, VCPU_SREG_SS); 6136 6137 if (guest_cpuid_has_longmode(vcpu)) 6138 kvm_x86_ops->set_efer(vcpu, 0); 6139 6140 kvm_update_cpuid(vcpu); 6141 kvm_mmu_reset_context(vcpu); 6142 } 6143 6144 static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu) 6145 { 6146 u64 eoi_exit_bitmap[4]; 6147 u32 tmr[8]; 6148 6149 if (!kvm_apic_hw_enabled(vcpu->arch.apic)) 6150 return; 6151 6152 memset(eoi_exit_bitmap, 0, 32); 6153 memset(tmr, 0, 32); 6154 6155 kvm_ioapic_scan_entry(vcpu, eoi_exit_bitmap, tmr); 6156 kvm_x86_ops->load_eoi_exitmap(vcpu, eoi_exit_bitmap); 6157 kvm_apic_update_tmr(vcpu, tmr); 6158 } 6159 6160 static void kvm_vcpu_flush_tlb(struct kvm_vcpu *vcpu) 6161 { 6162 ++vcpu->stat.tlb_flush; 6163 kvm_x86_ops->tlb_flush(vcpu); 6164 } 6165 6166 void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu) 6167 { 6168 struct page *page = NULL; 6169 6170 if (!irqchip_in_kernel(vcpu->kvm)) 6171 return; 6172 6173 if (!kvm_x86_ops->set_apic_access_page_addr) 6174 return; 6175 6176 page = gfn_to_page(vcpu->kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT); 6177 if (is_error_page(page)) 6178 return; 6179 kvm_x86_ops->set_apic_access_page_addr(vcpu, page_to_phys(page)); 6180 6181 /* 6182 * Do not pin apic access page in memory, the MMU notifier 6183 * will call us again if it is migrated or swapped out. 6184 */ 6185 put_page(page); 6186 } 6187 EXPORT_SYMBOL_GPL(kvm_vcpu_reload_apic_access_page); 6188 6189 void kvm_arch_mmu_notifier_invalidate_page(struct kvm *kvm, 6190 unsigned long address) 6191 { 6192 /* 6193 * The physical address of apic access page is stored in the VMCS. 6194 * Update it when it becomes invalid. 6195 */ 6196 if (address == gfn_to_hva(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT)) 6197 kvm_make_all_cpus_request(kvm, KVM_REQ_APIC_PAGE_RELOAD); 6198 } 6199 6200 /* 6201 * Returns 1 to let vcpu_run() continue the guest execution loop without 6202 * exiting to the userspace. Otherwise, the value will be returned to the 6203 * userspace. 6204 */ 6205 static int vcpu_enter_guest(struct kvm_vcpu *vcpu) 6206 { 6207 int r; 6208 bool req_int_win = !irqchip_in_kernel(vcpu->kvm) && 6209 vcpu->run->request_interrupt_window; 6210 bool req_immediate_exit = false; 6211 6212 if (vcpu->requests) { 6213 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu)) 6214 kvm_mmu_unload(vcpu); 6215 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu)) 6216 __kvm_migrate_timers(vcpu); 6217 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu)) 6218 kvm_gen_update_masterclock(vcpu->kvm); 6219 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu)) 6220 kvm_gen_kvmclock_update(vcpu); 6221 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) { 6222 r = kvm_guest_time_update(vcpu); 6223 if (unlikely(r)) 6224 goto out; 6225 } 6226 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu)) 6227 kvm_mmu_sync_roots(vcpu); 6228 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu)) 6229 kvm_vcpu_flush_tlb(vcpu); 6230 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) { 6231 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS; 6232 r = 0; 6233 goto out; 6234 } 6235 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) { 6236 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN; 6237 r = 0; 6238 goto out; 6239 } 6240 if (kvm_check_request(KVM_REQ_DEACTIVATE_FPU, vcpu)) { 6241 vcpu->fpu_active = 0; 6242 kvm_x86_ops->fpu_deactivate(vcpu); 6243 } 6244 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) { 6245 /* Page is swapped out. Do synthetic halt */ 6246 vcpu->arch.apf.halted = true; 6247 r = 1; 6248 goto out; 6249 } 6250 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu)) 6251 record_steal_time(vcpu); 6252 if (kvm_check_request(KVM_REQ_SMI, vcpu)) 6253 process_smi(vcpu); 6254 if (kvm_check_request(KVM_REQ_NMI, vcpu)) 6255 process_nmi(vcpu); 6256 if (kvm_check_request(KVM_REQ_PMU, vcpu)) 6257 kvm_pmu_handle_event(vcpu); 6258 if (kvm_check_request(KVM_REQ_PMI, vcpu)) 6259 kvm_pmu_deliver_pmi(vcpu); 6260 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu)) 6261 vcpu_scan_ioapic(vcpu); 6262 if (kvm_check_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu)) 6263 kvm_vcpu_reload_apic_access_page(vcpu); 6264 if (kvm_check_request(KVM_REQ_HV_CRASH, vcpu)) { 6265 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT; 6266 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_CRASH; 6267 r = 0; 6268 goto out; 6269 } 6270 } 6271 6272 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) { 6273 kvm_apic_accept_events(vcpu); 6274 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) { 6275 r = 1; 6276 goto out; 6277 } 6278 6279 if (inject_pending_event(vcpu, req_int_win) != 0) 6280 req_immediate_exit = true; 6281 /* enable NMI/IRQ window open exits if needed */ 6282 else if (vcpu->arch.nmi_pending) 6283 kvm_x86_ops->enable_nmi_window(vcpu); 6284 else if (kvm_cpu_has_injectable_intr(vcpu) || req_int_win) 6285 kvm_x86_ops->enable_irq_window(vcpu); 6286 6287 if (kvm_lapic_enabled(vcpu)) { 6288 /* 6289 * Update architecture specific hints for APIC 6290 * virtual interrupt delivery. 6291 */ 6292 if (kvm_x86_ops->hwapic_irr_update) 6293 kvm_x86_ops->hwapic_irr_update(vcpu, 6294 kvm_lapic_find_highest_irr(vcpu)); 6295 update_cr8_intercept(vcpu); 6296 kvm_lapic_sync_to_vapic(vcpu); 6297 } 6298 } 6299 6300 r = kvm_mmu_reload(vcpu); 6301 if (unlikely(r)) { 6302 goto cancel_injection; 6303 } 6304 6305 preempt_disable(); 6306 6307 kvm_x86_ops->prepare_guest_switch(vcpu); 6308 if (vcpu->fpu_active) 6309 kvm_load_guest_fpu(vcpu); 6310 kvm_load_guest_xcr0(vcpu); 6311 6312 vcpu->mode = IN_GUEST_MODE; 6313 6314 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx); 6315 6316 /* We should set ->mode before check ->requests, 6317 * see the comment in make_all_cpus_request. 6318 */ 6319 smp_mb__after_srcu_read_unlock(); 6320 6321 local_irq_disable(); 6322 6323 if (vcpu->mode == EXITING_GUEST_MODE || vcpu->requests 6324 || need_resched() || signal_pending(current)) { 6325 vcpu->mode = OUTSIDE_GUEST_MODE; 6326 smp_wmb(); 6327 local_irq_enable(); 6328 preempt_enable(); 6329 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu); 6330 r = 1; 6331 goto cancel_injection; 6332 } 6333 6334 if (req_immediate_exit) 6335 smp_send_reschedule(vcpu->cpu); 6336 6337 __kvm_guest_enter(); 6338 6339 if (unlikely(vcpu->arch.switch_db_regs)) { 6340 set_debugreg(0, 7); 6341 set_debugreg(vcpu->arch.eff_db[0], 0); 6342 set_debugreg(vcpu->arch.eff_db[1], 1); 6343 set_debugreg(vcpu->arch.eff_db[2], 2); 6344 set_debugreg(vcpu->arch.eff_db[3], 3); 6345 set_debugreg(vcpu->arch.dr6, 6); 6346 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD; 6347 } 6348 6349 trace_kvm_entry(vcpu->vcpu_id); 6350 wait_lapic_expire(vcpu); 6351 kvm_x86_ops->run(vcpu); 6352 6353 /* 6354 * Do this here before restoring debug registers on the host. And 6355 * since we do this before handling the vmexit, a DR access vmexit 6356 * can (a) read the correct value of the debug registers, (b) set 6357 * KVM_DEBUGREG_WONT_EXIT again. 6358 */ 6359 if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) { 6360 int i; 6361 6362 WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP); 6363 kvm_x86_ops->sync_dirty_debug_regs(vcpu); 6364 for (i = 0; i < KVM_NR_DB_REGS; i++) 6365 vcpu->arch.eff_db[i] = vcpu->arch.db[i]; 6366 } 6367 6368 /* 6369 * If the guest has used debug registers, at least dr7 6370 * will be disabled while returning to the host. 6371 * If we don't have active breakpoints in the host, we don't 6372 * care about the messed up debug address registers. But if 6373 * we have some of them active, restore the old state. 6374 */ 6375 if (hw_breakpoint_active()) 6376 hw_breakpoint_restore(); 6377 6378 vcpu->arch.last_guest_tsc = kvm_x86_ops->read_l1_tsc(vcpu, 6379 rdtsc()); 6380 6381 vcpu->mode = OUTSIDE_GUEST_MODE; 6382 smp_wmb(); 6383 6384 /* Interrupt is enabled by handle_external_intr() */ 6385 kvm_x86_ops->handle_external_intr(vcpu); 6386 6387 ++vcpu->stat.exits; 6388 6389 /* 6390 * We must have an instruction between local_irq_enable() and 6391 * kvm_guest_exit(), so the timer interrupt isn't delayed by 6392 * the interrupt shadow. The stat.exits increment will do nicely. 6393 * But we need to prevent reordering, hence this barrier(): 6394 */ 6395 barrier(); 6396 6397 kvm_guest_exit(); 6398 6399 preempt_enable(); 6400 6401 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu); 6402 6403 /* 6404 * Profile KVM exit RIPs: 6405 */ 6406 if (unlikely(prof_on == KVM_PROFILING)) { 6407 unsigned long rip = kvm_rip_read(vcpu); 6408 profile_hit(KVM_PROFILING, (void *)rip); 6409 } 6410 6411 if (unlikely(vcpu->arch.tsc_always_catchup)) 6412 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 6413 6414 if (vcpu->arch.apic_attention) 6415 kvm_lapic_sync_from_vapic(vcpu); 6416 6417 r = kvm_x86_ops->handle_exit(vcpu); 6418 return r; 6419 6420 cancel_injection: 6421 kvm_x86_ops->cancel_injection(vcpu); 6422 if (unlikely(vcpu->arch.apic_attention)) 6423 kvm_lapic_sync_from_vapic(vcpu); 6424 out: 6425 return r; 6426 } 6427 6428 static inline int vcpu_block(struct kvm *kvm, struct kvm_vcpu *vcpu) 6429 { 6430 if (!kvm_arch_vcpu_runnable(vcpu)) { 6431 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx); 6432 kvm_vcpu_block(vcpu); 6433 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu); 6434 if (!kvm_check_request(KVM_REQ_UNHALT, vcpu)) 6435 return 1; 6436 } 6437 6438 kvm_apic_accept_events(vcpu); 6439 switch(vcpu->arch.mp_state) { 6440 case KVM_MP_STATE_HALTED: 6441 vcpu->arch.pv.pv_unhalted = false; 6442 vcpu->arch.mp_state = 6443 KVM_MP_STATE_RUNNABLE; 6444 case KVM_MP_STATE_RUNNABLE: 6445 vcpu->arch.apf.halted = false; 6446 break; 6447 case KVM_MP_STATE_INIT_RECEIVED: 6448 break; 6449 default: 6450 return -EINTR; 6451 break; 6452 } 6453 return 1; 6454 } 6455 6456 static inline bool kvm_vcpu_running(struct kvm_vcpu *vcpu) 6457 { 6458 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE && 6459 !vcpu->arch.apf.halted); 6460 } 6461 6462 static int vcpu_run(struct kvm_vcpu *vcpu) 6463 { 6464 int r; 6465 struct kvm *kvm = vcpu->kvm; 6466 6467 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu); 6468 6469 for (;;) { 6470 if (kvm_vcpu_running(vcpu)) 6471 r = vcpu_enter_guest(vcpu); 6472 else 6473 r = vcpu_block(kvm, vcpu); 6474 if (r <= 0) 6475 break; 6476 6477 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests); 6478 if (kvm_cpu_has_pending_timer(vcpu)) 6479 kvm_inject_pending_timer_irqs(vcpu); 6480 6481 if (dm_request_for_irq_injection(vcpu)) { 6482 r = -EINTR; 6483 vcpu->run->exit_reason = KVM_EXIT_INTR; 6484 ++vcpu->stat.request_irq_exits; 6485 break; 6486 } 6487 6488 kvm_check_async_pf_completion(vcpu); 6489 6490 if (signal_pending(current)) { 6491 r = -EINTR; 6492 vcpu->run->exit_reason = KVM_EXIT_INTR; 6493 ++vcpu->stat.signal_exits; 6494 break; 6495 } 6496 if (need_resched()) { 6497 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx); 6498 cond_resched(); 6499 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu); 6500 } 6501 } 6502 6503 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx); 6504 6505 return r; 6506 } 6507 6508 static inline int complete_emulated_io(struct kvm_vcpu *vcpu) 6509 { 6510 int r; 6511 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu); 6512 r = emulate_instruction(vcpu, EMULTYPE_NO_DECODE); 6513 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx); 6514 if (r != EMULATE_DONE) 6515 return 0; 6516 return 1; 6517 } 6518 6519 static int complete_emulated_pio(struct kvm_vcpu *vcpu) 6520 { 6521 BUG_ON(!vcpu->arch.pio.count); 6522 6523 return complete_emulated_io(vcpu); 6524 } 6525 6526 /* 6527 * Implements the following, as a state machine: 6528 * 6529 * read: 6530 * for each fragment 6531 * for each mmio piece in the fragment 6532 * write gpa, len 6533 * exit 6534 * copy data 6535 * execute insn 6536 * 6537 * write: 6538 * for each fragment 6539 * for each mmio piece in the fragment 6540 * write gpa, len 6541 * copy data 6542 * exit 6543 */ 6544 static int complete_emulated_mmio(struct kvm_vcpu *vcpu) 6545 { 6546 struct kvm_run *run = vcpu->run; 6547 struct kvm_mmio_fragment *frag; 6548 unsigned len; 6549 6550 BUG_ON(!vcpu->mmio_needed); 6551 6552 /* Complete previous fragment */ 6553 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment]; 6554 len = min(8u, frag->len); 6555 if (!vcpu->mmio_is_write) 6556 memcpy(frag->data, run->mmio.data, len); 6557 6558 if (frag->len <= 8) { 6559 /* Switch to the next fragment. */ 6560 frag++; 6561 vcpu->mmio_cur_fragment++; 6562 } else { 6563 /* Go forward to the next mmio piece. */ 6564 frag->data += len; 6565 frag->gpa += len; 6566 frag->len -= len; 6567 } 6568 6569 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) { 6570 vcpu->mmio_needed = 0; 6571 6572 /* FIXME: return into emulator if single-stepping. */ 6573 if (vcpu->mmio_is_write) 6574 return 1; 6575 vcpu->mmio_read_completed = 1; 6576 return complete_emulated_io(vcpu); 6577 } 6578 6579 run->exit_reason = KVM_EXIT_MMIO; 6580 run->mmio.phys_addr = frag->gpa; 6581 if (vcpu->mmio_is_write) 6582 memcpy(run->mmio.data, frag->data, min(8u, frag->len)); 6583 run->mmio.len = min(8u, frag->len); 6584 run->mmio.is_write = vcpu->mmio_is_write; 6585 vcpu->arch.complete_userspace_io = complete_emulated_mmio; 6586 return 0; 6587 } 6588 6589 6590 int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) 6591 { 6592 struct fpu *fpu = ¤t->thread.fpu; 6593 int r; 6594 sigset_t sigsaved; 6595 6596 fpu__activate_curr(fpu); 6597 6598 if (vcpu->sigset_active) 6599 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved); 6600 6601 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) { 6602 kvm_vcpu_block(vcpu); 6603 kvm_apic_accept_events(vcpu); 6604 clear_bit(KVM_REQ_UNHALT, &vcpu->requests); 6605 r = -EAGAIN; 6606 goto out; 6607 } 6608 6609 /* re-sync apic's tpr */ 6610 if (!irqchip_in_kernel(vcpu->kvm)) { 6611 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) { 6612 r = -EINVAL; 6613 goto out; 6614 } 6615 } 6616 6617 if (unlikely(vcpu->arch.complete_userspace_io)) { 6618 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io; 6619 vcpu->arch.complete_userspace_io = NULL; 6620 r = cui(vcpu); 6621 if (r <= 0) 6622 goto out; 6623 } else 6624 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed); 6625 6626 r = vcpu_run(vcpu); 6627 6628 out: 6629 post_kvm_run_save(vcpu); 6630 if (vcpu->sigset_active) 6631 sigprocmask(SIG_SETMASK, &sigsaved, NULL); 6632 6633 return r; 6634 } 6635 6636 int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) 6637 { 6638 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) { 6639 /* 6640 * We are here if userspace calls get_regs() in the middle of 6641 * instruction emulation. Registers state needs to be copied 6642 * back from emulation context to vcpu. Userspace shouldn't do 6643 * that usually, but some bad designed PV devices (vmware 6644 * backdoor interface) need this to work 6645 */ 6646 emulator_writeback_register_cache(&vcpu->arch.emulate_ctxt); 6647 vcpu->arch.emulate_regs_need_sync_to_vcpu = false; 6648 } 6649 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX); 6650 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX); 6651 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX); 6652 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX); 6653 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI); 6654 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI); 6655 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP); 6656 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP); 6657 #ifdef CONFIG_X86_64 6658 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8); 6659 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9); 6660 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10); 6661 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11); 6662 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12); 6663 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13); 6664 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14); 6665 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15); 6666 #endif 6667 6668 regs->rip = kvm_rip_read(vcpu); 6669 regs->rflags = kvm_get_rflags(vcpu); 6670 6671 return 0; 6672 } 6673 6674 int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) 6675 { 6676 vcpu->arch.emulate_regs_need_sync_from_vcpu = true; 6677 vcpu->arch.emulate_regs_need_sync_to_vcpu = false; 6678 6679 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax); 6680 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx); 6681 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx); 6682 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx); 6683 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi); 6684 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi); 6685 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp); 6686 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp); 6687 #ifdef CONFIG_X86_64 6688 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8); 6689 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9); 6690 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10); 6691 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11); 6692 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12); 6693 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13); 6694 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14); 6695 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15); 6696 #endif 6697 6698 kvm_rip_write(vcpu, regs->rip); 6699 kvm_set_rflags(vcpu, regs->rflags); 6700 6701 vcpu->arch.exception.pending = false; 6702 6703 kvm_make_request(KVM_REQ_EVENT, vcpu); 6704 6705 return 0; 6706 } 6707 6708 void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l) 6709 { 6710 struct kvm_segment cs; 6711 6712 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS); 6713 *db = cs.db; 6714 *l = cs.l; 6715 } 6716 EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits); 6717 6718 int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu, 6719 struct kvm_sregs *sregs) 6720 { 6721 struct desc_ptr dt; 6722 6723 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS); 6724 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS); 6725 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES); 6726 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS); 6727 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS); 6728 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS); 6729 6730 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR); 6731 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR); 6732 6733 kvm_x86_ops->get_idt(vcpu, &dt); 6734 sregs->idt.limit = dt.size; 6735 sregs->idt.base = dt.address; 6736 kvm_x86_ops->get_gdt(vcpu, &dt); 6737 sregs->gdt.limit = dt.size; 6738 sregs->gdt.base = dt.address; 6739 6740 sregs->cr0 = kvm_read_cr0(vcpu); 6741 sregs->cr2 = vcpu->arch.cr2; 6742 sregs->cr3 = kvm_read_cr3(vcpu); 6743 sregs->cr4 = kvm_read_cr4(vcpu); 6744 sregs->cr8 = kvm_get_cr8(vcpu); 6745 sregs->efer = vcpu->arch.efer; 6746 sregs->apic_base = kvm_get_apic_base(vcpu); 6747 6748 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap); 6749 6750 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft) 6751 set_bit(vcpu->arch.interrupt.nr, 6752 (unsigned long *)sregs->interrupt_bitmap); 6753 6754 return 0; 6755 } 6756 6757 int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu, 6758 struct kvm_mp_state *mp_state) 6759 { 6760 kvm_apic_accept_events(vcpu); 6761 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED && 6762 vcpu->arch.pv.pv_unhalted) 6763 mp_state->mp_state = KVM_MP_STATE_RUNNABLE; 6764 else 6765 mp_state->mp_state = vcpu->arch.mp_state; 6766 6767 return 0; 6768 } 6769 6770 int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu, 6771 struct kvm_mp_state *mp_state) 6772 { 6773 if (!kvm_vcpu_has_lapic(vcpu) && 6774 mp_state->mp_state != KVM_MP_STATE_RUNNABLE) 6775 return -EINVAL; 6776 6777 if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) { 6778 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED; 6779 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events); 6780 } else 6781 vcpu->arch.mp_state = mp_state->mp_state; 6782 kvm_make_request(KVM_REQ_EVENT, vcpu); 6783 return 0; 6784 } 6785 6786 int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index, 6787 int reason, bool has_error_code, u32 error_code) 6788 { 6789 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt; 6790 int ret; 6791 6792 init_emulate_ctxt(vcpu); 6793 6794 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason, 6795 has_error_code, error_code); 6796 6797 if (ret) 6798 return EMULATE_FAIL; 6799 6800 kvm_rip_write(vcpu, ctxt->eip); 6801 kvm_set_rflags(vcpu, ctxt->eflags); 6802 kvm_make_request(KVM_REQ_EVENT, vcpu); 6803 return EMULATE_DONE; 6804 } 6805 EXPORT_SYMBOL_GPL(kvm_task_switch); 6806 6807 int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu, 6808 struct kvm_sregs *sregs) 6809 { 6810 struct msr_data apic_base_msr; 6811 int mmu_reset_needed = 0; 6812 int pending_vec, max_bits, idx; 6813 struct desc_ptr dt; 6814 6815 if (!guest_cpuid_has_xsave(vcpu) && (sregs->cr4 & X86_CR4_OSXSAVE)) 6816 return -EINVAL; 6817 6818 dt.size = sregs->idt.limit; 6819 dt.address = sregs->idt.base; 6820 kvm_x86_ops->set_idt(vcpu, &dt); 6821 dt.size = sregs->gdt.limit; 6822 dt.address = sregs->gdt.base; 6823 kvm_x86_ops->set_gdt(vcpu, &dt); 6824 6825 vcpu->arch.cr2 = sregs->cr2; 6826 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3; 6827 vcpu->arch.cr3 = sregs->cr3; 6828 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail); 6829 6830 kvm_set_cr8(vcpu, sregs->cr8); 6831 6832 mmu_reset_needed |= vcpu->arch.efer != sregs->efer; 6833 kvm_x86_ops->set_efer(vcpu, sregs->efer); 6834 apic_base_msr.data = sregs->apic_base; 6835 apic_base_msr.host_initiated = true; 6836 kvm_set_apic_base(vcpu, &apic_base_msr); 6837 6838 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0; 6839 kvm_x86_ops->set_cr0(vcpu, sregs->cr0); 6840 vcpu->arch.cr0 = sregs->cr0; 6841 6842 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4; 6843 kvm_x86_ops->set_cr4(vcpu, sregs->cr4); 6844 if (sregs->cr4 & X86_CR4_OSXSAVE) 6845 kvm_update_cpuid(vcpu); 6846 6847 idx = srcu_read_lock(&vcpu->kvm->srcu); 6848 if (!is_long_mode(vcpu) && is_pae(vcpu)) { 6849 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu)); 6850 mmu_reset_needed = 1; 6851 } 6852 srcu_read_unlock(&vcpu->kvm->srcu, idx); 6853 6854 if (mmu_reset_needed) 6855 kvm_mmu_reset_context(vcpu); 6856 6857 max_bits = KVM_NR_INTERRUPTS; 6858 pending_vec = find_first_bit( 6859 (const unsigned long *)sregs->interrupt_bitmap, max_bits); 6860 if (pending_vec < max_bits) { 6861 kvm_queue_interrupt(vcpu, pending_vec, false); 6862 pr_debug("Set back pending irq %d\n", pending_vec); 6863 } 6864 6865 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS); 6866 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS); 6867 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES); 6868 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS); 6869 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS); 6870 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS); 6871 6872 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR); 6873 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR); 6874 6875 update_cr8_intercept(vcpu); 6876 6877 /* Older userspace won't unhalt the vcpu on reset. */ 6878 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 && 6879 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 && 6880 !is_protmode(vcpu)) 6881 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; 6882 6883 kvm_make_request(KVM_REQ_EVENT, vcpu); 6884 6885 return 0; 6886 } 6887 6888 int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu, 6889 struct kvm_guest_debug *dbg) 6890 { 6891 unsigned long rflags; 6892 int i, r; 6893 6894 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) { 6895 r = -EBUSY; 6896 if (vcpu->arch.exception.pending) 6897 goto out; 6898 if (dbg->control & KVM_GUESTDBG_INJECT_DB) 6899 kvm_queue_exception(vcpu, DB_VECTOR); 6900 else 6901 kvm_queue_exception(vcpu, BP_VECTOR); 6902 } 6903 6904 /* 6905 * Read rflags as long as potentially injected trace flags are still 6906 * filtered out. 6907 */ 6908 rflags = kvm_get_rflags(vcpu); 6909 6910 vcpu->guest_debug = dbg->control; 6911 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE)) 6912 vcpu->guest_debug = 0; 6913 6914 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) { 6915 for (i = 0; i < KVM_NR_DB_REGS; ++i) 6916 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i]; 6917 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7]; 6918 } else { 6919 for (i = 0; i < KVM_NR_DB_REGS; i++) 6920 vcpu->arch.eff_db[i] = vcpu->arch.db[i]; 6921 } 6922 kvm_update_dr7(vcpu); 6923 6924 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) 6925 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) + 6926 get_segment_base(vcpu, VCPU_SREG_CS); 6927 6928 /* 6929 * Trigger an rflags update that will inject or remove the trace 6930 * flags. 6931 */ 6932 kvm_set_rflags(vcpu, rflags); 6933 6934 kvm_x86_ops->update_db_bp_intercept(vcpu); 6935 6936 r = 0; 6937 6938 out: 6939 6940 return r; 6941 } 6942 6943 /* 6944 * Translate a guest virtual address to a guest physical address. 6945 */ 6946 int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu, 6947 struct kvm_translation *tr) 6948 { 6949 unsigned long vaddr = tr->linear_address; 6950 gpa_t gpa; 6951 int idx; 6952 6953 idx = srcu_read_lock(&vcpu->kvm->srcu); 6954 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL); 6955 srcu_read_unlock(&vcpu->kvm->srcu, idx); 6956 tr->physical_address = gpa; 6957 tr->valid = gpa != UNMAPPED_GVA; 6958 tr->writeable = 1; 6959 tr->usermode = 0; 6960 6961 return 0; 6962 } 6963 6964 int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu) 6965 { 6966 struct fxregs_state *fxsave = 6967 &vcpu->arch.guest_fpu.state.fxsave; 6968 6969 memcpy(fpu->fpr, fxsave->st_space, 128); 6970 fpu->fcw = fxsave->cwd; 6971 fpu->fsw = fxsave->swd; 6972 fpu->ftwx = fxsave->twd; 6973 fpu->last_opcode = fxsave->fop; 6974 fpu->last_ip = fxsave->rip; 6975 fpu->last_dp = fxsave->rdp; 6976 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space); 6977 6978 return 0; 6979 } 6980 6981 int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu) 6982 { 6983 struct fxregs_state *fxsave = 6984 &vcpu->arch.guest_fpu.state.fxsave; 6985 6986 memcpy(fxsave->st_space, fpu->fpr, 128); 6987 fxsave->cwd = fpu->fcw; 6988 fxsave->swd = fpu->fsw; 6989 fxsave->twd = fpu->ftwx; 6990 fxsave->fop = fpu->last_opcode; 6991 fxsave->rip = fpu->last_ip; 6992 fxsave->rdp = fpu->last_dp; 6993 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space); 6994 6995 return 0; 6996 } 6997 6998 static void fx_init(struct kvm_vcpu *vcpu) 6999 { 7000 fpstate_init(&vcpu->arch.guest_fpu.state); 7001 if (cpu_has_xsaves) 7002 vcpu->arch.guest_fpu.state.xsave.header.xcomp_bv = 7003 host_xcr0 | XSTATE_COMPACTION_ENABLED; 7004 7005 /* 7006 * Ensure guest xcr0 is valid for loading 7007 */ 7008 vcpu->arch.xcr0 = XSTATE_FP; 7009 7010 vcpu->arch.cr0 |= X86_CR0_ET; 7011 } 7012 7013 void kvm_load_guest_fpu(struct kvm_vcpu *vcpu) 7014 { 7015 if (vcpu->guest_fpu_loaded) 7016 return; 7017 7018 /* 7019 * Restore all possible states in the guest, 7020 * and assume host would use all available bits. 7021 * Guest xcr0 would be loaded later. 7022 */ 7023 kvm_put_guest_xcr0(vcpu); 7024 vcpu->guest_fpu_loaded = 1; 7025 __kernel_fpu_begin(); 7026 __copy_kernel_to_fpregs(&vcpu->arch.guest_fpu.state); 7027 trace_kvm_fpu(1); 7028 } 7029 7030 void kvm_put_guest_fpu(struct kvm_vcpu *vcpu) 7031 { 7032 kvm_put_guest_xcr0(vcpu); 7033 7034 if (!vcpu->guest_fpu_loaded) { 7035 vcpu->fpu_counter = 0; 7036 return; 7037 } 7038 7039 vcpu->guest_fpu_loaded = 0; 7040 copy_fpregs_to_fpstate(&vcpu->arch.guest_fpu); 7041 __kernel_fpu_end(); 7042 ++vcpu->stat.fpu_reload; 7043 /* 7044 * If using eager FPU mode, or if the guest is a frequent user 7045 * of the FPU, just leave the FPU active for next time. 7046 * Every 255 times fpu_counter rolls over to 0; a guest that uses 7047 * the FPU in bursts will revert to loading it on demand. 7048 */ 7049 if (!vcpu->arch.eager_fpu) { 7050 if (++vcpu->fpu_counter < 5) 7051 kvm_make_request(KVM_REQ_DEACTIVATE_FPU, vcpu); 7052 } 7053 trace_kvm_fpu(0); 7054 } 7055 7056 void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu) 7057 { 7058 kvmclock_reset(vcpu); 7059 7060 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask); 7061 kvm_x86_ops->vcpu_free(vcpu); 7062 } 7063 7064 struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm, 7065 unsigned int id) 7066 { 7067 struct kvm_vcpu *vcpu; 7068 7069 if (check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0) 7070 printk_once(KERN_WARNING 7071 "kvm: SMP vm created on host with unstable TSC; " 7072 "guest TSC will not be reliable\n"); 7073 7074 vcpu = kvm_x86_ops->vcpu_create(kvm, id); 7075 7076 return vcpu; 7077 } 7078 7079 int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu) 7080 { 7081 int r; 7082 7083 kvm_vcpu_mtrr_init(vcpu); 7084 r = vcpu_load(vcpu); 7085 if (r) 7086 return r; 7087 kvm_vcpu_reset(vcpu, false); 7088 kvm_mmu_setup(vcpu); 7089 vcpu_put(vcpu); 7090 return r; 7091 } 7092 7093 void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu) 7094 { 7095 struct msr_data msr; 7096 struct kvm *kvm = vcpu->kvm; 7097 7098 if (vcpu_load(vcpu)) 7099 return; 7100 msr.data = 0x0; 7101 msr.index = MSR_IA32_TSC; 7102 msr.host_initiated = true; 7103 kvm_write_tsc(vcpu, &msr); 7104 vcpu_put(vcpu); 7105 7106 if (!kvmclock_periodic_sync) 7107 return; 7108 7109 schedule_delayed_work(&kvm->arch.kvmclock_sync_work, 7110 KVMCLOCK_SYNC_PERIOD); 7111 } 7112 7113 void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu) 7114 { 7115 int r; 7116 vcpu->arch.apf.msr_val = 0; 7117 7118 r = vcpu_load(vcpu); 7119 BUG_ON(r); 7120 kvm_mmu_unload(vcpu); 7121 vcpu_put(vcpu); 7122 7123 kvm_x86_ops->vcpu_free(vcpu); 7124 } 7125 7126 void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event) 7127 { 7128 vcpu->arch.hflags = 0; 7129 7130 atomic_set(&vcpu->arch.nmi_queued, 0); 7131 vcpu->arch.nmi_pending = 0; 7132 vcpu->arch.nmi_injected = false; 7133 kvm_clear_interrupt_queue(vcpu); 7134 kvm_clear_exception_queue(vcpu); 7135 7136 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db)); 7137 kvm_update_dr0123(vcpu); 7138 vcpu->arch.dr6 = DR6_INIT; 7139 kvm_update_dr6(vcpu); 7140 vcpu->arch.dr7 = DR7_FIXED_1; 7141 kvm_update_dr7(vcpu); 7142 7143 vcpu->arch.cr2 = 0; 7144 7145 kvm_make_request(KVM_REQ_EVENT, vcpu); 7146 vcpu->arch.apf.msr_val = 0; 7147 vcpu->arch.st.msr_val = 0; 7148 7149 kvmclock_reset(vcpu); 7150 7151 kvm_clear_async_pf_completion_queue(vcpu); 7152 kvm_async_pf_hash_reset(vcpu); 7153 vcpu->arch.apf.halted = false; 7154 7155 if (!init_event) { 7156 kvm_pmu_reset(vcpu); 7157 vcpu->arch.smbase = 0x30000; 7158 } 7159 7160 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs)); 7161 vcpu->arch.regs_avail = ~0; 7162 vcpu->arch.regs_dirty = ~0; 7163 7164 kvm_x86_ops->vcpu_reset(vcpu, init_event); 7165 } 7166 7167 void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector) 7168 { 7169 struct kvm_segment cs; 7170 7171 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS); 7172 cs.selector = vector << 8; 7173 cs.base = vector << 12; 7174 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS); 7175 kvm_rip_write(vcpu, 0); 7176 } 7177 7178 int kvm_arch_hardware_enable(void) 7179 { 7180 struct kvm *kvm; 7181 struct kvm_vcpu *vcpu; 7182 int i; 7183 int ret; 7184 u64 local_tsc; 7185 u64 max_tsc = 0; 7186 bool stable, backwards_tsc = false; 7187 7188 kvm_shared_msr_cpu_online(); 7189 ret = kvm_x86_ops->hardware_enable(); 7190 if (ret != 0) 7191 return ret; 7192 7193 local_tsc = rdtsc(); 7194 stable = !check_tsc_unstable(); 7195 list_for_each_entry(kvm, &vm_list, vm_list) { 7196 kvm_for_each_vcpu(i, vcpu, kvm) { 7197 if (!stable && vcpu->cpu == smp_processor_id()) 7198 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 7199 if (stable && vcpu->arch.last_host_tsc > local_tsc) { 7200 backwards_tsc = true; 7201 if (vcpu->arch.last_host_tsc > max_tsc) 7202 max_tsc = vcpu->arch.last_host_tsc; 7203 } 7204 } 7205 } 7206 7207 /* 7208 * Sometimes, even reliable TSCs go backwards. This happens on 7209 * platforms that reset TSC during suspend or hibernate actions, but 7210 * maintain synchronization. We must compensate. Fortunately, we can 7211 * detect that condition here, which happens early in CPU bringup, 7212 * before any KVM threads can be running. Unfortunately, we can't 7213 * bring the TSCs fully up to date with real time, as we aren't yet far 7214 * enough into CPU bringup that we know how much real time has actually 7215 * elapsed; our helper function, get_kernel_ns() will be using boot 7216 * variables that haven't been updated yet. 7217 * 7218 * So we simply find the maximum observed TSC above, then record the 7219 * adjustment to TSC in each VCPU. When the VCPU later gets loaded, 7220 * the adjustment will be applied. Note that we accumulate 7221 * adjustments, in case multiple suspend cycles happen before some VCPU 7222 * gets a chance to run again. In the event that no KVM threads get a 7223 * chance to run, we will miss the entire elapsed period, as we'll have 7224 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may 7225 * loose cycle time. This isn't too big a deal, since the loss will be 7226 * uniform across all VCPUs (not to mention the scenario is extremely 7227 * unlikely). It is possible that a second hibernate recovery happens 7228 * much faster than a first, causing the observed TSC here to be 7229 * smaller; this would require additional padding adjustment, which is 7230 * why we set last_host_tsc to the local tsc observed here. 7231 * 7232 * N.B. - this code below runs only on platforms with reliable TSC, 7233 * as that is the only way backwards_tsc is set above. Also note 7234 * that this runs for ALL vcpus, which is not a bug; all VCPUs should 7235 * have the same delta_cyc adjustment applied if backwards_tsc 7236 * is detected. Note further, this adjustment is only done once, 7237 * as we reset last_host_tsc on all VCPUs to stop this from being 7238 * called multiple times (one for each physical CPU bringup). 7239 * 7240 * Platforms with unreliable TSCs don't have to deal with this, they 7241 * will be compensated by the logic in vcpu_load, which sets the TSC to 7242 * catchup mode. This will catchup all VCPUs to real time, but cannot 7243 * guarantee that they stay in perfect synchronization. 7244 */ 7245 if (backwards_tsc) { 7246 u64 delta_cyc = max_tsc - local_tsc; 7247 backwards_tsc_observed = true; 7248 list_for_each_entry(kvm, &vm_list, vm_list) { 7249 kvm_for_each_vcpu(i, vcpu, kvm) { 7250 vcpu->arch.tsc_offset_adjustment += delta_cyc; 7251 vcpu->arch.last_host_tsc = local_tsc; 7252 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu); 7253 } 7254 7255 /* 7256 * We have to disable TSC offset matching.. if you were 7257 * booting a VM while issuing an S4 host suspend.... 7258 * you may have some problem. Solving this issue is 7259 * left as an exercise to the reader. 7260 */ 7261 kvm->arch.last_tsc_nsec = 0; 7262 kvm->arch.last_tsc_write = 0; 7263 } 7264 7265 } 7266 return 0; 7267 } 7268 7269 void kvm_arch_hardware_disable(void) 7270 { 7271 kvm_x86_ops->hardware_disable(); 7272 drop_user_return_notifiers(); 7273 } 7274 7275 int kvm_arch_hardware_setup(void) 7276 { 7277 int r; 7278 7279 r = kvm_x86_ops->hardware_setup(); 7280 if (r != 0) 7281 return r; 7282 7283 kvm_init_msr_list(); 7284 return 0; 7285 } 7286 7287 void kvm_arch_hardware_unsetup(void) 7288 { 7289 kvm_x86_ops->hardware_unsetup(); 7290 } 7291 7292 void kvm_arch_check_processor_compat(void *rtn) 7293 { 7294 kvm_x86_ops->check_processor_compatibility(rtn); 7295 } 7296 7297 bool kvm_vcpu_is_reset_bsp(struct kvm_vcpu *vcpu) 7298 { 7299 return vcpu->kvm->arch.bsp_vcpu_id == vcpu->vcpu_id; 7300 } 7301 EXPORT_SYMBOL_GPL(kvm_vcpu_is_reset_bsp); 7302 7303 bool kvm_vcpu_is_bsp(struct kvm_vcpu *vcpu) 7304 { 7305 return (vcpu->arch.apic_base & MSR_IA32_APICBASE_BSP) != 0; 7306 } 7307 7308 bool kvm_vcpu_compatible(struct kvm_vcpu *vcpu) 7309 { 7310 return irqchip_in_kernel(vcpu->kvm) == (vcpu->arch.apic != NULL); 7311 } 7312 7313 struct static_key kvm_no_apic_vcpu __read_mostly; 7314 7315 int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu) 7316 { 7317 struct page *page; 7318 struct kvm *kvm; 7319 int r; 7320 7321 BUG_ON(vcpu->kvm == NULL); 7322 kvm = vcpu->kvm; 7323 7324 vcpu->arch.pv.pv_unhalted = false; 7325 vcpu->arch.emulate_ctxt.ops = &emulate_ops; 7326 if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_reset_bsp(vcpu)) 7327 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; 7328 else 7329 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED; 7330 7331 page = alloc_page(GFP_KERNEL | __GFP_ZERO); 7332 if (!page) { 7333 r = -ENOMEM; 7334 goto fail; 7335 } 7336 vcpu->arch.pio_data = page_address(page); 7337 7338 kvm_set_tsc_khz(vcpu, max_tsc_khz); 7339 7340 r = kvm_mmu_create(vcpu); 7341 if (r < 0) 7342 goto fail_free_pio_data; 7343 7344 if (irqchip_in_kernel(kvm)) { 7345 r = kvm_create_lapic(vcpu); 7346 if (r < 0) 7347 goto fail_mmu_destroy; 7348 } else 7349 static_key_slow_inc(&kvm_no_apic_vcpu); 7350 7351 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4, 7352 GFP_KERNEL); 7353 if (!vcpu->arch.mce_banks) { 7354 r = -ENOMEM; 7355 goto fail_free_lapic; 7356 } 7357 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS; 7358 7359 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL)) { 7360 r = -ENOMEM; 7361 goto fail_free_mce_banks; 7362 } 7363 7364 fx_init(vcpu); 7365 7366 vcpu->arch.ia32_tsc_adjust_msr = 0x0; 7367 vcpu->arch.pv_time_enabled = false; 7368 7369 vcpu->arch.guest_supported_xcr0 = 0; 7370 vcpu->arch.guest_xstate_size = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET; 7371 7372 vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu); 7373 7374 vcpu->arch.pat = MSR_IA32_CR_PAT_DEFAULT; 7375 7376 kvm_async_pf_hash_reset(vcpu); 7377 kvm_pmu_init(vcpu); 7378 7379 return 0; 7380 7381 fail_free_mce_banks: 7382 kfree(vcpu->arch.mce_banks); 7383 fail_free_lapic: 7384 kvm_free_lapic(vcpu); 7385 fail_mmu_destroy: 7386 kvm_mmu_destroy(vcpu); 7387 fail_free_pio_data: 7388 free_page((unsigned long)vcpu->arch.pio_data); 7389 fail: 7390 return r; 7391 } 7392 7393 void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu) 7394 { 7395 int idx; 7396 7397 kvm_pmu_destroy(vcpu); 7398 kfree(vcpu->arch.mce_banks); 7399 kvm_free_lapic(vcpu); 7400 idx = srcu_read_lock(&vcpu->kvm->srcu); 7401 kvm_mmu_destroy(vcpu); 7402 srcu_read_unlock(&vcpu->kvm->srcu, idx); 7403 free_page((unsigned long)vcpu->arch.pio_data); 7404 if (!irqchip_in_kernel(vcpu->kvm)) 7405 static_key_slow_dec(&kvm_no_apic_vcpu); 7406 } 7407 7408 void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu) 7409 { 7410 kvm_x86_ops->sched_in(vcpu, cpu); 7411 } 7412 7413 int kvm_arch_init_vm(struct kvm *kvm, unsigned long type) 7414 { 7415 if (type) 7416 return -EINVAL; 7417 7418 INIT_HLIST_HEAD(&kvm->arch.mask_notifier_list); 7419 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages); 7420 INIT_LIST_HEAD(&kvm->arch.zapped_obsolete_pages); 7421 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head); 7422 atomic_set(&kvm->arch.noncoherent_dma_count, 0); 7423 7424 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */ 7425 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap); 7426 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */ 7427 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID, 7428 &kvm->arch.irq_sources_bitmap); 7429 7430 raw_spin_lock_init(&kvm->arch.tsc_write_lock); 7431 mutex_init(&kvm->arch.apic_map_lock); 7432 spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock); 7433 7434 pvclock_update_vm_gtod_copy(kvm); 7435 7436 INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn); 7437 INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn); 7438 7439 return 0; 7440 } 7441 7442 static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu) 7443 { 7444 int r; 7445 r = vcpu_load(vcpu); 7446 BUG_ON(r); 7447 kvm_mmu_unload(vcpu); 7448 vcpu_put(vcpu); 7449 } 7450 7451 static void kvm_free_vcpus(struct kvm *kvm) 7452 { 7453 unsigned int i; 7454 struct kvm_vcpu *vcpu; 7455 7456 /* 7457 * Unpin any mmu pages first. 7458 */ 7459 kvm_for_each_vcpu(i, vcpu, kvm) { 7460 kvm_clear_async_pf_completion_queue(vcpu); 7461 kvm_unload_vcpu_mmu(vcpu); 7462 } 7463 kvm_for_each_vcpu(i, vcpu, kvm) 7464 kvm_arch_vcpu_free(vcpu); 7465 7466 mutex_lock(&kvm->lock); 7467 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++) 7468 kvm->vcpus[i] = NULL; 7469 7470 atomic_set(&kvm->online_vcpus, 0); 7471 mutex_unlock(&kvm->lock); 7472 } 7473 7474 void kvm_arch_sync_events(struct kvm *kvm) 7475 { 7476 cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work); 7477 cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work); 7478 kvm_free_all_assigned_devices(kvm); 7479 kvm_free_pit(kvm); 7480 } 7481 7482 int __x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size) 7483 { 7484 int i, r; 7485 unsigned long hva; 7486 struct kvm_memslots *slots = kvm_memslots(kvm); 7487 struct kvm_memory_slot *slot, old; 7488 7489 /* Called with kvm->slots_lock held. */ 7490 if (WARN_ON(id >= KVM_MEM_SLOTS_NUM)) 7491 return -EINVAL; 7492 7493 slot = id_to_memslot(slots, id); 7494 if (size) { 7495 if (WARN_ON(slot->npages)) 7496 return -EEXIST; 7497 7498 /* 7499 * MAP_SHARED to prevent internal slot pages from being moved 7500 * by fork()/COW. 7501 */ 7502 hva = vm_mmap(NULL, 0, size, PROT_READ | PROT_WRITE, 7503 MAP_SHARED | MAP_ANONYMOUS, 0); 7504 if (IS_ERR((void *)hva)) 7505 return PTR_ERR((void *)hva); 7506 } else { 7507 if (!slot->npages) 7508 return 0; 7509 7510 hva = 0; 7511 } 7512 7513 old = *slot; 7514 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) { 7515 struct kvm_userspace_memory_region m; 7516 7517 m.slot = id | (i << 16); 7518 m.flags = 0; 7519 m.guest_phys_addr = gpa; 7520 m.userspace_addr = hva; 7521 m.memory_size = size; 7522 r = __kvm_set_memory_region(kvm, &m); 7523 if (r < 0) 7524 return r; 7525 } 7526 7527 if (!size) { 7528 r = vm_munmap(old.userspace_addr, old.npages * PAGE_SIZE); 7529 WARN_ON(r < 0); 7530 } 7531 7532 return 0; 7533 } 7534 EXPORT_SYMBOL_GPL(__x86_set_memory_region); 7535 7536 int x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size) 7537 { 7538 int r; 7539 7540 mutex_lock(&kvm->slots_lock); 7541 r = __x86_set_memory_region(kvm, id, gpa, size); 7542 mutex_unlock(&kvm->slots_lock); 7543 7544 return r; 7545 } 7546 EXPORT_SYMBOL_GPL(x86_set_memory_region); 7547 7548 void kvm_arch_destroy_vm(struct kvm *kvm) 7549 { 7550 if (current->mm == kvm->mm) { 7551 /* 7552 * Free memory regions allocated on behalf of userspace, 7553 * unless the the memory map has changed due to process exit 7554 * or fd copying. 7555 */ 7556 x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT, 0, 0); 7557 x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT, 0, 0); 7558 x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, 0, 0); 7559 } 7560 kvm_iommu_unmap_guest(kvm); 7561 kfree(kvm->arch.vpic); 7562 kfree(kvm->arch.vioapic); 7563 kvm_free_vcpus(kvm); 7564 kfree(rcu_dereference_check(kvm->arch.apic_map, 1)); 7565 } 7566 7567 void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *free, 7568 struct kvm_memory_slot *dont) 7569 { 7570 int i; 7571 7572 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) { 7573 if (!dont || free->arch.rmap[i] != dont->arch.rmap[i]) { 7574 kvfree(free->arch.rmap[i]); 7575 free->arch.rmap[i] = NULL; 7576 } 7577 if (i == 0) 7578 continue; 7579 7580 if (!dont || free->arch.lpage_info[i - 1] != 7581 dont->arch.lpage_info[i - 1]) { 7582 kvfree(free->arch.lpage_info[i - 1]); 7583 free->arch.lpage_info[i - 1] = NULL; 7584 } 7585 } 7586 } 7587 7588 int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot, 7589 unsigned long npages) 7590 { 7591 int i; 7592 7593 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) { 7594 unsigned long ugfn; 7595 int lpages; 7596 int level = i + 1; 7597 7598 lpages = gfn_to_index(slot->base_gfn + npages - 1, 7599 slot->base_gfn, level) + 1; 7600 7601 slot->arch.rmap[i] = 7602 kvm_kvzalloc(lpages * sizeof(*slot->arch.rmap[i])); 7603 if (!slot->arch.rmap[i]) 7604 goto out_free; 7605 if (i == 0) 7606 continue; 7607 7608 slot->arch.lpage_info[i - 1] = kvm_kvzalloc(lpages * 7609 sizeof(*slot->arch.lpage_info[i - 1])); 7610 if (!slot->arch.lpage_info[i - 1]) 7611 goto out_free; 7612 7613 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1)) 7614 slot->arch.lpage_info[i - 1][0].write_count = 1; 7615 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1)) 7616 slot->arch.lpage_info[i - 1][lpages - 1].write_count = 1; 7617 ugfn = slot->userspace_addr >> PAGE_SHIFT; 7618 /* 7619 * If the gfn and userspace address are not aligned wrt each 7620 * other, or if explicitly asked to, disable large page 7621 * support for this slot 7622 */ 7623 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) || 7624 !kvm_largepages_enabled()) { 7625 unsigned long j; 7626 7627 for (j = 0; j < lpages; ++j) 7628 slot->arch.lpage_info[i - 1][j].write_count = 1; 7629 } 7630 } 7631 7632 return 0; 7633 7634 out_free: 7635 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) { 7636 kvfree(slot->arch.rmap[i]); 7637 slot->arch.rmap[i] = NULL; 7638 if (i == 0) 7639 continue; 7640 7641 kvfree(slot->arch.lpage_info[i - 1]); 7642 slot->arch.lpage_info[i - 1] = NULL; 7643 } 7644 return -ENOMEM; 7645 } 7646 7647 void kvm_arch_memslots_updated(struct kvm *kvm, struct kvm_memslots *slots) 7648 { 7649 /* 7650 * memslots->generation has been incremented. 7651 * mmio generation may have reached its maximum value. 7652 */ 7653 kvm_mmu_invalidate_mmio_sptes(kvm, slots); 7654 } 7655 7656 int kvm_arch_prepare_memory_region(struct kvm *kvm, 7657 struct kvm_memory_slot *memslot, 7658 const struct kvm_userspace_memory_region *mem, 7659 enum kvm_mr_change change) 7660 { 7661 return 0; 7662 } 7663 7664 static void kvm_mmu_slot_apply_flags(struct kvm *kvm, 7665 struct kvm_memory_slot *new) 7666 { 7667 /* Still write protect RO slot */ 7668 if (new->flags & KVM_MEM_READONLY) { 7669 kvm_mmu_slot_remove_write_access(kvm, new); 7670 return; 7671 } 7672 7673 /* 7674 * Call kvm_x86_ops dirty logging hooks when they are valid. 7675 * 7676 * kvm_x86_ops->slot_disable_log_dirty is called when: 7677 * 7678 * - KVM_MR_CREATE with dirty logging is disabled 7679 * - KVM_MR_FLAGS_ONLY with dirty logging is disabled in new flag 7680 * 7681 * The reason is, in case of PML, we need to set D-bit for any slots 7682 * with dirty logging disabled in order to eliminate unnecessary GPA 7683 * logging in PML buffer (and potential PML buffer full VMEXT). This 7684 * guarantees leaving PML enabled during guest's lifetime won't have 7685 * any additonal overhead from PML when guest is running with dirty 7686 * logging disabled for memory slots. 7687 * 7688 * kvm_x86_ops->slot_enable_log_dirty is called when switching new slot 7689 * to dirty logging mode. 7690 * 7691 * If kvm_x86_ops dirty logging hooks are invalid, use write protect. 7692 * 7693 * In case of write protect: 7694 * 7695 * Write protect all pages for dirty logging. 7696 * 7697 * All the sptes including the large sptes which point to this 7698 * slot are set to readonly. We can not create any new large 7699 * spte on this slot until the end of the logging. 7700 * 7701 * See the comments in fast_page_fault(). 7702 */ 7703 if (new->flags & KVM_MEM_LOG_DIRTY_PAGES) { 7704 if (kvm_x86_ops->slot_enable_log_dirty) 7705 kvm_x86_ops->slot_enable_log_dirty(kvm, new); 7706 else 7707 kvm_mmu_slot_remove_write_access(kvm, new); 7708 } else { 7709 if (kvm_x86_ops->slot_disable_log_dirty) 7710 kvm_x86_ops->slot_disable_log_dirty(kvm, new); 7711 } 7712 } 7713 7714 void kvm_arch_commit_memory_region(struct kvm *kvm, 7715 const struct kvm_userspace_memory_region *mem, 7716 const struct kvm_memory_slot *old, 7717 const struct kvm_memory_slot *new, 7718 enum kvm_mr_change change) 7719 { 7720 int nr_mmu_pages = 0; 7721 7722 if (!kvm->arch.n_requested_mmu_pages) 7723 nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm); 7724 7725 if (nr_mmu_pages) 7726 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages); 7727 7728 /* 7729 * Dirty logging tracks sptes in 4k granularity, meaning that large 7730 * sptes have to be split. If live migration is successful, the guest 7731 * in the source machine will be destroyed and large sptes will be 7732 * created in the destination. However, if the guest continues to run 7733 * in the source machine (for example if live migration fails), small 7734 * sptes will remain around and cause bad performance. 7735 * 7736 * Scan sptes if dirty logging has been stopped, dropping those 7737 * which can be collapsed into a single large-page spte. Later 7738 * page faults will create the large-page sptes. 7739 */ 7740 if ((change != KVM_MR_DELETE) && 7741 (old->flags & KVM_MEM_LOG_DIRTY_PAGES) && 7742 !(new->flags & KVM_MEM_LOG_DIRTY_PAGES)) 7743 kvm_mmu_zap_collapsible_sptes(kvm, new); 7744 7745 /* 7746 * Set up write protection and/or dirty logging for the new slot. 7747 * 7748 * For KVM_MR_DELETE and KVM_MR_MOVE, the shadow pages of old slot have 7749 * been zapped so no dirty logging staff is needed for old slot. For 7750 * KVM_MR_FLAGS_ONLY, the old slot is essentially the same one as the 7751 * new and it's also covered when dealing with the new slot. 7752 * 7753 * FIXME: const-ify all uses of struct kvm_memory_slot. 7754 */ 7755 if (change != KVM_MR_DELETE) 7756 kvm_mmu_slot_apply_flags(kvm, (struct kvm_memory_slot *) new); 7757 } 7758 7759 void kvm_arch_flush_shadow_all(struct kvm *kvm) 7760 { 7761 kvm_mmu_invalidate_zap_all_pages(kvm); 7762 } 7763 7764 void kvm_arch_flush_shadow_memslot(struct kvm *kvm, 7765 struct kvm_memory_slot *slot) 7766 { 7767 kvm_mmu_invalidate_zap_all_pages(kvm); 7768 } 7769 7770 static inline bool kvm_vcpu_has_events(struct kvm_vcpu *vcpu) 7771 { 7772 if (!list_empty_careful(&vcpu->async_pf.done)) 7773 return true; 7774 7775 if (kvm_apic_has_events(vcpu)) 7776 return true; 7777 7778 if (vcpu->arch.pv.pv_unhalted) 7779 return true; 7780 7781 if (atomic_read(&vcpu->arch.nmi_queued)) 7782 return true; 7783 7784 if (test_bit(KVM_REQ_SMI, &vcpu->requests)) 7785 return true; 7786 7787 if (kvm_arch_interrupt_allowed(vcpu) && 7788 kvm_cpu_has_interrupt(vcpu)) 7789 return true; 7790 7791 return false; 7792 } 7793 7794 int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu) 7795 { 7796 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) 7797 kvm_x86_ops->check_nested_events(vcpu, false); 7798 7799 return kvm_vcpu_running(vcpu) || kvm_vcpu_has_events(vcpu); 7800 } 7801 7802 int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu) 7803 { 7804 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE; 7805 } 7806 7807 int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu) 7808 { 7809 return kvm_x86_ops->interrupt_allowed(vcpu); 7810 } 7811 7812 unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu) 7813 { 7814 if (is_64_bit_mode(vcpu)) 7815 return kvm_rip_read(vcpu); 7816 return (u32)(get_segment_base(vcpu, VCPU_SREG_CS) + 7817 kvm_rip_read(vcpu)); 7818 } 7819 EXPORT_SYMBOL_GPL(kvm_get_linear_rip); 7820 7821 bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip) 7822 { 7823 return kvm_get_linear_rip(vcpu) == linear_rip; 7824 } 7825 EXPORT_SYMBOL_GPL(kvm_is_linear_rip); 7826 7827 unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu) 7828 { 7829 unsigned long rflags; 7830 7831 rflags = kvm_x86_ops->get_rflags(vcpu); 7832 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) 7833 rflags &= ~X86_EFLAGS_TF; 7834 return rflags; 7835 } 7836 EXPORT_SYMBOL_GPL(kvm_get_rflags); 7837 7838 static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags) 7839 { 7840 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP && 7841 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip)) 7842 rflags |= X86_EFLAGS_TF; 7843 kvm_x86_ops->set_rflags(vcpu, rflags); 7844 } 7845 7846 void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags) 7847 { 7848 __kvm_set_rflags(vcpu, rflags); 7849 kvm_make_request(KVM_REQ_EVENT, vcpu); 7850 } 7851 EXPORT_SYMBOL_GPL(kvm_set_rflags); 7852 7853 void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work) 7854 { 7855 int r; 7856 7857 if ((vcpu->arch.mmu.direct_map != work->arch.direct_map) || 7858 work->wakeup_all) 7859 return; 7860 7861 r = kvm_mmu_reload(vcpu); 7862 if (unlikely(r)) 7863 return; 7864 7865 if (!vcpu->arch.mmu.direct_map && 7866 work->arch.cr3 != vcpu->arch.mmu.get_cr3(vcpu)) 7867 return; 7868 7869 vcpu->arch.mmu.page_fault(vcpu, work->gva, 0, true); 7870 } 7871 7872 static inline u32 kvm_async_pf_hash_fn(gfn_t gfn) 7873 { 7874 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU)); 7875 } 7876 7877 static inline u32 kvm_async_pf_next_probe(u32 key) 7878 { 7879 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1); 7880 } 7881 7882 static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn) 7883 { 7884 u32 key = kvm_async_pf_hash_fn(gfn); 7885 7886 while (vcpu->arch.apf.gfns[key] != ~0) 7887 key = kvm_async_pf_next_probe(key); 7888 7889 vcpu->arch.apf.gfns[key] = gfn; 7890 } 7891 7892 static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn) 7893 { 7894 int i; 7895 u32 key = kvm_async_pf_hash_fn(gfn); 7896 7897 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) && 7898 (vcpu->arch.apf.gfns[key] != gfn && 7899 vcpu->arch.apf.gfns[key] != ~0); i++) 7900 key = kvm_async_pf_next_probe(key); 7901 7902 return key; 7903 } 7904 7905 bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn) 7906 { 7907 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn; 7908 } 7909 7910 static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn) 7911 { 7912 u32 i, j, k; 7913 7914 i = j = kvm_async_pf_gfn_slot(vcpu, gfn); 7915 while (true) { 7916 vcpu->arch.apf.gfns[i] = ~0; 7917 do { 7918 j = kvm_async_pf_next_probe(j); 7919 if (vcpu->arch.apf.gfns[j] == ~0) 7920 return; 7921 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]); 7922 /* 7923 * k lies cyclically in ]i,j] 7924 * | i.k.j | 7925 * |....j i.k.| or |.k..j i...| 7926 */ 7927 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j)); 7928 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j]; 7929 i = j; 7930 } 7931 } 7932 7933 static int apf_put_user(struct kvm_vcpu *vcpu, u32 val) 7934 { 7935 7936 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val, 7937 sizeof(val)); 7938 } 7939 7940 void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu, 7941 struct kvm_async_pf *work) 7942 { 7943 struct x86_exception fault; 7944 7945 trace_kvm_async_pf_not_present(work->arch.token, work->gva); 7946 kvm_add_async_pf_gfn(vcpu, work->arch.gfn); 7947 7948 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) || 7949 (vcpu->arch.apf.send_user_only && 7950 kvm_x86_ops->get_cpl(vcpu) == 0)) 7951 kvm_make_request(KVM_REQ_APF_HALT, vcpu); 7952 else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) { 7953 fault.vector = PF_VECTOR; 7954 fault.error_code_valid = true; 7955 fault.error_code = 0; 7956 fault.nested_page_fault = false; 7957 fault.address = work->arch.token; 7958 kvm_inject_page_fault(vcpu, &fault); 7959 } 7960 } 7961 7962 void kvm_arch_async_page_present(struct kvm_vcpu *vcpu, 7963 struct kvm_async_pf *work) 7964 { 7965 struct x86_exception fault; 7966 7967 trace_kvm_async_pf_ready(work->arch.token, work->gva); 7968 if (work->wakeup_all) 7969 work->arch.token = ~0; /* broadcast wakeup */ 7970 else 7971 kvm_del_async_pf_gfn(vcpu, work->arch.gfn); 7972 7973 if ((vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) && 7974 !apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) { 7975 fault.vector = PF_VECTOR; 7976 fault.error_code_valid = true; 7977 fault.error_code = 0; 7978 fault.nested_page_fault = false; 7979 fault.address = work->arch.token; 7980 kvm_inject_page_fault(vcpu, &fault); 7981 } 7982 vcpu->arch.apf.halted = false; 7983 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; 7984 } 7985 7986 bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu) 7987 { 7988 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED)) 7989 return true; 7990 else 7991 return !kvm_event_needs_reinjection(vcpu) && 7992 kvm_x86_ops->interrupt_allowed(vcpu); 7993 } 7994 7995 void kvm_arch_start_assignment(struct kvm *kvm) 7996 { 7997 atomic_inc(&kvm->arch.assigned_device_count); 7998 } 7999 EXPORT_SYMBOL_GPL(kvm_arch_start_assignment); 8000 8001 void kvm_arch_end_assignment(struct kvm *kvm) 8002 { 8003 atomic_dec(&kvm->arch.assigned_device_count); 8004 } 8005 EXPORT_SYMBOL_GPL(kvm_arch_end_assignment); 8006 8007 bool kvm_arch_has_assigned_device(struct kvm *kvm) 8008 { 8009 return atomic_read(&kvm->arch.assigned_device_count); 8010 } 8011 EXPORT_SYMBOL_GPL(kvm_arch_has_assigned_device); 8012 8013 void kvm_arch_register_noncoherent_dma(struct kvm *kvm) 8014 { 8015 atomic_inc(&kvm->arch.noncoherent_dma_count); 8016 } 8017 EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma); 8018 8019 void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm) 8020 { 8021 atomic_dec(&kvm->arch.noncoherent_dma_count); 8022 } 8023 EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma); 8024 8025 bool kvm_arch_has_noncoherent_dma(struct kvm *kvm) 8026 { 8027 return atomic_read(&kvm->arch.noncoherent_dma_count); 8028 } 8029 EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma); 8030 8031 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit); 8032 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq); 8033 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault); 8034 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr); 8035 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr); 8036 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun); 8037 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit); 8038 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject); 8039 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit); 8040 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga); 8041 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit); 8042 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts); 8043 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset); 8044 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_ple_window); 8045 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pml_full); 8046