1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Kernel-based Virtual Machine driver for Linux 4 * 5 * derived from drivers/kvm/kvm_main.c 6 * 7 * Copyright (C) 2006 Qumranet, Inc. 8 * Copyright (C) 2008 Qumranet, Inc. 9 * Copyright IBM Corporation, 2008 10 * Copyright 2010 Red Hat, Inc. and/or its affiliates. 11 * 12 * Authors: 13 * Avi Kivity <avi@qumranet.com> 14 * Yaniv Kamay <yaniv@qumranet.com> 15 * Amit Shah <amit.shah@qumranet.com> 16 * Ben-Ami Yassour <benami@il.ibm.com> 17 */ 18 19 #include <linux/kvm_host.h> 20 #include "irq.h" 21 #include "ioapic.h" 22 #include "mmu.h" 23 #include "i8254.h" 24 #include "tss.h" 25 #include "kvm_cache_regs.h" 26 #include "kvm_emulate.h" 27 #include "x86.h" 28 #include "cpuid.h" 29 #include "pmu.h" 30 #include "hyperv.h" 31 #include "lapic.h" 32 #include "xen.h" 33 34 #include <linux/clocksource.h> 35 #include <linux/interrupt.h> 36 #include <linux/kvm.h> 37 #include <linux/fs.h> 38 #include <linux/vmalloc.h> 39 #include <linux/export.h> 40 #include <linux/moduleparam.h> 41 #include <linux/mman.h> 42 #include <linux/highmem.h> 43 #include <linux/iommu.h> 44 #include <linux/intel-iommu.h> 45 #include <linux/cpufreq.h> 46 #include <linux/user-return-notifier.h> 47 #include <linux/srcu.h> 48 #include <linux/slab.h> 49 #include <linux/perf_event.h> 50 #include <linux/uaccess.h> 51 #include <linux/hash.h> 52 #include <linux/pci.h> 53 #include <linux/timekeeper_internal.h> 54 #include <linux/pvclock_gtod.h> 55 #include <linux/kvm_irqfd.h> 56 #include <linux/irqbypass.h> 57 #include <linux/sched/stat.h> 58 #include <linux/sched/isolation.h> 59 #include <linux/mem_encrypt.h> 60 #include <linux/entry-kvm.h> 61 62 #include <trace/events/kvm.h> 63 64 #include <asm/debugreg.h> 65 #include <asm/msr.h> 66 #include <asm/desc.h> 67 #include <asm/mce.h> 68 #include <linux/kernel_stat.h> 69 #include <asm/fpu/internal.h> /* Ugh! */ 70 #include <asm/pvclock.h> 71 #include <asm/div64.h> 72 #include <asm/irq_remapping.h> 73 #include <asm/mshyperv.h> 74 #include <asm/hypervisor.h> 75 #include <asm/tlbflush.h> 76 #include <asm/intel_pt.h> 77 #include <asm/emulate_prefix.h> 78 #include <asm/sgx.h> 79 #include <clocksource/hyperv_timer.h> 80 81 #define CREATE_TRACE_POINTS 82 #include "trace.h" 83 84 #define MAX_IO_MSRS 256 85 #define KVM_MAX_MCE_BANKS 32 86 u64 __read_mostly kvm_mce_cap_supported = MCG_CTL_P | MCG_SER_P; 87 EXPORT_SYMBOL_GPL(kvm_mce_cap_supported); 88 89 #define emul_to_vcpu(ctxt) \ 90 ((struct kvm_vcpu *)(ctxt)->vcpu) 91 92 /* EFER defaults: 93 * - enable syscall per default because its emulated by KVM 94 * - enable LME and LMA per default on 64 bit KVM 95 */ 96 #ifdef CONFIG_X86_64 97 static 98 u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA)); 99 #else 100 static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE); 101 #endif 102 103 static u64 __read_mostly cr4_reserved_bits = CR4_RESERVED_BITS; 104 105 #define KVM_X2APIC_API_VALID_FLAGS (KVM_X2APIC_API_USE_32BIT_IDS | \ 106 KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK) 107 108 static void update_cr8_intercept(struct kvm_vcpu *vcpu); 109 static void process_nmi(struct kvm_vcpu *vcpu); 110 static void process_smi(struct kvm_vcpu *vcpu); 111 static void enter_smm(struct kvm_vcpu *vcpu); 112 static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags); 113 static void store_regs(struct kvm_vcpu *vcpu); 114 static int sync_regs(struct kvm_vcpu *vcpu); 115 116 struct kvm_x86_ops kvm_x86_ops __read_mostly; 117 EXPORT_SYMBOL_GPL(kvm_x86_ops); 118 119 #define KVM_X86_OP(func) \ 120 DEFINE_STATIC_CALL_NULL(kvm_x86_##func, \ 121 *(((struct kvm_x86_ops *)0)->func)); 122 #define KVM_X86_OP_NULL KVM_X86_OP 123 #include <asm/kvm-x86-ops.h> 124 EXPORT_STATIC_CALL_GPL(kvm_x86_get_cs_db_l_bits); 125 EXPORT_STATIC_CALL_GPL(kvm_x86_cache_reg); 126 EXPORT_STATIC_CALL_GPL(kvm_x86_tlb_flush_current); 127 128 static bool __read_mostly ignore_msrs = 0; 129 module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR); 130 131 bool __read_mostly report_ignored_msrs = true; 132 module_param(report_ignored_msrs, bool, S_IRUGO | S_IWUSR); 133 EXPORT_SYMBOL_GPL(report_ignored_msrs); 134 135 unsigned int min_timer_period_us = 200; 136 module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR); 137 138 static bool __read_mostly kvmclock_periodic_sync = true; 139 module_param(kvmclock_periodic_sync, bool, S_IRUGO); 140 141 bool __read_mostly kvm_has_tsc_control; 142 EXPORT_SYMBOL_GPL(kvm_has_tsc_control); 143 u32 __read_mostly kvm_max_guest_tsc_khz; 144 EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz); 145 u8 __read_mostly kvm_tsc_scaling_ratio_frac_bits; 146 EXPORT_SYMBOL_GPL(kvm_tsc_scaling_ratio_frac_bits); 147 u64 __read_mostly kvm_max_tsc_scaling_ratio; 148 EXPORT_SYMBOL_GPL(kvm_max_tsc_scaling_ratio); 149 u64 __read_mostly kvm_default_tsc_scaling_ratio; 150 EXPORT_SYMBOL_GPL(kvm_default_tsc_scaling_ratio); 151 bool __read_mostly kvm_has_bus_lock_exit; 152 EXPORT_SYMBOL_GPL(kvm_has_bus_lock_exit); 153 154 /* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */ 155 static u32 __read_mostly tsc_tolerance_ppm = 250; 156 module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR); 157 158 /* 159 * lapic timer advance (tscdeadline mode only) in nanoseconds. '-1' enables 160 * adaptive tuning starting from default advancement of 1000ns. '0' disables 161 * advancement entirely. Any other value is used as-is and disables adaptive 162 * tuning, i.e. allows privileged userspace to set an exact advancement time. 163 */ 164 static int __read_mostly lapic_timer_advance_ns = -1; 165 module_param(lapic_timer_advance_ns, int, S_IRUGO | S_IWUSR); 166 167 static bool __read_mostly vector_hashing = true; 168 module_param(vector_hashing, bool, S_IRUGO); 169 170 bool __read_mostly enable_vmware_backdoor = false; 171 module_param(enable_vmware_backdoor, bool, S_IRUGO); 172 EXPORT_SYMBOL_GPL(enable_vmware_backdoor); 173 174 static bool __read_mostly force_emulation_prefix = false; 175 module_param(force_emulation_prefix, bool, S_IRUGO); 176 177 int __read_mostly pi_inject_timer = -1; 178 module_param(pi_inject_timer, bint, S_IRUGO | S_IWUSR); 179 180 /* 181 * Restoring the host value for MSRs that are only consumed when running in 182 * usermode, e.g. SYSCALL MSRs and TSC_AUX, can be deferred until the CPU 183 * returns to userspace, i.e. the kernel can run with the guest's value. 184 */ 185 #define KVM_MAX_NR_USER_RETURN_MSRS 16 186 187 struct kvm_user_return_msrs { 188 struct user_return_notifier urn; 189 bool registered; 190 struct kvm_user_return_msr_values { 191 u64 host; 192 u64 curr; 193 } values[KVM_MAX_NR_USER_RETURN_MSRS]; 194 }; 195 196 u32 __read_mostly kvm_nr_uret_msrs; 197 EXPORT_SYMBOL_GPL(kvm_nr_uret_msrs); 198 static u32 __read_mostly kvm_uret_msrs_list[KVM_MAX_NR_USER_RETURN_MSRS]; 199 static struct kvm_user_return_msrs __percpu *user_return_msrs; 200 201 #define KVM_SUPPORTED_XCR0 (XFEATURE_MASK_FP | XFEATURE_MASK_SSE \ 202 | XFEATURE_MASK_YMM | XFEATURE_MASK_BNDREGS \ 203 | XFEATURE_MASK_BNDCSR | XFEATURE_MASK_AVX512 \ 204 | XFEATURE_MASK_PKRU) 205 206 u64 __read_mostly host_efer; 207 EXPORT_SYMBOL_GPL(host_efer); 208 209 bool __read_mostly allow_smaller_maxphyaddr = 0; 210 EXPORT_SYMBOL_GPL(allow_smaller_maxphyaddr); 211 212 u64 __read_mostly host_xss; 213 EXPORT_SYMBOL_GPL(host_xss); 214 u64 __read_mostly supported_xss; 215 EXPORT_SYMBOL_GPL(supported_xss); 216 217 struct kvm_stats_debugfs_item debugfs_entries[] = { 218 VCPU_STAT("pf_fixed", pf_fixed), 219 VCPU_STAT("pf_guest", pf_guest), 220 VCPU_STAT("tlb_flush", tlb_flush), 221 VCPU_STAT("invlpg", invlpg), 222 VCPU_STAT("exits", exits), 223 VCPU_STAT("io_exits", io_exits), 224 VCPU_STAT("mmio_exits", mmio_exits), 225 VCPU_STAT("signal_exits", signal_exits), 226 VCPU_STAT("irq_window", irq_window_exits), 227 VCPU_STAT("nmi_window", nmi_window_exits), 228 VCPU_STAT("halt_exits", halt_exits), 229 VCPU_STAT("halt_successful_poll", halt_successful_poll), 230 VCPU_STAT("halt_attempted_poll", halt_attempted_poll), 231 VCPU_STAT("halt_poll_invalid", halt_poll_invalid), 232 VCPU_STAT("halt_wakeup", halt_wakeup), 233 VCPU_STAT("hypercalls", hypercalls), 234 VCPU_STAT("request_irq", request_irq_exits), 235 VCPU_STAT("irq_exits", irq_exits), 236 VCPU_STAT("host_state_reload", host_state_reload), 237 VCPU_STAT("fpu_reload", fpu_reload), 238 VCPU_STAT("insn_emulation", insn_emulation), 239 VCPU_STAT("insn_emulation_fail", insn_emulation_fail), 240 VCPU_STAT("irq_injections", irq_injections), 241 VCPU_STAT("nmi_injections", nmi_injections), 242 VCPU_STAT("req_event", req_event), 243 VCPU_STAT("l1d_flush", l1d_flush), 244 VCPU_STAT("halt_poll_success_ns", halt_poll_success_ns), 245 VCPU_STAT("halt_poll_fail_ns", halt_poll_fail_ns), 246 VCPU_STAT("nested_run", nested_run), 247 VCPU_STAT("directed_yield_attempted", directed_yield_attempted), 248 VCPU_STAT("directed_yield_successful", directed_yield_successful), 249 VM_STAT("mmu_shadow_zapped", mmu_shadow_zapped), 250 VM_STAT("mmu_pte_write", mmu_pte_write), 251 VM_STAT("mmu_pde_zapped", mmu_pde_zapped), 252 VM_STAT("mmu_flooded", mmu_flooded), 253 VM_STAT("mmu_recycled", mmu_recycled), 254 VM_STAT("mmu_cache_miss", mmu_cache_miss), 255 VM_STAT("mmu_unsync", mmu_unsync), 256 VM_STAT("remote_tlb_flush", remote_tlb_flush), 257 VM_STAT("largepages", lpages, .mode = 0444), 258 VM_STAT("nx_largepages_splitted", nx_lpage_splits, .mode = 0444), 259 VM_STAT("max_mmu_page_hash_collisions", max_mmu_page_hash_collisions), 260 { NULL } 261 }; 262 263 u64 __read_mostly host_xcr0; 264 u64 __read_mostly supported_xcr0; 265 EXPORT_SYMBOL_GPL(supported_xcr0); 266 267 static struct kmem_cache *x86_fpu_cache; 268 269 static struct kmem_cache *x86_emulator_cache; 270 271 /* 272 * When called, it means the previous get/set msr reached an invalid msr. 273 * Return true if we want to ignore/silent this failed msr access. 274 */ 275 static bool kvm_msr_ignored_check(u32 msr, u64 data, bool write) 276 { 277 const char *op = write ? "wrmsr" : "rdmsr"; 278 279 if (ignore_msrs) { 280 if (report_ignored_msrs) 281 kvm_pr_unimpl("ignored %s: 0x%x data 0x%llx\n", 282 op, msr, data); 283 /* Mask the error */ 284 return true; 285 } else { 286 kvm_debug_ratelimited("unhandled %s: 0x%x data 0x%llx\n", 287 op, msr, data); 288 return false; 289 } 290 } 291 292 static struct kmem_cache *kvm_alloc_emulator_cache(void) 293 { 294 unsigned int useroffset = offsetof(struct x86_emulate_ctxt, src); 295 unsigned int size = sizeof(struct x86_emulate_ctxt); 296 297 return kmem_cache_create_usercopy("x86_emulator", size, 298 __alignof__(struct x86_emulate_ctxt), 299 SLAB_ACCOUNT, useroffset, 300 size - useroffset, NULL); 301 } 302 303 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt); 304 305 static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu) 306 { 307 int i; 308 for (i = 0; i < ASYNC_PF_PER_VCPU; i++) 309 vcpu->arch.apf.gfns[i] = ~0; 310 } 311 312 static void kvm_on_user_return(struct user_return_notifier *urn) 313 { 314 unsigned slot; 315 struct kvm_user_return_msrs *msrs 316 = container_of(urn, struct kvm_user_return_msrs, urn); 317 struct kvm_user_return_msr_values *values; 318 unsigned long flags; 319 320 /* 321 * Disabling irqs at this point since the following code could be 322 * interrupted and executed through kvm_arch_hardware_disable() 323 */ 324 local_irq_save(flags); 325 if (msrs->registered) { 326 msrs->registered = false; 327 user_return_notifier_unregister(urn); 328 } 329 local_irq_restore(flags); 330 for (slot = 0; slot < kvm_nr_uret_msrs; ++slot) { 331 values = &msrs->values[slot]; 332 if (values->host != values->curr) { 333 wrmsrl(kvm_uret_msrs_list[slot], values->host); 334 values->curr = values->host; 335 } 336 } 337 } 338 339 static int kvm_probe_user_return_msr(u32 msr) 340 { 341 u64 val; 342 int ret; 343 344 preempt_disable(); 345 ret = rdmsrl_safe(msr, &val); 346 if (ret) 347 goto out; 348 ret = wrmsrl_safe(msr, val); 349 out: 350 preempt_enable(); 351 return ret; 352 } 353 354 int kvm_add_user_return_msr(u32 msr) 355 { 356 BUG_ON(kvm_nr_uret_msrs >= KVM_MAX_NR_USER_RETURN_MSRS); 357 358 if (kvm_probe_user_return_msr(msr)) 359 return -1; 360 361 kvm_uret_msrs_list[kvm_nr_uret_msrs] = msr; 362 return kvm_nr_uret_msrs++; 363 } 364 EXPORT_SYMBOL_GPL(kvm_add_user_return_msr); 365 366 int kvm_find_user_return_msr(u32 msr) 367 { 368 int i; 369 370 for (i = 0; i < kvm_nr_uret_msrs; ++i) { 371 if (kvm_uret_msrs_list[i] == msr) 372 return i; 373 } 374 return -1; 375 } 376 EXPORT_SYMBOL_GPL(kvm_find_user_return_msr); 377 378 static void kvm_user_return_msr_cpu_online(void) 379 { 380 unsigned int cpu = smp_processor_id(); 381 struct kvm_user_return_msrs *msrs = per_cpu_ptr(user_return_msrs, cpu); 382 u64 value; 383 int i; 384 385 for (i = 0; i < kvm_nr_uret_msrs; ++i) { 386 rdmsrl_safe(kvm_uret_msrs_list[i], &value); 387 msrs->values[i].host = value; 388 msrs->values[i].curr = value; 389 } 390 } 391 392 int kvm_set_user_return_msr(unsigned slot, u64 value, u64 mask) 393 { 394 unsigned int cpu = smp_processor_id(); 395 struct kvm_user_return_msrs *msrs = per_cpu_ptr(user_return_msrs, cpu); 396 int err; 397 398 value = (value & mask) | (msrs->values[slot].host & ~mask); 399 if (value == msrs->values[slot].curr) 400 return 0; 401 err = wrmsrl_safe(kvm_uret_msrs_list[slot], value); 402 if (err) 403 return 1; 404 405 msrs->values[slot].curr = value; 406 if (!msrs->registered) { 407 msrs->urn.on_user_return = kvm_on_user_return; 408 user_return_notifier_register(&msrs->urn); 409 msrs->registered = true; 410 } 411 return 0; 412 } 413 EXPORT_SYMBOL_GPL(kvm_set_user_return_msr); 414 415 static void drop_user_return_notifiers(void) 416 { 417 unsigned int cpu = smp_processor_id(); 418 struct kvm_user_return_msrs *msrs = per_cpu_ptr(user_return_msrs, cpu); 419 420 if (msrs->registered) 421 kvm_on_user_return(&msrs->urn); 422 } 423 424 u64 kvm_get_apic_base(struct kvm_vcpu *vcpu) 425 { 426 return vcpu->arch.apic_base; 427 } 428 EXPORT_SYMBOL_GPL(kvm_get_apic_base); 429 430 enum lapic_mode kvm_get_apic_mode(struct kvm_vcpu *vcpu) 431 { 432 return kvm_apic_mode(kvm_get_apic_base(vcpu)); 433 } 434 EXPORT_SYMBOL_GPL(kvm_get_apic_mode); 435 436 int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info) 437 { 438 enum lapic_mode old_mode = kvm_get_apic_mode(vcpu); 439 enum lapic_mode new_mode = kvm_apic_mode(msr_info->data); 440 u64 reserved_bits = kvm_vcpu_reserved_gpa_bits_raw(vcpu) | 0x2ff | 441 (guest_cpuid_has(vcpu, X86_FEATURE_X2APIC) ? 0 : X2APIC_ENABLE); 442 443 if ((msr_info->data & reserved_bits) != 0 || new_mode == LAPIC_MODE_INVALID) 444 return 1; 445 if (!msr_info->host_initiated) { 446 if (old_mode == LAPIC_MODE_X2APIC && new_mode == LAPIC_MODE_XAPIC) 447 return 1; 448 if (old_mode == LAPIC_MODE_DISABLED && new_mode == LAPIC_MODE_X2APIC) 449 return 1; 450 } 451 452 kvm_lapic_set_base(vcpu, msr_info->data); 453 kvm_recalculate_apic_map(vcpu->kvm); 454 return 0; 455 } 456 EXPORT_SYMBOL_GPL(kvm_set_apic_base); 457 458 asmlinkage __visible noinstr void kvm_spurious_fault(void) 459 { 460 /* Fault while not rebooting. We want the trace. */ 461 BUG_ON(!kvm_rebooting); 462 } 463 EXPORT_SYMBOL_GPL(kvm_spurious_fault); 464 465 #define EXCPT_BENIGN 0 466 #define EXCPT_CONTRIBUTORY 1 467 #define EXCPT_PF 2 468 469 static int exception_class(int vector) 470 { 471 switch (vector) { 472 case PF_VECTOR: 473 return EXCPT_PF; 474 case DE_VECTOR: 475 case TS_VECTOR: 476 case NP_VECTOR: 477 case SS_VECTOR: 478 case GP_VECTOR: 479 return EXCPT_CONTRIBUTORY; 480 default: 481 break; 482 } 483 return EXCPT_BENIGN; 484 } 485 486 #define EXCPT_FAULT 0 487 #define EXCPT_TRAP 1 488 #define EXCPT_ABORT 2 489 #define EXCPT_INTERRUPT 3 490 491 static int exception_type(int vector) 492 { 493 unsigned int mask; 494 495 if (WARN_ON(vector > 31 || vector == NMI_VECTOR)) 496 return EXCPT_INTERRUPT; 497 498 mask = 1 << vector; 499 500 /* #DB is trap, as instruction watchpoints are handled elsewhere */ 501 if (mask & ((1 << DB_VECTOR) | (1 << BP_VECTOR) | (1 << OF_VECTOR))) 502 return EXCPT_TRAP; 503 504 if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR))) 505 return EXCPT_ABORT; 506 507 /* Reserved exceptions will result in fault */ 508 return EXCPT_FAULT; 509 } 510 511 void kvm_deliver_exception_payload(struct kvm_vcpu *vcpu) 512 { 513 unsigned nr = vcpu->arch.exception.nr; 514 bool has_payload = vcpu->arch.exception.has_payload; 515 unsigned long payload = vcpu->arch.exception.payload; 516 517 if (!has_payload) 518 return; 519 520 switch (nr) { 521 case DB_VECTOR: 522 /* 523 * "Certain debug exceptions may clear bit 0-3. The 524 * remaining contents of the DR6 register are never 525 * cleared by the processor". 526 */ 527 vcpu->arch.dr6 &= ~DR_TRAP_BITS; 528 /* 529 * In order to reflect the #DB exception payload in guest 530 * dr6, three components need to be considered: active low 531 * bit, FIXED_1 bits and active high bits (e.g. DR6_BD, 532 * DR6_BS and DR6_BT) 533 * DR6_ACTIVE_LOW contains the FIXED_1 and active low bits. 534 * In the target guest dr6: 535 * FIXED_1 bits should always be set. 536 * Active low bits should be cleared if 1-setting in payload. 537 * Active high bits should be set if 1-setting in payload. 538 * 539 * Note, the payload is compatible with the pending debug 540 * exceptions/exit qualification under VMX, that active_low bits 541 * are active high in payload. 542 * So they need to be flipped for DR6. 543 */ 544 vcpu->arch.dr6 |= DR6_ACTIVE_LOW; 545 vcpu->arch.dr6 |= payload; 546 vcpu->arch.dr6 ^= payload & DR6_ACTIVE_LOW; 547 548 /* 549 * The #DB payload is defined as compatible with the 'pending 550 * debug exceptions' field under VMX, not DR6. While bit 12 is 551 * defined in the 'pending debug exceptions' field (enabled 552 * breakpoint), it is reserved and must be zero in DR6. 553 */ 554 vcpu->arch.dr6 &= ~BIT(12); 555 break; 556 case PF_VECTOR: 557 vcpu->arch.cr2 = payload; 558 break; 559 } 560 561 vcpu->arch.exception.has_payload = false; 562 vcpu->arch.exception.payload = 0; 563 } 564 EXPORT_SYMBOL_GPL(kvm_deliver_exception_payload); 565 566 static void kvm_multiple_exception(struct kvm_vcpu *vcpu, 567 unsigned nr, bool has_error, u32 error_code, 568 bool has_payload, unsigned long payload, bool reinject) 569 { 570 u32 prev_nr; 571 int class1, class2; 572 573 kvm_make_request(KVM_REQ_EVENT, vcpu); 574 575 if (!vcpu->arch.exception.pending && !vcpu->arch.exception.injected) { 576 queue: 577 if (reinject) { 578 /* 579 * On vmentry, vcpu->arch.exception.pending is only 580 * true if an event injection was blocked by 581 * nested_run_pending. In that case, however, 582 * vcpu_enter_guest requests an immediate exit, 583 * and the guest shouldn't proceed far enough to 584 * need reinjection. 585 */ 586 WARN_ON_ONCE(vcpu->arch.exception.pending); 587 vcpu->arch.exception.injected = true; 588 if (WARN_ON_ONCE(has_payload)) { 589 /* 590 * A reinjected event has already 591 * delivered its payload. 592 */ 593 has_payload = false; 594 payload = 0; 595 } 596 } else { 597 vcpu->arch.exception.pending = true; 598 vcpu->arch.exception.injected = false; 599 } 600 vcpu->arch.exception.has_error_code = has_error; 601 vcpu->arch.exception.nr = nr; 602 vcpu->arch.exception.error_code = error_code; 603 vcpu->arch.exception.has_payload = has_payload; 604 vcpu->arch.exception.payload = payload; 605 if (!is_guest_mode(vcpu)) 606 kvm_deliver_exception_payload(vcpu); 607 return; 608 } 609 610 /* to check exception */ 611 prev_nr = vcpu->arch.exception.nr; 612 if (prev_nr == DF_VECTOR) { 613 /* triple fault -> shutdown */ 614 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); 615 return; 616 } 617 class1 = exception_class(prev_nr); 618 class2 = exception_class(nr); 619 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY) 620 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) { 621 /* 622 * Generate double fault per SDM Table 5-5. Set 623 * exception.pending = true so that the double fault 624 * can trigger a nested vmexit. 625 */ 626 vcpu->arch.exception.pending = true; 627 vcpu->arch.exception.injected = false; 628 vcpu->arch.exception.has_error_code = true; 629 vcpu->arch.exception.nr = DF_VECTOR; 630 vcpu->arch.exception.error_code = 0; 631 vcpu->arch.exception.has_payload = false; 632 vcpu->arch.exception.payload = 0; 633 } else 634 /* replace previous exception with a new one in a hope 635 that instruction re-execution will regenerate lost 636 exception */ 637 goto queue; 638 } 639 640 void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr) 641 { 642 kvm_multiple_exception(vcpu, nr, false, 0, false, 0, false); 643 } 644 EXPORT_SYMBOL_GPL(kvm_queue_exception); 645 646 void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr) 647 { 648 kvm_multiple_exception(vcpu, nr, false, 0, false, 0, true); 649 } 650 EXPORT_SYMBOL_GPL(kvm_requeue_exception); 651 652 void kvm_queue_exception_p(struct kvm_vcpu *vcpu, unsigned nr, 653 unsigned long payload) 654 { 655 kvm_multiple_exception(vcpu, nr, false, 0, true, payload, false); 656 } 657 EXPORT_SYMBOL_GPL(kvm_queue_exception_p); 658 659 static void kvm_queue_exception_e_p(struct kvm_vcpu *vcpu, unsigned nr, 660 u32 error_code, unsigned long payload) 661 { 662 kvm_multiple_exception(vcpu, nr, true, error_code, 663 true, payload, false); 664 } 665 666 int kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err) 667 { 668 if (err) 669 kvm_inject_gp(vcpu, 0); 670 else 671 return kvm_skip_emulated_instruction(vcpu); 672 673 return 1; 674 } 675 EXPORT_SYMBOL_GPL(kvm_complete_insn_gp); 676 677 void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault) 678 { 679 ++vcpu->stat.pf_guest; 680 vcpu->arch.exception.nested_apf = 681 is_guest_mode(vcpu) && fault->async_page_fault; 682 if (vcpu->arch.exception.nested_apf) { 683 vcpu->arch.apf.nested_apf_token = fault->address; 684 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code); 685 } else { 686 kvm_queue_exception_e_p(vcpu, PF_VECTOR, fault->error_code, 687 fault->address); 688 } 689 } 690 EXPORT_SYMBOL_GPL(kvm_inject_page_fault); 691 692 bool kvm_inject_emulated_page_fault(struct kvm_vcpu *vcpu, 693 struct x86_exception *fault) 694 { 695 struct kvm_mmu *fault_mmu; 696 WARN_ON_ONCE(fault->vector != PF_VECTOR); 697 698 fault_mmu = fault->nested_page_fault ? vcpu->arch.mmu : 699 vcpu->arch.walk_mmu; 700 701 /* 702 * Invalidate the TLB entry for the faulting address, if it exists, 703 * else the access will fault indefinitely (and to emulate hardware). 704 */ 705 if ((fault->error_code & PFERR_PRESENT_MASK) && 706 !(fault->error_code & PFERR_RSVD_MASK)) 707 kvm_mmu_invalidate_gva(vcpu, fault_mmu, fault->address, 708 fault_mmu->root_hpa); 709 710 fault_mmu->inject_page_fault(vcpu, fault); 711 return fault->nested_page_fault; 712 } 713 EXPORT_SYMBOL_GPL(kvm_inject_emulated_page_fault); 714 715 void kvm_inject_nmi(struct kvm_vcpu *vcpu) 716 { 717 atomic_inc(&vcpu->arch.nmi_queued); 718 kvm_make_request(KVM_REQ_NMI, vcpu); 719 } 720 EXPORT_SYMBOL_GPL(kvm_inject_nmi); 721 722 void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code) 723 { 724 kvm_multiple_exception(vcpu, nr, true, error_code, false, 0, false); 725 } 726 EXPORT_SYMBOL_GPL(kvm_queue_exception_e); 727 728 void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code) 729 { 730 kvm_multiple_exception(vcpu, nr, true, error_code, false, 0, true); 731 } 732 EXPORT_SYMBOL_GPL(kvm_requeue_exception_e); 733 734 /* 735 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue 736 * a #GP and return false. 737 */ 738 bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl) 739 { 740 if (static_call(kvm_x86_get_cpl)(vcpu) <= required_cpl) 741 return true; 742 kvm_queue_exception_e(vcpu, GP_VECTOR, 0); 743 return false; 744 } 745 EXPORT_SYMBOL_GPL(kvm_require_cpl); 746 747 bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr) 748 { 749 if ((dr != 4 && dr != 5) || !kvm_read_cr4_bits(vcpu, X86_CR4_DE)) 750 return true; 751 752 kvm_queue_exception(vcpu, UD_VECTOR); 753 return false; 754 } 755 EXPORT_SYMBOL_GPL(kvm_require_dr); 756 757 /* 758 * This function will be used to read from the physical memory of the currently 759 * running guest. The difference to kvm_vcpu_read_guest_page is that this function 760 * can read from guest physical or from the guest's guest physical memory. 761 */ 762 int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, 763 gfn_t ngfn, void *data, int offset, int len, 764 u32 access) 765 { 766 struct x86_exception exception; 767 gfn_t real_gfn; 768 gpa_t ngpa; 769 770 ngpa = gfn_to_gpa(ngfn); 771 real_gfn = mmu->translate_gpa(vcpu, ngpa, access, &exception); 772 if (real_gfn == UNMAPPED_GVA) 773 return -EFAULT; 774 775 real_gfn = gpa_to_gfn(real_gfn); 776 777 return kvm_vcpu_read_guest_page(vcpu, real_gfn, data, offset, len); 778 } 779 EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu); 780 781 static int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn, 782 void *data, int offset, int len, u32 access) 783 { 784 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn, 785 data, offset, len, access); 786 } 787 788 static inline u64 pdptr_rsvd_bits(struct kvm_vcpu *vcpu) 789 { 790 return vcpu->arch.reserved_gpa_bits | rsvd_bits(5, 8) | rsvd_bits(1, 2); 791 } 792 793 /* 794 * Load the pae pdptrs. Return 1 if they are all valid, 0 otherwise. 795 */ 796 int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3) 797 { 798 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT; 799 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2; 800 int i; 801 int ret; 802 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)]; 803 804 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte, 805 offset * sizeof(u64), sizeof(pdpte), 806 PFERR_USER_MASK|PFERR_WRITE_MASK); 807 if (ret < 0) { 808 ret = 0; 809 goto out; 810 } 811 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) { 812 if ((pdpte[i] & PT_PRESENT_MASK) && 813 (pdpte[i] & pdptr_rsvd_bits(vcpu))) { 814 ret = 0; 815 goto out; 816 } 817 } 818 ret = 1; 819 820 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs)); 821 kvm_register_mark_dirty(vcpu, VCPU_EXREG_PDPTR); 822 823 out: 824 825 return ret; 826 } 827 EXPORT_SYMBOL_GPL(load_pdptrs); 828 829 bool pdptrs_changed(struct kvm_vcpu *vcpu) 830 { 831 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)]; 832 int offset; 833 gfn_t gfn; 834 int r; 835 836 if (!is_pae_paging(vcpu)) 837 return false; 838 839 if (!kvm_register_is_available(vcpu, VCPU_EXREG_PDPTR)) 840 return true; 841 842 gfn = (kvm_read_cr3(vcpu) & 0xffffffe0ul) >> PAGE_SHIFT; 843 offset = (kvm_read_cr3(vcpu) & 0xffffffe0ul) & (PAGE_SIZE - 1); 844 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte), 845 PFERR_USER_MASK | PFERR_WRITE_MASK); 846 if (r < 0) 847 return true; 848 849 return memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0; 850 } 851 EXPORT_SYMBOL_GPL(pdptrs_changed); 852 853 void kvm_post_set_cr0(struct kvm_vcpu *vcpu, unsigned long old_cr0, unsigned long cr0) 854 { 855 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP; 856 857 if ((cr0 ^ old_cr0) & X86_CR0_PG) { 858 kvm_clear_async_pf_completion_queue(vcpu); 859 kvm_async_pf_hash_reset(vcpu); 860 } 861 862 if ((cr0 ^ old_cr0) & update_bits) 863 kvm_mmu_reset_context(vcpu); 864 865 if (((cr0 ^ old_cr0) & X86_CR0_CD) && 866 kvm_arch_has_noncoherent_dma(vcpu->kvm) && 867 !kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED)) 868 kvm_zap_gfn_range(vcpu->kvm, 0, ~0ULL); 869 } 870 EXPORT_SYMBOL_GPL(kvm_post_set_cr0); 871 872 int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0) 873 { 874 unsigned long old_cr0 = kvm_read_cr0(vcpu); 875 unsigned long pdptr_bits = X86_CR0_CD | X86_CR0_NW | X86_CR0_PG; 876 877 cr0 |= X86_CR0_ET; 878 879 #ifdef CONFIG_X86_64 880 if (cr0 & 0xffffffff00000000UL) 881 return 1; 882 #endif 883 884 cr0 &= ~CR0_RESERVED_BITS; 885 886 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD)) 887 return 1; 888 889 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE)) 890 return 1; 891 892 #ifdef CONFIG_X86_64 893 if ((vcpu->arch.efer & EFER_LME) && !is_paging(vcpu) && 894 (cr0 & X86_CR0_PG)) { 895 int cs_db, cs_l; 896 897 if (!is_pae(vcpu)) 898 return 1; 899 static_call(kvm_x86_get_cs_db_l_bits)(vcpu, &cs_db, &cs_l); 900 if (cs_l) 901 return 1; 902 } 903 #endif 904 if (!(vcpu->arch.efer & EFER_LME) && (cr0 & X86_CR0_PG) && 905 is_pae(vcpu) && ((cr0 ^ old_cr0) & pdptr_bits) && 906 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu))) 907 return 1; 908 909 if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE)) 910 return 1; 911 912 static_call(kvm_x86_set_cr0)(vcpu, cr0); 913 914 kvm_post_set_cr0(vcpu, old_cr0, cr0); 915 916 return 0; 917 } 918 EXPORT_SYMBOL_GPL(kvm_set_cr0); 919 920 void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw) 921 { 922 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f)); 923 } 924 EXPORT_SYMBOL_GPL(kvm_lmsw); 925 926 void kvm_load_guest_xsave_state(struct kvm_vcpu *vcpu) 927 { 928 if (vcpu->arch.guest_state_protected) 929 return; 930 931 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE)) { 932 933 if (vcpu->arch.xcr0 != host_xcr0) 934 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0); 935 936 if (vcpu->arch.xsaves_enabled && 937 vcpu->arch.ia32_xss != host_xss) 938 wrmsrl(MSR_IA32_XSS, vcpu->arch.ia32_xss); 939 } 940 941 if (static_cpu_has(X86_FEATURE_PKU) && 942 (kvm_read_cr4_bits(vcpu, X86_CR4_PKE) || 943 (vcpu->arch.xcr0 & XFEATURE_MASK_PKRU)) && 944 vcpu->arch.pkru != vcpu->arch.host_pkru) 945 __write_pkru(vcpu->arch.pkru); 946 } 947 EXPORT_SYMBOL_GPL(kvm_load_guest_xsave_state); 948 949 void kvm_load_host_xsave_state(struct kvm_vcpu *vcpu) 950 { 951 if (vcpu->arch.guest_state_protected) 952 return; 953 954 if (static_cpu_has(X86_FEATURE_PKU) && 955 (kvm_read_cr4_bits(vcpu, X86_CR4_PKE) || 956 (vcpu->arch.xcr0 & XFEATURE_MASK_PKRU))) { 957 vcpu->arch.pkru = rdpkru(); 958 if (vcpu->arch.pkru != vcpu->arch.host_pkru) 959 __write_pkru(vcpu->arch.host_pkru); 960 } 961 962 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE)) { 963 964 if (vcpu->arch.xcr0 != host_xcr0) 965 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0); 966 967 if (vcpu->arch.xsaves_enabled && 968 vcpu->arch.ia32_xss != host_xss) 969 wrmsrl(MSR_IA32_XSS, host_xss); 970 } 971 972 } 973 EXPORT_SYMBOL_GPL(kvm_load_host_xsave_state); 974 975 static int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr) 976 { 977 u64 xcr0 = xcr; 978 u64 old_xcr0 = vcpu->arch.xcr0; 979 u64 valid_bits; 980 981 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */ 982 if (index != XCR_XFEATURE_ENABLED_MASK) 983 return 1; 984 if (!(xcr0 & XFEATURE_MASK_FP)) 985 return 1; 986 if ((xcr0 & XFEATURE_MASK_YMM) && !(xcr0 & XFEATURE_MASK_SSE)) 987 return 1; 988 989 /* 990 * Do not allow the guest to set bits that we do not support 991 * saving. However, xcr0 bit 0 is always set, even if the 992 * emulated CPU does not support XSAVE (see fx_init). 993 */ 994 valid_bits = vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FP; 995 if (xcr0 & ~valid_bits) 996 return 1; 997 998 if ((!(xcr0 & XFEATURE_MASK_BNDREGS)) != 999 (!(xcr0 & XFEATURE_MASK_BNDCSR))) 1000 return 1; 1001 1002 if (xcr0 & XFEATURE_MASK_AVX512) { 1003 if (!(xcr0 & XFEATURE_MASK_YMM)) 1004 return 1; 1005 if ((xcr0 & XFEATURE_MASK_AVX512) != XFEATURE_MASK_AVX512) 1006 return 1; 1007 } 1008 vcpu->arch.xcr0 = xcr0; 1009 1010 if ((xcr0 ^ old_xcr0) & XFEATURE_MASK_EXTEND) 1011 kvm_update_cpuid_runtime(vcpu); 1012 return 0; 1013 } 1014 1015 int kvm_emulate_xsetbv(struct kvm_vcpu *vcpu) 1016 { 1017 if (static_call(kvm_x86_get_cpl)(vcpu) != 0 || 1018 __kvm_set_xcr(vcpu, kvm_rcx_read(vcpu), kvm_read_edx_eax(vcpu))) { 1019 kvm_inject_gp(vcpu, 0); 1020 return 1; 1021 } 1022 1023 return kvm_skip_emulated_instruction(vcpu); 1024 } 1025 EXPORT_SYMBOL_GPL(kvm_emulate_xsetbv); 1026 1027 bool kvm_is_valid_cr4(struct kvm_vcpu *vcpu, unsigned long cr4) 1028 { 1029 if (cr4 & cr4_reserved_bits) 1030 return false; 1031 1032 if (cr4 & vcpu->arch.cr4_guest_rsvd_bits) 1033 return false; 1034 1035 return static_call(kvm_x86_is_valid_cr4)(vcpu, cr4); 1036 } 1037 EXPORT_SYMBOL_GPL(kvm_is_valid_cr4); 1038 1039 void kvm_post_set_cr4(struct kvm_vcpu *vcpu, unsigned long old_cr4, unsigned long cr4) 1040 { 1041 unsigned long mmu_role_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE | 1042 X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE; 1043 1044 if (((cr4 ^ old_cr4) & mmu_role_bits) || 1045 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE))) 1046 kvm_mmu_reset_context(vcpu); 1047 } 1048 EXPORT_SYMBOL_GPL(kvm_post_set_cr4); 1049 1050 int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4) 1051 { 1052 unsigned long old_cr4 = kvm_read_cr4(vcpu); 1053 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE | 1054 X86_CR4_SMEP; 1055 1056 if (!kvm_is_valid_cr4(vcpu, cr4)) 1057 return 1; 1058 1059 if (is_long_mode(vcpu)) { 1060 if (!(cr4 & X86_CR4_PAE)) 1061 return 1; 1062 if ((cr4 ^ old_cr4) & X86_CR4_LA57) 1063 return 1; 1064 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE) 1065 && ((cr4 ^ old_cr4) & pdptr_bits) 1066 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu, 1067 kvm_read_cr3(vcpu))) 1068 return 1; 1069 1070 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) { 1071 if (!guest_cpuid_has(vcpu, X86_FEATURE_PCID)) 1072 return 1; 1073 1074 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */ 1075 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu)) 1076 return 1; 1077 } 1078 1079 static_call(kvm_x86_set_cr4)(vcpu, cr4); 1080 1081 kvm_post_set_cr4(vcpu, old_cr4, cr4); 1082 1083 return 0; 1084 } 1085 EXPORT_SYMBOL_GPL(kvm_set_cr4); 1086 1087 int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3) 1088 { 1089 bool skip_tlb_flush = false; 1090 #ifdef CONFIG_X86_64 1091 bool pcid_enabled = kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE); 1092 1093 if (pcid_enabled) { 1094 skip_tlb_flush = cr3 & X86_CR3_PCID_NOFLUSH; 1095 cr3 &= ~X86_CR3_PCID_NOFLUSH; 1096 } 1097 #endif 1098 1099 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) { 1100 if (!skip_tlb_flush) { 1101 kvm_mmu_sync_roots(vcpu); 1102 kvm_make_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu); 1103 } 1104 return 0; 1105 } 1106 1107 /* 1108 * Do not condition the GPA check on long mode, this helper is used to 1109 * stuff CR3, e.g. for RSM emulation, and there is no guarantee that 1110 * the current vCPU mode is accurate. 1111 */ 1112 if (kvm_vcpu_is_illegal_gpa(vcpu, cr3)) 1113 return 1; 1114 1115 if (is_pae_paging(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3)) 1116 return 1; 1117 1118 kvm_mmu_new_pgd(vcpu, cr3, skip_tlb_flush, skip_tlb_flush); 1119 vcpu->arch.cr3 = cr3; 1120 kvm_register_mark_available(vcpu, VCPU_EXREG_CR3); 1121 1122 return 0; 1123 } 1124 EXPORT_SYMBOL_GPL(kvm_set_cr3); 1125 1126 int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8) 1127 { 1128 if (cr8 & CR8_RESERVED_BITS) 1129 return 1; 1130 if (lapic_in_kernel(vcpu)) 1131 kvm_lapic_set_tpr(vcpu, cr8); 1132 else 1133 vcpu->arch.cr8 = cr8; 1134 return 0; 1135 } 1136 EXPORT_SYMBOL_GPL(kvm_set_cr8); 1137 1138 unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu) 1139 { 1140 if (lapic_in_kernel(vcpu)) 1141 return kvm_lapic_get_cr8(vcpu); 1142 else 1143 return vcpu->arch.cr8; 1144 } 1145 EXPORT_SYMBOL_GPL(kvm_get_cr8); 1146 1147 static void kvm_update_dr0123(struct kvm_vcpu *vcpu) 1148 { 1149 int i; 1150 1151 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) { 1152 for (i = 0; i < KVM_NR_DB_REGS; i++) 1153 vcpu->arch.eff_db[i] = vcpu->arch.db[i]; 1154 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_RELOAD; 1155 } 1156 } 1157 1158 void kvm_update_dr7(struct kvm_vcpu *vcpu) 1159 { 1160 unsigned long dr7; 1161 1162 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) 1163 dr7 = vcpu->arch.guest_debug_dr7; 1164 else 1165 dr7 = vcpu->arch.dr7; 1166 static_call(kvm_x86_set_dr7)(vcpu, dr7); 1167 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED; 1168 if (dr7 & DR7_BP_EN_MASK) 1169 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED; 1170 } 1171 EXPORT_SYMBOL_GPL(kvm_update_dr7); 1172 1173 static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu) 1174 { 1175 u64 fixed = DR6_FIXED_1; 1176 1177 if (!guest_cpuid_has(vcpu, X86_FEATURE_RTM)) 1178 fixed |= DR6_RTM; 1179 1180 if (!guest_cpuid_has(vcpu, X86_FEATURE_BUS_LOCK_DETECT)) 1181 fixed |= DR6_BUS_LOCK; 1182 return fixed; 1183 } 1184 1185 int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val) 1186 { 1187 size_t size = ARRAY_SIZE(vcpu->arch.db); 1188 1189 switch (dr) { 1190 case 0 ... 3: 1191 vcpu->arch.db[array_index_nospec(dr, size)] = val; 1192 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) 1193 vcpu->arch.eff_db[dr] = val; 1194 break; 1195 case 4: 1196 case 6: 1197 if (!kvm_dr6_valid(val)) 1198 return 1; /* #GP */ 1199 vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu); 1200 break; 1201 case 5: 1202 default: /* 7 */ 1203 if (!kvm_dr7_valid(val)) 1204 return 1; /* #GP */ 1205 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1; 1206 kvm_update_dr7(vcpu); 1207 break; 1208 } 1209 1210 return 0; 1211 } 1212 EXPORT_SYMBOL_GPL(kvm_set_dr); 1213 1214 void kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val) 1215 { 1216 size_t size = ARRAY_SIZE(vcpu->arch.db); 1217 1218 switch (dr) { 1219 case 0 ... 3: 1220 *val = vcpu->arch.db[array_index_nospec(dr, size)]; 1221 break; 1222 case 4: 1223 case 6: 1224 *val = vcpu->arch.dr6; 1225 break; 1226 case 5: 1227 default: /* 7 */ 1228 *val = vcpu->arch.dr7; 1229 break; 1230 } 1231 } 1232 EXPORT_SYMBOL_GPL(kvm_get_dr); 1233 1234 int kvm_emulate_rdpmc(struct kvm_vcpu *vcpu) 1235 { 1236 u32 ecx = kvm_rcx_read(vcpu); 1237 u64 data; 1238 1239 if (kvm_pmu_rdpmc(vcpu, ecx, &data)) { 1240 kvm_inject_gp(vcpu, 0); 1241 return 1; 1242 } 1243 1244 kvm_rax_write(vcpu, (u32)data); 1245 kvm_rdx_write(vcpu, data >> 32); 1246 return kvm_skip_emulated_instruction(vcpu); 1247 } 1248 EXPORT_SYMBOL_GPL(kvm_emulate_rdpmc); 1249 1250 /* 1251 * List of msr numbers which we expose to userspace through KVM_GET_MSRS 1252 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST. 1253 * 1254 * The three MSR lists(msrs_to_save, emulated_msrs, msr_based_features) 1255 * extract the supported MSRs from the related const lists. 1256 * msrs_to_save is selected from the msrs_to_save_all to reflect the 1257 * capabilities of the host cpu. This capabilities test skips MSRs that are 1258 * kvm-specific. Those are put in emulated_msrs_all; filtering of emulated_msrs 1259 * may depend on host virtualization features rather than host cpu features. 1260 */ 1261 1262 static const u32 msrs_to_save_all[] = { 1263 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP, 1264 MSR_STAR, 1265 #ifdef CONFIG_X86_64 1266 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR, 1267 #endif 1268 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA, 1269 MSR_IA32_FEAT_CTL, MSR_IA32_BNDCFGS, MSR_TSC_AUX, 1270 MSR_IA32_SPEC_CTRL, 1271 MSR_IA32_RTIT_CTL, MSR_IA32_RTIT_STATUS, MSR_IA32_RTIT_CR3_MATCH, 1272 MSR_IA32_RTIT_OUTPUT_BASE, MSR_IA32_RTIT_OUTPUT_MASK, 1273 MSR_IA32_RTIT_ADDR0_A, MSR_IA32_RTIT_ADDR0_B, 1274 MSR_IA32_RTIT_ADDR1_A, MSR_IA32_RTIT_ADDR1_B, 1275 MSR_IA32_RTIT_ADDR2_A, MSR_IA32_RTIT_ADDR2_B, 1276 MSR_IA32_RTIT_ADDR3_A, MSR_IA32_RTIT_ADDR3_B, 1277 MSR_IA32_UMWAIT_CONTROL, 1278 1279 MSR_ARCH_PERFMON_FIXED_CTR0, MSR_ARCH_PERFMON_FIXED_CTR1, 1280 MSR_ARCH_PERFMON_FIXED_CTR0 + 2, MSR_ARCH_PERFMON_FIXED_CTR0 + 3, 1281 MSR_CORE_PERF_FIXED_CTR_CTRL, MSR_CORE_PERF_GLOBAL_STATUS, 1282 MSR_CORE_PERF_GLOBAL_CTRL, MSR_CORE_PERF_GLOBAL_OVF_CTRL, 1283 MSR_ARCH_PERFMON_PERFCTR0, MSR_ARCH_PERFMON_PERFCTR1, 1284 MSR_ARCH_PERFMON_PERFCTR0 + 2, MSR_ARCH_PERFMON_PERFCTR0 + 3, 1285 MSR_ARCH_PERFMON_PERFCTR0 + 4, MSR_ARCH_PERFMON_PERFCTR0 + 5, 1286 MSR_ARCH_PERFMON_PERFCTR0 + 6, MSR_ARCH_PERFMON_PERFCTR0 + 7, 1287 MSR_ARCH_PERFMON_PERFCTR0 + 8, MSR_ARCH_PERFMON_PERFCTR0 + 9, 1288 MSR_ARCH_PERFMON_PERFCTR0 + 10, MSR_ARCH_PERFMON_PERFCTR0 + 11, 1289 MSR_ARCH_PERFMON_PERFCTR0 + 12, MSR_ARCH_PERFMON_PERFCTR0 + 13, 1290 MSR_ARCH_PERFMON_PERFCTR0 + 14, MSR_ARCH_PERFMON_PERFCTR0 + 15, 1291 MSR_ARCH_PERFMON_PERFCTR0 + 16, MSR_ARCH_PERFMON_PERFCTR0 + 17, 1292 MSR_ARCH_PERFMON_EVENTSEL0, MSR_ARCH_PERFMON_EVENTSEL1, 1293 MSR_ARCH_PERFMON_EVENTSEL0 + 2, MSR_ARCH_PERFMON_EVENTSEL0 + 3, 1294 MSR_ARCH_PERFMON_EVENTSEL0 + 4, MSR_ARCH_PERFMON_EVENTSEL0 + 5, 1295 MSR_ARCH_PERFMON_EVENTSEL0 + 6, MSR_ARCH_PERFMON_EVENTSEL0 + 7, 1296 MSR_ARCH_PERFMON_EVENTSEL0 + 8, MSR_ARCH_PERFMON_EVENTSEL0 + 9, 1297 MSR_ARCH_PERFMON_EVENTSEL0 + 10, MSR_ARCH_PERFMON_EVENTSEL0 + 11, 1298 MSR_ARCH_PERFMON_EVENTSEL0 + 12, MSR_ARCH_PERFMON_EVENTSEL0 + 13, 1299 MSR_ARCH_PERFMON_EVENTSEL0 + 14, MSR_ARCH_PERFMON_EVENTSEL0 + 15, 1300 MSR_ARCH_PERFMON_EVENTSEL0 + 16, MSR_ARCH_PERFMON_EVENTSEL0 + 17, 1301 }; 1302 1303 static u32 msrs_to_save[ARRAY_SIZE(msrs_to_save_all)]; 1304 static unsigned num_msrs_to_save; 1305 1306 static const u32 emulated_msrs_all[] = { 1307 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK, 1308 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW, 1309 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL, 1310 HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC, 1311 HV_X64_MSR_TSC_FREQUENCY, HV_X64_MSR_APIC_FREQUENCY, 1312 HV_X64_MSR_CRASH_P0, HV_X64_MSR_CRASH_P1, HV_X64_MSR_CRASH_P2, 1313 HV_X64_MSR_CRASH_P3, HV_X64_MSR_CRASH_P4, HV_X64_MSR_CRASH_CTL, 1314 HV_X64_MSR_RESET, 1315 HV_X64_MSR_VP_INDEX, 1316 HV_X64_MSR_VP_RUNTIME, 1317 HV_X64_MSR_SCONTROL, 1318 HV_X64_MSR_STIMER0_CONFIG, 1319 HV_X64_MSR_VP_ASSIST_PAGE, 1320 HV_X64_MSR_REENLIGHTENMENT_CONTROL, HV_X64_MSR_TSC_EMULATION_CONTROL, 1321 HV_X64_MSR_TSC_EMULATION_STATUS, 1322 HV_X64_MSR_SYNDBG_OPTIONS, 1323 HV_X64_MSR_SYNDBG_CONTROL, HV_X64_MSR_SYNDBG_STATUS, 1324 HV_X64_MSR_SYNDBG_SEND_BUFFER, HV_X64_MSR_SYNDBG_RECV_BUFFER, 1325 HV_X64_MSR_SYNDBG_PENDING_BUFFER, 1326 1327 MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME, 1328 MSR_KVM_PV_EOI_EN, MSR_KVM_ASYNC_PF_INT, MSR_KVM_ASYNC_PF_ACK, 1329 1330 MSR_IA32_TSC_ADJUST, 1331 MSR_IA32_TSC_DEADLINE, 1332 MSR_IA32_ARCH_CAPABILITIES, 1333 MSR_IA32_PERF_CAPABILITIES, 1334 MSR_IA32_MISC_ENABLE, 1335 MSR_IA32_MCG_STATUS, 1336 MSR_IA32_MCG_CTL, 1337 MSR_IA32_MCG_EXT_CTL, 1338 MSR_IA32_SMBASE, 1339 MSR_SMI_COUNT, 1340 MSR_PLATFORM_INFO, 1341 MSR_MISC_FEATURES_ENABLES, 1342 MSR_AMD64_VIRT_SPEC_CTRL, 1343 MSR_IA32_POWER_CTL, 1344 MSR_IA32_UCODE_REV, 1345 1346 /* 1347 * The following list leaves out MSRs whose values are determined 1348 * by arch/x86/kvm/vmx/nested.c based on CPUID or other MSRs. 1349 * We always support the "true" VMX control MSRs, even if the host 1350 * processor does not, so I am putting these registers here rather 1351 * than in msrs_to_save_all. 1352 */ 1353 MSR_IA32_VMX_BASIC, 1354 MSR_IA32_VMX_TRUE_PINBASED_CTLS, 1355 MSR_IA32_VMX_TRUE_PROCBASED_CTLS, 1356 MSR_IA32_VMX_TRUE_EXIT_CTLS, 1357 MSR_IA32_VMX_TRUE_ENTRY_CTLS, 1358 MSR_IA32_VMX_MISC, 1359 MSR_IA32_VMX_CR0_FIXED0, 1360 MSR_IA32_VMX_CR4_FIXED0, 1361 MSR_IA32_VMX_VMCS_ENUM, 1362 MSR_IA32_VMX_PROCBASED_CTLS2, 1363 MSR_IA32_VMX_EPT_VPID_CAP, 1364 MSR_IA32_VMX_VMFUNC, 1365 1366 MSR_K7_HWCR, 1367 MSR_KVM_POLL_CONTROL, 1368 }; 1369 1370 static u32 emulated_msrs[ARRAY_SIZE(emulated_msrs_all)]; 1371 static unsigned num_emulated_msrs; 1372 1373 /* 1374 * List of msr numbers which are used to expose MSR-based features that 1375 * can be used by a hypervisor to validate requested CPU features. 1376 */ 1377 static const u32 msr_based_features_all[] = { 1378 MSR_IA32_VMX_BASIC, 1379 MSR_IA32_VMX_TRUE_PINBASED_CTLS, 1380 MSR_IA32_VMX_PINBASED_CTLS, 1381 MSR_IA32_VMX_TRUE_PROCBASED_CTLS, 1382 MSR_IA32_VMX_PROCBASED_CTLS, 1383 MSR_IA32_VMX_TRUE_EXIT_CTLS, 1384 MSR_IA32_VMX_EXIT_CTLS, 1385 MSR_IA32_VMX_TRUE_ENTRY_CTLS, 1386 MSR_IA32_VMX_ENTRY_CTLS, 1387 MSR_IA32_VMX_MISC, 1388 MSR_IA32_VMX_CR0_FIXED0, 1389 MSR_IA32_VMX_CR0_FIXED1, 1390 MSR_IA32_VMX_CR4_FIXED0, 1391 MSR_IA32_VMX_CR4_FIXED1, 1392 MSR_IA32_VMX_VMCS_ENUM, 1393 MSR_IA32_VMX_PROCBASED_CTLS2, 1394 MSR_IA32_VMX_EPT_VPID_CAP, 1395 MSR_IA32_VMX_VMFUNC, 1396 1397 MSR_F10H_DECFG, 1398 MSR_IA32_UCODE_REV, 1399 MSR_IA32_ARCH_CAPABILITIES, 1400 MSR_IA32_PERF_CAPABILITIES, 1401 }; 1402 1403 static u32 msr_based_features[ARRAY_SIZE(msr_based_features_all)]; 1404 static unsigned int num_msr_based_features; 1405 1406 static u64 kvm_get_arch_capabilities(void) 1407 { 1408 u64 data = 0; 1409 1410 if (boot_cpu_has(X86_FEATURE_ARCH_CAPABILITIES)) 1411 rdmsrl(MSR_IA32_ARCH_CAPABILITIES, data); 1412 1413 /* 1414 * If nx_huge_pages is enabled, KVM's shadow paging will ensure that 1415 * the nested hypervisor runs with NX huge pages. If it is not, 1416 * L1 is anyway vulnerable to ITLB_MULTIHIT exploits from other 1417 * L1 guests, so it need not worry about its own (L2) guests. 1418 */ 1419 data |= ARCH_CAP_PSCHANGE_MC_NO; 1420 1421 /* 1422 * If we're doing cache flushes (either "always" or "cond") 1423 * we will do one whenever the guest does a vmlaunch/vmresume. 1424 * If an outer hypervisor is doing the cache flush for us 1425 * (VMENTER_L1D_FLUSH_NESTED_VM), we can safely pass that 1426 * capability to the guest too, and if EPT is disabled we're not 1427 * vulnerable. Overall, only VMENTER_L1D_FLUSH_NEVER will 1428 * require a nested hypervisor to do a flush of its own. 1429 */ 1430 if (l1tf_vmx_mitigation != VMENTER_L1D_FLUSH_NEVER) 1431 data |= ARCH_CAP_SKIP_VMENTRY_L1DFLUSH; 1432 1433 if (!boot_cpu_has_bug(X86_BUG_CPU_MELTDOWN)) 1434 data |= ARCH_CAP_RDCL_NO; 1435 if (!boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS)) 1436 data |= ARCH_CAP_SSB_NO; 1437 if (!boot_cpu_has_bug(X86_BUG_MDS)) 1438 data |= ARCH_CAP_MDS_NO; 1439 1440 if (!boot_cpu_has(X86_FEATURE_RTM)) { 1441 /* 1442 * If RTM=0 because the kernel has disabled TSX, the host might 1443 * have TAA_NO or TSX_CTRL. Clear TAA_NO (the guest sees RTM=0 1444 * and therefore knows that there cannot be TAA) but keep 1445 * TSX_CTRL: some buggy userspaces leave it set on tsx=on hosts, 1446 * and we want to allow migrating those guests to tsx=off hosts. 1447 */ 1448 data &= ~ARCH_CAP_TAA_NO; 1449 } else if (!boot_cpu_has_bug(X86_BUG_TAA)) { 1450 data |= ARCH_CAP_TAA_NO; 1451 } else { 1452 /* 1453 * Nothing to do here; we emulate TSX_CTRL if present on the 1454 * host so the guest can choose between disabling TSX or 1455 * using VERW to clear CPU buffers. 1456 */ 1457 } 1458 1459 return data; 1460 } 1461 1462 static int kvm_get_msr_feature(struct kvm_msr_entry *msr) 1463 { 1464 switch (msr->index) { 1465 case MSR_IA32_ARCH_CAPABILITIES: 1466 msr->data = kvm_get_arch_capabilities(); 1467 break; 1468 case MSR_IA32_UCODE_REV: 1469 rdmsrl_safe(msr->index, &msr->data); 1470 break; 1471 default: 1472 return static_call(kvm_x86_get_msr_feature)(msr); 1473 } 1474 return 0; 1475 } 1476 1477 static int do_get_msr_feature(struct kvm_vcpu *vcpu, unsigned index, u64 *data) 1478 { 1479 struct kvm_msr_entry msr; 1480 int r; 1481 1482 msr.index = index; 1483 r = kvm_get_msr_feature(&msr); 1484 1485 if (r == KVM_MSR_RET_INVALID) { 1486 /* Unconditionally clear the output for simplicity */ 1487 *data = 0; 1488 if (kvm_msr_ignored_check(index, 0, false)) 1489 r = 0; 1490 } 1491 1492 if (r) 1493 return r; 1494 1495 *data = msr.data; 1496 1497 return 0; 1498 } 1499 1500 static bool __kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer) 1501 { 1502 if (efer & EFER_FFXSR && !guest_cpuid_has(vcpu, X86_FEATURE_FXSR_OPT)) 1503 return false; 1504 1505 if (efer & EFER_SVME && !guest_cpuid_has(vcpu, X86_FEATURE_SVM)) 1506 return false; 1507 1508 if (efer & (EFER_LME | EFER_LMA) && 1509 !guest_cpuid_has(vcpu, X86_FEATURE_LM)) 1510 return false; 1511 1512 if (efer & EFER_NX && !guest_cpuid_has(vcpu, X86_FEATURE_NX)) 1513 return false; 1514 1515 return true; 1516 1517 } 1518 bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer) 1519 { 1520 if (efer & efer_reserved_bits) 1521 return false; 1522 1523 return __kvm_valid_efer(vcpu, efer); 1524 } 1525 EXPORT_SYMBOL_GPL(kvm_valid_efer); 1526 1527 static int set_efer(struct kvm_vcpu *vcpu, struct msr_data *msr_info) 1528 { 1529 u64 old_efer = vcpu->arch.efer; 1530 u64 efer = msr_info->data; 1531 int r; 1532 1533 if (efer & efer_reserved_bits) 1534 return 1; 1535 1536 if (!msr_info->host_initiated) { 1537 if (!__kvm_valid_efer(vcpu, efer)) 1538 return 1; 1539 1540 if (is_paging(vcpu) && 1541 (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME)) 1542 return 1; 1543 } 1544 1545 efer &= ~EFER_LMA; 1546 efer |= vcpu->arch.efer & EFER_LMA; 1547 1548 r = static_call(kvm_x86_set_efer)(vcpu, efer); 1549 if (r) { 1550 WARN_ON(r > 0); 1551 return r; 1552 } 1553 1554 /* Update reserved bits */ 1555 if ((efer ^ old_efer) & EFER_NX) 1556 kvm_mmu_reset_context(vcpu); 1557 1558 return 0; 1559 } 1560 1561 void kvm_enable_efer_bits(u64 mask) 1562 { 1563 efer_reserved_bits &= ~mask; 1564 } 1565 EXPORT_SYMBOL_GPL(kvm_enable_efer_bits); 1566 1567 bool kvm_msr_allowed(struct kvm_vcpu *vcpu, u32 index, u32 type) 1568 { 1569 struct kvm_x86_msr_filter *msr_filter; 1570 struct msr_bitmap_range *ranges; 1571 struct kvm *kvm = vcpu->kvm; 1572 bool allowed; 1573 int idx; 1574 u32 i; 1575 1576 /* x2APIC MSRs do not support filtering. */ 1577 if (index >= 0x800 && index <= 0x8ff) 1578 return true; 1579 1580 idx = srcu_read_lock(&kvm->srcu); 1581 1582 msr_filter = srcu_dereference(kvm->arch.msr_filter, &kvm->srcu); 1583 if (!msr_filter) { 1584 allowed = true; 1585 goto out; 1586 } 1587 1588 allowed = msr_filter->default_allow; 1589 ranges = msr_filter->ranges; 1590 1591 for (i = 0; i < msr_filter->count; i++) { 1592 u32 start = ranges[i].base; 1593 u32 end = start + ranges[i].nmsrs; 1594 u32 flags = ranges[i].flags; 1595 unsigned long *bitmap = ranges[i].bitmap; 1596 1597 if ((index >= start) && (index < end) && (flags & type)) { 1598 allowed = !!test_bit(index - start, bitmap); 1599 break; 1600 } 1601 } 1602 1603 out: 1604 srcu_read_unlock(&kvm->srcu, idx); 1605 1606 return allowed; 1607 } 1608 EXPORT_SYMBOL_GPL(kvm_msr_allowed); 1609 1610 /* 1611 * Write @data into the MSR specified by @index. Select MSR specific fault 1612 * checks are bypassed if @host_initiated is %true. 1613 * Returns 0 on success, non-0 otherwise. 1614 * Assumes vcpu_load() was already called. 1615 */ 1616 static int __kvm_set_msr(struct kvm_vcpu *vcpu, u32 index, u64 data, 1617 bool host_initiated) 1618 { 1619 struct msr_data msr; 1620 1621 if (!host_initiated && !kvm_msr_allowed(vcpu, index, KVM_MSR_FILTER_WRITE)) 1622 return KVM_MSR_RET_FILTERED; 1623 1624 switch (index) { 1625 case MSR_FS_BASE: 1626 case MSR_GS_BASE: 1627 case MSR_KERNEL_GS_BASE: 1628 case MSR_CSTAR: 1629 case MSR_LSTAR: 1630 if (is_noncanonical_address(data, vcpu)) 1631 return 1; 1632 break; 1633 case MSR_IA32_SYSENTER_EIP: 1634 case MSR_IA32_SYSENTER_ESP: 1635 /* 1636 * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if 1637 * non-canonical address is written on Intel but not on 1638 * AMD (which ignores the top 32-bits, because it does 1639 * not implement 64-bit SYSENTER). 1640 * 1641 * 64-bit code should hence be able to write a non-canonical 1642 * value on AMD. Making the address canonical ensures that 1643 * vmentry does not fail on Intel after writing a non-canonical 1644 * value, and that something deterministic happens if the guest 1645 * invokes 64-bit SYSENTER. 1646 */ 1647 data = get_canonical(data, vcpu_virt_addr_bits(vcpu)); 1648 break; 1649 case MSR_TSC_AUX: 1650 if (!kvm_is_supported_user_return_msr(MSR_TSC_AUX)) 1651 return 1; 1652 1653 if (!host_initiated && 1654 !guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP) && 1655 !guest_cpuid_has(vcpu, X86_FEATURE_RDPID)) 1656 return 1; 1657 1658 /* 1659 * Per Intel's SDM, bits 63:32 are reserved, but AMD's APM has 1660 * incomplete and conflicting architectural behavior. Current 1661 * AMD CPUs completely ignore bits 63:32, i.e. they aren't 1662 * reserved and always read as zeros. Enforce Intel's reserved 1663 * bits check if and only if the guest CPU is Intel, and clear 1664 * the bits in all other cases. This ensures cross-vendor 1665 * migration will provide consistent behavior for the guest. 1666 */ 1667 if (guest_cpuid_is_intel(vcpu) && (data >> 32) != 0) 1668 return 1; 1669 1670 data = (u32)data; 1671 break; 1672 } 1673 1674 msr.data = data; 1675 msr.index = index; 1676 msr.host_initiated = host_initiated; 1677 1678 return static_call(kvm_x86_set_msr)(vcpu, &msr); 1679 } 1680 1681 static int kvm_set_msr_ignored_check(struct kvm_vcpu *vcpu, 1682 u32 index, u64 data, bool host_initiated) 1683 { 1684 int ret = __kvm_set_msr(vcpu, index, data, host_initiated); 1685 1686 if (ret == KVM_MSR_RET_INVALID) 1687 if (kvm_msr_ignored_check(index, data, true)) 1688 ret = 0; 1689 1690 return ret; 1691 } 1692 1693 /* 1694 * Read the MSR specified by @index into @data. Select MSR specific fault 1695 * checks are bypassed if @host_initiated is %true. 1696 * Returns 0 on success, non-0 otherwise. 1697 * Assumes vcpu_load() was already called. 1698 */ 1699 int __kvm_get_msr(struct kvm_vcpu *vcpu, u32 index, u64 *data, 1700 bool host_initiated) 1701 { 1702 struct msr_data msr; 1703 int ret; 1704 1705 if (!host_initiated && !kvm_msr_allowed(vcpu, index, KVM_MSR_FILTER_READ)) 1706 return KVM_MSR_RET_FILTERED; 1707 1708 switch (index) { 1709 case MSR_TSC_AUX: 1710 if (!kvm_is_supported_user_return_msr(MSR_TSC_AUX)) 1711 return 1; 1712 1713 if (!host_initiated && 1714 !guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP) && 1715 !guest_cpuid_has(vcpu, X86_FEATURE_RDPID)) 1716 return 1; 1717 break; 1718 } 1719 1720 msr.index = index; 1721 msr.host_initiated = host_initiated; 1722 1723 ret = static_call(kvm_x86_get_msr)(vcpu, &msr); 1724 if (!ret) 1725 *data = msr.data; 1726 return ret; 1727 } 1728 1729 static int kvm_get_msr_ignored_check(struct kvm_vcpu *vcpu, 1730 u32 index, u64 *data, bool host_initiated) 1731 { 1732 int ret = __kvm_get_msr(vcpu, index, data, host_initiated); 1733 1734 if (ret == KVM_MSR_RET_INVALID) { 1735 /* Unconditionally clear *data for simplicity */ 1736 *data = 0; 1737 if (kvm_msr_ignored_check(index, 0, false)) 1738 ret = 0; 1739 } 1740 1741 return ret; 1742 } 1743 1744 int kvm_get_msr(struct kvm_vcpu *vcpu, u32 index, u64 *data) 1745 { 1746 return kvm_get_msr_ignored_check(vcpu, index, data, false); 1747 } 1748 EXPORT_SYMBOL_GPL(kvm_get_msr); 1749 1750 int kvm_set_msr(struct kvm_vcpu *vcpu, u32 index, u64 data) 1751 { 1752 return kvm_set_msr_ignored_check(vcpu, index, data, false); 1753 } 1754 EXPORT_SYMBOL_GPL(kvm_set_msr); 1755 1756 static int complete_emulated_rdmsr(struct kvm_vcpu *vcpu) 1757 { 1758 int err = vcpu->run->msr.error; 1759 if (!err) { 1760 kvm_rax_write(vcpu, (u32)vcpu->run->msr.data); 1761 kvm_rdx_write(vcpu, vcpu->run->msr.data >> 32); 1762 } 1763 1764 return static_call(kvm_x86_complete_emulated_msr)(vcpu, err); 1765 } 1766 1767 static int complete_emulated_wrmsr(struct kvm_vcpu *vcpu) 1768 { 1769 return static_call(kvm_x86_complete_emulated_msr)(vcpu, vcpu->run->msr.error); 1770 } 1771 1772 static u64 kvm_msr_reason(int r) 1773 { 1774 switch (r) { 1775 case KVM_MSR_RET_INVALID: 1776 return KVM_MSR_EXIT_REASON_UNKNOWN; 1777 case KVM_MSR_RET_FILTERED: 1778 return KVM_MSR_EXIT_REASON_FILTER; 1779 default: 1780 return KVM_MSR_EXIT_REASON_INVAL; 1781 } 1782 } 1783 1784 static int kvm_msr_user_space(struct kvm_vcpu *vcpu, u32 index, 1785 u32 exit_reason, u64 data, 1786 int (*completion)(struct kvm_vcpu *vcpu), 1787 int r) 1788 { 1789 u64 msr_reason = kvm_msr_reason(r); 1790 1791 /* Check if the user wanted to know about this MSR fault */ 1792 if (!(vcpu->kvm->arch.user_space_msr_mask & msr_reason)) 1793 return 0; 1794 1795 vcpu->run->exit_reason = exit_reason; 1796 vcpu->run->msr.error = 0; 1797 memset(vcpu->run->msr.pad, 0, sizeof(vcpu->run->msr.pad)); 1798 vcpu->run->msr.reason = msr_reason; 1799 vcpu->run->msr.index = index; 1800 vcpu->run->msr.data = data; 1801 vcpu->arch.complete_userspace_io = completion; 1802 1803 return 1; 1804 } 1805 1806 static int kvm_get_msr_user_space(struct kvm_vcpu *vcpu, u32 index, int r) 1807 { 1808 return kvm_msr_user_space(vcpu, index, KVM_EXIT_X86_RDMSR, 0, 1809 complete_emulated_rdmsr, r); 1810 } 1811 1812 static int kvm_set_msr_user_space(struct kvm_vcpu *vcpu, u32 index, u64 data, int r) 1813 { 1814 return kvm_msr_user_space(vcpu, index, KVM_EXIT_X86_WRMSR, data, 1815 complete_emulated_wrmsr, r); 1816 } 1817 1818 int kvm_emulate_rdmsr(struct kvm_vcpu *vcpu) 1819 { 1820 u32 ecx = kvm_rcx_read(vcpu); 1821 u64 data; 1822 int r; 1823 1824 r = kvm_get_msr(vcpu, ecx, &data); 1825 1826 /* MSR read failed? See if we should ask user space */ 1827 if (r && kvm_get_msr_user_space(vcpu, ecx, r)) { 1828 /* Bounce to user space */ 1829 return 0; 1830 } 1831 1832 if (!r) { 1833 trace_kvm_msr_read(ecx, data); 1834 1835 kvm_rax_write(vcpu, data & -1u); 1836 kvm_rdx_write(vcpu, (data >> 32) & -1u); 1837 } else { 1838 trace_kvm_msr_read_ex(ecx); 1839 } 1840 1841 return static_call(kvm_x86_complete_emulated_msr)(vcpu, r); 1842 } 1843 EXPORT_SYMBOL_GPL(kvm_emulate_rdmsr); 1844 1845 int kvm_emulate_wrmsr(struct kvm_vcpu *vcpu) 1846 { 1847 u32 ecx = kvm_rcx_read(vcpu); 1848 u64 data = kvm_read_edx_eax(vcpu); 1849 int r; 1850 1851 r = kvm_set_msr(vcpu, ecx, data); 1852 1853 /* MSR write failed? See if we should ask user space */ 1854 if (r && kvm_set_msr_user_space(vcpu, ecx, data, r)) 1855 /* Bounce to user space */ 1856 return 0; 1857 1858 /* Signal all other negative errors to userspace */ 1859 if (r < 0) 1860 return r; 1861 1862 if (!r) 1863 trace_kvm_msr_write(ecx, data); 1864 else 1865 trace_kvm_msr_write_ex(ecx, data); 1866 1867 return static_call(kvm_x86_complete_emulated_msr)(vcpu, r); 1868 } 1869 EXPORT_SYMBOL_GPL(kvm_emulate_wrmsr); 1870 1871 int kvm_emulate_as_nop(struct kvm_vcpu *vcpu) 1872 { 1873 return kvm_skip_emulated_instruction(vcpu); 1874 } 1875 EXPORT_SYMBOL_GPL(kvm_emulate_as_nop); 1876 1877 int kvm_emulate_invd(struct kvm_vcpu *vcpu) 1878 { 1879 /* Treat an INVD instruction as a NOP and just skip it. */ 1880 return kvm_emulate_as_nop(vcpu); 1881 } 1882 EXPORT_SYMBOL_GPL(kvm_emulate_invd); 1883 1884 int kvm_emulate_mwait(struct kvm_vcpu *vcpu) 1885 { 1886 pr_warn_once("kvm: MWAIT instruction emulated as NOP!\n"); 1887 return kvm_emulate_as_nop(vcpu); 1888 } 1889 EXPORT_SYMBOL_GPL(kvm_emulate_mwait); 1890 1891 int kvm_handle_invalid_op(struct kvm_vcpu *vcpu) 1892 { 1893 kvm_queue_exception(vcpu, UD_VECTOR); 1894 return 1; 1895 } 1896 EXPORT_SYMBOL_GPL(kvm_handle_invalid_op); 1897 1898 int kvm_emulate_monitor(struct kvm_vcpu *vcpu) 1899 { 1900 pr_warn_once("kvm: MONITOR instruction emulated as NOP!\n"); 1901 return kvm_emulate_as_nop(vcpu); 1902 } 1903 EXPORT_SYMBOL_GPL(kvm_emulate_monitor); 1904 1905 static inline bool kvm_vcpu_exit_request(struct kvm_vcpu *vcpu) 1906 { 1907 xfer_to_guest_mode_prepare(); 1908 return vcpu->mode == EXITING_GUEST_MODE || kvm_request_pending(vcpu) || 1909 xfer_to_guest_mode_work_pending(); 1910 } 1911 1912 /* 1913 * The fast path for frequent and performance sensitive wrmsr emulation, 1914 * i.e. the sending of IPI, sending IPI early in the VM-Exit flow reduces 1915 * the latency of virtual IPI by avoiding the expensive bits of transitioning 1916 * from guest to host, e.g. reacquiring KVM's SRCU lock. In contrast to the 1917 * other cases which must be called after interrupts are enabled on the host. 1918 */ 1919 static int handle_fastpath_set_x2apic_icr_irqoff(struct kvm_vcpu *vcpu, u64 data) 1920 { 1921 if (!lapic_in_kernel(vcpu) || !apic_x2apic_mode(vcpu->arch.apic)) 1922 return 1; 1923 1924 if (((data & APIC_SHORT_MASK) == APIC_DEST_NOSHORT) && 1925 ((data & APIC_DEST_MASK) == APIC_DEST_PHYSICAL) && 1926 ((data & APIC_MODE_MASK) == APIC_DM_FIXED) && 1927 ((u32)(data >> 32) != X2APIC_BROADCAST)) { 1928 1929 data &= ~(1 << 12); 1930 kvm_apic_send_ipi(vcpu->arch.apic, (u32)data, (u32)(data >> 32)); 1931 kvm_lapic_set_reg(vcpu->arch.apic, APIC_ICR2, (u32)(data >> 32)); 1932 kvm_lapic_set_reg(vcpu->arch.apic, APIC_ICR, (u32)data); 1933 trace_kvm_apic_write(APIC_ICR, (u32)data); 1934 return 0; 1935 } 1936 1937 return 1; 1938 } 1939 1940 static int handle_fastpath_set_tscdeadline(struct kvm_vcpu *vcpu, u64 data) 1941 { 1942 if (!kvm_can_use_hv_timer(vcpu)) 1943 return 1; 1944 1945 kvm_set_lapic_tscdeadline_msr(vcpu, data); 1946 return 0; 1947 } 1948 1949 fastpath_t handle_fastpath_set_msr_irqoff(struct kvm_vcpu *vcpu) 1950 { 1951 u32 msr = kvm_rcx_read(vcpu); 1952 u64 data; 1953 fastpath_t ret = EXIT_FASTPATH_NONE; 1954 1955 switch (msr) { 1956 case APIC_BASE_MSR + (APIC_ICR >> 4): 1957 data = kvm_read_edx_eax(vcpu); 1958 if (!handle_fastpath_set_x2apic_icr_irqoff(vcpu, data)) { 1959 kvm_skip_emulated_instruction(vcpu); 1960 ret = EXIT_FASTPATH_EXIT_HANDLED; 1961 } 1962 break; 1963 case MSR_IA32_TSC_DEADLINE: 1964 data = kvm_read_edx_eax(vcpu); 1965 if (!handle_fastpath_set_tscdeadline(vcpu, data)) { 1966 kvm_skip_emulated_instruction(vcpu); 1967 ret = EXIT_FASTPATH_REENTER_GUEST; 1968 } 1969 break; 1970 default: 1971 break; 1972 } 1973 1974 if (ret != EXIT_FASTPATH_NONE) 1975 trace_kvm_msr_write(msr, data); 1976 1977 return ret; 1978 } 1979 EXPORT_SYMBOL_GPL(handle_fastpath_set_msr_irqoff); 1980 1981 /* 1982 * Adapt set_msr() to msr_io()'s calling convention 1983 */ 1984 static int do_get_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data) 1985 { 1986 return kvm_get_msr_ignored_check(vcpu, index, data, true); 1987 } 1988 1989 static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data) 1990 { 1991 return kvm_set_msr_ignored_check(vcpu, index, *data, true); 1992 } 1993 1994 #ifdef CONFIG_X86_64 1995 struct pvclock_clock { 1996 int vclock_mode; 1997 u64 cycle_last; 1998 u64 mask; 1999 u32 mult; 2000 u32 shift; 2001 u64 base_cycles; 2002 u64 offset; 2003 }; 2004 2005 struct pvclock_gtod_data { 2006 seqcount_t seq; 2007 2008 struct pvclock_clock clock; /* extract of a clocksource struct */ 2009 struct pvclock_clock raw_clock; /* extract of a clocksource struct */ 2010 2011 ktime_t offs_boot; 2012 u64 wall_time_sec; 2013 }; 2014 2015 static struct pvclock_gtod_data pvclock_gtod_data; 2016 2017 static void update_pvclock_gtod(struct timekeeper *tk) 2018 { 2019 struct pvclock_gtod_data *vdata = &pvclock_gtod_data; 2020 2021 write_seqcount_begin(&vdata->seq); 2022 2023 /* copy pvclock gtod data */ 2024 vdata->clock.vclock_mode = tk->tkr_mono.clock->vdso_clock_mode; 2025 vdata->clock.cycle_last = tk->tkr_mono.cycle_last; 2026 vdata->clock.mask = tk->tkr_mono.mask; 2027 vdata->clock.mult = tk->tkr_mono.mult; 2028 vdata->clock.shift = tk->tkr_mono.shift; 2029 vdata->clock.base_cycles = tk->tkr_mono.xtime_nsec; 2030 vdata->clock.offset = tk->tkr_mono.base; 2031 2032 vdata->raw_clock.vclock_mode = tk->tkr_raw.clock->vdso_clock_mode; 2033 vdata->raw_clock.cycle_last = tk->tkr_raw.cycle_last; 2034 vdata->raw_clock.mask = tk->tkr_raw.mask; 2035 vdata->raw_clock.mult = tk->tkr_raw.mult; 2036 vdata->raw_clock.shift = tk->tkr_raw.shift; 2037 vdata->raw_clock.base_cycles = tk->tkr_raw.xtime_nsec; 2038 vdata->raw_clock.offset = tk->tkr_raw.base; 2039 2040 vdata->wall_time_sec = tk->xtime_sec; 2041 2042 vdata->offs_boot = tk->offs_boot; 2043 2044 write_seqcount_end(&vdata->seq); 2045 } 2046 2047 static s64 get_kvmclock_base_ns(void) 2048 { 2049 /* Count up from boot time, but with the frequency of the raw clock. */ 2050 return ktime_to_ns(ktime_add(ktime_get_raw(), pvclock_gtod_data.offs_boot)); 2051 } 2052 #else 2053 static s64 get_kvmclock_base_ns(void) 2054 { 2055 /* Master clock not used, so we can just use CLOCK_BOOTTIME. */ 2056 return ktime_get_boottime_ns(); 2057 } 2058 #endif 2059 2060 void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock, int sec_hi_ofs) 2061 { 2062 int version; 2063 int r; 2064 struct pvclock_wall_clock wc; 2065 u32 wc_sec_hi; 2066 u64 wall_nsec; 2067 2068 if (!wall_clock) 2069 return; 2070 2071 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version)); 2072 if (r) 2073 return; 2074 2075 if (version & 1) 2076 ++version; /* first time write, random junk */ 2077 2078 ++version; 2079 2080 if (kvm_write_guest(kvm, wall_clock, &version, sizeof(version))) 2081 return; 2082 2083 /* 2084 * The guest calculates current wall clock time by adding 2085 * system time (updated by kvm_guest_time_update below) to the 2086 * wall clock specified here. We do the reverse here. 2087 */ 2088 wall_nsec = ktime_get_real_ns() - get_kvmclock_ns(kvm); 2089 2090 wc.nsec = do_div(wall_nsec, 1000000000); 2091 wc.sec = (u32)wall_nsec; /* overflow in 2106 guest time */ 2092 wc.version = version; 2093 2094 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc)); 2095 2096 if (sec_hi_ofs) { 2097 wc_sec_hi = wall_nsec >> 32; 2098 kvm_write_guest(kvm, wall_clock + sec_hi_ofs, 2099 &wc_sec_hi, sizeof(wc_sec_hi)); 2100 } 2101 2102 version++; 2103 kvm_write_guest(kvm, wall_clock, &version, sizeof(version)); 2104 } 2105 2106 static void kvm_write_system_time(struct kvm_vcpu *vcpu, gpa_t system_time, 2107 bool old_msr, bool host_initiated) 2108 { 2109 struct kvm_arch *ka = &vcpu->kvm->arch; 2110 2111 if (vcpu->vcpu_id == 0 && !host_initiated) { 2112 if (ka->boot_vcpu_runs_old_kvmclock != old_msr) 2113 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu); 2114 2115 ka->boot_vcpu_runs_old_kvmclock = old_msr; 2116 } 2117 2118 vcpu->arch.time = system_time; 2119 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu); 2120 2121 /* we verify if the enable bit is set... */ 2122 vcpu->arch.pv_time_enabled = false; 2123 if (!(system_time & 1)) 2124 return; 2125 2126 if (!kvm_gfn_to_hva_cache_init(vcpu->kvm, 2127 &vcpu->arch.pv_time, system_time & ~1ULL, 2128 sizeof(struct pvclock_vcpu_time_info))) 2129 vcpu->arch.pv_time_enabled = true; 2130 2131 return; 2132 } 2133 2134 static uint32_t div_frac(uint32_t dividend, uint32_t divisor) 2135 { 2136 do_shl32_div32(dividend, divisor); 2137 return dividend; 2138 } 2139 2140 static void kvm_get_time_scale(uint64_t scaled_hz, uint64_t base_hz, 2141 s8 *pshift, u32 *pmultiplier) 2142 { 2143 uint64_t scaled64; 2144 int32_t shift = 0; 2145 uint64_t tps64; 2146 uint32_t tps32; 2147 2148 tps64 = base_hz; 2149 scaled64 = scaled_hz; 2150 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) { 2151 tps64 >>= 1; 2152 shift--; 2153 } 2154 2155 tps32 = (uint32_t)tps64; 2156 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) { 2157 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000) 2158 scaled64 >>= 1; 2159 else 2160 tps32 <<= 1; 2161 shift++; 2162 } 2163 2164 *pshift = shift; 2165 *pmultiplier = div_frac(scaled64, tps32); 2166 } 2167 2168 #ifdef CONFIG_X86_64 2169 static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0); 2170 #endif 2171 2172 static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz); 2173 static unsigned long max_tsc_khz; 2174 2175 static u32 adjust_tsc_khz(u32 khz, s32 ppm) 2176 { 2177 u64 v = (u64)khz * (1000000 + ppm); 2178 do_div(v, 1000000); 2179 return v; 2180 } 2181 2182 static int set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale) 2183 { 2184 u64 ratio; 2185 2186 /* Guest TSC same frequency as host TSC? */ 2187 if (!scale) { 2188 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio; 2189 return 0; 2190 } 2191 2192 /* TSC scaling supported? */ 2193 if (!kvm_has_tsc_control) { 2194 if (user_tsc_khz > tsc_khz) { 2195 vcpu->arch.tsc_catchup = 1; 2196 vcpu->arch.tsc_always_catchup = 1; 2197 return 0; 2198 } else { 2199 pr_warn_ratelimited("user requested TSC rate below hardware speed\n"); 2200 return -1; 2201 } 2202 } 2203 2204 /* TSC scaling required - calculate ratio */ 2205 ratio = mul_u64_u32_div(1ULL << kvm_tsc_scaling_ratio_frac_bits, 2206 user_tsc_khz, tsc_khz); 2207 2208 if (ratio == 0 || ratio >= kvm_max_tsc_scaling_ratio) { 2209 pr_warn_ratelimited("Invalid TSC scaling ratio - virtual-tsc-khz=%u\n", 2210 user_tsc_khz); 2211 return -1; 2212 } 2213 2214 vcpu->arch.tsc_scaling_ratio = ratio; 2215 return 0; 2216 } 2217 2218 static int kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz) 2219 { 2220 u32 thresh_lo, thresh_hi; 2221 int use_scaling = 0; 2222 2223 /* tsc_khz can be zero if TSC calibration fails */ 2224 if (user_tsc_khz == 0) { 2225 /* set tsc_scaling_ratio to a safe value */ 2226 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio; 2227 return -1; 2228 } 2229 2230 /* Compute a scale to convert nanoseconds in TSC cycles */ 2231 kvm_get_time_scale(user_tsc_khz * 1000LL, NSEC_PER_SEC, 2232 &vcpu->arch.virtual_tsc_shift, 2233 &vcpu->arch.virtual_tsc_mult); 2234 vcpu->arch.virtual_tsc_khz = user_tsc_khz; 2235 2236 /* 2237 * Compute the variation in TSC rate which is acceptable 2238 * within the range of tolerance and decide if the 2239 * rate being applied is within that bounds of the hardware 2240 * rate. If so, no scaling or compensation need be done. 2241 */ 2242 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm); 2243 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm); 2244 if (user_tsc_khz < thresh_lo || user_tsc_khz > thresh_hi) { 2245 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", user_tsc_khz, thresh_lo, thresh_hi); 2246 use_scaling = 1; 2247 } 2248 return set_tsc_khz(vcpu, user_tsc_khz, use_scaling); 2249 } 2250 2251 static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns) 2252 { 2253 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec, 2254 vcpu->arch.virtual_tsc_mult, 2255 vcpu->arch.virtual_tsc_shift); 2256 tsc += vcpu->arch.this_tsc_write; 2257 return tsc; 2258 } 2259 2260 static inline int gtod_is_based_on_tsc(int mode) 2261 { 2262 return mode == VDSO_CLOCKMODE_TSC || mode == VDSO_CLOCKMODE_HVCLOCK; 2263 } 2264 2265 static void kvm_track_tsc_matching(struct kvm_vcpu *vcpu) 2266 { 2267 #ifdef CONFIG_X86_64 2268 bool vcpus_matched; 2269 struct kvm_arch *ka = &vcpu->kvm->arch; 2270 struct pvclock_gtod_data *gtod = &pvclock_gtod_data; 2271 2272 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 == 2273 atomic_read(&vcpu->kvm->online_vcpus)); 2274 2275 /* 2276 * Once the masterclock is enabled, always perform request in 2277 * order to update it. 2278 * 2279 * In order to enable masterclock, the host clocksource must be TSC 2280 * and the vcpus need to have matched TSCs. When that happens, 2281 * perform request to enable masterclock. 2282 */ 2283 if (ka->use_master_clock || 2284 (gtod_is_based_on_tsc(gtod->clock.vclock_mode) && vcpus_matched)) 2285 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu); 2286 2287 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc, 2288 atomic_read(&vcpu->kvm->online_vcpus), 2289 ka->use_master_clock, gtod->clock.vclock_mode); 2290 #endif 2291 } 2292 2293 /* 2294 * Multiply tsc by a fixed point number represented by ratio. 2295 * 2296 * The most significant 64-N bits (mult) of ratio represent the 2297 * integral part of the fixed point number; the remaining N bits 2298 * (frac) represent the fractional part, ie. ratio represents a fixed 2299 * point number (mult + frac * 2^(-N)). 2300 * 2301 * N equals to kvm_tsc_scaling_ratio_frac_bits. 2302 */ 2303 static inline u64 __scale_tsc(u64 ratio, u64 tsc) 2304 { 2305 return mul_u64_u64_shr(tsc, ratio, kvm_tsc_scaling_ratio_frac_bits); 2306 } 2307 2308 u64 kvm_scale_tsc(struct kvm_vcpu *vcpu, u64 tsc) 2309 { 2310 u64 _tsc = tsc; 2311 u64 ratio = vcpu->arch.tsc_scaling_ratio; 2312 2313 if (ratio != kvm_default_tsc_scaling_ratio) 2314 _tsc = __scale_tsc(ratio, tsc); 2315 2316 return _tsc; 2317 } 2318 EXPORT_SYMBOL_GPL(kvm_scale_tsc); 2319 2320 static u64 kvm_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc) 2321 { 2322 u64 tsc; 2323 2324 tsc = kvm_scale_tsc(vcpu, rdtsc()); 2325 2326 return target_tsc - tsc; 2327 } 2328 2329 u64 kvm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc) 2330 { 2331 return vcpu->arch.l1_tsc_offset + kvm_scale_tsc(vcpu, host_tsc); 2332 } 2333 EXPORT_SYMBOL_GPL(kvm_read_l1_tsc); 2334 2335 static void kvm_vcpu_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset) 2336 { 2337 vcpu->arch.l1_tsc_offset = offset; 2338 vcpu->arch.tsc_offset = static_call(kvm_x86_write_l1_tsc_offset)(vcpu, offset); 2339 } 2340 2341 static inline bool kvm_check_tsc_unstable(void) 2342 { 2343 #ifdef CONFIG_X86_64 2344 /* 2345 * TSC is marked unstable when we're running on Hyper-V, 2346 * 'TSC page' clocksource is good. 2347 */ 2348 if (pvclock_gtod_data.clock.vclock_mode == VDSO_CLOCKMODE_HVCLOCK) 2349 return false; 2350 #endif 2351 return check_tsc_unstable(); 2352 } 2353 2354 static void kvm_synchronize_tsc(struct kvm_vcpu *vcpu, u64 data) 2355 { 2356 struct kvm *kvm = vcpu->kvm; 2357 u64 offset, ns, elapsed; 2358 unsigned long flags; 2359 bool matched; 2360 bool already_matched; 2361 bool synchronizing = false; 2362 2363 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags); 2364 offset = kvm_compute_tsc_offset(vcpu, data); 2365 ns = get_kvmclock_base_ns(); 2366 elapsed = ns - kvm->arch.last_tsc_nsec; 2367 2368 if (vcpu->arch.virtual_tsc_khz) { 2369 if (data == 0) { 2370 /* 2371 * detection of vcpu initialization -- need to sync 2372 * with other vCPUs. This particularly helps to keep 2373 * kvm_clock stable after CPU hotplug 2374 */ 2375 synchronizing = true; 2376 } else { 2377 u64 tsc_exp = kvm->arch.last_tsc_write + 2378 nsec_to_cycles(vcpu, elapsed); 2379 u64 tsc_hz = vcpu->arch.virtual_tsc_khz * 1000LL; 2380 /* 2381 * Special case: TSC write with a small delta (1 second) 2382 * of virtual cycle time against real time is 2383 * interpreted as an attempt to synchronize the CPU. 2384 */ 2385 synchronizing = data < tsc_exp + tsc_hz && 2386 data + tsc_hz > tsc_exp; 2387 } 2388 } 2389 2390 /* 2391 * For a reliable TSC, we can match TSC offsets, and for an unstable 2392 * TSC, we add elapsed time in this computation. We could let the 2393 * compensation code attempt to catch up if we fall behind, but 2394 * it's better to try to match offsets from the beginning. 2395 */ 2396 if (synchronizing && 2397 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) { 2398 if (!kvm_check_tsc_unstable()) { 2399 offset = kvm->arch.cur_tsc_offset; 2400 } else { 2401 u64 delta = nsec_to_cycles(vcpu, elapsed); 2402 data += delta; 2403 offset = kvm_compute_tsc_offset(vcpu, data); 2404 } 2405 matched = true; 2406 already_matched = (vcpu->arch.this_tsc_generation == kvm->arch.cur_tsc_generation); 2407 } else { 2408 /* 2409 * We split periods of matched TSC writes into generations. 2410 * For each generation, we track the original measured 2411 * nanosecond time, offset, and write, so if TSCs are in 2412 * sync, we can match exact offset, and if not, we can match 2413 * exact software computation in compute_guest_tsc() 2414 * 2415 * These values are tracked in kvm->arch.cur_xxx variables. 2416 */ 2417 kvm->arch.cur_tsc_generation++; 2418 kvm->arch.cur_tsc_nsec = ns; 2419 kvm->arch.cur_tsc_write = data; 2420 kvm->arch.cur_tsc_offset = offset; 2421 matched = false; 2422 } 2423 2424 /* 2425 * We also track th most recent recorded KHZ, write and time to 2426 * allow the matching interval to be extended at each write. 2427 */ 2428 kvm->arch.last_tsc_nsec = ns; 2429 kvm->arch.last_tsc_write = data; 2430 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz; 2431 2432 vcpu->arch.last_guest_tsc = data; 2433 2434 /* Keep track of which generation this VCPU has synchronized to */ 2435 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation; 2436 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec; 2437 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write; 2438 2439 kvm_vcpu_write_tsc_offset(vcpu, offset); 2440 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags); 2441 2442 spin_lock_irqsave(&kvm->arch.pvclock_gtod_sync_lock, flags); 2443 if (!matched) { 2444 kvm->arch.nr_vcpus_matched_tsc = 0; 2445 } else if (!already_matched) { 2446 kvm->arch.nr_vcpus_matched_tsc++; 2447 } 2448 2449 kvm_track_tsc_matching(vcpu); 2450 spin_unlock_irqrestore(&kvm->arch.pvclock_gtod_sync_lock, flags); 2451 } 2452 2453 static inline void adjust_tsc_offset_guest(struct kvm_vcpu *vcpu, 2454 s64 adjustment) 2455 { 2456 u64 tsc_offset = vcpu->arch.l1_tsc_offset; 2457 kvm_vcpu_write_tsc_offset(vcpu, tsc_offset + adjustment); 2458 } 2459 2460 static inline void adjust_tsc_offset_host(struct kvm_vcpu *vcpu, s64 adjustment) 2461 { 2462 if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio) 2463 WARN_ON(adjustment < 0); 2464 adjustment = kvm_scale_tsc(vcpu, (u64) adjustment); 2465 adjust_tsc_offset_guest(vcpu, adjustment); 2466 } 2467 2468 #ifdef CONFIG_X86_64 2469 2470 static u64 read_tsc(void) 2471 { 2472 u64 ret = (u64)rdtsc_ordered(); 2473 u64 last = pvclock_gtod_data.clock.cycle_last; 2474 2475 if (likely(ret >= last)) 2476 return ret; 2477 2478 /* 2479 * GCC likes to generate cmov here, but this branch is extremely 2480 * predictable (it's just a function of time and the likely is 2481 * very likely) and there's a data dependence, so force GCC 2482 * to generate a branch instead. I don't barrier() because 2483 * we don't actually need a barrier, and if this function 2484 * ever gets inlined it will generate worse code. 2485 */ 2486 asm volatile (""); 2487 return last; 2488 } 2489 2490 static inline u64 vgettsc(struct pvclock_clock *clock, u64 *tsc_timestamp, 2491 int *mode) 2492 { 2493 long v; 2494 u64 tsc_pg_val; 2495 2496 switch (clock->vclock_mode) { 2497 case VDSO_CLOCKMODE_HVCLOCK: 2498 tsc_pg_val = hv_read_tsc_page_tsc(hv_get_tsc_page(), 2499 tsc_timestamp); 2500 if (tsc_pg_val != U64_MAX) { 2501 /* TSC page valid */ 2502 *mode = VDSO_CLOCKMODE_HVCLOCK; 2503 v = (tsc_pg_val - clock->cycle_last) & 2504 clock->mask; 2505 } else { 2506 /* TSC page invalid */ 2507 *mode = VDSO_CLOCKMODE_NONE; 2508 } 2509 break; 2510 case VDSO_CLOCKMODE_TSC: 2511 *mode = VDSO_CLOCKMODE_TSC; 2512 *tsc_timestamp = read_tsc(); 2513 v = (*tsc_timestamp - clock->cycle_last) & 2514 clock->mask; 2515 break; 2516 default: 2517 *mode = VDSO_CLOCKMODE_NONE; 2518 } 2519 2520 if (*mode == VDSO_CLOCKMODE_NONE) 2521 *tsc_timestamp = v = 0; 2522 2523 return v * clock->mult; 2524 } 2525 2526 static int do_monotonic_raw(s64 *t, u64 *tsc_timestamp) 2527 { 2528 struct pvclock_gtod_data *gtod = &pvclock_gtod_data; 2529 unsigned long seq; 2530 int mode; 2531 u64 ns; 2532 2533 do { 2534 seq = read_seqcount_begin(>od->seq); 2535 ns = gtod->raw_clock.base_cycles; 2536 ns += vgettsc(>od->raw_clock, tsc_timestamp, &mode); 2537 ns >>= gtod->raw_clock.shift; 2538 ns += ktime_to_ns(ktime_add(gtod->raw_clock.offset, gtod->offs_boot)); 2539 } while (unlikely(read_seqcount_retry(>od->seq, seq))); 2540 *t = ns; 2541 2542 return mode; 2543 } 2544 2545 static int do_realtime(struct timespec64 *ts, u64 *tsc_timestamp) 2546 { 2547 struct pvclock_gtod_data *gtod = &pvclock_gtod_data; 2548 unsigned long seq; 2549 int mode; 2550 u64 ns; 2551 2552 do { 2553 seq = read_seqcount_begin(>od->seq); 2554 ts->tv_sec = gtod->wall_time_sec; 2555 ns = gtod->clock.base_cycles; 2556 ns += vgettsc(>od->clock, tsc_timestamp, &mode); 2557 ns >>= gtod->clock.shift; 2558 } while (unlikely(read_seqcount_retry(>od->seq, seq))); 2559 2560 ts->tv_sec += __iter_div_u64_rem(ns, NSEC_PER_SEC, &ns); 2561 ts->tv_nsec = ns; 2562 2563 return mode; 2564 } 2565 2566 /* returns true if host is using TSC based clocksource */ 2567 static bool kvm_get_time_and_clockread(s64 *kernel_ns, u64 *tsc_timestamp) 2568 { 2569 /* checked again under seqlock below */ 2570 if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode)) 2571 return false; 2572 2573 return gtod_is_based_on_tsc(do_monotonic_raw(kernel_ns, 2574 tsc_timestamp)); 2575 } 2576 2577 /* returns true if host is using TSC based clocksource */ 2578 static bool kvm_get_walltime_and_clockread(struct timespec64 *ts, 2579 u64 *tsc_timestamp) 2580 { 2581 /* checked again under seqlock below */ 2582 if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode)) 2583 return false; 2584 2585 return gtod_is_based_on_tsc(do_realtime(ts, tsc_timestamp)); 2586 } 2587 #endif 2588 2589 /* 2590 * 2591 * Assuming a stable TSC across physical CPUS, and a stable TSC 2592 * across virtual CPUs, the following condition is possible. 2593 * Each numbered line represents an event visible to both 2594 * CPUs at the next numbered event. 2595 * 2596 * "timespecX" represents host monotonic time. "tscX" represents 2597 * RDTSC value. 2598 * 2599 * VCPU0 on CPU0 | VCPU1 on CPU1 2600 * 2601 * 1. read timespec0,tsc0 2602 * 2. | timespec1 = timespec0 + N 2603 * | tsc1 = tsc0 + M 2604 * 3. transition to guest | transition to guest 2605 * 4. ret0 = timespec0 + (rdtsc - tsc0) | 2606 * 5. | ret1 = timespec1 + (rdtsc - tsc1) 2607 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M)) 2608 * 2609 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity: 2610 * 2611 * - ret0 < ret1 2612 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M)) 2613 * ... 2614 * - 0 < N - M => M < N 2615 * 2616 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not 2617 * always the case (the difference between two distinct xtime instances 2618 * might be smaller then the difference between corresponding TSC reads, 2619 * when updating guest vcpus pvclock areas). 2620 * 2621 * To avoid that problem, do not allow visibility of distinct 2622 * system_timestamp/tsc_timestamp values simultaneously: use a master 2623 * copy of host monotonic time values. Update that master copy 2624 * in lockstep. 2625 * 2626 * Rely on synchronization of host TSCs and guest TSCs for monotonicity. 2627 * 2628 */ 2629 2630 static void pvclock_update_vm_gtod_copy(struct kvm *kvm) 2631 { 2632 #ifdef CONFIG_X86_64 2633 struct kvm_arch *ka = &kvm->arch; 2634 int vclock_mode; 2635 bool host_tsc_clocksource, vcpus_matched; 2636 2637 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 == 2638 atomic_read(&kvm->online_vcpus)); 2639 2640 /* 2641 * If the host uses TSC clock, then passthrough TSC as stable 2642 * to the guest. 2643 */ 2644 host_tsc_clocksource = kvm_get_time_and_clockread( 2645 &ka->master_kernel_ns, 2646 &ka->master_cycle_now); 2647 2648 ka->use_master_clock = host_tsc_clocksource && vcpus_matched 2649 && !ka->backwards_tsc_observed 2650 && !ka->boot_vcpu_runs_old_kvmclock; 2651 2652 if (ka->use_master_clock) 2653 atomic_set(&kvm_guest_has_master_clock, 1); 2654 2655 vclock_mode = pvclock_gtod_data.clock.vclock_mode; 2656 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode, 2657 vcpus_matched); 2658 #endif 2659 } 2660 2661 void kvm_make_mclock_inprogress_request(struct kvm *kvm) 2662 { 2663 kvm_make_all_cpus_request(kvm, KVM_REQ_MCLOCK_INPROGRESS); 2664 } 2665 2666 static void kvm_gen_update_masterclock(struct kvm *kvm) 2667 { 2668 #ifdef CONFIG_X86_64 2669 int i; 2670 struct kvm_vcpu *vcpu; 2671 struct kvm_arch *ka = &kvm->arch; 2672 unsigned long flags; 2673 2674 kvm_hv_invalidate_tsc_page(kvm); 2675 2676 kvm_make_mclock_inprogress_request(kvm); 2677 2678 /* no guest entries from this point */ 2679 spin_lock_irqsave(&ka->pvclock_gtod_sync_lock, flags); 2680 pvclock_update_vm_gtod_copy(kvm); 2681 spin_unlock_irqrestore(&ka->pvclock_gtod_sync_lock, flags); 2682 2683 kvm_for_each_vcpu(i, vcpu, kvm) 2684 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 2685 2686 /* guest entries allowed */ 2687 kvm_for_each_vcpu(i, vcpu, kvm) 2688 kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu); 2689 #endif 2690 } 2691 2692 u64 get_kvmclock_ns(struct kvm *kvm) 2693 { 2694 struct kvm_arch *ka = &kvm->arch; 2695 struct pvclock_vcpu_time_info hv_clock; 2696 unsigned long flags; 2697 u64 ret; 2698 2699 spin_lock_irqsave(&ka->pvclock_gtod_sync_lock, flags); 2700 if (!ka->use_master_clock) { 2701 spin_unlock_irqrestore(&ka->pvclock_gtod_sync_lock, flags); 2702 return get_kvmclock_base_ns() + ka->kvmclock_offset; 2703 } 2704 2705 hv_clock.tsc_timestamp = ka->master_cycle_now; 2706 hv_clock.system_time = ka->master_kernel_ns + ka->kvmclock_offset; 2707 spin_unlock_irqrestore(&ka->pvclock_gtod_sync_lock, flags); 2708 2709 /* both __this_cpu_read() and rdtsc() should be on the same cpu */ 2710 get_cpu(); 2711 2712 if (__this_cpu_read(cpu_tsc_khz)) { 2713 kvm_get_time_scale(NSEC_PER_SEC, __this_cpu_read(cpu_tsc_khz) * 1000LL, 2714 &hv_clock.tsc_shift, 2715 &hv_clock.tsc_to_system_mul); 2716 ret = __pvclock_read_cycles(&hv_clock, rdtsc()); 2717 } else 2718 ret = get_kvmclock_base_ns() + ka->kvmclock_offset; 2719 2720 put_cpu(); 2721 2722 return ret; 2723 } 2724 2725 static void kvm_setup_pvclock_page(struct kvm_vcpu *v, 2726 struct gfn_to_hva_cache *cache, 2727 unsigned int offset) 2728 { 2729 struct kvm_vcpu_arch *vcpu = &v->arch; 2730 struct pvclock_vcpu_time_info guest_hv_clock; 2731 2732 if (unlikely(kvm_read_guest_offset_cached(v->kvm, cache, 2733 &guest_hv_clock, offset, sizeof(guest_hv_clock)))) 2734 return; 2735 2736 /* This VCPU is paused, but it's legal for a guest to read another 2737 * VCPU's kvmclock, so we really have to follow the specification where 2738 * it says that version is odd if data is being modified, and even after 2739 * it is consistent. 2740 * 2741 * Version field updates must be kept separate. This is because 2742 * kvm_write_guest_cached might use a "rep movs" instruction, and 2743 * writes within a string instruction are weakly ordered. So there 2744 * are three writes overall. 2745 * 2746 * As a small optimization, only write the version field in the first 2747 * and third write. The vcpu->pv_time cache is still valid, because the 2748 * version field is the first in the struct. 2749 */ 2750 BUILD_BUG_ON(offsetof(struct pvclock_vcpu_time_info, version) != 0); 2751 2752 if (guest_hv_clock.version & 1) 2753 ++guest_hv_clock.version; /* first time write, random junk */ 2754 2755 vcpu->hv_clock.version = guest_hv_clock.version + 1; 2756 kvm_write_guest_offset_cached(v->kvm, cache, 2757 &vcpu->hv_clock, offset, 2758 sizeof(vcpu->hv_clock.version)); 2759 2760 smp_wmb(); 2761 2762 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */ 2763 vcpu->hv_clock.flags |= (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED); 2764 2765 if (vcpu->pvclock_set_guest_stopped_request) { 2766 vcpu->hv_clock.flags |= PVCLOCK_GUEST_STOPPED; 2767 vcpu->pvclock_set_guest_stopped_request = false; 2768 } 2769 2770 trace_kvm_pvclock_update(v->vcpu_id, &vcpu->hv_clock); 2771 2772 kvm_write_guest_offset_cached(v->kvm, cache, 2773 &vcpu->hv_clock, offset, 2774 sizeof(vcpu->hv_clock)); 2775 2776 smp_wmb(); 2777 2778 vcpu->hv_clock.version++; 2779 kvm_write_guest_offset_cached(v->kvm, cache, 2780 &vcpu->hv_clock, offset, 2781 sizeof(vcpu->hv_clock.version)); 2782 } 2783 2784 static int kvm_guest_time_update(struct kvm_vcpu *v) 2785 { 2786 unsigned long flags, tgt_tsc_khz; 2787 struct kvm_vcpu_arch *vcpu = &v->arch; 2788 struct kvm_arch *ka = &v->kvm->arch; 2789 s64 kernel_ns; 2790 u64 tsc_timestamp, host_tsc; 2791 u8 pvclock_flags; 2792 bool use_master_clock; 2793 2794 kernel_ns = 0; 2795 host_tsc = 0; 2796 2797 /* 2798 * If the host uses TSC clock, then passthrough TSC as stable 2799 * to the guest. 2800 */ 2801 spin_lock_irqsave(&ka->pvclock_gtod_sync_lock, flags); 2802 use_master_clock = ka->use_master_clock; 2803 if (use_master_clock) { 2804 host_tsc = ka->master_cycle_now; 2805 kernel_ns = ka->master_kernel_ns; 2806 } 2807 spin_unlock_irqrestore(&ka->pvclock_gtod_sync_lock, flags); 2808 2809 /* Keep irq disabled to prevent changes to the clock */ 2810 local_irq_save(flags); 2811 tgt_tsc_khz = __this_cpu_read(cpu_tsc_khz); 2812 if (unlikely(tgt_tsc_khz == 0)) { 2813 local_irq_restore(flags); 2814 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v); 2815 return 1; 2816 } 2817 if (!use_master_clock) { 2818 host_tsc = rdtsc(); 2819 kernel_ns = get_kvmclock_base_ns(); 2820 } 2821 2822 tsc_timestamp = kvm_read_l1_tsc(v, host_tsc); 2823 2824 /* 2825 * We may have to catch up the TSC to match elapsed wall clock 2826 * time for two reasons, even if kvmclock is used. 2827 * 1) CPU could have been running below the maximum TSC rate 2828 * 2) Broken TSC compensation resets the base at each VCPU 2829 * entry to avoid unknown leaps of TSC even when running 2830 * again on the same CPU. This may cause apparent elapsed 2831 * time to disappear, and the guest to stand still or run 2832 * very slowly. 2833 */ 2834 if (vcpu->tsc_catchup) { 2835 u64 tsc = compute_guest_tsc(v, kernel_ns); 2836 if (tsc > tsc_timestamp) { 2837 adjust_tsc_offset_guest(v, tsc - tsc_timestamp); 2838 tsc_timestamp = tsc; 2839 } 2840 } 2841 2842 local_irq_restore(flags); 2843 2844 /* With all the info we got, fill in the values */ 2845 2846 if (kvm_has_tsc_control) 2847 tgt_tsc_khz = kvm_scale_tsc(v, tgt_tsc_khz); 2848 2849 if (unlikely(vcpu->hw_tsc_khz != tgt_tsc_khz)) { 2850 kvm_get_time_scale(NSEC_PER_SEC, tgt_tsc_khz * 1000LL, 2851 &vcpu->hv_clock.tsc_shift, 2852 &vcpu->hv_clock.tsc_to_system_mul); 2853 vcpu->hw_tsc_khz = tgt_tsc_khz; 2854 } 2855 2856 vcpu->hv_clock.tsc_timestamp = tsc_timestamp; 2857 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset; 2858 vcpu->last_guest_tsc = tsc_timestamp; 2859 2860 /* If the host uses TSC clocksource, then it is stable */ 2861 pvclock_flags = 0; 2862 if (use_master_clock) 2863 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT; 2864 2865 vcpu->hv_clock.flags = pvclock_flags; 2866 2867 if (vcpu->pv_time_enabled) 2868 kvm_setup_pvclock_page(v, &vcpu->pv_time, 0); 2869 if (vcpu->xen.vcpu_info_set) 2870 kvm_setup_pvclock_page(v, &vcpu->xen.vcpu_info_cache, 2871 offsetof(struct compat_vcpu_info, time)); 2872 if (vcpu->xen.vcpu_time_info_set) 2873 kvm_setup_pvclock_page(v, &vcpu->xen.vcpu_time_info_cache, 0); 2874 if (v == kvm_get_vcpu(v->kvm, 0)) 2875 kvm_hv_setup_tsc_page(v->kvm, &vcpu->hv_clock); 2876 return 0; 2877 } 2878 2879 /* 2880 * kvmclock updates which are isolated to a given vcpu, such as 2881 * vcpu->cpu migration, should not allow system_timestamp from 2882 * the rest of the vcpus to remain static. Otherwise ntp frequency 2883 * correction applies to one vcpu's system_timestamp but not 2884 * the others. 2885 * 2886 * So in those cases, request a kvmclock update for all vcpus. 2887 * We need to rate-limit these requests though, as they can 2888 * considerably slow guests that have a large number of vcpus. 2889 * The time for a remote vcpu to update its kvmclock is bound 2890 * by the delay we use to rate-limit the updates. 2891 */ 2892 2893 #define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100) 2894 2895 static void kvmclock_update_fn(struct work_struct *work) 2896 { 2897 int i; 2898 struct delayed_work *dwork = to_delayed_work(work); 2899 struct kvm_arch *ka = container_of(dwork, struct kvm_arch, 2900 kvmclock_update_work); 2901 struct kvm *kvm = container_of(ka, struct kvm, arch); 2902 struct kvm_vcpu *vcpu; 2903 2904 kvm_for_each_vcpu(i, vcpu, kvm) { 2905 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 2906 kvm_vcpu_kick(vcpu); 2907 } 2908 } 2909 2910 static void kvm_gen_kvmclock_update(struct kvm_vcpu *v) 2911 { 2912 struct kvm *kvm = v->kvm; 2913 2914 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v); 2915 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 2916 KVMCLOCK_UPDATE_DELAY); 2917 } 2918 2919 #define KVMCLOCK_SYNC_PERIOD (300 * HZ) 2920 2921 static void kvmclock_sync_fn(struct work_struct *work) 2922 { 2923 struct delayed_work *dwork = to_delayed_work(work); 2924 struct kvm_arch *ka = container_of(dwork, struct kvm_arch, 2925 kvmclock_sync_work); 2926 struct kvm *kvm = container_of(ka, struct kvm, arch); 2927 2928 if (!kvmclock_periodic_sync) 2929 return; 2930 2931 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0); 2932 schedule_delayed_work(&kvm->arch.kvmclock_sync_work, 2933 KVMCLOCK_SYNC_PERIOD); 2934 } 2935 2936 /* 2937 * On AMD, HWCR[McStatusWrEn] controls whether setting MCi_STATUS results in #GP. 2938 */ 2939 static bool can_set_mci_status(struct kvm_vcpu *vcpu) 2940 { 2941 /* McStatusWrEn enabled? */ 2942 if (guest_cpuid_is_amd_or_hygon(vcpu)) 2943 return !!(vcpu->arch.msr_hwcr & BIT_ULL(18)); 2944 2945 return false; 2946 } 2947 2948 static int set_msr_mce(struct kvm_vcpu *vcpu, struct msr_data *msr_info) 2949 { 2950 u64 mcg_cap = vcpu->arch.mcg_cap; 2951 unsigned bank_num = mcg_cap & 0xff; 2952 u32 msr = msr_info->index; 2953 u64 data = msr_info->data; 2954 2955 switch (msr) { 2956 case MSR_IA32_MCG_STATUS: 2957 vcpu->arch.mcg_status = data; 2958 break; 2959 case MSR_IA32_MCG_CTL: 2960 if (!(mcg_cap & MCG_CTL_P) && 2961 (data || !msr_info->host_initiated)) 2962 return 1; 2963 if (data != 0 && data != ~(u64)0) 2964 return 1; 2965 vcpu->arch.mcg_ctl = data; 2966 break; 2967 default: 2968 if (msr >= MSR_IA32_MC0_CTL && 2969 msr < MSR_IA32_MCx_CTL(bank_num)) { 2970 u32 offset = array_index_nospec( 2971 msr - MSR_IA32_MC0_CTL, 2972 MSR_IA32_MCx_CTL(bank_num) - MSR_IA32_MC0_CTL); 2973 2974 /* only 0 or all 1s can be written to IA32_MCi_CTL 2975 * some Linux kernels though clear bit 10 in bank 4 to 2976 * workaround a BIOS/GART TBL issue on AMD K8s, ignore 2977 * this to avoid an uncatched #GP in the guest 2978 */ 2979 if ((offset & 0x3) == 0 && 2980 data != 0 && (data | (1 << 10)) != ~(u64)0) 2981 return -1; 2982 2983 /* MCi_STATUS */ 2984 if (!msr_info->host_initiated && 2985 (offset & 0x3) == 1 && data != 0) { 2986 if (!can_set_mci_status(vcpu)) 2987 return -1; 2988 } 2989 2990 vcpu->arch.mce_banks[offset] = data; 2991 break; 2992 } 2993 return 1; 2994 } 2995 return 0; 2996 } 2997 2998 static inline bool kvm_pv_async_pf_enabled(struct kvm_vcpu *vcpu) 2999 { 3000 u64 mask = KVM_ASYNC_PF_ENABLED | KVM_ASYNC_PF_DELIVERY_AS_INT; 3001 3002 return (vcpu->arch.apf.msr_en_val & mask) == mask; 3003 } 3004 3005 static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data) 3006 { 3007 gpa_t gpa = data & ~0x3f; 3008 3009 /* Bits 4:5 are reserved, Should be zero */ 3010 if (data & 0x30) 3011 return 1; 3012 3013 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_VMEXIT) && 3014 (data & KVM_ASYNC_PF_DELIVERY_AS_PF_VMEXIT)) 3015 return 1; 3016 3017 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_INT) && 3018 (data & KVM_ASYNC_PF_DELIVERY_AS_INT)) 3019 return 1; 3020 3021 if (!lapic_in_kernel(vcpu)) 3022 return data ? 1 : 0; 3023 3024 vcpu->arch.apf.msr_en_val = data; 3025 3026 if (!kvm_pv_async_pf_enabled(vcpu)) { 3027 kvm_clear_async_pf_completion_queue(vcpu); 3028 kvm_async_pf_hash_reset(vcpu); 3029 return 0; 3030 } 3031 3032 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa, 3033 sizeof(u64))) 3034 return 1; 3035 3036 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS); 3037 vcpu->arch.apf.delivery_as_pf_vmexit = data & KVM_ASYNC_PF_DELIVERY_AS_PF_VMEXIT; 3038 3039 kvm_async_pf_wakeup_all(vcpu); 3040 3041 return 0; 3042 } 3043 3044 static int kvm_pv_enable_async_pf_int(struct kvm_vcpu *vcpu, u64 data) 3045 { 3046 /* Bits 8-63 are reserved */ 3047 if (data >> 8) 3048 return 1; 3049 3050 if (!lapic_in_kernel(vcpu)) 3051 return 1; 3052 3053 vcpu->arch.apf.msr_int_val = data; 3054 3055 vcpu->arch.apf.vec = data & KVM_ASYNC_PF_VEC_MASK; 3056 3057 return 0; 3058 } 3059 3060 static void kvmclock_reset(struct kvm_vcpu *vcpu) 3061 { 3062 vcpu->arch.pv_time_enabled = false; 3063 vcpu->arch.time = 0; 3064 } 3065 3066 static void kvm_vcpu_flush_tlb_all(struct kvm_vcpu *vcpu) 3067 { 3068 ++vcpu->stat.tlb_flush; 3069 static_call(kvm_x86_tlb_flush_all)(vcpu); 3070 } 3071 3072 static void kvm_vcpu_flush_tlb_guest(struct kvm_vcpu *vcpu) 3073 { 3074 ++vcpu->stat.tlb_flush; 3075 static_call(kvm_x86_tlb_flush_guest)(vcpu); 3076 } 3077 3078 static void record_steal_time(struct kvm_vcpu *vcpu) 3079 { 3080 struct kvm_host_map map; 3081 struct kvm_steal_time *st; 3082 3083 if (kvm_xen_msr_enabled(vcpu->kvm)) { 3084 kvm_xen_runstate_set_running(vcpu); 3085 return; 3086 } 3087 3088 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED)) 3089 return; 3090 3091 /* -EAGAIN is returned in atomic context so we can just return. */ 3092 if (kvm_map_gfn(vcpu, vcpu->arch.st.msr_val >> PAGE_SHIFT, 3093 &map, &vcpu->arch.st.cache, false)) 3094 return; 3095 3096 st = map.hva + 3097 offset_in_page(vcpu->arch.st.msr_val & KVM_STEAL_VALID_BITS); 3098 3099 /* 3100 * Doing a TLB flush here, on the guest's behalf, can avoid 3101 * expensive IPIs. 3102 */ 3103 if (guest_pv_has(vcpu, KVM_FEATURE_PV_TLB_FLUSH)) { 3104 trace_kvm_pv_tlb_flush(vcpu->vcpu_id, 3105 st->preempted & KVM_VCPU_FLUSH_TLB); 3106 if (xchg(&st->preempted, 0) & KVM_VCPU_FLUSH_TLB) 3107 kvm_vcpu_flush_tlb_guest(vcpu); 3108 } else { 3109 st->preempted = 0; 3110 } 3111 3112 vcpu->arch.st.preempted = 0; 3113 3114 if (st->version & 1) 3115 st->version += 1; /* first time write, random junk */ 3116 3117 st->version += 1; 3118 3119 smp_wmb(); 3120 3121 st->steal += current->sched_info.run_delay - 3122 vcpu->arch.st.last_steal; 3123 vcpu->arch.st.last_steal = current->sched_info.run_delay; 3124 3125 smp_wmb(); 3126 3127 st->version += 1; 3128 3129 kvm_unmap_gfn(vcpu, &map, &vcpu->arch.st.cache, true, false); 3130 } 3131 3132 int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info) 3133 { 3134 bool pr = false; 3135 u32 msr = msr_info->index; 3136 u64 data = msr_info->data; 3137 3138 if (msr && msr == vcpu->kvm->arch.xen_hvm_config.msr) 3139 return kvm_xen_write_hypercall_page(vcpu, data); 3140 3141 switch (msr) { 3142 case MSR_AMD64_NB_CFG: 3143 case MSR_IA32_UCODE_WRITE: 3144 case MSR_VM_HSAVE_PA: 3145 case MSR_AMD64_PATCH_LOADER: 3146 case MSR_AMD64_BU_CFG2: 3147 case MSR_AMD64_DC_CFG: 3148 case MSR_F15H_EX_CFG: 3149 break; 3150 3151 case MSR_IA32_UCODE_REV: 3152 if (msr_info->host_initiated) 3153 vcpu->arch.microcode_version = data; 3154 break; 3155 case MSR_IA32_ARCH_CAPABILITIES: 3156 if (!msr_info->host_initiated) 3157 return 1; 3158 vcpu->arch.arch_capabilities = data; 3159 break; 3160 case MSR_IA32_PERF_CAPABILITIES: { 3161 struct kvm_msr_entry msr_ent = {.index = msr, .data = 0}; 3162 3163 if (!msr_info->host_initiated) 3164 return 1; 3165 if (guest_cpuid_has(vcpu, X86_FEATURE_PDCM) && kvm_get_msr_feature(&msr_ent)) 3166 return 1; 3167 if (data & ~msr_ent.data) 3168 return 1; 3169 3170 vcpu->arch.perf_capabilities = data; 3171 3172 return 0; 3173 } 3174 case MSR_EFER: 3175 return set_efer(vcpu, msr_info); 3176 case MSR_K7_HWCR: 3177 data &= ~(u64)0x40; /* ignore flush filter disable */ 3178 data &= ~(u64)0x100; /* ignore ignne emulation enable */ 3179 data &= ~(u64)0x8; /* ignore TLB cache disable */ 3180 3181 /* Handle McStatusWrEn */ 3182 if (data == BIT_ULL(18)) { 3183 vcpu->arch.msr_hwcr = data; 3184 } else if (data != 0) { 3185 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n", 3186 data); 3187 return 1; 3188 } 3189 break; 3190 case MSR_FAM10H_MMIO_CONF_BASE: 3191 if (data != 0) { 3192 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: " 3193 "0x%llx\n", data); 3194 return 1; 3195 } 3196 break; 3197 case 0x200 ... 0x2ff: 3198 return kvm_mtrr_set_msr(vcpu, msr, data); 3199 case MSR_IA32_APICBASE: 3200 return kvm_set_apic_base(vcpu, msr_info); 3201 case APIC_BASE_MSR ... APIC_BASE_MSR + 0xff: 3202 return kvm_x2apic_msr_write(vcpu, msr, data); 3203 case MSR_IA32_TSC_DEADLINE: 3204 kvm_set_lapic_tscdeadline_msr(vcpu, data); 3205 break; 3206 case MSR_IA32_TSC_ADJUST: 3207 if (guest_cpuid_has(vcpu, X86_FEATURE_TSC_ADJUST)) { 3208 if (!msr_info->host_initiated) { 3209 s64 adj = data - vcpu->arch.ia32_tsc_adjust_msr; 3210 adjust_tsc_offset_guest(vcpu, adj); 3211 } 3212 vcpu->arch.ia32_tsc_adjust_msr = data; 3213 } 3214 break; 3215 case MSR_IA32_MISC_ENABLE: 3216 if (!kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_MISC_ENABLE_NO_MWAIT) && 3217 ((vcpu->arch.ia32_misc_enable_msr ^ data) & MSR_IA32_MISC_ENABLE_MWAIT)) { 3218 if (!guest_cpuid_has(vcpu, X86_FEATURE_XMM3)) 3219 return 1; 3220 vcpu->arch.ia32_misc_enable_msr = data; 3221 kvm_update_cpuid_runtime(vcpu); 3222 } else { 3223 vcpu->arch.ia32_misc_enable_msr = data; 3224 } 3225 break; 3226 case MSR_IA32_SMBASE: 3227 if (!msr_info->host_initiated) 3228 return 1; 3229 vcpu->arch.smbase = data; 3230 break; 3231 case MSR_IA32_POWER_CTL: 3232 vcpu->arch.msr_ia32_power_ctl = data; 3233 break; 3234 case MSR_IA32_TSC: 3235 if (msr_info->host_initiated) { 3236 kvm_synchronize_tsc(vcpu, data); 3237 } else { 3238 u64 adj = kvm_compute_tsc_offset(vcpu, data) - vcpu->arch.l1_tsc_offset; 3239 adjust_tsc_offset_guest(vcpu, adj); 3240 vcpu->arch.ia32_tsc_adjust_msr += adj; 3241 } 3242 break; 3243 case MSR_IA32_XSS: 3244 if (!msr_info->host_initiated && 3245 !guest_cpuid_has(vcpu, X86_FEATURE_XSAVES)) 3246 return 1; 3247 /* 3248 * KVM supports exposing PT to the guest, but does not support 3249 * IA32_XSS[bit 8]. Guests have to use RDMSR/WRMSR rather than 3250 * XSAVES/XRSTORS to save/restore PT MSRs. 3251 */ 3252 if (data & ~supported_xss) 3253 return 1; 3254 vcpu->arch.ia32_xss = data; 3255 break; 3256 case MSR_SMI_COUNT: 3257 if (!msr_info->host_initiated) 3258 return 1; 3259 vcpu->arch.smi_count = data; 3260 break; 3261 case MSR_KVM_WALL_CLOCK_NEW: 3262 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE2)) 3263 return 1; 3264 3265 vcpu->kvm->arch.wall_clock = data; 3266 kvm_write_wall_clock(vcpu->kvm, data, 0); 3267 break; 3268 case MSR_KVM_WALL_CLOCK: 3269 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE)) 3270 return 1; 3271 3272 vcpu->kvm->arch.wall_clock = data; 3273 kvm_write_wall_clock(vcpu->kvm, data, 0); 3274 break; 3275 case MSR_KVM_SYSTEM_TIME_NEW: 3276 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE2)) 3277 return 1; 3278 3279 kvm_write_system_time(vcpu, data, false, msr_info->host_initiated); 3280 break; 3281 case MSR_KVM_SYSTEM_TIME: 3282 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE)) 3283 return 1; 3284 3285 kvm_write_system_time(vcpu, data, true, msr_info->host_initiated); 3286 break; 3287 case MSR_KVM_ASYNC_PF_EN: 3288 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF)) 3289 return 1; 3290 3291 if (kvm_pv_enable_async_pf(vcpu, data)) 3292 return 1; 3293 break; 3294 case MSR_KVM_ASYNC_PF_INT: 3295 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_INT)) 3296 return 1; 3297 3298 if (kvm_pv_enable_async_pf_int(vcpu, data)) 3299 return 1; 3300 break; 3301 case MSR_KVM_ASYNC_PF_ACK: 3302 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF)) 3303 return 1; 3304 if (data & 0x1) { 3305 vcpu->arch.apf.pageready_pending = false; 3306 kvm_check_async_pf_completion(vcpu); 3307 } 3308 break; 3309 case MSR_KVM_STEAL_TIME: 3310 if (!guest_pv_has(vcpu, KVM_FEATURE_STEAL_TIME)) 3311 return 1; 3312 3313 if (unlikely(!sched_info_on())) 3314 return 1; 3315 3316 if (data & KVM_STEAL_RESERVED_MASK) 3317 return 1; 3318 3319 vcpu->arch.st.msr_val = data; 3320 3321 if (!(data & KVM_MSR_ENABLED)) 3322 break; 3323 3324 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu); 3325 3326 break; 3327 case MSR_KVM_PV_EOI_EN: 3328 if (!guest_pv_has(vcpu, KVM_FEATURE_PV_EOI)) 3329 return 1; 3330 3331 if (kvm_lapic_enable_pv_eoi(vcpu, data, sizeof(u8))) 3332 return 1; 3333 break; 3334 3335 case MSR_KVM_POLL_CONTROL: 3336 if (!guest_pv_has(vcpu, KVM_FEATURE_POLL_CONTROL)) 3337 return 1; 3338 3339 /* only enable bit supported */ 3340 if (data & (-1ULL << 1)) 3341 return 1; 3342 3343 vcpu->arch.msr_kvm_poll_control = data; 3344 break; 3345 3346 case MSR_IA32_MCG_CTL: 3347 case MSR_IA32_MCG_STATUS: 3348 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1: 3349 return set_msr_mce(vcpu, msr_info); 3350 3351 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3: 3352 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1: 3353 pr = true; 3354 fallthrough; 3355 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3: 3356 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1: 3357 if (kvm_pmu_is_valid_msr(vcpu, msr)) 3358 return kvm_pmu_set_msr(vcpu, msr_info); 3359 3360 if (pr || data != 0) 3361 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: " 3362 "0x%x data 0x%llx\n", msr, data); 3363 break; 3364 case MSR_K7_CLK_CTL: 3365 /* 3366 * Ignore all writes to this no longer documented MSR. 3367 * Writes are only relevant for old K7 processors, 3368 * all pre-dating SVM, but a recommended workaround from 3369 * AMD for these chips. It is possible to specify the 3370 * affected processor models on the command line, hence 3371 * the need to ignore the workaround. 3372 */ 3373 break; 3374 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15: 3375 case HV_X64_MSR_SYNDBG_CONTROL ... HV_X64_MSR_SYNDBG_PENDING_BUFFER: 3376 case HV_X64_MSR_SYNDBG_OPTIONS: 3377 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4: 3378 case HV_X64_MSR_CRASH_CTL: 3379 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT: 3380 case HV_X64_MSR_REENLIGHTENMENT_CONTROL: 3381 case HV_X64_MSR_TSC_EMULATION_CONTROL: 3382 case HV_X64_MSR_TSC_EMULATION_STATUS: 3383 return kvm_hv_set_msr_common(vcpu, msr, data, 3384 msr_info->host_initiated); 3385 case MSR_IA32_BBL_CR_CTL3: 3386 /* Drop writes to this legacy MSR -- see rdmsr 3387 * counterpart for further detail. 3388 */ 3389 if (report_ignored_msrs) 3390 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data 0x%llx\n", 3391 msr, data); 3392 break; 3393 case MSR_AMD64_OSVW_ID_LENGTH: 3394 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW)) 3395 return 1; 3396 vcpu->arch.osvw.length = data; 3397 break; 3398 case MSR_AMD64_OSVW_STATUS: 3399 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW)) 3400 return 1; 3401 vcpu->arch.osvw.status = data; 3402 break; 3403 case MSR_PLATFORM_INFO: 3404 if (!msr_info->host_initiated || 3405 (!(data & MSR_PLATFORM_INFO_CPUID_FAULT) && 3406 cpuid_fault_enabled(vcpu))) 3407 return 1; 3408 vcpu->arch.msr_platform_info = data; 3409 break; 3410 case MSR_MISC_FEATURES_ENABLES: 3411 if (data & ~MSR_MISC_FEATURES_ENABLES_CPUID_FAULT || 3412 (data & MSR_MISC_FEATURES_ENABLES_CPUID_FAULT && 3413 !supports_cpuid_fault(vcpu))) 3414 return 1; 3415 vcpu->arch.msr_misc_features_enables = data; 3416 break; 3417 default: 3418 if (kvm_pmu_is_valid_msr(vcpu, msr)) 3419 return kvm_pmu_set_msr(vcpu, msr_info); 3420 return KVM_MSR_RET_INVALID; 3421 } 3422 return 0; 3423 } 3424 EXPORT_SYMBOL_GPL(kvm_set_msr_common); 3425 3426 static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata, bool host) 3427 { 3428 u64 data; 3429 u64 mcg_cap = vcpu->arch.mcg_cap; 3430 unsigned bank_num = mcg_cap & 0xff; 3431 3432 switch (msr) { 3433 case MSR_IA32_P5_MC_ADDR: 3434 case MSR_IA32_P5_MC_TYPE: 3435 data = 0; 3436 break; 3437 case MSR_IA32_MCG_CAP: 3438 data = vcpu->arch.mcg_cap; 3439 break; 3440 case MSR_IA32_MCG_CTL: 3441 if (!(mcg_cap & MCG_CTL_P) && !host) 3442 return 1; 3443 data = vcpu->arch.mcg_ctl; 3444 break; 3445 case MSR_IA32_MCG_STATUS: 3446 data = vcpu->arch.mcg_status; 3447 break; 3448 default: 3449 if (msr >= MSR_IA32_MC0_CTL && 3450 msr < MSR_IA32_MCx_CTL(bank_num)) { 3451 u32 offset = array_index_nospec( 3452 msr - MSR_IA32_MC0_CTL, 3453 MSR_IA32_MCx_CTL(bank_num) - MSR_IA32_MC0_CTL); 3454 3455 data = vcpu->arch.mce_banks[offset]; 3456 break; 3457 } 3458 return 1; 3459 } 3460 *pdata = data; 3461 return 0; 3462 } 3463 3464 int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info) 3465 { 3466 switch (msr_info->index) { 3467 case MSR_IA32_PLATFORM_ID: 3468 case MSR_IA32_EBL_CR_POWERON: 3469 case MSR_IA32_LASTBRANCHFROMIP: 3470 case MSR_IA32_LASTBRANCHTOIP: 3471 case MSR_IA32_LASTINTFROMIP: 3472 case MSR_IA32_LASTINTTOIP: 3473 case MSR_AMD64_SYSCFG: 3474 case MSR_K8_TSEG_ADDR: 3475 case MSR_K8_TSEG_MASK: 3476 case MSR_VM_HSAVE_PA: 3477 case MSR_K8_INT_PENDING_MSG: 3478 case MSR_AMD64_NB_CFG: 3479 case MSR_FAM10H_MMIO_CONF_BASE: 3480 case MSR_AMD64_BU_CFG2: 3481 case MSR_IA32_PERF_CTL: 3482 case MSR_AMD64_DC_CFG: 3483 case MSR_F15H_EX_CFG: 3484 /* 3485 * Intel Sandy Bridge CPUs must support the RAPL (running average power 3486 * limit) MSRs. Just return 0, as we do not want to expose the host 3487 * data here. Do not conditionalize this on CPUID, as KVM does not do 3488 * so for existing CPU-specific MSRs. 3489 */ 3490 case MSR_RAPL_POWER_UNIT: 3491 case MSR_PP0_ENERGY_STATUS: /* Power plane 0 (core) */ 3492 case MSR_PP1_ENERGY_STATUS: /* Power plane 1 (graphics uncore) */ 3493 case MSR_PKG_ENERGY_STATUS: /* Total package */ 3494 case MSR_DRAM_ENERGY_STATUS: /* DRAM controller */ 3495 msr_info->data = 0; 3496 break; 3497 case MSR_F15H_PERF_CTL0 ... MSR_F15H_PERF_CTR5: 3498 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index)) 3499 return kvm_pmu_get_msr(vcpu, msr_info); 3500 if (!msr_info->host_initiated) 3501 return 1; 3502 msr_info->data = 0; 3503 break; 3504 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3: 3505 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3: 3506 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1: 3507 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1: 3508 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index)) 3509 return kvm_pmu_get_msr(vcpu, msr_info); 3510 msr_info->data = 0; 3511 break; 3512 case MSR_IA32_UCODE_REV: 3513 msr_info->data = vcpu->arch.microcode_version; 3514 break; 3515 case MSR_IA32_ARCH_CAPABILITIES: 3516 if (!msr_info->host_initiated && 3517 !guest_cpuid_has(vcpu, X86_FEATURE_ARCH_CAPABILITIES)) 3518 return 1; 3519 msr_info->data = vcpu->arch.arch_capabilities; 3520 break; 3521 case MSR_IA32_PERF_CAPABILITIES: 3522 if (!msr_info->host_initiated && 3523 !guest_cpuid_has(vcpu, X86_FEATURE_PDCM)) 3524 return 1; 3525 msr_info->data = vcpu->arch.perf_capabilities; 3526 break; 3527 case MSR_IA32_POWER_CTL: 3528 msr_info->data = vcpu->arch.msr_ia32_power_ctl; 3529 break; 3530 case MSR_IA32_TSC: { 3531 /* 3532 * Intel SDM states that MSR_IA32_TSC read adds the TSC offset 3533 * even when not intercepted. AMD manual doesn't explicitly 3534 * state this but appears to behave the same. 3535 * 3536 * On userspace reads and writes, however, we unconditionally 3537 * return L1's TSC value to ensure backwards-compatible 3538 * behavior for migration. 3539 */ 3540 u64 tsc_offset = msr_info->host_initiated ? vcpu->arch.l1_tsc_offset : 3541 vcpu->arch.tsc_offset; 3542 3543 msr_info->data = kvm_scale_tsc(vcpu, rdtsc()) + tsc_offset; 3544 break; 3545 } 3546 case MSR_MTRRcap: 3547 case 0x200 ... 0x2ff: 3548 return kvm_mtrr_get_msr(vcpu, msr_info->index, &msr_info->data); 3549 case 0xcd: /* fsb frequency */ 3550 msr_info->data = 3; 3551 break; 3552 /* 3553 * MSR_EBC_FREQUENCY_ID 3554 * Conservative value valid for even the basic CPU models. 3555 * Models 0,1: 000 in bits 23:21 indicating a bus speed of 3556 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz, 3557 * and 266MHz for model 3, or 4. Set Core Clock 3558 * Frequency to System Bus Frequency Ratio to 1 (bits 3559 * 31:24) even though these are only valid for CPU 3560 * models > 2, however guests may end up dividing or 3561 * multiplying by zero otherwise. 3562 */ 3563 case MSR_EBC_FREQUENCY_ID: 3564 msr_info->data = 1 << 24; 3565 break; 3566 case MSR_IA32_APICBASE: 3567 msr_info->data = kvm_get_apic_base(vcpu); 3568 break; 3569 case APIC_BASE_MSR ... APIC_BASE_MSR + 0xff: 3570 return kvm_x2apic_msr_read(vcpu, msr_info->index, &msr_info->data); 3571 case MSR_IA32_TSC_DEADLINE: 3572 msr_info->data = kvm_get_lapic_tscdeadline_msr(vcpu); 3573 break; 3574 case MSR_IA32_TSC_ADJUST: 3575 msr_info->data = (u64)vcpu->arch.ia32_tsc_adjust_msr; 3576 break; 3577 case MSR_IA32_MISC_ENABLE: 3578 msr_info->data = vcpu->arch.ia32_misc_enable_msr; 3579 break; 3580 case MSR_IA32_SMBASE: 3581 if (!msr_info->host_initiated) 3582 return 1; 3583 msr_info->data = vcpu->arch.smbase; 3584 break; 3585 case MSR_SMI_COUNT: 3586 msr_info->data = vcpu->arch.smi_count; 3587 break; 3588 case MSR_IA32_PERF_STATUS: 3589 /* TSC increment by tick */ 3590 msr_info->data = 1000ULL; 3591 /* CPU multiplier */ 3592 msr_info->data |= (((uint64_t)4ULL) << 40); 3593 break; 3594 case MSR_EFER: 3595 msr_info->data = vcpu->arch.efer; 3596 break; 3597 case MSR_KVM_WALL_CLOCK: 3598 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE)) 3599 return 1; 3600 3601 msr_info->data = vcpu->kvm->arch.wall_clock; 3602 break; 3603 case MSR_KVM_WALL_CLOCK_NEW: 3604 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE2)) 3605 return 1; 3606 3607 msr_info->data = vcpu->kvm->arch.wall_clock; 3608 break; 3609 case MSR_KVM_SYSTEM_TIME: 3610 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE)) 3611 return 1; 3612 3613 msr_info->data = vcpu->arch.time; 3614 break; 3615 case MSR_KVM_SYSTEM_TIME_NEW: 3616 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE2)) 3617 return 1; 3618 3619 msr_info->data = vcpu->arch.time; 3620 break; 3621 case MSR_KVM_ASYNC_PF_EN: 3622 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF)) 3623 return 1; 3624 3625 msr_info->data = vcpu->arch.apf.msr_en_val; 3626 break; 3627 case MSR_KVM_ASYNC_PF_INT: 3628 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_INT)) 3629 return 1; 3630 3631 msr_info->data = vcpu->arch.apf.msr_int_val; 3632 break; 3633 case MSR_KVM_ASYNC_PF_ACK: 3634 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF)) 3635 return 1; 3636 3637 msr_info->data = 0; 3638 break; 3639 case MSR_KVM_STEAL_TIME: 3640 if (!guest_pv_has(vcpu, KVM_FEATURE_STEAL_TIME)) 3641 return 1; 3642 3643 msr_info->data = vcpu->arch.st.msr_val; 3644 break; 3645 case MSR_KVM_PV_EOI_EN: 3646 if (!guest_pv_has(vcpu, KVM_FEATURE_PV_EOI)) 3647 return 1; 3648 3649 msr_info->data = vcpu->arch.pv_eoi.msr_val; 3650 break; 3651 case MSR_KVM_POLL_CONTROL: 3652 if (!guest_pv_has(vcpu, KVM_FEATURE_POLL_CONTROL)) 3653 return 1; 3654 3655 msr_info->data = vcpu->arch.msr_kvm_poll_control; 3656 break; 3657 case MSR_IA32_P5_MC_ADDR: 3658 case MSR_IA32_P5_MC_TYPE: 3659 case MSR_IA32_MCG_CAP: 3660 case MSR_IA32_MCG_CTL: 3661 case MSR_IA32_MCG_STATUS: 3662 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1: 3663 return get_msr_mce(vcpu, msr_info->index, &msr_info->data, 3664 msr_info->host_initiated); 3665 case MSR_IA32_XSS: 3666 if (!msr_info->host_initiated && 3667 !guest_cpuid_has(vcpu, X86_FEATURE_XSAVES)) 3668 return 1; 3669 msr_info->data = vcpu->arch.ia32_xss; 3670 break; 3671 case MSR_K7_CLK_CTL: 3672 /* 3673 * Provide expected ramp-up count for K7. All other 3674 * are set to zero, indicating minimum divisors for 3675 * every field. 3676 * 3677 * This prevents guest kernels on AMD host with CPU 3678 * type 6, model 8 and higher from exploding due to 3679 * the rdmsr failing. 3680 */ 3681 msr_info->data = 0x20000000; 3682 break; 3683 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15: 3684 case HV_X64_MSR_SYNDBG_CONTROL ... HV_X64_MSR_SYNDBG_PENDING_BUFFER: 3685 case HV_X64_MSR_SYNDBG_OPTIONS: 3686 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4: 3687 case HV_X64_MSR_CRASH_CTL: 3688 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT: 3689 case HV_X64_MSR_REENLIGHTENMENT_CONTROL: 3690 case HV_X64_MSR_TSC_EMULATION_CONTROL: 3691 case HV_X64_MSR_TSC_EMULATION_STATUS: 3692 return kvm_hv_get_msr_common(vcpu, 3693 msr_info->index, &msr_info->data, 3694 msr_info->host_initiated); 3695 case MSR_IA32_BBL_CR_CTL3: 3696 /* This legacy MSR exists but isn't fully documented in current 3697 * silicon. It is however accessed by winxp in very narrow 3698 * scenarios where it sets bit #19, itself documented as 3699 * a "reserved" bit. Best effort attempt to source coherent 3700 * read data here should the balance of the register be 3701 * interpreted by the guest: 3702 * 3703 * L2 cache control register 3: 64GB range, 256KB size, 3704 * enabled, latency 0x1, configured 3705 */ 3706 msr_info->data = 0xbe702111; 3707 break; 3708 case MSR_AMD64_OSVW_ID_LENGTH: 3709 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW)) 3710 return 1; 3711 msr_info->data = vcpu->arch.osvw.length; 3712 break; 3713 case MSR_AMD64_OSVW_STATUS: 3714 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW)) 3715 return 1; 3716 msr_info->data = vcpu->arch.osvw.status; 3717 break; 3718 case MSR_PLATFORM_INFO: 3719 if (!msr_info->host_initiated && 3720 !vcpu->kvm->arch.guest_can_read_msr_platform_info) 3721 return 1; 3722 msr_info->data = vcpu->arch.msr_platform_info; 3723 break; 3724 case MSR_MISC_FEATURES_ENABLES: 3725 msr_info->data = vcpu->arch.msr_misc_features_enables; 3726 break; 3727 case MSR_K7_HWCR: 3728 msr_info->data = vcpu->arch.msr_hwcr; 3729 break; 3730 default: 3731 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index)) 3732 return kvm_pmu_get_msr(vcpu, msr_info); 3733 return KVM_MSR_RET_INVALID; 3734 } 3735 return 0; 3736 } 3737 EXPORT_SYMBOL_GPL(kvm_get_msr_common); 3738 3739 /* 3740 * Read or write a bunch of msrs. All parameters are kernel addresses. 3741 * 3742 * @return number of msrs set successfully. 3743 */ 3744 static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs, 3745 struct kvm_msr_entry *entries, 3746 int (*do_msr)(struct kvm_vcpu *vcpu, 3747 unsigned index, u64 *data)) 3748 { 3749 int i; 3750 3751 for (i = 0; i < msrs->nmsrs; ++i) 3752 if (do_msr(vcpu, entries[i].index, &entries[i].data)) 3753 break; 3754 3755 return i; 3756 } 3757 3758 /* 3759 * Read or write a bunch of msrs. Parameters are user addresses. 3760 * 3761 * @return number of msrs set successfully. 3762 */ 3763 static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs, 3764 int (*do_msr)(struct kvm_vcpu *vcpu, 3765 unsigned index, u64 *data), 3766 int writeback) 3767 { 3768 struct kvm_msrs msrs; 3769 struct kvm_msr_entry *entries; 3770 int r, n; 3771 unsigned size; 3772 3773 r = -EFAULT; 3774 if (copy_from_user(&msrs, user_msrs, sizeof(msrs))) 3775 goto out; 3776 3777 r = -E2BIG; 3778 if (msrs.nmsrs >= MAX_IO_MSRS) 3779 goto out; 3780 3781 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs; 3782 entries = memdup_user(user_msrs->entries, size); 3783 if (IS_ERR(entries)) { 3784 r = PTR_ERR(entries); 3785 goto out; 3786 } 3787 3788 r = n = __msr_io(vcpu, &msrs, entries, do_msr); 3789 if (r < 0) 3790 goto out_free; 3791 3792 r = -EFAULT; 3793 if (writeback && copy_to_user(user_msrs->entries, entries, size)) 3794 goto out_free; 3795 3796 r = n; 3797 3798 out_free: 3799 kfree(entries); 3800 out: 3801 return r; 3802 } 3803 3804 static inline bool kvm_can_mwait_in_guest(void) 3805 { 3806 return boot_cpu_has(X86_FEATURE_MWAIT) && 3807 !boot_cpu_has_bug(X86_BUG_MONITOR) && 3808 boot_cpu_has(X86_FEATURE_ARAT); 3809 } 3810 3811 static int kvm_ioctl_get_supported_hv_cpuid(struct kvm_vcpu *vcpu, 3812 struct kvm_cpuid2 __user *cpuid_arg) 3813 { 3814 struct kvm_cpuid2 cpuid; 3815 int r; 3816 3817 r = -EFAULT; 3818 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid))) 3819 return r; 3820 3821 r = kvm_get_hv_cpuid(vcpu, &cpuid, cpuid_arg->entries); 3822 if (r) 3823 return r; 3824 3825 r = -EFAULT; 3826 if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid))) 3827 return r; 3828 3829 return 0; 3830 } 3831 3832 int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext) 3833 { 3834 int r = 0; 3835 3836 switch (ext) { 3837 case KVM_CAP_IRQCHIP: 3838 case KVM_CAP_HLT: 3839 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL: 3840 case KVM_CAP_SET_TSS_ADDR: 3841 case KVM_CAP_EXT_CPUID: 3842 case KVM_CAP_EXT_EMUL_CPUID: 3843 case KVM_CAP_CLOCKSOURCE: 3844 case KVM_CAP_PIT: 3845 case KVM_CAP_NOP_IO_DELAY: 3846 case KVM_CAP_MP_STATE: 3847 case KVM_CAP_SYNC_MMU: 3848 case KVM_CAP_USER_NMI: 3849 case KVM_CAP_REINJECT_CONTROL: 3850 case KVM_CAP_IRQ_INJECT_STATUS: 3851 case KVM_CAP_IOEVENTFD: 3852 case KVM_CAP_IOEVENTFD_NO_LENGTH: 3853 case KVM_CAP_PIT2: 3854 case KVM_CAP_PIT_STATE2: 3855 case KVM_CAP_SET_IDENTITY_MAP_ADDR: 3856 case KVM_CAP_VCPU_EVENTS: 3857 case KVM_CAP_HYPERV: 3858 case KVM_CAP_HYPERV_VAPIC: 3859 case KVM_CAP_HYPERV_SPIN: 3860 case KVM_CAP_HYPERV_SYNIC: 3861 case KVM_CAP_HYPERV_SYNIC2: 3862 case KVM_CAP_HYPERV_VP_INDEX: 3863 case KVM_CAP_HYPERV_EVENTFD: 3864 case KVM_CAP_HYPERV_TLBFLUSH: 3865 case KVM_CAP_HYPERV_SEND_IPI: 3866 case KVM_CAP_HYPERV_CPUID: 3867 case KVM_CAP_SYS_HYPERV_CPUID: 3868 case KVM_CAP_PCI_SEGMENT: 3869 case KVM_CAP_DEBUGREGS: 3870 case KVM_CAP_X86_ROBUST_SINGLESTEP: 3871 case KVM_CAP_XSAVE: 3872 case KVM_CAP_ASYNC_PF: 3873 case KVM_CAP_ASYNC_PF_INT: 3874 case KVM_CAP_GET_TSC_KHZ: 3875 case KVM_CAP_KVMCLOCK_CTRL: 3876 case KVM_CAP_READONLY_MEM: 3877 case KVM_CAP_HYPERV_TIME: 3878 case KVM_CAP_IOAPIC_POLARITY_IGNORED: 3879 case KVM_CAP_TSC_DEADLINE_TIMER: 3880 case KVM_CAP_DISABLE_QUIRKS: 3881 case KVM_CAP_SET_BOOT_CPU_ID: 3882 case KVM_CAP_SPLIT_IRQCHIP: 3883 case KVM_CAP_IMMEDIATE_EXIT: 3884 case KVM_CAP_PMU_EVENT_FILTER: 3885 case KVM_CAP_GET_MSR_FEATURES: 3886 case KVM_CAP_MSR_PLATFORM_INFO: 3887 case KVM_CAP_EXCEPTION_PAYLOAD: 3888 case KVM_CAP_SET_GUEST_DEBUG: 3889 case KVM_CAP_LAST_CPU: 3890 case KVM_CAP_X86_USER_SPACE_MSR: 3891 case KVM_CAP_X86_MSR_FILTER: 3892 case KVM_CAP_ENFORCE_PV_FEATURE_CPUID: 3893 #ifdef CONFIG_X86_SGX_KVM 3894 case KVM_CAP_SGX_ATTRIBUTE: 3895 #endif 3896 case KVM_CAP_VM_COPY_ENC_CONTEXT_FROM: 3897 r = 1; 3898 break; 3899 case KVM_CAP_SET_GUEST_DEBUG2: 3900 return KVM_GUESTDBG_VALID_MASK; 3901 #ifdef CONFIG_KVM_XEN 3902 case KVM_CAP_XEN_HVM: 3903 r = KVM_XEN_HVM_CONFIG_HYPERCALL_MSR | 3904 KVM_XEN_HVM_CONFIG_INTERCEPT_HCALL | 3905 KVM_XEN_HVM_CONFIG_SHARED_INFO; 3906 if (sched_info_on()) 3907 r |= KVM_XEN_HVM_CONFIG_RUNSTATE; 3908 break; 3909 #endif 3910 case KVM_CAP_SYNC_REGS: 3911 r = KVM_SYNC_X86_VALID_FIELDS; 3912 break; 3913 case KVM_CAP_ADJUST_CLOCK: 3914 r = KVM_CLOCK_TSC_STABLE; 3915 break; 3916 case KVM_CAP_X86_DISABLE_EXITS: 3917 r |= KVM_X86_DISABLE_EXITS_HLT | KVM_X86_DISABLE_EXITS_PAUSE | 3918 KVM_X86_DISABLE_EXITS_CSTATE; 3919 if(kvm_can_mwait_in_guest()) 3920 r |= KVM_X86_DISABLE_EXITS_MWAIT; 3921 break; 3922 case KVM_CAP_X86_SMM: 3923 /* SMBASE is usually relocated above 1M on modern chipsets, 3924 * and SMM handlers might indeed rely on 4G segment limits, 3925 * so do not report SMM to be available if real mode is 3926 * emulated via vm86 mode. Still, do not go to great lengths 3927 * to avoid userspace's usage of the feature, because it is a 3928 * fringe case that is not enabled except via specific settings 3929 * of the module parameters. 3930 */ 3931 r = static_call(kvm_x86_has_emulated_msr)(kvm, MSR_IA32_SMBASE); 3932 break; 3933 case KVM_CAP_VAPIC: 3934 r = !static_call(kvm_x86_cpu_has_accelerated_tpr)(); 3935 break; 3936 case KVM_CAP_NR_VCPUS: 3937 r = KVM_SOFT_MAX_VCPUS; 3938 break; 3939 case KVM_CAP_MAX_VCPUS: 3940 r = KVM_MAX_VCPUS; 3941 break; 3942 case KVM_CAP_MAX_VCPU_ID: 3943 r = KVM_MAX_VCPU_ID; 3944 break; 3945 case KVM_CAP_PV_MMU: /* obsolete */ 3946 r = 0; 3947 break; 3948 case KVM_CAP_MCE: 3949 r = KVM_MAX_MCE_BANKS; 3950 break; 3951 case KVM_CAP_XCRS: 3952 r = boot_cpu_has(X86_FEATURE_XSAVE); 3953 break; 3954 case KVM_CAP_TSC_CONTROL: 3955 r = kvm_has_tsc_control; 3956 break; 3957 case KVM_CAP_X2APIC_API: 3958 r = KVM_X2APIC_API_VALID_FLAGS; 3959 break; 3960 case KVM_CAP_NESTED_STATE: 3961 r = kvm_x86_ops.nested_ops->get_state ? 3962 kvm_x86_ops.nested_ops->get_state(NULL, NULL, 0) : 0; 3963 break; 3964 case KVM_CAP_HYPERV_DIRECT_TLBFLUSH: 3965 r = kvm_x86_ops.enable_direct_tlbflush != NULL; 3966 break; 3967 case KVM_CAP_HYPERV_ENLIGHTENED_VMCS: 3968 r = kvm_x86_ops.nested_ops->enable_evmcs != NULL; 3969 break; 3970 case KVM_CAP_SMALLER_MAXPHYADDR: 3971 r = (int) allow_smaller_maxphyaddr; 3972 break; 3973 case KVM_CAP_STEAL_TIME: 3974 r = sched_info_on(); 3975 break; 3976 case KVM_CAP_X86_BUS_LOCK_EXIT: 3977 if (kvm_has_bus_lock_exit) 3978 r = KVM_BUS_LOCK_DETECTION_OFF | 3979 KVM_BUS_LOCK_DETECTION_EXIT; 3980 else 3981 r = 0; 3982 break; 3983 default: 3984 break; 3985 } 3986 return r; 3987 3988 } 3989 3990 long kvm_arch_dev_ioctl(struct file *filp, 3991 unsigned int ioctl, unsigned long arg) 3992 { 3993 void __user *argp = (void __user *)arg; 3994 long r; 3995 3996 switch (ioctl) { 3997 case KVM_GET_MSR_INDEX_LIST: { 3998 struct kvm_msr_list __user *user_msr_list = argp; 3999 struct kvm_msr_list msr_list; 4000 unsigned n; 4001 4002 r = -EFAULT; 4003 if (copy_from_user(&msr_list, user_msr_list, sizeof(msr_list))) 4004 goto out; 4005 n = msr_list.nmsrs; 4006 msr_list.nmsrs = num_msrs_to_save + num_emulated_msrs; 4007 if (copy_to_user(user_msr_list, &msr_list, sizeof(msr_list))) 4008 goto out; 4009 r = -E2BIG; 4010 if (n < msr_list.nmsrs) 4011 goto out; 4012 r = -EFAULT; 4013 if (copy_to_user(user_msr_list->indices, &msrs_to_save, 4014 num_msrs_to_save * sizeof(u32))) 4015 goto out; 4016 if (copy_to_user(user_msr_list->indices + num_msrs_to_save, 4017 &emulated_msrs, 4018 num_emulated_msrs * sizeof(u32))) 4019 goto out; 4020 r = 0; 4021 break; 4022 } 4023 case KVM_GET_SUPPORTED_CPUID: 4024 case KVM_GET_EMULATED_CPUID: { 4025 struct kvm_cpuid2 __user *cpuid_arg = argp; 4026 struct kvm_cpuid2 cpuid; 4027 4028 r = -EFAULT; 4029 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid))) 4030 goto out; 4031 4032 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries, 4033 ioctl); 4034 if (r) 4035 goto out; 4036 4037 r = -EFAULT; 4038 if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid))) 4039 goto out; 4040 r = 0; 4041 break; 4042 } 4043 case KVM_X86_GET_MCE_CAP_SUPPORTED: 4044 r = -EFAULT; 4045 if (copy_to_user(argp, &kvm_mce_cap_supported, 4046 sizeof(kvm_mce_cap_supported))) 4047 goto out; 4048 r = 0; 4049 break; 4050 case KVM_GET_MSR_FEATURE_INDEX_LIST: { 4051 struct kvm_msr_list __user *user_msr_list = argp; 4052 struct kvm_msr_list msr_list; 4053 unsigned int n; 4054 4055 r = -EFAULT; 4056 if (copy_from_user(&msr_list, user_msr_list, sizeof(msr_list))) 4057 goto out; 4058 n = msr_list.nmsrs; 4059 msr_list.nmsrs = num_msr_based_features; 4060 if (copy_to_user(user_msr_list, &msr_list, sizeof(msr_list))) 4061 goto out; 4062 r = -E2BIG; 4063 if (n < msr_list.nmsrs) 4064 goto out; 4065 r = -EFAULT; 4066 if (copy_to_user(user_msr_list->indices, &msr_based_features, 4067 num_msr_based_features * sizeof(u32))) 4068 goto out; 4069 r = 0; 4070 break; 4071 } 4072 case KVM_GET_MSRS: 4073 r = msr_io(NULL, argp, do_get_msr_feature, 1); 4074 break; 4075 case KVM_GET_SUPPORTED_HV_CPUID: 4076 r = kvm_ioctl_get_supported_hv_cpuid(NULL, argp); 4077 break; 4078 default: 4079 r = -EINVAL; 4080 break; 4081 } 4082 out: 4083 return r; 4084 } 4085 4086 static void wbinvd_ipi(void *garbage) 4087 { 4088 wbinvd(); 4089 } 4090 4091 static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu) 4092 { 4093 return kvm_arch_has_noncoherent_dma(vcpu->kvm); 4094 } 4095 4096 void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu) 4097 { 4098 /* Address WBINVD may be executed by guest */ 4099 if (need_emulate_wbinvd(vcpu)) { 4100 if (static_call(kvm_x86_has_wbinvd_exit)()) 4101 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask); 4102 else if (vcpu->cpu != -1 && vcpu->cpu != cpu) 4103 smp_call_function_single(vcpu->cpu, 4104 wbinvd_ipi, NULL, 1); 4105 } 4106 4107 static_call(kvm_x86_vcpu_load)(vcpu, cpu); 4108 4109 /* Save host pkru register if supported */ 4110 vcpu->arch.host_pkru = read_pkru(); 4111 4112 /* Apply any externally detected TSC adjustments (due to suspend) */ 4113 if (unlikely(vcpu->arch.tsc_offset_adjustment)) { 4114 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment); 4115 vcpu->arch.tsc_offset_adjustment = 0; 4116 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 4117 } 4118 4119 if (unlikely(vcpu->cpu != cpu) || kvm_check_tsc_unstable()) { 4120 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 : 4121 rdtsc() - vcpu->arch.last_host_tsc; 4122 if (tsc_delta < 0) 4123 mark_tsc_unstable("KVM discovered backwards TSC"); 4124 4125 if (kvm_check_tsc_unstable()) { 4126 u64 offset = kvm_compute_tsc_offset(vcpu, 4127 vcpu->arch.last_guest_tsc); 4128 kvm_vcpu_write_tsc_offset(vcpu, offset); 4129 vcpu->arch.tsc_catchup = 1; 4130 } 4131 4132 if (kvm_lapic_hv_timer_in_use(vcpu)) 4133 kvm_lapic_restart_hv_timer(vcpu); 4134 4135 /* 4136 * On a host with synchronized TSC, there is no need to update 4137 * kvmclock on vcpu->cpu migration 4138 */ 4139 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1) 4140 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu); 4141 if (vcpu->cpu != cpu) 4142 kvm_make_request(KVM_REQ_MIGRATE_TIMER, vcpu); 4143 vcpu->cpu = cpu; 4144 } 4145 4146 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu); 4147 } 4148 4149 static void kvm_steal_time_set_preempted(struct kvm_vcpu *vcpu) 4150 { 4151 struct kvm_host_map map; 4152 struct kvm_steal_time *st; 4153 4154 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED)) 4155 return; 4156 4157 if (vcpu->arch.st.preempted) 4158 return; 4159 4160 if (kvm_map_gfn(vcpu, vcpu->arch.st.msr_val >> PAGE_SHIFT, &map, 4161 &vcpu->arch.st.cache, true)) 4162 return; 4163 4164 st = map.hva + 4165 offset_in_page(vcpu->arch.st.msr_val & KVM_STEAL_VALID_BITS); 4166 4167 st->preempted = vcpu->arch.st.preempted = KVM_VCPU_PREEMPTED; 4168 4169 kvm_unmap_gfn(vcpu, &map, &vcpu->arch.st.cache, true, true); 4170 } 4171 4172 void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu) 4173 { 4174 int idx; 4175 4176 if (vcpu->preempted && !vcpu->arch.guest_state_protected) 4177 vcpu->arch.preempted_in_kernel = !static_call(kvm_x86_get_cpl)(vcpu); 4178 4179 /* 4180 * Take the srcu lock as memslots will be accessed to check the gfn 4181 * cache generation against the memslots generation. 4182 */ 4183 idx = srcu_read_lock(&vcpu->kvm->srcu); 4184 if (kvm_xen_msr_enabled(vcpu->kvm)) 4185 kvm_xen_runstate_set_preempted(vcpu); 4186 else 4187 kvm_steal_time_set_preempted(vcpu); 4188 srcu_read_unlock(&vcpu->kvm->srcu, idx); 4189 4190 static_call(kvm_x86_vcpu_put)(vcpu); 4191 vcpu->arch.last_host_tsc = rdtsc(); 4192 /* 4193 * If userspace has set any breakpoints or watchpoints, dr6 is restored 4194 * on every vmexit, but if not, we might have a stale dr6 from the 4195 * guest. do_debug expects dr6 to be cleared after it runs, do the same. 4196 */ 4197 set_debugreg(0, 6); 4198 } 4199 4200 static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu, 4201 struct kvm_lapic_state *s) 4202 { 4203 if (vcpu->arch.apicv_active) 4204 static_call(kvm_x86_sync_pir_to_irr)(vcpu); 4205 4206 return kvm_apic_get_state(vcpu, s); 4207 } 4208 4209 static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu, 4210 struct kvm_lapic_state *s) 4211 { 4212 int r; 4213 4214 r = kvm_apic_set_state(vcpu, s); 4215 if (r) 4216 return r; 4217 update_cr8_intercept(vcpu); 4218 4219 return 0; 4220 } 4221 4222 static int kvm_cpu_accept_dm_intr(struct kvm_vcpu *vcpu) 4223 { 4224 /* 4225 * We can accept userspace's request for interrupt injection 4226 * as long as we have a place to store the interrupt number. 4227 * The actual injection will happen when the CPU is able to 4228 * deliver the interrupt. 4229 */ 4230 if (kvm_cpu_has_extint(vcpu)) 4231 return false; 4232 4233 /* Acknowledging ExtINT does not happen if LINT0 is masked. */ 4234 return (!lapic_in_kernel(vcpu) || 4235 kvm_apic_accept_pic_intr(vcpu)); 4236 } 4237 4238 static int kvm_vcpu_ready_for_interrupt_injection(struct kvm_vcpu *vcpu) 4239 { 4240 return kvm_arch_interrupt_allowed(vcpu) && 4241 kvm_cpu_accept_dm_intr(vcpu); 4242 } 4243 4244 static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu, 4245 struct kvm_interrupt *irq) 4246 { 4247 if (irq->irq >= KVM_NR_INTERRUPTS) 4248 return -EINVAL; 4249 4250 if (!irqchip_in_kernel(vcpu->kvm)) { 4251 kvm_queue_interrupt(vcpu, irq->irq, false); 4252 kvm_make_request(KVM_REQ_EVENT, vcpu); 4253 return 0; 4254 } 4255 4256 /* 4257 * With in-kernel LAPIC, we only use this to inject EXTINT, so 4258 * fail for in-kernel 8259. 4259 */ 4260 if (pic_in_kernel(vcpu->kvm)) 4261 return -ENXIO; 4262 4263 if (vcpu->arch.pending_external_vector != -1) 4264 return -EEXIST; 4265 4266 vcpu->arch.pending_external_vector = irq->irq; 4267 kvm_make_request(KVM_REQ_EVENT, vcpu); 4268 return 0; 4269 } 4270 4271 static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu) 4272 { 4273 kvm_inject_nmi(vcpu); 4274 4275 return 0; 4276 } 4277 4278 static int kvm_vcpu_ioctl_smi(struct kvm_vcpu *vcpu) 4279 { 4280 kvm_make_request(KVM_REQ_SMI, vcpu); 4281 4282 return 0; 4283 } 4284 4285 static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu, 4286 struct kvm_tpr_access_ctl *tac) 4287 { 4288 if (tac->flags) 4289 return -EINVAL; 4290 vcpu->arch.tpr_access_reporting = !!tac->enabled; 4291 return 0; 4292 } 4293 4294 static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu, 4295 u64 mcg_cap) 4296 { 4297 int r; 4298 unsigned bank_num = mcg_cap & 0xff, bank; 4299 4300 r = -EINVAL; 4301 if (!bank_num || bank_num > KVM_MAX_MCE_BANKS) 4302 goto out; 4303 if (mcg_cap & ~(kvm_mce_cap_supported | 0xff | 0xff0000)) 4304 goto out; 4305 r = 0; 4306 vcpu->arch.mcg_cap = mcg_cap; 4307 /* Init IA32_MCG_CTL to all 1s */ 4308 if (mcg_cap & MCG_CTL_P) 4309 vcpu->arch.mcg_ctl = ~(u64)0; 4310 /* Init IA32_MCi_CTL to all 1s */ 4311 for (bank = 0; bank < bank_num; bank++) 4312 vcpu->arch.mce_banks[bank*4] = ~(u64)0; 4313 4314 static_call(kvm_x86_setup_mce)(vcpu); 4315 out: 4316 return r; 4317 } 4318 4319 static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu, 4320 struct kvm_x86_mce *mce) 4321 { 4322 u64 mcg_cap = vcpu->arch.mcg_cap; 4323 unsigned bank_num = mcg_cap & 0xff; 4324 u64 *banks = vcpu->arch.mce_banks; 4325 4326 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL)) 4327 return -EINVAL; 4328 /* 4329 * if IA32_MCG_CTL is not all 1s, the uncorrected error 4330 * reporting is disabled 4331 */ 4332 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) && 4333 vcpu->arch.mcg_ctl != ~(u64)0) 4334 return 0; 4335 banks += 4 * mce->bank; 4336 /* 4337 * if IA32_MCi_CTL is not all 1s, the uncorrected error 4338 * reporting is disabled for the bank 4339 */ 4340 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0) 4341 return 0; 4342 if (mce->status & MCI_STATUS_UC) { 4343 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) || 4344 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) { 4345 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); 4346 return 0; 4347 } 4348 if (banks[1] & MCI_STATUS_VAL) 4349 mce->status |= MCI_STATUS_OVER; 4350 banks[2] = mce->addr; 4351 banks[3] = mce->misc; 4352 vcpu->arch.mcg_status = mce->mcg_status; 4353 banks[1] = mce->status; 4354 kvm_queue_exception(vcpu, MC_VECTOR); 4355 } else if (!(banks[1] & MCI_STATUS_VAL) 4356 || !(banks[1] & MCI_STATUS_UC)) { 4357 if (banks[1] & MCI_STATUS_VAL) 4358 mce->status |= MCI_STATUS_OVER; 4359 banks[2] = mce->addr; 4360 banks[3] = mce->misc; 4361 banks[1] = mce->status; 4362 } else 4363 banks[1] |= MCI_STATUS_OVER; 4364 return 0; 4365 } 4366 4367 static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu, 4368 struct kvm_vcpu_events *events) 4369 { 4370 process_nmi(vcpu); 4371 4372 if (kvm_check_request(KVM_REQ_SMI, vcpu)) 4373 process_smi(vcpu); 4374 4375 /* 4376 * In guest mode, payload delivery should be deferred, 4377 * so that the L1 hypervisor can intercept #PF before 4378 * CR2 is modified (or intercept #DB before DR6 is 4379 * modified under nVMX). Unless the per-VM capability, 4380 * KVM_CAP_EXCEPTION_PAYLOAD, is set, we may not defer the delivery of 4381 * an exception payload and handle after a KVM_GET_VCPU_EVENTS. Since we 4382 * opportunistically defer the exception payload, deliver it if the 4383 * capability hasn't been requested before processing a 4384 * KVM_GET_VCPU_EVENTS. 4385 */ 4386 if (!vcpu->kvm->arch.exception_payload_enabled && 4387 vcpu->arch.exception.pending && vcpu->arch.exception.has_payload) 4388 kvm_deliver_exception_payload(vcpu); 4389 4390 /* 4391 * The API doesn't provide the instruction length for software 4392 * exceptions, so don't report them. As long as the guest RIP 4393 * isn't advanced, we should expect to encounter the exception 4394 * again. 4395 */ 4396 if (kvm_exception_is_soft(vcpu->arch.exception.nr)) { 4397 events->exception.injected = 0; 4398 events->exception.pending = 0; 4399 } else { 4400 events->exception.injected = vcpu->arch.exception.injected; 4401 events->exception.pending = vcpu->arch.exception.pending; 4402 /* 4403 * For ABI compatibility, deliberately conflate 4404 * pending and injected exceptions when 4405 * KVM_CAP_EXCEPTION_PAYLOAD isn't enabled. 4406 */ 4407 if (!vcpu->kvm->arch.exception_payload_enabled) 4408 events->exception.injected |= 4409 vcpu->arch.exception.pending; 4410 } 4411 events->exception.nr = vcpu->arch.exception.nr; 4412 events->exception.has_error_code = vcpu->arch.exception.has_error_code; 4413 events->exception.error_code = vcpu->arch.exception.error_code; 4414 events->exception_has_payload = vcpu->arch.exception.has_payload; 4415 events->exception_payload = vcpu->arch.exception.payload; 4416 4417 events->interrupt.injected = 4418 vcpu->arch.interrupt.injected && !vcpu->arch.interrupt.soft; 4419 events->interrupt.nr = vcpu->arch.interrupt.nr; 4420 events->interrupt.soft = 0; 4421 events->interrupt.shadow = static_call(kvm_x86_get_interrupt_shadow)(vcpu); 4422 4423 events->nmi.injected = vcpu->arch.nmi_injected; 4424 events->nmi.pending = vcpu->arch.nmi_pending != 0; 4425 events->nmi.masked = static_call(kvm_x86_get_nmi_mask)(vcpu); 4426 events->nmi.pad = 0; 4427 4428 events->sipi_vector = 0; /* never valid when reporting to user space */ 4429 4430 events->smi.smm = is_smm(vcpu); 4431 events->smi.pending = vcpu->arch.smi_pending; 4432 events->smi.smm_inside_nmi = 4433 !!(vcpu->arch.hflags & HF_SMM_INSIDE_NMI_MASK); 4434 events->smi.latched_init = kvm_lapic_latched_init(vcpu); 4435 4436 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING 4437 | KVM_VCPUEVENT_VALID_SHADOW 4438 | KVM_VCPUEVENT_VALID_SMM); 4439 if (vcpu->kvm->arch.exception_payload_enabled) 4440 events->flags |= KVM_VCPUEVENT_VALID_PAYLOAD; 4441 4442 memset(&events->reserved, 0, sizeof(events->reserved)); 4443 } 4444 4445 static void kvm_smm_changed(struct kvm_vcpu *vcpu); 4446 4447 static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu, 4448 struct kvm_vcpu_events *events) 4449 { 4450 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING 4451 | KVM_VCPUEVENT_VALID_SIPI_VECTOR 4452 | KVM_VCPUEVENT_VALID_SHADOW 4453 | KVM_VCPUEVENT_VALID_SMM 4454 | KVM_VCPUEVENT_VALID_PAYLOAD)) 4455 return -EINVAL; 4456 4457 if (events->flags & KVM_VCPUEVENT_VALID_PAYLOAD) { 4458 if (!vcpu->kvm->arch.exception_payload_enabled) 4459 return -EINVAL; 4460 if (events->exception.pending) 4461 events->exception.injected = 0; 4462 else 4463 events->exception_has_payload = 0; 4464 } else { 4465 events->exception.pending = 0; 4466 events->exception_has_payload = 0; 4467 } 4468 4469 if ((events->exception.injected || events->exception.pending) && 4470 (events->exception.nr > 31 || events->exception.nr == NMI_VECTOR)) 4471 return -EINVAL; 4472 4473 /* INITs are latched while in SMM */ 4474 if (events->flags & KVM_VCPUEVENT_VALID_SMM && 4475 (events->smi.smm || events->smi.pending) && 4476 vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) 4477 return -EINVAL; 4478 4479 process_nmi(vcpu); 4480 vcpu->arch.exception.injected = events->exception.injected; 4481 vcpu->arch.exception.pending = events->exception.pending; 4482 vcpu->arch.exception.nr = events->exception.nr; 4483 vcpu->arch.exception.has_error_code = events->exception.has_error_code; 4484 vcpu->arch.exception.error_code = events->exception.error_code; 4485 vcpu->arch.exception.has_payload = events->exception_has_payload; 4486 vcpu->arch.exception.payload = events->exception_payload; 4487 4488 vcpu->arch.interrupt.injected = events->interrupt.injected; 4489 vcpu->arch.interrupt.nr = events->interrupt.nr; 4490 vcpu->arch.interrupt.soft = events->interrupt.soft; 4491 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW) 4492 static_call(kvm_x86_set_interrupt_shadow)(vcpu, 4493 events->interrupt.shadow); 4494 4495 vcpu->arch.nmi_injected = events->nmi.injected; 4496 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING) 4497 vcpu->arch.nmi_pending = events->nmi.pending; 4498 static_call(kvm_x86_set_nmi_mask)(vcpu, events->nmi.masked); 4499 4500 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR && 4501 lapic_in_kernel(vcpu)) 4502 vcpu->arch.apic->sipi_vector = events->sipi_vector; 4503 4504 if (events->flags & KVM_VCPUEVENT_VALID_SMM) { 4505 if (!!(vcpu->arch.hflags & HF_SMM_MASK) != events->smi.smm) { 4506 if (events->smi.smm) 4507 vcpu->arch.hflags |= HF_SMM_MASK; 4508 else 4509 vcpu->arch.hflags &= ~HF_SMM_MASK; 4510 kvm_smm_changed(vcpu); 4511 } 4512 4513 vcpu->arch.smi_pending = events->smi.pending; 4514 4515 if (events->smi.smm) { 4516 if (events->smi.smm_inside_nmi) 4517 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK; 4518 else 4519 vcpu->arch.hflags &= ~HF_SMM_INSIDE_NMI_MASK; 4520 } 4521 4522 if (lapic_in_kernel(vcpu)) { 4523 if (events->smi.latched_init) 4524 set_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events); 4525 else 4526 clear_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events); 4527 } 4528 } 4529 4530 kvm_make_request(KVM_REQ_EVENT, vcpu); 4531 4532 return 0; 4533 } 4534 4535 static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu, 4536 struct kvm_debugregs *dbgregs) 4537 { 4538 unsigned long val; 4539 4540 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db)); 4541 kvm_get_dr(vcpu, 6, &val); 4542 dbgregs->dr6 = val; 4543 dbgregs->dr7 = vcpu->arch.dr7; 4544 dbgregs->flags = 0; 4545 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved)); 4546 } 4547 4548 static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu, 4549 struct kvm_debugregs *dbgregs) 4550 { 4551 if (dbgregs->flags) 4552 return -EINVAL; 4553 4554 if (!kvm_dr6_valid(dbgregs->dr6)) 4555 return -EINVAL; 4556 if (!kvm_dr7_valid(dbgregs->dr7)) 4557 return -EINVAL; 4558 4559 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db)); 4560 kvm_update_dr0123(vcpu); 4561 vcpu->arch.dr6 = dbgregs->dr6; 4562 vcpu->arch.dr7 = dbgregs->dr7; 4563 kvm_update_dr7(vcpu); 4564 4565 return 0; 4566 } 4567 4568 #define XSTATE_COMPACTION_ENABLED (1ULL << 63) 4569 4570 static void fill_xsave(u8 *dest, struct kvm_vcpu *vcpu) 4571 { 4572 struct xregs_state *xsave = &vcpu->arch.guest_fpu->state.xsave; 4573 u64 xstate_bv = xsave->header.xfeatures; 4574 u64 valid; 4575 4576 /* 4577 * Copy legacy XSAVE area, to avoid complications with CPUID 4578 * leaves 0 and 1 in the loop below. 4579 */ 4580 memcpy(dest, xsave, XSAVE_HDR_OFFSET); 4581 4582 /* Set XSTATE_BV */ 4583 xstate_bv &= vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FPSSE; 4584 *(u64 *)(dest + XSAVE_HDR_OFFSET) = xstate_bv; 4585 4586 /* 4587 * Copy each region from the possibly compacted offset to the 4588 * non-compacted offset. 4589 */ 4590 valid = xstate_bv & ~XFEATURE_MASK_FPSSE; 4591 while (valid) { 4592 u64 xfeature_mask = valid & -valid; 4593 int xfeature_nr = fls64(xfeature_mask) - 1; 4594 void *src = get_xsave_addr(xsave, xfeature_nr); 4595 4596 if (src) { 4597 u32 size, offset, ecx, edx; 4598 cpuid_count(XSTATE_CPUID, xfeature_nr, 4599 &size, &offset, &ecx, &edx); 4600 if (xfeature_nr == XFEATURE_PKRU) 4601 memcpy(dest + offset, &vcpu->arch.pkru, 4602 sizeof(vcpu->arch.pkru)); 4603 else 4604 memcpy(dest + offset, src, size); 4605 4606 } 4607 4608 valid -= xfeature_mask; 4609 } 4610 } 4611 4612 static void load_xsave(struct kvm_vcpu *vcpu, u8 *src) 4613 { 4614 struct xregs_state *xsave = &vcpu->arch.guest_fpu->state.xsave; 4615 u64 xstate_bv = *(u64 *)(src + XSAVE_HDR_OFFSET); 4616 u64 valid; 4617 4618 /* 4619 * Copy legacy XSAVE area, to avoid complications with CPUID 4620 * leaves 0 and 1 in the loop below. 4621 */ 4622 memcpy(xsave, src, XSAVE_HDR_OFFSET); 4623 4624 /* Set XSTATE_BV and possibly XCOMP_BV. */ 4625 xsave->header.xfeatures = xstate_bv; 4626 if (boot_cpu_has(X86_FEATURE_XSAVES)) 4627 xsave->header.xcomp_bv = host_xcr0 | XSTATE_COMPACTION_ENABLED; 4628 4629 /* 4630 * Copy each region from the non-compacted offset to the 4631 * possibly compacted offset. 4632 */ 4633 valid = xstate_bv & ~XFEATURE_MASK_FPSSE; 4634 while (valid) { 4635 u64 xfeature_mask = valid & -valid; 4636 int xfeature_nr = fls64(xfeature_mask) - 1; 4637 void *dest = get_xsave_addr(xsave, xfeature_nr); 4638 4639 if (dest) { 4640 u32 size, offset, ecx, edx; 4641 cpuid_count(XSTATE_CPUID, xfeature_nr, 4642 &size, &offset, &ecx, &edx); 4643 if (xfeature_nr == XFEATURE_PKRU) 4644 memcpy(&vcpu->arch.pkru, src + offset, 4645 sizeof(vcpu->arch.pkru)); 4646 else 4647 memcpy(dest, src + offset, size); 4648 } 4649 4650 valid -= xfeature_mask; 4651 } 4652 } 4653 4654 static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu, 4655 struct kvm_xsave *guest_xsave) 4656 { 4657 if (!vcpu->arch.guest_fpu) 4658 return; 4659 4660 if (boot_cpu_has(X86_FEATURE_XSAVE)) { 4661 memset(guest_xsave, 0, sizeof(struct kvm_xsave)); 4662 fill_xsave((u8 *) guest_xsave->region, vcpu); 4663 } else { 4664 memcpy(guest_xsave->region, 4665 &vcpu->arch.guest_fpu->state.fxsave, 4666 sizeof(struct fxregs_state)); 4667 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] = 4668 XFEATURE_MASK_FPSSE; 4669 } 4670 } 4671 4672 #define XSAVE_MXCSR_OFFSET 24 4673 4674 static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu, 4675 struct kvm_xsave *guest_xsave) 4676 { 4677 u64 xstate_bv; 4678 u32 mxcsr; 4679 4680 if (!vcpu->arch.guest_fpu) 4681 return 0; 4682 4683 xstate_bv = *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)]; 4684 mxcsr = *(u32 *)&guest_xsave->region[XSAVE_MXCSR_OFFSET / sizeof(u32)]; 4685 4686 if (boot_cpu_has(X86_FEATURE_XSAVE)) { 4687 /* 4688 * Here we allow setting states that are not present in 4689 * CPUID leaf 0xD, index 0, EDX:EAX. This is for compatibility 4690 * with old userspace. 4691 */ 4692 if (xstate_bv & ~supported_xcr0 || mxcsr & ~mxcsr_feature_mask) 4693 return -EINVAL; 4694 load_xsave(vcpu, (u8 *)guest_xsave->region); 4695 } else { 4696 if (xstate_bv & ~XFEATURE_MASK_FPSSE || 4697 mxcsr & ~mxcsr_feature_mask) 4698 return -EINVAL; 4699 memcpy(&vcpu->arch.guest_fpu->state.fxsave, 4700 guest_xsave->region, sizeof(struct fxregs_state)); 4701 } 4702 return 0; 4703 } 4704 4705 static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu, 4706 struct kvm_xcrs *guest_xcrs) 4707 { 4708 if (!boot_cpu_has(X86_FEATURE_XSAVE)) { 4709 guest_xcrs->nr_xcrs = 0; 4710 return; 4711 } 4712 4713 guest_xcrs->nr_xcrs = 1; 4714 guest_xcrs->flags = 0; 4715 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK; 4716 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0; 4717 } 4718 4719 static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu, 4720 struct kvm_xcrs *guest_xcrs) 4721 { 4722 int i, r = 0; 4723 4724 if (!boot_cpu_has(X86_FEATURE_XSAVE)) 4725 return -EINVAL; 4726 4727 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags) 4728 return -EINVAL; 4729 4730 for (i = 0; i < guest_xcrs->nr_xcrs; i++) 4731 /* Only support XCR0 currently */ 4732 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) { 4733 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK, 4734 guest_xcrs->xcrs[i].value); 4735 break; 4736 } 4737 if (r) 4738 r = -EINVAL; 4739 return r; 4740 } 4741 4742 /* 4743 * kvm_set_guest_paused() indicates to the guest kernel that it has been 4744 * stopped by the hypervisor. This function will be called from the host only. 4745 * EINVAL is returned when the host attempts to set the flag for a guest that 4746 * does not support pv clocks. 4747 */ 4748 static int kvm_set_guest_paused(struct kvm_vcpu *vcpu) 4749 { 4750 if (!vcpu->arch.pv_time_enabled) 4751 return -EINVAL; 4752 vcpu->arch.pvclock_set_guest_stopped_request = true; 4753 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 4754 return 0; 4755 } 4756 4757 static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu, 4758 struct kvm_enable_cap *cap) 4759 { 4760 int r; 4761 uint16_t vmcs_version; 4762 void __user *user_ptr; 4763 4764 if (cap->flags) 4765 return -EINVAL; 4766 4767 switch (cap->cap) { 4768 case KVM_CAP_HYPERV_SYNIC2: 4769 if (cap->args[0]) 4770 return -EINVAL; 4771 fallthrough; 4772 4773 case KVM_CAP_HYPERV_SYNIC: 4774 if (!irqchip_in_kernel(vcpu->kvm)) 4775 return -EINVAL; 4776 return kvm_hv_activate_synic(vcpu, cap->cap == 4777 KVM_CAP_HYPERV_SYNIC2); 4778 case KVM_CAP_HYPERV_ENLIGHTENED_VMCS: 4779 if (!kvm_x86_ops.nested_ops->enable_evmcs) 4780 return -ENOTTY; 4781 r = kvm_x86_ops.nested_ops->enable_evmcs(vcpu, &vmcs_version); 4782 if (!r) { 4783 user_ptr = (void __user *)(uintptr_t)cap->args[0]; 4784 if (copy_to_user(user_ptr, &vmcs_version, 4785 sizeof(vmcs_version))) 4786 r = -EFAULT; 4787 } 4788 return r; 4789 case KVM_CAP_HYPERV_DIRECT_TLBFLUSH: 4790 if (!kvm_x86_ops.enable_direct_tlbflush) 4791 return -ENOTTY; 4792 4793 return static_call(kvm_x86_enable_direct_tlbflush)(vcpu); 4794 4795 case KVM_CAP_ENFORCE_PV_FEATURE_CPUID: 4796 vcpu->arch.pv_cpuid.enforce = cap->args[0]; 4797 if (vcpu->arch.pv_cpuid.enforce) 4798 kvm_update_pv_runtime(vcpu); 4799 4800 return 0; 4801 default: 4802 return -EINVAL; 4803 } 4804 } 4805 4806 long kvm_arch_vcpu_ioctl(struct file *filp, 4807 unsigned int ioctl, unsigned long arg) 4808 { 4809 struct kvm_vcpu *vcpu = filp->private_data; 4810 void __user *argp = (void __user *)arg; 4811 int r; 4812 union { 4813 struct kvm_lapic_state *lapic; 4814 struct kvm_xsave *xsave; 4815 struct kvm_xcrs *xcrs; 4816 void *buffer; 4817 } u; 4818 4819 vcpu_load(vcpu); 4820 4821 u.buffer = NULL; 4822 switch (ioctl) { 4823 case KVM_GET_LAPIC: { 4824 r = -EINVAL; 4825 if (!lapic_in_kernel(vcpu)) 4826 goto out; 4827 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), 4828 GFP_KERNEL_ACCOUNT); 4829 4830 r = -ENOMEM; 4831 if (!u.lapic) 4832 goto out; 4833 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic); 4834 if (r) 4835 goto out; 4836 r = -EFAULT; 4837 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state))) 4838 goto out; 4839 r = 0; 4840 break; 4841 } 4842 case KVM_SET_LAPIC: { 4843 r = -EINVAL; 4844 if (!lapic_in_kernel(vcpu)) 4845 goto out; 4846 u.lapic = memdup_user(argp, sizeof(*u.lapic)); 4847 if (IS_ERR(u.lapic)) { 4848 r = PTR_ERR(u.lapic); 4849 goto out_nofree; 4850 } 4851 4852 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic); 4853 break; 4854 } 4855 case KVM_INTERRUPT: { 4856 struct kvm_interrupt irq; 4857 4858 r = -EFAULT; 4859 if (copy_from_user(&irq, argp, sizeof(irq))) 4860 goto out; 4861 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq); 4862 break; 4863 } 4864 case KVM_NMI: { 4865 r = kvm_vcpu_ioctl_nmi(vcpu); 4866 break; 4867 } 4868 case KVM_SMI: { 4869 r = kvm_vcpu_ioctl_smi(vcpu); 4870 break; 4871 } 4872 case KVM_SET_CPUID: { 4873 struct kvm_cpuid __user *cpuid_arg = argp; 4874 struct kvm_cpuid cpuid; 4875 4876 r = -EFAULT; 4877 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid))) 4878 goto out; 4879 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries); 4880 break; 4881 } 4882 case KVM_SET_CPUID2: { 4883 struct kvm_cpuid2 __user *cpuid_arg = argp; 4884 struct kvm_cpuid2 cpuid; 4885 4886 r = -EFAULT; 4887 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid))) 4888 goto out; 4889 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid, 4890 cpuid_arg->entries); 4891 break; 4892 } 4893 case KVM_GET_CPUID2: { 4894 struct kvm_cpuid2 __user *cpuid_arg = argp; 4895 struct kvm_cpuid2 cpuid; 4896 4897 r = -EFAULT; 4898 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid))) 4899 goto out; 4900 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid, 4901 cpuid_arg->entries); 4902 if (r) 4903 goto out; 4904 r = -EFAULT; 4905 if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid))) 4906 goto out; 4907 r = 0; 4908 break; 4909 } 4910 case KVM_GET_MSRS: { 4911 int idx = srcu_read_lock(&vcpu->kvm->srcu); 4912 r = msr_io(vcpu, argp, do_get_msr, 1); 4913 srcu_read_unlock(&vcpu->kvm->srcu, idx); 4914 break; 4915 } 4916 case KVM_SET_MSRS: { 4917 int idx = srcu_read_lock(&vcpu->kvm->srcu); 4918 r = msr_io(vcpu, argp, do_set_msr, 0); 4919 srcu_read_unlock(&vcpu->kvm->srcu, idx); 4920 break; 4921 } 4922 case KVM_TPR_ACCESS_REPORTING: { 4923 struct kvm_tpr_access_ctl tac; 4924 4925 r = -EFAULT; 4926 if (copy_from_user(&tac, argp, sizeof(tac))) 4927 goto out; 4928 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac); 4929 if (r) 4930 goto out; 4931 r = -EFAULT; 4932 if (copy_to_user(argp, &tac, sizeof(tac))) 4933 goto out; 4934 r = 0; 4935 break; 4936 }; 4937 case KVM_SET_VAPIC_ADDR: { 4938 struct kvm_vapic_addr va; 4939 int idx; 4940 4941 r = -EINVAL; 4942 if (!lapic_in_kernel(vcpu)) 4943 goto out; 4944 r = -EFAULT; 4945 if (copy_from_user(&va, argp, sizeof(va))) 4946 goto out; 4947 idx = srcu_read_lock(&vcpu->kvm->srcu); 4948 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr); 4949 srcu_read_unlock(&vcpu->kvm->srcu, idx); 4950 break; 4951 } 4952 case KVM_X86_SETUP_MCE: { 4953 u64 mcg_cap; 4954 4955 r = -EFAULT; 4956 if (copy_from_user(&mcg_cap, argp, sizeof(mcg_cap))) 4957 goto out; 4958 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap); 4959 break; 4960 } 4961 case KVM_X86_SET_MCE: { 4962 struct kvm_x86_mce mce; 4963 4964 r = -EFAULT; 4965 if (copy_from_user(&mce, argp, sizeof(mce))) 4966 goto out; 4967 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce); 4968 break; 4969 } 4970 case KVM_GET_VCPU_EVENTS: { 4971 struct kvm_vcpu_events events; 4972 4973 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events); 4974 4975 r = -EFAULT; 4976 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events))) 4977 break; 4978 r = 0; 4979 break; 4980 } 4981 case KVM_SET_VCPU_EVENTS: { 4982 struct kvm_vcpu_events events; 4983 4984 r = -EFAULT; 4985 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events))) 4986 break; 4987 4988 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events); 4989 break; 4990 } 4991 case KVM_GET_DEBUGREGS: { 4992 struct kvm_debugregs dbgregs; 4993 4994 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs); 4995 4996 r = -EFAULT; 4997 if (copy_to_user(argp, &dbgregs, 4998 sizeof(struct kvm_debugregs))) 4999 break; 5000 r = 0; 5001 break; 5002 } 5003 case KVM_SET_DEBUGREGS: { 5004 struct kvm_debugregs dbgregs; 5005 5006 r = -EFAULT; 5007 if (copy_from_user(&dbgregs, argp, 5008 sizeof(struct kvm_debugregs))) 5009 break; 5010 5011 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs); 5012 break; 5013 } 5014 case KVM_GET_XSAVE: { 5015 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL_ACCOUNT); 5016 r = -ENOMEM; 5017 if (!u.xsave) 5018 break; 5019 5020 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave); 5021 5022 r = -EFAULT; 5023 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave))) 5024 break; 5025 r = 0; 5026 break; 5027 } 5028 case KVM_SET_XSAVE: { 5029 u.xsave = memdup_user(argp, sizeof(*u.xsave)); 5030 if (IS_ERR(u.xsave)) { 5031 r = PTR_ERR(u.xsave); 5032 goto out_nofree; 5033 } 5034 5035 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave); 5036 break; 5037 } 5038 case KVM_GET_XCRS: { 5039 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL_ACCOUNT); 5040 r = -ENOMEM; 5041 if (!u.xcrs) 5042 break; 5043 5044 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs); 5045 5046 r = -EFAULT; 5047 if (copy_to_user(argp, u.xcrs, 5048 sizeof(struct kvm_xcrs))) 5049 break; 5050 r = 0; 5051 break; 5052 } 5053 case KVM_SET_XCRS: { 5054 u.xcrs = memdup_user(argp, sizeof(*u.xcrs)); 5055 if (IS_ERR(u.xcrs)) { 5056 r = PTR_ERR(u.xcrs); 5057 goto out_nofree; 5058 } 5059 5060 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs); 5061 break; 5062 } 5063 case KVM_SET_TSC_KHZ: { 5064 u32 user_tsc_khz; 5065 5066 r = -EINVAL; 5067 user_tsc_khz = (u32)arg; 5068 5069 if (kvm_has_tsc_control && 5070 user_tsc_khz >= kvm_max_guest_tsc_khz) 5071 goto out; 5072 5073 if (user_tsc_khz == 0) 5074 user_tsc_khz = tsc_khz; 5075 5076 if (!kvm_set_tsc_khz(vcpu, user_tsc_khz)) 5077 r = 0; 5078 5079 goto out; 5080 } 5081 case KVM_GET_TSC_KHZ: { 5082 r = vcpu->arch.virtual_tsc_khz; 5083 goto out; 5084 } 5085 case KVM_KVMCLOCK_CTRL: { 5086 r = kvm_set_guest_paused(vcpu); 5087 goto out; 5088 } 5089 case KVM_ENABLE_CAP: { 5090 struct kvm_enable_cap cap; 5091 5092 r = -EFAULT; 5093 if (copy_from_user(&cap, argp, sizeof(cap))) 5094 goto out; 5095 r = kvm_vcpu_ioctl_enable_cap(vcpu, &cap); 5096 break; 5097 } 5098 case KVM_GET_NESTED_STATE: { 5099 struct kvm_nested_state __user *user_kvm_nested_state = argp; 5100 u32 user_data_size; 5101 5102 r = -EINVAL; 5103 if (!kvm_x86_ops.nested_ops->get_state) 5104 break; 5105 5106 BUILD_BUG_ON(sizeof(user_data_size) != sizeof(user_kvm_nested_state->size)); 5107 r = -EFAULT; 5108 if (get_user(user_data_size, &user_kvm_nested_state->size)) 5109 break; 5110 5111 r = kvm_x86_ops.nested_ops->get_state(vcpu, user_kvm_nested_state, 5112 user_data_size); 5113 if (r < 0) 5114 break; 5115 5116 if (r > user_data_size) { 5117 if (put_user(r, &user_kvm_nested_state->size)) 5118 r = -EFAULT; 5119 else 5120 r = -E2BIG; 5121 break; 5122 } 5123 5124 r = 0; 5125 break; 5126 } 5127 case KVM_SET_NESTED_STATE: { 5128 struct kvm_nested_state __user *user_kvm_nested_state = argp; 5129 struct kvm_nested_state kvm_state; 5130 int idx; 5131 5132 r = -EINVAL; 5133 if (!kvm_x86_ops.nested_ops->set_state) 5134 break; 5135 5136 r = -EFAULT; 5137 if (copy_from_user(&kvm_state, user_kvm_nested_state, sizeof(kvm_state))) 5138 break; 5139 5140 r = -EINVAL; 5141 if (kvm_state.size < sizeof(kvm_state)) 5142 break; 5143 5144 if (kvm_state.flags & 5145 ~(KVM_STATE_NESTED_RUN_PENDING | KVM_STATE_NESTED_GUEST_MODE 5146 | KVM_STATE_NESTED_EVMCS | KVM_STATE_NESTED_MTF_PENDING 5147 | KVM_STATE_NESTED_GIF_SET)) 5148 break; 5149 5150 /* nested_run_pending implies guest_mode. */ 5151 if ((kvm_state.flags & KVM_STATE_NESTED_RUN_PENDING) 5152 && !(kvm_state.flags & KVM_STATE_NESTED_GUEST_MODE)) 5153 break; 5154 5155 idx = srcu_read_lock(&vcpu->kvm->srcu); 5156 r = kvm_x86_ops.nested_ops->set_state(vcpu, user_kvm_nested_state, &kvm_state); 5157 srcu_read_unlock(&vcpu->kvm->srcu, idx); 5158 break; 5159 } 5160 case KVM_GET_SUPPORTED_HV_CPUID: 5161 r = kvm_ioctl_get_supported_hv_cpuid(vcpu, argp); 5162 break; 5163 #ifdef CONFIG_KVM_XEN 5164 case KVM_XEN_VCPU_GET_ATTR: { 5165 struct kvm_xen_vcpu_attr xva; 5166 5167 r = -EFAULT; 5168 if (copy_from_user(&xva, argp, sizeof(xva))) 5169 goto out; 5170 r = kvm_xen_vcpu_get_attr(vcpu, &xva); 5171 if (!r && copy_to_user(argp, &xva, sizeof(xva))) 5172 r = -EFAULT; 5173 break; 5174 } 5175 case KVM_XEN_VCPU_SET_ATTR: { 5176 struct kvm_xen_vcpu_attr xva; 5177 5178 r = -EFAULT; 5179 if (copy_from_user(&xva, argp, sizeof(xva))) 5180 goto out; 5181 r = kvm_xen_vcpu_set_attr(vcpu, &xva); 5182 break; 5183 } 5184 #endif 5185 default: 5186 r = -EINVAL; 5187 } 5188 out: 5189 kfree(u.buffer); 5190 out_nofree: 5191 vcpu_put(vcpu); 5192 return r; 5193 } 5194 5195 vm_fault_t kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf) 5196 { 5197 return VM_FAULT_SIGBUS; 5198 } 5199 5200 static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr) 5201 { 5202 int ret; 5203 5204 if (addr > (unsigned int)(-3 * PAGE_SIZE)) 5205 return -EINVAL; 5206 ret = static_call(kvm_x86_set_tss_addr)(kvm, addr); 5207 return ret; 5208 } 5209 5210 static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm, 5211 u64 ident_addr) 5212 { 5213 return static_call(kvm_x86_set_identity_map_addr)(kvm, ident_addr); 5214 } 5215 5216 static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm, 5217 unsigned long kvm_nr_mmu_pages) 5218 { 5219 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES) 5220 return -EINVAL; 5221 5222 mutex_lock(&kvm->slots_lock); 5223 5224 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages); 5225 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages; 5226 5227 mutex_unlock(&kvm->slots_lock); 5228 return 0; 5229 } 5230 5231 static unsigned long kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm) 5232 { 5233 return kvm->arch.n_max_mmu_pages; 5234 } 5235 5236 static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip) 5237 { 5238 struct kvm_pic *pic = kvm->arch.vpic; 5239 int r; 5240 5241 r = 0; 5242 switch (chip->chip_id) { 5243 case KVM_IRQCHIP_PIC_MASTER: 5244 memcpy(&chip->chip.pic, &pic->pics[0], 5245 sizeof(struct kvm_pic_state)); 5246 break; 5247 case KVM_IRQCHIP_PIC_SLAVE: 5248 memcpy(&chip->chip.pic, &pic->pics[1], 5249 sizeof(struct kvm_pic_state)); 5250 break; 5251 case KVM_IRQCHIP_IOAPIC: 5252 kvm_get_ioapic(kvm, &chip->chip.ioapic); 5253 break; 5254 default: 5255 r = -EINVAL; 5256 break; 5257 } 5258 return r; 5259 } 5260 5261 static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip) 5262 { 5263 struct kvm_pic *pic = kvm->arch.vpic; 5264 int r; 5265 5266 r = 0; 5267 switch (chip->chip_id) { 5268 case KVM_IRQCHIP_PIC_MASTER: 5269 spin_lock(&pic->lock); 5270 memcpy(&pic->pics[0], &chip->chip.pic, 5271 sizeof(struct kvm_pic_state)); 5272 spin_unlock(&pic->lock); 5273 break; 5274 case KVM_IRQCHIP_PIC_SLAVE: 5275 spin_lock(&pic->lock); 5276 memcpy(&pic->pics[1], &chip->chip.pic, 5277 sizeof(struct kvm_pic_state)); 5278 spin_unlock(&pic->lock); 5279 break; 5280 case KVM_IRQCHIP_IOAPIC: 5281 kvm_set_ioapic(kvm, &chip->chip.ioapic); 5282 break; 5283 default: 5284 r = -EINVAL; 5285 break; 5286 } 5287 kvm_pic_update_irq(pic); 5288 return r; 5289 } 5290 5291 static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps) 5292 { 5293 struct kvm_kpit_state *kps = &kvm->arch.vpit->pit_state; 5294 5295 BUILD_BUG_ON(sizeof(*ps) != sizeof(kps->channels)); 5296 5297 mutex_lock(&kps->lock); 5298 memcpy(ps, &kps->channels, sizeof(*ps)); 5299 mutex_unlock(&kps->lock); 5300 return 0; 5301 } 5302 5303 static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps) 5304 { 5305 int i; 5306 struct kvm_pit *pit = kvm->arch.vpit; 5307 5308 mutex_lock(&pit->pit_state.lock); 5309 memcpy(&pit->pit_state.channels, ps, sizeof(*ps)); 5310 for (i = 0; i < 3; i++) 5311 kvm_pit_load_count(pit, i, ps->channels[i].count, 0); 5312 mutex_unlock(&pit->pit_state.lock); 5313 return 0; 5314 } 5315 5316 static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps) 5317 { 5318 mutex_lock(&kvm->arch.vpit->pit_state.lock); 5319 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels, 5320 sizeof(ps->channels)); 5321 ps->flags = kvm->arch.vpit->pit_state.flags; 5322 mutex_unlock(&kvm->arch.vpit->pit_state.lock); 5323 memset(&ps->reserved, 0, sizeof(ps->reserved)); 5324 return 0; 5325 } 5326 5327 static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps) 5328 { 5329 int start = 0; 5330 int i; 5331 u32 prev_legacy, cur_legacy; 5332 struct kvm_pit *pit = kvm->arch.vpit; 5333 5334 mutex_lock(&pit->pit_state.lock); 5335 prev_legacy = pit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY; 5336 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY; 5337 if (!prev_legacy && cur_legacy) 5338 start = 1; 5339 memcpy(&pit->pit_state.channels, &ps->channels, 5340 sizeof(pit->pit_state.channels)); 5341 pit->pit_state.flags = ps->flags; 5342 for (i = 0; i < 3; i++) 5343 kvm_pit_load_count(pit, i, pit->pit_state.channels[i].count, 5344 start && i == 0); 5345 mutex_unlock(&pit->pit_state.lock); 5346 return 0; 5347 } 5348 5349 static int kvm_vm_ioctl_reinject(struct kvm *kvm, 5350 struct kvm_reinject_control *control) 5351 { 5352 struct kvm_pit *pit = kvm->arch.vpit; 5353 5354 /* pit->pit_state.lock was overloaded to prevent userspace from getting 5355 * an inconsistent state after running multiple KVM_REINJECT_CONTROL 5356 * ioctls in parallel. Use a separate lock if that ioctl isn't rare. 5357 */ 5358 mutex_lock(&pit->pit_state.lock); 5359 kvm_pit_set_reinject(pit, control->pit_reinject); 5360 mutex_unlock(&pit->pit_state.lock); 5361 5362 return 0; 5363 } 5364 5365 void kvm_arch_sync_dirty_log(struct kvm *kvm, struct kvm_memory_slot *memslot) 5366 { 5367 5368 /* 5369 * Flush all CPUs' dirty log buffers to the dirty_bitmap. Called 5370 * before reporting dirty_bitmap to userspace. KVM flushes the buffers 5371 * on all VM-Exits, thus we only need to kick running vCPUs to force a 5372 * VM-Exit. 5373 */ 5374 struct kvm_vcpu *vcpu; 5375 int i; 5376 5377 kvm_for_each_vcpu(i, vcpu, kvm) 5378 kvm_vcpu_kick(vcpu); 5379 } 5380 5381 int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event, 5382 bool line_status) 5383 { 5384 if (!irqchip_in_kernel(kvm)) 5385 return -ENXIO; 5386 5387 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID, 5388 irq_event->irq, irq_event->level, 5389 line_status); 5390 return 0; 5391 } 5392 5393 int kvm_vm_ioctl_enable_cap(struct kvm *kvm, 5394 struct kvm_enable_cap *cap) 5395 { 5396 int r; 5397 5398 if (cap->flags) 5399 return -EINVAL; 5400 5401 switch (cap->cap) { 5402 case KVM_CAP_DISABLE_QUIRKS: 5403 kvm->arch.disabled_quirks = cap->args[0]; 5404 r = 0; 5405 break; 5406 case KVM_CAP_SPLIT_IRQCHIP: { 5407 mutex_lock(&kvm->lock); 5408 r = -EINVAL; 5409 if (cap->args[0] > MAX_NR_RESERVED_IOAPIC_PINS) 5410 goto split_irqchip_unlock; 5411 r = -EEXIST; 5412 if (irqchip_in_kernel(kvm)) 5413 goto split_irqchip_unlock; 5414 if (kvm->created_vcpus) 5415 goto split_irqchip_unlock; 5416 r = kvm_setup_empty_irq_routing(kvm); 5417 if (r) 5418 goto split_irqchip_unlock; 5419 /* Pairs with irqchip_in_kernel. */ 5420 smp_wmb(); 5421 kvm->arch.irqchip_mode = KVM_IRQCHIP_SPLIT; 5422 kvm->arch.nr_reserved_ioapic_pins = cap->args[0]; 5423 r = 0; 5424 split_irqchip_unlock: 5425 mutex_unlock(&kvm->lock); 5426 break; 5427 } 5428 case KVM_CAP_X2APIC_API: 5429 r = -EINVAL; 5430 if (cap->args[0] & ~KVM_X2APIC_API_VALID_FLAGS) 5431 break; 5432 5433 if (cap->args[0] & KVM_X2APIC_API_USE_32BIT_IDS) 5434 kvm->arch.x2apic_format = true; 5435 if (cap->args[0] & KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK) 5436 kvm->arch.x2apic_broadcast_quirk_disabled = true; 5437 5438 r = 0; 5439 break; 5440 case KVM_CAP_X86_DISABLE_EXITS: 5441 r = -EINVAL; 5442 if (cap->args[0] & ~KVM_X86_DISABLE_VALID_EXITS) 5443 break; 5444 5445 if ((cap->args[0] & KVM_X86_DISABLE_EXITS_MWAIT) && 5446 kvm_can_mwait_in_guest()) 5447 kvm->arch.mwait_in_guest = true; 5448 if (cap->args[0] & KVM_X86_DISABLE_EXITS_HLT) 5449 kvm->arch.hlt_in_guest = true; 5450 if (cap->args[0] & KVM_X86_DISABLE_EXITS_PAUSE) 5451 kvm->arch.pause_in_guest = true; 5452 if (cap->args[0] & KVM_X86_DISABLE_EXITS_CSTATE) 5453 kvm->arch.cstate_in_guest = true; 5454 r = 0; 5455 break; 5456 case KVM_CAP_MSR_PLATFORM_INFO: 5457 kvm->arch.guest_can_read_msr_platform_info = cap->args[0]; 5458 r = 0; 5459 break; 5460 case KVM_CAP_EXCEPTION_PAYLOAD: 5461 kvm->arch.exception_payload_enabled = cap->args[0]; 5462 r = 0; 5463 break; 5464 case KVM_CAP_X86_USER_SPACE_MSR: 5465 kvm->arch.user_space_msr_mask = cap->args[0]; 5466 r = 0; 5467 break; 5468 case KVM_CAP_X86_BUS_LOCK_EXIT: 5469 r = -EINVAL; 5470 if (cap->args[0] & ~KVM_BUS_LOCK_DETECTION_VALID_MODE) 5471 break; 5472 5473 if ((cap->args[0] & KVM_BUS_LOCK_DETECTION_OFF) && 5474 (cap->args[0] & KVM_BUS_LOCK_DETECTION_EXIT)) 5475 break; 5476 5477 if (kvm_has_bus_lock_exit && 5478 cap->args[0] & KVM_BUS_LOCK_DETECTION_EXIT) 5479 kvm->arch.bus_lock_detection_enabled = true; 5480 r = 0; 5481 break; 5482 #ifdef CONFIG_X86_SGX_KVM 5483 case KVM_CAP_SGX_ATTRIBUTE: { 5484 unsigned long allowed_attributes = 0; 5485 5486 r = sgx_set_attribute(&allowed_attributes, cap->args[0]); 5487 if (r) 5488 break; 5489 5490 /* KVM only supports the PROVISIONKEY privileged attribute. */ 5491 if ((allowed_attributes & SGX_ATTR_PROVISIONKEY) && 5492 !(allowed_attributes & ~SGX_ATTR_PROVISIONKEY)) 5493 kvm->arch.sgx_provisioning_allowed = true; 5494 else 5495 r = -EINVAL; 5496 break; 5497 } 5498 #endif 5499 case KVM_CAP_VM_COPY_ENC_CONTEXT_FROM: 5500 r = -EINVAL; 5501 if (kvm_x86_ops.vm_copy_enc_context_from) 5502 r = kvm_x86_ops.vm_copy_enc_context_from(kvm, cap->args[0]); 5503 return r; 5504 default: 5505 r = -EINVAL; 5506 break; 5507 } 5508 return r; 5509 } 5510 5511 static struct kvm_x86_msr_filter *kvm_alloc_msr_filter(bool default_allow) 5512 { 5513 struct kvm_x86_msr_filter *msr_filter; 5514 5515 msr_filter = kzalloc(sizeof(*msr_filter), GFP_KERNEL_ACCOUNT); 5516 if (!msr_filter) 5517 return NULL; 5518 5519 msr_filter->default_allow = default_allow; 5520 return msr_filter; 5521 } 5522 5523 static void kvm_free_msr_filter(struct kvm_x86_msr_filter *msr_filter) 5524 { 5525 u32 i; 5526 5527 if (!msr_filter) 5528 return; 5529 5530 for (i = 0; i < msr_filter->count; i++) 5531 kfree(msr_filter->ranges[i].bitmap); 5532 5533 kfree(msr_filter); 5534 } 5535 5536 static int kvm_add_msr_filter(struct kvm_x86_msr_filter *msr_filter, 5537 struct kvm_msr_filter_range *user_range) 5538 { 5539 unsigned long *bitmap = NULL; 5540 size_t bitmap_size; 5541 5542 if (!user_range->nmsrs) 5543 return 0; 5544 5545 if (user_range->flags & ~(KVM_MSR_FILTER_READ | KVM_MSR_FILTER_WRITE)) 5546 return -EINVAL; 5547 5548 if (!user_range->flags) 5549 return -EINVAL; 5550 5551 bitmap_size = BITS_TO_LONGS(user_range->nmsrs) * sizeof(long); 5552 if (!bitmap_size || bitmap_size > KVM_MSR_FILTER_MAX_BITMAP_SIZE) 5553 return -EINVAL; 5554 5555 bitmap = memdup_user((__user u8*)user_range->bitmap, bitmap_size); 5556 if (IS_ERR(bitmap)) 5557 return PTR_ERR(bitmap); 5558 5559 msr_filter->ranges[msr_filter->count] = (struct msr_bitmap_range) { 5560 .flags = user_range->flags, 5561 .base = user_range->base, 5562 .nmsrs = user_range->nmsrs, 5563 .bitmap = bitmap, 5564 }; 5565 5566 msr_filter->count++; 5567 return 0; 5568 } 5569 5570 static int kvm_vm_ioctl_set_msr_filter(struct kvm *kvm, void __user *argp) 5571 { 5572 struct kvm_msr_filter __user *user_msr_filter = argp; 5573 struct kvm_x86_msr_filter *new_filter, *old_filter; 5574 struct kvm_msr_filter filter; 5575 bool default_allow; 5576 bool empty = true; 5577 int r = 0; 5578 u32 i; 5579 5580 if (copy_from_user(&filter, user_msr_filter, sizeof(filter))) 5581 return -EFAULT; 5582 5583 for (i = 0; i < ARRAY_SIZE(filter.ranges); i++) 5584 empty &= !filter.ranges[i].nmsrs; 5585 5586 default_allow = !(filter.flags & KVM_MSR_FILTER_DEFAULT_DENY); 5587 if (empty && !default_allow) 5588 return -EINVAL; 5589 5590 new_filter = kvm_alloc_msr_filter(default_allow); 5591 if (!new_filter) 5592 return -ENOMEM; 5593 5594 for (i = 0; i < ARRAY_SIZE(filter.ranges); i++) { 5595 r = kvm_add_msr_filter(new_filter, &filter.ranges[i]); 5596 if (r) { 5597 kvm_free_msr_filter(new_filter); 5598 return r; 5599 } 5600 } 5601 5602 mutex_lock(&kvm->lock); 5603 5604 /* The per-VM filter is protected by kvm->lock... */ 5605 old_filter = srcu_dereference_check(kvm->arch.msr_filter, &kvm->srcu, 1); 5606 5607 rcu_assign_pointer(kvm->arch.msr_filter, new_filter); 5608 synchronize_srcu(&kvm->srcu); 5609 5610 kvm_free_msr_filter(old_filter); 5611 5612 kvm_make_all_cpus_request(kvm, KVM_REQ_MSR_FILTER_CHANGED); 5613 mutex_unlock(&kvm->lock); 5614 5615 return 0; 5616 } 5617 5618 long kvm_arch_vm_ioctl(struct file *filp, 5619 unsigned int ioctl, unsigned long arg) 5620 { 5621 struct kvm *kvm = filp->private_data; 5622 void __user *argp = (void __user *)arg; 5623 int r = -ENOTTY; 5624 /* 5625 * This union makes it completely explicit to gcc-3.x 5626 * that these two variables' stack usage should be 5627 * combined, not added together. 5628 */ 5629 union { 5630 struct kvm_pit_state ps; 5631 struct kvm_pit_state2 ps2; 5632 struct kvm_pit_config pit_config; 5633 } u; 5634 5635 switch (ioctl) { 5636 case KVM_SET_TSS_ADDR: 5637 r = kvm_vm_ioctl_set_tss_addr(kvm, arg); 5638 break; 5639 case KVM_SET_IDENTITY_MAP_ADDR: { 5640 u64 ident_addr; 5641 5642 mutex_lock(&kvm->lock); 5643 r = -EINVAL; 5644 if (kvm->created_vcpus) 5645 goto set_identity_unlock; 5646 r = -EFAULT; 5647 if (copy_from_user(&ident_addr, argp, sizeof(ident_addr))) 5648 goto set_identity_unlock; 5649 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr); 5650 set_identity_unlock: 5651 mutex_unlock(&kvm->lock); 5652 break; 5653 } 5654 case KVM_SET_NR_MMU_PAGES: 5655 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg); 5656 break; 5657 case KVM_GET_NR_MMU_PAGES: 5658 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm); 5659 break; 5660 case KVM_CREATE_IRQCHIP: { 5661 mutex_lock(&kvm->lock); 5662 5663 r = -EEXIST; 5664 if (irqchip_in_kernel(kvm)) 5665 goto create_irqchip_unlock; 5666 5667 r = -EINVAL; 5668 if (kvm->created_vcpus) 5669 goto create_irqchip_unlock; 5670 5671 r = kvm_pic_init(kvm); 5672 if (r) 5673 goto create_irqchip_unlock; 5674 5675 r = kvm_ioapic_init(kvm); 5676 if (r) { 5677 kvm_pic_destroy(kvm); 5678 goto create_irqchip_unlock; 5679 } 5680 5681 r = kvm_setup_default_irq_routing(kvm); 5682 if (r) { 5683 kvm_ioapic_destroy(kvm); 5684 kvm_pic_destroy(kvm); 5685 goto create_irqchip_unlock; 5686 } 5687 /* Write kvm->irq_routing before enabling irqchip_in_kernel. */ 5688 smp_wmb(); 5689 kvm->arch.irqchip_mode = KVM_IRQCHIP_KERNEL; 5690 create_irqchip_unlock: 5691 mutex_unlock(&kvm->lock); 5692 break; 5693 } 5694 case KVM_CREATE_PIT: 5695 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY; 5696 goto create_pit; 5697 case KVM_CREATE_PIT2: 5698 r = -EFAULT; 5699 if (copy_from_user(&u.pit_config, argp, 5700 sizeof(struct kvm_pit_config))) 5701 goto out; 5702 create_pit: 5703 mutex_lock(&kvm->lock); 5704 r = -EEXIST; 5705 if (kvm->arch.vpit) 5706 goto create_pit_unlock; 5707 r = -ENOMEM; 5708 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags); 5709 if (kvm->arch.vpit) 5710 r = 0; 5711 create_pit_unlock: 5712 mutex_unlock(&kvm->lock); 5713 break; 5714 case KVM_GET_IRQCHIP: { 5715 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */ 5716 struct kvm_irqchip *chip; 5717 5718 chip = memdup_user(argp, sizeof(*chip)); 5719 if (IS_ERR(chip)) { 5720 r = PTR_ERR(chip); 5721 goto out; 5722 } 5723 5724 r = -ENXIO; 5725 if (!irqchip_kernel(kvm)) 5726 goto get_irqchip_out; 5727 r = kvm_vm_ioctl_get_irqchip(kvm, chip); 5728 if (r) 5729 goto get_irqchip_out; 5730 r = -EFAULT; 5731 if (copy_to_user(argp, chip, sizeof(*chip))) 5732 goto get_irqchip_out; 5733 r = 0; 5734 get_irqchip_out: 5735 kfree(chip); 5736 break; 5737 } 5738 case KVM_SET_IRQCHIP: { 5739 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */ 5740 struct kvm_irqchip *chip; 5741 5742 chip = memdup_user(argp, sizeof(*chip)); 5743 if (IS_ERR(chip)) { 5744 r = PTR_ERR(chip); 5745 goto out; 5746 } 5747 5748 r = -ENXIO; 5749 if (!irqchip_kernel(kvm)) 5750 goto set_irqchip_out; 5751 r = kvm_vm_ioctl_set_irqchip(kvm, chip); 5752 set_irqchip_out: 5753 kfree(chip); 5754 break; 5755 } 5756 case KVM_GET_PIT: { 5757 r = -EFAULT; 5758 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state))) 5759 goto out; 5760 r = -ENXIO; 5761 if (!kvm->arch.vpit) 5762 goto out; 5763 r = kvm_vm_ioctl_get_pit(kvm, &u.ps); 5764 if (r) 5765 goto out; 5766 r = -EFAULT; 5767 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state))) 5768 goto out; 5769 r = 0; 5770 break; 5771 } 5772 case KVM_SET_PIT: { 5773 r = -EFAULT; 5774 if (copy_from_user(&u.ps, argp, sizeof(u.ps))) 5775 goto out; 5776 mutex_lock(&kvm->lock); 5777 r = -ENXIO; 5778 if (!kvm->arch.vpit) 5779 goto set_pit_out; 5780 r = kvm_vm_ioctl_set_pit(kvm, &u.ps); 5781 set_pit_out: 5782 mutex_unlock(&kvm->lock); 5783 break; 5784 } 5785 case KVM_GET_PIT2: { 5786 r = -ENXIO; 5787 if (!kvm->arch.vpit) 5788 goto out; 5789 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2); 5790 if (r) 5791 goto out; 5792 r = -EFAULT; 5793 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2))) 5794 goto out; 5795 r = 0; 5796 break; 5797 } 5798 case KVM_SET_PIT2: { 5799 r = -EFAULT; 5800 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2))) 5801 goto out; 5802 mutex_lock(&kvm->lock); 5803 r = -ENXIO; 5804 if (!kvm->arch.vpit) 5805 goto set_pit2_out; 5806 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2); 5807 set_pit2_out: 5808 mutex_unlock(&kvm->lock); 5809 break; 5810 } 5811 case KVM_REINJECT_CONTROL: { 5812 struct kvm_reinject_control control; 5813 r = -EFAULT; 5814 if (copy_from_user(&control, argp, sizeof(control))) 5815 goto out; 5816 r = -ENXIO; 5817 if (!kvm->arch.vpit) 5818 goto out; 5819 r = kvm_vm_ioctl_reinject(kvm, &control); 5820 break; 5821 } 5822 case KVM_SET_BOOT_CPU_ID: 5823 r = 0; 5824 mutex_lock(&kvm->lock); 5825 if (kvm->created_vcpus) 5826 r = -EBUSY; 5827 else 5828 kvm->arch.bsp_vcpu_id = arg; 5829 mutex_unlock(&kvm->lock); 5830 break; 5831 #ifdef CONFIG_KVM_XEN 5832 case KVM_XEN_HVM_CONFIG: { 5833 struct kvm_xen_hvm_config xhc; 5834 r = -EFAULT; 5835 if (copy_from_user(&xhc, argp, sizeof(xhc))) 5836 goto out; 5837 r = kvm_xen_hvm_config(kvm, &xhc); 5838 break; 5839 } 5840 case KVM_XEN_HVM_GET_ATTR: { 5841 struct kvm_xen_hvm_attr xha; 5842 5843 r = -EFAULT; 5844 if (copy_from_user(&xha, argp, sizeof(xha))) 5845 goto out; 5846 r = kvm_xen_hvm_get_attr(kvm, &xha); 5847 if (!r && copy_to_user(argp, &xha, sizeof(xha))) 5848 r = -EFAULT; 5849 break; 5850 } 5851 case KVM_XEN_HVM_SET_ATTR: { 5852 struct kvm_xen_hvm_attr xha; 5853 5854 r = -EFAULT; 5855 if (copy_from_user(&xha, argp, sizeof(xha))) 5856 goto out; 5857 r = kvm_xen_hvm_set_attr(kvm, &xha); 5858 break; 5859 } 5860 #endif 5861 case KVM_SET_CLOCK: { 5862 struct kvm_arch *ka = &kvm->arch; 5863 struct kvm_clock_data user_ns; 5864 u64 now_ns; 5865 5866 r = -EFAULT; 5867 if (copy_from_user(&user_ns, argp, sizeof(user_ns))) 5868 goto out; 5869 5870 r = -EINVAL; 5871 if (user_ns.flags) 5872 goto out; 5873 5874 r = 0; 5875 /* 5876 * TODO: userspace has to take care of races with VCPU_RUN, so 5877 * kvm_gen_update_masterclock() can be cut down to locked 5878 * pvclock_update_vm_gtod_copy(). 5879 */ 5880 kvm_gen_update_masterclock(kvm); 5881 5882 /* 5883 * This pairs with kvm_guest_time_update(): when masterclock is 5884 * in use, we use master_kernel_ns + kvmclock_offset to set 5885 * unsigned 'system_time' so if we use get_kvmclock_ns() (which 5886 * is slightly ahead) here we risk going negative on unsigned 5887 * 'system_time' when 'user_ns.clock' is very small. 5888 */ 5889 spin_lock_irq(&ka->pvclock_gtod_sync_lock); 5890 if (kvm->arch.use_master_clock) 5891 now_ns = ka->master_kernel_ns; 5892 else 5893 now_ns = get_kvmclock_base_ns(); 5894 ka->kvmclock_offset = user_ns.clock - now_ns; 5895 spin_unlock_irq(&ka->pvclock_gtod_sync_lock); 5896 5897 kvm_make_all_cpus_request(kvm, KVM_REQ_CLOCK_UPDATE); 5898 break; 5899 } 5900 case KVM_GET_CLOCK: { 5901 struct kvm_clock_data user_ns; 5902 u64 now_ns; 5903 5904 now_ns = get_kvmclock_ns(kvm); 5905 user_ns.clock = now_ns; 5906 user_ns.flags = kvm->arch.use_master_clock ? KVM_CLOCK_TSC_STABLE : 0; 5907 memset(&user_ns.pad, 0, sizeof(user_ns.pad)); 5908 5909 r = -EFAULT; 5910 if (copy_to_user(argp, &user_ns, sizeof(user_ns))) 5911 goto out; 5912 r = 0; 5913 break; 5914 } 5915 case KVM_MEMORY_ENCRYPT_OP: { 5916 r = -ENOTTY; 5917 if (kvm_x86_ops.mem_enc_op) 5918 r = static_call(kvm_x86_mem_enc_op)(kvm, argp); 5919 break; 5920 } 5921 case KVM_MEMORY_ENCRYPT_REG_REGION: { 5922 struct kvm_enc_region region; 5923 5924 r = -EFAULT; 5925 if (copy_from_user(®ion, argp, sizeof(region))) 5926 goto out; 5927 5928 r = -ENOTTY; 5929 if (kvm_x86_ops.mem_enc_reg_region) 5930 r = static_call(kvm_x86_mem_enc_reg_region)(kvm, ®ion); 5931 break; 5932 } 5933 case KVM_MEMORY_ENCRYPT_UNREG_REGION: { 5934 struct kvm_enc_region region; 5935 5936 r = -EFAULT; 5937 if (copy_from_user(®ion, argp, sizeof(region))) 5938 goto out; 5939 5940 r = -ENOTTY; 5941 if (kvm_x86_ops.mem_enc_unreg_region) 5942 r = static_call(kvm_x86_mem_enc_unreg_region)(kvm, ®ion); 5943 break; 5944 } 5945 case KVM_HYPERV_EVENTFD: { 5946 struct kvm_hyperv_eventfd hvevfd; 5947 5948 r = -EFAULT; 5949 if (copy_from_user(&hvevfd, argp, sizeof(hvevfd))) 5950 goto out; 5951 r = kvm_vm_ioctl_hv_eventfd(kvm, &hvevfd); 5952 break; 5953 } 5954 case KVM_SET_PMU_EVENT_FILTER: 5955 r = kvm_vm_ioctl_set_pmu_event_filter(kvm, argp); 5956 break; 5957 case KVM_X86_SET_MSR_FILTER: 5958 r = kvm_vm_ioctl_set_msr_filter(kvm, argp); 5959 break; 5960 default: 5961 r = -ENOTTY; 5962 } 5963 out: 5964 return r; 5965 } 5966 5967 static void kvm_init_msr_list(void) 5968 { 5969 struct x86_pmu_capability x86_pmu; 5970 u32 dummy[2]; 5971 unsigned i; 5972 5973 BUILD_BUG_ON_MSG(INTEL_PMC_MAX_FIXED != 4, 5974 "Please update the fixed PMCs in msrs_to_saved_all[]"); 5975 5976 perf_get_x86_pmu_capability(&x86_pmu); 5977 5978 num_msrs_to_save = 0; 5979 num_emulated_msrs = 0; 5980 num_msr_based_features = 0; 5981 5982 for (i = 0; i < ARRAY_SIZE(msrs_to_save_all); i++) { 5983 if (rdmsr_safe(msrs_to_save_all[i], &dummy[0], &dummy[1]) < 0) 5984 continue; 5985 5986 /* 5987 * Even MSRs that are valid in the host may not be exposed 5988 * to the guests in some cases. 5989 */ 5990 switch (msrs_to_save_all[i]) { 5991 case MSR_IA32_BNDCFGS: 5992 if (!kvm_mpx_supported()) 5993 continue; 5994 break; 5995 case MSR_TSC_AUX: 5996 if (!kvm_cpu_cap_has(X86_FEATURE_RDTSCP) && 5997 !kvm_cpu_cap_has(X86_FEATURE_RDPID)) 5998 continue; 5999 break; 6000 case MSR_IA32_UMWAIT_CONTROL: 6001 if (!kvm_cpu_cap_has(X86_FEATURE_WAITPKG)) 6002 continue; 6003 break; 6004 case MSR_IA32_RTIT_CTL: 6005 case MSR_IA32_RTIT_STATUS: 6006 if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT)) 6007 continue; 6008 break; 6009 case MSR_IA32_RTIT_CR3_MATCH: 6010 if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT) || 6011 !intel_pt_validate_hw_cap(PT_CAP_cr3_filtering)) 6012 continue; 6013 break; 6014 case MSR_IA32_RTIT_OUTPUT_BASE: 6015 case MSR_IA32_RTIT_OUTPUT_MASK: 6016 if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT) || 6017 (!intel_pt_validate_hw_cap(PT_CAP_topa_output) && 6018 !intel_pt_validate_hw_cap(PT_CAP_single_range_output))) 6019 continue; 6020 break; 6021 case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B: 6022 if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT) || 6023 msrs_to_save_all[i] - MSR_IA32_RTIT_ADDR0_A >= 6024 intel_pt_validate_hw_cap(PT_CAP_num_address_ranges) * 2) 6025 continue; 6026 break; 6027 case MSR_ARCH_PERFMON_PERFCTR0 ... MSR_ARCH_PERFMON_PERFCTR0 + 17: 6028 if (msrs_to_save_all[i] - MSR_ARCH_PERFMON_PERFCTR0 >= 6029 min(INTEL_PMC_MAX_GENERIC, x86_pmu.num_counters_gp)) 6030 continue; 6031 break; 6032 case MSR_ARCH_PERFMON_EVENTSEL0 ... MSR_ARCH_PERFMON_EVENTSEL0 + 17: 6033 if (msrs_to_save_all[i] - MSR_ARCH_PERFMON_EVENTSEL0 >= 6034 min(INTEL_PMC_MAX_GENERIC, x86_pmu.num_counters_gp)) 6035 continue; 6036 break; 6037 default: 6038 break; 6039 } 6040 6041 msrs_to_save[num_msrs_to_save++] = msrs_to_save_all[i]; 6042 } 6043 6044 for (i = 0; i < ARRAY_SIZE(emulated_msrs_all); i++) { 6045 if (!static_call(kvm_x86_has_emulated_msr)(NULL, emulated_msrs_all[i])) 6046 continue; 6047 6048 emulated_msrs[num_emulated_msrs++] = emulated_msrs_all[i]; 6049 } 6050 6051 for (i = 0; i < ARRAY_SIZE(msr_based_features_all); i++) { 6052 struct kvm_msr_entry msr; 6053 6054 msr.index = msr_based_features_all[i]; 6055 if (kvm_get_msr_feature(&msr)) 6056 continue; 6057 6058 msr_based_features[num_msr_based_features++] = msr_based_features_all[i]; 6059 } 6060 } 6061 6062 static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len, 6063 const void *v) 6064 { 6065 int handled = 0; 6066 int n; 6067 6068 do { 6069 n = min(len, 8); 6070 if (!(lapic_in_kernel(vcpu) && 6071 !kvm_iodevice_write(vcpu, &vcpu->arch.apic->dev, addr, n, v)) 6072 && kvm_io_bus_write(vcpu, KVM_MMIO_BUS, addr, n, v)) 6073 break; 6074 handled += n; 6075 addr += n; 6076 len -= n; 6077 v += n; 6078 } while (len); 6079 6080 return handled; 6081 } 6082 6083 static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v) 6084 { 6085 int handled = 0; 6086 int n; 6087 6088 do { 6089 n = min(len, 8); 6090 if (!(lapic_in_kernel(vcpu) && 6091 !kvm_iodevice_read(vcpu, &vcpu->arch.apic->dev, 6092 addr, n, v)) 6093 && kvm_io_bus_read(vcpu, KVM_MMIO_BUS, addr, n, v)) 6094 break; 6095 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, v); 6096 handled += n; 6097 addr += n; 6098 len -= n; 6099 v += n; 6100 } while (len); 6101 6102 return handled; 6103 } 6104 6105 static void kvm_set_segment(struct kvm_vcpu *vcpu, 6106 struct kvm_segment *var, int seg) 6107 { 6108 static_call(kvm_x86_set_segment)(vcpu, var, seg); 6109 } 6110 6111 void kvm_get_segment(struct kvm_vcpu *vcpu, 6112 struct kvm_segment *var, int seg) 6113 { 6114 static_call(kvm_x86_get_segment)(vcpu, var, seg); 6115 } 6116 6117 gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access, 6118 struct x86_exception *exception) 6119 { 6120 gpa_t t_gpa; 6121 6122 BUG_ON(!mmu_is_nested(vcpu)); 6123 6124 /* NPT walks are always user-walks */ 6125 access |= PFERR_USER_MASK; 6126 t_gpa = vcpu->arch.mmu->gva_to_gpa(vcpu, gpa, access, exception); 6127 6128 return t_gpa; 6129 } 6130 6131 gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva, 6132 struct x86_exception *exception) 6133 { 6134 u32 access = (static_call(kvm_x86_get_cpl)(vcpu) == 3) ? PFERR_USER_MASK : 0; 6135 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception); 6136 } 6137 EXPORT_SYMBOL_GPL(kvm_mmu_gva_to_gpa_read); 6138 6139 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva, 6140 struct x86_exception *exception) 6141 { 6142 u32 access = (static_call(kvm_x86_get_cpl)(vcpu) == 3) ? PFERR_USER_MASK : 0; 6143 access |= PFERR_FETCH_MASK; 6144 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception); 6145 } 6146 6147 gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva, 6148 struct x86_exception *exception) 6149 { 6150 u32 access = (static_call(kvm_x86_get_cpl)(vcpu) == 3) ? PFERR_USER_MASK : 0; 6151 access |= PFERR_WRITE_MASK; 6152 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception); 6153 } 6154 EXPORT_SYMBOL_GPL(kvm_mmu_gva_to_gpa_write); 6155 6156 /* uses this to access any guest's mapped memory without checking CPL */ 6157 gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva, 6158 struct x86_exception *exception) 6159 { 6160 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception); 6161 } 6162 6163 static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes, 6164 struct kvm_vcpu *vcpu, u32 access, 6165 struct x86_exception *exception) 6166 { 6167 void *data = val; 6168 int r = X86EMUL_CONTINUE; 6169 6170 while (bytes) { 6171 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access, 6172 exception); 6173 unsigned offset = addr & (PAGE_SIZE-1); 6174 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset); 6175 int ret; 6176 6177 if (gpa == UNMAPPED_GVA) 6178 return X86EMUL_PROPAGATE_FAULT; 6179 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, data, 6180 offset, toread); 6181 if (ret < 0) { 6182 r = X86EMUL_IO_NEEDED; 6183 goto out; 6184 } 6185 6186 bytes -= toread; 6187 data += toread; 6188 addr += toread; 6189 } 6190 out: 6191 return r; 6192 } 6193 6194 /* used for instruction fetching */ 6195 static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt, 6196 gva_t addr, void *val, unsigned int bytes, 6197 struct x86_exception *exception) 6198 { 6199 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 6200 u32 access = (static_call(kvm_x86_get_cpl)(vcpu) == 3) ? PFERR_USER_MASK : 0; 6201 unsigned offset; 6202 int ret; 6203 6204 /* Inline kvm_read_guest_virt_helper for speed. */ 6205 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access|PFERR_FETCH_MASK, 6206 exception); 6207 if (unlikely(gpa == UNMAPPED_GVA)) 6208 return X86EMUL_PROPAGATE_FAULT; 6209 6210 offset = addr & (PAGE_SIZE-1); 6211 if (WARN_ON(offset + bytes > PAGE_SIZE)) 6212 bytes = (unsigned)PAGE_SIZE - offset; 6213 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, val, 6214 offset, bytes); 6215 if (unlikely(ret < 0)) 6216 return X86EMUL_IO_NEEDED; 6217 6218 return X86EMUL_CONTINUE; 6219 } 6220 6221 int kvm_read_guest_virt(struct kvm_vcpu *vcpu, 6222 gva_t addr, void *val, unsigned int bytes, 6223 struct x86_exception *exception) 6224 { 6225 u32 access = (static_call(kvm_x86_get_cpl)(vcpu) == 3) ? PFERR_USER_MASK : 0; 6226 6227 /* 6228 * FIXME: this should call handle_emulation_failure if X86EMUL_IO_NEEDED 6229 * is returned, but our callers are not ready for that and they blindly 6230 * call kvm_inject_page_fault. Ensure that they at least do not leak 6231 * uninitialized kernel stack memory into cr2 and error code. 6232 */ 6233 memset(exception, 0, sizeof(*exception)); 6234 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access, 6235 exception); 6236 } 6237 EXPORT_SYMBOL_GPL(kvm_read_guest_virt); 6238 6239 static int emulator_read_std(struct x86_emulate_ctxt *ctxt, 6240 gva_t addr, void *val, unsigned int bytes, 6241 struct x86_exception *exception, bool system) 6242 { 6243 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 6244 u32 access = 0; 6245 6246 if (!system && static_call(kvm_x86_get_cpl)(vcpu) == 3) 6247 access |= PFERR_USER_MASK; 6248 6249 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access, exception); 6250 } 6251 6252 static int kvm_read_guest_phys_system(struct x86_emulate_ctxt *ctxt, 6253 unsigned long addr, void *val, unsigned int bytes) 6254 { 6255 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 6256 int r = kvm_vcpu_read_guest(vcpu, addr, val, bytes); 6257 6258 return r < 0 ? X86EMUL_IO_NEEDED : X86EMUL_CONTINUE; 6259 } 6260 6261 static int kvm_write_guest_virt_helper(gva_t addr, void *val, unsigned int bytes, 6262 struct kvm_vcpu *vcpu, u32 access, 6263 struct x86_exception *exception) 6264 { 6265 void *data = val; 6266 int r = X86EMUL_CONTINUE; 6267 6268 while (bytes) { 6269 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, 6270 access, 6271 exception); 6272 unsigned offset = addr & (PAGE_SIZE-1); 6273 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset); 6274 int ret; 6275 6276 if (gpa == UNMAPPED_GVA) 6277 return X86EMUL_PROPAGATE_FAULT; 6278 ret = kvm_vcpu_write_guest(vcpu, gpa, data, towrite); 6279 if (ret < 0) { 6280 r = X86EMUL_IO_NEEDED; 6281 goto out; 6282 } 6283 6284 bytes -= towrite; 6285 data += towrite; 6286 addr += towrite; 6287 } 6288 out: 6289 return r; 6290 } 6291 6292 static int emulator_write_std(struct x86_emulate_ctxt *ctxt, gva_t addr, void *val, 6293 unsigned int bytes, struct x86_exception *exception, 6294 bool system) 6295 { 6296 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 6297 u32 access = PFERR_WRITE_MASK; 6298 6299 if (!system && static_call(kvm_x86_get_cpl)(vcpu) == 3) 6300 access |= PFERR_USER_MASK; 6301 6302 return kvm_write_guest_virt_helper(addr, val, bytes, vcpu, 6303 access, exception); 6304 } 6305 6306 int kvm_write_guest_virt_system(struct kvm_vcpu *vcpu, gva_t addr, void *val, 6307 unsigned int bytes, struct x86_exception *exception) 6308 { 6309 /* kvm_write_guest_virt_system can pull in tons of pages. */ 6310 vcpu->arch.l1tf_flush_l1d = true; 6311 6312 return kvm_write_guest_virt_helper(addr, val, bytes, vcpu, 6313 PFERR_WRITE_MASK, exception); 6314 } 6315 EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system); 6316 6317 int handle_ud(struct kvm_vcpu *vcpu) 6318 { 6319 static const char kvm_emulate_prefix[] = { __KVM_EMULATE_PREFIX }; 6320 int emul_type = EMULTYPE_TRAP_UD; 6321 char sig[5]; /* ud2; .ascii "kvm" */ 6322 struct x86_exception e; 6323 6324 if (unlikely(!static_call(kvm_x86_can_emulate_instruction)(vcpu, NULL, 0))) 6325 return 1; 6326 6327 if (force_emulation_prefix && 6328 kvm_read_guest_virt(vcpu, kvm_get_linear_rip(vcpu), 6329 sig, sizeof(sig), &e) == 0 && 6330 memcmp(sig, kvm_emulate_prefix, sizeof(sig)) == 0) { 6331 kvm_rip_write(vcpu, kvm_rip_read(vcpu) + sizeof(sig)); 6332 emul_type = EMULTYPE_TRAP_UD_FORCED; 6333 } 6334 6335 return kvm_emulate_instruction(vcpu, emul_type); 6336 } 6337 EXPORT_SYMBOL_GPL(handle_ud); 6338 6339 static int vcpu_is_mmio_gpa(struct kvm_vcpu *vcpu, unsigned long gva, 6340 gpa_t gpa, bool write) 6341 { 6342 /* For APIC access vmexit */ 6343 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE) 6344 return 1; 6345 6346 if (vcpu_match_mmio_gpa(vcpu, gpa)) { 6347 trace_vcpu_match_mmio(gva, gpa, write, true); 6348 return 1; 6349 } 6350 6351 return 0; 6352 } 6353 6354 static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva, 6355 gpa_t *gpa, struct x86_exception *exception, 6356 bool write) 6357 { 6358 u32 access = ((static_call(kvm_x86_get_cpl)(vcpu) == 3) ? PFERR_USER_MASK : 0) 6359 | (write ? PFERR_WRITE_MASK : 0); 6360 6361 /* 6362 * currently PKRU is only applied to ept enabled guest so 6363 * there is no pkey in EPT page table for L1 guest or EPT 6364 * shadow page table for L2 guest. 6365 */ 6366 if (vcpu_match_mmio_gva(vcpu, gva) 6367 && !permission_fault(vcpu, vcpu->arch.walk_mmu, 6368 vcpu->arch.mmio_access, 0, access)) { 6369 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT | 6370 (gva & (PAGE_SIZE - 1)); 6371 trace_vcpu_match_mmio(gva, *gpa, write, false); 6372 return 1; 6373 } 6374 6375 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception); 6376 6377 if (*gpa == UNMAPPED_GVA) 6378 return -1; 6379 6380 return vcpu_is_mmio_gpa(vcpu, gva, *gpa, write); 6381 } 6382 6383 int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa, 6384 const void *val, int bytes) 6385 { 6386 int ret; 6387 6388 ret = kvm_vcpu_write_guest(vcpu, gpa, val, bytes); 6389 if (ret < 0) 6390 return 0; 6391 kvm_page_track_write(vcpu, gpa, val, bytes); 6392 return 1; 6393 } 6394 6395 struct read_write_emulator_ops { 6396 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val, 6397 int bytes); 6398 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa, 6399 void *val, int bytes); 6400 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa, 6401 int bytes, void *val); 6402 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa, 6403 void *val, int bytes); 6404 bool write; 6405 }; 6406 6407 static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes) 6408 { 6409 if (vcpu->mmio_read_completed) { 6410 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes, 6411 vcpu->mmio_fragments[0].gpa, val); 6412 vcpu->mmio_read_completed = 0; 6413 return 1; 6414 } 6415 6416 return 0; 6417 } 6418 6419 static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa, 6420 void *val, int bytes) 6421 { 6422 return !kvm_vcpu_read_guest(vcpu, gpa, val, bytes); 6423 } 6424 6425 static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa, 6426 void *val, int bytes) 6427 { 6428 return emulator_write_phys(vcpu, gpa, val, bytes); 6429 } 6430 6431 static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val) 6432 { 6433 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, val); 6434 return vcpu_mmio_write(vcpu, gpa, bytes, val); 6435 } 6436 6437 static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, 6438 void *val, int bytes) 6439 { 6440 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, NULL); 6441 return X86EMUL_IO_NEEDED; 6442 } 6443 6444 static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, 6445 void *val, int bytes) 6446 { 6447 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0]; 6448 6449 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len)); 6450 return X86EMUL_CONTINUE; 6451 } 6452 6453 static const struct read_write_emulator_ops read_emultor = { 6454 .read_write_prepare = read_prepare, 6455 .read_write_emulate = read_emulate, 6456 .read_write_mmio = vcpu_mmio_read, 6457 .read_write_exit_mmio = read_exit_mmio, 6458 }; 6459 6460 static const struct read_write_emulator_ops write_emultor = { 6461 .read_write_emulate = write_emulate, 6462 .read_write_mmio = write_mmio, 6463 .read_write_exit_mmio = write_exit_mmio, 6464 .write = true, 6465 }; 6466 6467 static int emulator_read_write_onepage(unsigned long addr, void *val, 6468 unsigned int bytes, 6469 struct x86_exception *exception, 6470 struct kvm_vcpu *vcpu, 6471 const struct read_write_emulator_ops *ops) 6472 { 6473 gpa_t gpa; 6474 int handled, ret; 6475 bool write = ops->write; 6476 struct kvm_mmio_fragment *frag; 6477 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt; 6478 6479 /* 6480 * If the exit was due to a NPF we may already have a GPA. 6481 * If the GPA is present, use it to avoid the GVA to GPA table walk. 6482 * Note, this cannot be used on string operations since string 6483 * operation using rep will only have the initial GPA from the NPF 6484 * occurred. 6485 */ 6486 if (ctxt->gpa_available && emulator_can_use_gpa(ctxt) && 6487 (addr & ~PAGE_MASK) == (ctxt->gpa_val & ~PAGE_MASK)) { 6488 gpa = ctxt->gpa_val; 6489 ret = vcpu_is_mmio_gpa(vcpu, addr, gpa, write); 6490 } else { 6491 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write); 6492 if (ret < 0) 6493 return X86EMUL_PROPAGATE_FAULT; 6494 } 6495 6496 if (!ret && ops->read_write_emulate(vcpu, gpa, val, bytes)) 6497 return X86EMUL_CONTINUE; 6498 6499 /* 6500 * Is this MMIO handled locally? 6501 */ 6502 handled = ops->read_write_mmio(vcpu, gpa, bytes, val); 6503 if (handled == bytes) 6504 return X86EMUL_CONTINUE; 6505 6506 gpa += handled; 6507 bytes -= handled; 6508 val += handled; 6509 6510 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS); 6511 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++]; 6512 frag->gpa = gpa; 6513 frag->data = val; 6514 frag->len = bytes; 6515 return X86EMUL_CONTINUE; 6516 } 6517 6518 static int emulator_read_write(struct x86_emulate_ctxt *ctxt, 6519 unsigned long addr, 6520 void *val, unsigned int bytes, 6521 struct x86_exception *exception, 6522 const struct read_write_emulator_ops *ops) 6523 { 6524 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 6525 gpa_t gpa; 6526 int rc; 6527 6528 if (ops->read_write_prepare && 6529 ops->read_write_prepare(vcpu, val, bytes)) 6530 return X86EMUL_CONTINUE; 6531 6532 vcpu->mmio_nr_fragments = 0; 6533 6534 /* Crossing a page boundary? */ 6535 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) { 6536 int now; 6537 6538 now = -addr & ~PAGE_MASK; 6539 rc = emulator_read_write_onepage(addr, val, now, exception, 6540 vcpu, ops); 6541 6542 if (rc != X86EMUL_CONTINUE) 6543 return rc; 6544 addr += now; 6545 if (ctxt->mode != X86EMUL_MODE_PROT64) 6546 addr = (u32)addr; 6547 val += now; 6548 bytes -= now; 6549 } 6550 6551 rc = emulator_read_write_onepage(addr, val, bytes, exception, 6552 vcpu, ops); 6553 if (rc != X86EMUL_CONTINUE) 6554 return rc; 6555 6556 if (!vcpu->mmio_nr_fragments) 6557 return rc; 6558 6559 gpa = vcpu->mmio_fragments[0].gpa; 6560 6561 vcpu->mmio_needed = 1; 6562 vcpu->mmio_cur_fragment = 0; 6563 6564 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len); 6565 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write; 6566 vcpu->run->exit_reason = KVM_EXIT_MMIO; 6567 vcpu->run->mmio.phys_addr = gpa; 6568 6569 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes); 6570 } 6571 6572 static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt, 6573 unsigned long addr, 6574 void *val, 6575 unsigned int bytes, 6576 struct x86_exception *exception) 6577 { 6578 return emulator_read_write(ctxt, addr, val, bytes, 6579 exception, &read_emultor); 6580 } 6581 6582 static int emulator_write_emulated(struct x86_emulate_ctxt *ctxt, 6583 unsigned long addr, 6584 const void *val, 6585 unsigned int bytes, 6586 struct x86_exception *exception) 6587 { 6588 return emulator_read_write(ctxt, addr, (void *)val, bytes, 6589 exception, &write_emultor); 6590 } 6591 6592 #define CMPXCHG_TYPE(t, ptr, old, new) \ 6593 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old)) 6594 6595 #ifdef CONFIG_X86_64 6596 # define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new) 6597 #else 6598 # define CMPXCHG64(ptr, old, new) \ 6599 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old)) 6600 #endif 6601 6602 static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt, 6603 unsigned long addr, 6604 const void *old, 6605 const void *new, 6606 unsigned int bytes, 6607 struct x86_exception *exception) 6608 { 6609 struct kvm_host_map map; 6610 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 6611 u64 page_line_mask; 6612 gpa_t gpa; 6613 char *kaddr; 6614 bool exchanged; 6615 6616 /* guests cmpxchg8b have to be emulated atomically */ 6617 if (bytes > 8 || (bytes & (bytes - 1))) 6618 goto emul_write; 6619 6620 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL); 6621 6622 if (gpa == UNMAPPED_GVA || 6623 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE) 6624 goto emul_write; 6625 6626 /* 6627 * Emulate the atomic as a straight write to avoid #AC if SLD is 6628 * enabled in the host and the access splits a cache line. 6629 */ 6630 if (boot_cpu_has(X86_FEATURE_SPLIT_LOCK_DETECT)) 6631 page_line_mask = ~(cache_line_size() - 1); 6632 else 6633 page_line_mask = PAGE_MASK; 6634 6635 if (((gpa + bytes - 1) & page_line_mask) != (gpa & page_line_mask)) 6636 goto emul_write; 6637 6638 if (kvm_vcpu_map(vcpu, gpa_to_gfn(gpa), &map)) 6639 goto emul_write; 6640 6641 kaddr = map.hva + offset_in_page(gpa); 6642 6643 switch (bytes) { 6644 case 1: 6645 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new); 6646 break; 6647 case 2: 6648 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new); 6649 break; 6650 case 4: 6651 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new); 6652 break; 6653 case 8: 6654 exchanged = CMPXCHG64(kaddr, old, new); 6655 break; 6656 default: 6657 BUG(); 6658 } 6659 6660 kvm_vcpu_unmap(vcpu, &map, true); 6661 6662 if (!exchanged) 6663 return X86EMUL_CMPXCHG_FAILED; 6664 6665 kvm_page_track_write(vcpu, gpa, new, bytes); 6666 6667 return X86EMUL_CONTINUE; 6668 6669 emul_write: 6670 printk_once(KERN_WARNING "kvm: emulating exchange as write\n"); 6671 6672 return emulator_write_emulated(ctxt, addr, new, bytes, exception); 6673 } 6674 6675 static int kernel_pio(struct kvm_vcpu *vcpu, void *pd) 6676 { 6677 int r = 0, i; 6678 6679 for (i = 0; i < vcpu->arch.pio.count; i++) { 6680 if (vcpu->arch.pio.in) 6681 r = kvm_io_bus_read(vcpu, KVM_PIO_BUS, vcpu->arch.pio.port, 6682 vcpu->arch.pio.size, pd); 6683 else 6684 r = kvm_io_bus_write(vcpu, KVM_PIO_BUS, 6685 vcpu->arch.pio.port, vcpu->arch.pio.size, 6686 pd); 6687 if (r) 6688 break; 6689 pd += vcpu->arch.pio.size; 6690 } 6691 return r; 6692 } 6693 6694 static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size, 6695 unsigned short port, void *val, 6696 unsigned int count, bool in) 6697 { 6698 vcpu->arch.pio.port = port; 6699 vcpu->arch.pio.in = in; 6700 vcpu->arch.pio.count = count; 6701 vcpu->arch.pio.size = size; 6702 6703 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) { 6704 vcpu->arch.pio.count = 0; 6705 return 1; 6706 } 6707 6708 vcpu->run->exit_reason = KVM_EXIT_IO; 6709 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT; 6710 vcpu->run->io.size = size; 6711 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE; 6712 vcpu->run->io.count = count; 6713 vcpu->run->io.port = port; 6714 6715 return 0; 6716 } 6717 6718 static int emulator_pio_in(struct kvm_vcpu *vcpu, int size, 6719 unsigned short port, void *val, unsigned int count) 6720 { 6721 int ret; 6722 6723 if (vcpu->arch.pio.count) 6724 goto data_avail; 6725 6726 memset(vcpu->arch.pio_data, 0, size * count); 6727 6728 ret = emulator_pio_in_out(vcpu, size, port, val, count, true); 6729 if (ret) { 6730 data_avail: 6731 memcpy(val, vcpu->arch.pio_data, size * count); 6732 trace_kvm_pio(KVM_PIO_IN, port, size, count, vcpu->arch.pio_data); 6733 vcpu->arch.pio.count = 0; 6734 return 1; 6735 } 6736 6737 return 0; 6738 } 6739 6740 static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt, 6741 int size, unsigned short port, void *val, 6742 unsigned int count) 6743 { 6744 return emulator_pio_in(emul_to_vcpu(ctxt), size, port, val, count); 6745 6746 } 6747 6748 static int emulator_pio_out(struct kvm_vcpu *vcpu, int size, 6749 unsigned short port, const void *val, 6750 unsigned int count) 6751 { 6752 memcpy(vcpu->arch.pio_data, val, size * count); 6753 trace_kvm_pio(KVM_PIO_OUT, port, size, count, vcpu->arch.pio_data); 6754 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false); 6755 } 6756 6757 static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt, 6758 int size, unsigned short port, 6759 const void *val, unsigned int count) 6760 { 6761 return emulator_pio_out(emul_to_vcpu(ctxt), size, port, val, count); 6762 } 6763 6764 static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg) 6765 { 6766 return static_call(kvm_x86_get_segment_base)(vcpu, seg); 6767 } 6768 6769 static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address) 6770 { 6771 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address); 6772 } 6773 6774 static int kvm_emulate_wbinvd_noskip(struct kvm_vcpu *vcpu) 6775 { 6776 if (!need_emulate_wbinvd(vcpu)) 6777 return X86EMUL_CONTINUE; 6778 6779 if (static_call(kvm_x86_has_wbinvd_exit)()) { 6780 int cpu = get_cpu(); 6781 6782 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask); 6783 on_each_cpu_mask(vcpu->arch.wbinvd_dirty_mask, 6784 wbinvd_ipi, NULL, 1); 6785 put_cpu(); 6786 cpumask_clear(vcpu->arch.wbinvd_dirty_mask); 6787 } else 6788 wbinvd(); 6789 return X86EMUL_CONTINUE; 6790 } 6791 6792 int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu) 6793 { 6794 kvm_emulate_wbinvd_noskip(vcpu); 6795 return kvm_skip_emulated_instruction(vcpu); 6796 } 6797 EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd); 6798 6799 6800 6801 static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt) 6802 { 6803 kvm_emulate_wbinvd_noskip(emul_to_vcpu(ctxt)); 6804 } 6805 6806 static void emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr, 6807 unsigned long *dest) 6808 { 6809 kvm_get_dr(emul_to_vcpu(ctxt), dr, dest); 6810 } 6811 6812 static int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr, 6813 unsigned long value) 6814 { 6815 6816 return kvm_set_dr(emul_to_vcpu(ctxt), dr, value); 6817 } 6818 6819 static u64 mk_cr_64(u64 curr_cr, u32 new_val) 6820 { 6821 return (curr_cr & ~((1ULL << 32) - 1)) | new_val; 6822 } 6823 6824 static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr) 6825 { 6826 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 6827 unsigned long value; 6828 6829 switch (cr) { 6830 case 0: 6831 value = kvm_read_cr0(vcpu); 6832 break; 6833 case 2: 6834 value = vcpu->arch.cr2; 6835 break; 6836 case 3: 6837 value = kvm_read_cr3(vcpu); 6838 break; 6839 case 4: 6840 value = kvm_read_cr4(vcpu); 6841 break; 6842 case 8: 6843 value = kvm_get_cr8(vcpu); 6844 break; 6845 default: 6846 kvm_err("%s: unexpected cr %u\n", __func__, cr); 6847 return 0; 6848 } 6849 6850 return value; 6851 } 6852 6853 static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val) 6854 { 6855 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 6856 int res = 0; 6857 6858 switch (cr) { 6859 case 0: 6860 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val)); 6861 break; 6862 case 2: 6863 vcpu->arch.cr2 = val; 6864 break; 6865 case 3: 6866 res = kvm_set_cr3(vcpu, val); 6867 break; 6868 case 4: 6869 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val)); 6870 break; 6871 case 8: 6872 res = kvm_set_cr8(vcpu, val); 6873 break; 6874 default: 6875 kvm_err("%s: unexpected cr %u\n", __func__, cr); 6876 res = -1; 6877 } 6878 6879 return res; 6880 } 6881 6882 static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt) 6883 { 6884 return static_call(kvm_x86_get_cpl)(emul_to_vcpu(ctxt)); 6885 } 6886 6887 static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt) 6888 { 6889 static_call(kvm_x86_get_gdt)(emul_to_vcpu(ctxt), dt); 6890 } 6891 6892 static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt) 6893 { 6894 static_call(kvm_x86_get_idt)(emul_to_vcpu(ctxt), dt); 6895 } 6896 6897 static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt) 6898 { 6899 static_call(kvm_x86_set_gdt)(emul_to_vcpu(ctxt), dt); 6900 } 6901 6902 static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt) 6903 { 6904 static_call(kvm_x86_set_idt)(emul_to_vcpu(ctxt), dt); 6905 } 6906 6907 static unsigned long emulator_get_cached_segment_base( 6908 struct x86_emulate_ctxt *ctxt, int seg) 6909 { 6910 return get_segment_base(emul_to_vcpu(ctxt), seg); 6911 } 6912 6913 static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector, 6914 struct desc_struct *desc, u32 *base3, 6915 int seg) 6916 { 6917 struct kvm_segment var; 6918 6919 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg); 6920 *selector = var.selector; 6921 6922 if (var.unusable) { 6923 memset(desc, 0, sizeof(*desc)); 6924 if (base3) 6925 *base3 = 0; 6926 return false; 6927 } 6928 6929 if (var.g) 6930 var.limit >>= 12; 6931 set_desc_limit(desc, var.limit); 6932 set_desc_base(desc, (unsigned long)var.base); 6933 #ifdef CONFIG_X86_64 6934 if (base3) 6935 *base3 = var.base >> 32; 6936 #endif 6937 desc->type = var.type; 6938 desc->s = var.s; 6939 desc->dpl = var.dpl; 6940 desc->p = var.present; 6941 desc->avl = var.avl; 6942 desc->l = var.l; 6943 desc->d = var.db; 6944 desc->g = var.g; 6945 6946 return true; 6947 } 6948 6949 static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector, 6950 struct desc_struct *desc, u32 base3, 6951 int seg) 6952 { 6953 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 6954 struct kvm_segment var; 6955 6956 var.selector = selector; 6957 var.base = get_desc_base(desc); 6958 #ifdef CONFIG_X86_64 6959 var.base |= ((u64)base3) << 32; 6960 #endif 6961 var.limit = get_desc_limit(desc); 6962 if (desc->g) 6963 var.limit = (var.limit << 12) | 0xfff; 6964 var.type = desc->type; 6965 var.dpl = desc->dpl; 6966 var.db = desc->d; 6967 var.s = desc->s; 6968 var.l = desc->l; 6969 var.g = desc->g; 6970 var.avl = desc->avl; 6971 var.present = desc->p; 6972 var.unusable = !var.present; 6973 var.padding = 0; 6974 6975 kvm_set_segment(vcpu, &var, seg); 6976 return; 6977 } 6978 6979 static int emulator_get_msr(struct x86_emulate_ctxt *ctxt, 6980 u32 msr_index, u64 *pdata) 6981 { 6982 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 6983 int r; 6984 6985 r = kvm_get_msr(vcpu, msr_index, pdata); 6986 6987 if (r && kvm_get_msr_user_space(vcpu, msr_index, r)) { 6988 /* Bounce to user space */ 6989 return X86EMUL_IO_NEEDED; 6990 } 6991 6992 return r; 6993 } 6994 6995 static int emulator_set_msr(struct x86_emulate_ctxt *ctxt, 6996 u32 msr_index, u64 data) 6997 { 6998 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 6999 int r; 7000 7001 r = kvm_set_msr(vcpu, msr_index, data); 7002 7003 if (r && kvm_set_msr_user_space(vcpu, msr_index, data, r)) { 7004 /* Bounce to user space */ 7005 return X86EMUL_IO_NEEDED; 7006 } 7007 7008 return r; 7009 } 7010 7011 static u64 emulator_get_smbase(struct x86_emulate_ctxt *ctxt) 7012 { 7013 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 7014 7015 return vcpu->arch.smbase; 7016 } 7017 7018 static void emulator_set_smbase(struct x86_emulate_ctxt *ctxt, u64 smbase) 7019 { 7020 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 7021 7022 vcpu->arch.smbase = smbase; 7023 } 7024 7025 static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt, 7026 u32 pmc) 7027 { 7028 return kvm_pmu_is_valid_rdpmc_ecx(emul_to_vcpu(ctxt), pmc); 7029 } 7030 7031 static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt, 7032 u32 pmc, u64 *pdata) 7033 { 7034 return kvm_pmu_rdpmc(emul_to_vcpu(ctxt), pmc, pdata); 7035 } 7036 7037 static void emulator_halt(struct x86_emulate_ctxt *ctxt) 7038 { 7039 emul_to_vcpu(ctxt)->arch.halt_request = 1; 7040 } 7041 7042 static int emulator_intercept(struct x86_emulate_ctxt *ctxt, 7043 struct x86_instruction_info *info, 7044 enum x86_intercept_stage stage) 7045 { 7046 return static_call(kvm_x86_check_intercept)(emul_to_vcpu(ctxt), info, stage, 7047 &ctxt->exception); 7048 } 7049 7050 static bool emulator_get_cpuid(struct x86_emulate_ctxt *ctxt, 7051 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx, 7052 bool exact_only) 7053 { 7054 return kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx, exact_only); 7055 } 7056 7057 static bool emulator_guest_has_long_mode(struct x86_emulate_ctxt *ctxt) 7058 { 7059 return guest_cpuid_has(emul_to_vcpu(ctxt), X86_FEATURE_LM); 7060 } 7061 7062 static bool emulator_guest_has_movbe(struct x86_emulate_ctxt *ctxt) 7063 { 7064 return guest_cpuid_has(emul_to_vcpu(ctxt), X86_FEATURE_MOVBE); 7065 } 7066 7067 static bool emulator_guest_has_fxsr(struct x86_emulate_ctxt *ctxt) 7068 { 7069 return guest_cpuid_has(emul_to_vcpu(ctxt), X86_FEATURE_FXSR); 7070 } 7071 7072 static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg) 7073 { 7074 return kvm_register_read_raw(emul_to_vcpu(ctxt), reg); 7075 } 7076 7077 static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val) 7078 { 7079 kvm_register_write_raw(emul_to_vcpu(ctxt), reg, val); 7080 } 7081 7082 static void emulator_set_nmi_mask(struct x86_emulate_ctxt *ctxt, bool masked) 7083 { 7084 static_call(kvm_x86_set_nmi_mask)(emul_to_vcpu(ctxt), masked); 7085 } 7086 7087 static unsigned emulator_get_hflags(struct x86_emulate_ctxt *ctxt) 7088 { 7089 return emul_to_vcpu(ctxt)->arch.hflags; 7090 } 7091 7092 static void emulator_set_hflags(struct x86_emulate_ctxt *ctxt, unsigned emul_flags) 7093 { 7094 emul_to_vcpu(ctxt)->arch.hflags = emul_flags; 7095 } 7096 7097 static int emulator_pre_leave_smm(struct x86_emulate_ctxt *ctxt, 7098 const char *smstate) 7099 { 7100 return static_call(kvm_x86_pre_leave_smm)(emul_to_vcpu(ctxt), smstate); 7101 } 7102 7103 static void emulator_post_leave_smm(struct x86_emulate_ctxt *ctxt) 7104 { 7105 kvm_smm_changed(emul_to_vcpu(ctxt)); 7106 } 7107 7108 static int emulator_set_xcr(struct x86_emulate_ctxt *ctxt, u32 index, u64 xcr) 7109 { 7110 return __kvm_set_xcr(emul_to_vcpu(ctxt), index, xcr); 7111 } 7112 7113 static const struct x86_emulate_ops emulate_ops = { 7114 .read_gpr = emulator_read_gpr, 7115 .write_gpr = emulator_write_gpr, 7116 .read_std = emulator_read_std, 7117 .write_std = emulator_write_std, 7118 .read_phys = kvm_read_guest_phys_system, 7119 .fetch = kvm_fetch_guest_virt, 7120 .read_emulated = emulator_read_emulated, 7121 .write_emulated = emulator_write_emulated, 7122 .cmpxchg_emulated = emulator_cmpxchg_emulated, 7123 .invlpg = emulator_invlpg, 7124 .pio_in_emulated = emulator_pio_in_emulated, 7125 .pio_out_emulated = emulator_pio_out_emulated, 7126 .get_segment = emulator_get_segment, 7127 .set_segment = emulator_set_segment, 7128 .get_cached_segment_base = emulator_get_cached_segment_base, 7129 .get_gdt = emulator_get_gdt, 7130 .get_idt = emulator_get_idt, 7131 .set_gdt = emulator_set_gdt, 7132 .set_idt = emulator_set_idt, 7133 .get_cr = emulator_get_cr, 7134 .set_cr = emulator_set_cr, 7135 .cpl = emulator_get_cpl, 7136 .get_dr = emulator_get_dr, 7137 .set_dr = emulator_set_dr, 7138 .get_smbase = emulator_get_smbase, 7139 .set_smbase = emulator_set_smbase, 7140 .set_msr = emulator_set_msr, 7141 .get_msr = emulator_get_msr, 7142 .check_pmc = emulator_check_pmc, 7143 .read_pmc = emulator_read_pmc, 7144 .halt = emulator_halt, 7145 .wbinvd = emulator_wbinvd, 7146 .fix_hypercall = emulator_fix_hypercall, 7147 .intercept = emulator_intercept, 7148 .get_cpuid = emulator_get_cpuid, 7149 .guest_has_long_mode = emulator_guest_has_long_mode, 7150 .guest_has_movbe = emulator_guest_has_movbe, 7151 .guest_has_fxsr = emulator_guest_has_fxsr, 7152 .set_nmi_mask = emulator_set_nmi_mask, 7153 .get_hflags = emulator_get_hflags, 7154 .set_hflags = emulator_set_hflags, 7155 .pre_leave_smm = emulator_pre_leave_smm, 7156 .post_leave_smm = emulator_post_leave_smm, 7157 .set_xcr = emulator_set_xcr, 7158 }; 7159 7160 static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask) 7161 { 7162 u32 int_shadow = static_call(kvm_x86_get_interrupt_shadow)(vcpu); 7163 /* 7164 * an sti; sti; sequence only disable interrupts for the first 7165 * instruction. So, if the last instruction, be it emulated or 7166 * not, left the system with the INT_STI flag enabled, it 7167 * means that the last instruction is an sti. We should not 7168 * leave the flag on in this case. The same goes for mov ss 7169 */ 7170 if (int_shadow & mask) 7171 mask = 0; 7172 if (unlikely(int_shadow || mask)) { 7173 static_call(kvm_x86_set_interrupt_shadow)(vcpu, mask); 7174 if (!mask) 7175 kvm_make_request(KVM_REQ_EVENT, vcpu); 7176 } 7177 } 7178 7179 static bool inject_emulated_exception(struct kvm_vcpu *vcpu) 7180 { 7181 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt; 7182 if (ctxt->exception.vector == PF_VECTOR) 7183 return kvm_inject_emulated_page_fault(vcpu, &ctxt->exception); 7184 7185 if (ctxt->exception.error_code_valid) 7186 kvm_queue_exception_e(vcpu, ctxt->exception.vector, 7187 ctxt->exception.error_code); 7188 else 7189 kvm_queue_exception(vcpu, ctxt->exception.vector); 7190 return false; 7191 } 7192 7193 static struct x86_emulate_ctxt *alloc_emulate_ctxt(struct kvm_vcpu *vcpu) 7194 { 7195 struct x86_emulate_ctxt *ctxt; 7196 7197 ctxt = kmem_cache_zalloc(x86_emulator_cache, GFP_KERNEL_ACCOUNT); 7198 if (!ctxt) { 7199 pr_err("kvm: failed to allocate vcpu's emulator\n"); 7200 return NULL; 7201 } 7202 7203 ctxt->vcpu = vcpu; 7204 ctxt->ops = &emulate_ops; 7205 vcpu->arch.emulate_ctxt = ctxt; 7206 7207 return ctxt; 7208 } 7209 7210 static void init_emulate_ctxt(struct kvm_vcpu *vcpu) 7211 { 7212 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt; 7213 int cs_db, cs_l; 7214 7215 static_call(kvm_x86_get_cs_db_l_bits)(vcpu, &cs_db, &cs_l); 7216 7217 ctxt->gpa_available = false; 7218 ctxt->eflags = kvm_get_rflags(vcpu); 7219 ctxt->tf = (ctxt->eflags & X86_EFLAGS_TF) != 0; 7220 7221 ctxt->eip = kvm_rip_read(vcpu); 7222 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL : 7223 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 : 7224 (cs_l && is_long_mode(vcpu)) ? X86EMUL_MODE_PROT64 : 7225 cs_db ? X86EMUL_MODE_PROT32 : 7226 X86EMUL_MODE_PROT16; 7227 BUILD_BUG_ON(HF_GUEST_MASK != X86EMUL_GUEST_MASK); 7228 BUILD_BUG_ON(HF_SMM_MASK != X86EMUL_SMM_MASK); 7229 BUILD_BUG_ON(HF_SMM_INSIDE_NMI_MASK != X86EMUL_SMM_INSIDE_NMI_MASK); 7230 7231 ctxt->interruptibility = 0; 7232 ctxt->have_exception = false; 7233 ctxt->exception.vector = -1; 7234 ctxt->perm_ok = false; 7235 7236 init_decode_cache(ctxt); 7237 vcpu->arch.emulate_regs_need_sync_from_vcpu = false; 7238 } 7239 7240 void kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip) 7241 { 7242 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt; 7243 int ret; 7244 7245 init_emulate_ctxt(vcpu); 7246 7247 ctxt->op_bytes = 2; 7248 ctxt->ad_bytes = 2; 7249 ctxt->_eip = ctxt->eip + inc_eip; 7250 ret = emulate_int_real(ctxt, irq); 7251 7252 if (ret != X86EMUL_CONTINUE) { 7253 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); 7254 } else { 7255 ctxt->eip = ctxt->_eip; 7256 kvm_rip_write(vcpu, ctxt->eip); 7257 kvm_set_rflags(vcpu, ctxt->eflags); 7258 } 7259 } 7260 EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt); 7261 7262 static int handle_emulation_failure(struct kvm_vcpu *vcpu, int emulation_type) 7263 { 7264 ++vcpu->stat.insn_emulation_fail; 7265 trace_kvm_emulate_insn_failed(vcpu); 7266 7267 if (emulation_type & EMULTYPE_VMWARE_GP) { 7268 kvm_queue_exception_e(vcpu, GP_VECTOR, 0); 7269 return 1; 7270 } 7271 7272 if (emulation_type & EMULTYPE_SKIP) { 7273 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR; 7274 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION; 7275 vcpu->run->internal.ndata = 0; 7276 return 0; 7277 } 7278 7279 kvm_queue_exception(vcpu, UD_VECTOR); 7280 7281 if (!is_guest_mode(vcpu) && static_call(kvm_x86_get_cpl)(vcpu) == 0) { 7282 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR; 7283 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION; 7284 vcpu->run->internal.ndata = 0; 7285 return 0; 7286 } 7287 7288 return 1; 7289 } 7290 7291 static bool reexecute_instruction(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa, 7292 bool write_fault_to_shadow_pgtable, 7293 int emulation_type) 7294 { 7295 gpa_t gpa = cr2_or_gpa; 7296 kvm_pfn_t pfn; 7297 7298 if (!(emulation_type & EMULTYPE_ALLOW_RETRY_PF)) 7299 return false; 7300 7301 if (WARN_ON_ONCE(is_guest_mode(vcpu)) || 7302 WARN_ON_ONCE(!(emulation_type & EMULTYPE_PF))) 7303 return false; 7304 7305 if (!vcpu->arch.mmu->direct_map) { 7306 /* 7307 * Write permission should be allowed since only 7308 * write access need to be emulated. 7309 */ 7310 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2_or_gpa, NULL); 7311 7312 /* 7313 * If the mapping is invalid in guest, let cpu retry 7314 * it to generate fault. 7315 */ 7316 if (gpa == UNMAPPED_GVA) 7317 return true; 7318 } 7319 7320 /* 7321 * Do not retry the unhandleable instruction if it faults on the 7322 * readonly host memory, otherwise it will goto a infinite loop: 7323 * retry instruction -> write #PF -> emulation fail -> retry 7324 * instruction -> ... 7325 */ 7326 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa)); 7327 7328 /* 7329 * If the instruction failed on the error pfn, it can not be fixed, 7330 * report the error to userspace. 7331 */ 7332 if (is_error_noslot_pfn(pfn)) 7333 return false; 7334 7335 kvm_release_pfn_clean(pfn); 7336 7337 /* The instructions are well-emulated on direct mmu. */ 7338 if (vcpu->arch.mmu->direct_map) { 7339 unsigned int indirect_shadow_pages; 7340 7341 write_lock(&vcpu->kvm->mmu_lock); 7342 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages; 7343 write_unlock(&vcpu->kvm->mmu_lock); 7344 7345 if (indirect_shadow_pages) 7346 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa)); 7347 7348 return true; 7349 } 7350 7351 /* 7352 * if emulation was due to access to shadowed page table 7353 * and it failed try to unshadow page and re-enter the 7354 * guest to let CPU execute the instruction. 7355 */ 7356 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa)); 7357 7358 /* 7359 * If the access faults on its page table, it can not 7360 * be fixed by unprotecting shadow page and it should 7361 * be reported to userspace. 7362 */ 7363 return !write_fault_to_shadow_pgtable; 7364 } 7365 7366 static bool retry_instruction(struct x86_emulate_ctxt *ctxt, 7367 gpa_t cr2_or_gpa, int emulation_type) 7368 { 7369 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 7370 unsigned long last_retry_eip, last_retry_addr, gpa = cr2_or_gpa; 7371 7372 last_retry_eip = vcpu->arch.last_retry_eip; 7373 last_retry_addr = vcpu->arch.last_retry_addr; 7374 7375 /* 7376 * If the emulation is caused by #PF and it is non-page_table 7377 * writing instruction, it means the VM-EXIT is caused by shadow 7378 * page protected, we can zap the shadow page and retry this 7379 * instruction directly. 7380 * 7381 * Note: if the guest uses a non-page-table modifying instruction 7382 * on the PDE that points to the instruction, then we will unmap 7383 * the instruction and go to an infinite loop. So, we cache the 7384 * last retried eip and the last fault address, if we meet the eip 7385 * and the address again, we can break out of the potential infinite 7386 * loop. 7387 */ 7388 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0; 7389 7390 if (!(emulation_type & EMULTYPE_ALLOW_RETRY_PF)) 7391 return false; 7392 7393 if (WARN_ON_ONCE(is_guest_mode(vcpu)) || 7394 WARN_ON_ONCE(!(emulation_type & EMULTYPE_PF))) 7395 return false; 7396 7397 if (x86_page_table_writing_insn(ctxt)) 7398 return false; 7399 7400 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2_or_gpa) 7401 return false; 7402 7403 vcpu->arch.last_retry_eip = ctxt->eip; 7404 vcpu->arch.last_retry_addr = cr2_or_gpa; 7405 7406 if (!vcpu->arch.mmu->direct_map) 7407 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2_or_gpa, NULL); 7408 7409 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa)); 7410 7411 return true; 7412 } 7413 7414 static int complete_emulated_mmio(struct kvm_vcpu *vcpu); 7415 static int complete_emulated_pio(struct kvm_vcpu *vcpu); 7416 7417 static void kvm_smm_changed(struct kvm_vcpu *vcpu) 7418 { 7419 if (!(vcpu->arch.hflags & HF_SMM_MASK)) { 7420 /* This is a good place to trace that we are exiting SMM. */ 7421 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, false); 7422 7423 /* Process a latched INIT or SMI, if any. */ 7424 kvm_make_request(KVM_REQ_EVENT, vcpu); 7425 } 7426 7427 kvm_mmu_reset_context(vcpu); 7428 } 7429 7430 static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7, 7431 unsigned long *db) 7432 { 7433 u32 dr6 = 0; 7434 int i; 7435 u32 enable, rwlen; 7436 7437 enable = dr7; 7438 rwlen = dr7 >> 16; 7439 for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4) 7440 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr) 7441 dr6 |= (1 << i); 7442 return dr6; 7443 } 7444 7445 static int kvm_vcpu_do_singlestep(struct kvm_vcpu *vcpu) 7446 { 7447 struct kvm_run *kvm_run = vcpu->run; 7448 7449 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) { 7450 kvm_run->debug.arch.dr6 = DR6_BS | DR6_ACTIVE_LOW; 7451 kvm_run->debug.arch.pc = kvm_get_linear_rip(vcpu); 7452 kvm_run->debug.arch.exception = DB_VECTOR; 7453 kvm_run->exit_reason = KVM_EXIT_DEBUG; 7454 return 0; 7455 } 7456 kvm_queue_exception_p(vcpu, DB_VECTOR, DR6_BS); 7457 return 1; 7458 } 7459 7460 int kvm_skip_emulated_instruction(struct kvm_vcpu *vcpu) 7461 { 7462 unsigned long rflags = static_call(kvm_x86_get_rflags)(vcpu); 7463 int r; 7464 7465 r = static_call(kvm_x86_skip_emulated_instruction)(vcpu); 7466 if (unlikely(!r)) 7467 return 0; 7468 7469 /* 7470 * rflags is the old, "raw" value of the flags. The new value has 7471 * not been saved yet. 7472 * 7473 * This is correct even for TF set by the guest, because "the 7474 * processor will not generate this exception after the instruction 7475 * that sets the TF flag". 7476 */ 7477 if (unlikely(rflags & X86_EFLAGS_TF)) 7478 r = kvm_vcpu_do_singlestep(vcpu); 7479 return r; 7480 } 7481 EXPORT_SYMBOL_GPL(kvm_skip_emulated_instruction); 7482 7483 static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r) 7484 { 7485 if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) && 7486 (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) { 7487 struct kvm_run *kvm_run = vcpu->run; 7488 unsigned long eip = kvm_get_linear_rip(vcpu); 7489 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0, 7490 vcpu->arch.guest_debug_dr7, 7491 vcpu->arch.eff_db); 7492 7493 if (dr6 != 0) { 7494 kvm_run->debug.arch.dr6 = dr6 | DR6_ACTIVE_LOW; 7495 kvm_run->debug.arch.pc = eip; 7496 kvm_run->debug.arch.exception = DB_VECTOR; 7497 kvm_run->exit_reason = KVM_EXIT_DEBUG; 7498 *r = 0; 7499 return true; 7500 } 7501 } 7502 7503 if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) && 7504 !(kvm_get_rflags(vcpu) & X86_EFLAGS_RF)) { 7505 unsigned long eip = kvm_get_linear_rip(vcpu); 7506 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0, 7507 vcpu->arch.dr7, 7508 vcpu->arch.db); 7509 7510 if (dr6 != 0) { 7511 kvm_queue_exception_p(vcpu, DB_VECTOR, dr6); 7512 *r = 1; 7513 return true; 7514 } 7515 } 7516 7517 return false; 7518 } 7519 7520 static bool is_vmware_backdoor_opcode(struct x86_emulate_ctxt *ctxt) 7521 { 7522 switch (ctxt->opcode_len) { 7523 case 1: 7524 switch (ctxt->b) { 7525 case 0xe4: /* IN */ 7526 case 0xe5: 7527 case 0xec: 7528 case 0xed: 7529 case 0xe6: /* OUT */ 7530 case 0xe7: 7531 case 0xee: 7532 case 0xef: 7533 case 0x6c: /* INS */ 7534 case 0x6d: 7535 case 0x6e: /* OUTS */ 7536 case 0x6f: 7537 return true; 7538 } 7539 break; 7540 case 2: 7541 switch (ctxt->b) { 7542 case 0x33: /* RDPMC */ 7543 return true; 7544 } 7545 break; 7546 } 7547 7548 return false; 7549 } 7550 7551 /* 7552 * Decode to be emulated instruction. Return EMULATION_OK if success. 7553 */ 7554 int x86_decode_emulated_instruction(struct kvm_vcpu *vcpu, int emulation_type, 7555 void *insn, int insn_len) 7556 { 7557 int r = EMULATION_OK; 7558 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt; 7559 7560 init_emulate_ctxt(vcpu); 7561 7562 /* 7563 * We will reenter on the same instruction since we do not set 7564 * complete_userspace_io. This does not handle watchpoints yet, 7565 * those would be handled in the emulate_ops. 7566 */ 7567 if (!(emulation_type & EMULTYPE_SKIP) && 7568 kvm_vcpu_check_breakpoint(vcpu, &r)) 7569 return r; 7570 7571 r = x86_decode_insn(ctxt, insn, insn_len, emulation_type); 7572 7573 trace_kvm_emulate_insn_start(vcpu); 7574 ++vcpu->stat.insn_emulation; 7575 7576 return r; 7577 } 7578 EXPORT_SYMBOL_GPL(x86_decode_emulated_instruction); 7579 7580 int x86_emulate_instruction(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa, 7581 int emulation_type, void *insn, int insn_len) 7582 { 7583 int r; 7584 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt; 7585 bool writeback = true; 7586 bool write_fault_to_spt; 7587 7588 if (unlikely(!static_call(kvm_x86_can_emulate_instruction)(vcpu, insn, insn_len))) 7589 return 1; 7590 7591 vcpu->arch.l1tf_flush_l1d = true; 7592 7593 /* 7594 * Clear write_fault_to_shadow_pgtable here to ensure it is 7595 * never reused. 7596 */ 7597 write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable; 7598 vcpu->arch.write_fault_to_shadow_pgtable = false; 7599 7600 if (!(emulation_type & EMULTYPE_NO_DECODE)) { 7601 kvm_clear_exception_queue(vcpu); 7602 7603 r = x86_decode_emulated_instruction(vcpu, emulation_type, 7604 insn, insn_len); 7605 if (r != EMULATION_OK) { 7606 if ((emulation_type & EMULTYPE_TRAP_UD) || 7607 (emulation_type & EMULTYPE_TRAP_UD_FORCED)) { 7608 kvm_queue_exception(vcpu, UD_VECTOR); 7609 return 1; 7610 } 7611 if (reexecute_instruction(vcpu, cr2_or_gpa, 7612 write_fault_to_spt, 7613 emulation_type)) 7614 return 1; 7615 if (ctxt->have_exception) { 7616 /* 7617 * #UD should result in just EMULATION_FAILED, and trap-like 7618 * exception should not be encountered during decode. 7619 */ 7620 WARN_ON_ONCE(ctxt->exception.vector == UD_VECTOR || 7621 exception_type(ctxt->exception.vector) == EXCPT_TRAP); 7622 inject_emulated_exception(vcpu); 7623 return 1; 7624 } 7625 return handle_emulation_failure(vcpu, emulation_type); 7626 } 7627 } 7628 7629 if ((emulation_type & EMULTYPE_VMWARE_GP) && 7630 !is_vmware_backdoor_opcode(ctxt)) { 7631 kvm_queue_exception_e(vcpu, GP_VECTOR, 0); 7632 return 1; 7633 } 7634 7635 /* 7636 * Note, EMULTYPE_SKIP is intended for use *only* by vendor callbacks 7637 * for kvm_skip_emulated_instruction(). The caller is responsible for 7638 * updating interruptibility state and injecting single-step #DBs. 7639 */ 7640 if (emulation_type & EMULTYPE_SKIP) { 7641 kvm_rip_write(vcpu, ctxt->_eip); 7642 if (ctxt->eflags & X86_EFLAGS_RF) 7643 kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF); 7644 return 1; 7645 } 7646 7647 if (retry_instruction(ctxt, cr2_or_gpa, emulation_type)) 7648 return 1; 7649 7650 /* this is needed for vmware backdoor interface to work since it 7651 changes registers values during IO operation */ 7652 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) { 7653 vcpu->arch.emulate_regs_need_sync_from_vcpu = false; 7654 emulator_invalidate_register_cache(ctxt); 7655 } 7656 7657 restart: 7658 if (emulation_type & EMULTYPE_PF) { 7659 /* Save the faulting GPA (cr2) in the address field */ 7660 ctxt->exception.address = cr2_or_gpa; 7661 7662 /* With shadow page tables, cr2 contains a GVA or nGPA. */ 7663 if (vcpu->arch.mmu->direct_map) { 7664 ctxt->gpa_available = true; 7665 ctxt->gpa_val = cr2_or_gpa; 7666 } 7667 } else { 7668 /* Sanitize the address out of an abundance of paranoia. */ 7669 ctxt->exception.address = 0; 7670 } 7671 7672 r = x86_emulate_insn(ctxt); 7673 7674 if (r == EMULATION_INTERCEPTED) 7675 return 1; 7676 7677 if (r == EMULATION_FAILED) { 7678 if (reexecute_instruction(vcpu, cr2_or_gpa, write_fault_to_spt, 7679 emulation_type)) 7680 return 1; 7681 7682 return handle_emulation_failure(vcpu, emulation_type); 7683 } 7684 7685 if (ctxt->have_exception) { 7686 r = 1; 7687 if (inject_emulated_exception(vcpu)) 7688 return r; 7689 } else if (vcpu->arch.pio.count) { 7690 if (!vcpu->arch.pio.in) { 7691 /* FIXME: return into emulator if single-stepping. */ 7692 vcpu->arch.pio.count = 0; 7693 } else { 7694 writeback = false; 7695 vcpu->arch.complete_userspace_io = complete_emulated_pio; 7696 } 7697 r = 0; 7698 } else if (vcpu->mmio_needed) { 7699 ++vcpu->stat.mmio_exits; 7700 7701 if (!vcpu->mmio_is_write) 7702 writeback = false; 7703 r = 0; 7704 vcpu->arch.complete_userspace_io = complete_emulated_mmio; 7705 } else if (r == EMULATION_RESTART) 7706 goto restart; 7707 else 7708 r = 1; 7709 7710 if (writeback) { 7711 unsigned long rflags = static_call(kvm_x86_get_rflags)(vcpu); 7712 toggle_interruptibility(vcpu, ctxt->interruptibility); 7713 vcpu->arch.emulate_regs_need_sync_to_vcpu = false; 7714 if (!ctxt->have_exception || 7715 exception_type(ctxt->exception.vector) == EXCPT_TRAP) { 7716 kvm_rip_write(vcpu, ctxt->eip); 7717 if (r && (ctxt->tf || (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP))) 7718 r = kvm_vcpu_do_singlestep(vcpu); 7719 if (kvm_x86_ops.update_emulated_instruction) 7720 static_call(kvm_x86_update_emulated_instruction)(vcpu); 7721 __kvm_set_rflags(vcpu, ctxt->eflags); 7722 } 7723 7724 /* 7725 * For STI, interrupts are shadowed; so KVM_REQ_EVENT will 7726 * do nothing, and it will be requested again as soon as 7727 * the shadow expires. But we still need to check here, 7728 * because POPF has no interrupt shadow. 7729 */ 7730 if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF)) 7731 kvm_make_request(KVM_REQ_EVENT, vcpu); 7732 } else 7733 vcpu->arch.emulate_regs_need_sync_to_vcpu = true; 7734 7735 return r; 7736 } 7737 7738 int kvm_emulate_instruction(struct kvm_vcpu *vcpu, int emulation_type) 7739 { 7740 return x86_emulate_instruction(vcpu, 0, emulation_type, NULL, 0); 7741 } 7742 EXPORT_SYMBOL_GPL(kvm_emulate_instruction); 7743 7744 int kvm_emulate_instruction_from_buffer(struct kvm_vcpu *vcpu, 7745 void *insn, int insn_len) 7746 { 7747 return x86_emulate_instruction(vcpu, 0, 0, insn, insn_len); 7748 } 7749 EXPORT_SYMBOL_GPL(kvm_emulate_instruction_from_buffer); 7750 7751 static int complete_fast_pio_out_port_0x7e(struct kvm_vcpu *vcpu) 7752 { 7753 vcpu->arch.pio.count = 0; 7754 return 1; 7755 } 7756 7757 static int complete_fast_pio_out(struct kvm_vcpu *vcpu) 7758 { 7759 vcpu->arch.pio.count = 0; 7760 7761 if (unlikely(!kvm_is_linear_rip(vcpu, vcpu->arch.pio.linear_rip))) 7762 return 1; 7763 7764 return kvm_skip_emulated_instruction(vcpu); 7765 } 7766 7767 static int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, 7768 unsigned short port) 7769 { 7770 unsigned long val = kvm_rax_read(vcpu); 7771 int ret = emulator_pio_out(vcpu, size, port, &val, 1); 7772 7773 if (ret) 7774 return ret; 7775 7776 /* 7777 * Workaround userspace that relies on old KVM behavior of %rip being 7778 * incremented prior to exiting to userspace to handle "OUT 0x7e". 7779 */ 7780 if (port == 0x7e && 7781 kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_OUT_7E_INC_RIP)) { 7782 vcpu->arch.complete_userspace_io = 7783 complete_fast_pio_out_port_0x7e; 7784 kvm_skip_emulated_instruction(vcpu); 7785 } else { 7786 vcpu->arch.pio.linear_rip = kvm_get_linear_rip(vcpu); 7787 vcpu->arch.complete_userspace_io = complete_fast_pio_out; 7788 } 7789 return 0; 7790 } 7791 7792 static int complete_fast_pio_in(struct kvm_vcpu *vcpu) 7793 { 7794 unsigned long val; 7795 7796 /* We should only ever be called with arch.pio.count equal to 1 */ 7797 BUG_ON(vcpu->arch.pio.count != 1); 7798 7799 if (unlikely(!kvm_is_linear_rip(vcpu, vcpu->arch.pio.linear_rip))) { 7800 vcpu->arch.pio.count = 0; 7801 return 1; 7802 } 7803 7804 /* For size less than 4 we merge, else we zero extend */ 7805 val = (vcpu->arch.pio.size < 4) ? kvm_rax_read(vcpu) : 0; 7806 7807 /* 7808 * Since vcpu->arch.pio.count == 1 let emulator_pio_in perform 7809 * the copy and tracing 7810 */ 7811 emulator_pio_in(vcpu, vcpu->arch.pio.size, vcpu->arch.pio.port, &val, 1); 7812 kvm_rax_write(vcpu, val); 7813 7814 return kvm_skip_emulated_instruction(vcpu); 7815 } 7816 7817 static int kvm_fast_pio_in(struct kvm_vcpu *vcpu, int size, 7818 unsigned short port) 7819 { 7820 unsigned long val; 7821 int ret; 7822 7823 /* For size less than 4 we merge, else we zero extend */ 7824 val = (size < 4) ? kvm_rax_read(vcpu) : 0; 7825 7826 ret = emulator_pio_in(vcpu, size, port, &val, 1); 7827 if (ret) { 7828 kvm_rax_write(vcpu, val); 7829 return ret; 7830 } 7831 7832 vcpu->arch.pio.linear_rip = kvm_get_linear_rip(vcpu); 7833 vcpu->arch.complete_userspace_io = complete_fast_pio_in; 7834 7835 return 0; 7836 } 7837 7838 int kvm_fast_pio(struct kvm_vcpu *vcpu, int size, unsigned short port, int in) 7839 { 7840 int ret; 7841 7842 if (in) 7843 ret = kvm_fast_pio_in(vcpu, size, port); 7844 else 7845 ret = kvm_fast_pio_out(vcpu, size, port); 7846 return ret && kvm_skip_emulated_instruction(vcpu); 7847 } 7848 EXPORT_SYMBOL_GPL(kvm_fast_pio); 7849 7850 static int kvmclock_cpu_down_prep(unsigned int cpu) 7851 { 7852 __this_cpu_write(cpu_tsc_khz, 0); 7853 return 0; 7854 } 7855 7856 static void tsc_khz_changed(void *data) 7857 { 7858 struct cpufreq_freqs *freq = data; 7859 unsigned long khz = 0; 7860 7861 if (data) 7862 khz = freq->new; 7863 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) 7864 khz = cpufreq_quick_get(raw_smp_processor_id()); 7865 if (!khz) 7866 khz = tsc_khz; 7867 __this_cpu_write(cpu_tsc_khz, khz); 7868 } 7869 7870 #ifdef CONFIG_X86_64 7871 static void kvm_hyperv_tsc_notifier(void) 7872 { 7873 struct kvm *kvm; 7874 struct kvm_vcpu *vcpu; 7875 int cpu; 7876 unsigned long flags; 7877 7878 mutex_lock(&kvm_lock); 7879 list_for_each_entry(kvm, &vm_list, vm_list) 7880 kvm_make_mclock_inprogress_request(kvm); 7881 7882 hyperv_stop_tsc_emulation(); 7883 7884 /* TSC frequency always matches when on Hyper-V */ 7885 for_each_present_cpu(cpu) 7886 per_cpu(cpu_tsc_khz, cpu) = tsc_khz; 7887 kvm_max_guest_tsc_khz = tsc_khz; 7888 7889 list_for_each_entry(kvm, &vm_list, vm_list) { 7890 struct kvm_arch *ka = &kvm->arch; 7891 7892 spin_lock_irqsave(&ka->pvclock_gtod_sync_lock, flags); 7893 pvclock_update_vm_gtod_copy(kvm); 7894 spin_unlock_irqrestore(&ka->pvclock_gtod_sync_lock, flags); 7895 7896 kvm_for_each_vcpu(cpu, vcpu, kvm) 7897 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 7898 7899 kvm_for_each_vcpu(cpu, vcpu, kvm) 7900 kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu); 7901 } 7902 mutex_unlock(&kvm_lock); 7903 } 7904 #endif 7905 7906 static void __kvmclock_cpufreq_notifier(struct cpufreq_freqs *freq, int cpu) 7907 { 7908 struct kvm *kvm; 7909 struct kvm_vcpu *vcpu; 7910 int i, send_ipi = 0; 7911 7912 /* 7913 * We allow guests to temporarily run on slowing clocks, 7914 * provided we notify them after, or to run on accelerating 7915 * clocks, provided we notify them before. Thus time never 7916 * goes backwards. 7917 * 7918 * However, we have a problem. We can't atomically update 7919 * the frequency of a given CPU from this function; it is 7920 * merely a notifier, which can be called from any CPU. 7921 * Changing the TSC frequency at arbitrary points in time 7922 * requires a recomputation of local variables related to 7923 * the TSC for each VCPU. We must flag these local variables 7924 * to be updated and be sure the update takes place with the 7925 * new frequency before any guests proceed. 7926 * 7927 * Unfortunately, the combination of hotplug CPU and frequency 7928 * change creates an intractable locking scenario; the order 7929 * of when these callouts happen is undefined with respect to 7930 * CPU hotplug, and they can race with each other. As such, 7931 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is 7932 * undefined; you can actually have a CPU frequency change take 7933 * place in between the computation of X and the setting of the 7934 * variable. To protect against this problem, all updates of 7935 * the per_cpu tsc_khz variable are done in an interrupt 7936 * protected IPI, and all callers wishing to update the value 7937 * must wait for a synchronous IPI to complete (which is trivial 7938 * if the caller is on the CPU already). This establishes the 7939 * necessary total order on variable updates. 7940 * 7941 * Note that because a guest time update may take place 7942 * anytime after the setting of the VCPU's request bit, the 7943 * correct TSC value must be set before the request. However, 7944 * to ensure the update actually makes it to any guest which 7945 * starts running in hardware virtualization between the set 7946 * and the acquisition of the spinlock, we must also ping the 7947 * CPU after setting the request bit. 7948 * 7949 */ 7950 7951 smp_call_function_single(cpu, tsc_khz_changed, freq, 1); 7952 7953 mutex_lock(&kvm_lock); 7954 list_for_each_entry(kvm, &vm_list, vm_list) { 7955 kvm_for_each_vcpu(i, vcpu, kvm) { 7956 if (vcpu->cpu != cpu) 7957 continue; 7958 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 7959 if (vcpu->cpu != raw_smp_processor_id()) 7960 send_ipi = 1; 7961 } 7962 } 7963 mutex_unlock(&kvm_lock); 7964 7965 if (freq->old < freq->new && send_ipi) { 7966 /* 7967 * We upscale the frequency. Must make the guest 7968 * doesn't see old kvmclock values while running with 7969 * the new frequency, otherwise we risk the guest sees 7970 * time go backwards. 7971 * 7972 * In case we update the frequency for another cpu 7973 * (which might be in guest context) send an interrupt 7974 * to kick the cpu out of guest context. Next time 7975 * guest context is entered kvmclock will be updated, 7976 * so the guest will not see stale values. 7977 */ 7978 smp_call_function_single(cpu, tsc_khz_changed, freq, 1); 7979 } 7980 } 7981 7982 static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val, 7983 void *data) 7984 { 7985 struct cpufreq_freqs *freq = data; 7986 int cpu; 7987 7988 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new) 7989 return 0; 7990 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new) 7991 return 0; 7992 7993 for_each_cpu(cpu, freq->policy->cpus) 7994 __kvmclock_cpufreq_notifier(freq, cpu); 7995 7996 return 0; 7997 } 7998 7999 static struct notifier_block kvmclock_cpufreq_notifier_block = { 8000 .notifier_call = kvmclock_cpufreq_notifier 8001 }; 8002 8003 static int kvmclock_cpu_online(unsigned int cpu) 8004 { 8005 tsc_khz_changed(NULL); 8006 return 0; 8007 } 8008 8009 static void kvm_timer_init(void) 8010 { 8011 max_tsc_khz = tsc_khz; 8012 8013 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) { 8014 #ifdef CONFIG_CPU_FREQ 8015 struct cpufreq_policy *policy; 8016 int cpu; 8017 8018 cpu = get_cpu(); 8019 policy = cpufreq_cpu_get(cpu); 8020 if (policy) { 8021 if (policy->cpuinfo.max_freq) 8022 max_tsc_khz = policy->cpuinfo.max_freq; 8023 cpufreq_cpu_put(policy); 8024 } 8025 put_cpu(); 8026 #endif 8027 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block, 8028 CPUFREQ_TRANSITION_NOTIFIER); 8029 } 8030 8031 cpuhp_setup_state(CPUHP_AP_X86_KVM_CLK_ONLINE, "x86/kvm/clk:online", 8032 kvmclock_cpu_online, kvmclock_cpu_down_prep); 8033 } 8034 8035 DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu); 8036 EXPORT_PER_CPU_SYMBOL_GPL(current_vcpu); 8037 8038 int kvm_is_in_guest(void) 8039 { 8040 return __this_cpu_read(current_vcpu) != NULL; 8041 } 8042 8043 static int kvm_is_user_mode(void) 8044 { 8045 int user_mode = 3; 8046 8047 if (__this_cpu_read(current_vcpu)) 8048 user_mode = static_call(kvm_x86_get_cpl)(__this_cpu_read(current_vcpu)); 8049 8050 return user_mode != 0; 8051 } 8052 8053 static unsigned long kvm_get_guest_ip(void) 8054 { 8055 unsigned long ip = 0; 8056 8057 if (__this_cpu_read(current_vcpu)) 8058 ip = kvm_rip_read(__this_cpu_read(current_vcpu)); 8059 8060 return ip; 8061 } 8062 8063 static void kvm_handle_intel_pt_intr(void) 8064 { 8065 struct kvm_vcpu *vcpu = __this_cpu_read(current_vcpu); 8066 8067 kvm_make_request(KVM_REQ_PMI, vcpu); 8068 __set_bit(MSR_CORE_PERF_GLOBAL_OVF_CTRL_TRACE_TOPA_PMI_BIT, 8069 (unsigned long *)&vcpu->arch.pmu.global_status); 8070 } 8071 8072 static struct perf_guest_info_callbacks kvm_guest_cbs = { 8073 .is_in_guest = kvm_is_in_guest, 8074 .is_user_mode = kvm_is_user_mode, 8075 .get_guest_ip = kvm_get_guest_ip, 8076 .handle_intel_pt_intr = kvm_handle_intel_pt_intr, 8077 }; 8078 8079 #ifdef CONFIG_X86_64 8080 static void pvclock_gtod_update_fn(struct work_struct *work) 8081 { 8082 struct kvm *kvm; 8083 8084 struct kvm_vcpu *vcpu; 8085 int i; 8086 8087 mutex_lock(&kvm_lock); 8088 list_for_each_entry(kvm, &vm_list, vm_list) 8089 kvm_for_each_vcpu(i, vcpu, kvm) 8090 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu); 8091 atomic_set(&kvm_guest_has_master_clock, 0); 8092 mutex_unlock(&kvm_lock); 8093 } 8094 8095 static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn); 8096 8097 /* 8098 * Indirection to move queue_work() out of the tk_core.seq write held 8099 * region to prevent possible deadlocks against time accessors which 8100 * are invoked with work related locks held. 8101 */ 8102 static void pvclock_irq_work_fn(struct irq_work *w) 8103 { 8104 queue_work(system_long_wq, &pvclock_gtod_work); 8105 } 8106 8107 static DEFINE_IRQ_WORK(pvclock_irq_work, pvclock_irq_work_fn); 8108 8109 /* 8110 * Notification about pvclock gtod data update. 8111 */ 8112 static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused, 8113 void *priv) 8114 { 8115 struct pvclock_gtod_data *gtod = &pvclock_gtod_data; 8116 struct timekeeper *tk = priv; 8117 8118 update_pvclock_gtod(tk); 8119 8120 /* 8121 * Disable master clock if host does not trust, or does not use, 8122 * TSC based clocksource. Delegate queue_work() to irq_work as 8123 * this is invoked with tk_core.seq write held. 8124 */ 8125 if (!gtod_is_based_on_tsc(gtod->clock.vclock_mode) && 8126 atomic_read(&kvm_guest_has_master_clock) != 0) 8127 irq_work_queue(&pvclock_irq_work); 8128 return 0; 8129 } 8130 8131 static struct notifier_block pvclock_gtod_notifier = { 8132 .notifier_call = pvclock_gtod_notify, 8133 }; 8134 #endif 8135 8136 int kvm_arch_init(void *opaque) 8137 { 8138 struct kvm_x86_init_ops *ops = opaque; 8139 int r; 8140 8141 if (kvm_x86_ops.hardware_enable) { 8142 printk(KERN_ERR "kvm: already loaded the other module\n"); 8143 r = -EEXIST; 8144 goto out; 8145 } 8146 8147 if (!ops->cpu_has_kvm_support()) { 8148 pr_err_ratelimited("kvm: no hardware support\n"); 8149 r = -EOPNOTSUPP; 8150 goto out; 8151 } 8152 if (ops->disabled_by_bios()) { 8153 pr_err_ratelimited("kvm: disabled by bios\n"); 8154 r = -EOPNOTSUPP; 8155 goto out; 8156 } 8157 8158 /* 8159 * KVM explicitly assumes that the guest has an FPU and 8160 * FXSAVE/FXRSTOR. For example, the KVM_GET_FPU explicitly casts the 8161 * vCPU's FPU state as a fxregs_state struct. 8162 */ 8163 if (!boot_cpu_has(X86_FEATURE_FPU) || !boot_cpu_has(X86_FEATURE_FXSR)) { 8164 printk(KERN_ERR "kvm: inadequate fpu\n"); 8165 r = -EOPNOTSUPP; 8166 goto out; 8167 } 8168 8169 r = -ENOMEM; 8170 x86_fpu_cache = kmem_cache_create("x86_fpu", sizeof(struct fpu), 8171 __alignof__(struct fpu), SLAB_ACCOUNT, 8172 NULL); 8173 if (!x86_fpu_cache) { 8174 printk(KERN_ERR "kvm: failed to allocate cache for x86 fpu\n"); 8175 goto out; 8176 } 8177 8178 x86_emulator_cache = kvm_alloc_emulator_cache(); 8179 if (!x86_emulator_cache) { 8180 pr_err("kvm: failed to allocate cache for x86 emulator\n"); 8181 goto out_free_x86_fpu_cache; 8182 } 8183 8184 user_return_msrs = alloc_percpu(struct kvm_user_return_msrs); 8185 if (!user_return_msrs) { 8186 printk(KERN_ERR "kvm: failed to allocate percpu kvm_user_return_msrs\n"); 8187 goto out_free_x86_emulator_cache; 8188 } 8189 kvm_nr_uret_msrs = 0; 8190 8191 r = kvm_mmu_module_init(); 8192 if (r) 8193 goto out_free_percpu; 8194 8195 kvm_timer_init(); 8196 8197 perf_register_guest_info_callbacks(&kvm_guest_cbs); 8198 8199 if (boot_cpu_has(X86_FEATURE_XSAVE)) { 8200 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK); 8201 supported_xcr0 = host_xcr0 & KVM_SUPPORTED_XCR0; 8202 } 8203 8204 if (pi_inject_timer == -1) 8205 pi_inject_timer = housekeeping_enabled(HK_FLAG_TIMER); 8206 #ifdef CONFIG_X86_64 8207 pvclock_gtod_register_notifier(&pvclock_gtod_notifier); 8208 8209 if (hypervisor_is_type(X86_HYPER_MS_HYPERV)) 8210 set_hv_tscchange_cb(kvm_hyperv_tsc_notifier); 8211 #endif 8212 8213 return 0; 8214 8215 out_free_percpu: 8216 free_percpu(user_return_msrs); 8217 out_free_x86_emulator_cache: 8218 kmem_cache_destroy(x86_emulator_cache); 8219 out_free_x86_fpu_cache: 8220 kmem_cache_destroy(x86_fpu_cache); 8221 out: 8222 return r; 8223 } 8224 8225 void kvm_arch_exit(void) 8226 { 8227 #ifdef CONFIG_X86_64 8228 if (hypervisor_is_type(X86_HYPER_MS_HYPERV)) 8229 clear_hv_tscchange_cb(); 8230 #endif 8231 kvm_lapic_exit(); 8232 perf_unregister_guest_info_callbacks(&kvm_guest_cbs); 8233 8234 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) 8235 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block, 8236 CPUFREQ_TRANSITION_NOTIFIER); 8237 cpuhp_remove_state_nocalls(CPUHP_AP_X86_KVM_CLK_ONLINE); 8238 #ifdef CONFIG_X86_64 8239 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier); 8240 irq_work_sync(&pvclock_irq_work); 8241 cancel_work_sync(&pvclock_gtod_work); 8242 #endif 8243 kvm_x86_ops.hardware_enable = NULL; 8244 kvm_mmu_module_exit(); 8245 free_percpu(user_return_msrs); 8246 kmem_cache_destroy(x86_fpu_cache); 8247 #ifdef CONFIG_KVM_XEN 8248 static_key_deferred_flush(&kvm_xen_enabled); 8249 WARN_ON(static_branch_unlikely(&kvm_xen_enabled.key)); 8250 #endif 8251 } 8252 8253 static int __kvm_vcpu_halt(struct kvm_vcpu *vcpu, int state, int reason) 8254 { 8255 ++vcpu->stat.halt_exits; 8256 if (lapic_in_kernel(vcpu)) { 8257 vcpu->arch.mp_state = state; 8258 return 1; 8259 } else { 8260 vcpu->run->exit_reason = reason; 8261 return 0; 8262 } 8263 } 8264 8265 int kvm_vcpu_halt(struct kvm_vcpu *vcpu) 8266 { 8267 return __kvm_vcpu_halt(vcpu, KVM_MP_STATE_HALTED, KVM_EXIT_HLT); 8268 } 8269 EXPORT_SYMBOL_GPL(kvm_vcpu_halt); 8270 8271 int kvm_emulate_halt(struct kvm_vcpu *vcpu) 8272 { 8273 int ret = kvm_skip_emulated_instruction(vcpu); 8274 /* 8275 * TODO: we might be squashing a GUESTDBG_SINGLESTEP-triggered 8276 * KVM_EXIT_DEBUG here. 8277 */ 8278 return kvm_vcpu_halt(vcpu) && ret; 8279 } 8280 EXPORT_SYMBOL_GPL(kvm_emulate_halt); 8281 8282 int kvm_emulate_ap_reset_hold(struct kvm_vcpu *vcpu) 8283 { 8284 int ret = kvm_skip_emulated_instruction(vcpu); 8285 8286 return __kvm_vcpu_halt(vcpu, KVM_MP_STATE_AP_RESET_HOLD, KVM_EXIT_AP_RESET_HOLD) && ret; 8287 } 8288 EXPORT_SYMBOL_GPL(kvm_emulate_ap_reset_hold); 8289 8290 #ifdef CONFIG_X86_64 8291 static int kvm_pv_clock_pairing(struct kvm_vcpu *vcpu, gpa_t paddr, 8292 unsigned long clock_type) 8293 { 8294 struct kvm_clock_pairing clock_pairing; 8295 struct timespec64 ts; 8296 u64 cycle; 8297 int ret; 8298 8299 if (clock_type != KVM_CLOCK_PAIRING_WALLCLOCK) 8300 return -KVM_EOPNOTSUPP; 8301 8302 if (!kvm_get_walltime_and_clockread(&ts, &cycle)) 8303 return -KVM_EOPNOTSUPP; 8304 8305 clock_pairing.sec = ts.tv_sec; 8306 clock_pairing.nsec = ts.tv_nsec; 8307 clock_pairing.tsc = kvm_read_l1_tsc(vcpu, cycle); 8308 clock_pairing.flags = 0; 8309 memset(&clock_pairing.pad, 0, sizeof(clock_pairing.pad)); 8310 8311 ret = 0; 8312 if (kvm_write_guest(vcpu->kvm, paddr, &clock_pairing, 8313 sizeof(struct kvm_clock_pairing))) 8314 ret = -KVM_EFAULT; 8315 8316 return ret; 8317 } 8318 #endif 8319 8320 /* 8321 * kvm_pv_kick_cpu_op: Kick a vcpu. 8322 * 8323 * @apicid - apicid of vcpu to be kicked. 8324 */ 8325 static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid) 8326 { 8327 struct kvm_lapic_irq lapic_irq; 8328 8329 lapic_irq.shorthand = APIC_DEST_NOSHORT; 8330 lapic_irq.dest_mode = APIC_DEST_PHYSICAL; 8331 lapic_irq.level = 0; 8332 lapic_irq.dest_id = apicid; 8333 lapic_irq.msi_redir_hint = false; 8334 8335 lapic_irq.delivery_mode = APIC_DM_REMRD; 8336 kvm_irq_delivery_to_apic(kvm, NULL, &lapic_irq, NULL); 8337 } 8338 8339 bool kvm_apicv_activated(struct kvm *kvm) 8340 { 8341 return (READ_ONCE(kvm->arch.apicv_inhibit_reasons) == 0); 8342 } 8343 EXPORT_SYMBOL_GPL(kvm_apicv_activated); 8344 8345 void kvm_apicv_init(struct kvm *kvm, bool enable) 8346 { 8347 if (enable) 8348 clear_bit(APICV_INHIBIT_REASON_DISABLE, 8349 &kvm->arch.apicv_inhibit_reasons); 8350 else 8351 set_bit(APICV_INHIBIT_REASON_DISABLE, 8352 &kvm->arch.apicv_inhibit_reasons); 8353 } 8354 EXPORT_SYMBOL_GPL(kvm_apicv_init); 8355 8356 static void kvm_sched_yield(struct kvm_vcpu *vcpu, unsigned long dest_id) 8357 { 8358 struct kvm_vcpu *target = NULL; 8359 struct kvm_apic_map *map; 8360 8361 vcpu->stat.directed_yield_attempted++; 8362 8363 if (single_task_running()) 8364 goto no_yield; 8365 8366 rcu_read_lock(); 8367 map = rcu_dereference(vcpu->kvm->arch.apic_map); 8368 8369 if (likely(map) && dest_id <= map->max_apic_id && map->phys_map[dest_id]) 8370 target = map->phys_map[dest_id]->vcpu; 8371 8372 rcu_read_unlock(); 8373 8374 if (!target || !READ_ONCE(target->ready)) 8375 goto no_yield; 8376 8377 /* Ignore requests to yield to self */ 8378 if (vcpu == target) 8379 goto no_yield; 8380 8381 if (kvm_vcpu_yield_to(target) <= 0) 8382 goto no_yield; 8383 8384 vcpu->stat.directed_yield_successful++; 8385 8386 no_yield: 8387 return; 8388 } 8389 8390 int kvm_emulate_hypercall(struct kvm_vcpu *vcpu) 8391 { 8392 unsigned long nr, a0, a1, a2, a3, ret; 8393 int op_64_bit; 8394 8395 if (kvm_xen_hypercall_enabled(vcpu->kvm)) 8396 return kvm_xen_hypercall(vcpu); 8397 8398 if (kvm_hv_hypercall_enabled(vcpu)) 8399 return kvm_hv_hypercall(vcpu); 8400 8401 nr = kvm_rax_read(vcpu); 8402 a0 = kvm_rbx_read(vcpu); 8403 a1 = kvm_rcx_read(vcpu); 8404 a2 = kvm_rdx_read(vcpu); 8405 a3 = kvm_rsi_read(vcpu); 8406 8407 trace_kvm_hypercall(nr, a0, a1, a2, a3); 8408 8409 op_64_bit = is_64_bit_mode(vcpu); 8410 if (!op_64_bit) { 8411 nr &= 0xFFFFFFFF; 8412 a0 &= 0xFFFFFFFF; 8413 a1 &= 0xFFFFFFFF; 8414 a2 &= 0xFFFFFFFF; 8415 a3 &= 0xFFFFFFFF; 8416 } 8417 8418 if (static_call(kvm_x86_get_cpl)(vcpu) != 0) { 8419 ret = -KVM_EPERM; 8420 goto out; 8421 } 8422 8423 ret = -KVM_ENOSYS; 8424 8425 switch (nr) { 8426 case KVM_HC_VAPIC_POLL_IRQ: 8427 ret = 0; 8428 break; 8429 case KVM_HC_KICK_CPU: 8430 if (!guest_pv_has(vcpu, KVM_FEATURE_PV_UNHALT)) 8431 break; 8432 8433 kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1); 8434 kvm_sched_yield(vcpu, a1); 8435 ret = 0; 8436 break; 8437 #ifdef CONFIG_X86_64 8438 case KVM_HC_CLOCK_PAIRING: 8439 ret = kvm_pv_clock_pairing(vcpu, a0, a1); 8440 break; 8441 #endif 8442 case KVM_HC_SEND_IPI: 8443 if (!guest_pv_has(vcpu, KVM_FEATURE_PV_SEND_IPI)) 8444 break; 8445 8446 ret = kvm_pv_send_ipi(vcpu->kvm, a0, a1, a2, a3, op_64_bit); 8447 break; 8448 case KVM_HC_SCHED_YIELD: 8449 if (!guest_pv_has(vcpu, KVM_FEATURE_PV_SCHED_YIELD)) 8450 break; 8451 8452 kvm_sched_yield(vcpu, a0); 8453 ret = 0; 8454 break; 8455 default: 8456 ret = -KVM_ENOSYS; 8457 break; 8458 } 8459 out: 8460 if (!op_64_bit) 8461 ret = (u32)ret; 8462 kvm_rax_write(vcpu, ret); 8463 8464 ++vcpu->stat.hypercalls; 8465 return kvm_skip_emulated_instruction(vcpu); 8466 } 8467 EXPORT_SYMBOL_GPL(kvm_emulate_hypercall); 8468 8469 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt) 8470 { 8471 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 8472 char instruction[3]; 8473 unsigned long rip = kvm_rip_read(vcpu); 8474 8475 static_call(kvm_x86_patch_hypercall)(vcpu, instruction); 8476 8477 return emulator_write_emulated(ctxt, rip, instruction, 3, 8478 &ctxt->exception); 8479 } 8480 8481 static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu) 8482 { 8483 return vcpu->run->request_interrupt_window && 8484 likely(!pic_in_kernel(vcpu->kvm)); 8485 } 8486 8487 static void post_kvm_run_save(struct kvm_vcpu *vcpu) 8488 { 8489 struct kvm_run *kvm_run = vcpu->run; 8490 8491 /* 8492 * if_flag is obsolete and useless, so do not bother 8493 * setting it for SEV-ES guests. Userspace can just 8494 * use kvm_run->ready_for_interrupt_injection. 8495 */ 8496 kvm_run->if_flag = !vcpu->arch.guest_state_protected 8497 && (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0; 8498 8499 kvm_run->cr8 = kvm_get_cr8(vcpu); 8500 kvm_run->apic_base = kvm_get_apic_base(vcpu); 8501 kvm_run->ready_for_interrupt_injection = 8502 pic_in_kernel(vcpu->kvm) || 8503 kvm_vcpu_ready_for_interrupt_injection(vcpu); 8504 8505 if (is_smm(vcpu)) 8506 kvm_run->flags |= KVM_RUN_X86_SMM; 8507 } 8508 8509 static void update_cr8_intercept(struct kvm_vcpu *vcpu) 8510 { 8511 int max_irr, tpr; 8512 8513 if (!kvm_x86_ops.update_cr8_intercept) 8514 return; 8515 8516 if (!lapic_in_kernel(vcpu)) 8517 return; 8518 8519 if (vcpu->arch.apicv_active) 8520 return; 8521 8522 if (!vcpu->arch.apic->vapic_addr) 8523 max_irr = kvm_lapic_find_highest_irr(vcpu); 8524 else 8525 max_irr = -1; 8526 8527 if (max_irr != -1) 8528 max_irr >>= 4; 8529 8530 tpr = kvm_lapic_get_cr8(vcpu); 8531 8532 static_call(kvm_x86_update_cr8_intercept)(vcpu, tpr, max_irr); 8533 } 8534 8535 8536 int kvm_check_nested_events(struct kvm_vcpu *vcpu) 8537 { 8538 if (WARN_ON_ONCE(!is_guest_mode(vcpu))) 8539 return -EIO; 8540 8541 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) { 8542 kvm_x86_ops.nested_ops->triple_fault(vcpu); 8543 return 1; 8544 } 8545 8546 return kvm_x86_ops.nested_ops->check_events(vcpu); 8547 } 8548 8549 static void kvm_inject_exception(struct kvm_vcpu *vcpu) 8550 { 8551 if (vcpu->arch.exception.error_code && !is_protmode(vcpu)) 8552 vcpu->arch.exception.error_code = false; 8553 static_call(kvm_x86_queue_exception)(vcpu); 8554 } 8555 8556 static void inject_pending_event(struct kvm_vcpu *vcpu, bool *req_immediate_exit) 8557 { 8558 int r; 8559 bool can_inject = true; 8560 8561 /* try to reinject previous events if any */ 8562 8563 if (vcpu->arch.exception.injected) { 8564 kvm_inject_exception(vcpu); 8565 can_inject = false; 8566 } 8567 /* 8568 * Do not inject an NMI or interrupt if there is a pending 8569 * exception. Exceptions and interrupts are recognized at 8570 * instruction boundaries, i.e. the start of an instruction. 8571 * Trap-like exceptions, e.g. #DB, have higher priority than 8572 * NMIs and interrupts, i.e. traps are recognized before an 8573 * NMI/interrupt that's pending on the same instruction. 8574 * Fault-like exceptions, e.g. #GP and #PF, are the lowest 8575 * priority, but are only generated (pended) during instruction 8576 * execution, i.e. a pending fault-like exception means the 8577 * fault occurred on the *previous* instruction and must be 8578 * serviced prior to recognizing any new events in order to 8579 * fully complete the previous instruction. 8580 */ 8581 else if (!vcpu->arch.exception.pending) { 8582 if (vcpu->arch.nmi_injected) { 8583 static_call(kvm_x86_set_nmi)(vcpu); 8584 can_inject = false; 8585 } else if (vcpu->arch.interrupt.injected) { 8586 static_call(kvm_x86_set_irq)(vcpu); 8587 can_inject = false; 8588 } 8589 } 8590 8591 WARN_ON_ONCE(vcpu->arch.exception.injected && 8592 vcpu->arch.exception.pending); 8593 8594 /* 8595 * Call check_nested_events() even if we reinjected a previous event 8596 * in order for caller to determine if it should require immediate-exit 8597 * from L2 to L1 due to pending L1 events which require exit 8598 * from L2 to L1. 8599 */ 8600 if (is_guest_mode(vcpu)) { 8601 r = kvm_check_nested_events(vcpu); 8602 if (r < 0) 8603 goto busy; 8604 } 8605 8606 /* try to inject new event if pending */ 8607 if (vcpu->arch.exception.pending) { 8608 trace_kvm_inj_exception(vcpu->arch.exception.nr, 8609 vcpu->arch.exception.has_error_code, 8610 vcpu->arch.exception.error_code); 8611 8612 vcpu->arch.exception.pending = false; 8613 vcpu->arch.exception.injected = true; 8614 8615 if (exception_type(vcpu->arch.exception.nr) == EXCPT_FAULT) 8616 __kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) | 8617 X86_EFLAGS_RF); 8618 8619 if (vcpu->arch.exception.nr == DB_VECTOR) { 8620 kvm_deliver_exception_payload(vcpu); 8621 if (vcpu->arch.dr7 & DR7_GD) { 8622 vcpu->arch.dr7 &= ~DR7_GD; 8623 kvm_update_dr7(vcpu); 8624 } 8625 } 8626 8627 kvm_inject_exception(vcpu); 8628 can_inject = false; 8629 } 8630 8631 /* 8632 * Finally, inject interrupt events. If an event cannot be injected 8633 * due to architectural conditions (e.g. IF=0) a window-open exit 8634 * will re-request KVM_REQ_EVENT. Sometimes however an event is pending 8635 * and can architecturally be injected, but we cannot do it right now: 8636 * an interrupt could have arrived just now and we have to inject it 8637 * as a vmexit, or there could already an event in the queue, which is 8638 * indicated by can_inject. In that case we request an immediate exit 8639 * in order to make progress and get back here for another iteration. 8640 * The kvm_x86_ops hooks communicate this by returning -EBUSY. 8641 */ 8642 if (vcpu->arch.smi_pending) { 8643 r = can_inject ? static_call(kvm_x86_smi_allowed)(vcpu, true) : -EBUSY; 8644 if (r < 0) 8645 goto busy; 8646 if (r) { 8647 vcpu->arch.smi_pending = false; 8648 ++vcpu->arch.smi_count; 8649 enter_smm(vcpu); 8650 can_inject = false; 8651 } else 8652 static_call(kvm_x86_enable_smi_window)(vcpu); 8653 } 8654 8655 if (vcpu->arch.nmi_pending) { 8656 r = can_inject ? static_call(kvm_x86_nmi_allowed)(vcpu, true) : -EBUSY; 8657 if (r < 0) 8658 goto busy; 8659 if (r) { 8660 --vcpu->arch.nmi_pending; 8661 vcpu->arch.nmi_injected = true; 8662 static_call(kvm_x86_set_nmi)(vcpu); 8663 can_inject = false; 8664 WARN_ON(static_call(kvm_x86_nmi_allowed)(vcpu, true) < 0); 8665 } 8666 if (vcpu->arch.nmi_pending) 8667 static_call(kvm_x86_enable_nmi_window)(vcpu); 8668 } 8669 8670 if (kvm_cpu_has_injectable_intr(vcpu)) { 8671 r = can_inject ? static_call(kvm_x86_interrupt_allowed)(vcpu, true) : -EBUSY; 8672 if (r < 0) 8673 goto busy; 8674 if (r) { 8675 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu), false); 8676 static_call(kvm_x86_set_irq)(vcpu); 8677 WARN_ON(static_call(kvm_x86_interrupt_allowed)(vcpu, true) < 0); 8678 } 8679 if (kvm_cpu_has_injectable_intr(vcpu)) 8680 static_call(kvm_x86_enable_irq_window)(vcpu); 8681 } 8682 8683 if (is_guest_mode(vcpu) && 8684 kvm_x86_ops.nested_ops->hv_timer_pending && 8685 kvm_x86_ops.nested_ops->hv_timer_pending(vcpu)) 8686 *req_immediate_exit = true; 8687 8688 WARN_ON(vcpu->arch.exception.pending); 8689 return; 8690 8691 busy: 8692 *req_immediate_exit = true; 8693 return; 8694 } 8695 8696 static void process_nmi(struct kvm_vcpu *vcpu) 8697 { 8698 unsigned limit = 2; 8699 8700 /* 8701 * x86 is limited to one NMI running, and one NMI pending after it. 8702 * If an NMI is already in progress, limit further NMIs to just one. 8703 * Otherwise, allow two (and we'll inject the first one immediately). 8704 */ 8705 if (static_call(kvm_x86_get_nmi_mask)(vcpu) || vcpu->arch.nmi_injected) 8706 limit = 1; 8707 8708 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0); 8709 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit); 8710 kvm_make_request(KVM_REQ_EVENT, vcpu); 8711 } 8712 8713 static u32 enter_smm_get_segment_flags(struct kvm_segment *seg) 8714 { 8715 u32 flags = 0; 8716 flags |= seg->g << 23; 8717 flags |= seg->db << 22; 8718 flags |= seg->l << 21; 8719 flags |= seg->avl << 20; 8720 flags |= seg->present << 15; 8721 flags |= seg->dpl << 13; 8722 flags |= seg->s << 12; 8723 flags |= seg->type << 8; 8724 return flags; 8725 } 8726 8727 static void enter_smm_save_seg_32(struct kvm_vcpu *vcpu, char *buf, int n) 8728 { 8729 struct kvm_segment seg; 8730 int offset; 8731 8732 kvm_get_segment(vcpu, &seg, n); 8733 put_smstate(u32, buf, 0x7fa8 + n * 4, seg.selector); 8734 8735 if (n < 3) 8736 offset = 0x7f84 + n * 12; 8737 else 8738 offset = 0x7f2c + (n - 3) * 12; 8739 8740 put_smstate(u32, buf, offset + 8, seg.base); 8741 put_smstate(u32, buf, offset + 4, seg.limit); 8742 put_smstate(u32, buf, offset, enter_smm_get_segment_flags(&seg)); 8743 } 8744 8745 #ifdef CONFIG_X86_64 8746 static void enter_smm_save_seg_64(struct kvm_vcpu *vcpu, char *buf, int n) 8747 { 8748 struct kvm_segment seg; 8749 int offset; 8750 u16 flags; 8751 8752 kvm_get_segment(vcpu, &seg, n); 8753 offset = 0x7e00 + n * 16; 8754 8755 flags = enter_smm_get_segment_flags(&seg) >> 8; 8756 put_smstate(u16, buf, offset, seg.selector); 8757 put_smstate(u16, buf, offset + 2, flags); 8758 put_smstate(u32, buf, offset + 4, seg.limit); 8759 put_smstate(u64, buf, offset + 8, seg.base); 8760 } 8761 #endif 8762 8763 static void enter_smm_save_state_32(struct kvm_vcpu *vcpu, char *buf) 8764 { 8765 struct desc_ptr dt; 8766 struct kvm_segment seg; 8767 unsigned long val; 8768 int i; 8769 8770 put_smstate(u32, buf, 0x7ffc, kvm_read_cr0(vcpu)); 8771 put_smstate(u32, buf, 0x7ff8, kvm_read_cr3(vcpu)); 8772 put_smstate(u32, buf, 0x7ff4, kvm_get_rflags(vcpu)); 8773 put_smstate(u32, buf, 0x7ff0, kvm_rip_read(vcpu)); 8774 8775 for (i = 0; i < 8; i++) 8776 put_smstate(u32, buf, 0x7fd0 + i * 4, kvm_register_read_raw(vcpu, i)); 8777 8778 kvm_get_dr(vcpu, 6, &val); 8779 put_smstate(u32, buf, 0x7fcc, (u32)val); 8780 kvm_get_dr(vcpu, 7, &val); 8781 put_smstate(u32, buf, 0x7fc8, (u32)val); 8782 8783 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR); 8784 put_smstate(u32, buf, 0x7fc4, seg.selector); 8785 put_smstate(u32, buf, 0x7f64, seg.base); 8786 put_smstate(u32, buf, 0x7f60, seg.limit); 8787 put_smstate(u32, buf, 0x7f5c, enter_smm_get_segment_flags(&seg)); 8788 8789 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR); 8790 put_smstate(u32, buf, 0x7fc0, seg.selector); 8791 put_smstate(u32, buf, 0x7f80, seg.base); 8792 put_smstate(u32, buf, 0x7f7c, seg.limit); 8793 put_smstate(u32, buf, 0x7f78, enter_smm_get_segment_flags(&seg)); 8794 8795 static_call(kvm_x86_get_gdt)(vcpu, &dt); 8796 put_smstate(u32, buf, 0x7f74, dt.address); 8797 put_smstate(u32, buf, 0x7f70, dt.size); 8798 8799 static_call(kvm_x86_get_idt)(vcpu, &dt); 8800 put_smstate(u32, buf, 0x7f58, dt.address); 8801 put_smstate(u32, buf, 0x7f54, dt.size); 8802 8803 for (i = 0; i < 6; i++) 8804 enter_smm_save_seg_32(vcpu, buf, i); 8805 8806 put_smstate(u32, buf, 0x7f14, kvm_read_cr4(vcpu)); 8807 8808 /* revision id */ 8809 put_smstate(u32, buf, 0x7efc, 0x00020000); 8810 put_smstate(u32, buf, 0x7ef8, vcpu->arch.smbase); 8811 } 8812 8813 #ifdef CONFIG_X86_64 8814 static void enter_smm_save_state_64(struct kvm_vcpu *vcpu, char *buf) 8815 { 8816 struct desc_ptr dt; 8817 struct kvm_segment seg; 8818 unsigned long val; 8819 int i; 8820 8821 for (i = 0; i < 16; i++) 8822 put_smstate(u64, buf, 0x7ff8 - i * 8, kvm_register_read_raw(vcpu, i)); 8823 8824 put_smstate(u64, buf, 0x7f78, kvm_rip_read(vcpu)); 8825 put_smstate(u32, buf, 0x7f70, kvm_get_rflags(vcpu)); 8826 8827 kvm_get_dr(vcpu, 6, &val); 8828 put_smstate(u64, buf, 0x7f68, val); 8829 kvm_get_dr(vcpu, 7, &val); 8830 put_smstate(u64, buf, 0x7f60, val); 8831 8832 put_smstate(u64, buf, 0x7f58, kvm_read_cr0(vcpu)); 8833 put_smstate(u64, buf, 0x7f50, kvm_read_cr3(vcpu)); 8834 put_smstate(u64, buf, 0x7f48, kvm_read_cr4(vcpu)); 8835 8836 put_smstate(u32, buf, 0x7f00, vcpu->arch.smbase); 8837 8838 /* revision id */ 8839 put_smstate(u32, buf, 0x7efc, 0x00020064); 8840 8841 put_smstate(u64, buf, 0x7ed0, vcpu->arch.efer); 8842 8843 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR); 8844 put_smstate(u16, buf, 0x7e90, seg.selector); 8845 put_smstate(u16, buf, 0x7e92, enter_smm_get_segment_flags(&seg) >> 8); 8846 put_smstate(u32, buf, 0x7e94, seg.limit); 8847 put_smstate(u64, buf, 0x7e98, seg.base); 8848 8849 static_call(kvm_x86_get_idt)(vcpu, &dt); 8850 put_smstate(u32, buf, 0x7e84, dt.size); 8851 put_smstate(u64, buf, 0x7e88, dt.address); 8852 8853 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR); 8854 put_smstate(u16, buf, 0x7e70, seg.selector); 8855 put_smstate(u16, buf, 0x7e72, enter_smm_get_segment_flags(&seg) >> 8); 8856 put_smstate(u32, buf, 0x7e74, seg.limit); 8857 put_smstate(u64, buf, 0x7e78, seg.base); 8858 8859 static_call(kvm_x86_get_gdt)(vcpu, &dt); 8860 put_smstate(u32, buf, 0x7e64, dt.size); 8861 put_smstate(u64, buf, 0x7e68, dt.address); 8862 8863 for (i = 0; i < 6; i++) 8864 enter_smm_save_seg_64(vcpu, buf, i); 8865 } 8866 #endif 8867 8868 static void enter_smm(struct kvm_vcpu *vcpu) 8869 { 8870 struct kvm_segment cs, ds; 8871 struct desc_ptr dt; 8872 char buf[512]; 8873 u32 cr0; 8874 8875 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, true); 8876 memset(buf, 0, 512); 8877 #ifdef CONFIG_X86_64 8878 if (guest_cpuid_has(vcpu, X86_FEATURE_LM)) 8879 enter_smm_save_state_64(vcpu, buf); 8880 else 8881 #endif 8882 enter_smm_save_state_32(vcpu, buf); 8883 8884 /* 8885 * Give pre_enter_smm() a chance to make ISA-specific changes to the 8886 * vCPU state (e.g. leave guest mode) after we've saved the state into 8887 * the SMM state-save area. 8888 */ 8889 static_call(kvm_x86_pre_enter_smm)(vcpu, buf); 8890 8891 vcpu->arch.hflags |= HF_SMM_MASK; 8892 kvm_vcpu_write_guest(vcpu, vcpu->arch.smbase + 0xfe00, buf, sizeof(buf)); 8893 8894 if (static_call(kvm_x86_get_nmi_mask)(vcpu)) 8895 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK; 8896 else 8897 static_call(kvm_x86_set_nmi_mask)(vcpu, true); 8898 8899 kvm_set_rflags(vcpu, X86_EFLAGS_FIXED); 8900 kvm_rip_write(vcpu, 0x8000); 8901 8902 cr0 = vcpu->arch.cr0 & ~(X86_CR0_PE | X86_CR0_EM | X86_CR0_TS | X86_CR0_PG); 8903 static_call(kvm_x86_set_cr0)(vcpu, cr0); 8904 vcpu->arch.cr0 = cr0; 8905 8906 static_call(kvm_x86_set_cr4)(vcpu, 0); 8907 8908 /* Undocumented: IDT limit is set to zero on entry to SMM. */ 8909 dt.address = dt.size = 0; 8910 static_call(kvm_x86_set_idt)(vcpu, &dt); 8911 8912 kvm_set_dr(vcpu, 7, DR7_FIXED_1); 8913 8914 cs.selector = (vcpu->arch.smbase >> 4) & 0xffff; 8915 cs.base = vcpu->arch.smbase; 8916 8917 ds.selector = 0; 8918 ds.base = 0; 8919 8920 cs.limit = ds.limit = 0xffffffff; 8921 cs.type = ds.type = 0x3; 8922 cs.dpl = ds.dpl = 0; 8923 cs.db = ds.db = 0; 8924 cs.s = ds.s = 1; 8925 cs.l = ds.l = 0; 8926 cs.g = ds.g = 1; 8927 cs.avl = ds.avl = 0; 8928 cs.present = ds.present = 1; 8929 cs.unusable = ds.unusable = 0; 8930 cs.padding = ds.padding = 0; 8931 8932 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS); 8933 kvm_set_segment(vcpu, &ds, VCPU_SREG_DS); 8934 kvm_set_segment(vcpu, &ds, VCPU_SREG_ES); 8935 kvm_set_segment(vcpu, &ds, VCPU_SREG_FS); 8936 kvm_set_segment(vcpu, &ds, VCPU_SREG_GS); 8937 kvm_set_segment(vcpu, &ds, VCPU_SREG_SS); 8938 8939 #ifdef CONFIG_X86_64 8940 if (guest_cpuid_has(vcpu, X86_FEATURE_LM)) 8941 static_call(kvm_x86_set_efer)(vcpu, 0); 8942 #endif 8943 8944 kvm_update_cpuid_runtime(vcpu); 8945 kvm_mmu_reset_context(vcpu); 8946 } 8947 8948 static void process_smi(struct kvm_vcpu *vcpu) 8949 { 8950 vcpu->arch.smi_pending = true; 8951 kvm_make_request(KVM_REQ_EVENT, vcpu); 8952 } 8953 8954 void kvm_make_scan_ioapic_request_mask(struct kvm *kvm, 8955 unsigned long *vcpu_bitmap) 8956 { 8957 cpumask_var_t cpus; 8958 8959 zalloc_cpumask_var(&cpus, GFP_ATOMIC); 8960 8961 kvm_make_vcpus_request_mask(kvm, KVM_REQ_SCAN_IOAPIC, 8962 NULL, vcpu_bitmap, cpus); 8963 8964 free_cpumask_var(cpus); 8965 } 8966 8967 void kvm_make_scan_ioapic_request(struct kvm *kvm) 8968 { 8969 kvm_make_all_cpus_request(kvm, KVM_REQ_SCAN_IOAPIC); 8970 } 8971 8972 void kvm_vcpu_update_apicv(struct kvm_vcpu *vcpu) 8973 { 8974 if (!lapic_in_kernel(vcpu)) 8975 return; 8976 8977 vcpu->arch.apicv_active = kvm_apicv_activated(vcpu->kvm); 8978 kvm_apic_update_apicv(vcpu); 8979 static_call(kvm_x86_refresh_apicv_exec_ctrl)(vcpu); 8980 } 8981 EXPORT_SYMBOL_GPL(kvm_vcpu_update_apicv); 8982 8983 /* 8984 * NOTE: Do not hold any lock prior to calling this. 8985 * 8986 * In particular, kvm_request_apicv_update() expects kvm->srcu not to be 8987 * locked, because it calls __x86_set_memory_region() which does 8988 * synchronize_srcu(&kvm->srcu). 8989 */ 8990 void kvm_request_apicv_update(struct kvm *kvm, bool activate, ulong bit) 8991 { 8992 struct kvm_vcpu *except; 8993 unsigned long old, new, expected; 8994 8995 if (!kvm_x86_ops.check_apicv_inhibit_reasons || 8996 !static_call(kvm_x86_check_apicv_inhibit_reasons)(bit)) 8997 return; 8998 8999 old = READ_ONCE(kvm->arch.apicv_inhibit_reasons); 9000 do { 9001 expected = new = old; 9002 if (activate) 9003 __clear_bit(bit, &new); 9004 else 9005 __set_bit(bit, &new); 9006 if (new == old) 9007 break; 9008 old = cmpxchg(&kvm->arch.apicv_inhibit_reasons, expected, new); 9009 } while (old != expected); 9010 9011 if (!!old == !!new) 9012 return; 9013 9014 trace_kvm_apicv_update_request(activate, bit); 9015 if (kvm_x86_ops.pre_update_apicv_exec_ctrl) 9016 static_call(kvm_x86_pre_update_apicv_exec_ctrl)(kvm, activate); 9017 9018 /* 9019 * Sending request to update APICV for all other vcpus, 9020 * while update the calling vcpu immediately instead of 9021 * waiting for another #VMEXIT to handle the request. 9022 */ 9023 except = kvm_get_running_vcpu(); 9024 kvm_make_all_cpus_request_except(kvm, KVM_REQ_APICV_UPDATE, 9025 except); 9026 if (except) 9027 kvm_vcpu_update_apicv(except); 9028 } 9029 EXPORT_SYMBOL_GPL(kvm_request_apicv_update); 9030 9031 static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu) 9032 { 9033 if (!kvm_apic_present(vcpu)) 9034 return; 9035 9036 bitmap_zero(vcpu->arch.ioapic_handled_vectors, 256); 9037 9038 if (irqchip_split(vcpu->kvm)) 9039 kvm_scan_ioapic_routes(vcpu, vcpu->arch.ioapic_handled_vectors); 9040 else { 9041 if (vcpu->arch.apicv_active) 9042 static_call(kvm_x86_sync_pir_to_irr)(vcpu); 9043 if (ioapic_in_kernel(vcpu->kvm)) 9044 kvm_ioapic_scan_entry(vcpu, vcpu->arch.ioapic_handled_vectors); 9045 } 9046 9047 if (is_guest_mode(vcpu)) 9048 vcpu->arch.load_eoi_exitmap_pending = true; 9049 else 9050 kvm_make_request(KVM_REQ_LOAD_EOI_EXITMAP, vcpu); 9051 } 9052 9053 static void vcpu_load_eoi_exitmap(struct kvm_vcpu *vcpu) 9054 { 9055 u64 eoi_exit_bitmap[4]; 9056 9057 if (!kvm_apic_hw_enabled(vcpu->arch.apic)) 9058 return; 9059 9060 if (to_hv_vcpu(vcpu)) 9061 bitmap_or((ulong *)eoi_exit_bitmap, 9062 vcpu->arch.ioapic_handled_vectors, 9063 to_hv_synic(vcpu)->vec_bitmap, 256); 9064 9065 static_call(kvm_x86_load_eoi_exitmap)(vcpu, eoi_exit_bitmap); 9066 } 9067 9068 void kvm_arch_mmu_notifier_invalidate_range(struct kvm *kvm, 9069 unsigned long start, unsigned long end) 9070 { 9071 unsigned long apic_address; 9072 9073 /* 9074 * The physical address of apic access page is stored in the VMCS. 9075 * Update it when it becomes invalid. 9076 */ 9077 apic_address = gfn_to_hva(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT); 9078 if (start <= apic_address && apic_address < end) 9079 kvm_make_all_cpus_request(kvm, KVM_REQ_APIC_PAGE_RELOAD); 9080 } 9081 9082 void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu) 9083 { 9084 if (!lapic_in_kernel(vcpu)) 9085 return; 9086 9087 if (!kvm_x86_ops.set_apic_access_page_addr) 9088 return; 9089 9090 static_call(kvm_x86_set_apic_access_page_addr)(vcpu); 9091 } 9092 9093 void __kvm_request_immediate_exit(struct kvm_vcpu *vcpu) 9094 { 9095 smp_send_reschedule(vcpu->cpu); 9096 } 9097 EXPORT_SYMBOL_GPL(__kvm_request_immediate_exit); 9098 9099 /* 9100 * Returns 1 to let vcpu_run() continue the guest execution loop without 9101 * exiting to the userspace. Otherwise, the value will be returned to the 9102 * userspace. 9103 */ 9104 static int vcpu_enter_guest(struct kvm_vcpu *vcpu) 9105 { 9106 int r; 9107 bool req_int_win = 9108 dm_request_for_irq_injection(vcpu) && 9109 kvm_cpu_accept_dm_intr(vcpu); 9110 fastpath_t exit_fastpath; 9111 9112 bool req_immediate_exit = false; 9113 9114 /* Forbid vmenter if vcpu dirty ring is soft-full */ 9115 if (unlikely(vcpu->kvm->dirty_ring_size && 9116 kvm_dirty_ring_soft_full(&vcpu->dirty_ring))) { 9117 vcpu->run->exit_reason = KVM_EXIT_DIRTY_RING_FULL; 9118 trace_kvm_dirty_ring_exit(vcpu); 9119 r = 0; 9120 goto out; 9121 } 9122 9123 if (kvm_request_pending(vcpu)) { 9124 if (kvm_check_request(KVM_REQ_GET_NESTED_STATE_PAGES, vcpu)) { 9125 if (unlikely(!kvm_x86_ops.nested_ops->get_nested_state_pages(vcpu))) { 9126 r = 0; 9127 goto out; 9128 } 9129 } 9130 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu)) 9131 kvm_mmu_unload(vcpu); 9132 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu)) 9133 __kvm_migrate_timers(vcpu); 9134 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu)) 9135 kvm_gen_update_masterclock(vcpu->kvm); 9136 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu)) 9137 kvm_gen_kvmclock_update(vcpu); 9138 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) { 9139 r = kvm_guest_time_update(vcpu); 9140 if (unlikely(r)) 9141 goto out; 9142 } 9143 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu)) 9144 kvm_mmu_sync_roots(vcpu); 9145 if (kvm_check_request(KVM_REQ_LOAD_MMU_PGD, vcpu)) 9146 kvm_mmu_load_pgd(vcpu); 9147 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu)) { 9148 kvm_vcpu_flush_tlb_all(vcpu); 9149 9150 /* Flushing all ASIDs flushes the current ASID... */ 9151 kvm_clear_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu); 9152 } 9153 if (kvm_check_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu)) 9154 kvm_vcpu_flush_tlb_current(vcpu); 9155 if (kvm_check_request(KVM_REQ_HV_TLB_FLUSH, vcpu)) 9156 kvm_vcpu_flush_tlb_guest(vcpu); 9157 9158 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) { 9159 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS; 9160 r = 0; 9161 goto out; 9162 } 9163 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) { 9164 if (is_guest_mode(vcpu)) { 9165 kvm_x86_ops.nested_ops->triple_fault(vcpu); 9166 } else { 9167 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN; 9168 vcpu->mmio_needed = 0; 9169 r = 0; 9170 goto out; 9171 } 9172 } 9173 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) { 9174 /* Page is swapped out. Do synthetic halt */ 9175 vcpu->arch.apf.halted = true; 9176 r = 1; 9177 goto out; 9178 } 9179 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu)) 9180 record_steal_time(vcpu); 9181 if (kvm_check_request(KVM_REQ_SMI, vcpu)) 9182 process_smi(vcpu); 9183 if (kvm_check_request(KVM_REQ_NMI, vcpu)) 9184 process_nmi(vcpu); 9185 if (kvm_check_request(KVM_REQ_PMU, vcpu)) 9186 kvm_pmu_handle_event(vcpu); 9187 if (kvm_check_request(KVM_REQ_PMI, vcpu)) 9188 kvm_pmu_deliver_pmi(vcpu); 9189 if (kvm_check_request(KVM_REQ_IOAPIC_EOI_EXIT, vcpu)) { 9190 BUG_ON(vcpu->arch.pending_ioapic_eoi > 255); 9191 if (test_bit(vcpu->arch.pending_ioapic_eoi, 9192 vcpu->arch.ioapic_handled_vectors)) { 9193 vcpu->run->exit_reason = KVM_EXIT_IOAPIC_EOI; 9194 vcpu->run->eoi.vector = 9195 vcpu->arch.pending_ioapic_eoi; 9196 r = 0; 9197 goto out; 9198 } 9199 } 9200 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu)) 9201 vcpu_scan_ioapic(vcpu); 9202 if (kvm_check_request(KVM_REQ_LOAD_EOI_EXITMAP, vcpu)) 9203 vcpu_load_eoi_exitmap(vcpu); 9204 if (kvm_check_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu)) 9205 kvm_vcpu_reload_apic_access_page(vcpu); 9206 if (kvm_check_request(KVM_REQ_HV_CRASH, vcpu)) { 9207 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT; 9208 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_CRASH; 9209 r = 0; 9210 goto out; 9211 } 9212 if (kvm_check_request(KVM_REQ_HV_RESET, vcpu)) { 9213 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT; 9214 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_RESET; 9215 r = 0; 9216 goto out; 9217 } 9218 if (kvm_check_request(KVM_REQ_HV_EXIT, vcpu)) { 9219 struct kvm_vcpu_hv *hv_vcpu = to_hv_vcpu(vcpu); 9220 9221 vcpu->run->exit_reason = KVM_EXIT_HYPERV; 9222 vcpu->run->hyperv = hv_vcpu->exit; 9223 r = 0; 9224 goto out; 9225 } 9226 9227 /* 9228 * KVM_REQ_HV_STIMER has to be processed after 9229 * KVM_REQ_CLOCK_UPDATE, because Hyper-V SynIC timers 9230 * depend on the guest clock being up-to-date 9231 */ 9232 if (kvm_check_request(KVM_REQ_HV_STIMER, vcpu)) 9233 kvm_hv_process_stimers(vcpu); 9234 if (kvm_check_request(KVM_REQ_APICV_UPDATE, vcpu)) 9235 kvm_vcpu_update_apicv(vcpu); 9236 if (kvm_check_request(KVM_REQ_APF_READY, vcpu)) 9237 kvm_check_async_pf_completion(vcpu); 9238 if (kvm_check_request(KVM_REQ_MSR_FILTER_CHANGED, vcpu)) 9239 static_call(kvm_x86_msr_filter_changed)(vcpu); 9240 9241 if (kvm_check_request(KVM_REQ_UPDATE_CPU_DIRTY_LOGGING, vcpu)) 9242 static_call(kvm_x86_update_cpu_dirty_logging)(vcpu); 9243 } 9244 9245 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win || 9246 kvm_xen_has_interrupt(vcpu)) { 9247 ++vcpu->stat.req_event; 9248 kvm_apic_accept_events(vcpu); 9249 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) { 9250 r = 1; 9251 goto out; 9252 } 9253 9254 inject_pending_event(vcpu, &req_immediate_exit); 9255 if (req_int_win) 9256 static_call(kvm_x86_enable_irq_window)(vcpu); 9257 9258 if (kvm_lapic_enabled(vcpu)) { 9259 update_cr8_intercept(vcpu); 9260 kvm_lapic_sync_to_vapic(vcpu); 9261 } 9262 } 9263 9264 r = kvm_mmu_reload(vcpu); 9265 if (unlikely(r)) { 9266 goto cancel_injection; 9267 } 9268 9269 preempt_disable(); 9270 9271 static_call(kvm_x86_prepare_guest_switch)(vcpu); 9272 9273 /* 9274 * Disable IRQs before setting IN_GUEST_MODE. Posted interrupt 9275 * IPI are then delayed after guest entry, which ensures that they 9276 * result in virtual interrupt delivery. 9277 */ 9278 local_irq_disable(); 9279 vcpu->mode = IN_GUEST_MODE; 9280 9281 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx); 9282 9283 /* 9284 * 1) We should set ->mode before checking ->requests. Please see 9285 * the comment in kvm_vcpu_exiting_guest_mode(). 9286 * 9287 * 2) For APICv, we should set ->mode before checking PID.ON. This 9288 * pairs with the memory barrier implicit in pi_test_and_set_on 9289 * (see vmx_deliver_posted_interrupt). 9290 * 9291 * 3) This also orders the write to mode from any reads to the page 9292 * tables done while the VCPU is running. Please see the comment 9293 * in kvm_flush_remote_tlbs. 9294 */ 9295 smp_mb__after_srcu_read_unlock(); 9296 9297 /* 9298 * This handles the case where a posted interrupt was 9299 * notified with kvm_vcpu_kick. 9300 */ 9301 if (kvm_lapic_enabled(vcpu) && vcpu->arch.apicv_active) 9302 static_call(kvm_x86_sync_pir_to_irr)(vcpu); 9303 9304 if (kvm_vcpu_exit_request(vcpu)) { 9305 vcpu->mode = OUTSIDE_GUEST_MODE; 9306 smp_wmb(); 9307 local_irq_enable(); 9308 preempt_enable(); 9309 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu); 9310 r = 1; 9311 goto cancel_injection; 9312 } 9313 9314 if (req_immediate_exit) { 9315 kvm_make_request(KVM_REQ_EVENT, vcpu); 9316 static_call(kvm_x86_request_immediate_exit)(vcpu); 9317 } 9318 9319 fpregs_assert_state_consistent(); 9320 if (test_thread_flag(TIF_NEED_FPU_LOAD)) 9321 switch_fpu_return(); 9322 9323 if (unlikely(vcpu->arch.switch_db_regs)) { 9324 set_debugreg(0, 7); 9325 set_debugreg(vcpu->arch.eff_db[0], 0); 9326 set_debugreg(vcpu->arch.eff_db[1], 1); 9327 set_debugreg(vcpu->arch.eff_db[2], 2); 9328 set_debugreg(vcpu->arch.eff_db[3], 3); 9329 set_debugreg(vcpu->arch.dr6, 6); 9330 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD; 9331 } 9332 9333 for (;;) { 9334 exit_fastpath = static_call(kvm_x86_run)(vcpu); 9335 if (likely(exit_fastpath != EXIT_FASTPATH_REENTER_GUEST)) 9336 break; 9337 9338 if (unlikely(kvm_vcpu_exit_request(vcpu))) { 9339 exit_fastpath = EXIT_FASTPATH_EXIT_HANDLED; 9340 break; 9341 } 9342 9343 if (vcpu->arch.apicv_active) 9344 static_call(kvm_x86_sync_pir_to_irr)(vcpu); 9345 } 9346 9347 /* 9348 * Do this here before restoring debug registers on the host. And 9349 * since we do this before handling the vmexit, a DR access vmexit 9350 * can (a) read the correct value of the debug registers, (b) set 9351 * KVM_DEBUGREG_WONT_EXIT again. 9352 */ 9353 if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) { 9354 WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP); 9355 static_call(kvm_x86_sync_dirty_debug_regs)(vcpu); 9356 kvm_update_dr0123(vcpu); 9357 kvm_update_dr7(vcpu); 9358 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD; 9359 } 9360 9361 /* 9362 * If the guest has used debug registers, at least dr7 9363 * will be disabled while returning to the host. 9364 * If we don't have active breakpoints in the host, we don't 9365 * care about the messed up debug address registers. But if 9366 * we have some of them active, restore the old state. 9367 */ 9368 if (hw_breakpoint_active()) 9369 hw_breakpoint_restore(); 9370 9371 vcpu->arch.last_vmentry_cpu = vcpu->cpu; 9372 vcpu->arch.last_guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc()); 9373 9374 vcpu->mode = OUTSIDE_GUEST_MODE; 9375 smp_wmb(); 9376 9377 static_call(kvm_x86_handle_exit_irqoff)(vcpu); 9378 9379 /* 9380 * Consume any pending interrupts, including the possible source of 9381 * VM-Exit on SVM and any ticks that occur between VM-Exit and now. 9382 * An instruction is required after local_irq_enable() to fully unblock 9383 * interrupts on processors that implement an interrupt shadow, the 9384 * stat.exits increment will do nicely. 9385 */ 9386 kvm_before_interrupt(vcpu); 9387 local_irq_enable(); 9388 ++vcpu->stat.exits; 9389 local_irq_disable(); 9390 kvm_after_interrupt(vcpu); 9391 9392 /* 9393 * Wait until after servicing IRQs to account guest time so that any 9394 * ticks that occurred while running the guest are properly accounted 9395 * to the guest. Waiting until IRQs are enabled degrades the accuracy 9396 * of accounting via context tracking, but the loss of accuracy is 9397 * acceptable for all known use cases. 9398 */ 9399 vtime_account_guest_exit(); 9400 9401 if (lapic_in_kernel(vcpu)) { 9402 s64 delta = vcpu->arch.apic->lapic_timer.advance_expire_delta; 9403 if (delta != S64_MIN) { 9404 trace_kvm_wait_lapic_expire(vcpu->vcpu_id, delta); 9405 vcpu->arch.apic->lapic_timer.advance_expire_delta = S64_MIN; 9406 } 9407 } 9408 9409 local_irq_enable(); 9410 preempt_enable(); 9411 9412 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu); 9413 9414 /* 9415 * Profile KVM exit RIPs: 9416 */ 9417 if (unlikely(prof_on == KVM_PROFILING)) { 9418 unsigned long rip = kvm_rip_read(vcpu); 9419 profile_hit(KVM_PROFILING, (void *)rip); 9420 } 9421 9422 if (unlikely(vcpu->arch.tsc_always_catchup)) 9423 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 9424 9425 if (vcpu->arch.apic_attention) 9426 kvm_lapic_sync_from_vapic(vcpu); 9427 9428 r = static_call(kvm_x86_handle_exit)(vcpu, exit_fastpath); 9429 return r; 9430 9431 cancel_injection: 9432 if (req_immediate_exit) 9433 kvm_make_request(KVM_REQ_EVENT, vcpu); 9434 static_call(kvm_x86_cancel_injection)(vcpu); 9435 if (unlikely(vcpu->arch.apic_attention)) 9436 kvm_lapic_sync_from_vapic(vcpu); 9437 out: 9438 return r; 9439 } 9440 9441 static inline int vcpu_block(struct kvm *kvm, struct kvm_vcpu *vcpu) 9442 { 9443 if (!kvm_arch_vcpu_runnable(vcpu) && 9444 (!kvm_x86_ops.pre_block || static_call(kvm_x86_pre_block)(vcpu) == 0)) { 9445 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx); 9446 kvm_vcpu_block(vcpu); 9447 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu); 9448 9449 if (kvm_x86_ops.post_block) 9450 static_call(kvm_x86_post_block)(vcpu); 9451 9452 if (!kvm_check_request(KVM_REQ_UNHALT, vcpu)) 9453 return 1; 9454 } 9455 9456 kvm_apic_accept_events(vcpu); 9457 switch(vcpu->arch.mp_state) { 9458 case KVM_MP_STATE_HALTED: 9459 case KVM_MP_STATE_AP_RESET_HOLD: 9460 vcpu->arch.pv.pv_unhalted = false; 9461 vcpu->arch.mp_state = 9462 KVM_MP_STATE_RUNNABLE; 9463 fallthrough; 9464 case KVM_MP_STATE_RUNNABLE: 9465 vcpu->arch.apf.halted = false; 9466 break; 9467 case KVM_MP_STATE_INIT_RECEIVED: 9468 break; 9469 default: 9470 return -EINTR; 9471 } 9472 return 1; 9473 } 9474 9475 static inline bool kvm_vcpu_running(struct kvm_vcpu *vcpu) 9476 { 9477 if (is_guest_mode(vcpu)) 9478 kvm_check_nested_events(vcpu); 9479 9480 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE && 9481 !vcpu->arch.apf.halted); 9482 } 9483 9484 static int vcpu_run(struct kvm_vcpu *vcpu) 9485 { 9486 int r; 9487 struct kvm *kvm = vcpu->kvm; 9488 9489 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu); 9490 vcpu->arch.l1tf_flush_l1d = true; 9491 9492 for (;;) { 9493 if (kvm_vcpu_running(vcpu)) { 9494 r = vcpu_enter_guest(vcpu); 9495 } else { 9496 r = vcpu_block(kvm, vcpu); 9497 } 9498 9499 if (r <= 0) 9500 break; 9501 9502 kvm_clear_request(KVM_REQ_UNBLOCK, vcpu); 9503 if (kvm_cpu_has_pending_timer(vcpu)) 9504 kvm_inject_pending_timer_irqs(vcpu); 9505 9506 if (dm_request_for_irq_injection(vcpu) && 9507 kvm_vcpu_ready_for_interrupt_injection(vcpu)) { 9508 r = 0; 9509 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN; 9510 ++vcpu->stat.request_irq_exits; 9511 break; 9512 } 9513 9514 if (__xfer_to_guest_mode_work_pending()) { 9515 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx); 9516 r = xfer_to_guest_mode_handle_work(vcpu); 9517 if (r) 9518 return r; 9519 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu); 9520 } 9521 } 9522 9523 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx); 9524 9525 return r; 9526 } 9527 9528 static inline int complete_emulated_io(struct kvm_vcpu *vcpu) 9529 { 9530 int r; 9531 9532 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu); 9533 r = kvm_emulate_instruction(vcpu, EMULTYPE_NO_DECODE); 9534 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx); 9535 return r; 9536 } 9537 9538 static int complete_emulated_pio(struct kvm_vcpu *vcpu) 9539 { 9540 BUG_ON(!vcpu->arch.pio.count); 9541 9542 return complete_emulated_io(vcpu); 9543 } 9544 9545 /* 9546 * Implements the following, as a state machine: 9547 * 9548 * read: 9549 * for each fragment 9550 * for each mmio piece in the fragment 9551 * write gpa, len 9552 * exit 9553 * copy data 9554 * execute insn 9555 * 9556 * write: 9557 * for each fragment 9558 * for each mmio piece in the fragment 9559 * write gpa, len 9560 * copy data 9561 * exit 9562 */ 9563 static int complete_emulated_mmio(struct kvm_vcpu *vcpu) 9564 { 9565 struct kvm_run *run = vcpu->run; 9566 struct kvm_mmio_fragment *frag; 9567 unsigned len; 9568 9569 BUG_ON(!vcpu->mmio_needed); 9570 9571 /* Complete previous fragment */ 9572 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment]; 9573 len = min(8u, frag->len); 9574 if (!vcpu->mmio_is_write) 9575 memcpy(frag->data, run->mmio.data, len); 9576 9577 if (frag->len <= 8) { 9578 /* Switch to the next fragment. */ 9579 frag++; 9580 vcpu->mmio_cur_fragment++; 9581 } else { 9582 /* Go forward to the next mmio piece. */ 9583 frag->data += len; 9584 frag->gpa += len; 9585 frag->len -= len; 9586 } 9587 9588 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) { 9589 vcpu->mmio_needed = 0; 9590 9591 /* FIXME: return into emulator if single-stepping. */ 9592 if (vcpu->mmio_is_write) 9593 return 1; 9594 vcpu->mmio_read_completed = 1; 9595 return complete_emulated_io(vcpu); 9596 } 9597 9598 run->exit_reason = KVM_EXIT_MMIO; 9599 run->mmio.phys_addr = frag->gpa; 9600 if (vcpu->mmio_is_write) 9601 memcpy(run->mmio.data, frag->data, min(8u, frag->len)); 9602 run->mmio.len = min(8u, frag->len); 9603 run->mmio.is_write = vcpu->mmio_is_write; 9604 vcpu->arch.complete_userspace_io = complete_emulated_mmio; 9605 return 0; 9606 } 9607 9608 static void kvm_save_current_fpu(struct fpu *fpu) 9609 { 9610 /* 9611 * If the target FPU state is not resident in the CPU registers, just 9612 * memcpy() from current, else save CPU state directly to the target. 9613 */ 9614 if (test_thread_flag(TIF_NEED_FPU_LOAD)) 9615 memcpy(&fpu->state, ¤t->thread.fpu.state, 9616 fpu_kernel_xstate_size); 9617 else 9618 copy_fpregs_to_fpstate(fpu); 9619 } 9620 9621 /* Swap (qemu) user FPU context for the guest FPU context. */ 9622 static void kvm_load_guest_fpu(struct kvm_vcpu *vcpu) 9623 { 9624 fpregs_lock(); 9625 9626 kvm_save_current_fpu(vcpu->arch.user_fpu); 9627 9628 /* 9629 * Guests with protected state can't have it set by the hypervisor, 9630 * so skip trying to set it. 9631 */ 9632 if (vcpu->arch.guest_fpu) 9633 /* PKRU is separately restored in kvm_x86_ops.run. */ 9634 __copy_kernel_to_fpregs(&vcpu->arch.guest_fpu->state, 9635 ~XFEATURE_MASK_PKRU); 9636 9637 fpregs_mark_activate(); 9638 fpregs_unlock(); 9639 9640 trace_kvm_fpu(1); 9641 } 9642 9643 /* When vcpu_run ends, restore user space FPU context. */ 9644 static void kvm_put_guest_fpu(struct kvm_vcpu *vcpu) 9645 { 9646 fpregs_lock(); 9647 9648 /* 9649 * Guests with protected state can't have it read by the hypervisor, 9650 * so skip trying to save it. 9651 */ 9652 if (vcpu->arch.guest_fpu) 9653 kvm_save_current_fpu(vcpu->arch.guest_fpu); 9654 9655 copy_kernel_to_fpregs(&vcpu->arch.user_fpu->state); 9656 9657 fpregs_mark_activate(); 9658 fpregs_unlock(); 9659 9660 ++vcpu->stat.fpu_reload; 9661 trace_kvm_fpu(0); 9662 } 9663 9664 int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu) 9665 { 9666 struct kvm_run *kvm_run = vcpu->run; 9667 int r; 9668 9669 vcpu_load(vcpu); 9670 kvm_sigset_activate(vcpu); 9671 kvm_run->flags = 0; 9672 kvm_load_guest_fpu(vcpu); 9673 9674 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) { 9675 if (kvm_run->immediate_exit) { 9676 r = -EINTR; 9677 goto out; 9678 } 9679 kvm_vcpu_block(vcpu); 9680 kvm_apic_accept_events(vcpu); 9681 kvm_clear_request(KVM_REQ_UNHALT, vcpu); 9682 r = -EAGAIN; 9683 if (signal_pending(current)) { 9684 r = -EINTR; 9685 kvm_run->exit_reason = KVM_EXIT_INTR; 9686 ++vcpu->stat.signal_exits; 9687 } 9688 goto out; 9689 } 9690 9691 if (kvm_run->kvm_valid_regs & ~KVM_SYNC_X86_VALID_FIELDS) { 9692 r = -EINVAL; 9693 goto out; 9694 } 9695 9696 if (kvm_run->kvm_dirty_regs) { 9697 r = sync_regs(vcpu); 9698 if (r != 0) 9699 goto out; 9700 } 9701 9702 /* re-sync apic's tpr */ 9703 if (!lapic_in_kernel(vcpu)) { 9704 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) { 9705 r = -EINVAL; 9706 goto out; 9707 } 9708 } 9709 9710 if (unlikely(vcpu->arch.complete_userspace_io)) { 9711 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io; 9712 vcpu->arch.complete_userspace_io = NULL; 9713 r = cui(vcpu); 9714 if (r <= 0) 9715 goto out; 9716 } else 9717 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed); 9718 9719 if (kvm_run->immediate_exit) 9720 r = -EINTR; 9721 else 9722 r = vcpu_run(vcpu); 9723 9724 out: 9725 kvm_put_guest_fpu(vcpu); 9726 if (kvm_run->kvm_valid_regs) 9727 store_regs(vcpu); 9728 post_kvm_run_save(vcpu); 9729 kvm_sigset_deactivate(vcpu); 9730 9731 vcpu_put(vcpu); 9732 return r; 9733 } 9734 9735 static void __get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) 9736 { 9737 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) { 9738 /* 9739 * We are here if userspace calls get_regs() in the middle of 9740 * instruction emulation. Registers state needs to be copied 9741 * back from emulation context to vcpu. Userspace shouldn't do 9742 * that usually, but some bad designed PV devices (vmware 9743 * backdoor interface) need this to work 9744 */ 9745 emulator_writeback_register_cache(vcpu->arch.emulate_ctxt); 9746 vcpu->arch.emulate_regs_need_sync_to_vcpu = false; 9747 } 9748 regs->rax = kvm_rax_read(vcpu); 9749 regs->rbx = kvm_rbx_read(vcpu); 9750 regs->rcx = kvm_rcx_read(vcpu); 9751 regs->rdx = kvm_rdx_read(vcpu); 9752 regs->rsi = kvm_rsi_read(vcpu); 9753 regs->rdi = kvm_rdi_read(vcpu); 9754 regs->rsp = kvm_rsp_read(vcpu); 9755 regs->rbp = kvm_rbp_read(vcpu); 9756 #ifdef CONFIG_X86_64 9757 regs->r8 = kvm_r8_read(vcpu); 9758 regs->r9 = kvm_r9_read(vcpu); 9759 regs->r10 = kvm_r10_read(vcpu); 9760 regs->r11 = kvm_r11_read(vcpu); 9761 regs->r12 = kvm_r12_read(vcpu); 9762 regs->r13 = kvm_r13_read(vcpu); 9763 regs->r14 = kvm_r14_read(vcpu); 9764 regs->r15 = kvm_r15_read(vcpu); 9765 #endif 9766 9767 regs->rip = kvm_rip_read(vcpu); 9768 regs->rflags = kvm_get_rflags(vcpu); 9769 } 9770 9771 int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) 9772 { 9773 vcpu_load(vcpu); 9774 __get_regs(vcpu, regs); 9775 vcpu_put(vcpu); 9776 return 0; 9777 } 9778 9779 static void __set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) 9780 { 9781 vcpu->arch.emulate_regs_need_sync_from_vcpu = true; 9782 vcpu->arch.emulate_regs_need_sync_to_vcpu = false; 9783 9784 kvm_rax_write(vcpu, regs->rax); 9785 kvm_rbx_write(vcpu, regs->rbx); 9786 kvm_rcx_write(vcpu, regs->rcx); 9787 kvm_rdx_write(vcpu, regs->rdx); 9788 kvm_rsi_write(vcpu, regs->rsi); 9789 kvm_rdi_write(vcpu, regs->rdi); 9790 kvm_rsp_write(vcpu, regs->rsp); 9791 kvm_rbp_write(vcpu, regs->rbp); 9792 #ifdef CONFIG_X86_64 9793 kvm_r8_write(vcpu, regs->r8); 9794 kvm_r9_write(vcpu, regs->r9); 9795 kvm_r10_write(vcpu, regs->r10); 9796 kvm_r11_write(vcpu, regs->r11); 9797 kvm_r12_write(vcpu, regs->r12); 9798 kvm_r13_write(vcpu, regs->r13); 9799 kvm_r14_write(vcpu, regs->r14); 9800 kvm_r15_write(vcpu, regs->r15); 9801 #endif 9802 9803 kvm_rip_write(vcpu, regs->rip); 9804 kvm_set_rflags(vcpu, regs->rflags | X86_EFLAGS_FIXED); 9805 9806 vcpu->arch.exception.pending = false; 9807 9808 kvm_make_request(KVM_REQ_EVENT, vcpu); 9809 } 9810 9811 int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) 9812 { 9813 vcpu_load(vcpu); 9814 __set_regs(vcpu, regs); 9815 vcpu_put(vcpu); 9816 return 0; 9817 } 9818 9819 void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l) 9820 { 9821 struct kvm_segment cs; 9822 9823 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS); 9824 *db = cs.db; 9825 *l = cs.l; 9826 } 9827 EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits); 9828 9829 static void __get_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs) 9830 { 9831 struct desc_ptr dt; 9832 9833 if (vcpu->arch.guest_state_protected) 9834 goto skip_protected_regs; 9835 9836 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS); 9837 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS); 9838 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES); 9839 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS); 9840 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS); 9841 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS); 9842 9843 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR); 9844 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR); 9845 9846 static_call(kvm_x86_get_idt)(vcpu, &dt); 9847 sregs->idt.limit = dt.size; 9848 sregs->idt.base = dt.address; 9849 static_call(kvm_x86_get_gdt)(vcpu, &dt); 9850 sregs->gdt.limit = dt.size; 9851 sregs->gdt.base = dt.address; 9852 9853 sregs->cr2 = vcpu->arch.cr2; 9854 sregs->cr3 = kvm_read_cr3(vcpu); 9855 9856 skip_protected_regs: 9857 sregs->cr0 = kvm_read_cr0(vcpu); 9858 sregs->cr4 = kvm_read_cr4(vcpu); 9859 sregs->cr8 = kvm_get_cr8(vcpu); 9860 sregs->efer = vcpu->arch.efer; 9861 sregs->apic_base = kvm_get_apic_base(vcpu); 9862 9863 memset(sregs->interrupt_bitmap, 0, sizeof(sregs->interrupt_bitmap)); 9864 9865 if (vcpu->arch.interrupt.injected && !vcpu->arch.interrupt.soft) 9866 set_bit(vcpu->arch.interrupt.nr, 9867 (unsigned long *)sregs->interrupt_bitmap); 9868 } 9869 9870 int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu, 9871 struct kvm_sregs *sregs) 9872 { 9873 vcpu_load(vcpu); 9874 __get_sregs(vcpu, sregs); 9875 vcpu_put(vcpu); 9876 return 0; 9877 } 9878 9879 int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu, 9880 struct kvm_mp_state *mp_state) 9881 { 9882 vcpu_load(vcpu); 9883 if (kvm_mpx_supported()) 9884 kvm_load_guest_fpu(vcpu); 9885 9886 kvm_apic_accept_events(vcpu); 9887 if ((vcpu->arch.mp_state == KVM_MP_STATE_HALTED || 9888 vcpu->arch.mp_state == KVM_MP_STATE_AP_RESET_HOLD) && 9889 vcpu->arch.pv.pv_unhalted) 9890 mp_state->mp_state = KVM_MP_STATE_RUNNABLE; 9891 else 9892 mp_state->mp_state = vcpu->arch.mp_state; 9893 9894 if (kvm_mpx_supported()) 9895 kvm_put_guest_fpu(vcpu); 9896 vcpu_put(vcpu); 9897 return 0; 9898 } 9899 9900 int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu, 9901 struct kvm_mp_state *mp_state) 9902 { 9903 int ret = -EINVAL; 9904 9905 vcpu_load(vcpu); 9906 9907 if (!lapic_in_kernel(vcpu) && 9908 mp_state->mp_state != KVM_MP_STATE_RUNNABLE) 9909 goto out; 9910 9911 /* 9912 * KVM_MP_STATE_INIT_RECEIVED means the processor is in 9913 * INIT state; latched init should be reported using 9914 * KVM_SET_VCPU_EVENTS, so reject it here. 9915 */ 9916 if ((kvm_vcpu_latch_init(vcpu) || vcpu->arch.smi_pending) && 9917 (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED || 9918 mp_state->mp_state == KVM_MP_STATE_INIT_RECEIVED)) 9919 goto out; 9920 9921 if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) { 9922 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED; 9923 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events); 9924 } else 9925 vcpu->arch.mp_state = mp_state->mp_state; 9926 kvm_make_request(KVM_REQ_EVENT, vcpu); 9927 9928 ret = 0; 9929 out: 9930 vcpu_put(vcpu); 9931 return ret; 9932 } 9933 9934 int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index, 9935 int reason, bool has_error_code, u32 error_code) 9936 { 9937 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt; 9938 int ret; 9939 9940 init_emulate_ctxt(vcpu); 9941 9942 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason, 9943 has_error_code, error_code); 9944 if (ret) { 9945 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR; 9946 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION; 9947 vcpu->run->internal.ndata = 0; 9948 return 0; 9949 } 9950 9951 kvm_rip_write(vcpu, ctxt->eip); 9952 kvm_set_rflags(vcpu, ctxt->eflags); 9953 return 1; 9954 } 9955 EXPORT_SYMBOL_GPL(kvm_task_switch); 9956 9957 static bool kvm_is_valid_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs) 9958 { 9959 if ((sregs->efer & EFER_LME) && (sregs->cr0 & X86_CR0_PG)) { 9960 /* 9961 * When EFER.LME and CR0.PG are set, the processor is in 9962 * 64-bit mode (though maybe in a 32-bit code segment). 9963 * CR4.PAE and EFER.LMA must be set. 9964 */ 9965 if (!(sregs->cr4 & X86_CR4_PAE) || !(sregs->efer & EFER_LMA)) 9966 return false; 9967 if (kvm_vcpu_is_illegal_gpa(vcpu, sregs->cr3)) 9968 return false; 9969 } else { 9970 /* 9971 * Not in 64-bit mode: EFER.LMA is clear and the code 9972 * segment cannot be 64-bit. 9973 */ 9974 if (sregs->efer & EFER_LMA || sregs->cs.l) 9975 return false; 9976 } 9977 9978 return kvm_is_valid_cr4(vcpu, sregs->cr4); 9979 } 9980 9981 static int __set_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs) 9982 { 9983 struct msr_data apic_base_msr; 9984 int mmu_reset_needed = 0; 9985 int pending_vec, max_bits, idx; 9986 struct desc_ptr dt; 9987 int ret = -EINVAL; 9988 9989 if (!kvm_is_valid_sregs(vcpu, sregs)) 9990 goto out; 9991 9992 apic_base_msr.data = sregs->apic_base; 9993 apic_base_msr.host_initiated = true; 9994 if (kvm_set_apic_base(vcpu, &apic_base_msr)) 9995 goto out; 9996 9997 if (vcpu->arch.guest_state_protected) 9998 goto skip_protected_regs; 9999 10000 dt.size = sregs->idt.limit; 10001 dt.address = sregs->idt.base; 10002 static_call(kvm_x86_set_idt)(vcpu, &dt); 10003 dt.size = sregs->gdt.limit; 10004 dt.address = sregs->gdt.base; 10005 static_call(kvm_x86_set_gdt)(vcpu, &dt); 10006 10007 vcpu->arch.cr2 = sregs->cr2; 10008 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3; 10009 vcpu->arch.cr3 = sregs->cr3; 10010 kvm_register_mark_available(vcpu, VCPU_EXREG_CR3); 10011 10012 kvm_set_cr8(vcpu, sregs->cr8); 10013 10014 mmu_reset_needed |= vcpu->arch.efer != sregs->efer; 10015 static_call(kvm_x86_set_efer)(vcpu, sregs->efer); 10016 10017 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0; 10018 static_call(kvm_x86_set_cr0)(vcpu, sregs->cr0); 10019 vcpu->arch.cr0 = sregs->cr0; 10020 10021 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4; 10022 static_call(kvm_x86_set_cr4)(vcpu, sregs->cr4); 10023 10024 idx = srcu_read_lock(&vcpu->kvm->srcu); 10025 if (is_pae_paging(vcpu)) { 10026 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu)); 10027 mmu_reset_needed = 1; 10028 } 10029 srcu_read_unlock(&vcpu->kvm->srcu, idx); 10030 10031 if (mmu_reset_needed) 10032 kvm_mmu_reset_context(vcpu); 10033 10034 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS); 10035 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS); 10036 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES); 10037 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS); 10038 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS); 10039 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS); 10040 10041 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR); 10042 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR); 10043 10044 update_cr8_intercept(vcpu); 10045 10046 /* Older userspace won't unhalt the vcpu on reset. */ 10047 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 && 10048 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 && 10049 !is_protmode(vcpu)) 10050 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; 10051 10052 skip_protected_regs: 10053 max_bits = KVM_NR_INTERRUPTS; 10054 pending_vec = find_first_bit( 10055 (const unsigned long *)sregs->interrupt_bitmap, max_bits); 10056 if (pending_vec < max_bits) { 10057 kvm_queue_interrupt(vcpu, pending_vec, false); 10058 pr_debug("Set back pending irq %d\n", pending_vec); 10059 } 10060 10061 kvm_make_request(KVM_REQ_EVENT, vcpu); 10062 10063 ret = 0; 10064 out: 10065 return ret; 10066 } 10067 10068 int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu, 10069 struct kvm_sregs *sregs) 10070 { 10071 int ret; 10072 10073 vcpu_load(vcpu); 10074 ret = __set_sregs(vcpu, sregs); 10075 vcpu_put(vcpu); 10076 return ret; 10077 } 10078 10079 int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu, 10080 struct kvm_guest_debug *dbg) 10081 { 10082 unsigned long rflags; 10083 int i, r; 10084 10085 if (vcpu->arch.guest_state_protected) 10086 return -EINVAL; 10087 10088 vcpu_load(vcpu); 10089 10090 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) { 10091 r = -EBUSY; 10092 if (vcpu->arch.exception.pending) 10093 goto out; 10094 if (dbg->control & KVM_GUESTDBG_INJECT_DB) 10095 kvm_queue_exception(vcpu, DB_VECTOR); 10096 else 10097 kvm_queue_exception(vcpu, BP_VECTOR); 10098 } 10099 10100 /* 10101 * Read rflags as long as potentially injected trace flags are still 10102 * filtered out. 10103 */ 10104 rflags = kvm_get_rflags(vcpu); 10105 10106 vcpu->guest_debug = dbg->control; 10107 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE)) 10108 vcpu->guest_debug = 0; 10109 10110 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) { 10111 for (i = 0; i < KVM_NR_DB_REGS; ++i) 10112 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i]; 10113 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7]; 10114 } else { 10115 for (i = 0; i < KVM_NR_DB_REGS; i++) 10116 vcpu->arch.eff_db[i] = vcpu->arch.db[i]; 10117 } 10118 kvm_update_dr7(vcpu); 10119 10120 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) 10121 vcpu->arch.singlestep_rip = kvm_get_linear_rip(vcpu); 10122 10123 /* 10124 * Trigger an rflags update that will inject or remove the trace 10125 * flags. 10126 */ 10127 kvm_set_rflags(vcpu, rflags); 10128 10129 static_call(kvm_x86_update_exception_bitmap)(vcpu); 10130 10131 r = 0; 10132 10133 out: 10134 vcpu_put(vcpu); 10135 return r; 10136 } 10137 10138 /* 10139 * Translate a guest virtual address to a guest physical address. 10140 */ 10141 int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu, 10142 struct kvm_translation *tr) 10143 { 10144 unsigned long vaddr = tr->linear_address; 10145 gpa_t gpa; 10146 int idx; 10147 10148 vcpu_load(vcpu); 10149 10150 idx = srcu_read_lock(&vcpu->kvm->srcu); 10151 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL); 10152 srcu_read_unlock(&vcpu->kvm->srcu, idx); 10153 tr->physical_address = gpa; 10154 tr->valid = gpa != UNMAPPED_GVA; 10155 tr->writeable = 1; 10156 tr->usermode = 0; 10157 10158 vcpu_put(vcpu); 10159 return 0; 10160 } 10161 10162 int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu) 10163 { 10164 struct fxregs_state *fxsave; 10165 10166 if (!vcpu->arch.guest_fpu) 10167 return 0; 10168 10169 vcpu_load(vcpu); 10170 10171 fxsave = &vcpu->arch.guest_fpu->state.fxsave; 10172 memcpy(fpu->fpr, fxsave->st_space, 128); 10173 fpu->fcw = fxsave->cwd; 10174 fpu->fsw = fxsave->swd; 10175 fpu->ftwx = fxsave->twd; 10176 fpu->last_opcode = fxsave->fop; 10177 fpu->last_ip = fxsave->rip; 10178 fpu->last_dp = fxsave->rdp; 10179 memcpy(fpu->xmm, fxsave->xmm_space, sizeof(fxsave->xmm_space)); 10180 10181 vcpu_put(vcpu); 10182 return 0; 10183 } 10184 10185 int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu) 10186 { 10187 struct fxregs_state *fxsave; 10188 10189 if (!vcpu->arch.guest_fpu) 10190 return 0; 10191 10192 vcpu_load(vcpu); 10193 10194 fxsave = &vcpu->arch.guest_fpu->state.fxsave; 10195 10196 memcpy(fxsave->st_space, fpu->fpr, 128); 10197 fxsave->cwd = fpu->fcw; 10198 fxsave->swd = fpu->fsw; 10199 fxsave->twd = fpu->ftwx; 10200 fxsave->fop = fpu->last_opcode; 10201 fxsave->rip = fpu->last_ip; 10202 fxsave->rdp = fpu->last_dp; 10203 memcpy(fxsave->xmm_space, fpu->xmm, sizeof(fxsave->xmm_space)); 10204 10205 vcpu_put(vcpu); 10206 return 0; 10207 } 10208 10209 static void store_regs(struct kvm_vcpu *vcpu) 10210 { 10211 BUILD_BUG_ON(sizeof(struct kvm_sync_regs) > SYNC_REGS_SIZE_BYTES); 10212 10213 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_REGS) 10214 __get_regs(vcpu, &vcpu->run->s.regs.regs); 10215 10216 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_SREGS) 10217 __get_sregs(vcpu, &vcpu->run->s.regs.sregs); 10218 10219 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_EVENTS) 10220 kvm_vcpu_ioctl_x86_get_vcpu_events( 10221 vcpu, &vcpu->run->s.regs.events); 10222 } 10223 10224 static int sync_regs(struct kvm_vcpu *vcpu) 10225 { 10226 if (vcpu->run->kvm_dirty_regs & ~KVM_SYNC_X86_VALID_FIELDS) 10227 return -EINVAL; 10228 10229 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_REGS) { 10230 __set_regs(vcpu, &vcpu->run->s.regs.regs); 10231 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_REGS; 10232 } 10233 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_SREGS) { 10234 if (__set_sregs(vcpu, &vcpu->run->s.regs.sregs)) 10235 return -EINVAL; 10236 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_SREGS; 10237 } 10238 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_EVENTS) { 10239 if (kvm_vcpu_ioctl_x86_set_vcpu_events( 10240 vcpu, &vcpu->run->s.regs.events)) 10241 return -EINVAL; 10242 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_EVENTS; 10243 } 10244 10245 return 0; 10246 } 10247 10248 static void fx_init(struct kvm_vcpu *vcpu) 10249 { 10250 if (!vcpu->arch.guest_fpu) 10251 return; 10252 10253 fpstate_init(&vcpu->arch.guest_fpu->state); 10254 if (boot_cpu_has(X86_FEATURE_XSAVES)) 10255 vcpu->arch.guest_fpu->state.xsave.header.xcomp_bv = 10256 host_xcr0 | XSTATE_COMPACTION_ENABLED; 10257 10258 /* 10259 * Ensure guest xcr0 is valid for loading 10260 */ 10261 vcpu->arch.xcr0 = XFEATURE_MASK_FP; 10262 10263 vcpu->arch.cr0 |= X86_CR0_ET; 10264 } 10265 10266 void kvm_free_guest_fpu(struct kvm_vcpu *vcpu) 10267 { 10268 if (vcpu->arch.guest_fpu) { 10269 kmem_cache_free(x86_fpu_cache, vcpu->arch.guest_fpu); 10270 vcpu->arch.guest_fpu = NULL; 10271 } 10272 } 10273 EXPORT_SYMBOL_GPL(kvm_free_guest_fpu); 10274 10275 int kvm_arch_vcpu_precreate(struct kvm *kvm, unsigned int id) 10276 { 10277 if (kvm_check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0) 10278 pr_warn_once("kvm: SMP vm created on host with unstable TSC; " 10279 "guest TSC will not be reliable\n"); 10280 10281 return 0; 10282 } 10283 10284 int kvm_arch_vcpu_create(struct kvm_vcpu *vcpu) 10285 { 10286 struct page *page; 10287 int r; 10288 10289 if (!irqchip_in_kernel(vcpu->kvm) || kvm_vcpu_is_reset_bsp(vcpu)) 10290 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; 10291 else 10292 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED; 10293 10294 kvm_set_tsc_khz(vcpu, max_tsc_khz); 10295 10296 r = kvm_mmu_create(vcpu); 10297 if (r < 0) 10298 return r; 10299 10300 if (irqchip_in_kernel(vcpu->kvm)) { 10301 r = kvm_create_lapic(vcpu, lapic_timer_advance_ns); 10302 if (r < 0) 10303 goto fail_mmu_destroy; 10304 if (kvm_apicv_activated(vcpu->kvm)) 10305 vcpu->arch.apicv_active = true; 10306 } else 10307 static_branch_inc(&kvm_has_noapic_vcpu); 10308 10309 r = -ENOMEM; 10310 10311 page = alloc_page(GFP_KERNEL_ACCOUNT | __GFP_ZERO); 10312 if (!page) 10313 goto fail_free_lapic; 10314 vcpu->arch.pio_data = page_address(page); 10315 10316 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4, 10317 GFP_KERNEL_ACCOUNT); 10318 if (!vcpu->arch.mce_banks) 10319 goto fail_free_pio_data; 10320 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS; 10321 10322 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, 10323 GFP_KERNEL_ACCOUNT)) 10324 goto fail_free_mce_banks; 10325 10326 if (!alloc_emulate_ctxt(vcpu)) 10327 goto free_wbinvd_dirty_mask; 10328 10329 vcpu->arch.user_fpu = kmem_cache_zalloc(x86_fpu_cache, 10330 GFP_KERNEL_ACCOUNT); 10331 if (!vcpu->arch.user_fpu) { 10332 pr_err("kvm: failed to allocate userspace's fpu\n"); 10333 goto free_emulate_ctxt; 10334 } 10335 10336 vcpu->arch.guest_fpu = kmem_cache_zalloc(x86_fpu_cache, 10337 GFP_KERNEL_ACCOUNT); 10338 if (!vcpu->arch.guest_fpu) { 10339 pr_err("kvm: failed to allocate vcpu's fpu\n"); 10340 goto free_user_fpu; 10341 } 10342 fx_init(vcpu); 10343 10344 vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu); 10345 vcpu->arch.reserved_gpa_bits = kvm_vcpu_reserved_gpa_bits_raw(vcpu); 10346 10347 vcpu->arch.pat = MSR_IA32_CR_PAT_DEFAULT; 10348 10349 kvm_async_pf_hash_reset(vcpu); 10350 kvm_pmu_init(vcpu); 10351 10352 vcpu->arch.pending_external_vector = -1; 10353 vcpu->arch.preempted_in_kernel = false; 10354 10355 r = static_call(kvm_x86_vcpu_create)(vcpu); 10356 if (r) 10357 goto free_guest_fpu; 10358 10359 vcpu->arch.arch_capabilities = kvm_get_arch_capabilities(); 10360 vcpu->arch.msr_platform_info = MSR_PLATFORM_INFO_CPUID_FAULT; 10361 kvm_vcpu_mtrr_init(vcpu); 10362 vcpu_load(vcpu); 10363 kvm_vcpu_reset(vcpu, false); 10364 kvm_init_mmu(vcpu, false); 10365 vcpu_put(vcpu); 10366 return 0; 10367 10368 free_guest_fpu: 10369 kvm_free_guest_fpu(vcpu); 10370 free_user_fpu: 10371 kmem_cache_free(x86_fpu_cache, vcpu->arch.user_fpu); 10372 free_emulate_ctxt: 10373 kmem_cache_free(x86_emulator_cache, vcpu->arch.emulate_ctxt); 10374 free_wbinvd_dirty_mask: 10375 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask); 10376 fail_free_mce_banks: 10377 kfree(vcpu->arch.mce_banks); 10378 fail_free_pio_data: 10379 free_page((unsigned long)vcpu->arch.pio_data); 10380 fail_free_lapic: 10381 kvm_free_lapic(vcpu); 10382 fail_mmu_destroy: 10383 kvm_mmu_destroy(vcpu); 10384 return r; 10385 } 10386 10387 void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu) 10388 { 10389 struct kvm *kvm = vcpu->kvm; 10390 10391 if (mutex_lock_killable(&vcpu->mutex)) 10392 return; 10393 vcpu_load(vcpu); 10394 kvm_synchronize_tsc(vcpu, 0); 10395 vcpu_put(vcpu); 10396 10397 /* poll control enabled by default */ 10398 vcpu->arch.msr_kvm_poll_control = 1; 10399 10400 mutex_unlock(&vcpu->mutex); 10401 10402 if (kvmclock_periodic_sync && vcpu->vcpu_idx == 0) 10403 schedule_delayed_work(&kvm->arch.kvmclock_sync_work, 10404 KVMCLOCK_SYNC_PERIOD); 10405 } 10406 10407 void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu) 10408 { 10409 struct gfn_to_pfn_cache *cache = &vcpu->arch.st.cache; 10410 int idx; 10411 10412 kvm_release_pfn(cache->pfn, cache->dirty, cache); 10413 10414 kvmclock_reset(vcpu); 10415 10416 static_call(kvm_x86_vcpu_free)(vcpu); 10417 10418 kmem_cache_free(x86_emulator_cache, vcpu->arch.emulate_ctxt); 10419 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask); 10420 kmem_cache_free(x86_fpu_cache, vcpu->arch.user_fpu); 10421 kvm_free_guest_fpu(vcpu); 10422 10423 kvm_hv_vcpu_uninit(vcpu); 10424 kvm_pmu_destroy(vcpu); 10425 kfree(vcpu->arch.mce_banks); 10426 kvm_free_lapic(vcpu); 10427 idx = srcu_read_lock(&vcpu->kvm->srcu); 10428 kvm_mmu_destroy(vcpu); 10429 srcu_read_unlock(&vcpu->kvm->srcu, idx); 10430 free_page((unsigned long)vcpu->arch.pio_data); 10431 kvfree(vcpu->arch.cpuid_entries); 10432 if (!lapic_in_kernel(vcpu)) 10433 static_branch_dec(&kvm_has_noapic_vcpu); 10434 } 10435 10436 void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event) 10437 { 10438 kvm_lapic_reset(vcpu, init_event); 10439 10440 vcpu->arch.hflags = 0; 10441 10442 vcpu->arch.smi_pending = 0; 10443 vcpu->arch.smi_count = 0; 10444 atomic_set(&vcpu->arch.nmi_queued, 0); 10445 vcpu->arch.nmi_pending = 0; 10446 vcpu->arch.nmi_injected = false; 10447 kvm_clear_interrupt_queue(vcpu); 10448 kvm_clear_exception_queue(vcpu); 10449 10450 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db)); 10451 kvm_update_dr0123(vcpu); 10452 vcpu->arch.dr6 = DR6_ACTIVE_LOW; 10453 vcpu->arch.dr7 = DR7_FIXED_1; 10454 kvm_update_dr7(vcpu); 10455 10456 vcpu->arch.cr2 = 0; 10457 10458 kvm_make_request(KVM_REQ_EVENT, vcpu); 10459 vcpu->arch.apf.msr_en_val = 0; 10460 vcpu->arch.apf.msr_int_val = 0; 10461 vcpu->arch.st.msr_val = 0; 10462 10463 kvmclock_reset(vcpu); 10464 10465 kvm_clear_async_pf_completion_queue(vcpu); 10466 kvm_async_pf_hash_reset(vcpu); 10467 vcpu->arch.apf.halted = false; 10468 10469 if (vcpu->arch.guest_fpu && kvm_mpx_supported()) { 10470 void *mpx_state_buffer; 10471 10472 /* 10473 * To avoid have the INIT path from kvm_apic_has_events() that be 10474 * called with loaded FPU and does not let userspace fix the state. 10475 */ 10476 if (init_event) 10477 kvm_put_guest_fpu(vcpu); 10478 mpx_state_buffer = get_xsave_addr(&vcpu->arch.guest_fpu->state.xsave, 10479 XFEATURE_BNDREGS); 10480 if (mpx_state_buffer) 10481 memset(mpx_state_buffer, 0, sizeof(struct mpx_bndreg_state)); 10482 mpx_state_buffer = get_xsave_addr(&vcpu->arch.guest_fpu->state.xsave, 10483 XFEATURE_BNDCSR); 10484 if (mpx_state_buffer) 10485 memset(mpx_state_buffer, 0, sizeof(struct mpx_bndcsr)); 10486 if (init_event) 10487 kvm_load_guest_fpu(vcpu); 10488 } 10489 10490 if (!init_event) { 10491 kvm_pmu_reset(vcpu); 10492 vcpu->arch.smbase = 0x30000; 10493 10494 vcpu->arch.msr_misc_features_enables = 0; 10495 10496 vcpu->arch.xcr0 = XFEATURE_MASK_FP; 10497 } 10498 10499 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs)); 10500 vcpu->arch.regs_avail = ~0; 10501 vcpu->arch.regs_dirty = ~0; 10502 10503 vcpu->arch.ia32_xss = 0; 10504 10505 static_call(kvm_x86_vcpu_reset)(vcpu, init_event); 10506 } 10507 10508 void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector) 10509 { 10510 struct kvm_segment cs; 10511 10512 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS); 10513 cs.selector = vector << 8; 10514 cs.base = vector << 12; 10515 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS); 10516 kvm_rip_write(vcpu, 0); 10517 } 10518 EXPORT_SYMBOL_GPL(kvm_vcpu_deliver_sipi_vector); 10519 10520 int kvm_arch_hardware_enable(void) 10521 { 10522 struct kvm *kvm; 10523 struct kvm_vcpu *vcpu; 10524 int i; 10525 int ret; 10526 u64 local_tsc; 10527 u64 max_tsc = 0; 10528 bool stable, backwards_tsc = false; 10529 10530 kvm_user_return_msr_cpu_online(); 10531 ret = static_call(kvm_x86_hardware_enable)(); 10532 if (ret != 0) 10533 return ret; 10534 10535 local_tsc = rdtsc(); 10536 stable = !kvm_check_tsc_unstable(); 10537 list_for_each_entry(kvm, &vm_list, vm_list) { 10538 kvm_for_each_vcpu(i, vcpu, kvm) { 10539 if (!stable && vcpu->cpu == smp_processor_id()) 10540 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 10541 if (stable && vcpu->arch.last_host_tsc > local_tsc) { 10542 backwards_tsc = true; 10543 if (vcpu->arch.last_host_tsc > max_tsc) 10544 max_tsc = vcpu->arch.last_host_tsc; 10545 } 10546 } 10547 } 10548 10549 /* 10550 * Sometimes, even reliable TSCs go backwards. This happens on 10551 * platforms that reset TSC during suspend or hibernate actions, but 10552 * maintain synchronization. We must compensate. Fortunately, we can 10553 * detect that condition here, which happens early in CPU bringup, 10554 * before any KVM threads can be running. Unfortunately, we can't 10555 * bring the TSCs fully up to date with real time, as we aren't yet far 10556 * enough into CPU bringup that we know how much real time has actually 10557 * elapsed; our helper function, ktime_get_boottime_ns() will be using boot 10558 * variables that haven't been updated yet. 10559 * 10560 * So we simply find the maximum observed TSC above, then record the 10561 * adjustment to TSC in each VCPU. When the VCPU later gets loaded, 10562 * the adjustment will be applied. Note that we accumulate 10563 * adjustments, in case multiple suspend cycles happen before some VCPU 10564 * gets a chance to run again. In the event that no KVM threads get a 10565 * chance to run, we will miss the entire elapsed period, as we'll have 10566 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may 10567 * loose cycle time. This isn't too big a deal, since the loss will be 10568 * uniform across all VCPUs (not to mention the scenario is extremely 10569 * unlikely). It is possible that a second hibernate recovery happens 10570 * much faster than a first, causing the observed TSC here to be 10571 * smaller; this would require additional padding adjustment, which is 10572 * why we set last_host_tsc to the local tsc observed here. 10573 * 10574 * N.B. - this code below runs only on platforms with reliable TSC, 10575 * as that is the only way backwards_tsc is set above. Also note 10576 * that this runs for ALL vcpus, which is not a bug; all VCPUs should 10577 * have the same delta_cyc adjustment applied if backwards_tsc 10578 * is detected. Note further, this adjustment is only done once, 10579 * as we reset last_host_tsc on all VCPUs to stop this from being 10580 * called multiple times (one for each physical CPU bringup). 10581 * 10582 * Platforms with unreliable TSCs don't have to deal with this, they 10583 * will be compensated by the logic in vcpu_load, which sets the TSC to 10584 * catchup mode. This will catchup all VCPUs to real time, but cannot 10585 * guarantee that they stay in perfect synchronization. 10586 */ 10587 if (backwards_tsc) { 10588 u64 delta_cyc = max_tsc - local_tsc; 10589 list_for_each_entry(kvm, &vm_list, vm_list) { 10590 kvm->arch.backwards_tsc_observed = true; 10591 kvm_for_each_vcpu(i, vcpu, kvm) { 10592 vcpu->arch.tsc_offset_adjustment += delta_cyc; 10593 vcpu->arch.last_host_tsc = local_tsc; 10594 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu); 10595 } 10596 10597 /* 10598 * We have to disable TSC offset matching.. if you were 10599 * booting a VM while issuing an S4 host suspend.... 10600 * you may have some problem. Solving this issue is 10601 * left as an exercise to the reader. 10602 */ 10603 kvm->arch.last_tsc_nsec = 0; 10604 kvm->arch.last_tsc_write = 0; 10605 } 10606 10607 } 10608 return 0; 10609 } 10610 10611 void kvm_arch_hardware_disable(void) 10612 { 10613 static_call(kvm_x86_hardware_disable)(); 10614 drop_user_return_notifiers(); 10615 } 10616 10617 int kvm_arch_hardware_setup(void *opaque) 10618 { 10619 struct kvm_x86_init_ops *ops = opaque; 10620 int r; 10621 10622 rdmsrl_safe(MSR_EFER, &host_efer); 10623 10624 if (boot_cpu_has(X86_FEATURE_XSAVES)) 10625 rdmsrl(MSR_IA32_XSS, host_xss); 10626 10627 r = ops->hardware_setup(); 10628 if (r != 0) 10629 return r; 10630 10631 memcpy(&kvm_x86_ops, ops->runtime_ops, sizeof(kvm_x86_ops)); 10632 kvm_ops_static_call_update(); 10633 10634 if (!kvm_cpu_cap_has(X86_FEATURE_XSAVES)) 10635 supported_xss = 0; 10636 10637 #define __kvm_cpu_cap_has(UNUSED_, f) kvm_cpu_cap_has(f) 10638 cr4_reserved_bits = __cr4_reserved_bits(__kvm_cpu_cap_has, UNUSED_); 10639 #undef __kvm_cpu_cap_has 10640 10641 if (kvm_has_tsc_control) { 10642 /* 10643 * Make sure the user can only configure tsc_khz values that 10644 * fit into a signed integer. 10645 * A min value is not calculated because it will always 10646 * be 1 on all machines. 10647 */ 10648 u64 max = min(0x7fffffffULL, 10649 __scale_tsc(kvm_max_tsc_scaling_ratio, tsc_khz)); 10650 kvm_max_guest_tsc_khz = max; 10651 10652 kvm_default_tsc_scaling_ratio = 1ULL << kvm_tsc_scaling_ratio_frac_bits; 10653 } 10654 10655 kvm_init_msr_list(); 10656 return 0; 10657 } 10658 10659 void kvm_arch_hardware_unsetup(void) 10660 { 10661 static_call(kvm_x86_hardware_unsetup)(); 10662 } 10663 10664 int kvm_arch_check_processor_compat(void *opaque) 10665 { 10666 struct cpuinfo_x86 *c = &cpu_data(smp_processor_id()); 10667 struct kvm_x86_init_ops *ops = opaque; 10668 10669 WARN_ON(!irqs_disabled()); 10670 10671 if (__cr4_reserved_bits(cpu_has, c) != 10672 __cr4_reserved_bits(cpu_has, &boot_cpu_data)) 10673 return -EIO; 10674 10675 return ops->check_processor_compatibility(); 10676 } 10677 10678 bool kvm_vcpu_is_reset_bsp(struct kvm_vcpu *vcpu) 10679 { 10680 return vcpu->kvm->arch.bsp_vcpu_id == vcpu->vcpu_id; 10681 } 10682 EXPORT_SYMBOL_GPL(kvm_vcpu_is_reset_bsp); 10683 10684 bool kvm_vcpu_is_bsp(struct kvm_vcpu *vcpu) 10685 { 10686 return (vcpu->arch.apic_base & MSR_IA32_APICBASE_BSP) != 0; 10687 } 10688 10689 __read_mostly DEFINE_STATIC_KEY_FALSE(kvm_has_noapic_vcpu); 10690 EXPORT_SYMBOL_GPL(kvm_has_noapic_vcpu); 10691 10692 void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu) 10693 { 10694 struct kvm_pmu *pmu = vcpu_to_pmu(vcpu); 10695 10696 vcpu->arch.l1tf_flush_l1d = true; 10697 if (pmu->version && unlikely(pmu->event_count)) { 10698 pmu->need_cleanup = true; 10699 kvm_make_request(KVM_REQ_PMU, vcpu); 10700 } 10701 static_call(kvm_x86_sched_in)(vcpu, cpu); 10702 } 10703 10704 void kvm_arch_free_vm(struct kvm *kvm) 10705 { 10706 kfree(to_kvm_hv(kvm)->hv_pa_pg); 10707 vfree(kvm); 10708 } 10709 10710 10711 int kvm_arch_init_vm(struct kvm *kvm, unsigned long type) 10712 { 10713 if (type) 10714 return -EINVAL; 10715 10716 INIT_HLIST_HEAD(&kvm->arch.mask_notifier_list); 10717 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages); 10718 INIT_LIST_HEAD(&kvm->arch.zapped_obsolete_pages); 10719 INIT_LIST_HEAD(&kvm->arch.lpage_disallowed_mmu_pages); 10720 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head); 10721 atomic_set(&kvm->arch.noncoherent_dma_count, 0); 10722 10723 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */ 10724 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap); 10725 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */ 10726 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID, 10727 &kvm->arch.irq_sources_bitmap); 10728 10729 raw_spin_lock_init(&kvm->arch.tsc_write_lock); 10730 mutex_init(&kvm->arch.apic_map_lock); 10731 spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock); 10732 10733 kvm->arch.kvmclock_offset = -get_kvmclock_base_ns(); 10734 pvclock_update_vm_gtod_copy(kvm); 10735 10736 kvm->arch.guest_can_read_msr_platform_info = true; 10737 10738 INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn); 10739 INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn); 10740 10741 kvm_hv_init_vm(kvm); 10742 kvm_page_track_init(kvm); 10743 kvm_mmu_init_vm(kvm); 10744 10745 return static_call(kvm_x86_vm_init)(kvm); 10746 } 10747 10748 int kvm_arch_post_init_vm(struct kvm *kvm) 10749 { 10750 return kvm_mmu_post_init_vm(kvm); 10751 } 10752 10753 static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu) 10754 { 10755 vcpu_load(vcpu); 10756 kvm_mmu_unload(vcpu); 10757 vcpu_put(vcpu); 10758 } 10759 10760 static void kvm_free_vcpus(struct kvm *kvm) 10761 { 10762 unsigned int i; 10763 struct kvm_vcpu *vcpu; 10764 10765 /* 10766 * Unpin any mmu pages first. 10767 */ 10768 kvm_for_each_vcpu(i, vcpu, kvm) { 10769 kvm_clear_async_pf_completion_queue(vcpu); 10770 kvm_unload_vcpu_mmu(vcpu); 10771 } 10772 kvm_for_each_vcpu(i, vcpu, kvm) 10773 kvm_vcpu_destroy(vcpu); 10774 10775 mutex_lock(&kvm->lock); 10776 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++) 10777 kvm->vcpus[i] = NULL; 10778 10779 atomic_set(&kvm->online_vcpus, 0); 10780 mutex_unlock(&kvm->lock); 10781 } 10782 10783 void kvm_arch_sync_events(struct kvm *kvm) 10784 { 10785 cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work); 10786 cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work); 10787 kvm_free_pit(kvm); 10788 } 10789 10790 #define ERR_PTR_USR(e) ((void __user *)ERR_PTR(e)) 10791 10792 /** 10793 * __x86_set_memory_region: Setup KVM internal memory slot 10794 * 10795 * @kvm: the kvm pointer to the VM. 10796 * @id: the slot ID to setup. 10797 * @gpa: the GPA to install the slot (unused when @size == 0). 10798 * @size: the size of the slot. Set to zero to uninstall a slot. 10799 * 10800 * This function helps to setup a KVM internal memory slot. Specify 10801 * @size > 0 to install a new slot, while @size == 0 to uninstall a 10802 * slot. The return code can be one of the following: 10803 * 10804 * HVA: on success (uninstall will return a bogus HVA) 10805 * -errno: on error 10806 * 10807 * The caller should always use IS_ERR() to check the return value 10808 * before use. Note, the KVM internal memory slots are guaranteed to 10809 * remain valid and unchanged until the VM is destroyed, i.e., the 10810 * GPA->HVA translation will not change. However, the HVA is a user 10811 * address, i.e. its accessibility is not guaranteed, and must be 10812 * accessed via __copy_{to,from}_user(). 10813 */ 10814 void __user * __x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, 10815 u32 size) 10816 { 10817 int i, r; 10818 unsigned long hva, old_npages; 10819 struct kvm_memslots *slots = kvm_memslots(kvm); 10820 struct kvm_memory_slot *slot; 10821 10822 /* Called with kvm->slots_lock held. */ 10823 if (WARN_ON(id >= KVM_MEM_SLOTS_NUM)) 10824 return ERR_PTR_USR(-EINVAL); 10825 10826 slot = id_to_memslot(slots, id); 10827 if (size) { 10828 if (slot && slot->npages) 10829 return ERR_PTR_USR(-EEXIST); 10830 10831 /* 10832 * MAP_SHARED to prevent internal slot pages from being moved 10833 * by fork()/COW. 10834 */ 10835 hva = vm_mmap(NULL, 0, size, PROT_READ | PROT_WRITE, 10836 MAP_SHARED | MAP_ANONYMOUS, 0); 10837 if (IS_ERR((void *)hva)) 10838 return (void __user *)hva; 10839 } else { 10840 if (!slot || !slot->npages) 10841 return NULL; 10842 10843 old_npages = slot->npages; 10844 hva = slot->userspace_addr; 10845 } 10846 10847 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) { 10848 struct kvm_userspace_memory_region m; 10849 10850 m.slot = id | (i << 16); 10851 m.flags = 0; 10852 m.guest_phys_addr = gpa; 10853 m.userspace_addr = hva; 10854 m.memory_size = size; 10855 r = __kvm_set_memory_region(kvm, &m); 10856 if (r < 0) 10857 return ERR_PTR_USR(r); 10858 } 10859 10860 if (!size) 10861 vm_munmap(hva, old_npages * PAGE_SIZE); 10862 10863 return (void __user *)hva; 10864 } 10865 EXPORT_SYMBOL_GPL(__x86_set_memory_region); 10866 10867 void kvm_arch_pre_destroy_vm(struct kvm *kvm) 10868 { 10869 kvm_mmu_pre_destroy_vm(kvm); 10870 } 10871 10872 void kvm_arch_destroy_vm(struct kvm *kvm) 10873 { 10874 if (current->mm == kvm->mm) { 10875 /* 10876 * Free memory regions allocated on behalf of userspace, 10877 * unless the the memory map has changed due to process exit 10878 * or fd copying. 10879 */ 10880 mutex_lock(&kvm->slots_lock); 10881 __x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT, 10882 0, 0); 10883 __x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT, 10884 0, 0); 10885 __x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, 0, 0); 10886 mutex_unlock(&kvm->slots_lock); 10887 } 10888 static_call_cond(kvm_x86_vm_destroy)(kvm); 10889 kvm_free_msr_filter(srcu_dereference_check(kvm->arch.msr_filter, &kvm->srcu, 1)); 10890 kvm_pic_destroy(kvm); 10891 kvm_ioapic_destroy(kvm); 10892 kvm_free_vcpus(kvm); 10893 kvfree(rcu_dereference_check(kvm->arch.apic_map, 1)); 10894 kfree(srcu_dereference_check(kvm->arch.pmu_event_filter, &kvm->srcu, 1)); 10895 kvm_mmu_uninit_vm(kvm); 10896 kvm_page_track_cleanup(kvm); 10897 kvm_xen_destroy_vm(kvm); 10898 kvm_hv_destroy_vm(kvm); 10899 } 10900 10901 void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *slot) 10902 { 10903 int i; 10904 10905 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) { 10906 kvfree(slot->arch.rmap[i]); 10907 slot->arch.rmap[i] = NULL; 10908 10909 if (i == 0) 10910 continue; 10911 10912 kvfree(slot->arch.lpage_info[i - 1]); 10913 slot->arch.lpage_info[i - 1] = NULL; 10914 } 10915 10916 kvm_page_track_free_memslot(slot); 10917 } 10918 10919 static int kvm_alloc_memslot_metadata(struct kvm_memory_slot *slot, 10920 unsigned long npages) 10921 { 10922 int i; 10923 10924 /* 10925 * Clear out the previous array pointers for the KVM_MR_MOVE case. The 10926 * old arrays will be freed by __kvm_set_memory_region() if installing 10927 * the new memslot is successful. 10928 */ 10929 memset(&slot->arch, 0, sizeof(slot->arch)); 10930 10931 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) { 10932 struct kvm_lpage_info *linfo; 10933 unsigned long ugfn; 10934 int lpages; 10935 int level = i + 1; 10936 10937 lpages = gfn_to_index(slot->base_gfn + npages - 1, 10938 slot->base_gfn, level) + 1; 10939 10940 slot->arch.rmap[i] = 10941 kvcalloc(lpages, sizeof(*slot->arch.rmap[i]), 10942 GFP_KERNEL_ACCOUNT); 10943 if (!slot->arch.rmap[i]) 10944 goto out_free; 10945 if (i == 0) 10946 continue; 10947 10948 linfo = kvcalloc(lpages, sizeof(*linfo), GFP_KERNEL_ACCOUNT); 10949 if (!linfo) 10950 goto out_free; 10951 10952 slot->arch.lpage_info[i - 1] = linfo; 10953 10954 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1)) 10955 linfo[0].disallow_lpage = 1; 10956 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1)) 10957 linfo[lpages - 1].disallow_lpage = 1; 10958 ugfn = slot->userspace_addr >> PAGE_SHIFT; 10959 /* 10960 * If the gfn and userspace address are not aligned wrt each 10961 * other, disable large page support for this slot. 10962 */ 10963 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1)) { 10964 unsigned long j; 10965 10966 for (j = 0; j < lpages; ++j) 10967 linfo[j].disallow_lpage = 1; 10968 } 10969 } 10970 10971 if (kvm_page_track_create_memslot(slot, npages)) 10972 goto out_free; 10973 10974 return 0; 10975 10976 out_free: 10977 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) { 10978 kvfree(slot->arch.rmap[i]); 10979 slot->arch.rmap[i] = NULL; 10980 if (i == 0) 10981 continue; 10982 10983 kvfree(slot->arch.lpage_info[i - 1]); 10984 slot->arch.lpage_info[i - 1] = NULL; 10985 } 10986 return -ENOMEM; 10987 } 10988 10989 void kvm_arch_memslots_updated(struct kvm *kvm, u64 gen) 10990 { 10991 struct kvm_vcpu *vcpu; 10992 int i; 10993 10994 /* 10995 * memslots->generation has been incremented. 10996 * mmio generation may have reached its maximum value. 10997 */ 10998 kvm_mmu_invalidate_mmio_sptes(kvm, gen); 10999 11000 /* Force re-initialization of steal_time cache */ 11001 kvm_for_each_vcpu(i, vcpu, kvm) 11002 kvm_vcpu_kick(vcpu); 11003 } 11004 11005 int kvm_arch_prepare_memory_region(struct kvm *kvm, 11006 struct kvm_memory_slot *memslot, 11007 const struct kvm_userspace_memory_region *mem, 11008 enum kvm_mr_change change) 11009 { 11010 if (change == KVM_MR_CREATE || change == KVM_MR_MOVE) 11011 return kvm_alloc_memslot_metadata(memslot, 11012 mem->memory_size >> PAGE_SHIFT); 11013 return 0; 11014 } 11015 11016 11017 static void kvm_mmu_update_cpu_dirty_logging(struct kvm *kvm, bool enable) 11018 { 11019 struct kvm_arch *ka = &kvm->arch; 11020 11021 if (!kvm_x86_ops.cpu_dirty_log_size) 11022 return; 11023 11024 if ((enable && ++ka->cpu_dirty_logging_count == 1) || 11025 (!enable && --ka->cpu_dirty_logging_count == 0)) 11026 kvm_make_all_cpus_request(kvm, KVM_REQ_UPDATE_CPU_DIRTY_LOGGING); 11027 11028 WARN_ON_ONCE(ka->cpu_dirty_logging_count < 0); 11029 } 11030 11031 static void kvm_mmu_slot_apply_flags(struct kvm *kvm, 11032 struct kvm_memory_slot *old, 11033 struct kvm_memory_slot *new, 11034 enum kvm_mr_change change) 11035 { 11036 bool log_dirty_pages = new->flags & KVM_MEM_LOG_DIRTY_PAGES; 11037 11038 /* 11039 * Update CPU dirty logging if dirty logging is being toggled. This 11040 * applies to all operations. 11041 */ 11042 if ((old->flags ^ new->flags) & KVM_MEM_LOG_DIRTY_PAGES) 11043 kvm_mmu_update_cpu_dirty_logging(kvm, log_dirty_pages); 11044 11045 /* 11046 * Nothing more to do for RO slots (which can't be dirtied and can't be 11047 * made writable) or CREATE/MOVE/DELETE of a slot. 11048 * 11049 * For a memslot with dirty logging disabled: 11050 * CREATE: No dirty mappings will already exist. 11051 * MOVE/DELETE: The old mappings will already have been cleaned up by 11052 * kvm_arch_flush_shadow_memslot() 11053 * 11054 * For a memslot with dirty logging enabled: 11055 * CREATE: No shadow pages exist, thus nothing to write-protect 11056 * and no dirty bits to clear. 11057 * MOVE/DELETE: The old mappings will already have been cleaned up by 11058 * kvm_arch_flush_shadow_memslot(). 11059 */ 11060 if ((change != KVM_MR_FLAGS_ONLY) || (new->flags & KVM_MEM_READONLY)) 11061 return; 11062 11063 /* 11064 * READONLY and non-flags changes were filtered out above, and the only 11065 * other flag is LOG_DIRTY_PAGES, i.e. something is wrong if dirty 11066 * logging isn't being toggled on or off. 11067 */ 11068 if (WARN_ON_ONCE(!((old->flags ^ new->flags) & KVM_MEM_LOG_DIRTY_PAGES))) 11069 return; 11070 11071 if (!log_dirty_pages) { 11072 /* 11073 * Dirty logging tracks sptes in 4k granularity, meaning that 11074 * large sptes have to be split. If live migration succeeds, 11075 * the guest in the source machine will be destroyed and large 11076 * sptes will be created in the destination. However, if the 11077 * guest continues to run in the source machine (for example if 11078 * live migration fails), small sptes will remain around and 11079 * cause bad performance. 11080 * 11081 * Scan sptes if dirty logging has been stopped, dropping those 11082 * which can be collapsed into a single large-page spte. Later 11083 * page faults will create the large-page sptes. 11084 */ 11085 kvm_mmu_zap_collapsible_sptes(kvm, new); 11086 } else { 11087 /* By default, write-protect everything to log writes. */ 11088 int level = PG_LEVEL_4K; 11089 11090 if (kvm_x86_ops.cpu_dirty_log_size) { 11091 /* 11092 * Clear all dirty bits, unless pages are treated as 11093 * dirty from the get-go. 11094 */ 11095 if (!kvm_dirty_log_manual_protect_and_init_set(kvm)) 11096 kvm_mmu_slot_leaf_clear_dirty(kvm, new); 11097 11098 /* 11099 * Write-protect large pages on write so that dirty 11100 * logging happens at 4k granularity. No need to 11101 * write-protect small SPTEs since write accesses are 11102 * logged by the CPU via dirty bits. 11103 */ 11104 level = PG_LEVEL_2M; 11105 } else if (kvm_dirty_log_manual_protect_and_init_set(kvm)) { 11106 /* 11107 * If we're with initial-all-set, we don't need 11108 * to write protect any small page because 11109 * they're reported as dirty already. However 11110 * we still need to write-protect huge pages 11111 * so that the page split can happen lazily on 11112 * the first write to the huge page. 11113 */ 11114 level = PG_LEVEL_2M; 11115 } 11116 kvm_mmu_slot_remove_write_access(kvm, new, level); 11117 } 11118 } 11119 11120 void kvm_arch_commit_memory_region(struct kvm *kvm, 11121 const struct kvm_userspace_memory_region *mem, 11122 struct kvm_memory_slot *old, 11123 const struct kvm_memory_slot *new, 11124 enum kvm_mr_change change) 11125 { 11126 if (!kvm->arch.n_requested_mmu_pages) 11127 kvm_mmu_change_mmu_pages(kvm, 11128 kvm_mmu_calculate_default_mmu_pages(kvm)); 11129 11130 /* 11131 * FIXME: const-ify all uses of struct kvm_memory_slot. 11132 */ 11133 kvm_mmu_slot_apply_flags(kvm, old, (struct kvm_memory_slot *) new, change); 11134 11135 /* Free the arrays associated with the old memslot. */ 11136 if (change == KVM_MR_MOVE) 11137 kvm_arch_free_memslot(kvm, old); 11138 } 11139 11140 void kvm_arch_flush_shadow_all(struct kvm *kvm) 11141 { 11142 kvm_mmu_zap_all(kvm); 11143 } 11144 11145 void kvm_arch_flush_shadow_memslot(struct kvm *kvm, 11146 struct kvm_memory_slot *slot) 11147 { 11148 kvm_page_track_flush_slot(kvm, slot); 11149 } 11150 11151 static inline bool kvm_guest_apic_has_interrupt(struct kvm_vcpu *vcpu) 11152 { 11153 return (is_guest_mode(vcpu) && 11154 kvm_x86_ops.guest_apic_has_interrupt && 11155 static_call(kvm_x86_guest_apic_has_interrupt)(vcpu)); 11156 } 11157 11158 static inline bool kvm_vcpu_has_events(struct kvm_vcpu *vcpu) 11159 { 11160 if (!list_empty_careful(&vcpu->async_pf.done)) 11161 return true; 11162 11163 if (kvm_apic_has_events(vcpu)) 11164 return true; 11165 11166 if (vcpu->arch.pv.pv_unhalted) 11167 return true; 11168 11169 if (vcpu->arch.exception.pending) 11170 return true; 11171 11172 if (kvm_test_request(KVM_REQ_NMI, vcpu) || 11173 (vcpu->arch.nmi_pending && 11174 static_call(kvm_x86_nmi_allowed)(vcpu, false))) 11175 return true; 11176 11177 if (kvm_test_request(KVM_REQ_SMI, vcpu) || 11178 (vcpu->arch.smi_pending && 11179 static_call(kvm_x86_smi_allowed)(vcpu, false))) 11180 return true; 11181 11182 if (kvm_arch_interrupt_allowed(vcpu) && 11183 (kvm_cpu_has_interrupt(vcpu) || 11184 kvm_guest_apic_has_interrupt(vcpu))) 11185 return true; 11186 11187 if (kvm_hv_has_stimer_pending(vcpu)) 11188 return true; 11189 11190 if (is_guest_mode(vcpu) && 11191 kvm_x86_ops.nested_ops->hv_timer_pending && 11192 kvm_x86_ops.nested_ops->hv_timer_pending(vcpu)) 11193 return true; 11194 11195 return false; 11196 } 11197 11198 int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu) 11199 { 11200 return kvm_vcpu_running(vcpu) || kvm_vcpu_has_events(vcpu); 11201 } 11202 11203 bool kvm_arch_dy_has_pending_interrupt(struct kvm_vcpu *vcpu) 11204 { 11205 if (vcpu->arch.apicv_active && static_call(kvm_x86_dy_apicv_has_pending_interrupt)(vcpu)) 11206 return true; 11207 11208 return false; 11209 } 11210 11211 bool kvm_arch_dy_runnable(struct kvm_vcpu *vcpu) 11212 { 11213 if (READ_ONCE(vcpu->arch.pv.pv_unhalted)) 11214 return true; 11215 11216 if (kvm_test_request(KVM_REQ_NMI, vcpu) || 11217 kvm_test_request(KVM_REQ_SMI, vcpu) || 11218 kvm_test_request(KVM_REQ_EVENT, vcpu)) 11219 return true; 11220 11221 return kvm_arch_dy_has_pending_interrupt(vcpu); 11222 } 11223 11224 bool kvm_arch_vcpu_in_kernel(struct kvm_vcpu *vcpu) 11225 { 11226 if (vcpu->arch.guest_state_protected) 11227 return true; 11228 11229 return vcpu->arch.preempted_in_kernel; 11230 } 11231 11232 int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu) 11233 { 11234 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE; 11235 } 11236 11237 int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu) 11238 { 11239 return static_call(kvm_x86_interrupt_allowed)(vcpu, false); 11240 } 11241 11242 unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu) 11243 { 11244 /* Can't read the RIP when guest state is protected, just return 0 */ 11245 if (vcpu->arch.guest_state_protected) 11246 return 0; 11247 11248 if (is_64_bit_mode(vcpu)) 11249 return kvm_rip_read(vcpu); 11250 return (u32)(get_segment_base(vcpu, VCPU_SREG_CS) + 11251 kvm_rip_read(vcpu)); 11252 } 11253 EXPORT_SYMBOL_GPL(kvm_get_linear_rip); 11254 11255 bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip) 11256 { 11257 return kvm_get_linear_rip(vcpu) == linear_rip; 11258 } 11259 EXPORT_SYMBOL_GPL(kvm_is_linear_rip); 11260 11261 unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu) 11262 { 11263 unsigned long rflags; 11264 11265 rflags = static_call(kvm_x86_get_rflags)(vcpu); 11266 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) 11267 rflags &= ~X86_EFLAGS_TF; 11268 return rflags; 11269 } 11270 EXPORT_SYMBOL_GPL(kvm_get_rflags); 11271 11272 static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags) 11273 { 11274 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP && 11275 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip)) 11276 rflags |= X86_EFLAGS_TF; 11277 static_call(kvm_x86_set_rflags)(vcpu, rflags); 11278 } 11279 11280 void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags) 11281 { 11282 __kvm_set_rflags(vcpu, rflags); 11283 kvm_make_request(KVM_REQ_EVENT, vcpu); 11284 } 11285 EXPORT_SYMBOL_GPL(kvm_set_rflags); 11286 11287 void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work) 11288 { 11289 int r; 11290 11291 if ((vcpu->arch.mmu->direct_map != work->arch.direct_map) || 11292 work->wakeup_all) 11293 return; 11294 11295 r = kvm_mmu_reload(vcpu); 11296 if (unlikely(r)) 11297 return; 11298 11299 if (!vcpu->arch.mmu->direct_map && 11300 work->arch.cr3 != vcpu->arch.mmu->get_guest_pgd(vcpu)) 11301 return; 11302 11303 kvm_mmu_do_page_fault(vcpu, work->cr2_or_gpa, 0, true); 11304 } 11305 11306 static inline u32 kvm_async_pf_hash_fn(gfn_t gfn) 11307 { 11308 BUILD_BUG_ON(!is_power_of_2(ASYNC_PF_PER_VCPU)); 11309 11310 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU)); 11311 } 11312 11313 static inline u32 kvm_async_pf_next_probe(u32 key) 11314 { 11315 return (key + 1) & (ASYNC_PF_PER_VCPU - 1); 11316 } 11317 11318 static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn) 11319 { 11320 u32 key = kvm_async_pf_hash_fn(gfn); 11321 11322 while (vcpu->arch.apf.gfns[key] != ~0) 11323 key = kvm_async_pf_next_probe(key); 11324 11325 vcpu->arch.apf.gfns[key] = gfn; 11326 } 11327 11328 static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn) 11329 { 11330 int i; 11331 u32 key = kvm_async_pf_hash_fn(gfn); 11332 11333 for (i = 0; i < ASYNC_PF_PER_VCPU && 11334 (vcpu->arch.apf.gfns[key] != gfn && 11335 vcpu->arch.apf.gfns[key] != ~0); i++) 11336 key = kvm_async_pf_next_probe(key); 11337 11338 return key; 11339 } 11340 11341 bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn) 11342 { 11343 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn; 11344 } 11345 11346 static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn) 11347 { 11348 u32 i, j, k; 11349 11350 i = j = kvm_async_pf_gfn_slot(vcpu, gfn); 11351 11352 if (WARN_ON_ONCE(vcpu->arch.apf.gfns[i] != gfn)) 11353 return; 11354 11355 while (true) { 11356 vcpu->arch.apf.gfns[i] = ~0; 11357 do { 11358 j = kvm_async_pf_next_probe(j); 11359 if (vcpu->arch.apf.gfns[j] == ~0) 11360 return; 11361 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]); 11362 /* 11363 * k lies cyclically in ]i,j] 11364 * | i.k.j | 11365 * |....j i.k.| or |.k..j i...| 11366 */ 11367 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j)); 11368 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j]; 11369 i = j; 11370 } 11371 } 11372 11373 static inline int apf_put_user_notpresent(struct kvm_vcpu *vcpu) 11374 { 11375 u32 reason = KVM_PV_REASON_PAGE_NOT_PRESENT; 11376 11377 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &reason, 11378 sizeof(reason)); 11379 } 11380 11381 static inline int apf_put_user_ready(struct kvm_vcpu *vcpu, u32 token) 11382 { 11383 unsigned int offset = offsetof(struct kvm_vcpu_pv_apf_data, token); 11384 11385 return kvm_write_guest_offset_cached(vcpu->kvm, &vcpu->arch.apf.data, 11386 &token, offset, sizeof(token)); 11387 } 11388 11389 static inline bool apf_pageready_slot_free(struct kvm_vcpu *vcpu) 11390 { 11391 unsigned int offset = offsetof(struct kvm_vcpu_pv_apf_data, token); 11392 u32 val; 11393 11394 if (kvm_read_guest_offset_cached(vcpu->kvm, &vcpu->arch.apf.data, 11395 &val, offset, sizeof(val))) 11396 return false; 11397 11398 return !val; 11399 } 11400 11401 static bool kvm_can_deliver_async_pf(struct kvm_vcpu *vcpu) 11402 { 11403 if (!vcpu->arch.apf.delivery_as_pf_vmexit && is_guest_mode(vcpu)) 11404 return false; 11405 11406 if (!kvm_pv_async_pf_enabled(vcpu) || 11407 (vcpu->arch.apf.send_user_only && static_call(kvm_x86_get_cpl)(vcpu) == 0)) 11408 return false; 11409 11410 return true; 11411 } 11412 11413 bool kvm_can_do_async_pf(struct kvm_vcpu *vcpu) 11414 { 11415 if (unlikely(!lapic_in_kernel(vcpu) || 11416 kvm_event_needs_reinjection(vcpu) || 11417 vcpu->arch.exception.pending)) 11418 return false; 11419 11420 if (kvm_hlt_in_guest(vcpu->kvm) && !kvm_can_deliver_async_pf(vcpu)) 11421 return false; 11422 11423 /* 11424 * If interrupts are off we cannot even use an artificial 11425 * halt state. 11426 */ 11427 return kvm_arch_interrupt_allowed(vcpu); 11428 } 11429 11430 bool kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu, 11431 struct kvm_async_pf *work) 11432 { 11433 struct x86_exception fault; 11434 11435 trace_kvm_async_pf_not_present(work->arch.token, work->cr2_or_gpa); 11436 kvm_add_async_pf_gfn(vcpu, work->arch.gfn); 11437 11438 if (kvm_can_deliver_async_pf(vcpu) && 11439 !apf_put_user_notpresent(vcpu)) { 11440 fault.vector = PF_VECTOR; 11441 fault.error_code_valid = true; 11442 fault.error_code = 0; 11443 fault.nested_page_fault = false; 11444 fault.address = work->arch.token; 11445 fault.async_page_fault = true; 11446 kvm_inject_page_fault(vcpu, &fault); 11447 return true; 11448 } else { 11449 /* 11450 * It is not possible to deliver a paravirtualized asynchronous 11451 * page fault, but putting the guest in an artificial halt state 11452 * can be beneficial nevertheless: if an interrupt arrives, we 11453 * can deliver it timely and perhaps the guest will schedule 11454 * another process. When the instruction that triggered a page 11455 * fault is retried, hopefully the page will be ready in the host. 11456 */ 11457 kvm_make_request(KVM_REQ_APF_HALT, vcpu); 11458 return false; 11459 } 11460 } 11461 11462 void kvm_arch_async_page_present(struct kvm_vcpu *vcpu, 11463 struct kvm_async_pf *work) 11464 { 11465 struct kvm_lapic_irq irq = { 11466 .delivery_mode = APIC_DM_FIXED, 11467 .vector = vcpu->arch.apf.vec 11468 }; 11469 11470 if (work->wakeup_all) 11471 work->arch.token = ~0; /* broadcast wakeup */ 11472 else 11473 kvm_del_async_pf_gfn(vcpu, work->arch.gfn); 11474 trace_kvm_async_pf_ready(work->arch.token, work->cr2_or_gpa); 11475 11476 if ((work->wakeup_all || work->notpresent_injected) && 11477 kvm_pv_async_pf_enabled(vcpu) && 11478 !apf_put_user_ready(vcpu, work->arch.token)) { 11479 vcpu->arch.apf.pageready_pending = true; 11480 kvm_apic_set_irq(vcpu, &irq, NULL); 11481 } 11482 11483 vcpu->arch.apf.halted = false; 11484 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; 11485 } 11486 11487 void kvm_arch_async_page_present_queued(struct kvm_vcpu *vcpu) 11488 { 11489 kvm_make_request(KVM_REQ_APF_READY, vcpu); 11490 if (!vcpu->arch.apf.pageready_pending) 11491 kvm_vcpu_kick(vcpu); 11492 } 11493 11494 bool kvm_arch_can_dequeue_async_page_present(struct kvm_vcpu *vcpu) 11495 { 11496 if (!kvm_pv_async_pf_enabled(vcpu)) 11497 return true; 11498 else 11499 return kvm_lapic_enabled(vcpu) && apf_pageready_slot_free(vcpu); 11500 } 11501 11502 void kvm_arch_start_assignment(struct kvm *kvm) 11503 { 11504 if (atomic_inc_return(&kvm->arch.assigned_device_count) == 1) 11505 static_call_cond(kvm_x86_start_assignment)(kvm); 11506 } 11507 EXPORT_SYMBOL_GPL(kvm_arch_start_assignment); 11508 11509 void kvm_arch_end_assignment(struct kvm *kvm) 11510 { 11511 atomic_dec(&kvm->arch.assigned_device_count); 11512 } 11513 EXPORT_SYMBOL_GPL(kvm_arch_end_assignment); 11514 11515 bool kvm_arch_has_assigned_device(struct kvm *kvm) 11516 { 11517 return atomic_read(&kvm->arch.assigned_device_count); 11518 } 11519 EXPORT_SYMBOL_GPL(kvm_arch_has_assigned_device); 11520 11521 void kvm_arch_register_noncoherent_dma(struct kvm *kvm) 11522 { 11523 atomic_inc(&kvm->arch.noncoherent_dma_count); 11524 } 11525 EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma); 11526 11527 void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm) 11528 { 11529 atomic_dec(&kvm->arch.noncoherent_dma_count); 11530 } 11531 EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma); 11532 11533 bool kvm_arch_has_noncoherent_dma(struct kvm *kvm) 11534 { 11535 return atomic_read(&kvm->arch.noncoherent_dma_count); 11536 } 11537 EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma); 11538 11539 bool kvm_arch_has_irq_bypass(void) 11540 { 11541 return true; 11542 } 11543 11544 int kvm_arch_irq_bypass_add_producer(struct irq_bypass_consumer *cons, 11545 struct irq_bypass_producer *prod) 11546 { 11547 struct kvm_kernel_irqfd *irqfd = 11548 container_of(cons, struct kvm_kernel_irqfd, consumer); 11549 int ret; 11550 11551 irqfd->producer = prod; 11552 kvm_arch_start_assignment(irqfd->kvm); 11553 ret = static_call(kvm_x86_update_pi_irte)(irqfd->kvm, 11554 prod->irq, irqfd->gsi, 1); 11555 11556 if (ret) 11557 kvm_arch_end_assignment(irqfd->kvm); 11558 11559 return ret; 11560 } 11561 11562 void kvm_arch_irq_bypass_del_producer(struct irq_bypass_consumer *cons, 11563 struct irq_bypass_producer *prod) 11564 { 11565 int ret; 11566 struct kvm_kernel_irqfd *irqfd = 11567 container_of(cons, struct kvm_kernel_irqfd, consumer); 11568 11569 WARN_ON(irqfd->producer != prod); 11570 irqfd->producer = NULL; 11571 11572 /* 11573 * When producer of consumer is unregistered, we change back to 11574 * remapped mode, so we can re-use the current implementation 11575 * when the irq is masked/disabled or the consumer side (KVM 11576 * int this case doesn't want to receive the interrupts. 11577 */ 11578 ret = static_call(kvm_x86_update_pi_irte)(irqfd->kvm, prod->irq, irqfd->gsi, 0); 11579 if (ret) 11580 printk(KERN_INFO "irq bypass consumer (token %p) unregistration" 11581 " fails: %d\n", irqfd->consumer.token, ret); 11582 11583 kvm_arch_end_assignment(irqfd->kvm); 11584 } 11585 11586 int kvm_arch_update_irqfd_routing(struct kvm *kvm, unsigned int host_irq, 11587 uint32_t guest_irq, bool set) 11588 { 11589 return static_call(kvm_x86_update_pi_irte)(kvm, host_irq, guest_irq, set); 11590 } 11591 11592 bool kvm_vector_hashing_enabled(void) 11593 { 11594 return vector_hashing; 11595 } 11596 11597 bool kvm_arch_no_poll(struct kvm_vcpu *vcpu) 11598 { 11599 return (vcpu->arch.msr_kvm_poll_control & 1) == 0; 11600 } 11601 EXPORT_SYMBOL_GPL(kvm_arch_no_poll); 11602 11603 11604 int kvm_spec_ctrl_test_value(u64 value) 11605 { 11606 /* 11607 * test that setting IA32_SPEC_CTRL to given value 11608 * is allowed by the host processor 11609 */ 11610 11611 u64 saved_value; 11612 unsigned long flags; 11613 int ret = 0; 11614 11615 local_irq_save(flags); 11616 11617 if (rdmsrl_safe(MSR_IA32_SPEC_CTRL, &saved_value)) 11618 ret = 1; 11619 else if (wrmsrl_safe(MSR_IA32_SPEC_CTRL, value)) 11620 ret = 1; 11621 else 11622 wrmsrl(MSR_IA32_SPEC_CTRL, saved_value); 11623 11624 local_irq_restore(flags); 11625 11626 return ret; 11627 } 11628 EXPORT_SYMBOL_GPL(kvm_spec_ctrl_test_value); 11629 11630 void kvm_fixup_and_inject_pf_error(struct kvm_vcpu *vcpu, gva_t gva, u16 error_code) 11631 { 11632 struct x86_exception fault; 11633 u32 access = error_code & 11634 (PFERR_WRITE_MASK | PFERR_FETCH_MASK | PFERR_USER_MASK); 11635 11636 if (!(error_code & PFERR_PRESENT_MASK) || 11637 vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, &fault) != UNMAPPED_GVA) { 11638 /* 11639 * If vcpu->arch.walk_mmu->gva_to_gpa succeeded, the page 11640 * tables probably do not match the TLB. Just proceed 11641 * with the error code that the processor gave. 11642 */ 11643 fault.vector = PF_VECTOR; 11644 fault.error_code_valid = true; 11645 fault.error_code = error_code; 11646 fault.nested_page_fault = false; 11647 fault.address = gva; 11648 } 11649 vcpu->arch.walk_mmu->inject_page_fault(vcpu, &fault); 11650 } 11651 EXPORT_SYMBOL_GPL(kvm_fixup_and_inject_pf_error); 11652 11653 /* 11654 * Handles kvm_read/write_guest_virt*() result and either injects #PF or returns 11655 * KVM_EXIT_INTERNAL_ERROR for cases not currently handled by KVM. Return value 11656 * indicates whether exit to userspace is needed. 11657 */ 11658 int kvm_handle_memory_failure(struct kvm_vcpu *vcpu, int r, 11659 struct x86_exception *e) 11660 { 11661 if (r == X86EMUL_PROPAGATE_FAULT) { 11662 kvm_inject_emulated_page_fault(vcpu, e); 11663 return 1; 11664 } 11665 11666 /* 11667 * In case kvm_read/write_guest_virt*() failed with X86EMUL_IO_NEEDED 11668 * while handling a VMX instruction KVM could've handled the request 11669 * correctly by exiting to userspace and performing I/O but there 11670 * doesn't seem to be a real use-case behind such requests, just return 11671 * KVM_EXIT_INTERNAL_ERROR for now. 11672 */ 11673 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR; 11674 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION; 11675 vcpu->run->internal.ndata = 0; 11676 11677 return 0; 11678 } 11679 EXPORT_SYMBOL_GPL(kvm_handle_memory_failure); 11680 11681 int kvm_handle_invpcid(struct kvm_vcpu *vcpu, unsigned long type, gva_t gva) 11682 { 11683 bool pcid_enabled; 11684 struct x86_exception e; 11685 unsigned i; 11686 unsigned long roots_to_free = 0; 11687 struct { 11688 u64 pcid; 11689 u64 gla; 11690 } operand; 11691 int r; 11692 11693 r = kvm_read_guest_virt(vcpu, gva, &operand, sizeof(operand), &e); 11694 if (r != X86EMUL_CONTINUE) 11695 return kvm_handle_memory_failure(vcpu, r, &e); 11696 11697 if (operand.pcid >> 12 != 0) { 11698 kvm_inject_gp(vcpu, 0); 11699 return 1; 11700 } 11701 11702 pcid_enabled = kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE); 11703 11704 switch (type) { 11705 case INVPCID_TYPE_INDIV_ADDR: 11706 if ((!pcid_enabled && (operand.pcid != 0)) || 11707 is_noncanonical_address(operand.gla, vcpu)) { 11708 kvm_inject_gp(vcpu, 0); 11709 return 1; 11710 } 11711 kvm_mmu_invpcid_gva(vcpu, operand.gla, operand.pcid); 11712 return kvm_skip_emulated_instruction(vcpu); 11713 11714 case INVPCID_TYPE_SINGLE_CTXT: 11715 if (!pcid_enabled && (operand.pcid != 0)) { 11716 kvm_inject_gp(vcpu, 0); 11717 return 1; 11718 } 11719 11720 if (kvm_get_active_pcid(vcpu) == operand.pcid) { 11721 kvm_mmu_sync_roots(vcpu); 11722 kvm_make_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu); 11723 } 11724 11725 for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++) 11726 if (kvm_get_pcid(vcpu, vcpu->arch.mmu->prev_roots[i].pgd) 11727 == operand.pcid) 11728 roots_to_free |= KVM_MMU_ROOT_PREVIOUS(i); 11729 11730 kvm_mmu_free_roots(vcpu, vcpu->arch.mmu, roots_to_free); 11731 /* 11732 * If neither the current cr3 nor any of the prev_roots use the 11733 * given PCID, then nothing needs to be done here because a 11734 * resync will happen anyway before switching to any other CR3. 11735 */ 11736 11737 return kvm_skip_emulated_instruction(vcpu); 11738 11739 case INVPCID_TYPE_ALL_NON_GLOBAL: 11740 /* 11741 * Currently, KVM doesn't mark global entries in the shadow 11742 * page tables, so a non-global flush just degenerates to a 11743 * global flush. If needed, we could optimize this later by 11744 * keeping track of global entries in shadow page tables. 11745 */ 11746 11747 fallthrough; 11748 case INVPCID_TYPE_ALL_INCL_GLOBAL: 11749 kvm_make_request(KVM_REQ_MMU_RELOAD, vcpu); 11750 return kvm_skip_emulated_instruction(vcpu); 11751 11752 default: 11753 BUG(); /* We have already checked above that type <= 3 */ 11754 } 11755 } 11756 EXPORT_SYMBOL_GPL(kvm_handle_invpcid); 11757 11758 static int complete_sev_es_emulated_mmio(struct kvm_vcpu *vcpu) 11759 { 11760 struct kvm_run *run = vcpu->run; 11761 struct kvm_mmio_fragment *frag; 11762 unsigned int len; 11763 11764 BUG_ON(!vcpu->mmio_needed); 11765 11766 /* Complete previous fragment */ 11767 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment]; 11768 len = min(8u, frag->len); 11769 if (!vcpu->mmio_is_write) 11770 memcpy(frag->data, run->mmio.data, len); 11771 11772 if (frag->len <= 8) { 11773 /* Switch to the next fragment. */ 11774 frag++; 11775 vcpu->mmio_cur_fragment++; 11776 } else { 11777 /* Go forward to the next mmio piece. */ 11778 frag->data += len; 11779 frag->gpa += len; 11780 frag->len -= len; 11781 } 11782 11783 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) { 11784 vcpu->mmio_needed = 0; 11785 11786 // VMG change, at this point, we're always done 11787 // RIP has already been advanced 11788 return 1; 11789 } 11790 11791 // More MMIO is needed 11792 run->mmio.phys_addr = frag->gpa; 11793 run->mmio.len = min(8u, frag->len); 11794 run->mmio.is_write = vcpu->mmio_is_write; 11795 if (run->mmio.is_write) 11796 memcpy(run->mmio.data, frag->data, min(8u, frag->len)); 11797 run->exit_reason = KVM_EXIT_MMIO; 11798 11799 vcpu->arch.complete_userspace_io = complete_sev_es_emulated_mmio; 11800 11801 return 0; 11802 } 11803 11804 int kvm_sev_es_mmio_write(struct kvm_vcpu *vcpu, gpa_t gpa, unsigned int bytes, 11805 void *data) 11806 { 11807 int handled; 11808 struct kvm_mmio_fragment *frag; 11809 11810 if (!data) 11811 return -EINVAL; 11812 11813 handled = write_emultor.read_write_mmio(vcpu, gpa, bytes, data); 11814 if (handled == bytes) 11815 return 1; 11816 11817 bytes -= handled; 11818 gpa += handled; 11819 data += handled; 11820 11821 /*TODO: Check if need to increment number of frags */ 11822 frag = vcpu->mmio_fragments; 11823 vcpu->mmio_nr_fragments = 1; 11824 frag->len = bytes; 11825 frag->gpa = gpa; 11826 frag->data = data; 11827 11828 vcpu->mmio_needed = 1; 11829 vcpu->mmio_cur_fragment = 0; 11830 11831 vcpu->run->mmio.phys_addr = gpa; 11832 vcpu->run->mmio.len = min(8u, frag->len); 11833 vcpu->run->mmio.is_write = 1; 11834 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len)); 11835 vcpu->run->exit_reason = KVM_EXIT_MMIO; 11836 11837 vcpu->arch.complete_userspace_io = complete_sev_es_emulated_mmio; 11838 11839 return 0; 11840 } 11841 EXPORT_SYMBOL_GPL(kvm_sev_es_mmio_write); 11842 11843 int kvm_sev_es_mmio_read(struct kvm_vcpu *vcpu, gpa_t gpa, unsigned int bytes, 11844 void *data) 11845 { 11846 int handled; 11847 struct kvm_mmio_fragment *frag; 11848 11849 if (!data) 11850 return -EINVAL; 11851 11852 handled = read_emultor.read_write_mmio(vcpu, gpa, bytes, data); 11853 if (handled == bytes) 11854 return 1; 11855 11856 bytes -= handled; 11857 gpa += handled; 11858 data += handled; 11859 11860 /*TODO: Check if need to increment number of frags */ 11861 frag = vcpu->mmio_fragments; 11862 vcpu->mmio_nr_fragments = 1; 11863 frag->len = bytes; 11864 frag->gpa = gpa; 11865 frag->data = data; 11866 11867 vcpu->mmio_needed = 1; 11868 vcpu->mmio_cur_fragment = 0; 11869 11870 vcpu->run->mmio.phys_addr = gpa; 11871 vcpu->run->mmio.len = min(8u, frag->len); 11872 vcpu->run->mmio.is_write = 0; 11873 vcpu->run->exit_reason = KVM_EXIT_MMIO; 11874 11875 vcpu->arch.complete_userspace_io = complete_sev_es_emulated_mmio; 11876 11877 return 0; 11878 } 11879 EXPORT_SYMBOL_GPL(kvm_sev_es_mmio_read); 11880 11881 static int complete_sev_es_emulated_ins(struct kvm_vcpu *vcpu) 11882 { 11883 memcpy(vcpu->arch.guest_ins_data, vcpu->arch.pio_data, 11884 vcpu->arch.pio.count * vcpu->arch.pio.size); 11885 vcpu->arch.pio.count = 0; 11886 11887 return 1; 11888 } 11889 11890 static int kvm_sev_es_outs(struct kvm_vcpu *vcpu, unsigned int size, 11891 unsigned int port, void *data, unsigned int count) 11892 { 11893 int ret; 11894 11895 ret = emulator_pio_out_emulated(vcpu->arch.emulate_ctxt, size, port, 11896 data, count); 11897 if (ret) 11898 return ret; 11899 11900 vcpu->arch.pio.count = 0; 11901 11902 return 0; 11903 } 11904 11905 static int kvm_sev_es_ins(struct kvm_vcpu *vcpu, unsigned int size, 11906 unsigned int port, void *data, unsigned int count) 11907 { 11908 int ret; 11909 11910 ret = emulator_pio_in_emulated(vcpu->arch.emulate_ctxt, size, port, 11911 data, count); 11912 if (ret) { 11913 vcpu->arch.pio.count = 0; 11914 } else { 11915 vcpu->arch.guest_ins_data = data; 11916 vcpu->arch.complete_userspace_io = complete_sev_es_emulated_ins; 11917 } 11918 11919 return 0; 11920 } 11921 11922 int kvm_sev_es_string_io(struct kvm_vcpu *vcpu, unsigned int size, 11923 unsigned int port, void *data, unsigned int count, 11924 int in) 11925 { 11926 return in ? kvm_sev_es_ins(vcpu, size, port, data, count) 11927 : kvm_sev_es_outs(vcpu, size, port, data, count); 11928 } 11929 EXPORT_SYMBOL_GPL(kvm_sev_es_string_io); 11930 11931 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_entry); 11932 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit); 11933 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_fast_mmio); 11934 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq); 11935 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault); 11936 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr); 11937 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr); 11938 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun); 11939 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit); 11940 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject); 11941 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit); 11942 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmenter_failed); 11943 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga); 11944 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit); 11945 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts); 11946 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset); 11947 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_ple_window_update); 11948 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pml_full); 11949 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pi_irte_update); 11950 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_unaccelerated_access); 11951 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_incomplete_ipi); 11952 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_ga_log); 11953 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_apicv_update_request); 11954 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_vmgexit_enter); 11955 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_vmgexit_exit); 11956 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_vmgexit_msr_protocol_enter); 11957 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_vmgexit_msr_protocol_exit); 11958