1 /* 2 * Kernel-based Virtual Machine driver for Linux 3 * 4 * derived from drivers/kvm/kvm_main.c 5 * 6 * Copyright (C) 2006 Qumranet, Inc. 7 * Copyright (C) 2008 Qumranet, Inc. 8 * Copyright IBM Corporation, 2008 9 * Copyright 2010 Red Hat, Inc. and/or its affiliates. 10 * 11 * Authors: 12 * Avi Kivity <avi@qumranet.com> 13 * Yaniv Kamay <yaniv@qumranet.com> 14 * Amit Shah <amit.shah@qumranet.com> 15 * Ben-Ami Yassour <benami@il.ibm.com> 16 * 17 * This work is licensed under the terms of the GNU GPL, version 2. See 18 * the COPYING file in the top-level directory. 19 * 20 */ 21 22 #include <linux/kvm_host.h> 23 #include "irq.h" 24 #include "mmu.h" 25 #include "i8254.h" 26 #include "tss.h" 27 #include "kvm_cache_regs.h" 28 #include "x86.h" 29 #include "cpuid.h" 30 #include "pmu.h" 31 #include "hyperv.h" 32 33 #include <linux/clocksource.h> 34 #include <linux/interrupt.h> 35 #include <linux/kvm.h> 36 #include <linux/fs.h> 37 #include <linux/vmalloc.h> 38 #include <linux/export.h> 39 #include <linux/moduleparam.h> 40 #include <linux/mman.h> 41 #include <linux/highmem.h> 42 #include <linux/iommu.h> 43 #include <linux/intel-iommu.h> 44 #include <linux/cpufreq.h> 45 #include <linux/user-return-notifier.h> 46 #include <linux/srcu.h> 47 #include <linux/slab.h> 48 #include <linux/perf_event.h> 49 #include <linux/uaccess.h> 50 #include <linux/hash.h> 51 #include <linux/pci.h> 52 #include <linux/timekeeper_internal.h> 53 #include <linux/pvclock_gtod.h> 54 #include <linux/kvm_irqfd.h> 55 #include <linux/irqbypass.h> 56 #include <linux/sched/stat.h> 57 #include <linux/mem_encrypt.h> 58 59 #include <trace/events/kvm.h> 60 61 #include <asm/debugreg.h> 62 #include <asm/msr.h> 63 #include <asm/desc.h> 64 #include <asm/mce.h> 65 #include <linux/kernel_stat.h> 66 #include <asm/fpu/internal.h> /* Ugh! */ 67 #include <asm/pvclock.h> 68 #include <asm/div64.h> 69 #include <asm/irq_remapping.h> 70 #include <asm/mshyperv.h> 71 #include <asm/hypervisor.h> 72 #include <asm/intel_pt.h> 73 74 #define CREATE_TRACE_POINTS 75 #include "trace.h" 76 77 #define MAX_IO_MSRS 256 78 #define KVM_MAX_MCE_BANKS 32 79 u64 __read_mostly kvm_mce_cap_supported = MCG_CTL_P | MCG_SER_P; 80 EXPORT_SYMBOL_GPL(kvm_mce_cap_supported); 81 82 #define emul_to_vcpu(ctxt) \ 83 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt) 84 85 /* EFER defaults: 86 * - enable syscall per default because its emulated by KVM 87 * - enable LME and LMA per default on 64 bit KVM 88 */ 89 #ifdef CONFIG_X86_64 90 static 91 u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA)); 92 #else 93 static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE); 94 #endif 95 96 #define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM 97 #define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU 98 99 #define KVM_X2APIC_API_VALID_FLAGS (KVM_X2APIC_API_USE_32BIT_IDS | \ 100 KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK) 101 102 static void update_cr8_intercept(struct kvm_vcpu *vcpu); 103 static void process_nmi(struct kvm_vcpu *vcpu); 104 static void enter_smm(struct kvm_vcpu *vcpu); 105 static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags); 106 static void store_regs(struct kvm_vcpu *vcpu); 107 static int sync_regs(struct kvm_vcpu *vcpu); 108 109 struct kvm_x86_ops *kvm_x86_ops __read_mostly; 110 EXPORT_SYMBOL_GPL(kvm_x86_ops); 111 112 static bool __read_mostly ignore_msrs = 0; 113 module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR); 114 115 static bool __read_mostly report_ignored_msrs = true; 116 module_param(report_ignored_msrs, bool, S_IRUGO | S_IWUSR); 117 118 unsigned int min_timer_period_us = 200; 119 module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR); 120 121 static bool __read_mostly kvmclock_periodic_sync = true; 122 module_param(kvmclock_periodic_sync, bool, S_IRUGO); 123 124 bool __read_mostly kvm_has_tsc_control; 125 EXPORT_SYMBOL_GPL(kvm_has_tsc_control); 126 u32 __read_mostly kvm_max_guest_tsc_khz; 127 EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz); 128 u8 __read_mostly kvm_tsc_scaling_ratio_frac_bits; 129 EXPORT_SYMBOL_GPL(kvm_tsc_scaling_ratio_frac_bits); 130 u64 __read_mostly kvm_max_tsc_scaling_ratio; 131 EXPORT_SYMBOL_GPL(kvm_max_tsc_scaling_ratio); 132 u64 __read_mostly kvm_default_tsc_scaling_ratio; 133 EXPORT_SYMBOL_GPL(kvm_default_tsc_scaling_ratio); 134 135 /* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */ 136 static u32 __read_mostly tsc_tolerance_ppm = 250; 137 module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR); 138 139 /* 140 * lapic timer advance (tscdeadline mode only) in nanoseconds. '-1' enables 141 * adaptive tuning starting from default advancment of 1000ns. '0' disables 142 * advancement entirely. Any other value is used as-is and disables adaptive 143 * tuning, i.e. allows priveleged userspace to set an exact advancement time. 144 */ 145 static int __read_mostly lapic_timer_advance_ns = -1; 146 module_param(lapic_timer_advance_ns, uint, S_IRUGO | S_IWUSR); 147 148 static bool __read_mostly vector_hashing = true; 149 module_param(vector_hashing, bool, S_IRUGO); 150 151 bool __read_mostly enable_vmware_backdoor = false; 152 module_param(enable_vmware_backdoor, bool, S_IRUGO); 153 EXPORT_SYMBOL_GPL(enable_vmware_backdoor); 154 155 static bool __read_mostly force_emulation_prefix = false; 156 module_param(force_emulation_prefix, bool, S_IRUGO); 157 158 #define KVM_NR_SHARED_MSRS 16 159 160 struct kvm_shared_msrs_global { 161 int nr; 162 u32 msrs[KVM_NR_SHARED_MSRS]; 163 }; 164 165 struct kvm_shared_msrs { 166 struct user_return_notifier urn; 167 bool registered; 168 struct kvm_shared_msr_values { 169 u64 host; 170 u64 curr; 171 } values[KVM_NR_SHARED_MSRS]; 172 }; 173 174 static struct kvm_shared_msrs_global __read_mostly shared_msrs_global; 175 static struct kvm_shared_msrs __percpu *shared_msrs; 176 177 struct kvm_stats_debugfs_item debugfs_entries[] = { 178 { "pf_fixed", VCPU_STAT(pf_fixed) }, 179 { "pf_guest", VCPU_STAT(pf_guest) }, 180 { "tlb_flush", VCPU_STAT(tlb_flush) }, 181 { "invlpg", VCPU_STAT(invlpg) }, 182 { "exits", VCPU_STAT(exits) }, 183 { "io_exits", VCPU_STAT(io_exits) }, 184 { "mmio_exits", VCPU_STAT(mmio_exits) }, 185 { "signal_exits", VCPU_STAT(signal_exits) }, 186 { "irq_window", VCPU_STAT(irq_window_exits) }, 187 { "nmi_window", VCPU_STAT(nmi_window_exits) }, 188 { "halt_exits", VCPU_STAT(halt_exits) }, 189 { "halt_successful_poll", VCPU_STAT(halt_successful_poll) }, 190 { "halt_attempted_poll", VCPU_STAT(halt_attempted_poll) }, 191 { "halt_poll_invalid", VCPU_STAT(halt_poll_invalid) }, 192 { "halt_wakeup", VCPU_STAT(halt_wakeup) }, 193 { "hypercalls", VCPU_STAT(hypercalls) }, 194 { "request_irq", VCPU_STAT(request_irq_exits) }, 195 { "irq_exits", VCPU_STAT(irq_exits) }, 196 { "host_state_reload", VCPU_STAT(host_state_reload) }, 197 { "fpu_reload", VCPU_STAT(fpu_reload) }, 198 { "insn_emulation", VCPU_STAT(insn_emulation) }, 199 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) }, 200 { "irq_injections", VCPU_STAT(irq_injections) }, 201 { "nmi_injections", VCPU_STAT(nmi_injections) }, 202 { "req_event", VCPU_STAT(req_event) }, 203 { "l1d_flush", VCPU_STAT(l1d_flush) }, 204 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) }, 205 { "mmu_pte_write", VM_STAT(mmu_pte_write) }, 206 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) }, 207 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) }, 208 { "mmu_flooded", VM_STAT(mmu_flooded) }, 209 { "mmu_recycled", VM_STAT(mmu_recycled) }, 210 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) }, 211 { "mmu_unsync", VM_STAT(mmu_unsync) }, 212 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) }, 213 { "largepages", VM_STAT(lpages) }, 214 { "max_mmu_page_hash_collisions", 215 VM_STAT(max_mmu_page_hash_collisions) }, 216 { NULL } 217 }; 218 219 u64 __read_mostly host_xcr0; 220 221 struct kmem_cache *x86_fpu_cache; 222 EXPORT_SYMBOL_GPL(x86_fpu_cache); 223 224 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt); 225 226 static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu) 227 { 228 int i; 229 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++) 230 vcpu->arch.apf.gfns[i] = ~0; 231 } 232 233 static void kvm_on_user_return(struct user_return_notifier *urn) 234 { 235 unsigned slot; 236 struct kvm_shared_msrs *locals 237 = container_of(urn, struct kvm_shared_msrs, urn); 238 struct kvm_shared_msr_values *values; 239 unsigned long flags; 240 241 /* 242 * Disabling irqs at this point since the following code could be 243 * interrupted and executed through kvm_arch_hardware_disable() 244 */ 245 local_irq_save(flags); 246 if (locals->registered) { 247 locals->registered = false; 248 user_return_notifier_unregister(urn); 249 } 250 local_irq_restore(flags); 251 for (slot = 0; slot < shared_msrs_global.nr; ++slot) { 252 values = &locals->values[slot]; 253 if (values->host != values->curr) { 254 wrmsrl(shared_msrs_global.msrs[slot], values->host); 255 values->curr = values->host; 256 } 257 } 258 } 259 260 static void shared_msr_update(unsigned slot, u32 msr) 261 { 262 u64 value; 263 unsigned int cpu = smp_processor_id(); 264 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu); 265 266 /* only read, and nobody should modify it at this time, 267 * so don't need lock */ 268 if (slot >= shared_msrs_global.nr) { 269 printk(KERN_ERR "kvm: invalid MSR slot!"); 270 return; 271 } 272 rdmsrl_safe(msr, &value); 273 smsr->values[slot].host = value; 274 smsr->values[slot].curr = value; 275 } 276 277 void kvm_define_shared_msr(unsigned slot, u32 msr) 278 { 279 BUG_ON(slot >= KVM_NR_SHARED_MSRS); 280 shared_msrs_global.msrs[slot] = msr; 281 if (slot >= shared_msrs_global.nr) 282 shared_msrs_global.nr = slot + 1; 283 } 284 EXPORT_SYMBOL_GPL(kvm_define_shared_msr); 285 286 static void kvm_shared_msr_cpu_online(void) 287 { 288 unsigned i; 289 290 for (i = 0; i < shared_msrs_global.nr; ++i) 291 shared_msr_update(i, shared_msrs_global.msrs[i]); 292 } 293 294 int kvm_set_shared_msr(unsigned slot, u64 value, u64 mask) 295 { 296 unsigned int cpu = smp_processor_id(); 297 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu); 298 int err; 299 300 if (((value ^ smsr->values[slot].curr) & mask) == 0) 301 return 0; 302 smsr->values[slot].curr = value; 303 err = wrmsrl_safe(shared_msrs_global.msrs[slot], value); 304 if (err) 305 return 1; 306 307 if (!smsr->registered) { 308 smsr->urn.on_user_return = kvm_on_user_return; 309 user_return_notifier_register(&smsr->urn); 310 smsr->registered = true; 311 } 312 return 0; 313 } 314 EXPORT_SYMBOL_GPL(kvm_set_shared_msr); 315 316 static void drop_user_return_notifiers(void) 317 { 318 unsigned int cpu = smp_processor_id(); 319 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu); 320 321 if (smsr->registered) 322 kvm_on_user_return(&smsr->urn); 323 } 324 325 u64 kvm_get_apic_base(struct kvm_vcpu *vcpu) 326 { 327 return vcpu->arch.apic_base; 328 } 329 EXPORT_SYMBOL_GPL(kvm_get_apic_base); 330 331 enum lapic_mode kvm_get_apic_mode(struct kvm_vcpu *vcpu) 332 { 333 return kvm_apic_mode(kvm_get_apic_base(vcpu)); 334 } 335 EXPORT_SYMBOL_GPL(kvm_get_apic_mode); 336 337 int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info) 338 { 339 enum lapic_mode old_mode = kvm_get_apic_mode(vcpu); 340 enum lapic_mode new_mode = kvm_apic_mode(msr_info->data); 341 u64 reserved_bits = ((~0ULL) << cpuid_maxphyaddr(vcpu)) | 0x2ff | 342 (guest_cpuid_has(vcpu, X86_FEATURE_X2APIC) ? 0 : X2APIC_ENABLE); 343 344 if ((msr_info->data & reserved_bits) != 0 || new_mode == LAPIC_MODE_INVALID) 345 return 1; 346 if (!msr_info->host_initiated) { 347 if (old_mode == LAPIC_MODE_X2APIC && new_mode == LAPIC_MODE_XAPIC) 348 return 1; 349 if (old_mode == LAPIC_MODE_DISABLED && new_mode == LAPIC_MODE_X2APIC) 350 return 1; 351 } 352 353 kvm_lapic_set_base(vcpu, msr_info->data); 354 return 0; 355 } 356 EXPORT_SYMBOL_GPL(kvm_set_apic_base); 357 358 asmlinkage __visible void kvm_spurious_fault(void) 359 { 360 /* Fault while not rebooting. We want the trace. */ 361 BUG(); 362 } 363 EXPORT_SYMBOL_GPL(kvm_spurious_fault); 364 365 #define EXCPT_BENIGN 0 366 #define EXCPT_CONTRIBUTORY 1 367 #define EXCPT_PF 2 368 369 static int exception_class(int vector) 370 { 371 switch (vector) { 372 case PF_VECTOR: 373 return EXCPT_PF; 374 case DE_VECTOR: 375 case TS_VECTOR: 376 case NP_VECTOR: 377 case SS_VECTOR: 378 case GP_VECTOR: 379 return EXCPT_CONTRIBUTORY; 380 default: 381 break; 382 } 383 return EXCPT_BENIGN; 384 } 385 386 #define EXCPT_FAULT 0 387 #define EXCPT_TRAP 1 388 #define EXCPT_ABORT 2 389 #define EXCPT_INTERRUPT 3 390 391 static int exception_type(int vector) 392 { 393 unsigned int mask; 394 395 if (WARN_ON(vector > 31 || vector == NMI_VECTOR)) 396 return EXCPT_INTERRUPT; 397 398 mask = 1 << vector; 399 400 /* #DB is trap, as instruction watchpoints are handled elsewhere */ 401 if (mask & ((1 << DB_VECTOR) | (1 << BP_VECTOR) | (1 << OF_VECTOR))) 402 return EXCPT_TRAP; 403 404 if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR))) 405 return EXCPT_ABORT; 406 407 /* Reserved exceptions will result in fault */ 408 return EXCPT_FAULT; 409 } 410 411 void kvm_deliver_exception_payload(struct kvm_vcpu *vcpu) 412 { 413 unsigned nr = vcpu->arch.exception.nr; 414 bool has_payload = vcpu->arch.exception.has_payload; 415 unsigned long payload = vcpu->arch.exception.payload; 416 417 if (!has_payload) 418 return; 419 420 switch (nr) { 421 case DB_VECTOR: 422 /* 423 * "Certain debug exceptions may clear bit 0-3. The 424 * remaining contents of the DR6 register are never 425 * cleared by the processor". 426 */ 427 vcpu->arch.dr6 &= ~DR_TRAP_BITS; 428 /* 429 * DR6.RTM is set by all #DB exceptions that don't clear it. 430 */ 431 vcpu->arch.dr6 |= DR6_RTM; 432 vcpu->arch.dr6 |= payload; 433 /* 434 * Bit 16 should be set in the payload whenever the #DB 435 * exception should clear DR6.RTM. This makes the payload 436 * compatible with the pending debug exceptions under VMX. 437 * Though not currently documented in the SDM, this also 438 * makes the payload compatible with the exit qualification 439 * for #DB exceptions under VMX. 440 */ 441 vcpu->arch.dr6 ^= payload & DR6_RTM; 442 break; 443 case PF_VECTOR: 444 vcpu->arch.cr2 = payload; 445 break; 446 } 447 448 vcpu->arch.exception.has_payload = false; 449 vcpu->arch.exception.payload = 0; 450 } 451 EXPORT_SYMBOL_GPL(kvm_deliver_exception_payload); 452 453 static void kvm_multiple_exception(struct kvm_vcpu *vcpu, 454 unsigned nr, bool has_error, u32 error_code, 455 bool has_payload, unsigned long payload, bool reinject) 456 { 457 u32 prev_nr; 458 int class1, class2; 459 460 kvm_make_request(KVM_REQ_EVENT, vcpu); 461 462 if (!vcpu->arch.exception.pending && !vcpu->arch.exception.injected) { 463 queue: 464 if (has_error && !is_protmode(vcpu)) 465 has_error = false; 466 if (reinject) { 467 /* 468 * On vmentry, vcpu->arch.exception.pending is only 469 * true if an event injection was blocked by 470 * nested_run_pending. In that case, however, 471 * vcpu_enter_guest requests an immediate exit, 472 * and the guest shouldn't proceed far enough to 473 * need reinjection. 474 */ 475 WARN_ON_ONCE(vcpu->arch.exception.pending); 476 vcpu->arch.exception.injected = true; 477 if (WARN_ON_ONCE(has_payload)) { 478 /* 479 * A reinjected event has already 480 * delivered its payload. 481 */ 482 has_payload = false; 483 payload = 0; 484 } 485 } else { 486 vcpu->arch.exception.pending = true; 487 vcpu->arch.exception.injected = false; 488 } 489 vcpu->arch.exception.has_error_code = has_error; 490 vcpu->arch.exception.nr = nr; 491 vcpu->arch.exception.error_code = error_code; 492 vcpu->arch.exception.has_payload = has_payload; 493 vcpu->arch.exception.payload = payload; 494 /* 495 * In guest mode, payload delivery should be deferred, 496 * so that the L1 hypervisor can intercept #PF before 497 * CR2 is modified (or intercept #DB before DR6 is 498 * modified under nVMX). However, for ABI 499 * compatibility with KVM_GET_VCPU_EVENTS and 500 * KVM_SET_VCPU_EVENTS, we can't delay payload 501 * delivery unless userspace has enabled this 502 * functionality via the per-VM capability, 503 * KVM_CAP_EXCEPTION_PAYLOAD. 504 */ 505 if (!vcpu->kvm->arch.exception_payload_enabled || 506 !is_guest_mode(vcpu)) 507 kvm_deliver_exception_payload(vcpu); 508 return; 509 } 510 511 /* to check exception */ 512 prev_nr = vcpu->arch.exception.nr; 513 if (prev_nr == DF_VECTOR) { 514 /* triple fault -> shutdown */ 515 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); 516 return; 517 } 518 class1 = exception_class(prev_nr); 519 class2 = exception_class(nr); 520 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY) 521 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) { 522 /* 523 * Generate double fault per SDM Table 5-5. Set 524 * exception.pending = true so that the double fault 525 * can trigger a nested vmexit. 526 */ 527 vcpu->arch.exception.pending = true; 528 vcpu->arch.exception.injected = false; 529 vcpu->arch.exception.has_error_code = true; 530 vcpu->arch.exception.nr = DF_VECTOR; 531 vcpu->arch.exception.error_code = 0; 532 vcpu->arch.exception.has_payload = false; 533 vcpu->arch.exception.payload = 0; 534 } else 535 /* replace previous exception with a new one in a hope 536 that instruction re-execution will regenerate lost 537 exception */ 538 goto queue; 539 } 540 541 void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr) 542 { 543 kvm_multiple_exception(vcpu, nr, false, 0, false, 0, false); 544 } 545 EXPORT_SYMBOL_GPL(kvm_queue_exception); 546 547 void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr) 548 { 549 kvm_multiple_exception(vcpu, nr, false, 0, false, 0, true); 550 } 551 EXPORT_SYMBOL_GPL(kvm_requeue_exception); 552 553 static void kvm_queue_exception_p(struct kvm_vcpu *vcpu, unsigned nr, 554 unsigned long payload) 555 { 556 kvm_multiple_exception(vcpu, nr, false, 0, true, payload, false); 557 } 558 559 static void kvm_queue_exception_e_p(struct kvm_vcpu *vcpu, unsigned nr, 560 u32 error_code, unsigned long payload) 561 { 562 kvm_multiple_exception(vcpu, nr, true, error_code, 563 true, payload, false); 564 } 565 566 int kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err) 567 { 568 if (err) 569 kvm_inject_gp(vcpu, 0); 570 else 571 return kvm_skip_emulated_instruction(vcpu); 572 573 return 1; 574 } 575 EXPORT_SYMBOL_GPL(kvm_complete_insn_gp); 576 577 void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault) 578 { 579 ++vcpu->stat.pf_guest; 580 vcpu->arch.exception.nested_apf = 581 is_guest_mode(vcpu) && fault->async_page_fault; 582 if (vcpu->arch.exception.nested_apf) { 583 vcpu->arch.apf.nested_apf_token = fault->address; 584 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code); 585 } else { 586 kvm_queue_exception_e_p(vcpu, PF_VECTOR, fault->error_code, 587 fault->address); 588 } 589 } 590 EXPORT_SYMBOL_GPL(kvm_inject_page_fault); 591 592 static bool kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault) 593 { 594 if (mmu_is_nested(vcpu) && !fault->nested_page_fault) 595 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault); 596 else 597 vcpu->arch.mmu->inject_page_fault(vcpu, fault); 598 599 return fault->nested_page_fault; 600 } 601 602 void kvm_inject_nmi(struct kvm_vcpu *vcpu) 603 { 604 atomic_inc(&vcpu->arch.nmi_queued); 605 kvm_make_request(KVM_REQ_NMI, vcpu); 606 } 607 EXPORT_SYMBOL_GPL(kvm_inject_nmi); 608 609 void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code) 610 { 611 kvm_multiple_exception(vcpu, nr, true, error_code, false, 0, false); 612 } 613 EXPORT_SYMBOL_GPL(kvm_queue_exception_e); 614 615 void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code) 616 { 617 kvm_multiple_exception(vcpu, nr, true, error_code, false, 0, true); 618 } 619 EXPORT_SYMBOL_GPL(kvm_requeue_exception_e); 620 621 /* 622 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue 623 * a #GP and return false. 624 */ 625 bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl) 626 { 627 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl) 628 return true; 629 kvm_queue_exception_e(vcpu, GP_VECTOR, 0); 630 return false; 631 } 632 EXPORT_SYMBOL_GPL(kvm_require_cpl); 633 634 bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr) 635 { 636 if ((dr != 4 && dr != 5) || !kvm_read_cr4_bits(vcpu, X86_CR4_DE)) 637 return true; 638 639 kvm_queue_exception(vcpu, UD_VECTOR); 640 return false; 641 } 642 EXPORT_SYMBOL_GPL(kvm_require_dr); 643 644 /* 645 * This function will be used to read from the physical memory of the currently 646 * running guest. The difference to kvm_vcpu_read_guest_page is that this function 647 * can read from guest physical or from the guest's guest physical memory. 648 */ 649 int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, 650 gfn_t ngfn, void *data, int offset, int len, 651 u32 access) 652 { 653 struct x86_exception exception; 654 gfn_t real_gfn; 655 gpa_t ngpa; 656 657 ngpa = gfn_to_gpa(ngfn); 658 real_gfn = mmu->translate_gpa(vcpu, ngpa, access, &exception); 659 if (real_gfn == UNMAPPED_GVA) 660 return -EFAULT; 661 662 real_gfn = gpa_to_gfn(real_gfn); 663 664 return kvm_vcpu_read_guest_page(vcpu, real_gfn, data, offset, len); 665 } 666 EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu); 667 668 static int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn, 669 void *data, int offset, int len, u32 access) 670 { 671 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn, 672 data, offset, len, access); 673 } 674 675 /* 676 * Load the pae pdptrs. Return true is they are all valid. 677 */ 678 int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3) 679 { 680 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT; 681 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2; 682 int i; 683 int ret; 684 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)]; 685 686 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte, 687 offset * sizeof(u64), sizeof(pdpte), 688 PFERR_USER_MASK|PFERR_WRITE_MASK); 689 if (ret < 0) { 690 ret = 0; 691 goto out; 692 } 693 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) { 694 if ((pdpte[i] & PT_PRESENT_MASK) && 695 (pdpte[i] & 696 vcpu->arch.mmu->guest_rsvd_check.rsvd_bits_mask[0][2])) { 697 ret = 0; 698 goto out; 699 } 700 } 701 ret = 1; 702 703 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs)); 704 __set_bit(VCPU_EXREG_PDPTR, 705 (unsigned long *)&vcpu->arch.regs_avail); 706 __set_bit(VCPU_EXREG_PDPTR, 707 (unsigned long *)&vcpu->arch.regs_dirty); 708 out: 709 710 return ret; 711 } 712 EXPORT_SYMBOL_GPL(load_pdptrs); 713 714 bool pdptrs_changed(struct kvm_vcpu *vcpu) 715 { 716 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)]; 717 bool changed = true; 718 int offset; 719 gfn_t gfn; 720 int r; 721 722 if (is_long_mode(vcpu) || !is_pae(vcpu) || !is_paging(vcpu)) 723 return false; 724 725 if (!test_bit(VCPU_EXREG_PDPTR, 726 (unsigned long *)&vcpu->arch.regs_avail)) 727 return true; 728 729 gfn = (kvm_read_cr3(vcpu) & 0xffffffe0ul) >> PAGE_SHIFT; 730 offset = (kvm_read_cr3(vcpu) & 0xffffffe0ul) & (PAGE_SIZE - 1); 731 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte), 732 PFERR_USER_MASK | PFERR_WRITE_MASK); 733 if (r < 0) 734 goto out; 735 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0; 736 out: 737 738 return changed; 739 } 740 EXPORT_SYMBOL_GPL(pdptrs_changed); 741 742 int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0) 743 { 744 unsigned long old_cr0 = kvm_read_cr0(vcpu); 745 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP; 746 747 cr0 |= X86_CR0_ET; 748 749 #ifdef CONFIG_X86_64 750 if (cr0 & 0xffffffff00000000UL) 751 return 1; 752 #endif 753 754 cr0 &= ~CR0_RESERVED_BITS; 755 756 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD)) 757 return 1; 758 759 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE)) 760 return 1; 761 762 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) { 763 #ifdef CONFIG_X86_64 764 if ((vcpu->arch.efer & EFER_LME)) { 765 int cs_db, cs_l; 766 767 if (!is_pae(vcpu)) 768 return 1; 769 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l); 770 if (cs_l) 771 return 1; 772 } else 773 #endif 774 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu, 775 kvm_read_cr3(vcpu))) 776 return 1; 777 } 778 779 if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE)) 780 return 1; 781 782 kvm_x86_ops->set_cr0(vcpu, cr0); 783 784 if ((cr0 ^ old_cr0) & X86_CR0_PG) { 785 kvm_clear_async_pf_completion_queue(vcpu); 786 kvm_async_pf_hash_reset(vcpu); 787 } 788 789 if ((cr0 ^ old_cr0) & update_bits) 790 kvm_mmu_reset_context(vcpu); 791 792 if (((cr0 ^ old_cr0) & X86_CR0_CD) && 793 kvm_arch_has_noncoherent_dma(vcpu->kvm) && 794 !kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED)) 795 kvm_zap_gfn_range(vcpu->kvm, 0, ~0ULL); 796 797 return 0; 798 } 799 EXPORT_SYMBOL_GPL(kvm_set_cr0); 800 801 void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw) 802 { 803 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f)); 804 } 805 EXPORT_SYMBOL_GPL(kvm_lmsw); 806 807 void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu) 808 { 809 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) && 810 !vcpu->guest_xcr0_loaded) { 811 /* kvm_set_xcr() also depends on this */ 812 if (vcpu->arch.xcr0 != host_xcr0) 813 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0); 814 vcpu->guest_xcr0_loaded = 1; 815 } 816 } 817 EXPORT_SYMBOL_GPL(kvm_load_guest_xcr0); 818 819 void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu) 820 { 821 if (vcpu->guest_xcr0_loaded) { 822 if (vcpu->arch.xcr0 != host_xcr0) 823 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0); 824 vcpu->guest_xcr0_loaded = 0; 825 } 826 } 827 EXPORT_SYMBOL_GPL(kvm_put_guest_xcr0); 828 829 static int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr) 830 { 831 u64 xcr0 = xcr; 832 u64 old_xcr0 = vcpu->arch.xcr0; 833 u64 valid_bits; 834 835 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */ 836 if (index != XCR_XFEATURE_ENABLED_MASK) 837 return 1; 838 if (!(xcr0 & XFEATURE_MASK_FP)) 839 return 1; 840 if ((xcr0 & XFEATURE_MASK_YMM) && !(xcr0 & XFEATURE_MASK_SSE)) 841 return 1; 842 843 /* 844 * Do not allow the guest to set bits that we do not support 845 * saving. However, xcr0 bit 0 is always set, even if the 846 * emulated CPU does not support XSAVE (see fx_init). 847 */ 848 valid_bits = vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FP; 849 if (xcr0 & ~valid_bits) 850 return 1; 851 852 if ((!(xcr0 & XFEATURE_MASK_BNDREGS)) != 853 (!(xcr0 & XFEATURE_MASK_BNDCSR))) 854 return 1; 855 856 if (xcr0 & XFEATURE_MASK_AVX512) { 857 if (!(xcr0 & XFEATURE_MASK_YMM)) 858 return 1; 859 if ((xcr0 & XFEATURE_MASK_AVX512) != XFEATURE_MASK_AVX512) 860 return 1; 861 } 862 vcpu->arch.xcr0 = xcr0; 863 864 if ((xcr0 ^ old_xcr0) & XFEATURE_MASK_EXTEND) 865 kvm_update_cpuid(vcpu); 866 return 0; 867 } 868 869 int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr) 870 { 871 if (kvm_x86_ops->get_cpl(vcpu) != 0 || 872 __kvm_set_xcr(vcpu, index, xcr)) { 873 kvm_inject_gp(vcpu, 0); 874 return 1; 875 } 876 return 0; 877 } 878 EXPORT_SYMBOL_GPL(kvm_set_xcr); 879 880 int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4) 881 { 882 unsigned long old_cr4 = kvm_read_cr4(vcpu); 883 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE | 884 X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE; 885 886 if (cr4 & CR4_RESERVED_BITS) 887 return 1; 888 889 if (!guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) && (cr4 & X86_CR4_OSXSAVE)) 890 return 1; 891 892 if (!guest_cpuid_has(vcpu, X86_FEATURE_SMEP) && (cr4 & X86_CR4_SMEP)) 893 return 1; 894 895 if (!guest_cpuid_has(vcpu, X86_FEATURE_SMAP) && (cr4 & X86_CR4_SMAP)) 896 return 1; 897 898 if (!guest_cpuid_has(vcpu, X86_FEATURE_FSGSBASE) && (cr4 & X86_CR4_FSGSBASE)) 899 return 1; 900 901 if (!guest_cpuid_has(vcpu, X86_FEATURE_PKU) && (cr4 & X86_CR4_PKE)) 902 return 1; 903 904 if (!guest_cpuid_has(vcpu, X86_FEATURE_LA57) && (cr4 & X86_CR4_LA57)) 905 return 1; 906 907 if (!guest_cpuid_has(vcpu, X86_FEATURE_UMIP) && (cr4 & X86_CR4_UMIP)) 908 return 1; 909 910 if (is_long_mode(vcpu)) { 911 if (!(cr4 & X86_CR4_PAE)) 912 return 1; 913 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE) 914 && ((cr4 ^ old_cr4) & pdptr_bits) 915 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu, 916 kvm_read_cr3(vcpu))) 917 return 1; 918 919 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) { 920 if (!guest_cpuid_has(vcpu, X86_FEATURE_PCID)) 921 return 1; 922 923 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */ 924 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu)) 925 return 1; 926 } 927 928 if (kvm_x86_ops->set_cr4(vcpu, cr4)) 929 return 1; 930 931 if (((cr4 ^ old_cr4) & pdptr_bits) || 932 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE))) 933 kvm_mmu_reset_context(vcpu); 934 935 if ((cr4 ^ old_cr4) & (X86_CR4_OSXSAVE | X86_CR4_PKE)) 936 kvm_update_cpuid(vcpu); 937 938 return 0; 939 } 940 EXPORT_SYMBOL_GPL(kvm_set_cr4); 941 942 int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3) 943 { 944 bool skip_tlb_flush = false; 945 #ifdef CONFIG_X86_64 946 bool pcid_enabled = kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE); 947 948 if (pcid_enabled) { 949 skip_tlb_flush = cr3 & X86_CR3_PCID_NOFLUSH; 950 cr3 &= ~X86_CR3_PCID_NOFLUSH; 951 } 952 #endif 953 954 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) { 955 if (!skip_tlb_flush) { 956 kvm_mmu_sync_roots(vcpu); 957 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu); 958 } 959 return 0; 960 } 961 962 if (is_long_mode(vcpu) && 963 (cr3 & rsvd_bits(cpuid_maxphyaddr(vcpu), 63))) 964 return 1; 965 else if (is_pae(vcpu) && is_paging(vcpu) && 966 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3)) 967 return 1; 968 969 kvm_mmu_new_cr3(vcpu, cr3, skip_tlb_flush); 970 vcpu->arch.cr3 = cr3; 971 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail); 972 973 return 0; 974 } 975 EXPORT_SYMBOL_GPL(kvm_set_cr3); 976 977 int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8) 978 { 979 if (cr8 & CR8_RESERVED_BITS) 980 return 1; 981 if (lapic_in_kernel(vcpu)) 982 kvm_lapic_set_tpr(vcpu, cr8); 983 else 984 vcpu->arch.cr8 = cr8; 985 return 0; 986 } 987 EXPORT_SYMBOL_GPL(kvm_set_cr8); 988 989 unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu) 990 { 991 if (lapic_in_kernel(vcpu)) 992 return kvm_lapic_get_cr8(vcpu); 993 else 994 return vcpu->arch.cr8; 995 } 996 EXPORT_SYMBOL_GPL(kvm_get_cr8); 997 998 static void kvm_update_dr0123(struct kvm_vcpu *vcpu) 999 { 1000 int i; 1001 1002 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) { 1003 for (i = 0; i < KVM_NR_DB_REGS; i++) 1004 vcpu->arch.eff_db[i] = vcpu->arch.db[i]; 1005 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_RELOAD; 1006 } 1007 } 1008 1009 static void kvm_update_dr6(struct kvm_vcpu *vcpu) 1010 { 1011 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) 1012 kvm_x86_ops->set_dr6(vcpu, vcpu->arch.dr6); 1013 } 1014 1015 static void kvm_update_dr7(struct kvm_vcpu *vcpu) 1016 { 1017 unsigned long dr7; 1018 1019 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) 1020 dr7 = vcpu->arch.guest_debug_dr7; 1021 else 1022 dr7 = vcpu->arch.dr7; 1023 kvm_x86_ops->set_dr7(vcpu, dr7); 1024 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED; 1025 if (dr7 & DR7_BP_EN_MASK) 1026 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED; 1027 } 1028 1029 static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu) 1030 { 1031 u64 fixed = DR6_FIXED_1; 1032 1033 if (!guest_cpuid_has(vcpu, X86_FEATURE_RTM)) 1034 fixed |= DR6_RTM; 1035 return fixed; 1036 } 1037 1038 static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val) 1039 { 1040 switch (dr) { 1041 case 0 ... 3: 1042 vcpu->arch.db[dr] = val; 1043 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) 1044 vcpu->arch.eff_db[dr] = val; 1045 break; 1046 case 4: 1047 /* fall through */ 1048 case 6: 1049 if (val & 0xffffffff00000000ULL) 1050 return -1; /* #GP */ 1051 vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu); 1052 kvm_update_dr6(vcpu); 1053 break; 1054 case 5: 1055 /* fall through */ 1056 default: /* 7 */ 1057 if (val & 0xffffffff00000000ULL) 1058 return -1; /* #GP */ 1059 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1; 1060 kvm_update_dr7(vcpu); 1061 break; 1062 } 1063 1064 return 0; 1065 } 1066 1067 int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val) 1068 { 1069 if (__kvm_set_dr(vcpu, dr, val)) { 1070 kvm_inject_gp(vcpu, 0); 1071 return 1; 1072 } 1073 return 0; 1074 } 1075 EXPORT_SYMBOL_GPL(kvm_set_dr); 1076 1077 int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val) 1078 { 1079 switch (dr) { 1080 case 0 ... 3: 1081 *val = vcpu->arch.db[dr]; 1082 break; 1083 case 4: 1084 /* fall through */ 1085 case 6: 1086 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) 1087 *val = vcpu->arch.dr6; 1088 else 1089 *val = kvm_x86_ops->get_dr6(vcpu); 1090 break; 1091 case 5: 1092 /* fall through */ 1093 default: /* 7 */ 1094 *val = vcpu->arch.dr7; 1095 break; 1096 } 1097 return 0; 1098 } 1099 EXPORT_SYMBOL_GPL(kvm_get_dr); 1100 1101 bool kvm_rdpmc(struct kvm_vcpu *vcpu) 1102 { 1103 u32 ecx = kvm_register_read(vcpu, VCPU_REGS_RCX); 1104 u64 data; 1105 int err; 1106 1107 err = kvm_pmu_rdpmc(vcpu, ecx, &data); 1108 if (err) 1109 return err; 1110 kvm_register_write(vcpu, VCPU_REGS_RAX, (u32)data); 1111 kvm_register_write(vcpu, VCPU_REGS_RDX, data >> 32); 1112 return err; 1113 } 1114 EXPORT_SYMBOL_GPL(kvm_rdpmc); 1115 1116 /* 1117 * List of msr numbers which we expose to userspace through KVM_GET_MSRS 1118 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST. 1119 * 1120 * This list is modified at module load time to reflect the 1121 * capabilities of the host cpu. This capabilities test skips MSRs that are 1122 * kvm-specific. Those are put in emulated_msrs; filtering of emulated_msrs 1123 * may depend on host virtualization features rather than host cpu features. 1124 */ 1125 1126 static u32 msrs_to_save[] = { 1127 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP, 1128 MSR_STAR, 1129 #ifdef CONFIG_X86_64 1130 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR, 1131 #endif 1132 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA, 1133 MSR_IA32_FEATURE_CONTROL, MSR_IA32_BNDCFGS, MSR_TSC_AUX, 1134 MSR_IA32_SPEC_CTRL, 1135 MSR_IA32_RTIT_CTL, MSR_IA32_RTIT_STATUS, MSR_IA32_RTIT_CR3_MATCH, 1136 MSR_IA32_RTIT_OUTPUT_BASE, MSR_IA32_RTIT_OUTPUT_MASK, 1137 MSR_IA32_RTIT_ADDR0_A, MSR_IA32_RTIT_ADDR0_B, 1138 MSR_IA32_RTIT_ADDR1_A, MSR_IA32_RTIT_ADDR1_B, 1139 MSR_IA32_RTIT_ADDR2_A, MSR_IA32_RTIT_ADDR2_B, 1140 MSR_IA32_RTIT_ADDR3_A, MSR_IA32_RTIT_ADDR3_B, 1141 }; 1142 1143 static unsigned num_msrs_to_save; 1144 1145 static u32 emulated_msrs[] = { 1146 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK, 1147 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW, 1148 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL, 1149 HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC, 1150 HV_X64_MSR_TSC_FREQUENCY, HV_X64_MSR_APIC_FREQUENCY, 1151 HV_X64_MSR_CRASH_P0, HV_X64_MSR_CRASH_P1, HV_X64_MSR_CRASH_P2, 1152 HV_X64_MSR_CRASH_P3, HV_X64_MSR_CRASH_P4, HV_X64_MSR_CRASH_CTL, 1153 HV_X64_MSR_RESET, 1154 HV_X64_MSR_VP_INDEX, 1155 HV_X64_MSR_VP_RUNTIME, 1156 HV_X64_MSR_SCONTROL, 1157 HV_X64_MSR_STIMER0_CONFIG, 1158 HV_X64_MSR_VP_ASSIST_PAGE, 1159 HV_X64_MSR_REENLIGHTENMENT_CONTROL, HV_X64_MSR_TSC_EMULATION_CONTROL, 1160 HV_X64_MSR_TSC_EMULATION_STATUS, 1161 1162 MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME, 1163 MSR_KVM_PV_EOI_EN, 1164 1165 MSR_IA32_TSC_ADJUST, 1166 MSR_IA32_TSCDEADLINE, 1167 MSR_IA32_ARCH_CAPABILITIES, 1168 MSR_IA32_MISC_ENABLE, 1169 MSR_IA32_MCG_STATUS, 1170 MSR_IA32_MCG_CTL, 1171 MSR_IA32_MCG_EXT_CTL, 1172 MSR_IA32_SMBASE, 1173 MSR_SMI_COUNT, 1174 MSR_PLATFORM_INFO, 1175 MSR_MISC_FEATURES_ENABLES, 1176 MSR_AMD64_VIRT_SPEC_CTRL, 1177 }; 1178 1179 static unsigned num_emulated_msrs; 1180 1181 /* 1182 * List of msr numbers which are used to expose MSR-based features that 1183 * can be used by a hypervisor to validate requested CPU features. 1184 */ 1185 static u32 msr_based_features[] = { 1186 MSR_IA32_VMX_BASIC, 1187 MSR_IA32_VMX_TRUE_PINBASED_CTLS, 1188 MSR_IA32_VMX_PINBASED_CTLS, 1189 MSR_IA32_VMX_TRUE_PROCBASED_CTLS, 1190 MSR_IA32_VMX_PROCBASED_CTLS, 1191 MSR_IA32_VMX_TRUE_EXIT_CTLS, 1192 MSR_IA32_VMX_EXIT_CTLS, 1193 MSR_IA32_VMX_TRUE_ENTRY_CTLS, 1194 MSR_IA32_VMX_ENTRY_CTLS, 1195 MSR_IA32_VMX_MISC, 1196 MSR_IA32_VMX_CR0_FIXED0, 1197 MSR_IA32_VMX_CR0_FIXED1, 1198 MSR_IA32_VMX_CR4_FIXED0, 1199 MSR_IA32_VMX_CR4_FIXED1, 1200 MSR_IA32_VMX_VMCS_ENUM, 1201 MSR_IA32_VMX_PROCBASED_CTLS2, 1202 MSR_IA32_VMX_EPT_VPID_CAP, 1203 MSR_IA32_VMX_VMFUNC, 1204 1205 MSR_F10H_DECFG, 1206 MSR_IA32_UCODE_REV, 1207 MSR_IA32_ARCH_CAPABILITIES, 1208 }; 1209 1210 static unsigned int num_msr_based_features; 1211 1212 u64 kvm_get_arch_capabilities(void) 1213 { 1214 u64 data; 1215 1216 rdmsrl_safe(MSR_IA32_ARCH_CAPABILITIES, &data); 1217 1218 /* 1219 * If we're doing cache flushes (either "always" or "cond") 1220 * we will do one whenever the guest does a vmlaunch/vmresume. 1221 * If an outer hypervisor is doing the cache flush for us 1222 * (VMENTER_L1D_FLUSH_NESTED_VM), we can safely pass that 1223 * capability to the guest too, and if EPT is disabled we're not 1224 * vulnerable. Overall, only VMENTER_L1D_FLUSH_NEVER will 1225 * require a nested hypervisor to do a flush of its own. 1226 */ 1227 if (l1tf_vmx_mitigation != VMENTER_L1D_FLUSH_NEVER) 1228 data |= ARCH_CAP_SKIP_VMENTRY_L1DFLUSH; 1229 1230 return data; 1231 } 1232 EXPORT_SYMBOL_GPL(kvm_get_arch_capabilities); 1233 1234 static int kvm_get_msr_feature(struct kvm_msr_entry *msr) 1235 { 1236 switch (msr->index) { 1237 case MSR_IA32_ARCH_CAPABILITIES: 1238 msr->data = kvm_get_arch_capabilities(); 1239 break; 1240 case MSR_IA32_UCODE_REV: 1241 rdmsrl_safe(msr->index, &msr->data); 1242 break; 1243 default: 1244 if (kvm_x86_ops->get_msr_feature(msr)) 1245 return 1; 1246 } 1247 return 0; 1248 } 1249 1250 static int do_get_msr_feature(struct kvm_vcpu *vcpu, unsigned index, u64 *data) 1251 { 1252 struct kvm_msr_entry msr; 1253 int r; 1254 1255 msr.index = index; 1256 r = kvm_get_msr_feature(&msr); 1257 if (r) 1258 return r; 1259 1260 *data = msr.data; 1261 1262 return 0; 1263 } 1264 1265 bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer) 1266 { 1267 if (efer & efer_reserved_bits) 1268 return false; 1269 1270 if (efer & EFER_FFXSR && !guest_cpuid_has(vcpu, X86_FEATURE_FXSR_OPT)) 1271 return false; 1272 1273 if (efer & EFER_SVME && !guest_cpuid_has(vcpu, X86_FEATURE_SVM)) 1274 return false; 1275 1276 return true; 1277 } 1278 EXPORT_SYMBOL_GPL(kvm_valid_efer); 1279 1280 static int set_efer(struct kvm_vcpu *vcpu, u64 efer) 1281 { 1282 u64 old_efer = vcpu->arch.efer; 1283 1284 if (!kvm_valid_efer(vcpu, efer)) 1285 return 1; 1286 1287 if (is_paging(vcpu) 1288 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME)) 1289 return 1; 1290 1291 efer &= ~EFER_LMA; 1292 efer |= vcpu->arch.efer & EFER_LMA; 1293 1294 kvm_x86_ops->set_efer(vcpu, efer); 1295 1296 /* Update reserved bits */ 1297 if ((efer ^ old_efer) & EFER_NX) 1298 kvm_mmu_reset_context(vcpu); 1299 1300 return 0; 1301 } 1302 1303 void kvm_enable_efer_bits(u64 mask) 1304 { 1305 efer_reserved_bits &= ~mask; 1306 } 1307 EXPORT_SYMBOL_GPL(kvm_enable_efer_bits); 1308 1309 /* 1310 * Writes msr value into into the appropriate "register". 1311 * Returns 0 on success, non-0 otherwise. 1312 * Assumes vcpu_load() was already called. 1313 */ 1314 int kvm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr) 1315 { 1316 switch (msr->index) { 1317 case MSR_FS_BASE: 1318 case MSR_GS_BASE: 1319 case MSR_KERNEL_GS_BASE: 1320 case MSR_CSTAR: 1321 case MSR_LSTAR: 1322 if (is_noncanonical_address(msr->data, vcpu)) 1323 return 1; 1324 break; 1325 case MSR_IA32_SYSENTER_EIP: 1326 case MSR_IA32_SYSENTER_ESP: 1327 /* 1328 * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if 1329 * non-canonical address is written on Intel but not on 1330 * AMD (which ignores the top 32-bits, because it does 1331 * not implement 64-bit SYSENTER). 1332 * 1333 * 64-bit code should hence be able to write a non-canonical 1334 * value on AMD. Making the address canonical ensures that 1335 * vmentry does not fail on Intel after writing a non-canonical 1336 * value, and that something deterministic happens if the guest 1337 * invokes 64-bit SYSENTER. 1338 */ 1339 msr->data = get_canonical(msr->data, vcpu_virt_addr_bits(vcpu)); 1340 } 1341 return kvm_x86_ops->set_msr(vcpu, msr); 1342 } 1343 EXPORT_SYMBOL_GPL(kvm_set_msr); 1344 1345 /* 1346 * Adapt set_msr() to msr_io()'s calling convention 1347 */ 1348 static int do_get_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data) 1349 { 1350 struct msr_data msr; 1351 int r; 1352 1353 msr.index = index; 1354 msr.host_initiated = true; 1355 r = kvm_get_msr(vcpu, &msr); 1356 if (r) 1357 return r; 1358 1359 *data = msr.data; 1360 return 0; 1361 } 1362 1363 static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data) 1364 { 1365 struct msr_data msr; 1366 1367 msr.data = *data; 1368 msr.index = index; 1369 msr.host_initiated = true; 1370 return kvm_set_msr(vcpu, &msr); 1371 } 1372 1373 #ifdef CONFIG_X86_64 1374 struct pvclock_gtod_data { 1375 seqcount_t seq; 1376 1377 struct { /* extract of a clocksource struct */ 1378 int vclock_mode; 1379 u64 cycle_last; 1380 u64 mask; 1381 u32 mult; 1382 u32 shift; 1383 } clock; 1384 1385 u64 boot_ns; 1386 u64 nsec_base; 1387 u64 wall_time_sec; 1388 }; 1389 1390 static struct pvclock_gtod_data pvclock_gtod_data; 1391 1392 static void update_pvclock_gtod(struct timekeeper *tk) 1393 { 1394 struct pvclock_gtod_data *vdata = &pvclock_gtod_data; 1395 u64 boot_ns; 1396 1397 boot_ns = ktime_to_ns(ktime_add(tk->tkr_mono.base, tk->offs_boot)); 1398 1399 write_seqcount_begin(&vdata->seq); 1400 1401 /* copy pvclock gtod data */ 1402 vdata->clock.vclock_mode = tk->tkr_mono.clock->archdata.vclock_mode; 1403 vdata->clock.cycle_last = tk->tkr_mono.cycle_last; 1404 vdata->clock.mask = tk->tkr_mono.mask; 1405 vdata->clock.mult = tk->tkr_mono.mult; 1406 vdata->clock.shift = tk->tkr_mono.shift; 1407 1408 vdata->boot_ns = boot_ns; 1409 vdata->nsec_base = tk->tkr_mono.xtime_nsec; 1410 1411 vdata->wall_time_sec = tk->xtime_sec; 1412 1413 write_seqcount_end(&vdata->seq); 1414 } 1415 #endif 1416 1417 void kvm_set_pending_timer(struct kvm_vcpu *vcpu) 1418 { 1419 /* 1420 * Note: KVM_REQ_PENDING_TIMER is implicitly checked in 1421 * vcpu_enter_guest. This function is only called from 1422 * the physical CPU that is running vcpu. 1423 */ 1424 kvm_make_request(KVM_REQ_PENDING_TIMER, vcpu); 1425 } 1426 1427 static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock) 1428 { 1429 int version; 1430 int r; 1431 struct pvclock_wall_clock wc; 1432 struct timespec64 boot; 1433 1434 if (!wall_clock) 1435 return; 1436 1437 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version)); 1438 if (r) 1439 return; 1440 1441 if (version & 1) 1442 ++version; /* first time write, random junk */ 1443 1444 ++version; 1445 1446 if (kvm_write_guest(kvm, wall_clock, &version, sizeof(version))) 1447 return; 1448 1449 /* 1450 * The guest calculates current wall clock time by adding 1451 * system time (updated by kvm_guest_time_update below) to the 1452 * wall clock specified here. guest system time equals host 1453 * system time for us, thus we must fill in host boot time here. 1454 */ 1455 getboottime64(&boot); 1456 1457 if (kvm->arch.kvmclock_offset) { 1458 struct timespec64 ts = ns_to_timespec64(kvm->arch.kvmclock_offset); 1459 boot = timespec64_sub(boot, ts); 1460 } 1461 wc.sec = (u32)boot.tv_sec; /* overflow in 2106 guest time */ 1462 wc.nsec = boot.tv_nsec; 1463 wc.version = version; 1464 1465 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc)); 1466 1467 version++; 1468 kvm_write_guest(kvm, wall_clock, &version, sizeof(version)); 1469 } 1470 1471 static uint32_t div_frac(uint32_t dividend, uint32_t divisor) 1472 { 1473 do_shl32_div32(dividend, divisor); 1474 return dividend; 1475 } 1476 1477 static void kvm_get_time_scale(uint64_t scaled_hz, uint64_t base_hz, 1478 s8 *pshift, u32 *pmultiplier) 1479 { 1480 uint64_t scaled64; 1481 int32_t shift = 0; 1482 uint64_t tps64; 1483 uint32_t tps32; 1484 1485 tps64 = base_hz; 1486 scaled64 = scaled_hz; 1487 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) { 1488 tps64 >>= 1; 1489 shift--; 1490 } 1491 1492 tps32 = (uint32_t)tps64; 1493 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) { 1494 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000) 1495 scaled64 >>= 1; 1496 else 1497 tps32 <<= 1; 1498 shift++; 1499 } 1500 1501 *pshift = shift; 1502 *pmultiplier = div_frac(scaled64, tps32); 1503 1504 pr_debug("%s: base_hz %llu => %llu, shift %d, mul %u\n", 1505 __func__, base_hz, scaled_hz, shift, *pmultiplier); 1506 } 1507 1508 #ifdef CONFIG_X86_64 1509 static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0); 1510 #endif 1511 1512 static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz); 1513 static unsigned long max_tsc_khz; 1514 1515 static u32 adjust_tsc_khz(u32 khz, s32 ppm) 1516 { 1517 u64 v = (u64)khz * (1000000 + ppm); 1518 do_div(v, 1000000); 1519 return v; 1520 } 1521 1522 static int set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale) 1523 { 1524 u64 ratio; 1525 1526 /* Guest TSC same frequency as host TSC? */ 1527 if (!scale) { 1528 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio; 1529 return 0; 1530 } 1531 1532 /* TSC scaling supported? */ 1533 if (!kvm_has_tsc_control) { 1534 if (user_tsc_khz > tsc_khz) { 1535 vcpu->arch.tsc_catchup = 1; 1536 vcpu->arch.tsc_always_catchup = 1; 1537 return 0; 1538 } else { 1539 WARN(1, "user requested TSC rate below hardware speed\n"); 1540 return -1; 1541 } 1542 } 1543 1544 /* TSC scaling required - calculate ratio */ 1545 ratio = mul_u64_u32_div(1ULL << kvm_tsc_scaling_ratio_frac_bits, 1546 user_tsc_khz, tsc_khz); 1547 1548 if (ratio == 0 || ratio >= kvm_max_tsc_scaling_ratio) { 1549 WARN_ONCE(1, "Invalid TSC scaling ratio - virtual-tsc-khz=%u\n", 1550 user_tsc_khz); 1551 return -1; 1552 } 1553 1554 vcpu->arch.tsc_scaling_ratio = ratio; 1555 return 0; 1556 } 1557 1558 static int kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz) 1559 { 1560 u32 thresh_lo, thresh_hi; 1561 int use_scaling = 0; 1562 1563 /* tsc_khz can be zero if TSC calibration fails */ 1564 if (user_tsc_khz == 0) { 1565 /* set tsc_scaling_ratio to a safe value */ 1566 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio; 1567 return -1; 1568 } 1569 1570 /* Compute a scale to convert nanoseconds in TSC cycles */ 1571 kvm_get_time_scale(user_tsc_khz * 1000LL, NSEC_PER_SEC, 1572 &vcpu->arch.virtual_tsc_shift, 1573 &vcpu->arch.virtual_tsc_mult); 1574 vcpu->arch.virtual_tsc_khz = user_tsc_khz; 1575 1576 /* 1577 * Compute the variation in TSC rate which is acceptable 1578 * within the range of tolerance and decide if the 1579 * rate being applied is within that bounds of the hardware 1580 * rate. If so, no scaling or compensation need be done. 1581 */ 1582 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm); 1583 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm); 1584 if (user_tsc_khz < thresh_lo || user_tsc_khz > thresh_hi) { 1585 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", user_tsc_khz, thresh_lo, thresh_hi); 1586 use_scaling = 1; 1587 } 1588 return set_tsc_khz(vcpu, user_tsc_khz, use_scaling); 1589 } 1590 1591 static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns) 1592 { 1593 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec, 1594 vcpu->arch.virtual_tsc_mult, 1595 vcpu->arch.virtual_tsc_shift); 1596 tsc += vcpu->arch.this_tsc_write; 1597 return tsc; 1598 } 1599 1600 static inline int gtod_is_based_on_tsc(int mode) 1601 { 1602 return mode == VCLOCK_TSC || mode == VCLOCK_HVCLOCK; 1603 } 1604 1605 static void kvm_track_tsc_matching(struct kvm_vcpu *vcpu) 1606 { 1607 #ifdef CONFIG_X86_64 1608 bool vcpus_matched; 1609 struct kvm_arch *ka = &vcpu->kvm->arch; 1610 struct pvclock_gtod_data *gtod = &pvclock_gtod_data; 1611 1612 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 == 1613 atomic_read(&vcpu->kvm->online_vcpus)); 1614 1615 /* 1616 * Once the masterclock is enabled, always perform request in 1617 * order to update it. 1618 * 1619 * In order to enable masterclock, the host clocksource must be TSC 1620 * and the vcpus need to have matched TSCs. When that happens, 1621 * perform request to enable masterclock. 1622 */ 1623 if (ka->use_master_clock || 1624 (gtod_is_based_on_tsc(gtod->clock.vclock_mode) && vcpus_matched)) 1625 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu); 1626 1627 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc, 1628 atomic_read(&vcpu->kvm->online_vcpus), 1629 ka->use_master_clock, gtod->clock.vclock_mode); 1630 #endif 1631 } 1632 1633 static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset) 1634 { 1635 u64 curr_offset = kvm_x86_ops->read_l1_tsc_offset(vcpu); 1636 vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset; 1637 } 1638 1639 /* 1640 * Multiply tsc by a fixed point number represented by ratio. 1641 * 1642 * The most significant 64-N bits (mult) of ratio represent the 1643 * integral part of the fixed point number; the remaining N bits 1644 * (frac) represent the fractional part, ie. ratio represents a fixed 1645 * point number (mult + frac * 2^(-N)). 1646 * 1647 * N equals to kvm_tsc_scaling_ratio_frac_bits. 1648 */ 1649 static inline u64 __scale_tsc(u64 ratio, u64 tsc) 1650 { 1651 return mul_u64_u64_shr(tsc, ratio, kvm_tsc_scaling_ratio_frac_bits); 1652 } 1653 1654 u64 kvm_scale_tsc(struct kvm_vcpu *vcpu, u64 tsc) 1655 { 1656 u64 _tsc = tsc; 1657 u64 ratio = vcpu->arch.tsc_scaling_ratio; 1658 1659 if (ratio != kvm_default_tsc_scaling_ratio) 1660 _tsc = __scale_tsc(ratio, tsc); 1661 1662 return _tsc; 1663 } 1664 EXPORT_SYMBOL_GPL(kvm_scale_tsc); 1665 1666 static u64 kvm_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc) 1667 { 1668 u64 tsc; 1669 1670 tsc = kvm_scale_tsc(vcpu, rdtsc()); 1671 1672 return target_tsc - tsc; 1673 } 1674 1675 u64 kvm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc) 1676 { 1677 u64 tsc_offset = kvm_x86_ops->read_l1_tsc_offset(vcpu); 1678 1679 return tsc_offset + kvm_scale_tsc(vcpu, host_tsc); 1680 } 1681 EXPORT_SYMBOL_GPL(kvm_read_l1_tsc); 1682 1683 static void kvm_vcpu_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset) 1684 { 1685 vcpu->arch.tsc_offset = kvm_x86_ops->write_l1_tsc_offset(vcpu, offset); 1686 } 1687 1688 static inline bool kvm_check_tsc_unstable(void) 1689 { 1690 #ifdef CONFIG_X86_64 1691 /* 1692 * TSC is marked unstable when we're running on Hyper-V, 1693 * 'TSC page' clocksource is good. 1694 */ 1695 if (pvclock_gtod_data.clock.vclock_mode == VCLOCK_HVCLOCK) 1696 return false; 1697 #endif 1698 return check_tsc_unstable(); 1699 } 1700 1701 void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr) 1702 { 1703 struct kvm *kvm = vcpu->kvm; 1704 u64 offset, ns, elapsed; 1705 unsigned long flags; 1706 bool matched; 1707 bool already_matched; 1708 u64 data = msr->data; 1709 bool synchronizing = false; 1710 1711 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags); 1712 offset = kvm_compute_tsc_offset(vcpu, data); 1713 ns = ktime_get_boot_ns(); 1714 elapsed = ns - kvm->arch.last_tsc_nsec; 1715 1716 if (vcpu->arch.virtual_tsc_khz) { 1717 if (data == 0 && msr->host_initiated) { 1718 /* 1719 * detection of vcpu initialization -- need to sync 1720 * with other vCPUs. This particularly helps to keep 1721 * kvm_clock stable after CPU hotplug 1722 */ 1723 synchronizing = true; 1724 } else { 1725 u64 tsc_exp = kvm->arch.last_tsc_write + 1726 nsec_to_cycles(vcpu, elapsed); 1727 u64 tsc_hz = vcpu->arch.virtual_tsc_khz * 1000LL; 1728 /* 1729 * Special case: TSC write with a small delta (1 second) 1730 * of virtual cycle time against real time is 1731 * interpreted as an attempt to synchronize the CPU. 1732 */ 1733 synchronizing = data < tsc_exp + tsc_hz && 1734 data + tsc_hz > tsc_exp; 1735 } 1736 } 1737 1738 /* 1739 * For a reliable TSC, we can match TSC offsets, and for an unstable 1740 * TSC, we add elapsed time in this computation. We could let the 1741 * compensation code attempt to catch up if we fall behind, but 1742 * it's better to try to match offsets from the beginning. 1743 */ 1744 if (synchronizing && 1745 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) { 1746 if (!kvm_check_tsc_unstable()) { 1747 offset = kvm->arch.cur_tsc_offset; 1748 pr_debug("kvm: matched tsc offset for %llu\n", data); 1749 } else { 1750 u64 delta = nsec_to_cycles(vcpu, elapsed); 1751 data += delta; 1752 offset = kvm_compute_tsc_offset(vcpu, data); 1753 pr_debug("kvm: adjusted tsc offset by %llu\n", delta); 1754 } 1755 matched = true; 1756 already_matched = (vcpu->arch.this_tsc_generation == kvm->arch.cur_tsc_generation); 1757 } else { 1758 /* 1759 * We split periods of matched TSC writes into generations. 1760 * For each generation, we track the original measured 1761 * nanosecond time, offset, and write, so if TSCs are in 1762 * sync, we can match exact offset, and if not, we can match 1763 * exact software computation in compute_guest_tsc() 1764 * 1765 * These values are tracked in kvm->arch.cur_xxx variables. 1766 */ 1767 kvm->arch.cur_tsc_generation++; 1768 kvm->arch.cur_tsc_nsec = ns; 1769 kvm->arch.cur_tsc_write = data; 1770 kvm->arch.cur_tsc_offset = offset; 1771 matched = false; 1772 pr_debug("kvm: new tsc generation %llu, clock %llu\n", 1773 kvm->arch.cur_tsc_generation, data); 1774 } 1775 1776 /* 1777 * We also track th most recent recorded KHZ, write and time to 1778 * allow the matching interval to be extended at each write. 1779 */ 1780 kvm->arch.last_tsc_nsec = ns; 1781 kvm->arch.last_tsc_write = data; 1782 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz; 1783 1784 vcpu->arch.last_guest_tsc = data; 1785 1786 /* Keep track of which generation this VCPU has synchronized to */ 1787 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation; 1788 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec; 1789 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write; 1790 1791 if (!msr->host_initiated && guest_cpuid_has(vcpu, X86_FEATURE_TSC_ADJUST)) 1792 update_ia32_tsc_adjust_msr(vcpu, offset); 1793 1794 kvm_vcpu_write_tsc_offset(vcpu, offset); 1795 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags); 1796 1797 spin_lock(&kvm->arch.pvclock_gtod_sync_lock); 1798 if (!matched) { 1799 kvm->arch.nr_vcpus_matched_tsc = 0; 1800 } else if (!already_matched) { 1801 kvm->arch.nr_vcpus_matched_tsc++; 1802 } 1803 1804 kvm_track_tsc_matching(vcpu); 1805 spin_unlock(&kvm->arch.pvclock_gtod_sync_lock); 1806 } 1807 1808 EXPORT_SYMBOL_GPL(kvm_write_tsc); 1809 1810 static inline void adjust_tsc_offset_guest(struct kvm_vcpu *vcpu, 1811 s64 adjustment) 1812 { 1813 u64 tsc_offset = kvm_x86_ops->read_l1_tsc_offset(vcpu); 1814 kvm_vcpu_write_tsc_offset(vcpu, tsc_offset + adjustment); 1815 } 1816 1817 static inline void adjust_tsc_offset_host(struct kvm_vcpu *vcpu, s64 adjustment) 1818 { 1819 if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio) 1820 WARN_ON(adjustment < 0); 1821 adjustment = kvm_scale_tsc(vcpu, (u64) adjustment); 1822 adjust_tsc_offset_guest(vcpu, adjustment); 1823 } 1824 1825 #ifdef CONFIG_X86_64 1826 1827 static u64 read_tsc(void) 1828 { 1829 u64 ret = (u64)rdtsc_ordered(); 1830 u64 last = pvclock_gtod_data.clock.cycle_last; 1831 1832 if (likely(ret >= last)) 1833 return ret; 1834 1835 /* 1836 * GCC likes to generate cmov here, but this branch is extremely 1837 * predictable (it's just a function of time and the likely is 1838 * very likely) and there's a data dependence, so force GCC 1839 * to generate a branch instead. I don't barrier() because 1840 * we don't actually need a barrier, and if this function 1841 * ever gets inlined it will generate worse code. 1842 */ 1843 asm volatile (""); 1844 return last; 1845 } 1846 1847 static inline u64 vgettsc(u64 *tsc_timestamp, int *mode) 1848 { 1849 long v; 1850 struct pvclock_gtod_data *gtod = &pvclock_gtod_data; 1851 u64 tsc_pg_val; 1852 1853 switch (gtod->clock.vclock_mode) { 1854 case VCLOCK_HVCLOCK: 1855 tsc_pg_val = hv_read_tsc_page_tsc(hv_get_tsc_page(), 1856 tsc_timestamp); 1857 if (tsc_pg_val != U64_MAX) { 1858 /* TSC page valid */ 1859 *mode = VCLOCK_HVCLOCK; 1860 v = (tsc_pg_val - gtod->clock.cycle_last) & 1861 gtod->clock.mask; 1862 } else { 1863 /* TSC page invalid */ 1864 *mode = VCLOCK_NONE; 1865 } 1866 break; 1867 case VCLOCK_TSC: 1868 *mode = VCLOCK_TSC; 1869 *tsc_timestamp = read_tsc(); 1870 v = (*tsc_timestamp - gtod->clock.cycle_last) & 1871 gtod->clock.mask; 1872 break; 1873 default: 1874 *mode = VCLOCK_NONE; 1875 } 1876 1877 if (*mode == VCLOCK_NONE) 1878 *tsc_timestamp = v = 0; 1879 1880 return v * gtod->clock.mult; 1881 } 1882 1883 static int do_monotonic_boot(s64 *t, u64 *tsc_timestamp) 1884 { 1885 struct pvclock_gtod_data *gtod = &pvclock_gtod_data; 1886 unsigned long seq; 1887 int mode; 1888 u64 ns; 1889 1890 do { 1891 seq = read_seqcount_begin(>od->seq); 1892 ns = gtod->nsec_base; 1893 ns += vgettsc(tsc_timestamp, &mode); 1894 ns >>= gtod->clock.shift; 1895 ns += gtod->boot_ns; 1896 } while (unlikely(read_seqcount_retry(>od->seq, seq))); 1897 *t = ns; 1898 1899 return mode; 1900 } 1901 1902 static int do_realtime(struct timespec64 *ts, u64 *tsc_timestamp) 1903 { 1904 struct pvclock_gtod_data *gtod = &pvclock_gtod_data; 1905 unsigned long seq; 1906 int mode; 1907 u64 ns; 1908 1909 do { 1910 seq = read_seqcount_begin(>od->seq); 1911 ts->tv_sec = gtod->wall_time_sec; 1912 ns = gtod->nsec_base; 1913 ns += vgettsc(tsc_timestamp, &mode); 1914 ns >>= gtod->clock.shift; 1915 } while (unlikely(read_seqcount_retry(>od->seq, seq))); 1916 1917 ts->tv_sec += __iter_div_u64_rem(ns, NSEC_PER_SEC, &ns); 1918 ts->tv_nsec = ns; 1919 1920 return mode; 1921 } 1922 1923 /* returns true if host is using TSC based clocksource */ 1924 static bool kvm_get_time_and_clockread(s64 *kernel_ns, u64 *tsc_timestamp) 1925 { 1926 /* checked again under seqlock below */ 1927 if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode)) 1928 return false; 1929 1930 return gtod_is_based_on_tsc(do_monotonic_boot(kernel_ns, 1931 tsc_timestamp)); 1932 } 1933 1934 /* returns true if host is using TSC based clocksource */ 1935 static bool kvm_get_walltime_and_clockread(struct timespec64 *ts, 1936 u64 *tsc_timestamp) 1937 { 1938 /* checked again under seqlock below */ 1939 if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode)) 1940 return false; 1941 1942 return gtod_is_based_on_tsc(do_realtime(ts, tsc_timestamp)); 1943 } 1944 #endif 1945 1946 /* 1947 * 1948 * Assuming a stable TSC across physical CPUS, and a stable TSC 1949 * across virtual CPUs, the following condition is possible. 1950 * Each numbered line represents an event visible to both 1951 * CPUs at the next numbered event. 1952 * 1953 * "timespecX" represents host monotonic time. "tscX" represents 1954 * RDTSC value. 1955 * 1956 * VCPU0 on CPU0 | VCPU1 on CPU1 1957 * 1958 * 1. read timespec0,tsc0 1959 * 2. | timespec1 = timespec0 + N 1960 * | tsc1 = tsc0 + M 1961 * 3. transition to guest | transition to guest 1962 * 4. ret0 = timespec0 + (rdtsc - tsc0) | 1963 * 5. | ret1 = timespec1 + (rdtsc - tsc1) 1964 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M)) 1965 * 1966 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity: 1967 * 1968 * - ret0 < ret1 1969 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M)) 1970 * ... 1971 * - 0 < N - M => M < N 1972 * 1973 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not 1974 * always the case (the difference between two distinct xtime instances 1975 * might be smaller then the difference between corresponding TSC reads, 1976 * when updating guest vcpus pvclock areas). 1977 * 1978 * To avoid that problem, do not allow visibility of distinct 1979 * system_timestamp/tsc_timestamp values simultaneously: use a master 1980 * copy of host monotonic time values. Update that master copy 1981 * in lockstep. 1982 * 1983 * Rely on synchronization of host TSCs and guest TSCs for monotonicity. 1984 * 1985 */ 1986 1987 static void pvclock_update_vm_gtod_copy(struct kvm *kvm) 1988 { 1989 #ifdef CONFIG_X86_64 1990 struct kvm_arch *ka = &kvm->arch; 1991 int vclock_mode; 1992 bool host_tsc_clocksource, vcpus_matched; 1993 1994 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 == 1995 atomic_read(&kvm->online_vcpus)); 1996 1997 /* 1998 * If the host uses TSC clock, then passthrough TSC as stable 1999 * to the guest. 2000 */ 2001 host_tsc_clocksource = kvm_get_time_and_clockread( 2002 &ka->master_kernel_ns, 2003 &ka->master_cycle_now); 2004 2005 ka->use_master_clock = host_tsc_clocksource && vcpus_matched 2006 && !ka->backwards_tsc_observed 2007 && !ka->boot_vcpu_runs_old_kvmclock; 2008 2009 if (ka->use_master_clock) 2010 atomic_set(&kvm_guest_has_master_clock, 1); 2011 2012 vclock_mode = pvclock_gtod_data.clock.vclock_mode; 2013 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode, 2014 vcpus_matched); 2015 #endif 2016 } 2017 2018 void kvm_make_mclock_inprogress_request(struct kvm *kvm) 2019 { 2020 kvm_make_all_cpus_request(kvm, KVM_REQ_MCLOCK_INPROGRESS); 2021 } 2022 2023 static void kvm_gen_update_masterclock(struct kvm *kvm) 2024 { 2025 #ifdef CONFIG_X86_64 2026 int i; 2027 struct kvm_vcpu *vcpu; 2028 struct kvm_arch *ka = &kvm->arch; 2029 2030 spin_lock(&ka->pvclock_gtod_sync_lock); 2031 kvm_make_mclock_inprogress_request(kvm); 2032 /* no guest entries from this point */ 2033 pvclock_update_vm_gtod_copy(kvm); 2034 2035 kvm_for_each_vcpu(i, vcpu, kvm) 2036 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 2037 2038 /* guest entries allowed */ 2039 kvm_for_each_vcpu(i, vcpu, kvm) 2040 kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu); 2041 2042 spin_unlock(&ka->pvclock_gtod_sync_lock); 2043 #endif 2044 } 2045 2046 u64 get_kvmclock_ns(struct kvm *kvm) 2047 { 2048 struct kvm_arch *ka = &kvm->arch; 2049 struct pvclock_vcpu_time_info hv_clock; 2050 u64 ret; 2051 2052 spin_lock(&ka->pvclock_gtod_sync_lock); 2053 if (!ka->use_master_clock) { 2054 spin_unlock(&ka->pvclock_gtod_sync_lock); 2055 return ktime_get_boot_ns() + ka->kvmclock_offset; 2056 } 2057 2058 hv_clock.tsc_timestamp = ka->master_cycle_now; 2059 hv_clock.system_time = ka->master_kernel_ns + ka->kvmclock_offset; 2060 spin_unlock(&ka->pvclock_gtod_sync_lock); 2061 2062 /* both __this_cpu_read() and rdtsc() should be on the same cpu */ 2063 get_cpu(); 2064 2065 if (__this_cpu_read(cpu_tsc_khz)) { 2066 kvm_get_time_scale(NSEC_PER_SEC, __this_cpu_read(cpu_tsc_khz) * 1000LL, 2067 &hv_clock.tsc_shift, 2068 &hv_clock.tsc_to_system_mul); 2069 ret = __pvclock_read_cycles(&hv_clock, rdtsc()); 2070 } else 2071 ret = ktime_get_boot_ns() + ka->kvmclock_offset; 2072 2073 put_cpu(); 2074 2075 return ret; 2076 } 2077 2078 static void kvm_setup_pvclock_page(struct kvm_vcpu *v) 2079 { 2080 struct kvm_vcpu_arch *vcpu = &v->arch; 2081 struct pvclock_vcpu_time_info guest_hv_clock; 2082 2083 if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time, 2084 &guest_hv_clock, sizeof(guest_hv_clock)))) 2085 return; 2086 2087 /* This VCPU is paused, but it's legal for a guest to read another 2088 * VCPU's kvmclock, so we really have to follow the specification where 2089 * it says that version is odd if data is being modified, and even after 2090 * it is consistent. 2091 * 2092 * Version field updates must be kept separate. This is because 2093 * kvm_write_guest_cached might use a "rep movs" instruction, and 2094 * writes within a string instruction are weakly ordered. So there 2095 * are three writes overall. 2096 * 2097 * As a small optimization, only write the version field in the first 2098 * and third write. The vcpu->pv_time cache is still valid, because the 2099 * version field is the first in the struct. 2100 */ 2101 BUILD_BUG_ON(offsetof(struct pvclock_vcpu_time_info, version) != 0); 2102 2103 if (guest_hv_clock.version & 1) 2104 ++guest_hv_clock.version; /* first time write, random junk */ 2105 2106 vcpu->hv_clock.version = guest_hv_clock.version + 1; 2107 kvm_write_guest_cached(v->kvm, &vcpu->pv_time, 2108 &vcpu->hv_clock, 2109 sizeof(vcpu->hv_clock.version)); 2110 2111 smp_wmb(); 2112 2113 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */ 2114 vcpu->hv_clock.flags |= (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED); 2115 2116 if (vcpu->pvclock_set_guest_stopped_request) { 2117 vcpu->hv_clock.flags |= PVCLOCK_GUEST_STOPPED; 2118 vcpu->pvclock_set_guest_stopped_request = false; 2119 } 2120 2121 trace_kvm_pvclock_update(v->vcpu_id, &vcpu->hv_clock); 2122 2123 kvm_write_guest_cached(v->kvm, &vcpu->pv_time, 2124 &vcpu->hv_clock, 2125 sizeof(vcpu->hv_clock)); 2126 2127 smp_wmb(); 2128 2129 vcpu->hv_clock.version++; 2130 kvm_write_guest_cached(v->kvm, &vcpu->pv_time, 2131 &vcpu->hv_clock, 2132 sizeof(vcpu->hv_clock.version)); 2133 } 2134 2135 static int kvm_guest_time_update(struct kvm_vcpu *v) 2136 { 2137 unsigned long flags, tgt_tsc_khz; 2138 struct kvm_vcpu_arch *vcpu = &v->arch; 2139 struct kvm_arch *ka = &v->kvm->arch; 2140 s64 kernel_ns; 2141 u64 tsc_timestamp, host_tsc; 2142 u8 pvclock_flags; 2143 bool use_master_clock; 2144 2145 kernel_ns = 0; 2146 host_tsc = 0; 2147 2148 /* 2149 * If the host uses TSC clock, then passthrough TSC as stable 2150 * to the guest. 2151 */ 2152 spin_lock(&ka->pvclock_gtod_sync_lock); 2153 use_master_clock = ka->use_master_clock; 2154 if (use_master_clock) { 2155 host_tsc = ka->master_cycle_now; 2156 kernel_ns = ka->master_kernel_ns; 2157 } 2158 spin_unlock(&ka->pvclock_gtod_sync_lock); 2159 2160 /* Keep irq disabled to prevent changes to the clock */ 2161 local_irq_save(flags); 2162 tgt_tsc_khz = __this_cpu_read(cpu_tsc_khz); 2163 if (unlikely(tgt_tsc_khz == 0)) { 2164 local_irq_restore(flags); 2165 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v); 2166 return 1; 2167 } 2168 if (!use_master_clock) { 2169 host_tsc = rdtsc(); 2170 kernel_ns = ktime_get_boot_ns(); 2171 } 2172 2173 tsc_timestamp = kvm_read_l1_tsc(v, host_tsc); 2174 2175 /* 2176 * We may have to catch up the TSC to match elapsed wall clock 2177 * time for two reasons, even if kvmclock is used. 2178 * 1) CPU could have been running below the maximum TSC rate 2179 * 2) Broken TSC compensation resets the base at each VCPU 2180 * entry to avoid unknown leaps of TSC even when running 2181 * again on the same CPU. This may cause apparent elapsed 2182 * time to disappear, and the guest to stand still or run 2183 * very slowly. 2184 */ 2185 if (vcpu->tsc_catchup) { 2186 u64 tsc = compute_guest_tsc(v, kernel_ns); 2187 if (tsc > tsc_timestamp) { 2188 adjust_tsc_offset_guest(v, tsc - tsc_timestamp); 2189 tsc_timestamp = tsc; 2190 } 2191 } 2192 2193 local_irq_restore(flags); 2194 2195 /* With all the info we got, fill in the values */ 2196 2197 if (kvm_has_tsc_control) 2198 tgt_tsc_khz = kvm_scale_tsc(v, tgt_tsc_khz); 2199 2200 if (unlikely(vcpu->hw_tsc_khz != tgt_tsc_khz)) { 2201 kvm_get_time_scale(NSEC_PER_SEC, tgt_tsc_khz * 1000LL, 2202 &vcpu->hv_clock.tsc_shift, 2203 &vcpu->hv_clock.tsc_to_system_mul); 2204 vcpu->hw_tsc_khz = tgt_tsc_khz; 2205 } 2206 2207 vcpu->hv_clock.tsc_timestamp = tsc_timestamp; 2208 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset; 2209 vcpu->last_guest_tsc = tsc_timestamp; 2210 2211 /* If the host uses TSC clocksource, then it is stable */ 2212 pvclock_flags = 0; 2213 if (use_master_clock) 2214 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT; 2215 2216 vcpu->hv_clock.flags = pvclock_flags; 2217 2218 if (vcpu->pv_time_enabled) 2219 kvm_setup_pvclock_page(v); 2220 if (v == kvm_get_vcpu(v->kvm, 0)) 2221 kvm_hv_setup_tsc_page(v->kvm, &vcpu->hv_clock); 2222 return 0; 2223 } 2224 2225 /* 2226 * kvmclock updates which are isolated to a given vcpu, such as 2227 * vcpu->cpu migration, should not allow system_timestamp from 2228 * the rest of the vcpus to remain static. Otherwise ntp frequency 2229 * correction applies to one vcpu's system_timestamp but not 2230 * the others. 2231 * 2232 * So in those cases, request a kvmclock update for all vcpus. 2233 * We need to rate-limit these requests though, as they can 2234 * considerably slow guests that have a large number of vcpus. 2235 * The time for a remote vcpu to update its kvmclock is bound 2236 * by the delay we use to rate-limit the updates. 2237 */ 2238 2239 #define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100) 2240 2241 static void kvmclock_update_fn(struct work_struct *work) 2242 { 2243 int i; 2244 struct delayed_work *dwork = to_delayed_work(work); 2245 struct kvm_arch *ka = container_of(dwork, struct kvm_arch, 2246 kvmclock_update_work); 2247 struct kvm *kvm = container_of(ka, struct kvm, arch); 2248 struct kvm_vcpu *vcpu; 2249 2250 kvm_for_each_vcpu(i, vcpu, kvm) { 2251 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 2252 kvm_vcpu_kick(vcpu); 2253 } 2254 } 2255 2256 static void kvm_gen_kvmclock_update(struct kvm_vcpu *v) 2257 { 2258 struct kvm *kvm = v->kvm; 2259 2260 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v); 2261 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 2262 KVMCLOCK_UPDATE_DELAY); 2263 } 2264 2265 #define KVMCLOCK_SYNC_PERIOD (300 * HZ) 2266 2267 static void kvmclock_sync_fn(struct work_struct *work) 2268 { 2269 struct delayed_work *dwork = to_delayed_work(work); 2270 struct kvm_arch *ka = container_of(dwork, struct kvm_arch, 2271 kvmclock_sync_work); 2272 struct kvm *kvm = container_of(ka, struct kvm, arch); 2273 2274 if (!kvmclock_periodic_sync) 2275 return; 2276 2277 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0); 2278 schedule_delayed_work(&kvm->arch.kvmclock_sync_work, 2279 KVMCLOCK_SYNC_PERIOD); 2280 } 2281 2282 static int set_msr_mce(struct kvm_vcpu *vcpu, struct msr_data *msr_info) 2283 { 2284 u64 mcg_cap = vcpu->arch.mcg_cap; 2285 unsigned bank_num = mcg_cap & 0xff; 2286 u32 msr = msr_info->index; 2287 u64 data = msr_info->data; 2288 2289 switch (msr) { 2290 case MSR_IA32_MCG_STATUS: 2291 vcpu->arch.mcg_status = data; 2292 break; 2293 case MSR_IA32_MCG_CTL: 2294 if (!(mcg_cap & MCG_CTL_P) && 2295 (data || !msr_info->host_initiated)) 2296 return 1; 2297 if (data != 0 && data != ~(u64)0) 2298 return 1; 2299 vcpu->arch.mcg_ctl = data; 2300 break; 2301 default: 2302 if (msr >= MSR_IA32_MC0_CTL && 2303 msr < MSR_IA32_MCx_CTL(bank_num)) { 2304 u32 offset = msr - MSR_IA32_MC0_CTL; 2305 /* only 0 or all 1s can be written to IA32_MCi_CTL 2306 * some Linux kernels though clear bit 10 in bank 4 to 2307 * workaround a BIOS/GART TBL issue on AMD K8s, ignore 2308 * this to avoid an uncatched #GP in the guest 2309 */ 2310 if ((offset & 0x3) == 0 && 2311 data != 0 && (data | (1 << 10)) != ~(u64)0) 2312 return -1; 2313 if (!msr_info->host_initiated && 2314 (offset & 0x3) == 1 && data != 0) 2315 return -1; 2316 vcpu->arch.mce_banks[offset] = data; 2317 break; 2318 } 2319 return 1; 2320 } 2321 return 0; 2322 } 2323 2324 static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data) 2325 { 2326 struct kvm *kvm = vcpu->kvm; 2327 int lm = is_long_mode(vcpu); 2328 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64 2329 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32; 2330 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64 2331 : kvm->arch.xen_hvm_config.blob_size_32; 2332 u32 page_num = data & ~PAGE_MASK; 2333 u64 page_addr = data & PAGE_MASK; 2334 u8 *page; 2335 int r; 2336 2337 r = -E2BIG; 2338 if (page_num >= blob_size) 2339 goto out; 2340 r = -ENOMEM; 2341 page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE); 2342 if (IS_ERR(page)) { 2343 r = PTR_ERR(page); 2344 goto out; 2345 } 2346 if (kvm_vcpu_write_guest(vcpu, page_addr, page, PAGE_SIZE)) 2347 goto out_free; 2348 r = 0; 2349 out_free: 2350 kfree(page); 2351 out: 2352 return r; 2353 } 2354 2355 static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data) 2356 { 2357 gpa_t gpa = data & ~0x3f; 2358 2359 /* Bits 3:5 are reserved, Should be zero */ 2360 if (data & 0x38) 2361 return 1; 2362 2363 vcpu->arch.apf.msr_val = data; 2364 2365 if (!(data & KVM_ASYNC_PF_ENABLED)) { 2366 kvm_clear_async_pf_completion_queue(vcpu); 2367 kvm_async_pf_hash_reset(vcpu); 2368 return 0; 2369 } 2370 2371 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa, 2372 sizeof(u32))) 2373 return 1; 2374 2375 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS); 2376 vcpu->arch.apf.delivery_as_pf_vmexit = data & KVM_ASYNC_PF_DELIVERY_AS_PF_VMEXIT; 2377 kvm_async_pf_wakeup_all(vcpu); 2378 return 0; 2379 } 2380 2381 static void kvmclock_reset(struct kvm_vcpu *vcpu) 2382 { 2383 vcpu->arch.pv_time_enabled = false; 2384 } 2385 2386 static void kvm_vcpu_flush_tlb(struct kvm_vcpu *vcpu, bool invalidate_gpa) 2387 { 2388 ++vcpu->stat.tlb_flush; 2389 kvm_x86_ops->tlb_flush(vcpu, invalidate_gpa); 2390 } 2391 2392 static void record_steal_time(struct kvm_vcpu *vcpu) 2393 { 2394 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED)) 2395 return; 2396 2397 if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime, 2398 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time)))) 2399 return; 2400 2401 /* 2402 * Doing a TLB flush here, on the guest's behalf, can avoid 2403 * expensive IPIs. 2404 */ 2405 if (xchg(&vcpu->arch.st.steal.preempted, 0) & KVM_VCPU_FLUSH_TLB) 2406 kvm_vcpu_flush_tlb(vcpu, false); 2407 2408 if (vcpu->arch.st.steal.version & 1) 2409 vcpu->arch.st.steal.version += 1; /* first time write, random junk */ 2410 2411 vcpu->arch.st.steal.version += 1; 2412 2413 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime, 2414 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time)); 2415 2416 smp_wmb(); 2417 2418 vcpu->arch.st.steal.steal += current->sched_info.run_delay - 2419 vcpu->arch.st.last_steal; 2420 vcpu->arch.st.last_steal = current->sched_info.run_delay; 2421 2422 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime, 2423 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time)); 2424 2425 smp_wmb(); 2426 2427 vcpu->arch.st.steal.version += 1; 2428 2429 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime, 2430 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time)); 2431 } 2432 2433 int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info) 2434 { 2435 bool pr = false; 2436 u32 msr = msr_info->index; 2437 u64 data = msr_info->data; 2438 2439 switch (msr) { 2440 case MSR_AMD64_NB_CFG: 2441 case MSR_IA32_UCODE_WRITE: 2442 case MSR_VM_HSAVE_PA: 2443 case MSR_AMD64_PATCH_LOADER: 2444 case MSR_AMD64_BU_CFG2: 2445 case MSR_AMD64_DC_CFG: 2446 case MSR_F15H_EX_CFG: 2447 break; 2448 2449 case MSR_IA32_UCODE_REV: 2450 if (msr_info->host_initiated) 2451 vcpu->arch.microcode_version = data; 2452 break; 2453 case MSR_IA32_ARCH_CAPABILITIES: 2454 if (!msr_info->host_initiated) 2455 return 1; 2456 vcpu->arch.arch_capabilities = data; 2457 break; 2458 case MSR_EFER: 2459 return set_efer(vcpu, data); 2460 case MSR_K7_HWCR: 2461 data &= ~(u64)0x40; /* ignore flush filter disable */ 2462 data &= ~(u64)0x100; /* ignore ignne emulation enable */ 2463 data &= ~(u64)0x8; /* ignore TLB cache disable */ 2464 data &= ~(u64)0x40000; /* ignore Mc status write enable */ 2465 if (data != 0) { 2466 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n", 2467 data); 2468 return 1; 2469 } 2470 break; 2471 case MSR_FAM10H_MMIO_CONF_BASE: 2472 if (data != 0) { 2473 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: " 2474 "0x%llx\n", data); 2475 return 1; 2476 } 2477 break; 2478 case MSR_IA32_DEBUGCTLMSR: 2479 if (!data) { 2480 /* We support the non-activated case already */ 2481 break; 2482 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) { 2483 /* Values other than LBR and BTF are vendor-specific, 2484 thus reserved and should throw a #GP */ 2485 return 1; 2486 } 2487 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n", 2488 __func__, data); 2489 break; 2490 case 0x200 ... 0x2ff: 2491 return kvm_mtrr_set_msr(vcpu, msr, data); 2492 case MSR_IA32_APICBASE: 2493 return kvm_set_apic_base(vcpu, msr_info); 2494 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff: 2495 return kvm_x2apic_msr_write(vcpu, msr, data); 2496 case MSR_IA32_TSCDEADLINE: 2497 kvm_set_lapic_tscdeadline_msr(vcpu, data); 2498 break; 2499 case MSR_IA32_TSC_ADJUST: 2500 if (guest_cpuid_has(vcpu, X86_FEATURE_TSC_ADJUST)) { 2501 if (!msr_info->host_initiated) { 2502 s64 adj = data - vcpu->arch.ia32_tsc_adjust_msr; 2503 adjust_tsc_offset_guest(vcpu, adj); 2504 } 2505 vcpu->arch.ia32_tsc_adjust_msr = data; 2506 } 2507 break; 2508 case MSR_IA32_MISC_ENABLE: 2509 vcpu->arch.ia32_misc_enable_msr = data; 2510 break; 2511 case MSR_IA32_SMBASE: 2512 if (!msr_info->host_initiated) 2513 return 1; 2514 vcpu->arch.smbase = data; 2515 break; 2516 case MSR_IA32_TSC: 2517 kvm_write_tsc(vcpu, msr_info); 2518 break; 2519 case MSR_SMI_COUNT: 2520 if (!msr_info->host_initiated) 2521 return 1; 2522 vcpu->arch.smi_count = data; 2523 break; 2524 case MSR_KVM_WALL_CLOCK_NEW: 2525 case MSR_KVM_WALL_CLOCK: 2526 vcpu->kvm->arch.wall_clock = data; 2527 kvm_write_wall_clock(vcpu->kvm, data); 2528 break; 2529 case MSR_KVM_SYSTEM_TIME_NEW: 2530 case MSR_KVM_SYSTEM_TIME: { 2531 struct kvm_arch *ka = &vcpu->kvm->arch; 2532 2533 kvmclock_reset(vcpu); 2534 2535 if (vcpu->vcpu_id == 0 && !msr_info->host_initiated) { 2536 bool tmp = (msr == MSR_KVM_SYSTEM_TIME); 2537 2538 if (ka->boot_vcpu_runs_old_kvmclock != tmp) 2539 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu); 2540 2541 ka->boot_vcpu_runs_old_kvmclock = tmp; 2542 } 2543 2544 vcpu->arch.time = data; 2545 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu); 2546 2547 /* we verify if the enable bit is set... */ 2548 if (!(data & 1)) 2549 break; 2550 2551 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, 2552 &vcpu->arch.pv_time, data & ~1ULL, 2553 sizeof(struct pvclock_vcpu_time_info))) 2554 vcpu->arch.pv_time_enabled = false; 2555 else 2556 vcpu->arch.pv_time_enabled = true; 2557 2558 break; 2559 } 2560 case MSR_KVM_ASYNC_PF_EN: 2561 if (kvm_pv_enable_async_pf(vcpu, data)) 2562 return 1; 2563 break; 2564 case MSR_KVM_STEAL_TIME: 2565 2566 if (unlikely(!sched_info_on())) 2567 return 1; 2568 2569 if (data & KVM_STEAL_RESERVED_MASK) 2570 return 1; 2571 2572 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime, 2573 data & KVM_STEAL_VALID_BITS, 2574 sizeof(struct kvm_steal_time))) 2575 return 1; 2576 2577 vcpu->arch.st.msr_val = data; 2578 2579 if (!(data & KVM_MSR_ENABLED)) 2580 break; 2581 2582 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu); 2583 2584 break; 2585 case MSR_KVM_PV_EOI_EN: 2586 if (kvm_lapic_enable_pv_eoi(vcpu, data, sizeof(u8))) 2587 return 1; 2588 break; 2589 2590 case MSR_IA32_MCG_CTL: 2591 case MSR_IA32_MCG_STATUS: 2592 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1: 2593 return set_msr_mce(vcpu, msr_info); 2594 2595 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3: 2596 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1: 2597 pr = true; /* fall through */ 2598 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3: 2599 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1: 2600 if (kvm_pmu_is_valid_msr(vcpu, msr)) 2601 return kvm_pmu_set_msr(vcpu, msr_info); 2602 2603 if (pr || data != 0) 2604 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: " 2605 "0x%x data 0x%llx\n", msr, data); 2606 break; 2607 case MSR_K7_CLK_CTL: 2608 /* 2609 * Ignore all writes to this no longer documented MSR. 2610 * Writes are only relevant for old K7 processors, 2611 * all pre-dating SVM, but a recommended workaround from 2612 * AMD for these chips. It is possible to specify the 2613 * affected processor models on the command line, hence 2614 * the need to ignore the workaround. 2615 */ 2616 break; 2617 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15: 2618 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4: 2619 case HV_X64_MSR_CRASH_CTL: 2620 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT: 2621 case HV_X64_MSR_REENLIGHTENMENT_CONTROL: 2622 case HV_X64_MSR_TSC_EMULATION_CONTROL: 2623 case HV_X64_MSR_TSC_EMULATION_STATUS: 2624 return kvm_hv_set_msr_common(vcpu, msr, data, 2625 msr_info->host_initiated); 2626 case MSR_IA32_BBL_CR_CTL3: 2627 /* Drop writes to this legacy MSR -- see rdmsr 2628 * counterpart for further detail. 2629 */ 2630 if (report_ignored_msrs) 2631 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data 0x%llx\n", 2632 msr, data); 2633 break; 2634 case MSR_AMD64_OSVW_ID_LENGTH: 2635 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW)) 2636 return 1; 2637 vcpu->arch.osvw.length = data; 2638 break; 2639 case MSR_AMD64_OSVW_STATUS: 2640 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW)) 2641 return 1; 2642 vcpu->arch.osvw.status = data; 2643 break; 2644 case MSR_PLATFORM_INFO: 2645 if (!msr_info->host_initiated || 2646 (!(data & MSR_PLATFORM_INFO_CPUID_FAULT) && 2647 cpuid_fault_enabled(vcpu))) 2648 return 1; 2649 vcpu->arch.msr_platform_info = data; 2650 break; 2651 case MSR_MISC_FEATURES_ENABLES: 2652 if (data & ~MSR_MISC_FEATURES_ENABLES_CPUID_FAULT || 2653 (data & MSR_MISC_FEATURES_ENABLES_CPUID_FAULT && 2654 !supports_cpuid_fault(vcpu))) 2655 return 1; 2656 vcpu->arch.msr_misc_features_enables = data; 2657 break; 2658 default: 2659 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr)) 2660 return xen_hvm_config(vcpu, data); 2661 if (kvm_pmu_is_valid_msr(vcpu, msr)) 2662 return kvm_pmu_set_msr(vcpu, msr_info); 2663 if (!ignore_msrs) { 2664 vcpu_debug_ratelimited(vcpu, "unhandled wrmsr: 0x%x data 0x%llx\n", 2665 msr, data); 2666 return 1; 2667 } else { 2668 if (report_ignored_msrs) 2669 vcpu_unimpl(vcpu, 2670 "ignored wrmsr: 0x%x data 0x%llx\n", 2671 msr, data); 2672 break; 2673 } 2674 } 2675 return 0; 2676 } 2677 EXPORT_SYMBOL_GPL(kvm_set_msr_common); 2678 2679 2680 /* 2681 * Reads an msr value (of 'msr_index') into 'pdata'. 2682 * Returns 0 on success, non-0 otherwise. 2683 * Assumes vcpu_load() was already called. 2684 */ 2685 int kvm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr) 2686 { 2687 return kvm_x86_ops->get_msr(vcpu, msr); 2688 } 2689 EXPORT_SYMBOL_GPL(kvm_get_msr); 2690 2691 static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata, bool host) 2692 { 2693 u64 data; 2694 u64 mcg_cap = vcpu->arch.mcg_cap; 2695 unsigned bank_num = mcg_cap & 0xff; 2696 2697 switch (msr) { 2698 case MSR_IA32_P5_MC_ADDR: 2699 case MSR_IA32_P5_MC_TYPE: 2700 data = 0; 2701 break; 2702 case MSR_IA32_MCG_CAP: 2703 data = vcpu->arch.mcg_cap; 2704 break; 2705 case MSR_IA32_MCG_CTL: 2706 if (!(mcg_cap & MCG_CTL_P) && !host) 2707 return 1; 2708 data = vcpu->arch.mcg_ctl; 2709 break; 2710 case MSR_IA32_MCG_STATUS: 2711 data = vcpu->arch.mcg_status; 2712 break; 2713 default: 2714 if (msr >= MSR_IA32_MC0_CTL && 2715 msr < MSR_IA32_MCx_CTL(bank_num)) { 2716 u32 offset = msr - MSR_IA32_MC0_CTL; 2717 data = vcpu->arch.mce_banks[offset]; 2718 break; 2719 } 2720 return 1; 2721 } 2722 *pdata = data; 2723 return 0; 2724 } 2725 2726 int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info) 2727 { 2728 switch (msr_info->index) { 2729 case MSR_IA32_PLATFORM_ID: 2730 case MSR_IA32_EBL_CR_POWERON: 2731 case MSR_IA32_DEBUGCTLMSR: 2732 case MSR_IA32_LASTBRANCHFROMIP: 2733 case MSR_IA32_LASTBRANCHTOIP: 2734 case MSR_IA32_LASTINTFROMIP: 2735 case MSR_IA32_LASTINTTOIP: 2736 case MSR_K8_SYSCFG: 2737 case MSR_K8_TSEG_ADDR: 2738 case MSR_K8_TSEG_MASK: 2739 case MSR_K7_HWCR: 2740 case MSR_VM_HSAVE_PA: 2741 case MSR_K8_INT_PENDING_MSG: 2742 case MSR_AMD64_NB_CFG: 2743 case MSR_FAM10H_MMIO_CONF_BASE: 2744 case MSR_AMD64_BU_CFG2: 2745 case MSR_IA32_PERF_CTL: 2746 case MSR_AMD64_DC_CFG: 2747 case MSR_F15H_EX_CFG: 2748 msr_info->data = 0; 2749 break; 2750 case MSR_F15H_PERF_CTL0 ... MSR_F15H_PERF_CTR5: 2751 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3: 2752 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3: 2753 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1: 2754 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1: 2755 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index)) 2756 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data); 2757 msr_info->data = 0; 2758 break; 2759 case MSR_IA32_UCODE_REV: 2760 msr_info->data = vcpu->arch.microcode_version; 2761 break; 2762 case MSR_IA32_ARCH_CAPABILITIES: 2763 if (!msr_info->host_initiated && 2764 !guest_cpuid_has(vcpu, X86_FEATURE_ARCH_CAPABILITIES)) 2765 return 1; 2766 msr_info->data = vcpu->arch.arch_capabilities; 2767 break; 2768 case MSR_IA32_TSC: 2769 msr_info->data = kvm_scale_tsc(vcpu, rdtsc()) + vcpu->arch.tsc_offset; 2770 break; 2771 case MSR_MTRRcap: 2772 case 0x200 ... 0x2ff: 2773 return kvm_mtrr_get_msr(vcpu, msr_info->index, &msr_info->data); 2774 case 0xcd: /* fsb frequency */ 2775 msr_info->data = 3; 2776 break; 2777 /* 2778 * MSR_EBC_FREQUENCY_ID 2779 * Conservative value valid for even the basic CPU models. 2780 * Models 0,1: 000 in bits 23:21 indicating a bus speed of 2781 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz, 2782 * and 266MHz for model 3, or 4. Set Core Clock 2783 * Frequency to System Bus Frequency Ratio to 1 (bits 2784 * 31:24) even though these are only valid for CPU 2785 * models > 2, however guests may end up dividing or 2786 * multiplying by zero otherwise. 2787 */ 2788 case MSR_EBC_FREQUENCY_ID: 2789 msr_info->data = 1 << 24; 2790 break; 2791 case MSR_IA32_APICBASE: 2792 msr_info->data = kvm_get_apic_base(vcpu); 2793 break; 2794 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff: 2795 return kvm_x2apic_msr_read(vcpu, msr_info->index, &msr_info->data); 2796 break; 2797 case MSR_IA32_TSCDEADLINE: 2798 msr_info->data = kvm_get_lapic_tscdeadline_msr(vcpu); 2799 break; 2800 case MSR_IA32_TSC_ADJUST: 2801 msr_info->data = (u64)vcpu->arch.ia32_tsc_adjust_msr; 2802 break; 2803 case MSR_IA32_MISC_ENABLE: 2804 msr_info->data = vcpu->arch.ia32_misc_enable_msr; 2805 break; 2806 case MSR_IA32_SMBASE: 2807 if (!msr_info->host_initiated) 2808 return 1; 2809 msr_info->data = vcpu->arch.smbase; 2810 break; 2811 case MSR_SMI_COUNT: 2812 msr_info->data = vcpu->arch.smi_count; 2813 break; 2814 case MSR_IA32_PERF_STATUS: 2815 /* TSC increment by tick */ 2816 msr_info->data = 1000ULL; 2817 /* CPU multiplier */ 2818 msr_info->data |= (((uint64_t)4ULL) << 40); 2819 break; 2820 case MSR_EFER: 2821 msr_info->data = vcpu->arch.efer; 2822 break; 2823 case MSR_KVM_WALL_CLOCK: 2824 case MSR_KVM_WALL_CLOCK_NEW: 2825 msr_info->data = vcpu->kvm->arch.wall_clock; 2826 break; 2827 case MSR_KVM_SYSTEM_TIME: 2828 case MSR_KVM_SYSTEM_TIME_NEW: 2829 msr_info->data = vcpu->arch.time; 2830 break; 2831 case MSR_KVM_ASYNC_PF_EN: 2832 msr_info->data = vcpu->arch.apf.msr_val; 2833 break; 2834 case MSR_KVM_STEAL_TIME: 2835 msr_info->data = vcpu->arch.st.msr_val; 2836 break; 2837 case MSR_KVM_PV_EOI_EN: 2838 msr_info->data = vcpu->arch.pv_eoi.msr_val; 2839 break; 2840 case MSR_IA32_P5_MC_ADDR: 2841 case MSR_IA32_P5_MC_TYPE: 2842 case MSR_IA32_MCG_CAP: 2843 case MSR_IA32_MCG_CTL: 2844 case MSR_IA32_MCG_STATUS: 2845 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1: 2846 return get_msr_mce(vcpu, msr_info->index, &msr_info->data, 2847 msr_info->host_initiated); 2848 case MSR_K7_CLK_CTL: 2849 /* 2850 * Provide expected ramp-up count for K7. All other 2851 * are set to zero, indicating minimum divisors for 2852 * every field. 2853 * 2854 * This prevents guest kernels on AMD host with CPU 2855 * type 6, model 8 and higher from exploding due to 2856 * the rdmsr failing. 2857 */ 2858 msr_info->data = 0x20000000; 2859 break; 2860 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15: 2861 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4: 2862 case HV_X64_MSR_CRASH_CTL: 2863 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT: 2864 case HV_X64_MSR_REENLIGHTENMENT_CONTROL: 2865 case HV_X64_MSR_TSC_EMULATION_CONTROL: 2866 case HV_X64_MSR_TSC_EMULATION_STATUS: 2867 return kvm_hv_get_msr_common(vcpu, 2868 msr_info->index, &msr_info->data, 2869 msr_info->host_initiated); 2870 break; 2871 case MSR_IA32_BBL_CR_CTL3: 2872 /* This legacy MSR exists but isn't fully documented in current 2873 * silicon. It is however accessed by winxp in very narrow 2874 * scenarios where it sets bit #19, itself documented as 2875 * a "reserved" bit. Best effort attempt to source coherent 2876 * read data here should the balance of the register be 2877 * interpreted by the guest: 2878 * 2879 * L2 cache control register 3: 64GB range, 256KB size, 2880 * enabled, latency 0x1, configured 2881 */ 2882 msr_info->data = 0xbe702111; 2883 break; 2884 case MSR_AMD64_OSVW_ID_LENGTH: 2885 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW)) 2886 return 1; 2887 msr_info->data = vcpu->arch.osvw.length; 2888 break; 2889 case MSR_AMD64_OSVW_STATUS: 2890 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW)) 2891 return 1; 2892 msr_info->data = vcpu->arch.osvw.status; 2893 break; 2894 case MSR_PLATFORM_INFO: 2895 if (!msr_info->host_initiated && 2896 !vcpu->kvm->arch.guest_can_read_msr_platform_info) 2897 return 1; 2898 msr_info->data = vcpu->arch.msr_platform_info; 2899 break; 2900 case MSR_MISC_FEATURES_ENABLES: 2901 msr_info->data = vcpu->arch.msr_misc_features_enables; 2902 break; 2903 default: 2904 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index)) 2905 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data); 2906 if (!ignore_msrs) { 2907 vcpu_debug_ratelimited(vcpu, "unhandled rdmsr: 0x%x\n", 2908 msr_info->index); 2909 return 1; 2910 } else { 2911 if (report_ignored_msrs) 2912 vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n", 2913 msr_info->index); 2914 msr_info->data = 0; 2915 } 2916 break; 2917 } 2918 return 0; 2919 } 2920 EXPORT_SYMBOL_GPL(kvm_get_msr_common); 2921 2922 /* 2923 * Read or write a bunch of msrs. All parameters are kernel addresses. 2924 * 2925 * @return number of msrs set successfully. 2926 */ 2927 static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs, 2928 struct kvm_msr_entry *entries, 2929 int (*do_msr)(struct kvm_vcpu *vcpu, 2930 unsigned index, u64 *data)) 2931 { 2932 int i; 2933 2934 for (i = 0; i < msrs->nmsrs; ++i) 2935 if (do_msr(vcpu, entries[i].index, &entries[i].data)) 2936 break; 2937 2938 return i; 2939 } 2940 2941 /* 2942 * Read or write a bunch of msrs. Parameters are user addresses. 2943 * 2944 * @return number of msrs set successfully. 2945 */ 2946 static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs, 2947 int (*do_msr)(struct kvm_vcpu *vcpu, 2948 unsigned index, u64 *data), 2949 int writeback) 2950 { 2951 struct kvm_msrs msrs; 2952 struct kvm_msr_entry *entries; 2953 int r, n; 2954 unsigned size; 2955 2956 r = -EFAULT; 2957 if (copy_from_user(&msrs, user_msrs, sizeof(msrs))) 2958 goto out; 2959 2960 r = -E2BIG; 2961 if (msrs.nmsrs >= MAX_IO_MSRS) 2962 goto out; 2963 2964 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs; 2965 entries = memdup_user(user_msrs->entries, size); 2966 if (IS_ERR(entries)) { 2967 r = PTR_ERR(entries); 2968 goto out; 2969 } 2970 2971 r = n = __msr_io(vcpu, &msrs, entries, do_msr); 2972 if (r < 0) 2973 goto out_free; 2974 2975 r = -EFAULT; 2976 if (writeback && copy_to_user(user_msrs->entries, entries, size)) 2977 goto out_free; 2978 2979 r = n; 2980 2981 out_free: 2982 kfree(entries); 2983 out: 2984 return r; 2985 } 2986 2987 static inline bool kvm_can_mwait_in_guest(void) 2988 { 2989 return boot_cpu_has(X86_FEATURE_MWAIT) && 2990 !boot_cpu_has_bug(X86_BUG_MONITOR) && 2991 boot_cpu_has(X86_FEATURE_ARAT); 2992 } 2993 2994 int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext) 2995 { 2996 int r = 0; 2997 2998 switch (ext) { 2999 case KVM_CAP_IRQCHIP: 3000 case KVM_CAP_HLT: 3001 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL: 3002 case KVM_CAP_SET_TSS_ADDR: 3003 case KVM_CAP_EXT_CPUID: 3004 case KVM_CAP_EXT_EMUL_CPUID: 3005 case KVM_CAP_CLOCKSOURCE: 3006 case KVM_CAP_PIT: 3007 case KVM_CAP_NOP_IO_DELAY: 3008 case KVM_CAP_MP_STATE: 3009 case KVM_CAP_SYNC_MMU: 3010 case KVM_CAP_USER_NMI: 3011 case KVM_CAP_REINJECT_CONTROL: 3012 case KVM_CAP_IRQ_INJECT_STATUS: 3013 case KVM_CAP_IOEVENTFD: 3014 case KVM_CAP_IOEVENTFD_NO_LENGTH: 3015 case KVM_CAP_PIT2: 3016 case KVM_CAP_PIT_STATE2: 3017 case KVM_CAP_SET_IDENTITY_MAP_ADDR: 3018 case KVM_CAP_XEN_HVM: 3019 case KVM_CAP_VCPU_EVENTS: 3020 case KVM_CAP_HYPERV: 3021 case KVM_CAP_HYPERV_VAPIC: 3022 case KVM_CAP_HYPERV_SPIN: 3023 case KVM_CAP_HYPERV_SYNIC: 3024 case KVM_CAP_HYPERV_SYNIC2: 3025 case KVM_CAP_HYPERV_VP_INDEX: 3026 case KVM_CAP_HYPERV_EVENTFD: 3027 case KVM_CAP_HYPERV_TLBFLUSH: 3028 case KVM_CAP_HYPERV_SEND_IPI: 3029 case KVM_CAP_HYPERV_ENLIGHTENED_VMCS: 3030 case KVM_CAP_HYPERV_CPUID: 3031 case KVM_CAP_PCI_SEGMENT: 3032 case KVM_CAP_DEBUGREGS: 3033 case KVM_CAP_X86_ROBUST_SINGLESTEP: 3034 case KVM_CAP_XSAVE: 3035 case KVM_CAP_ASYNC_PF: 3036 case KVM_CAP_GET_TSC_KHZ: 3037 case KVM_CAP_KVMCLOCK_CTRL: 3038 case KVM_CAP_READONLY_MEM: 3039 case KVM_CAP_HYPERV_TIME: 3040 case KVM_CAP_IOAPIC_POLARITY_IGNORED: 3041 case KVM_CAP_TSC_DEADLINE_TIMER: 3042 case KVM_CAP_DISABLE_QUIRKS: 3043 case KVM_CAP_SET_BOOT_CPU_ID: 3044 case KVM_CAP_SPLIT_IRQCHIP: 3045 case KVM_CAP_IMMEDIATE_EXIT: 3046 case KVM_CAP_GET_MSR_FEATURES: 3047 case KVM_CAP_MSR_PLATFORM_INFO: 3048 case KVM_CAP_EXCEPTION_PAYLOAD: 3049 r = 1; 3050 break; 3051 case KVM_CAP_SYNC_REGS: 3052 r = KVM_SYNC_X86_VALID_FIELDS; 3053 break; 3054 case KVM_CAP_ADJUST_CLOCK: 3055 r = KVM_CLOCK_TSC_STABLE; 3056 break; 3057 case KVM_CAP_X86_DISABLE_EXITS: 3058 r |= KVM_X86_DISABLE_EXITS_HLT | KVM_X86_DISABLE_EXITS_PAUSE; 3059 if(kvm_can_mwait_in_guest()) 3060 r |= KVM_X86_DISABLE_EXITS_MWAIT; 3061 break; 3062 case KVM_CAP_X86_SMM: 3063 /* SMBASE is usually relocated above 1M on modern chipsets, 3064 * and SMM handlers might indeed rely on 4G segment limits, 3065 * so do not report SMM to be available if real mode is 3066 * emulated via vm86 mode. Still, do not go to great lengths 3067 * to avoid userspace's usage of the feature, because it is a 3068 * fringe case that is not enabled except via specific settings 3069 * of the module parameters. 3070 */ 3071 r = kvm_x86_ops->has_emulated_msr(MSR_IA32_SMBASE); 3072 break; 3073 case KVM_CAP_VAPIC: 3074 r = !kvm_x86_ops->cpu_has_accelerated_tpr(); 3075 break; 3076 case KVM_CAP_NR_VCPUS: 3077 r = KVM_SOFT_MAX_VCPUS; 3078 break; 3079 case KVM_CAP_MAX_VCPUS: 3080 r = KVM_MAX_VCPUS; 3081 break; 3082 case KVM_CAP_NR_MEMSLOTS: 3083 r = KVM_USER_MEM_SLOTS; 3084 break; 3085 case KVM_CAP_PV_MMU: /* obsolete */ 3086 r = 0; 3087 break; 3088 case KVM_CAP_MCE: 3089 r = KVM_MAX_MCE_BANKS; 3090 break; 3091 case KVM_CAP_XCRS: 3092 r = boot_cpu_has(X86_FEATURE_XSAVE); 3093 break; 3094 case KVM_CAP_TSC_CONTROL: 3095 r = kvm_has_tsc_control; 3096 break; 3097 case KVM_CAP_X2APIC_API: 3098 r = KVM_X2APIC_API_VALID_FLAGS; 3099 break; 3100 case KVM_CAP_NESTED_STATE: 3101 r = kvm_x86_ops->get_nested_state ? 3102 kvm_x86_ops->get_nested_state(NULL, NULL, 0) : 0; 3103 break; 3104 default: 3105 break; 3106 } 3107 return r; 3108 3109 } 3110 3111 long kvm_arch_dev_ioctl(struct file *filp, 3112 unsigned int ioctl, unsigned long arg) 3113 { 3114 void __user *argp = (void __user *)arg; 3115 long r; 3116 3117 switch (ioctl) { 3118 case KVM_GET_MSR_INDEX_LIST: { 3119 struct kvm_msr_list __user *user_msr_list = argp; 3120 struct kvm_msr_list msr_list; 3121 unsigned n; 3122 3123 r = -EFAULT; 3124 if (copy_from_user(&msr_list, user_msr_list, sizeof(msr_list))) 3125 goto out; 3126 n = msr_list.nmsrs; 3127 msr_list.nmsrs = num_msrs_to_save + num_emulated_msrs; 3128 if (copy_to_user(user_msr_list, &msr_list, sizeof(msr_list))) 3129 goto out; 3130 r = -E2BIG; 3131 if (n < msr_list.nmsrs) 3132 goto out; 3133 r = -EFAULT; 3134 if (copy_to_user(user_msr_list->indices, &msrs_to_save, 3135 num_msrs_to_save * sizeof(u32))) 3136 goto out; 3137 if (copy_to_user(user_msr_list->indices + num_msrs_to_save, 3138 &emulated_msrs, 3139 num_emulated_msrs * sizeof(u32))) 3140 goto out; 3141 r = 0; 3142 break; 3143 } 3144 case KVM_GET_SUPPORTED_CPUID: 3145 case KVM_GET_EMULATED_CPUID: { 3146 struct kvm_cpuid2 __user *cpuid_arg = argp; 3147 struct kvm_cpuid2 cpuid; 3148 3149 r = -EFAULT; 3150 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid))) 3151 goto out; 3152 3153 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries, 3154 ioctl); 3155 if (r) 3156 goto out; 3157 3158 r = -EFAULT; 3159 if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid))) 3160 goto out; 3161 r = 0; 3162 break; 3163 } 3164 case KVM_X86_GET_MCE_CAP_SUPPORTED: { 3165 r = -EFAULT; 3166 if (copy_to_user(argp, &kvm_mce_cap_supported, 3167 sizeof(kvm_mce_cap_supported))) 3168 goto out; 3169 r = 0; 3170 break; 3171 case KVM_GET_MSR_FEATURE_INDEX_LIST: { 3172 struct kvm_msr_list __user *user_msr_list = argp; 3173 struct kvm_msr_list msr_list; 3174 unsigned int n; 3175 3176 r = -EFAULT; 3177 if (copy_from_user(&msr_list, user_msr_list, sizeof(msr_list))) 3178 goto out; 3179 n = msr_list.nmsrs; 3180 msr_list.nmsrs = num_msr_based_features; 3181 if (copy_to_user(user_msr_list, &msr_list, sizeof(msr_list))) 3182 goto out; 3183 r = -E2BIG; 3184 if (n < msr_list.nmsrs) 3185 goto out; 3186 r = -EFAULT; 3187 if (copy_to_user(user_msr_list->indices, &msr_based_features, 3188 num_msr_based_features * sizeof(u32))) 3189 goto out; 3190 r = 0; 3191 break; 3192 } 3193 case KVM_GET_MSRS: 3194 r = msr_io(NULL, argp, do_get_msr_feature, 1); 3195 break; 3196 } 3197 default: 3198 r = -EINVAL; 3199 } 3200 out: 3201 return r; 3202 } 3203 3204 static void wbinvd_ipi(void *garbage) 3205 { 3206 wbinvd(); 3207 } 3208 3209 static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu) 3210 { 3211 return kvm_arch_has_noncoherent_dma(vcpu->kvm); 3212 } 3213 3214 void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu) 3215 { 3216 /* Address WBINVD may be executed by guest */ 3217 if (need_emulate_wbinvd(vcpu)) { 3218 if (kvm_x86_ops->has_wbinvd_exit()) 3219 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask); 3220 else if (vcpu->cpu != -1 && vcpu->cpu != cpu) 3221 smp_call_function_single(vcpu->cpu, 3222 wbinvd_ipi, NULL, 1); 3223 } 3224 3225 kvm_x86_ops->vcpu_load(vcpu, cpu); 3226 3227 /* Apply any externally detected TSC adjustments (due to suspend) */ 3228 if (unlikely(vcpu->arch.tsc_offset_adjustment)) { 3229 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment); 3230 vcpu->arch.tsc_offset_adjustment = 0; 3231 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 3232 } 3233 3234 if (unlikely(vcpu->cpu != cpu) || kvm_check_tsc_unstable()) { 3235 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 : 3236 rdtsc() - vcpu->arch.last_host_tsc; 3237 if (tsc_delta < 0) 3238 mark_tsc_unstable("KVM discovered backwards TSC"); 3239 3240 if (kvm_check_tsc_unstable()) { 3241 u64 offset = kvm_compute_tsc_offset(vcpu, 3242 vcpu->arch.last_guest_tsc); 3243 kvm_vcpu_write_tsc_offset(vcpu, offset); 3244 vcpu->arch.tsc_catchup = 1; 3245 } 3246 3247 if (kvm_lapic_hv_timer_in_use(vcpu)) 3248 kvm_lapic_restart_hv_timer(vcpu); 3249 3250 /* 3251 * On a host with synchronized TSC, there is no need to update 3252 * kvmclock on vcpu->cpu migration 3253 */ 3254 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1) 3255 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu); 3256 if (vcpu->cpu != cpu) 3257 kvm_make_request(KVM_REQ_MIGRATE_TIMER, vcpu); 3258 vcpu->cpu = cpu; 3259 } 3260 3261 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu); 3262 } 3263 3264 static void kvm_steal_time_set_preempted(struct kvm_vcpu *vcpu) 3265 { 3266 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED)) 3267 return; 3268 3269 vcpu->arch.st.steal.preempted = KVM_VCPU_PREEMPTED; 3270 3271 kvm_write_guest_offset_cached(vcpu->kvm, &vcpu->arch.st.stime, 3272 &vcpu->arch.st.steal.preempted, 3273 offsetof(struct kvm_steal_time, preempted), 3274 sizeof(vcpu->arch.st.steal.preempted)); 3275 } 3276 3277 void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu) 3278 { 3279 int idx; 3280 3281 if (vcpu->preempted) 3282 vcpu->arch.preempted_in_kernel = !kvm_x86_ops->get_cpl(vcpu); 3283 3284 /* 3285 * Disable page faults because we're in atomic context here. 3286 * kvm_write_guest_offset_cached() would call might_fault() 3287 * that relies on pagefault_disable() to tell if there's a 3288 * bug. NOTE: the write to guest memory may not go through if 3289 * during postcopy live migration or if there's heavy guest 3290 * paging. 3291 */ 3292 pagefault_disable(); 3293 /* 3294 * kvm_memslots() will be called by 3295 * kvm_write_guest_offset_cached() so take the srcu lock. 3296 */ 3297 idx = srcu_read_lock(&vcpu->kvm->srcu); 3298 kvm_steal_time_set_preempted(vcpu); 3299 srcu_read_unlock(&vcpu->kvm->srcu, idx); 3300 pagefault_enable(); 3301 kvm_x86_ops->vcpu_put(vcpu); 3302 vcpu->arch.last_host_tsc = rdtsc(); 3303 /* 3304 * If userspace has set any breakpoints or watchpoints, dr6 is restored 3305 * on every vmexit, but if not, we might have a stale dr6 from the 3306 * guest. do_debug expects dr6 to be cleared after it runs, do the same. 3307 */ 3308 set_debugreg(0, 6); 3309 } 3310 3311 static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu, 3312 struct kvm_lapic_state *s) 3313 { 3314 if (vcpu->arch.apicv_active) 3315 kvm_x86_ops->sync_pir_to_irr(vcpu); 3316 3317 return kvm_apic_get_state(vcpu, s); 3318 } 3319 3320 static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu, 3321 struct kvm_lapic_state *s) 3322 { 3323 int r; 3324 3325 r = kvm_apic_set_state(vcpu, s); 3326 if (r) 3327 return r; 3328 update_cr8_intercept(vcpu); 3329 3330 return 0; 3331 } 3332 3333 static int kvm_cpu_accept_dm_intr(struct kvm_vcpu *vcpu) 3334 { 3335 return (!lapic_in_kernel(vcpu) || 3336 kvm_apic_accept_pic_intr(vcpu)); 3337 } 3338 3339 /* 3340 * if userspace requested an interrupt window, check that the 3341 * interrupt window is open. 3342 * 3343 * No need to exit to userspace if we already have an interrupt queued. 3344 */ 3345 static int kvm_vcpu_ready_for_interrupt_injection(struct kvm_vcpu *vcpu) 3346 { 3347 return kvm_arch_interrupt_allowed(vcpu) && 3348 !kvm_cpu_has_interrupt(vcpu) && 3349 !kvm_event_needs_reinjection(vcpu) && 3350 kvm_cpu_accept_dm_intr(vcpu); 3351 } 3352 3353 static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu, 3354 struct kvm_interrupt *irq) 3355 { 3356 if (irq->irq >= KVM_NR_INTERRUPTS) 3357 return -EINVAL; 3358 3359 if (!irqchip_in_kernel(vcpu->kvm)) { 3360 kvm_queue_interrupt(vcpu, irq->irq, false); 3361 kvm_make_request(KVM_REQ_EVENT, vcpu); 3362 return 0; 3363 } 3364 3365 /* 3366 * With in-kernel LAPIC, we only use this to inject EXTINT, so 3367 * fail for in-kernel 8259. 3368 */ 3369 if (pic_in_kernel(vcpu->kvm)) 3370 return -ENXIO; 3371 3372 if (vcpu->arch.pending_external_vector != -1) 3373 return -EEXIST; 3374 3375 vcpu->arch.pending_external_vector = irq->irq; 3376 kvm_make_request(KVM_REQ_EVENT, vcpu); 3377 return 0; 3378 } 3379 3380 static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu) 3381 { 3382 kvm_inject_nmi(vcpu); 3383 3384 return 0; 3385 } 3386 3387 static int kvm_vcpu_ioctl_smi(struct kvm_vcpu *vcpu) 3388 { 3389 kvm_make_request(KVM_REQ_SMI, vcpu); 3390 3391 return 0; 3392 } 3393 3394 static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu, 3395 struct kvm_tpr_access_ctl *tac) 3396 { 3397 if (tac->flags) 3398 return -EINVAL; 3399 vcpu->arch.tpr_access_reporting = !!tac->enabled; 3400 return 0; 3401 } 3402 3403 static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu, 3404 u64 mcg_cap) 3405 { 3406 int r; 3407 unsigned bank_num = mcg_cap & 0xff, bank; 3408 3409 r = -EINVAL; 3410 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS) 3411 goto out; 3412 if (mcg_cap & ~(kvm_mce_cap_supported | 0xff | 0xff0000)) 3413 goto out; 3414 r = 0; 3415 vcpu->arch.mcg_cap = mcg_cap; 3416 /* Init IA32_MCG_CTL to all 1s */ 3417 if (mcg_cap & MCG_CTL_P) 3418 vcpu->arch.mcg_ctl = ~(u64)0; 3419 /* Init IA32_MCi_CTL to all 1s */ 3420 for (bank = 0; bank < bank_num; bank++) 3421 vcpu->arch.mce_banks[bank*4] = ~(u64)0; 3422 3423 if (kvm_x86_ops->setup_mce) 3424 kvm_x86_ops->setup_mce(vcpu); 3425 out: 3426 return r; 3427 } 3428 3429 static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu, 3430 struct kvm_x86_mce *mce) 3431 { 3432 u64 mcg_cap = vcpu->arch.mcg_cap; 3433 unsigned bank_num = mcg_cap & 0xff; 3434 u64 *banks = vcpu->arch.mce_banks; 3435 3436 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL)) 3437 return -EINVAL; 3438 /* 3439 * if IA32_MCG_CTL is not all 1s, the uncorrected error 3440 * reporting is disabled 3441 */ 3442 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) && 3443 vcpu->arch.mcg_ctl != ~(u64)0) 3444 return 0; 3445 banks += 4 * mce->bank; 3446 /* 3447 * if IA32_MCi_CTL is not all 1s, the uncorrected error 3448 * reporting is disabled for the bank 3449 */ 3450 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0) 3451 return 0; 3452 if (mce->status & MCI_STATUS_UC) { 3453 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) || 3454 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) { 3455 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); 3456 return 0; 3457 } 3458 if (banks[1] & MCI_STATUS_VAL) 3459 mce->status |= MCI_STATUS_OVER; 3460 banks[2] = mce->addr; 3461 banks[3] = mce->misc; 3462 vcpu->arch.mcg_status = mce->mcg_status; 3463 banks[1] = mce->status; 3464 kvm_queue_exception(vcpu, MC_VECTOR); 3465 } else if (!(banks[1] & MCI_STATUS_VAL) 3466 || !(banks[1] & MCI_STATUS_UC)) { 3467 if (banks[1] & MCI_STATUS_VAL) 3468 mce->status |= MCI_STATUS_OVER; 3469 banks[2] = mce->addr; 3470 banks[3] = mce->misc; 3471 banks[1] = mce->status; 3472 } else 3473 banks[1] |= MCI_STATUS_OVER; 3474 return 0; 3475 } 3476 3477 static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu, 3478 struct kvm_vcpu_events *events) 3479 { 3480 process_nmi(vcpu); 3481 3482 /* 3483 * The API doesn't provide the instruction length for software 3484 * exceptions, so don't report them. As long as the guest RIP 3485 * isn't advanced, we should expect to encounter the exception 3486 * again. 3487 */ 3488 if (kvm_exception_is_soft(vcpu->arch.exception.nr)) { 3489 events->exception.injected = 0; 3490 events->exception.pending = 0; 3491 } else { 3492 events->exception.injected = vcpu->arch.exception.injected; 3493 events->exception.pending = vcpu->arch.exception.pending; 3494 /* 3495 * For ABI compatibility, deliberately conflate 3496 * pending and injected exceptions when 3497 * KVM_CAP_EXCEPTION_PAYLOAD isn't enabled. 3498 */ 3499 if (!vcpu->kvm->arch.exception_payload_enabled) 3500 events->exception.injected |= 3501 vcpu->arch.exception.pending; 3502 } 3503 events->exception.nr = vcpu->arch.exception.nr; 3504 events->exception.has_error_code = vcpu->arch.exception.has_error_code; 3505 events->exception.error_code = vcpu->arch.exception.error_code; 3506 events->exception_has_payload = vcpu->arch.exception.has_payload; 3507 events->exception_payload = vcpu->arch.exception.payload; 3508 3509 events->interrupt.injected = 3510 vcpu->arch.interrupt.injected && !vcpu->arch.interrupt.soft; 3511 events->interrupt.nr = vcpu->arch.interrupt.nr; 3512 events->interrupt.soft = 0; 3513 events->interrupt.shadow = kvm_x86_ops->get_interrupt_shadow(vcpu); 3514 3515 events->nmi.injected = vcpu->arch.nmi_injected; 3516 events->nmi.pending = vcpu->arch.nmi_pending != 0; 3517 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu); 3518 events->nmi.pad = 0; 3519 3520 events->sipi_vector = 0; /* never valid when reporting to user space */ 3521 3522 events->smi.smm = is_smm(vcpu); 3523 events->smi.pending = vcpu->arch.smi_pending; 3524 events->smi.smm_inside_nmi = 3525 !!(vcpu->arch.hflags & HF_SMM_INSIDE_NMI_MASK); 3526 events->smi.latched_init = kvm_lapic_latched_init(vcpu); 3527 3528 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING 3529 | KVM_VCPUEVENT_VALID_SHADOW 3530 | KVM_VCPUEVENT_VALID_SMM); 3531 if (vcpu->kvm->arch.exception_payload_enabled) 3532 events->flags |= KVM_VCPUEVENT_VALID_PAYLOAD; 3533 3534 memset(&events->reserved, 0, sizeof(events->reserved)); 3535 } 3536 3537 static void kvm_smm_changed(struct kvm_vcpu *vcpu); 3538 3539 static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu, 3540 struct kvm_vcpu_events *events) 3541 { 3542 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING 3543 | KVM_VCPUEVENT_VALID_SIPI_VECTOR 3544 | KVM_VCPUEVENT_VALID_SHADOW 3545 | KVM_VCPUEVENT_VALID_SMM 3546 | KVM_VCPUEVENT_VALID_PAYLOAD)) 3547 return -EINVAL; 3548 3549 if (events->flags & KVM_VCPUEVENT_VALID_PAYLOAD) { 3550 if (!vcpu->kvm->arch.exception_payload_enabled) 3551 return -EINVAL; 3552 if (events->exception.pending) 3553 events->exception.injected = 0; 3554 else 3555 events->exception_has_payload = 0; 3556 } else { 3557 events->exception.pending = 0; 3558 events->exception_has_payload = 0; 3559 } 3560 3561 if ((events->exception.injected || events->exception.pending) && 3562 (events->exception.nr > 31 || events->exception.nr == NMI_VECTOR)) 3563 return -EINVAL; 3564 3565 /* INITs are latched while in SMM */ 3566 if (events->flags & KVM_VCPUEVENT_VALID_SMM && 3567 (events->smi.smm || events->smi.pending) && 3568 vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) 3569 return -EINVAL; 3570 3571 process_nmi(vcpu); 3572 vcpu->arch.exception.injected = events->exception.injected; 3573 vcpu->arch.exception.pending = events->exception.pending; 3574 vcpu->arch.exception.nr = events->exception.nr; 3575 vcpu->arch.exception.has_error_code = events->exception.has_error_code; 3576 vcpu->arch.exception.error_code = events->exception.error_code; 3577 vcpu->arch.exception.has_payload = events->exception_has_payload; 3578 vcpu->arch.exception.payload = events->exception_payload; 3579 3580 vcpu->arch.interrupt.injected = events->interrupt.injected; 3581 vcpu->arch.interrupt.nr = events->interrupt.nr; 3582 vcpu->arch.interrupt.soft = events->interrupt.soft; 3583 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW) 3584 kvm_x86_ops->set_interrupt_shadow(vcpu, 3585 events->interrupt.shadow); 3586 3587 vcpu->arch.nmi_injected = events->nmi.injected; 3588 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING) 3589 vcpu->arch.nmi_pending = events->nmi.pending; 3590 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked); 3591 3592 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR && 3593 lapic_in_kernel(vcpu)) 3594 vcpu->arch.apic->sipi_vector = events->sipi_vector; 3595 3596 if (events->flags & KVM_VCPUEVENT_VALID_SMM) { 3597 if (!!(vcpu->arch.hflags & HF_SMM_MASK) != events->smi.smm) { 3598 if (events->smi.smm) 3599 vcpu->arch.hflags |= HF_SMM_MASK; 3600 else 3601 vcpu->arch.hflags &= ~HF_SMM_MASK; 3602 kvm_smm_changed(vcpu); 3603 } 3604 3605 vcpu->arch.smi_pending = events->smi.pending; 3606 3607 if (events->smi.smm) { 3608 if (events->smi.smm_inside_nmi) 3609 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK; 3610 else 3611 vcpu->arch.hflags &= ~HF_SMM_INSIDE_NMI_MASK; 3612 if (lapic_in_kernel(vcpu)) { 3613 if (events->smi.latched_init) 3614 set_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events); 3615 else 3616 clear_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events); 3617 } 3618 } 3619 } 3620 3621 kvm_make_request(KVM_REQ_EVENT, vcpu); 3622 3623 return 0; 3624 } 3625 3626 static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu, 3627 struct kvm_debugregs *dbgregs) 3628 { 3629 unsigned long val; 3630 3631 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db)); 3632 kvm_get_dr(vcpu, 6, &val); 3633 dbgregs->dr6 = val; 3634 dbgregs->dr7 = vcpu->arch.dr7; 3635 dbgregs->flags = 0; 3636 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved)); 3637 } 3638 3639 static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu, 3640 struct kvm_debugregs *dbgregs) 3641 { 3642 if (dbgregs->flags) 3643 return -EINVAL; 3644 3645 if (dbgregs->dr6 & ~0xffffffffull) 3646 return -EINVAL; 3647 if (dbgregs->dr7 & ~0xffffffffull) 3648 return -EINVAL; 3649 3650 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db)); 3651 kvm_update_dr0123(vcpu); 3652 vcpu->arch.dr6 = dbgregs->dr6; 3653 kvm_update_dr6(vcpu); 3654 vcpu->arch.dr7 = dbgregs->dr7; 3655 kvm_update_dr7(vcpu); 3656 3657 return 0; 3658 } 3659 3660 #define XSTATE_COMPACTION_ENABLED (1ULL << 63) 3661 3662 static void fill_xsave(u8 *dest, struct kvm_vcpu *vcpu) 3663 { 3664 struct xregs_state *xsave = &vcpu->arch.guest_fpu->state.xsave; 3665 u64 xstate_bv = xsave->header.xfeatures; 3666 u64 valid; 3667 3668 /* 3669 * Copy legacy XSAVE area, to avoid complications with CPUID 3670 * leaves 0 and 1 in the loop below. 3671 */ 3672 memcpy(dest, xsave, XSAVE_HDR_OFFSET); 3673 3674 /* Set XSTATE_BV */ 3675 xstate_bv &= vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FPSSE; 3676 *(u64 *)(dest + XSAVE_HDR_OFFSET) = xstate_bv; 3677 3678 /* 3679 * Copy each region from the possibly compacted offset to the 3680 * non-compacted offset. 3681 */ 3682 valid = xstate_bv & ~XFEATURE_MASK_FPSSE; 3683 while (valid) { 3684 u64 feature = valid & -valid; 3685 int index = fls64(feature) - 1; 3686 void *src = get_xsave_addr(xsave, feature); 3687 3688 if (src) { 3689 u32 size, offset, ecx, edx; 3690 cpuid_count(XSTATE_CPUID, index, 3691 &size, &offset, &ecx, &edx); 3692 if (feature == XFEATURE_MASK_PKRU) 3693 memcpy(dest + offset, &vcpu->arch.pkru, 3694 sizeof(vcpu->arch.pkru)); 3695 else 3696 memcpy(dest + offset, src, size); 3697 3698 } 3699 3700 valid -= feature; 3701 } 3702 } 3703 3704 static void load_xsave(struct kvm_vcpu *vcpu, u8 *src) 3705 { 3706 struct xregs_state *xsave = &vcpu->arch.guest_fpu->state.xsave; 3707 u64 xstate_bv = *(u64 *)(src + XSAVE_HDR_OFFSET); 3708 u64 valid; 3709 3710 /* 3711 * Copy legacy XSAVE area, to avoid complications with CPUID 3712 * leaves 0 and 1 in the loop below. 3713 */ 3714 memcpy(xsave, src, XSAVE_HDR_OFFSET); 3715 3716 /* Set XSTATE_BV and possibly XCOMP_BV. */ 3717 xsave->header.xfeatures = xstate_bv; 3718 if (boot_cpu_has(X86_FEATURE_XSAVES)) 3719 xsave->header.xcomp_bv = host_xcr0 | XSTATE_COMPACTION_ENABLED; 3720 3721 /* 3722 * Copy each region from the non-compacted offset to the 3723 * possibly compacted offset. 3724 */ 3725 valid = xstate_bv & ~XFEATURE_MASK_FPSSE; 3726 while (valid) { 3727 u64 feature = valid & -valid; 3728 int index = fls64(feature) - 1; 3729 void *dest = get_xsave_addr(xsave, feature); 3730 3731 if (dest) { 3732 u32 size, offset, ecx, edx; 3733 cpuid_count(XSTATE_CPUID, index, 3734 &size, &offset, &ecx, &edx); 3735 if (feature == XFEATURE_MASK_PKRU) 3736 memcpy(&vcpu->arch.pkru, src + offset, 3737 sizeof(vcpu->arch.pkru)); 3738 else 3739 memcpy(dest, src + offset, size); 3740 } 3741 3742 valid -= feature; 3743 } 3744 } 3745 3746 static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu, 3747 struct kvm_xsave *guest_xsave) 3748 { 3749 if (boot_cpu_has(X86_FEATURE_XSAVE)) { 3750 memset(guest_xsave, 0, sizeof(struct kvm_xsave)); 3751 fill_xsave((u8 *) guest_xsave->region, vcpu); 3752 } else { 3753 memcpy(guest_xsave->region, 3754 &vcpu->arch.guest_fpu->state.fxsave, 3755 sizeof(struct fxregs_state)); 3756 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] = 3757 XFEATURE_MASK_FPSSE; 3758 } 3759 } 3760 3761 #define XSAVE_MXCSR_OFFSET 24 3762 3763 static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu, 3764 struct kvm_xsave *guest_xsave) 3765 { 3766 u64 xstate_bv = 3767 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)]; 3768 u32 mxcsr = *(u32 *)&guest_xsave->region[XSAVE_MXCSR_OFFSET / sizeof(u32)]; 3769 3770 if (boot_cpu_has(X86_FEATURE_XSAVE)) { 3771 /* 3772 * Here we allow setting states that are not present in 3773 * CPUID leaf 0xD, index 0, EDX:EAX. This is for compatibility 3774 * with old userspace. 3775 */ 3776 if (xstate_bv & ~kvm_supported_xcr0() || 3777 mxcsr & ~mxcsr_feature_mask) 3778 return -EINVAL; 3779 load_xsave(vcpu, (u8 *)guest_xsave->region); 3780 } else { 3781 if (xstate_bv & ~XFEATURE_MASK_FPSSE || 3782 mxcsr & ~mxcsr_feature_mask) 3783 return -EINVAL; 3784 memcpy(&vcpu->arch.guest_fpu->state.fxsave, 3785 guest_xsave->region, sizeof(struct fxregs_state)); 3786 } 3787 return 0; 3788 } 3789 3790 static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu, 3791 struct kvm_xcrs *guest_xcrs) 3792 { 3793 if (!boot_cpu_has(X86_FEATURE_XSAVE)) { 3794 guest_xcrs->nr_xcrs = 0; 3795 return; 3796 } 3797 3798 guest_xcrs->nr_xcrs = 1; 3799 guest_xcrs->flags = 0; 3800 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK; 3801 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0; 3802 } 3803 3804 static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu, 3805 struct kvm_xcrs *guest_xcrs) 3806 { 3807 int i, r = 0; 3808 3809 if (!boot_cpu_has(X86_FEATURE_XSAVE)) 3810 return -EINVAL; 3811 3812 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags) 3813 return -EINVAL; 3814 3815 for (i = 0; i < guest_xcrs->nr_xcrs; i++) 3816 /* Only support XCR0 currently */ 3817 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) { 3818 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK, 3819 guest_xcrs->xcrs[i].value); 3820 break; 3821 } 3822 if (r) 3823 r = -EINVAL; 3824 return r; 3825 } 3826 3827 /* 3828 * kvm_set_guest_paused() indicates to the guest kernel that it has been 3829 * stopped by the hypervisor. This function will be called from the host only. 3830 * EINVAL is returned when the host attempts to set the flag for a guest that 3831 * does not support pv clocks. 3832 */ 3833 static int kvm_set_guest_paused(struct kvm_vcpu *vcpu) 3834 { 3835 if (!vcpu->arch.pv_time_enabled) 3836 return -EINVAL; 3837 vcpu->arch.pvclock_set_guest_stopped_request = true; 3838 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 3839 return 0; 3840 } 3841 3842 static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu, 3843 struct kvm_enable_cap *cap) 3844 { 3845 int r; 3846 uint16_t vmcs_version; 3847 void __user *user_ptr; 3848 3849 if (cap->flags) 3850 return -EINVAL; 3851 3852 switch (cap->cap) { 3853 case KVM_CAP_HYPERV_SYNIC2: 3854 if (cap->args[0]) 3855 return -EINVAL; 3856 /* fall through */ 3857 3858 case KVM_CAP_HYPERV_SYNIC: 3859 if (!irqchip_in_kernel(vcpu->kvm)) 3860 return -EINVAL; 3861 return kvm_hv_activate_synic(vcpu, cap->cap == 3862 KVM_CAP_HYPERV_SYNIC2); 3863 case KVM_CAP_HYPERV_ENLIGHTENED_VMCS: 3864 if (!kvm_x86_ops->nested_enable_evmcs) 3865 return -ENOTTY; 3866 r = kvm_x86_ops->nested_enable_evmcs(vcpu, &vmcs_version); 3867 if (!r) { 3868 user_ptr = (void __user *)(uintptr_t)cap->args[0]; 3869 if (copy_to_user(user_ptr, &vmcs_version, 3870 sizeof(vmcs_version))) 3871 r = -EFAULT; 3872 } 3873 return r; 3874 3875 default: 3876 return -EINVAL; 3877 } 3878 } 3879 3880 long kvm_arch_vcpu_ioctl(struct file *filp, 3881 unsigned int ioctl, unsigned long arg) 3882 { 3883 struct kvm_vcpu *vcpu = filp->private_data; 3884 void __user *argp = (void __user *)arg; 3885 int r; 3886 union { 3887 struct kvm_lapic_state *lapic; 3888 struct kvm_xsave *xsave; 3889 struct kvm_xcrs *xcrs; 3890 void *buffer; 3891 } u; 3892 3893 vcpu_load(vcpu); 3894 3895 u.buffer = NULL; 3896 switch (ioctl) { 3897 case KVM_GET_LAPIC: { 3898 r = -EINVAL; 3899 if (!lapic_in_kernel(vcpu)) 3900 goto out; 3901 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), 3902 GFP_KERNEL_ACCOUNT); 3903 3904 r = -ENOMEM; 3905 if (!u.lapic) 3906 goto out; 3907 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic); 3908 if (r) 3909 goto out; 3910 r = -EFAULT; 3911 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state))) 3912 goto out; 3913 r = 0; 3914 break; 3915 } 3916 case KVM_SET_LAPIC: { 3917 r = -EINVAL; 3918 if (!lapic_in_kernel(vcpu)) 3919 goto out; 3920 u.lapic = memdup_user(argp, sizeof(*u.lapic)); 3921 if (IS_ERR(u.lapic)) { 3922 r = PTR_ERR(u.lapic); 3923 goto out_nofree; 3924 } 3925 3926 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic); 3927 break; 3928 } 3929 case KVM_INTERRUPT: { 3930 struct kvm_interrupt irq; 3931 3932 r = -EFAULT; 3933 if (copy_from_user(&irq, argp, sizeof(irq))) 3934 goto out; 3935 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq); 3936 break; 3937 } 3938 case KVM_NMI: { 3939 r = kvm_vcpu_ioctl_nmi(vcpu); 3940 break; 3941 } 3942 case KVM_SMI: { 3943 r = kvm_vcpu_ioctl_smi(vcpu); 3944 break; 3945 } 3946 case KVM_SET_CPUID: { 3947 struct kvm_cpuid __user *cpuid_arg = argp; 3948 struct kvm_cpuid cpuid; 3949 3950 r = -EFAULT; 3951 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid))) 3952 goto out; 3953 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries); 3954 break; 3955 } 3956 case KVM_SET_CPUID2: { 3957 struct kvm_cpuid2 __user *cpuid_arg = argp; 3958 struct kvm_cpuid2 cpuid; 3959 3960 r = -EFAULT; 3961 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid))) 3962 goto out; 3963 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid, 3964 cpuid_arg->entries); 3965 break; 3966 } 3967 case KVM_GET_CPUID2: { 3968 struct kvm_cpuid2 __user *cpuid_arg = argp; 3969 struct kvm_cpuid2 cpuid; 3970 3971 r = -EFAULT; 3972 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid))) 3973 goto out; 3974 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid, 3975 cpuid_arg->entries); 3976 if (r) 3977 goto out; 3978 r = -EFAULT; 3979 if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid))) 3980 goto out; 3981 r = 0; 3982 break; 3983 } 3984 case KVM_GET_MSRS: { 3985 int idx = srcu_read_lock(&vcpu->kvm->srcu); 3986 r = msr_io(vcpu, argp, do_get_msr, 1); 3987 srcu_read_unlock(&vcpu->kvm->srcu, idx); 3988 break; 3989 } 3990 case KVM_SET_MSRS: { 3991 int idx = srcu_read_lock(&vcpu->kvm->srcu); 3992 r = msr_io(vcpu, argp, do_set_msr, 0); 3993 srcu_read_unlock(&vcpu->kvm->srcu, idx); 3994 break; 3995 } 3996 case KVM_TPR_ACCESS_REPORTING: { 3997 struct kvm_tpr_access_ctl tac; 3998 3999 r = -EFAULT; 4000 if (copy_from_user(&tac, argp, sizeof(tac))) 4001 goto out; 4002 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac); 4003 if (r) 4004 goto out; 4005 r = -EFAULT; 4006 if (copy_to_user(argp, &tac, sizeof(tac))) 4007 goto out; 4008 r = 0; 4009 break; 4010 }; 4011 case KVM_SET_VAPIC_ADDR: { 4012 struct kvm_vapic_addr va; 4013 int idx; 4014 4015 r = -EINVAL; 4016 if (!lapic_in_kernel(vcpu)) 4017 goto out; 4018 r = -EFAULT; 4019 if (copy_from_user(&va, argp, sizeof(va))) 4020 goto out; 4021 idx = srcu_read_lock(&vcpu->kvm->srcu); 4022 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr); 4023 srcu_read_unlock(&vcpu->kvm->srcu, idx); 4024 break; 4025 } 4026 case KVM_X86_SETUP_MCE: { 4027 u64 mcg_cap; 4028 4029 r = -EFAULT; 4030 if (copy_from_user(&mcg_cap, argp, sizeof(mcg_cap))) 4031 goto out; 4032 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap); 4033 break; 4034 } 4035 case KVM_X86_SET_MCE: { 4036 struct kvm_x86_mce mce; 4037 4038 r = -EFAULT; 4039 if (copy_from_user(&mce, argp, sizeof(mce))) 4040 goto out; 4041 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce); 4042 break; 4043 } 4044 case KVM_GET_VCPU_EVENTS: { 4045 struct kvm_vcpu_events events; 4046 4047 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events); 4048 4049 r = -EFAULT; 4050 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events))) 4051 break; 4052 r = 0; 4053 break; 4054 } 4055 case KVM_SET_VCPU_EVENTS: { 4056 struct kvm_vcpu_events events; 4057 4058 r = -EFAULT; 4059 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events))) 4060 break; 4061 4062 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events); 4063 break; 4064 } 4065 case KVM_GET_DEBUGREGS: { 4066 struct kvm_debugregs dbgregs; 4067 4068 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs); 4069 4070 r = -EFAULT; 4071 if (copy_to_user(argp, &dbgregs, 4072 sizeof(struct kvm_debugregs))) 4073 break; 4074 r = 0; 4075 break; 4076 } 4077 case KVM_SET_DEBUGREGS: { 4078 struct kvm_debugregs dbgregs; 4079 4080 r = -EFAULT; 4081 if (copy_from_user(&dbgregs, argp, 4082 sizeof(struct kvm_debugregs))) 4083 break; 4084 4085 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs); 4086 break; 4087 } 4088 case KVM_GET_XSAVE: { 4089 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL_ACCOUNT); 4090 r = -ENOMEM; 4091 if (!u.xsave) 4092 break; 4093 4094 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave); 4095 4096 r = -EFAULT; 4097 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave))) 4098 break; 4099 r = 0; 4100 break; 4101 } 4102 case KVM_SET_XSAVE: { 4103 u.xsave = memdup_user(argp, sizeof(*u.xsave)); 4104 if (IS_ERR(u.xsave)) { 4105 r = PTR_ERR(u.xsave); 4106 goto out_nofree; 4107 } 4108 4109 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave); 4110 break; 4111 } 4112 case KVM_GET_XCRS: { 4113 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL_ACCOUNT); 4114 r = -ENOMEM; 4115 if (!u.xcrs) 4116 break; 4117 4118 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs); 4119 4120 r = -EFAULT; 4121 if (copy_to_user(argp, u.xcrs, 4122 sizeof(struct kvm_xcrs))) 4123 break; 4124 r = 0; 4125 break; 4126 } 4127 case KVM_SET_XCRS: { 4128 u.xcrs = memdup_user(argp, sizeof(*u.xcrs)); 4129 if (IS_ERR(u.xcrs)) { 4130 r = PTR_ERR(u.xcrs); 4131 goto out_nofree; 4132 } 4133 4134 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs); 4135 break; 4136 } 4137 case KVM_SET_TSC_KHZ: { 4138 u32 user_tsc_khz; 4139 4140 r = -EINVAL; 4141 user_tsc_khz = (u32)arg; 4142 4143 if (user_tsc_khz >= kvm_max_guest_tsc_khz) 4144 goto out; 4145 4146 if (user_tsc_khz == 0) 4147 user_tsc_khz = tsc_khz; 4148 4149 if (!kvm_set_tsc_khz(vcpu, user_tsc_khz)) 4150 r = 0; 4151 4152 goto out; 4153 } 4154 case KVM_GET_TSC_KHZ: { 4155 r = vcpu->arch.virtual_tsc_khz; 4156 goto out; 4157 } 4158 case KVM_KVMCLOCK_CTRL: { 4159 r = kvm_set_guest_paused(vcpu); 4160 goto out; 4161 } 4162 case KVM_ENABLE_CAP: { 4163 struct kvm_enable_cap cap; 4164 4165 r = -EFAULT; 4166 if (copy_from_user(&cap, argp, sizeof(cap))) 4167 goto out; 4168 r = kvm_vcpu_ioctl_enable_cap(vcpu, &cap); 4169 break; 4170 } 4171 case KVM_GET_NESTED_STATE: { 4172 struct kvm_nested_state __user *user_kvm_nested_state = argp; 4173 u32 user_data_size; 4174 4175 r = -EINVAL; 4176 if (!kvm_x86_ops->get_nested_state) 4177 break; 4178 4179 BUILD_BUG_ON(sizeof(user_data_size) != sizeof(user_kvm_nested_state->size)); 4180 r = -EFAULT; 4181 if (get_user(user_data_size, &user_kvm_nested_state->size)) 4182 break; 4183 4184 r = kvm_x86_ops->get_nested_state(vcpu, user_kvm_nested_state, 4185 user_data_size); 4186 if (r < 0) 4187 break; 4188 4189 if (r > user_data_size) { 4190 if (put_user(r, &user_kvm_nested_state->size)) 4191 r = -EFAULT; 4192 else 4193 r = -E2BIG; 4194 break; 4195 } 4196 4197 r = 0; 4198 break; 4199 } 4200 case KVM_SET_NESTED_STATE: { 4201 struct kvm_nested_state __user *user_kvm_nested_state = argp; 4202 struct kvm_nested_state kvm_state; 4203 4204 r = -EINVAL; 4205 if (!kvm_x86_ops->set_nested_state) 4206 break; 4207 4208 r = -EFAULT; 4209 if (copy_from_user(&kvm_state, user_kvm_nested_state, sizeof(kvm_state))) 4210 break; 4211 4212 r = -EINVAL; 4213 if (kvm_state.size < sizeof(kvm_state)) 4214 break; 4215 4216 if (kvm_state.flags & 4217 ~(KVM_STATE_NESTED_RUN_PENDING | KVM_STATE_NESTED_GUEST_MODE 4218 | KVM_STATE_NESTED_EVMCS)) 4219 break; 4220 4221 /* nested_run_pending implies guest_mode. */ 4222 if ((kvm_state.flags & KVM_STATE_NESTED_RUN_PENDING) 4223 && !(kvm_state.flags & KVM_STATE_NESTED_GUEST_MODE)) 4224 break; 4225 4226 r = kvm_x86_ops->set_nested_state(vcpu, user_kvm_nested_state, &kvm_state); 4227 break; 4228 } 4229 case KVM_GET_SUPPORTED_HV_CPUID: { 4230 struct kvm_cpuid2 __user *cpuid_arg = argp; 4231 struct kvm_cpuid2 cpuid; 4232 4233 r = -EFAULT; 4234 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid))) 4235 goto out; 4236 4237 r = kvm_vcpu_ioctl_get_hv_cpuid(vcpu, &cpuid, 4238 cpuid_arg->entries); 4239 if (r) 4240 goto out; 4241 4242 r = -EFAULT; 4243 if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid))) 4244 goto out; 4245 r = 0; 4246 break; 4247 } 4248 default: 4249 r = -EINVAL; 4250 } 4251 out: 4252 kfree(u.buffer); 4253 out_nofree: 4254 vcpu_put(vcpu); 4255 return r; 4256 } 4257 4258 vm_fault_t kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf) 4259 { 4260 return VM_FAULT_SIGBUS; 4261 } 4262 4263 static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr) 4264 { 4265 int ret; 4266 4267 if (addr > (unsigned int)(-3 * PAGE_SIZE)) 4268 return -EINVAL; 4269 ret = kvm_x86_ops->set_tss_addr(kvm, addr); 4270 return ret; 4271 } 4272 4273 static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm, 4274 u64 ident_addr) 4275 { 4276 return kvm_x86_ops->set_identity_map_addr(kvm, ident_addr); 4277 } 4278 4279 static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm, 4280 unsigned long kvm_nr_mmu_pages) 4281 { 4282 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES) 4283 return -EINVAL; 4284 4285 mutex_lock(&kvm->slots_lock); 4286 4287 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages); 4288 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages; 4289 4290 mutex_unlock(&kvm->slots_lock); 4291 return 0; 4292 } 4293 4294 static unsigned long kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm) 4295 { 4296 return kvm->arch.n_max_mmu_pages; 4297 } 4298 4299 static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip) 4300 { 4301 struct kvm_pic *pic = kvm->arch.vpic; 4302 int r; 4303 4304 r = 0; 4305 switch (chip->chip_id) { 4306 case KVM_IRQCHIP_PIC_MASTER: 4307 memcpy(&chip->chip.pic, &pic->pics[0], 4308 sizeof(struct kvm_pic_state)); 4309 break; 4310 case KVM_IRQCHIP_PIC_SLAVE: 4311 memcpy(&chip->chip.pic, &pic->pics[1], 4312 sizeof(struct kvm_pic_state)); 4313 break; 4314 case KVM_IRQCHIP_IOAPIC: 4315 kvm_get_ioapic(kvm, &chip->chip.ioapic); 4316 break; 4317 default: 4318 r = -EINVAL; 4319 break; 4320 } 4321 return r; 4322 } 4323 4324 static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip) 4325 { 4326 struct kvm_pic *pic = kvm->arch.vpic; 4327 int r; 4328 4329 r = 0; 4330 switch (chip->chip_id) { 4331 case KVM_IRQCHIP_PIC_MASTER: 4332 spin_lock(&pic->lock); 4333 memcpy(&pic->pics[0], &chip->chip.pic, 4334 sizeof(struct kvm_pic_state)); 4335 spin_unlock(&pic->lock); 4336 break; 4337 case KVM_IRQCHIP_PIC_SLAVE: 4338 spin_lock(&pic->lock); 4339 memcpy(&pic->pics[1], &chip->chip.pic, 4340 sizeof(struct kvm_pic_state)); 4341 spin_unlock(&pic->lock); 4342 break; 4343 case KVM_IRQCHIP_IOAPIC: 4344 kvm_set_ioapic(kvm, &chip->chip.ioapic); 4345 break; 4346 default: 4347 r = -EINVAL; 4348 break; 4349 } 4350 kvm_pic_update_irq(pic); 4351 return r; 4352 } 4353 4354 static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps) 4355 { 4356 struct kvm_kpit_state *kps = &kvm->arch.vpit->pit_state; 4357 4358 BUILD_BUG_ON(sizeof(*ps) != sizeof(kps->channels)); 4359 4360 mutex_lock(&kps->lock); 4361 memcpy(ps, &kps->channels, sizeof(*ps)); 4362 mutex_unlock(&kps->lock); 4363 return 0; 4364 } 4365 4366 static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps) 4367 { 4368 int i; 4369 struct kvm_pit *pit = kvm->arch.vpit; 4370 4371 mutex_lock(&pit->pit_state.lock); 4372 memcpy(&pit->pit_state.channels, ps, sizeof(*ps)); 4373 for (i = 0; i < 3; i++) 4374 kvm_pit_load_count(pit, i, ps->channels[i].count, 0); 4375 mutex_unlock(&pit->pit_state.lock); 4376 return 0; 4377 } 4378 4379 static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps) 4380 { 4381 mutex_lock(&kvm->arch.vpit->pit_state.lock); 4382 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels, 4383 sizeof(ps->channels)); 4384 ps->flags = kvm->arch.vpit->pit_state.flags; 4385 mutex_unlock(&kvm->arch.vpit->pit_state.lock); 4386 memset(&ps->reserved, 0, sizeof(ps->reserved)); 4387 return 0; 4388 } 4389 4390 static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps) 4391 { 4392 int start = 0; 4393 int i; 4394 u32 prev_legacy, cur_legacy; 4395 struct kvm_pit *pit = kvm->arch.vpit; 4396 4397 mutex_lock(&pit->pit_state.lock); 4398 prev_legacy = pit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY; 4399 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY; 4400 if (!prev_legacy && cur_legacy) 4401 start = 1; 4402 memcpy(&pit->pit_state.channels, &ps->channels, 4403 sizeof(pit->pit_state.channels)); 4404 pit->pit_state.flags = ps->flags; 4405 for (i = 0; i < 3; i++) 4406 kvm_pit_load_count(pit, i, pit->pit_state.channels[i].count, 4407 start && i == 0); 4408 mutex_unlock(&pit->pit_state.lock); 4409 return 0; 4410 } 4411 4412 static int kvm_vm_ioctl_reinject(struct kvm *kvm, 4413 struct kvm_reinject_control *control) 4414 { 4415 struct kvm_pit *pit = kvm->arch.vpit; 4416 4417 if (!pit) 4418 return -ENXIO; 4419 4420 /* pit->pit_state.lock was overloaded to prevent userspace from getting 4421 * an inconsistent state after running multiple KVM_REINJECT_CONTROL 4422 * ioctls in parallel. Use a separate lock if that ioctl isn't rare. 4423 */ 4424 mutex_lock(&pit->pit_state.lock); 4425 kvm_pit_set_reinject(pit, control->pit_reinject); 4426 mutex_unlock(&pit->pit_state.lock); 4427 4428 return 0; 4429 } 4430 4431 /** 4432 * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot 4433 * @kvm: kvm instance 4434 * @log: slot id and address to which we copy the log 4435 * 4436 * Steps 1-4 below provide general overview of dirty page logging. See 4437 * kvm_get_dirty_log_protect() function description for additional details. 4438 * 4439 * We call kvm_get_dirty_log_protect() to handle steps 1-3, upon return we 4440 * always flush the TLB (step 4) even if previous step failed and the dirty 4441 * bitmap may be corrupt. Regardless of previous outcome the KVM logging API 4442 * does not preclude user space subsequent dirty log read. Flushing TLB ensures 4443 * writes will be marked dirty for next log read. 4444 * 4445 * 1. Take a snapshot of the bit and clear it if needed. 4446 * 2. Write protect the corresponding page. 4447 * 3. Copy the snapshot to the userspace. 4448 * 4. Flush TLB's if needed. 4449 */ 4450 int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log) 4451 { 4452 bool flush = false; 4453 int r; 4454 4455 mutex_lock(&kvm->slots_lock); 4456 4457 /* 4458 * Flush potentially hardware-cached dirty pages to dirty_bitmap. 4459 */ 4460 if (kvm_x86_ops->flush_log_dirty) 4461 kvm_x86_ops->flush_log_dirty(kvm); 4462 4463 r = kvm_get_dirty_log_protect(kvm, log, &flush); 4464 4465 /* 4466 * All the TLBs can be flushed out of mmu lock, see the comments in 4467 * kvm_mmu_slot_remove_write_access(). 4468 */ 4469 lockdep_assert_held(&kvm->slots_lock); 4470 if (flush) 4471 kvm_flush_remote_tlbs(kvm); 4472 4473 mutex_unlock(&kvm->slots_lock); 4474 return r; 4475 } 4476 4477 int kvm_vm_ioctl_clear_dirty_log(struct kvm *kvm, struct kvm_clear_dirty_log *log) 4478 { 4479 bool flush = false; 4480 int r; 4481 4482 mutex_lock(&kvm->slots_lock); 4483 4484 /* 4485 * Flush potentially hardware-cached dirty pages to dirty_bitmap. 4486 */ 4487 if (kvm_x86_ops->flush_log_dirty) 4488 kvm_x86_ops->flush_log_dirty(kvm); 4489 4490 r = kvm_clear_dirty_log_protect(kvm, log, &flush); 4491 4492 /* 4493 * All the TLBs can be flushed out of mmu lock, see the comments in 4494 * kvm_mmu_slot_remove_write_access(). 4495 */ 4496 lockdep_assert_held(&kvm->slots_lock); 4497 if (flush) 4498 kvm_flush_remote_tlbs(kvm); 4499 4500 mutex_unlock(&kvm->slots_lock); 4501 return r; 4502 } 4503 4504 int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event, 4505 bool line_status) 4506 { 4507 if (!irqchip_in_kernel(kvm)) 4508 return -ENXIO; 4509 4510 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID, 4511 irq_event->irq, irq_event->level, 4512 line_status); 4513 return 0; 4514 } 4515 4516 int kvm_vm_ioctl_enable_cap(struct kvm *kvm, 4517 struct kvm_enable_cap *cap) 4518 { 4519 int r; 4520 4521 if (cap->flags) 4522 return -EINVAL; 4523 4524 switch (cap->cap) { 4525 case KVM_CAP_DISABLE_QUIRKS: 4526 kvm->arch.disabled_quirks = cap->args[0]; 4527 r = 0; 4528 break; 4529 case KVM_CAP_SPLIT_IRQCHIP: { 4530 mutex_lock(&kvm->lock); 4531 r = -EINVAL; 4532 if (cap->args[0] > MAX_NR_RESERVED_IOAPIC_PINS) 4533 goto split_irqchip_unlock; 4534 r = -EEXIST; 4535 if (irqchip_in_kernel(kvm)) 4536 goto split_irqchip_unlock; 4537 if (kvm->created_vcpus) 4538 goto split_irqchip_unlock; 4539 r = kvm_setup_empty_irq_routing(kvm); 4540 if (r) 4541 goto split_irqchip_unlock; 4542 /* Pairs with irqchip_in_kernel. */ 4543 smp_wmb(); 4544 kvm->arch.irqchip_mode = KVM_IRQCHIP_SPLIT; 4545 kvm->arch.nr_reserved_ioapic_pins = cap->args[0]; 4546 r = 0; 4547 split_irqchip_unlock: 4548 mutex_unlock(&kvm->lock); 4549 break; 4550 } 4551 case KVM_CAP_X2APIC_API: 4552 r = -EINVAL; 4553 if (cap->args[0] & ~KVM_X2APIC_API_VALID_FLAGS) 4554 break; 4555 4556 if (cap->args[0] & KVM_X2APIC_API_USE_32BIT_IDS) 4557 kvm->arch.x2apic_format = true; 4558 if (cap->args[0] & KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK) 4559 kvm->arch.x2apic_broadcast_quirk_disabled = true; 4560 4561 r = 0; 4562 break; 4563 case KVM_CAP_X86_DISABLE_EXITS: 4564 r = -EINVAL; 4565 if (cap->args[0] & ~KVM_X86_DISABLE_VALID_EXITS) 4566 break; 4567 4568 if ((cap->args[0] & KVM_X86_DISABLE_EXITS_MWAIT) && 4569 kvm_can_mwait_in_guest()) 4570 kvm->arch.mwait_in_guest = true; 4571 if (cap->args[0] & KVM_X86_DISABLE_EXITS_HLT) 4572 kvm->arch.hlt_in_guest = true; 4573 if (cap->args[0] & KVM_X86_DISABLE_EXITS_PAUSE) 4574 kvm->arch.pause_in_guest = true; 4575 r = 0; 4576 break; 4577 case KVM_CAP_MSR_PLATFORM_INFO: 4578 kvm->arch.guest_can_read_msr_platform_info = cap->args[0]; 4579 r = 0; 4580 break; 4581 case KVM_CAP_EXCEPTION_PAYLOAD: 4582 kvm->arch.exception_payload_enabled = cap->args[0]; 4583 r = 0; 4584 break; 4585 default: 4586 r = -EINVAL; 4587 break; 4588 } 4589 return r; 4590 } 4591 4592 long kvm_arch_vm_ioctl(struct file *filp, 4593 unsigned int ioctl, unsigned long arg) 4594 { 4595 struct kvm *kvm = filp->private_data; 4596 void __user *argp = (void __user *)arg; 4597 int r = -ENOTTY; 4598 /* 4599 * This union makes it completely explicit to gcc-3.x 4600 * that these two variables' stack usage should be 4601 * combined, not added together. 4602 */ 4603 union { 4604 struct kvm_pit_state ps; 4605 struct kvm_pit_state2 ps2; 4606 struct kvm_pit_config pit_config; 4607 } u; 4608 4609 switch (ioctl) { 4610 case KVM_SET_TSS_ADDR: 4611 r = kvm_vm_ioctl_set_tss_addr(kvm, arg); 4612 break; 4613 case KVM_SET_IDENTITY_MAP_ADDR: { 4614 u64 ident_addr; 4615 4616 mutex_lock(&kvm->lock); 4617 r = -EINVAL; 4618 if (kvm->created_vcpus) 4619 goto set_identity_unlock; 4620 r = -EFAULT; 4621 if (copy_from_user(&ident_addr, argp, sizeof(ident_addr))) 4622 goto set_identity_unlock; 4623 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr); 4624 set_identity_unlock: 4625 mutex_unlock(&kvm->lock); 4626 break; 4627 } 4628 case KVM_SET_NR_MMU_PAGES: 4629 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg); 4630 break; 4631 case KVM_GET_NR_MMU_PAGES: 4632 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm); 4633 break; 4634 case KVM_CREATE_IRQCHIP: { 4635 mutex_lock(&kvm->lock); 4636 4637 r = -EEXIST; 4638 if (irqchip_in_kernel(kvm)) 4639 goto create_irqchip_unlock; 4640 4641 r = -EINVAL; 4642 if (kvm->created_vcpus) 4643 goto create_irqchip_unlock; 4644 4645 r = kvm_pic_init(kvm); 4646 if (r) 4647 goto create_irqchip_unlock; 4648 4649 r = kvm_ioapic_init(kvm); 4650 if (r) { 4651 kvm_pic_destroy(kvm); 4652 goto create_irqchip_unlock; 4653 } 4654 4655 r = kvm_setup_default_irq_routing(kvm); 4656 if (r) { 4657 kvm_ioapic_destroy(kvm); 4658 kvm_pic_destroy(kvm); 4659 goto create_irqchip_unlock; 4660 } 4661 /* Write kvm->irq_routing before enabling irqchip_in_kernel. */ 4662 smp_wmb(); 4663 kvm->arch.irqchip_mode = KVM_IRQCHIP_KERNEL; 4664 create_irqchip_unlock: 4665 mutex_unlock(&kvm->lock); 4666 break; 4667 } 4668 case KVM_CREATE_PIT: 4669 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY; 4670 goto create_pit; 4671 case KVM_CREATE_PIT2: 4672 r = -EFAULT; 4673 if (copy_from_user(&u.pit_config, argp, 4674 sizeof(struct kvm_pit_config))) 4675 goto out; 4676 create_pit: 4677 mutex_lock(&kvm->lock); 4678 r = -EEXIST; 4679 if (kvm->arch.vpit) 4680 goto create_pit_unlock; 4681 r = -ENOMEM; 4682 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags); 4683 if (kvm->arch.vpit) 4684 r = 0; 4685 create_pit_unlock: 4686 mutex_unlock(&kvm->lock); 4687 break; 4688 case KVM_GET_IRQCHIP: { 4689 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */ 4690 struct kvm_irqchip *chip; 4691 4692 chip = memdup_user(argp, sizeof(*chip)); 4693 if (IS_ERR(chip)) { 4694 r = PTR_ERR(chip); 4695 goto out; 4696 } 4697 4698 r = -ENXIO; 4699 if (!irqchip_kernel(kvm)) 4700 goto get_irqchip_out; 4701 r = kvm_vm_ioctl_get_irqchip(kvm, chip); 4702 if (r) 4703 goto get_irqchip_out; 4704 r = -EFAULT; 4705 if (copy_to_user(argp, chip, sizeof(*chip))) 4706 goto get_irqchip_out; 4707 r = 0; 4708 get_irqchip_out: 4709 kfree(chip); 4710 break; 4711 } 4712 case KVM_SET_IRQCHIP: { 4713 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */ 4714 struct kvm_irqchip *chip; 4715 4716 chip = memdup_user(argp, sizeof(*chip)); 4717 if (IS_ERR(chip)) { 4718 r = PTR_ERR(chip); 4719 goto out; 4720 } 4721 4722 r = -ENXIO; 4723 if (!irqchip_kernel(kvm)) 4724 goto set_irqchip_out; 4725 r = kvm_vm_ioctl_set_irqchip(kvm, chip); 4726 if (r) 4727 goto set_irqchip_out; 4728 r = 0; 4729 set_irqchip_out: 4730 kfree(chip); 4731 break; 4732 } 4733 case KVM_GET_PIT: { 4734 r = -EFAULT; 4735 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state))) 4736 goto out; 4737 r = -ENXIO; 4738 if (!kvm->arch.vpit) 4739 goto out; 4740 r = kvm_vm_ioctl_get_pit(kvm, &u.ps); 4741 if (r) 4742 goto out; 4743 r = -EFAULT; 4744 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state))) 4745 goto out; 4746 r = 0; 4747 break; 4748 } 4749 case KVM_SET_PIT: { 4750 r = -EFAULT; 4751 if (copy_from_user(&u.ps, argp, sizeof(u.ps))) 4752 goto out; 4753 r = -ENXIO; 4754 if (!kvm->arch.vpit) 4755 goto out; 4756 r = kvm_vm_ioctl_set_pit(kvm, &u.ps); 4757 break; 4758 } 4759 case KVM_GET_PIT2: { 4760 r = -ENXIO; 4761 if (!kvm->arch.vpit) 4762 goto out; 4763 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2); 4764 if (r) 4765 goto out; 4766 r = -EFAULT; 4767 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2))) 4768 goto out; 4769 r = 0; 4770 break; 4771 } 4772 case KVM_SET_PIT2: { 4773 r = -EFAULT; 4774 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2))) 4775 goto out; 4776 r = -ENXIO; 4777 if (!kvm->arch.vpit) 4778 goto out; 4779 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2); 4780 break; 4781 } 4782 case KVM_REINJECT_CONTROL: { 4783 struct kvm_reinject_control control; 4784 r = -EFAULT; 4785 if (copy_from_user(&control, argp, sizeof(control))) 4786 goto out; 4787 r = kvm_vm_ioctl_reinject(kvm, &control); 4788 break; 4789 } 4790 case KVM_SET_BOOT_CPU_ID: 4791 r = 0; 4792 mutex_lock(&kvm->lock); 4793 if (kvm->created_vcpus) 4794 r = -EBUSY; 4795 else 4796 kvm->arch.bsp_vcpu_id = arg; 4797 mutex_unlock(&kvm->lock); 4798 break; 4799 case KVM_XEN_HVM_CONFIG: { 4800 struct kvm_xen_hvm_config xhc; 4801 r = -EFAULT; 4802 if (copy_from_user(&xhc, argp, sizeof(xhc))) 4803 goto out; 4804 r = -EINVAL; 4805 if (xhc.flags) 4806 goto out; 4807 memcpy(&kvm->arch.xen_hvm_config, &xhc, sizeof(xhc)); 4808 r = 0; 4809 break; 4810 } 4811 case KVM_SET_CLOCK: { 4812 struct kvm_clock_data user_ns; 4813 u64 now_ns; 4814 4815 r = -EFAULT; 4816 if (copy_from_user(&user_ns, argp, sizeof(user_ns))) 4817 goto out; 4818 4819 r = -EINVAL; 4820 if (user_ns.flags) 4821 goto out; 4822 4823 r = 0; 4824 /* 4825 * TODO: userspace has to take care of races with VCPU_RUN, so 4826 * kvm_gen_update_masterclock() can be cut down to locked 4827 * pvclock_update_vm_gtod_copy(). 4828 */ 4829 kvm_gen_update_masterclock(kvm); 4830 now_ns = get_kvmclock_ns(kvm); 4831 kvm->arch.kvmclock_offset += user_ns.clock - now_ns; 4832 kvm_make_all_cpus_request(kvm, KVM_REQ_CLOCK_UPDATE); 4833 break; 4834 } 4835 case KVM_GET_CLOCK: { 4836 struct kvm_clock_data user_ns; 4837 u64 now_ns; 4838 4839 now_ns = get_kvmclock_ns(kvm); 4840 user_ns.clock = now_ns; 4841 user_ns.flags = kvm->arch.use_master_clock ? KVM_CLOCK_TSC_STABLE : 0; 4842 memset(&user_ns.pad, 0, sizeof(user_ns.pad)); 4843 4844 r = -EFAULT; 4845 if (copy_to_user(argp, &user_ns, sizeof(user_ns))) 4846 goto out; 4847 r = 0; 4848 break; 4849 } 4850 case KVM_MEMORY_ENCRYPT_OP: { 4851 r = -ENOTTY; 4852 if (kvm_x86_ops->mem_enc_op) 4853 r = kvm_x86_ops->mem_enc_op(kvm, argp); 4854 break; 4855 } 4856 case KVM_MEMORY_ENCRYPT_REG_REGION: { 4857 struct kvm_enc_region region; 4858 4859 r = -EFAULT; 4860 if (copy_from_user(®ion, argp, sizeof(region))) 4861 goto out; 4862 4863 r = -ENOTTY; 4864 if (kvm_x86_ops->mem_enc_reg_region) 4865 r = kvm_x86_ops->mem_enc_reg_region(kvm, ®ion); 4866 break; 4867 } 4868 case KVM_MEMORY_ENCRYPT_UNREG_REGION: { 4869 struct kvm_enc_region region; 4870 4871 r = -EFAULT; 4872 if (copy_from_user(®ion, argp, sizeof(region))) 4873 goto out; 4874 4875 r = -ENOTTY; 4876 if (kvm_x86_ops->mem_enc_unreg_region) 4877 r = kvm_x86_ops->mem_enc_unreg_region(kvm, ®ion); 4878 break; 4879 } 4880 case KVM_HYPERV_EVENTFD: { 4881 struct kvm_hyperv_eventfd hvevfd; 4882 4883 r = -EFAULT; 4884 if (copy_from_user(&hvevfd, argp, sizeof(hvevfd))) 4885 goto out; 4886 r = kvm_vm_ioctl_hv_eventfd(kvm, &hvevfd); 4887 break; 4888 } 4889 default: 4890 r = -ENOTTY; 4891 } 4892 out: 4893 return r; 4894 } 4895 4896 static void kvm_init_msr_list(void) 4897 { 4898 u32 dummy[2]; 4899 unsigned i, j; 4900 4901 for (i = j = 0; i < ARRAY_SIZE(msrs_to_save); i++) { 4902 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0) 4903 continue; 4904 4905 /* 4906 * Even MSRs that are valid in the host may not be exposed 4907 * to the guests in some cases. 4908 */ 4909 switch (msrs_to_save[i]) { 4910 case MSR_IA32_BNDCFGS: 4911 if (!kvm_mpx_supported()) 4912 continue; 4913 break; 4914 case MSR_TSC_AUX: 4915 if (!kvm_x86_ops->rdtscp_supported()) 4916 continue; 4917 break; 4918 case MSR_IA32_RTIT_CTL: 4919 case MSR_IA32_RTIT_STATUS: 4920 if (!kvm_x86_ops->pt_supported()) 4921 continue; 4922 break; 4923 case MSR_IA32_RTIT_CR3_MATCH: 4924 if (!kvm_x86_ops->pt_supported() || 4925 !intel_pt_validate_hw_cap(PT_CAP_cr3_filtering)) 4926 continue; 4927 break; 4928 case MSR_IA32_RTIT_OUTPUT_BASE: 4929 case MSR_IA32_RTIT_OUTPUT_MASK: 4930 if (!kvm_x86_ops->pt_supported() || 4931 (!intel_pt_validate_hw_cap(PT_CAP_topa_output) && 4932 !intel_pt_validate_hw_cap(PT_CAP_single_range_output))) 4933 continue; 4934 break; 4935 case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B: { 4936 if (!kvm_x86_ops->pt_supported() || 4937 msrs_to_save[i] - MSR_IA32_RTIT_ADDR0_A >= 4938 intel_pt_validate_hw_cap(PT_CAP_num_address_ranges) * 2) 4939 continue; 4940 break; 4941 } 4942 default: 4943 break; 4944 } 4945 4946 if (j < i) 4947 msrs_to_save[j] = msrs_to_save[i]; 4948 j++; 4949 } 4950 num_msrs_to_save = j; 4951 4952 for (i = j = 0; i < ARRAY_SIZE(emulated_msrs); i++) { 4953 if (!kvm_x86_ops->has_emulated_msr(emulated_msrs[i])) 4954 continue; 4955 4956 if (j < i) 4957 emulated_msrs[j] = emulated_msrs[i]; 4958 j++; 4959 } 4960 num_emulated_msrs = j; 4961 4962 for (i = j = 0; i < ARRAY_SIZE(msr_based_features); i++) { 4963 struct kvm_msr_entry msr; 4964 4965 msr.index = msr_based_features[i]; 4966 if (kvm_get_msr_feature(&msr)) 4967 continue; 4968 4969 if (j < i) 4970 msr_based_features[j] = msr_based_features[i]; 4971 j++; 4972 } 4973 num_msr_based_features = j; 4974 } 4975 4976 static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len, 4977 const void *v) 4978 { 4979 int handled = 0; 4980 int n; 4981 4982 do { 4983 n = min(len, 8); 4984 if (!(lapic_in_kernel(vcpu) && 4985 !kvm_iodevice_write(vcpu, &vcpu->arch.apic->dev, addr, n, v)) 4986 && kvm_io_bus_write(vcpu, KVM_MMIO_BUS, addr, n, v)) 4987 break; 4988 handled += n; 4989 addr += n; 4990 len -= n; 4991 v += n; 4992 } while (len); 4993 4994 return handled; 4995 } 4996 4997 static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v) 4998 { 4999 int handled = 0; 5000 int n; 5001 5002 do { 5003 n = min(len, 8); 5004 if (!(lapic_in_kernel(vcpu) && 5005 !kvm_iodevice_read(vcpu, &vcpu->arch.apic->dev, 5006 addr, n, v)) 5007 && kvm_io_bus_read(vcpu, KVM_MMIO_BUS, addr, n, v)) 5008 break; 5009 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, v); 5010 handled += n; 5011 addr += n; 5012 len -= n; 5013 v += n; 5014 } while (len); 5015 5016 return handled; 5017 } 5018 5019 static void kvm_set_segment(struct kvm_vcpu *vcpu, 5020 struct kvm_segment *var, int seg) 5021 { 5022 kvm_x86_ops->set_segment(vcpu, var, seg); 5023 } 5024 5025 void kvm_get_segment(struct kvm_vcpu *vcpu, 5026 struct kvm_segment *var, int seg) 5027 { 5028 kvm_x86_ops->get_segment(vcpu, var, seg); 5029 } 5030 5031 gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access, 5032 struct x86_exception *exception) 5033 { 5034 gpa_t t_gpa; 5035 5036 BUG_ON(!mmu_is_nested(vcpu)); 5037 5038 /* NPT walks are always user-walks */ 5039 access |= PFERR_USER_MASK; 5040 t_gpa = vcpu->arch.mmu->gva_to_gpa(vcpu, gpa, access, exception); 5041 5042 return t_gpa; 5043 } 5044 5045 gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva, 5046 struct x86_exception *exception) 5047 { 5048 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0; 5049 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception); 5050 } 5051 5052 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva, 5053 struct x86_exception *exception) 5054 { 5055 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0; 5056 access |= PFERR_FETCH_MASK; 5057 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception); 5058 } 5059 5060 gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva, 5061 struct x86_exception *exception) 5062 { 5063 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0; 5064 access |= PFERR_WRITE_MASK; 5065 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception); 5066 } 5067 5068 /* uses this to access any guest's mapped memory without checking CPL */ 5069 gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva, 5070 struct x86_exception *exception) 5071 { 5072 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception); 5073 } 5074 5075 static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes, 5076 struct kvm_vcpu *vcpu, u32 access, 5077 struct x86_exception *exception) 5078 { 5079 void *data = val; 5080 int r = X86EMUL_CONTINUE; 5081 5082 while (bytes) { 5083 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access, 5084 exception); 5085 unsigned offset = addr & (PAGE_SIZE-1); 5086 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset); 5087 int ret; 5088 5089 if (gpa == UNMAPPED_GVA) 5090 return X86EMUL_PROPAGATE_FAULT; 5091 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, data, 5092 offset, toread); 5093 if (ret < 0) { 5094 r = X86EMUL_IO_NEEDED; 5095 goto out; 5096 } 5097 5098 bytes -= toread; 5099 data += toread; 5100 addr += toread; 5101 } 5102 out: 5103 return r; 5104 } 5105 5106 /* used for instruction fetching */ 5107 static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt, 5108 gva_t addr, void *val, unsigned int bytes, 5109 struct x86_exception *exception) 5110 { 5111 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 5112 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0; 5113 unsigned offset; 5114 int ret; 5115 5116 /* Inline kvm_read_guest_virt_helper for speed. */ 5117 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access|PFERR_FETCH_MASK, 5118 exception); 5119 if (unlikely(gpa == UNMAPPED_GVA)) 5120 return X86EMUL_PROPAGATE_FAULT; 5121 5122 offset = addr & (PAGE_SIZE-1); 5123 if (WARN_ON(offset + bytes > PAGE_SIZE)) 5124 bytes = (unsigned)PAGE_SIZE - offset; 5125 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, val, 5126 offset, bytes); 5127 if (unlikely(ret < 0)) 5128 return X86EMUL_IO_NEEDED; 5129 5130 return X86EMUL_CONTINUE; 5131 } 5132 5133 int kvm_read_guest_virt(struct kvm_vcpu *vcpu, 5134 gva_t addr, void *val, unsigned int bytes, 5135 struct x86_exception *exception) 5136 { 5137 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0; 5138 5139 /* 5140 * FIXME: this should call handle_emulation_failure if X86EMUL_IO_NEEDED 5141 * is returned, but our callers are not ready for that and they blindly 5142 * call kvm_inject_page_fault. Ensure that they at least do not leak 5143 * uninitialized kernel stack memory into cr2 and error code. 5144 */ 5145 memset(exception, 0, sizeof(*exception)); 5146 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access, 5147 exception); 5148 } 5149 EXPORT_SYMBOL_GPL(kvm_read_guest_virt); 5150 5151 static int emulator_read_std(struct x86_emulate_ctxt *ctxt, 5152 gva_t addr, void *val, unsigned int bytes, 5153 struct x86_exception *exception, bool system) 5154 { 5155 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 5156 u32 access = 0; 5157 5158 if (!system && kvm_x86_ops->get_cpl(vcpu) == 3) 5159 access |= PFERR_USER_MASK; 5160 5161 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access, exception); 5162 } 5163 5164 static int kvm_read_guest_phys_system(struct x86_emulate_ctxt *ctxt, 5165 unsigned long addr, void *val, unsigned int bytes) 5166 { 5167 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 5168 int r = kvm_vcpu_read_guest(vcpu, addr, val, bytes); 5169 5170 return r < 0 ? X86EMUL_IO_NEEDED : X86EMUL_CONTINUE; 5171 } 5172 5173 static int kvm_write_guest_virt_helper(gva_t addr, void *val, unsigned int bytes, 5174 struct kvm_vcpu *vcpu, u32 access, 5175 struct x86_exception *exception) 5176 { 5177 void *data = val; 5178 int r = X86EMUL_CONTINUE; 5179 5180 while (bytes) { 5181 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, 5182 access, 5183 exception); 5184 unsigned offset = addr & (PAGE_SIZE-1); 5185 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset); 5186 int ret; 5187 5188 if (gpa == UNMAPPED_GVA) 5189 return X86EMUL_PROPAGATE_FAULT; 5190 ret = kvm_vcpu_write_guest(vcpu, gpa, data, towrite); 5191 if (ret < 0) { 5192 r = X86EMUL_IO_NEEDED; 5193 goto out; 5194 } 5195 5196 bytes -= towrite; 5197 data += towrite; 5198 addr += towrite; 5199 } 5200 out: 5201 return r; 5202 } 5203 5204 static int emulator_write_std(struct x86_emulate_ctxt *ctxt, gva_t addr, void *val, 5205 unsigned int bytes, struct x86_exception *exception, 5206 bool system) 5207 { 5208 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 5209 u32 access = PFERR_WRITE_MASK; 5210 5211 if (!system && kvm_x86_ops->get_cpl(vcpu) == 3) 5212 access |= PFERR_USER_MASK; 5213 5214 return kvm_write_guest_virt_helper(addr, val, bytes, vcpu, 5215 access, exception); 5216 } 5217 5218 int kvm_write_guest_virt_system(struct kvm_vcpu *vcpu, gva_t addr, void *val, 5219 unsigned int bytes, struct x86_exception *exception) 5220 { 5221 /* kvm_write_guest_virt_system can pull in tons of pages. */ 5222 vcpu->arch.l1tf_flush_l1d = true; 5223 5224 return kvm_write_guest_virt_helper(addr, val, bytes, vcpu, 5225 PFERR_WRITE_MASK, exception); 5226 } 5227 EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system); 5228 5229 int handle_ud(struct kvm_vcpu *vcpu) 5230 { 5231 int emul_type = EMULTYPE_TRAP_UD; 5232 enum emulation_result er; 5233 char sig[5]; /* ud2; .ascii "kvm" */ 5234 struct x86_exception e; 5235 5236 if (force_emulation_prefix && 5237 kvm_read_guest_virt(vcpu, kvm_get_linear_rip(vcpu), 5238 sig, sizeof(sig), &e) == 0 && 5239 memcmp(sig, "\xf\xbkvm", sizeof(sig)) == 0) { 5240 kvm_rip_write(vcpu, kvm_rip_read(vcpu) + sizeof(sig)); 5241 emul_type = 0; 5242 } 5243 5244 er = kvm_emulate_instruction(vcpu, emul_type); 5245 if (er == EMULATE_USER_EXIT) 5246 return 0; 5247 if (er != EMULATE_DONE) 5248 kvm_queue_exception(vcpu, UD_VECTOR); 5249 return 1; 5250 } 5251 EXPORT_SYMBOL_GPL(handle_ud); 5252 5253 static int vcpu_is_mmio_gpa(struct kvm_vcpu *vcpu, unsigned long gva, 5254 gpa_t gpa, bool write) 5255 { 5256 /* For APIC access vmexit */ 5257 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE) 5258 return 1; 5259 5260 if (vcpu_match_mmio_gpa(vcpu, gpa)) { 5261 trace_vcpu_match_mmio(gva, gpa, write, true); 5262 return 1; 5263 } 5264 5265 return 0; 5266 } 5267 5268 static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva, 5269 gpa_t *gpa, struct x86_exception *exception, 5270 bool write) 5271 { 5272 u32 access = ((kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0) 5273 | (write ? PFERR_WRITE_MASK : 0); 5274 5275 /* 5276 * currently PKRU is only applied to ept enabled guest so 5277 * there is no pkey in EPT page table for L1 guest or EPT 5278 * shadow page table for L2 guest. 5279 */ 5280 if (vcpu_match_mmio_gva(vcpu, gva) 5281 && !permission_fault(vcpu, vcpu->arch.walk_mmu, 5282 vcpu->arch.access, 0, access)) { 5283 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT | 5284 (gva & (PAGE_SIZE - 1)); 5285 trace_vcpu_match_mmio(gva, *gpa, write, false); 5286 return 1; 5287 } 5288 5289 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception); 5290 5291 if (*gpa == UNMAPPED_GVA) 5292 return -1; 5293 5294 return vcpu_is_mmio_gpa(vcpu, gva, *gpa, write); 5295 } 5296 5297 int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa, 5298 const void *val, int bytes) 5299 { 5300 int ret; 5301 5302 ret = kvm_vcpu_write_guest(vcpu, gpa, val, bytes); 5303 if (ret < 0) 5304 return 0; 5305 kvm_page_track_write(vcpu, gpa, val, bytes); 5306 return 1; 5307 } 5308 5309 struct read_write_emulator_ops { 5310 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val, 5311 int bytes); 5312 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa, 5313 void *val, int bytes); 5314 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa, 5315 int bytes, void *val); 5316 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa, 5317 void *val, int bytes); 5318 bool write; 5319 }; 5320 5321 static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes) 5322 { 5323 if (vcpu->mmio_read_completed) { 5324 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes, 5325 vcpu->mmio_fragments[0].gpa, val); 5326 vcpu->mmio_read_completed = 0; 5327 return 1; 5328 } 5329 5330 return 0; 5331 } 5332 5333 static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa, 5334 void *val, int bytes) 5335 { 5336 return !kvm_vcpu_read_guest(vcpu, gpa, val, bytes); 5337 } 5338 5339 static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa, 5340 void *val, int bytes) 5341 { 5342 return emulator_write_phys(vcpu, gpa, val, bytes); 5343 } 5344 5345 static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val) 5346 { 5347 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, val); 5348 return vcpu_mmio_write(vcpu, gpa, bytes, val); 5349 } 5350 5351 static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, 5352 void *val, int bytes) 5353 { 5354 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, NULL); 5355 return X86EMUL_IO_NEEDED; 5356 } 5357 5358 static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, 5359 void *val, int bytes) 5360 { 5361 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0]; 5362 5363 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len)); 5364 return X86EMUL_CONTINUE; 5365 } 5366 5367 static const struct read_write_emulator_ops read_emultor = { 5368 .read_write_prepare = read_prepare, 5369 .read_write_emulate = read_emulate, 5370 .read_write_mmio = vcpu_mmio_read, 5371 .read_write_exit_mmio = read_exit_mmio, 5372 }; 5373 5374 static const struct read_write_emulator_ops write_emultor = { 5375 .read_write_emulate = write_emulate, 5376 .read_write_mmio = write_mmio, 5377 .read_write_exit_mmio = write_exit_mmio, 5378 .write = true, 5379 }; 5380 5381 static int emulator_read_write_onepage(unsigned long addr, void *val, 5382 unsigned int bytes, 5383 struct x86_exception *exception, 5384 struct kvm_vcpu *vcpu, 5385 const struct read_write_emulator_ops *ops) 5386 { 5387 gpa_t gpa; 5388 int handled, ret; 5389 bool write = ops->write; 5390 struct kvm_mmio_fragment *frag; 5391 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt; 5392 5393 /* 5394 * If the exit was due to a NPF we may already have a GPA. 5395 * If the GPA is present, use it to avoid the GVA to GPA table walk. 5396 * Note, this cannot be used on string operations since string 5397 * operation using rep will only have the initial GPA from the NPF 5398 * occurred. 5399 */ 5400 if (vcpu->arch.gpa_available && 5401 emulator_can_use_gpa(ctxt) && 5402 (addr & ~PAGE_MASK) == (vcpu->arch.gpa_val & ~PAGE_MASK)) { 5403 gpa = vcpu->arch.gpa_val; 5404 ret = vcpu_is_mmio_gpa(vcpu, addr, gpa, write); 5405 } else { 5406 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write); 5407 if (ret < 0) 5408 return X86EMUL_PROPAGATE_FAULT; 5409 } 5410 5411 if (!ret && ops->read_write_emulate(vcpu, gpa, val, bytes)) 5412 return X86EMUL_CONTINUE; 5413 5414 /* 5415 * Is this MMIO handled locally? 5416 */ 5417 handled = ops->read_write_mmio(vcpu, gpa, bytes, val); 5418 if (handled == bytes) 5419 return X86EMUL_CONTINUE; 5420 5421 gpa += handled; 5422 bytes -= handled; 5423 val += handled; 5424 5425 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS); 5426 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++]; 5427 frag->gpa = gpa; 5428 frag->data = val; 5429 frag->len = bytes; 5430 return X86EMUL_CONTINUE; 5431 } 5432 5433 static int emulator_read_write(struct x86_emulate_ctxt *ctxt, 5434 unsigned long addr, 5435 void *val, unsigned int bytes, 5436 struct x86_exception *exception, 5437 const struct read_write_emulator_ops *ops) 5438 { 5439 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 5440 gpa_t gpa; 5441 int rc; 5442 5443 if (ops->read_write_prepare && 5444 ops->read_write_prepare(vcpu, val, bytes)) 5445 return X86EMUL_CONTINUE; 5446 5447 vcpu->mmio_nr_fragments = 0; 5448 5449 /* Crossing a page boundary? */ 5450 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) { 5451 int now; 5452 5453 now = -addr & ~PAGE_MASK; 5454 rc = emulator_read_write_onepage(addr, val, now, exception, 5455 vcpu, ops); 5456 5457 if (rc != X86EMUL_CONTINUE) 5458 return rc; 5459 addr += now; 5460 if (ctxt->mode != X86EMUL_MODE_PROT64) 5461 addr = (u32)addr; 5462 val += now; 5463 bytes -= now; 5464 } 5465 5466 rc = emulator_read_write_onepage(addr, val, bytes, exception, 5467 vcpu, ops); 5468 if (rc != X86EMUL_CONTINUE) 5469 return rc; 5470 5471 if (!vcpu->mmio_nr_fragments) 5472 return rc; 5473 5474 gpa = vcpu->mmio_fragments[0].gpa; 5475 5476 vcpu->mmio_needed = 1; 5477 vcpu->mmio_cur_fragment = 0; 5478 5479 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len); 5480 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write; 5481 vcpu->run->exit_reason = KVM_EXIT_MMIO; 5482 vcpu->run->mmio.phys_addr = gpa; 5483 5484 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes); 5485 } 5486 5487 static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt, 5488 unsigned long addr, 5489 void *val, 5490 unsigned int bytes, 5491 struct x86_exception *exception) 5492 { 5493 return emulator_read_write(ctxt, addr, val, bytes, 5494 exception, &read_emultor); 5495 } 5496 5497 static int emulator_write_emulated(struct x86_emulate_ctxt *ctxt, 5498 unsigned long addr, 5499 const void *val, 5500 unsigned int bytes, 5501 struct x86_exception *exception) 5502 { 5503 return emulator_read_write(ctxt, addr, (void *)val, bytes, 5504 exception, &write_emultor); 5505 } 5506 5507 #define CMPXCHG_TYPE(t, ptr, old, new) \ 5508 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old)) 5509 5510 #ifdef CONFIG_X86_64 5511 # define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new) 5512 #else 5513 # define CMPXCHG64(ptr, old, new) \ 5514 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old)) 5515 #endif 5516 5517 static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt, 5518 unsigned long addr, 5519 const void *old, 5520 const void *new, 5521 unsigned int bytes, 5522 struct x86_exception *exception) 5523 { 5524 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 5525 gpa_t gpa; 5526 struct page *page; 5527 char *kaddr; 5528 bool exchanged; 5529 5530 /* guests cmpxchg8b have to be emulated atomically */ 5531 if (bytes > 8 || (bytes & (bytes - 1))) 5532 goto emul_write; 5533 5534 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL); 5535 5536 if (gpa == UNMAPPED_GVA || 5537 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE) 5538 goto emul_write; 5539 5540 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK)) 5541 goto emul_write; 5542 5543 page = kvm_vcpu_gfn_to_page(vcpu, gpa >> PAGE_SHIFT); 5544 if (is_error_page(page)) 5545 goto emul_write; 5546 5547 kaddr = kmap_atomic(page); 5548 kaddr += offset_in_page(gpa); 5549 switch (bytes) { 5550 case 1: 5551 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new); 5552 break; 5553 case 2: 5554 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new); 5555 break; 5556 case 4: 5557 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new); 5558 break; 5559 case 8: 5560 exchanged = CMPXCHG64(kaddr, old, new); 5561 break; 5562 default: 5563 BUG(); 5564 } 5565 kunmap_atomic(kaddr); 5566 kvm_release_page_dirty(page); 5567 5568 if (!exchanged) 5569 return X86EMUL_CMPXCHG_FAILED; 5570 5571 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT); 5572 kvm_page_track_write(vcpu, gpa, new, bytes); 5573 5574 return X86EMUL_CONTINUE; 5575 5576 emul_write: 5577 printk_once(KERN_WARNING "kvm: emulating exchange as write\n"); 5578 5579 return emulator_write_emulated(ctxt, addr, new, bytes, exception); 5580 } 5581 5582 static int kernel_pio(struct kvm_vcpu *vcpu, void *pd) 5583 { 5584 int r = 0, i; 5585 5586 for (i = 0; i < vcpu->arch.pio.count; i++) { 5587 if (vcpu->arch.pio.in) 5588 r = kvm_io_bus_read(vcpu, KVM_PIO_BUS, vcpu->arch.pio.port, 5589 vcpu->arch.pio.size, pd); 5590 else 5591 r = kvm_io_bus_write(vcpu, KVM_PIO_BUS, 5592 vcpu->arch.pio.port, vcpu->arch.pio.size, 5593 pd); 5594 if (r) 5595 break; 5596 pd += vcpu->arch.pio.size; 5597 } 5598 return r; 5599 } 5600 5601 static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size, 5602 unsigned short port, void *val, 5603 unsigned int count, bool in) 5604 { 5605 vcpu->arch.pio.port = port; 5606 vcpu->arch.pio.in = in; 5607 vcpu->arch.pio.count = count; 5608 vcpu->arch.pio.size = size; 5609 5610 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) { 5611 vcpu->arch.pio.count = 0; 5612 return 1; 5613 } 5614 5615 vcpu->run->exit_reason = KVM_EXIT_IO; 5616 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT; 5617 vcpu->run->io.size = size; 5618 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE; 5619 vcpu->run->io.count = count; 5620 vcpu->run->io.port = port; 5621 5622 return 0; 5623 } 5624 5625 static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt, 5626 int size, unsigned short port, void *val, 5627 unsigned int count) 5628 { 5629 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 5630 int ret; 5631 5632 if (vcpu->arch.pio.count) 5633 goto data_avail; 5634 5635 memset(vcpu->arch.pio_data, 0, size * count); 5636 5637 ret = emulator_pio_in_out(vcpu, size, port, val, count, true); 5638 if (ret) { 5639 data_avail: 5640 memcpy(val, vcpu->arch.pio_data, size * count); 5641 trace_kvm_pio(KVM_PIO_IN, port, size, count, vcpu->arch.pio_data); 5642 vcpu->arch.pio.count = 0; 5643 return 1; 5644 } 5645 5646 return 0; 5647 } 5648 5649 static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt, 5650 int size, unsigned short port, 5651 const void *val, unsigned int count) 5652 { 5653 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 5654 5655 memcpy(vcpu->arch.pio_data, val, size * count); 5656 trace_kvm_pio(KVM_PIO_OUT, port, size, count, vcpu->arch.pio_data); 5657 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false); 5658 } 5659 5660 static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg) 5661 { 5662 return kvm_x86_ops->get_segment_base(vcpu, seg); 5663 } 5664 5665 static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address) 5666 { 5667 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address); 5668 } 5669 5670 static int kvm_emulate_wbinvd_noskip(struct kvm_vcpu *vcpu) 5671 { 5672 if (!need_emulate_wbinvd(vcpu)) 5673 return X86EMUL_CONTINUE; 5674 5675 if (kvm_x86_ops->has_wbinvd_exit()) { 5676 int cpu = get_cpu(); 5677 5678 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask); 5679 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask, 5680 wbinvd_ipi, NULL, 1); 5681 put_cpu(); 5682 cpumask_clear(vcpu->arch.wbinvd_dirty_mask); 5683 } else 5684 wbinvd(); 5685 return X86EMUL_CONTINUE; 5686 } 5687 5688 int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu) 5689 { 5690 kvm_emulate_wbinvd_noskip(vcpu); 5691 return kvm_skip_emulated_instruction(vcpu); 5692 } 5693 EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd); 5694 5695 5696 5697 static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt) 5698 { 5699 kvm_emulate_wbinvd_noskip(emul_to_vcpu(ctxt)); 5700 } 5701 5702 static int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr, 5703 unsigned long *dest) 5704 { 5705 return kvm_get_dr(emul_to_vcpu(ctxt), dr, dest); 5706 } 5707 5708 static int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr, 5709 unsigned long value) 5710 { 5711 5712 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value); 5713 } 5714 5715 static u64 mk_cr_64(u64 curr_cr, u32 new_val) 5716 { 5717 return (curr_cr & ~((1ULL << 32) - 1)) | new_val; 5718 } 5719 5720 static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr) 5721 { 5722 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 5723 unsigned long value; 5724 5725 switch (cr) { 5726 case 0: 5727 value = kvm_read_cr0(vcpu); 5728 break; 5729 case 2: 5730 value = vcpu->arch.cr2; 5731 break; 5732 case 3: 5733 value = kvm_read_cr3(vcpu); 5734 break; 5735 case 4: 5736 value = kvm_read_cr4(vcpu); 5737 break; 5738 case 8: 5739 value = kvm_get_cr8(vcpu); 5740 break; 5741 default: 5742 kvm_err("%s: unexpected cr %u\n", __func__, cr); 5743 return 0; 5744 } 5745 5746 return value; 5747 } 5748 5749 static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val) 5750 { 5751 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 5752 int res = 0; 5753 5754 switch (cr) { 5755 case 0: 5756 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val)); 5757 break; 5758 case 2: 5759 vcpu->arch.cr2 = val; 5760 break; 5761 case 3: 5762 res = kvm_set_cr3(vcpu, val); 5763 break; 5764 case 4: 5765 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val)); 5766 break; 5767 case 8: 5768 res = kvm_set_cr8(vcpu, val); 5769 break; 5770 default: 5771 kvm_err("%s: unexpected cr %u\n", __func__, cr); 5772 res = -1; 5773 } 5774 5775 return res; 5776 } 5777 5778 static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt) 5779 { 5780 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt)); 5781 } 5782 5783 static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt) 5784 { 5785 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt); 5786 } 5787 5788 static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt) 5789 { 5790 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt); 5791 } 5792 5793 static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt) 5794 { 5795 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt); 5796 } 5797 5798 static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt) 5799 { 5800 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt); 5801 } 5802 5803 static unsigned long emulator_get_cached_segment_base( 5804 struct x86_emulate_ctxt *ctxt, int seg) 5805 { 5806 return get_segment_base(emul_to_vcpu(ctxt), seg); 5807 } 5808 5809 static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector, 5810 struct desc_struct *desc, u32 *base3, 5811 int seg) 5812 { 5813 struct kvm_segment var; 5814 5815 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg); 5816 *selector = var.selector; 5817 5818 if (var.unusable) { 5819 memset(desc, 0, sizeof(*desc)); 5820 if (base3) 5821 *base3 = 0; 5822 return false; 5823 } 5824 5825 if (var.g) 5826 var.limit >>= 12; 5827 set_desc_limit(desc, var.limit); 5828 set_desc_base(desc, (unsigned long)var.base); 5829 #ifdef CONFIG_X86_64 5830 if (base3) 5831 *base3 = var.base >> 32; 5832 #endif 5833 desc->type = var.type; 5834 desc->s = var.s; 5835 desc->dpl = var.dpl; 5836 desc->p = var.present; 5837 desc->avl = var.avl; 5838 desc->l = var.l; 5839 desc->d = var.db; 5840 desc->g = var.g; 5841 5842 return true; 5843 } 5844 5845 static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector, 5846 struct desc_struct *desc, u32 base3, 5847 int seg) 5848 { 5849 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 5850 struct kvm_segment var; 5851 5852 var.selector = selector; 5853 var.base = get_desc_base(desc); 5854 #ifdef CONFIG_X86_64 5855 var.base |= ((u64)base3) << 32; 5856 #endif 5857 var.limit = get_desc_limit(desc); 5858 if (desc->g) 5859 var.limit = (var.limit << 12) | 0xfff; 5860 var.type = desc->type; 5861 var.dpl = desc->dpl; 5862 var.db = desc->d; 5863 var.s = desc->s; 5864 var.l = desc->l; 5865 var.g = desc->g; 5866 var.avl = desc->avl; 5867 var.present = desc->p; 5868 var.unusable = !var.present; 5869 var.padding = 0; 5870 5871 kvm_set_segment(vcpu, &var, seg); 5872 return; 5873 } 5874 5875 static int emulator_get_msr(struct x86_emulate_ctxt *ctxt, 5876 u32 msr_index, u64 *pdata) 5877 { 5878 struct msr_data msr; 5879 int r; 5880 5881 msr.index = msr_index; 5882 msr.host_initiated = false; 5883 r = kvm_get_msr(emul_to_vcpu(ctxt), &msr); 5884 if (r) 5885 return r; 5886 5887 *pdata = msr.data; 5888 return 0; 5889 } 5890 5891 static int emulator_set_msr(struct x86_emulate_ctxt *ctxt, 5892 u32 msr_index, u64 data) 5893 { 5894 struct msr_data msr; 5895 5896 msr.data = data; 5897 msr.index = msr_index; 5898 msr.host_initiated = false; 5899 return kvm_set_msr(emul_to_vcpu(ctxt), &msr); 5900 } 5901 5902 static u64 emulator_get_smbase(struct x86_emulate_ctxt *ctxt) 5903 { 5904 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 5905 5906 return vcpu->arch.smbase; 5907 } 5908 5909 static void emulator_set_smbase(struct x86_emulate_ctxt *ctxt, u64 smbase) 5910 { 5911 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 5912 5913 vcpu->arch.smbase = smbase; 5914 } 5915 5916 static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt, 5917 u32 pmc) 5918 { 5919 return kvm_pmu_is_valid_msr_idx(emul_to_vcpu(ctxt), pmc); 5920 } 5921 5922 static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt, 5923 u32 pmc, u64 *pdata) 5924 { 5925 return kvm_pmu_rdpmc(emul_to_vcpu(ctxt), pmc, pdata); 5926 } 5927 5928 static void emulator_halt(struct x86_emulate_ctxt *ctxt) 5929 { 5930 emul_to_vcpu(ctxt)->arch.halt_request = 1; 5931 } 5932 5933 static int emulator_intercept(struct x86_emulate_ctxt *ctxt, 5934 struct x86_instruction_info *info, 5935 enum x86_intercept_stage stage) 5936 { 5937 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage); 5938 } 5939 5940 static bool emulator_get_cpuid(struct x86_emulate_ctxt *ctxt, 5941 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx, bool check_limit) 5942 { 5943 return kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx, check_limit); 5944 } 5945 5946 static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg) 5947 { 5948 return kvm_register_read(emul_to_vcpu(ctxt), reg); 5949 } 5950 5951 static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val) 5952 { 5953 kvm_register_write(emul_to_vcpu(ctxt), reg, val); 5954 } 5955 5956 static void emulator_set_nmi_mask(struct x86_emulate_ctxt *ctxt, bool masked) 5957 { 5958 kvm_x86_ops->set_nmi_mask(emul_to_vcpu(ctxt), masked); 5959 } 5960 5961 static unsigned emulator_get_hflags(struct x86_emulate_ctxt *ctxt) 5962 { 5963 return emul_to_vcpu(ctxt)->arch.hflags; 5964 } 5965 5966 static void emulator_set_hflags(struct x86_emulate_ctxt *ctxt, unsigned emul_flags) 5967 { 5968 emul_to_vcpu(ctxt)->arch.hflags = emul_flags; 5969 } 5970 5971 static int emulator_pre_leave_smm(struct x86_emulate_ctxt *ctxt, 5972 const char *smstate) 5973 { 5974 return kvm_x86_ops->pre_leave_smm(emul_to_vcpu(ctxt), smstate); 5975 } 5976 5977 static void emulator_post_leave_smm(struct x86_emulate_ctxt *ctxt) 5978 { 5979 kvm_smm_changed(emul_to_vcpu(ctxt)); 5980 } 5981 5982 static const struct x86_emulate_ops emulate_ops = { 5983 .read_gpr = emulator_read_gpr, 5984 .write_gpr = emulator_write_gpr, 5985 .read_std = emulator_read_std, 5986 .write_std = emulator_write_std, 5987 .read_phys = kvm_read_guest_phys_system, 5988 .fetch = kvm_fetch_guest_virt, 5989 .read_emulated = emulator_read_emulated, 5990 .write_emulated = emulator_write_emulated, 5991 .cmpxchg_emulated = emulator_cmpxchg_emulated, 5992 .invlpg = emulator_invlpg, 5993 .pio_in_emulated = emulator_pio_in_emulated, 5994 .pio_out_emulated = emulator_pio_out_emulated, 5995 .get_segment = emulator_get_segment, 5996 .set_segment = emulator_set_segment, 5997 .get_cached_segment_base = emulator_get_cached_segment_base, 5998 .get_gdt = emulator_get_gdt, 5999 .get_idt = emulator_get_idt, 6000 .set_gdt = emulator_set_gdt, 6001 .set_idt = emulator_set_idt, 6002 .get_cr = emulator_get_cr, 6003 .set_cr = emulator_set_cr, 6004 .cpl = emulator_get_cpl, 6005 .get_dr = emulator_get_dr, 6006 .set_dr = emulator_set_dr, 6007 .get_smbase = emulator_get_smbase, 6008 .set_smbase = emulator_set_smbase, 6009 .set_msr = emulator_set_msr, 6010 .get_msr = emulator_get_msr, 6011 .check_pmc = emulator_check_pmc, 6012 .read_pmc = emulator_read_pmc, 6013 .halt = emulator_halt, 6014 .wbinvd = emulator_wbinvd, 6015 .fix_hypercall = emulator_fix_hypercall, 6016 .intercept = emulator_intercept, 6017 .get_cpuid = emulator_get_cpuid, 6018 .set_nmi_mask = emulator_set_nmi_mask, 6019 .get_hflags = emulator_get_hflags, 6020 .set_hflags = emulator_set_hflags, 6021 .pre_leave_smm = emulator_pre_leave_smm, 6022 .post_leave_smm = emulator_post_leave_smm, 6023 }; 6024 6025 static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask) 6026 { 6027 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu); 6028 /* 6029 * an sti; sti; sequence only disable interrupts for the first 6030 * instruction. So, if the last instruction, be it emulated or 6031 * not, left the system with the INT_STI flag enabled, it 6032 * means that the last instruction is an sti. We should not 6033 * leave the flag on in this case. The same goes for mov ss 6034 */ 6035 if (int_shadow & mask) 6036 mask = 0; 6037 if (unlikely(int_shadow || mask)) { 6038 kvm_x86_ops->set_interrupt_shadow(vcpu, mask); 6039 if (!mask) 6040 kvm_make_request(KVM_REQ_EVENT, vcpu); 6041 } 6042 } 6043 6044 static bool inject_emulated_exception(struct kvm_vcpu *vcpu) 6045 { 6046 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt; 6047 if (ctxt->exception.vector == PF_VECTOR) 6048 return kvm_propagate_fault(vcpu, &ctxt->exception); 6049 6050 if (ctxt->exception.error_code_valid) 6051 kvm_queue_exception_e(vcpu, ctxt->exception.vector, 6052 ctxt->exception.error_code); 6053 else 6054 kvm_queue_exception(vcpu, ctxt->exception.vector); 6055 return false; 6056 } 6057 6058 static void init_emulate_ctxt(struct kvm_vcpu *vcpu) 6059 { 6060 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt; 6061 int cs_db, cs_l; 6062 6063 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l); 6064 6065 ctxt->eflags = kvm_get_rflags(vcpu); 6066 ctxt->tf = (ctxt->eflags & X86_EFLAGS_TF) != 0; 6067 6068 ctxt->eip = kvm_rip_read(vcpu); 6069 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL : 6070 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 : 6071 (cs_l && is_long_mode(vcpu)) ? X86EMUL_MODE_PROT64 : 6072 cs_db ? X86EMUL_MODE_PROT32 : 6073 X86EMUL_MODE_PROT16; 6074 BUILD_BUG_ON(HF_GUEST_MASK != X86EMUL_GUEST_MASK); 6075 BUILD_BUG_ON(HF_SMM_MASK != X86EMUL_SMM_MASK); 6076 BUILD_BUG_ON(HF_SMM_INSIDE_NMI_MASK != X86EMUL_SMM_INSIDE_NMI_MASK); 6077 6078 init_decode_cache(ctxt); 6079 vcpu->arch.emulate_regs_need_sync_from_vcpu = false; 6080 } 6081 6082 int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip) 6083 { 6084 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt; 6085 int ret; 6086 6087 init_emulate_ctxt(vcpu); 6088 6089 ctxt->op_bytes = 2; 6090 ctxt->ad_bytes = 2; 6091 ctxt->_eip = ctxt->eip + inc_eip; 6092 ret = emulate_int_real(ctxt, irq); 6093 6094 if (ret != X86EMUL_CONTINUE) 6095 return EMULATE_FAIL; 6096 6097 ctxt->eip = ctxt->_eip; 6098 kvm_rip_write(vcpu, ctxt->eip); 6099 kvm_set_rflags(vcpu, ctxt->eflags); 6100 6101 return EMULATE_DONE; 6102 } 6103 EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt); 6104 6105 static int handle_emulation_failure(struct kvm_vcpu *vcpu, int emulation_type) 6106 { 6107 int r = EMULATE_DONE; 6108 6109 ++vcpu->stat.insn_emulation_fail; 6110 trace_kvm_emulate_insn_failed(vcpu); 6111 6112 if (emulation_type & EMULTYPE_NO_UD_ON_FAIL) 6113 return EMULATE_FAIL; 6114 6115 if (!is_guest_mode(vcpu) && kvm_x86_ops->get_cpl(vcpu) == 0) { 6116 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR; 6117 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION; 6118 vcpu->run->internal.ndata = 0; 6119 r = EMULATE_USER_EXIT; 6120 } 6121 6122 kvm_queue_exception(vcpu, UD_VECTOR); 6123 6124 return r; 6125 } 6126 6127 static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t cr2, 6128 bool write_fault_to_shadow_pgtable, 6129 int emulation_type) 6130 { 6131 gpa_t gpa = cr2; 6132 kvm_pfn_t pfn; 6133 6134 if (!(emulation_type & EMULTYPE_ALLOW_RETRY)) 6135 return false; 6136 6137 if (WARN_ON_ONCE(is_guest_mode(vcpu))) 6138 return false; 6139 6140 if (!vcpu->arch.mmu->direct_map) { 6141 /* 6142 * Write permission should be allowed since only 6143 * write access need to be emulated. 6144 */ 6145 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL); 6146 6147 /* 6148 * If the mapping is invalid in guest, let cpu retry 6149 * it to generate fault. 6150 */ 6151 if (gpa == UNMAPPED_GVA) 6152 return true; 6153 } 6154 6155 /* 6156 * Do not retry the unhandleable instruction if it faults on the 6157 * readonly host memory, otherwise it will goto a infinite loop: 6158 * retry instruction -> write #PF -> emulation fail -> retry 6159 * instruction -> ... 6160 */ 6161 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa)); 6162 6163 /* 6164 * If the instruction failed on the error pfn, it can not be fixed, 6165 * report the error to userspace. 6166 */ 6167 if (is_error_noslot_pfn(pfn)) 6168 return false; 6169 6170 kvm_release_pfn_clean(pfn); 6171 6172 /* The instructions are well-emulated on direct mmu. */ 6173 if (vcpu->arch.mmu->direct_map) { 6174 unsigned int indirect_shadow_pages; 6175 6176 spin_lock(&vcpu->kvm->mmu_lock); 6177 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages; 6178 spin_unlock(&vcpu->kvm->mmu_lock); 6179 6180 if (indirect_shadow_pages) 6181 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa)); 6182 6183 return true; 6184 } 6185 6186 /* 6187 * if emulation was due to access to shadowed page table 6188 * and it failed try to unshadow page and re-enter the 6189 * guest to let CPU execute the instruction. 6190 */ 6191 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa)); 6192 6193 /* 6194 * If the access faults on its page table, it can not 6195 * be fixed by unprotecting shadow page and it should 6196 * be reported to userspace. 6197 */ 6198 return !write_fault_to_shadow_pgtable; 6199 } 6200 6201 static bool retry_instruction(struct x86_emulate_ctxt *ctxt, 6202 unsigned long cr2, int emulation_type) 6203 { 6204 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 6205 unsigned long last_retry_eip, last_retry_addr, gpa = cr2; 6206 6207 last_retry_eip = vcpu->arch.last_retry_eip; 6208 last_retry_addr = vcpu->arch.last_retry_addr; 6209 6210 /* 6211 * If the emulation is caused by #PF and it is non-page_table 6212 * writing instruction, it means the VM-EXIT is caused by shadow 6213 * page protected, we can zap the shadow page and retry this 6214 * instruction directly. 6215 * 6216 * Note: if the guest uses a non-page-table modifying instruction 6217 * on the PDE that points to the instruction, then we will unmap 6218 * the instruction and go to an infinite loop. So, we cache the 6219 * last retried eip and the last fault address, if we meet the eip 6220 * and the address again, we can break out of the potential infinite 6221 * loop. 6222 */ 6223 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0; 6224 6225 if (!(emulation_type & EMULTYPE_ALLOW_RETRY)) 6226 return false; 6227 6228 if (WARN_ON_ONCE(is_guest_mode(vcpu))) 6229 return false; 6230 6231 if (x86_page_table_writing_insn(ctxt)) 6232 return false; 6233 6234 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2) 6235 return false; 6236 6237 vcpu->arch.last_retry_eip = ctxt->eip; 6238 vcpu->arch.last_retry_addr = cr2; 6239 6240 if (!vcpu->arch.mmu->direct_map) 6241 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL); 6242 6243 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa)); 6244 6245 return true; 6246 } 6247 6248 static int complete_emulated_mmio(struct kvm_vcpu *vcpu); 6249 static int complete_emulated_pio(struct kvm_vcpu *vcpu); 6250 6251 static void kvm_smm_changed(struct kvm_vcpu *vcpu) 6252 { 6253 if (!(vcpu->arch.hflags & HF_SMM_MASK)) { 6254 /* This is a good place to trace that we are exiting SMM. */ 6255 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, false); 6256 6257 /* Process a latched INIT or SMI, if any. */ 6258 kvm_make_request(KVM_REQ_EVENT, vcpu); 6259 } 6260 6261 kvm_mmu_reset_context(vcpu); 6262 } 6263 6264 static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7, 6265 unsigned long *db) 6266 { 6267 u32 dr6 = 0; 6268 int i; 6269 u32 enable, rwlen; 6270 6271 enable = dr7; 6272 rwlen = dr7 >> 16; 6273 for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4) 6274 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr) 6275 dr6 |= (1 << i); 6276 return dr6; 6277 } 6278 6279 static void kvm_vcpu_do_singlestep(struct kvm_vcpu *vcpu, int *r) 6280 { 6281 struct kvm_run *kvm_run = vcpu->run; 6282 6283 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) { 6284 kvm_run->debug.arch.dr6 = DR6_BS | DR6_FIXED_1 | DR6_RTM; 6285 kvm_run->debug.arch.pc = vcpu->arch.singlestep_rip; 6286 kvm_run->debug.arch.exception = DB_VECTOR; 6287 kvm_run->exit_reason = KVM_EXIT_DEBUG; 6288 *r = EMULATE_USER_EXIT; 6289 } else { 6290 kvm_queue_exception_p(vcpu, DB_VECTOR, DR6_BS); 6291 } 6292 } 6293 6294 int kvm_skip_emulated_instruction(struct kvm_vcpu *vcpu) 6295 { 6296 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu); 6297 int r = EMULATE_DONE; 6298 6299 kvm_x86_ops->skip_emulated_instruction(vcpu); 6300 6301 /* 6302 * rflags is the old, "raw" value of the flags. The new value has 6303 * not been saved yet. 6304 * 6305 * This is correct even for TF set by the guest, because "the 6306 * processor will not generate this exception after the instruction 6307 * that sets the TF flag". 6308 */ 6309 if (unlikely(rflags & X86_EFLAGS_TF)) 6310 kvm_vcpu_do_singlestep(vcpu, &r); 6311 return r == EMULATE_DONE; 6312 } 6313 EXPORT_SYMBOL_GPL(kvm_skip_emulated_instruction); 6314 6315 static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r) 6316 { 6317 if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) && 6318 (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) { 6319 struct kvm_run *kvm_run = vcpu->run; 6320 unsigned long eip = kvm_get_linear_rip(vcpu); 6321 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0, 6322 vcpu->arch.guest_debug_dr7, 6323 vcpu->arch.eff_db); 6324 6325 if (dr6 != 0) { 6326 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1 | DR6_RTM; 6327 kvm_run->debug.arch.pc = eip; 6328 kvm_run->debug.arch.exception = DB_VECTOR; 6329 kvm_run->exit_reason = KVM_EXIT_DEBUG; 6330 *r = EMULATE_USER_EXIT; 6331 return true; 6332 } 6333 } 6334 6335 if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) && 6336 !(kvm_get_rflags(vcpu) & X86_EFLAGS_RF)) { 6337 unsigned long eip = kvm_get_linear_rip(vcpu); 6338 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0, 6339 vcpu->arch.dr7, 6340 vcpu->arch.db); 6341 6342 if (dr6 != 0) { 6343 vcpu->arch.dr6 &= ~15; 6344 vcpu->arch.dr6 |= dr6 | DR6_RTM; 6345 kvm_queue_exception(vcpu, DB_VECTOR); 6346 *r = EMULATE_DONE; 6347 return true; 6348 } 6349 } 6350 6351 return false; 6352 } 6353 6354 static bool is_vmware_backdoor_opcode(struct x86_emulate_ctxt *ctxt) 6355 { 6356 switch (ctxt->opcode_len) { 6357 case 1: 6358 switch (ctxt->b) { 6359 case 0xe4: /* IN */ 6360 case 0xe5: 6361 case 0xec: 6362 case 0xed: 6363 case 0xe6: /* OUT */ 6364 case 0xe7: 6365 case 0xee: 6366 case 0xef: 6367 case 0x6c: /* INS */ 6368 case 0x6d: 6369 case 0x6e: /* OUTS */ 6370 case 0x6f: 6371 return true; 6372 } 6373 break; 6374 case 2: 6375 switch (ctxt->b) { 6376 case 0x33: /* RDPMC */ 6377 return true; 6378 } 6379 break; 6380 } 6381 6382 return false; 6383 } 6384 6385 int x86_emulate_instruction(struct kvm_vcpu *vcpu, 6386 unsigned long cr2, 6387 int emulation_type, 6388 void *insn, 6389 int insn_len) 6390 { 6391 int r; 6392 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt; 6393 bool writeback = true; 6394 bool write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable; 6395 6396 vcpu->arch.l1tf_flush_l1d = true; 6397 6398 /* 6399 * Clear write_fault_to_shadow_pgtable here to ensure it is 6400 * never reused. 6401 */ 6402 vcpu->arch.write_fault_to_shadow_pgtable = false; 6403 kvm_clear_exception_queue(vcpu); 6404 6405 if (!(emulation_type & EMULTYPE_NO_DECODE)) { 6406 init_emulate_ctxt(vcpu); 6407 6408 /* 6409 * We will reenter on the same instruction since 6410 * we do not set complete_userspace_io. This does not 6411 * handle watchpoints yet, those would be handled in 6412 * the emulate_ops. 6413 */ 6414 if (!(emulation_type & EMULTYPE_SKIP) && 6415 kvm_vcpu_check_breakpoint(vcpu, &r)) 6416 return r; 6417 6418 ctxt->interruptibility = 0; 6419 ctxt->have_exception = false; 6420 ctxt->exception.vector = -1; 6421 ctxt->perm_ok = false; 6422 6423 ctxt->ud = emulation_type & EMULTYPE_TRAP_UD; 6424 6425 r = x86_decode_insn(ctxt, insn, insn_len); 6426 6427 trace_kvm_emulate_insn_start(vcpu); 6428 ++vcpu->stat.insn_emulation; 6429 if (r != EMULATION_OK) { 6430 if (emulation_type & EMULTYPE_TRAP_UD) 6431 return EMULATE_FAIL; 6432 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt, 6433 emulation_type)) 6434 return EMULATE_DONE; 6435 if (ctxt->have_exception && inject_emulated_exception(vcpu)) 6436 return EMULATE_DONE; 6437 if (emulation_type & EMULTYPE_SKIP) 6438 return EMULATE_FAIL; 6439 return handle_emulation_failure(vcpu, emulation_type); 6440 } 6441 } 6442 6443 if ((emulation_type & EMULTYPE_VMWARE) && 6444 !is_vmware_backdoor_opcode(ctxt)) 6445 return EMULATE_FAIL; 6446 6447 if (emulation_type & EMULTYPE_SKIP) { 6448 kvm_rip_write(vcpu, ctxt->_eip); 6449 if (ctxt->eflags & X86_EFLAGS_RF) 6450 kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF); 6451 return EMULATE_DONE; 6452 } 6453 6454 if (retry_instruction(ctxt, cr2, emulation_type)) 6455 return EMULATE_DONE; 6456 6457 /* this is needed for vmware backdoor interface to work since it 6458 changes registers values during IO operation */ 6459 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) { 6460 vcpu->arch.emulate_regs_need_sync_from_vcpu = false; 6461 emulator_invalidate_register_cache(ctxt); 6462 } 6463 6464 restart: 6465 /* Save the faulting GPA (cr2) in the address field */ 6466 ctxt->exception.address = cr2; 6467 6468 r = x86_emulate_insn(ctxt); 6469 6470 if (r == EMULATION_INTERCEPTED) 6471 return EMULATE_DONE; 6472 6473 if (r == EMULATION_FAILED) { 6474 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt, 6475 emulation_type)) 6476 return EMULATE_DONE; 6477 6478 return handle_emulation_failure(vcpu, emulation_type); 6479 } 6480 6481 if (ctxt->have_exception) { 6482 r = EMULATE_DONE; 6483 if (inject_emulated_exception(vcpu)) 6484 return r; 6485 } else if (vcpu->arch.pio.count) { 6486 if (!vcpu->arch.pio.in) { 6487 /* FIXME: return into emulator if single-stepping. */ 6488 vcpu->arch.pio.count = 0; 6489 } else { 6490 writeback = false; 6491 vcpu->arch.complete_userspace_io = complete_emulated_pio; 6492 } 6493 r = EMULATE_USER_EXIT; 6494 } else if (vcpu->mmio_needed) { 6495 if (!vcpu->mmio_is_write) 6496 writeback = false; 6497 r = EMULATE_USER_EXIT; 6498 vcpu->arch.complete_userspace_io = complete_emulated_mmio; 6499 } else if (r == EMULATION_RESTART) 6500 goto restart; 6501 else 6502 r = EMULATE_DONE; 6503 6504 if (writeback) { 6505 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu); 6506 toggle_interruptibility(vcpu, ctxt->interruptibility); 6507 vcpu->arch.emulate_regs_need_sync_to_vcpu = false; 6508 kvm_rip_write(vcpu, ctxt->eip); 6509 if (r == EMULATE_DONE && ctxt->tf) 6510 kvm_vcpu_do_singlestep(vcpu, &r); 6511 if (!ctxt->have_exception || 6512 exception_type(ctxt->exception.vector) == EXCPT_TRAP) 6513 __kvm_set_rflags(vcpu, ctxt->eflags); 6514 6515 /* 6516 * For STI, interrupts are shadowed; so KVM_REQ_EVENT will 6517 * do nothing, and it will be requested again as soon as 6518 * the shadow expires. But we still need to check here, 6519 * because POPF has no interrupt shadow. 6520 */ 6521 if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF)) 6522 kvm_make_request(KVM_REQ_EVENT, vcpu); 6523 } else 6524 vcpu->arch.emulate_regs_need_sync_to_vcpu = true; 6525 6526 return r; 6527 } 6528 6529 int kvm_emulate_instruction(struct kvm_vcpu *vcpu, int emulation_type) 6530 { 6531 return x86_emulate_instruction(vcpu, 0, emulation_type, NULL, 0); 6532 } 6533 EXPORT_SYMBOL_GPL(kvm_emulate_instruction); 6534 6535 int kvm_emulate_instruction_from_buffer(struct kvm_vcpu *vcpu, 6536 void *insn, int insn_len) 6537 { 6538 return x86_emulate_instruction(vcpu, 0, 0, insn, insn_len); 6539 } 6540 EXPORT_SYMBOL_GPL(kvm_emulate_instruction_from_buffer); 6541 6542 static int complete_fast_pio_out_port_0x7e(struct kvm_vcpu *vcpu) 6543 { 6544 vcpu->arch.pio.count = 0; 6545 return 1; 6546 } 6547 6548 static int complete_fast_pio_out(struct kvm_vcpu *vcpu) 6549 { 6550 vcpu->arch.pio.count = 0; 6551 6552 if (unlikely(!kvm_is_linear_rip(vcpu, vcpu->arch.pio.linear_rip))) 6553 return 1; 6554 6555 return kvm_skip_emulated_instruction(vcpu); 6556 } 6557 6558 static int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, 6559 unsigned short port) 6560 { 6561 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX); 6562 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt, 6563 size, port, &val, 1); 6564 if (ret) 6565 return ret; 6566 6567 /* 6568 * Workaround userspace that relies on old KVM behavior of %rip being 6569 * incremented prior to exiting to userspace to handle "OUT 0x7e". 6570 */ 6571 if (port == 0x7e && 6572 kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_OUT_7E_INC_RIP)) { 6573 vcpu->arch.complete_userspace_io = 6574 complete_fast_pio_out_port_0x7e; 6575 kvm_skip_emulated_instruction(vcpu); 6576 } else { 6577 vcpu->arch.pio.linear_rip = kvm_get_linear_rip(vcpu); 6578 vcpu->arch.complete_userspace_io = complete_fast_pio_out; 6579 } 6580 return 0; 6581 } 6582 6583 static int complete_fast_pio_in(struct kvm_vcpu *vcpu) 6584 { 6585 unsigned long val; 6586 6587 /* We should only ever be called with arch.pio.count equal to 1 */ 6588 BUG_ON(vcpu->arch.pio.count != 1); 6589 6590 if (unlikely(!kvm_is_linear_rip(vcpu, vcpu->arch.pio.linear_rip))) { 6591 vcpu->arch.pio.count = 0; 6592 return 1; 6593 } 6594 6595 /* For size less than 4 we merge, else we zero extend */ 6596 val = (vcpu->arch.pio.size < 4) ? kvm_register_read(vcpu, VCPU_REGS_RAX) 6597 : 0; 6598 6599 /* 6600 * Since vcpu->arch.pio.count == 1 let emulator_pio_in_emulated perform 6601 * the copy and tracing 6602 */ 6603 emulator_pio_in_emulated(&vcpu->arch.emulate_ctxt, vcpu->arch.pio.size, 6604 vcpu->arch.pio.port, &val, 1); 6605 kvm_register_write(vcpu, VCPU_REGS_RAX, val); 6606 6607 return kvm_skip_emulated_instruction(vcpu); 6608 } 6609 6610 static int kvm_fast_pio_in(struct kvm_vcpu *vcpu, int size, 6611 unsigned short port) 6612 { 6613 unsigned long val; 6614 int ret; 6615 6616 /* For size less than 4 we merge, else we zero extend */ 6617 val = (size < 4) ? kvm_register_read(vcpu, VCPU_REGS_RAX) : 0; 6618 6619 ret = emulator_pio_in_emulated(&vcpu->arch.emulate_ctxt, size, port, 6620 &val, 1); 6621 if (ret) { 6622 kvm_register_write(vcpu, VCPU_REGS_RAX, val); 6623 return ret; 6624 } 6625 6626 vcpu->arch.pio.linear_rip = kvm_get_linear_rip(vcpu); 6627 vcpu->arch.complete_userspace_io = complete_fast_pio_in; 6628 6629 return 0; 6630 } 6631 6632 int kvm_fast_pio(struct kvm_vcpu *vcpu, int size, unsigned short port, int in) 6633 { 6634 int ret; 6635 6636 if (in) 6637 ret = kvm_fast_pio_in(vcpu, size, port); 6638 else 6639 ret = kvm_fast_pio_out(vcpu, size, port); 6640 return ret && kvm_skip_emulated_instruction(vcpu); 6641 } 6642 EXPORT_SYMBOL_GPL(kvm_fast_pio); 6643 6644 static int kvmclock_cpu_down_prep(unsigned int cpu) 6645 { 6646 __this_cpu_write(cpu_tsc_khz, 0); 6647 return 0; 6648 } 6649 6650 static void tsc_khz_changed(void *data) 6651 { 6652 struct cpufreq_freqs *freq = data; 6653 unsigned long khz = 0; 6654 6655 if (data) 6656 khz = freq->new; 6657 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) 6658 khz = cpufreq_quick_get(raw_smp_processor_id()); 6659 if (!khz) 6660 khz = tsc_khz; 6661 __this_cpu_write(cpu_tsc_khz, khz); 6662 } 6663 6664 #ifdef CONFIG_X86_64 6665 static void kvm_hyperv_tsc_notifier(void) 6666 { 6667 struct kvm *kvm; 6668 struct kvm_vcpu *vcpu; 6669 int cpu; 6670 6671 spin_lock(&kvm_lock); 6672 list_for_each_entry(kvm, &vm_list, vm_list) 6673 kvm_make_mclock_inprogress_request(kvm); 6674 6675 hyperv_stop_tsc_emulation(); 6676 6677 /* TSC frequency always matches when on Hyper-V */ 6678 for_each_present_cpu(cpu) 6679 per_cpu(cpu_tsc_khz, cpu) = tsc_khz; 6680 kvm_max_guest_tsc_khz = tsc_khz; 6681 6682 list_for_each_entry(kvm, &vm_list, vm_list) { 6683 struct kvm_arch *ka = &kvm->arch; 6684 6685 spin_lock(&ka->pvclock_gtod_sync_lock); 6686 6687 pvclock_update_vm_gtod_copy(kvm); 6688 6689 kvm_for_each_vcpu(cpu, vcpu, kvm) 6690 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 6691 6692 kvm_for_each_vcpu(cpu, vcpu, kvm) 6693 kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu); 6694 6695 spin_unlock(&ka->pvclock_gtod_sync_lock); 6696 } 6697 spin_unlock(&kvm_lock); 6698 } 6699 #endif 6700 6701 static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val, 6702 void *data) 6703 { 6704 struct cpufreq_freqs *freq = data; 6705 struct kvm *kvm; 6706 struct kvm_vcpu *vcpu; 6707 int i, send_ipi = 0; 6708 6709 /* 6710 * We allow guests to temporarily run on slowing clocks, 6711 * provided we notify them after, or to run on accelerating 6712 * clocks, provided we notify them before. Thus time never 6713 * goes backwards. 6714 * 6715 * However, we have a problem. We can't atomically update 6716 * the frequency of a given CPU from this function; it is 6717 * merely a notifier, which can be called from any CPU. 6718 * Changing the TSC frequency at arbitrary points in time 6719 * requires a recomputation of local variables related to 6720 * the TSC for each VCPU. We must flag these local variables 6721 * to be updated and be sure the update takes place with the 6722 * new frequency before any guests proceed. 6723 * 6724 * Unfortunately, the combination of hotplug CPU and frequency 6725 * change creates an intractable locking scenario; the order 6726 * of when these callouts happen is undefined with respect to 6727 * CPU hotplug, and they can race with each other. As such, 6728 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is 6729 * undefined; you can actually have a CPU frequency change take 6730 * place in between the computation of X and the setting of the 6731 * variable. To protect against this problem, all updates of 6732 * the per_cpu tsc_khz variable are done in an interrupt 6733 * protected IPI, and all callers wishing to update the value 6734 * must wait for a synchronous IPI to complete (which is trivial 6735 * if the caller is on the CPU already). This establishes the 6736 * necessary total order on variable updates. 6737 * 6738 * Note that because a guest time update may take place 6739 * anytime after the setting of the VCPU's request bit, the 6740 * correct TSC value must be set before the request. However, 6741 * to ensure the update actually makes it to any guest which 6742 * starts running in hardware virtualization between the set 6743 * and the acquisition of the spinlock, we must also ping the 6744 * CPU after setting the request bit. 6745 * 6746 */ 6747 6748 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new) 6749 return 0; 6750 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new) 6751 return 0; 6752 6753 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1); 6754 6755 spin_lock(&kvm_lock); 6756 list_for_each_entry(kvm, &vm_list, vm_list) { 6757 kvm_for_each_vcpu(i, vcpu, kvm) { 6758 if (vcpu->cpu != freq->cpu) 6759 continue; 6760 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 6761 if (vcpu->cpu != smp_processor_id()) 6762 send_ipi = 1; 6763 } 6764 } 6765 spin_unlock(&kvm_lock); 6766 6767 if (freq->old < freq->new && send_ipi) { 6768 /* 6769 * We upscale the frequency. Must make the guest 6770 * doesn't see old kvmclock values while running with 6771 * the new frequency, otherwise we risk the guest sees 6772 * time go backwards. 6773 * 6774 * In case we update the frequency for another cpu 6775 * (which might be in guest context) send an interrupt 6776 * to kick the cpu out of guest context. Next time 6777 * guest context is entered kvmclock will be updated, 6778 * so the guest will not see stale values. 6779 */ 6780 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1); 6781 } 6782 return 0; 6783 } 6784 6785 static struct notifier_block kvmclock_cpufreq_notifier_block = { 6786 .notifier_call = kvmclock_cpufreq_notifier 6787 }; 6788 6789 static int kvmclock_cpu_online(unsigned int cpu) 6790 { 6791 tsc_khz_changed(NULL); 6792 return 0; 6793 } 6794 6795 static void kvm_timer_init(void) 6796 { 6797 max_tsc_khz = tsc_khz; 6798 6799 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) { 6800 #ifdef CONFIG_CPU_FREQ 6801 struct cpufreq_policy policy; 6802 int cpu; 6803 6804 memset(&policy, 0, sizeof(policy)); 6805 cpu = get_cpu(); 6806 cpufreq_get_policy(&policy, cpu); 6807 if (policy.cpuinfo.max_freq) 6808 max_tsc_khz = policy.cpuinfo.max_freq; 6809 put_cpu(); 6810 #endif 6811 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block, 6812 CPUFREQ_TRANSITION_NOTIFIER); 6813 } 6814 pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz); 6815 6816 cpuhp_setup_state(CPUHP_AP_X86_KVM_CLK_ONLINE, "x86/kvm/clk:online", 6817 kvmclock_cpu_online, kvmclock_cpu_down_prep); 6818 } 6819 6820 DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu); 6821 EXPORT_PER_CPU_SYMBOL_GPL(current_vcpu); 6822 6823 int kvm_is_in_guest(void) 6824 { 6825 return __this_cpu_read(current_vcpu) != NULL; 6826 } 6827 6828 static int kvm_is_user_mode(void) 6829 { 6830 int user_mode = 3; 6831 6832 if (__this_cpu_read(current_vcpu)) 6833 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu)); 6834 6835 return user_mode != 0; 6836 } 6837 6838 static unsigned long kvm_get_guest_ip(void) 6839 { 6840 unsigned long ip = 0; 6841 6842 if (__this_cpu_read(current_vcpu)) 6843 ip = kvm_rip_read(__this_cpu_read(current_vcpu)); 6844 6845 return ip; 6846 } 6847 6848 static struct perf_guest_info_callbacks kvm_guest_cbs = { 6849 .is_in_guest = kvm_is_in_guest, 6850 .is_user_mode = kvm_is_user_mode, 6851 .get_guest_ip = kvm_get_guest_ip, 6852 }; 6853 6854 static void kvm_set_mmio_spte_mask(void) 6855 { 6856 u64 mask; 6857 int maxphyaddr = boot_cpu_data.x86_phys_bits; 6858 6859 /* 6860 * Set the reserved bits and the present bit of an paging-structure 6861 * entry to generate page fault with PFER.RSV = 1. 6862 */ 6863 6864 /* 6865 * Mask the uppermost physical address bit, which would be reserved as 6866 * long as the supported physical address width is less than 52. 6867 */ 6868 mask = 1ull << 51; 6869 6870 /* Set the present bit. */ 6871 mask |= 1ull; 6872 6873 /* 6874 * If reserved bit is not supported, clear the present bit to disable 6875 * mmio page fault. 6876 */ 6877 if (IS_ENABLED(CONFIG_X86_64) && maxphyaddr == 52) 6878 mask &= ~1ull; 6879 6880 kvm_mmu_set_mmio_spte_mask(mask, mask); 6881 } 6882 6883 #ifdef CONFIG_X86_64 6884 static void pvclock_gtod_update_fn(struct work_struct *work) 6885 { 6886 struct kvm *kvm; 6887 6888 struct kvm_vcpu *vcpu; 6889 int i; 6890 6891 spin_lock(&kvm_lock); 6892 list_for_each_entry(kvm, &vm_list, vm_list) 6893 kvm_for_each_vcpu(i, vcpu, kvm) 6894 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu); 6895 atomic_set(&kvm_guest_has_master_clock, 0); 6896 spin_unlock(&kvm_lock); 6897 } 6898 6899 static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn); 6900 6901 /* 6902 * Notification about pvclock gtod data update. 6903 */ 6904 static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused, 6905 void *priv) 6906 { 6907 struct pvclock_gtod_data *gtod = &pvclock_gtod_data; 6908 struct timekeeper *tk = priv; 6909 6910 update_pvclock_gtod(tk); 6911 6912 /* disable master clock if host does not trust, or does not 6913 * use, TSC based clocksource. 6914 */ 6915 if (!gtod_is_based_on_tsc(gtod->clock.vclock_mode) && 6916 atomic_read(&kvm_guest_has_master_clock) != 0) 6917 queue_work(system_long_wq, &pvclock_gtod_work); 6918 6919 return 0; 6920 } 6921 6922 static struct notifier_block pvclock_gtod_notifier = { 6923 .notifier_call = pvclock_gtod_notify, 6924 }; 6925 #endif 6926 6927 int kvm_arch_init(void *opaque) 6928 { 6929 int r; 6930 struct kvm_x86_ops *ops = opaque; 6931 6932 if (kvm_x86_ops) { 6933 printk(KERN_ERR "kvm: already loaded the other module\n"); 6934 r = -EEXIST; 6935 goto out; 6936 } 6937 6938 if (!ops->cpu_has_kvm_support()) { 6939 printk(KERN_ERR "kvm: no hardware support\n"); 6940 r = -EOPNOTSUPP; 6941 goto out; 6942 } 6943 if (ops->disabled_by_bios()) { 6944 printk(KERN_ERR "kvm: disabled by bios\n"); 6945 r = -EOPNOTSUPP; 6946 goto out; 6947 } 6948 6949 /* 6950 * KVM explicitly assumes that the guest has an FPU and 6951 * FXSAVE/FXRSTOR. For example, the KVM_GET_FPU explicitly casts the 6952 * vCPU's FPU state as a fxregs_state struct. 6953 */ 6954 if (!boot_cpu_has(X86_FEATURE_FPU) || !boot_cpu_has(X86_FEATURE_FXSR)) { 6955 printk(KERN_ERR "kvm: inadequate fpu\n"); 6956 r = -EOPNOTSUPP; 6957 goto out; 6958 } 6959 6960 r = -ENOMEM; 6961 x86_fpu_cache = kmem_cache_create("x86_fpu", sizeof(struct fpu), 6962 __alignof__(struct fpu), SLAB_ACCOUNT, 6963 NULL); 6964 if (!x86_fpu_cache) { 6965 printk(KERN_ERR "kvm: failed to allocate cache for x86 fpu\n"); 6966 goto out; 6967 } 6968 6969 shared_msrs = alloc_percpu(struct kvm_shared_msrs); 6970 if (!shared_msrs) { 6971 printk(KERN_ERR "kvm: failed to allocate percpu kvm_shared_msrs\n"); 6972 goto out_free_x86_fpu_cache; 6973 } 6974 6975 r = kvm_mmu_module_init(); 6976 if (r) 6977 goto out_free_percpu; 6978 6979 kvm_set_mmio_spte_mask(); 6980 6981 kvm_x86_ops = ops; 6982 6983 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK, 6984 PT_DIRTY_MASK, PT64_NX_MASK, 0, 6985 PT_PRESENT_MASK, 0, sme_me_mask); 6986 kvm_timer_init(); 6987 6988 perf_register_guest_info_callbacks(&kvm_guest_cbs); 6989 6990 if (boot_cpu_has(X86_FEATURE_XSAVE)) 6991 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK); 6992 6993 kvm_lapic_init(); 6994 #ifdef CONFIG_X86_64 6995 pvclock_gtod_register_notifier(&pvclock_gtod_notifier); 6996 6997 if (hypervisor_is_type(X86_HYPER_MS_HYPERV)) 6998 set_hv_tscchange_cb(kvm_hyperv_tsc_notifier); 6999 #endif 7000 7001 return 0; 7002 7003 out_free_percpu: 7004 free_percpu(shared_msrs); 7005 out_free_x86_fpu_cache: 7006 kmem_cache_destroy(x86_fpu_cache); 7007 out: 7008 return r; 7009 } 7010 7011 void kvm_arch_exit(void) 7012 { 7013 #ifdef CONFIG_X86_64 7014 if (hypervisor_is_type(X86_HYPER_MS_HYPERV)) 7015 clear_hv_tscchange_cb(); 7016 #endif 7017 kvm_lapic_exit(); 7018 perf_unregister_guest_info_callbacks(&kvm_guest_cbs); 7019 7020 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) 7021 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block, 7022 CPUFREQ_TRANSITION_NOTIFIER); 7023 cpuhp_remove_state_nocalls(CPUHP_AP_X86_KVM_CLK_ONLINE); 7024 #ifdef CONFIG_X86_64 7025 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier); 7026 #endif 7027 kvm_x86_ops = NULL; 7028 kvm_mmu_module_exit(); 7029 free_percpu(shared_msrs); 7030 kmem_cache_destroy(x86_fpu_cache); 7031 } 7032 7033 int kvm_vcpu_halt(struct kvm_vcpu *vcpu) 7034 { 7035 ++vcpu->stat.halt_exits; 7036 if (lapic_in_kernel(vcpu)) { 7037 vcpu->arch.mp_state = KVM_MP_STATE_HALTED; 7038 return 1; 7039 } else { 7040 vcpu->run->exit_reason = KVM_EXIT_HLT; 7041 return 0; 7042 } 7043 } 7044 EXPORT_SYMBOL_GPL(kvm_vcpu_halt); 7045 7046 int kvm_emulate_halt(struct kvm_vcpu *vcpu) 7047 { 7048 int ret = kvm_skip_emulated_instruction(vcpu); 7049 /* 7050 * TODO: we might be squashing a GUESTDBG_SINGLESTEP-triggered 7051 * KVM_EXIT_DEBUG here. 7052 */ 7053 return kvm_vcpu_halt(vcpu) && ret; 7054 } 7055 EXPORT_SYMBOL_GPL(kvm_emulate_halt); 7056 7057 #ifdef CONFIG_X86_64 7058 static int kvm_pv_clock_pairing(struct kvm_vcpu *vcpu, gpa_t paddr, 7059 unsigned long clock_type) 7060 { 7061 struct kvm_clock_pairing clock_pairing; 7062 struct timespec64 ts; 7063 u64 cycle; 7064 int ret; 7065 7066 if (clock_type != KVM_CLOCK_PAIRING_WALLCLOCK) 7067 return -KVM_EOPNOTSUPP; 7068 7069 if (kvm_get_walltime_and_clockread(&ts, &cycle) == false) 7070 return -KVM_EOPNOTSUPP; 7071 7072 clock_pairing.sec = ts.tv_sec; 7073 clock_pairing.nsec = ts.tv_nsec; 7074 clock_pairing.tsc = kvm_read_l1_tsc(vcpu, cycle); 7075 clock_pairing.flags = 0; 7076 memset(&clock_pairing.pad, 0, sizeof(clock_pairing.pad)); 7077 7078 ret = 0; 7079 if (kvm_write_guest(vcpu->kvm, paddr, &clock_pairing, 7080 sizeof(struct kvm_clock_pairing))) 7081 ret = -KVM_EFAULT; 7082 7083 return ret; 7084 } 7085 #endif 7086 7087 /* 7088 * kvm_pv_kick_cpu_op: Kick a vcpu. 7089 * 7090 * @apicid - apicid of vcpu to be kicked. 7091 */ 7092 static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid) 7093 { 7094 struct kvm_lapic_irq lapic_irq; 7095 7096 lapic_irq.shorthand = 0; 7097 lapic_irq.dest_mode = 0; 7098 lapic_irq.level = 0; 7099 lapic_irq.dest_id = apicid; 7100 lapic_irq.msi_redir_hint = false; 7101 7102 lapic_irq.delivery_mode = APIC_DM_REMRD; 7103 kvm_irq_delivery_to_apic(kvm, NULL, &lapic_irq, NULL); 7104 } 7105 7106 void kvm_vcpu_deactivate_apicv(struct kvm_vcpu *vcpu) 7107 { 7108 if (!lapic_in_kernel(vcpu)) { 7109 WARN_ON_ONCE(vcpu->arch.apicv_active); 7110 return; 7111 } 7112 if (!vcpu->arch.apicv_active) 7113 return; 7114 7115 vcpu->arch.apicv_active = false; 7116 kvm_x86_ops->refresh_apicv_exec_ctrl(vcpu); 7117 } 7118 7119 int kvm_emulate_hypercall(struct kvm_vcpu *vcpu) 7120 { 7121 unsigned long nr, a0, a1, a2, a3, ret; 7122 int op_64_bit; 7123 7124 if (kvm_hv_hypercall_enabled(vcpu->kvm)) 7125 return kvm_hv_hypercall(vcpu); 7126 7127 nr = kvm_register_read(vcpu, VCPU_REGS_RAX); 7128 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX); 7129 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX); 7130 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX); 7131 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI); 7132 7133 trace_kvm_hypercall(nr, a0, a1, a2, a3); 7134 7135 op_64_bit = is_64_bit_mode(vcpu); 7136 if (!op_64_bit) { 7137 nr &= 0xFFFFFFFF; 7138 a0 &= 0xFFFFFFFF; 7139 a1 &= 0xFFFFFFFF; 7140 a2 &= 0xFFFFFFFF; 7141 a3 &= 0xFFFFFFFF; 7142 } 7143 7144 if (kvm_x86_ops->get_cpl(vcpu) != 0) { 7145 ret = -KVM_EPERM; 7146 goto out; 7147 } 7148 7149 switch (nr) { 7150 case KVM_HC_VAPIC_POLL_IRQ: 7151 ret = 0; 7152 break; 7153 case KVM_HC_KICK_CPU: 7154 kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1); 7155 ret = 0; 7156 break; 7157 #ifdef CONFIG_X86_64 7158 case KVM_HC_CLOCK_PAIRING: 7159 ret = kvm_pv_clock_pairing(vcpu, a0, a1); 7160 break; 7161 #endif 7162 case KVM_HC_SEND_IPI: 7163 ret = kvm_pv_send_ipi(vcpu->kvm, a0, a1, a2, a3, op_64_bit); 7164 break; 7165 default: 7166 ret = -KVM_ENOSYS; 7167 break; 7168 } 7169 out: 7170 if (!op_64_bit) 7171 ret = (u32)ret; 7172 kvm_register_write(vcpu, VCPU_REGS_RAX, ret); 7173 7174 ++vcpu->stat.hypercalls; 7175 return kvm_skip_emulated_instruction(vcpu); 7176 } 7177 EXPORT_SYMBOL_GPL(kvm_emulate_hypercall); 7178 7179 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt) 7180 { 7181 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 7182 char instruction[3]; 7183 unsigned long rip = kvm_rip_read(vcpu); 7184 7185 kvm_x86_ops->patch_hypercall(vcpu, instruction); 7186 7187 return emulator_write_emulated(ctxt, rip, instruction, 3, 7188 &ctxt->exception); 7189 } 7190 7191 static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu) 7192 { 7193 return vcpu->run->request_interrupt_window && 7194 likely(!pic_in_kernel(vcpu->kvm)); 7195 } 7196 7197 static void post_kvm_run_save(struct kvm_vcpu *vcpu) 7198 { 7199 struct kvm_run *kvm_run = vcpu->run; 7200 7201 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0; 7202 kvm_run->flags = is_smm(vcpu) ? KVM_RUN_X86_SMM : 0; 7203 kvm_run->cr8 = kvm_get_cr8(vcpu); 7204 kvm_run->apic_base = kvm_get_apic_base(vcpu); 7205 kvm_run->ready_for_interrupt_injection = 7206 pic_in_kernel(vcpu->kvm) || 7207 kvm_vcpu_ready_for_interrupt_injection(vcpu); 7208 } 7209 7210 static void update_cr8_intercept(struct kvm_vcpu *vcpu) 7211 { 7212 int max_irr, tpr; 7213 7214 if (!kvm_x86_ops->update_cr8_intercept) 7215 return; 7216 7217 if (!lapic_in_kernel(vcpu)) 7218 return; 7219 7220 if (vcpu->arch.apicv_active) 7221 return; 7222 7223 if (!vcpu->arch.apic->vapic_addr) 7224 max_irr = kvm_lapic_find_highest_irr(vcpu); 7225 else 7226 max_irr = -1; 7227 7228 if (max_irr != -1) 7229 max_irr >>= 4; 7230 7231 tpr = kvm_lapic_get_cr8(vcpu); 7232 7233 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr); 7234 } 7235 7236 static int inject_pending_event(struct kvm_vcpu *vcpu, bool req_int_win) 7237 { 7238 int r; 7239 7240 /* try to reinject previous events if any */ 7241 7242 if (vcpu->arch.exception.injected) 7243 kvm_x86_ops->queue_exception(vcpu); 7244 /* 7245 * Do not inject an NMI or interrupt if there is a pending 7246 * exception. Exceptions and interrupts are recognized at 7247 * instruction boundaries, i.e. the start of an instruction. 7248 * Trap-like exceptions, e.g. #DB, have higher priority than 7249 * NMIs and interrupts, i.e. traps are recognized before an 7250 * NMI/interrupt that's pending on the same instruction. 7251 * Fault-like exceptions, e.g. #GP and #PF, are the lowest 7252 * priority, but are only generated (pended) during instruction 7253 * execution, i.e. a pending fault-like exception means the 7254 * fault occurred on the *previous* instruction and must be 7255 * serviced prior to recognizing any new events in order to 7256 * fully complete the previous instruction. 7257 */ 7258 else if (!vcpu->arch.exception.pending) { 7259 if (vcpu->arch.nmi_injected) 7260 kvm_x86_ops->set_nmi(vcpu); 7261 else if (vcpu->arch.interrupt.injected) 7262 kvm_x86_ops->set_irq(vcpu); 7263 } 7264 7265 /* 7266 * Call check_nested_events() even if we reinjected a previous event 7267 * in order for caller to determine if it should require immediate-exit 7268 * from L2 to L1 due to pending L1 events which require exit 7269 * from L2 to L1. 7270 */ 7271 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) { 7272 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win); 7273 if (r != 0) 7274 return r; 7275 } 7276 7277 /* try to inject new event if pending */ 7278 if (vcpu->arch.exception.pending) { 7279 trace_kvm_inj_exception(vcpu->arch.exception.nr, 7280 vcpu->arch.exception.has_error_code, 7281 vcpu->arch.exception.error_code); 7282 7283 WARN_ON_ONCE(vcpu->arch.exception.injected); 7284 vcpu->arch.exception.pending = false; 7285 vcpu->arch.exception.injected = true; 7286 7287 if (exception_type(vcpu->arch.exception.nr) == EXCPT_FAULT) 7288 __kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) | 7289 X86_EFLAGS_RF); 7290 7291 if (vcpu->arch.exception.nr == DB_VECTOR) { 7292 /* 7293 * This code assumes that nSVM doesn't use 7294 * check_nested_events(). If it does, the 7295 * DR6/DR7 changes should happen before L1 7296 * gets a #VMEXIT for an intercepted #DB in 7297 * L2. (Under VMX, on the other hand, the 7298 * DR6/DR7 changes should not happen in the 7299 * event of a VM-exit to L1 for an intercepted 7300 * #DB in L2.) 7301 */ 7302 kvm_deliver_exception_payload(vcpu); 7303 if (vcpu->arch.dr7 & DR7_GD) { 7304 vcpu->arch.dr7 &= ~DR7_GD; 7305 kvm_update_dr7(vcpu); 7306 } 7307 } 7308 7309 kvm_x86_ops->queue_exception(vcpu); 7310 } 7311 7312 /* Don't consider new event if we re-injected an event */ 7313 if (kvm_event_needs_reinjection(vcpu)) 7314 return 0; 7315 7316 if (vcpu->arch.smi_pending && !is_smm(vcpu) && 7317 kvm_x86_ops->smi_allowed(vcpu)) { 7318 vcpu->arch.smi_pending = false; 7319 ++vcpu->arch.smi_count; 7320 enter_smm(vcpu); 7321 } else if (vcpu->arch.nmi_pending && kvm_x86_ops->nmi_allowed(vcpu)) { 7322 --vcpu->arch.nmi_pending; 7323 vcpu->arch.nmi_injected = true; 7324 kvm_x86_ops->set_nmi(vcpu); 7325 } else if (kvm_cpu_has_injectable_intr(vcpu)) { 7326 /* 7327 * Because interrupts can be injected asynchronously, we are 7328 * calling check_nested_events again here to avoid a race condition. 7329 * See https://lkml.org/lkml/2014/7/2/60 for discussion about this 7330 * proposal and current concerns. Perhaps we should be setting 7331 * KVM_REQ_EVENT only on certain events and not unconditionally? 7332 */ 7333 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) { 7334 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win); 7335 if (r != 0) 7336 return r; 7337 } 7338 if (kvm_x86_ops->interrupt_allowed(vcpu)) { 7339 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu), 7340 false); 7341 kvm_x86_ops->set_irq(vcpu); 7342 } 7343 } 7344 7345 return 0; 7346 } 7347 7348 static void process_nmi(struct kvm_vcpu *vcpu) 7349 { 7350 unsigned limit = 2; 7351 7352 /* 7353 * x86 is limited to one NMI running, and one NMI pending after it. 7354 * If an NMI is already in progress, limit further NMIs to just one. 7355 * Otherwise, allow two (and we'll inject the first one immediately). 7356 */ 7357 if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected) 7358 limit = 1; 7359 7360 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0); 7361 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit); 7362 kvm_make_request(KVM_REQ_EVENT, vcpu); 7363 } 7364 7365 static u32 enter_smm_get_segment_flags(struct kvm_segment *seg) 7366 { 7367 u32 flags = 0; 7368 flags |= seg->g << 23; 7369 flags |= seg->db << 22; 7370 flags |= seg->l << 21; 7371 flags |= seg->avl << 20; 7372 flags |= seg->present << 15; 7373 flags |= seg->dpl << 13; 7374 flags |= seg->s << 12; 7375 flags |= seg->type << 8; 7376 return flags; 7377 } 7378 7379 static void enter_smm_save_seg_32(struct kvm_vcpu *vcpu, char *buf, int n) 7380 { 7381 struct kvm_segment seg; 7382 int offset; 7383 7384 kvm_get_segment(vcpu, &seg, n); 7385 put_smstate(u32, buf, 0x7fa8 + n * 4, seg.selector); 7386 7387 if (n < 3) 7388 offset = 0x7f84 + n * 12; 7389 else 7390 offset = 0x7f2c + (n - 3) * 12; 7391 7392 put_smstate(u32, buf, offset + 8, seg.base); 7393 put_smstate(u32, buf, offset + 4, seg.limit); 7394 put_smstate(u32, buf, offset, enter_smm_get_segment_flags(&seg)); 7395 } 7396 7397 #ifdef CONFIG_X86_64 7398 static void enter_smm_save_seg_64(struct kvm_vcpu *vcpu, char *buf, int n) 7399 { 7400 struct kvm_segment seg; 7401 int offset; 7402 u16 flags; 7403 7404 kvm_get_segment(vcpu, &seg, n); 7405 offset = 0x7e00 + n * 16; 7406 7407 flags = enter_smm_get_segment_flags(&seg) >> 8; 7408 put_smstate(u16, buf, offset, seg.selector); 7409 put_smstate(u16, buf, offset + 2, flags); 7410 put_smstate(u32, buf, offset + 4, seg.limit); 7411 put_smstate(u64, buf, offset + 8, seg.base); 7412 } 7413 #endif 7414 7415 static void enter_smm_save_state_32(struct kvm_vcpu *vcpu, char *buf) 7416 { 7417 struct desc_ptr dt; 7418 struct kvm_segment seg; 7419 unsigned long val; 7420 int i; 7421 7422 put_smstate(u32, buf, 0x7ffc, kvm_read_cr0(vcpu)); 7423 put_smstate(u32, buf, 0x7ff8, kvm_read_cr3(vcpu)); 7424 put_smstate(u32, buf, 0x7ff4, kvm_get_rflags(vcpu)); 7425 put_smstate(u32, buf, 0x7ff0, kvm_rip_read(vcpu)); 7426 7427 for (i = 0; i < 8; i++) 7428 put_smstate(u32, buf, 0x7fd0 + i * 4, kvm_register_read(vcpu, i)); 7429 7430 kvm_get_dr(vcpu, 6, &val); 7431 put_smstate(u32, buf, 0x7fcc, (u32)val); 7432 kvm_get_dr(vcpu, 7, &val); 7433 put_smstate(u32, buf, 0x7fc8, (u32)val); 7434 7435 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR); 7436 put_smstate(u32, buf, 0x7fc4, seg.selector); 7437 put_smstate(u32, buf, 0x7f64, seg.base); 7438 put_smstate(u32, buf, 0x7f60, seg.limit); 7439 put_smstate(u32, buf, 0x7f5c, enter_smm_get_segment_flags(&seg)); 7440 7441 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR); 7442 put_smstate(u32, buf, 0x7fc0, seg.selector); 7443 put_smstate(u32, buf, 0x7f80, seg.base); 7444 put_smstate(u32, buf, 0x7f7c, seg.limit); 7445 put_smstate(u32, buf, 0x7f78, enter_smm_get_segment_flags(&seg)); 7446 7447 kvm_x86_ops->get_gdt(vcpu, &dt); 7448 put_smstate(u32, buf, 0x7f74, dt.address); 7449 put_smstate(u32, buf, 0x7f70, dt.size); 7450 7451 kvm_x86_ops->get_idt(vcpu, &dt); 7452 put_smstate(u32, buf, 0x7f58, dt.address); 7453 put_smstate(u32, buf, 0x7f54, dt.size); 7454 7455 for (i = 0; i < 6; i++) 7456 enter_smm_save_seg_32(vcpu, buf, i); 7457 7458 put_smstate(u32, buf, 0x7f14, kvm_read_cr4(vcpu)); 7459 7460 /* revision id */ 7461 put_smstate(u32, buf, 0x7efc, 0x00020000); 7462 put_smstate(u32, buf, 0x7ef8, vcpu->arch.smbase); 7463 } 7464 7465 #ifdef CONFIG_X86_64 7466 static void enter_smm_save_state_64(struct kvm_vcpu *vcpu, char *buf) 7467 { 7468 struct desc_ptr dt; 7469 struct kvm_segment seg; 7470 unsigned long val; 7471 int i; 7472 7473 for (i = 0; i < 16; i++) 7474 put_smstate(u64, buf, 0x7ff8 - i * 8, kvm_register_read(vcpu, i)); 7475 7476 put_smstate(u64, buf, 0x7f78, kvm_rip_read(vcpu)); 7477 put_smstate(u32, buf, 0x7f70, kvm_get_rflags(vcpu)); 7478 7479 kvm_get_dr(vcpu, 6, &val); 7480 put_smstate(u64, buf, 0x7f68, val); 7481 kvm_get_dr(vcpu, 7, &val); 7482 put_smstate(u64, buf, 0x7f60, val); 7483 7484 put_smstate(u64, buf, 0x7f58, kvm_read_cr0(vcpu)); 7485 put_smstate(u64, buf, 0x7f50, kvm_read_cr3(vcpu)); 7486 put_smstate(u64, buf, 0x7f48, kvm_read_cr4(vcpu)); 7487 7488 put_smstate(u32, buf, 0x7f00, vcpu->arch.smbase); 7489 7490 /* revision id */ 7491 put_smstate(u32, buf, 0x7efc, 0x00020064); 7492 7493 put_smstate(u64, buf, 0x7ed0, vcpu->arch.efer); 7494 7495 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR); 7496 put_smstate(u16, buf, 0x7e90, seg.selector); 7497 put_smstate(u16, buf, 0x7e92, enter_smm_get_segment_flags(&seg) >> 8); 7498 put_smstate(u32, buf, 0x7e94, seg.limit); 7499 put_smstate(u64, buf, 0x7e98, seg.base); 7500 7501 kvm_x86_ops->get_idt(vcpu, &dt); 7502 put_smstate(u32, buf, 0x7e84, dt.size); 7503 put_smstate(u64, buf, 0x7e88, dt.address); 7504 7505 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR); 7506 put_smstate(u16, buf, 0x7e70, seg.selector); 7507 put_smstate(u16, buf, 0x7e72, enter_smm_get_segment_flags(&seg) >> 8); 7508 put_smstate(u32, buf, 0x7e74, seg.limit); 7509 put_smstate(u64, buf, 0x7e78, seg.base); 7510 7511 kvm_x86_ops->get_gdt(vcpu, &dt); 7512 put_smstate(u32, buf, 0x7e64, dt.size); 7513 put_smstate(u64, buf, 0x7e68, dt.address); 7514 7515 for (i = 0; i < 6; i++) 7516 enter_smm_save_seg_64(vcpu, buf, i); 7517 } 7518 #endif 7519 7520 static void enter_smm(struct kvm_vcpu *vcpu) 7521 { 7522 struct kvm_segment cs, ds; 7523 struct desc_ptr dt; 7524 char buf[512]; 7525 u32 cr0; 7526 7527 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, true); 7528 memset(buf, 0, 512); 7529 #ifdef CONFIG_X86_64 7530 if (guest_cpuid_has(vcpu, X86_FEATURE_LM)) 7531 enter_smm_save_state_64(vcpu, buf); 7532 else 7533 #endif 7534 enter_smm_save_state_32(vcpu, buf); 7535 7536 /* 7537 * Give pre_enter_smm() a chance to make ISA-specific changes to the 7538 * vCPU state (e.g. leave guest mode) after we've saved the state into 7539 * the SMM state-save area. 7540 */ 7541 kvm_x86_ops->pre_enter_smm(vcpu, buf); 7542 7543 vcpu->arch.hflags |= HF_SMM_MASK; 7544 kvm_vcpu_write_guest(vcpu, vcpu->arch.smbase + 0xfe00, buf, sizeof(buf)); 7545 7546 if (kvm_x86_ops->get_nmi_mask(vcpu)) 7547 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK; 7548 else 7549 kvm_x86_ops->set_nmi_mask(vcpu, true); 7550 7551 kvm_set_rflags(vcpu, X86_EFLAGS_FIXED); 7552 kvm_rip_write(vcpu, 0x8000); 7553 7554 cr0 = vcpu->arch.cr0 & ~(X86_CR0_PE | X86_CR0_EM | X86_CR0_TS | X86_CR0_PG); 7555 kvm_x86_ops->set_cr0(vcpu, cr0); 7556 vcpu->arch.cr0 = cr0; 7557 7558 kvm_x86_ops->set_cr4(vcpu, 0); 7559 7560 /* Undocumented: IDT limit is set to zero on entry to SMM. */ 7561 dt.address = dt.size = 0; 7562 kvm_x86_ops->set_idt(vcpu, &dt); 7563 7564 __kvm_set_dr(vcpu, 7, DR7_FIXED_1); 7565 7566 cs.selector = (vcpu->arch.smbase >> 4) & 0xffff; 7567 cs.base = vcpu->arch.smbase; 7568 7569 ds.selector = 0; 7570 ds.base = 0; 7571 7572 cs.limit = ds.limit = 0xffffffff; 7573 cs.type = ds.type = 0x3; 7574 cs.dpl = ds.dpl = 0; 7575 cs.db = ds.db = 0; 7576 cs.s = ds.s = 1; 7577 cs.l = ds.l = 0; 7578 cs.g = ds.g = 1; 7579 cs.avl = ds.avl = 0; 7580 cs.present = ds.present = 1; 7581 cs.unusable = ds.unusable = 0; 7582 cs.padding = ds.padding = 0; 7583 7584 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS); 7585 kvm_set_segment(vcpu, &ds, VCPU_SREG_DS); 7586 kvm_set_segment(vcpu, &ds, VCPU_SREG_ES); 7587 kvm_set_segment(vcpu, &ds, VCPU_SREG_FS); 7588 kvm_set_segment(vcpu, &ds, VCPU_SREG_GS); 7589 kvm_set_segment(vcpu, &ds, VCPU_SREG_SS); 7590 7591 #ifdef CONFIG_X86_64 7592 if (guest_cpuid_has(vcpu, X86_FEATURE_LM)) 7593 kvm_x86_ops->set_efer(vcpu, 0); 7594 #endif 7595 7596 kvm_update_cpuid(vcpu); 7597 kvm_mmu_reset_context(vcpu); 7598 } 7599 7600 static void process_smi(struct kvm_vcpu *vcpu) 7601 { 7602 vcpu->arch.smi_pending = true; 7603 kvm_make_request(KVM_REQ_EVENT, vcpu); 7604 } 7605 7606 void kvm_make_scan_ioapic_request(struct kvm *kvm) 7607 { 7608 kvm_make_all_cpus_request(kvm, KVM_REQ_SCAN_IOAPIC); 7609 } 7610 7611 static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu) 7612 { 7613 if (!kvm_apic_present(vcpu)) 7614 return; 7615 7616 bitmap_zero(vcpu->arch.ioapic_handled_vectors, 256); 7617 7618 if (irqchip_split(vcpu->kvm)) 7619 kvm_scan_ioapic_routes(vcpu, vcpu->arch.ioapic_handled_vectors); 7620 else { 7621 if (vcpu->arch.apicv_active) 7622 kvm_x86_ops->sync_pir_to_irr(vcpu); 7623 if (ioapic_in_kernel(vcpu->kvm)) 7624 kvm_ioapic_scan_entry(vcpu, vcpu->arch.ioapic_handled_vectors); 7625 } 7626 7627 if (is_guest_mode(vcpu)) 7628 vcpu->arch.load_eoi_exitmap_pending = true; 7629 else 7630 kvm_make_request(KVM_REQ_LOAD_EOI_EXITMAP, vcpu); 7631 } 7632 7633 static void vcpu_load_eoi_exitmap(struct kvm_vcpu *vcpu) 7634 { 7635 u64 eoi_exit_bitmap[4]; 7636 7637 if (!kvm_apic_hw_enabled(vcpu->arch.apic)) 7638 return; 7639 7640 bitmap_or((ulong *)eoi_exit_bitmap, vcpu->arch.ioapic_handled_vectors, 7641 vcpu_to_synic(vcpu)->vec_bitmap, 256); 7642 kvm_x86_ops->load_eoi_exitmap(vcpu, eoi_exit_bitmap); 7643 } 7644 7645 int kvm_arch_mmu_notifier_invalidate_range(struct kvm *kvm, 7646 unsigned long start, unsigned long end, 7647 bool blockable) 7648 { 7649 unsigned long apic_address; 7650 7651 /* 7652 * The physical address of apic access page is stored in the VMCS. 7653 * Update it when it becomes invalid. 7654 */ 7655 apic_address = gfn_to_hva(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT); 7656 if (start <= apic_address && apic_address < end) 7657 kvm_make_all_cpus_request(kvm, KVM_REQ_APIC_PAGE_RELOAD); 7658 7659 return 0; 7660 } 7661 7662 void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu) 7663 { 7664 struct page *page = NULL; 7665 7666 if (!lapic_in_kernel(vcpu)) 7667 return; 7668 7669 if (!kvm_x86_ops->set_apic_access_page_addr) 7670 return; 7671 7672 page = gfn_to_page(vcpu->kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT); 7673 if (is_error_page(page)) 7674 return; 7675 kvm_x86_ops->set_apic_access_page_addr(vcpu, page_to_phys(page)); 7676 7677 /* 7678 * Do not pin apic access page in memory, the MMU notifier 7679 * will call us again if it is migrated or swapped out. 7680 */ 7681 put_page(page); 7682 } 7683 EXPORT_SYMBOL_GPL(kvm_vcpu_reload_apic_access_page); 7684 7685 void __kvm_request_immediate_exit(struct kvm_vcpu *vcpu) 7686 { 7687 smp_send_reschedule(vcpu->cpu); 7688 } 7689 EXPORT_SYMBOL_GPL(__kvm_request_immediate_exit); 7690 7691 /* 7692 * Returns 1 to let vcpu_run() continue the guest execution loop without 7693 * exiting to the userspace. Otherwise, the value will be returned to the 7694 * userspace. 7695 */ 7696 static int vcpu_enter_guest(struct kvm_vcpu *vcpu) 7697 { 7698 int r; 7699 bool req_int_win = 7700 dm_request_for_irq_injection(vcpu) && 7701 kvm_cpu_accept_dm_intr(vcpu); 7702 7703 bool req_immediate_exit = false; 7704 7705 if (kvm_request_pending(vcpu)) { 7706 if (kvm_check_request(KVM_REQ_GET_VMCS12_PAGES, vcpu)) 7707 kvm_x86_ops->get_vmcs12_pages(vcpu); 7708 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu)) 7709 kvm_mmu_unload(vcpu); 7710 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu)) 7711 __kvm_migrate_timers(vcpu); 7712 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu)) 7713 kvm_gen_update_masterclock(vcpu->kvm); 7714 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu)) 7715 kvm_gen_kvmclock_update(vcpu); 7716 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) { 7717 r = kvm_guest_time_update(vcpu); 7718 if (unlikely(r)) 7719 goto out; 7720 } 7721 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu)) 7722 kvm_mmu_sync_roots(vcpu); 7723 if (kvm_check_request(KVM_REQ_LOAD_CR3, vcpu)) 7724 kvm_mmu_load_cr3(vcpu); 7725 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu)) 7726 kvm_vcpu_flush_tlb(vcpu, true); 7727 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) { 7728 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS; 7729 r = 0; 7730 goto out; 7731 } 7732 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) { 7733 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN; 7734 vcpu->mmio_needed = 0; 7735 r = 0; 7736 goto out; 7737 } 7738 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) { 7739 /* Page is swapped out. Do synthetic halt */ 7740 vcpu->arch.apf.halted = true; 7741 r = 1; 7742 goto out; 7743 } 7744 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu)) 7745 record_steal_time(vcpu); 7746 if (kvm_check_request(KVM_REQ_SMI, vcpu)) 7747 process_smi(vcpu); 7748 if (kvm_check_request(KVM_REQ_NMI, vcpu)) 7749 process_nmi(vcpu); 7750 if (kvm_check_request(KVM_REQ_PMU, vcpu)) 7751 kvm_pmu_handle_event(vcpu); 7752 if (kvm_check_request(KVM_REQ_PMI, vcpu)) 7753 kvm_pmu_deliver_pmi(vcpu); 7754 if (kvm_check_request(KVM_REQ_IOAPIC_EOI_EXIT, vcpu)) { 7755 BUG_ON(vcpu->arch.pending_ioapic_eoi > 255); 7756 if (test_bit(vcpu->arch.pending_ioapic_eoi, 7757 vcpu->arch.ioapic_handled_vectors)) { 7758 vcpu->run->exit_reason = KVM_EXIT_IOAPIC_EOI; 7759 vcpu->run->eoi.vector = 7760 vcpu->arch.pending_ioapic_eoi; 7761 r = 0; 7762 goto out; 7763 } 7764 } 7765 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu)) 7766 vcpu_scan_ioapic(vcpu); 7767 if (kvm_check_request(KVM_REQ_LOAD_EOI_EXITMAP, vcpu)) 7768 vcpu_load_eoi_exitmap(vcpu); 7769 if (kvm_check_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu)) 7770 kvm_vcpu_reload_apic_access_page(vcpu); 7771 if (kvm_check_request(KVM_REQ_HV_CRASH, vcpu)) { 7772 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT; 7773 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_CRASH; 7774 r = 0; 7775 goto out; 7776 } 7777 if (kvm_check_request(KVM_REQ_HV_RESET, vcpu)) { 7778 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT; 7779 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_RESET; 7780 r = 0; 7781 goto out; 7782 } 7783 if (kvm_check_request(KVM_REQ_HV_EXIT, vcpu)) { 7784 vcpu->run->exit_reason = KVM_EXIT_HYPERV; 7785 vcpu->run->hyperv = vcpu->arch.hyperv.exit; 7786 r = 0; 7787 goto out; 7788 } 7789 7790 /* 7791 * KVM_REQ_HV_STIMER has to be processed after 7792 * KVM_REQ_CLOCK_UPDATE, because Hyper-V SynIC timers 7793 * depend on the guest clock being up-to-date 7794 */ 7795 if (kvm_check_request(KVM_REQ_HV_STIMER, vcpu)) 7796 kvm_hv_process_stimers(vcpu); 7797 } 7798 7799 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) { 7800 ++vcpu->stat.req_event; 7801 kvm_apic_accept_events(vcpu); 7802 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) { 7803 r = 1; 7804 goto out; 7805 } 7806 7807 if (inject_pending_event(vcpu, req_int_win) != 0) 7808 req_immediate_exit = true; 7809 else { 7810 /* Enable SMI/NMI/IRQ window open exits if needed. 7811 * 7812 * SMIs have three cases: 7813 * 1) They can be nested, and then there is nothing to 7814 * do here because RSM will cause a vmexit anyway. 7815 * 2) There is an ISA-specific reason why SMI cannot be 7816 * injected, and the moment when this changes can be 7817 * intercepted. 7818 * 3) Or the SMI can be pending because 7819 * inject_pending_event has completed the injection 7820 * of an IRQ or NMI from the previous vmexit, and 7821 * then we request an immediate exit to inject the 7822 * SMI. 7823 */ 7824 if (vcpu->arch.smi_pending && !is_smm(vcpu)) 7825 if (!kvm_x86_ops->enable_smi_window(vcpu)) 7826 req_immediate_exit = true; 7827 if (vcpu->arch.nmi_pending) 7828 kvm_x86_ops->enable_nmi_window(vcpu); 7829 if (kvm_cpu_has_injectable_intr(vcpu) || req_int_win) 7830 kvm_x86_ops->enable_irq_window(vcpu); 7831 WARN_ON(vcpu->arch.exception.pending); 7832 } 7833 7834 if (kvm_lapic_enabled(vcpu)) { 7835 update_cr8_intercept(vcpu); 7836 kvm_lapic_sync_to_vapic(vcpu); 7837 } 7838 } 7839 7840 r = kvm_mmu_reload(vcpu); 7841 if (unlikely(r)) { 7842 goto cancel_injection; 7843 } 7844 7845 preempt_disable(); 7846 7847 kvm_x86_ops->prepare_guest_switch(vcpu); 7848 7849 /* 7850 * Disable IRQs before setting IN_GUEST_MODE. Posted interrupt 7851 * IPI are then delayed after guest entry, which ensures that they 7852 * result in virtual interrupt delivery. 7853 */ 7854 local_irq_disable(); 7855 vcpu->mode = IN_GUEST_MODE; 7856 7857 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx); 7858 7859 /* 7860 * 1) We should set ->mode before checking ->requests. Please see 7861 * the comment in kvm_vcpu_exiting_guest_mode(). 7862 * 7863 * 2) For APICv, we should set ->mode before checking PID.ON. This 7864 * pairs with the memory barrier implicit in pi_test_and_set_on 7865 * (see vmx_deliver_posted_interrupt). 7866 * 7867 * 3) This also orders the write to mode from any reads to the page 7868 * tables done while the VCPU is running. Please see the comment 7869 * in kvm_flush_remote_tlbs. 7870 */ 7871 smp_mb__after_srcu_read_unlock(); 7872 7873 /* 7874 * This handles the case where a posted interrupt was 7875 * notified with kvm_vcpu_kick. 7876 */ 7877 if (kvm_lapic_enabled(vcpu) && vcpu->arch.apicv_active) 7878 kvm_x86_ops->sync_pir_to_irr(vcpu); 7879 7880 if (vcpu->mode == EXITING_GUEST_MODE || kvm_request_pending(vcpu) 7881 || need_resched() || signal_pending(current)) { 7882 vcpu->mode = OUTSIDE_GUEST_MODE; 7883 smp_wmb(); 7884 local_irq_enable(); 7885 preempt_enable(); 7886 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu); 7887 r = 1; 7888 goto cancel_injection; 7889 } 7890 7891 if (req_immediate_exit) { 7892 kvm_make_request(KVM_REQ_EVENT, vcpu); 7893 kvm_x86_ops->request_immediate_exit(vcpu); 7894 } 7895 7896 trace_kvm_entry(vcpu->vcpu_id); 7897 if (lapic_in_kernel(vcpu) && 7898 vcpu->arch.apic->lapic_timer.timer_advance_ns) 7899 wait_lapic_expire(vcpu); 7900 guest_enter_irqoff(); 7901 7902 if (unlikely(vcpu->arch.switch_db_regs)) { 7903 set_debugreg(0, 7); 7904 set_debugreg(vcpu->arch.eff_db[0], 0); 7905 set_debugreg(vcpu->arch.eff_db[1], 1); 7906 set_debugreg(vcpu->arch.eff_db[2], 2); 7907 set_debugreg(vcpu->arch.eff_db[3], 3); 7908 set_debugreg(vcpu->arch.dr6, 6); 7909 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD; 7910 } 7911 7912 kvm_x86_ops->run(vcpu); 7913 7914 /* 7915 * Do this here before restoring debug registers on the host. And 7916 * since we do this before handling the vmexit, a DR access vmexit 7917 * can (a) read the correct value of the debug registers, (b) set 7918 * KVM_DEBUGREG_WONT_EXIT again. 7919 */ 7920 if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) { 7921 WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP); 7922 kvm_x86_ops->sync_dirty_debug_regs(vcpu); 7923 kvm_update_dr0123(vcpu); 7924 kvm_update_dr6(vcpu); 7925 kvm_update_dr7(vcpu); 7926 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD; 7927 } 7928 7929 /* 7930 * If the guest has used debug registers, at least dr7 7931 * will be disabled while returning to the host. 7932 * If we don't have active breakpoints in the host, we don't 7933 * care about the messed up debug address registers. But if 7934 * we have some of them active, restore the old state. 7935 */ 7936 if (hw_breakpoint_active()) 7937 hw_breakpoint_restore(); 7938 7939 vcpu->arch.last_guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc()); 7940 7941 vcpu->mode = OUTSIDE_GUEST_MODE; 7942 smp_wmb(); 7943 7944 kvm_before_interrupt(vcpu); 7945 kvm_x86_ops->handle_external_intr(vcpu); 7946 kvm_after_interrupt(vcpu); 7947 7948 ++vcpu->stat.exits; 7949 7950 guest_exit_irqoff(); 7951 7952 local_irq_enable(); 7953 preempt_enable(); 7954 7955 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu); 7956 7957 /* 7958 * Profile KVM exit RIPs: 7959 */ 7960 if (unlikely(prof_on == KVM_PROFILING)) { 7961 unsigned long rip = kvm_rip_read(vcpu); 7962 profile_hit(KVM_PROFILING, (void *)rip); 7963 } 7964 7965 if (unlikely(vcpu->arch.tsc_always_catchup)) 7966 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 7967 7968 if (vcpu->arch.apic_attention) 7969 kvm_lapic_sync_from_vapic(vcpu); 7970 7971 vcpu->arch.gpa_available = false; 7972 r = kvm_x86_ops->handle_exit(vcpu); 7973 return r; 7974 7975 cancel_injection: 7976 kvm_x86_ops->cancel_injection(vcpu); 7977 if (unlikely(vcpu->arch.apic_attention)) 7978 kvm_lapic_sync_from_vapic(vcpu); 7979 out: 7980 return r; 7981 } 7982 7983 static inline int vcpu_block(struct kvm *kvm, struct kvm_vcpu *vcpu) 7984 { 7985 if (!kvm_arch_vcpu_runnable(vcpu) && 7986 (!kvm_x86_ops->pre_block || kvm_x86_ops->pre_block(vcpu) == 0)) { 7987 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx); 7988 kvm_vcpu_block(vcpu); 7989 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu); 7990 7991 if (kvm_x86_ops->post_block) 7992 kvm_x86_ops->post_block(vcpu); 7993 7994 if (!kvm_check_request(KVM_REQ_UNHALT, vcpu)) 7995 return 1; 7996 } 7997 7998 kvm_apic_accept_events(vcpu); 7999 switch(vcpu->arch.mp_state) { 8000 case KVM_MP_STATE_HALTED: 8001 vcpu->arch.pv.pv_unhalted = false; 8002 vcpu->arch.mp_state = 8003 KVM_MP_STATE_RUNNABLE; 8004 /* fall through */ 8005 case KVM_MP_STATE_RUNNABLE: 8006 vcpu->arch.apf.halted = false; 8007 break; 8008 case KVM_MP_STATE_INIT_RECEIVED: 8009 break; 8010 default: 8011 return -EINTR; 8012 break; 8013 } 8014 return 1; 8015 } 8016 8017 static inline bool kvm_vcpu_running(struct kvm_vcpu *vcpu) 8018 { 8019 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) 8020 kvm_x86_ops->check_nested_events(vcpu, false); 8021 8022 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE && 8023 !vcpu->arch.apf.halted); 8024 } 8025 8026 static int vcpu_run(struct kvm_vcpu *vcpu) 8027 { 8028 int r; 8029 struct kvm *kvm = vcpu->kvm; 8030 8031 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu); 8032 vcpu->arch.l1tf_flush_l1d = true; 8033 8034 for (;;) { 8035 if (kvm_vcpu_running(vcpu)) { 8036 r = vcpu_enter_guest(vcpu); 8037 } else { 8038 r = vcpu_block(kvm, vcpu); 8039 } 8040 8041 if (r <= 0) 8042 break; 8043 8044 kvm_clear_request(KVM_REQ_PENDING_TIMER, vcpu); 8045 if (kvm_cpu_has_pending_timer(vcpu)) 8046 kvm_inject_pending_timer_irqs(vcpu); 8047 8048 if (dm_request_for_irq_injection(vcpu) && 8049 kvm_vcpu_ready_for_interrupt_injection(vcpu)) { 8050 r = 0; 8051 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN; 8052 ++vcpu->stat.request_irq_exits; 8053 break; 8054 } 8055 8056 kvm_check_async_pf_completion(vcpu); 8057 8058 if (signal_pending(current)) { 8059 r = -EINTR; 8060 vcpu->run->exit_reason = KVM_EXIT_INTR; 8061 ++vcpu->stat.signal_exits; 8062 break; 8063 } 8064 if (need_resched()) { 8065 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx); 8066 cond_resched(); 8067 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu); 8068 } 8069 } 8070 8071 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx); 8072 8073 return r; 8074 } 8075 8076 static inline int complete_emulated_io(struct kvm_vcpu *vcpu) 8077 { 8078 int r; 8079 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu); 8080 r = kvm_emulate_instruction(vcpu, EMULTYPE_NO_DECODE); 8081 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx); 8082 if (r != EMULATE_DONE) 8083 return 0; 8084 return 1; 8085 } 8086 8087 static int complete_emulated_pio(struct kvm_vcpu *vcpu) 8088 { 8089 BUG_ON(!vcpu->arch.pio.count); 8090 8091 return complete_emulated_io(vcpu); 8092 } 8093 8094 /* 8095 * Implements the following, as a state machine: 8096 * 8097 * read: 8098 * for each fragment 8099 * for each mmio piece in the fragment 8100 * write gpa, len 8101 * exit 8102 * copy data 8103 * execute insn 8104 * 8105 * write: 8106 * for each fragment 8107 * for each mmio piece in the fragment 8108 * write gpa, len 8109 * copy data 8110 * exit 8111 */ 8112 static int complete_emulated_mmio(struct kvm_vcpu *vcpu) 8113 { 8114 struct kvm_run *run = vcpu->run; 8115 struct kvm_mmio_fragment *frag; 8116 unsigned len; 8117 8118 BUG_ON(!vcpu->mmio_needed); 8119 8120 /* Complete previous fragment */ 8121 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment]; 8122 len = min(8u, frag->len); 8123 if (!vcpu->mmio_is_write) 8124 memcpy(frag->data, run->mmio.data, len); 8125 8126 if (frag->len <= 8) { 8127 /* Switch to the next fragment. */ 8128 frag++; 8129 vcpu->mmio_cur_fragment++; 8130 } else { 8131 /* Go forward to the next mmio piece. */ 8132 frag->data += len; 8133 frag->gpa += len; 8134 frag->len -= len; 8135 } 8136 8137 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) { 8138 vcpu->mmio_needed = 0; 8139 8140 /* FIXME: return into emulator if single-stepping. */ 8141 if (vcpu->mmio_is_write) 8142 return 1; 8143 vcpu->mmio_read_completed = 1; 8144 return complete_emulated_io(vcpu); 8145 } 8146 8147 run->exit_reason = KVM_EXIT_MMIO; 8148 run->mmio.phys_addr = frag->gpa; 8149 if (vcpu->mmio_is_write) 8150 memcpy(run->mmio.data, frag->data, min(8u, frag->len)); 8151 run->mmio.len = min(8u, frag->len); 8152 run->mmio.is_write = vcpu->mmio_is_write; 8153 vcpu->arch.complete_userspace_io = complete_emulated_mmio; 8154 return 0; 8155 } 8156 8157 /* Swap (qemu) user FPU context for the guest FPU context. */ 8158 static void kvm_load_guest_fpu(struct kvm_vcpu *vcpu) 8159 { 8160 preempt_disable(); 8161 copy_fpregs_to_fpstate(¤t->thread.fpu); 8162 /* PKRU is separately restored in kvm_x86_ops->run. */ 8163 __copy_kernel_to_fpregs(&vcpu->arch.guest_fpu->state, 8164 ~XFEATURE_MASK_PKRU); 8165 preempt_enable(); 8166 trace_kvm_fpu(1); 8167 } 8168 8169 /* When vcpu_run ends, restore user space FPU context. */ 8170 static void kvm_put_guest_fpu(struct kvm_vcpu *vcpu) 8171 { 8172 preempt_disable(); 8173 copy_fpregs_to_fpstate(vcpu->arch.guest_fpu); 8174 copy_kernel_to_fpregs(¤t->thread.fpu.state); 8175 preempt_enable(); 8176 ++vcpu->stat.fpu_reload; 8177 trace_kvm_fpu(0); 8178 } 8179 8180 int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) 8181 { 8182 int r; 8183 8184 vcpu_load(vcpu); 8185 kvm_sigset_activate(vcpu); 8186 kvm_load_guest_fpu(vcpu); 8187 8188 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) { 8189 if (kvm_run->immediate_exit) { 8190 r = -EINTR; 8191 goto out; 8192 } 8193 kvm_vcpu_block(vcpu); 8194 kvm_apic_accept_events(vcpu); 8195 kvm_clear_request(KVM_REQ_UNHALT, vcpu); 8196 r = -EAGAIN; 8197 if (signal_pending(current)) { 8198 r = -EINTR; 8199 vcpu->run->exit_reason = KVM_EXIT_INTR; 8200 ++vcpu->stat.signal_exits; 8201 } 8202 goto out; 8203 } 8204 8205 if (vcpu->run->kvm_valid_regs & ~KVM_SYNC_X86_VALID_FIELDS) { 8206 r = -EINVAL; 8207 goto out; 8208 } 8209 8210 if (vcpu->run->kvm_dirty_regs) { 8211 r = sync_regs(vcpu); 8212 if (r != 0) 8213 goto out; 8214 } 8215 8216 /* re-sync apic's tpr */ 8217 if (!lapic_in_kernel(vcpu)) { 8218 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) { 8219 r = -EINVAL; 8220 goto out; 8221 } 8222 } 8223 8224 if (unlikely(vcpu->arch.complete_userspace_io)) { 8225 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io; 8226 vcpu->arch.complete_userspace_io = NULL; 8227 r = cui(vcpu); 8228 if (r <= 0) 8229 goto out; 8230 } else 8231 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed); 8232 8233 if (kvm_run->immediate_exit) 8234 r = -EINTR; 8235 else 8236 r = vcpu_run(vcpu); 8237 8238 out: 8239 kvm_put_guest_fpu(vcpu); 8240 if (vcpu->run->kvm_valid_regs) 8241 store_regs(vcpu); 8242 post_kvm_run_save(vcpu); 8243 kvm_sigset_deactivate(vcpu); 8244 8245 vcpu_put(vcpu); 8246 return r; 8247 } 8248 8249 static void __get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) 8250 { 8251 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) { 8252 /* 8253 * We are here if userspace calls get_regs() in the middle of 8254 * instruction emulation. Registers state needs to be copied 8255 * back from emulation context to vcpu. Userspace shouldn't do 8256 * that usually, but some bad designed PV devices (vmware 8257 * backdoor interface) need this to work 8258 */ 8259 emulator_writeback_register_cache(&vcpu->arch.emulate_ctxt); 8260 vcpu->arch.emulate_regs_need_sync_to_vcpu = false; 8261 } 8262 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX); 8263 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX); 8264 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX); 8265 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX); 8266 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI); 8267 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI); 8268 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP); 8269 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP); 8270 #ifdef CONFIG_X86_64 8271 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8); 8272 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9); 8273 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10); 8274 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11); 8275 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12); 8276 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13); 8277 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14); 8278 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15); 8279 #endif 8280 8281 regs->rip = kvm_rip_read(vcpu); 8282 regs->rflags = kvm_get_rflags(vcpu); 8283 } 8284 8285 int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) 8286 { 8287 vcpu_load(vcpu); 8288 __get_regs(vcpu, regs); 8289 vcpu_put(vcpu); 8290 return 0; 8291 } 8292 8293 static void __set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) 8294 { 8295 vcpu->arch.emulate_regs_need_sync_from_vcpu = true; 8296 vcpu->arch.emulate_regs_need_sync_to_vcpu = false; 8297 8298 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax); 8299 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx); 8300 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx); 8301 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx); 8302 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi); 8303 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi); 8304 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp); 8305 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp); 8306 #ifdef CONFIG_X86_64 8307 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8); 8308 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9); 8309 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10); 8310 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11); 8311 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12); 8312 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13); 8313 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14); 8314 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15); 8315 #endif 8316 8317 kvm_rip_write(vcpu, regs->rip); 8318 kvm_set_rflags(vcpu, regs->rflags | X86_EFLAGS_FIXED); 8319 8320 vcpu->arch.exception.pending = false; 8321 8322 kvm_make_request(KVM_REQ_EVENT, vcpu); 8323 } 8324 8325 int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) 8326 { 8327 vcpu_load(vcpu); 8328 __set_regs(vcpu, regs); 8329 vcpu_put(vcpu); 8330 return 0; 8331 } 8332 8333 void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l) 8334 { 8335 struct kvm_segment cs; 8336 8337 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS); 8338 *db = cs.db; 8339 *l = cs.l; 8340 } 8341 EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits); 8342 8343 static void __get_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs) 8344 { 8345 struct desc_ptr dt; 8346 8347 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS); 8348 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS); 8349 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES); 8350 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS); 8351 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS); 8352 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS); 8353 8354 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR); 8355 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR); 8356 8357 kvm_x86_ops->get_idt(vcpu, &dt); 8358 sregs->idt.limit = dt.size; 8359 sregs->idt.base = dt.address; 8360 kvm_x86_ops->get_gdt(vcpu, &dt); 8361 sregs->gdt.limit = dt.size; 8362 sregs->gdt.base = dt.address; 8363 8364 sregs->cr0 = kvm_read_cr0(vcpu); 8365 sregs->cr2 = vcpu->arch.cr2; 8366 sregs->cr3 = kvm_read_cr3(vcpu); 8367 sregs->cr4 = kvm_read_cr4(vcpu); 8368 sregs->cr8 = kvm_get_cr8(vcpu); 8369 sregs->efer = vcpu->arch.efer; 8370 sregs->apic_base = kvm_get_apic_base(vcpu); 8371 8372 memset(sregs->interrupt_bitmap, 0, sizeof(sregs->interrupt_bitmap)); 8373 8374 if (vcpu->arch.interrupt.injected && !vcpu->arch.interrupt.soft) 8375 set_bit(vcpu->arch.interrupt.nr, 8376 (unsigned long *)sregs->interrupt_bitmap); 8377 } 8378 8379 int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu, 8380 struct kvm_sregs *sregs) 8381 { 8382 vcpu_load(vcpu); 8383 __get_sregs(vcpu, sregs); 8384 vcpu_put(vcpu); 8385 return 0; 8386 } 8387 8388 int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu, 8389 struct kvm_mp_state *mp_state) 8390 { 8391 vcpu_load(vcpu); 8392 8393 kvm_apic_accept_events(vcpu); 8394 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED && 8395 vcpu->arch.pv.pv_unhalted) 8396 mp_state->mp_state = KVM_MP_STATE_RUNNABLE; 8397 else 8398 mp_state->mp_state = vcpu->arch.mp_state; 8399 8400 vcpu_put(vcpu); 8401 return 0; 8402 } 8403 8404 int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu, 8405 struct kvm_mp_state *mp_state) 8406 { 8407 int ret = -EINVAL; 8408 8409 vcpu_load(vcpu); 8410 8411 if (!lapic_in_kernel(vcpu) && 8412 mp_state->mp_state != KVM_MP_STATE_RUNNABLE) 8413 goto out; 8414 8415 /* INITs are latched while in SMM */ 8416 if ((is_smm(vcpu) || vcpu->arch.smi_pending) && 8417 (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED || 8418 mp_state->mp_state == KVM_MP_STATE_INIT_RECEIVED)) 8419 goto out; 8420 8421 if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) { 8422 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED; 8423 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events); 8424 } else 8425 vcpu->arch.mp_state = mp_state->mp_state; 8426 kvm_make_request(KVM_REQ_EVENT, vcpu); 8427 8428 ret = 0; 8429 out: 8430 vcpu_put(vcpu); 8431 return ret; 8432 } 8433 8434 int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index, 8435 int reason, bool has_error_code, u32 error_code) 8436 { 8437 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt; 8438 int ret; 8439 8440 init_emulate_ctxt(vcpu); 8441 8442 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason, 8443 has_error_code, error_code); 8444 8445 if (ret) 8446 return EMULATE_FAIL; 8447 8448 kvm_rip_write(vcpu, ctxt->eip); 8449 kvm_set_rflags(vcpu, ctxt->eflags); 8450 kvm_make_request(KVM_REQ_EVENT, vcpu); 8451 return EMULATE_DONE; 8452 } 8453 EXPORT_SYMBOL_GPL(kvm_task_switch); 8454 8455 static int kvm_valid_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs) 8456 { 8457 if (!guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) && 8458 (sregs->cr4 & X86_CR4_OSXSAVE)) 8459 return -EINVAL; 8460 8461 if ((sregs->efer & EFER_LME) && (sregs->cr0 & X86_CR0_PG)) { 8462 /* 8463 * When EFER.LME and CR0.PG are set, the processor is in 8464 * 64-bit mode (though maybe in a 32-bit code segment). 8465 * CR4.PAE and EFER.LMA must be set. 8466 */ 8467 if (!(sregs->cr4 & X86_CR4_PAE) 8468 || !(sregs->efer & EFER_LMA)) 8469 return -EINVAL; 8470 } else { 8471 /* 8472 * Not in 64-bit mode: EFER.LMA is clear and the code 8473 * segment cannot be 64-bit. 8474 */ 8475 if (sregs->efer & EFER_LMA || sregs->cs.l) 8476 return -EINVAL; 8477 } 8478 8479 return 0; 8480 } 8481 8482 static int __set_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs) 8483 { 8484 struct msr_data apic_base_msr; 8485 int mmu_reset_needed = 0; 8486 int cpuid_update_needed = 0; 8487 int pending_vec, max_bits, idx; 8488 struct desc_ptr dt; 8489 int ret = -EINVAL; 8490 8491 if (kvm_valid_sregs(vcpu, sregs)) 8492 goto out; 8493 8494 apic_base_msr.data = sregs->apic_base; 8495 apic_base_msr.host_initiated = true; 8496 if (kvm_set_apic_base(vcpu, &apic_base_msr)) 8497 goto out; 8498 8499 dt.size = sregs->idt.limit; 8500 dt.address = sregs->idt.base; 8501 kvm_x86_ops->set_idt(vcpu, &dt); 8502 dt.size = sregs->gdt.limit; 8503 dt.address = sregs->gdt.base; 8504 kvm_x86_ops->set_gdt(vcpu, &dt); 8505 8506 vcpu->arch.cr2 = sregs->cr2; 8507 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3; 8508 vcpu->arch.cr3 = sregs->cr3; 8509 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail); 8510 8511 kvm_set_cr8(vcpu, sregs->cr8); 8512 8513 mmu_reset_needed |= vcpu->arch.efer != sregs->efer; 8514 kvm_x86_ops->set_efer(vcpu, sregs->efer); 8515 8516 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0; 8517 kvm_x86_ops->set_cr0(vcpu, sregs->cr0); 8518 vcpu->arch.cr0 = sregs->cr0; 8519 8520 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4; 8521 cpuid_update_needed |= ((kvm_read_cr4(vcpu) ^ sregs->cr4) & 8522 (X86_CR4_OSXSAVE | X86_CR4_PKE)); 8523 kvm_x86_ops->set_cr4(vcpu, sregs->cr4); 8524 if (cpuid_update_needed) 8525 kvm_update_cpuid(vcpu); 8526 8527 idx = srcu_read_lock(&vcpu->kvm->srcu); 8528 if (!is_long_mode(vcpu) && is_pae(vcpu) && is_paging(vcpu)) { 8529 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu)); 8530 mmu_reset_needed = 1; 8531 } 8532 srcu_read_unlock(&vcpu->kvm->srcu, idx); 8533 8534 if (mmu_reset_needed) 8535 kvm_mmu_reset_context(vcpu); 8536 8537 max_bits = KVM_NR_INTERRUPTS; 8538 pending_vec = find_first_bit( 8539 (const unsigned long *)sregs->interrupt_bitmap, max_bits); 8540 if (pending_vec < max_bits) { 8541 kvm_queue_interrupt(vcpu, pending_vec, false); 8542 pr_debug("Set back pending irq %d\n", pending_vec); 8543 } 8544 8545 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS); 8546 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS); 8547 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES); 8548 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS); 8549 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS); 8550 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS); 8551 8552 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR); 8553 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR); 8554 8555 update_cr8_intercept(vcpu); 8556 8557 /* Older userspace won't unhalt the vcpu on reset. */ 8558 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 && 8559 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 && 8560 !is_protmode(vcpu)) 8561 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; 8562 8563 kvm_make_request(KVM_REQ_EVENT, vcpu); 8564 8565 ret = 0; 8566 out: 8567 return ret; 8568 } 8569 8570 int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu, 8571 struct kvm_sregs *sregs) 8572 { 8573 int ret; 8574 8575 vcpu_load(vcpu); 8576 ret = __set_sregs(vcpu, sregs); 8577 vcpu_put(vcpu); 8578 return ret; 8579 } 8580 8581 int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu, 8582 struct kvm_guest_debug *dbg) 8583 { 8584 unsigned long rflags; 8585 int i, r; 8586 8587 vcpu_load(vcpu); 8588 8589 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) { 8590 r = -EBUSY; 8591 if (vcpu->arch.exception.pending) 8592 goto out; 8593 if (dbg->control & KVM_GUESTDBG_INJECT_DB) 8594 kvm_queue_exception(vcpu, DB_VECTOR); 8595 else 8596 kvm_queue_exception(vcpu, BP_VECTOR); 8597 } 8598 8599 /* 8600 * Read rflags as long as potentially injected trace flags are still 8601 * filtered out. 8602 */ 8603 rflags = kvm_get_rflags(vcpu); 8604 8605 vcpu->guest_debug = dbg->control; 8606 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE)) 8607 vcpu->guest_debug = 0; 8608 8609 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) { 8610 for (i = 0; i < KVM_NR_DB_REGS; ++i) 8611 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i]; 8612 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7]; 8613 } else { 8614 for (i = 0; i < KVM_NR_DB_REGS; i++) 8615 vcpu->arch.eff_db[i] = vcpu->arch.db[i]; 8616 } 8617 kvm_update_dr7(vcpu); 8618 8619 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) 8620 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) + 8621 get_segment_base(vcpu, VCPU_SREG_CS); 8622 8623 /* 8624 * Trigger an rflags update that will inject or remove the trace 8625 * flags. 8626 */ 8627 kvm_set_rflags(vcpu, rflags); 8628 8629 kvm_x86_ops->update_bp_intercept(vcpu); 8630 8631 r = 0; 8632 8633 out: 8634 vcpu_put(vcpu); 8635 return r; 8636 } 8637 8638 /* 8639 * Translate a guest virtual address to a guest physical address. 8640 */ 8641 int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu, 8642 struct kvm_translation *tr) 8643 { 8644 unsigned long vaddr = tr->linear_address; 8645 gpa_t gpa; 8646 int idx; 8647 8648 vcpu_load(vcpu); 8649 8650 idx = srcu_read_lock(&vcpu->kvm->srcu); 8651 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL); 8652 srcu_read_unlock(&vcpu->kvm->srcu, idx); 8653 tr->physical_address = gpa; 8654 tr->valid = gpa != UNMAPPED_GVA; 8655 tr->writeable = 1; 8656 tr->usermode = 0; 8657 8658 vcpu_put(vcpu); 8659 return 0; 8660 } 8661 8662 int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu) 8663 { 8664 struct fxregs_state *fxsave; 8665 8666 vcpu_load(vcpu); 8667 8668 fxsave = &vcpu->arch.guest_fpu->state.fxsave; 8669 memcpy(fpu->fpr, fxsave->st_space, 128); 8670 fpu->fcw = fxsave->cwd; 8671 fpu->fsw = fxsave->swd; 8672 fpu->ftwx = fxsave->twd; 8673 fpu->last_opcode = fxsave->fop; 8674 fpu->last_ip = fxsave->rip; 8675 fpu->last_dp = fxsave->rdp; 8676 memcpy(fpu->xmm, fxsave->xmm_space, sizeof(fxsave->xmm_space)); 8677 8678 vcpu_put(vcpu); 8679 return 0; 8680 } 8681 8682 int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu) 8683 { 8684 struct fxregs_state *fxsave; 8685 8686 vcpu_load(vcpu); 8687 8688 fxsave = &vcpu->arch.guest_fpu->state.fxsave; 8689 8690 memcpy(fxsave->st_space, fpu->fpr, 128); 8691 fxsave->cwd = fpu->fcw; 8692 fxsave->swd = fpu->fsw; 8693 fxsave->twd = fpu->ftwx; 8694 fxsave->fop = fpu->last_opcode; 8695 fxsave->rip = fpu->last_ip; 8696 fxsave->rdp = fpu->last_dp; 8697 memcpy(fxsave->xmm_space, fpu->xmm, sizeof(fxsave->xmm_space)); 8698 8699 vcpu_put(vcpu); 8700 return 0; 8701 } 8702 8703 static void store_regs(struct kvm_vcpu *vcpu) 8704 { 8705 BUILD_BUG_ON(sizeof(struct kvm_sync_regs) > SYNC_REGS_SIZE_BYTES); 8706 8707 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_REGS) 8708 __get_regs(vcpu, &vcpu->run->s.regs.regs); 8709 8710 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_SREGS) 8711 __get_sregs(vcpu, &vcpu->run->s.regs.sregs); 8712 8713 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_EVENTS) 8714 kvm_vcpu_ioctl_x86_get_vcpu_events( 8715 vcpu, &vcpu->run->s.regs.events); 8716 } 8717 8718 static int sync_regs(struct kvm_vcpu *vcpu) 8719 { 8720 if (vcpu->run->kvm_dirty_regs & ~KVM_SYNC_X86_VALID_FIELDS) 8721 return -EINVAL; 8722 8723 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_REGS) { 8724 __set_regs(vcpu, &vcpu->run->s.regs.regs); 8725 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_REGS; 8726 } 8727 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_SREGS) { 8728 if (__set_sregs(vcpu, &vcpu->run->s.regs.sregs)) 8729 return -EINVAL; 8730 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_SREGS; 8731 } 8732 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_EVENTS) { 8733 if (kvm_vcpu_ioctl_x86_set_vcpu_events( 8734 vcpu, &vcpu->run->s.regs.events)) 8735 return -EINVAL; 8736 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_EVENTS; 8737 } 8738 8739 return 0; 8740 } 8741 8742 static void fx_init(struct kvm_vcpu *vcpu) 8743 { 8744 fpstate_init(&vcpu->arch.guest_fpu->state); 8745 if (boot_cpu_has(X86_FEATURE_XSAVES)) 8746 vcpu->arch.guest_fpu->state.xsave.header.xcomp_bv = 8747 host_xcr0 | XSTATE_COMPACTION_ENABLED; 8748 8749 /* 8750 * Ensure guest xcr0 is valid for loading 8751 */ 8752 vcpu->arch.xcr0 = XFEATURE_MASK_FP; 8753 8754 vcpu->arch.cr0 |= X86_CR0_ET; 8755 } 8756 8757 void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu) 8758 { 8759 void *wbinvd_dirty_mask = vcpu->arch.wbinvd_dirty_mask; 8760 8761 kvmclock_reset(vcpu); 8762 8763 kvm_x86_ops->vcpu_free(vcpu); 8764 free_cpumask_var(wbinvd_dirty_mask); 8765 } 8766 8767 struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm, 8768 unsigned int id) 8769 { 8770 struct kvm_vcpu *vcpu; 8771 8772 if (kvm_check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0) 8773 printk_once(KERN_WARNING 8774 "kvm: SMP vm created on host with unstable TSC; " 8775 "guest TSC will not be reliable\n"); 8776 8777 vcpu = kvm_x86_ops->vcpu_create(kvm, id); 8778 8779 return vcpu; 8780 } 8781 8782 int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu) 8783 { 8784 vcpu->arch.arch_capabilities = kvm_get_arch_capabilities(); 8785 vcpu->arch.msr_platform_info = MSR_PLATFORM_INFO_CPUID_FAULT; 8786 kvm_vcpu_mtrr_init(vcpu); 8787 vcpu_load(vcpu); 8788 kvm_vcpu_reset(vcpu, false); 8789 kvm_init_mmu(vcpu, false); 8790 vcpu_put(vcpu); 8791 return 0; 8792 } 8793 8794 void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu) 8795 { 8796 struct msr_data msr; 8797 struct kvm *kvm = vcpu->kvm; 8798 8799 kvm_hv_vcpu_postcreate(vcpu); 8800 8801 if (mutex_lock_killable(&vcpu->mutex)) 8802 return; 8803 vcpu_load(vcpu); 8804 msr.data = 0x0; 8805 msr.index = MSR_IA32_TSC; 8806 msr.host_initiated = true; 8807 kvm_write_tsc(vcpu, &msr); 8808 vcpu_put(vcpu); 8809 mutex_unlock(&vcpu->mutex); 8810 8811 if (!kvmclock_periodic_sync) 8812 return; 8813 8814 schedule_delayed_work(&kvm->arch.kvmclock_sync_work, 8815 KVMCLOCK_SYNC_PERIOD); 8816 } 8817 8818 void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu) 8819 { 8820 vcpu->arch.apf.msr_val = 0; 8821 8822 vcpu_load(vcpu); 8823 kvm_mmu_unload(vcpu); 8824 vcpu_put(vcpu); 8825 8826 kvm_x86_ops->vcpu_free(vcpu); 8827 } 8828 8829 void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event) 8830 { 8831 kvm_lapic_reset(vcpu, init_event); 8832 8833 vcpu->arch.hflags = 0; 8834 8835 vcpu->arch.smi_pending = 0; 8836 vcpu->arch.smi_count = 0; 8837 atomic_set(&vcpu->arch.nmi_queued, 0); 8838 vcpu->arch.nmi_pending = 0; 8839 vcpu->arch.nmi_injected = false; 8840 kvm_clear_interrupt_queue(vcpu); 8841 kvm_clear_exception_queue(vcpu); 8842 vcpu->arch.exception.pending = false; 8843 8844 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db)); 8845 kvm_update_dr0123(vcpu); 8846 vcpu->arch.dr6 = DR6_INIT; 8847 kvm_update_dr6(vcpu); 8848 vcpu->arch.dr7 = DR7_FIXED_1; 8849 kvm_update_dr7(vcpu); 8850 8851 vcpu->arch.cr2 = 0; 8852 8853 kvm_make_request(KVM_REQ_EVENT, vcpu); 8854 vcpu->arch.apf.msr_val = 0; 8855 vcpu->arch.st.msr_val = 0; 8856 8857 kvmclock_reset(vcpu); 8858 8859 kvm_clear_async_pf_completion_queue(vcpu); 8860 kvm_async_pf_hash_reset(vcpu); 8861 vcpu->arch.apf.halted = false; 8862 8863 if (kvm_mpx_supported()) { 8864 void *mpx_state_buffer; 8865 8866 /* 8867 * To avoid have the INIT path from kvm_apic_has_events() that be 8868 * called with loaded FPU and does not let userspace fix the state. 8869 */ 8870 if (init_event) 8871 kvm_put_guest_fpu(vcpu); 8872 mpx_state_buffer = get_xsave_addr(&vcpu->arch.guest_fpu->state.xsave, 8873 XFEATURE_MASK_BNDREGS); 8874 if (mpx_state_buffer) 8875 memset(mpx_state_buffer, 0, sizeof(struct mpx_bndreg_state)); 8876 mpx_state_buffer = get_xsave_addr(&vcpu->arch.guest_fpu->state.xsave, 8877 XFEATURE_MASK_BNDCSR); 8878 if (mpx_state_buffer) 8879 memset(mpx_state_buffer, 0, sizeof(struct mpx_bndcsr)); 8880 if (init_event) 8881 kvm_load_guest_fpu(vcpu); 8882 } 8883 8884 if (!init_event) { 8885 kvm_pmu_reset(vcpu); 8886 vcpu->arch.smbase = 0x30000; 8887 8888 vcpu->arch.msr_misc_features_enables = 0; 8889 8890 vcpu->arch.xcr0 = XFEATURE_MASK_FP; 8891 } 8892 8893 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs)); 8894 vcpu->arch.regs_avail = ~0; 8895 vcpu->arch.regs_dirty = ~0; 8896 8897 vcpu->arch.ia32_xss = 0; 8898 8899 kvm_x86_ops->vcpu_reset(vcpu, init_event); 8900 } 8901 8902 void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector) 8903 { 8904 struct kvm_segment cs; 8905 8906 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS); 8907 cs.selector = vector << 8; 8908 cs.base = vector << 12; 8909 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS); 8910 kvm_rip_write(vcpu, 0); 8911 } 8912 8913 int kvm_arch_hardware_enable(void) 8914 { 8915 struct kvm *kvm; 8916 struct kvm_vcpu *vcpu; 8917 int i; 8918 int ret; 8919 u64 local_tsc; 8920 u64 max_tsc = 0; 8921 bool stable, backwards_tsc = false; 8922 8923 kvm_shared_msr_cpu_online(); 8924 ret = kvm_x86_ops->hardware_enable(); 8925 if (ret != 0) 8926 return ret; 8927 8928 local_tsc = rdtsc(); 8929 stable = !kvm_check_tsc_unstable(); 8930 list_for_each_entry(kvm, &vm_list, vm_list) { 8931 kvm_for_each_vcpu(i, vcpu, kvm) { 8932 if (!stable && vcpu->cpu == smp_processor_id()) 8933 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 8934 if (stable && vcpu->arch.last_host_tsc > local_tsc) { 8935 backwards_tsc = true; 8936 if (vcpu->arch.last_host_tsc > max_tsc) 8937 max_tsc = vcpu->arch.last_host_tsc; 8938 } 8939 } 8940 } 8941 8942 /* 8943 * Sometimes, even reliable TSCs go backwards. This happens on 8944 * platforms that reset TSC during suspend or hibernate actions, but 8945 * maintain synchronization. We must compensate. Fortunately, we can 8946 * detect that condition here, which happens early in CPU bringup, 8947 * before any KVM threads can be running. Unfortunately, we can't 8948 * bring the TSCs fully up to date with real time, as we aren't yet far 8949 * enough into CPU bringup that we know how much real time has actually 8950 * elapsed; our helper function, ktime_get_boot_ns() will be using boot 8951 * variables that haven't been updated yet. 8952 * 8953 * So we simply find the maximum observed TSC above, then record the 8954 * adjustment to TSC in each VCPU. When the VCPU later gets loaded, 8955 * the adjustment will be applied. Note that we accumulate 8956 * adjustments, in case multiple suspend cycles happen before some VCPU 8957 * gets a chance to run again. In the event that no KVM threads get a 8958 * chance to run, we will miss the entire elapsed period, as we'll have 8959 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may 8960 * loose cycle time. This isn't too big a deal, since the loss will be 8961 * uniform across all VCPUs (not to mention the scenario is extremely 8962 * unlikely). It is possible that a second hibernate recovery happens 8963 * much faster than a first, causing the observed TSC here to be 8964 * smaller; this would require additional padding adjustment, which is 8965 * why we set last_host_tsc to the local tsc observed here. 8966 * 8967 * N.B. - this code below runs only on platforms with reliable TSC, 8968 * as that is the only way backwards_tsc is set above. Also note 8969 * that this runs for ALL vcpus, which is not a bug; all VCPUs should 8970 * have the same delta_cyc adjustment applied if backwards_tsc 8971 * is detected. Note further, this adjustment is only done once, 8972 * as we reset last_host_tsc on all VCPUs to stop this from being 8973 * called multiple times (one for each physical CPU bringup). 8974 * 8975 * Platforms with unreliable TSCs don't have to deal with this, they 8976 * will be compensated by the logic in vcpu_load, which sets the TSC to 8977 * catchup mode. This will catchup all VCPUs to real time, but cannot 8978 * guarantee that they stay in perfect synchronization. 8979 */ 8980 if (backwards_tsc) { 8981 u64 delta_cyc = max_tsc - local_tsc; 8982 list_for_each_entry(kvm, &vm_list, vm_list) { 8983 kvm->arch.backwards_tsc_observed = true; 8984 kvm_for_each_vcpu(i, vcpu, kvm) { 8985 vcpu->arch.tsc_offset_adjustment += delta_cyc; 8986 vcpu->arch.last_host_tsc = local_tsc; 8987 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu); 8988 } 8989 8990 /* 8991 * We have to disable TSC offset matching.. if you were 8992 * booting a VM while issuing an S4 host suspend.... 8993 * you may have some problem. Solving this issue is 8994 * left as an exercise to the reader. 8995 */ 8996 kvm->arch.last_tsc_nsec = 0; 8997 kvm->arch.last_tsc_write = 0; 8998 } 8999 9000 } 9001 return 0; 9002 } 9003 9004 void kvm_arch_hardware_disable(void) 9005 { 9006 kvm_x86_ops->hardware_disable(); 9007 drop_user_return_notifiers(); 9008 } 9009 9010 int kvm_arch_hardware_setup(void) 9011 { 9012 int r; 9013 9014 r = kvm_x86_ops->hardware_setup(); 9015 if (r != 0) 9016 return r; 9017 9018 if (kvm_has_tsc_control) { 9019 /* 9020 * Make sure the user can only configure tsc_khz values that 9021 * fit into a signed integer. 9022 * A min value is not calculated because it will always 9023 * be 1 on all machines. 9024 */ 9025 u64 max = min(0x7fffffffULL, 9026 __scale_tsc(kvm_max_tsc_scaling_ratio, tsc_khz)); 9027 kvm_max_guest_tsc_khz = max; 9028 9029 kvm_default_tsc_scaling_ratio = 1ULL << kvm_tsc_scaling_ratio_frac_bits; 9030 } 9031 9032 kvm_init_msr_list(); 9033 return 0; 9034 } 9035 9036 void kvm_arch_hardware_unsetup(void) 9037 { 9038 kvm_x86_ops->hardware_unsetup(); 9039 } 9040 9041 void kvm_arch_check_processor_compat(void *rtn) 9042 { 9043 kvm_x86_ops->check_processor_compatibility(rtn); 9044 } 9045 9046 bool kvm_vcpu_is_reset_bsp(struct kvm_vcpu *vcpu) 9047 { 9048 return vcpu->kvm->arch.bsp_vcpu_id == vcpu->vcpu_id; 9049 } 9050 EXPORT_SYMBOL_GPL(kvm_vcpu_is_reset_bsp); 9051 9052 bool kvm_vcpu_is_bsp(struct kvm_vcpu *vcpu) 9053 { 9054 return (vcpu->arch.apic_base & MSR_IA32_APICBASE_BSP) != 0; 9055 } 9056 9057 struct static_key kvm_no_apic_vcpu __read_mostly; 9058 EXPORT_SYMBOL_GPL(kvm_no_apic_vcpu); 9059 9060 int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu) 9061 { 9062 struct page *page; 9063 int r; 9064 9065 vcpu->arch.emulate_ctxt.ops = &emulate_ops; 9066 if (!irqchip_in_kernel(vcpu->kvm) || kvm_vcpu_is_reset_bsp(vcpu)) 9067 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; 9068 else 9069 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED; 9070 9071 page = alloc_page(GFP_KERNEL | __GFP_ZERO); 9072 if (!page) { 9073 r = -ENOMEM; 9074 goto fail; 9075 } 9076 vcpu->arch.pio_data = page_address(page); 9077 9078 kvm_set_tsc_khz(vcpu, max_tsc_khz); 9079 9080 r = kvm_mmu_create(vcpu); 9081 if (r < 0) 9082 goto fail_free_pio_data; 9083 9084 if (irqchip_in_kernel(vcpu->kvm)) { 9085 vcpu->arch.apicv_active = kvm_x86_ops->get_enable_apicv(vcpu); 9086 r = kvm_create_lapic(vcpu, lapic_timer_advance_ns); 9087 if (r < 0) 9088 goto fail_mmu_destroy; 9089 } else 9090 static_key_slow_inc(&kvm_no_apic_vcpu); 9091 9092 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4, 9093 GFP_KERNEL_ACCOUNT); 9094 if (!vcpu->arch.mce_banks) { 9095 r = -ENOMEM; 9096 goto fail_free_lapic; 9097 } 9098 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS; 9099 9100 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, 9101 GFP_KERNEL_ACCOUNT)) { 9102 r = -ENOMEM; 9103 goto fail_free_mce_banks; 9104 } 9105 9106 fx_init(vcpu); 9107 9108 vcpu->arch.guest_xstate_size = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET; 9109 9110 vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu); 9111 9112 vcpu->arch.pat = MSR_IA32_CR_PAT_DEFAULT; 9113 9114 kvm_async_pf_hash_reset(vcpu); 9115 kvm_pmu_init(vcpu); 9116 9117 vcpu->arch.pending_external_vector = -1; 9118 vcpu->arch.preempted_in_kernel = false; 9119 9120 kvm_hv_vcpu_init(vcpu); 9121 9122 return 0; 9123 9124 fail_free_mce_banks: 9125 kfree(vcpu->arch.mce_banks); 9126 fail_free_lapic: 9127 kvm_free_lapic(vcpu); 9128 fail_mmu_destroy: 9129 kvm_mmu_destroy(vcpu); 9130 fail_free_pio_data: 9131 free_page((unsigned long)vcpu->arch.pio_data); 9132 fail: 9133 return r; 9134 } 9135 9136 void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu) 9137 { 9138 int idx; 9139 9140 kvm_hv_vcpu_uninit(vcpu); 9141 kvm_pmu_destroy(vcpu); 9142 kfree(vcpu->arch.mce_banks); 9143 kvm_free_lapic(vcpu); 9144 idx = srcu_read_lock(&vcpu->kvm->srcu); 9145 kvm_mmu_destroy(vcpu); 9146 srcu_read_unlock(&vcpu->kvm->srcu, idx); 9147 free_page((unsigned long)vcpu->arch.pio_data); 9148 if (!lapic_in_kernel(vcpu)) 9149 static_key_slow_dec(&kvm_no_apic_vcpu); 9150 } 9151 9152 void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu) 9153 { 9154 vcpu->arch.l1tf_flush_l1d = true; 9155 kvm_x86_ops->sched_in(vcpu, cpu); 9156 } 9157 9158 int kvm_arch_init_vm(struct kvm *kvm, unsigned long type) 9159 { 9160 if (type) 9161 return -EINVAL; 9162 9163 INIT_HLIST_HEAD(&kvm->arch.mask_notifier_list); 9164 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages); 9165 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head); 9166 atomic_set(&kvm->arch.noncoherent_dma_count, 0); 9167 9168 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */ 9169 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap); 9170 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */ 9171 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID, 9172 &kvm->arch.irq_sources_bitmap); 9173 9174 raw_spin_lock_init(&kvm->arch.tsc_write_lock); 9175 mutex_init(&kvm->arch.apic_map_lock); 9176 spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock); 9177 9178 kvm->arch.kvmclock_offset = -ktime_get_boot_ns(); 9179 pvclock_update_vm_gtod_copy(kvm); 9180 9181 kvm->arch.guest_can_read_msr_platform_info = true; 9182 9183 INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn); 9184 INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn); 9185 9186 kvm_hv_init_vm(kvm); 9187 kvm_page_track_init(kvm); 9188 kvm_mmu_init_vm(kvm); 9189 9190 if (kvm_x86_ops->vm_init) 9191 return kvm_x86_ops->vm_init(kvm); 9192 9193 return 0; 9194 } 9195 9196 static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu) 9197 { 9198 vcpu_load(vcpu); 9199 kvm_mmu_unload(vcpu); 9200 vcpu_put(vcpu); 9201 } 9202 9203 static void kvm_free_vcpus(struct kvm *kvm) 9204 { 9205 unsigned int i; 9206 struct kvm_vcpu *vcpu; 9207 9208 /* 9209 * Unpin any mmu pages first. 9210 */ 9211 kvm_for_each_vcpu(i, vcpu, kvm) { 9212 kvm_clear_async_pf_completion_queue(vcpu); 9213 kvm_unload_vcpu_mmu(vcpu); 9214 } 9215 kvm_for_each_vcpu(i, vcpu, kvm) 9216 kvm_arch_vcpu_free(vcpu); 9217 9218 mutex_lock(&kvm->lock); 9219 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++) 9220 kvm->vcpus[i] = NULL; 9221 9222 atomic_set(&kvm->online_vcpus, 0); 9223 mutex_unlock(&kvm->lock); 9224 } 9225 9226 void kvm_arch_sync_events(struct kvm *kvm) 9227 { 9228 cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work); 9229 cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work); 9230 kvm_free_pit(kvm); 9231 } 9232 9233 int __x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size) 9234 { 9235 int i, r; 9236 unsigned long hva; 9237 struct kvm_memslots *slots = kvm_memslots(kvm); 9238 struct kvm_memory_slot *slot, old; 9239 9240 /* Called with kvm->slots_lock held. */ 9241 if (WARN_ON(id >= KVM_MEM_SLOTS_NUM)) 9242 return -EINVAL; 9243 9244 slot = id_to_memslot(slots, id); 9245 if (size) { 9246 if (slot->npages) 9247 return -EEXIST; 9248 9249 /* 9250 * MAP_SHARED to prevent internal slot pages from being moved 9251 * by fork()/COW. 9252 */ 9253 hva = vm_mmap(NULL, 0, size, PROT_READ | PROT_WRITE, 9254 MAP_SHARED | MAP_ANONYMOUS, 0); 9255 if (IS_ERR((void *)hva)) 9256 return PTR_ERR((void *)hva); 9257 } else { 9258 if (!slot->npages) 9259 return 0; 9260 9261 hva = 0; 9262 } 9263 9264 old = *slot; 9265 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) { 9266 struct kvm_userspace_memory_region m; 9267 9268 m.slot = id | (i << 16); 9269 m.flags = 0; 9270 m.guest_phys_addr = gpa; 9271 m.userspace_addr = hva; 9272 m.memory_size = size; 9273 r = __kvm_set_memory_region(kvm, &m); 9274 if (r < 0) 9275 return r; 9276 } 9277 9278 if (!size) 9279 vm_munmap(old.userspace_addr, old.npages * PAGE_SIZE); 9280 9281 return 0; 9282 } 9283 EXPORT_SYMBOL_GPL(__x86_set_memory_region); 9284 9285 int x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size) 9286 { 9287 int r; 9288 9289 mutex_lock(&kvm->slots_lock); 9290 r = __x86_set_memory_region(kvm, id, gpa, size); 9291 mutex_unlock(&kvm->slots_lock); 9292 9293 return r; 9294 } 9295 EXPORT_SYMBOL_GPL(x86_set_memory_region); 9296 9297 void kvm_arch_destroy_vm(struct kvm *kvm) 9298 { 9299 if (current->mm == kvm->mm) { 9300 /* 9301 * Free memory regions allocated on behalf of userspace, 9302 * unless the the memory map has changed due to process exit 9303 * or fd copying. 9304 */ 9305 x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT, 0, 0); 9306 x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT, 0, 0); 9307 x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, 0, 0); 9308 } 9309 if (kvm_x86_ops->vm_destroy) 9310 kvm_x86_ops->vm_destroy(kvm); 9311 kvm_pic_destroy(kvm); 9312 kvm_ioapic_destroy(kvm); 9313 kvm_free_vcpus(kvm); 9314 kvfree(rcu_dereference_check(kvm->arch.apic_map, 1)); 9315 kvm_mmu_uninit_vm(kvm); 9316 kvm_page_track_cleanup(kvm); 9317 kvm_hv_destroy_vm(kvm); 9318 } 9319 9320 void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *free, 9321 struct kvm_memory_slot *dont) 9322 { 9323 int i; 9324 9325 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) { 9326 if (!dont || free->arch.rmap[i] != dont->arch.rmap[i]) { 9327 kvfree(free->arch.rmap[i]); 9328 free->arch.rmap[i] = NULL; 9329 } 9330 if (i == 0) 9331 continue; 9332 9333 if (!dont || free->arch.lpage_info[i - 1] != 9334 dont->arch.lpage_info[i - 1]) { 9335 kvfree(free->arch.lpage_info[i - 1]); 9336 free->arch.lpage_info[i - 1] = NULL; 9337 } 9338 } 9339 9340 kvm_page_track_free_memslot(free, dont); 9341 } 9342 9343 int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot, 9344 unsigned long npages) 9345 { 9346 int i; 9347 9348 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) { 9349 struct kvm_lpage_info *linfo; 9350 unsigned long ugfn; 9351 int lpages; 9352 int level = i + 1; 9353 9354 lpages = gfn_to_index(slot->base_gfn + npages - 1, 9355 slot->base_gfn, level) + 1; 9356 9357 slot->arch.rmap[i] = 9358 kvcalloc(lpages, sizeof(*slot->arch.rmap[i]), 9359 GFP_KERNEL_ACCOUNT); 9360 if (!slot->arch.rmap[i]) 9361 goto out_free; 9362 if (i == 0) 9363 continue; 9364 9365 linfo = kvcalloc(lpages, sizeof(*linfo), GFP_KERNEL_ACCOUNT); 9366 if (!linfo) 9367 goto out_free; 9368 9369 slot->arch.lpage_info[i - 1] = linfo; 9370 9371 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1)) 9372 linfo[0].disallow_lpage = 1; 9373 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1)) 9374 linfo[lpages - 1].disallow_lpage = 1; 9375 ugfn = slot->userspace_addr >> PAGE_SHIFT; 9376 /* 9377 * If the gfn and userspace address are not aligned wrt each 9378 * other, or if explicitly asked to, disable large page 9379 * support for this slot 9380 */ 9381 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) || 9382 !kvm_largepages_enabled()) { 9383 unsigned long j; 9384 9385 for (j = 0; j < lpages; ++j) 9386 linfo[j].disallow_lpage = 1; 9387 } 9388 } 9389 9390 if (kvm_page_track_create_memslot(slot, npages)) 9391 goto out_free; 9392 9393 return 0; 9394 9395 out_free: 9396 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) { 9397 kvfree(slot->arch.rmap[i]); 9398 slot->arch.rmap[i] = NULL; 9399 if (i == 0) 9400 continue; 9401 9402 kvfree(slot->arch.lpage_info[i - 1]); 9403 slot->arch.lpage_info[i - 1] = NULL; 9404 } 9405 return -ENOMEM; 9406 } 9407 9408 void kvm_arch_memslots_updated(struct kvm *kvm, u64 gen) 9409 { 9410 /* 9411 * memslots->generation has been incremented. 9412 * mmio generation may have reached its maximum value. 9413 */ 9414 kvm_mmu_invalidate_mmio_sptes(kvm, gen); 9415 } 9416 9417 int kvm_arch_prepare_memory_region(struct kvm *kvm, 9418 struct kvm_memory_slot *memslot, 9419 const struct kvm_userspace_memory_region *mem, 9420 enum kvm_mr_change change) 9421 { 9422 return 0; 9423 } 9424 9425 static void kvm_mmu_slot_apply_flags(struct kvm *kvm, 9426 struct kvm_memory_slot *new) 9427 { 9428 /* Still write protect RO slot */ 9429 if (new->flags & KVM_MEM_READONLY) { 9430 kvm_mmu_slot_remove_write_access(kvm, new); 9431 return; 9432 } 9433 9434 /* 9435 * Call kvm_x86_ops dirty logging hooks when they are valid. 9436 * 9437 * kvm_x86_ops->slot_disable_log_dirty is called when: 9438 * 9439 * - KVM_MR_CREATE with dirty logging is disabled 9440 * - KVM_MR_FLAGS_ONLY with dirty logging is disabled in new flag 9441 * 9442 * The reason is, in case of PML, we need to set D-bit for any slots 9443 * with dirty logging disabled in order to eliminate unnecessary GPA 9444 * logging in PML buffer (and potential PML buffer full VMEXT). This 9445 * guarantees leaving PML enabled during guest's lifetime won't have 9446 * any additional overhead from PML when guest is running with dirty 9447 * logging disabled for memory slots. 9448 * 9449 * kvm_x86_ops->slot_enable_log_dirty is called when switching new slot 9450 * to dirty logging mode. 9451 * 9452 * If kvm_x86_ops dirty logging hooks are invalid, use write protect. 9453 * 9454 * In case of write protect: 9455 * 9456 * Write protect all pages for dirty logging. 9457 * 9458 * All the sptes including the large sptes which point to this 9459 * slot are set to readonly. We can not create any new large 9460 * spte on this slot until the end of the logging. 9461 * 9462 * See the comments in fast_page_fault(). 9463 */ 9464 if (new->flags & KVM_MEM_LOG_DIRTY_PAGES) { 9465 if (kvm_x86_ops->slot_enable_log_dirty) 9466 kvm_x86_ops->slot_enable_log_dirty(kvm, new); 9467 else 9468 kvm_mmu_slot_remove_write_access(kvm, new); 9469 } else { 9470 if (kvm_x86_ops->slot_disable_log_dirty) 9471 kvm_x86_ops->slot_disable_log_dirty(kvm, new); 9472 } 9473 } 9474 9475 void kvm_arch_commit_memory_region(struct kvm *kvm, 9476 const struct kvm_userspace_memory_region *mem, 9477 const struct kvm_memory_slot *old, 9478 const struct kvm_memory_slot *new, 9479 enum kvm_mr_change change) 9480 { 9481 if (!kvm->arch.n_requested_mmu_pages) 9482 kvm_mmu_change_mmu_pages(kvm, 9483 kvm_mmu_calculate_default_mmu_pages(kvm)); 9484 9485 /* 9486 * Dirty logging tracks sptes in 4k granularity, meaning that large 9487 * sptes have to be split. If live migration is successful, the guest 9488 * in the source machine will be destroyed and large sptes will be 9489 * created in the destination. However, if the guest continues to run 9490 * in the source machine (for example if live migration fails), small 9491 * sptes will remain around and cause bad performance. 9492 * 9493 * Scan sptes if dirty logging has been stopped, dropping those 9494 * which can be collapsed into a single large-page spte. Later 9495 * page faults will create the large-page sptes. 9496 */ 9497 if ((change != KVM_MR_DELETE) && 9498 (old->flags & KVM_MEM_LOG_DIRTY_PAGES) && 9499 !(new->flags & KVM_MEM_LOG_DIRTY_PAGES)) 9500 kvm_mmu_zap_collapsible_sptes(kvm, new); 9501 9502 /* 9503 * Set up write protection and/or dirty logging for the new slot. 9504 * 9505 * For KVM_MR_DELETE and KVM_MR_MOVE, the shadow pages of old slot have 9506 * been zapped so no dirty logging staff is needed for old slot. For 9507 * KVM_MR_FLAGS_ONLY, the old slot is essentially the same one as the 9508 * new and it's also covered when dealing with the new slot. 9509 * 9510 * FIXME: const-ify all uses of struct kvm_memory_slot. 9511 */ 9512 if (change != KVM_MR_DELETE) 9513 kvm_mmu_slot_apply_flags(kvm, (struct kvm_memory_slot *) new); 9514 } 9515 9516 void kvm_arch_flush_shadow_all(struct kvm *kvm) 9517 { 9518 kvm_mmu_zap_all(kvm); 9519 } 9520 9521 void kvm_arch_flush_shadow_memslot(struct kvm *kvm, 9522 struct kvm_memory_slot *slot) 9523 { 9524 kvm_page_track_flush_slot(kvm, slot); 9525 } 9526 9527 static inline bool kvm_guest_apic_has_interrupt(struct kvm_vcpu *vcpu) 9528 { 9529 return (is_guest_mode(vcpu) && 9530 kvm_x86_ops->guest_apic_has_interrupt && 9531 kvm_x86_ops->guest_apic_has_interrupt(vcpu)); 9532 } 9533 9534 static inline bool kvm_vcpu_has_events(struct kvm_vcpu *vcpu) 9535 { 9536 if (!list_empty_careful(&vcpu->async_pf.done)) 9537 return true; 9538 9539 if (kvm_apic_has_events(vcpu)) 9540 return true; 9541 9542 if (vcpu->arch.pv.pv_unhalted) 9543 return true; 9544 9545 if (vcpu->arch.exception.pending) 9546 return true; 9547 9548 if (kvm_test_request(KVM_REQ_NMI, vcpu) || 9549 (vcpu->arch.nmi_pending && 9550 kvm_x86_ops->nmi_allowed(vcpu))) 9551 return true; 9552 9553 if (kvm_test_request(KVM_REQ_SMI, vcpu) || 9554 (vcpu->arch.smi_pending && !is_smm(vcpu))) 9555 return true; 9556 9557 if (kvm_arch_interrupt_allowed(vcpu) && 9558 (kvm_cpu_has_interrupt(vcpu) || 9559 kvm_guest_apic_has_interrupt(vcpu))) 9560 return true; 9561 9562 if (kvm_hv_has_stimer_pending(vcpu)) 9563 return true; 9564 9565 return false; 9566 } 9567 9568 int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu) 9569 { 9570 return kvm_vcpu_running(vcpu) || kvm_vcpu_has_events(vcpu); 9571 } 9572 9573 bool kvm_arch_vcpu_in_kernel(struct kvm_vcpu *vcpu) 9574 { 9575 return vcpu->arch.preempted_in_kernel; 9576 } 9577 9578 int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu) 9579 { 9580 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE; 9581 } 9582 9583 int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu) 9584 { 9585 return kvm_x86_ops->interrupt_allowed(vcpu); 9586 } 9587 9588 unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu) 9589 { 9590 if (is_64_bit_mode(vcpu)) 9591 return kvm_rip_read(vcpu); 9592 return (u32)(get_segment_base(vcpu, VCPU_SREG_CS) + 9593 kvm_rip_read(vcpu)); 9594 } 9595 EXPORT_SYMBOL_GPL(kvm_get_linear_rip); 9596 9597 bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip) 9598 { 9599 return kvm_get_linear_rip(vcpu) == linear_rip; 9600 } 9601 EXPORT_SYMBOL_GPL(kvm_is_linear_rip); 9602 9603 unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu) 9604 { 9605 unsigned long rflags; 9606 9607 rflags = kvm_x86_ops->get_rflags(vcpu); 9608 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) 9609 rflags &= ~X86_EFLAGS_TF; 9610 return rflags; 9611 } 9612 EXPORT_SYMBOL_GPL(kvm_get_rflags); 9613 9614 static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags) 9615 { 9616 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP && 9617 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip)) 9618 rflags |= X86_EFLAGS_TF; 9619 kvm_x86_ops->set_rflags(vcpu, rflags); 9620 } 9621 9622 void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags) 9623 { 9624 __kvm_set_rflags(vcpu, rflags); 9625 kvm_make_request(KVM_REQ_EVENT, vcpu); 9626 } 9627 EXPORT_SYMBOL_GPL(kvm_set_rflags); 9628 9629 void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work) 9630 { 9631 int r; 9632 9633 if ((vcpu->arch.mmu->direct_map != work->arch.direct_map) || 9634 work->wakeup_all) 9635 return; 9636 9637 r = kvm_mmu_reload(vcpu); 9638 if (unlikely(r)) 9639 return; 9640 9641 if (!vcpu->arch.mmu->direct_map && 9642 work->arch.cr3 != vcpu->arch.mmu->get_cr3(vcpu)) 9643 return; 9644 9645 vcpu->arch.mmu->page_fault(vcpu, work->gva, 0, true); 9646 } 9647 9648 static inline u32 kvm_async_pf_hash_fn(gfn_t gfn) 9649 { 9650 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU)); 9651 } 9652 9653 static inline u32 kvm_async_pf_next_probe(u32 key) 9654 { 9655 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1); 9656 } 9657 9658 static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn) 9659 { 9660 u32 key = kvm_async_pf_hash_fn(gfn); 9661 9662 while (vcpu->arch.apf.gfns[key] != ~0) 9663 key = kvm_async_pf_next_probe(key); 9664 9665 vcpu->arch.apf.gfns[key] = gfn; 9666 } 9667 9668 static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn) 9669 { 9670 int i; 9671 u32 key = kvm_async_pf_hash_fn(gfn); 9672 9673 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) && 9674 (vcpu->arch.apf.gfns[key] != gfn && 9675 vcpu->arch.apf.gfns[key] != ~0); i++) 9676 key = kvm_async_pf_next_probe(key); 9677 9678 return key; 9679 } 9680 9681 bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn) 9682 { 9683 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn; 9684 } 9685 9686 static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn) 9687 { 9688 u32 i, j, k; 9689 9690 i = j = kvm_async_pf_gfn_slot(vcpu, gfn); 9691 while (true) { 9692 vcpu->arch.apf.gfns[i] = ~0; 9693 do { 9694 j = kvm_async_pf_next_probe(j); 9695 if (vcpu->arch.apf.gfns[j] == ~0) 9696 return; 9697 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]); 9698 /* 9699 * k lies cyclically in ]i,j] 9700 * | i.k.j | 9701 * |....j i.k.| or |.k..j i...| 9702 */ 9703 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j)); 9704 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j]; 9705 i = j; 9706 } 9707 } 9708 9709 static int apf_put_user(struct kvm_vcpu *vcpu, u32 val) 9710 { 9711 9712 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val, 9713 sizeof(val)); 9714 } 9715 9716 static int apf_get_user(struct kvm_vcpu *vcpu, u32 *val) 9717 { 9718 9719 return kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, val, 9720 sizeof(u32)); 9721 } 9722 9723 void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu, 9724 struct kvm_async_pf *work) 9725 { 9726 struct x86_exception fault; 9727 9728 trace_kvm_async_pf_not_present(work->arch.token, work->gva); 9729 kvm_add_async_pf_gfn(vcpu, work->arch.gfn); 9730 9731 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) || 9732 (vcpu->arch.apf.send_user_only && 9733 kvm_x86_ops->get_cpl(vcpu) == 0)) 9734 kvm_make_request(KVM_REQ_APF_HALT, vcpu); 9735 else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) { 9736 fault.vector = PF_VECTOR; 9737 fault.error_code_valid = true; 9738 fault.error_code = 0; 9739 fault.nested_page_fault = false; 9740 fault.address = work->arch.token; 9741 fault.async_page_fault = true; 9742 kvm_inject_page_fault(vcpu, &fault); 9743 } 9744 } 9745 9746 void kvm_arch_async_page_present(struct kvm_vcpu *vcpu, 9747 struct kvm_async_pf *work) 9748 { 9749 struct x86_exception fault; 9750 u32 val; 9751 9752 if (work->wakeup_all) 9753 work->arch.token = ~0; /* broadcast wakeup */ 9754 else 9755 kvm_del_async_pf_gfn(vcpu, work->arch.gfn); 9756 trace_kvm_async_pf_ready(work->arch.token, work->gva); 9757 9758 if (vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED && 9759 !apf_get_user(vcpu, &val)) { 9760 if (val == KVM_PV_REASON_PAGE_NOT_PRESENT && 9761 vcpu->arch.exception.pending && 9762 vcpu->arch.exception.nr == PF_VECTOR && 9763 !apf_put_user(vcpu, 0)) { 9764 vcpu->arch.exception.injected = false; 9765 vcpu->arch.exception.pending = false; 9766 vcpu->arch.exception.nr = 0; 9767 vcpu->arch.exception.has_error_code = false; 9768 vcpu->arch.exception.error_code = 0; 9769 vcpu->arch.exception.has_payload = false; 9770 vcpu->arch.exception.payload = 0; 9771 } else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) { 9772 fault.vector = PF_VECTOR; 9773 fault.error_code_valid = true; 9774 fault.error_code = 0; 9775 fault.nested_page_fault = false; 9776 fault.address = work->arch.token; 9777 fault.async_page_fault = true; 9778 kvm_inject_page_fault(vcpu, &fault); 9779 } 9780 } 9781 vcpu->arch.apf.halted = false; 9782 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; 9783 } 9784 9785 bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu) 9786 { 9787 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED)) 9788 return true; 9789 else 9790 return kvm_can_do_async_pf(vcpu); 9791 } 9792 9793 void kvm_arch_start_assignment(struct kvm *kvm) 9794 { 9795 atomic_inc(&kvm->arch.assigned_device_count); 9796 } 9797 EXPORT_SYMBOL_GPL(kvm_arch_start_assignment); 9798 9799 void kvm_arch_end_assignment(struct kvm *kvm) 9800 { 9801 atomic_dec(&kvm->arch.assigned_device_count); 9802 } 9803 EXPORT_SYMBOL_GPL(kvm_arch_end_assignment); 9804 9805 bool kvm_arch_has_assigned_device(struct kvm *kvm) 9806 { 9807 return atomic_read(&kvm->arch.assigned_device_count); 9808 } 9809 EXPORT_SYMBOL_GPL(kvm_arch_has_assigned_device); 9810 9811 void kvm_arch_register_noncoherent_dma(struct kvm *kvm) 9812 { 9813 atomic_inc(&kvm->arch.noncoherent_dma_count); 9814 } 9815 EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma); 9816 9817 void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm) 9818 { 9819 atomic_dec(&kvm->arch.noncoherent_dma_count); 9820 } 9821 EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma); 9822 9823 bool kvm_arch_has_noncoherent_dma(struct kvm *kvm) 9824 { 9825 return atomic_read(&kvm->arch.noncoherent_dma_count); 9826 } 9827 EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma); 9828 9829 bool kvm_arch_has_irq_bypass(void) 9830 { 9831 return kvm_x86_ops->update_pi_irte != NULL; 9832 } 9833 9834 int kvm_arch_irq_bypass_add_producer(struct irq_bypass_consumer *cons, 9835 struct irq_bypass_producer *prod) 9836 { 9837 struct kvm_kernel_irqfd *irqfd = 9838 container_of(cons, struct kvm_kernel_irqfd, consumer); 9839 9840 irqfd->producer = prod; 9841 9842 return kvm_x86_ops->update_pi_irte(irqfd->kvm, 9843 prod->irq, irqfd->gsi, 1); 9844 } 9845 9846 void kvm_arch_irq_bypass_del_producer(struct irq_bypass_consumer *cons, 9847 struct irq_bypass_producer *prod) 9848 { 9849 int ret; 9850 struct kvm_kernel_irqfd *irqfd = 9851 container_of(cons, struct kvm_kernel_irqfd, consumer); 9852 9853 WARN_ON(irqfd->producer != prod); 9854 irqfd->producer = NULL; 9855 9856 /* 9857 * When producer of consumer is unregistered, we change back to 9858 * remapped mode, so we can re-use the current implementation 9859 * when the irq is masked/disabled or the consumer side (KVM 9860 * int this case doesn't want to receive the interrupts. 9861 */ 9862 ret = kvm_x86_ops->update_pi_irte(irqfd->kvm, prod->irq, irqfd->gsi, 0); 9863 if (ret) 9864 printk(KERN_INFO "irq bypass consumer (token %p) unregistration" 9865 " fails: %d\n", irqfd->consumer.token, ret); 9866 } 9867 9868 int kvm_arch_update_irqfd_routing(struct kvm *kvm, unsigned int host_irq, 9869 uint32_t guest_irq, bool set) 9870 { 9871 if (!kvm_x86_ops->update_pi_irte) 9872 return -EINVAL; 9873 9874 return kvm_x86_ops->update_pi_irte(kvm, host_irq, guest_irq, set); 9875 } 9876 9877 bool kvm_vector_hashing_enabled(void) 9878 { 9879 return vector_hashing; 9880 } 9881 EXPORT_SYMBOL_GPL(kvm_vector_hashing_enabled); 9882 9883 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit); 9884 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_fast_mmio); 9885 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq); 9886 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault); 9887 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr); 9888 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr); 9889 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun); 9890 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit); 9891 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject); 9892 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit); 9893 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga); 9894 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit); 9895 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts); 9896 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset); 9897 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_ple_window); 9898 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pml_full); 9899 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pi_irte_update); 9900 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_unaccelerated_access); 9901 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_incomplete_ipi); 9902