1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Kernel-based Virtual Machine driver for Linux 4 * 5 * derived from drivers/kvm/kvm_main.c 6 * 7 * Copyright (C) 2006 Qumranet, Inc. 8 * Copyright (C) 2008 Qumranet, Inc. 9 * Copyright IBM Corporation, 2008 10 * Copyright 2010 Red Hat, Inc. and/or its affiliates. 11 * 12 * Authors: 13 * Avi Kivity <avi@qumranet.com> 14 * Yaniv Kamay <yaniv@qumranet.com> 15 * Amit Shah <amit.shah@qumranet.com> 16 * Ben-Ami Yassour <benami@il.ibm.com> 17 */ 18 19 #include <linux/kvm_host.h> 20 #include "irq.h" 21 #include "ioapic.h" 22 #include "mmu.h" 23 #include "i8254.h" 24 #include "tss.h" 25 #include "kvm_cache_regs.h" 26 #include "kvm_emulate.h" 27 #include "x86.h" 28 #include "cpuid.h" 29 #include "pmu.h" 30 #include "hyperv.h" 31 #include "lapic.h" 32 #include "xen.h" 33 34 #include <linux/clocksource.h> 35 #include <linux/interrupt.h> 36 #include <linux/kvm.h> 37 #include <linux/fs.h> 38 #include <linux/vmalloc.h> 39 #include <linux/export.h> 40 #include <linux/moduleparam.h> 41 #include <linux/mman.h> 42 #include <linux/highmem.h> 43 #include <linux/iommu.h> 44 #include <linux/intel-iommu.h> 45 #include <linux/cpufreq.h> 46 #include <linux/user-return-notifier.h> 47 #include <linux/srcu.h> 48 #include <linux/slab.h> 49 #include <linux/perf_event.h> 50 #include <linux/uaccess.h> 51 #include <linux/hash.h> 52 #include <linux/pci.h> 53 #include <linux/timekeeper_internal.h> 54 #include <linux/pvclock_gtod.h> 55 #include <linux/kvm_irqfd.h> 56 #include <linux/irqbypass.h> 57 #include <linux/sched/stat.h> 58 #include <linux/sched/isolation.h> 59 #include <linux/mem_encrypt.h> 60 #include <linux/entry-kvm.h> 61 62 #include <trace/events/kvm.h> 63 64 #include <asm/debugreg.h> 65 #include <asm/msr.h> 66 #include <asm/desc.h> 67 #include <asm/mce.h> 68 #include <linux/kernel_stat.h> 69 #include <asm/fpu/internal.h> /* Ugh! */ 70 #include <asm/pvclock.h> 71 #include <asm/div64.h> 72 #include <asm/irq_remapping.h> 73 #include <asm/mshyperv.h> 74 #include <asm/hypervisor.h> 75 #include <asm/tlbflush.h> 76 #include <asm/intel_pt.h> 77 #include <asm/emulate_prefix.h> 78 #include <asm/sgx.h> 79 #include <clocksource/hyperv_timer.h> 80 81 #define CREATE_TRACE_POINTS 82 #include "trace.h" 83 84 #define MAX_IO_MSRS 256 85 #define KVM_MAX_MCE_BANKS 32 86 u64 __read_mostly kvm_mce_cap_supported = MCG_CTL_P | MCG_SER_P; 87 EXPORT_SYMBOL_GPL(kvm_mce_cap_supported); 88 89 #define emul_to_vcpu(ctxt) \ 90 ((struct kvm_vcpu *)(ctxt)->vcpu) 91 92 /* EFER defaults: 93 * - enable syscall per default because its emulated by KVM 94 * - enable LME and LMA per default on 64 bit KVM 95 */ 96 #ifdef CONFIG_X86_64 97 static 98 u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA)); 99 #else 100 static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE); 101 #endif 102 103 static u64 __read_mostly cr4_reserved_bits = CR4_RESERVED_BITS; 104 105 #define KVM_X2APIC_API_VALID_FLAGS (KVM_X2APIC_API_USE_32BIT_IDS | \ 106 KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK) 107 108 static void update_cr8_intercept(struct kvm_vcpu *vcpu); 109 static void process_nmi(struct kvm_vcpu *vcpu); 110 static void process_smi(struct kvm_vcpu *vcpu); 111 static void enter_smm(struct kvm_vcpu *vcpu); 112 static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags); 113 static void store_regs(struct kvm_vcpu *vcpu); 114 static int sync_regs(struct kvm_vcpu *vcpu); 115 116 struct kvm_x86_ops kvm_x86_ops __read_mostly; 117 EXPORT_SYMBOL_GPL(kvm_x86_ops); 118 119 #define KVM_X86_OP(func) \ 120 DEFINE_STATIC_CALL_NULL(kvm_x86_##func, \ 121 *(((struct kvm_x86_ops *)0)->func)); 122 #define KVM_X86_OP_NULL KVM_X86_OP 123 #include <asm/kvm-x86-ops.h> 124 EXPORT_STATIC_CALL_GPL(kvm_x86_get_cs_db_l_bits); 125 EXPORT_STATIC_CALL_GPL(kvm_x86_cache_reg); 126 EXPORT_STATIC_CALL_GPL(kvm_x86_tlb_flush_current); 127 128 static bool __read_mostly ignore_msrs = 0; 129 module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR); 130 131 bool __read_mostly report_ignored_msrs = true; 132 module_param(report_ignored_msrs, bool, S_IRUGO | S_IWUSR); 133 EXPORT_SYMBOL_GPL(report_ignored_msrs); 134 135 unsigned int min_timer_period_us = 200; 136 module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR); 137 138 static bool __read_mostly kvmclock_periodic_sync = true; 139 module_param(kvmclock_periodic_sync, bool, S_IRUGO); 140 141 bool __read_mostly kvm_has_tsc_control; 142 EXPORT_SYMBOL_GPL(kvm_has_tsc_control); 143 u32 __read_mostly kvm_max_guest_tsc_khz; 144 EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz); 145 u8 __read_mostly kvm_tsc_scaling_ratio_frac_bits; 146 EXPORT_SYMBOL_GPL(kvm_tsc_scaling_ratio_frac_bits); 147 u64 __read_mostly kvm_max_tsc_scaling_ratio; 148 EXPORT_SYMBOL_GPL(kvm_max_tsc_scaling_ratio); 149 u64 __read_mostly kvm_default_tsc_scaling_ratio; 150 EXPORT_SYMBOL_GPL(kvm_default_tsc_scaling_ratio); 151 bool __read_mostly kvm_has_bus_lock_exit; 152 EXPORT_SYMBOL_GPL(kvm_has_bus_lock_exit); 153 154 /* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */ 155 static u32 __read_mostly tsc_tolerance_ppm = 250; 156 module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR); 157 158 /* 159 * lapic timer advance (tscdeadline mode only) in nanoseconds. '-1' enables 160 * adaptive tuning starting from default advancement of 1000ns. '0' disables 161 * advancement entirely. Any other value is used as-is and disables adaptive 162 * tuning, i.e. allows privileged userspace to set an exact advancement time. 163 */ 164 static int __read_mostly lapic_timer_advance_ns = -1; 165 module_param(lapic_timer_advance_ns, int, S_IRUGO | S_IWUSR); 166 167 static bool __read_mostly vector_hashing = true; 168 module_param(vector_hashing, bool, S_IRUGO); 169 170 bool __read_mostly enable_vmware_backdoor = false; 171 module_param(enable_vmware_backdoor, bool, S_IRUGO); 172 EXPORT_SYMBOL_GPL(enable_vmware_backdoor); 173 174 static bool __read_mostly force_emulation_prefix = false; 175 module_param(force_emulation_prefix, bool, S_IRUGO); 176 177 int __read_mostly pi_inject_timer = -1; 178 module_param(pi_inject_timer, bint, S_IRUGO | S_IWUSR); 179 180 /* 181 * Restoring the host value for MSRs that are only consumed when running in 182 * usermode, e.g. SYSCALL MSRs and TSC_AUX, can be deferred until the CPU 183 * returns to userspace, i.e. the kernel can run with the guest's value. 184 */ 185 #define KVM_MAX_NR_USER_RETURN_MSRS 16 186 187 struct kvm_user_return_msrs { 188 struct user_return_notifier urn; 189 bool registered; 190 struct kvm_user_return_msr_values { 191 u64 host; 192 u64 curr; 193 } values[KVM_MAX_NR_USER_RETURN_MSRS]; 194 }; 195 196 u32 __read_mostly kvm_nr_uret_msrs; 197 EXPORT_SYMBOL_GPL(kvm_nr_uret_msrs); 198 static u32 __read_mostly kvm_uret_msrs_list[KVM_MAX_NR_USER_RETURN_MSRS]; 199 static struct kvm_user_return_msrs __percpu *user_return_msrs; 200 201 #define KVM_SUPPORTED_XCR0 (XFEATURE_MASK_FP | XFEATURE_MASK_SSE \ 202 | XFEATURE_MASK_YMM | XFEATURE_MASK_BNDREGS \ 203 | XFEATURE_MASK_BNDCSR | XFEATURE_MASK_AVX512 \ 204 | XFEATURE_MASK_PKRU) 205 206 u64 __read_mostly host_efer; 207 EXPORT_SYMBOL_GPL(host_efer); 208 209 bool __read_mostly allow_smaller_maxphyaddr = 0; 210 EXPORT_SYMBOL_GPL(allow_smaller_maxphyaddr); 211 212 u64 __read_mostly host_xss; 213 EXPORT_SYMBOL_GPL(host_xss); 214 u64 __read_mostly supported_xss; 215 EXPORT_SYMBOL_GPL(supported_xss); 216 217 struct kvm_stats_debugfs_item debugfs_entries[] = { 218 VCPU_STAT("pf_fixed", pf_fixed), 219 VCPU_STAT("pf_guest", pf_guest), 220 VCPU_STAT("tlb_flush", tlb_flush), 221 VCPU_STAT("invlpg", invlpg), 222 VCPU_STAT("exits", exits), 223 VCPU_STAT("io_exits", io_exits), 224 VCPU_STAT("mmio_exits", mmio_exits), 225 VCPU_STAT("signal_exits", signal_exits), 226 VCPU_STAT("irq_window", irq_window_exits), 227 VCPU_STAT("nmi_window", nmi_window_exits), 228 VCPU_STAT("halt_exits", halt_exits), 229 VCPU_STAT("halt_successful_poll", halt_successful_poll), 230 VCPU_STAT("halt_attempted_poll", halt_attempted_poll), 231 VCPU_STAT("halt_poll_invalid", halt_poll_invalid), 232 VCPU_STAT("halt_wakeup", halt_wakeup), 233 VCPU_STAT("hypercalls", hypercalls), 234 VCPU_STAT("request_irq", request_irq_exits), 235 VCPU_STAT("irq_exits", irq_exits), 236 VCPU_STAT("host_state_reload", host_state_reload), 237 VCPU_STAT("fpu_reload", fpu_reload), 238 VCPU_STAT("insn_emulation", insn_emulation), 239 VCPU_STAT("insn_emulation_fail", insn_emulation_fail), 240 VCPU_STAT("irq_injections", irq_injections), 241 VCPU_STAT("nmi_injections", nmi_injections), 242 VCPU_STAT("req_event", req_event), 243 VCPU_STAT("l1d_flush", l1d_flush), 244 VCPU_STAT("halt_poll_success_ns", halt_poll_success_ns), 245 VCPU_STAT("halt_poll_fail_ns", halt_poll_fail_ns), 246 VCPU_STAT("nested_run", nested_run), 247 VCPU_STAT("directed_yield_attempted", directed_yield_attempted), 248 VCPU_STAT("directed_yield_successful", directed_yield_successful), 249 VM_STAT("mmu_shadow_zapped", mmu_shadow_zapped), 250 VM_STAT("mmu_pte_write", mmu_pte_write), 251 VM_STAT("mmu_pde_zapped", mmu_pde_zapped), 252 VM_STAT("mmu_flooded", mmu_flooded), 253 VM_STAT("mmu_recycled", mmu_recycled), 254 VM_STAT("mmu_cache_miss", mmu_cache_miss), 255 VM_STAT("mmu_unsync", mmu_unsync), 256 VM_STAT("remote_tlb_flush", remote_tlb_flush), 257 VM_STAT("largepages", lpages, .mode = 0444), 258 VM_STAT("nx_largepages_splitted", nx_lpage_splits, .mode = 0444), 259 VM_STAT("max_mmu_page_hash_collisions", max_mmu_page_hash_collisions), 260 { NULL } 261 }; 262 263 u64 __read_mostly host_xcr0; 264 u64 __read_mostly supported_xcr0; 265 EXPORT_SYMBOL_GPL(supported_xcr0); 266 267 static struct kmem_cache *x86_fpu_cache; 268 269 static struct kmem_cache *x86_emulator_cache; 270 271 /* 272 * When called, it means the previous get/set msr reached an invalid msr. 273 * Return true if we want to ignore/silent this failed msr access. 274 */ 275 static bool kvm_msr_ignored_check(u32 msr, u64 data, bool write) 276 { 277 const char *op = write ? "wrmsr" : "rdmsr"; 278 279 if (ignore_msrs) { 280 if (report_ignored_msrs) 281 kvm_pr_unimpl("ignored %s: 0x%x data 0x%llx\n", 282 op, msr, data); 283 /* Mask the error */ 284 return true; 285 } else { 286 kvm_debug_ratelimited("unhandled %s: 0x%x data 0x%llx\n", 287 op, msr, data); 288 return false; 289 } 290 } 291 292 static struct kmem_cache *kvm_alloc_emulator_cache(void) 293 { 294 unsigned int useroffset = offsetof(struct x86_emulate_ctxt, src); 295 unsigned int size = sizeof(struct x86_emulate_ctxt); 296 297 return kmem_cache_create_usercopy("x86_emulator", size, 298 __alignof__(struct x86_emulate_ctxt), 299 SLAB_ACCOUNT, useroffset, 300 size - useroffset, NULL); 301 } 302 303 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt); 304 305 static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu) 306 { 307 int i; 308 for (i = 0; i < ASYNC_PF_PER_VCPU; i++) 309 vcpu->arch.apf.gfns[i] = ~0; 310 } 311 312 static void kvm_on_user_return(struct user_return_notifier *urn) 313 { 314 unsigned slot; 315 struct kvm_user_return_msrs *msrs 316 = container_of(urn, struct kvm_user_return_msrs, urn); 317 struct kvm_user_return_msr_values *values; 318 unsigned long flags; 319 320 /* 321 * Disabling irqs at this point since the following code could be 322 * interrupted and executed through kvm_arch_hardware_disable() 323 */ 324 local_irq_save(flags); 325 if (msrs->registered) { 326 msrs->registered = false; 327 user_return_notifier_unregister(urn); 328 } 329 local_irq_restore(flags); 330 for (slot = 0; slot < kvm_nr_uret_msrs; ++slot) { 331 values = &msrs->values[slot]; 332 if (values->host != values->curr) { 333 wrmsrl(kvm_uret_msrs_list[slot], values->host); 334 values->curr = values->host; 335 } 336 } 337 } 338 339 static int kvm_probe_user_return_msr(u32 msr) 340 { 341 u64 val; 342 int ret; 343 344 preempt_disable(); 345 ret = rdmsrl_safe(msr, &val); 346 if (ret) 347 goto out; 348 ret = wrmsrl_safe(msr, val); 349 out: 350 preempt_enable(); 351 return ret; 352 } 353 354 int kvm_add_user_return_msr(u32 msr) 355 { 356 BUG_ON(kvm_nr_uret_msrs >= KVM_MAX_NR_USER_RETURN_MSRS); 357 358 if (kvm_probe_user_return_msr(msr)) 359 return -1; 360 361 kvm_uret_msrs_list[kvm_nr_uret_msrs] = msr; 362 return kvm_nr_uret_msrs++; 363 } 364 EXPORT_SYMBOL_GPL(kvm_add_user_return_msr); 365 366 int kvm_find_user_return_msr(u32 msr) 367 { 368 int i; 369 370 for (i = 0; i < kvm_nr_uret_msrs; ++i) { 371 if (kvm_uret_msrs_list[i] == msr) 372 return i; 373 } 374 return -1; 375 } 376 EXPORT_SYMBOL_GPL(kvm_find_user_return_msr); 377 378 static void kvm_user_return_msr_cpu_online(void) 379 { 380 unsigned int cpu = smp_processor_id(); 381 struct kvm_user_return_msrs *msrs = per_cpu_ptr(user_return_msrs, cpu); 382 u64 value; 383 int i; 384 385 for (i = 0; i < kvm_nr_uret_msrs; ++i) { 386 rdmsrl_safe(kvm_uret_msrs_list[i], &value); 387 msrs->values[i].host = value; 388 msrs->values[i].curr = value; 389 } 390 } 391 392 int kvm_set_user_return_msr(unsigned slot, u64 value, u64 mask) 393 { 394 unsigned int cpu = smp_processor_id(); 395 struct kvm_user_return_msrs *msrs = per_cpu_ptr(user_return_msrs, cpu); 396 int err; 397 398 value = (value & mask) | (msrs->values[slot].host & ~mask); 399 if (value == msrs->values[slot].curr) 400 return 0; 401 err = wrmsrl_safe(kvm_uret_msrs_list[slot], value); 402 if (err) 403 return 1; 404 405 msrs->values[slot].curr = value; 406 if (!msrs->registered) { 407 msrs->urn.on_user_return = kvm_on_user_return; 408 user_return_notifier_register(&msrs->urn); 409 msrs->registered = true; 410 } 411 return 0; 412 } 413 EXPORT_SYMBOL_GPL(kvm_set_user_return_msr); 414 415 static void drop_user_return_notifiers(void) 416 { 417 unsigned int cpu = smp_processor_id(); 418 struct kvm_user_return_msrs *msrs = per_cpu_ptr(user_return_msrs, cpu); 419 420 if (msrs->registered) 421 kvm_on_user_return(&msrs->urn); 422 } 423 424 u64 kvm_get_apic_base(struct kvm_vcpu *vcpu) 425 { 426 return vcpu->arch.apic_base; 427 } 428 EXPORT_SYMBOL_GPL(kvm_get_apic_base); 429 430 enum lapic_mode kvm_get_apic_mode(struct kvm_vcpu *vcpu) 431 { 432 return kvm_apic_mode(kvm_get_apic_base(vcpu)); 433 } 434 EXPORT_SYMBOL_GPL(kvm_get_apic_mode); 435 436 int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info) 437 { 438 enum lapic_mode old_mode = kvm_get_apic_mode(vcpu); 439 enum lapic_mode new_mode = kvm_apic_mode(msr_info->data); 440 u64 reserved_bits = kvm_vcpu_reserved_gpa_bits_raw(vcpu) | 0x2ff | 441 (guest_cpuid_has(vcpu, X86_FEATURE_X2APIC) ? 0 : X2APIC_ENABLE); 442 443 if ((msr_info->data & reserved_bits) != 0 || new_mode == LAPIC_MODE_INVALID) 444 return 1; 445 if (!msr_info->host_initiated) { 446 if (old_mode == LAPIC_MODE_X2APIC && new_mode == LAPIC_MODE_XAPIC) 447 return 1; 448 if (old_mode == LAPIC_MODE_DISABLED && new_mode == LAPIC_MODE_X2APIC) 449 return 1; 450 } 451 452 kvm_lapic_set_base(vcpu, msr_info->data); 453 kvm_recalculate_apic_map(vcpu->kvm); 454 return 0; 455 } 456 EXPORT_SYMBOL_GPL(kvm_set_apic_base); 457 458 asmlinkage __visible noinstr void kvm_spurious_fault(void) 459 { 460 /* Fault while not rebooting. We want the trace. */ 461 BUG_ON(!kvm_rebooting); 462 } 463 EXPORT_SYMBOL_GPL(kvm_spurious_fault); 464 465 #define EXCPT_BENIGN 0 466 #define EXCPT_CONTRIBUTORY 1 467 #define EXCPT_PF 2 468 469 static int exception_class(int vector) 470 { 471 switch (vector) { 472 case PF_VECTOR: 473 return EXCPT_PF; 474 case DE_VECTOR: 475 case TS_VECTOR: 476 case NP_VECTOR: 477 case SS_VECTOR: 478 case GP_VECTOR: 479 return EXCPT_CONTRIBUTORY; 480 default: 481 break; 482 } 483 return EXCPT_BENIGN; 484 } 485 486 #define EXCPT_FAULT 0 487 #define EXCPT_TRAP 1 488 #define EXCPT_ABORT 2 489 #define EXCPT_INTERRUPT 3 490 491 static int exception_type(int vector) 492 { 493 unsigned int mask; 494 495 if (WARN_ON(vector > 31 || vector == NMI_VECTOR)) 496 return EXCPT_INTERRUPT; 497 498 mask = 1 << vector; 499 500 /* #DB is trap, as instruction watchpoints are handled elsewhere */ 501 if (mask & ((1 << DB_VECTOR) | (1 << BP_VECTOR) | (1 << OF_VECTOR))) 502 return EXCPT_TRAP; 503 504 if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR))) 505 return EXCPT_ABORT; 506 507 /* Reserved exceptions will result in fault */ 508 return EXCPT_FAULT; 509 } 510 511 void kvm_deliver_exception_payload(struct kvm_vcpu *vcpu) 512 { 513 unsigned nr = vcpu->arch.exception.nr; 514 bool has_payload = vcpu->arch.exception.has_payload; 515 unsigned long payload = vcpu->arch.exception.payload; 516 517 if (!has_payload) 518 return; 519 520 switch (nr) { 521 case DB_VECTOR: 522 /* 523 * "Certain debug exceptions may clear bit 0-3. The 524 * remaining contents of the DR6 register are never 525 * cleared by the processor". 526 */ 527 vcpu->arch.dr6 &= ~DR_TRAP_BITS; 528 /* 529 * In order to reflect the #DB exception payload in guest 530 * dr6, three components need to be considered: active low 531 * bit, FIXED_1 bits and active high bits (e.g. DR6_BD, 532 * DR6_BS and DR6_BT) 533 * DR6_ACTIVE_LOW contains the FIXED_1 and active low bits. 534 * In the target guest dr6: 535 * FIXED_1 bits should always be set. 536 * Active low bits should be cleared if 1-setting in payload. 537 * Active high bits should be set if 1-setting in payload. 538 * 539 * Note, the payload is compatible with the pending debug 540 * exceptions/exit qualification under VMX, that active_low bits 541 * are active high in payload. 542 * So they need to be flipped for DR6. 543 */ 544 vcpu->arch.dr6 |= DR6_ACTIVE_LOW; 545 vcpu->arch.dr6 |= payload; 546 vcpu->arch.dr6 ^= payload & DR6_ACTIVE_LOW; 547 548 /* 549 * The #DB payload is defined as compatible with the 'pending 550 * debug exceptions' field under VMX, not DR6. While bit 12 is 551 * defined in the 'pending debug exceptions' field (enabled 552 * breakpoint), it is reserved and must be zero in DR6. 553 */ 554 vcpu->arch.dr6 &= ~BIT(12); 555 break; 556 case PF_VECTOR: 557 vcpu->arch.cr2 = payload; 558 break; 559 } 560 561 vcpu->arch.exception.has_payload = false; 562 vcpu->arch.exception.payload = 0; 563 } 564 EXPORT_SYMBOL_GPL(kvm_deliver_exception_payload); 565 566 static void kvm_multiple_exception(struct kvm_vcpu *vcpu, 567 unsigned nr, bool has_error, u32 error_code, 568 bool has_payload, unsigned long payload, bool reinject) 569 { 570 u32 prev_nr; 571 int class1, class2; 572 573 kvm_make_request(KVM_REQ_EVENT, vcpu); 574 575 if (!vcpu->arch.exception.pending && !vcpu->arch.exception.injected) { 576 queue: 577 if (reinject) { 578 /* 579 * On vmentry, vcpu->arch.exception.pending is only 580 * true if an event injection was blocked by 581 * nested_run_pending. In that case, however, 582 * vcpu_enter_guest requests an immediate exit, 583 * and the guest shouldn't proceed far enough to 584 * need reinjection. 585 */ 586 WARN_ON_ONCE(vcpu->arch.exception.pending); 587 vcpu->arch.exception.injected = true; 588 if (WARN_ON_ONCE(has_payload)) { 589 /* 590 * A reinjected event has already 591 * delivered its payload. 592 */ 593 has_payload = false; 594 payload = 0; 595 } 596 } else { 597 vcpu->arch.exception.pending = true; 598 vcpu->arch.exception.injected = false; 599 } 600 vcpu->arch.exception.has_error_code = has_error; 601 vcpu->arch.exception.nr = nr; 602 vcpu->arch.exception.error_code = error_code; 603 vcpu->arch.exception.has_payload = has_payload; 604 vcpu->arch.exception.payload = payload; 605 if (!is_guest_mode(vcpu)) 606 kvm_deliver_exception_payload(vcpu); 607 return; 608 } 609 610 /* to check exception */ 611 prev_nr = vcpu->arch.exception.nr; 612 if (prev_nr == DF_VECTOR) { 613 /* triple fault -> shutdown */ 614 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); 615 return; 616 } 617 class1 = exception_class(prev_nr); 618 class2 = exception_class(nr); 619 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY) 620 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) { 621 /* 622 * Generate double fault per SDM Table 5-5. Set 623 * exception.pending = true so that the double fault 624 * can trigger a nested vmexit. 625 */ 626 vcpu->arch.exception.pending = true; 627 vcpu->arch.exception.injected = false; 628 vcpu->arch.exception.has_error_code = true; 629 vcpu->arch.exception.nr = DF_VECTOR; 630 vcpu->arch.exception.error_code = 0; 631 vcpu->arch.exception.has_payload = false; 632 vcpu->arch.exception.payload = 0; 633 } else 634 /* replace previous exception with a new one in a hope 635 that instruction re-execution will regenerate lost 636 exception */ 637 goto queue; 638 } 639 640 void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr) 641 { 642 kvm_multiple_exception(vcpu, nr, false, 0, false, 0, false); 643 } 644 EXPORT_SYMBOL_GPL(kvm_queue_exception); 645 646 void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr) 647 { 648 kvm_multiple_exception(vcpu, nr, false, 0, false, 0, true); 649 } 650 EXPORT_SYMBOL_GPL(kvm_requeue_exception); 651 652 void kvm_queue_exception_p(struct kvm_vcpu *vcpu, unsigned nr, 653 unsigned long payload) 654 { 655 kvm_multiple_exception(vcpu, nr, false, 0, true, payload, false); 656 } 657 EXPORT_SYMBOL_GPL(kvm_queue_exception_p); 658 659 static void kvm_queue_exception_e_p(struct kvm_vcpu *vcpu, unsigned nr, 660 u32 error_code, unsigned long payload) 661 { 662 kvm_multiple_exception(vcpu, nr, true, error_code, 663 true, payload, false); 664 } 665 666 int kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err) 667 { 668 if (err) 669 kvm_inject_gp(vcpu, 0); 670 else 671 return kvm_skip_emulated_instruction(vcpu); 672 673 return 1; 674 } 675 EXPORT_SYMBOL_GPL(kvm_complete_insn_gp); 676 677 void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault) 678 { 679 ++vcpu->stat.pf_guest; 680 vcpu->arch.exception.nested_apf = 681 is_guest_mode(vcpu) && fault->async_page_fault; 682 if (vcpu->arch.exception.nested_apf) { 683 vcpu->arch.apf.nested_apf_token = fault->address; 684 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code); 685 } else { 686 kvm_queue_exception_e_p(vcpu, PF_VECTOR, fault->error_code, 687 fault->address); 688 } 689 } 690 EXPORT_SYMBOL_GPL(kvm_inject_page_fault); 691 692 bool kvm_inject_emulated_page_fault(struct kvm_vcpu *vcpu, 693 struct x86_exception *fault) 694 { 695 struct kvm_mmu *fault_mmu; 696 WARN_ON_ONCE(fault->vector != PF_VECTOR); 697 698 fault_mmu = fault->nested_page_fault ? vcpu->arch.mmu : 699 vcpu->arch.walk_mmu; 700 701 /* 702 * Invalidate the TLB entry for the faulting address, if it exists, 703 * else the access will fault indefinitely (and to emulate hardware). 704 */ 705 if ((fault->error_code & PFERR_PRESENT_MASK) && 706 !(fault->error_code & PFERR_RSVD_MASK)) 707 kvm_mmu_invalidate_gva(vcpu, fault_mmu, fault->address, 708 fault_mmu->root_hpa); 709 710 fault_mmu->inject_page_fault(vcpu, fault); 711 return fault->nested_page_fault; 712 } 713 EXPORT_SYMBOL_GPL(kvm_inject_emulated_page_fault); 714 715 void kvm_inject_nmi(struct kvm_vcpu *vcpu) 716 { 717 atomic_inc(&vcpu->arch.nmi_queued); 718 kvm_make_request(KVM_REQ_NMI, vcpu); 719 } 720 EXPORT_SYMBOL_GPL(kvm_inject_nmi); 721 722 void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code) 723 { 724 kvm_multiple_exception(vcpu, nr, true, error_code, false, 0, false); 725 } 726 EXPORT_SYMBOL_GPL(kvm_queue_exception_e); 727 728 void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code) 729 { 730 kvm_multiple_exception(vcpu, nr, true, error_code, false, 0, true); 731 } 732 EXPORT_SYMBOL_GPL(kvm_requeue_exception_e); 733 734 /* 735 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue 736 * a #GP and return false. 737 */ 738 bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl) 739 { 740 if (static_call(kvm_x86_get_cpl)(vcpu) <= required_cpl) 741 return true; 742 kvm_queue_exception_e(vcpu, GP_VECTOR, 0); 743 return false; 744 } 745 EXPORT_SYMBOL_GPL(kvm_require_cpl); 746 747 bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr) 748 { 749 if ((dr != 4 && dr != 5) || !kvm_read_cr4_bits(vcpu, X86_CR4_DE)) 750 return true; 751 752 kvm_queue_exception(vcpu, UD_VECTOR); 753 return false; 754 } 755 EXPORT_SYMBOL_GPL(kvm_require_dr); 756 757 /* 758 * This function will be used to read from the physical memory of the currently 759 * running guest. The difference to kvm_vcpu_read_guest_page is that this function 760 * can read from guest physical or from the guest's guest physical memory. 761 */ 762 int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, 763 gfn_t ngfn, void *data, int offset, int len, 764 u32 access) 765 { 766 struct x86_exception exception; 767 gfn_t real_gfn; 768 gpa_t ngpa; 769 770 ngpa = gfn_to_gpa(ngfn); 771 real_gfn = mmu->translate_gpa(vcpu, ngpa, access, &exception); 772 if (real_gfn == UNMAPPED_GVA) 773 return -EFAULT; 774 775 real_gfn = gpa_to_gfn(real_gfn); 776 777 return kvm_vcpu_read_guest_page(vcpu, real_gfn, data, offset, len); 778 } 779 EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu); 780 781 static int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn, 782 void *data, int offset, int len, u32 access) 783 { 784 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn, 785 data, offset, len, access); 786 } 787 788 static inline u64 pdptr_rsvd_bits(struct kvm_vcpu *vcpu) 789 { 790 return vcpu->arch.reserved_gpa_bits | rsvd_bits(5, 8) | rsvd_bits(1, 2); 791 } 792 793 /* 794 * Load the pae pdptrs. Return 1 if they are all valid, 0 otherwise. 795 */ 796 int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3) 797 { 798 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT; 799 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2; 800 int i; 801 int ret; 802 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)]; 803 804 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte, 805 offset * sizeof(u64), sizeof(pdpte), 806 PFERR_USER_MASK|PFERR_WRITE_MASK); 807 if (ret < 0) { 808 ret = 0; 809 goto out; 810 } 811 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) { 812 if ((pdpte[i] & PT_PRESENT_MASK) && 813 (pdpte[i] & pdptr_rsvd_bits(vcpu))) { 814 ret = 0; 815 goto out; 816 } 817 } 818 ret = 1; 819 820 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs)); 821 kvm_register_mark_dirty(vcpu, VCPU_EXREG_PDPTR); 822 823 out: 824 825 return ret; 826 } 827 EXPORT_SYMBOL_GPL(load_pdptrs); 828 829 bool pdptrs_changed(struct kvm_vcpu *vcpu) 830 { 831 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)]; 832 int offset; 833 gfn_t gfn; 834 int r; 835 836 if (!is_pae_paging(vcpu)) 837 return false; 838 839 if (!kvm_register_is_available(vcpu, VCPU_EXREG_PDPTR)) 840 return true; 841 842 gfn = (kvm_read_cr3(vcpu) & 0xffffffe0ul) >> PAGE_SHIFT; 843 offset = (kvm_read_cr3(vcpu) & 0xffffffe0ul) & (PAGE_SIZE - 1); 844 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte), 845 PFERR_USER_MASK | PFERR_WRITE_MASK); 846 if (r < 0) 847 return true; 848 849 return memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0; 850 } 851 EXPORT_SYMBOL_GPL(pdptrs_changed); 852 853 void kvm_post_set_cr0(struct kvm_vcpu *vcpu, unsigned long old_cr0, unsigned long cr0) 854 { 855 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP; 856 857 if ((cr0 ^ old_cr0) & X86_CR0_PG) { 858 kvm_clear_async_pf_completion_queue(vcpu); 859 kvm_async_pf_hash_reset(vcpu); 860 } 861 862 if ((cr0 ^ old_cr0) & update_bits) 863 kvm_mmu_reset_context(vcpu); 864 865 if (((cr0 ^ old_cr0) & X86_CR0_CD) && 866 kvm_arch_has_noncoherent_dma(vcpu->kvm) && 867 !kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED)) 868 kvm_zap_gfn_range(vcpu->kvm, 0, ~0ULL); 869 } 870 EXPORT_SYMBOL_GPL(kvm_post_set_cr0); 871 872 int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0) 873 { 874 unsigned long old_cr0 = kvm_read_cr0(vcpu); 875 unsigned long pdptr_bits = X86_CR0_CD | X86_CR0_NW | X86_CR0_PG; 876 877 cr0 |= X86_CR0_ET; 878 879 #ifdef CONFIG_X86_64 880 if (cr0 & 0xffffffff00000000UL) 881 return 1; 882 #endif 883 884 cr0 &= ~CR0_RESERVED_BITS; 885 886 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD)) 887 return 1; 888 889 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE)) 890 return 1; 891 892 #ifdef CONFIG_X86_64 893 if ((vcpu->arch.efer & EFER_LME) && !is_paging(vcpu) && 894 (cr0 & X86_CR0_PG)) { 895 int cs_db, cs_l; 896 897 if (!is_pae(vcpu)) 898 return 1; 899 static_call(kvm_x86_get_cs_db_l_bits)(vcpu, &cs_db, &cs_l); 900 if (cs_l) 901 return 1; 902 } 903 #endif 904 if (!(vcpu->arch.efer & EFER_LME) && (cr0 & X86_CR0_PG) && 905 is_pae(vcpu) && ((cr0 ^ old_cr0) & pdptr_bits) && 906 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu))) 907 return 1; 908 909 if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE)) 910 return 1; 911 912 static_call(kvm_x86_set_cr0)(vcpu, cr0); 913 914 kvm_post_set_cr0(vcpu, old_cr0, cr0); 915 916 return 0; 917 } 918 EXPORT_SYMBOL_GPL(kvm_set_cr0); 919 920 void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw) 921 { 922 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f)); 923 } 924 EXPORT_SYMBOL_GPL(kvm_lmsw); 925 926 void kvm_load_guest_xsave_state(struct kvm_vcpu *vcpu) 927 { 928 if (vcpu->arch.guest_state_protected) 929 return; 930 931 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE)) { 932 933 if (vcpu->arch.xcr0 != host_xcr0) 934 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0); 935 936 if (vcpu->arch.xsaves_enabled && 937 vcpu->arch.ia32_xss != host_xss) 938 wrmsrl(MSR_IA32_XSS, vcpu->arch.ia32_xss); 939 } 940 941 if (static_cpu_has(X86_FEATURE_PKU) && 942 (kvm_read_cr4_bits(vcpu, X86_CR4_PKE) || 943 (vcpu->arch.xcr0 & XFEATURE_MASK_PKRU)) && 944 vcpu->arch.pkru != vcpu->arch.host_pkru) 945 __write_pkru(vcpu->arch.pkru); 946 } 947 EXPORT_SYMBOL_GPL(kvm_load_guest_xsave_state); 948 949 void kvm_load_host_xsave_state(struct kvm_vcpu *vcpu) 950 { 951 if (vcpu->arch.guest_state_protected) 952 return; 953 954 if (static_cpu_has(X86_FEATURE_PKU) && 955 (kvm_read_cr4_bits(vcpu, X86_CR4_PKE) || 956 (vcpu->arch.xcr0 & XFEATURE_MASK_PKRU))) { 957 vcpu->arch.pkru = rdpkru(); 958 if (vcpu->arch.pkru != vcpu->arch.host_pkru) 959 __write_pkru(vcpu->arch.host_pkru); 960 } 961 962 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE)) { 963 964 if (vcpu->arch.xcr0 != host_xcr0) 965 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0); 966 967 if (vcpu->arch.xsaves_enabled && 968 vcpu->arch.ia32_xss != host_xss) 969 wrmsrl(MSR_IA32_XSS, host_xss); 970 } 971 972 } 973 EXPORT_SYMBOL_GPL(kvm_load_host_xsave_state); 974 975 static int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr) 976 { 977 u64 xcr0 = xcr; 978 u64 old_xcr0 = vcpu->arch.xcr0; 979 u64 valid_bits; 980 981 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */ 982 if (index != XCR_XFEATURE_ENABLED_MASK) 983 return 1; 984 if (!(xcr0 & XFEATURE_MASK_FP)) 985 return 1; 986 if ((xcr0 & XFEATURE_MASK_YMM) && !(xcr0 & XFEATURE_MASK_SSE)) 987 return 1; 988 989 /* 990 * Do not allow the guest to set bits that we do not support 991 * saving. However, xcr0 bit 0 is always set, even if the 992 * emulated CPU does not support XSAVE (see fx_init). 993 */ 994 valid_bits = vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FP; 995 if (xcr0 & ~valid_bits) 996 return 1; 997 998 if ((!(xcr0 & XFEATURE_MASK_BNDREGS)) != 999 (!(xcr0 & XFEATURE_MASK_BNDCSR))) 1000 return 1; 1001 1002 if (xcr0 & XFEATURE_MASK_AVX512) { 1003 if (!(xcr0 & XFEATURE_MASK_YMM)) 1004 return 1; 1005 if ((xcr0 & XFEATURE_MASK_AVX512) != XFEATURE_MASK_AVX512) 1006 return 1; 1007 } 1008 vcpu->arch.xcr0 = xcr0; 1009 1010 if ((xcr0 ^ old_xcr0) & XFEATURE_MASK_EXTEND) 1011 kvm_update_cpuid_runtime(vcpu); 1012 return 0; 1013 } 1014 1015 int kvm_emulate_xsetbv(struct kvm_vcpu *vcpu) 1016 { 1017 if (static_call(kvm_x86_get_cpl)(vcpu) != 0 || 1018 __kvm_set_xcr(vcpu, kvm_rcx_read(vcpu), kvm_read_edx_eax(vcpu))) { 1019 kvm_inject_gp(vcpu, 0); 1020 return 1; 1021 } 1022 1023 return kvm_skip_emulated_instruction(vcpu); 1024 } 1025 EXPORT_SYMBOL_GPL(kvm_emulate_xsetbv); 1026 1027 bool kvm_is_valid_cr4(struct kvm_vcpu *vcpu, unsigned long cr4) 1028 { 1029 if (cr4 & cr4_reserved_bits) 1030 return false; 1031 1032 if (cr4 & vcpu->arch.cr4_guest_rsvd_bits) 1033 return false; 1034 1035 return static_call(kvm_x86_is_valid_cr4)(vcpu, cr4); 1036 } 1037 EXPORT_SYMBOL_GPL(kvm_is_valid_cr4); 1038 1039 void kvm_post_set_cr4(struct kvm_vcpu *vcpu, unsigned long old_cr4, unsigned long cr4) 1040 { 1041 unsigned long mmu_role_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE | 1042 X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE; 1043 1044 if (((cr4 ^ old_cr4) & mmu_role_bits) || 1045 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE))) 1046 kvm_mmu_reset_context(vcpu); 1047 } 1048 EXPORT_SYMBOL_GPL(kvm_post_set_cr4); 1049 1050 int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4) 1051 { 1052 unsigned long old_cr4 = kvm_read_cr4(vcpu); 1053 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE | 1054 X86_CR4_SMEP; 1055 1056 if (!kvm_is_valid_cr4(vcpu, cr4)) 1057 return 1; 1058 1059 if (is_long_mode(vcpu)) { 1060 if (!(cr4 & X86_CR4_PAE)) 1061 return 1; 1062 if ((cr4 ^ old_cr4) & X86_CR4_LA57) 1063 return 1; 1064 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE) 1065 && ((cr4 ^ old_cr4) & pdptr_bits) 1066 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu, 1067 kvm_read_cr3(vcpu))) 1068 return 1; 1069 1070 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) { 1071 if (!guest_cpuid_has(vcpu, X86_FEATURE_PCID)) 1072 return 1; 1073 1074 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */ 1075 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu)) 1076 return 1; 1077 } 1078 1079 static_call(kvm_x86_set_cr4)(vcpu, cr4); 1080 1081 kvm_post_set_cr4(vcpu, old_cr4, cr4); 1082 1083 return 0; 1084 } 1085 EXPORT_SYMBOL_GPL(kvm_set_cr4); 1086 1087 int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3) 1088 { 1089 bool skip_tlb_flush = false; 1090 #ifdef CONFIG_X86_64 1091 bool pcid_enabled = kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE); 1092 1093 if (pcid_enabled) { 1094 skip_tlb_flush = cr3 & X86_CR3_PCID_NOFLUSH; 1095 cr3 &= ~X86_CR3_PCID_NOFLUSH; 1096 } 1097 #endif 1098 1099 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) { 1100 if (!skip_tlb_flush) { 1101 kvm_mmu_sync_roots(vcpu); 1102 kvm_make_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu); 1103 } 1104 return 0; 1105 } 1106 1107 /* 1108 * Do not condition the GPA check on long mode, this helper is used to 1109 * stuff CR3, e.g. for RSM emulation, and there is no guarantee that 1110 * the current vCPU mode is accurate. 1111 */ 1112 if (kvm_vcpu_is_illegal_gpa(vcpu, cr3)) 1113 return 1; 1114 1115 if (is_pae_paging(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3)) 1116 return 1; 1117 1118 kvm_mmu_new_pgd(vcpu, cr3, skip_tlb_flush, skip_tlb_flush); 1119 vcpu->arch.cr3 = cr3; 1120 kvm_register_mark_available(vcpu, VCPU_EXREG_CR3); 1121 1122 return 0; 1123 } 1124 EXPORT_SYMBOL_GPL(kvm_set_cr3); 1125 1126 int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8) 1127 { 1128 if (cr8 & CR8_RESERVED_BITS) 1129 return 1; 1130 if (lapic_in_kernel(vcpu)) 1131 kvm_lapic_set_tpr(vcpu, cr8); 1132 else 1133 vcpu->arch.cr8 = cr8; 1134 return 0; 1135 } 1136 EXPORT_SYMBOL_GPL(kvm_set_cr8); 1137 1138 unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu) 1139 { 1140 if (lapic_in_kernel(vcpu)) 1141 return kvm_lapic_get_cr8(vcpu); 1142 else 1143 return vcpu->arch.cr8; 1144 } 1145 EXPORT_SYMBOL_GPL(kvm_get_cr8); 1146 1147 static void kvm_update_dr0123(struct kvm_vcpu *vcpu) 1148 { 1149 int i; 1150 1151 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) { 1152 for (i = 0; i < KVM_NR_DB_REGS; i++) 1153 vcpu->arch.eff_db[i] = vcpu->arch.db[i]; 1154 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_RELOAD; 1155 } 1156 } 1157 1158 void kvm_update_dr7(struct kvm_vcpu *vcpu) 1159 { 1160 unsigned long dr7; 1161 1162 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) 1163 dr7 = vcpu->arch.guest_debug_dr7; 1164 else 1165 dr7 = vcpu->arch.dr7; 1166 static_call(kvm_x86_set_dr7)(vcpu, dr7); 1167 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED; 1168 if (dr7 & DR7_BP_EN_MASK) 1169 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED; 1170 } 1171 EXPORT_SYMBOL_GPL(kvm_update_dr7); 1172 1173 static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu) 1174 { 1175 u64 fixed = DR6_FIXED_1; 1176 1177 if (!guest_cpuid_has(vcpu, X86_FEATURE_RTM)) 1178 fixed |= DR6_RTM; 1179 1180 if (!guest_cpuid_has(vcpu, X86_FEATURE_BUS_LOCK_DETECT)) 1181 fixed |= DR6_BUS_LOCK; 1182 return fixed; 1183 } 1184 1185 int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val) 1186 { 1187 size_t size = ARRAY_SIZE(vcpu->arch.db); 1188 1189 switch (dr) { 1190 case 0 ... 3: 1191 vcpu->arch.db[array_index_nospec(dr, size)] = val; 1192 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) 1193 vcpu->arch.eff_db[dr] = val; 1194 break; 1195 case 4: 1196 case 6: 1197 if (!kvm_dr6_valid(val)) 1198 return 1; /* #GP */ 1199 vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu); 1200 break; 1201 case 5: 1202 default: /* 7 */ 1203 if (!kvm_dr7_valid(val)) 1204 return 1; /* #GP */ 1205 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1; 1206 kvm_update_dr7(vcpu); 1207 break; 1208 } 1209 1210 return 0; 1211 } 1212 EXPORT_SYMBOL_GPL(kvm_set_dr); 1213 1214 void kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val) 1215 { 1216 size_t size = ARRAY_SIZE(vcpu->arch.db); 1217 1218 switch (dr) { 1219 case 0 ... 3: 1220 *val = vcpu->arch.db[array_index_nospec(dr, size)]; 1221 break; 1222 case 4: 1223 case 6: 1224 *val = vcpu->arch.dr6; 1225 break; 1226 case 5: 1227 default: /* 7 */ 1228 *val = vcpu->arch.dr7; 1229 break; 1230 } 1231 } 1232 EXPORT_SYMBOL_GPL(kvm_get_dr); 1233 1234 int kvm_emulate_rdpmc(struct kvm_vcpu *vcpu) 1235 { 1236 u32 ecx = kvm_rcx_read(vcpu); 1237 u64 data; 1238 1239 if (kvm_pmu_rdpmc(vcpu, ecx, &data)) { 1240 kvm_inject_gp(vcpu, 0); 1241 return 1; 1242 } 1243 1244 kvm_rax_write(vcpu, (u32)data); 1245 kvm_rdx_write(vcpu, data >> 32); 1246 return kvm_skip_emulated_instruction(vcpu); 1247 } 1248 EXPORT_SYMBOL_GPL(kvm_emulate_rdpmc); 1249 1250 /* 1251 * List of msr numbers which we expose to userspace through KVM_GET_MSRS 1252 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST. 1253 * 1254 * The three MSR lists(msrs_to_save, emulated_msrs, msr_based_features) 1255 * extract the supported MSRs from the related const lists. 1256 * msrs_to_save is selected from the msrs_to_save_all to reflect the 1257 * capabilities of the host cpu. This capabilities test skips MSRs that are 1258 * kvm-specific. Those are put in emulated_msrs_all; filtering of emulated_msrs 1259 * may depend on host virtualization features rather than host cpu features. 1260 */ 1261 1262 static const u32 msrs_to_save_all[] = { 1263 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP, 1264 MSR_STAR, 1265 #ifdef CONFIG_X86_64 1266 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR, 1267 #endif 1268 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA, 1269 MSR_IA32_FEAT_CTL, MSR_IA32_BNDCFGS, MSR_TSC_AUX, 1270 MSR_IA32_SPEC_CTRL, 1271 MSR_IA32_RTIT_CTL, MSR_IA32_RTIT_STATUS, MSR_IA32_RTIT_CR3_MATCH, 1272 MSR_IA32_RTIT_OUTPUT_BASE, MSR_IA32_RTIT_OUTPUT_MASK, 1273 MSR_IA32_RTIT_ADDR0_A, MSR_IA32_RTIT_ADDR0_B, 1274 MSR_IA32_RTIT_ADDR1_A, MSR_IA32_RTIT_ADDR1_B, 1275 MSR_IA32_RTIT_ADDR2_A, MSR_IA32_RTIT_ADDR2_B, 1276 MSR_IA32_RTIT_ADDR3_A, MSR_IA32_RTIT_ADDR3_B, 1277 MSR_IA32_UMWAIT_CONTROL, 1278 1279 MSR_ARCH_PERFMON_FIXED_CTR0, MSR_ARCH_PERFMON_FIXED_CTR1, 1280 MSR_ARCH_PERFMON_FIXED_CTR0 + 2, MSR_ARCH_PERFMON_FIXED_CTR0 + 3, 1281 MSR_CORE_PERF_FIXED_CTR_CTRL, MSR_CORE_PERF_GLOBAL_STATUS, 1282 MSR_CORE_PERF_GLOBAL_CTRL, MSR_CORE_PERF_GLOBAL_OVF_CTRL, 1283 MSR_ARCH_PERFMON_PERFCTR0, MSR_ARCH_PERFMON_PERFCTR1, 1284 MSR_ARCH_PERFMON_PERFCTR0 + 2, MSR_ARCH_PERFMON_PERFCTR0 + 3, 1285 MSR_ARCH_PERFMON_PERFCTR0 + 4, MSR_ARCH_PERFMON_PERFCTR0 + 5, 1286 MSR_ARCH_PERFMON_PERFCTR0 + 6, MSR_ARCH_PERFMON_PERFCTR0 + 7, 1287 MSR_ARCH_PERFMON_PERFCTR0 + 8, MSR_ARCH_PERFMON_PERFCTR0 + 9, 1288 MSR_ARCH_PERFMON_PERFCTR0 + 10, MSR_ARCH_PERFMON_PERFCTR0 + 11, 1289 MSR_ARCH_PERFMON_PERFCTR0 + 12, MSR_ARCH_PERFMON_PERFCTR0 + 13, 1290 MSR_ARCH_PERFMON_PERFCTR0 + 14, MSR_ARCH_PERFMON_PERFCTR0 + 15, 1291 MSR_ARCH_PERFMON_PERFCTR0 + 16, MSR_ARCH_PERFMON_PERFCTR0 + 17, 1292 MSR_ARCH_PERFMON_EVENTSEL0, MSR_ARCH_PERFMON_EVENTSEL1, 1293 MSR_ARCH_PERFMON_EVENTSEL0 + 2, MSR_ARCH_PERFMON_EVENTSEL0 + 3, 1294 MSR_ARCH_PERFMON_EVENTSEL0 + 4, MSR_ARCH_PERFMON_EVENTSEL0 + 5, 1295 MSR_ARCH_PERFMON_EVENTSEL0 + 6, MSR_ARCH_PERFMON_EVENTSEL0 + 7, 1296 MSR_ARCH_PERFMON_EVENTSEL0 + 8, MSR_ARCH_PERFMON_EVENTSEL0 + 9, 1297 MSR_ARCH_PERFMON_EVENTSEL0 + 10, MSR_ARCH_PERFMON_EVENTSEL0 + 11, 1298 MSR_ARCH_PERFMON_EVENTSEL0 + 12, MSR_ARCH_PERFMON_EVENTSEL0 + 13, 1299 MSR_ARCH_PERFMON_EVENTSEL0 + 14, MSR_ARCH_PERFMON_EVENTSEL0 + 15, 1300 MSR_ARCH_PERFMON_EVENTSEL0 + 16, MSR_ARCH_PERFMON_EVENTSEL0 + 17, 1301 }; 1302 1303 static u32 msrs_to_save[ARRAY_SIZE(msrs_to_save_all)]; 1304 static unsigned num_msrs_to_save; 1305 1306 static const u32 emulated_msrs_all[] = { 1307 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK, 1308 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW, 1309 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL, 1310 HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC, 1311 HV_X64_MSR_TSC_FREQUENCY, HV_X64_MSR_APIC_FREQUENCY, 1312 HV_X64_MSR_CRASH_P0, HV_X64_MSR_CRASH_P1, HV_X64_MSR_CRASH_P2, 1313 HV_X64_MSR_CRASH_P3, HV_X64_MSR_CRASH_P4, HV_X64_MSR_CRASH_CTL, 1314 HV_X64_MSR_RESET, 1315 HV_X64_MSR_VP_INDEX, 1316 HV_X64_MSR_VP_RUNTIME, 1317 HV_X64_MSR_SCONTROL, 1318 HV_X64_MSR_STIMER0_CONFIG, 1319 HV_X64_MSR_VP_ASSIST_PAGE, 1320 HV_X64_MSR_REENLIGHTENMENT_CONTROL, HV_X64_MSR_TSC_EMULATION_CONTROL, 1321 HV_X64_MSR_TSC_EMULATION_STATUS, 1322 HV_X64_MSR_SYNDBG_OPTIONS, 1323 HV_X64_MSR_SYNDBG_CONTROL, HV_X64_MSR_SYNDBG_STATUS, 1324 HV_X64_MSR_SYNDBG_SEND_BUFFER, HV_X64_MSR_SYNDBG_RECV_BUFFER, 1325 HV_X64_MSR_SYNDBG_PENDING_BUFFER, 1326 1327 MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME, 1328 MSR_KVM_PV_EOI_EN, MSR_KVM_ASYNC_PF_INT, MSR_KVM_ASYNC_PF_ACK, 1329 1330 MSR_IA32_TSC_ADJUST, 1331 MSR_IA32_TSC_DEADLINE, 1332 MSR_IA32_ARCH_CAPABILITIES, 1333 MSR_IA32_PERF_CAPABILITIES, 1334 MSR_IA32_MISC_ENABLE, 1335 MSR_IA32_MCG_STATUS, 1336 MSR_IA32_MCG_CTL, 1337 MSR_IA32_MCG_EXT_CTL, 1338 MSR_IA32_SMBASE, 1339 MSR_SMI_COUNT, 1340 MSR_PLATFORM_INFO, 1341 MSR_MISC_FEATURES_ENABLES, 1342 MSR_AMD64_VIRT_SPEC_CTRL, 1343 MSR_IA32_POWER_CTL, 1344 MSR_IA32_UCODE_REV, 1345 1346 /* 1347 * The following list leaves out MSRs whose values are determined 1348 * by arch/x86/kvm/vmx/nested.c based on CPUID or other MSRs. 1349 * We always support the "true" VMX control MSRs, even if the host 1350 * processor does not, so I am putting these registers here rather 1351 * than in msrs_to_save_all. 1352 */ 1353 MSR_IA32_VMX_BASIC, 1354 MSR_IA32_VMX_TRUE_PINBASED_CTLS, 1355 MSR_IA32_VMX_TRUE_PROCBASED_CTLS, 1356 MSR_IA32_VMX_TRUE_EXIT_CTLS, 1357 MSR_IA32_VMX_TRUE_ENTRY_CTLS, 1358 MSR_IA32_VMX_MISC, 1359 MSR_IA32_VMX_CR0_FIXED0, 1360 MSR_IA32_VMX_CR4_FIXED0, 1361 MSR_IA32_VMX_VMCS_ENUM, 1362 MSR_IA32_VMX_PROCBASED_CTLS2, 1363 MSR_IA32_VMX_EPT_VPID_CAP, 1364 MSR_IA32_VMX_VMFUNC, 1365 1366 MSR_K7_HWCR, 1367 MSR_KVM_POLL_CONTROL, 1368 }; 1369 1370 static u32 emulated_msrs[ARRAY_SIZE(emulated_msrs_all)]; 1371 static unsigned num_emulated_msrs; 1372 1373 /* 1374 * List of msr numbers which are used to expose MSR-based features that 1375 * can be used by a hypervisor to validate requested CPU features. 1376 */ 1377 static const u32 msr_based_features_all[] = { 1378 MSR_IA32_VMX_BASIC, 1379 MSR_IA32_VMX_TRUE_PINBASED_CTLS, 1380 MSR_IA32_VMX_PINBASED_CTLS, 1381 MSR_IA32_VMX_TRUE_PROCBASED_CTLS, 1382 MSR_IA32_VMX_PROCBASED_CTLS, 1383 MSR_IA32_VMX_TRUE_EXIT_CTLS, 1384 MSR_IA32_VMX_EXIT_CTLS, 1385 MSR_IA32_VMX_TRUE_ENTRY_CTLS, 1386 MSR_IA32_VMX_ENTRY_CTLS, 1387 MSR_IA32_VMX_MISC, 1388 MSR_IA32_VMX_CR0_FIXED0, 1389 MSR_IA32_VMX_CR0_FIXED1, 1390 MSR_IA32_VMX_CR4_FIXED0, 1391 MSR_IA32_VMX_CR4_FIXED1, 1392 MSR_IA32_VMX_VMCS_ENUM, 1393 MSR_IA32_VMX_PROCBASED_CTLS2, 1394 MSR_IA32_VMX_EPT_VPID_CAP, 1395 MSR_IA32_VMX_VMFUNC, 1396 1397 MSR_F10H_DECFG, 1398 MSR_IA32_UCODE_REV, 1399 MSR_IA32_ARCH_CAPABILITIES, 1400 MSR_IA32_PERF_CAPABILITIES, 1401 }; 1402 1403 static u32 msr_based_features[ARRAY_SIZE(msr_based_features_all)]; 1404 static unsigned int num_msr_based_features; 1405 1406 static u64 kvm_get_arch_capabilities(void) 1407 { 1408 u64 data = 0; 1409 1410 if (boot_cpu_has(X86_FEATURE_ARCH_CAPABILITIES)) 1411 rdmsrl(MSR_IA32_ARCH_CAPABILITIES, data); 1412 1413 /* 1414 * If nx_huge_pages is enabled, KVM's shadow paging will ensure that 1415 * the nested hypervisor runs with NX huge pages. If it is not, 1416 * L1 is anyway vulnerable to ITLB_MULTIHIT exploits from other 1417 * L1 guests, so it need not worry about its own (L2) guests. 1418 */ 1419 data |= ARCH_CAP_PSCHANGE_MC_NO; 1420 1421 /* 1422 * If we're doing cache flushes (either "always" or "cond") 1423 * we will do one whenever the guest does a vmlaunch/vmresume. 1424 * If an outer hypervisor is doing the cache flush for us 1425 * (VMENTER_L1D_FLUSH_NESTED_VM), we can safely pass that 1426 * capability to the guest too, and if EPT is disabled we're not 1427 * vulnerable. Overall, only VMENTER_L1D_FLUSH_NEVER will 1428 * require a nested hypervisor to do a flush of its own. 1429 */ 1430 if (l1tf_vmx_mitigation != VMENTER_L1D_FLUSH_NEVER) 1431 data |= ARCH_CAP_SKIP_VMENTRY_L1DFLUSH; 1432 1433 if (!boot_cpu_has_bug(X86_BUG_CPU_MELTDOWN)) 1434 data |= ARCH_CAP_RDCL_NO; 1435 if (!boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS)) 1436 data |= ARCH_CAP_SSB_NO; 1437 if (!boot_cpu_has_bug(X86_BUG_MDS)) 1438 data |= ARCH_CAP_MDS_NO; 1439 1440 if (!boot_cpu_has(X86_FEATURE_RTM)) { 1441 /* 1442 * If RTM=0 because the kernel has disabled TSX, the host might 1443 * have TAA_NO or TSX_CTRL. Clear TAA_NO (the guest sees RTM=0 1444 * and therefore knows that there cannot be TAA) but keep 1445 * TSX_CTRL: some buggy userspaces leave it set on tsx=on hosts, 1446 * and we want to allow migrating those guests to tsx=off hosts. 1447 */ 1448 data &= ~ARCH_CAP_TAA_NO; 1449 } else if (!boot_cpu_has_bug(X86_BUG_TAA)) { 1450 data |= ARCH_CAP_TAA_NO; 1451 } else { 1452 /* 1453 * Nothing to do here; we emulate TSX_CTRL if present on the 1454 * host so the guest can choose between disabling TSX or 1455 * using VERW to clear CPU buffers. 1456 */ 1457 } 1458 1459 return data; 1460 } 1461 1462 static int kvm_get_msr_feature(struct kvm_msr_entry *msr) 1463 { 1464 switch (msr->index) { 1465 case MSR_IA32_ARCH_CAPABILITIES: 1466 msr->data = kvm_get_arch_capabilities(); 1467 break; 1468 case MSR_IA32_UCODE_REV: 1469 rdmsrl_safe(msr->index, &msr->data); 1470 break; 1471 default: 1472 return static_call(kvm_x86_get_msr_feature)(msr); 1473 } 1474 return 0; 1475 } 1476 1477 static int do_get_msr_feature(struct kvm_vcpu *vcpu, unsigned index, u64 *data) 1478 { 1479 struct kvm_msr_entry msr; 1480 int r; 1481 1482 msr.index = index; 1483 r = kvm_get_msr_feature(&msr); 1484 1485 if (r == KVM_MSR_RET_INVALID) { 1486 /* Unconditionally clear the output for simplicity */ 1487 *data = 0; 1488 if (kvm_msr_ignored_check(index, 0, false)) 1489 r = 0; 1490 } 1491 1492 if (r) 1493 return r; 1494 1495 *data = msr.data; 1496 1497 return 0; 1498 } 1499 1500 static bool __kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer) 1501 { 1502 if (efer & EFER_FFXSR && !guest_cpuid_has(vcpu, X86_FEATURE_FXSR_OPT)) 1503 return false; 1504 1505 if (efer & EFER_SVME && !guest_cpuid_has(vcpu, X86_FEATURE_SVM)) 1506 return false; 1507 1508 if (efer & (EFER_LME | EFER_LMA) && 1509 !guest_cpuid_has(vcpu, X86_FEATURE_LM)) 1510 return false; 1511 1512 if (efer & EFER_NX && !guest_cpuid_has(vcpu, X86_FEATURE_NX)) 1513 return false; 1514 1515 return true; 1516 1517 } 1518 bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer) 1519 { 1520 if (efer & efer_reserved_bits) 1521 return false; 1522 1523 return __kvm_valid_efer(vcpu, efer); 1524 } 1525 EXPORT_SYMBOL_GPL(kvm_valid_efer); 1526 1527 static int set_efer(struct kvm_vcpu *vcpu, struct msr_data *msr_info) 1528 { 1529 u64 old_efer = vcpu->arch.efer; 1530 u64 efer = msr_info->data; 1531 int r; 1532 1533 if (efer & efer_reserved_bits) 1534 return 1; 1535 1536 if (!msr_info->host_initiated) { 1537 if (!__kvm_valid_efer(vcpu, efer)) 1538 return 1; 1539 1540 if (is_paging(vcpu) && 1541 (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME)) 1542 return 1; 1543 } 1544 1545 efer &= ~EFER_LMA; 1546 efer |= vcpu->arch.efer & EFER_LMA; 1547 1548 r = static_call(kvm_x86_set_efer)(vcpu, efer); 1549 if (r) { 1550 WARN_ON(r > 0); 1551 return r; 1552 } 1553 1554 /* Update reserved bits */ 1555 if ((efer ^ old_efer) & EFER_NX) 1556 kvm_mmu_reset_context(vcpu); 1557 1558 return 0; 1559 } 1560 1561 void kvm_enable_efer_bits(u64 mask) 1562 { 1563 efer_reserved_bits &= ~mask; 1564 } 1565 EXPORT_SYMBOL_GPL(kvm_enable_efer_bits); 1566 1567 bool kvm_msr_allowed(struct kvm_vcpu *vcpu, u32 index, u32 type) 1568 { 1569 struct kvm_x86_msr_filter *msr_filter; 1570 struct msr_bitmap_range *ranges; 1571 struct kvm *kvm = vcpu->kvm; 1572 bool allowed; 1573 int idx; 1574 u32 i; 1575 1576 /* x2APIC MSRs do not support filtering. */ 1577 if (index >= 0x800 && index <= 0x8ff) 1578 return true; 1579 1580 idx = srcu_read_lock(&kvm->srcu); 1581 1582 msr_filter = srcu_dereference(kvm->arch.msr_filter, &kvm->srcu); 1583 if (!msr_filter) { 1584 allowed = true; 1585 goto out; 1586 } 1587 1588 allowed = msr_filter->default_allow; 1589 ranges = msr_filter->ranges; 1590 1591 for (i = 0; i < msr_filter->count; i++) { 1592 u32 start = ranges[i].base; 1593 u32 end = start + ranges[i].nmsrs; 1594 u32 flags = ranges[i].flags; 1595 unsigned long *bitmap = ranges[i].bitmap; 1596 1597 if ((index >= start) && (index < end) && (flags & type)) { 1598 allowed = !!test_bit(index - start, bitmap); 1599 break; 1600 } 1601 } 1602 1603 out: 1604 srcu_read_unlock(&kvm->srcu, idx); 1605 1606 return allowed; 1607 } 1608 EXPORT_SYMBOL_GPL(kvm_msr_allowed); 1609 1610 /* 1611 * Write @data into the MSR specified by @index. Select MSR specific fault 1612 * checks are bypassed if @host_initiated is %true. 1613 * Returns 0 on success, non-0 otherwise. 1614 * Assumes vcpu_load() was already called. 1615 */ 1616 static int __kvm_set_msr(struct kvm_vcpu *vcpu, u32 index, u64 data, 1617 bool host_initiated) 1618 { 1619 struct msr_data msr; 1620 1621 if (!host_initiated && !kvm_msr_allowed(vcpu, index, KVM_MSR_FILTER_WRITE)) 1622 return KVM_MSR_RET_FILTERED; 1623 1624 switch (index) { 1625 case MSR_FS_BASE: 1626 case MSR_GS_BASE: 1627 case MSR_KERNEL_GS_BASE: 1628 case MSR_CSTAR: 1629 case MSR_LSTAR: 1630 if (is_noncanonical_address(data, vcpu)) 1631 return 1; 1632 break; 1633 case MSR_IA32_SYSENTER_EIP: 1634 case MSR_IA32_SYSENTER_ESP: 1635 /* 1636 * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if 1637 * non-canonical address is written on Intel but not on 1638 * AMD (which ignores the top 32-bits, because it does 1639 * not implement 64-bit SYSENTER). 1640 * 1641 * 64-bit code should hence be able to write a non-canonical 1642 * value on AMD. Making the address canonical ensures that 1643 * vmentry does not fail on Intel after writing a non-canonical 1644 * value, and that something deterministic happens if the guest 1645 * invokes 64-bit SYSENTER. 1646 */ 1647 data = get_canonical(data, vcpu_virt_addr_bits(vcpu)); 1648 break; 1649 case MSR_TSC_AUX: 1650 if (!kvm_is_supported_user_return_msr(MSR_TSC_AUX)) 1651 return 1; 1652 1653 if (!host_initiated && 1654 !guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP) && 1655 !guest_cpuid_has(vcpu, X86_FEATURE_RDPID)) 1656 return 1; 1657 1658 /* 1659 * Per Intel's SDM, bits 63:32 are reserved, but AMD's APM has 1660 * incomplete and conflicting architectural behavior. Current 1661 * AMD CPUs completely ignore bits 63:32, i.e. they aren't 1662 * reserved and always read as zeros. Enforce Intel's reserved 1663 * bits check if and only if the guest CPU is Intel, and clear 1664 * the bits in all other cases. This ensures cross-vendor 1665 * migration will provide consistent behavior for the guest. 1666 */ 1667 if (guest_cpuid_is_intel(vcpu) && (data >> 32) != 0) 1668 return 1; 1669 1670 data = (u32)data; 1671 break; 1672 } 1673 1674 msr.data = data; 1675 msr.index = index; 1676 msr.host_initiated = host_initiated; 1677 1678 return static_call(kvm_x86_set_msr)(vcpu, &msr); 1679 } 1680 1681 static int kvm_set_msr_ignored_check(struct kvm_vcpu *vcpu, 1682 u32 index, u64 data, bool host_initiated) 1683 { 1684 int ret = __kvm_set_msr(vcpu, index, data, host_initiated); 1685 1686 if (ret == KVM_MSR_RET_INVALID) 1687 if (kvm_msr_ignored_check(index, data, true)) 1688 ret = 0; 1689 1690 return ret; 1691 } 1692 1693 /* 1694 * Read the MSR specified by @index into @data. Select MSR specific fault 1695 * checks are bypassed if @host_initiated is %true. 1696 * Returns 0 on success, non-0 otherwise. 1697 * Assumes vcpu_load() was already called. 1698 */ 1699 int __kvm_get_msr(struct kvm_vcpu *vcpu, u32 index, u64 *data, 1700 bool host_initiated) 1701 { 1702 struct msr_data msr; 1703 int ret; 1704 1705 if (!host_initiated && !kvm_msr_allowed(vcpu, index, KVM_MSR_FILTER_READ)) 1706 return KVM_MSR_RET_FILTERED; 1707 1708 switch (index) { 1709 case MSR_TSC_AUX: 1710 if (!kvm_is_supported_user_return_msr(MSR_TSC_AUX)) 1711 return 1; 1712 1713 if (!host_initiated && 1714 !guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP) && 1715 !guest_cpuid_has(vcpu, X86_FEATURE_RDPID)) 1716 return 1; 1717 break; 1718 } 1719 1720 msr.index = index; 1721 msr.host_initiated = host_initiated; 1722 1723 ret = static_call(kvm_x86_get_msr)(vcpu, &msr); 1724 if (!ret) 1725 *data = msr.data; 1726 return ret; 1727 } 1728 1729 static int kvm_get_msr_ignored_check(struct kvm_vcpu *vcpu, 1730 u32 index, u64 *data, bool host_initiated) 1731 { 1732 int ret = __kvm_get_msr(vcpu, index, data, host_initiated); 1733 1734 if (ret == KVM_MSR_RET_INVALID) { 1735 /* Unconditionally clear *data for simplicity */ 1736 *data = 0; 1737 if (kvm_msr_ignored_check(index, 0, false)) 1738 ret = 0; 1739 } 1740 1741 return ret; 1742 } 1743 1744 int kvm_get_msr(struct kvm_vcpu *vcpu, u32 index, u64 *data) 1745 { 1746 return kvm_get_msr_ignored_check(vcpu, index, data, false); 1747 } 1748 EXPORT_SYMBOL_GPL(kvm_get_msr); 1749 1750 int kvm_set_msr(struct kvm_vcpu *vcpu, u32 index, u64 data) 1751 { 1752 return kvm_set_msr_ignored_check(vcpu, index, data, false); 1753 } 1754 EXPORT_SYMBOL_GPL(kvm_set_msr); 1755 1756 static int complete_emulated_rdmsr(struct kvm_vcpu *vcpu) 1757 { 1758 int err = vcpu->run->msr.error; 1759 if (!err) { 1760 kvm_rax_write(vcpu, (u32)vcpu->run->msr.data); 1761 kvm_rdx_write(vcpu, vcpu->run->msr.data >> 32); 1762 } 1763 1764 return static_call(kvm_x86_complete_emulated_msr)(vcpu, err); 1765 } 1766 1767 static int complete_emulated_wrmsr(struct kvm_vcpu *vcpu) 1768 { 1769 return static_call(kvm_x86_complete_emulated_msr)(vcpu, vcpu->run->msr.error); 1770 } 1771 1772 static u64 kvm_msr_reason(int r) 1773 { 1774 switch (r) { 1775 case KVM_MSR_RET_INVALID: 1776 return KVM_MSR_EXIT_REASON_UNKNOWN; 1777 case KVM_MSR_RET_FILTERED: 1778 return KVM_MSR_EXIT_REASON_FILTER; 1779 default: 1780 return KVM_MSR_EXIT_REASON_INVAL; 1781 } 1782 } 1783 1784 static int kvm_msr_user_space(struct kvm_vcpu *vcpu, u32 index, 1785 u32 exit_reason, u64 data, 1786 int (*completion)(struct kvm_vcpu *vcpu), 1787 int r) 1788 { 1789 u64 msr_reason = kvm_msr_reason(r); 1790 1791 /* Check if the user wanted to know about this MSR fault */ 1792 if (!(vcpu->kvm->arch.user_space_msr_mask & msr_reason)) 1793 return 0; 1794 1795 vcpu->run->exit_reason = exit_reason; 1796 vcpu->run->msr.error = 0; 1797 memset(vcpu->run->msr.pad, 0, sizeof(vcpu->run->msr.pad)); 1798 vcpu->run->msr.reason = msr_reason; 1799 vcpu->run->msr.index = index; 1800 vcpu->run->msr.data = data; 1801 vcpu->arch.complete_userspace_io = completion; 1802 1803 return 1; 1804 } 1805 1806 static int kvm_get_msr_user_space(struct kvm_vcpu *vcpu, u32 index, int r) 1807 { 1808 return kvm_msr_user_space(vcpu, index, KVM_EXIT_X86_RDMSR, 0, 1809 complete_emulated_rdmsr, r); 1810 } 1811 1812 static int kvm_set_msr_user_space(struct kvm_vcpu *vcpu, u32 index, u64 data, int r) 1813 { 1814 return kvm_msr_user_space(vcpu, index, KVM_EXIT_X86_WRMSR, data, 1815 complete_emulated_wrmsr, r); 1816 } 1817 1818 int kvm_emulate_rdmsr(struct kvm_vcpu *vcpu) 1819 { 1820 u32 ecx = kvm_rcx_read(vcpu); 1821 u64 data; 1822 int r; 1823 1824 r = kvm_get_msr(vcpu, ecx, &data); 1825 1826 /* MSR read failed? See if we should ask user space */ 1827 if (r && kvm_get_msr_user_space(vcpu, ecx, r)) { 1828 /* Bounce to user space */ 1829 return 0; 1830 } 1831 1832 if (!r) { 1833 trace_kvm_msr_read(ecx, data); 1834 1835 kvm_rax_write(vcpu, data & -1u); 1836 kvm_rdx_write(vcpu, (data >> 32) & -1u); 1837 } else { 1838 trace_kvm_msr_read_ex(ecx); 1839 } 1840 1841 return static_call(kvm_x86_complete_emulated_msr)(vcpu, r); 1842 } 1843 EXPORT_SYMBOL_GPL(kvm_emulate_rdmsr); 1844 1845 int kvm_emulate_wrmsr(struct kvm_vcpu *vcpu) 1846 { 1847 u32 ecx = kvm_rcx_read(vcpu); 1848 u64 data = kvm_read_edx_eax(vcpu); 1849 int r; 1850 1851 r = kvm_set_msr(vcpu, ecx, data); 1852 1853 /* MSR write failed? See if we should ask user space */ 1854 if (r && kvm_set_msr_user_space(vcpu, ecx, data, r)) 1855 /* Bounce to user space */ 1856 return 0; 1857 1858 /* Signal all other negative errors to userspace */ 1859 if (r < 0) 1860 return r; 1861 1862 if (!r) 1863 trace_kvm_msr_write(ecx, data); 1864 else 1865 trace_kvm_msr_write_ex(ecx, data); 1866 1867 return static_call(kvm_x86_complete_emulated_msr)(vcpu, r); 1868 } 1869 EXPORT_SYMBOL_GPL(kvm_emulate_wrmsr); 1870 1871 int kvm_emulate_as_nop(struct kvm_vcpu *vcpu) 1872 { 1873 return kvm_skip_emulated_instruction(vcpu); 1874 } 1875 EXPORT_SYMBOL_GPL(kvm_emulate_as_nop); 1876 1877 int kvm_emulate_invd(struct kvm_vcpu *vcpu) 1878 { 1879 /* Treat an INVD instruction as a NOP and just skip it. */ 1880 return kvm_emulate_as_nop(vcpu); 1881 } 1882 EXPORT_SYMBOL_GPL(kvm_emulate_invd); 1883 1884 int kvm_emulate_mwait(struct kvm_vcpu *vcpu) 1885 { 1886 pr_warn_once("kvm: MWAIT instruction emulated as NOP!\n"); 1887 return kvm_emulate_as_nop(vcpu); 1888 } 1889 EXPORT_SYMBOL_GPL(kvm_emulate_mwait); 1890 1891 int kvm_handle_invalid_op(struct kvm_vcpu *vcpu) 1892 { 1893 kvm_queue_exception(vcpu, UD_VECTOR); 1894 return 1; 1895 } 1896 EXPORT_SYMBOL_GPL(kvm_handle_invalid_op); 1897 1898 int kvm_emulate_monitor(struct kvm_vcpu *vcpu) 1899 { 1900 pr_warn_once("kvm: MONITOR instruction emulated as NOP!\n"); 1901 return kvm_emulate_as_nop(vcpu); 1902 } 1903 EXPORT_SYMBOL_GPL(kvm_emulate_monitor); 1904 1905 static inline bool kvm_vcpu_exit_request(struct kvm_vcpu *vcpu) 1906 { 1907 xfer_to_guest_mode_prepare(); 1908 return vcpu->mode == EXITING_GUEST_MODE || kvm_request_pending(vcpu) || 1909 xfer_to_guest_mode_work_pending(); 1910 } 1911 1912 /* 1913 * The fast path for frequent and performance sensitive wrmsr emulation, 1914 * i.e. the sending of IPI, sending IPI early in the VM-Exit flow reduces 1915 * the latency of virtual IPI by avoiding the expensive bits of transitioning 1916 * from guest to host, e.g. reacquiring KVM's SRCU lock. In contrast to the 1917 * other cases which must be called after interrupts are enabled on the host. 1918 */ 1919 static int handle_fastpath_set_x2apic_icr_irqoff(struct kvm_vcpu *vcpu, u64 data) 1920 { 1921 if (!lapic_in_kernel(vcpu) || !apic_x2apic_mode(vcpu->arch.apic)) 1922 return 1; 1923 1924 if (((data & APIC_SHORT_MASK) == APIC_DEST_NOSHORT) && 1925 ((data & APIC_DEST_MASK) == APIC_DEST_PHYSICAL) && 1926 ((data & APIC_MODE_MASK) == APIC_DM_FIXED) && 1927 ((u32)(data >> 32) != X2APIC_BROADCAST)) { 1928 1929 data &= ~(1 << 12); 1930 kvm_apic_send_ipi(vcpu->arch.apic, (u32)data, (u32)(data >> 32)); 1931 kvm_lapic_set_reg(vcpu->arch.apic, APIC_ICR2, (u32)(data >> 32)); 1932 kvm_lapic_set_reg(vcpu->arch.apic, APIC_ICR, (u32)data); 1933 trace_kvm_apic_write(APIC_ICR, (u32)data); 1934 return 0; 1935 } 1936 1937 return 1; 1938 } 1939 1940 static int handle_fastpath_set_tscdeadline(struct kvm_vcpu *vcpu, u64 data) 1941 { 1942 if (!kvm_can_use_hv_timer(vcpu)) 1943 return 1; 1944 1945 kvm_set_lapic_tscdeadline_msr(vcpu, data); 1946 return 0; 1947 } 1948 1949 fastpath_t handle_fastpath_set_msr_irqoff(struct kvm_vcpu *vcpu) 1950 { 1951 u32 msr = kvm_rcx_read(vcpu); 1952 u64 data; 1953 fastpath_t ret = EXIT_FASTPATH_NONE; 1954 1955 switch (msr) { 1956 case APIC_BASE_MSR + (APIC_ICR >> 4): 1957 data = kvm_read_edx_eax(vcpu); 1958 if (!handle_fastpath_set_x2apic_icr_irqoff(vcpu, data)) { 1959 kvm_skip_emulated_instruction(vcpu); 1960 ret = EXIT_FASTPATH_EXIT_HANDLED; 1961 } 1962 break; 1963 case MSR_IA32_TSC_DEADLINE: 1964 data = kvm_read_edx_eax(vcpu); 1965 if (!handle_fastpath_set_tscdeadline(vcpu, data)) { 1966 kvm_skip_emulated_instruction(vcpu); 1967 ret = EXIT_FASTPATH_REENTER_GUEST; 1968 } 1969 break; 1970 default: 1971 break; 1972 } 1973 1974 if (ret != EXIT_FASTPATH_NONE) 1975 trace_kvm_msr_write(msr, data); 1976 1977 return ret; 1978 } 1979 EXPORT_SYMBOL_GPL(handle_fastpath_set_msr_irqoff); 1980 1981 /* 1982 * Adapt set_msr() to msr_io()'s calling convention 1983 */ 1984 static int do_get_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data) 1985 { 1986 return kvm_get_msr_ignored_check(vcpu, index, data, true); 1987 } 1988 1989 static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data) 1990 { 1991 return kvm_set_msr_ignored_check(vcpu, index, *data, true); 1992 } 1993 1994 #ifdef CONFIG_X86_64 1995 struct pvclock_clock { 1996 int vclock_mode; 1997 u64 cycle_last; 1998 u64 mask; 1999 u32 mult; 2000 u32 shift; 2001 u64 base_cycles; 2002 u64 offset; 2003 }; 2004 2005 struct pvclock_gtod_data { 2006 seqcount_t seq; 2007 2008 struct pvclock_clock clock; /* extract of a clocksource struct */ 2009 struct pvclock_clock raw_clock; /* extract of a clocksource struct */ 2010 2011 ktime_t offs_boot; 2012 u64 wall_time_sec; 2013 }; 2014 2015 static struct pvclock_gtod_data pvclock_gtod_data; 2016 2017 static void update_pvclock_gtod(struct timekeeper *tk) 2018 { 2019 struct pvclock_gtod_data *vdata = &pvclock_gtod_data; 2020 2021 write_seqcount_begin(&vdata->seq); 2022 2023 /* copy pvclock gtod data */ 2024 vdata->clock.vclock_mode = tk->tkr_mono.clock->vdso_clock_mode; 2025 vdata->clock.cycle_last = tk->tkr_mono.cycle_last; 2026 vdata->clock.mask = tk->tkr_mono.mask; 2027 vdata->clock.mult = tk->tkr_mono.mult; 2028 vdata->clock.shift = tk->tkr_mono.shift; 2029 vdata->clock.base_cycles = tk->tkr_mono.xtime_nsec; 2030 vdata->clock.offset = tk->tkr_mono.base; 2031 2032 vdata->raw_clock.vclock_mode = tk->tkr_raw.clock->vdso_clock_mode; 2033 vdata->raw_clock.cycle_last = tk->tkr_raw.cycle_last; 2034 vdata->raw_clock.mask = tk->tkr_raw.mask; 2035 vdata->raw_clock.mult = tk->tkr_raw.mult; 2036 vdata->raw_clock.shift = tk->tkr_raw.shift; 2037 vdata->raw_clock.base_cycles = tk->tkr_raw.xtime_nsec; 2038 vdata->raw_clock.offset = tk->tkr_raw.base; 2039 2040 vdata->wall_time_sec = tk->xtime_sec; 2041 2042 vdata->offs_boot = tk->offs_boot; 2043 2044 write_seqcount_end(&vdata->seq); 2045 } 2046 2047 static s64 get_kvmclock_base_ns(void) 2048 { 2049 /* Count up from boot time, but with the frequency of the raw clock. */ 2050 return ktime_to_ns(ktime_add(ktime_get_raw(), pvclock_gtod_data.offs_boot)); 2051 } 2052 #else 2053 static s64 get_kvmclock_base_ns(void) 2054 { 2055 /* Master clock not used, so we can just use CLOCK_BOOTTIME. */ 2056 return ktime_get_boottime_ns(); 2057 } 2058 #endif 2059 2060 void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock, int sec_hi_ofs) 2061 { 2062 int version; 2063 int r; 2064 struct pvclock_wall_clock wc; 2065 u32 wc_sec_hi; 2066 u64 wall_nsec; 2067 2068 if (!wall_clock) 2069 return; 2070 2071 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version)); 2072 if (r) 2073 return; 2074 2075 if (version & 1) 2076 ++version; /* first time write, random junk */ 2077 2078 ++version; 2079 2080 if (kvm_write_guest(kvm, wall_clock, &version, sizeof(version))) 2081 return; 2082 2083 /* 2084 * The guest calculates current wall clock time by adding 2085 * system time (updated by kvm_guest_time_update below) to the 2086 * wall clock specified here. We do the reverse here. 2087 */ 2088 wall_nsec = ktime_get_real_ns() - get_kvmclock_ns(kvm); 2089 2090 wc.nsec = do_div(wall_nsec, 1000000000); 2091 wc.sec = (u32)wall_nsec; /* overflow in 2106 guest time */ 2092 wc.version = version; 2093 2094 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc)); 2095 2096 if (sec_hi_ofs) { 2097 wc_sec_hi = wall_nsec >> 32; 2098 kvm_write_guest(kvm, wall_clock + sec_hi_ofs, 2099 &wc_sec_hi, sizeof(wc_sec_hi)); 2100 } 2101 2102 version++; 2103 kvm_write_guest(kvm, wall_clock, &version, sizeof(version)); 2104 } 2105 2106 static void kvm_write_system_time(struct kvm_vcpu *vcpu, gpa_t system_time, 2107 bool old_msr, bool host_initiated) 2108 { 2109 struct kvm_arch *ka = &vcpu->kvm->arch; 2110 2111 if (vcpu->vcpu_id == 0 && !host_initiated) { 2112 if (ka->boot_vcpu_runs_old_kvmclock != old_msr) 2113 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu); 2114 2115 ka->boot_vcpu_runs_old_kvmclock = old_msr; 2116 } 2117 2118 vcpu->arch.time = system_time; 2119 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu); 2120 2121 /* we verify if the enable bit is set... */ 2122 vcpu->arch.pv_time_enabled = false; 2123 if (!(system_time & 1)) 2124 return; 2125 2126 if (!kvm_gfn_to_hva_cache_init(vcpu->kvm, 2127 &vcpu->arch.pv_time, system_time & ~1ULL, 2128 sizeof(struct pvclock_vcpu_time_info))) 2129 vcpu->arch.pv_time_enabled = true; 2130 2131 return; 2132 } 2133 2134 static uint32_t div_frac(uint32_t dividend, uint32_t divisor) 2135 { 2136 do_shl32_div32(dividend, divisor); 2137 return dividend; 2138 } 2139 2140 static void kvm_get_time_scale(uint64_t scaled_hz, uint64_t base_hz, 2141 s8 *pshift, u32 *pmultiplier) 2142 { 2143 uint64_t scaled64; 2144 int32_t shift = 0; 2145 uint64_t tps64; 2146 uint32_t tps32; 2147 2148 tps64 = base_hz; 2149 scaled64 = scaled_hz; 2150 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) { 2151 tps64 >>= 1; 2152 shift--; 2153 } 2154 2155 tps32 = (uint32_t)tps64; 2156 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) { 2157 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000) 2158 scaled64 >>= 1; 2159 else 2160 tps32 <<= 1; 2161 shift++; 2162 } 2163 2164 *pshift = shift; 2165 *pmultiplier = div_frac(scaled64, tps32); 2166 } 2167 2168 #ifdef CONFIG_X86_64 2169 static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0); 2170 #endif 2171 2172 static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz); 2173 static unsigned long max_tsc_khz; 2174 2175 static u32 adjust_tsc_khz(u32 khz, s32 ppm) 2176 { 2177 u64 v = (u64)khz * (1000000 + ppm); 2178 do_div(v, 1000000); 2179 return v; 2180 } 2181 2182 static int set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale) 2183 { 2184 u64 ratio; 2185 2186 /* Guest TSC same frequency as host TSC? */ 2187 if (!scale) { 2188 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio; 2189 return 0; 2190 } 2191 2192 /* TSC scaling supported? */ 2193 if (!kvm_has_tsc_control) { 2194 if (user_tsc_khz > tsc_khz) { 2195 vcpu->arch.tsc_catchup = 1; 2196 vcpu->arch.tsc_always_catchup = 1; 2197 return 0; 2198 } else { 2199 pr_warn_ratelimited("user requested TSC rate below hardware speed\n"); 2200 return -1; 2201 } 2202 } 2203 2204 /* TSC scaling required - calculate ratio */ 2205 ratio = mul_u64_u32_div(1ULL << kvm_tsc_scaling_ratio_frac_bits, 2206 user_tsc_khz, tsc_khz); 2207 2208 if (ratio == 0 || ratio >= kvm_max_tsc_scaling_ratio) { 2209 pr_warn_ratelimited("Invalid TSC scaling ratio - virtual-tsc-khz=%u\n", 2210 user_tsc_khz); 2211 return -1; 2212 } 2213 2214 vcpu->arch.tsc_scaling_ratio = ratio; 2215 return 0; 2216 } 2217 2218 static int kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz) 2219 { 2220 u32 thresh_lo, thresh_hi; 2221 int use_scaling = 0; 2222 2223 /* tsc_khz can be zero if TSC calibration fails */ 2224 if (user_tsc_khz == 0) { 2225 /* set tsc_scaling_ratio to a safe value */ 2226 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio; 2227 return -1; 2228 } 2229 2230 /* Compute a scale to convert nanoseconds in TSC cycles */ 2231 kvm_get_time_scale(user_tsc_khz * 1000LL, NSEC_PER_SEC, 2232 &vcpu->arch.virtual_tsc_shift, 2233 &vcpu->arch.virtual_tsc_mult); 2234 vcpu->arch.virtual_tsc_khz = user_tsc_khz; 2235 2236 /* 2237 * Compute the variation in TSC rate which is acceptable 2238 * within the range of tolerance and decide if the 2239 * rate being applied is within that bounds of the hardware 2240 * rate. If so, no scaling or compensation need be done. 2241 */ 2242 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm); 2243 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm); 2244 if (user_tsc_khz < thresh_lo || user_tsc_khz > thresh_hi) { 2245 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", user_tsc_khz, thresh_lo, thresh_hi); 2246 use_scaling = 1; 2247 } 2248 return set_tsc_khz(vcpu, user_tsc_khz, use_scaling); 2249 } 2250 2251 static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns) 2252 { 2253 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec, 2254 vcpu->arch.virtual_tsc_mult, 2255 vcpu->arch.virtual_tsc_shift); 2256 tsc += vcpu->arch.this_tsc_write; 2257 return tsc; 2258 } 2259 2260 static inline int gtod_is_based_on_tsc(int mode) 2261 { 2262 return mode == VDSO_CLOCKMODE_TSC || mode == VDSO_CLOCKMODE_HVCLOCK; 2263 } 2264 2265 static void kvm_track_tsc_matching(struct kvm_vcpu *vcpu) 2266 { 2267 #ifdef CONFIG_X86_64 2268 bool vcpus_matched; 2269 struct kvm_arch *ka = &vcpu->kvm->arch; 2270 struct pvclock_gtod_data *gtod = &pvclock_gtod_data; 2271 2272 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 == 2273 atomic_read(&vcpu->kvm->online_vcpus)); 2274 2275 /* 2276 * Once the masterclock is enabled, always perform request in 2277 * order to update it. 2278 * 2279 * In order to enable masterclock, the host clocksource must be TSC 2280 * and the vcpus need to have matched TSCs. When that happens, 2281 * perform request to enable masterclock. 2282 */ 2283 if (ka->use_master_clock || 2284 (gtod_is_based_on_tsc(gtod->clock.vclock_mode) && vcpus_matched)) 2285 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu); 2286 2287 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc, 2288 atomic_read(&vcpu->kvm->online_vcpus), 2289 ka->use_master_clock, gtod->clock.vclock_mode); 2290 #endif 2291 } 2292 2293 /* 2294 * Multiply tsc by a fixed point number represented by ratio. 2295 * 2296 * The most significant 64-N bits (mult) of ratio represent the 2297 * integral part of the fixed point number; the remaining N bits 2298 * (frac) represent the fractional part, ie. ratio represents a fixed 2299 * point number (mult + frac * 2^(-N)). 2300 * 2301 * N equals to kvm_tsc_scaling_ratio_frac_bits. 2302 */ 2303 static inline u64 __scale_tsc(u64 ratio, u64 tsc) 2304 { 2305 return mul_u64_u64_shr(tsc, ratio, kvm_tsc_scaling_ratio_frac_bits); 2306 } 2307 2308 u64 kvm_scale_tsc(struct kvm_vcpu *vcpu, u64 tsc) 2309 { 2310 u64 _tsc = tsc; 2311 u64 ratio = vcpu->arch.tsc_scaling_ratio; 2312 2313 if (ratio != kvm_default_tsc_scaling_ratio) 2314 _tsc = __scale_tsc(ratio, tsc); 2315 2316 return _tsc; 2317 } 2318 EXPORT_SYMBOL_GPL(kvm_scale_tsc); 2319 2320 static u64 kvm_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc) 2321 { 2322 u64 tsc; 2323 2324 tsc = kvm_scale_tsc(vcpu, rdtsc()); 2325 2326 return target_tsc - tsc; 2327 } 2328 2329 u64 kvm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc) 2330 { 2331 return vcpu->arch.l1_tsc_offset + kvm_scale_tsc(vcpu, host_tsc); 2332 } 2333 EXPORT_SYMBOL_GPL(kvm_read_l1_tsc); 2334 2335 static void kvm_vcpu_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset) 2336 { 2337 vcpu->arch.l1_tsc_offset = offset; 2338 vcpu->arch.tsc_offset = static_call(kvm_x86_write_l1_tsc_offset)(vcpu, offset); 2339 } 2340 2341 static inline bool kvm_check_tsc_unstable(void) 2342 { 2343 #ifdef CONFIG_X86_64 2344 /* 2345 * TSC is marked unstable when we're running on Hyper-V, 2346 * 'TSC page' clocksource is good. 2347 */ 2348 if (pvclock_gtod_data.clock.vclock_mode == VDSO_CLOCKMODE_HVCLOCK) 2349 return false; 2350 #endif 2351 return check_tsc_unstable(); 2352 } 2353 2354 static void kvm_synchronize_tsc(struct kvm_vcpu *vcpu, u64 data) 2355 { 2356 struct kvm *kvm = vcpu->kvm; 2357 u64 offset, ns, elapsed; 2358 unsigned long flags; 2359 bool matched; 2360 bool already_matched; 2361 bool synchronizing = false; 2362 2363 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags); 2364 offset = kvm_compute_tsc_offset(vcpu, data); 2365 ns = get_kvmclock_base_ns(); 2366 elapsed = ns - kvm->arch.last_tsc_nsec; 2367 2368 if (vcpu->arch.virtual_tsc_khz) { 2369 if (data == 0) { 2370 /* 2371 * detection of vcpu initialization -- need to sync 2372 * with other vCPUs. This particularly helps to keep 2373 * kvm_clock stable after CPU hotplug 2374 */ 2375 synchronizing = true; 2376 } else { 2377 u64 tsc_exp = kvm->arch.last_tsc_write + 2378 nsec_to_cycles(vcpu, elapsed); 2379 u64 tsc_hz = vcpu->arch.virtual_tsc_khz * 1000LL; 2380 /* 2381 * Special case: TSC write with a small delta (1 second) 2382 * of virtual cycle time against real time is 2383 * interpreted as an attempt to synchronize the CPU. 2384 */ 2385 synchronizing = data < tsc_exp + tsc_hz && 2386 data + tsc_hz > tsc_exp; 2387 } 2388 } 2389 2390 /* 2391 * For a reliable TSC, we can match TSC offsets, and for an unstable 2392 * TSC, we add elapsed time in this computation. We could let the 2393 * compensation code attempt to catch up if we fall behind, but 2394 * it's better to try to match offsets from the beginning. 2395 */ 2396 if (synchronizing && 2397 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) { 2398 if (!kvm_check_tsc_unstable()) { 2399 offset = kvm->arch.cur_tsc_offset; 2400 } else { 2401 u64 delta = nsec_to_cycles(vcpu, elapsed); 2402 data += delta; 2403 offset = kvm_compute_tsc_offset(vcpu, data); 2404 } 2405 matched = true; 2406 already_matched = (vcpu->arch.this_tsc_generation == kvm->arch.cur_tsc_generation); 2407 } else { 2408 /* 2409 * We split periods of matched TSC writes into generations. 2410 * For each generation, we track the original measured 2411 * nanosecond time, offset, and write, so if TSCs are in 2412 * sync, we can match exact offset, and if not, we can match 2413 * exact software computation in compute_guest_tsc() 2414 * 2415 * These values are tracked in kvm->arch.cur_xxx variables. 2416 */ 2417 kvm->arch.cur_tsc_generation++; 2418 kvm->arch.cur_tsc_nsec = ns; 2419 kvm->arch.cur_tsc_write = data; 2420 kvm->arch.cur_tsc_offset = offset; 2421 matched = false; 2422 } 2423 2424 /* 2425 * We also track th most recent recorded KHZ, write and time to 2426 * allow the matching interval to be extended at each write. 2427 */ 2428 kvm->arch.last_tsc_nsec = ns; 2429 kvm->arch.last_tsc_write = data; 2430 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz; 2431 2432 vcpu->arch.last_guest_tsc = data; 2433 2434 /* Keep track of which generation this VCPU has synchronized to */ 2435 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation; 2436 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec; 2437 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write; 2438 2439 kvm_vcpu_write_tsc_offset(vcpu, offset); 2440 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags); 2441 2442 spin_lock_irqsave(&kvm->arch.pvclock_gtod_sync_lock, flags); 2443 if (!matched) { 2444 kvm->arch.nr_vcpus_matched_tsc = 0; 2445 } else if (!already_matched) { 2446 kvm->arch.nr_vcpus_matched_tsc++; 2447 } 2448 2449 kvm_track_tsc_matching(vcpu); 2450 spin_unlock_irqrestore(&kvm->arch.pvclock_gtod_sync_lock, flags); 2451 } 2452 2453 static inline void adjust_tsc_offset_guest(struct kvm_vcpu *vcpu, 2454 s64 adjustment) 2455 { 2456 u64 tsc_offset = vcpu->arch.l1_tsc_offset; 2457 kvm_vcpu_write_tsc_offset(vcpu, tsc_offset + adjustment); 2458 } 2459 2460 static inline void adjust_tsc_offset_host(struct kvm_vcpu *vcpu, s64 adjustment) 2461 { 2462 if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio) 2463 WARN_ON(adjustment < 0); 2464 adjustment = kvm_scale_tsc(vcpu, (u64) adjustment); 2465 adjust_tsc_offset_guest(vcpu, adjustment); 2466 } 2467 2468 #ifdef CONFIG_X86_64 2469 2470 static u64 read_tsc(void) 2471 { 2472 u64 ret = (u64)rdtsc_ordered(); 2473 u64 last = pvclock_gtod_data.clock.cycle_last; 2474 2475 if (likely(ret >= last)) 2476 return ret; 2477 2478 /* 2479 * GCC likes to generate cmov here, but this branch is extremely 2480 * predictable (it's just a function of time and the likely is 2481 * very likely) and there's a data dependence, so force GCC 2482 * to generate a branch instead. I don't barrier() because 2483 * we don't actually need a barrier, and if this function 2484 * ever gets inlined it will generate worse code. 2485 */ 2486 asm volatile (""); 2487 return last; 2488 } 2489 2490 static inline u64 vgettsc(struct pvclock_clock *clock, u64 *tsc_timestamp, 2491 int *mode) 2492 { 2493 long v; 2494 u64 tsc_pg_val; 2495 2496 switch (clock->vclock_mode) { 2497 case VDSO_CLOCKMODE_HVCLOCK: 2498 tsc_pg_val = hv_read_tsc_page_tsc(hv_get_tsc_page(), 2499 tsc_timestamp); 2500 if (tsc_pg_val != U64_MAX) { 2501 /* TSC page valid */ 2502 *mode = VDSO_CLOCKMODE_HVCLOCK; 2503 v = (tsc_pg_val - clock->cycle_last) & 2504 clock->mask; 2505 } else { 2506 /* TSC page invalid */ 2507 *mode = VDSO_CLOCKMODE_NONE; 2508 } 2509 break; 2510 case VDSO_CLOCKMODE_TSC: 2511 *mode = VDSO_CLOCKMODE_TSC; 2512 *tsc_timestamp = read_tsc(); 2513 v = (*tsc_timestamp - clock->cycle_last) & 2514 clock->mask; 2515 break; 2516 default: 2517 *mode = VDSO_CLOCKMODE_NONE; 2518 } 2519 2520 if (*mode == VDSO_CLOCKMODE_NONE) 2521 *tsc_timestamp = v = 0; 2522 2523 return v * clock->mult; 2524 } 2525 2526 static int do_monotonic_raw(s64 *t, u64 *tsc_timestamp) 2527 { 2528 struct pvclock_gtod_data *gtod = &pvclock_gtod_data; 2529 unsigned long seq; 2530 int mode; 2531 u64 ns; 2532 2533 do { 2534 seq = read_seqcount_begin(>od->seq); 2535 ns = gtod->raw_clock.base_cycles; 2536 ns += vgettsc(>od->raw_clock, tsc_timestamp, &mode); 2537 ns >>= gtod->raw_clock.shift; 2538 ns += ktime_to_ns(ktime_add(gtod->raw_clock.offset, gtod->offs_boot)); 2539 } while (unlikely(read_seqcount_retry(>od->seq, seq))); 2540 *t = ns; 2541 2542 return mode; 2543 } 2544 2545 static int do_realtime(struct timespec64 *ts, u64 *tsc_timestamp) 2546 { 2547 struct pvclock_gtod_data *gtod = &pvclock_gtod_data; 2548 unsigned long seq; 2549 int mode; 2550 u64 ns; 2551 2552 do { 2553 seq = read_seqcount_begin(>od->seq); 2554 ts->tv_sec = gtod->wall_time_sec; 2555 ns = gtod->clock.base_cycles; 2556 ns += vgettsc(>od->clock, tsc_timestamp, &mode); 2557 ns >>= gtod->clock.shift; 2558 } while (unlikely(read_seqcount_retry(>od->seq, seq))); 2559 2560 ts->tv_sec += __iter_div_u64_rem(ns, NSEC_PER_SEC, &ns); 2561 ts->tv_nsec = ns; 2562 2563 return mode; 2564 } 2565 2566 /* returns true if host is using TSC based clocksource */ 2567 static bool kvm_get_time_and_clockread(s64 *kernel_ns, u64 *tsc_timestamp) 2568 { 2569 /* checked again under seqlock below */ 2570 if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode)) 2571 return false; 2572 2573 return gtod_is_based_on_tsc(do_monotonic_raw(kernel_ns, 2574 tsc_timestamp)); 2575 } 2576 2577 /* returns true if host is using TSC based clocksource */ 2578 static bool kvm_get_walltime_and_clockread(struct timespec64 *ts, 2579 u64 *tsc_timestamp) 2580 { 2581 /* checked again under seqlock below */ 2582 if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode)) 2583 return false; 2584 2585 return gtod_is_based_on_tsc(do_realtime(ts, tsc_timestamp)); 2586 } 2587 #endif 2588 2589 /* 2590 * 2591 * Assuming a stable TSC across physical CPUS, and a stable TSC 2592 * across virtual CPUs, the following condition is possible. 2593 * Each numbered line represents an event visible to both 2594 * CPUs at the next numbered event. 2595 * 2596 * "timespecX" represents host monotonic time. "tscX" represents 2597 * RDTSC value. 2598 * 2599 * VCPU0 on CPU0 | VCPU1 on CPU1 2600 * 2601 * 1. read timespec0,tsc0 2602 * 2. | timespec1 = timespec0 + N 2603 * | tsc1 = tsc0 + M 2604 * 3. transition to guest | transition to guest 2605 * 4. ret0 = timespec0 + (rdtsc - tsc0) | 2606 * 5. | ret1 = timespec1 + (rdtsc - tsc1) 2607 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M)) 2608 * 2609 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity: 2610 * 2611 * - ret0 < ret1 2612 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M)) 2613 * ... 2614 * - 0 < N - M => M < N 2615 * 2616 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not 2617 * always the case (the difference between two distinct xtime instances 2618 * might be smaller then the difference between corresponding TSC reads, 2619 * when updating guest vcpus pvclock areas). 2620 * 2621 * To avoid that problem, do not allow visibility of distinct 2622 * system_timestamp/tsc_timestamp values simultaneously: use a master 2623 * copy of host monotonic time values. Update that master copy 2624 * in lockstep. 2625 * 2626 * Rely on synchronization of host TSCs and guest TSCs for monotonicity. 2627 * 2628 */ 2629 2630 static void pvclock_update_vm_gtod_copy(struct kvm *kvm) 2631 { 2632 #ifdef CONFIG_X86_64 2633 struct kvm_arch *ka = &kvm->arch; 2634 int vclock_mode; 2635 bool host_tsc_clocksource, vcpus_matched; 2636 2637 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 == 2638 atomic_read(&kvm->online_vcpus)); 2639 2640 /* 2641 * If the host uses TSC clock, then passthrough TSC as stable 2642 * to the guest. 2643 */ 2644 host_tsc_clocksource = kvm_get_time_and_clockread( 2645 &ka->master_kernel_ns, 2646 &ka->master_cycle_now); 2647 2648 ka->use_master_clock = host_tsc_clocksource && vcpus_matched 2649 && !ka->backwards_tsc_observed 2650 && !ka->boot_vcpu_runs_old_kvmclock; 2651 2652 if (ka->use_master_clock) 2653 atomic_set(&kvm_guest_has_master_clock, 1); 2654 2655 vclock_mode = pvclock_gtod_data.clock.vclock_mode; 2656 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode, 2657 vcpus_matched); 2658 #endif 2659 } 2660 2661 void kvm_make_mclock_inprogress_request(struct kvm *kvm) 2662 { 2663 kvm_make_all_cpus_request(kvm, KVM_REQ_MCLOCK_INPROGRESS); 2664 } 2665 2666 static void kvm_gen_update_masterclock(struct kvm *kvm) 2667 { 2668 #ifdef CONFIG_X86_64 2669 int i; 2670 struct kvm_vcpu *vcpu; 2671 struct kvm_arch *ka = &kvm->arch; 2672 unsigned long flags; 2673 2674 kvm_hv_invalidate_tsc_page(kvm); 2675 2676 kvm_make_mclock_inprogress_request(kvm); 2677 2678 /* no guest entries from this point */ 2679 spin_lock_irqsave(&ka->pvclock_gtod_sync_lock, flags); 2680 pvclock_update_vm_gtod_copy(kvm); 2681 spin_unlock_irqrestore(&ka->pvclock_gtod_sync_lock, flags); 2682 2683 kvm_for_each_vcpu(i, vcpu, kvm) 2684 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 2685 2686 /* guest entries allowed */ 2687 kvm_for_each_vcpu(i, vcpu, kvm) 2688 kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu); 2689 #endif 2690 } 2691 2692 u64 get_kvmclock_ns(struct kvm *kvm) 2693 { 2694 struct kvm_arch *ka = &kvm->arch; 2695 struct pvclock_vcpu_time_info hv_clock; 2696 unsigned long flags; 2697 u64 ret; 2698 2699 spin_lock_irqsave(&ka->pvclock_gtod_sync_lock, flags); 2700 if (!ka->use_master_clock) { 2701 spin_unlock_irqrestore(&ka->pvclock_gtod_sync_lock, flags); 2702 return get_kvmclock_base_ns() + ka->kvmclock_offset; 2703 } 2704 2705 hv_clock.tsc_timestamp = ka->master_cycle_now; 2706 hv_clock.system_time = ka->master_kernel_ns + ka->kvmclock_offset; 2707 spin_unlock_irqrestore(&ka->pvclock_gtod_sync_lock, flags); 2708 2709 /* both __this_cpu_read() and rdtsc() should be on the same cpu */ 2710 get_cpu(); 2711 2712 if (__this_cpu_read(cpu_tsc_khz)) { 2713 kvm_get_time_scale(NSEC_PER_SEC, __this_cpu_read(cpu_tsc_khz) * 1000LL, 2714 &hv_clock.tsc_shift, 2715 &hv_clock.tsc_to_system_mul); 2716 ret = __pvclock_read_cycles(&hv_clock, rdtsc()); 2717 } else 2718 ret = get_kvmclock_base_ns() + ka->kvmclock_offset; 2719 2720 put_cpu(); 2721 2722 return ret; 2723 } 2724 2725 static void kvm_setup_pvclock_page(struct kvm_vcpu *v, 2726 struct gfn_to_hva_cache *cache, 2727 unsigned int offset) 2728 { 2729 struct kvm_vcpu_arch *vcpu = &v->arch; 2730 struct pvclock_vcpu_time_info guest_hv_clock; 2731 2732 if (unlikely(kvm_read_guest_offset_cached(v->kvm, cache, 2733 &guest_hv_clock, offset, sizeof(guest_hv_clock)))) 2734 return; 2735 2736 /* This VCPU is paused, but it's legal for a guest to read another 2737 * VCPU's kvmclock, so we really have to follow the specification where 2738 * it says that version is odd if data is being modified, and even after 2739 * it is consistent. 2740 * 2741 * Version field updates must be kept separate. This is because 2742 * kvm_write_guest_cached might use a "rep movs" instruction, and 2743 * writes within a string instruction are weakly ordered. So there 2744 * are three writes overall. 2745 * 2746 * As a small optimization, only write the version field in the first 2747 * and third write. The vcpu->pv_time cache is still valid, because the 2748 * version field is the first in the struct. 2749 */ 2750 BUILD_BUG_ON(offsetof(struct pvclock_vcpu_time_info, version) != 0); 2751 2752 if (guest_hv_clock.version & 1) 2753 ++guest_hv_clock.version; /* first time write, random junk */ 2754 2755 vcpu->hv_clock.version = guest_hv_clock.version + 1; 2756 kvm_write_guest_offset_cached(v->kvm, cache, 2757 &vcpu->hv_clock, offset, 2758 sizeof(vcpu->hv_clock.version)); 2759 2760 smp_wmb(); 2761 2762 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */ 2763 vcpu->hv_clock.flags |= (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED); 2764 2765 if (vcpu->pvclock_set_guest_stopped_request) { 2766 vcpu->hv_clock.flags |= PVCLOCK_GUEST_STOPPED; 2767 vcpu->pvclock_set_guest_stopped_request = false; 2768 } 2769 2770 trace_kvm_pvclock_update(v->vcpu_id, &vcpu->hv_clock); 2771 2772 kvm_write_guest_offset_cached(v->kvm, cache, 2773 &vcpu->hv_clock, offset, 2774 sizeof(vcpu->hv_clock)); 2775 2776 smp_wmb(); 2777 2778 vcpu->hv_clock.version++; 2779 kvm_write_guest_offset_cached(v->kvm, cache, 2780 &vcpu->hv_clock, offset, 2781 sizeof(vcpu->hv_clock.version)); 2782 } 2783 2784 static int kvm_guest_time_update(struct kvm_vcpu *v) 2785 { 2786 unsigned long flags, tgt_tsc_khz; 2787 struct kvm_vcpu_arch *vcpu = &v->arch; 2788 struct kvm_arch *ka = &v->kvm->arch; 2789 s64 kernel_ns; 2790 u64 tsc_timestamp, host_tsc; 2791 u8 pvclock_flags; 2792 bool use_master_clock; 2793 2794 kernel_ns = 0; 2795 host_tsc = 0; 2796 2797 /* 2798 * If the host uses TSC clock, then passthrough TSC as stable 2799 * to the guest. 2800 */ 2801 spin_lock_irqsave(&ka->pvclock_gtod_sync_lock, flags); 2802 use_master_clock = ka->use_master_clock; 2803 if (use_master_clock) { 2804 host_tsc = ka->master_cycle_now; 2805 kernel_ns = ka->master_kernel_ns; 2806 } 2807 spin_unlock_irqrestore(&ka->pvclock_gtod_sync_lock, flags); 2808 2809 /* Keep irq disabled to prevent changes to the clock */ 2810 local_irq_save(flags); 2811 tgt_tsc_khz = __this_cpu_read(cpu_tsc_khz); 2812 if (unlikely(tgt_tsc_khz == 0)) { 2813 local_irq_restore(flags); 2814 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v); 2815 return 1; 2816 } 2817 if (!use_master_clock) { 2818 host_tsc = rdtsc(); 2819 kernel_ns = get_kvmclock_base_ns(); 2820 } 2821 2822 tsc_timestamp = kvm_read_l1_tsc(v, host_tsc); 2823 2824 /* 2825 * We may have to catch up the TSC to match elapsed wall clock 2826 * time for two reasons, even if kvmclock is used. 2827 * 1) CPU could have been running below the maximum TSC rate 2828 * 2) Broken TSC compensation resets the base at each VCPU 2829 * entry to avoid unknown leaps of TSC even when running 2830 * again on the same CPU. This may cause apparent elapsed 2831 * time to disappear, and the guest to stand still or run 2832 * very slowly. 2833 */ 2834 if (vcpu->tsc_catchup) { 2835 u64 tsc = compute_guest_tsc(v, kernel_ns); 2836 if (tsc > tsc_timestamp) { 2837 adjust_tsc_offset_guest(v, tsc - tsc_timestamp); 2838 tsc_timestamp = tsc; 2839 } 2840 } 2841 2842 local_irq_restore(flags); 2843 2844 /* With all the info we got, fill in the values */ 2845 2846 if (kvm_has_tsc_control) 2847 tgt_tsc_khz = kvm_scale_tsc(v, tgt_tsc_khz); 2848 2849 if (unlikely(vcpu->hw_tsc_khz != tgt_tsc_khz)) { 2850 kvm_get_time_scale(NSEC_PER_SEC, tgt_tsc_khz * 1000LL, 2851 &vcpu->hv_clock.tsc_shift, 2852 &vcpu->hv_clock.tsc_to_system_mul); 2853 vcpu->hw_tsc_khz = tgt_tsc_khz; 2854 } 2855 2856 vcpu->hv_clock.tsc_timestamp = tsc_timestamp; 2857 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset; 2858 vcpu->last_guest_tsc = tsc_timestamp; 2859 2860 /* If the host uses TSC clocksource, then it is stable */ 2861 pvclock_flags = 0; 2862 if (use_master_clock) 2863 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT; 2864 2865 vcpu->hv_clock.flags = pvclock_flags; 2866 2867 if (vcpu->pv_time_enabled) 2868 kvm_setup_pvclock_page(v, &vcpu->pv_time, 0); 2869 if (vcpu->xen.vcpu_info_set) 2870 kvm_setup_pvclock_page(v, &vcpu->xen.vcpu_info_cache, 2871 offsetof(struct compat_vcpu_info, time)); 2872 if (vcpu->xen.vcpu_time_info_set) 2873 kvm_setup_pvclock_page(v, &vcpu->xen.vcpu_time_info_cache, 0); 2874 if (v == kvm_get_vcpu(v->kvm, 0)) 2875 kvm_hv_setup_tsc_page(v->kvm, &vcpu->hv_clock); 2876 return 0; 2877 } 2878 2879 /* 2880 * kvmclock updates which are isolated to a given vcpu, such as 2881 * vcpu->cpu migration, should not allow system_timestamp from 2882 * the rest of the vcpus to remain static. Otherwise ntp frequency 2883 * correction applies to one vcpu's system_timestamp but not 2884 * the others. 2885 * 2886 * So in those cases, request a kvmclock update for all vcpus. 2887 * We need to rate-limit these requests though, as they can 2888 * considerably slow guests that have a large number of vcpus. 2889 * The time for a remote vcpu to update its kvmclock is bound 2890 * by the delay we use to rate-limit the updates. 2891 */ 2892 2893 #define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100) 2894 2895 static void kvmclock_update_fn(struct work_struct *work) 2896 { 2897 int i; 2898 struct delayed_work *dwork = to_delayed_work(work); 2899 struct kvm_arch *ka = container_of(dwork, struct kvm_arch, 2900 kvmclock_update_work); 2901 struct kvm *kvm = container_of(ka, struct kvm, arch); 2902 struct kvm_vcpu *vcpu; 2903 2904 kvm_for_each_vcpu(i, vcpu, kvm) { 2905 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 2906 kvm_vcpu_kick(vcpu); 2907 } 2908 } 2909 2910 static void kvm_gen_kvmclock_update(struct kvm_vcpu *v) 2911 { 2912 struct kvm *kvm = v->kvm; 2913 2914 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v); 2915 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 2916 KVMCLOCK_UPDATE_DELAY); 2917 } 2918 2919 #define KVMCLOCK_SYNC_PERIOD (300 * HZ) 2920 2921 static void kvmclock_sync_fn(struct work_struct *work) 2922 { 2923 struct delayed_work *dwork = to_delayed_work(work); 2924 struct kvm_arch *ka = container_of(dwork, struct kvm_arch, 2925 kvmclock_sync_work); 2926 struct kvm *kvm = container_of(ka, struct kvm, arch); 2927 2928 if (!kvmclock_periodic_sync) 2929 return; 2930 2931 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0); 2932 schedule_delayed_work(&kvm->arch.kvmclock_sync_work, 2933 KVMCLOCK_SYNC_PERIOD); 2934 } 2935 2936 /* 2937 * On AMD, HWCR[McStatusWrEn] controls whether setting MCi_STATUS results in #GP. 2938 */ 2939 static bool can_set_mci_status(struct kvm_vcpu *vcpu) 2940 { 2941 /* McStatusWrEn enabled? */ 2942 if (guest_cpuid_is_amd_or_hygon(vcpu)) 2943 return !!(vcpu->arch.msr_hwcr & BIT_ULL(18)); 2944 2945 return false; 2946 } 2947 2948 static int set_msr_mce(struct kvm_vcpu *vcpu, struct msr_data *msr_info) 2949 { 2950 u64 mcg_cap = vcpu->arch.mcg_cap; 2951 unsigned bank_num = mcg_cap & 0xff; 2952 u32 msr = msr_info->index; 2953 u64 data = msr_info->data; 2954 2955 switch (msr) { 2956 case MSR_IA32_MCG_STATUS: 2957 vcpu->arch.mcg_status = data; 2958 break; 2959 case MSR_IA32_MCG_CTL: 2960 if (!(mcg_cap & MCG_CTL_P) && 2961 (data || !msr_info->host_initiated)) 2962 return 1; 2963 if (data != 0 && data != ~(u64)0) 2964 return 1; 2965 vcpu->arch.mcg_ctl = data; 2966 break; 2967 default: 2968 if (msr >= MSR_IA32_MC0_CTL && 2969 msr < MSR_IA32_MCx_CTL(bank_num)) { 2970 u32 offset = array_index_nospec( 2971 msr - MSR_IA32_MC0_CTL, 2972 MSR_IA32_MCx_CTL(bank_num) - MSR_IA32_MC0_CTL); 2973 2974 /* only 0 or all 1s can be written to IA32_MCi_CTL 2975 * some Linux kernels though clear bit 10 in bank 4 to 2976 * workaround a BIOS/GART TBL issue on AMD K8s, ignore 2977 * this to avoid an uncatched #GP in the guest 2978 */ 2979 if ((offset & 0x3) == 0 && 2980 data != 0 && (data | (1 << 10)) != ~(u64)0) 2981 return -1; 2982 2983 /* MCi_STATUS */ 2984 if (!msr_info->host_initiated && 2985 (offset & 0x3) == 1 && data != 0) { 2986 if (!can_set_mci_status(vcpu)) 2987 return -1; 2988 } 2989 2990 vcpu->arch.mce_banks[offset] = data; 2991 break; 2992 } 2993 return 1; 2994 } 2995 return 0; 2996 } 2997 2998 static inline bool kvm_pv_async_pf_enabled(struct kvm_vcpu *vcpu) 2999 { 3000 u64 mask = KVM_ASYNC_PF_ENABLED | KVM_ASYNC_PF_DELIVERY_AS_INT; 3001 3002 return (vcpu->arch.apf.msr_en_val & mask) == mask; 3003 } 3004 3005 static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data) 3006 { 3007 gpa_t gpa = data & ~0x3f; 3008 3009 /* Bits 4:5 are reserved, Should be zero */ 3010 if (data & 0x30) 3011 return 1; 3012 3013 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_VMEXIT) && 3014 (data & KVM_ASYNC_PF_DELIVERY_AS_PF_VMEXIT)) 3015 return 1; 3016 3017 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_INT) && 3018 (data & KVM_ASYNC_PF_DELIVERY_AS_INT)) 3019 return 1; 3020 3021 if (!lapic_in_kernel(vcpu)) 3022 return data ? 1 : 0; 3023 3024 vcpu->arch.apf.msr_en_val = data; 3025 3026 if (!kvm_pv_async_pf_enabled(vcpu)) { 3027 kvm_clear_async_pf_completion_queue(vcpu); 3028 kvm_async_pf_hash_reset(vcpu); 3029 return 0; 3030 } 3031 3032 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa, 3033 sizeof(u64))) 3034 return 1; 3035 3036 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS); 3037 vcpu->arch.apf.delivery_as_pf_vmexit = data & KVM_ASYNC_PF_DELIVERY_AS_PF_VMEXIT; 3038 3039 kvm_async_pf_wakeup_all(vcpu); 3040 3041 return 0; 3042 } 3043 3044 static int kvm_pv_enable_async_pf_int(struct kvm_vcpu *vcpu, u64 data) 3045 { 3046 /* Bits 8-63 are reserved */ 3047 if (data >> 8) 3048 return 1; 3049 3050 if (!lapic_in_kernel(vcpu)) 3051 return 1; 3052 3053 vcpu->arch.apf.msr_int_val = data; 3054 3055 vcpu->arch.apf.vec = data & KVM_ASYNC_PF_VEC_MASK; 3056 3057 return 0; 3058 } 3059 3060 static void kvmclock_reset(struct kvm_vcpu *vcpu) 3061 { 3062 vcpu->arch.pv_time_enabled = false; 3063 vcpu->arch.time = 0; 3064 } 3065 3066 static void kvm_vcpu_flush_tlb_all(struct kvm_vcpu *vcpu) 3067 { 3068 ++vcpu->stat.tlb_flush; 3069 static_call(kvm_x86_tlb_flush_all)(vcpu); 3070 } 3071 3072 static void kvm_vcpu_flush_tlb_guest(struct kvm_vcpu *vcpu) 3073 { 3074 ++vcpu->stat.tlb_flush; 3075 static_call(kvm_x86_tlb_flush_guest)(vcpu); 3076 } 3077 3078 static void record_steal_time(struct kvm_vcpu *vcpu) 3079 { 3080 struct kvm_host_map map; 3081 struct kvm_steal_time *st; 3082 3083 if (kvm_xen_msr_enabled(vcpu->kvm)) { 3084 kvm_xen_runstate_set_running(vcpu); 3085 return; 3086 } 3087 3088 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED)) 3089 return; 3090 3091 /* -EAGAIN is returned in atomic context so we can just return. */ 3092 if (kvm_map_gfn(vcpu, vcpu->arch.st.msr_val >> PAGE_SHIFT, 3093 &map, &vcpu->arch.st.cache, false)) 3094 return; 3095 3096 st = map.hva + 3097 offset_in_page(vcpu->arch.st.msr_val & KVM_STEAL_VALID_BITS); 3098 3099 /* 3100 * Doing a TLB flush here, on the guest's behalf, can avoid 3101 * expensive IPIs. 3102 */ 3103 if (guest_pv_has(vcpu, KVM_FEATURE_PV_TLB_FLUSH)) { 3104 trace_kvm_pv_tlb_flush(vcpu->vcpu_id, 3105 st->preempted & KVM_VCPU_FLUSH_TLB); 3106 if (xchg(&st->preempted, 0) & KVM_VCPU_FLUSH_TLB) 3107 kvm_vcpu_flush_tlb_guest(vcpu); 3108 } 3109 3110 vcpu->arch.st.preempted = 0; 3111 3112 if (st->version & 1) 3113 st->version += 1; /* first time write, random junk */ 3114 3115 st->version += 1; 3116 3117 smp_wmb(); 3118 3119 st->steal += current->sched_info.run_delay - 3120 vcpu->arch.st.last_steal; 3121 vcpu->arch.st.last_steal = current->sched_info.run_delay; 3122 3123 smp_wmb(); 3124 3125 st->version += 1; 3126 3127 kvm_unmap_gfn(vcpu, &map, &vcpu->arch.st.cache, true, false); 3128 } 3129 3130 int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info) 3131 { 3132 bool pr = false; 3133 u32 msr = msr_info->index; 3134 u64 data = msr_info->data; 3135 3136 if (msr && msr == vcpu->kvm->arch.xen_hvm_config.msr) 3137 return kvm_xen_write_hypercall_page(vcpu, data); 3138 3139 switch (msr) { 3140 case MSR_AMD64_NB_CFG: 3141 case MSR_IA32_UCODE_WRITE: 3142 case MSR_VM_HSAVE_PA: 3143 case MSR_AMD64_PATCH_LOADER: 3144 case MSR_AMD64_BU_CFG2: 3145 case MSR_AMD64_DC_CFG: 3146 case MSR_F15H_EX_CFG: 3147 break; 3148 3149 case MSR_IA32_UCODE_REV: 3150 if (msr_info->host_initiated) 3151 vcpu->arch.microcode_version = data; 3152 break; 3153 case MSR_IA32_ARCH_CAPABILITIES: 3154 if (!msr_info->host_initiated) 3155 return 1; 3156 vcpu->arch.arch_capabilities = data; 3157 break; 3158 case MSR_IA32_PERF_CAPABILITIES: { 3159 struct kvm_msr_entry msr_ent = {.index = msr, .data = 0}; 3160 3161 if (!msr_info->host_initiated) 3162 return 1; 3163 if (guest_cpuid_has(vcpu, X86_FEATURE_PDCM) && kvm_get_msr_feature(&msr_ent)) 3164 return 1; 3165 if (data & ~msr_ent.data) 3166 return 1; 3167 3168 vcpu->arch.perf_capabilities = data; 3169 3170 return 0; 3171 } 3172 case MSR_EFER: 3173 return set_efer(vcpu, msr_info); 3174 case MSR_K7_HWCR: 3175 data &= ~(u64)0x40; /* ignore flush filter disable */ 3176 data &= ~(u64)0x100; /* ignore ignne emulation enable */ 3177 data &= ~(u64)0x8; /* ignore TLB cache disable */ 3178 3179 /* Handle McStatusWrEn */ 3180 if (data == BIT_ULL(18)) { 3181 vcpu->arch.msr_hwcr = data; 3182 } else if (data != 0) { 3183 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n", 3184 data); 3185 return 1; 3186 } 3187 break; 3188 case MSR_FAM10H_MMIO_CONF_BASE: 3189 if (data != 0) { 3190 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: " 3191 "0x%llx\n", data); 3192 return 1; 3193 } 3194 break; 3195 case 0x200 ... 0x2ff: 3196 return kvm_mtrr_set_msr(vcpu, msr, data); 3197 case MSR_IA32_APICBASE: 3198 return kvm_set_apic_base(vcpu, msr_info); 3199 case APIC_BASE_MSR ... APIC_BASE_MSR + 0xff: 3200 return kvm_x2apic_msr_write(vcpu, msr, data); 3201 case MSR_IA32_TSC_DEADLINE: 3202 kvm_set_lapic_tscdeadline_msr(vcpu, data); 3203 break; 3204 case MSR_IA32_TSC_ADJUST: 3205 if (guest_cpuid_has(vcpu, X86_FEATURE_TSC_ADJUST)) { 3206 if (!msr_info->host_initiated) { 3207 s64 adj = data - vcpu->arch.ia32_tsc_adjust_msr; 3208 adjust_tsc_offset_guest(vcpu, adj); 3209 } 3210 vcpu->arch.ia32_tsc_adjust_msr = data; 3211 } 3212 break; 3213 case MSR_IA32_MISC_ENABLE: 3214 if (!kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_MISC_ENABLE_NO_MWAIT) && 3215 ((vcpu->arch.ia32_misc_enable_msr ^ data) & MSR_IA32_MISC_ENABLE_MWAIT)) { 3216 if (!guest_cpuid_has(vcpu, X86_FEATURE_XMM3)) 3217 return 1; 3218 vcpu->arch.ia32_misc_enable_msr = data; 3219 kvm_update_cpuid_runtime(vcpu); 3220 } else { 3221 vcpu->arch.ia32_misc_enable_msr = data; 3222 } 3223 break; 3224 case MSR_IA32_SMBASE: 3225 if (!msr_info->host_initiated) 3226 return 1; 3227 vcpu->arch.smbase = data; 3228 break; 3229 case MSR_IA32_POWER_CTL: 3230 vcpu->arch.msr_ia32_power_ctl = data; 3231 break; 3232 case MSR_IA32_TSC: 3233 if (msr_info->host_initiated) { 3234 kvm_synchronize_tsc(vcpu, data); 3235 } else { 3236 u64 adj = kvm_compute_tsc_offset(vcpu, data) - vcpu->arch.l1_tsc_offset; 3237 adjust_tsc_offset_guest(vcpu, adj); 3238 vcpu->arch.ia32_tsc_adjust_msr += adj; 3239 } 3240 break; 3241 case MSR_IA32_XSS: 3242 if (!msr_info->host_initiated && 3243 !guest_cpuid_has(vcpu, X86_FEATURE_XSAVES)) 3244 return 1; 3245 /* 3246 * KVM supports exposing PT to the guest, but does not support 3247 * IA32_XSS[bit 8]. Guests have to use RDMSR/WRMSR rather than 3248 * XSAVES/XRSTORS to save/restore PT MSRs. 3249 */ 3250 if (data & ~supported_xss) 3251 return 1; 3252 vcpu->arch.ia32_xss = data; 3253 break; 3254 case MSR_SMI_COUNT: 3255 if (!msr_info->host_initiated) 3256 return 1; 3257 vcpu->arch.smi_count = data; 3258 break; 3259 case MSR_KVM_WALL_CLOCK_NEW: 3260 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE2)) 3261 return 1; 3262 3263 vcpu->kvm->arch.wall_clock = data; 3264 kvm_write_wall_clock(vcpu->kvm, data, 0); 3265 break; 3266 case MSR_KVM_WALL_CLOCK: 3267 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE)) 3268 return 1; 3269 3270 vcpu->kvm->arch.wall_clock = data; 3271 kvm_write_wall_clock(vcpu->kvm, data, 0); 3272 break; 3273 case MSR_KVM_SYSTEM_TIME_NEW: 3274 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE2)) 3275 return 1; 3276 3277 kvm_write_system_time(vcpu, data, false, msr_info->host_initiated); 3278 break; 3279 case MSR_KVM_SYSTEM_TIME: 3280 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE)) 3281 return 1; 3282 3283 kvm_write_system_time(vcpu, data, true, msr_info->host_initiated); 3284 break; 3285 case MSR_KVM_ASYNC_PF_EN: 3286 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF)) 3287 return 1; 3288 3289 if (kvm_pv_enable_async_pf(vcpu, data)) 3290 return 1; 3291 break; 3292 case MSR_KVM_ASYNC_PF_INT: 3293 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_INT)) 3294 return 1; 3295 3296 if (kvm_pv_enable_async_pf_int(vcpu, data)) 3297 return 1; 3298 break; 3299 case MSR_KVM_ASYNC_PF_ACK: 3300 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF)) 3301 return 1; 3302 if (data & 0x1) { 3303 vcpu->arch.apf.pageready_pending = false; 3304 kvm_check_async_pf_completion(vcpu); 3305 } 3306 break; 3307 case MSR_KVM_STEAL_TIME: 3308 if (!guest_pv_has(vcpu, KVM_FEATURE_STEAL_TIME)) 3309 return 1; 3310 3311 if (unlikely(!sched_info_on())) 3312 return 1; 3313 3314 if (data & KVM_STEAL_RESERVED_MASK) 3315 return 1; 3316 3317 vcpu->arch.st.msr_val = data; 3318 3319 if (!(data & KVM_MSR_ENABLED)) 3320 break; 3321 3322 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu); 3323 3324 break; 3325 case MSR_KVM_PV_EOI_EN: 3326 if (!guest_pv_has(vcpu, KVM_FEATURE_PV_EOI)) 3327 return 1; 3328 3329 if (kvm_lapic_enable_pv_eoi(vcpu, data, sizeof(u8))) 3330 return 1; 3331 break; 3332 3333 case MSR_KVM_POLL_CONTROL: 3334 if (!guest_pv_has(vcpu, KVM_FEATURE_POLL_CONTROL)) 3335 return 1; 3336 3337 /* only enable bit supported */ 3338 if (data & (-1ULL << 1)) 3339 return 1; 3340 3341 vcpu->arch.msr_kvm_poll_control = data; 3342 break; 3343 3344 case MSR_IA32_MCG_CTL: 3345 case MSR_IA32_MCG_STATUS: 3346 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1: 3347 return set_msr_mce(vcpu, msr_info); 3348 3349 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3: 3350 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1: 3351 pr = true; 3352 fallthrough; 3353 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3: 3354 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1: 3355 if (kvm_pmu_is_valid_msr(vcpu, msr)) 3356 return kvm_pmu_set_msr(vcpu, msr_info); 3357 3358 if (pr || data != 0) 3359 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: " 3360 "0x%x data 0x%llx\n", msr, data); 3361 break; 3362 case MSR_K7_CLK_CTL: 3363 /* 3364 * Ignore all writes to this no longer documented MSR. 3365 * Writes are only relevant for old K7 processors, 3366 * all pre-dating SVM, but a recommended workaround from 3367 * AMD for these chips. It is possible to specify the 3368 * affected processor models on the command line, hence 3369 * the need to ignore the workaround. 3370 */ 3371 break; 3372 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15: 3373 case HV_X64_MSR_SYNDBG_CONTROL ... HV_X64_MSR_SYNDBG_PENDING_BUFFER: 3374 case HV_X64_MSR_SYNDBG_OPTIONS: 3375 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4: 3376 case HV_X64_MSR_CRASH_CTL: 3377 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT: 3378 case HV_X64_MSR_REENLIGHTENMENT_CONTROL: 3379 case HV_X64_MSR_TSC_EMULATION_CONTROL: 3380 case HV_X64_MSR_TSC_EMULATION_STATUS: 3381 return kvm_hv_set_msr_common(vcpu, msr, data, 3382 msr_info->host_initiated); 3383 case MSR_IA32_BBL_CR_CTL3: 3384 /* Drop writes to this legacy MSR -- see rdmsr 3385 * counterpart for further detail. 3386 */ 3387 if (report_ignored_msrs) 3388 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data 0x%llx\n", 3389 msr, data); 3390 break; 3391 case MSR_AMD64_OSVW_ID_LENGTH: 3392 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW)) 3393 return 1; 3394 vcpu->arch.osvw.length = data; 3395 break; 3396 case MSR_AMD64_OSVW_STATUS: 3397 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW)) 3398 return 1; 3399 vcpu->arch.osvw.status = data; 3400 break; 3401 case MSR_PLATFORM_INFO: 3402 if (!msr_info->host_initiated || 3403 (!(data & MSR_PLATFORM_INFO_CPUID_FAULT) && 3404 cpuid_fault_enabled(vcpu))) 3405 return 1; 3406 vcpu->arch.msr_platform_info = data; 3407 break; 3408 case MSR_MISC_FEATURES_ENABLES: 3409 if (data & ~MSR_MISC_FEATURES_ENABLES_CPUID_FAULT || 3410 (data & MSR_MISC_FEATURES_ENABLES_CPUID_FAULT && 3411 !supports_cpuid_fault(vcpu))) 3412 return 1; 3413 vcpu->arch.msr_misc_features_enables = data; 3414 break; 3415 default: 3416 if (kvm_pmu_is_valid_msr(vcpu, msr)) 3417 return kvm_pmu_set_msr(vcpu, msr_info); 3418 return KVM_MSR_RET_INVALID; 3419 } 3420 return 0; 3421 } 3422 EXPORT_SYMBOL_GPL(kvm_set_msr_common); 3423 3424 static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata, bool host) 3425 { 3426 u64 data; 3427 u64 mcg_cap = vcpu->arch.mcg_cap; 3428 unsigned bank_num = mcg_cap & 0xff; 3429 3430 switch (msr) { 3431 case MSR_IA32_P5_MC_ADDR: 3432 case MSR_IA32_P5_MC_TYPE: 3433 data = 0; 3434 break; 3435 case MSR_IA32_MCG_CAP: 3436 data = vcpu->arch.mcg_cap; 3437 break; 3438 case MSR_IA32_MCG_CTL: 3439 if (!(mcg_cap & MCG_CTL_P) && !host) 3440 return 1; 3441 data = vcpu->arch.mcg_ctl; 3442 break; 3443 case MSR_IA32_MCG_STATUS: 3444 data = vcpu->arch.mcg_status; 3445 break; 3446 default: 3447 if (msr >= MSR_IA32_MC0_CTL && 3448 msr < MSR_IA32_MCx_CTL(bank_num)) { 3449 u32 offset = array_index_nospec( 3450 msr - MSR_IA32_MC0_CTL, 3451 MSR_IA32_MCx_CTL(bank_num) - MSR_IA32_MC0_CTL); 3452 3453 data = vcpu->arch.mce_banks[offset]; 3454 break; 3455 } 3456 return 1; 3457 } 3458 *pdata = data; 3459 return 0; 3460 } 3461 3462 int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info) 3463 { 3464 switch (msr_info->index) { 3465 case MSR_IA32_PLATFORM_ID: 3466 case MSR_IA32_EBL_CR_POWERON: 3467 case MSR_IA32_LASTBRANCHFROMIP: 3468 case MSR_IA32_LASTBRANCHTOIP: 3469 case MSR_IA32_LASTINTFROMIP: 3470 case MSR_IA32_LASTINTTOIP: 3471 case MSR_AMD64_SYSCFG: 3472 case MSR_K8_TSEG_ADDR: 3473 case MSR_K8_TSEG_MASK: 3474 case MSR_VM_HSAVE_PA: 3475 case MSR_K8_INT_PENDING_MSG: 3476 case MSR_AMD64_NB_CFG: 3477 case MSR_FAM10H_MMIO_CONF_BASE: 3478 case MSR_AMD64_BU_CFG2: 3479 case MSR_IA32_PERF_CTL: 3480 case MSR_AMD64_DC_CFG: 3481 case MSR_F15H_EX_CFG: 3482 /* 3483 * Intel Sandy Bridge CPUs must support the RAPL (running average power 3484 * limit) MSRs. Just return 0, as we do not want to expose the host 3485 * data here. Do not conditionalize this on CPUID, as KVM does not do 3486 * so for existing CPU-specific MSRs. 3487 */ 3488 case MSR_RAPL_POWER_UNIT: 3489 case MSR_PP0_ENERGY_STATUS: /* Power plane 0 (core) */ 3490 case MSR_PP1_ENERGY_STATUS: /* Power plane 1 (graphics uncore) */ 3491 case MSR_PKG_ENERGY_STATUS: /* Total package */ 3492 case MSR_DRAM_ENERGY_STATUS: /* DRAM controller */ 3493 msr_info->data = 0; 3494 break; 3495 case MSR_F15H_PERF_CTL0 ... MSR_F15H_PERF_CTR5: 3496 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index)) 3497 return kvm_pmu_get_msr(vcpu, msr_info); 3498 if (!msr_info->host_initiated) 3499 return 1; 3500 msr_info->data = 0; 3501 break; 3502 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3: 3503 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3: 3504 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1: 3505 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1: 3506 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index)) 3507 return kvm_pmu_get_msr(vcpu, msr_info); 3508 msr_info->data = 0; 3509 break; 3510 case MSR_IA32_UCODE_REV: 3511 msr_info->data = vcpu->arch.microcode_version; 3512 break; 3513 case MSR_IA32_ARCH_CAPABILITIES: 3514 if (!msr_info->host_initiated && 3515 !guest_cpuid_has(vcpu, X86_FEATURE_ARCH_CAPABILITIES)) 3516 return 1; 3517 msr_info->data = vcpu->arch.arch_capabilities; 3518 break; 3519 case MSR_IA32_PERF_CAPABILITIES: 3520 if (!msr_info->host_initiated && 3521 !guest_cpuid_has(vcpu, X86_FEATURE_PDCM)) 3522 return 1; 3523 msr_info->data = vcpu->arch.perf_capabilities; 3524 break; 3525 case MSR_IA32_POWER_CTL: 3526 msr_info->data = vcpu->arch.msr_ia32_power_ctl; 3527 break; 3528 case MSR_IA32_TSC: { 3529 /* 3530 * Intel SDM states that MSR_IA32_TSC read adds the TSC offset 3531 * even when not intercepted. AMD manual doesn't explicitly 3532 * state this but appears to behave the same. 3533 * 3534 * On userspace reads and writes, however, we unconditionally 3535 * return L1's TSC value to ensure backwards-compatible 3536 * behavior for migration. 3537 */ 3538 u64 tsc_offset = msr_info->host_initiated ? vcpu->arch.l1_tsc_offset : 3539 vcpu->arch.tsc_offset; 3540 3541 msr_info->data = kvm_scale_tsc(vcpu, rdtsc()) + tsc_offset; 3542 break; 3543 } 3544 case MSR_MTRRcap: 3545 case 0x200 ... 0x2ff: 3546 return kvm_mtrr_get_msr(vcpu, msr_info->index, &msr_info->data); 3547 case 0xcd: /* fsb frequency */ 3548 msr_info->data = 3; 3549 break; 3550 /* 3551 * MSR_EBC_FREQUENCY_ID 3552 * Conservative value valid for even the basic CPU models. 3553 * Models 0,1: 000 in bits 23:21 indicating a bus speed of 3554 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz, 3555 * and 266MHz for model 3, or 4. Set Core Clock 3556 * Frequency to System Bus Frequency Ratio to 1 (bits 3557 * 31:24) even though these are only valid for CPU 3558 * models > 2, however guests may end up dividing or 3559 * multiplying by zero otherwise. 3560 */ 3561 case MSR_EBC_FREQUENCY_ID: 3562 msr_info->data = 1 << 24; 3563 break; 3564 case MSR_IA32_APICBASE: 3565 msr_info->data = kvm_get_apic_base(vcpu); 3566 break; 3567 case APIC_BASE_MSR ... APIC_BASE_MSR + 0xff: 3568 return kvm_x2apic_msr_read(vcpu, msr_info->index, &msr_info->data); 3569 case MSR_IA32_TSC_DEADLINE: 3570 msr_info->data = kvm_get_lapic_tscdeadline_msr(vcpu); 3571 break; 3572 case MSR_IA32_TSC_ADJUST: 3573 msr_info->data = (u64)vcpu->arch.ia32_tsc_adjust_msr; 3574 break; 3575 case MSR_IA32_MISC_ENABLE: 3576 msr_info->data = vcpu->arch.ia32_misc_enable_msr; 3577 break; 3578 case MSR_IA32_SMBASE: 3579 if (!msr_info->host_initiated) 3580 return 1; 3581 msr_info->data = vcpu->arch.smbase; 3582 break; 3583 case MSR_SMI_COUNT: 3584 msr_info->data = vcpu->arch.smi_count; 3585 break; 3586 case MSR_IA32_PERF_STATUS: 3587 /* TSC increment by tick */ 3588 msr_info->data = 1000ULL; 3589 /* CPU multiplier */ 3590 msr_info->data |= (((uint64_t)4ULL) << 40); 3591 break; 3592 case MSR_EFER: 3593 msr_info->data = vcpu->arch.efer; 3594 break; 3595 case MSR_KVM_WALL_CLOCK: 3596 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE)) 3597 return 1; 3598 3599 msr_info->data = vcpu->kvm->arch.wall_clock; 3600 break; 3601 case MSR_KVM_WALL_CLOCK_NEW: 3602 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE2)) 3603 return 1; 3604 3605 msr_info->data = vcpu->kvm->arch.wall_clock; 3606 break; 3607 case MSR_KVM_SYSTEM_TIME: 3608 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE)) 3609 return 1; 3610 3611 msr_info->data = vcpu->arch.time; 3612 break; 3613 case MSR_KVM_SYSTEM_TIME_NEW: 3614 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE2)) 3615 return 1; 3616 3617 msr_info->data = vcpu->arch.time; 3618 break; 3619 case MSR_KVM_ASYNC_PF_EN: 3620 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF)) 3621 return 1; 3622 3623 msr_info->data = vcpu->arch.apf.msr_en_val; 3624 break; 3625 case MSR_KVM_ASYNC_PF_INT: 3626 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_INT)) 3627 return 1; 3628 3629 msr_info->data = vcpu->arch.apf.msr_int_val; 3630 break; 3631 case MSR_KVM_ASYNC_PF_ACK: 3632 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF)) 3633 return 1; 3634 3635 msr_info->data = 0; 3636 break; 3637 case MSR_KVM_STEAL_TIME: 3638 if (!guest_pv_has(vcpu, KVM_FEATURE_STEAL_TIME)) 3639 return 1; 3640 3641 msr_info->data = vcpu->arch.st.msr_val; 3642 break; 3643 case MSR_KVM_PV_EOI_EN: 3644 if (!guest_pv_has(vcpu, KVM_FEATURE_PV_EOI)) 3645 return 1; 3646 3647 msr_info->data = vcpu->arch.pv_eoi.msr_val; 3648 break; 3649 case MSR_KVM_POLL_CONTROL: 3650 if (!guest_pv_has(vcpu, KVM_FEATURE_POLL_CONTROL)) 3651 return 1; 3652 3653 msr_info->data = vcpu->arch.msr_kvm_poll_control; 3654 break; 3655 case MSR_IA32_P5_MC_ADDR: 3656 case MSR_IA32_P5_MC_TYPE: 3657 case MSR_IA32_MCG_CAP: 3658 case MSR_IA32_MCG_CTL: 3659 case MSR_IA32_MCG_STATUS: 3660 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1: 3661 return get_msr_mce(vcpu, msr_info->index, &msr_info->data, 3662 msr_info->host_initiated); 3663 case MSR_IA32_XSS: 3664 if (!msr_info->host_initiated && 3665 !guest_cpuid_has(vcpu, X86_FEATURE_XSAVES)) 3666 return 1; 3667 msr_info->data = vcpu->arch.ia32_xss; 3668 break; 3669 case MSR_K7_CLK_CTL: 3670 /* 3671 * Provide expected ramp-up count for K7. All other 3672 * are set to zero, indicating minimum divisors for 3673 * every field. 3674 * 3675 * This prevents guest kernels on AMD host with CPU 3676 * type 6, model 8 and higher from exploding due to 3677 * the rdmsr failing. 3678 */ 3679 msr_info->data = 0x20000000; 3680 break; 3681 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15: 3682 case HV_X64_MSR_SYNDBG_CONTROL ... HV_X64_MSR_SYNDBG_PENDING_BUFFER: 3683 case HV_X64_MSR_SYNDBG_OPTIONS: 3684 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4: 3685 case HV_X64_MSR_CRASH_CTL: 3686 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT: 3687 case HV_X64_MSR_REENLIGHTENMENT_CONTROL: 3688 case HV_X64_MSR_TSC_EMULATION_CONTROL: 3689 case HV_X64_MSR_TSC_EMULATION_STATUS: 3690 return kvm_hv_get_msr_common(vcpu, 3691 msr_info->index, &msr_info->data, 3692 msr_info->host_initiated); 3693 case MSR_IA32_BBL_CR_CTL3: 3694 /* This legacy MSR exists but isn't fully documented in current 3695 * silicon. It is however accessed by winxp in very narrow 3696 * scenarios where it sets bit #19, itself documented as 3697 * a "reserved" bit. Best effort attempt to source coherent 3698 * read data here should the balance of the register be 3699 * interpreted by the guest: 3700 * 3701 * L2 cache control register 3: 64GB range, 256KB size, 3702 * enabled, latency 0x1, configured 3703 */ 3704 msr_info->data = 0xbe702111; 3705 break; 3706 case MSR_AMD64_OSVW_ID_LENGTH: 3707 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW)) 3708 return 1; 3709 msr_info->data = vcpu->arch.osvw.length; 3710 break; 3711 case MSR_AMD64_OSVW_STATUS: 3712 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW)) 3713 return 1; 3714 msr_info->data = vcpu->arch.osvw.status; 3715 break; 3716 case MSR_PLATFORM_INFO: 3717 if (!msr_info->host_initiated && 3718 !vcpu->kvm->arch.guest_can_read_msr_platform_info) 3719 return 1; 3720 msr_info->data = vcpu->arch.msr_platform_info; 3721 break; 3722 case MSR_MISC_FEATURES_ENABLES: 3723 msr_info->data = vcpu->arch.msr_misc_features_enables; 3724 break; 3725 case MSR_K7_HWCR: 3726 msr_info->data = vcpu->arch.msr_hwcr; 3727 break; 3728 default: 3729 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index)) 3730 return kvm_pmu_get_msr(vcpu, msr_info); 3731 return KVM_MSR_RET_INVALID; 3732 } 3733 return 0; 3734 } 3735 EXPORT_SYMBOL_GPL(kvm_get_msr_common); 3736 3737 /* 3738 * Read or write a bunch of msrs. All parameters are kernel addresses. 3739 * 3740 * @return number of msrs set successfully. 3741 */ 3742 static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs, 3743 struct kvm_msr_entry *entries, 3744 int (*do_msr)(struct kvm_vcpu *vcpu, 3745 unsigned index, u64 *data)) 3746 { 3747 int i; 3748 3749 for (i = 0; i < msrs->nmsrs; ++i) 3750 if (do_msr(vcpu, entries[i].index, &entries[i].data)) 3751 break; 3752 3753 return i; 3754 } 3755 3756 /* 3757 * Read or write a bunch of msrs. Parameters are user addresses. 3758 * 3759 * @return number of msrs set successfully. 3760 */ 3761 static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs, 3762 int (*do_msr)(struct kvm_vcpu *vcpu, 3763 unsigned index, u64 *data), 3764 int writeback) 3765 { 3766 struct kvm_msrs msrs; 3767 struct kvm_msr_entry *entries; 3768 int r, n; 3769 unsigned size; 3770 3771 r = -EFAULT; 3772 if (copy_from_user(&msrs, user_msrs, sizeof(msrs))) 3773 goto out; 3774 3775 r = -E2BIG; 3776 if (msrs.nmsrs >= MAX_IO_MSRS) 3777 goto out; 3778 3779 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs; 3780 entries = memdup_user(user_msrs->entries, size); 3781 if (IS_ERR(entries)) { 3782 r = PTR_ERR(entries); 3783 goto out; 3784 } 3785 3786 r = n = __msr_io(vcpu, &msrs, entries, do_msr); 3787 if (r < 0) 3788 goto out_free; 3789 3790 r = -EFAULT; 3791 if (writeback && copy_to_user(user_msrs->entries, entries, size)) 3792 goto out_free; 3793 3794 r = n; 3795 3796 out_free: 3797 kfree(entries); 3798 out: 3799 return r; 3800 } 3801 3802 static inline bool kvm_can_mwait_in_guest(void) 3803 { 3804 return boot_cpu_has(X86_FEATURE_MWAIT) && 3805 !boot_cpu_has_bug(X86_BUG_MONITOR) && 3806 boot_cpu_has(X86_FEATURE_ARAT); 3807 } 3808 3809 static int kvm_ioctl_get_supported_hv_cpuid(struct kvm_vcpu *vcpu, 3810 struct kvm_cpuid2 __user *cpuid_arg) 3811 { 3812 struct kvm_cpuid2 cpuid; 3813 int r; 3814 3815 r = -EFAULT; 3816 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid))) 3817 return r; 3818 3819 r = kvm_get_hv_cpuid(vcpu, &cpuid, cpuid_arg->entries); 3820 if (r) 3821 return r; 3822 3823 r = -EFAULT; 3824 if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid))) 3825 return r; 3826 3827 return 0; 3828 } 3829 3830 int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext) 3831 { 3832 int r = 0; 3833 3834 switch (ext) { 3835 case KVM_CAP_IRQCHIP: 3836 case KVM_CAP_HLT: 3837 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL: 3838 case KVM_CAP_SET_TSS_ADDR: 3839 case KVM_CAP_EXT_CPUID: 3840 case KVM_CAP_EXT_EMUL_CPUID: 3841 case KVM_CAP_CLOCKSOURCE: 3842 case KVM_CAP_PIT: 3843 case KVM_CAP_NOP_IO_DELAY: 3844 case KVM_CAP_MP_STATE: 3845 case KVM_CAP_SYNC_MMU: 3846 case KVM_CAP_USER_NMI: 3847 case KVM_CAP_REINJECT_CONTROL: 3848 case KVM_CAP_IRQ_INJECT_STATUS: 3849 case KVM_CAP_IOEVENTFD: 3850 case KVM_CAP_IOEVENTFD_NO_LENGTH: 3851 case KVM_CAP_PIT2: 3852 case KVM_CAP_PIT_STATE2: 3853 case KVM_CAP_SET_IDENTITY_MAP_ADDR: 3854 case KVM_CAP_VCPU_EVENTS: 3855 case KVM_CAP_HYPERV: 3856 case KVM_CAP_HYPERV_VAPIC: 3857 case KVM_CAP_HYPERV_SPIN: 3858 case KVM_CAP_HYPERV_SYNIC: 3859 case KVM_CAP_HYPERV_SYNIC2: 3860 case KVM_CAP_HYPERV_VP_INDEX: 3861 case KVM_CAP_HYPERV_EVENTFD: 3862 case KVM_CAP_HYPERV_TLBFLUSH: 3863 case KVM_CAP_HYPERV_SEND_IPI: 3864 case KVM_CAP_HYPERV_CPUID: 3865 case KVM_CAP_SYS_HYPERV_CPUID: 3866 case KVM_CAP_PCI_SEGMENT: 3867 case KVM_CAP_DEBUGREGS: 3868 case KVM_CAP_X86_ROBUST_SINGLESTEP: 3869 case KVM_CAP_XSAVE: 3870 case KVM_CAP_ASYNC_PF: 3871 case KVM_CAP_ASYNC_PF_INT: 3872 case KVM_CAP_GET_TSC_KHZ: 3873 case KVM_CAP_KVMCLOCK_CTRL: 3874 case KVM_CAP_READONLY_MEM: 3875 case KVM_CAP_HYPERV_TIME: 3876 case KVM_CAP_IOAPIC_POLARITY_IGNORED: 3877 case KVM_CAP_TSC_DEADLINE_TIMER: 3878 case KVM_CAP_DISABLE_QUIRKS: 3879 case KVM_CAP_SET_BOOT_CPU_ID: 3880 case KVM_CAP_SPLIT_IRQCHIP: 3881 case KVM_CAP_IMMEDIATE_EXIT: 3882 case KVM_CAP_PMU_EVENT_FILTER: 3883 case KVM_CAP_GET_MSR_FEATURES: 3884 case KVM_CAP_MSR_PLATFORM_INFO: 3885 case KVM_CAP_EXCEPTION_PAYLOAD: 3886 case KVM_CAP_SET_GUEST_DEBUG: 3887 case KVM_CAP_LAST_CPU: 3888 case KVM_CAP_X86_USER_SPACE_MSR: 3889 case KVM_CAP_X86_MSR_FILTER: 3890 case KVM_CAP_ENFORCE_PV_FEATURE_CPUID: 3891 #ifdef CONFIG_X86_SGX_KVM 3892 case KVM_CAP_SGX_ATTRIBUTE: 3893 #endif 3894 case KVM_CAP_VM_COPY_ENC_CONTEXT_FROM: 3895 r = 1; 3896 break; 3897 case KVM_CAP_SET_GUEST_DEBUG2: 3898 return KVM_GUESTDBG_VALID_MASK; 3899 #ifdef CONFIG_KVM_XEN 3900 case KVM_CAP_XEN_HVM: 3901 r = KVM_XEN_HVM_CONFIG_HYPERCALL_MSR | 3902 KVM_XEN_HVM_CONFIG_INTERCEPT_HCALL | 3903 KVM_XEN_HVM_CONFIG_SHARED_INFO; 3904 if (sched_info_on()) 3905 r |= KVM_XEN_HVM_CONFIG_RUNSTATE; 3906 break; 3907 #endif 3908 case KVM_CAP_SYNC_REGS: 3909 r = KVM_SYNC_X86_VALID_FIELDS; 3910 break; 3911 case KVM_CAP_ADJUST_CLOCK: 3912 r = KVM_CLOCK_TSC_STABLE; 3913 break; 3914 case KVM_CAP_X86_DISABLE_EXITS: 3915 r |= KVM_X86_DISABLE_EXITS_HLT | KVM_X86_DISABLE_EXITS_PAUSE | 3916 KVM_X86_DISABLE_EXITS_CSTATE; 3917 if(kvm_can_mwait_in_guest()) 3918 r |= KVM_X86_DISABLE_EXITS_MWAIT; 3919 break; 3920 case KVM_CAP_X86_SMM: 3921 /* SMBASE is usually relocated above 1M on modern chipsets, 3922 * and SMM handlers might indeed rely on 4G segment limits, 3923 * so do not report SMM to be available if real mode is 3924 * emulated via vm86 mode. Still, do not go to great lengths 3925 * to avoid userspace's usage of the feature, because it is a 3926 * fringe case that is not enabled except via specific settings 3927 * of the module parameters. 3928 */ 3929 r = static_call(kvm_x86_has_emulated_msr)(kvm, MSR_IA32_SMBASE); 3930 break; 3931 case KVM_CAP_VAPIC: 3932 r = !static_call(kvm_x86_cpu_has_accelerated_tpr)(); 3933 break; 3934 case KVM_CAP_NR_VCPUS: 3935 r = KVM_SOFT_MAX_VCPUS; 3936 break; 3937 case KVM_CAP_MAX_VCPUS: 3938 r = KVM_MAX_VCPUS; 3939 break; 3940 case KVM_CAP_MAX_VCPU_ID: 3941 r = KVM_MAX_VCPU_ID; 3942 break; 3943 case KVM_CAP_PV_MMU: /* obsolete */ 3944 r = 0; 3945 break; 3946 case KVM_CAP_MCE: 3947 r = KVM_MAX_MCE_BANKS; 3948 break; 3949 case KVM_CAP_XCRS: 3950 r = boot_cpu_has(X86_FEATURE_XSAVE); 3951 break; 3952 case KVM_CAP_TSC_CONTROL: 3953 r = kvm_has_tsc_control; 3954 break; 3955 case KVM_CAP_X2APIC_API: 3956 r = KVM_X2APIC_API_VALID_FLAGS; 3957 break; 3958 case KVM_CAP_NESTED_STATE: 3959 r = kvm_x86_ops.nested_ops->get_state ? 3960 kvm_x86_ops.nested_ops->get_state(NULL, NULL, 0) : 0; 3961 break; 3962 case KVM_CAP_HYPERV_DIRECT_TLBFLUSH: 3963 r = kvm_x86_ops.enable_direct_tlbflush != NULL; 3964 break; 3965 case KVM_CAP_HYPERV_ENLIGHTENED_VMCS: 3966 r = kvm_x86_ops.nested_ops->enable_evmcs != NULL; 3967 break; 3968 case KVM_CAP_SMALLER_MAXPHYADDR: 3969 r = (int) allow_smaller_maxphyaddr; 3970 break; 3971 case KVM_CAP_STEAL_TIME: 3972 r = sched_info_on(); 3973 break; 3974 case KVM_CAP_X86_BUS_LOCK_EXIT: 3975 if (kvm_has_bus_lock_exit) 3976 r = KVM_BUS_LOCK_DETECTION_OFF | 3977 KVM_BUS_LOCK_DETECTION_EXIT; 3978 else 3979 r = 0; 3980 break; 3981 default: 3982 break; 3983 } 3984 return r; 3985 3986 } 3987 3988 long kvm_arch_dev_ioctl(struct file *filp, 3989 unsigned int ioctl, unsigned long arg) 3990 { 3991 void __user *argp = (void __user *)arg; 3992 long r; 3993 3994 switch (ioctl) { 3995 case KVM_GET_MSR_INDEX_LIST: { 3996 struct kvm_msr_list __user *user_msr_list = argp; 3997 struct kvm_msr_list msr_list; 3998 unsigned n; 3999 4000 r = -EFAULT; 4001 if (copy_from_user(&msr_list, user_msr_list, sizeof(msr_list))) 4002 goto out; 4003 n = msr_list.nmsrs; 4004 msr_list.nmsrs = num_msrs_to_save + num_emulated_msrs; 4005 if (copy_to_user(user_msr_list, &msr_list, sizeof(msr_list))) 4006 goto out; 4007 r = -E2BIG; 4008 if (n < msr_list.nmsrs) 4009 goto out; 4010 r = -EFAULT; 4011 if (copy_to_user(user_msr_list->indices, &msrs_to_save, 4012 num_msrs_to_save * sizeof(u32))) 4013 goto out; 4014 if (copy_to_user(user_msr_list->indices + num_msrs_to_save, 4015 &emulated_msrs, 4016 num_emulated_msrs * sizeof(u32))) 4017 goto out; 4018 r = 0; 4019 break; 4020 } 4021 case KVM_GET_SUPPORTED_CPUID: 4022 case KVM_GET_EMULATED_CPUID: { 4023 struct kvm_cpuid2 __user *cpuid_arg = argp; 4024 struct kvm_cpuid2 cpuid; 4025 4026 r = -EFAULT; 4027 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid))) 4028 goto out; 4029 4030 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries, 4031 ioctl); 4032 if (r) 4033 goto out; 4034 4035 r = -EFAULT; 4036 if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid))) 4037 goto out; 4038 r = 0; 4039 break; 4040 } 4041 case KVM_X86_GET_MCE_CAP_SUPPORTED: 4042 r = -EFAULT; 4043 if (copy_to_user(argp, &kvm_mce_cap_supported, 4044 sizeof(kvm_mce_cap_supported))) 4045 goto out; 4046 r = 0; 4047 break; 4048 case KVM_GET_MSR_FEATURE_INDEX_LIST: { 4049 struct kvm_msr_list __user *user_msr_list = argp; 4050 struct kvm_msr_list msr_list; 4051 unsigned int n; 4052 4053 r = -EFAULT; 4054 if (copy_from_user(&msr_list, user_msr_list, sizeof(msr_list))) 4055 goto out; 4056 n = msr_list.nmsrs; 4057 msr_list.nmsrs = num_msr_based_features; 4058 if (copy_to_user(user_msr_list, &msr_list, sizeof(msr_list))) 4059 goto out; 4060 r = -E2BIG; 4061 if (n < msr_list.nmsrs) 4062 goto out; 4063 r = -EFAULT; 4064 if (copy_to_user(user_msr_list->indices, &msr_based_features, 4065 num_msr_based_features * sizeof(u32))) 4066 goto out; 4067 r = 0; 4068 break; 4069 } 4070 case KVM_GET_MSRS: 4071 r = msr_io(NULL, argp, do_get_msr_feature, 1); 4072 break; 4073 case KVM_GET_SUPPORTED_HV_CPUID: 4074 r = kvm_ioctl_get_supported_hv_cpuid(NULL, argp); 4075 break; 4076 default: 4077 r = -EINVAL; 4078 break; 4079 } 4080 out: 4081 return r; 4082 } 4083 4084 static void wbinvd_ipi(void *garbage) 4085 { 4086 wbinvd(); 4087 } 4088 4089 static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu) 4090 { 4091 return kvm_arch_has_noncoherent_dma(vcpu->kvm); 4092 } 4093 4094 void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu) 4095 { 4096 /* Address WBINVD may be executed by guest */ 4097 if (need_emulate_wbinvd(vcpu)) { 4098 if (static_call(kvm_x86_has_wbinvd_exit)()) 4099 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask); 4100 else if (vcpu->cpu != -1 && vcpu->cpu != cpu) 4101 smp_call_function_single(vcpu->cpu, 4102 wbinvd_ipi, NULL, 1); 4103 } 4104 4105 static_call(kvm_x86_vcpu_load)(vcpu, cpu); 4106 4107 /* Save host pkru register if supported */ 4108 vcpu->arch.host_pkru = read_pkru(); 4109 4110 /* Apply any externally detected TSC adjustments (due to suspend) */ 4111 if (unlikely(vcpu->arch.tsc_offset_adjustment)) { 4112 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment); 4113 vcpu->arch.tsc_offset_adjustment = 0; 4114 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 4115 } 4116 4117 if (unlikely(vcpu->cpu != cpu) || kvm_check_tsc_unstable()) { 4118 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 : 4119 rdtsc() - vcpu->arch.last_host_tsc; 4120 if (tsc_delta < 0) 4121 mark_tsc_unstable("KVM discovered backwards TSC"); 4122 4123 if (kvm_check_tsc_unstable()) { 4124 u64 offset = kvm_compute_tsc_offset(vcpu, 4125 vcpu->arch.last_guest_tsc); 4126 kvm_vcpu_write_tsc_offset(vcpu, offset); 4127 vcpu->arch.tsc_catchup = 1; 4128 } 4129 4130 if (kvm_lapic_hv_timer_in_use(vcpu)) 4131 kvm_lapic_restart_hv_timer(vcpu); 4132 4133 /* 4134 * On a host with synchronized TSC, there is no need to update 4135 * kvmclock on vcpu->cpu migration 4136 */ 4137 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1) 4138 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu); 4139 if (vcpu->cpu != cpu) 4140 kvm_make_request(KVM_REQ_MIGRATE_TIMER, vcpu); 4141 vcpu->cpu = cpu; 4142 } 4143 4144 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu); 4145 } 4146 4147 static void kvm_steal_time_set_preempted(struct kvm_vcpu *vcpu) 4148 { 4149 struct kvm_host_map map; 4150 struct kvm_steal_time *st; 4151 4152 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED)) 4153 return; 4154 4155 if (vcpu->arch.st.preempted) 4156 return; 4157 4158 if (kvm_map_gfn(vcpu, vcpu->arch.st.msr_val >> PAGE_SHIFT, &map, 4159 &vcpu->arch.st.cache, true)) 4160 return; 4161 4162 st = map.hva + 4163 offset_in_page(vcpu->arch.st.msr_val & KVM_STEAL_VALID_BITS); 4164 4165 st->preempted = vcpu->arch.st.preempted = KVM_VCPU_PREEMPTED; 4166 4167 kvm_unmap_gfn(vcpu, &map, &vcpu->arch.st.cache, true, true); 4168 } 4169 4170 void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu) 4171 { 4172 int idx; 4173 4174 if (vcpu->preempted && !vcpu->arch.guest_state_protected) 4175 vcpu->arch.preempted_in_kernel = !static_call(kvm_x86_get_cpl)(vcpu); 4176 4177 /* 4178 * Take the srcu lock as memslots will be accessed to check the gfn 4179 * cache generation against the memslots generation. 4180 */ 4181 idx = srcu_read_lock(&vcpu->kvm->srcu); 4182 if (kvm_xen_msr_enabled(vcpu->kvm)) 4183 kvm_xen_runstate_set_preempted(vcpu); 4184 else 4185 kvm_steal_time_set_preempted(vcpu); 4186 srcu_read_unlock(&vcpu->kvm->srcu, idx); 4187 4188 static_call(kvm_x86_vcpu_put)(vcpu); 4189 vcpu->arch.last_host_tsc = rdtsc(); 4190 /* 4191 * If userspace has set any breakpoints or watchpoints, dr6 is restored 4192 * on every vmexit, but if not, we might have a stale dr6 from the 4193 * guest. do_debug expects dr6 to be cleared after it runs, do the same. 4194 */ 4195 set_debugreg(0, 6); 4196 } 4197 4198 static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu, 4199 struct kvm_lapic_state *s) 4200 { 4201 if (vcpu->arch.apicv_active) 4202 static_call(kvm_x86_sync_pir_to_irr)(vcpu); 4203 4204 return kvm_apic_get_state(vcpu, s); 4205 } 4206 4207 static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu, 4208 struct kvm_lapic_state *s) 4209 { 4210 int r; 4211 4212 r = kvm_apic_set_state(vcpu, s); 4213 if (r) 4214 return r; 4215 update_cr8_intercept(vcpu); 4216 4217 return 0; 4218 } 4219 4220 static int kvm_cpu_accept_dm_intr(struct kvm_vcpu *vcpu) 4221 { 4222 /* 4223 * We can accept userspace's request for interrupt injection 4224 * as long as we have a place to store the interrupt number. 4225 * The actual injection will happen when the CPU is able to 4226 * deliver the interrupt. 4227 */ 4228 if (kvm_cpu_has_extint(vcpu)) 4229 return false; 4230 4231 /* Acknowledging ExtINT does not happen if LINT0 is masked. */ 4232 return (!lapic_in_kernel(vcpu) || 4233 kvm_apic_accept_pic_intr(vcpu)); 4234 } 4235 4236 static int kvm_vcpu_ready_for_interrupt_injection(struct kvm_vcpu *vcpu) 4237 { 4238 return kvm_arch_interrupt_allowed(vcpu) && 4239 kvm_cpu_accept_dm_intr(vcpu); 4240 } 4241 4242 static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu, 4243 struct kvm_interrupt *irq) 4244 { 4245 if (irq->irq >= KVM_NR_INTERRUPTS) 4246 return -EINVAL; 4247 4248 if (!irqchip_in_kernel(vcpu->kvm)) { 4249 kvm_queue_interrupt(vcpu, irq->irq, false); 4250 kvm_make_request(KVM_REQ_EVENT, vcpu); 4251 return 0; 4252 } 4253 4254 /* 4255 * With in-kernel LAPIC, we only use this to inject EXTINT, so 4256 * fail for in-kernel 8259. 4257 */ 4258 if (pic_in_kernel(vcpu->kvm)) 4259 return -ENXIO; 4260 4261 if (vcpu->arch.pending_external_vector != -1) 4262 return -EEXIST; 4263 4264 vcpu->arch.pending_external_vector = irq->irq; 4265 kvm_make_request(KVM_REQ_EVENT, vcpu); 4266 return 0; 4267 } 4268 4269 static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu) 4270 { 4271 kvm_inject_nmi(vcpu); 4272 4273 return 0; 4274 } 4275 4276 static int kvm_vcpu_ioctl_smi(struct kvm_vcpu *vcpu) 4277 { 4278 kvm_make_request(KVM_REQ_SMI, vcpu); 4279 4280 return 0; 4281 } 4282 4283 static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu, 4284 struct kvm_tpr_access_ctl *tac) 4285 { 4286 if (tac->flags) 4287 return -EINVAL; 4288 vcpu->arch.tpr_access_reporting = !!tac->enabled; 4289 return 0; 4290 } 4291 4292 static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu, 4293 u64 mcg_cap) 4294 { 4295 int r; 4296 unsigned bank_num = mcg_cap & 0xff, bank; 4297 4298 r = -EINVAL; 4299 if (!bank_num || bank_num > KVM_MAX_MCE_BANKS) 4300 goto out; 4301 if (mcg_cap & ~(kvm_mce_cap_supported | 0xff | 0xff0000)) 4302 goto out; 4303 r = 0; 4304 vcpu->arch.mcg_cap = mcg_cap; 4305 /* Init IA32_MCG_CTL to all 1s */ 4306 if (mcg_cap & MCG_CTL_P) 4307 vcpu->arch.mcg_ctl = ~(u64)0; 4308 /* Init IA32_MCi_CTL to all 1s */ 4309 for (bank = 0; bank < bank_num; bank++) 4310 vcpu->arch.mce_banks[bank*4] = ~(u64)0; 4311 4312 static_call(kvm_x86_setup_mce)(vcpu); 4313 out: 4314 return r; 4315 } 4316 4317 static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu, 4318 struct kvm_x86_mce *mce) 4319 { 4320 u64 mcg_cap = vcpu->arch.mcg_cap; 4321 unsigned bank_num = mcg_cap & 0xff; 4322 u64 *banks = vcpu->arch.mce_banks; 4323 4324 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL)) 4325 return -EINVAL; 4326 /* 4327 * if IA32_MCG_CTL is not all 1s, the uncorrected error 4328 * reporting is disabled 4329 */ 4330 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) && 4331 vcpu->arch.mcg_ctl != ~(u64)0) 4332 return 0; 4333 banks += 4 * mce->bank; 4334 /* 4335 * if IA32_MCi_CTL is not all 1s, the uncorrected error 4336 * reporting is disabled for the bank 4337 */ 4338 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0) 4339 return 0; 4340 if (mce->status & MCI_STATUS_UC) { 4341 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) || 4342 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) { 4343 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); 4344 return 0; 4345 } 4346 if (banks[1] & MCI_STATUS_VAL) 4347 mce->status |= MCI_STATUS_OVER; 4348 banks[2] = mce->addr; 4349 banks[3] = mce->misc; 4350 vcpu->arch.mcg_status = mce->mcg_status; 4351 banks[1] = mce->status; 4352 kvm_queue_exception(vcpu, MC_VECTOR); 4353 } else if (!(banks[1] & MCI_STATUS_VAL) 4354 || !(banks[1] & MCI_STATUS_UC)) { 4355 if (banks[1] & MCI_STATUS_VAL) 4356 mce->status |= MCI_STATUS_OVER; 4357 banks[2] = mce->addr; 4358 banks[3] = mce->misc; 4359 banks[1] = mce->status; 4360 } else 4361 banks[1] |= MCI_STATUS_OVER; 4362 return 0; 4363 } 4364 4365 static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu, 4366 struct kvm_vcpu_events *events) 4367 { 4368 process_nmi(vcpu); 4369 4370 if (kvm_check_request(KVM_REQ_SMI, vcpu)) 4371 process_smi(vcpu); 4372 4373 /* 4374 * In guest mode, payload delivery should be deferred, 4375 * so that the L1 hypervisor can intercept #PF before 4376 * CR2 is modified (or intercept #DB before DR6 is 4377 * modified under nVMX). Unless the per-VM capability, 4378 * KVM_CAP_EXCEPTION_PAYLOAD, is set, we may not defer the delivery of 4379 * an exception payload and handle after a KVM_GET_VCPU_EVENTS. Since we 4380 * opportunistically defer the exception payload, deliver it if the 4381 * capability hasn't been requested before processing a 4382 * KVM_GET_VCPU_EVENTS. 4383 */ 4384 if (!vcpu->kvm->arch.exception_payload_enabled && 4385 vcpu->arch.exception.pending && vcpu->arch.exception.has_payload) 4386 kvm_deliver_exception_payload(vcpu); 4387 4388 /* 4389 * The API doesn't provide the instruction length for software 4390 * exceptions, so don't report them. As long as the guest RIP 4391 * isn't advanced, we should expect to encounter the exception 4392 * again. 4393 */ 4394 if (kvm_exception_is_soft(vcpu->arch.exception.nr)) { 4395 events->exception.injected = 0; 4396 events->exception.pending = 0; 4397 } else { 4398 events->exception.injected = vcpu->arch.exception.injected; 4399 events->exception.pending = vcpu->arch.exception.pending; 4400 /* 4401 * For ABI compatibility, deliberately conflate 4402 * pending and injected exceptions when 4403 * KVM_CAP_EXCEPTION_PAYLOAD isn't enabled. 4404 */ 4405 if (!vcpu->kvm->arch.exception_payload_enabled) 4406 events->exception.injected |= 4407 vcpu->arch.exception.pending; 4408 } 4409 events->exception.nr = vcpu->arch.exception.nr; 4410 events->exception.has_error_code = vcpu->arch.exception.has_error_code; 4411 events->exception.error_code = vcpu->arch.exception.error_code; 4412 events->exception_has_payload = vcpu->arch.exception.has_payload; 4413 events->exception_payload = vcpu->arch.exception.payload; 4414 4415 events->interrupt.injected = 4416 vcpu->arch.interrupt.injected && !vcpu->arch.interrupt.soft; 4417 events->interrupt.nr = vcpu->arch.interrupt.nr; 4418 events->interrupt.soft = 0; 4419 events->interrupt.shadow = static_call(kvm_x86_get_interrupt_shadow)(vcpu); 4420 4421 events->nmi.injected = vcpu->arch.nmi_injected; 4422 events->nmi.pending = vcpu->arch.nmi_pending != 0; 4423 events->nmi.masked = static_call(kvm_x86_get_nmi_mask)(vcpu); 4424 events->nmi.pad = 0; 4425 4426 events->sipi_vector = 0; /* never valid when reporting to user space */ 4427 4428 events->smi.smm = is_smm(vcpu); 4429 events->smi.pending = vcpu->arch.smi_pending; 4430 events->smi.smm_inside_nmi = 4431 !!(vcpu->arch.hflags & HF_SMM_INSIDE_NMI_MASK); 4432 events->smi.latched_init = kvm_lapic_latched_init(vcpu); 4433 4434 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING 4435 | KVM_VCPUEVENT_VALID_SHADOW 4436 | KVM_VCPUEVENT_VALID_SMM); 4437 if (vcpu->kvm->arch.exception_payload_enabled) 4438 events->flags |= KVM_VCPUEVENT_VALID_PAYLOAD; 4439 4440 memset(&events->reserved, 0, sizeof(events->reserved)); 4441 } 4442 4443 static void kvm_smm_changed(struct kvm_vcpu *vcpu); 4444 4445 static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu, 4446 struct kvm_vcpu_events *events) 4447 { 4448 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING 4449 | KVM_VCPUEVENT_VALID_SIPI_VECTOR 4450 | KVM_VCPUEVENT_VALID_SHADOW 4451 | KVM_VCPUEVENT_VALID_SMM 4452 | KVM_VCPUEVENT_VALID_PAYLOAD)) 4453 return -EINVAL; 4454 4455 if (events->flags & KVM_VCPUEVENT_VALID_PAYLOAD) { 4456 if (!vcpu->kvm->arch.exception_payload_enabled) 4457 return -EINVAL; 4458 if (events->exception.pending) 4459 events->exception.injected = 0; 4460 else 4461 events->exception_has_payload = 0; 4462 } else { 4463 events->exception.pending = 0; 4464 events->exception_has_payload = 0; 4465 } 4466 4467 if ((events->exception.injected || events->exception.pending) && 4468 (events->exception.nr > 31 || events->exception.nr == NMI_VECTOR)) 4469 return -EINVAL; 4470 4471 /* INITs are latched while in SMM */ 4472 if (events->flags & KVM_VCPUEVENT_VALID_SMM && 4473 (events->smi.smm || events->smi.pending) && 4474 vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) 4475 return -EINVAL; 4476 4477 process_nmi(vcpu); 4478 vcpu->arch.exception.injected = events->exception.injected; 4479 vcpu->arch.exception.pending = events->exception.pending; 4480 vcpu->arch.exception.nr = events->exception.nr; 4481 vcpu->arch.exception.has_error_code = events->exception.has_error_code; 4482 vcpu->arch.exception.error_code = events->exception.error_code; 4483 vcpu->arch.exception.has_payload = events->exception_has_payload; 4484 vcpu->arch.exception.payload = events->exception_payload; 4485 4486 vcpu->arch.interrupt.injected = events->interrupt.injected; 4487 vcpu->arch.interrupt.nr = events->interrupt.nr; 4488 vcpu->arch.interrupt.soft = events->interrupt.soft; 4489 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW) 4490 static_call(kvm_x86_set_interrupt_shadow)(vcpu, 4491 events->interrupt.shadow); 4492 4493 vcpu->arch.nmi_injected = events->nmi.injected; 4494 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING) 4495 vcpu->arch.nmi_pending = events->nmi.pending; 4496 static_call(kvm_x86_set_nmi_mask)(vcpu, events->nmi.masked); 4497 4498 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR && 4499 lapic_in_kernel(vcpu)) 4500 vcpu->arch.apic->sipi_vector = events->sipi_vector; 4501 4502 if (events->flags & KVM_VCPUEVENT_VALID_SMM) { 4503 if (!!(vcpu->arch.hflags & HF_SMM_MASK) != events->smi.smm) { 4504 if (events->smi.smm) 4505 vcpu->arch.hflags |= HF_SMM_MASK; 4506 else 4507 vcpu->arch.hflags &= ~HF_SMM_MASK; 4508 kvm_smm_changed(vcpu); 4509 } 4510 4511 vcpu->arch.smi_pending = events->smi.pending; 4512 4513 if (events->smi.smm) { 4514 if (events->smi.smm_inside_nmi) 4515 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK; 4516 else 4517 vcpu->arch.hflags &= ~HF_SMM_INSIDE_NMI_MASK; 4518 } 4519 4520 if (lapic_in_kernel(vcpu)) { 4521 if (events->smi.latched_init) 4522 set_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events); 4523 else 4524 clear_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events); 4525 } 4526 } 4527 4528 kvm_make_request(KVM_REQ_EVENT, vcpu); 4529 4530 return 0; 4531 } 4532 4533 static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu, 4534 struct kvm_debugregs *dbgregs) 4535 { 4536 unsigned long val; 4537 4538 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db)); 4539 kvm_get_dr(vcpu, 6, &val); 4540 dbgregs->dr6 = val; 4541 dbgregs->dr7 = vcpu->arch.dr7; 4542 dbgregs->flags = 0; 4543 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved)); 4544 } 4545 4546 static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu, 4547 struct kvm_debugregs *dbgregs) 4548 { 4549 if (dbgregs->flags) 4550 return -EINVAL; 4551 4552 if (!kvm_dr6_valid(dbgregs->dr6)) 4553 return -EINVAL; 4554 if (!kvm_dr7_valid(dbgregs->dr7)) 4555 return -EINVAL; 4556 4557 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db)); 4558 kvm_update_dr0123(vcpu); 4559 vcpu->arch.dr6 = dbgregs->dr6; 4560 vcpu->arch.dr7 = dbgregs->dr7; 4561 kvm_update_dr7(vcpu); 4562 4563 return 0; 4564 } 4565 4566 #define XSTATE_COMPACTION_ENABLED (1ULL << 63) 4567 4568 static void fill_xsave(u8 *dest, struct kvm_vcpu *vcpu) 4569 { 4570 struct xregs_state *xsave = &vcpu->arch.guest_fpu->state.xsave; 4571 u64 xstate_bv = xsave->header.xfeatures; 4572 u64 valid; 4573 4574 /* 4575 * Copy legacy XSAVE area, to avoid complications with CPUID 4576 * leaves 0 and 1 in the loop below. 4577 */ 4578 memcpy(dest, xsave, XSAVE_HDR_OFFSET); 4579 4580 /* Set XSTATE_BV */ 4581 xstate_bv &= vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FPSSE; 4582 *(u64 *)(dest + XSAVE_HDR_OFFSET) = xstate_bv; 4583 4584 /* 4585 * Copy each region from the possibly compacted offset to the 4586 * non-compacted offset. 4587 */ 4588 valid = xstate_bv & ~XFEATURE_MASK_FPSSE; 4589 while (valid) { 4590 u64 xfeature_mask = valid & -valid; 4591 int xfeature_nr = fls64(xfeature_mask) - 1; 4592 void *src = get_xsave_addr(xsave, xfeature_nr); 4593 4594 if (src) { 4595 u32 size, offset, ecx, edx; 4596 cpuid_count(XSTATE_CPUID, xfeature_nr, 4597 &size, &offset, &ecx, &edx); 4598 if (xfeature_nr == XFEATURE_PKRU) 4599 memcpy(dest + offset, &vcpu->arch.pkru, 4600 sizeof(vcpu->arch.pkru)); 4601 else 4602 memcpy(dest + offset, src, size); 4603 4604 } 4605 4606 valid -= xfeature_mask; 4607 } 4608 } 4609 4610 static void load_xsave(struct kvm_vcpu *vcpu, u8 *src) 4611 { 4612 struct xregs_state *xsave = &vcpu->arch.guest_fpu->state.xsave; 4613 u64 xstate_bv = *(u64 *)(src + XSAVE_HDR_OFFSET); 4614 u64 valid; 4615 4616 /* 4617 * Copy legacy XSAVE area, to avoid complications with CPUID 4618 * leaves 0 and 1 in the loop below. 4619 */ 4620 memcpy(xsave, src, XSAVE_HDR_OFFSET); 4621 4622 /* Set XSTATE_BV and possibly XCOMP_BV. */ 4623 xsave->header.xfeatures = xstate_bv; 4624 if (boot_cpu_has(X86_FEATURE_XSAVES)) 4625 xsave->header.xcomp_bv = host_xcr0 | XSTATE_COMPACTION_ENABLED; 4626 4627 /* 4628 * Copy each region from the non-compacted offset to the 4629 * possibly compacted offset. 4630 */ 4631 valid = xstate_bv & ~XFEATURE_MASK_FPSSE; 4632 while (valid) { 4633 u64 xfeature_mask = valid & -valid; 4634 int xfeature_nr = fls64(xfeature_mask) - 1; 4635 void *dest = get_xsave_addr(xsave, xfeature_nr); 4636 4637 if (dest) { 4638 u32 size, offset, ecx, edx; 4639 cpuid_count(XSTATE_CPUID, xfeature_nr, 4640 &size, &offset, &ecx, &edx); 4641 if (xfeature_nr == XFEATURE_PKRU) 4642 memcpy(&vcpu->arch.pkru, src + offset, 4643 sizeof(vcpu->arch.pkru)); 4644 else 4645 memcpy(dest, src + offset, size); 4646 } 4647 4648 valid -= xfeature_mask; 4649 } 4650 } 4651 4652 static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu, 4653 struct kvm_xsave *guest_xsave) 4654 { 4655 if (!vcpu->arch.guest_fpu) 4656 return; 4657 4658 if (boot_cpu_has(X86_FEATURE_XSAVE)) { 4659 memset(guest_xsave, 0, sizeof(struct kvm_xsave)); 4660 fill_xsave((u8 *) guest_xsave->region, vcpu); 4661 } else { 4662 memcpy(guest_xsave->region, 4663 &vcpu->arch.guest_fpu->state.fxsave, 4664 sizeof(struct fxregs_state)); 4665 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] = 4666 XFEATURE_MASK_FPSSE; 4667 } 4668 } 4669 4670 #define XSAVE_MXCSR_OFFSET 24 4671 4672 static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu, 4673 struct kvm_xsave *guest_xsave) 4674 { 4675 u64 xstate_bv; 4676 u32 mxcsr; 4677 4678 if (!vcpu->arch.guest_fpu) 4679 return 0; 4680 4681 xstate_bv = *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)]; 4682 mxcsr = *(u32 *)&guest_xsave->region[XSAVE_MXCSR_OFFSET / sizeof(u32)]; 4683 4684 if (boot_cpu_has(X86_FEATURE_XSAVE)) { 4685 /* 4686 * Here we allow setting states that are not present in 4687 * CPUID leaf 0xD, index 0, EDX:EAX. This is for compatibility 4688 * with old userspace. 4689 */ 4690 if (xstate_bv & ~supported_xcr0 || mxcsr & ~mxcsr_feature_mask) 4691 return -EINVAL; 4692 load_xsave(vcpu, (u8 *)guest_xsave->region); 4693 } else { 4694 if (xstate_bv & ~XFEATURE_MASK_FPSSE || 4695 mxcsr & ~mxcsr_feature_mask) 4696 return -EINVAL; 4697 memcpy(&vcpu->arch.guest_fpu->state.fxsave, 4698 guest_xsave->region, sizeof(struct fxregs_state)); 4699 } 4700 return 0; 4701 } 4702 4703 static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu, 4704 struct kvm_xcrs *guest_xcrs) 4705 { 4706 if (!boot_cpu_has(X86_FEATURE_XSAVE)) { 4707 guest_xcrs->nr_xcrs = 0; 4708 return; 4709 } 4710 4711 guest_xcrs->nr_xcrs = 1; 4712 guest_xcrs->flags = 0; 4713 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK; 4714 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0; 4715 } 4716 4717 static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu, 4718 struct kvm_xcrs *guest_xcrs) 4719 { 4720 int i, r = 0; 4721 4722 if (!boot_cpu_has(X86_FEATURE_XSAVE)) 4723 return -EINVAL; 4724 4725 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags) 4726 return -EINVAL; 4727 4728 for (i = 0; i < guest_xcrs->nr_xcrs; i++) 4729 /* Only support XCR0 currently */ 4730 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) { 4731 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK, 4732 guest_xcrs->xcrs[i].value); 4733 break; 4734 } 4735 if (r) 4736 r = -EINVAL; 4737 return r; 4738 } 4739 4740 /* 4741 * kvm_set_guest_paused() indicates to the guest kernel that it has been 4742 * stopped by the hypervisor. This function will be called from the host only. 4743 * EINVAL is returned when the host attempts to set the flag for a guest that 4744 * does not support pv clocks. 4745 */ 4746 static int kvm_set_guest_paused(struct kvm_vcpu *vcpu) 4747 { 4748 if (!vcpu->arch.pv_time_enabled) 4749 return -EINVAL; 4750 vcpu->arch.pvclock_set_guest_stopped_request = true; 4751 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 4752 return 0; 4753 } 4754 4755 static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu, 4756 struct kvm_enable_cap *cap) 4757 { 4758 int r; 4759 uint16_t vmcs_version; 4760 void __user *user_ptr; 4761 4762 if (cap->flags) 4763 return -EINVAL; 4764 4765 switch (cap->cap) { 4766 case KVM_CAP_HYPERV_SYNIC2: 4767 if (cap->args[0]) 4768 return -EINVAL; 4769 fallthrough; 4770 4771 case KVM_CAP_HYPERV_SYNIC: 4772 if (!irqchip_in_kernel(vcpu->kvm)) 4773 return -EINVAL; 4774 return kvm_hv_activate_synic(vcpu, cap->cap == 4775 KVM_CAP_HYPERV_SYNIC2); 4776 case KVM_CAP_HYPERV_ENLIGHTENED_VMCS: 4777 if (!kvm_x86_ops.nested_ops->enable_evmcs) 4778 return -ENOTTY; 4779 r = kvm_x86_ops.nested_ops->enable_evmcs(vcpu, &vmcs_version); 4780 if (!r) { 4781 user_ptr = (void __user *)(uintptr_t)cap->args[0]; 4782 if (copy_to_user(user_ptr, &vmcs_version, 4783 sizeof(vmcs_version))) 4784 r = -EFAULT; 4785 } 4786 return r; 4787 case KVM_CAP_HYPERV_DIRECT_TLBFLUSH: 4788 if (!kvm_x86_ops.enable_direct_tlbflush) 4789 return -ENOTTY; 4790 4791 return static_call(kvm_x86_enable_direct_tlbflush)(vcpu); 4792 4793 case KVM_CAP_ENFORCE_PV_FEATURE_CPUID: 4794 vcpu->arch.pv_cpuid.enforce = cap->args[0]; 4795 if (vcpu->arch.pv_cpuid.enforce) 4796 kvm_update_pv_runtime(vcpu); 4797 4798 return 0; 4799 default: 4800 return -EINVAL; 4801 } 4802 } 4803 4804 long kvm_arch_vcpu_ioctl(struct file *filp, 4805 unsigned int ioctl, unsigned long arg) 4806 { 4807 struct kvm_vcpu *vcpu = filp->private_data; 4808 void __user *argp = (void __user *)arg; 4809 int r; 4810 union { 4811 struct kvm_lapic_state *lapic; 4812 struct kvm_xsave *xsave; 4813 struct kvm_xcrs *xcrs; 4814 void *buffer; 4815 } u; 4816 4817 vcpu_load(vcpu); 4818 4819 u.buffer = NULL; 4820 switch (ioctl) { 4821 case KVM_GET_LAPIC: { 4822 r = -EINVAL; 4823 if (!lapic_in_kernel(vcpu)) 4824 goto out; 4825 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), 4826 GFP_KERNEL_ACCOUNT); 4827 4828 r = -ENOMEM; 4829 if (!u.lapic) 4830 goto out; 4831 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic); 4832 if (r) 4833 goto out; 4834 r = -EFAULT; 4835 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state))) 4836 goto out; 4837 r = 0; 4838 break; 4839 } 4840 case KVM_SET_LAPIC: { 4841 r = -EINVAL; 4842 if (!lapic_in_kernel(vcpu)) 4843 goto out; 4844 u.lapic = memdup_user(argp, sizeof(*u.lapic)); 4845 if (IS_ERR(u.lapic)) { 4846 r = PTR_ERR(u.lapic); 4847 goto out_nofree; 4848 } 4849 4850 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic); 4851 break; 4852 } 4853 case KVM_INTERRUPT: { 4854 struct kvm_interrupt irq; 4855 4856 r = -EFAULT; 4857 if (copy_from_user(&irq, argp, sizeof(irq))) 4858 goto out; 4859 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq); 4860 break; 4861 } 4862 case KVM_NMI: { 4863 r = kvm_vcpu_ioctl_nmi(vcpu); 4864 break; 4865 } 4866 case KVM_SMI: { 4867 r = kvm_vcpu_ioctl_smi(vcpu); 4868 break; 4869 } 4870 case KVM_SET_CPUID: { 4871 struct kvm_cpuid __user *cpuid_arg = argp; 4872 struct kvm_cpuid cpuid; 4873 4874 r = -EFAULT; 4875 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid))) 4876 goto out; 4877 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries); 4878 break; 4879 } 4880 case KVM_SET_CPUID2: { 4881 struct kvm_cpuid2 __user *cpuid_arg = argp; 4882 struct kvm_cpuid2 cpuid; 4883 4884 r = -EFAULT; 4885 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid))) 4886 goto out; 4887 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid, 4888 cpuid_arg->entries); 4889 break; 4890 } 4891 case KVM_GET_CPUID2: { 4892 struct kvm_cpuid2 __user *cpuid_arg = argp; 4893 struct kvm_cpuid2 cpuid; 4894 4895 r = -EFAULT; 4896 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid))) 4897 goto out; 4898 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid, 4899 cpuid_arg->entries); 4900 if (r) 4901 goto out; 4902 r = -EFAULT; 4903 if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid))) 4904 goto out; 4905 r = 0; 4906 break; 4907 } 4908 case KVM_GET_MSRS: { 4909 int idx = srcu_read_lock(&vcpu->kvm->srcu); 4910 r = msr_io(vcpu, argp, do_get_msr, 1); 4911 srcu_read_unlock(&vcpu->kvm->srcu, idx); 4912 break; 4913 } 4914 case KVM_SET_MSRS: { 4915 int idx = srcu_read_lock(&vcpu->kvm->srcu); 4916 r = msr_io(vcpu, argp, do_set_msr, 0); 4917 srcu_read_unlock(&vcpu->kvm->srcu, idx); 4918 break; 4919 } 4920 case KVM_TPR_ACCESS_REPORTING: { 4921 struct kvm_tpr_access_ctl tac; 4922 4923 r = -EFAULT; 4924 if (copy_from_user(&tac, argp, sizeof(tac))) 4925 goto out; 4926 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac); 4927 if (r) 4928 goto out; 4929 r = -EFAULT; 4930 if (copy_to_user(argp, &tac, sizeof(tac))) 4931 goto out; 4932 r = 0; 4933 break; 4934 }; 4935 case KVM_SET_VAPIC_ADDR: { 4936 struct kvm_vapic_addr va; 4937 int idx; 4938 4939 r = -EINVAL; 4940 if (!lapic_in_kernel(vcpu)) 4941 goto out; 4942 r = -EFAULT; 4943 if (copy_from_user(&va, argp, sizeof(va))) 4944 goto out; 4945 idx = srcu_read_lock(&vcpu->kvm->srcu); 4946 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr); 4947 srcu_read_unlock(&vcpu->kvm->srcu, idx); 4948 break; 4949 } 4950 case KVM_X86_SETUP_MCE: { 4951 u64 mcg_cap; 4952 4953 r = -EFAULT; 4954 if (copy_from_user(&mcg_cap, argp, sizeof(mcg_cap))) 4955 goto out; 4956 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap); 4957 break; 4958 } 4959 case KVM_X86_SET_MCE: { 4960 struct kvm_x86_mce mce; 4961 4962 r = -EFAULT; 4963 if (copy_from_user(&mce, argp, sizeof(mce))) 4964 goto out; 4965 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce); 4966 break; 4967 } 4968 case KVM_GET_VCPU_EVENTS: { 4969 struct kvm_vcpu_events events; 4970 4971 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events); 4972 4973 r = -EFAULT; 4974 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events))) 4975 break; 4976 r = 0; 4977 break; 4978 } 4979 case KVM_SET_VCPU_EVENTS: { 4980 struct kvm_vcpu_events events; 4981 4982 r = -EFAULT; 4983 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events))) 4984 break; 4985 4986 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events); 4987 break; 4988 } 4989 case KVM_GET_DEBUGREGS: { 4990 struct kvm_debugregs dbgregs; 4991 4992 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs); 4993 4994 r = -EFAULT; 4995 if (copy_to_user(argp, &dbgregs, 4996 sizeof(struct kvm_debugregs))) 4997 break; 4998 r = 0; 4999 break; 5000 } 5001 case KVM_SET_DEBUGREGS: { 5002 struct kvm_debugregs dbgregs; 5003 5004 r = -EFAULT; 5005 if (copy_from_user(&dbgregs, argp, 5006 sizeof(struct kvm_debugregs))) 5007 break; 5008 5009 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs); 5010 break; 5011 } 5012 case KVM_GET_XSAVE: { 5013 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL_ACCOUNT); 5014 r = -ENOMEM; 5015 if (!u.xsave) 5016 break; 5017 5018 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave); 5019 5020 r = -EFAULT; 5021 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave))) 5022 break; 5023 r = 0; 5024 break; 5025 } 5026 case KVM_SET_XSAVE: { 5027 u.xsave = memdup_user(argp, sizeof(*u.xsave)); 5028 if (IS_ERR(u.xsave)) { 5029 r = PTR_ERR(u.xsave); 5030 goto out_nofree; 5031 } 5032 5033 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave); 5034 break; 5035 } 5036 case KVM_GET_XCRS: { 5037 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL_ACCOUNT); 5038 r = -ENOMEM; 5039 if (!u.xcrs) 5040 break; 5041 5042 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs); 5043 5044 r = -EFAULT; 5045 if (copy_to_user(argp, u.xcrs, 5046 sizeof(struct kvm_xcrs))) 5047 break; 5048 r = 0; 5049 break; 5050 } 5051 case KVM_SET_XCRS: { 5052 u.xcrs = memdup_user(argp, sizeof(*u.xcrs)); 5053 if (IS_ERR(u.xcrs)) { 5054 r = PTR_ERR(u.xcrs); 5055 goto out_nofree; 5056 } 5057 5058 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs); 5059 break; 5060 } 5061 case KVM_SET_TSC_KHZ: { 5062 u32 user_tsc_khz; 5063 5064 r = -EINVAL; 5065 user_tsc_khz = (u32)arg; 5066 5067 if (kvm_has_tsc_control && 5068 user_tsc_khz >= kvm_max_guest_tsc_khz) 5069 goto out; 5070 5071 if (user_tsc_khz == 0) 5072 user_tsc_khz = tsc_khz; 5073 5074 if (!kvm_set_tsc_khz(vcpu, user_tsc_khz)) 5075 r = 0; 5076 5077 goto out; 5078 } 5079 case KVM_GET_TSC_KHZ: { 5080 r = vcpu->arch.virtual_tsc_khz; 5081 goto out; 5082 } 5083 case KVM_KVMCLOCK_CTRL: { 5084 r = kvm_set_guest_paused(vcpu); 5085 goto out; 5086 } 5087 case KVM_ENABLE_CAP: { 5088 struct kvm_enable_cap cap; 5089 5090 r = -EFAULT; 5091 if (copy_from_user(&cap, argp, sizeof(cap))) 5092 goto out; 5093 r = kvm_vcpu_ioctl_enable_cap(vcpu, &cap); 5094 break; 5095 } 5096 case KVM_GET_NESTED_STATE: { 5097 struct kvm_nested_state __user *user_kvm_nested_state = argp; 5098 u32 user_data_size; 5099 5100 r = -EINVAL; 5101 if (!kvm_x86_ops.nested_ops->get_state) 5102 break; 5103 5104 BUILD_BUG_ON(sizeof(user_data_size) != sizeof(user_kvm_nested_state->size)); 5105 r = -EFAULT; 5106 if (get_user(user_data_size, &user_kvm_nested_state->size)) 5107 break; 5108 5109 r = kvm_x86_ops.nested_ops->get_state(vcpu, user_kvm_nested_state, 5110 user_data_size); 5111 if (r < 0) 5112 break; 5113 5114 if (r > user_data_size) { 5115 if (put_user(r, &user_kvm_nested_state->size)) 5116 r = -EFAULT; 5117 else 5118 r = -E2BIG; 5119 break; 5120 } 5121 5122 r = 0; 5123 break; 5124 } 5125 case KVM_SET_NESTED_STATE: { 5126 struct kvm_nested_state __user *user_kvm_nested_state = argp; 5127 struct kvm_nested_state kvm_state; 5128 int idx; 5129 5130 r = -EINVAL; 5131 if (!kvm_x86_ops.nested_ops->set_state) 5132 break; 5133 5134 r = -EFAULT; 5135 if (copy_from_user(&kvm_state, user_kvm_nested_state, sizeof(kvm_state))) 5136 break; 5137 5138 r = -EINVAL; 5139 if (kvm_state.size < sizeof(kvm_state)) 5140 break; 5141 5142 if (kvm_state.flags & 5143 ~(KVM_STATE_NESTED_RUN_PENDING | KVM_STATE_NESTED_GUEST_MODE 5144 | KVM_STATE_NESTED_EVMCS | KVM_STATE_NESTED_MTF_PENDING 5145 | KVM_STATE_NESTED_GIF_SET)) 5146 break; 5147 5148 /* nested_run_pending implies guest_mode. */ 5149 if ((kvm_state.flags & KVM_STATE_NESTED_RUN_PENDING) 5150 && !(kvm_state.flags & KVM_STATE_NESTED_GUEST_MODE)) 5151 break; 5152 5153 idx = srcu_read_lock(&vcpu->kvm->srcu); 5154 r = kvm_x86_ops.nested_ops->set_state(vcpu, user_kvm_nested_state, &kvm_state); 5155 srcu_read_unlock(&vcpu->kvm->srcu, idx); 5156 break; 5157 } 5158 case KVM_GET_SUPPORTED_HV_CPUID: 5159 r = kvm_ioctl_get_supported_hv_cpuid(vcpu, argp); 5160 break; 5161 #ifdef CONFIG_KVM_XEN 5162 case KVM_XEN_VCPU_GET_ATTR: { 5163 struct kvm_xen_vcpu_attr xva; 5164 5165 r = -EFAULT; 5166 if (copy_from_user(&xva, argp, sizeof(xva))) 5167 goto out; 5168 r = kvm_xen_vcpu_get_attr(vcpu, &xva); 5169 if (!r && copy_to_user(argp, &xva, sizeof(xva))) 5170 r = -EFAULT; 5171 break; 5172 } 5173 case KVM_XEN_VCPU_SET_ATTR: { 5174 struct kvm_xen_vcpu_attr xva; 5175 5176 r = -EFAULT; 5177 if (copy_from_user(&xva, argp, sizeof(xva))) 5178 goto out; 5179 r = kvm_xen_vcpu_set_attr(vcpu, &xva); 5180 break; 5181 } 5182 #endif 5183 default: 5184 r = -EINVAL; 5185 } 5186 out: 5187 kfree(u.buffer); 5188 out_nofree: 5189 vcpu_put(vcpu); 5190 return r; 5191 } 5192 5193 vm_fault_t kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf) 5194 { 5195 return VM_FAULT_SIGBUS; 5196 } 5197 5198 static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr) 5199 { 5200 int ret; 5201 5202 if (addr > (unsigned int)(-3 * PAGE_SIZE)) 5203 return -EINVAL; 5204 ret = static_call(kvm_x86_set_tss_addr)(kvm, addr); 5205 return ret; 5206 } 5207 5208 static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm, 5209 u64 ident_addr) 5210 { 5211 return static_call(kvm_x86_set_identity_map_addr)(kvm, ident_addr); 5212 } 5213 5214 static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm, 5215 unsigned long kvm_nr_mmu_pages) 5216 { 5217 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES) 5218 return -EINVAL; 5219 5220 mutex_lock(&kvm->slots_lock); 5221 5222 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages); 5223 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages; 5224 5225 mutex_unlock(&kvm->slots_lock); 5226 return 0; 5227 } 5228 5229 static unsigned long kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm) 5230 { 5231 return kvm->arch.n_max_mmu_pages; 5232 } 5233 5234 static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip) 5235 { 5236 struct kvm_pic *pic = kvm->arch.vpic; 5237 int r; 5238 5239 r = 0; 5240 switch (chip->chip_id) { 5241 case KVM_IRQCHIP_PIC_MASTER: 5242 memcpy(&chip->chip.pic, &pic->pics[0], 5243 sizeof(struct kvm_pic_state)); 5244 break; 5245 case KVM_IRQCHIP_PIC_SLAVE: 5246 memcpy(&chip->chip.pic, &pic->pics[1], 5247 sizeof(struct kvm_pic_state)); 5248 break; 5249 case KVM_IRQCHIP_IOAPIC: 5250 kvm_get_ioapic(kvm, &chip->chip.ioapic); 5251 break; 5252 default: 5253 r = -EINVAL; 5254 break; 5255 } 5256 return r; 5257 } 5258 5259 static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip) 5260 { 5261 struct kvm_pic *pic = kvm->arch.vpic; 5262 int r; 5263 5264 r = 0; 5265 switch (chip->chip_id) { 5266 case KVM_IRQCHIP_PIC_MASTER: 5267 spin_lock(&pic->lock); 5268 memcpy(&pic->pics[0], &chip->chip.pic, 5269 sizeof(struct kvm_pic_state)); 5270 spin_unlock(&pic->lock); 5271 break; 5272 case KVM_IRQCHIP_PIC_SLAVE: 5273 spin_lock(&pic->lock); 5274 memcpy(&pic->pics[1], &chip->chip.pic, 5275 sizeof(struct kvm_pic_state)); 5276 spin_unlock(&pic->lock); 5277 break; 5278 case KVM_IRQCHIP_IOAPIC: 5279 kvm_set_ioapic(kvm, &chip->chip.ioapic); 5280 break; 5281 default: 5282 r = -EINVAL; 5283 break; 5284 } 5285 kvm_pic_update_irq(pic); 5286 return r; 5287 } 5288 5289 static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps) 5290 { 5291 struct kvm_kpit_state *kps = &kvm->arch.vpit->pit_state; 5292 5293 BUILD_BUG_ON(sizeof(*ps) != sizeof(kps->channels)); 5294 5295 mutex_lock(&kps->lock); 5296 memcpy(ps, &kps->channels, sizeof(*ps)); 5297 mutex_unlock(&kps->lock); 5298 return 0; 5299 } 5300 5301 static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps) 5302 { 5303 int i; 5304 struct kvm_pit *pit = kvm->arch.vpit; 5305 5306 mutex_lock(&pit->pit_state.lock); 5307 memcpy(&pit->pit_state.channels, ps, sizeof(*ps)); 5308 for (i = 0; i < 3; i++) 5309 kvm_pit_load_count(pit, i, ps->channels[i].count, 0); 5310 mutex_unlock(&pit->pit_state.lock); 5311 return 0; 5312 } 5313 5314 static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps) 5315 { 5316 mutex_lock(&kvm->arch.vpit->pit_state.lock); 5317 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels, 5318 sizeof(ps->channels)); 5319 ps->flags = kvm->arch.vpit->pit_state.flags; 5320 mutex_unlock(&kvm->arch.vpit->pit_state.lock); 5321 memset(&ps->reserved, 0, sizeof(ps->reserved)); 5322 return 0; 5323 } 5324 5325 static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps) 5326 { 5327 int start = 0; 5328 int i; 5329 u32 prev_legacy, cur_legacy; 5330 struct kvm_pit *pit = kvm->arch.vpit; 5331 5332 mutex_lock(&pit->pit_state.lock); 5333 prev_legacy = pit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY; 5334 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY; 5335 if (!prev_legacy && cur_legacy) 5336 start = 1; 5337 memcpy(&pit->pit_state.channels, &ps->channels, 5338 sizeof(pit->pit_state.channels)); 5339 pit->pit_state.flags = ps->flags; 5340 for (i = 0; i < 3; i++) 5341 kvm_pit_load_count(pit, i, pit->pit_state.channels[i].count, 5342 start && i == 0); 5343 mutex_unlock(&pit->pit_state.lock); 5344 return 0; 5345 } 5346 5347 static int kvm_vm_ioctl_reinject(struct kvm *kvm, 5348 struct kvm_reinject_control *control) 5349 { 5350 struct kvm_pit *pit = kvm->arch.vpit; 5351 5352 /* pit->pit_state.lock was overloaded to prevent userspace from getting 5353 * an inconsistent state after running multiple KVM_REINJECT_CONTROL 5354 * ioctls in parallel. Use a separate lock if that ioctl isn't rare. 5355 */ 5356 mutex_lock(&pit->pit_state.lock); 5357 kvm_pit_set_reinject(pit, control->pit_reinject); 5358 mutex_unlock(&pit->pit_state.lock); 5359 5360 return 0; 5361 } 5362 5363 void kvm_arch_sync_dirty_log(struct kvm *kvm, struct kvm_memory_slot *memslot) 5364 { 5365 5366 /* 5367 * Flush all CPUs' dirty log buffers to the dirty_bitmap. Called 5368 * before reporting dirty_bitmap to userspace. KVM flushes the buffers 5369 * on all VM-Exits, thus we only need to kick running vCPUs to force a 5370 * VM-Exit. 5371 */ 5372 struct kvm_vcpu *vcpu; 5373 int i; 5374 5375 kvm_for_each_vcpu(i, vcpu, kvm) 5376 kvm_vcpu_kick(vcpu); 5377 } 5378 5379 int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event, 5380 bool line_status) 5381 { 5382 if (!irqchip_in_kernel(kvm)) 5383 return -ENXIO; 5384 5385 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID, 5386 irq_event->irq, irq_event->level, 5387 line_status); 5388 return 0; 5389 } 5390 5391 int kvm_vm_ioctl_enable_cap(struct kvm *kvm, 5392 struct kvm_enable_cap *cap) 5393 { 5394 int r; 5395 5396 if (cap->flags) 5397 return -EINVAL; 5398 5399 switch (cap->cap) { 5400 case KVM_CAP_DISABLE_QUIRKS: 5401 kvm->arch.disabled_quirks = cap->args[0]; 5402 r = 0; 5403 break; 5404 case KVM_CAP_SPLIT_IRQCHIP: { 5405 mutex_lock(&kvm->lock); 5406 r = -EINVAL; 5407 if (cap->args[0] > MAX_NR_RESERVED_IOAPIC_PINS) 5408 goto split_irqchip_unlock; 5409 r = -EEXIST; 5410 if (irqchip_in_kernel(kvm)) 5411 goto split_irqchip_unlock; 5412 if (kvm->created_vcpus) 5413 goto split_irqchip_unlock; 5414 r = kvm_setup_empty_irq_routing(kvm); 5415 if (r) 5416 goto split_irqchip_unlock; 5417 /* Pairs with irqchip_in_kernel. */ 5418 smp_wmb(); 5419 kvm->arch.irqchip_mode = KVM_IRQCHIP_SPLIT; 5420 kvm->arch.nr_reserved_ioapic_pins = cap->args[0]; 5421 r = 0; 5422 split_irqchip_unlock: 5423 mutex_unlock(&kvm->lock); 5424 break; 5425 } 5426 case KVM_CAP_X2APIC_API: 5427 r = -EINVAL; 5428 if (cap->args[0] & ~KVM_X2APIC_API_VALID_FLAGS) 5429 break; 5430 5431 if (cap->args[0] & KVM_X2APIC_API_USE_32BIT_IDS) 5432 kvm->arch.x2apic_format = true; 5433 if (cap->args[0] & KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK) 5434 kvm->arch.x2apic_broadcast_quirk_disabled = true; 5435 5436 r = 0; 5437 break; 5438 case KVM_CAP_X86_DISABLE_EXITS: 5439 r = -EINVAL; 5440 if (cap->args[0] & ~KVM_X86_DISABLE_VALID_EXITS) 5441 break; 5442 5443 if ((cap->args[0] & KVM_X86_DISABLE_EXITS_MWAIT) && 5444 kvm_can_mwait_in_guest()) 5445 kvm->arch.mwait_in_guest = true; 5446 if (cap->args[0] & KVM_X86_DISABLE_EXITS_HLT) 5447 kvm->arch.hlt_in_guest = true; 5448 if (cap->args[0] & KVM_X86_DISABLE_EXITS_PAUSE) 5449 kvm->arch.pause_in_guest = true; 5450 if (cap->args[0] & KVM_X86_DISABLE_EXITS_CSTATE) 5451 kvm->arch.cstate_in_guest = true; 5452 r = 0; 5453 break; 5454 case KVM_CAP_MSR_PLATFORM_INFO: 5455 kvm->arch.guest_can_read_msr_platform_info = cap->args[0]; 5456 r = 0; 5457 break; 5458 case KVM_CAP_EXCEPTION_PAYLOAD: 5459 kvm->arch.exception_payload_enabled = cap->args[0]; 5460 r = 0; 5461 break; 5462 case KVM_CAP_X86_USER_SPACE_MSR: 5463 kvm->arch.user_space_msr_mask = cap->args[0]; 5464 r = 0; 5465 break; 5466 case KVM_CAP_X86_BUS_LOCK_EXIT: 5467 r = -EINVAL; 5468 if (cap->args[0] & ~KVM_BUS_LOCK_DETECTION_VALID_MODE) 5469 break; 5470 5471 if ((cap->args[0] & KVM_BUS_LOCK_DETECTION_OFF) && 5472 (cap->args[0] & KVM_BUS_LOCK_DETECTION_EXIT)) 5473 break; 5474 5475 if (kvm_has_bus_lock_exit && 5476 cap->args[0] & KVM_BUS_LOCK_DETECTION_EXIT) 5477 kvm->arch.bus_lock_detection_enabled = true; 5478 r = 0; 5479 break; 5480 #ifdef CONFIG_X86_SGX_KVM 5481 case KVM_CAP_SGX_ATTRIBUTE: { 5482 unsigned long allowed_attributes = 0; 5483 5484 r = sgx_set_attribute(&allowed_attributes, cap->args[0]); 5485 if (r) 5486 break; 5487 5488 /* KVM only supports the PROVISIONKEY privileged attribute. */ 5489 if ((allowed_attributes & SGX_ATTR_PROVISIONKEY) && 5490 !(allowed_attributes & ~SGX_ATTR_PROVISIONKEY)) 5491 kvm->arch.sgx_provisioning_allowed = true; 5492 else 5493 r = -EINVAL; 5494 break; 5495 } 5496 #endif 5497 case KVM_CAP_VM_COPY_ENC_CONTEXT_FROM: 5498 r = -EINVAL; 5499 if (kvm_x86_ops.vm_copy_enc_context_from) 5500 r = kvm_x86_ops.vm_copy_enc_context_from(kvm, cap->args[0]); 5501 return r; 5502 default: 5503 r = -EINVAL; 5504 break; 5505 } 5506 return r; 5507 } 5508 5509 static struct kvm_x86_msr_filter *kvm_alloc_msr_filter(bool default_allow) 5510 { 5511 struct kvm_x86_msr_filter *msr_filter; 5512 5513 msr_filter = kzalloc(sizeof(*msr_filter), GFP_KERNEL_ACCOUNT); 5514 if (!msr_filter) 5515 return NULL; 5516 5517 msr_filter->default_allow = default_allow; 5518 return msr_filter; 5519 } 5520 5521 static void kvm_free_msr_filter(struct kvm_x86_msr_filter *msr_filter) 5522 { 5523 u32 i; 5524 5525 if (!msr_filter) 5526 return; 5527 5528 for (i = 0; i < msr_filter->count; i++) 5529 kfree(msr_filter->ranges[i].bitmap); 5530 5531 kfree(msr_filter); 5532 } 5533 5534 static int kvm_add_msr_filter(struct kvm_x86_msr_filter *msr_filter, 5535 struct kvm_msr_filter_range *user_range) 5536 { 5537 unsigned long *bitmap = NULL; 5538 size_t bitmap_size; 5539 5540 if (!user_range->nmsrs) 5541 return 0; 5542 5543 if (user_range->flags & ~(KVM_MSR_FILTER_READ | KVM_MSR_FILTER_WRITE)) 5544 return -EINVAL; 5545 5546 if (!user_range->flags) 5547 return -EINVAL; 5548 5549 bitmap_size = BITS_TO_LONGS(user_range->nmsrs) * sizeof(long); 5550 if (!bitmap_size || bitmap_size > KVM_MSR_FILTER_MAX_BITMAP_SIZE) 5551 return -EINVAL; 5552 5553 bitmap = memdup_user((__user u8*)user_range->bitmap, bitmap_size); 5554 if (IS_ERR(bitmap)) 5555 return PTR_ERR(bitmap); 5556 5557 msr_filter->ranges[msr_filter->count] = (struct msr_bitmap_range) { 5558 .flags = user_range->flags, 5559 .base = user_range->base, 5560 .nmsrs = user_range->nmsrs, 5561 .bitmap = bitmap, 5562 }; 5563 5564 msr_filter->count++; 5565 return 0; 5566 } 5567 5568 static int kvm_vm_ioctl_set_msr_filter(struct kvm *kvm, void __user *argp) 5569 { 5570 struct kvm_msr_filter __user *user_msr_filter = argp; 5571 struct kvm_x86_msr_filter *new_filter, *old_filter; 5572 struct kvm_msr_filter filter; 5573 bool default_allow; 5574 bool empty = true; 5575 int r = 0; 5576 u32 i; 5577 5578 if (copy_from_user(&filter, user_msr_filter, sizeof(filter))) 5579 return -EFAULT; 5580 5581 for (i = 0; i < ARRAY_SIZE(filter.ranges); i++) 5582 empty &= !filter.ranges[i].nmsrs; 5583 5584 default_allow = !(filter.flags & KVM_MSR_FILTER_DEFAULT_DENY); 5585 if (empty && !default_allow) 5586 return -EINVAL; 5587 5588 new_filter = kvm_alloc_msr_filter(default_allow); 5589 if (!new_filter) 5590 return -ENOMEM; 5591 5592 for (i = 0; i < ARRAY_SIZE(filter.ranges); i++) { 5593 r = kvm_add_msr_filter(new_filter, &filter.ranges[i]); 5594 if (r) { 5595 kvm_free_msr_filter(new_filter); 5596 return r; 5597 } 5598 } 5599 5600 mutex_lock(&kvm->lock); 5601 5602 /* The per-VM filter is protected by kvm->lock... */ 5603 old_filter = srcu_dereference_check(kvm->arch.msr_filter, &kvm->srcu, 1); 5604 5605 rcu_assign_pointer(kvm->arch.msr_filter, new_filter); 5606 synchronize_srcu(&kvm->srcu); 5607 5608 kvm_free_msr_filter(old_filter); 5609 5610 kvm_make_all_cpus_request(kvm, KVM_REQ_MSR_FILTER_CHANGED); 5611 mutex_unlock(&kvm->lock); 5612 5613 return 0; 5614 } 5615 5616 long kvm_arch_vm_ioctl(struct file *filp, 5617 unsigned int ioctl, unsigned long arg) 5618 { 5619 struct kvm *kvm = filp->private_data; 5620 void __user *argp = (void __user *)arg; 5621 int r = -ENOTTY; 5622 /* 5623 * This union makes it completely explicit to gcc-3.x 5624 * that these two variables' stack usage should be 5625 * combined, not added together. 5626 */ 5627 union { 5628 struct kvm_pit_state ps; 5629 struct kvm_pit_state2 ps2; 5630 struct kvm_pit_config pit_config; 5631 } u; 5632 5633 switch (ioctl) { 5634 case KVM_SET_TSS_ADDR: 5635 r = kvm_vm_ioctl_set_tss_addr(kvm, arg); 5636 break; 5637 case KVM_SET_IDENTITY_MAP_ADDR: { 5638 u64 ident_addr; 5639 5640 mutex_lock(&kvm->lock); 5641 r = -EINVAL; 5642 if (kvm->created_vcpus) 5643 goto set_identity_unlock; 5644 r = -EFAULT; 5645 if (copy_from_user(&ident_addr, argp, sizeof(ident_addr))) 5646 goto set_identity_unlock; 5647 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr); 5648 set_identity_unlock: 5649 mutex_unlock(&kvm->lock); 5650 break; 5651 } 5652 case KVM_SET_NR_MMU_PAGES: 5653 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg); 5654 break; 5655 case KVM_GET_NR_MMU_PAGES: 5656 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm); 5657 break; 5658 case KVM_CREATE_IRQCHIP: { 5659 mutex_lock(&kvm->lock); 5660 5661 r = -EEXIST; 5662 if (irqchip_in_kernel(kvm)) 5663 goto create_irqchip_unlock; 5664 5665 r = -EINVAL; 5666 if (kvm->created_vcpus) 5667 goto create_irqchip_unlock; 5668 5669 r = kvm_pic_init(kvm); 5670 if (r) 5671 goto create_irqchip_unlock; 5672 5673 r = kvm_ioapic_init(kvm); 5674 if (r) { 5675 kvm_pic_destroy(kvm); 5676 goto create_irqchip_unlock; 5677 } 5678 5679 r = kvm_setup_default_irq_routing(kvm); 5680 if (r) { 5681 kvm_ioapic_destroy(kvm); 5682 kvm_pic_destroy(kvm); 5683 goto create_irqchip_unlock; 5684 } 5685 /* Write kvm->irq_routing before enabling irqchip_in_kernel. */ 5686 smp_wmb(); 5687 kvm->arch.irqchip_mode = KVM_IRQCHIP_KERNEL; 5688 create_irqchip_unlock: 5689 mutex_unlock(&kvm->lock); 5690 break; 5691 } 5692 case KVM_CREATE_PIT: 5693 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY; 5694 goto create_pit; 5695 case KVM_CREATE_PIT2: 5696 r = -EFAULT; 5697 if (copy_from_user(&u.pit_config, argp, 5698 sizeof(struct kvm_pit_config))) 5699 goto out; 5700 create_pit: 5701 mutex_lock(&kvm->lock); 5702 r = -EEXIST; 5703 if (kvm->arch.vpit) 5704 goto create_pit_unlock; 5705 r = -ENOMEM; 5706 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags); 5707 if (kvm->arch.vpit) 5708 r = 0; 5709 create_pit_unlock: 5710 mutex_unlock(&kvm->lock); 5711 break; 5712 case KVM_GET_IRQCHIP: { 5713 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */ 5714 struct kvm_irqchip *chip; 5715 5716 chip = memdup_user(argp, sizeof(*chip)); 5717 if (IS_ERR(chip)) { 5718 r = PTR_ERR(chip); 5719 goto out; 5720 } 5721 5722 r = -ENXIO; 5723 if (!irqchip_kernel(kvm)) 5724 goto get_irqchip_out; 5725 r = kvm_vm_ioctl_get_irqchip(kvm, chip); 5726 if (r) 5727 goto get_irqchip_out; 5728 r = -EFAULT; 5729 if (copy_to_user(argp, chip, sizeof(*chip))) 5730 goto get_irqchip_out; 5731 r = 0; 5732 get_irqchip_out: 5733 kfree(chip); 5734 break; 5735 } 5736 case KVM_SET_IRQCHIP: { 5737 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */ 5738 struct kvm_irqchip *chip; 5739 5740 chip = memdup_user(argp, sizeof(*chip)); 5741 if (IS_ERR(chip)) { 5742 r = PTR_ERR(chip); 5743 goto out; 5744 } 5745 5746 r = -ENXIO; 5747 if (!irqchip_kernel(kvm)) 5748 goto set_irqchip_out; 5749 r = kvm_vm_ioctl_set_irqchip(kvm, chip); 5750 set_irqchip_out: 5751 kfree(chip); 5752 break; 5753 } 5754 case KVM_GET_PIT: { 5755 r = -EFAULT; 5756 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state))) 5757 goto out; 5758 r = -ENXIO; 5759 if (!kvm->arch.vpit) 5760 goto out; 5761 r = kvm_vm_ioctl_get_pit(kvm, &u.ps); 5762 if (r) 5763 goto out; 5764 r = -EFAULT; 5765 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state))) 5766 goto out; 5767 r = 0; 5768 break; 5769 } 5770 case KVM_SET_PIT: { 5771 r = -EFAULT; 5772 if (copy_from_user(&u.ps, argp, sizeof(u.ps))) 5773 goto out; 5774 mutex_lock(&kvm->lock); 5775 r = -ENXIO; 5776 if (!kvm->arch.vpit) 5777 goto set_pit_out; 5778 r = kvm_vm_ioctl_set_pit(kvm, &u.ps); 5779 set_pit_out: 5780 mutex_unlock(&kvm->lock); 5781 break; 5782 } 5783 case KVM_GET_PIT2: { 5784 r = -ENXIO; 5785 if (!kvm->arch.vpit) 5786 goto out; 5787 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2); 5788 if (r) 5789 goto out; 5790 r = -EFAULT; 5791 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2))) 5792 goto out; 5793 r = 0; 5794 break; 5795 } 5796 case KVM_SET_PIT2: { 5797 r = -EFAULT; 5798 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2))) 5799 goto out; 5800 mutex_lock(&kvm->lock); 5801 r = -ENXIO; 5802 if (!kvm->arch.vpit) 5803 goto set_pit2_out; 5804 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2); 5805 set_pit2_out: 5806 mutex_unlock(&kvm->lock); 5807 break; 5808 } 5809 case KVM_REINJECT_CONTROL: { 5810 struct kvm_reinject_control control; 5811 r = -EFAULT; 5812 if (copy_from_user(&control, argp, sizeof(control))) 5813 goto out; 5814 r = -ENXIO; 5815 if (!kvm->arch.vpit) 5816 goto out; 5817 r = kvm_vm_ioctl_reinject(kvm, &control); 5818 break; 5819 } 5820 case KVM_SET_BOOT_CPU_ID: 5821 r = 0; 5822 mutex_lock(&kvm->lock); 5823 if (kvm->created_vcpus) 5824 r = -EBUSY; 5825 else 5826 kvm->arch.bsp_vcpu_id = arg; 5827 mutex_unlock(&kvm->lock); 5828 break; 5829 #ifdef CONFIG_KVM_XEN 5830 case KVM_XEN_HVM_CONFIG: { 5831 struct kvm_xen_hvm_config xhc; 5832 r = -EFAULT; 5833 if (copy_from_user(&xhc, argp, sizeof(xhc))) 5834 goto out; 5835 r = kvm_xen_hvm_config(kvm, &xhc); 5836 break; 5837 } 5838 case KVM_XEN_HVM_GET_ATTR: { 5839 struct kvm_xen_hvm_attr xha; 5840 5841 r = -EFAULT; 5842 if (copy_from_user(&xha, argp, sizeof(xha))) 5843 goto out; 5844 r = kvm_xen_hvm_get_attr(kvm, &xha); 5845 if (!r && copy_to_user(argp, &xha, sizeof(xha))) 5846 r = -EFAULT; 5847 break; 5848 } 5849 case KVM_XEN_HVM_SET_ATTR: { 5850 struct kvm_xen_hvm_attr xha; 5851 5852 r = -EFAULT; 5853 if (copy_from_user(&xha, argp, sizeof(xha))) 5854 goto out; 5855 r = kvm_xen_hvm_set_attr(kvm, &xha); 5856 break; 5857 } 5858 #endif 5859 case KVM_SET_CLOCK: { 5860 struct kvm_arch *ka = &kvm->arch; 5861 struct kvm_clock_data user_ns; 5862 u64 now_ns; 5863 5864 r = -EFAULT; 5865 if (copy_from_user(&user_ns, argp, sizeof(user_ns))) 5866 goto out; 5867 5868 r = -EINVAL; 5869 if (user_ns.flags) 5870 goto out; 5871 5872 r = 0; 5873 /* 5874 * TODO: userspace has to take care of races with VCPU_RUN, so 5875 * kvm_gen_update_masterclock() can be cut down to locked 5876 * pvclock_update_vm_gtod_copy(). 5877 */ 5878 kvm_gen_update_masterclock(kvm); 5879 5880 /* 5881 * This pairs with kvm_guest_time_update(): when masterclock is 5882 * in use, we use master_kernel_ns + kvmclock_offset to set 5883 * unsigned 'system_time' so if we use get_kvmclock_ns() (which 5884 * is slightly ahead) here we risk going negative on unsigned 5885 * 'system_time' when 'user_ns.clock' is very small. 5886 */ 5887 spin_lock_irq(&ka->pvclock_gtod_sync_lock); 5888 if (kvm->arch.use_master_clock) 5889 now_ns = ka->master_kernel_ns; 5890 else 5891 now_ns = get_kvmclock_base_ns(); 5892 ka->kvmclock_offset = user_ns.clock - now_ns; 5893 spin_unlock_irq(&ka->pvclock_gtod_sync_lock); 5894 5895 kvm_make_all_cpus_request(kvm, KVM_REQ_CLOCK_UPDATE); 5896 break; 5897 } 5898 case KVM_GET_CLOCK: { 5899 struct kvm_clock_data user_ns; 5900 u64 now_ns; 5901 5902 now_ns = get_kvmclock_ns(kvm); 5903 user_ns.clock = now_ns; 5904 user_ns.flags = kvm->arch.use_master_clock ? KVM_CLOCK_TSC_STABLE : 0; 5905 memset(&user_ns.pad, 0, sizeof(user_ns.pad)); 5906 5907 r = -EFAULT; 5908 if (copy_to_user(argp, &user_ns, sizeof(user_ns))) 5909 goto out; 5910 r = 0; 5911 break; 5912 } 5913 case KVM_MEMORY_ENCRYPT_OP: { 5914 r = -ENOTTY; 5915 if (kvm_x86_ops.mem_enc_op) 5916 r = static_call(kvm_x86_mem_enc_op)(kvm, argp); 5917 break; 5918 } 5919 case KVM_MEMORY_ENCRYPT_REG_REGION: { 5920 struct kvm_enc_region region; 5921 5922 r = -EFAULT; 5923 if (copy_from_user(®ion, argp, sizeof(region))) 5924 goto out; 5925 5926 r = -ENOTTY; 5927 if (kvm_x86_ops.mem_enc_reg_region) 5928 r = static_call(kvm_x86_mem_enc_reg_region)(kvm, ®ion); 5929 break; 5930 } 5931 case KVM_MEMORY_ENCRYPT_UNREG_REGION: { 5932 struct kvm_enc_region region; 5933 5934 r = -EFAULT; 5935 if (copy_from_user(®ion, argp, sizeof(region))) 5936 goto out; 5937 5938 r = -ENOTTY; 5939 if (kvm_x86_ops.mem_enc_unreg_region) 5940 r = static_call(kvm_x86_mem_enc_unreg_region)(kvm, ®ion); 5941 break; 5942 } 5943 case KVM_HYPERV_EVENTFD: { 5944 struct kvm_hyperv_eventfd hvevfd; 5945 5946 r = -EFAULT; 5947 if (copy_from_user(&hvevfd, argp, sizeof(hvevfd))) 5948 goto out; 5949 r = kvm_vm_ioctl_hv_eventfd(kvm, &hvevfd); 5950 break; 5951 } 5952 case KVM_SET_PMU_EVENT_FILTER: 5953 r = kvm_vm_ioctl_set_pmu_event_filter(kvm, argp); 5954 break; 5955 case KVM_X86_SET_MSR_FILTER: 5956 r = kvm_vm_ioctl_set_msr_filter(kvm, argp); 5957 break; 5958 default: 5959 r = -ENOTTY; 5960 } 5961 out: 5962 return r; 5963 } 5964 5965 static void kvm_init_msr_list(void) 5966 { 5967 struct x86_pmu_capability x86_pmu; 5968 u32 dummy[2]; 5969 unsigned i; 5970 5971 BUILD_BUG_ON_MSG(INTEL_PMC_MAX_FIXED != 4, 5972 "Please update the fixed PMCs in msrs_to_saved_all[]"); 5973 5974 perf_get_x86_pmu_capability(&x86_pmu); 5975 5976 num_msrs_to_save = 0; 5977 num_emulated_msrs = 0; 5978 num_msr_based_features = 0; 5979 5980 for (i = 0; i < ARRAY_SIZE(msrs_to_save_all); i++) { 5981 if (rdmsr_safe(msrs_to_save_all[i], &dummy[0], &dummy[1]) < 0) 5982 continue; 5983 5984 /* 5985 * Even MSRs that are valid in the host may not be exposed 5986 * to the guests in some cases. 5987 */ 5988 switch (msrs_to_save_all[i]) { 5989 case MSR_IA32_BNDCFGS: 5990 if (!kvm_mpx_supported()) 5991 continue; 5992 break; 5993 case MSR_TSC_AUX: 5994 if (!kvm_cpu_cap_has(X86_FEATURE_RDTSCP) && 5995 !kvm_cpu_cap_has(X86_FEATURE_RDPID)) 5996 continue; 5997 break; 5998 case MSR_IA32_UMWAIT_CONTROL: 5999 if (!kvm_cpu_cap_has(X86_FEATURE_WAITPKG)) 6000 continue; 6001 break; 6002 case MSR_IA32_RTIT_CTL: 6003 case MSR_IA32_RTIT_STATUS: 6004 if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT)) 6005 continue; 6006 break; 6007 case MSR_IA32_RTIT_CR3_MATCH: 6008 if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT) || 6009 !intel_pt_validate_hw_cap(PT_CAP_cr3_filtering)) 6010 continue; 6011 break; 6012 case MSR_IA32_RTIT_OUTPUT_BASE: 6013 case MSR_IA32_RTIT_OUTPUT_MASK: 6014 if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT) || 6015 (!intel_pt_validate_hw_cap(PT_CAP_topa_output) && 6016 !intel_pt_validate_hw_cap(PT_CAP_single_range_output))) 6017 continue; 6018 break; 6019 case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B: 6020 if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT) || 6021 msrs_to_save_all[i] - MSR_IA32_RTIT_ADDR0_A >= 6022 intel_pt_validate_hw_cap(PT_CAP_num_address_ranges) * 2) 6023 continue; 6024 break; 6025 case MSR_ARCH_PERFMON_PERFCTR0 ... MSR_ARCH_PERFMON_PERFCTR0 + 17: 6026 if (msrs_to_save_all[i] - MSR_ARCH_PERFMON_PERFCTR0 >= 6027 min(INTEL_PMC_MAX_GENERIC, x86_pmu.num_counters_gp)) 6028 continue; 6029 break; 6030 case MSR_ARCH_PERFMON_EVENTSEL0 ... MSR_ARCH_PERFMON_EVENTSEL0 + 17: 6031 if (msrs_to_save_all[i] - MSR_ARCH_PERFMON_EVENTSEL0 >= 6032 min(INTEL_PMC_MAX_GENERIC, x86_pmu.num_counters_gp)) 6033 continue; 6034 break; 6035 default: 6036 break; 6037 } 6038 6039 msrs_to_save[num_msrs_to_save++] = msrs_to_save_all[i]; 6040 } 6041 6042 for (i = 0; i < ARRAY_SIZE(emulated_msrs_all); i++) { 6043 if (!static_call(kvm_x86_has_emulated_msr)(NULL, emulated_msrs_all[i])) 6044 continue; 6045 6046 emulated_msrs[num_emulated_msrs++] = emulated_msrs_all[i]; 6047 } 6048 6049 for (i = 0; i < ARRAY_SIZE(msr_based_features_all); i++) { 6050 struct kvm_msr_entry msr; 6051 6052 msr.index = msr_based_features_all[i]; 6053 if (kvm_get_msr_feature(&msr)) 6054 continue; 6055 6056 msr_based_features[num_msr_based_features++] = msr_based_features_all[i]; 6057 } 6058 } 6059 6060 static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len, 6061 const void *v) 6062 { 6063 int handled = 0; 6064 int n; 6065 6066 do { 6067 n = min(len, 8); 6068 if (!(lapic_in_kernel(vcpu) && 6069 !kvm_iodevice_write(vcpu, &vcpu->arch.apic->dev, addr, n, v)) 6070 && kvm_io_bus_write(vcpu, KVM_MMIO_BUS, addr, n, v)) 6071 break; 6072 handled += n; 6073 addr += n; 6074 len -= n; 6075 v += n; 6076 } while (len); 6077 6078 return handled; 6079 } 6080 6081 static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v) 6082 { 6083 int handled = 0; 6084 int n; 6085 6086 do { 6087 n = min(len, 8); 6088 if (!(lapic_in_kernel(vcpu) && 6089 !kvm_iodevice_read(vcpu, &vcpu->arch.apic->dev, 6090 addr, n, v)) 6091 && kvm_io_bus_read(vcpu, KVM_MMIO_BUS, addr, n, v)) 6092 break; 6093 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, v); 6094 handled += n; 6095 addr += n; 6096 len -= n; 6097 v += n; 6098 } while (len); 6099 6100 return handled; 6101 } 6102 6103 static void kvm_set_segment(struct kvm_vcpu *vcpu, 6104 struct kvm_segment *var, int seg) 6105 { 6106 static_call(kvm_x86_set_segment)(vcpu, var, seg); 6107 } 6108 6109 void kvm_get_segment(struct kvm_vcpu *vcpu, 6110 struct kvm_segment *var, int seg) 6111 { 6112 static_call(kvm_x86_get_segment)(vcpu, var, seg); 6113 } 6114 6115 gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access, 6116 struct x86_exception *exception) 6117 { 6118 gpa_t t_gpa; 6119 6120 BUG_ON(!mmu_is_nested(vcpu)); 6121 6122 /* NPT walks are always user-walks */ 6123 access |= PFERR_USER_MASK; 6124 t_gpa = vcpu->arch.mmu->gva_to_gpa(vcpu, gpa, access, exception); 6125 6126 return t_gpa; 6127 } 6128 6129 gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva, 6130 struct x86_exception *exception) 6131 { 6132 u32 access = (static_call(kvm_x86_get_cpl)(vcpu) == 3) ? PFERR_USER_MASK : 0; 6133 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception); 6134 } 6135 EXPORT_SYMBOL_GPL(kvm_mmu_gva_to_gpa_read); 6136 6137 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva, 6138 struct x86_exception *exception) 6139 { 6140 u32 access = (static_call(kvm_x86_get_cpl)(vcpu) == 3) ? PFERR_USER_MASK : 0; 6141 access |= PFERR_FETCH_MASK; 6142 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception); 6143 } 6144 6145 gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva, 6146 struct x86_exception *exception) 6147 { 6148 u32 access = (static_call(kvm_x86_get_cpl)(vcpu) == 3) ? PFERR_USER_MASK : 0; 6149 access |= PFERR_WRITE_MASK; 6150 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception); 6151 } 6152 EXPORT_SYMBOL_GPL(kvm_mmu_gva_to_gpa_write); 6153 6154 /* uses this to access any guest's mapped memory without checking CPL */ 6155 gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva, 6156 struct x86_exception *exception) 6157 { 6158 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception); 6159 } 6160 6161 static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes, 6162 struct kvm_vcpu *vcpu, u32 access, 6163 struct x86_exception *exception) 6164 { 6165 void *data = val; 6166 int r = X86EMUL_CONTINUE; 6167 6168 while (bytes) { 6169 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access, 6170 exception); 6171 unsigned offset = addr & (PAGE_SIZE-1); 6172 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset); 6173 int ret; 6174 6175 if (gpa == UNMAPPED_GVA) 6176 return X86EMUL_PROPAGATE_FAULT; 6177 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, data, 6178 offset, toread); 6179 if (ret < 0) { 6180 r = X86EMUL_IO_NEEDED; 6181 goto out; 6182 } 6183 6184 bytes -= toread; 6185 data += toread; 6186 addr += toread; 6187 } 6188 out: 6189 return r; 6190 } 6191 6192 /* used for instruction fetching */ 6193 static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt, 6194 gva_t addr, void *val, unsigned int bytes, 6195 struct x86_exception *exception) 6196 { 6197 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 6198 u32 access = (static_call(kvm_x86_get_cpl)(vcpu) == 3) ? PFERR_USER_MASK : 0; 6199 unsigned offset; 6200 int ret; 6201 6202 /* Inline kvm_read_guest_virt_helper for speed. */ 6203 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access|PFERR_FETCH_MASK, 6204 exception); 6205 if (unlikely(gpa == UNMAPPED_GVA)) 6206 return X86EMUL_PROPAGATE_FAULT; 6207 6208 offset = addr & (PAGE_SIZE-1); 6209 if (WARN_ON(offset + bytes > PAGE_SIZE)) 6210 bytes = (unsigned)PAGE_SIZE - offset; 6211 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, val, 6212 offset, bytes); 6213 if (unlikely(ret < 0)) 6214 return X86EMUL_IO_NEEDED; 6215 6216 return X86EMUL_CONTINUE; 6217 } 6218 6219 int kvm_read_guest_virt(struct kvm_vcpu *vcpu, 6220 gva_t addr, void *val, unsigned int bytes, 6221 struct x86_exception *exception) 6222 { 6223 u32 access = (static_call(kvm_x86_get_cpl)(vcpu) == 3) ? PFERR_USER_MASK : 0; 6224 6225 /* 6226 * FIXME: this should call handle_emulation_failure if X86EMUL_IO_NEEDED 6227 * is returned, but our callers are not ready for that and they blindly 6228 * call kvm_inject_page_fault. Ensure that they at least do not leak 6229 * uninitialized kernel stack memory into cr2 and error code. 6230 */ 6231 memset(exception, 0, sizeof(*exception)); 6232 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access, 6233 exception); 6234 } 6235 EXPORT_SYMBOL_GPL(kvm_read_guest_virt); 6236 6237 static int emulator_read_std(struct x86_emulate_ctxt *ctxt, 6238 gva_t addr, void *val, unsigned int bytes, 6239 struct x86_exception *exception, bool system) 6240 { 6241 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 6242 u32 access = 0; 6243 6244 if (!system && static_call(kvm_x86_get_cpl)(vcpu) == 3) 6245 access |= PFERR_USER_MASK; 6246 6247 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access, exception); 6248 } 6249 6250 static int kvm_read_guest_phys_system(struct x86_emulate_ctxt *ctxt, 6251 unsigned long addr, void *val, unsigned int bytes) 6252 { 6253 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 6254 int r = kvm_vcpu_read_guest(vcpu, addr, val, bytes); 6255 6256 return r < 0 ? X86EMUL_IO_NEEDED : X86EMUL_CONTINUE; 6257 } 6258 6259 static int kvm_write_guest_virt_helper(gva_t addr, void *val, unsigned int bytes, 6260 struct kvm_vcpu *vcpu, u32 access, 6261 struct x86_exception *exception) 6262 { 6263 void *data = val; 6264 int r = X86EMUL_CONTINUE; 6265 6266 while (bytes) { 6267 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, 6268 access, 6269 exception); 6270 unsigned offset = addr & (PAGE_SIZE-1); 6271 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset); 6272 int ret; 6273 6274 if (gpa == UNMAPPED_GVA) 6275 return X86EMUL_PROPAGATE_FAULT; 6276 ret = kvm_vcpu_write_guest(vcpu, gpa, data, towrite); 6277 if (ret < 0) { 6278 r = X86EMUL_IO_NEEDED; 6279 goto out; 6280 } 6281 6282 bytes -= towrite; 6283 data += towrite; 6284 addr += towrite; 6285 } 6286 out: 6287 return r; 6288 } 6289 6290 static int emulator_write_std(struct x86_emulate_ctxt *ctxt, gva_t addr, void *val, 6291 unsigned int bytes, struct x86_exception *exception, 6292 bool system) 6293 { 6294 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 6295 u32 access = PFERR_WRITE_MASK; 6296 6297 if (!system && static_call(kvm_x86_get_cpl)(vcpu) == 3) 6298 access |= PFERR_USER_MASK; 6299 6300 return kvm_write_guest_virt_helper(addr, val, bytes, vcpu, 6301 access, exception); 6302 } 6303 6304 int kvm_write_guest_virt_system(struct kvm_vcpu *vcpu, gva_t addr, void *val, 6305 unsigned int bytes, struct x86_exception *exception) 6306 { 6307 /* kvm_write_guest_virt_system can pull in tons of pages. */ 6308 vcpu->arch.l1tf_flush_l1d = true; 6309 6310 return kvm_write_guest_virt_helper(addr, val, bytes, vcpu, 6311 PFERR_WRITE_MASK, exception); 6312 } 6313 EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system); 6314 6315 int handle_ud(struct kvm_vcpu *vcpu) 6316 { 6317 static const char kvm_emulate_prefix[] = { __KVM_EMULATE_PREFIX }; 6318 int emul_type = EMULTYPE_TRAP_UD; 6319 char sig[5]; /* ud2; .ascii "kvm" */ 6320 struct x86_exception e; 6321 6322 if (unlikely(!static_call(kvm_x86_can_emulate_instruction)(vcpu, NULL, 0))) 6323 return 1; 6324 6325 if (force_emulation_prefix && 6326 kvm_read_guest_virt(vcpu, kvm_get_linear_rip(vcpu), 6327 sig, sizeof(sig), &e) == 0 && 6328 memcmp(sig, kvm_emulate_prefix, sizeof(sig)) == 0) { 6329 kvm_rip_write(vcpu, kvm_rip_read(vcpu) + sizeof(sig)); 6330 emul_type = EMULTYPE_TRAP_UD_FORCED; 6331 } 6332 6333 return kvm_emulate_instruction(vcpu, emul_type); 6334 } 6335 EXPORT_SYMBOL_GPL(handle_ud); 6336 6337 static int vcpu_is_mmio_gpa(struct kvm_vcpu *vcpu, unsigned long gva, 6338 gpa_t gpa, bool write) 6339 { 6340 /* For APIC access vmexit */ 6341 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE) 6342 return 1; 6343 6344 if (vcpu_match_mmio_gpa(vcpu, gpa)) { 6345 trace_vcpu_match_mmio(gva, gpa, write, true); 6346 return 1; 6347 } 6348 6349 return 0; 6350 } 6351 6352 static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva, 6353 gpa_t *gpa, struct x86_exception *exception, 6354 bool write) 6355 { 6356 u32 access = ((static_call(kvm_x86_get_cpl)(vcpu) == 3) ? PFERR_USER_MASK : 0) 6357 | (write ? PFERR_WRITE_MASK : 0); 6358 6359 /* 6360 * currently PKRU is only applied to ept enabled guest so 6361 * there is no pkey in EPT page table for L1 guest or EPT 6362 * shadow page table for L2 guest. 6363 */ 6364 if (vcpu_match_mmio_gva(vcpu, gva) 6365 && !permission_fault(vcpu, vcpu->arch.walk_mmu, 6366 vcpu->arch.mmio_access, 0, access)) { 6367 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT | 6368 (gva & (PAGE_SIZE - 1)); 6369 trace_vcpu_match_mmio(gva, *gpa, write, false); 6370 return 1; 6371 } 6372 6373 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception); 6374 6375 if (*gpa == UNMAPPED_GVA) 6376 return -1; 6377 6378 return vcpu_is_mmio_gpa(vcpu, gva, *gpa, write); 6379 } 6380 6381 int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa, 6382 const void *val, int bytes) 6383 { 6384 int ret; 6385 6386 ret = kvm_vcpu_write_guest(vcpu, gpa, val, bytes); 6387 if (ret < 0) 6388 return 0; 6389 kvm_page_track_write(vcpu, gpa, val, bytes); 6390 return 1; 6391 } 6392 6393 struct read_write_emulator_ops { 6394 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val, 6395 int bytes); 6396 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa, 6397 void *val, int bytes); 6398 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa, 6399 int bytes, void *val); 6400 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa, 6401 void *val, int bytes); 6402 bool write; 6403 }; 6404 6405 static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes) 6406 { 6407 if (vcpu->mmio_read_completed) { 6408 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes, 6409 vcpu->mmio_fragments[0].gpa, val); 6410 vcpu->mmio_read_completed = 0; 6411 return 1; 6412 } 6413 6414 return 0; 6415 } 6416 6417 static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa, 6418 void *val, int bytes) 6419 { 6420 return !kvm_vcpu_read_guest(vcpu, gpa, val, bytes); 6421 } 6422 6423 static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa, 6424 void *val, int bytes) 6425 { 6426 return emulator_write_phys(vcpu, gpa, val, bytes); 6427 } 6428 6429 static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val) 6430 { 6431 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, val); 6432 return vcpu_mmio_write(vcpu, gpa, bytes, val); 6433 } 6434 6435 static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, 6436 void *val, int bytes) 6437 { 6438 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, NULL); 6439 return X86EMUL_IO_NEEDED; 6440 } 6441 6442 static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, 6443 void *val, int bytes) 6444 { 6445 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0]; 6446 6447 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len)); 6448 return X86EMUL_CONTINUE; 6449 } 6450 6451 static const struct read_write_emulator_ops read_emultor = { 6452 .read_write_prepare = read_prepare, 6453 .read_write_emulate = read_emulate, 6454 .read_write_mmio = vcpu_mmio_read, 6455 .read_write_exit_mmio = read_exit_mmio, 6456 }; 6457 6458 static const struct read_write_emulator_ops write_emultor = { 6459 .read_write_emulate = write_emulate, 6460 .read_write_mmio = write_mmio, 6461 .read_write_exit_mmio = write_exit_mmio, 6462 .write = true, 6463 }; 6464 6465 static int emulator_read_write_onepage(unsigned long addr, void *val, 6466 unsigned int bytes, 6467 struct x86_exception *exception, 6468 struct kvm_vcpu *vcpu, 6469 const struct read_write_emulator_ops *ops) 6470 { 6471 gpa_t gpa; 6472 int handled, ret; 6473 bool write = ops->write; 6474 struct kvm_mmio_fragment *frag; 6475 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt; 6476 6477 /* 6478 * If the exit was due to a NPF we may already have a GPA. 6479 * If the GPA is present, use it to avoid the GVA to GPA table walk. 6480 * Note, this cannot be used on string operations since string 6481 * operation using rep will only have the initial GPA from the NPF 6482 * occurred. 6483 */ 6484 if (ctxt->gpa_available && emulator_can_use_gpa(ctxt) && 6485 (addr & ~PAGE_MASK) == (ctxt->gpa_val & ~PAGE_MASK)) { 6486 gpa = ctxt->gpa_val; 6487 ret = vcpu_is_mmio_gpa(vcpu, addr, gpa, write); 6488 } else { 6489 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write); 6490 if (ret < 0) 6491 return X86EMUL_PROPAGATE_FAULT; 6492 } 6493 6494 if (!ret && ops->read_write_emulate(vcpu, gpa, val, bytes)) 6495 return X86EMUL_CONTINUE; 6496 6497 /* 6498 * Is this MMIO handled locally? 6499 */ 6500 handled = ops->read_write_mmio(vcpu, gpa, bytes, val); 6501 if (handled == bytes) 6502 return X86EMUL_CONTINUE; 6503 6504 gpa += handled; 6505 bytes -= handled; 6506 val += handled; 6507 6508 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS); 6509 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++]; 6510 frag->gpa = gpa; 6511 frag->data = val; 6512 frag->len = bytes; 6513 return X86EMUL_CONTINUE; 6514 } 6515 6516 static int emulator_read_write(struct x86_emulate_ctxt *ctxt, 6517 unsigned long addr, 6518 void *val, unsigned int bytes, 6519 struct x86_exception *exception, 6520 const struct read_write_emulator_ops *ops) 6521 { 6522 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 6523 gpa_t gpa; 6524 int rc; 6525 6526 if (ops->read_write_prepare && 6527 ops->read_write_prepare(vcpu, val, bytes)) 6528 return X86EMUL_CONTINUE; 6529 6530 vcpu->mmio_nr_fragments = 0; 6531 6532 /* Crossing a page boundary? */ 6533 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) { 6534 int now; 6535 6536 now = -addr & ~PAGE_MASK; 6537 rc = emulator_read_write_onepage(addr, val, now, exception, 6538 vcpu, ops); 6539 6540 if (rc != X86EMUL_CONTINUE) 6541 return rc; 6542 addr += now; 6543 if (ctxt->mode != X86EMUL_MODE_PROT64) 6544 addr = (u32)addr; 6545 val += now; 6546 bytes -= now; 6547 } 6548 6549 rc = emulator_read_write_onepage(addr, val, bytes, exception, 6550 vcpu, ops); 6551 if (rc != X86EMUL_CONTINUE) 6552 return rc; 6553 6554 if (!vcpu->mmio_nr_fragments) 6555 return rc; 6556 6557 gpa = vcpu->mmio_fragments[0].gpa; 6558 6559 vcpu->mmio_needed = 1; 6560 vcpu->mmio_cur_fragment = 0; 6561 6562 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len); 6563 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write; 6564 vcpu->run->exit_reason = KVM_EXIT_MMIO; 6565 vcpu->run->mmio.phys_addr = gpa; 6566 6567 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes); 6568 } 6569 6570 static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt, 6571 unsigned long addr, 6572 void *val, 6573 unsigned int bytes, 6574 struct x86_exception *exception) 6575 { 6576 return emulator_read_write(ctxt, addr, val, bytes, 6577 exception, &read_emultor); 6578 } 6579 6580 static int emulator_write_emulated(struct x86_emulate_ctxt *ctxt, 6581 unsigned long addr, 6582 const void *val, 6583 unsigned int bytes, 6584 struct x86_exception *exception) 6585 { 6586 return emulator_read_write(ctxt, addr, (void *)val, bytes, 6587 exception, &write_emultor); 6588 } 6589 6590 #define CMPXCHG_TYPE(t, ptr, old, new) \ 6591 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old)) 6592 6593 #ifdef CONFIG_X86_64 6594 # define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new) 6595 #else 6596 # define CMPXCHG64(ptr, old, new) \ 6597 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old)) 6598 #endif 6599 6600 static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt, 6601 unsigned long addr, 6602 const void *old, 6603 const void *new, 6604 unsigned int bytes, 6605 struct x86_exception *exception) 6606 { 6607 struct kvm_host_map map; 6608 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 6609 u64 page_line_mask; 6610 gpa_t gpa; 6611 char *kaddr; 6612 bool exchanged; 6613 6614 /* guests cmpxchg8b have to be emulated atomically */ 6615 if (bytes > 8 || (bytes & (bytes - 1))) 6616 goto emul_write; 6617 6618 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL); 6619 6620 if (gpa == UNMAPPED_GVA || 6621 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE) 6622 goto emul_write; 6623 6624 /* 6625 * Emulate the atomic as a straight write to avoid #AC if SLD is 6626 * enabled in the host and the access splits a cache line. 6627 */ 6628 if (boot_cpu_has(X86_FEATURE_SPLIT_LOCK_DETECT)) 6629 page_line_mask = ~(cache_line_size() - 1); 6630 else 6631 page_line_mask = PAGE_MASK; 6632 6633 if (((gpa + bytes - 1) & page_line_mask) != (gpa & page_line_mask)) 6634 goto emul_write; 6635 6636 if (kvm_vcpu_map(vcpu, gpa_to_gfn(gpa), &map)) 6637 goto emul_write; 6638 6639 kaddr = map.hva + offset_in_page(gpa); 6640 6641 switch (bytes) { 6642 case 1: 6643 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new); 6644 break; 6645 case 2: 6646 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new); 6647 break; 6648 case 4: 6649 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new); 6650 break; 6651 case 8: 6652 exchanged = CMPXCHG64(kaddr, old, new); 6653 break; 6654 default: 6655 BUG(); 6656 } 6657 6658 kvm_vcpu_unmap(vcpu, &map, true); 6659 6660 if (!exchanged) 6661 return X86EMUL_CMPXCHG_FAILED; 6662 6663 kvm_page_track_write(vcpu, gpa, new, bytes); 6664 6665 return X86EMUL_CONTINUE; 6666 6667 emul_write: 6668 printk_once(KERN_WARNING "kvm: emulating exchange as write\n"); 6669 6670 return emulator_write_emulated(ctxt, addr, new, bytes, exception); 6671 } 6672 6673 static int kernel_pio(struct kvm_vcpu *vcpu, void *pd) 6674 { 6675 int r = 0, i; 6676 6677 for (i = 0; i < vcpu->arch.pio.count; i++) { 6678 if (vcpu->arch.pio.in) 6679 r = kvm_io_bus_read(vcpu, KVM_PIO_BUS, vcpu->arch.pio.port, 6680 vcpu->arch.pio.size, pd); 6681 else 6682 r = kvm_io_bus_write(vcpu, KVM_PIO_BUS, 6683 vcpu->arch.pio.port, vcpu->arch.pio.size, 6684 pd); 6685 if (r) 6686 break; 6687 pd += vcpu->arch.pio.size; 6688 } 6689 return r; 6690 } 6691 6692 static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size, 6693 unsigned short port, void *val, 6694 unsigned int count, bool in) 6695 { 6696 vcpu->arch.pio.port = port; 6697 vcpu->arch.pio.in = in; 6698 vcpu->arch.pio.count = count; 6699 vcpu->arch.pio.size = size; 6700 6701 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) { 6702 vcpu->arch.pio.count = 0; 6703 return 1; 6704 } 6705 6706 vcpu->run->exit_reason = KVM_EXIT_IO; 6707 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT; 6708 vcpu->run->io.size = size; 6709 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE; 6710 vcpu->run->io.count = count; 6711 vcpu->run->io.port = port; 6712 6713 return 0; 6714 } 6715 6716 static int emulator_pio_in(struct kvm_vcpu *vcpu, int size, 6717 unsigned short port, void *val, unsigned int count) 6718 { 6719 int ret; 6720 6721 if (vcpu->arch.pio.count) 6722 goto data_avail; 6723 6724 memset(vcpu->arch.pio_data, 0, size * count); 6725 6726 ret = emulator_pio_in_out(vcpu, size, port, val, count, true); 6727 if (ret) { 6728 data_avail: 6729 memcpy(val, vcpu->arch.pio_data, size * count); 6730 trace_kvm_pio(KVM_PIO_IN, port, size, count, vcpu->arch.pio_data); 6731 vcpu->arch.pio.count = 0; 6732 return 1; 6733 } 6734 6735 return 0; 6736 } 6737 6738 static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt, 6739 int size, unsigned short port, void *val, 6740 unsigned int count) 6741 { 6742 return emulator_pio_in(emul_to_vcpu(ctxt), size, port, val, count); 6743 6744 } 6745 6746 static int emulator_pio_out(struct kvm_vcpu *vcpu, int size, 6747 unsigned short port, const void *val, 6748 unsigned int count) 6749 { 6750 memcpy(vcpu->arch.pio_data, val, size * count); 6751 trace_kvm_pio(KVM_PIO_OUT, port, size, count, vcpu->arch.pio_data); 6752 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false); 6753 } 6754 6755 static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt, 6756 int size, unsigned short port, 6757 const void *val, unsigned int count) 6758 { 6759 return emulator_pio_out(emul_to_vcpu(ctxt), size, port, val, count); 6760 } 6761 6762 static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg) 6763 { 6764 return static_call(kvm_x86_get_segment_base)(vcpu, seg); 6765 } 6766 6767 static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address) 6768 { 6769 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address); 6770 } 6771 6772 static int kvm_emulate_wbinvd_noskip(struct kvm_vcpu *vcpu) 6773 { 6774 if (!need_emulate_wbinvd(vcpu)) 6775 return X86EMUL_CONTINUE; 6776 6777 if (static_call(kvm_x86_has_wbinvd_exit)()) { 6778 int cpu = get_cpu(); 6779 6780 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask); 6781 on_each_cpu_mask(vcpu->arch.wbinvd_dirty_mask, 6782 wbinvd_ipi, NULL, 1); 6783 put_cpu(); 6784 cpumask_clear(vcpu->arch.wbinvd_dirty_mask); 6785 } else 6786 wbinvd(); 6787 return X86EMUL_CONTINUE; 6788 } 6789 6790 int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu) 6791 { 6792 kvm_emulate_wbinvd_noskip(vcpu); 6793 return kvm_skip_emulated_instruction(vcpu); 6794 } 6795 EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd); 6796 6797 6798 6799 static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt) 6800 { 6801 kvm_emulate_wbinvd_noskip(emul_to_vcpu(ctxt)); 6802 } 6803 6804 static void emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr, 6805 unsigned long *dest) 6806 { 6807 kvm_get_dr(emul_to_vcpu(ctxt), dr, dest); 6808 } 6809 6810 static int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr, 6811 unsigned long value) 6812 { 6813 6814 return kvm_set_dr(emul_to_vcpu(ctxt), dr, value); 6815 } 6816 6817 static u64 mk_cr_64(u64 curr_cr, u32 new_val) 6818 { 6819 return (curr_cr & ~((1ULL << 32) - 1)) | new_val; 6820 } 6821 6822 static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr) 6823 { 6824 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 6825 unsigned long value; 6826 6827 switch (cr) { 6828 case 0: 6829 value = kvm_read_cr0(vcpu); 6830 break; 6831 case 2: 6832 value = vcpu->arch.cr2; 6833 break; 6834 case 3: 6835 value = kvm_read_cr3(vcpu); 6836 break; 6837 case 4: 6838 value = kvm_read_cr4(vcpu); 6839 break; 6840 case 8: 6841 value = kvm_get_cr8(vcpu); 6842 break; 6843 default: 6844 kvm_err("%s: unexpected cr %u\n", __func__, cr); 6845 return 0; 6846 } 6847 6848 return value; 6849 } 6850 6851 static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val) 6852 { 6853 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 6854 int res = 0; 6855 6856 switch (cr) { 6857 case 0: 6858 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val)); 6859 break; 6860 case 2: 6861 vcpu->arch.cr2 = val; 6862 break; 6863 case 3: 6864 res = kvm_set_cr3(vcpu, val); 6865 break; 6866 case 4: 6867 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val)); 6868 break; 6869 case 8: 6870 res = kvm_set_cr8(vcpu, val); 6871 break; 6872 default: 6873 kvm_err("%s: unexpected cr %u\n", __func__, cr); 6874 res = -1; 6875 } 6876 6877 return res; 6878 } 6879 6880 static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt) 6881 { 6882 return static_call(kvm_x86_get_cpl)(emul_to_vcpu(ctxt)); 6883 } 6884 6885 static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt) 6886 { 6887 static_call(kvm_x86_get_gdt)(emul_to_vcpu(ctxt), dt); 6888 } 6889 6890 static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt) 6891 { 6892 static_call(kvm_x86_get_idt)(emul_to_vcpu(ctxt), dt); 6893 } 6894 6895 static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt) 6896 { 6897 static_call(kvm_x86_set_gdt)(emul_to_vcpu(ctxt), dt); 6898 } 6899 6900 static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt) 6901 { 6902 static_call(kvm_x86_set_idt)(emul_to_vcpu(ctxt), dt); 6903 } 6904 6905 static unsigned long emulator_get_cached_segment_base( 6906 struct x86_emulate_ctxt *ctxt, int seg) 6907 { 6908 return get_segment_base(emul_to_vcpu(ctxt), seg); 6909 } 6910 6911 static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector, 6912 struct desc_struct *desc, u32 *base3, 6913 int seg) 6914 { 6915 struct kvm_segment var; 6916 6917 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg); 6918 *selector = var.selector; 6919 6920 if (var.unusable) { 6921 memset(desc, 0, sizeof(*desc)); 6922 if (base3) 6923 *base3 = 0; 6924 return false; 6925 } 6926 6927 if (var.g) 6928 var.limit >>= 12; 6929 set_desc_limit(desc, var.limit); 6930 set_desc_base(desc, (unsigned long)var.base); 6931 #ifdef CONFIG_X86_64 6932 if (base3) 6933 *base3 = var.base >> 32; 6934 #endif 6935 desc->type = var.type; 6936 desc->s = var.s; 6937 desc->dpl = var.dpl; 6938 desc->p = var.present; 6939 desc->avl = var.avl; 6940 desc->l = var.l; 6941 desc->d = var.db; 6942 desc->g = var.g; 6943 6944 return true; 6945 } 6946 6947 static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector, 6948 struct desc_struct *desc, u32 base3, 6949 int seg) 6950 { 6951 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 6952 struct kvm_segment var; 6953 6954 var.selector = selector; 6955 var.base = get_desc_base(desc); 6956 #ifdef CONFIG_X86_64 6957 var.base |= ((u64)base3) << 32; 6958 #endif 6959 var.limit = get_desc_limit(desc); 6960 if (desc->g) 6961 var.limit = (var.limit << 12) | 0xfff; 6962 var.type = desc->type; 6963 var.dpl = desc->dpl; 6964 var.db = desc->d; 6965 var.s = desc->s; 6966 var.l = desc->l; 6967 var.g = desc->g; 6968 var.avl = desc->avl; 6969 var.present = desc->p; 6970 var.unusable = !var.present; 6971 var.padding = 0; 6972 6973 kvm_set_segment(vcpu, &var, seg); 6974 return; 6975 } 6976 6977 static int emulator_get_msr(struct x86_emulate_ctxt *ctxt, 6978 u32 msr_index, u64 *pdata) 6979 { 6980 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 6981 int r; 6982 6983 r = kvm_get_msr(vcpu, msr_index, pdata); 6984 6985 if (r && kvm_get_msr_user_space(vcpu, msr_index, r)) { 6986 /* Bounce to user space */ 6987 return X86EMUL_IO_NEEDED; 6988 } 6989 6990 return r; 6991 } 6992 6993 static int emulator_set_msr(struct x86_emulate_ctxt *ctxt, 6994 u32 msr_index, u64 data) 6995 { 6996 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 6997 int r; 6998 6999 r = kvm_set_msr(vcpu, msr_index, data); 7000 7001 if (r && kvm_set_msr_user_space(vcpu, msr_index, data, r)) { 7002 /* Bounce to user space */ 7003 return X86EMUL_IO_NEEDED; 7004 } 7005 7006 return r; 7007 } 7008 7009 static u64 emulator_get_smbase(struct x86_emulate_ctxt *ctxt) 7010 { 7011 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 7012 7013 return vcpu->arch.smbase; 7014 } 7015 7016 static void emulator_set_smbase(struct x86_emulate_ctxt *ctxt, u64 smbase) 7017 { 7018 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 7019 7020 vcpu->arch.smbase = smbase; 7021 } 7022 7023 static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt, 7024 u32 pmc) 7025 { 7026 return kvm_pmu_is_valid_rdpmc_ecx(emul_to_vcpu(ctxt), pmc); 7027 } 7028 7029 static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt, 7030 u32 pmc, u64 *pdata) 7031 { 7032 return kvm_pmu_rdpmc(emul_to_vcpu(ctxt), pmc, pdata); 7033 } 7034 7035 static void emulator_halt(struct x86_emulate_ctxt *ctxt) 7036 { 7037 emul_to_vcpu(ctxt)->arch.halt_request = 1; 7038 } 7039 7040 static int emulator_intercept(struct x86_emulate_ctxt *ctxt, 7041 struct x86_instruction_info *info, 7042 enum x86_intercept_stage stage) 7043 { 7044 return static_call(kvm_x86_check_intercept)(emul_to_vcpu(ctxt), info, stage, 7045 &ctxt->exception); 7046 } 7047 7048 static bool emulator_get_cpuid(struct x86_emulate_ctxt *ctxt, 7049 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx, 7050 bool exact_only) 7051 { 7052 return kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx, exact_only); 7053 } 7054 7055 static bool emulator_guest_has_long_mode(struct x86_emulate_ctxt *ctxt) 7056 { 7057 return guest_cpuid_has(emul_to_vcpu(ctxt), X86_FEATURE_LM); 7058 } 7059 7060 static bool emulator_guest_has_movbe(struct x86_emulate_ctxt *ctxt) 7061 { 7062 return guest_cpuid_has(emul_to_vcpu(ctxt), X86_FEATURE_MOVBE); 7063 } 7064 7065 static bool emulator_guest_has_fxsr(struct x86_emulate_ctxt *ctxt) 7066 { 7067 return guest_cpuid_has(emul_to_vcpu(ctxt), X86_FEATURE_FXSR); 7068 } 7069 7070 static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg) 7071 { 7072 return kvm_register_read_raw(emul_to_vcpu(ctxt), reg); 7073 } 7074 7075 static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val) 7076 { 7077 kvm_register_write_raw(emul_to_vcpu(ctxt), reg, val); 7078 } 7079 7080 static void emulator_set_nmi_mask(struct x86_emulate_ctxt *ctxt, bool masked) 7081 { 7082 static_call(kvm_x86_set_nmi_mask)(emul_to_vcpu(ctxt), masked); 7083 } 7084 7085 static unsigned emulator_get_hflags(struct x86_emulate_ctxt *ctxt) 7086 { 7087 return emul_to_vcpu(ctxt)->arch.hflags; 7088 } 7089 7090 static void emulator_set_hflags(struct x86_emulate_ctxt *ctxt, unsigned emul_flags) 7091 { 7092 emul_to_vcpu(ctxt)->arch.hflags = emul_flags; 7093 } 7094 7095 static int emulator_pre_leave_smm(struct x86_emulate_ctxt *ctxt, 7096 const char *smstate) 7097 { 7098 return static_call(kvm_x86_pre_leave_smm)(emul_to_vcpu(ctxt), smstate); 7099 } 7100 7101 static void emulator_post_leave_smm(struct x86_emulate_ctxt *ctxt) 7102 { 7103 kvm_smm_changed(emul_to_vcpu(ctxt)); 7104 } 7105 7106 static int emulator_set_xcr(struct x86_emulate_ctxt *ctxt, u32 index, u64 xcr) 7107 { 7108 return __kvm_set_xcr(emul_to_vcpu(ctxt), index, xcr); 7109 } 7110 7111 static const struct x86_emulate_ops emulate_ops = { 7112 .read_gpr = emulator_read_gpr, 7113 .write_gpr = emulator_write_gpr, 7114 .read_std = emulator_read_std, 7115 .write_std = emulator_write_std, 7116 .read_phys = kvm_read_guest_phys_system, 7117 .fetch = kvm_fetch_guest_virt, 7118 .read_emulated = emulator_read_emulated, 7119 .write_emulated = emulator_write_emulated, 7120 .cmpxchg_emulated = emulator_cmpxchg_emulated, 7121 .invlpg = emulator_invlpg, 7122 .pio_in_emulated = emulator_pio_in_emulated, 7123 .pio_out_emulated = emulator_pio_out_emulated, 7124 .get_segment = emulator_get_segment, 7125 .set_segment = emulator_set_segment, 7126 .get_cached_segment_base = emulator_get_cached_segment_base, 7127 .get_gdt = emulator_get_gdt, 7128 .get_idt = emulator_get_idt, 7129 .set_gdt = emulator_set_gdt, 7130 .set_idt = emulator_set_idt, 7131 .get_cr = emulator_get_cr, 7132 .set_cr = emulator_set_cr, 7133 .cpl = emulator_get_cpl, 7134 .get_dr = emulator_get_dr, 7135 .set_dr = emulator_set_dr, 7136 .get_smbase = emulator_get_smbase, 7137 .set_smbase = emulator_set_smbase, 7138 .set_msr = emulator_set_msr, 7139 .get_msr = emulator_get_msr, 7140 .check_pmc = emulator_check_pmc, 7141 .read_pmc = emulator_read_pmc, 7142 .halt = emulator_halt, 7143 .wbinvd = emulator_wbinvd, 7144 .fix_hypercall = emulator_fix_hypercall, 7145 .intercept = emulator_intercept, 7146 .get_cpuid = emulator_get_cpuid, 7147 .guest_has_long_mode = emulator_guest_has_long_mode, 7148 .guest_has_movbe = emulator_guest_has_movbe, 7149 .guest_has_fxsr = emulator_guest_has_fxsr, 7150 .set_nmi_mask = emulator_set_nmi_mask, 7151 .get_hflags = emulator_get_hflags, 7152 .set_hflags = emulator_set_hflags, 7153 .pre_leave_smm = emulator_pre_leave_smm, 7154 .post_leave_smm = emulator_post_leave_smm, 7155 .set_xcr = emulator_set_xcr, 7156 }; 7157 7158 static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask) 7159 { 7160 u32 int_shadow = static_call(kvm_x86_get_interrupt_shadow)(vcpu); 7161 /* 7162 * an sti; sti; sequence only disable interrupts for the first 7163 * instruction. So, if the last instruction, be it emulated or 7164 * not, left the system with the INT_STI flag enabled, it 7165 * means that the last instruction is an sti. We should not 7166 * leave the flag on in this case. The same goes for mov ss 7167 */ 7168 if (int_shadow & mask) 7169 mask = 0; 7170 if (unlikely(int_shadow || mask)) { 7171 static_call(kvm_x86_set_interrupt_shadow)(vcpu, mask); 7172 if (!mask) 7173 kvm_make_request(KVM_REQ_EVENT, vcpu); 7174 } 7175 } 7176 7177 static bool inject_emulated_exception(struct kvm_vcpu *vcpu) 7178 { 7179 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt; 7180 if (ctxt->exception.vector == PF_VECTOR) 7181 return kvm_inject_emulated_page_fault(vcpu, &ctxt->exception); 7182 7183 if (ctxt->exception.error_code_valid) 7184 kvm_queue_exception_e(vcpu, ctxt->exception.vector, 7185 ctxt->exception.error_code); 7186 else 7187 kvm_queue_exception(vcpu, ctxt->exception.vector); 7188 return false; 7189 } 7190 7191 static struct x86_emulate_ctxt *alloc_emulate_ctxt(struct kvm_vcpu *vcpu) 7192 { 7193 struct x86_emulate_ctxt *ctxt; 7194 7195 ctxt = kmem_cache_zalloc(x86_emulator_cache, GFP_KERNEL_ACCOUNT); 7196 if (!ctxt) { 7197 pr_err("kvm: failed to allocate vcpu's emulator\n"); 7198 return NULL; 7199 } 7200 7201 ctxt->vcpu = vcpu; 7202 ctxt->ops = &emulate_ops; 7203 vcpu->arch.emulate_ctxt = ctxt; 7204 7205 return ctxt; 7206 } 7207 7208 static void init_emulate_ctxt(struct kvm_vcpu *vcpu) 7209 { 7210 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt; 7211 int cs_db, cs_l; 7212 7213 static_call(kvm_x86_get_cs_db_l_bits)(vcpu, &cs_db, &cs_l); 7214 7215 ctxt->gpa_available = false; 7216 ctxt->eflags = kvm_get_rflags(vcpu); 7217 ctxt->tf = (ctxt->eflags & X86_EFLAGS_TF) != 0; 7218 7219 ctxt->eip = kvm_rip_read(vcpu); 7220 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL : 7221 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 : 7222 (cs_l && is_long_mode(vcpu)) ? X86EMUL_MODE_PROT64 : 7223 cs_db ? X86EMUL_MODE_PROT32 : 7224 X86EMUL_MODE_PROT16; 7225 BUILD_BUG_ON(HF_GUEST_MASK != X86EMUL_GUEST_MASK); 7226 BUILD_BUG_ON(HF_SMM_MASK != X86EMUL_SMM_MASK); 7227 BUILD_BUG_ON(HF_SMM_INSIDE_NMI_MASK != X86EMUL_SMM_INSIDE_NMI_MASK); 7228 7229 init_decode_cache(ctxt); 7230 vcpu->arch.emulate_regs_need_sync_from_vcpu = false; 7231 } 7232 7233 void kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip) 7234 { 7235 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt; 7236 int ret; 7237 7238 init_emulate_ctxt(vcpu); 7239 7240 ctxt->op_bytes = 2; 7241 ctxt->ad_bytes = 2; 7242 ctxt->_eip = ctxt->eip + inc_eip; 7243 ret = emulate_int_real(ctxt, irq); 7244 7245 if (ret != X86EMUL_CONTINUE) { 7246 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); 7247 } else { 7248 ctxt->eip = ctxt->_eip; 7249 kvm_rip_write(vcpu, ctxt->eip); 7250 kvm_set_rflags(vcpu, ctxt->eflags); 7251 } 7252 } 7253 EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt); 7254 7255 static int handle_emulation_failure(struct kvm_vcpu *vcpu, int emulation_type) 7256 { 7257 ++vcpu->stat.insn_emulation_fail; 7258 trace_kvm_emulate_insn_failed(vcpu); 7259 7260 if (emulation_type & EMULTYPE_VMWARE_GP) { 7261 kvm_queue_exception_e(vcpu, GP_VECTOR, 0); 7262 return 1; 7263 } 7264 7265 if (emulation_type & EMULTYPE_SKIP) { 7266 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR; 7267 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION; 7268 vcpu->run->internal.ndata = 0; 7269 return 0; 7270 } 7271 7272 kvm_queue_exception(vcpu, UD_VECTOR); 7273 7274 if (!is_guest_mode(vcpu) && static_call(kvm_x86_get_cpl)(vcpu) == 0) { 7275 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR; 7276 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION; 7277 vcpu->run->internal.ndata = 0; 7278 return 0; 7279 } 7280 7281 return 1; 7282 } 7283 7284 static bool reexecute_instruction(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa, 7285 bool write_fault_to_shadow_pgtable, 7286 int emulation_type) 7287 { 7288 gpa_t gpa = cr2_or_gpa; 7289 kvm_pfn_t pfn; 7290 7291 if (!(emulation_type & EMULTYPE_ALLOW_RETRY_PF)) 7292 return false; 7293 7294 if (WARN_ON_ONCE(is_guest_mode(vcpu)) || 7295 WARN_ON_ONCE(!(emulation_type & EMULTYPE_PF))) 7296 return false; 7297 7298 if (!vcpu->arch.mmu->direct_map) { 7299 /* 7300 * Write permission should be allowed since only 7301 * write access need to be emulated. 7302 */ 7303 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2_or_gpa, NULL); 7304 7305 /* 7306 * If the mapping is invalid in guest, let cpu retry 7307 * it to generate fault. 7308 */ 7309 if (gpa == UNMAPPED_GVA) 7310 return true; 7311 } 7312 7313 /* 7314 * Do not retry the unhandleable instruction if it faults on the 7315 * readonly host memory, otherwise it will goto a infinite loop: 7316 * retry instruction -> write #PF -> emulation fail -> retry 7317 * instruction -> ... 7318 */ 7319 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa)); 7320 7321 /* 7322 * If the instruction failed on the error pfn, it can not be fixed, 7323 * report the error to userspace. 7324 */ 7325 if (is_error_noslot_pfn(pfn)) 7326 return false; 7327 7328 kvm_release_pfn_clean(pfn); 7329 7330 /* The instructions are well-emulated on direct mmu. */ 7331 if (vcpu->arch.mmu->direct_map) { 7332 unsigned int indirect_shadow_pages; 7333 7334 write_lock(&vcpu->kvm->mmu_lock); 7335 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages; 7336 write_unlock(&vcpu->kvm->mmu_lock); 7337 7338 if (indirect_shadow_pages) 7339 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa)); 7340 7341 return true; 7342 } 7343 7344 /* 7345 * if emulation was due to access to shadowed page table 7346 * and it failed try to unshadow page and re-enter the 7347 * guest to let CPU execute the instruction. 7348 */ 7349 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa)); 7350 7351 /* 7352 * If the access faults on its page table, it can not 7353 * be fixed by unprotecting shadow page and it should 7354 * be reported to userspace. 7355 */ 7356 return !write_fault_to_shadow_pgtable; 7357 } 7358 7359 static bool retry_instruction(struct x86_emulate_ctxt *ctxt, 7360 gpa_t cr2_or_gpa, int emulation_type) 7361 { 7362 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 7363 unsigned long last_retry_eip, last_retry_addr, gpa = cr2_or_gpa; 7364 7365 last_retry_eip = vcpu->arch.last_retry_eip; 7366 last_retry_addr = vcpu->arch.last_retry_addr; 7367 7368 /* 7369 * If the emulation is caused by #PF and it is non-page_table 7370 * writing instruction, it means the VM-EXIT is caused by shadow 7371 * page protected, we can zap the shadow page and retry this 7372 * instruction directly. 7373 * 7374 * Note: if the guest uses a non-page-table modifying instruction 7375 * on the PDE that points to the instruction, then we will unmap 7376 * the instruction and go to an infinite loop. So, we cache the 7377 * last retried eip and the last fault address, if we meet the eip 7378 * and the address again, we can break out of the potential infinite 7379 * loop. 7380 */ 7381 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0; 7382 7383 if (!(emulation_type & EMULTYPE_ALLOW_RETRY_PF)) 7384 return false; 7385 7386 if (WARN_ON_ONCE(is_guest_mode(vcpu)) || 7387 WARN_ON_ONCE(!(emulation_type & EMULTYPE_PF))) 7388 return false; 7389 7390 if (x86_page_table_writing_insn(ctxt)) 7391 return false; 7392 7393 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2_or_gpa) 7394 return false; 7395 7396 vcpu->arch.last_retry_eip = ctxt->eip; 7397 vcpu->arch.last_retry_addr = cr2_or_gpa; 7398 7399 if (!vcpu->arch.mmu->direct_map) 7400 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2_or_gpa, NULL); 7401 7402 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa)); 7403 7404 return true; 7405 } 7406 7407 static int complete_emulated_mmio(struct kvm_vcpu *vcpu); 7408 static int complete_emulated_pio(struct kvm_vcpu *vcpu); 7409 7410 static void kvm_smm_changed(struct kvm_vcpu *vcpu) 7411 { 7412 if (!(vcpu->arch.hflags & HF_SMM_MASK)) { 7413 /* This is a good place to trace that we are exiting SMM. */ 7414 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, false); 7415 7416 /* Process a latched INIT or SMI, if any. */ 7417 kvm_make_request(KVM_REQ_EVENT, vcpu); 7418 } 7419 7420 kvm_mmu_reset_context(vcpu); 7421 } 7422 7423 static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7, 7424 unsigned long *db) 7425 { 7426 u32 dr6 = 0; 7427 int i; 7428 u32 enable, rwlen; 7429 7430 enable = dr7; 7431 rwlen = dr7 >> 16; 7432 for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4) 7433 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr) 7434 dr6 |= (1 << i); 7435 return dr6; 7436 } 7437 7438 static int kvm_vcpu_do_singlestep(struct kvm_vcpu *vcpu) 7439 { 7440 struct kvm_run *kvm_run = vcpu->run; 7441 7442 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) { 7443 kvm_run->debug.arch.dr6 = DR6_BS | DR6_ACTIVE_LOW; 7444 kvm_run->debug.arch.pc = kvm_get_linear_rip(vcpu); 7445 kvm_run->debug.arch.exception = DB_VECTOR; 7446 kvm_run->exit_reason = KVM_EXIT_DEBUG; 7447 return 0; 7448 } 7449 kvm_queue_exception_p(vcpu, DB_VECTOR, DR6_BS); 7450 return 1; 7451 } 7452 7453 int kvm_skip_emulated_instruction(struct kvm_vcpu *vcpu) 7454 { 7455 unsigned long rflags = static_call(kvm_x86_get_rflags)(vcpu); 7456 int r; 7457 7458 r = static_call(kvm_x86_skip_emulated_instruction)(vcpu); 7459 if (unlikely(!r)) 7460 return 0; 7461 7462 /* 7463 * rflags is the old, "raw" value of the flags. The new value has 7464 * not been saved yet. 7465 * 7466 * This is correct even for TF set by the guest, because "the 7467 * processor will not generate this exception after the instruction 7468 * that sets the TF flag". 7469 */ 7470 if (unlikely(rflags & X86_EFLAGS_TF)) 7471 r = kvm_vcpu_do_singlestep(vcpu); 7472 return r; 7473 } 7474 EXPORT_SYMBOL_GPL(kvm_skip_emulated_instruction); 7475 7476 static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r) 7477 { 7478 if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) && 7479 (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) { 7480 struct kvm_run *kvm_run = vcpu->run; 7481 unsigned long eip = kvm_get_linear_rip(vcpu); 7482 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0, 7483 vcpu->arch.guest_debug_dr7, 7484 vcpu->arch.eff_db); 7485 7486 if (dr6 != 0) { 7487 kvm_run->debug.arch.dr6 = dr6 | DR6_ACTIVE_LOW; 7488 kvm_run->debug.arch.pc = eip; 7489 kvm_run->debug.arch.exception = DB_VECTOR; 7490 kvm_run->exit_reason = KVM_EXIT_DEBUG; 7491 *r = 0; 7492 return true; 7493 } 7494 } 7495 7496 if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) && 7497 !(kvm_get_rflags(vcpu) & X86_EFLAGS_RF)) { 7498 unsigned long eip = kvm_get_linear_rip(vcpu); 7499 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0, 7500 vcpu->arch.dr7, 7501 vcpu->arch.db); 7502 7503 if (dr6 != 0) { 7504 kvm_queue_exception_p(vcpu, DB_VECTOR, dr6); 7505 *r = 1; 7506 return true; 7507 } 7508 } 7509 7510 return false; 7511 } 7512 7513 static bool is_vmware_backdoor_opcode(struct x86_emulate_ctxt *ctxt) 7514 { 7515 switch (ctxt->opcode_len) { 7516 case 1: 7517 switch (ctxt->b) { 7518 case 0xe4: /* IN */ 7519 case 0xe5: 7520 case 0xec: 7521 case 0xed: 7522 case 0xe6: /* OUT */ 7523 case 0xe7: 7524 case 0xee: 7525 case 0xef: 7526 case 0x6c: /* INS */ 7527 case 0x6d: 7528 case 0x6e: /* OUTS */ 7529 case 0x6f: 7530 return true; 7531 } 7532 break; 7533 case 2: 7534 switch (ctxt->b) { 7535 case 0x33: /* RDPMC */ 7536 return true; 7537 } 7538 break; 7539 } 7540 7541 return false; 7542 } 7543 7544 /* 7545 * Decode to be emulated instruction. Return EMULATION_OK if success. 7546 */ 7547 int x86_decode_emulated_instruction(struct kvm_vcpu *vcpu, int emulation_type, 7548 void *insn, int insn_len) 7549 { 7550 int r = EMULATION_OK; 7551 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt; 7552 7553 init_emulate_ctxt(vcpu); 7554 7555 /* 7556 * We will reenter on the same instruction since we do not set 7557 * complete_userspace_io. This does not handle watchpoints yet, 7558 * those would be handled in the emulate_ops. 7559 */ 7560 if (!(emulation_type & EMULTYPE_SKIP) && 7561 kvm_vcpu_check_breakpoint(vcpu, &r)) 7562 return r; 7563 7564 ctxt->interruptibility = 0; 7565 ctxt->have_exception = false; 7566 ctxt->exception.vector = -1; 7567 ctxt->perm_ok = false; 7568 7569 ctxt->ud = emulation_type & EMULTYPE_TRAP_UD; 7570 7571 r = x86_decode_insn(ctxt, insn, insn_len); 7572 7573 trace_kvm_emulate_insn_start(vcpu); 7574 ++vcpu->stat.insn_emulation; 7575 7576 return r; 7577 } 7578 EXPORT_SYMBOL_GPL(x86_decode_emulated_instruction); 7579 7580 int x86_emulate_instruction(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa, 7581 int emulation_type, void *insn, int insn_len) 7582 { 7583 int r; 7584 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt; 7585 bool writeback = true; 7586 bool write_fault_to_spt; 7587 7588 if (unlikely(!static_call(kvm_x86_can_emulate_instruction)(vcpu, insn, insn_len))) 7589 return 1; 7590 7591 vcpu->arch.l1tf_flush_l1d = true; 7592 7593 /* 7594 * Clear write_fault_to_shadow_pgtable here to ensure it is 7595 * never reused. 7596 */ 7597 write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable; 7598 vcpu->arch.write_fault_to_shadow_pgtable = false; 7599 7600 if (!(emulation_type & EMULTYPE_NO_DECODE)) { 7601 kvm_clear_exception_queue(vcpu); 7602 7603 r = x86_decode_emulated_instruction(vcpu, emulation_type, 7604 insn, insn_len); 7605 if (r != EMULATION_OK) { 7606 if ((emulation_type & EMULTYPE_TRAP_UD) || 7607 (emulation_type & EMULTYPE_TRAP_UD_FORCED)) { 7608 kvm_queue_exception(vcpu, UD_VECTOR); 7609 return 1; 7610 } 7611 if (reexecute_instruction(vcpu, cr2_or_gpa, 7612 write_fault_to_spt, 7613 emulation_type)) 7614 return 1; 7615 if (ctxt->have_exception) { 7616 /* 7617 * #UD should result in just EMULATION_FAILED, and trap-like 7618 * exception should not be encountered during decode. 7619 */ 7620 WARN_ON_ONCE(ctxt->exception.vector == UD_VECTOR || 7621 exception_type(ctxt->exception.vector) == EXCPT_TRAP); 7622 inject_emulated_exception(vcpu); 7623 return 1; 7624 } 7625 return handle_emulation_failure(vcpu, emulation_type); 7626 } 7627 } 7628 7629 if ((emulation_type & EMULTYPE_VMWARE_GP) && 7630 !is_vmware_backdoor_opcode(ctxt)) { 7631 kvm_queue_exception_e(vcpu, GP_VECTOR, 0); 7632 return 1; 7633 } 7634 7635 /* 7636 * Note, EMULTYPE_SKIP is intended for use *only* by vendor callbacks 7637 * for kvm_skip_emulated_instruction(). The caller is responsible for 7638 * updating interruptibility state and injecting single-step #DBs. 7639 */ 7640 if (emulation_type & EMULTYPE_SKIP) { 7641 kvm_rip_write(vcpu, ctxt->_eip); 7642 if (ctxt->eflags & X86_EFLAGS_RF) 7643 kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF); 7644 return 1; 7645 } 7646 7647 if (retry_instruction(ctxt, cr2_or_gpa, emulation_type)) 7648 return 1; 7649 7650 /* this is needed for vmware backdoor interface to work since it 7651 changes registers values during IO operation */ 7652 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) { 7653 vcpu->arch.emulate_regs_need_sync_from_vcpu = false; 7654 emulator_invalidate_register_cache(ctxt); 7655 } 7656 7657 restart: 7658 if (emulation_type & EMULTYPE_PF) { 7659 /* Save the faulting GPA (cr2) in the address field */ 7660 ctxt->exception.address = cr2_or_gpa; 7661 7662 /* With shadow page tables, cr2 contains a GVA or nGPA. */ 7663 if (vcpu->arch.mmu->direct_map) { 7664 ctxt->gpa_available = true; 7665 ctxt->gpa_val = cr2_or_gpa; 7666 } 7667 } else { 7668 /* Sanitize the address out of an abundance of paranoia. */ 7669 ctxt->exception.address = 0; 7670 } 7671 7672 r = x86_emulate_insn(ctxt); 7673 7674 if (r == EMULATION_INTERCEPTED) 7675 return 1; 7676 7677 if (r == EMULATION_FAILED) { 7678 if (reexecute_instruction(vcpu, cr2_or_gpa, write_fault_to_spt, 7679 emulation_type)) 7680 return 1; 7681 7682 return handle_emulation_failure(vcpu, emulation_type); 7683 } 7684 7685 if (ctxt->have_exception) { 7686 r = 1; 7687 if (inject_emulated_exception(vcpu)) 7688 return r; 7689 } else if (vcpu->arch.pio.count) { 7690 if (!vcpu->arch.pio.in) { 7691 /* FIXME: return into emulator if single-stepping. */ 7692 vcpu->arch.pio.count = 0; 7693 } else { 7694 writeback = false; 7695 vcpu->arch.complete_userspace_io = complete_emulated_pio; 7696 } 7697 r = 0; 7698 } else if (vcpu->mmio_needed) { 7699 ++vcpu->stat.mmio_exits; 7700 7701 if (!vcpu->mmio_is_write) 7702 writeback = false; 7703 r = 0; 7704 vcpu->arch.complete_userspace_io = complete_emulated_mmio; 7705 } else if (r == EMULATION_RESTART) 7706 goto restart; 7707 else 7708 r = 1; 7709 7710 if (writeback) { 7711 unsigned long rflags = static_call(kvm_x86_get_rflags)(vcpu); 7712 toggle_interruptibility(vcpu, ctxt->interruptibility); 7713 vcpu->arch.emulate_regs_need_sync_to_vcpu = false; 7714 if (!ctxt->have_exception || 7715 exception_type(ctxt->exception.vector) == EXCPT_TRAP) { 7716 kvm_rip_write(vcpu, ctxt->eip); 7717 if (r && (ctxt->tf || (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP))) 7718 r = kvm_vcpu_do_singlestep(vcpu); 7719 if (kvm_x86_ops.update_emulated_instruction) 7720 static_call(kvm_x86_update_emulated_instruction)(vcpu); 7721 __kvm_set_rflags(vcpu, ctxt->eflags); 7722 } 7723 7724 /* 7725 * For STI, interrupts are shadowed; so KVM_REQ_EVENT will 7726 * do nothing, and it will be requested again as soon as 7727 * the shadow expires. But we still need to check here, 7728 * because POPF has no interrupt shadow. 7729 */ 7730 if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF)) 7731 kvm_make_request(KVM_REQ_EVENT, vcpu); 7732 } else 7733 vcpu->arch.emulate_regs_need_sync_to_vcpu = true; 7734 7735 return r; 7736 } 7737 7738 int kvm_emulate_instruction(struct kvm_vcpu *vcpu, int emulation_type) 7739 { 7740 return x86_emulate_instruction(vcpu, 0, emulation_type, NULL, 0); 7741 } 7742 EXPORT_SYMBOL_GPL(kvm_emulate_instruction); 7743 7744 int kvm_emulate_instruction_from_buffer(struct kvm_vcpu *vcpu, 7745 void *insn, int insn_len) 7746 { 7747 return x86_emulate_instruction(vcpu, 0, 0, insn, insn_len); 7748 } 7749 EXPORT_SYMBOL_GPL(kvm_emulate_instruction_from_buffer); 7750 7751 static int complete_fast_pio_out_port_0x7e(struct kvm_vcpu *vcpu) 7752 { 7753 vcpu->arch.pio.count = 0; 7754 return 1; 7755 } 7756 7757 static int complete_fast_pio_out(struct kvm_vcpu *vcpu) 7758 { 7759 vcpu->arch.pio.count = 0; 7760 7761 if (unlikely(!kvm_is_linear_rip(vcpu, vcpu->arch.pio.linear_rip))) 7762 return 1; 7763 7764 return kvm_skip_emulated_instruction(vcpu); 7765 } 7766 7767 static int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, 7768 unsigned short port) 7769 { 7770 unsigned long val = kvm_rax_read(vcpu); 7771 int ret = emulator_pio_out(vcpu, size, port, &val, 1); 7772 7773 if (ret) 7774 return ret; 7775 7776 /* 7777 * Workaround userspace that relies on old KVM behavior of %rip being 7778 * incremented prior to exiting to userspace to handle "OUT 0x7e". 7779 */ 7780 if (port == 0x7e && 7781 kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_OUT_7E_INC_RIP)) { 7782 vcpu->arch.complete_userspace_io = 7783 complete_fast_pio_out_port_0x7e; 7784 kvm_skip_emulated_instruction(vcpu); 7785 } else { 7786 vcpu->arch.pio.linear_rip = kvm_get_linear_rip(vcpu); 7787 vcpu->arch.complete_userspace_io = complete_fast_pio_out; 7788 } 7789 return 0; 7790 } 7791 7792 static int complete_fast_pio_in(struct kvm_vcpu *vcpu) 7793 { 7794 unsigned long val; 7795 7796 /* We should only ever be called with arch.pio.count equal to 1 */ 7797 BUG_ON(vcpu->arch.pio.count != 1); 7798 7799 if (unlikely(!kvm_is_linear_rip(vcpu, vcpu->arch.pio.linear_rip))) { 7800 vcpu->arch.pio.count = 0; 7801 return 1; 7802 } 7803 7804 /* For size less than 4 we merge, else we zero extend */ 7805 val = (vcpu->arch.pio.size < 4) ? kvm_rax_read(vcpu) : 0; 7806 7807 /* 7808 * Since vcpu->arch.pio.count == 1 let emulator_pio_in perform 7809 * the copy and tracing 7810 */ 7811 emulator_pio_in(vcpu, vcpu->arch.pio.size, vcpu->arch.pio.port, &val, 1); 7812 kvm_rax_write(vcpu, val); 7813 7814 return kvm_skip_emulated_instruction(vcpu); 7815 } 7816 7817 static int kvm_fast_pio_in(struct kvm_vcpu *vcpu, int size, 7818 unsigned short port) 7819 { 7820 unsigned long val; 7821 int ret; 7822 7823 /* For size less than 4 we merge, else we zero extend */ 7824 val = (size < 4) ? kvm_rax_read(vcpu) : 0; 7825 7826 ret = emulator_pio_in(vcpu, size, port, &val, 1); 7827 if (ret) { 7828 kvm_rax_write(vcpu, val); 7829 return ret; 7830 } 7831 7832 vcpu->arch.pio.linear_rip = kvm_get_linear_rip(vcpu); 7833 vcpu->arch.complete_userspace_io = complete_fast_pio_in; 7834 7835 return 0; 7836 } 7837 7838 int kvm_fast_pio(struct kvm_vcpu *vcpu, int size, unsigned short port, int in) 7839 { 7840 int ret; 7841 7842 if (in) 7843 ret = kvm_fast_pio_in(vcpu, size, port); 7844 else 7845 ret = kvm_fast_pio_out(vcpu, size, port); 7846 return ret && kvm_skip_emulated_instruction(vcpu); 7847 } 7848 EXPORT_SYMBOL_GPL(kvm_fast_pio); 7849 7850 static int kvmclock_cpu_down_prep(unsigned int cpu) 7851 { 7852 __this_cpu_write(cpu_tsc_khz, 0); 7853 return 0; 7854 } 7855 7856 static void tsc_khz_changed(void *data) 7857 { 7858 struct cpufreq_freqs *freq = data; 7859 unsigned long khz = 0; 7860 7861 if (data) 7862 khz = freq->new; 7863 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) 7864 khz = cpufreq_quick_get(raw_smp_processor_id()); 7865 if (!khz) 7866 khz = tsc_khz; 7867 __this_cpu_write(cpu_tsc_khz, khz); 7868 } 7869 7870 #ifdef CONFIG_X86_64 7871 static void kvm_hyperv_tsc_notifier(void) 7872 { 7873 struct kvm *kvm; 7874 struct kvm_vcpu *vcpu; 7875 int cpu; 7876 unsigned long flags; 7877 7878 mutex_lock(&kvm_lock); 7879 list_for_each_entry(kvm, &vm_list, vm_list) 7880 kvm_make_mclock_inprogress_request(kvm); 7881 7882 hyperv_stop_tsc_emulation(); 7883 7884 /* TSC frequency always matches when on Hyper-V */ 7885 for_each_present_cpu(cpu) 7886 per_cpu(cpu_tsc_khz, cpu) = tsc_khz; 7887 kvm_max_guest_tsc_khz = tsc_khz; 7888 7889 list_for_each_entry(kvm, &vm_list, vm_list) { 7890 struct kvm_arch *ka = &kvm->arch; 7891 7892 spin_lock_irqsave(&ka->pvclock_gtod_sync_lock, flags); 7893 pvclock_update_vm_gtod_copy(kvm); 7894 spin_unlock_irqrestore(&ka->pvclock_gtod_sync_lock, flags); 7895 7896 kvm_for_each_vcpu(cpu, vcpu, kvm) 7897 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 7898 7899 kvm_for_each_vcpu(cpu, vcpu, kvm) 7900 kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu); 7901 } 7902 mutex_unlock(&kvm_lock); 7903 } 7904 #endif 7905 7906 static void __kvmclock_cpufreq_notifier(struct cpufreq_freqs *freq, int cpu) 7907 { 7908 struct kvm *kvm; 7909 struct kvm_vcpu *vcpu; 7910 int i, send_ipi = 0; 7911 7912 /* 7913 * We allow guests to temporarily run on slowing clocks, 7914 * provided we notify them after, or to run on accelerating 7915 * clocks, provided we notify them before. Thus time never 7916 * goes backwards. 7917 * 7918 * However, we have a problem. We can't atomically update 7919 * the frequency of a given CPU from this function; it is 7920 * merely a notifier, which can be called from any CPU. 7921 * Changing the TSC frequency at arbitrary points in time 7922 * requires a recomputation of local variables related to 7923 * the TSC for each VCPU. We must flag these local variables 7924 * to be updated and be sure the update takes place with the 7925 * new frequency before any guests proceed. 7926 * 7927 * Unfortunately, the combination of hotplug CPU and frequency 7928 * change creates an intractable locking scenario; the order 7929 * of when these callouts happen is undefined with respect to 7930 * CPU hotplug, and they can race with each other. As such, 7931 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is 7932 * undefined; you can actually have a CPU frequency change take 7933 * place in between the computation of X and the setting of the 7934 * variable. To protect against this problem, all updates of 7935 * the per_cpu tsc_khz variable are done in an interrupt 7936 * protected IPI, and all callers wishing to update the value 7937 * must wait for a synchronous IPI to complete (which is trivial 7938 * if the caller is on the CPU already). This establishes the 7939 * necessary total order on variable updates. 7940 * 7941 * Note that because a guest time update may take place 7942 * anytime after the setting of the VCPU's request bit, the 7943 * correct TSC value must be set before the request. However, 7944 * to ensure the update actually makes it to any guest which 7945 * starts running in hardware virtualization between the set 7946 * and the acquisition of the spinlock, we must also ping the 7947 * CPU after setting the request bit. 7948 * 7949 */ 7950 7951 smp_call_function_single(cpu, tsc_khz_changed, freq, 1); 7952 7953 mutex_lock(&kvm_lock); 7954 list_for_each_entry(kvm, &vm_list, vm_list) { 7955 kvm_for_each_vcpu(i, vcpu, kvm) { 7956 if (vcpu->cpu != cpu) 7957 continue; 7958 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 7959 if (vcpu->cpu != raw_smp_processor_id()) 7960 send_ipi = 1; 7961 } 7962 } 7963 mutex_unlock(&kvm_lock); 7964 7965 if (freq->old < freq->new && send_ipi) { 7966 /* 7967 * We upscale the frequency. Must make the guest 7968 * doesn't see old kvmclock values while running with 7969 * the new frequency, otherwise we risk the guest sees 7970 * time go backwards. 7971 * 7972 * In case we update the frequency for another cpu 7973 * (which might be in guest context) send an interrupt 7974 * to kick the cpu out of guest context. Next time 7975 * guest context is entered kvmclock will be updated, 7976 * so the guest will not see stale values. 7977 */ 7978 smp_call_function_single(cpu, tsc_khz_changed, freq, 1); 7979 } 7980 } 7981 7982 static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val, 7983 void *data) 7984 { 7985 struct cpufreq_freqs *freq = data; 7986 int cpu; 7987 7988 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new) 7989 return 0; 7990 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new) 7991 return 0; 7992 7993 for_each_cpu(cpu, freq->policy->cpus) 7994 __kvmclock_cpufreq_notifier(freq, cpu); 7995 7996 return 0; 7997 } 7998 7999 static struct notifier_block kvmclock_cpufreq_notifier_block = { 8000 .notifier_call = kvmclock_cpufreq_notifier 8001 }; 8002 8003 static int kvmclock_cpu_online(unsigned int cpu) 8004 { 8005 tsc_khz_changed(NULL); 8006 return 0; 8007 } 8008 8009 static void kvm_timer_init(void) 8010 { 8011 max_tsc_khz = tsc_khz; 8012 8013 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) { 8014 #ifdef CONFIG_CPU_FREQ 8015 struct cpufreq_policy *policy; 8016 int cpu; 8017 8018 cpu = get_cpu(); 8019 policy = cpufreq_cpu_get(cpu); 8020 if (policy) { 8021 if (policy->cpuinfo.max_freq) 8022 max_tsc_khz = policy->cpuinfo.max_freq; 8023 cpufreq_cpu_put(policy); 8024 } 8025 put_cpu(); 8026 #endif 8027 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block, 8028 CPUFREQ_TRANSITION_NOTIFIER); 8029 } 8030 8031 cpuhp_setup_state(CPUHP_AP_X86_KVM_CLK_ONLINE, "x86/kvm/clk:online", 8032 kvmclock_cpu_online, kvmclock_cpu_down_prep); 8033 } 8034 8035 DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu); 8036 EXPORT_PER_CPU_SYMBOL_GPL(current_vcpu); 8037 8038 int kvm_is_in_guest(void) 8039 { 8040 return __this_cpu_read(current_vcpu) != NULL; 8041 } 8042 8043 static int kvm_is_user_mode(void) 8044 { 8045 int user_mode = 3; 8046 8047 if (__this_cpu_read(current_vcpu)) 8048 user_mode = static_call(kvm_x86_get_cpl)(__this_cpu_read(current_vcpu)); 8049 8050 return user_mode != 0; 8051 } 8052 8053 static unsigned long kvm_get_guest_ip(void) 8054 { 8055 unsigned long ip = 0; 8056 8057 if (__this_cpu_read(current_vcpu)) 8058 ip = kvm_rip_read(__this_cpu_read(current_vcpu)); 8059 8060 return ip; 8061 } 8062 8063 static void kvm_handle_intel_pt_intr(void) 8064 { 8065 struct kvm_vcpu *vcpu = __this_cpu_read(current_vcpu); 8066 8067 kvm_make_request(KVM_REQ_PMI, vcpu); 8068 __set_bit(MSR_CORE_PERF_GLOBAL_OVF_CTRL_TRACE_TOPA_PMI_BIT, 8069 (unsigned long *)&vcpu->arch.pmu.global_status); 8070 } 8071 8072 static struct perf_guest_info_callbacks kvm_guest_cbs = { 8073 .is_in_guest = kvm_is_in_guest, 8074 .is_user_mode = kvm_is_user_mode, 8075 .get_guest_ip = kvm_get_guest_ip, 8076 .handle_intel_pt_intr = kvm_handle_intel_pt_intr, 8077 }; 8078 8079 #ifdef CONFIG_X86_64 8080 static void pvclock_gtod_update_fn(struct work_struct *work) 8081 { 8082 struct kvm *kvm; 8083 8084 struct kvm_vcpu *vcpu; 8085 int i; 8086 8087 mutex_lock(&kvm_lock); 8088 list_for_each_entry(kvm, &vm_list, vm_list) 8089 kvm_for_each_vcpu(i, vcpu, kvm) 8090 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu); 8091 atomic_set(&kvm_guest_has_master_clock, 0); 8092 mutex_unlock(&kvm_lock); 8093 } 8094 8095 static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn); 8096 8097 /* 8098 * Indirection to move queue_work() out of the tk_core.seq write held 8099 * region to prevent possible deadlocks against time accessors which 8100 * are invoked with work related locks held. 8101 */ 8102 static void pvclock_irq_work_fn(struct irq_work *w) 8103 { 8104 queue_work(system_long_wq, &pvclock_gtod_work); 8105 } 8106 8107 static DEFINE_IRQ_WORK(pvclock_irq_work, pvclock_irq_work_fn); 8108 8109 /* 8110 * Notification about pvclock gtod data update. 8111 */ 8112 static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused, 8113 void *priv) 8114 { 8115 struct pvclock_gtod_data *gtod = &pvclock_gtod_data; 8116 struct timekeeper *tk = priv; 8117 8118 update_pvclock_gtod(tk); 8119 8120 /* 8121 * Disable master clock if host does not trust, or does not use, 8122 * TSC based clocksource. Delegate queue_work() to irq_work as 8123 * this is invoked with tk_core.seq write held. 8124 */ 8125 if (!gtod_is_based_on_tsc(gtod->clock.vclock_mode) && 8126 atomic_read(&kvm_guest_has_master_clock) != 0) 8127 irq_work_queue(&pvclock_irq_work); 8128 return 0; 8129 } 8130 8131 static struct notifier_block pvclock_gtod_notifier = { 8132 .notifier_call = pvclock_gtod_notify, 8133 }; 8134 #endif 8135 8136 int kvm_arch_init(void *opaque) 8137 { 8138 struct kvm_x86_init_ops *ops = opaque; 8139 int r; 8140 8141 if (kvm_x86_ops.hardware_enable) { 8142 printk(KERN_ERR "kvm: already loaded the other module\n"); 8143 r = -EEXIST; 8144 goto out; 8145 } 8146 8147 if (!ops->cpu_has_kvm_support()) { 8148 pr_err_ratelimited("kvm: no hardware support\n"); 8149 r = -EOPNOTSUPP; 8150 goto out; 8151 } 8152 if (ops->disabled_by_bios()) { 8153 pr_err_ratelimited("kvm: disabled by bios\n"); 8154 r = -EOPNOTSUPP; 8155 goto out; 8156 } 8157 8158 /* 8159 * KVM explicitly assumes that the guest has an FPU and 8160 * FXSAVE/FXRSTOR. For example, the KVM_GET_FPU explicitly casts the 8161 * vCPU's FPU state as a fxregs_state struct. 8162 */ 8163 if (!boot_cpu_has(X86_FEATURE_FPU) || !boot_cpu_has(X86_FEATURE_FXSR)) { 8164 printk(KERN_ERR "kvm: inadequate fpu\n"); 8165 r = -EOPNOTSUPP; 8166 goto out; 8167 } 8168 8169 r = -ENOMEM; 8170 x86_fpu_cache = kmem_cache_create("x86_fpu", sizeof(struct fpu), 8171 __alignof__(struct fpu), SLAB_ACCOUNT, 8172 NULL); 8173 if (!x86_fpu_cache) { 8174 printk(KERN_ERR "kvm: failed to allocate cache for x86 fpu\n"); 8175 goto out; 8176 } 8177 8178 x86_emulator_cache = kvm_alloc_emulator_cache(); 8179 if (!x86_emulator_cache) { 8180 pr_err("kvm: failed to allocate cache for x86 emulator\n"); 8181 goto out_free_x86_fpu_cache; 8182 } 8183 8184 user_return_msrs = alloc_percpu(struct kvm_user_return_msrs); 8185 if (!user_return_msrs) { 8186 printk(KERN_ERR "kvm: failed to allocate percpu kvm_user_return_msrs\n"); 8187 goto out_free_x86_emulator_cache; 8188 } 8189 kvm_nr_uret_msrs = 0; 8190 8191 r = kvm_mmu_module_init(); 8192 if (r) 8193 goto out_free_percpu; 8194 8195 kvm_timer_init(); 8196 8197 perf_register_guest_info_callbacks(&kvm_guest_cbs); 8198 8199 if (boot_cpu_has(X86_FEATURE_XSAVE)) { 8200 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK); 8201 supported_xcr0 = host_xcr0 & KVM_SUPPORTED_XCR0; 8202 } 8203 8204 if (pi_inject_timer == -1) 8205 pi_inject_timer = housekeeping_enabled(HK_FLAG_TIMER); 8206 #ifdef CONFIG_X86_64 8207 pvclock_gtod_register_notifier(&pvclock_gtod_notifier); 8208 8209 if (hypervisor_is_type(X86_HYPER_MS_HYPERV)) 8210 set_hv_tscchange_cb(kvm_hyperv_tsc_notifier); 8211 #endif 8212 8213 return 0; 8214 8215 out_free_percpu: 8216 free_percpu(user_return_msrs); 8217 out_free_x86_emulator_cache: 8218 kmem_cache_destroy(x86_emulator_cache); 8219 out_free_x86_fpu_cache: 8220 kmem_cache_destroy(x86_fpu_cache); 8221 out: 8222 return r; 8223 } 8224 8225 void kvm_arch_exit(void) 8226 { 8227 #ifdef CONFIG_X86_64 8228 if (hypervisor_is_type(X86_HYPER_MS_HYPERV)) 8229 clear_hv_tscchange_cb(); 8230 #endif 8231 kvm_lapic_exit(); 8232 perf_unregister_guest_info_callbacks(&kvm_guest_cbs); 8233 8234 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) 8235 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block, 8236 CPUFREQ_TRANSITION_NOTIFIER); 8237 cpuhp_remove_state_nocalls(CPUHP_AP_X86_KVM_CLK_ONLINE); 8238 #ifdef CONFIG_X86_64 8239 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier); 8240 irq_work_sync(&pvclock_irq_work); 8241 cancel_work_sync(&pvclock_gtod_work); 8242 #endif 8243 kvm_x86_ops.hardware_enable = NULL; 8244 kvm_mmu_module_exit(); 8245 free_percpu(user_return_msrs); 8246 kmem_cache_destroy(x86_fpu_cache); 8247 #ifdef CONFIG_KVM_XEN 8248 static_key_deferred_flush(&kvm_xen_enabled); 8249 WARN_ON(static_branch_unlikely(&kvm_xen_enabled.key)); 8250 #endif 8251 } 8252 8253 static int __kvm_vcpu_halt(struct kvm_vcpu *vcpu, int state, int reason) 8254 { 8255 ++vcpu->stat.halt_exits; 8256 if (lapic_in_kernel(vcpu)) { 8257 vcpu->arch.mp_state = state; 8258 return 1; 8259 } else { 8260 vcpu->run->exit_reason = reason; 8261 return 0; 8262 } 8263 } 8264 8265 int kvm_vcpu_halt(struct kvm_vcpu *vcpu) 8266 { 8267 return __kvm_vcpu_halt(vcpu, KVM_MP_STATE_HALTED, KVM_EXIT_HLT); 8268 } 8269 EXPORT_SYMBOL_GPL(kvm_vcpu_halt); 8270 8271 int kvm_emulate_halt(struct kvm_vcpu *vcpu) 8272 { 8273 int ret = kvm_skip_emulated_instruction(vcpu); 8274 /* 8275 * TODO: we might be squashing a GUESTDBG_SINGLESTEP-triggered 8276 * KVM_EXIT_DEBUG here. 8277 */ 8278 return kvm_vcpu_halt(vcpu) && ret; 8279 } 8280 EXPORT_SYMBOL_GPL(kvm_emulate_halt); 8281 8282 int kvm_emulate_ap_reset_hold(struct kvm_vcpu *vcpu) 8283 { 8284 int ret = kvm_skip_emulated_instruction(vcpu); 8285 8286 return __kvm_vcpu_halt(vcpu, KVM_MP_STATE_AP_RESET_HOLD, KVM_EXIT_AP_RESET_HOLD) && ret; 8287 } 8288 EXPORT_SYMBOL_GPL(kvm_emulate_ap_reset_hold); 8289 8290 #ifdef CONFIG_X86_64 8291 static int kvm_pv_clock_pairing(struct kvm_vcpu *vcpu, gpa_t paddr, 8292 unsigned long clock_type) 8293 { 8294 struct kvm_clock_pairing clock_pairing; 8295 struct timespec64 ts; 8296 u64 cycle; 8297 int ret; 8298 8299 if (clock_type != KVM_CLOCK_PAIRING_WALLCLOCK) 8300 return -KVM_EOPNOTSUPP; 8301 8302 if (!kvm_get_walltime_and_clockread(&ts, &cycle)) 8303 return -KVM_EOPNOTSUPP; 8304 8305 clock_pairing.sec = ts.tv_sec; 8306 clock_pairing.nsec = ts.tv_nsec; 8307 clock_pairing.tsc = kvm_read_l1_tsc(vcpu, cycle); 8308 clock_pairing.flags = 0; 8309 memset(&clock_pairing.pad, 0, sizeof(clock_pairing.pad)); 8310 8311 ret = 0; 8312 if (kvm_write_guest(vcpu->kvm, paddr, &clock_pairing, 8313 sizeof(struct kvm_clock_pairing))) 8314 ret = -KVM_EFAULT; 8315 8316 return ret; 8317 } 8318 #endif 8319 8320 /* 8321 * kvm_pv_kick_cpu_op: Kick a vcpu. 8322 * 8323 * @apicid - apicid of vcpu to be kicked. 8324 */ 8325 static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid) 8326 { 8327 struct kvm_lapic_irq lapic_irq; 8328 8329 lapic_irq.shorthand = APIC_DEST_NOSHORT; 8330 lapic_irq.dest_mode = APIC_DEST_PHYSICAL; 8331 lapic_irq.level = 0; 8332 lapic_irq.dest_id = apicid; 8333 lapic_irq.msi_redir_hint = false; 8334 8335 lapic_irq.delivery_mode = APIC_DM_REMRD; 8336 kvm_irq_delivery_to_apic(kvm, NULL, &lapic_irq, NULL); 8337 } 8338 8339 bool kvm_apicv_activated(struct kvm *kvm) 8340 { 8341 return (READ_ONCE(kvm->arch.apicv_inhibit_reasons) == 0); 8342 } 8343 EXPORT_SYMBOL_GPL(kvm_apicv_activated); 8344 8345 void kvm_apicv_init(struct kvm *kvm, bool enable) 8346 { 8347 if (enable) 8348 clear_bit(APICV_INHIBIT_REASON_DISABLE, 8349 &kvm->arch.apicv_inhibit_reasons); 8350 else 8351 set_bit(APICV_INHIBIT_REASON_DISABLE, 8352 &kvm->arch.apicv_inhibit_reasons); 8353 } 8354 EXPORT_SYMBOL_GPL(kvm_apicv_init); 8355 8356 static void kvm_sched_yield(struct kvm_vcpu *vcpu, unsigned long dest_id) 8357 { 8358 struct kvm_vcpu *target = NULL; 8359 struct kvm_apic_map *map; 8360 8361 vcpu->stat.directed_yield_attempted++; 8362 8363 rcu_read_lock(); 8364 map = rcu_dereference(vcpu->kvm->arch.apic_map); 8365 8366 if (likely(map) && dest_id <= map->max_apic_id && map->phys_map[dest_id]) 8367 target = map->phys_map[dest_id]->vcpu; 8368 8369 rcu_read_unlock(); 8370 8371 if (!target || !READ_ONCE(target->ready)) 8372 goto no_yield; 8373 8374 /* Ignore requests to yield to self */ 8375 if (vcpu == target) 8376 goto no_yield; 8377 8378 if (kvm_vcpu_yield_to(target) <= 0) 8379 goto no_yield; 8380 8381 vcpu->stat.directed_yield_successful++; 8382 8383 no_yield: 8384 return; 8385 } 8386 8387 int kvm_emulate_hypercall(struct kvm_vcpu *vcpu) 8388 { 8389 unsigned long nr, a0, a1, a2, a3, ret; 8390 int op_64_bit; 8391 8392 if (kvm_xen_hypercall_enabled(vcpu->kvm)) 8393 return kvm_xen_hypercall(vcpu); 8394 8395 if (kvm_hv_hypercall_enabled(vcpu)) 8396 return kvm_hv_hypercall(vcpu); 8397 8398 nr = kvm_rax_read(vcpu); 8399 a0 = kvm_rbx_read(vcpu); 8400 a1 = kvm_rcx_read(vcpu); 8401 a2 = kvm_rdx_read(vcpu); 8402 a3 = kvm_rsi_read(vcpu); 8403 8404 trace_kvm_hypercall(nr, a0, a1, a2, a3); 8405 8406 op_64_bit = is_64_bit_mode(vcpu); 8407 if (!op_64_bit) { 8408 nr &= 0xFFFFFFFF; 8409 a0 &= 0xFFFFFFFF; 8410 a1 &= 0xFFFFFFFF; 8411 a2 &= 0xFFFFFFFF; 8412 a3 &= 0xFFFFFFFF; 8413 } 8414 8415 if (static_call(kvm_x86_get_cpl)(vcpu) != 0) { 8416 ret = -KVM_EPERM; 8417 goto out; 8418 } 8419 8420 ret = -KVM_ENOSYS; 8421 8422 switch (nr) { 8423 case KVM_HC_VAPIC_POLL_IRQ: 8424 ret = 0; 8425 break; 8426 case KVM_HC_KICK_CPU: 8427 if (!guest_pv_has(vcpu, KVM_FEATURE_PV_UNHALT)) 8428 break; 8429 8430 kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1); 8431 kvm_sched_yield(vcpu, a1); 8432 ret = 0; 8433 break; 8434 #ifdef CONFIG_X86_64 8435 case KVM_HC_CLOCK_PAIRING: 8436 ret = kvm_pv_clock_pairing(vcpu, a0, a1); 8437 break; 8438 #endif 8439 case KVM_HC_SEND_IPI: 8440 if (!guest_pv_has(vcpu, KVM_FEATURE_PV_SEND_IPI)) 8441 break; 8442 8443 ret = kvm_pv_send_ipi(vcpu->kvm, a0, a1, a2, a3, op_64_bit); 8444 break; 8445 case KVM_HC_SCHED_YIELD: 8446 if (!guest_pv_has(vcpu, KVM_FEATURE_PV_SCHED_YIELD)) 8447 break; 8448 8449 kvm_sched_yield(vcpu, a0); 8450 ret = 0; 8451 break; 8452 default: 8453 ret = -KVM_ENOSYS; 8454 break; 8455 } 8456 out: 8457 if (!op_64_bit) 8458 ret = (u32)ret; 8459 kvm_rax_write(vcpu, ret); 8460 8461 ++vcpu->stat.hypercalls; 8462 return kvm_skip_emulated_instruction(vcpu); 8463 } 8464 EXPORT_SYMBOL_GPL(kvm_emulate_hypercall); 8465 8466 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt) 8467 { 8468 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 8469 char instruction[3]; 8470 unsigned long rip = kvm_rip_read(vcpu); 8471 8472 static_call(kvm_x86_patch_hypercall)(vcpu, instruction); 8473 8474 return emulator_write_emulated(ctxt, rip, instruction, 3, 8475 &ctxt->exception); 8476 } 8477 8478 static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu) 8479 { 8480 return vcpu->run->request_interrupt_window && 8481 likely(!pic_in_kernel(vcpu->kvm)); 8482 } 8483 8484 static void post_kvm_run_save(struct kvm_vcpu *vcpu) 8485 { 8486 struct kvm_run *kvm_run = vcpu->run; 8487 8488 /* 8489 * if_flag is obsolete and useless, so do not bother 8490 * setting it for SEV-ES guests. Userspace can just 8491 * use kvm_run->ready_for_interrupt_injection. 8492 */ 8493 kvm_run->if_flag = !vcpu->arch.guest_state_protected 8494 && (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0; 8495 8496 kvm_run->cr8 = kvm_get_cr8(vcpu); 8497 kvm_run->apic_base = kvm_get_apic_base(vcpu); 8498 kvm_run->ready_for_interrupt_injection = 8499 pic_in_kernel(vcpu->kvm) || 8500 kvm_vcpu_ready_for_interrupt_injection(vcpu); 8501 8502 if (is_smm(vcpu)) 8503 kvm_run->flags |= KVM_RUN_X86_SMM; 8504 } 8505 8506 static void update_cr8_intercept(struct kvm_vcpu *vcpu) 8507 { 8508 int max_irr, tpr; 8509 8510 if (!kvm_x86_ops.update_cr8_intercept) 8511 return; 8512 8513 if (!lapic_in_kernel(vcpu)) 8514 return; 8515 8516 if (vcpu->arch.apicv_active) 8517 return; 8518 8519 if (!vcpu->arch.apic->vapic_addr) 8520 max_irr = kvm_lapic_find_highest_irr(vcpu); 8521 else 8522 max_irr = -1; 8523 8524 if (max_irr != -1) 8525 max_irr >>= 4; 8526 8527 tpr = kvm_lapic_get_cr8(vcpu); 8528 8529 static_call(kvm_x86_update_cr8_intercept)(vcpu, tpr, max_irr); 8530 } 8531 8532 8533 int kvm_check_nested_events(struct kvm_vcpu *vcpu) 8534 { 8535 if (WARN_ON_ONCE(!is_guest_mode(vcpu))) 8536 return -EIO; 8537 8538 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) { 8539 kvm_x86_ops.nested_ops->triple_fault(vcpu); 8540 return 1; 8541 } 8542 8543 return kvm_x86_ops.nested_ops->check_events(vcpu); 8544 } 8545 8546 static void kvm_inject_exception(struct kvm_vcpu *vcpu) 8547 { 8548 if (vcpu->arch.exception.error_code && !is_protmode(vcpu)) 8549 vcpu->arch.exception.error_code = false; 8550 static_call(kvm_x86_queue_exception)(vcpu); 8551 } 8552 8553 static void inject_pending_event(struct kvm_vcpu *vcpu, bool *req_immediate_exit) 8554 { 8555 int r; 8556 bool can_inject = true; 8557 8558 /* try to reinject previous events if any */ 8559 8560 if (vcpu->arch.exception.injected) { 8561 kvm_inject_exception(vcpu); 8562 can_inject = false; 8563 } 8564 /* 8565 * Do not inject an NMI or interrupt if there is a pending 8566 * exception. Exceptions and interrupts are recognized at 8567 * instruction boundaries, i.e. the start of an instruction. 8568 * Trap-like exceptions, e.g. #DB, have higher priority than 8569 * NMIs and interrupts, i.e. traps are recognized before an 8570 * NMI/interrupt that's pending on the same instruction. 8571 * Fault-like exceptions, e.g. #GP and #PF, are the lowest 8572 * priority, but are only generated (pended) during instruction 8573 * execution, i.e. a pending fault-like exception means the 8574 * fault occurred on the *previous* instruction and must be 8575 * serviced prior to recognizing any new events in order to 8576 * fully complete the previous instruction. 8577 */ 8578 else if (!vcpu->arch.exception.pending) { 8579 if (vcpu->arch.nmi_injected) { 8580 static_call(kvm_x86_set_nmi)(vcpu); 8581 can_inject = false; 8582 } else if (vcpu->arch.interrupt.injected) { 8583 static_call(kvm_x86_set_irq)(vcpu); 8584 can_inject = false; 8585 } 8586 } 8587 8588 WARN_ON_ONCE(vcpu->arch.exception.injected && 8589 vcpu->arch.exception.pending); 8590 8591 /* 8592 * Call check_nested_events() even if we reinjected a previous event 8593 * in order for caller to determine if it should require immediate-exit 8594 * from L2 to L1 due to pending L1 events which require exit 8595 * from L2 to L1. 8596 */ 8597 if (is_guest_mode(vcpu)) { 8598 r = kvm_check_nested_events(vcpu); 8599 if (r < 0) 8600 goto busy; 8601 } 8602 8603 /* try to inject new event if pending */ 8604 if (vcpu->arch.exception.pending) { 8605 trace_kvm_inj_exception(vcpu->arch.exception.nr, 8606 vcpu->arch.exception.has_error_code, 8607 vcpu->arch.exception.error_code); 8608 8609 vcpu->arch.exception.pending = false; 8610 vcpu->arch.exception.injected = true; 8611 8612 if (exception_type(vcpu->arch.exception.nr) == EXCPT_FAULT) 8613 __kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) | 8614 X86_EFLAGS_RF); 8615 8616 if (vcpu->arch.exception.nr == DB_VECTOR) { 8617 kvm_deliver_exception_payload(vcpu); 8618 if (vcpu->arch.dr7 & DR7_GD) { 8619 vcpu->arch.dr7 &= ~DR7_GD; 8620 kvm_update_dr7(vcpu); 8621 } 8622 } 8623 8624 kvm_inject_exception(vcpu); 8625 can_inject = false; 8626 } 8627 8628 /* 8629 * Finally, inject interrupt events. If an event cannot be injected 8630 * due to architectural conditions (e.g. IF=0) a window-open exit 8631 * will re-request KVM_REQ_EVENT. Sometimes however an event is pending 8632 * and can architecturally be injected, but we cannot do it right now: 8633 * an interrupt could have arrived just now and we have to inject it 8634 * as a vmexit, or there could already an event in the queue, which is 8635 * indicated by can_inject. In that case we request an immediate exit 8636 * in order to make progress and get back here for another iteration. 8637 * The kvm_x86_ops hooks communicate this by returning -EBUSY. 8638 */ 8639 if (vcpu->arch.smi_pending) { 8640 r = can_inject ? static_call(kvm_x86_smi_allowed)(vcpu, true) : -EBUSY; 8641 if (r < 0) 8642 goto busy; 8643 if (r) { 8644 vcpu->arch.smi_pending = false; 8645 ++vcpu->arch.smi_count; 8646 enter_smm(vcpu); 8647 can_inject = false; 8648 } else 8649 static_call(kvm_x86_enable_smi_window)(vcpu); 8650 } 8651 8652 if (vcpu->arch.nmi_pending) { 8653 r = can_inject ? static_call(kvm_x86_nmi_allowed)(vcpu, true) : -EBUSY; 8654 if (r < 0) 8655 goto busy; 8656 if (r) { 8657 --vcpu->arch.nmi_pending; 8658 vcpu->arch.nmi_injected = true; 8659 static_call(kvm_x86_set_nmi)(vcpu); 8660 can_inject = false; 8661 WARN_ON(static_call(kvm_x86_nmi_allowed)(vcpu, true) < 0); 8662 } 8663 if (vcpu->arch.nmi_pending) 8664 static_call(kvm_x86_enable_nmi_window)(vcpu); 8665 } 8666 8667 if (kvm_cpu_has_injectable_intr(vcpu)) { 8668 r = can_inject ? static_call(kvm_x86_interrupt_allowed)(vcpu, true) : -EBUSY; 8669 if (r < 0) 8670 goto busy; 8671 if (r) { 8672 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu), false); 8673 static_call(kvm_x86_set_irq)(vcpu); 8674 WARN_ON(static_call(kvm_x86_interrupt_allowed)(vcpu, true) < 0); 8675 } 8676 if (kvm_cpu_has_injectable_intr(vcpu)) 8677 static_call(kvm_x86_enable_irq_window)(vcpu); 8678 } 8679 8680 if (is_guest_mode(vcpu) && 8681 kvm_x86_ops.nested_ops->hv_timer_pending && 8682 kvm_x86_ops.nested_ops->hv_timer_pending(vcpu)) 8683 *req_immediate_exit = true; 8684 8685 WARN_ON(vcpu->arch.exception.pending); 8686 return; 8687 8688 busy: 8689 *req_immediate_exit = true; 8690 return; 8691 } 8692 8693 static void process_nmi(struct kvm_vcpu *vcpu) 8694 { 8695 unsigned limit = 2; 8696 8697 /* 8698 * x86 is limited to one NMI running, and one NMI pending after it. 8699 * If an NMI is already in progress, limit further NMIs to just one. 8700 * Otherwise, allow two (and we'll inject the first one immediately). 8701 */ 8702 if (static_call(kvm_x86_get_nmi_mask)(vcpu) || vcpu->arch.nmi_injected) 8703 limit = 1; 8704 8705 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0); 8706 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit); 8707 kvm_make_request(KVM_REQ_EVENT, vcpu); 8708 } 8709 8710 static u32 enter_smm_get_segment_flags(struct kvm_segment *seg) 8711 { 8712 u32 flags = 0; 8713 flags |= seg->g << 23; 8714 flags |= seg->db << 22; 8715 flags |= seg->l << 21; 8716 flags |= seg->avl << 20; 8717 flags |= seg->present << 15; 8718 flags |= seg->dpl << 13; 8719 flags |= seg->s << 12; 8720 flags |= seg->type << 8; 8721 return flags; 8722 } 8723 8724 static void enter_smm_save_seg_32(struct kvm_vcpu *vcpu, char *buf, int n) 8725 { 8726 struct kvm_segment seg; 8727 int offset; 8728 8729 kvm_get_segment(vcpu, &seg, n); 8730 put_smstate(u32, buf, 0x7fa8 + n * 4, seg.selector); 8731 8732 if (n < 3) 8733 offset = 0x7f84 + n * 12; 8734 else 8735 offset = 0x7f2c + (n - 3) * 12; 8736 8737 put_smstate(u32, buf, offset + 8, seg.base); 8738 put_smstate(u32, buf, offset + 4, seg.limit); 8739 put_smstate(u32, buf, offset, enter_smm_get_segment_flags(&seg)); 8740 } 8741 8742 #ifdef CONFIG_X86_64 8743 static void enter_smm_save_seg_64(struct kvm_vcpu *vcpu, char *buf, int n) 8744 { 8745 struct kvm_segment seg; 8746 int offset; 8747 u16 flags; 8748 8749 kvm_get_segment(vcpu, &seg, n); 8750 offset = 0x7e00 + n * 16; 8751 8752 flags = enter_smm_get_segment_flags(&seg) >> 8; 8753 put_smstate(u16, buf, offset, seg.selector); 8754 put_smstate(u16, buf, offset + 2, flags); 8755 put_smstate(u32, buf, offset + 4, seg.limit); 8756 put_smstate(u64, buf, offset + 8, seg.base); 8757 } 8758 #endif 8759 8760 static void enter_smm_save_state_32(struct kvm_vcpu *vcpu, char *buf) 8761 { 8762 struct desc_ptr dt; 8763 struct kvm_segment seg; 8764 unsigned long val; 8765 int i; 8766 8767 put_smstate(u32, buf, 0x7ffc, kvm_read_cr0(vcpu)); 8768 put_smstate(u32, buf, 0x7ff8, kvm_read_cr3(vcpu)); 8769 put_smstate(u32, buf, 0x7ff4, kvm_get_rflags(vcpu)); 8770 put_smstate(u32, buf, 0x7ff0, kvm_rip_read(vcpu)); 8771 8772 for (i = 0; i < 8; i++) 8773 put_smstate(u32, buf, 0x7fd0 + i * 4, kvm_register_read_raw(vcpu, i)); 8774 8775 kvm_get_dr(vcpu, 6, &val); 8776 put_smstate(u32, buf, 0x7fcc, (u32)val); 8777 kvm_get_dr(vcpu, 7, &val); 8778 put_smstate(u32, buf, 0x7fc8, (u32)val); 8779 8780 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR); 8781 put_smstate(u32, buf, 0x7fc4, seg.selector); 8782 put_smstate(u32, buf, 0x7f64, seg.base); 8783 put_smstate(u32, buf, 0x7f60, seg.limit); 8784 put_smstate(u32, buf, 0x7f5c, enter_smm_get_segment_flags(&seg)); 8785 8786 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR); 8787 put_smstate(u32, buf, 0x7fc0, seg.selector); 8788 put_smstate(u32, buf, 0x7f80, seg.base); 8789 put_smstate(u32, buf, 0x7f7c, seg.limit); 8790 put_smstate(u32, buf, 0x7f78, enter_smm_get_segment_flags(&seg)); 8791 8792 static_call(kvm_x86_get_gdt)(vcpu, &dt); 8793 put_smstate(u32, buf, 0x7f74, dt.address); 8794 put_smstate(u32, buf, 0x7f70, dt.size); 8795 8796 static_call(kvm_x86_get_idt)(vcpu, &dt); 8797 put_smstate(u32, buf, 0x7f58, dt.address); 8798 put_smstate(u32, buf, 0x7f54, dt.size); 8799 8800 for (i = 0; i < 6; i++) 8801 enter_smm_save_seg_32(vcpu, buf, i); 8802 8803 put_smstate(u32, buf, 0x7f14, kvm_read_cr4(vcpu)); 8804 8805 /* revision id */ 8806 put_smstate(u32, buf, 0x7efc, 0x00020000); 8807 put_smstate(u32, buf, 0x7ef8, vcpu->arch.smbase); 8808 } 8809 8810 #ifdef CONFIG_X86_64 8811 static void enter_smm_save_state_64(struct kvm_vcpu *vcpu, char *buf) 8812 { 8813 struct desc_ptr dt; 8814 struct kvm_segment seg; 8815 unsigned long val; 8816 int i; 8817 8818 for (i = 0; i < 16; i++) 8819 put_smstate(u64, buf, 0x7ff8 - i * 8, kvm_register_read_raw(vcpu, i)); 8820 8821 put_smstate(u64, buf, 0x7f78, kvm_rip_read(vcpu)); 8822 put_smstate(u32, buf, 0x7f70, kvm_get_rflags(vcpu)); 8823 8824 kvm_get_dr(vcpu, 6, &val); 8825 put_smstate(u64, buf, 0x7f68, val); 8826 kvm_get_dr(vcpu, 7, &val); 8827 put_smstate(u64, buf, 0x7f60, val); 8828 8829 put_smstate(u64, buf, 0x7f58, kvm_read_cr0(vcpu)); 8830 put_smstate(u64, buf, 0x7f50, kvm_read_cr3(vcpu)); 8831 put_smstate(u64, buf, 0x7f48, kvm_read_cr4(vcpu)); 8832 8833 put_smstate(u32, buf, 0x7f00, vcpu->arch.smbase); 8834 8835 /* revision id */ 8836 put_smstate(u32, buf, 0x7efc, 0x00020064); 8837 8838 put_smstate(u64, buf, 0x7ed0, vcpu->arch.efer); 8839 8840 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR); 8841 put_smstate(u16, buf, 0x7e90, seg.selector); 8842 put_smstate(u16, buf, 0x7e92, enter_smm_get_segment_flags(&seg) >> 8); 8843 put_smstate(u32, buf, 0x7e94, seg.limit); 8844 put_smstate(u64, buf, 0x7e98, seg.base); 8845 8846 static_call(kvm_x86_get_idt)(vcpu, &dt); 8847 put_smstate(u32, buf, 0x7e84, dt.size); 8848 put_smstate(u64, buf, 0x7e88, dt.address); 8849 8850 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR); 8851 put_smstate(u16, buf, 0x7e70, seg.selector); 8852 put_smstate(u16, buf, 0x7e72, enter_smm_get_segment_flags(&seg) >> 8); 8853 put_smstate(u32, buf, 0x7e74, seg.limit); 8854 put_smstate(u64, buf, 0x7e78, seg.base); 8855 8856 static_call(kvm_x86_get_gdt)(vcpu, &dt); 8857 put_smstate(u32, buf, 0x7e64, dt.size); 8858 put_smstate(u64, buf, 0x7e68, dt.address); 8859 8860 for (i = 0; i < 6; i++) 8861 enter_smm_save_seg_64(vcpu, buf, i); 8862 } 8863 #endif 8864 8865 static void enter_smm(struct kvm_vcpu *vcpu) 8866 { 8867 struct kvm_segment cs, ds; 8868 struct desc_ptr dt; 8869 char buf[512]; 8870 u32 cr0; 8871 8872 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, true); 8873 memset(buf, 0, 512); 8874 #ifdef CONFIG_X86_64 8875 if (guest_cpuid_has(vcpu, X86_FEATURE_LM)) 8876 enter_smm_save_state_64(vcpu, buf); 8877 else 8878 #endif 8879 enter_smm_save_state_32(vcpu, buf); 8880 8881 /* 8882 * Give pre_enter_smm() a chance to make ISA-specific changes to the 8883 * vCPU state (e.g. leave guest mode) after we've saved the state into 8884 * the SMM state-save area. 8885 */ 8886 static_call(kvm_x86_pre_enter_smm)(vcpu, buf); 8887 8888 vcpu->arch.hflags |= HF_SMM_MASK; 8889 kvm_vcpu_write_guest(vcpu, vcpu->arch.smbase + 0xfe00, buf, sizeof(buf)); 8890 8891 if (static_call(kvm_x86_get_nmi_mask)(vcpu)) 8892 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK; 8893 else 8894 static_call(kvm_x86_set_nmi_mask)(vcpu, true); 8895 8896 kvm_set_rflags(vcpu, X86_EFLAGS_FIXED); 8897 kvm_rip_write(vcpu, 0x8000); 8898 8899 cr0 = vcpu->arch.cr0 & ~(X86_CR0_PE | X86_CR0_EM | X86_CR0_TS | X86_CR0_PG); 8900 static_call(kvm_x86_set_cr0)(vcpu, cr0); 8901 vcpu->arch.cr0 = cr0; 8902 8903 static_call(kvm_x86_set_cr4)(vcpu, 0); 8904 8905 /* Undocumented: IDT limit is set to zero on entry to SMM. */ 8906 dt.address = dt.size = 0; 8907 static_call(kvm_x86_set_idt)(vcpu, &dt); 8908 8909 kvm_set_dr(vcpu, 7, DR7_FIXED_1); 8910 8911 cs.selector = (vcpu->arch.smbase >> 4) & 0xffff; 8912 cs.base = vcpu->arch.smbase; 8913 8914 ds.selector = 0; 8915 ds.base = 0; 8916 8917 cs.limit = ds.limit = 0xffffffff; 8918 cs.type = ds.type = 0x3; 8919 cs.dpl = ds.dpl = 0; 8920 cs.db = ds.db = 0; 8921 cs.s = ds.s = 1; 8922 cs.l = ds.l = 0; 8923 cs.g = ds.g = 1; 8924 cs.avl = ds.avl = 0; 8925 cs.present = ds.present = 1; 8926 cs.unusable = ds.unusable = 0; 8927 cs.padding = ds.padding = 0; 8928 8929 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS); 8930 kvm_set_segment(vcpu, &ds, VCPU_SREG_DS); 8931 kvm_set_segment(vcpu, &ds, VCPU_SREG_ES); 8932 kvm_set_segment(vcpu, &ds, VCPU_SREG_FS); 8933 kvm_set_segment(vcpu, &ds, VCPU_SREG_GS); 8934 kvm_set_segment(vcpu, &ds, VCPU_SREG_SS); 8935 8936 #ifdef CONFIG_X86_64 8937 if (guest_cpuid_has(vcpu, X86_FEATURE_LM)) 8938 static_call(kvm_x86_set_efer)(vcpu, 0); 8939 #endif 8940 8941 kvm_update_cpuid_runtime(vcpu); 8942 kvm_mmu_reset_context(vcpu); 8943 } 8944 8945 static void process_smi(struct kvm_vcpu *vcpu) 8946 { 8947 vcpu->arch.smi_pending = true; 8948 kvm_make_request(KVM_REQ_EVENT, vcpu); 8949 } 8950 8951 void kvm_make_scan_ioapic_request_mask(struct kvm *kvm, 8952 unsigned long *vcpu_bitmap) 8953 { 8954 cpumask_var_t cpus; 8955 8956 zalloc_cpumask_var(&cpus, GFP_ATOMIC); 8957 8958 kvm_make_vcpus_request_mask(kvm, KVM_REQ_SCAN_IOAPIC, 8959 NULL, vcpu_bitmap, cpus); 8960 8961 free_cpumask_var(cpus); 8962 } 8963 8964 void kvm_make_scan_ioapic_request(struct kvm *kvm) 8965 { 8966 kvm_make_all_cpus_request(kvm, KVM_REQ_SCAN_IOAPIC); 8967 } 8968 8969 void kvm_vcpu_update_apicv(struct kvm_vcpu *vcpu) 8970 { 8971 if (!lapic_in_kernel(vcpu)) 8972 return; 8973 8974 vcpu->arch.apicv_active = kvm_apicv_activated(vcpu->kvm); 8975 kvm_apic_update_apicv(vcpu); 8976 static_call(kvm_x86_refresh_apicv_exec_ctrl)(vcpu); 8977 } 8978 EXPORT_SYMBOL_GPL(kvm_vcpu_update_apicv); 8979 8980 /* 8981 * NOTE: Do not hold any lock prior to calling this. 8982 * 8983 * In particular, kvm_request_apicv_update() expects kvm->srcu not to be 8984 * locked, because it calls __x86_set_memory_region() which does 8985 * synchronize_srcu(&kvm->srcu). 8986 */ 8987 void kvm_request_apicv_update(struct kvm *kvm, bool activate, ulong bit) 8988 { 8989 struct kvm_vcpu *except; 8990 unsigned long old, new, expected; 8991 8992 if (!kvm_x86_ops.check_apicv_inhibit_reasons || 8993 !static_call(kvm_x86_check_apicv_inhibit_reasons)(bit)) 8994 return; 8995 8996 old = READ_ONCE(kvm->arch.apicv_inhibit_reasons); 8997 do { 8998 expected = new = old; 8999 if (activate) 9000 __clear_bit(bit, &new); 9001 else 9002 __set_bit(bit, &new); 9003 if (new == old) 9004 break; 9005 old = cmpxchg(&kvm->arch.apicv_inhibit_reasons, expected, new); 9006 } while (old != expected); 9007 9008 if (!!old == !!new) 9009 return; 9010 9011 trace_kvm_apicv_update_request(activate, bit); 9012 if (kvm_x86_ops.pre_update_apicv_exec_ctrl) 9013 static_call(kvm_x86_pre_update_apicv_exec_ctrl)(kvm, activate); 9014 9015 /* 9016 * Sending request to update APICV for all other vcpus, 9017 * while update the calling vcpu immediately instead of 9018 * waiting for another #VMEXIT to handle the request. 9019 */ 9020 except = kvm_get_running_vcpu(); 9021 kvm_make_all_cpus_request_except(kvm, KVM_REQ_APICV_UPDATE, 9022 except); 9023 if (except) 9024 kvm_vcpu_update_apicv(except); 9025 } 9026 EXPORT_SYMBOL_GPL(kvm_request_apicv_update); 9027 9028 static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu) 9029 { 9030 if (!kvm_apic_present(vcpu)) 9031 return; 9032 9033 bitmap_zero(vcpu->arch.ioapic_handled_vectors, 256); 9034 9035 if (irqchip_split(vcpu->kvm)) 9036 kvm_scan_ioapic_routes(vcpu, vcpu->arch.ioapic_handled_vectors); 9037 else { 9038 if (vcpu->arch.apicv_active) 9039 static_call(kvm_x86_sync_pir_to_irr)(vcpu); 9040 if (ioapic_in_kernel(vcpu->kvm)) 9041 kvm_ioapic_scan_entry(vcpu, vcpu->arch.ioapic_handled_vectors); 9042 } 9043 9044 if (is_guest_mode(vcpu)) 9045 vcpu->arch.load_eoi_exitmap_pending = true; 9046 else 9047 kvm_make_request(KVM_REQ_LOAD_EOI_EXITMAP, vcpu); 9048 } 9049 9050 static void vcpu_load_eoi_exitmap(struct kvm_vcpu *vcpu) 9051 { 9052 u64 eoi_exit_bitmap[4]; 9053 9054 if (!kvm_apic_hw_enabled(vcpu->arch.apic)) 9055 return; 9056 9057 if (to_hv_vcpu(vcpu)) 9058 bitmap_or((ulong *)eoi_exit_bitmap, 9059 vcpu->arch.ioapic_handled_vectors, 9060 to_hv_synic(vcpu)->vec_bitmap, 256); 9061 9062 static_call(kvm_x86_load_eoi_exitmap)(vcpu, eoi_exit_bitmap); 9063 } 9064 9065 void kvm_arch_mmu_notifier_invalidate_range(struct kvm *kvm, 9066 unsigned long start, unsigned long end) 9067 { 9068 unsigned long apic_address; 9069 9070 /* 9071 * The physical address of apic access page is stored in the VMCS. 9072 * Update it when it becomes invalid. 9073 */ 9074 apic_address = gfn_to_hva(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT); 9075 if (start <= apic_address && apic_address < end) 9076 kvm_make_all_cpus_request(kvm, KVM_REQ_APIC_PAGE_RELOAD); 9077 } 9078 9079 void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu) 9080 { 9081 if (!lapic_in_kernel(vcpu)) 9082 return; 9083 9084 if (!kvm_x86_ops.set_apic_access_page_addr) 9085 return; 9086 9087 static_call(kvm_x86_set_apic_access_page_addr)(vcpu); 9088 } 9089 9090 void __kvm_request_immediate_exit(struct kvm_vcpu *vcpu) 9091 { 9092 smp_send_reschedule(vcpu->cpu); 9093 } 9094 EXPORT_SYMBOL_GPL(__kvm_request_immediate_exit); 9095 9096 /* 9097 * Returns 1 to let vcpu_run() continue the guest execution loop without 9098 * exiting to the userspace. Otherwise, the value will be returned to the 9099 * userspace. 9100 */ 9101 static int vcpu_enter_guest(struct kvm_vcpu *vcpu) 9102 { 9103 int r; 9104 bool req_int_win = 9105 dm_request_for_irq_injection(vcpu) && 9106 kvm_cpu_accept_dm_intr(vcpu); 9107 fastpath_t exit_fastpath; 9108 9109 bool req_immediate_exit = false; 9110 9111 /* Forbid vmenter if vcpu dirty ring is soft-full */ 9112 if (unlikely(vcpu->kvm->dirty_ring_size && 9113 kvm_dirty_ring_soft_full(&vcpu->dirty_ring))) { 9114 vcpu->run->exit_reason = KVM_EXIT_DIRTY_RING_FULL; 9115 trace_kvm_dirty_ring_exit(vcpu); 9116 r = 0; 9117 goto out; 9118 } 9119 9120 if (kvm_request_pending(vcpu)) { 9121 if (kvm_check_request(KVM_REQ_GET_NESTED_STATE_PAGES, vcpu)) { 9122 if (unlikely(!kvm_x86_ops.nested_ops->get_nested_state_pages(vcpu))) { 9123 r = 0; 9124 goto out; 9125 } 9126 } 9127 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu)) 9128 kvm_mmu_unload(vcpu); 9129 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu)) 9130 __kvm_migrate_timers(vcpu); 9131 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu)) 9132 kvm_gen_update_masterclock(vcpu->kvm); 9133 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu)) 9134 kvm_gen_kvmclock_update(vcpu); 9135 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) { 9136 r = kvm_guest_time_update(vcpu); 9137 if (unlikely(r)) 9138 goto out; 9139 } 9140 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu)) 9141 kvm_mmu_sync_roots(vcpu); 9142 if (kvm_check_request(KVM_REQ_LOAD_MMU_PGD, vcpu)) 9143 kvm_mmu_load_pgd(vcpu); 9144 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu)) { 9145 kvm_vcpu_flush_tlb_all(vcpu); 9146 9147 /* Flushing all ASIDs flushes the current ASID... */ 9148 kvm_clear_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu); 9149 } 9150 if (kvm_check_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu)) 9151 kvm_vcpu_flush_tlb_current(vcpu); 9152 if (kvm_check_request(KVM_REQ_HV_TLB_FLUSH, vcpu)) 9153 kvm_vcpu_flush_tlb_guest(vcpu); 9154 9155 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) { 9156 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS; 9157 r = 0; 9158 goto out; 9159 } 9160 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) { 9161 if (is_guest_mode(vcpu)) { 9162 kvm_x86_ops.nested_ops->triple_fault(vcpu); 9163 } else { 9164 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN; 9165 vcpu->mmio_needed = 0; 9166 r = 0; 9167 goto out; 9168 } 9169 } 9170 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) { 9171 /* Page is swapped out. Do synthetic halt */ 9172 vcpu->arch.apf.halted = true; 9173 r = 1; 9174 goto out; 9175 } 9176 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu)) 9177 record_steal_time(vcpu); 9178 if (kvm_check_request(KVM_REQ_SMI, vcpu)) 9179 process_smi(vcpu); 9180 if (kvm_check_request(KVM_REQ_NMI, vcpu)) 9181 process_nmi(vcpu); 9182 if (kvm_check_request(KVM_REQ_PMU, vcpu)) 9183 kvm_pmu_handle_event(vcpu); 9184 if (kvm_check_request(KVM_REQ_PMI, vcpu)) 9185 kvm_pmu_deliver_pmi(vcpu); 9186 if (kvm_check_request(KVM_REQ_IOAPIC_EOI_EXIT, vcpu)) { 9187 BUG_ON(vcpu->arch.pending_ioapic_eoi > 255); 9188 if (test_bit(vcpu->arch.pending_ioapic_eoi, 9189 vcpu->arch.ioapic_handled_vectors)) { 9190 vcpu->run->exit_reason = KVM_EXIT_IOAPIC_EOI; 9191 vcpu->run->eoi.vector = 9192 vcpu->arch.pending_ioapic_eoi; 9193 r = 0; 9194 goto out; 9195 } 9196 } 9197 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu)) 9198 vcpu_scan_ioapic(vcpu); 9199 if (kvm_check_request(KVM_REQ_LOAD_EOI_EXITMAP, vcpu)) 9200 vcpu_load_eoi_exitmap(vcpu); 9201 if (kvm_check_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu)) 9202 kvm_vcpu_reload_apic_access_page(vcpu); 9203 if (kvm_check_request(KVM_REQ_HV_CRASH, vcpu)) { 9204 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT; 9205 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_CRASH; 9206 r = 0; 9207 goto out; 9208 } 9209 if (kvm_check_request(KVM_REQ_HV_RESET, vcpu)) { 9210 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT; 9211 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_RESET; 9212 r = 0; 9213 goto out; 9214 } 9215 if (kvm_check_request(KVM_REQ_HV_EXIT, vcpu)) { 9216 struct kvm_vcpu_hv *hv_vcpu = to_hv_vcpu(vcpu); 9217 9218 vcpu->run->exit_reason = KVM_EXIT_HYPERV; 9219 vcpu->run->hyperv = hv_vcpu->exit; 9220 r = 0; 9221 goto out; 9222 } 9223 9224 /* 9225 * KVM_REQ_HV_STIMER has to be processed after 9226 * KVM_REQ_CLOCK_UPDATE, because Hyper-V SynIC timers 9227 * depend on the guest clock being up-to-date 9228 */ 9229 if (kvm_check_request(KVM_REQ_HV_STIMER, vcpu)) 9230 kvm_hv_process_stimers(vcpu); 9231 if (kvm_check_request(KVM_REQ_APICV_UPDATE, vcpu)) 9232 kvm_vcpu_update_apicv(vcpu); 9233 if (kvm_check_request(KVM_REQ_APF_READY, vcpu)) 9234 kvm_check_async_pf_completion(vcpu); 9235 if (kvm_check_request(KVM_REQ_MSR_FILTER_CHANGED, vcpu)) 9236 static_call(kvm_x86_msr_filter_changed)(vcpu); 9237 9238 if (kvm_check_request(KVM_REQ_UPDATE_CPU_DIRTY_LOGGING, vcpu)) 9239 static_call(kvm_x86_update_cpu_dirty_logging)(vcpu); 9240 } 9241 9242 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win || 9243 kvm_xen_has_interrupt(vcpu)) { 9244 ++vcpu->stat.req_event; 9245 kvm_apic_accept_events(vcpu); 9246 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) { 9247 r = 1; 9248 goto out; 9249 } 9250 9251 inject_pending_event(vcpu, &req_immediate_exit); 9252 if (req_int_win) 9253 static_call(kvm_x86_enable_irq_window)(vcpu); 9254 9255 if (kvm_lapic_enabled(vcpu)) { 9256 update_cr8_intercept(vcpu); 9257 kvm_lapic_sync_to_vapic(vcpu); 9258 } 9259 } 9260 9261 r = kvm_mmu_reload(vcpu); 9262 if (unlikely(r)) { 9263 goto cancel_injection; 9264 } 9265 9266 preempt_disable(); 9267 9268 static_call(kvm_x86_prepare_guest_switch)(vcpu); 9269 9270 /* 9271 * Disable IRQs before setting IN_GUEST_MODE. Posted interrupt 9272 * IPI are then delayed after guest entry, which ensures that they 9273 * result in virtual interrupt delivery. 9274 */ 9275 local_irq_disable(); 9276 vcpu->mode = IN_GUEST_MODE; 9277 9278 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx); 9279 9280 /* 9281 * 1) We should set ->mode before checking ->requests. Please see 9282 * the comment in kvm_vcpu_exiting_guest_mode(). 9283 * 9284 * 2) For APICv, we should set ->mode before checking PID.ON. This 9285 * pairs with the memory barrier implicit in pi_test_and_set_on 9286 * (see vmx_deliver_posted_interrupt). 9287 * 9288 * 3) This also orders the write to mode from any reads to the page 9289 * tables done while the VCPU is running. Please see the comment 9290 * in kvm_flush_remote_tlbs. 9291 */ 9292 smp_mb__after_srcu_read_unlock(); 9293 9294 /* 9295 * This handles the case where a posted interrupt was 9296 * notified with kvm_vcpu_kick. 9297 */ 9298 if (kvm_lapic_enabled(vcpu) && vcpu->arch.apicv_active) 9299 static_call(kvm_x86_sync_pir_to_irr)(vcpu); 9300 9301 if (kvm_vcpu_exit_request(vcpu)) { 9302 vcpu->mode = OUTSIDE_GUEST_MODE; 9303 smp_wmb(); 9304 local_irq_enable(); 9305 preempt_enable(); 9306 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu); 9307 r = 1; 9308 goto cancel_injection; 9309 } 9310 9311 if (req_immediate_exit) { 9312 kvm_make_request(KVM_REQ_EVENT, vcpu); 9313 static_call(kvm_x86_request_immediate_exit)(vcpu); 9314 } 9315 9316 fpregs_assert_state_consistent(); 9317 if (test_thread_flag(TIF_NEED_FPU_LOAD)) 9318 switch_fpu_return(); 9319 9320 if (unlikely(vcpu->arch.switch_db_regs)) { 9321 set_debugreg(0, 7); 9322 set_debugreg(vcpu->arch.eff_db[0], 0); 9323 set_debugreg(vcpu->arch.eff_db[1], 1); 9324 set_debugreg(vcpu->arch.eff_db[2], 2); 9325 set_debugreg(vcpu->arch.eff_db[3], 3); 9326 set_debugreg(vcpu->arch.dr6, 6); 9327 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD; 9328 } 9329 9330 for (;;) { 9331 exit_fastpath = static_call(kvm_x86_run)(vcpu); 9332 if (likely(exit_fastpath != EXIT_FASTPATH_REENTER_GUEST)) 9333 break; 9334 9335 if (unlikely(kvm_vcpu_exit_request(vcpu))) { 9336 exit_fastpath = EXIT_FASTPATH_EXIT_HANDLED; 9337 break; 9338 } 9339 9340 if (vcpu->arch.apicv_active) 9341 static_call(kvm_x86_sync_pir_to_irr)(vcpu); 9342 } 9343 9344 /* 9345 * Do this here before restoring debug registers on the host. And 9346 * since we do this before handling the vmexit, a DR access vmexit 9347 * can (a) read the correct value of the debug registers, (b) set 9348 * KVM_DEBUGREG_WONT_EXIT again. 9349 */ 9350 if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) { 9351 WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP); 9352 static_call(kvm_x86_sync_dirty_debug_regs)(vcpu); 9353 kvm_update_dr0123(vcpu); 9354 kvm_update_dr7(vcpu); 9355 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD; 9356 } 9357 9358 /* 9359 * If the guest has used debug registers, at least dr7 9360 * will be disabled while returning to the host. 9361 * If we don't have active breakpoints in the host, we don't 9362 * care about the messed up debug address registers. But if 9363 * we have some of them active, restore the old state. 9364 */ 9365 if (hw_breakpoint_active()) 9366 hw_breakpoint_restore(); 9367 9368 vcpu->arch.last_vmentry_cpu = vcpu->cpu; 9369 vcpu->arch.last_guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc()); 9370 9371 vcpu->mode = OUTSIDE_GUEST_MODE; 9372 smp_wmb(); 9373 9374 static_call(kvm_x86_handle_exit_irqoff)(vcpu); 9375 9376 /* 9377 * Consume any pending interrupts, including the possible source of 9378 * VM-Exit on SVM and any ticks that occur between VM-Exit and now. 9379 * An instruction is required after local_irq_enable() to fully unblock 9380 * interrupts on processors that implement an interrupt shadow, the 9381 * stat.exits increment will do nicely. 9382 */ 9383 kvm_before_interrupt(vcpu); 9384 local_irq_enable(); 9385 ++vcpu->stat.exits; 9386 local_irq_disable(); 9387 kvm_after_interrupt(vcpu); 9388 9389 /* 9390 * Wait until after servicing IRQs to account guest time so that any 9391 * ticks that occurred while running the guest are properly accounted 9392 * to the guest. Waiting until IRQs are enabled degrades the accuracy 9393 * of accounting via context tracking, but the loss of accuracy is 9394 * acceptable for all known use cases. 9395 */ 9396 vtime_account_guest_exit(); 9397 9398 if (lapic_in_kernel(vcpu)) { 9399 s64 delta = vcpu->arch.apic->lapic_timer.advance_expire_delta; 9400 if (delta != S64_MIN) { 9401 trace_kvm_wait_lapic_expire(vcpu->vcpu_id, delta); 9402 vcpu->arch.apic->lapic_timer.advance_expire_delta = S64_MIN; 9403 } 9404 } 9405 9406 local_irq_enable(); 9407 preempt_enable(); 9408 9409 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu); 9410 9411 /* 9412 * Profile KVM exit RIPs: 9413 */ 9414 if (unlikely(prof_on == KVM_PROFILING)) { 9415 unsigned long rip = kvm_rip_read(vcpu); 9416 profile_hit(KVM_PROFILING, (void *)rip); 9417 } 9418 9419 if (unlikely(vcpu->arch.tsc_always_catchup)) 9420 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 9421 9422 if (vcpu->arch.apic_attention) 9423 kvm_lapic_sync_from_vapic(vcpu); 9424 9425 r = static_call(kvm_x86_handle_exit)(vcpu, exit_fastpath); 9426 return r; 9427 9428 cancel_injection: 9429 if (req_immediate_exit) 9430 kvm_make_request(KVM_REQ_EVENT, vcpu); 9431 static_call(kvm_x86_cancel_injection)(vcpu); 9432 if (unlikely(vcpu->arch.apic_attention)) 9433 kvm_lapic_sync_from_vapic(vcpu); 9434 out: 9435 return r; 9436 } 9437 9438 static inline int vcpu_block(struct kvm *kvm, struct kvm_vcpu *vcpu) 9439 { 9440 if (!kvm_arch_vcpu_runnable(vcpu) && 9441 (!kvm_x86_ops.pre_block || static_call(kvm_x86_pre_block)(vcpu) == 0)) { 9442 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx); 9443 kvm_vcpu_block(vcpu); 9444 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu); 9445 9446 if (kvm_x86_ops.post_block) 9447 static_call(kvm_x86_post_block)(vcpu); 9448 9449 if (!kvm_check_request(KVM_REQ_UNHALT, vcpu)) 9450 return 1; 9451 } 9452 9453 kvm_apic_accept_events(vcpu); 9454 switch(vcpu->arch.mp_state) { 9455 case KVM_MP_STATE_HALTED: 9456 case KVM_MP_STATE_AP_RESET_HOLD: 9457 vcpu->arch.pv.pv_unhalted = false; 9458 vcpu->arch.mp_state = 9459 KVM_MP_STATE_RUNNABLE; 9460 fallthrough; 9461 case KVM_MP_STATE_RUNNABLE: 9462 vcpu->arch.apf.halted = false; 9463 break; 9464 case KVM_MP_STATE_INIT_RECEIVED: 9465 break; 9466 default: 9467 return -EINTR; 9468 } 9469 return 1; 9470 } 9471 9472 static inline bool kvm_vcpu_running(struct kvm_vcpu *vcpu) 9473 { 9474 if (is_guest_mode(vcpu)) 9475 kvm_check_nested_events(vcpu); 9476 9477 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE && 9478 !vcpu->arch.apf.halted); 9479 } 9480 9481 static int vcpu_run(struct kvm_vcpu *vcpu) 9482 { 9483 int r; 9484 struct kvm *kvm = vcpu->kvm; 9485 9486 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu); 9487 vcpu->arch.l1tf_flush_l1d = true; 9488 9489 for (;;) { 9490 if (kvm_vcpu_running(vcpu)) { 9491 r = vcpu_enter_guest(vcpu); 9492 } else { 9493 r = vcpu_block(kvm, vcpu); 9494 } 9495 9496 if (r <= 0) 9497 break; 9498 9499 kvm_clear_request(KVM_REQ_PENDING_TIMER, vcpu); 9500 if (kvm_cpu_has_pending_timer(vcpu)) 9501 kvm_inject_pending_timer_irqs(vcpu); 9502 9503 if (dm_request_for_irq_injection(vcpu) && 9504 kvm_vcpu_ready_for_interrupt_injection(vcpu)) { 9505 r = 0; 9506 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN; 9507 ++vcpu->stat.request_irq_exits; 9508 break; 9509 } 9510 9511 if (__xfer_to_guest_mode_work_pending()) { 9512 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx); 9513 r = xfer_to_guest_mode_handle_work(vcpu); 9514 if (r) 9515 return r; 9516 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu); 9517 } 9518 } 9519 9520 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx); 9521 9522 return r; 9523 } 9524 9525 static inline int complete_emulated_io(struct kvm_vcpu *vcpu) 9526 { 9527 int r; 9528 9529 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu); 9530 r = kvm_emulate_instruction(vcpu, EMULTYPE_NO_DECODE); 9531 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx); 9532 return r; 9533 } 9534 9535 static int complete_emulated_pio(struct kvm_vcpu *vcpu) 9536 { 9537 BUG_ON(!vcpu->arch.pio.count); 9538 9539 return complete_emulated_io(vcpu); 9540 } 9541 9542 /* 9543 * Implements the following, as a state machine: 9544 * 9545 * read: 9546 * for each fragment 9547 * for each mmio piece in the fragment 9548 * write gpa, len 9549 * exit 9550 * copy data 9551 * execute insn 9552 * 9553 * write: 9554 * for each fragment 9555 * for each mmio piece in the fragment 9556 * write gpa, len 9557 * copy data 9558 * exit 9559 */ 9560 static int complete_emulated_mmio(struct kvm_vcpu *vcpu) 9561 { 9562 struct kvm_run *run = vcpu->run; 9563 struct kvm_mmio_fragment *frag; 9564 unsigned len; 9565 9566 BUG_ON(!vcpu->mmio_needed); 9567 9568 /* Complete previous fragment */ 9569 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment]; 9570 len = min(8u, frag->len); 9571 if (!vcpu->mmio_is_write) 9572 memcpy(frag->data, run->mmio.data, len); 9573 9574 if (frag->len <= 8) { 9575 /* Switch to the next fragment. */ 9576 frag++; 9577 vcpu->mmio_cur_fragment++; 9578 } else { 9579 /* Go forward to the next mmio piece. */ 9580 frag->data += len; 9581 frag->gpa += len; 9582 frag->len -= len; 9583 } 9584 9585 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) { 9586 vcpu->mmio_needed = 0; 9587 9588 /* FIXME: return into emulator if single-stepping. */ 9589 if (vcpu->mmio_is_write) 9590 return 1; 9591 vcpu->mmio_read_completed = 1; 9592 return complete_emulated_io(vcpu); 9593 } 9594 9595 run->exit_reason = KVM_EXIT_MMIO; 9596 run->mmio.phys_addr = frag->gpa; 9597 if (vcpu->mmio_is_write) 9598 memcpy(run->mmio.data, frag->data, min(8u, frag->len)); 9599 run->mmio.len = min(8u, frag->len); 9600 run->mmio.is_write = vcpu->mmio_is_write; 9601 vcpu->arch.complete_userspace_io = complete_emulated_mmio; 9602 return 0; 9603 } 9604 9605 static void kvm_save_current_fpu(struct fpu *fpu) 9606 { 9607 /* 9608 * If the target FPU state is not resident in the CPU registers, just 9609 * memcpy() from current, else save CPU state directly to the target. 9610 */ 9611 if (test_thread_flag(TIF_NEED_FPU_LOAD)) 9612 memcpy(&fpu->state, ¤t->thread.fpu.state, 9613 fpu_kernel_xstate_size); 9614 else 9615 copy_fpregs_to_fpstate(fpu); 9616 } 9617 9618 /* Swap (qemu) user FPU context for the guest FPU context. */ 9619 static void kvm_load_guest_fpu(struct kvm_vcpu *vcpu) 9620 { 9621 fpregs_lock(); 9622 9623 kvm_save_current_fpu(vcpu->arch.user_fpu); 9624 9625 /* 9626 * Guests with protected state can't have it set by the hypervisor, 9627 * so skip trying to set it. 9628 */ 9629 if (vcpu->arch.guest_fpu) 9630 /* PKRU is separately restored in kvm_x86_ops.run. */ 9631 __copy_kernel_to_fpregs(&vcpu->arch.guest_fpu->state, 9632 ~XFEATURE_MASK_PKRU); 9633 9634 fpregs_mark_activate(); 9635 fpregs_unlock(); 9636 9637 trace_kvm_fpu(1); 9638 } 9639 9640 /* When vcpu_run ends, restore user space FPU context. */ 9641 static void kvm_put_guest_fpu(struct kvm_vcpu *vcpu) 9642 { 9643 fpregs_lock(); 9644 9645 /* 9646 * Guests with protected state can't have it read by the hypervisor, 9647 * so skip trying to save it. 9648 */ 9649 if (vcpu->arch.guest_fpu) 9650 kvm_save_current_fpu(vcpu->arch.guest_fpu); 9651 9652 copy_kernel_to_fpregs(&vcpu->arch.user_fpu->state); 9653 9654 fpregs_mark_activate(); 9655 fpregs_unlock(); 9656 9657 ++vcpu->stat.fpu_reload; 9658 trace_kvm_fpu(0); 9659 } 9660 9661 int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu) 9662 { 9663 struct kvm_run *kvm_run = vcpu->run; 9664 int r; 9665 9666 vcpu_load(vcpu); 9667 kvm_sigset_activate(vcpu); 9668 kvm_run->flags = 0; 9669 kvm_load_guest_fpu(vcpu); 9670 9671 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) { 9672 if (kvm_run->immediate_exit) { 9673 r = -EINTR; 9674 goto out; 9675 } 9676 kvm_vcpu_block(vcpu); 9677 kvm_apic_accept_events(vcpu); 9678 kvm_clear_request(KVM_REQ_UNHALT, vcpu); 9679 r = -EAGAIN; 9680 if (signal_pending(current)) { 9681 r = -EINTR; 9682 kvm_run->exit_reason = KVM_EXIT_INTR; 9683 ++vcpu->stat.signal_exits; 9684 } 9685 goto out; 9686 } 9687 9688 if (kvm_run->kvm_valid_regs & ~KVM_SYNC_X86_VALID_FIELDS) { 9689 r = -EINVAL; 9690 goto out; 9691 } 9692 9693 if (kvm_run->kvm_dirty_regs) { 9694 r = sync_regs(vcpu); 9695 if (r != 0) 9696 goto out; 9697 } 9698 9699 /* re-sync apic's tpr */ 9700 if (!lapic_in_kernel(vcpu)) { 9701 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) { 9702 r = -EINVAL; 9703 goto out; 9704 } 9705 } 9706 9707 if (unlikely(vcpu->arch.complete_userspace_io)) { 9708 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io; 9709 vcpu->arch.complete_userspace_io = NULL; 9710 r = cui(vcpu); 9711 if (r <= 0) 9712 goto out; 9713 } else 9714 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed); 9715 9716 if (kvm_run->immediate_exit) 9717 r = -EINTR; 9718 else 9719 r = vcpu_run(vcpu); 9720 9721 out: 9722 kvm_put_guest_fpu(vcpu); 9723 if (kvm_run->kvm_valid_regs) 9724 store_regs(vcpu); 9725 post_kvm_run_save(vcpu); 9726 kvm_sigset_deactivate(vcpu); 9727 9728 vcpu_put(vcpu); 9729 return r; 9730 } 9731 9732 static void __get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) 9733 { 9734 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) { 9735 /* 9736 * We are here if userspace calls get_regs() in the middle of 9737 * instruction emulation. Registers state needs to be copied 9738 * back from emulation context to vcpu. Userspace shouldn't do 9739 * that usually, but some bad designed PV devices (vmware 9740 * backdoor interface) need this to work 9741 */ 9742 emulator_writeback_register_cache(vcpu->arch.emulate_ctxt); 9743 vcpu->arch.emulate_regs_need_sync_to_vcpu = false; 9744 } 9745 regs->rax = kvm_rax_read(vcpu); 9746 regs->rbx = kvm_rbx_read(vcpu); 9747 regs->rcx = kvm_rcx_read(vcpu); 9748 regs->rdx = kvm_rdx_read(vcpu); 9749 regs->rsi = kvm_rsi_read(vcpu); 9750 regs->rdi = kvm_rdi_read(vcpu); 9751 regs->rsp = kvm_rsp_read(vcpu); 9752 regs->rbp = kvm_rbp_read(vcpu); 9753 #ifdef CONFIG_X86_64 9754 regs->r8 = kvm_r8_read(vcpu); 9755 regs->r9 = kvm_r9_read(vcpu); 9756 regs->r10 = kvm_r10_read(vcpu); 9757 regs->r11 = kvm_r11_read(vcpu); 9758 regs->r12 = kvm_r12_read(vcpu); 9759 regs->r13 = kvm_r13_read(vcpu); 9760 regs->r14 = kvm_r14_read(vcpu); 9761 regs->r15 = kvm_r15_read(vcpu); 9762 #endif 9763 9764 regs->rip = kvm_rip_read(vcpu); 9765 regs->rflags = kvm_get_rflags(vcpu); 9766 } 9767 9768 int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) 9769 { 9770 vcpu_load(vcpu); 9771 __get_regs(vcpu, regs); 9772 vcpu_put(vcpu); 9773 return 0; 9774 } 9775 9776 static void __set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) 9777 { 9778 vcpu->arch.emulate_regs_need_sync_from_vcpu = true; 9779 vcpu->arch.emulate_regs_need_sync_to_vcpu = false; 9780 9781 kvm_rax_write(vcpu, regs->rax); 9782 kvm_rbx_write(vcpu, regs->rbx); 9783 kvm_rcx_write(vcpu, regs->rcx); 9784 kvm_rdx_write(vcpu, regs->rdx); 9785 kvm_rsi_write(vcpu, regs->rsi); 9786 kvm_rdi_write(vcpu, regs->rdi); 9787 kvm_rsp_write(vcpu, regs->rsp); 9788 kvm_rbp_write(vcpu, regs->rbp); 9789 #ifdef CONFIG_X86_64 9790 kvm_r8_write(vcpu, regs->r8); 9791 kvm_r9_write(vcpu, regs->r9); 9792 kvm_r10_write(vcpu, regs->r10); 9793 kvm_r11_write(vcpu, regs->r11); 9794 kvm_r12_write(vcpu, regs->r12); 9795 kvm_r13_write(vcpu, regs->r13); 9796 kvm_r14_write(vcpu, regs->r14); 9797 kvm_r15_write(vcpu, regs->r15); 9798 #endif 9799 9800 kvm_rip_write(vcpu, regs->rip); 9801 kvm_set_rflags(vcpu, regs->rflags | X86_EFLAGS_FIXED); 9802 9803 vcpu->arch.exception.pending = false; 9804 9805 kvm_make_request(KVM_REQ_EVENT, vcpu); 9806 } 9807 9808 int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) 9809 { 9810 vcpu_load(vcpu); 9811 __set_regs(vcpu, regs); 9812 vcpu_put(vcpu); 9813 return 0; 9814 } 9815 9816 void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l) 9817 { 9818 struct kvm_segment cs; 9819 9820 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS); 9821 *db = cs.db; 9822 *l = cs.l; 9823 } 9824 EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits); 9825 9826 static void __get_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs) 9827 { 9828 struct desc_ptr dt; 9829 9830 if (vcpu->arch.guest_state_protected) 9831 goto skip_protected_regs; 9832 9833 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS); 9834 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS); 9835 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES); 9836 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS); 9837 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS); 9838 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS); 9839 9840 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR); 9841 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR); 9842 9843 static_call(kvm_x86_get_idt)(vcpu, &dt); 9844 sregs->idt.limit = dt.size; 9845 sregs->idt.base = dt.address; 9846 static_call(kvm_x86_get_gdt)(vcpu, &dt); 9847 sregs->gdt.limit = dt.size; 9848 sregs->gdt.base = dt.address; 9849 9850 sregs->cr2 = vcpu->arch.cr2; 9851 sregs->cr3 = kvm_read_cr3(vcpu); 9852 9853 skip_protected_regs: 9854 sregs->cr0 = kvm_read_cr0(vcpu); 9855 sregs->cr4 = kvm_read_cr4(vcpu); 9856 sregs->cr8 = kvm_get_cr8(vcpu); 9857 sregs->efer = vcpu->arch.efer; 9858 sregs->apic_base = kvm_get_apic_base(vcpu); 9859 9860 memset(sregs->interrupt_bitmap, 0, sizeof(sregs->interrupt_bitmap)); 9861 9862 if (vcpu->arch.interrupt.injected && !vcpu->arch.interrupt.soft) 9863 set_bit(vcpu->arch.interrupt.nr, 9864 (unsigned long *)sregs->interrupt_bitmap); 9865 } 9866 9867 int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu, 9868 struct kvm_sregs *sregs) 9869 { 9870 vcpu_load(vcpu); 9871 __get_sregs(vcpu, sregs); 9872 vcpu_put(vcpu); 9873 return 0; 9874 } 9875 9876 int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu, 9877 struct kvm_mp_state *mp_state) 9878 { 9879 vcpu_load(vcpu); 9880 if (kvm_mpx_supported()) 9881 kvm_load_guest_fpu(vcpu); 9882 9883 kvm_apic_accept_events(vcpu); 9884 if ((vcpu->arch.mp_state == KVM_MP_STATE_HALTED || 9885 vcpu->arch.mp_state == KVM_MP_STATE_AP_RESET_HOLD) && 9886 vcpu->arch.pv.pv_unhalted) 9887 mp_state->mp_state = KVM_MP_STATE_RUNNABLE; 9888 else 9889 mp_state->mp_state = vcpu->arch.mp_state; 9890 9891 if (kvm_mpx_supported()) 9892 kvm_put_guest_fpu(vcpu); 9893 vcpu_put(vcpu); 9894 return 0; 9895 } 9896 9897 int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu, 9898 struct kvm_mp_state *mp_state) 9899 { 9900 int ret = -EINVAL; 9901 9902 vcpu_load(vcpu); 9903 9904 if (!lapic_in_kernel(vcpu) && 9905 mp_state->mp_state != KVM_MP_STATE_RUNNABLE) 9906 goto out; 9907 9908 /* 9909 * KVM_MP_STATE_INIT_RECEIVED means the processor is in 9910 * INIT state; latched init should be reported using 9911 * KVM_SET_VCPU_EVENTS, so reject it here. 9912 */ 9913 if ((kvm_vcpu_latch_init(vcpu) || vcpu->arch.smi_pending) && 9914 (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED || 9915 mp_state->mp_state == KVM_MP_STATE_INIT_RECEIVED)) 9916 goto out; 9917 9918 if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) { 9919 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED; 9920 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events); 9921 } else 9922 vcpu->arch.mp_state = mp_state->mp_state; 9923 kvm_make_request(KVM_REQ_EVENT, vcpu); 9924 9925 ret = 0; 9926 out: 9927 vcpu_put(vcpu); 9928 return ret; 9929 } 9930 9931 int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index, 9932 int reason, bool has_error_code, u32 error_code) 9933 { 9934 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt; 9935 int ret; 9936 9937 init_emulate_ctxt(vcpu); 9938 9939 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason, 9940 has_error_code, error_code); 9941 if (ret) { 9942 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR; 9943 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION; 9944 vcpu->run->internal.ndata = 0; 9945 return 0; 9946 } 9947 9948 kvm_rip_write(vcpu, ctxt->eip); 9949 kvm_set_rflags(vcpu, ctxt->eflags); 9950 return 1; 9951 } 9952 EXPORT_SYMBOL_GPL(kvm_task_switch); 9953 9954 static bool kvm_is_valid_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs) 9955 { 9956 if ((sregs->efer & EFER_LME) && (sregs->cr0 & X86_CR0_PG)) { 9957 /* 9958 * When EFER.LME and CR0.PG are set, the processor is in 9959 * 64-bit mode (though maybe in a 32-bit code segment). 9960 * CR4.PAE and EFER.LMA must be set. 9961 */ 9962 if (!(sregs->cr4 & X86_CR4_PAE) || !(sregs->efer & EFER_LMA)) 9963 return false; 9964 if (kvm_vcpu_is_illegal_gpa(vcpu, sregs->cr3)) 9965 return false; 9966 } else { 9967 /* 9968 * Not in 64-bit mode: EFER.LMA is clear and the code 9969 * segment cannot be 64-bit. 9970 */ 9971 if (sregs->efer & EFER_LMA || sregs->cs.l) 9972 return false; 9973 } 9974 9975 return kvm_is_valid_cr4(vcpu, sregs->cr4); 9976 } 9977 9978 static int __set_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs) 9979 { 9980 struct msr_data apic_base_msr; 9981 int mmu_reset_needed = 0; 9982 int pending_vec, max_bits, idx; 9983 struct desc_ptr dt; 9984 int ret = -EINVAL; 9985 9986 if (!kvm_is_valid_sregs(vcpu, sregs)) 9987 goto out; 9988 9989 apic_base_msr.data = sregs->apic_base; 9990 apic_base_msr.host_initiated = true; 9991 if (kvm_set_apic_base(vcpu, &apic_base_msr)) 9992 goto out; 9993 9994 if (vcpu->arch.guest_state_protected) 9995 goto skip_protected_regs; 9996 9997 dt.size = sregs->idt.limit; 9998 dt.address = sregs->idt.base; 9999 static_call(kvm_x86_set_idt)(vcpu, &dt); 10000 dt.size = sregs->gdt.limit; 10001 dt.address = sregs->gdt.base; 10002 static_call(kvm_x86_set_gdt)(vcpu, &dt); 10003 10004 vcpu->arch.cr2 = sregs->cr2; 10005 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3; 10006 vcpu->arch.cr3 = sregs->cr3; 10007 kvm_register_mark_available(vcpu, VCPU_EXREG_CR3); 10008 10009 kvm_set_cr8(vcpu, sregs->cr8); 10010 10011 mmu_reset_needed |= vcpu->arch.efer != sregs->efer; 10012 static_call(kvm_x86_set_efer)(vcpu, sregs->efer); 10013 10014 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0; 10015 static_call(kvm_x86_set_cr0)(vcpu, sregs->cr0); 10016 vcpu->arch.cr0 = sregs->cr0; 10017 10018 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4; 10019 static_call(kvm_x86_set_cr4)(vcpu, sregs->cr4); 10020 10021 idx = srcu_read_lock(&vcpu->kvm->srcu); 10022 if (is_pae_paging(vcpu)) { 10023 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu)); 10024 mmu_reset_needed = 1; 10025 } 10026 srcu_read_unlock(&vcpu->kvm->srcu, idx); 10027 10028 if (mmu_reset_needed) 10029 kvm_mmu_reset_context(vcpu); 10030 10031 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS); 10032 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS); 10033 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES); 10034 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS); 10035 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS); 10036 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS); 10037 10038 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR); 10039 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR); 10040 10041 update_cr8_intercept(vcpu); 10042 10043 /* Older userspace won't unhalt the vcpu on reset. */ 10044 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 && 10045 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 && 10046 !is_protmode(vcpu)) 10047 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; 10048 10049 skip_protected_regs: 10050 max_bits = KVM_NR_INTERRUPTS; 10051 pending_vec = find_first_bit( 10052 (const unsigned long *)sregs->interrupt_bitmap, max_bits); 10053 if (pending_vec < max_bits) { 10054 kvm_queue_interrupt(vcpu, pending_vec, false); 10055 pr_debug("Set back pending irq %d\n", pending_vec); 10056 } 10057 10058 kvm_make_request(KVM_REQ_EVENT, vcpu); 10059 10060 ret = 0; 10061 out: 10062 return ret; 10063 } 10064 10065 int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu, 10066 struct kvm_sregs *sregs) 10067 { 10068 int ret; 10069 10070 vcpu_load(vcpu); 10071 ret = __set_sregs(vcpu, sregs); 10072 vcpu_put(vcpu); 10073 return ret; 10074 } 10075 10076 int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu, 10077 struct kvm_guest_debug *dbg) 10078 { 10079 unsigned long rflags; 10080 int i, r; 10081 10082 if (vcpu->arch.guest_state_protected) 10083 return -EINVAL; 10084 10085 vcpu_load(vcpu); 10086 10087 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) { 10088 r = -EBUSY; 10089 if (vcpu->arch.exception.pending) 10090 goto out; 10091 if (dbg->control & KVM_GUESTDBG_INJECT_DB) 10092 kvm_queue_exception(vcpu, DB_VECTOR); 10093 else 10094 kvm_queue_exception(vcpu, BP_VECTOR); 10095 } 10096 10097 /* 10098 * Read rflags as long as potentially injected trace flags are still 10099 * filtered out. 10100 */ 10101 rflags = kvm_get_rflags(vcpu); 10102 10103 vcpu->guest_debug = dbg->control; 10104 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE)) 10105 vcpu->guest_debug = 0; 10106 10107 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) { 10108 for (i = 0; i < KVM_NR_DB_REGS; ++i) 10109 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i]; 10110 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7]; 10111 } else { 10112 for (i = 0; i < KVM_NR_DB_REGS; i++) 10113 vcpu->arch.eff_db[i] = vcpu->arch.db[i]; 10114 } 10115 kvm_update_dr7(vcpu); 10116 10117 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) 10118 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) + 10119 get_segment_base(vcpu, VCPU_SREG_CS); 10120 10121 /* 10122 * Trigger an rflags update that will inject or remove the trace 10123 * flags. 10124 */ 10125 kvm_set_rflags(vcpu, rflags); 10126 10127 static_call(kvm_x86_update_exception_bitmap)(vcpu); 10128 10129 r = 0; 10130 10131 out: 10132 vcpu_put(vcpu); 10133 return r; 10134 } 10135 10136 /* 10137 * Translate a guest virtual address to a guest physical address. 10138 */ 10139 int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu, 10140 struct kvm_translation *tr) 10141 { 10142 unsigned long vaddr = tr->linear_address; 10143 gpa_t gpa; 10144 int idx; 10145 10146 vcpu_load(vcpu); 10147 10148 idx = srcu_read_lock(&vcpu->kvm->srcu); 10149 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL); 10150 srcu_read_unlock(&vcpu->kvm->srcu, idx); 10151 tr->physical_address = gpa; 10152 tr->valid = gpa != UNMAPPED_GVA; 10153 tr->writeable = 1; 10154 tr->usermode = 0; 10155 10156 vcpu_put(vcpu); 10157 return 0; 10158 } 10159 10160 int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu) 10161 { 10162 struct fxregs_state *fxsave; 10163 10164 if (!vcpu->arch.guest_fpu) 10165 return 0; 10166 10167 vcpu_load(vcpu); 10168 10169 fxsave = &vcpu->arch.guest_fpu->state.fxsave; 10170 memcpy(fpu->fpr, fxsave->st_space, 128); 10171 fpu->fcw = fxsave->cwd; 10172 fpu->fsw = fxsave->swd; 10173 fpu->ftwx = fxsave->twd; 10174 fpu->last_opcode = fxsave->fop; 10175 fpu->last_ip = fxsave->rip; 10176 fpu->last_dp = fxsave->rdp; 10177 memcpy(fpu->xmm, fxsave->xmm_space, sizeof(fxsave->xmm_space)); 10178 10179 vcpu_put(vcpu); 10180 return 0; 10181 } 10182 10183 int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu) 10184 { 10185 struct fxregs_state *fxsave; 10186 10187 if (!vcpu->arch.guest_fpu) 10188 return 0; 10189 10190 vcpu_load(vcpu); 10191 10192 fxsave = &vcpu->arch.guest_fpu->state.fxsave; 10193 10194 memcpy(fxsave->st_space, fpu->fpr, 128); 10195 fxsave->cwd = fpu->fcw; 10196 fxsave->swd = fpu->fsw; 10197 fxsave->twd = fpu->ftwx; 10198 fxsave->fop = fpu->last_opcode; 10199 fxsave->rip = fpu->last_ip; 10200 fxsave->rdp = fpu->last_dp; 10201 memcpy(fxsave->xmm_space, fpu->xmm, sizeof(fxsave->xmm_space)); 10202 10203 vcpu_put(vcpu); 10204 return 0; 10205 } 10206 10207 static void store_regs(struct kvm_vcpu *vcpu) 10208 { 10209 BUILD_BUG_ON(sizeof(struct kvm_sync_regs) > SYNC_REGS_SIZE_BYTES); 10210 10211 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_REGS) 10212 __get_regs(vcpu, &vcpu->run->s.regs.regs); 10213 10214 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_SREGS) 10215 __get_sregs(vcpu, &vcpu->run->s.regs.sregs); 10216 10217 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_EVENTS) 10218 kvm_vcpu_ioctl_x86_get_vcpu_events( 10219 vcpu, &vcpu->run->s.regs.events); 10220 } 10221 10222 static int sync_regs(struct kvm_vcpu *vcpu) 10223 { 10224 if (vcpu->run->kvm_dirty_regs & ~KVM_SYNC_X86_VALID_FIELDS) 10225 return -EINVAL; 10226 10227 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_REGS) { 10228 __set_regs(vcpu, &vcpu->run->s.regs.regs); 10229 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_REGS; 10230 } 10231 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_SREGS) { 10232 if (__set_sregs(vcpu, &vcpu->run->s.regs.sregs)) 10233 return -EINVAL; 10234 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_SREGS; 10235 } 10236 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_EVENTS) { 10237 if (kvm_vcpu_ioctl_x86_set_vcpu_events( 10238 vcpu, &vcpu->run->s.regs.events)) 10239 return -EINVAL; 10240 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_EVENTS; 10241 } 10242 10243 return 0; 10244 } 10245 10246 static void fx_init(struct kvm_vcpu *vcpu) 10247 { 10248 if (!vcpu->arch.guest_fpu) 10249 return; 10250 10251 fpstate_init(&vcpu->arch.guest_fpu->state); 10252 if (boot_cpu_has(X86_FEATURE_XSAVES)) 10253 vcpu->arch.guest_fpu->state.xsave.header.xcomp_bv = 10254 host_xcr0 | XSTATE_COMPACTION_ENABLED; 10255 10256 /* 10257 * Ensure guest xcr0 is valid for loading 10258 */ 10259 vcpu->arch.xcr0 = XFEATURE_MASK_FP; 10260 10261 vcpu->arch.cr0 |= X86_CR0_ET; 10262 } 10263 10264 void kvm_free_guest_fpu(struct kvm_vcpu *vcpu) 10265 { 10266 if (vcpu->arch.guest_fpu) { 10267 kmem_cache_free(x86_fpu_cache, vcpu->arch.guest_fpu); 10268 vcpu->arch.guest_fpu = NULL; 10269 } 10270 } 10271 EXPORT_SYMBOL_GPL(kvm_free_guest_fpu); 10272 10273 int kvm_arch_vcpu_precreate(struct kvm *kvm, unsigned int id) 10274 { 10275 if (kvm_check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0) 10276 pr_warn_once("kvm: SMP vm created on host with unstable TSC; " 10277 "guest TSC will not be reliable\n"); 10278 10279 return 0; 10280 } 10281 10282 int kvm_arch_vcpu_create(struct kvm_vcpu *vcpu) 10283 { 10284 struct page *page; 10285 int r; 10286 10287 if (!irqchip_in_kernel(vcpu->kvm) || kvm_vcpu_is_reset_bsp(vcpu)) 10288 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; 10289 else 10290 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED; 10291 10292 kvm_set_tsc_khz(vcpu, max_tsc_khz); 10293 10294 r = kvm_mmu_create(vcpu); 10295 if (r < 0) 10296 return r; 10297 10298 if (irqchip_in_kernel(vcpu->kvm)) { 10299 r = kvm_create_lapic(vcpu, lapic_timer_advance_ns); 10300 if (r < 0) 10301 goto fail_mmu_destroy; 10302 if (kvm_apicv_activated(vcpu->kvm)) 10303 vcpu->arch.apicv_active = true; 10304 } else 10305 static_branch_inc(&kvm_has_noapic_vcpu); 10306 10307 r = -ENOMEM; 10308 10309 page = alloc_page(GFP_KERNEL_ACCOUNT | __GFP_ZERO); 10310 if (!page) 10311 goto fail_free_lapic; 10312 vcpu->arch.pio_data = page_address(page); 10313 10314 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4, 10315 GFP_KERNEL_ACCOUNT); 10316 if (!vcpu->arch.mce_banks) 10317 goto fail_free_pio_data; 10318 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS; 10319 10320 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, 10321 GFP_KERNEL_ACCOUNT)) 10322 goto fail_free_mce_banks; 10323 10324 if (!alloc_emulate_ctxt(vcpu)) 10325 goto free_wbinvd_dirty_mask; 10326 10327 vcpu->arch.user_fpu = kmem_cache_zalloc(x86_fpu_cache, 10328 GFP_KERNEL_ACCOUNT); 10329 if (!vcpu->arch.user_fpu) { 10330 pr_err("kvm: failed to allocate userspace's fpu\n"); 10331 goto free_emulate_ctxt; 10332 } 10333 10334 vcpu->arch.guest_fpu = kmem_cache_zalloc(x86_fpu_cache, 10335 GFP_KERNEL_ACCOUNT); 10336 if (!vcpu->arch.guest_fpu) { 10337 pr_err("kvm: failed to allocate vcpu's fpu\n"); 10338 goto free_user_fpu; 10339 } 10340 fx_init(vcpu); 10341 10342 vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu); 10343 vcpu->arch.reserved_gpa_bits = kvm_vcpu_reserved_gpa_bits_raw(vcpu); 10344 10345 vcpu->arch.pat = MSR_IA32_CR_PAT_DEFAULT; 10346 10347 kvm_async_pf_hash_reset(vcpu); 10348 kvm_pmu_init(vcpu); 10349 10350 vcpu->arch.pending_external_vector = -1; 10351 vcpu->arch.preempted_in_kernel = false; 10352 10353 r = static_call(kvm_x86_vcpu_create)(vcpu); 10354 if (r) 10355 goto free_guest_fpu; 10356 10357 vcpu->arch.arch_capabilities = kvm_get_arch_capabilities(); 10358 vcpu->arch.msr_platform_info = MSR_PLATFORM_INFO_CPUID_FAULT; 10359 kvm_vcpu_mtrr_init(vcpu); 10360 vcpu_load(vcpu); 10361 kvm_vcpu_reset(vcpu, false); 10362 kvm_init_mmu(vcpu, false); 10363 vcpu_put(vcpu); 10364 return 0; 10365 10366 free_guest_fpu: 10367 kvm_free_guest_fpu(vcpu); 10368 free_user_fpu: 10369 kmem_cache_free(x86_fpu_cache, vcpu->arch.user_fpu); 10370 free_emulate_ctxt: 10371 kmem_cache_free(x86_emulator_cache, vcpu->arch.emulate_ctxt); 10372 free_wbinvd_dirty_mask: 10373 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask); 10374 fail_free_mce_banks: 10375 kfree(vcpu->arch.mce_banks); 10376 fail_free_pio_data: 10377 free_page((unsigned long)vcpu->arch.pio_data); 10378 fail_free_lapic: 10379 kvm_free_lapic(vcpu); 10380 fail_mmu_destroy: 10381 kvm_mmu_destroy(vcpu); 10382 return r; 10383 } 10384 10385 void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu) 10386 { 10387 struct kvm *kvm = vcpu->kvm; 10388 10389 if (mutex_lock_killable(&vcpu->mutex)) 10390 return; 10391 vcpu_load(vcpu); 10392 kvm_synchronize_tsc(vcpu, 0); 10393 vcpu_put(vcpu); 10394 10395 /* poll control enabled by default */ 10396 vcpu->arch.msr_kvm_poll_control = 1; 10397 10398 mutex_unlock(&vcpu->mutex); 10399 10400 if (kvmclock_periodic_sync && vcpu->vcpu_idx == 0) 10401 schedule_delayed_work(&kvm->arch.kvmclock_sync_work, 10402 KVMCLOCK_SYNC_PERIOD); 10403 } 10404 10405 void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu) 10406 { 10407 struct gfn_to_pfn_cache *cache = &vcpu->arch.st.cache; 10408 int idx; 10409 10410 kvm_release_pfn(cache->pfn, cache->dirty, cache); 10411 10412 kvmclock_reset(vcpu); 10413 10414 static_call(kvm_x86_vcpu_free)(vcpu); 10415 10416 kmem_cache_free(x86_emulator_cache, vcpu->arch.emulate_ctxt); 10417 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask); 10418 kmem_cache_free(x86_fpu_cache, vcpu->arch.user_fpu); 10419 kvm_free_guest_fpu(vcpu); 10420 10421 kvm_hv_vcpu_uninit(vcpu); 10422 kvm_pmu_destroy(vcpu); 10423 kfree(vcpu->arch.mce_banks); 10424 kvm_free_lapic(vcpu); 10425 idx = srcu_read_lock(&vcpu->kvm->srcu); 10426 kvm_mmu_destroy(vcpu); 10427 srcu_read_unlock(&vcpu->kvm->srcu, idx); 10428 free_page((unsigned long)vcpu->arch.pio_data); 10429 kvfree(vcpu->arch.cpuid_entries); 10430 if (!lapic_in_kernel(vcpu)) 10431 static_branch_dec(&kvm_has_noapic_vcpu); 10432 } 10433 10434 void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event) 10435 { 10436 kvm_lapic_reset(vcpu, init_event); 10437 10438 vcpu->arch.hflags = 0; 10439 10440 vcpu->arch.smi_pending = 0; 10441 vcpu->arch.smi_count = 0; 10442 atomic_set(&vcpu->arch.nmi_queued, 0); 10443 vcpu->arch.nmi_pending = 0; 10444 vcpu->arch.nmi_injected = false; 10445 kvm_clear_interrupt_queue(vcpu); 10446 kvm_clear_exception_queue(vcpu); 10447 10448 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db)); 10449 kvm_update_dr0123(vcpu); 10450 vcpu->arch.dr6 = DR6_ACTIVE_LOW; 10451 vcpu->arch.dr7 = DR7_FIXED_1; 10452 kvm_update_dr7(vcpu); 10453 10454 vcpu->arch.cr2 = 0; 10455 10456 kvm_make_request(KVM_REQ_EVENT, vcpu); 10457 vcpu->arch.apf.msr_en_val = 0; 10458 vcpu->arch.apf.msr_int_val = 0; 10459 vcpu->arch.st.msr_val = 0; 10460 10461 kvmclock_reset(vcpu); 10462 10463 kvm_clear_async_pf_completion_queue(vcpu); 10464 kvm_async_pf_hash_reset(vcpu); 10465 vcpu->arch.apf.halted = false; 10466 10467 if (vcpu->arch.guest_fpu && kvm_mpx_supported()) { 10468 void *mpx_state_buffer; 10469 10470 /* 10471 * To avoid have the INIT path from kvm_apic_has_events() that be 10472 * called with loaded FPU and does not let userspace fix the state. 10473 */ 10474 if (init_event) 10475 kvm_put_guest_fpu(vcpu); 10476 mpx_state_buffer = get_xsave_addr(&vcpu->arch.guest_fpu->state.xsave, 10477 XFEATURE_BNDREGS); 10478 if (mpx_state_buffer) 10479 memset(mpx_state_buffer, 0, sizeof(struct mpx_bndreg_state)); 10480 mpx_state_buffer = get_xsave_addr(&vcpu->arch.guest_fpu->state.xsave, 10481 XFEATURE_BNDCSR); 10482 if (mpx_state_buffer) 10483 memset(mpx_state_buffer, 0, sizeof(struct mpx_bndcsr)); 10484 if (init_event) 10485 kvm_load_guest_fpu(vcpu); 10486 } 10487 10488 if (!init_event) { 10489 kvm_pmu_reset(vcpu); 10490 vcpu->arch.smbase = 0x30000; 10491 10492 vcpu->arch.msr_misc_features_enables = 0; 10493 10494 vcpu->arch.xcr0 = XFEATURE_MASK_FP; 10495 } 10496 10497 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs)); 10498 vcpu->arch.regs_avail = ~0; 10499 vcpu->arch.regs_dirty = ~0; 10500 10501 vcpu->arch.ia32_xss = 0; 10502 10503 static_call(kvm_x86_vcpu_reset)(vcpu, init_event); 10504 } 10505 10506 void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector) 10507 { 10508 struct kvm_segment cs; 10509 10510 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS); 10511 cs.selector = vector << 8; 10512 cs.base = vector << 12; 10513 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS); 10514 kvm_rip_write(vcpu, 0); 10515 } 10516 EXPORT_SYMBOL_GPL(kvm_vcpu_deliver_sipi_vector); 10517 10518 int kvm_arch_hardware_enable(void) 10519 { 10520 struct kvm *kvm; 10521 struct kvm_vcpu *vcpu; 10522 int i; 10523 int ret; 10524 u64 local_tsc; 10525 u64 max_tsc = 0; 10526 bool stable, backwards_tsc = false; 10527 10528 kvm_user_return_msr_cpu_online(); 10529 ret = static_call(kvm_x86_hardware_enable)(); 10530 if (ret != 0) 10531 return ret; 10532 10533 local_tsc = rdtsc(); 10534 stable = !kvm_check_tsc_unstable(); 10535 list_for_each_entry(kvm, &vm_list, vm_list) { 10536 kvm_for_each_vcpu(i, vcpu, kvm) { 10537 if (!stable && vcpu->cpu == smp_processor_id()) 10538 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 10539 if (stable && vcpu->arch.last_host_tsc > local_tsc) { 10540 backwards_tsc = true; 10541 if (vcpu->arch.last_host_tsc > max_tsc) 10542 max_tsc = vcpu->arch.last_host_tsc; 10543 } 10544 } 10545 } 10546 10547 /* 10548 * Sometimes, even reliable TSCs go backwards. This happens on 10549 * platforms that reset TSC during suspend or hibernate actions, but 10550 * maintain synchronization. We must compensate. Fortunately, we can 10551 * detect that condition here, which happens early in CPU bringup, 10552 * before any KVM threads can be running. Unfortunately, we can't 10553 * bring the TSCs fully up to date with real time, as we aren't yet far 10554 * enough into CPU bringup that we know how much real time has actually 10555 * elapsed; our helper function, ktime_get_boottime_ns() will be using boot 10556 * variables that haven't been updated yet. 10557 * 10558 * So we simply find the maximum observed TSC above, then record the 10559 * adjustment to TSC in each VCPU. When the VCPU later gets loaded, 10560 * the adjustment will be applied. Note that we accumulate 10561 * adjustments, in case multiple suspend cycles happen before some VCPU 10562 * gets a chance to run again. In the event that no KVM threads get a 10563 * chance to run, we will miss the entire elapsed period, as we'll have 10564 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may 10565 * loose cycle time. This isn't too big a deal, since the loss will be 10566 * uniform across all VCPUs (not to mention the scenario is extremely 10567 * unlikely). It is possible that a second hibernate recovery happens 10568 * much faster than a first, causing the observed TSC here to be 10569 * smaller; this would require additional padding adjustment, which is 10570 * why we set last_host_tsc to the local tsc observed here. 10571 * 10572 * N.B. - this code below runs only on platforms with reliable TSC, 10573 * as that is the only way backwards_tsc is set above. Also note 10574 * that this runs for ALL vcpus, which is not a bug; all VCPUs should 10575 * have the same delta_cyc adjustment applied if backwards_tsc 10576 * is detected. Note further, this adjustment is only done once, 10577 * as we reset last_host_tsc on all VCPUs to stop this from being 10578 * called multiple times (one for each physical CPU bringup). 10579 * 10580 * Platforms with unreliable TSCs don't have to deal with this, they 10581 * will be compensated by the logic in vcpu_load, which sets the TSC to 10582 * catchup mode. This will catchup all VCPUs to real time, but cannot 10583 * guarantee that they stay in perfect synchronization. 10584 */ 10585 if (backwards_tsc) { 10586 u64 delta_cyc = max_tsc - local_tsc; 10587 list_for_each_entry(kvm, &vm_list, vm_list) { 10588 kvm->arch.backwards_tsc_observed = true; 10589 kvm_for_each_vcpu(i, vcpu, kvm) { 10590 vcpu->arch.tsc_offset_adjustment += delta_cyc; 10591 vcpu->arch.last_host_tsc = local_tsc; 10592 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu); 10593 } 10594 10595 /* 10596 * We have to disable TSC offset matching.. if you were 10597 * booting a VM while issuing an S4 host suspend.... 10598 * you may have some problem. Solving this issue is 10599 * left as an exercise to the reader. 10600 */ 10601 kvm->arch.last_tsc_nsec = 0; 10602 kvm->arch.last_tsc_write = 0; 10603 } 10604 10605 } 10606 return 0; 10607 } 10608 10609 void kvm_arch_hardware_disable(void) 10610 { 10611 static_call(kvm_x86_hardware_disable)(); 10612 drop_user_return_notifiers(); 10613 } 10614 10615 int kvm_arch_hardware_setup(void *opaque) 10616 { 10617 struct kvm_x86_init_ops *ops = opaque; 10618 int r; 10619 10620 rdmsrl_safe(MSR_EFER, &host_efer); 10621 10622 if (boot_cpu_has(X86_FEATURE_XSAVES)) 10623 rdmsrl(MSR_IA32_XSS, host_xss); 10624 10625 r = ops->hardware_setup(); 10626 if (r != 0) 10627 return r; 10628 10629 memcpy(&kvm_x86_ops, ops->runtime_ops, sizeof(kvm_x86_ops)); 10630 kvm_ops_static_call_update(); 10631 10632 if (!kvm_cpu_cap_has(X86_FEATURE_XSAVES)) 10633 supported_xss = 0; 10634 10635 #define __kvm_cpu_cap_has(UNUSED_, f) kvm_cpu_cap_has(f) 10636 cr4_reserved_bits = __cr4_reserved_bits(__kvm_cpu_cap_has, UNUSED_); 10637 #undef __kvm_cpu_cap_has 10638 10639 if (kvm_has_tsc_control) { 10640 /* 10641 * Make sure the user can only configure tsc_khz values that 10642 * fit into a signed integer. 10643 * A min value is not calculated because it will always 10644 * be 1 on all machines. 10645 */ 10646 u64 max = min(0x7fffffffULL, 10647 __scale_tsc(kvm_max_tsc_scaling_ratio, tsc_khz)); 10648 kvm_max_guest_tsc_khz = max; 10649 10650 kvm_default_tsc_scaling_ratio = 1ULL << kvm_tsc_scaling_ratio_frac_bits; 10651 } 10652 10653 kvm_init_msr_list(); 10654 return 0; 10655 } 10656 10657 void kvm_arch_hardware_unsetup(void) 10658 { 10659 static_call(kvm_x86_hardware_unsetup)(); 10660 } 10661 10662 int kvm_arch_check_processor_compat(void *opaque) 10663 { 10664 struct cpuinfo_x86 *c = &cpu_data(smp_processor_id()); 10665 struct kvm_x86_init_ops *ops = opaque; 10666 10667 WARN_ON(!irqs_disabled()); 10668 10669 if (__cr4_reserved_bits(cpu_has, c) != 10670 __cr4_reserved_bits(cpu_has, &boot_cpu_data)) 10671 return -EIO; 10672 10673 return ops->check_processor_compatibility(); 10674 } 10675 10676 bool kvm_vcpu_is_reset_bsp(struct kvm_vcpu *vcpu) 10677 { 10678 return vcpu->kvm->arch.bsp_vcpu_id == vcpu->vcpu_id; 10679 } 10680 EXPORT_SYMBOL_GPL(kvm_vcpu_is_reset_bsp); 10681 10682 bool kvm_vcpu_is_bsp(struct kvm_vcpu *vcpu) 10683 { 10684 return (vcpu->arch.apic_base & MSR_IA32_APICBASE_BSP) != 0; 10685 } 10686 10687 __read_mostly DEFINE_STATIC_KEY_FALSE(kvm_has_noapic_vcpu); 10688 EXPORT_SYMBOL_GPL(kvm_has_noapic_vcpu); 10689 10690 void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu) 10691 { 10692 struct kvm_pmu *pmu = vcpu_to_pmu(vcpu); 10693 10694 vcpu->arch.l1tf_flush_l1d = true; 10695 if (pmu->version && unlikely(pmu->event_count)) { 10696 pmu->need_cleanup = true; 10697 kvm_make_request(KVM_REQ_PMU, vcpu); 10698 } 10699 static_call(kvm_x86_sched_in)(vcpu, cpu); 10700 } 10701 10702 void kvm_arch_free_vm(struct kvm *kvm) 10703 { 10704 kfree(to_kvm_hv(kvm)->hv_pa_pg); 10705 vfree(kvm); 10706 } 10707 10708 10709 int kvm_arch_init_vm(struct kvm *kvm, unsigned long type) 10710 { 10711 if (type) 10712 return -EINVAL; 10713 10714 INIT_HLIST_HEAD(&kvm->arch.mask_notifier_list); 10715 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages); 10716 INIT_LIST_HEAD(&kvm->arch.zapped_obsolete_pages); 10717 INIT_LIST_HEAD(&kvm->arch.lpage_disallowed_mmu_pages); 10718 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head); 10719 atomic_set(&kvm->arch.noncoherent_dma_count, 0); 10720 10721 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */ 10722 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap); 10723 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */ 10724 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID, 10725 &kvm->arch.irq_sources_bitmap); 10726 10727 raw_spin_lock_init(&kvm->arch.tsc_write_lock); 10728 mutex_init(&kvm->arch.apic_map_lock); 10729 spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock); 10730 10731 kvm->arch.kvmclock_offset = -get_kvmclock_base_ns(); 10732 pvclock_update_vm_gtod_copy(kvm); 10733 10734 kvm->arch.guest_can_read_msr_platform_info = true; 10735 10736 INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn); 10737 INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn); 10738 10739 kvm_hv_init_vm(kvm); 10740 kvm_page_track_init(kvm); 10741 kvm_mmu_init_vm(kvm); 10742 10743 return static_call(kvm_x86_vm_init)(kvm); 10744 } 10745 10746 int kvm_arch_post_init_vm(struct kvm *kvm) 10747 { 10748 return kvm_mmu_post_init_vm(kvm); 10749 } 10750 10751 static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu) 10752 { 10753 vcpu_load(vcpu); 10754 kvm_mmu_unload(vcpu); 10755 vcpu_put(vcpu); 10756 } 10757 10758 static void kvm_free_vcpus(struct kvm *kvm) 10759 { 10760 unsigned int i; 10761 struct kvm_vcpu *vcpu; 10762 10763 /* 10764 * Unpin any mmu pages first. 10765 */ 10766 kvm_for_each_vcpu(i, vcpu, kvm) { 10767 kvm_clear_async_pf_completion_queue(vcpu); 10768 kvm_unload_vcpu_mmu(vcpu); 10769 } 10770 kvm_for_each_vcpu(i, vcpu, kvm) 10771 kvm_vcpu_destroy(vcpu); 10772 10773 mutex_lock(&kvm->lock); 10774 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++) 10775 kvm->vcpus[i] = NULL; 10776 10777 atomic_set(&kvm->online_vcpus, 0); 10778 mutex_unlock(&kvm->lock); 10779 } 10780 10781 void kvm_arch_sync_events(struct kvm *kvm) 10782 { 10783 cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work); 10784 cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work); 10785 kvm_free_pit(kvm); 10786 } 10787 10788 #define ERR_PTR_USR(e) ((void __user *)ERR_PTR(e)) 10789 10790 /** 10791 * __x86_set_memory_region: Setup KVM internal memory slot 10792 * 10793 * @kvm: the kvm pointer to the VM. 10794 * @id: the slot ID to setup. 10795 * @gpa: the GPA to install the slot (unused when @size == 0). 10796 * @size: the size of the slot. Set to zero to uninstall a slot. 10797 * 10798 * This function helps to setup a KVM internal memory slot. Specify 10799 * @size > 0 to install a new slot, while @size == 0 to uninstall a 10800 * slot. The return code can be one of the following: 10801 * 10802 * HVA: on success (uninstall will return a bogus HVA) 10803 * -errno: on error 10804 * 10805 * The caller should always use IS_ERR() to check the return value 10806 * before use. Note, the KVM internal memory slots are guaranteed to 10807 * remain valid and unchanged until the VM is destroyed, i.e., the 10808 * GPA->HVA translation will not change. However, the HVA is a user 10809 * address, i.e. its accessibility is not guaranteed, and must be 10810 * accessed via __copy_{to,from}_user(). 10811 */ 10812 void __user * __x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, 10813 u32 size) 10814 { 10815 int i, r; 10816 unsigned long hva, old_npages; 10817 struct kvm_memslots *slots = kvm_memslots(kvm); 10818 struct kvm_memory_slot *slot; 10819 10820 /* Called with kvm->slots_lock held. */ 10821 if (WARN_ON(id >= KVM_MEM_SLOTS_NUM)) 10822 return ERR_PTR_USR(-EINVAL); 10823 10824 slot = id_to_memslot(slots, id); 10825 if (size) { 10826 if (slot && slot->npages) 10827 return ERR_PTR_USR(-EEXIST); 10828 10829 /* 10830 * MAP_SHARED to prevent internal slot pages from being moved 10831 * by fork()/COW. 10832 */ 10833 hva = vm_mmap(NULL, 0, size, PROT_READ | PROT_WRITE, 10834 MAP_SHARED | MAP_ANONYMOUS, 0); 10835 if (IS_ERR((void *)hva)) 10836 return (void __user *)hva; 10837 } else { 10838 if (!slot || !slot->npages) 10839 return NULL; 10840 10841 old_npages = slot->npages; 10842 hva = slot->userspace_addr; 10843 } 10844 10845 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) { 10846 struct kvm_userspace_memory_region m; 10847 10848 m.slot = id | (i << 16); 10849 m.flags = 0; 10850 m.guest_phys_addr = gpa; 10851 m.userspace_addr = hva; 10852 m.memory_size = size; 10853 r = __kvm_set_memory_region(kvm, &m); 10854 if (r < 0) 10855 return ERR_PTR_USR(r); 10856 } 10857 10858 if (!size) 10859 vm_munmap(hva, old_npages * PAGE_SIZE); 10860 10861 return (void __user *)hva; 10862 } 10863 EXPORT_SYMBOL_GPL(__x86_set_memory_region); 10864 10865 void kvm_arch_pre_destroy_vm(struct kvm *kvm) 10866 { 10867 kvm_mmu_pre_destroy_vm(kvm); 10868 } 10869 10870 void kvm_arch_destroy_vm(struct kvm *kvm) 10871 { 10872 if (current->mm == kvm->mm) { 10873 /* 10874 * Free memory regions allocated on behalf of userspace, 10875 * unless the the memory map has changed due to process exit 10876 * or fd copying. 10877 */ 10878 mutex_lock(&kvm->slots_lock); 10879 __x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT, 10880 0, 0); 10881 __x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT, 10882 0, 0); 10883 __x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, 0, 0); 10884 mutex_unlock(&kvm->slots_lock); 10885 } 10886 static_call_cond(kvm_x86_vm_destroy)(kvm); 10887 kvm_free_msr_filter(srcu_dereference_check(kvm->arch.msr_filter, &kvm->srcu, 1)); 10888 kvm_pic_destroy(kvm); 10889 kvm_ioapic_destroy(kvm); 10890 kvm_free_vcpus(kvm); 10891 kvfree(rcu_dereference_check(kvm->arch.apic_map, 1)); 10892 kfree(srcu_dereference_check(kvm->arch.pmu_event_filter, &kvm->srcu, 1)); 10893 kvm_mmu_uninit_vm(kvm); 10894 kvm_page_track_cleanup(kvm); 10895 kvm_xen_destroy_vm(kvm); 10896 kvm_hv_destroy_vm(kvm); 10897 } 10898 10899 void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *slot) 10900 { 10901 int i; 10902 10903 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) { 10904 kvfree(slot->arch.rmap[i]); 10905 slot->arch.rmap[i] = NULL; 10906 10907 if (i == 0) 10908 continue; 10909 10910 kvfree(slot->arch.lpage_info[i - 1]); 10911 slot->arch.lpage_info[i - 1] = NULL; 10912 } 10913 10914 kvm_page_track_free_memslot(slot); 10915 } 10916 10917 static int kvm_alloc_memslot_metadata(struct kvm_memory_slot *slot, 10918 unsigned long npages) 10919 { 10920 int i; 10921 10922 /* 10923 * Clear out the previous array pointers for the KVM_MR_MOVE case. The 10924 * old arrays will be freed by __kvm_set_memory_region() if installing 10925 * the new memslot is successful. 10926 */ 10927 memset(&slot->arch, 0, sizeof(slot->arch)); 10928 10929 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) { 10930 struct kvm_lpage_info *linfo; 10931 unsigned long ugfn; 10932 int lpages; 10933 int level = i + 1; 10934 10935 lpages = gfn_to_index(slot->base_gfn + npages - 1, 10936 slot->base_gfn, level) + 1; 10937 10938 slot->arch.rmap[i] = 10939 kvcalloc(lpages, sizeof(*slot->arch.rmap[i]), 10940 GFP_KERNEL_ACCOUNT); 10941 if (!slot->arch.rmap[i]) 10942 goto out_free; 10943 if (i == 0) 10944 continue; 10945 10946 linfo = kvcalloc(lpages, sizeof(*linfo), GFP_KERNEL_ACCOUNT); 10947 if (!linfo) 10948 goto out_free; 10949 10950 slot->arch.lpage_info[i - 1] = linfo; 10951 10952 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1)) 10953 linfo[0].disallow_lpage = 1; 10954 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1)) 10955 linfo[lpages - 1].disallow_lpage = 1; 10956 ugfn = slot->userspace_addr >> PAGE_SHIFT; 10957 /* 10958 * If the gfn and userspace address are not aligned wrt each 10959 * other, disable large page support for this slot. 10960 */ 10961 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1)) { 10962 unsigned long j; 10963 10964 for (j = 0; j < lpages; ++j) 10965 linfo[j].disallow_lpage = 1; 10966 } 10967 } 10968 10969 if (kvm_page_track_create_memslot(slot, npages)) 10970 goto out_free; 10971 10972 return 0; 10973 10974 out_free: 10975 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) { 10976 kvfree(slot->arch.rmap[i]); 10977 slot->arch.rmap[i] = NULL; 10978 if (i == 0) 10979 continue; 10980 10981 kvfree(slot->arch.lpage_info[i - 1]); 10982 slot->arch.lpage_info[i - 1] = NULL; 10983 } 10984 return -ENOMEM; 10985 } 10986 10987 void kvm_arch_memslots_updated(struct kvm *kvm, u64 gen) 10988 { 10989 struct kvm_vcpu *vcpu; 10990 int i; 10991 10992 /* 10993 * memslots->generation has been incremented. 10994 * mmio generation may have reached its maximum value. 10995 */ 10996 kvm_mmu_invalidate_mmio_sptes(kvm, gen); 10997 10998 /* Force re-initialization of steal_time cache */ 10999 kvm_for_each_vcpu(i, vcpu, kvm) 11000 kvm_vcpu_kick(vcpu); 11001 } 11002 11003 int kvm_arch_prepare_memory_region(struct kvm *kvm, 11004 struct kvm_memory_slot *memslot, 11005 const struct kvm_userspace_memory_region *mem, 11006 enum kvm_mr_change change) 11007 { 11008 if (change == KVM_MR_CREATE || change == KVM_MR_MOVE) 11009 return kvm_alloc_memslot_metadata(memslot, 11010 mem->memory_size >> PAGE_SHIFT); 11011 return 0; 11012 } 11013 11014 11015 static void kvm_mmu_update_cpu_dirty_logging(struct kvm *kvm, bool enable) 11016 { 11017 struct kvm_arch *ka = &kvm->arch; 11018 11019 if (!kvm_x86_ops.cpu_dirty_log_size) 11020 return; 11021 11022 if ((enable && ++ka->cpu_dirty_logging_count == 1) || 11023 (!enable && --ka->cpu_dirty_logging_count == 0)) 11024 kvm_make_all_cpus_request(kvm, KVM_REQ_UPDATE_CPU_DIRTY_LOGGING); 11025 11026 WARN_ON_ONCE(ka->cpu_dirty_logging_count < 0); 11027 } 11028 11029 static void kvm_mmu_slot_apply_flags(struct kvm *kvm, 11030 struct kvm_memory_slot *old, 11031 struct kvm_memory_slot *new, 11032 enum kvm_mr_change change) 11033 { 11034 bool log_dirty_pages = new->flags & KVM_MEM_LOG_DIRTY_PAGES; 11035 11036 /* 11037 * Update CPU dirty logging if dirty logging is being toggled. This 11038 * applies to all operations. 11039 */ 11040 if ((old->flags ^ new->flags) & KVM_MEM_LOG_DIRTY_PAGES) 11041 kvm_mmu_update_cpu_dirty_logging(kvm, log_dirty_pages); 11042 11043 /* 11044 * Nothing more to do for RO slots (which can't be dirtied and can't be 11045 * made writable) or CREATE/MOVE/DELETE of a slot. 11046 * 11047 * For a memslot with dirty logging disabled: 11048 * CREATE: No dirty mappings will already exist. 11049 * MOVE/DELETE: The old mappings will already have been cleaned up by 11050 * kvm_arch_flush_shadow_memslot() 11051 * 11052 * For a memslot with dirty logging enabled: 11053 * CREATE: No shadow pages exist, thus nothing to write-protect 11054 * and no dirty bits to clear. 11055 * MOVE/DELETE: The old mappings will already have been cleaned up by 11056 * kvm_arch_flush_shadow_memslot(). 11057 */ 11058 if ((change != KVM_MR_FLAGS_ONLY) || (new->flags & KVM_MEM_READONLY)) 11059 return; 11060 11061 /* 11062 * READONLY and non-flags changes were filtered out above, and the only 11063 * other flag is LOG_DIRTY_PAGES, i.e. something is wrong if dirty 11064 * logging isn't being toggled on or off. 11065 */ 11066 if (WARN_ON_ONCE(!((old->flags ^ new->flags) & KVM_MEM_LOG_DIRTY_PAGES))) 11067 return; 11068 11069 if (!log_dirty_pages) { 11070 /* 11071 * Dirty logging tracks sptes in 4k granularity, meaning that 11072 * large sptes have to be split. If live migration succeeds, 11073 * the guest in the source machine will be destroyed and large 11074 * sptes will be created in the destination. However, if the 11075 * guest continues to run in the source machine (for example if 11076 * live migration fails), small sptes will remain around and 11077 * cause bad performance. 11078 * 11079 * Scan sptes if dirty logging has been stopped, dropping those 11080 * which can be collapsed into a single large-page spte. Later 11081 * page faults will create the large-page sptes. 11082 */ 11083 kvm_mmu_zap_collapsible_sptes(kvm, new); 11084 } else { 11085 /* By default, write-protect everything to log writes. */ 11086 int level = PG_LEVEL_4K; 11087 11088 if (kvm_x86_ops.cpu_dirty_log_size) { 11089 /* 11090 * Clear all dirty bits, unless pages are treated as 11091 * dirty from the get-go. 11092 */ 11093 if (!kvm_dirty_log_manual_protect_and_init_set(kvm)) 11094 kvm_mmu_slot_leaf_clear_dirty(kvm, new); 11095 11096 /* 11097 * Write-protect large pages on write so that dirty 11098 * logging happens at 4k granularity. No need to 11099 * write-protect small SPTEs since write accesses are 11100 * logged by the CPU via dirty bits. 11101 */ 11102 level = PG_LEVEL_2M; 11103 } else if (kvm_dirty_log_manual_protect_and_init_set(kvm)) { 11104 /* 11105 * If we're with initial-all-set, we don't need 11106 * to write protect any small page because 11107 * they're reported as dirty already. However 11108 * we still need to write-protect huge pages 11109 * so that the page split can happen lazily on 11110 * the first write to the huge page. 11111 */ 11112 level = PG_LEVEL_2M; 11113 } 11114 kvm_mmu_slot_remove_write_access(kvm, new, level); 11115 } 11116 } 11117 11118 void kvm_arch_commit_memory_region(struct kvm *kvm, 11119 const struct kvm_userspace_memory_region *mem, 11120 struct kvm_memory_slot *old, 11121 const struct kvm_memory_slot *new, 11122 enum kvm_mr_change change) 11123 { 11124 if (!kvm->arch.n_requested_mmu_pages) 11125 kvm_mmu_change_mmu_pages(kvm, 11126 kvm_mmu_calculate_default_mmu_pages(kvm)); 11127 11128 /* 11129 * FIXME: const-ify all uses of struct kvm_memory_slot. 11130 */ 11131 kvm_mmu_slot_apply_flags(kvm, old, (struct kvm_memory_slot *) new, change); 11132 11133 /* Free the arrays associated with the old memslot. */ 11134 if (change == KVM_MR_MOVE) 11135 kvm_arch_free_memslot(kvm, old); 11136 } 11137 11138 void kvm_arch_flush_shadow_all(struct kvm *kvm) 11139 { 11140 kvm_mmu_zap_all(kvm); 11141 } 11142 11143 void kvm_arch_flush_shadow_memslot(struct kvm *kvm, 11144 struct kvm_memory_slot *slot) 11145 { 11146 kvm_page_track_flush_slot(kvm, slot); 11147 } 11148 11149 static inline bool kvm_guest_apic_has_interrupt(struct kvm_vcpu *vcpu) 11150 { 11151 return (is_guest_mode(vcpu) && 11152 kvm_x86_ops.guest_apic_has_interrupt && 11153 static_call(kvm_x86_guest_apic_has_interrupt)(vcpu)); 11154 } 11155 11156 static inline bool kvm_vcpu_has_events(struct kvm_vcpu *vcpu) 11157 { 11158 if (!list_empty_careful(&vcpu->async_pf.done)) 11159 return true; 11160 11161 if (kvm_apic_has_events(vcpu)) 11162 return true; 11163 11164 if (vcpu->arch.pv.pv_unhalted) 11165 return true; 11166 11167 if (vcpu->arch.exception.pending) 11168 return true; 11169 11170 if (kvm_test_request(KVM_REQ_NMI, vcpu) || 11171 (vcpu->arch.nmi_pending && 11172 static_call(kvm_x86_nmi_allowed)(vcpu, false))) 11173 return true; 11174 11175 if (kvm_test_request(KVM_REQ_SMI, vcpu) || 11176 (vcpu->arch.smi_pending && 11177 static_call(kvm_x86_smi_allowed)(vcpu, false))) 11178 return true; 11179 11180 if (kvm_arch_interrupt_allowed(vcpu) && 11181 (kvm_cpu_has_interrupt(vcpu) || 11182 kvm_guest_apic_has_interrupt(vcpu))) 11183 return true; 11184 11185 if (kvm_hv_has_stimer_pending(vcpu)) 11186 return true; 11187 11188 if (is_guest_mode(vcpu) && 11189 kvm_x86_ops.nested_ops->hv_timer_pending && 11190 kvm_x86_ops.nested_ops->hv_timer_pending(vcpu)) 11191 return true; 11192 11193 return false; 11194 } 11195 11196 int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu) 11197 { 11198 return kvm_vcpu_running(vcpu) || kvm_vcpu_has_events(vcpu); 11199 } 11200 11201 bool kvm_arch_dy_has_pending_interrupt(struct kvm_vcpu *vcpu) 11202 { 11203 if (vcpu->arch.apicv_active && static_call(kvm_x86_dy_apicv_has_pending_interrupt)(vcpu)) 11204 return true; 11205 11206 return false; 11207 } 11208 11209 bool kvm_arch_dy_runnable(struct kvm_vcpu *vcpu) 11210 { 11211 if (READ_ONCE(vcpu->arch.pv.pv_unhalted)) 11212 return true; 11213 11214 if (kvm_test_request(KVM_REQ_NMI, vcpu) || 11215 kvm_test_request(KVM_REQ_SMI, vcpu) || 11216 kvm_test_request(KVM_REQ_EVENT, vcpu)) 11217 return true; 11218 11219 return kvm_arch_dy_has_pending_interrupt(vcpu); 11220 } 11221 11222 bool kvm_arch_vcpu_in_kernel(struct kvm_vcpu *vcpu) 11223 { 11224 if (vcpu->arch.guest_state_protected) 11225 return true; 11226 11227 return vcpu->arch.preempted_in_kernel; 11228 } 11229 11230 int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu) 11231 { 11232 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE; 11233 } 11234 11235 int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu) 11236 { 11237 return static_call(kvm_x86_interrupt_allowed)(vcpu, false); 11238 } 11239 11240 unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu) 11241 { 11242 /* Can't read the RIP when guest state is protected, just return 0 */ 11243 if (vcpu->arch.guest_state_protected) 11244 return 0; 11245 11246 if (is_64_bit_mode(vcpu)) 11247 return kvm_rip_read(vcpu); 11248 return (u32)(get_segment_base(vcpu, VCPU_SREG_CS) + 11249 kvm_rip_read(vcpu)); 11250 } 11251 EXPORT_SYMBOL_GPL(kvm_get_linear_rip); 11252 11253 bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip) 11254 { 11255 return kvm_get_linear_rip(vcpu) == linear_rip; 11256 } 11257 EXPORT_SYMBOL_GPL(kvm_is_linear_rip); 11258 11259 unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu) 11260 { 11261 unsigned long rflags; 11262 11263 rflags = static_call(kvm_x86_get_rflags)(vcpu); 11264 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) 11265 rflags &= ~X86_EFLAGS_TF; 11266 return rflags; 11267 } 11268 EXPORT_SYMBOL_GPL(kvm_get_rflags); 11269 11270 static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags) 11271 { 11272 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP && 11273 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip)) 11274 rflags |= X86_EFLAGS_TF; 11275 static_call(kvm_x86_set_rflags)(vcpu, rflags); 11276 } 11277 11278 void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags) 11279 { 11280 __kvm_set_rflags(vcpu, rflags); 11281 kvm_make_request(KVM_REQ_EVENT, vcpu); 11282 } 11283 EXPORT_SYMBOL_GPL(kvm_set_rflags); 11284 11285 void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work) 11286 { 11287 int r; 11288 11289 if ((vcpu->arch.mmu->direct_map != work->arch.direct_map) || 11290 work->wakeup_all) 11291 return; 11292 11293 r = kvm_mmu_reload(vcpu); 11294 if (unlikely(r)) 11295 return; 11296 11297 if (!vcpu->arch.mmu->direct_map && 11298 work->arch.cr3 != vcpu->arch.mmu->get_guest_pgd(vcpu)) 11299 return; 11300 11301 kvm_mmu_do_page_fault(vcpu, work->cr2_or_gpa, 0, true); 11302 } 11303 11304 static inline u32 kvm_async_pf_hash_fn(gfn_t gfn) 11305 { 11306 BUILD_BUG_ON(!is_power_of_2(ASYNC_PF_PER_VCPU)); 11307 11308 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU)); 11309 } 11310 11311 static inline u32 kvm_async_pf_next_probe(u32 key) 11312 { 11313 return (key + 1) & (ASYNC_PF_PER_VCPU - 1); 11314 } 11315 11316 static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn) 11317 { 11318 u32 key = kvm_async_pf_hash_fn(gfn); 11319 11320 while (vcpu->arch.apf.gfns[key] != ~0) 11321 key = kvm_async_pf_next_probe(key); 11322 11323 vcpu->arch.apf.gfns[key] = gfn; 11324 } 11325 11326 static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn) 11327 { 11328 int i; 11329 u32 key = kvm_async_pf_hash_fn(gfn); 11330 11331 for (i = 0; i < ASYNC_PF_PER_VCPU && 11332 (vcpu->arch.apf.gfns[key] != gfn && 11333 vcpu->arch.apf.gfns[key] != ~0); i++) 11334 key = kvm_async_pf_next_probe(key); 11335 11336 return key; 11337 } 11338 11339 bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn) 11340 { 11341 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn; 11342 } 11343 11344 static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn) 11345 { 11346 u32 i, j, k; 11347 11348 i = j = kvm_async_pf_gfn_slot(vcpu, gfn); 11349 11350 if (WARN_ON_ONCE(vcpu->arch.apf.gfns[i] != gfn)) 11351 return; 11352 11353 while (true) { 11354 vcpu->arch.apf.gfns[i] = ~0; 11355 do { 11356 j = kvm_async_pf_next_probe(j); 11357 if (vcpu->arch.apf.gfns[j] == ~0) 11358 return; 11359 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]); 11360 /* 11361 * k lies cyclically in ]i,j] 11362 * | i.k.j | 11363 * |....j i.k.| or |.k..j i...| 11364 */ 11365 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j)); 11366 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j]; 11367 i = j; 11368 } 11369 } 11370 11371 static inline int apf_put_user_notpresent(struct kvm_vcpu *vcpu) 11372 { 11373 u32 reason = KVM_PV_REASON_PAGE_NOT_PRESENT; 11374 11375 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &reason, 11376 sizeof(reason)); 11377 } 11378 11379 static inline int apf_put_user_ready(struct kvm_vcpu *vcpu, u32 token) 11380 { 11381 unsigned int offset = offsetof(struct kvm_vcpu_pv_apf_data, token); 11382 11383 return kvm_write_guest_offset_cached(vcpu->kvm, &vcpu->arch.apf.data, 11384 &token, offset, sizeof(token)); 11385 } 11386 11387 static inline bool apf_pageready_slot_free(struct kvm_vcpu *vcpu) 11388 { 11389 unsigned int offset = offsetof(struct kvm_vcpu_pv_apf_data, token); 11390 u32 val; 11391 11392 if (kvm_read_guest_offset_cached(vcpu->kvm, &vcpu->arch.apf.data, 11393 &val, offset, sizeof(val))) 11394 return false; 11395 11396 return !val; 11397 } 11398 11399 static bool kvm_can_deliver_async_pf(struct kvm_vcpu *vcpu) 11400 { 11401 if (!vcpu->arch.apf.delivery_as_pf_vmexit && is_guest_mode(vcpu)) 11402 return false; 11403 11404 if (!kvm_pv_async_pf_enabled(vcpu) || 11405 (vcpu->arch.apf.send_user_only && static_call(kvm_x86_get_cpl)(vcpu) == 0)) 11406 return false; 11407 11408 return true; 11409 } 11410 11411 bool kvm_can_do_async_pf(struct kvm_vcpu *vcpu) 11412 { 11413 if (unlikely(!lapic_in_kernel(vcpu) || 11414 kvm_event_needs_reinjection(vcpu) || 11415 vcpu->arch.exception.pending)) 11416 return false; 11417 11418 if (kvm_hlt_in_guest(vcpu->kvm) && !kvm_can_deliver_async_pf(vcpu)) 11419 return false; 11420 11421 /* 11422 * If interrupts are off we cannot even use an artificial 11423 * halt state. 11424 */ 11425 return kvm_arch_interrupt_allowed(vcpu); 11426 } 11427 11428 bool kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu, 11429 struct kvm_async_pf *work) 11430 { 11431 struct x86_exception fault; 11432 11433 trace_kvm_async_pf_not_present(work->arch.token, work->cr2_or_gpa); 11434 kvm_add_async_pf_gfn(vcpu, work->arch.gfn); 11435 11436 if (kvm_can_deliver_async_pf(vcpu) && 11437 !apf_put_user_notpresent(vcpu)) { 11438 fault.vector = PF_VECTOR; 11439 fault.error_code_valid = true; 11440 fault.error_code = 0; 11441 fault.nested_page_fault = false; 11442 fault.address = work->arch.token; 11443 fault.async_page_fault = true; 11444 kvm_inject_page_fault(vcpu, &fault); 11445 return true; 11446 } else { 11447 /* 11448 * It is not possible to deliver a paravirtualized asynchronous 11449 * page fault, but putting the guest in an artificial halt state 11450 * can be beneficial nevertheless: if an interrupt arrives, we 11451 * can deliver it timely and perhaps the guest will schedule 11452 * another process. When the instruction that triggered a page 11453 * fault is retried, hopefully the page will be ready in the host. 11454 */ 11455 kvm_make_request(KVM_REQ_APF_HALT, vcpu); 11456 return false; 11457 } 11458 } 11459 11460 void kvm_arch_async_page_present(struct kvm_vcpu *vcpu, 11461 struct kvm_async_pf *work) 11462 { 11463 struct kvm_lapic_irq irq = { 11464 .delivery_mode = APIC_DM_FIXED, 11465 .vector = vcpu->arch.apf.vec 11466 }; 11467 11468 if (work->wakeup_all) 11469 work->arch.token = ~0; /* broadcast wakeup */ 11470 else 11471 kvm_del_async_pf_gfn(vcpu, work->arch.gfn); 11472 trace_kvm_async_pf_ready(work->arch.token, work->cr2_or_gpa); 11473 11474 if ((work->wakeup_all || work->notpresent_injected) && 11475 kvm_pv_async_pf_enabled(vcpu) && 11476 !apf_put_user_ready(vcpu, work->arch.token)) { 11477 vcpu->arch.apf.pageready_pending = true; 11478 kvm_apic_set_irq(vcpu, &irq, NULL); 11479 } 11480 11481 vcpu->arch.apf.halted = false; 11482 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; 11483 } 11484 11485 void kvm_arch_async_page_present_queued(struct kvm_vcpu *vcpu) 11486 { 11487 kvm_make_request(KVM_REQ_APF_READY, vcpu); 11488 if (!vcpu->arch.apf.pageready_pending) 11489 kvm_vcpu_kick(vcpu); 11490 } 11491 11492 bool kvm_arch_can_dequeue_async_page_present(struct kvm_vcpu *vcpu) 11493 { 11494 if (!kvm_pv_async_pf_enabled(vcpu)) 11495 return true; 11496 else 11497 return kvm_lapic_enabled(vcpu) && apf_pageready_slot_free(vcpu); 11498 } 11499 11500 void kvm_arch_start_assignment(struct kvm *kvm) 11501 { 11502 atomic_inc(&kvm->arch.assigned_device_count); 11503 } 11504 EXPORT_SYMBOL_GPL(kvm_arch_start_assignment); 11505 11506 void kvm_arch_end_assignment(struct kvm *kvm) 11507 { 11508 atomic_dec(&kvm->arch.assigned_device_count); 11509 } 11510 EXPORT_SYMBOL_GPL(kvm_arch_end_assignment); 11511 11512 bool kvm_arch_has_assigned_device(struct kvm *kvm) 11513 { 11514 return atomic_read(&kvm->arch.assigned_device_count); 11515 } 11516 EXPORT_SYMBOL_GPL(kvm_arch_has_assigned_device); 11517 11518 void kvm_arch_register_noncoherent_dma(struct kvm *kvm) 11519 { 11520 atomic_inc(&kvm->arch.noncoherent_dma_count); 11521 } 11522 EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma); 11523 11524 void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm) 11525 { 11526 atomic_dec(&kvm->arch.noncoherent_dma_count); 11527 } 11528 EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma); 11529 11530 bool kvm_arch_has_noncoherent_dma(struct kvm *kvm) 11531 { 11532 return atomic_read(&kvm->arch.noncoherent_dma_count); 11533 } 11534 EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma); 11535 11536 bool kvm_arch_has_irq_bypass(void) 11537 { 11538 return true; 11539 } 11540 11541 int kvm_arch_irq_bypass_add_producer(struct irq_bypass_consumer *cons, 11542 struct irq_bypass_producer *prod) 11543 { 11544 struct kvm_kernel_irqfd *irqfd = 11545 container_of(cons, struct kvm_kernel_irqfd, consumer); 11546 int ret; 11547 11548 irqfd->producer = prod; 11549 kvm_arch_start_assignment(irqfd->kvm); 11550 ret = static_call(kvm_x86_update_pi_irte)(irqfd->kvm, 11551 prod->irq, irqfd->gsi, 1); 11552 11553 if (ret) 11554 kvm_arch_end_assignment(irqfd->kvm); 11555 11556 return ret; 11557 } 11558 11559 void kvm_arch_irq_bypass_del_producer(struct irq_bypass_consumer *cons, 11560 struct irq_bypass_producer *prod) 11561 { 11562 int ret; 11563 struct kvm_kernel_irqfd *irqfd = 11564 container_of(cons, struct kvm_kernel_irqfd, consumer); 11565 11566 WARN_ON(irqfd->producer != prod); 11567 irqfd->producer = NULL; 11568 11569 /* 11570 * When producer of consumer is unregistered, we change back to 11571 * remapped mode, so we can re-use the current implementation 11572 * when the irq is masked/disabled or the consumer side (KVM 11573 * int this case doesn't want to receive the interrupts. 11574 */ 11575 ret = static_call(kvm_x86_update_pi_irte)(irqfd->kvm, prod->irq, irqfd->gsi, 0); 11576 if (ret) 11577 printk(KERN_INFO "irq bypass consumer (token %p) unregistration" 11578 " fails: %d\n", irqfd->consumer.token, ret); 11579 11580 kvm_arch_end_assignment(irqfd->kvm); 11581 } 11582 11583 int kvm_arch_update_irqfd_routing(struct kvm *kvm, unsigned int host_irq, 11584 uint32_t guest_irq, bool set) 11585 { 11586 return static_call(kvm_x86_update_pi_irte)(kvm, host_irq, guest_irq, set); 11587 } 11588 11589 bool kvm_vector_hashing_enabled(void) 11590 { 11591 return vector_hashing; 11592 } 11593 11594 bool kvm_arch_no_poll(struct kvm_vcpu *vcpu) 11595 { 11596 return (vcpu->arch.msr_kvm_poll_control & 1) == 0; 11597 } 11598 EXPORT_SYMBOL_GPL(kvm_arch_no_poll); 11599 11600 11601 int kvm_spec_ctrl_test_value(u64 value) 11602 { 11603 /* 11604 * test that setting IA32_SPEC_CTRL to given value 11605 * is allowed by the host processor 11606 */ 11607 11608 u64 saved_value; 11609 unsigned long flags; 11610 int ret = 0; 11611 11612 local_irq_save(flags); 11613 11614 if (rdmsrl_safe(MSR_IA32_SPEC_CTRL, &saved_value)) 11615 ret = 1; 11616 else if (wrmsrl_safe(MSR_IA32_SPEC_CTRL, value)) 11617 ret = 1; 11618 else 11619 wrmsrl(MSR_IA32_SPEC_CTRL, saved_value); 11620 11621 local_irq_restore(flags); 11622 11623 return ret; 11624 } 11625 EXPORT_SYMBOL_GPL(kvm_spec_ctrl_test_value); 11626 11627 void kvm_fixup_and_inject_pf_error(struct kvm_vcpu *vcpu, gva_t gva, u16 error_code) 11628 { 11629 struct x86_exception fault; 11630 u32 access = error_code & 11631 (PFERR_WRITE_MASK | PFERR_FETCH_MASK | PFERR_USER_MASK); 11632 11633 if (!(error_code & PFERR_PRESENT_MASK) || 11634 vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, &fault) != UNMAPPED_GVA) { 11635 /* 11636 * If vcpu->arch.walk_mmu->gva_to_gpa succeeded, the page 11637 * tables probably do not match the TLB. Just proceed 11638 * with the error code that the processor gave. 11639 */ 11640 fault.vector = PF_VECTOR; 11641 fault.error_code_valid = true; 11642 fault.error_code = error_code; 11643 fault.nested_page_fault = false; 11644 fault.address = gva; 11645 } 11646 vcpu->arch.walk_mmu->inject_page_fault(vcpu, &fault); 11647 } 11648 EXPORT_SYMBOL_GPL(kvm_fixup_and_inject_pf_error); 11649 11650 /* 11651 * Handles kvm_read/write_guest_virt*() result and either injects #PF or returns 11652 * KVM_EXIT_INTERNAL_ERROR for cases not currently handled by KVM. Return value 11653 * indicates whether exit to userspace is needed. 11654 */ 11655 int kvm_handle_memory_failure(struct kvm_vcpu *vcpu, int r, 11656 struct x86_exception *e) 11657 { 11658 if (r == X86EMUL_PROPAGATE_FAULT) { 11659 kvm_inject_emulated_page_fault(vcpu, e); 11660 return 1; 11661 } 11662 11663 /* 11664 * In case kvm_read/write_guest_virt*() failed with X86EMUL_IO_NEEDED 11665 * while handling a VMX instruction KVM could've handled the request 11666 * correctly by exiting to userspace and performing I/O but there 11667 * doesn't seem to be a real use-case behind such requests, just return 11668 * KVM_EXIT_INTERNAL_ERROR for now. 11669 */ 11670 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR; 11671 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION; 11672 vcpu->run->internal.ndata = 0; 11673 11674 return 0; 11675 } 11676 EXPORT_SYMBOL_GPL(kvm_handle_memory_failure); 11677 11678 int kvm_handle_invpcid(struct kvm_vcpu *vcpu, unsigned long type, gva_t gva) 11679 { 11680 bool pcid_enabled; 11681 struct x86_exception e; 11682 unsigned i; 11683 unsigned long roots_to_free = 0; 11684 struct { 11685 u64 pcid; 11686 u64 gla; 11687 } operand; 11688 int r; 11689 11690 r = kvm_read_guest_virt(vcpu, gva, &operand, sizeof(operand), &e); 11691 if (r != X86EMUL_CONTINUE) 11692 return kvm_handle_memory_failure(vcpu, r, &e); 11693 11694 if (operand.pcid >> 12 != 0) { 11695 kvm_inject_gp(vcpu, 0); 11696 return 1; 11697 } 11698 11699 pcid_enabled = kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE); 11700 11701 switch (type) { 11702 case INVPCID_TYPE_INDIV_ADDR: 11703 if ((!pcid_enabled && (operand.pcid != 0)) || 11704 is_noncanonical_address(operand.gla, vcpu)) { 11705 kvm_inject_gp(vcpu, 0); 11706 return 1; 11707 } 11708 kvm_mmu_invpcid_gva(vcpu, operand.gla, operand.pcid); 11709 return kvm_skip_emulated_instruction(vcpu); 11710 11711 case INVPCID_TYPE_SINGLE_CTXT: 11712 if (!pcid_enabled && (operand.pcid != 0)) { 11713 kvm_inject_gp(vcpu, 0); 11714 return 1; 11715 } 11716 11717 if (kvm_get_active_pcid(vcpu) == operand.pcid) { 11718 kvm_mmu_sync_roots(vcpu); 11719 kvm_make_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu); 11720 } 11721 11722 for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++) 11723 if (kvm_get_pcid(vcpu, vcpu->arch.mmu->prev_roots[i].pgd) 11724 == operand.pcid) 11725 roots_to_free |= KVM_MMU_ROOT_PREVIOUS(i); 11726 11727 kvm_mmu_free_roots(vcpu, vcpu->arch.mmu, roots_to_free); 11728 /* 11729 * If neither the current cr3 nor any of the prev_roots use the 11730 * given PCID, then nothing needs to be done here because a 11731 * resync will happen anyway before switching to any other CR3. 11732 */ 11733 11734 return kvm_skip_emulated_instruction(vcpu); 11735 11736 case INVPCID_TYPE_ALL_NON_GLOBAL: 11737 /* 11738 * Currently, KVM doesn't mark global entries in the shadow 11739 * page tables, so a non-global flush just degenerates to a 11740 * global flush. If needed, we could optimize this later by 11741 * keeping track of global entries in shadow page tables. 11742 */ 11743 11744 fallthrough; 11745 case INVPCID_TYPE_ALL_INCL_GLOBAL: 11746 kvm_make_request(KVM_REQ_MMU_RELOAD, vcpu); 11747 return kvm_skip_emulated_instruction(vcpu); 11748 11749 default: 11750 BUG(); /* We have already checked above that type <= 3 */ 11751 } 11752 } 11753 EXPORT_SYMBOL_GPL(kvm_handle_invpcid); 11754 11755 static int complete_sev_es_emulated_mmio(struct kvm_vcpu *vcpu) 11756 { 11757 struct kvm_run *run = vcpu->run; 11758 struct kvm_mmio_fragment *frag; 11759 unsigned int len; 11760 11761 BUG_ON(!vcpu->mmio_needed); 11762 11763 /* Complete previous fragment */ 11764 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment]; 11765 len = min(8u, frag->len); 11766 if (!vcpu->mmio_is_write) 11767 memcpy(frag->data, run->mmio.data, len); 11768 11769 if (frag->len <= 8) { 11770 /* Switch to the next fragment. */ 11771 frag++; 11772 vcpu->mmio_cur_fragment++; 11773 } else { 11774 /* Go forward to the next mmio piece. */ 11775 frag->data += len; 11776 frag->gpa += len; 11777 frag->len -= len; 11778 } 11779 11780 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) { 11781 vcpu->mmio_needed = 0; 11782 11783 // VMG change, at this point, we're always done 11784 // RIP has already been advanced 11785 return 1; 11786 } 11787 11788 // More MMIO is needed 11789 run->mmio.phys_addr = frag->gpa; 11790 run->mmio.len = min(8u, frag->len); 11791 run->mmio.is_write = vcpu->mmio_is_write; 11792 if (run->mmio.is_write) 11793 memcpy(run->mmio.data, frag->data, min(8u, frag->len)); 11794 run->exit_reason = KVM_EXIT_MMIO; 11795 11796 vcpu->arch.complete_userspace_io = complete_sev_es_emulated_mmio; 11797 11798 return 0; 11799 } 11800 11801 int kvm_sev_es_mmio_write(struct kvm_vcpu *vcpu, gpa_t gpa, unsigned int bytes, 11802 void *data) 11803 { 11804 int handled; 11805 struct kvm_mmio_fragment *frag; 11806 11807 if (!data) 11808 return -EINVAL; 11809 11810 handled = write_emultor.read_write_mmio(vcpu, gpa, bytes, data); 11811 if (handled == bytes) 11812 return 1; 11813 11814 bytes -= handled; 11815 gpa += handled; 11816 data += handled; 11817 11818 /*TODO: Check if need to increment number of frags */ 11819 frag = vcpu->mmio_fragments; 11820 vcpu->mmio_nr_fragments = 1; 11821 frag->len = bytes; 11822 frag->gpa = gpa; 11823 frag->data = data; 11824 11825 vcpu->mmio_needed = 1; 11826 vcpu->mmio_cur_fragment = 0; 11827 11828 vcpu->run->mmio.phys_addr = gpa; 11829 vcpu->run->mmio.len = min(8u, frag->len); 11830 vcpu->run->mmio.is_write = 1; 11831 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len)); 11832 vcpu->run->exit_reason = KVM_EXIT_MMIO; 11833 11834 vcpu->arch.complete_userspace_io = complete_sev_es_emulated_mmio; 11835 11836 return 0; 11837 } 11838 EXPORT_SYMBOL_GPL(kvm_sev_es_mmio_write); 11839 11840 int kvm_sev_es_mmio_read(struct kvm_vcpu *vcpu, gpa_t gpa, unsigned int bytes, 11841 void *data) 11842 { 11843 int handled; 11844 struct kvm_mmio_fragment *frag; 11845 11846 if (!data) 11847 return -EINVAL; 11848 11849 handled = read_emultor.read_write_mmio(vcpu, gpa, bytes, data); 11850 if (handled == bytes) 11851 return 1; 11852 11853 bytes -= handled; 11854 gpa += handled; 11855 data += handled; 11856 11857 /*TODO: Check if need to increment number of frags */ 11858 frag = vcpu->mmio_fragments; 11859 vcpu->mmio_nr_fragments = 1; 11860 frag->len = bytes; 11861 frag->gpa = gpa; 11862 frag->data = data; 11863 11864 vcpu->mmio_needed = 1; 11865 vcpu->mmio_cur_fragment = 0; 11866 11867 vcpu->run->mmio.phys_addr = gpa; 11868 vcpu->run->mmio.len = min(8u, frag->len); 11869 vcpu->run->mmio.is_write = 0; 11870 vcpu->run->exit_reason = KVM_EXIT_MMIO; 11871 11872 vcpu->arch.complete_userspace_io = complete_sev_es_emulated_mmio; 11873 11874 return 0; 11875 } 11876 EXPORT_SYMBOL_GPL(kvm_sev_es_mmio_read); 11877 11878 static int complete_sev_es_emulated_ins(struct kvm_vcpu *vcpu) 11879 { 11880 memcpy(vcpu->arch.guest_ins_data, vcpu->arch.pio_data, 11881 vcpu->arch.pio.count * vcpu->arch.pio.size); 11882 vcpu->arch.pio.count = 0; 11883 11884 return 1; 11885 } 11886 11887 static int kvm_sev_es_outs(struct kvm_vcpu *vcpu, unsigned int size, 11888 unsigned int port, void *data, unsigned int count) 11889 { 11890 int ret; 11891 11892 ret = emulator_pio_out_emulated(vcpu->arch.emulate_ctxt, size, port, 11893 data, count); 11894 if (ret) 11895 return ret; 11896 11897 vcpu->arch.pio.count = 0; 11898 11899 return 0; 11900 } 11901 11902 static int kvm_sev_es_ins(struct kvm_vcpu *vcpu, unsigned int size, 11903 unsigned int port, void *data, unsigned int count) 11904 { 11905 int ret; 11906 11907 ret = emulator_pio_in_emulated(vcpu->arch.emulate_ctxt, size, port, 11908 data, count); 11909 if (ret) { 11910 vcpu->arch.pio.count = 0; 11911 } else { 11912 vcpu->arch.guest_ins_data = data; 11913 vcpu->arch.complete_userspace_io = complete_sev_es_emulated_ins; 11914 } 11915 11916 return 0; 11917 } 11918 11919 int kvm_sev_es_string_io(struct kvm_vcpu *vcpu, unsigned int size, 11920 unsigned int port, void *data, unsigned int count, 11921 int in) 11922 { 11923 return in ? kvm_sev_es_ins(vcpu, size, port, data, count) 11924 : kvm_sev_es_outs(vcpu, size, port, data, count); 11925 } 11926 EXPORT_SYMBOL_GPL(kvm_sev_es_string_io); 11927 11928 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_entry); 11929 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit); 11930 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_fast_mmio); 11931 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq); 11932 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault); 11933 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr); 11934 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr); 11935 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun); 11936 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit); 11937 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject); 11938 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit); 11939 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmenter_failed); 11940 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga); 11941 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit); 11942 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts); 11943 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset); 11944 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_ple_window_update); 11945 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pml_full); 11946 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pi_irte_update); 11947 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_unaccelerated_access); 11948 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_incomplete_ipi); 11949 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_ga_log); 11950 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_apicv_update_request); 11951 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_vmgexit_enter); 11952 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_vmgexit_exit); 11953 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_vmgexit_msr_protocol_enter); 11954 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_vmgexit_msr_protocol_exit); 11955