1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Kernel-based Virtual Machine driver for Linux 4 * 5 * derived from drivers/kvm/kvm_main.c 6 * 7 * Copyright (C) 2006 Qumranet, Inc. 8 * Copyright (C) 2008 Qumranet, Inc. 9 * Copyright IBM Corporation, 2008 10 * Copyright 2010 Red Hat, Inc. and/or its affiliates. 11 * 12 * Authors: 13 * Avi Kivity <avi@qumranet.com> 14 * Yaniv Kamay <yaniv@qumranet.com> 15 * Amit Shah <amit.shah@qumranet.com> 16 * Ben-Ami Yassour <benami@il.ibm.com> 17 */ 18 19 #include <linux/kvm_host.h> 20 #include "irq.h" 21 #include "ioapic.h" 22 #include "mmu.h" 23 #include "i8254.h" 24 #include "tss.h" 25 #include "kvm_cache_regs.h" 26 #include "kvm_emulate.h" 27 #include "x86.h" 28 #include "cpuid.h" 29 #include "pmu.h" 30 #include "hyperv.h" 31 #include "lapic.h" 32 #include "xen.h" 33 34 #include <linux/clocksource.h> 35 #include <linux/interrupt.h> 36 #include <linux/kvm.h> 37 #include <linux/fs.h> 38 #include <linux/vmalloc.h> 39 #include <linux/export.h> 40 #include <linux/moduleparam.h> 41 #include <linux/mman.h> 42 #include <linux/highmem.h> 43 #include <linux/iommu.h> 44 #include <linux/intel-iommu.h> 45 #include <linux/cpufreq.h> 46 #include <linux/user-return-notifier.h> 47 #include <linux/srcu.h> 48 #include <linux/slab.h> 49 #include <linux/perf_event.h> 50 #include <linux/uaccess.h> 51 #include <linux/hash.h> 52 #include <linux/pci.h> 53 #include <linux/timekeeper_internal.h> 54 #include <linux/pvclock_gtod.h> 55 #include <linux/kvm_irqfd.h> 56 #include <linux/irqbypass.h> 57 #include <linux/sched/stat.h> 58 #include <linux/sched/isolation.h> 59 #include <linux/mem_encrypt.h> 60 #include <linux/entry-kvm.h> 61 #include <linux/suspend.h> 62 63 #include <trace/events/kvm.h> 64 65 #include <asm/debugreg.h> 66 #include <asm/msr.h> 67 #include <asm/desc.h> 68 #include <asm/mce.h> 69 #include <asm/pkru.h> 70 #include <linux/kernel_stat.h> 71 #include <asm/fpu/internal.h> /* Ugh! */ 72 #include <asm/pvclock.h> 73 #include <asm/div64.h> 74 #include <asm/irq_remapping.h> 75 #include <asm/mshyperv.h> 76 #include <asm/hypervisor.h> 77 #include <asm/tlbflush.h> 78 #include <asm/intel_pt.h> 79 #include <asm/emulate_prefix.h> 80 #include <asm/sgx.h> 81 #include <clocksource/hyperv_timer.h> 82 83 #define CREATE_TRACE_POINTS 84 #include "trace.h" 85 86 #define MAX_IO_MSRS 256 87 #define KVM_MAX_MCE_BANKS 32 88 u64 __read_mostly kvm_mce_cap_supported = MCG_CTL_P | MCG_SER_P; 89 EXPORT_SYMBOL_GPL(kvm_mce_cap_supported); 90 91 #define emul_to_vcpu(ctxt) \ 92 ((struct kvm_vcpu *)(ctxt)->vcpu) 93 94 /* EFER defaults: 95 * - enable syscall per default because its emulated by KVM 96 * - enable LME and LMA per default on 64 bit KVM 97 */ 98 #ifdef CONFIG_X86_64 99 static 100 u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA)); 101 #else 102 static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE); 103 #endif 104 105 static u64 __read_mostly cr4_reserved_bits = CR4_RESERVED_BITS; 106 107 #define KVM_EXIT_HYPERCALL_VALID_MASK (1 << KVM_HC_MAP_GPA_RANGE) 108 109 #define KVM_X2APIC_API_VALID_FLAGS (KVM_X2APIC_API_USE_32BIT_IDS | \ 110 KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK) 111 112 static void update_cr8_intercept(struct kvm_vcpu *vcpu); 113 static void process_nmi(struct kvm_vcpu *vcpu); 114 static void process_smi(struct kvm_vcpu *vcpu); 115 static void enter_smm(struct kvm_vcpu *vcpu); 116 static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags); 117 static void store_regs(struct kvm_vcpu *vcpu); 118 static int sync_regs(struct kvm_vcpu *vcpu); 119 120 static int __set_sregs2(struct kvm_vcpu *vcpu, struct kvm_sregs2 *sregs2); 121 static void __get_sregs2(struct kvm_vcpu *vcpu, struct kvm_sregs2 *sregs2); 122 123 struct kvm_x86_ops kvm_x86_ops __read_mostly; 124 EXPORT_SYMBOL_GPL(kvm_x86_ops); 125 126 #define KVM_X86_OP(func) \ 127 DEFINE_STATIC_CALL_NULL(kvm_x86_##func, \ 128 *(((struct kvm_x86_ops *)0)->func)); 129 #define KVM_X86_OP_NULL KVM_X86_OP 130 #include <asm/kvm-x86-ops.h> 131 EXPORT_STATIC_CALL_GPL(kvm_x86_get_cs_db_l_bits); 132 EXPORT_STATIC_CALL_GPL(kvm_x86_cache_reg); 133 EXPORT_STATIC_CALL_GPL(kvm_x86_tlb_flush_current); 134 135 static bool __read_mostly ignore_msrs = 0; 136 module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR); 137 138 bool __read_mostly report_ignored_msrs = true; 139 module_param(report_ignored_msrs, bool, S_IRUGO | S_IWUSR); 140 EXPORT_SYMBOL_GPL(report_ignored_msrs); 141 142 unsigned int min_timer_period_us = 200; 143 module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR); 144 145 static bool __read_mostly kvmclock_periodic_sync = true; 146 module_param(kvmclock_periodic_sync, bool, S_IRUGO); 147 148 bool __read_mostly kvm_has_tsc_control; 149 EXPORT_SYMBOL_GPL(kvm_has_tsc_control); 150 u32 __read_mostly kvm_max_guest_tsc_khz; 151 EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz); 152 u8 __read_mostly kvm_tsc_scaling_ratio_frac_bits; 153 EXPORT_SYMBOL_GPL(kvm_tsc_scaling_ratio_frac_bits); 154 u64 __read_mostly kvm_max_tsc_scaling_ratio; 155 EXPORT_SYMBOL_GPL(kvm_max_tsc_scaling_ratio); 156 u64 __read_mostly kvm_default_tsc_scaling_ratio; 157 EXPORT_SYMBOL_GPL(kvm_default_tsc_scaling_ratio); 158 bool __read_mostly kvm_has_bus_lock_exit; 159 EXPORT_SYMBOL_GPL(kvm_has_bus_lock_exit); 160 161 /* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */ 162 static u32 __read_mostly tsc_tolerance_ppm = 250; 163 module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR); 164 165 /* 166 * lapic timer advance (tscdeadline mode only) in nanoseconds. '-1' enables 167 * adaptive tuning starting from default advancement of 1000ns. '0' disables 168 * advancement entirely. Any other value is used as-is and disables adaptive 169 * tuning, i.e. allows privileged userspace to set an exact advancement time. 170 */ 171 static int __read_mostly lapic_timer_advance_ns = -1; 172 module_param(lapic_timer_advance_ns, int, S_IRUGO | S_IWUSR); 173 174 static bool __read_mostly vector_hashing = true; 175 module_param(vector_hashing, bool, S_IRUGO); 176 177 bool __read_mostly enable_vmware_backdoor = false; 178 module_param(enable_vmware_backdoor, bool, S_IRUGO); 179 EXPORT_SYMBOL_GPL(enable_vmware_backdoor); 180 181 static bool __read_mostly force_emulation_prefix = false; 182 module_param(force_emulation_prefix, bool, S_IRUGO); 183 184 int __read_mostly pi_inject_timer = -1; 185 module_param(pi_inject_timer, bint, S_IRUGO | S_IWUSR); 186 187 /* 188 * Restoring the host value for MSRs that are only consumed when running in 189 * usermode, e.g. SYSCALL MSRs and TSC_AUX, can be deferred until the CPU 190 * returns to userspace, i.e. the kernel can run with the guest's value. 191 */ 192 #define KVM_MAX_NR_USER_RETURN_MSRS 16 193 194 struct kvm_user_return_msrs { 195 struct user_return_notifier urn; 196 bool registered; 197 struct kvm_user_return_msr_values { 198 u64 host; 199 u64 curr; 200 } values[KVM_MAX_NR_USER_RETURN_MSRS]; 201 }; 202 203 u32 __read_mostly kvm_nr_uret_msrs; 204 EXPORT_SYMBOL_GPL(kvm_nr_uret_msrs); 205 static u32 __read_mostly kvm_uret_msrs_list[KVM_MAX_NR_USER_RETURN_MSRS]; 206 static struct kvm_user_return_msrs __percpu *user_return_msrs; 207 208 #define KVM_SUPPORTED_XCR0 (XFEATURE_MASK_FP | XFEATURE_MASK_SSE \ 209 | XFEATURE_MASK_YMM | XFEATURE_MASK_BNDREGS \ 210 | XFEATURE_MASK_BNDCSR | XFEATURE_MASK_AVX512 \ 211 | XFEATURE_MASK_PKRU) 212 213 u64 __read_mostly host_efer; 214 EXPORT_SYMBOL_GPL(host_efer); 215 216 bool __read_mostly allow_smaller_maxphyaddr = 0; 217 EXPORT_SYMBOL_GPL(allow_smaller_maxphyaddr); 218 219 bool __read_mostly enable_apicv = true; 220 EXPORT_SYMBOL_GPL(enable_apicv); 221 222 u64 __read_mostly host_xss; 223 EXPORT_SYMBOL_GPL(host_xss); 224 u64 __read_mostly supported_xss; 225 EXPORT_SYMBOL_GPL(supported_xss); 226 227 const struct _kvm_stats_desc kvm_vm_stats_desc[] = { 228 KVM_GENERIC_VM_STATS(), 229 STATS_DESC_COUNTER(VM, mmu_shadow_zapped), 230 STATS_DESC_COUNTER(VM, mmu_pte_write), 231 STATS_DESC_COUNTER(VM, mmu_pde_zapped), 232 STATS_DESC_COUNTER(VM, mmu_flooded), 233 STATS_DESC_COUNTER(VM, mmu_recycled), 234 STATS_DESC_COUNTER(VM, mmu_cache_miss), 235 STATS_DESC_ICOUNTER(VM, mmu_unsync), 236 STATS_DESC_ICOUNTER(VM, lpages), 237 STATS_DESC_ICOUNTER(VM, nx_lpage_splits), 238 STATS_DESC_PCOUNTER(VM, max_mmu_page_hash_collisions) 239 }; 240 static_assert(ARRAY_SIZE(kvm_vm_stats_desc) == 241 sizeof(struct kvm_vm_stat) / sizeof(u64)); 242 243 const struct kvm_stats_header kvm_vm_stats_header = { 244 .name_size = KVM_STATS_NAME_SIZE, 245 .num_desc = ARRAY_SIZE(kvm_vm_stats_desc), 246 .id_offset = sizeof(struct kvm_stats_header), 247 .desc_offset = sizeof(struct kvm_stats_header) + KVM_STATS_NAME_SIZE, 248 .data_offset = sizeof(struct kvm_stats_header) + KVM_STATS_NAME_SIZE + 249 sizeof(kvm_vm_stats_desc), 250 }; 251 252 const struct _kvm_stats_desc kvm_vcpu_stats_desc[] = { 253 KVM_GENERIC_VCPU_STATS(), 254 STATS_DESC_COUNTER(VCPU, pf_fixed), 255 STATS_DESC_COUNTER(VCPU, pf_guest), 256 STATS_DESC_COUNTER(VCPU, tlb_flush), 257 STATS_DESC_COUNTER(VCPU, invlpg), 258 STATS_DESC_COUNTER(VCPU, exits), 259 STATS_DESC_COUNTER(VCPU, io_exits), 260 STATS_DESC_COUNTER(VCPU, mmio_exits), 261 STATS_DESC_COUNTER(VCPU, signal_exits), 262 STATS_DESC_COUNTER(VCPU, irq_window_exits), 263 STATS_DESC_COUNTER(VCPU, nmi_window_exits), 264 STATS_DESC_COUNTER(VCPU, l1d_flush), 265 STATS_DESC_COUNTER(VCPU, halt_exits), 266 STATS_DESC_COUNTER(VCPU, request_irq_exits), 267 STATS_DESC_COUNTER(VCPU, irq_exits), 268 STATS_DESC_COUNTER(VCPU, host_state_reload), 269 STATS_DESC_COUNTER(VCPU, fpu_reload), 270 STATS_DESC_COUNTER(VCPU, insn_emulation), 271 STATS_DESC_COUNTER(VCPU, insn_emulation_fail), 272 STATS_DESC_COUNTER(VCPU, hypercalls), 273 STATS_DESC_COUNTER(VCPU, irq_injections), 274 STATS_DESC_COUNTER(VCPU, nmi_injections), 275 STATS_DESC_COUNTER(VCPU, req_event), 276 STATS_DESC_COUNTER(VCPU, nested_run), 277 STATS_DESC_COUNTER(VCPU, directed_yield_attempted), 278 STATS_DESC_COUNTER(VCPU, directed_yield_successful), 279 STATS_DESC_ICOUNTER(VCPU, guest_mode) 280 }; 281 static_assert(ARRAY_SIZE(kvm_vcpu_stats_desc) == 282 sizeof(struct kvm_vcpu_stat) / sizeof(u64)); 283 284 const struct kvm_stats_header kvm_vcpu_stats_header = { 285 .name_size = KVM_STATS_NAME_SIZE, 286 .num_desc = ARRAY_SIZE(kvm_vcpu_stats_desc), 287 .id_offset = sizeof(struct kvm_stats_header), 288 .desc_offset = sizeof(struct kvm_stats_header) + KVM_STATS_NAME_SIZE, 289 .data_offset = sizeof(struct kvm_stats_header) + KVM_STATS_NAME_SIZE + 290 sizeof(kvm_vcpu_stats_desc), 291 }; 292 293 u64 __read_mostly host_xcr0; 294 u64 __read_mostly supported_xcr0; 295 EXPORT_SYMBOL_GPL(supported_xcr0); 296 297 static struct kmem_cache *x86_fpu_cache; 298 299 static struct kmem_cache *x86_emulator_cache; 300 301 /* 302 * When called, it means the previous get/set msr reached an invalid msr. 303 * Return true if we want to ignore/silent this failed msr access. 304 */ 305 static bool kvm_msr_ignored_check(u32 msr, u64 data, bool write) 306 { 307 const char *op = write ? "wrmsr" : "rdmsr"; 308 309 if (ignore_msrs) { 310 if (report_ignored_msrs) 311 kvm_pr_unimpl("ignored %s: 0x%x data 0x%llx\n", 312 op, msr, data); 313 /* Mask the error */ 314 return true; 315 } else { 316 kvm_debug_ratelimited("unhandled %s: 0x%x data 0x%llx\n", 317 op, msr, data); 318 return false; 319 } 320 } 321 322 static struct kmem_cache *kvm_alloc_emulator_cache(void) 323 { 324 unsigned int useroffset = offsetof(struct x86_emulate_ctxt, src); 325 unsigned int size = sizeof(struct x86_emulate_ctxt); 326 327 return kmem_cache_create_usercopy("x86_emulator", size, 328 __alignof__(struct x86_emulate_ctxt), 329 SLAB_ACCOUNT, useroffset, 330 size - useroffset, NULL); 331 } 332 333 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt); 334 335 static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu) 336 { 337 int i; 338 for (i = 0; i < ASYNC_PF_PER_VCPU; i++) 339 vcpu->arch.apf.gfns[i] = ~0; 340 } 341 342 static void kvm_on_user_return(struct user_return_notifier *urn) 343 { 344 unsigned slot; 345 struct kvm_user_return_msrs *msrs 346 = container_of(urn, struct kvm_user_return_msrs, urn); 347 struct kvm_user_return_msr_values *values; 348 unsigned long flags; 349 350 /* 351 * Disabling irqs at this point since the following code could be 352 * interrupted and executed through kvm_arch_hardware_disable() 353 */ 354 local_irq_save(flags); 355 if (msrs->registered) { 356 msrs->registered = false; 357 user_return_notifier_unregister(urn); 358 } 359 local_irq_restore(flags); 360 for (slot = 0; slot < kvm_nr_uret_msrs; ++slot) { 361 values = &msrs->values[slot]; 362 if (values->host != values->curr) { 363 wrmsrl(kvm_uret_msrs_list[slot], values->host); 364 values->curr = values->host; 365 } 366 } 367 } 368 369 static int kvm_probe_user_return_msr(u32 msr) 370 { 371 u64 val; 372 int ret; 373 374 preempt_disable(); 375 ret = rdmsrl_safe(msr, &val); 376 if (ret) 377 goto out; 378 ret = wrmsrl_safe(msr, val); 379 out: 380 preempt_enable(); 381 return ret; 382 } 383 384 int kvm_add_user_return_msr(u32 msr) 385 { 386 BUG_ON(kvm_nr_uret_msrs >= KVM_MAX_NR_USER_RETURN_MSRS); 387 388 if (kvm_probe_user_return_msr(msr)) 389 return -1; 390 391 kvm_uret_msrs_list[kvm_nr_uret_msrs] = msr; 392 return kvm_nr_uret_msrs++; 393 } 394 EXPORT_SYMBOL_GPL(kvm_add_user_return_msr); 395 396 int kvm_find_user_return_msr(u32 msr) 397 { 398 int i; 399 400 for (i = 0; i < kvm_nr_uret_msrs; ++i) { 401 if (kvm_uret_msrs_list[i] == msr) 402 return i; 403 } 404 return -1; 405 } 406 EXPORT_SYMBOL_GPL(kvm_find_user_return_msr); 407 408 static void kvm_user_return_msr_cpu_online(void) 409 { 410 unsigned int cpu = smp_processor_id(); 411 struct kvm_user_return_msrs *msrs = per_cpu_ptr(user_return_msrs, cpu); 412 u64 value; 413 int i; 414 415 for (i = 0; i < kvm_nr_uret_msrs; ++i) { 416 rdmsrl_safe(kvm_uret_msrs_list[i], &value); 417 msrs->values[i].host = value; 418 msrs->values[i].curr = value; 419 } 420 } 421 422 int kvm_set_user_return_msr(unsigned slot, u64 value, u64 mask) 423 { 424 unsigned int cpu = smp_processor_id(); 425 struct kvm_user_return_msrs *msrs = per_cpu_ptr(user_return_msrs, cpu); 426 int err; 427 428 value = (value & mask) | (msrs->values[slot].host & ~mask); 429 if (value == msrs->values[slot].curr) 430 return 0; 431 err = wrmsrl_safe(kvm_uret_msrs_list[slot], value); 432 if (err) 433 return 1; 434 435 msrs->values[slot].curr = value; 436 if (!msrs->registered) { 437 msrs->urn.on_user_return = kvm_on_user_return; 438 user_return_notifier_register(&msrs->urn); 439 msrs->registered = true; 440 } 441 return 0; 442 } 443 EXPORT_SYMBOL_GPL(kvm_set_user_return_msr); 444 445 static void drop_user_return_notifiers(void) 446 { 447 unsigned int cpu = smp_processor_id(); 448 struct kvm_user_return_msrs *msrs = per_cpu_ptr(user_return_msrs, cpu); 449 450 if (msrs->registered) 451 kvm_on_user_return(&msrs->urn); 452 } 453 454 u64 kvm_get_apic_base(struct kvm_vcpu *vcpu) 455 { 456 return vcpu->arch.apic_base; 457 } 458 EXPORT_SYMBOL_GPL(kvm_get_apic_base); 459 460 enum lapic_mode kvm_get_apic_mode(struct kvm_vcpu *vcpu) 461 { 462 return kvm_apic_mode(kvm_get_apic_base(vcpu)); 463 } 464 EXPORT_SYMBOL_GPL(kvm_get_apic_mode); 465 466 int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info) 467 { 468 enum lapic_mode old_mode = kvm_get_apic_mode(vcpu); 469 enum lapic_mode new_mode = kvm_apic_mode(msr_info->data); 470 u64 reserved_bits = kvm_vcpu_reserved_gpa_bits_raw(vcpu) | 0x2ff | 471 (guest_cpuid_has(vcpu, X86_FEATURE_X2APIC) ? 0 : X2APIC_ENABLE); 472 473 if ((msr_info->data & reserved_bits) != 0 || new_mode == LAPIC_MODE_INVALID) 474 return 1; 475 if (!msr_info->host_initiated) { 476 if (old_mode == LAPIC_MODE_X2APIC && new_mode == LAPIC_MODE_XAPIC) 477 return 1; 478 if (old_mode == LAPIC_MODE_DISABLED && new_mode == LAPIC_MODE_X2APIC) 479 return 1; 480 } 481 482 kvm_lapic_set_base(vcpu, msr_info->data); 483 kvm_recalculate_apic_map(vcpu->kvm); 484 return 0; 485 } 486 EXPORT_SYMBOL_GPL(kvm_set_apic_base); 487 488 asmlinkage __visible noinstr void kvm_spurious_fault(void) 489 { 490 /* Fault while not rebooting. We want the trace. */ 491 BUG_ON(!kvm_rebooting); 492 } 493 EXPORT_SYMBOL_GPL(kvm_spurious_fault); 494 495 #define EXCPT_BENIGN 0 496 #define EXCPT_CONTRIBUTORY 1 497 #define EXCPT_PF 2 498 499 static int exception_class(int vector) 500 { 501 switch (vector) { 502 case PF_VECTOR: 503 return EXCPT_PF; 504 case DE_VECTOR: 505 case TS_VECTOR: 506 case NP_VECTOR: 507 case SS_VECTOR: 508 case GP_VECTOR: 509 return EXCPT_CONTRIBUTORY; 510 default: 511 break; 512 } 513 return EXCPT_BENIGN; 514 } 515 516 #define EXCPT_FAULT 0 517 #define EXCPT_TRAP 1 518 #define EXCPT_ABORT 2 519 #define EXCPT_INTERRUPT 3 520 521 static int exception_type(int vector) 522 { 523 unsigned int mask; 524 525 if (WARN_ON(vector > 31 || vector == NMI_VECTOR)) 526 return EXCPT_INTERRUPT; 527 528 mask = 1 << vector; 529 530 /* #DB is trap, as instruction watchpoints are handled elsewhere */ 531 if (mask & ((1 << DB_VECTOR) | (1 << BP_VECTOR) | (1 << OF_VECTOR))) 532 return EXCPT_TRAP; 533 534 if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR))) 535 return EXCPT_ABORT; 536 537 /* Reserved exceptions will result in fault */ 538 return EXCPT_FAULT; 539 } 540 541 void kvm_deliver_exception_payload(struct kvm_vcpu *vcpu) 542 { 543 unsigned nr = vcpu->arch.exception.nr; 544 bool has_payload = vcpu->arch.exception.has_payload; 545 unsigned long payload = vcpu->arch.exception.payload; 546 547 if (!has_payload) 548 return; 549 550 switch (nr) { 551 case DB_VECTOR: 552 /* 553 * "Certain debug exceptions may clear bit 0-3. The 554 * remaining contents of the DR6 register are never 555 * cleared by the processor". 556 */ 557 vcpu->arch.dr6 &= ~DR_TRAP_BITS; 558 /* 559 * In order to reflect the #DB exception payload in guest 560 * dr6, three components need to be considered: active low 561 * bit, FIXED_1 bits and active high bits (e.g. DR6_BD, 562 * DR6_BS and DR6_BT) 563 * DR6_ACTIVE_LOW contains the FIXED_1 and active low bits. 564 * In the target guest dr6: 565 * FIXED_1 bits should always be set. 566 * Active low bits should be cleared if 1-setting in payload. 567 * Active high bits should be set if 1-setting in payload. 568 * 569 * Note, the payload is compatible with the pending debug 570 * exceptions/exit qualification under VMX, that active_low bits 571 * are active high in payload. 572 * So they need to be flipped for DR6. 573 */ 574 vcpu->arch.dr6 |= DR6_ACTIVE_LOW; 575 vcpu->arch.dr6 |= payload; 576 vcpu->arch.dr6 ^= payload & DR6_ACTIVE_LOW; 577 578 /* 579 * The #DB payload is defined as compatible with the 'pending 580 * debug exceptions' field under VMX, not DR6. While bit 12 is 581 * defined in the 'pending debug exceptions' field (enabled 582 * breakpoint), it is reserved and must be zero in DR6. 583 */ 584 vcpu->arch.dr6 &= ~BIT(12); 585 break; 586 case PF_VECTOR: 587 vcpu->arch.cr2 = payload; 588 break; 589 } 590 591 vcpu->arch.exception.has_payload = false; 592 vcpu->arch.exception.payload = 0; 593 } 594 EXPORT_SYMBOL_GPL(kvm_deliver_exception_payload); 595 596 static void kvm_multiple_exception(struct kvm_vcpu *vcpu, 597 unsigned nr, bool has_error, u32 error_code, 598 bool has_payload, unsigned long payload, bool reinject) 599 { 600 u32 prev_nr; 601 int class1, class2; 602 603 kvm_make_request(KVM_REQ_EVENT, vcpu); 604 605 if (!vcpu->arch.exception.pending && !vcpu->arch.exception.injected) { 606 queue: 607 if (reinject) { 608 /* 609 * On vmentry, vcpu->arch.exception.pending is only 610 * true if an event injection was blocked by 611 * nested_run_pending. In that case, however, 612 * vcpu_enter_guest requests an immediate exit, 613 * and the guest shouldn't proceed far enough to 614 * need reinjection. 615 */ 616 WARN_ON_ONCE(vcpu->arch.exception.pending); 617 vcpu->arch.exception.injected = true; 618 if (WARN_ON_ONCE(has_payload)) { 619 /* 620 * A reinjected event has already 621 * delivered its payload. 622 */ 623 has_payload = false; 624 payload = 0; 625 } 626 } else { 627 vcpu->arch.exception.pending = true; 628 vcpu->arch.exception.injected = false; 629 } 630 vcpu->arch.exception.has_error_code = has_error; 631 vcpu->arch.exception.nr = nr; 632 vcpu->arch.exception.error_code = error_code; 633 vcpu->arch.exception.has_payload = has_payload; 634 vcpu->arch.exception.payload = payload; 635 if (!is_guest_mode(vcpu)) 636 kvm_deliver_exception_payload(vcpu); 637 return; 638 } 639 640 /* to check exception */ 641 prev_nr = vcpu->arch.exception.nr; 642 if (prev_nr == DF_VECTOR) { 643 /* triple fault -> shutdown */ 644 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); 645 return; 646 } 647 class1 = exception_class(prev_nr); 648 class2 = exception_class(nr); 649 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY) 650 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) { 651 /* 652 * Generate double fault per SDM Table 5-5. Set 653 * exception.pending = true so that the double fault 654 * can trigger a nested vmexit. 655 */ 656 vcpu->arch.exception.pending = true; 657 vcpu->arch.exception.injected = false; 658 vcpu->arch.exception.has_error_code = true; 659 vcpu->arch.exception.nr = DF_VECTOR; 660 vcpu->arch.exception.error_code = 0; 661 vcpu->arch.exception.has_payload = false; 662 vcpu->arch.exception.payload = 0; 663 } else 664 /* replace previous exception with a new one in a hope 665 that instruction re-execution will regenerate lost 666 exception */ 667 goto queue; 668 } 669 670 void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr) 671 { 672 kvm_multiple_exception(vcpu, nr, false, 0, false, 0, false); 673 } 674 EXPORT_SYMBOL_GPL(kvm_queue_exception); 675 676 void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr) 677 { 678 kvm_multiple_exception(vcpu, nr, false, 0, false, 0, true); 679 } 680 EXPORT_SYMBOL_GPL(kvm_requeue_exception); 681 682 void kvm_queue_exception_p(struct kvm_vcpu *vcpu, unsigned nr, 683 unsigned long payload) 684 { 685 kvm_multiple_exception(vcpu, nr, false, 0, true, payload, false); 686 } 687 EXPORT_SYMBOL_GPL(kvm_queue_exception_p); 688 689 static void kvm_queue_exception_e_p(struct kvm_vcpu *vcpu, unsigned nr, 690 u32 error_code, unsigned long payload) 691 { 692 kvm_multiple_exception(vcpu, nr, true, error_code, 693 true, payload, false); 694 } 695 696 int kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err) 697 { 698 if (err) 699 kvm_inject_gp(vcpu, 0); 700 else 701 return kvm_skip_emulated_instruction(vcpu); 702 703 return 1; 704 } 705 EXPORT_SYMBOL_GPL(kvm_complete_insn_gp); 706 707 void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault) 708 { 709 ++vcpu->stat.pf_guest; 710 vcpu->arch.exception.nested_apf = 711 is_guest_mode(vcpu) && fault->async_page_fault; 712 if (vcpu->arch.exception.nested_apf) { 713 vcpu->arch.apf.nested_apf_token = fault->address; 714 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code); 715 } else { 716 kvm_queue_exception_e_p(vcpu, PF_VECTOR, fault->error_code, 717 fault->address); 718 } 719 } 720 EXPORT_SYMBOL_GPL(kvm_inject_page_fault); 721 722 bool kvm_inject_emulated_page_fault(struct kvm_vcpu *vcpu, 723 struct x86_exception *fault) 724 { 725 struct kvm_mmu *fault_mmu; 726 WARN_ON_ONCE(fault->vector != PF_VECTOR); 727 728 fault_mmu = fault->nested_page_fault ? vcpu->arch.mmu : 729 vcpu->arch.walk_mmu; 730 731 /* 732 * Invalidate the TLB entry for the faulting address, if it exists, 733 * else the access will fault indefinitely (and to emulate hardware). 734 */ 735 if ((fault->error_code & PFERR_PRESENT_MASK) && 736 !(fault->error_code & PFERR_RSVD_MASK)) 737 kvm_mmu_invalidate_gva(vcpu, fault_mmu, fault->address, 738 fault_mmu->root_hpa); 739 740 fault_mmu->inject_page_fault(vcpu, fault); 741 return fault->nested_page_fault; 742 } 743 EXPORT_SYMBOL_GPL(kvm_inject_emulated_page_fault); 744 745 void kvm_inject_nmi(struct kvm_vcpu *vcpu) 746 { 747 atomic_inc(&vcpu->arch.nmi_queued); 748 kvm_make_request(KVM_REQ_NMI, vcpu); 749 } 750 EXPORT_SYMBOL_GPL(kvm_inject_nmi); 751 752 void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code) 753 { 754 kvm_multiple_exception(vcpu, nr, true, error_code, false, 0, false); 755 } 756 EXPORT_SYMBOL_GPL(kvm_queue_exception_e); 757 758 void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code) 759 { 760 kvm_multiple_exception(vcpu, nr, true, error_code, false, 0, true); 761 } 762 EXPORT_SYMBOL_GPL(kvm_requeue_exception_e); 763 764 /* 765 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue 766 * a #GP and return false. 767 */ 768 bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl) 769 { 770 if (static_call(kvm_x86_get_cpl)(vcpu) <= required_cpl) 771 return true; 772 kvm_queue_exception_e(vcpu, GP_VECTOR, 0); 773 return false; 774 } 775 EXPORT_SYMBOL_GPL(kvm_require_cpl); 776 777 bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr) 778 { 779 if ((dr != 4 && dr != 5) || !kvm_read_cr4_bits(vcpu, X86_CR4_DE)) 780 return true; 781 782 kvm_queue_exception(vcpu, UD_VECTOR); 783 return false; 784 } 785 EXPORT_SYMBOL_GPL(kvm_require_dr); 786 787 /* 788 * This function will be used to read from the physical memory of the currently 789 * running guest. The difference to kvm_vcpu_read_guest_page is that this function 790 * can read from guest physical or from the guest's guest physical memory. 791 */ 792 int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, 793 gfn_t ngfn, void *data, int offset, int len, 794 u32 access) 795 { 796 struct x86_exception exception; 797 gfn_t real_gfn; 798 gpa_t ngpa; 799 800 ngpa = gfn_to_gpa(ngfn); 801 real_gfn = mmu->translate_gpa(vcpu, ngpa, access, &exception); 802 if (real_gfn == UNMAPPED_GVA) 803 return -EFAULT; 804 805 real_gfn = gpa_to_gfn(real_gfn); 806 807 return kvm_vcpu_read_guest_page(vcpu, real_gfn, data, offset, len); 808 } 809 EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu); 810 811 static inline u64 pdptr_rsvd_bits(struct kvm_vcpu *vcpu) 812 { 813 return vcpu->arch.reserved_gpa_bits | rsvd_bits(5, 8) | rsvd_bits(1, 2); 814 } 815 816 /* 817 * Load the pae pdptrs. Return 1 if they are all valid, 0 otherwise. 818 */ 819 int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3) 820 { 821 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT; 822 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2; 823 int i; 824 int ret; 825 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)]; 826 827 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte, 828 offset * sizeof(u64), sizeof(pdpte), 829 PFERR_USER_MASK|PFERR_WRITE_MASK); 830 if (ret < 0) { 831 ret = 0; 832 goto out; 833 } 834 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) { 835 if ((pdpte[i] & PT_PRESENT_MASK) && 836 (pdpte[i] & pdptr_rsvd_bits(vcpu))) { 837 ret = 0; 838 goto out; 839 } 840 } 841 ret = 1; 842 843 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs)); 844 kvm_register_mark_dirty(vcpu, VCPU_EXREG_PDPTR); 845 vcpu->arch.pdptrs_from_userspace = false; 846 847 out: 848 849 return ret; 850 } 851 EXPORT_SYMBOL_GPL(load_pdptrs); 852 853 void kvm_post_set_cr0(struct kvm_vcpu *vcpu, unsigned long old_cr0, unsigned long cr0) 854 { 855 if ((cr0 ^ old_cr0) & X86_CR0_PG) { 856 kvm_clear_async_pf_completion_queue(vcpu); 857 kvm_async_pf_hash_reset(vcpu); 858 } 859 860 if ((cr0 ^ old_cr0) & KVM_MMU_CR0_ROLE_BITS) 861 kvm_mmu_reset_context(vcpu); 862 863 if (((cr0 ^ old_cr0) & X86_CR0_CD) && 864 kvm_arch_has_noncoherent_dma(vcpu->kvm) && 865 !kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED)) 866 kvm_zap_gfn_range(vcpu->kvm, 0, ~0ULL); 867 } 868 EXPORT_SYMBOL_GPL(kvm_post_set_cr0); 869 870 int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0) 871 { 872 unsigned long old_cr0 = kvm_read_cr0(vcpu); 873 unsigned long pdptr_bits = X86_CR0_CD | X86_CR0_NW | X86_CR0_PG; 874 875 cr0 |= X86_CR0_ET; 876 877 #ifdef CONFIG_X86_64 878 if (cr0 & 0xffffffff00000000UL) 879 return 1; 880 #endif 881 882 cr0 &= ~CR0_RESERVED_BITS; 883 884 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD)) 885 return 1; 886 887 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE)) 888 return 1; 889 890 #ifdef CONFIG_X86_64 891 if ((vcpu->arch.efer & EFER_LME) && !is_paging(vcpu) && 892 (cr0 & X86_CR0_PG)) { 893 int cs_db, cs_l; 894 895 if (!is_pae(vcpu)) 896 return 1; 897 static_call(kvm_x86_get_cs_db_l_bits)(vcpu, &cs_db, &cs_l); 898 if (cs_l) 899 return 1; 900 } 901 #endif 902 if (!(vcpu->arch.efer & EFER_LME) && (cr0 & X86_CR0_PG) && 903 is_pae(vcpu) && ((cr0 ^ old_cr0) & pdptr_bits) && 904 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu))) 905 return 1; 906 907 if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE)) 908 return 1; 909 910 static_call(kvm_x86_set_cr0)(vcpu, cr0); 911 912 kvm_post_set_cr0(vcpu, old_cr0, cr0); 913 914 return 0; 915 } 916 EXPORT_SYMBOL_GPL(kvm_set_cr0); 917 918 void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw) 919 { 920 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f)); 921 } 922 EXPORT_SYMBOL_GPL(kvm_lmsw); 923 924 void kvm_load_guest_xsave_state(struct kvm_vcpu *vcpu) 925 { 926 if (vcpu->arch.guest_state_protected) 927 return; 928 929 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE)) { 930 931 if (vcpu->arch.xcr0 != host_xcr0) 932 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0); 933 934 if (vcpu->arch.xsaves_enabled && 935 vcpu->arch.ia32_xss != host_xss) 936 wrmsrl(MSR_IA32_XSS, vcpu->arch.ia32_xss); 937 } 938 939 if (static_cpu_has(X86_FEATURE_PKU) && 940 (kvm_read_cr4_bits(vcpu, X86_CR4_PKE) || 941 (vcpu->arch.xcr0 & XFEATURE_MASK_PKRU)) && 942 vcpu->arch.pkru != vcpu->arch.host_pkru) 943 write_pkru(vcpu->arch.pkru); 944 } 945 EXPORT_SYMBOL_GPL(kvm_load_guest_xsave_state); 946 947 void kvm_load_host_xsave_state(struct kvm_vcpu *vcpu) 948 { 949 if (vcpu->arch.guest_state_protected) 950 return; 951 952 if (static_cpu_has(X86_FEATURE_PKU) && 953 (kvm_read_cr4_bits(vcpu, X86_CR4_PKE) || 954 (vcpu->arch.xcr0 & XFEATURE_MASK_PKRU))) { 955 vcpu->arch.pkru = rdpkru(); 956 if (vcpu->arch.pkru != vcpu->arch.host_pkru) 957 write_pkru(vcpu->arch.host_pkru); 958 } 959 960 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE)) { 961 962 if (vcpu->arch.xcr0 != host_xcr0) 963 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0); 964 965 if (vcpu->arch.xsaves_enabled && 966 vcpu->arch.ia32_xss != host_xss) 967 wrmsrl(MSR_IA32_XSS, host_xss); 968 } 969 970 } 971 EXPORT_SYMBOL_GPL(kvm_load_host_xsave_state); 972 973 static int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr) 974 { 975 u64 xcr0 = xcr; 976 u64 old_xcr0 = vcpu->arch.xcr0; 977 u64 valid_bits; 978 979 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */ 980 if (index != XCR_XFEATURE_ENABLED_MASK) 981 return 1; 982 if (!(xcr0 & XFEATURE_MASK_FP)) 983 return 1; 984 if ((xcr0 & XFEATURE_MASK_YMM) && !(xcr0 & XFEATURE_MASK_SSE)) 985 return 1; 986 987 /* 988 * Do not allow the guest to set bits that we do not support 989 * saving. However, xcr0 bit 0 is always set, even if the 990 * emulated CPU does not support XSAVE (see fx_init). 991 */ 992 valid_bits = vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FP; 993 if (xcr0 & ~valid_bits) 994 return 1; 995 996 if ((!(xcr0 & XFEATURE_MASK_BNDREGS)) != 997 (!(xcr0 & XFEATURE_MASK_BNDCSR))) 998 return 1; 999 1000 if (xcr0 & XFEATURE_MASK_AVX512) { 1001 if (!(xcr0 & XFEATURE_MASK_YMM)) 1002 return 1; 1003 if ((xcr0 & XFEATURE_MASK_AVX512) != XFEATURE_MASK_AVX512) 1004 return 1; 1005 } 1006 vcpu->arch.xcr0 = xcr0; 1007 1008 if ((xcr0 ^ old_xcr0) & XFEATURE_MASK_EXTEND) 1009 kvm_update_cpuid_runtime(vcpu); 1010 return 0; 1011 } 1012 1013 int kvm_emulate_xsetbv(struct kvm_vcpu *vcpu) 1014 { 1015 if (static_call(kvm_x86_get_cpl)(vcpu) != 0 || 1016 __kvm_set_xcr(vcpu, kvm_rcx_read(vcpu), kvm_read_edx_eax(vcpu))) { 1017 kvm_inject_gp(vcpu, 0); 1018 return 1; 1019 } 1020 1021 return kvm_skip_emulated_instruction(vcpu); 1022 } 1023 EXPORT_SYMBOL_GPL(kvm_emulate_xsetbv); 1024 1025 bool kvm_is_valid_cr4(struct kvm_vcpu *vcpu, unsigned long cr4) 1026 { 1027 if (cr4 & cr4_reserved_bits) 1028 return false; 1029 1030 if (cr4 & vcpu->arch.cr4_guest_rsvd_bits) 1031 return false; 1032 1033 return static_call(kvm_x86_is_valid_cr4)(vcpu, cr4); 1034 } 1035 EXPORT_SYMBOL_GPL(kvm_is_valid_cr4); 1036 1037 void kvm_post_set_cr4(struct kvm_vcpu *vcpu, unsigned long old_cr4, unsigned long cr4) 1038 { 1039 if (((cr4 ^ old_cr4) & KVM_MMU_CR4_ROLE_BITS) || 1040 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE))) 1041 kvm_mmu_reset_context(vcpu); 1042 } 1043 EXPORT_SYMBOL_GPL(kvm_post_set_cr4); 1044 1045 int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4) 1046 { 1047 unsigned long old_cr4 = kvm_read_cr4(vcpu); 1048 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE | 1049 X86_CR4_SMEP; 1050 1051 if (!kvm_is_valid_cr4(vcpu, cr4)) 1052 return 1; 1053 1054 if (is_long_mode(vcpu)) { 1055 if (!(cr4 & X86_CR4_PAE)) 1056 return 1; 1057 if ((cr4 ^ old_cr4) & X86_CR4_LA57) 1058 return 1; 1059 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE) 1060 && ((cr4 ^ old_cr4) & pdptr_bits) 1061 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu, 1062 kvm_read_cr3(vcpu))) 1063 return 1; 1064 1065 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) { 1066 if (!guest_cpuid_has(vcpu, X86_FEATURE_PCID)) 1067 return 1; 1068 1069 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */ 1070 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu)) 1071 return 1; 1072 } 1073 1074 static_call(kvm_x86_set_cr4)(vcpu, cr4); 1075 1076 kvm_post_set_cr4(vcpu, old_cr4, cr4); 1077 1078 return 0; 1079 } 1080 EXPORT_SYMBOL_GPL(kvm_set_cr4); 1081 1082 static void kvm_invalidate_pcid(struct kvm_vcpu *vcpu, unsigned long pcid) 1083 { 1084 struct kvm_mmu *mmu = vcpu->arch.mmu; 1085 unsigned long roots_to_free = 0; 1086 int i; 1087 1088 /* 1089 * If neither the current CR3 nor any of the prev_roots use the given 1090 * PCID, then nothing needs to be done here because a resync will 1091 * happen anyway before switching to any other CR3. 1092 */ 1093 if (kvm_get_active_pcid(vcpu) == pcid) { 1094 kvm_make_request(KVM_REQ_MMU_SYNC, vcpu); 1095 kvm_make_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu); 1096 } 1097 1098 for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++) 1099 if (kvm_get_pcid(vcpu, mmu->prev_roots[i].pgd) == pcid) 1100 roots_to_free |= KVM_MMU_ROOT_PREVIOUS(i); 1101 1102 kvm_mmu_free_roots(vcpu, mmu, roots_to_free); 1103 } 1104 1105 int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3) 1106 { 1107 bool skip_tlb_flush = false; 1108 unsigned long pcid = 0; 1109 #ifdef CONFIG_X86_64 1110 bool pcid_enabled = kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE); 1111 1112 if (pcid_enabled) { 1113 skip_tlb_flush = cr3 & X86_CR3_PCID_NOFLUSH; 1114 cr3 &= ~X86_CR3_PCID_NOFLUSH; 1115 pcid = cr3 & X86_CR3_PCID_MASK; 1116 } 1117 #endif 1118 1119 /* PDPTRs are always reloaded for PAE paging. */ 1120 if (cr3 == kvm_read_cr3(vcpu) && !is_pae_paging(vcpu)) 1121 goto handle_tlb_flush; 1122 1123 /* 1124 * Do not condition the GPA check on long mode, this helper is used to 1125 * stuff CR3, e.g. for RSM emulation, and there is no guarantee that 1126 * the current vCPU mode is accurate. 1127 */ 1128 if (kvm_vcpu_is_illegal_gpa(vcpu, cr3)) 1129 return 1; 1130 1131 if (is_pae_paging(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3)) 1132 return 1; 1133 1134 if (cr3 != kvm_read_cr3(vcpu)) 1135 kvm_mmu_new_pgd(vcpu, cr3); 1136 1137 vcpu->arch.cr3 = cr3; 1138 kvm_register_mark_available(vcpu, VCPU_EXREG_CR3); 1139 1140 handle_tlb_flush: 1141 /* 1142 * A load of CR3 that flushes the TLB flushes only the current PCID, 1143 * even if PCID is disabled, in which case PCID=0 is flushed. It's a 1144 * moot point in the end because _disabling_ PCID will flush all PCIDs, 1145 * and it's impossible to use a non-zero PCID when PCID is disabled, 1146 * i.e. only PCID=0 can be relevant. 1147 */ 1148 if (!skip_tlb_flush) 1149 kvm_invalidate_pcid(vcpu, pcid); 1150 1151 return 0; 1152 } 1153 EXPORT_SYMBOL_GPL(kvm_set_cr3); 1154 1155 int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8) 1156 { 1157 if (cr8 & CR8_RESERVED_BITS) 1158 return 1; 1159 if (lapic_in_kernel(vcpu)) 1160 kvm_lapic_set_tpr(vcpu, cr8); 1161 else 1162 vcpu->arch.cr8 = cr8; 1163 return 0; 1164 } 1165 EXPORT_SYMBOL_GPL(kvm_set_cr8); 1166 1167 unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu) 1168 { 1169 if (lapic_in_kernel(vcpu)) 1170 return kvm_lapic_get_cr8(vcpu); 1171 else 1172 return vcpu->arch.cr8; 1173 } 1174 EXPORT_SYMBOL_GPL(kvm_get_cr8); 1175 1176 static void kvm_update_dr0123(struct kvm_vcpu *vcpu) 1177 { 1178 int i; 1179 1180 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) { 1181 for (i = 0; i < KVM_NR_DB_REGS; i++) 1182 vcpu->arch.eff_db[i] = vcpu->arch.db[i]; 1183 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_RELOAD; 1184 } 1185 } 1186 1187 void kvm_update_dr7(struct kvm_vcpu *vcpu) 1188 { 1189 unsigned long dr7; 1190 1191 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) 1192 dr7 = vcpu->arch.guest_debug_dr7; 1193 else 1194 dr7 = vcpu->arch.dr7; 1195 static_call(kvm_x86_set_dr7)(vcpu, dr7); 1196 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED; 1197 if (dr7 & DR7_BP_EN_MASK) 1198 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED; 1199 } 1200 EXPORT_SYMBOL_GPL(kvm_update_dr7); 1201 1202 static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu) 1203 { 1204 u64 fixed = DR6_FIXED_1; 1205 1206 if (!guest_cpuid_has(vcpu, X86_FEATURE_RTM)) 1207 fixed |= DR6_RTM; 1208 1209 if (!guest_cpuid_has(vcpu, X86_FEATURE_BUS_LOCK_DETECT)) 1210 fixed |= DR6_BUS_LOCK; 1211 return fixed; 1212 } 1213 1214 int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val) 1215 { 1216 size_t size = ARRAY_SIZE(vcpu->arch.db); 1217 1218 switch (dr) { 1219 case 0 ... 3: 1220 vcpu->arch.db[array_index_nospec(dr, size)] = val; 1221 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) 1222 vcpu->arch.eff_db[dr] = val; 1223 break; 1224 case 4: 1225 case 6: 1226 if (!kvm_dr6_valid(val)) 1227 return 1; /* #GP */ 1228 vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu); 1229 break; 1230 case 5: 1231 default: /* 7 */ 1232 if (!kvm_dr7_valid(val)) 1233 return 1; /* #GP */ 1234 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1; 1235 kvm_update_dr7(vcpu); 1236 break; 1237 } 1238 1239 return 0; 1240 } 1241 EXPORT_SYMBOL_GPL(kvm_set_dr); 1242 1243 void kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val) 1244 { 1245 size_t size = ARRAY_SIZE(vcpu->arch.db); 1246 1247 switch (dr) { 1248 case 0 ... 3: 1249 *val = vcpu->arch.db[array_index_nospec(dr, size)]; 1250 break; 1251 case 4: 1252 case 6: 1253 *val = vcpu->arch.dr6; 1254 break; 1255 case 5: 1256 default: /* 7 */ 1257 *val = vcpu->arch.dr7; 1258 break; 1259 } 1260 } 1261 EXPORT_SYMBOL_GPL(kvm_get_dr); 1262 1263 int kvm_emulate_rdpmc(struct kvm_vcpu *vcpu) 1264 { 1265 u32 ecx = kvm_rcx_read(vcpu); 1266 u64 data; 1267 1268 if (kvm_pmu_rdpmc(vcpu, ecx, &data)) { 1269 kvm_inject_gp(vcpu, 0); 1270 return 1; 1271 } 1272 1273 kvm_rax_write(vcpu, (u32)data); 1274 kvm_rdx_write(vcpu, data >> 32); 1275 return kvm_skip_emulated_instruction(vcpu); 1276 } 1277 EXPORT_SYMBOL_GPL(kvm_emulate_rdpmc); 1278 1279 /* 1280 * List of msr numbers which we expose to userspace through KVM_GET_MSRS 1281 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST. 1282 * 1283 * The three MSR lists(msrs_to_save, emulated_msrs, msr_based_features) 1284 * extract the supported MSRs from the related const lists. 1285 * msrs_to_save is selected from the msrs_to_save_all to reflect the 1286 * capabilities of the host cpu. This capabilities test skips MSRs that are 1287 * kvm-specific. Those are put in emulated_msrs_all; filtering of emulated_msrs 1288 * may depend on host virtualization features rather than host cpu features. 1289 */ 1290 1291 static const u32 msrs_to_save_all[] = { 1292 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP, 1293 MSR_STAR, 1294 #ifdef CONFIG_X86_64 1295 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR, 1296 #endif 1297 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA, 1298 MSR_IA32_FEAT_CTL, MSR_IA32_BNDCFGS, MSR_TSC_AUX, 1299 MSR_IA32_SPEC_CTRL, 1300 MSR_IA32_RTIT_CTL, MSR_IA32_RTIT_STATUS, MSR_IA32_RTIT_CR3_MATCH, 1301 MSR_IA32_RTIT_OUTPUT_BASE, MSR_IA32_RTIT_OUTPUT_MASK, 1302 MSR_IA32_RTIT_ADDR0_A, MSR_IA32_RTIT_ADDR0_B, 1303 MSR_IA32_RTIT_ADDR1_A, MSR_IA32_RTIT_ADDR1_B, 1304 MSR_IA32_RTIT_ADDR2_A, MSR_IA32_RTIT_ADDR2_B, 1305 MSR_IA32_RTIT_ADDR3_A, MSR_IA32_RTIT_ADDR3_B, 1306 MSR_IA32_UMWAIT_CONTROL, 1307 1308 MSR_ARCH_PERFMON_FIXED_CTR0, MSR_ARCH_PERFMON_FIXED_CTR1, 1309 MSR_ARCH_PERFMON_FIXED_CTR0 + 2, MSR_ARCH_PERFMON_FIXED_CTR0 + 3, 1310 MSR_CORE_PERF_FIXED_CTR_CTRL, MSR_CORE_PERF_GLOBAL_STATUS, 1311 MSR_CORE_PERF_GLOBAL_CTRL, MSR_CORE_PERF_GLOBAL_OVF_CTRL, 1312 MSR_ARCH_PERFMON_PERFCTR0, MSR_ARCH_PERFMON_PERFCTR1, 1313 MSR_ARCH_PERFMON_PERFCTR0 + 2, MSR_ARCH_PERFMON_PERFCTR0 + 3, 1314 MSR_ARCH_PERFMON_PERFCTR0 + 4, MSR_ARCH_PERFMON_PERFCTR0 + 5, 1315 MSR_ARCH_PERFMON_PERFCTR0 + 6, MSR_ARCH_PERFMON_PERFCTR0 + 7, 1316 MSR_ARCH_PERFMON_PERFCTR0 + 8, MSR_ARCH_PERFMON_PERFCTR0 + 9, 1317 MSR_ARCH_PERFMON_PERFCTR0 + 10, MSR_ARCH_PERFMON_PERFCTR0 + 11, 1318 MSR_ARCH_PERFMON_PERFCTR0 + 12, MSR_ARCH_PERFMON_PERFCTR0 + 13, 1319 MSR_ARCH_PERFMON_PERFCTR0 + 14, MSR_ARCH_PERFMON_PERFCTR0 + 15, 1320 MSR_ARCH_PERFMON_PERFCTR0 + 16, MSR_ARCH_PERFMON_PERFCTR0 + 17, 1321 MSR_ARCH_PERFMON_EVENTSEL0, MSR_ARCH_PERFMON_EVENTSEL1, 1322 MSR_ARCH_PERFMON_EVENTSEL0 + 2, MSR_ARCH_PERFMON_EVENTSEL0 + 3, 1323 MSR_ARCH_PERFMON_EVENTSEL0 + 4, MSR_ARCH_PERFMON_EVENTSEL0 + 5, 1324 MSR_ARCH_PERFMON_EVENTSEL0 + 6, MSR_ARCH_PERFMON_EVENTSEL0 + 7, 1325 MSR_ARCH_PERFMON_EVENTSEL0 + 8, MSR_ARCH_PERFMON_EVENTSEL0 + 9, 1326 MSR_ARCH_PERFMON_EVENTSEL0 + 10, MSR_ARCH_PERFMON_EVENTSEL0 + 11, 1327 MSR_ARCH_PERFMON_EVENTSEL0 + 12, MSR_ARCH_PERFMON_EVENTSEL0 + 13, 1328 MSR_ARCH_PERFMON_EVENTSEL0 + 14, MSR_ARCH_PERFMON_EVENTSEL0 + 15, 1329 MSR_ARCH_PERFMON_EVENTSEL0 + 16, MSR_ARCH_PERFMON_EVENTSEL0 + 17, 1330 }; 1331 1332 static u32 msrs_to_save[ARRAY_SIZE(msrs_to_save_all)]; 1333 static unsigned num_msrs_to_save; 1334 1335 static const u32 emulated_msrs_all[] = { 1336 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK, 1337 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW, 1338 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL, 1339 HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC, 1340 HV_X64_MSR_TSC_FREQUENCY, HV_X64_MSR_APIC_FREQUENCY, 1341 HV_X64_MSR_CRASH_P0, HV_X64_MSR_CRASH_P1, HV_X64_MSR_CRASH_P2, 1342 HV_X64_MSR_CRASH_P3, HV_X64_MSR_CRASH_P4, HV_X64_MSR_CRASH_CTL, 1343 HV_X64_MSR_RESET, 1344 HV_X64_MSR_VP_INDEX, 1345 HV_X64_MSR_VP_RUNTIME, 1346 HV_X64_MSR_SCONTROL, 1347 HV_X64_MSR_STIMER0_CONFIG, 1348 HV_X64_MSR_VP_ASSIST_PAGE, 1349 HV_X64_MSR_REENLIGHTENMENT_CONTROL, HV_X64_MSR_TSC_EMULATION_CONTROL, 1350 HV_X64_MSR_TSC_EMULATION_STATUS, 1351 HV_X64_MSR_SYNDBG_OPTIONS, 1352 HV_X64_MSR_SYNDBG_CONTROL, HV_X64_MSR_SYNDBG_STATUS, 1353 HV_X64_MSR_SYNDBG_SEND_BUFFER, HV_X64_MSR_SYNDBG_RECV_BUFFER, 1354 HV_X64_MSR_SYNDBG_PENDING_BUFFER, 1355 1356 MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME, 1357 MSR_KVM_PV_EOI_EN, MSR_KVM_ASYNC_PF_INT, MSR_KVM_ASYNC_PF_ACK, 1358 1359 MSR_IA32_TSC_ADJUST, 1360 MSR_IA32_TSC_DEADLINE, 1361 MSR_IA32_ARCH_CAPABILITIES, 1362 MSR_IA32_PERF_CAPABILITIES, 1363 MSR_IA32_MISC_ENABLE, 1364 MSR_IA32_MCG_STATUS, 1365 MSR_IA32_MCG_CTL, 1366 MSR_IA32_MCG_EXT_CTL, 1367 MSR_IA32_SMBASE, 1368 MSR_SMI_COUNT, 1369 MSR_PLATFORM_INFO, 1370 MSR_MISC_FEATURES_ENABLES, 1371 MSR_AMD64_VIRT_SPEC_CTRL, 1372 MSR_IA32_POWER_CTL, 1373 MSR_IA32_UCODE_REV, 1374 1375 /* 1376 * The following list leaves out MSRs whose values are determined 1377 * by arch/x86/kvm/vmx/nested.c based on CPUID or other MSRs. 1378 * We always support the "true" VMX control MSRs, even if the host 1379 * processor does not, so I am putting these registers here rather 1380 * than in msrs_to_save_all. 1381 */ 1382 MSR_IA32_VMX_BASIC, 1383 MSR_IA32_VMX_TRUE_PINBASED_CTLS, 1384 MSR_IA32_VMX_TRUE_PROCBASED_CTLS, 1385 MSR_IA32_VMX_TRUE_EXIT_CTLS, 1386 MSR_IA32_VMX_TRUE_ENTRY_CTLS, 1387 MSR_IA32_VMX_MISC, 1388 MSR_IA32_VMX_CR0_FIXED0, 1389 MSR_IA32_VMX_CR4_FIXED0, 1390 MSR_IA32_VMX_VMCS_ENUM, 1391 MSR_IA32_VMX_PROCBASED_CTLS2, 1392 MSR_IA32_VMX_EPT_VPID_CAP, 1393 MSR_IA32_VMX_VMFUNC, 1394 1395 MSR_K7_HWCR, 1396 MSR_KVM_POLL_CONTROL, 1397 }; 1398 1399 static u32 emulated_msrs[ARRAY_SIZE(emulated_msrs_all)]; 1400 static unsigned num_emulated_msrs; 1401 1402 /* 1403 * List of msr numbers which are used to expose MSR-based features that 1404 * can be used by a hypervisor to validate requested CPU features. 1405 */ 1406 static const u32 msr_based_features_all[] = { 1407 MSR_IA32_VMX_BASIC, 1408 MSR_IA32_VMX_TRUE_PINBASED_CTLS, 1409 MSR_IA32_VMX_PINBASED_CTLS, 1410 MSR_IA32_VMX_TRUE_PROCBASED_CTLS, 1411 MSR_IA32_VMX_PROCBASED_CTLS, 1412 MSR_IA32_VMX_TRUE_EXIT_CTLS, 1413 MSR_IA32_VMX_EXIT_CTLS, 1414 MSR_IA32_VMX_TRUE_ENTRY_CTLS, 1415 MSR_IA32_VMX_ENTRY_CTLS, 1416 MSR_IA32_VMX_MISC, 1417 MSR_IA32_VMX_CR0_FIXED0, 1418 MSR_IA32_VMX_CR0_FIXED1, 1419 MSR_IA32_VMX_CR4_FIXED0, 1420 MSR_IA32_VMX_CR4_FIXED1, 1421 MSR_IA32_VMX_VMCS_ENUM, 1422 MSR_IA32_VMX_PROCBASED_CTLS2, 1423 MSR_IA32_VMX_EPT_VPID_CAP, 1424 MSR_IA32_VMX_VMFUNC, 1425 1426 MSR_F10H_DECFG, 1427 MSR_IA32_UCODE_REV, 1428 MSR_IA32_ARCH_CAPABILITIES, 1429 MSR_IA32_PERF_CAPABILITIES, 1430 }; 1431 1432 static u32 msr_based_features[ARRAY_SIZE(msr_based_features_all)]; 1433 static unsigned int num_msr_based_features; 1434 1435 static u64 kvm_get_arch_capabilities(void) 1436 { 1437 u64 data = 0; 1438 1439 if (boot_cpu_has(X86_FEATURE_ARCH_CAPABILITIES)) 1440 rdmsrl(MSR_IA32_ARCH_CAPABILITIES, data); 1441 1442 /* 1443 * If nx_huge_pages is enabled, KVM's shadow paging will ensure that 1444 * the nested hypervisor runs with NX huge pages. If it is not, 1445 * L1 is anyway vulnerable to ITLB_MULTIHIT exploits from other 1446 * L1 guests, so it need not worry about its own (L2) guests. 1447 */ 1448 data |= ARCH_CAP_PSCHANGE_MC_NO; 1449 1450 /* 1451 * If we're doing cache flushes (either "always" or "cond") 1452 * we will do one whenever the guest does a vmlaunch/vmresume. 1453 * If an outer hypervisor is doing the cache flush for us 1454 * (VMENTER_L1D_FLUSH_NESTED_VM), we can safely pass that 1455 * capability to the guest too, and if EPT is disabled we're not 1456 * vulnerable. Overall, only VMENTER_L1D_FLUSH_NEVER will 1457 * require a nested hypervisor to do a flush of its own. 1458 */ 1459 if (l1tf_vmx_mitigation != VMENTER_L1D_FLUSH_NEVER) 1460 data |= ARCH_CAP_SKIP_VMENTRY_L1DFLUSH; 1461 1462 if (!boot_cpu_has_bug(X86_BUG_CPU_MELTDOWN)) 1463 data |= ARCH_CAP_RDCL_NO; 1464 if (!boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS)) 1465 data |= ARCH_CAP_SSB_NO; 1466 if (!boot_cpu_has_bug(X86_BUG_MDS)) 1467 data |= ARCH_CAP_MDS_NO; 1468 1469 if (!boot_cpu_has(X86_FEATURE_RTM)) { 1470 /* 1471 * If RTM=0 because the kernel has disabled TSX, the host might 1472 * have TAA_NO or TSX_CTRL. Clear TAA_NO (the guest sees RTM=0 1473 * and therefore knows that there cannot be TAA) but keep 1474 * TSX_CTRL: some buggy userspaces leave it set on tsx=on hosts, 1475 * and we want to allow migrating those guests to tsx=off hosts. 1476 */ 1477 data &= ~ARCH_CAP_TAA_NO; 1478 } else if (!boot_cpu_has_bug(X86_BUG_TAA)) { 1479 data |= ARCH_CAP_TAA_NO; 1480 } else { 1481 /* 1482 * Nothing to do here; we emulate TSX_CTRL if present on the 1483 * host so the guest can choose between disabling TSX or 1484 * using VERW to clear CPU buffers. 1485 */ 1486 } 1487 1488 return data; 1489 } 1490 1491 static int kvm_get_msr_feature(struct kvm_msr_entry *msr) 1492 { 1493 switch (msr->index) { 1494 case MSR_IA32_ARCH_CAPABILITIES: 1495 msr->data = kvm_get_arch_capabilities(); 1496 break; 1497 case MSR_IA32_UCODE_REV: 1498 rdmsrl_safe(msr->index, &msr->data); 1499 break; 1500 default: 1501 return static_call(kvm_x86_get_msr_feature)(msr); 1502 } 1503 return 0; 1504 } 1505 1506 static int do_get_msr_feature(struct kvm_vcpu *vcpu, unsigned index, u64 *data) 1507 { 1508 struct kvm_msr_entry msr; 1509 int r; 1510 1511 msr.index = index; 1512 r = kvm_get_msr_feature(&msr); 1513 1514 if (r == KVM_MSR_RET_INVALID) { 1515 /* Unconditionally clear the output for simplicity */ 1516 *data = 0; 1517 if (kvm_msr_ignored_check(index, 0, false)) 1518 r = 0; 1519 } 1520 1521 if (r) 1522 return r; 1523 1524 *data = msr.data; 1525 1526 return 0; 1527 } 1528 1529 static bool __kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer) 1530 { 1531 if (efer & EFER_FFXSR && !guest_cpuid_has(vcpu, X86_FEATURE_FXSR_OPT)) 1532 return false; 1533 1534 if (efer & EFER_SVME && !guest_cpuid_has(vcpu, X86_FEATURE_SVM)) 1535 return false; 1536 1537 if (efer & (EFER_LME | EFER_LMA) && 1538 !guest_cpuid_has(vcpu, X86_FEATURE_LM)) 1539 return false; 1540 1541 if (efer & EFER_NX && !guest_cpuid_has(vcpu, X86_FEATURE_NX)) 1542 return false; 1543 1544 return true; 1545 1546 } 1547 bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer) 1548 { 1549 if (efer & efer_reserved_bits) 1550 return false; 1551 1552 return __kvm_valid_efer(vcpu, efer); 1553 } 1554 EXPORT_SYMBOL_GPL(kvm_valid_efer); 1555 1556 static int set_efer(struct kvm_vcpu *vcpu, struct msr_data *msr_info) 1557 { 1558 u64 old_efer = vcpu->arch.efer; 1559 u64 efer = msr_info->data; 1560 int r; 1561 1562 if (efer & efer_reserved_bits) 1563 return 1; 1564 1565 if (!msr_info->host_initiated) { 1566 if (!__kvm_valid_efer(vcpu, efer)) 1567 return 1; 1568 1569 if (is_paging(vcpu) && 1570 (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME)) 1571 return 1; 1572 } 1573 1574 efer &= ~EFER_LMA; 1575 efer |= vcpu->arch.efer & EFER_LMA; 1576 1577 r = static_call(kvm_x86_set_efer)(vcpu, efer); 1578 if (r) { 1579 WARN_ON(r > 0); 1580 return r; 1581 } 1582 1583 /* Update reserved bits */ 1584 if ((efer ^ old_efer) & EFER_NX) 1585 kvm_mmu_reset_context(vcpu); 1586 1587 return 0; 1588 } 1589 1590 void kvm_enable_efer_bits(u64 mask) 1591 { 1592 efer_reserved_bits &= ~mask; 1593 } 1594 EXPORT_SYMBOL_GPL(kvm_enable_efer_bits); 1595 1596 bool kvm_msr_allowed(struct kvm_vcpu *vcpu, u32 index, u32 type) 1597 { 1598 struct kvm_x86_msr_filter *msr_filter; 1599 struct msr_bitmap_range *ranges; 1600 struct kvm *kvm = vcpu->kvm; 1601 bool allowed; 1602 int idx; 1603 u32 i; 1604 1605 /* x2APIC MSRs do not support filtering. */ 1606 if (index >= 0x800 && index <= 0x8ff) 1607 return true; 1608 1609 idx = srcu_read_lock(&kvm->srcu); 1610 1611 msr_filter = srcu_dereference(kvm->arch.msr_filter, &kvm->srcu); 1612 if (!msr_filter) { 1613 allowed = true; 1614 goto out; 1615 } 1616 1617 allowed = msr_filter->default_allow; 1618 ranges = msr_filter->ranges; 1619 1620 for (i = 0; i < msr_filter->count; i++) { 1621 u32 start = ranges[i].base; 1622 u32 end = start + ranges[i].nmsrs; 1623 u32 flags = ranges[i].flags; 1624 unsigned long *bitmap = ranges[i].bitmap; 1625 1626 if ((index >= start) && (index < end) && (flags & type)) { 1627 allowed = !!test_bit(index - start, bitmap); 1628 break; 1629 } 1630 } 1631 1632 out: 1633 srcu_read_unlock(&kvm->srcu, idx); 1634 1635 return allowed; 1636 } 1637 EXPORT_SYMBOL_GPL(kvm_msr_allowed); 1638 1639 /* 1640 * Write @data into the MSR specified by @index. Select MSR specific fault 1641 * checks are bypassed if @host_initiated is %true. 1642 * Returns 0 on success, non-0 otherwise. 1643 * Assumes vcpu_load() was already called. 1644 */ 1645 static int __kvm_set_msr(struct kvm_vcpu *vcpu, u32 index, u64 data, 1646 bool host_initiated) 1647 { 1648 struct msr_data msr; 1649 1650 if (!host_initiated && !kvm_msr_allowed(vcpu, index, KVM_MSR_FILTER_WRITE)) 1651 return KVM_MSR_RET_FILTERED; 1652 1653 switch (index) { 1654 case MSR_FS_BASE: 1655 case MSR_GS_BASE: 1656 case MSR_KERNEL_GS_BASE: 1657 case MSR_CSTAR: 1658 case MSR_LSTAR: 1659 if (is_noncanonical_address(data, vcpu)) 1660 return 1; 1661 break; 1662 case MSR_IA32_SYSENTER_EIP: 1663 case MSR_IA32_SYSENTER_ESP: 1664 /* 1665 * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if 1666 * non-canonical address is written on Intel but not on 1667 * AMD (which ignores the top 32-bits, because it does 1668 * not implement 64-bit SYSENTER). 1669 * 1670 * 64-bit code should hence be able to write a non-canonical 1671 * value on AMD. Making the address canonical ensures that 1672 * vmentry does not fail on Intel after writing a non-canonical 1673 * value, and that something deterministic happens if the guest 1674 * invokes 64-bit SYSENTER. 1675 */ 1676 data = get_canonical(data, vcpu_virt_addr_bits(vcpu)); 1677 break; 1678 case MSR_TSC_AUX: 1679 if (!kvm_is_supported_user_return_msr(MSR_TSC_AUX)) 1680 return 1; 1681 1682 if (!host_initiated && 1683 !guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP) && 1684 !guest_cpuid_has(vcpu, X86_FEATURE_RDPID)) 1685 return 1; 1686 1687 /* 1688 * Per Intel's SDM, bits 63:32 are reserved, but AMD's APM has 1689 * incomplete and conflicting architectural behavior. Current 1690 * AMD CPUs completely ignore bits 63:32, i.e. they aren't 1691 * reserved and always read as zeros. Enforce Intel's reserved 1692 * bits check if and only if the guest CPU is Intel, and clear 1693 * the bits in all other cases. This ensures cross-vendor 1694 * migration will provide consistent behavior for the guest. 1695 */ 1696 if (guest_cpuid_is_intel(vcpu) && (data >> 32) != 0) 1697 return 1; 1698 1699 data = (u32)data; 1700 break; 1701 } 1702 1703 msr.data = data; 1704 msr.index = index; 1705 msr.host_initiated = host_initiated; 1706 1707 return static_call(kvm_x86_set_msr)(vcpu, &msr); 1708 } 1709 1710 static int kvm_set_msr_ignored_check(struct kvm_vcpu *vcpu, 1711 u32 index, u64 data, bool host_initiated) 1712 { 1713 int ret = __kvm_set_msr(vcpu, index, data, host_initiated); 1714 1715 if (ret == KVM_MSR_RET_INVALID) 1716 if (kvm_msr_ignored_check(index, data, true)) 1717 ret = 0; 1718 1719 return ret; 1720 } 1721 1722 /* 1723 * Read the MSR specified by @index into @data. Select MSR specific fault 1724 * checks are bypassed if @host_initiated is %true. 1725 * Returns 0 on success, non-0 otherwise. 1726 * Assumes vcpu_load() was already called. 1727 */ 1728 int __kvm_get_msr(struct kvm_vcpu *vcpu, u32 index, u64 *data, 1729 bool host_initiated) 1730 { 1731 struct msr_data msr; 1732 int ret; 1733 1734 if (!host_initiated && !kvm_msr_allowed(vcpu, index, KVM_MSR_FILTER_READ)) 1735 return KVM_MSR_RET_FILTERED; 1736 1737 switch (index) { 1738 case MSR_TSC_AUX: 1739 if (!kvm_is_supported_user_return_msr(MSR_TSC_AUX)) 1740 return 1; 1741 1742 if (!host_initiated && 1743 !guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP) && 1744 !guest_cpuid_has(vcpu, X86_FEATURE_RDPID)) 1745 return 1; 1746 break; 1747 } 1748 1749 msr.index = index; 1750 msr.host_initiated = host_initiated; 1751 1752 ret = static_call(kvm_x86_get_msr)(vcpu, &msr); 1753 if (!ret) 1754 *data = msr.data; 1755 return ret; 1756 } 1757 1758 static int kvm_get_msr_ignored_check(struct kvm_vcpu *vcpu, 1759 u32 index, u64 *data, bool host_initiated) 1760 { 1761 int ret = __kvm_get_msr(vcpu, index, data, host_initiated); 1762 1763 if (ret == KVM_MSR_RET_INVALID) { 1764 /* Unconditionally clear *data for simplicity */ 1765 *data = 0; 1766 if (kvm_msr_ignored_check(index, 0, false)) 1767 ret = 0; 1768 } 1769 1770 return ret; 1771 } 1772 1773 int kvm_get_msr(struct kvm_vcpu *vcpu, u32 index, u64 *data) 1774 { 1775 return kvm_get_msr_ignored_check(vcpu, index, data, false); 1776 } 1777 EXPORT_SYMBOL_GPL(kvm_get_msr); 1778 1779 int kvm_set_msr(struct kvm_vcpu *vcpu, u32 index, u64 data) 1780 { 1781 return kvm_set_msr_ignored_check(vcpu, index, data, false); 1782 } 1783 EXPORT_SYMBOL_GPL(kvm_set_msr); 1784 1785 static int complete_emulated_rdmsr(struct kvm_vcpu *vcpu) 1786 { 1787 int err = vcpu->run->msr.error; 1788 if (!err) { 1789 kvm_rax_write(vcpu, (u32)vcpu->run->msr.data); 1790 kvm_rdx_write(vcpu, vcpu->run->msr.data >> 32); 1791 } 1792 1793 return static_call(kvm_x86_complete_emulated_msr)(vcpu, err); 1794 } 1795 1796 static int complete_emulated_wrmsr(struct kvm_vcpu *vcpu) 1797 { 1798 return static_call(kvm_x86_complete_emulated_msr)(vcpu, vcpu->run->msr.error); 1799 } 1800 1801 static u64 kvm_msr_reason(int r) 1802 { 1803 switch (r) { 1804 case KVM_MSR_RET_INVALID: 1805 return KVM_MSR_EXIT_REASON_UNKNOWN; 1806 case KVM_MSR_RET_FILTERED: 1807 return KVM_MSR_EXIT_REASON_FILTER; 1808 default: 1809 return KVM_MSR_EXIT_REASON_INVAL; 1810 } 1811 } 1812 1813 static int kvm_msr_user_space(struct kvm_vcpu *vcpu, u32 index, 1814 u32 exit_reason, u64 data, 1815 int (*completion)(struct kvm_vcpu *vcpu), 1816 int r) 1817 { 1818 u64 msr_reason = kvm_msr_reason(r); 1819 1820 /* Check if the user wanted to know about this MSR fault */ 1821 if (!(vcpu->kvm->arch.user_space_msr_mask & msr_reason)) 1822 return 0; 1823 1824 vcpu->run->exit_reason = exit_reason; 1825 vcpu->run->msr.error = 0; 1826 memset(vcpu->run->msr.pad, 0, sizeof(vcpu->run->msr.pad)); 1827 vcpu->run->msr.reason = msr_reason; 1828 vcpu->run->msr.index = index; 1829 vcpu->run->msr.data = data; 1830 vcpu->arch.complete_userspace_io = completion; 1831 1832 return 1; 1833 } 1834 1835 static int kvm_get_msr_user_space(struct kvm_vcpu *vcpu, u32 index, int r) 1836 { 1837 return kvm_msr_user_space(vcpu, index, KVM_EXIT_X86_RDMSR, 0, 1838 complete_emulated_rdmsr, r); 1839 } 1840 1841 static int kvm_set_msr_user_space(struct kvm_vcpu *vcpu, u32 index, u64 data, int r) 1842 { 1843 return kvm_msr_user_space(vcpu, index, KVM_EXIT_X86_WRMSR, data, 1844 complete_emulated_wrmsr, r); 1845 } 1846 1847 int kvm_emulate_rdmsr(struct kvm_vcpu *vcpu) 1848 { 1849 u32 ecx = kvm_rcx_read(vcpu); 1850 u64 data; 1851 int r; 1852 1853 r = kvm_get_msr(vcpu, ecx, &data); 1854 1855 /* MSR read failed? See if we should ask user space */ 1856 if (r && kvm_get_msr_user_space(vcpu, ecx, r)) { 1857 /* Bounce to user space */ 1858 return 0; 1859 } 1860 1861 if (!r) { 1862 trace_kvm_msr_read(ecx, data); 1863 1864 kvm_rax_write(vcpu, data & -1u); 1865 kvm_rdx_write(vcpu, (data >> 32) & -1u); 1866 } else { 1867 trace_kvm_msr_read_ex(ecx); 1868 } 1869 1870 return static_call(kvm_x86_complete_emulated_msr)(vcpu, r); 1871 } 1872 EXPORT_SYMBOL_GPL(kvm_emulate_rdmsr); 1873 1874 int kvm_emulate_wrmsr(struct kvm_vcpu *vcpu) 1875 { 1876 u32 ecx = kvm_rcx_read(vcpu); 1877 u64 data = kvm_read_edx_eax(vcpu); 1878 int r; 1879 1880 r = kvm_set_msr(vcpu, ecx, data); 1881 1882 /* MSR write failed? See if we should ask user space */ 1883 if (r && kvm_set_msr_user_space(vcpu, ecx, data, r)) 1884 /* Bounce to user space */ 1885 return 0; 1886 1887 /* Signal all other negative errors to userspace */ 1888 if (r < 0) 1889 return r; 1890 1891 if (!r) 1892 trace_kvm_msr_write(ecx, data); 1893 else 1894 trace_kvm_msr_write_ex(ecx, data); 1895 1896 return static_call(kvm_x86_complete_emulated_msr)(vcpu, r); 1897 } 1898 EXPORT_SYMBOL_GPL(kvm_emulate_wrmsr); 1899 1900 int kvm_emulate_as_nop(struct kvm_vcpu *vcpu) 1901 { 1902 return kvm_skip_emulated_instruction(vcpu); 1903 } 1904 EXPORT_SYMBOL_GPL(kvm_emulate_as_nop); 1905 1906 int kvm_emulate_invd(struct kvm_vcpu *vcpu) 1907 { 1908 /* Treat an INVD instruction as a NOP and just skip it. */ 1909 return kvm_emulate_as_nop(vcpu); 1910 } 1911 EXPORT_SYMBOL_GPL(kvm_emulate_invd); 1912 1913 int kvm_emulate_mwait(struct kvm_vcpu *vcpu) 1914 { 1915 pr_warn_once("kvm: MWAIT instruction emulated as NOP!\n"); 1916 return kvm_emulate_as_nop(vcpu); 1917 } 1918 EXPORT_SYMBOL_GPL(kvm_emulate_mwait); 1919 1920 int kvm_handle_invalid_op(struct kvm_vcpu *vcpu) 1921 { 1922 kvm_queue_exception(vcpu, UD_VECTOR); 1923 return 1; 1924 } 1925 EXPORT_SYMBOL_GPL(kvm_handle_invalid_op); 1926 1927 int kvm_emulate_monitor(struct kvm_vcpu *vcpu) 1928 { 1929 pr_warn_once("kvm: MONITOR instruction emulated as NOP!\n"); 1930 return kvm_emulate_as_nop(vcpu); 1931 } 1932 EXPORT_SYMBOL_GPL(kvm_emulate_monitor); 1933 1934 static inline bool kvm_vcpu_exit_request(struct kvm_vcpu *vcpu) 1935 { 1936 xfer_to_guest_mode_prepare(); 1937 return vcpu->mode == EXITING_GUEST_MODE || kvm_request_pending(vcpu) || 1938 xfer_to_guest_mode_work_pending(); 1939 } 1940 1941 /* 1942 * The fast path for frequent and performance sensitive wrmsr emulation, 1943 * i.e. the sending of IPI, sending IPI early in the VM-Exit flow reduces 1944 * the latency of virtual IPI by avoiding the expensive bits of transitioning 1945 * from guest to host, e.g. reacquiring KVM's SRCU lock. In contrast to the 1946 * other cases which must be called after interrupts are enabled on the host. 1947 */ 1948 static int handle_fastpath_set_x2apic_icr_irqoff(struct kvm_vcpu *vcpu, u64 data) 1949 { 1950 if (!lapic_in_kernel(vcpu) || !apic_x2apic_mode(vcpu->arch.apic)) 1951 return 1; 1952 1953 if (((data & APIC_SHORT_MASK) == APIC_DEST_NOSHORT) && 1954 ((data & APIC_DEST_MASK) == APIC_DEST_PHYSICAL) && 1955 ((data & APIC_MODE_MASK) == APIC_DM_FIXED) && 1956 ((u32)(data >> 32) != X2APIC_BROADCAST)) { 1957 1958 data &= ~(1 << 12); 1959 kvm_apic_send_ipi(vcpu->arch.apic, (u32)data, (u32)(data >> 32)); 1960 kvm_lapic_set_reg(vcpu->arch.apic, APIC_ICR2, (u32)(data >> 32)); 1961 kvm_lapic_set_reg(vcpu->arch.apic, APIC_ICR, (u32)data); 1962 trace_kvm_apic_write(APIC_ICR, (u32)data); 1963 return 0; 1964 } 1965 1966 return 1; 1967 } 1968 1969 static int handle_fastpath_set_tscdeadline(struct kvm_vcpu *vcpu, u64 data) 1970 { 1971 if (!kvm_can_use_hv_timer(vcpu)) 1972 return 1; 1973 1974 kvm_set_lapic_tscdeadline_msr(vcpu, data); 1975 return 0; 1976 } 1977 1978 fastpath_t handle_fastpath_set_msr_irqoff(struct kvm_vcpu *vcpu) 1979 { 1980 u32 msr = kvm_rcx_read(vcpu); 1981 u64 data; 1982 fastpath_t ret = EXIT_FASTPATH_NONE; 1983 1984 switch (msr) { 1985 case APIC_BASE_MSR + (APIC_ICR >> 4): 1986 data = kvm_read_edx_eax(vcpu); 1987 if (!handle_fastpath_set_x2apic_icr_irqoff(vcpu, data)) { 1988 kvm_skip_emulated_instruction(vcpu); 1989 ret = EXIT_FASTPATH_EXIT_HANDLED; 1990 } 1991 break; 1992 case MSR_IA32_TSC_DEADLINE: 1993 data = kvm_read_edx_eax(vcpu); 1994 if (!handle_fastpath_set_tscdeadline(vcpu, data)) { 1995 kvm_skip_emulated_instruction(vcpu); 1996 ret = EXIT_FASTPATH_REENTER_GUEST; 1997 } 1998 break; 1999 default: 2000 break; 2001 } 2002 2003 if (ret != EXIT_FASTPATH_NONE) 2004 trace_kvm_msr_write(msr, data); 2005 2006 return ret; 2007 } 2008 EXPORT_SYMBOL_GPL(handle_fastpath_set_msr_irqoff); 2009 2010 /* 2011 * Adapt set_msr() to msr_io()'s calling convention 2012 */ 2013 static int do_get_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data) 2014 { 2015 return kvm_get_msr_ignored_check(vcpu, index, data, true); 2016 } 2017 2018 static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data) 2019 { 2020 return kvm_set_msr_ignored_check(vcpu, index, *data, true); 2021 } 2022 2023 #ifdef CONFIG_X86_64 2024 struct pvclock_clock { 2025 int vclock_mode; 2026 u64 cycle_last; 2027 u64 mask; 2028 u32 mult; 2029 u32 shift; 2030 u64 base_cycles; 2031 u64 offset; 2032 }; 2033 2034 struct pvclock_gtod_data { 2035 seqcount_t seq; 2036 2037 struct pvclock_clock clock; /* extract of a clocksource struct */ 2038 struct pvclock_clock raw_clock; /* extract of a clocksource struct */ 2039 2040 ktime_t offs_boot; 2041 u64 wall_time_sec; 2042 }; 2043 2044 static struct pvclock_gtod_data pvclock_gtod_data; 2045 2046 static void update_pvclock_gtod(struct timekeeper *tk) 2047 { 2048 struct pvclock_gtod_data *vdata = &pvclock_gtod_data; 2049 2050 write_seqcount_begin(&vdata->seq); 2051 2052 /* copy pvclock gtod data */ 2053 vdata->clock.vclock_mode = tk->tkr_mono.clock->vdso_clock_mode; 2054 vdata->clock.cycle_last = tk->tkr_mono.cycle_last; 2055 vdata->clock.mask = tk->tkr_mono.mask; 2056 vdata->clock.mult = tk->tkr_mono.mult; 2057 vdata->clock.shift = tk->tkr_mono.shift; 2058 vdata->clock.base_cycles = tk->tkr_mono.xtime_nsec; 2059 vdata->clock.offset = tk->tkr_mono.base; 2060 2061 vdata->raw_clock.vclock_mode = tk->tkr_raw.clock->vdso_clock_mode; 2062 vdata->raw_clock.cycle_last = tk->tkr_raw.cycle_last; 2063 vdata->raw_clock.mask = tk->tkr_raw.mask; 2064 vdata->raw_clock.mult = tk->tkr_raw.mult; 2065 vdata->raw_clock.shift = tk->tkr_raw.shift; 2066 vdata->raw_clock.base_cycles = tk->tkr_raw.xtime_nsec; 2067 vdata->raw_clock.offset = tk->tkr_raw.base; 2068 2069 vdata->wall_time_sec = tk->xtime_sec; 2070 2071 vdata->offs_boot = tk->offs_boot; 2072 2073 write_seqcount_end(&vdata->seq); 2074 } 2075 2076 static s64 get_kvmclock_base_ns(void) 2077 { 2078 /* Count up from boot time, but with the frequency of the raw clock. */ 2079 return ktime_to_ns(ktime_add(ktime_get_raw(), pvclock_gtod_data.offs_boot)); 2080 } 2081 #else 2082 static s64 get_kvmclock_base_ns(void) 2083 { 2084 /* Master clock not used, so we can just use CLOCK_BOOTTIME. */ 2085 return ktime_get_boottime_ns(); 2086 } 2087 #endif 2088 2089 void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock, int sec_hi_ofs) 2090 { 2091 int version; 2092 int r; 2093 struct pvclock_wall_clock wc; 2094 u32 wc_sec_hi; 2095 u64 wall_nsec; 2096 2097 if (!wall_clock) 2098 return; 2099 2100 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version)); 2101 if (r) 2102 return; 2103 2104 if (version & 1) 2105 ++version; /* first time write, random junk */ 2106 2107 ++version; 2108 2109 if (kvm_write_guest(kvm, wall_clock, &version, sizeof(version))) 2110 return; 2111 2112 /* 2113 * The guest calculates current wall clock time by adding 2114 * system time (updated by kvm_guest_time_update below) to the 2115 * wall clock specified here. We do the reverse here. 2116 */ 2117 wall_nsec = ktime_get_real_ns() - get_kvmclock_ns(kvm); 2118 2119 wc.nsec = do_div(wall_nsec, 1000000000); 2120 wc.sec = (u32)wall_nsec; /* overflow in 2106 guest time */ 2121 wc.version = version; 2122 2123 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc)); 2124 2125 if (sec_hi_ofs) { 2126 wc_sec_hi = wall_nsec >> 32; 2127 kvm_write_guest(kvm, wall_clock + sec_hi_ofs, 2128 &wc_sec_hi, sizeof(wc_sec_hi)); 2129 } 2130 2131 version++; 2132 kvm_write_guest(kvm, wall_clock, &version, sizeof(version)); 2133 } 2134 2135 static void kvm_write_system_time(struct kvm_vcpu *vcpu, gpa_t system_time, 2136 bool old_msr, bool host_initiated) 2137 { 2138 struct kvm_arch *ka = &vcpu->kvm->arch; 2139 2140 if (vcpu->vcpu_id == 0 && !host_initiated) { 2141 if (ka->boot_vcpu_runs_old_kvmclock != old_msr) 2142 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu); 2143 2144 ka->boot_vcpu_runs_old_kvmclock = old_msr; 2145 } 2146 2147 vcpu->arch.time = system_time; 2148 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu); 2149 2150 /* we verify if the enable bit is set... */ 2151 vcpu->arch.pv_time_enabled = false; 2152 if (!(system_time & 1)) 2153 return; 2154 2155 if (!kvm_gfn_to_hva_cache_init(vcpu->kvm, 2156 &vcpu->arch.pv_time, system_time & ~1ULL, 2157 sizeof(struct pvclock_vcpu_time_info))) 2158 vcpu->arch.pv_time_enabled = true; 2159 2160 return; 2161 } 2162 2163 static uint32_t div_frac(uint32_t dividend, uint32_t divisor) 2164 { 2165 do_shl32_div32(dividend, divisor); 2166 return dividend; 2167 } 2168 2169 static void kvm_get_time_scale(uint64_t scaled_hz, uint64_t base_hz, 2170 s8 *pshift, u32 *pmultiplier) 2171 { 2172 uint64_t scaled64; 2173 int32_t shift = 0; 2174 uint64_t tps64; 2175 uint32_t tps32; 2176 2177 tps64 = base_hz; 2178 scaled64 = scaled_hz; 2179 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) { 2180 tps64 >>= 1; 2181 shift--; 2182 } 2183 2184 tps32 = (uint32_t)tps64; 2185 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) { 2186 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000) 2187 scaled64 >>= 1; 2188 else 2189 tps32 <<= 1; 2190 shift++; 2191 } 2192 2193 *pshift = shift; 2194 *pmultiplier = div_frac(scaled64, tps32); 2195 } 2196 2197 #ifdef CONFIG_X86_64 2198 static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0); 2199 #endif 2200 2201 static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz); 2202 static unsigned long max_tsc_khz; 2203 2204 static u32 adjust_tsc_khz(u32 khz, s32 ppm) 2205 { 2206 u64 v = (u64)khz * (1000000 + ppm); 2207 do_div(v, 1000000); 2208 return v; 2209 } 2210 2211 static void kvm_vcpu_write_tsc_multiplier(struct kvm_vcpu *vcpu, u64 l1_multiplier); 2212 2213 static int set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale) 2214 { 2215 u64 ratio; 2216 2217 /* Guest TSC same frequency as host TSC? */ 2218 if (!scale) { 2219 kvm_vcpu_write_tsc_multiplier(vcpu, kvm_default_tsc_scaling_ratio); 2220 return 0; 2221 } 2222 2223 /* TSC scaling supported? */ 2224 if (!kvm_has_tsc_control) { 2225 if (user_tsc_khz > tsc_khz) { 2226 vcpu->arch.tsc_catchup = 1; 2227 vcpu->arch.tsc_always_catchup = 1; 2228 return 0; 2229 } else { 2230 pr_warn_ratelimited("user requested TSC rate below hardware speed\n"); 2231 return -1; 2232 } 2233 } 2234 2235 /* TSC scaling required - calculate ratio */ 2236 ratio = mul_u64_u32_div(1ULL << kvm_tsc_scaling_ratio_frac_bits, 2237 user_tsc_khz, tsc_khz); 2238 2239 if (ratio == 0 || ratio >= kvm_max_tsc_scaling_ratio) { 2240 pr_warn_ratelimited("Invalid TSC scaling ratio - virtual-tsc-khz=%u\n", 2241 user_tsc_khz); 2242 return -1; 2243 } 2244 2245 kvm_vcpu_write_tsc_multiplier(vcpu, ratio); 2246 return 0; 2247 } 2248 2249 static int kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz) 2250 { 2251 u32 thresh_lo, thresh_hi; 2252 int use_scaling = 0; 2253 2254 /* tsc_khz can be zero if TSC calibration fails */ 2255 if (user_tsc_khz == 0) { 2256 /* set tsc_scaling_ratio to a safe value */ 2257 kvm_vcpu_write_tsc_multiplier(vcpu, kvm_default_tsc_scaling_ratio); 2258 return -1; 2259 } 2260 2261 /* Compute a scale to convert nanoseconds in TSC cycles */ 2262 kvm_get_time_scale(user_tsc_khz * 1000LL, NSEC_PER_SEC, 2263 &vcpu->arch.virtual_tsc_shift, 2264 &vcpu->arch.virtual_tsc_mult); 2265 vcpu->arch.virtual_tsc_khz = user_tsc_khz; 2266 2267 /* 2268 * Compute the variation in TSC rate which is acceptable 2269 * within the range of tolerance and decide if the 2270 * rate being applied is within that bounds of the hardware 2271 * rate. If so, no scaling or compensation need be done. 2272 */ 2273 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm); 2274 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm); 2275 if (user_tsc_khz < thresh_lo || user_tsc_khz > thresh_hi) { 2276 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", user_tsc_khz, thresh_lo, thresh_hi); 2277 use_scaling = 1; 2278 } 2279 return set_tsc_khz(vcpu, user_tsc_khz, use_scaling); 2280 } 2281 2282 static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns) 2283 { 2284 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec, 2285 vcpu->arch.virtual_tsc_mult, 2286 vcpu->arch.virtual_tsc_shift); 2287 tsc += vcpu->arch.this_tsc_write; 2288 return tsc; 2289 } 2290 2291 static inline int gtod_is_based_on_tsc(int mode) 2292 { 2293 return mode == VDSO_CLOCKMODE_TSC || mode == VDSO_CLOCKMODE_HVCLOCK; 2294 } 2295 2296 static void kvm_track_tsc_matching(struct kvm_vcpu *vcpu) 2297 { 2298 #ifdef CONFIG_X86_64 2299 bool vcpus_matched; 2300 struct kvm_arch *ka = &vcpu->kvm->arch; 2301 struct pvclock_gtod_data *gtod = &pvclock_gtod_data; 2302 2303 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 == 2304 atomic_read(&vcpu->kvm->online_vcpus)); 2305 2306 /* 2307 * Once the masterclock is enabled, always perform request in 2308 * order to update it. 2309 * 2310 * In order to enable masterclock, the host clocksource must be TSC 2311 * and the vcpus need to have matched TSCs. When that happens, 2312 * perform request to enable masterclock. 2313 */ 2314 if (ka->use_master_clock || 2315 (gtod_is_based_on_tsc(gtod->clock.vclock_mode) && vcpus_matched)) 2316 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu); 2317 2318 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc, 2319 atomic_read(&vcpu->kvm->online_vcpus), 2320 ka->use_master_clock, gtod->clock.vclock_mode); 2321 #endif 2322 } 2323 2324 /* 2325 * Multiply tsc by a fixed point number represented by ratio. 2326 * 2327 * The most significant 64-N bits (mult) of ratio represent the 2328 * integral part of the fixed point number; the remaining N bits 2329 * (frac) represent the fractional part, ie. ratio represents a fixed 2330 * point number (mult + frac * 2^(-N)). 2331 * 2332 * N equals to kvm_tsc_scaling_ratio_frac_bits. 2333 */ 2334 static inline u64 __scale_tsc(u64 ratio, u64 tsc) 2335 { 2336 return mul_u64_u64_shr(tsc, ratio, kvm_tsc_scaling_ratio_frac_bits); 2337 } 2338 2339 u64 kvm_scale_tsc(struct kvm_vcpu *vcpu, u64 tsc, u64 ratio) 2340 { 2341 u64 _tsc = tsc; 2342 2343 if (ratio != kvm_default_tsc_scaling_ratio) 2344 _tsc = __scale_tsc(ratio, tsc); 2345 2346 return _tsc; 2347 } 2348 EXPORT_SYMBOL_GPL(kvm_scale_tsc); 2349 2350 static u64 kvm_compute_l1_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc) 2351 { 2352 u64 tsc; 2353 2354 tsc = kvm_scale_tsc(vcpu, rdtsc(), vcpu->arch.l1_tsc_scaling_ratio); 2355 2356 return target_tsc - tsc; 2357 } 2358 2359 u64 kvm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc) 2360 { 2361 return vcpu->arch.l1_tsc_offset + 2362 kvm_scale_tsc(vcpu, host_tsc, vcpu->arch.l1_tsc_scaling_ratio); 2363 } 2364 EXPORT_SYMBOL_GPL(kvm_read_l1_tsc); 2365 2366 u64 kvm_calc_nested_tsc_offset(u64 l1_offset, u64 l2_offset, u64 l2_multiplier) 2367 { 2368 u64 nested_offset; 2369 2370 if (l2_multiplier == kvm_default_tsc_scaling_ratio) 2371 nested_offset = l1_offset; 2372 else 2373 nested_offset = mul_s64_u64_shr((s64) l1_offset, l2_multiplier, 2374 kvm_tsc_scaling_ratio_frac_bits); 2375 2376 nested_offset += l2_offset; 2377 return nested_offset; 2378 } 2379 EXPORT_SYMBOL_GPL(kvm_calc_nested_tsc_offset); 2380 2381 u64 kvm_calc_nested_tsc_multiplier(u64 l1_multiplier, u64 l2_multiplier) 2382 { 2383 if (l2_multiplier != kvm_default_tsc_scaling_ratio) 2384 return mul_u64_u64_shr(l1_multiplier, l2_multiplier, 2385 kvm_tsc_scaling_ratio_frac_bits); 2386 2387 return l1_multiplier; 2388 } 2389 EXPORT_SYMBOL_GPL(kvm_calc_nested_tsc_multiplier); 2390 2391 static void kvm_vcpu_write_tsc_offset(struct kvm_vcpu *vcpu, u64 l1_offset) 2392 { 2393 trace_kvm_write_tsc_offset(vcpu->vcpu_id, 2394 vcpu->arch.l1_tsc_offset, 2395 l1_offset); 2396 2397 vcpu->arch.l1_tsc_offset = l1_offset; 2398 2399 /* 2400 * If we are here because L1 chose not to trap WRMSR to TSC then 2401 * according to the spec this should set L1's TSC (as opposed to 2402 * setting L1's offset for L2). 2403 */ 2404 if (is_guest_mode(vcpu)) 2405 vcpu->arch.tsc_offset = kvm_calc_nested_tsc_offset( 2406 l1_offset, 2407 static_call(kvm_x86_get_l2_tsc_offset)(vcpu), 2408 static_call(kvm_x86_get_l2_tsc_multiplier)(vcpu)); 2409 else 2410 vcpu->arch.tsc_offset = l1_offset; 2411 2412 static_call(kvm_x86_write_tsc_offset)(vcpu, vcpu->arch.tsc_offset); 2413 } 2414 2415 static void kvm_vcpu_write_tsc_multiplier(struct kvm_vcpu *vcpu, u64 l1_multiplier) 2416 { 2417 vcpu->arch.l1_tsc_scaling_ratio = l1_multiplier; 2418 2419 /* Userspace is changing the multiplier while L2 is active */ 2420 if (is_guest_mode(vcpu)) 2421 vcpu->arch.tsc_scaling_ratio = kvm_calc_nested_tsc_multiplier( 2422 l1_multiplier, 2423 static_call(kvm_x86_get_l2_tsc_multiplier)(vcpu)); 2424 else 2425 vcpu->arch.tsc_scaling_ratio = l1_multiplier; 2426 2427 if (kvm_has_tsc_control) 2428 static_call(kvm_x86_write_tsc_multiplier)( 2429 vcpu, vcpu->arch.tsc_scaling_ratio); 2430 } 2431 2432 static inline bool kvm_check_tsc_unstable(void) 2433 { 2434 #ifdef CONFIG_X86_64 2435 /* 2436 * TSC is marked unstable when we're running on Hyper-V, 2437 * 'TSC page' clocksource is good. 2438 */ 2439 if (pvclock_gtod_data.clock.vclock_mode == VDSO_CLOCKMODE_HVCLOCK) 2440 return false; 2441 #endif 2442 return check_tsc_unstable(); 2443 } 2444 2445 static void kvm_synchronize_tsc(struct kvm_vcpu *vcpu, u64 data) 2446 { 2447 struct kvm *kvm = vcpu->kvm; 2448 u64 offset, ns, elapsed; 2449 unsigned long flags; 2450 bool matched; 2451 bool already_matched; 2452 bool synchronizing = false; 2453 2454 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags); 2455 offset = kvm_compute_l1_tsc_offset(vcpu, data); 2456 ns = get_kvmclock_base_ns(); 2457 elapsed = ns - kvm->arch.last_tsc_nsec; 2458 2459 if (vcpu->arch.virtual_tsc_khz) { 2460 if (data == 0) { 2461 /* 2462 * detection of vcpu initialization -- need to sync 2463 * with other vCPUs. This particularly helps to keep 2464 * kvm_clock stable after CPU hotplug 2465 */ 2466 synchronizing = true; 2467 } else { 2468 u64 tsc_exp = kvm->arch.last_tsc_write + 2469 nsec_to_cycles(vcpu, elapsed); 2470 u64 tsc_hz = vcpu->arch.virtual_tsc_khz * 1000LL; 2471 /* 2472 * Special case: TSC write with a small delta (1 second) 2473 * of virtual cycle time against real time is 2474 * interpreted as an attempt to synchronize the CPU. 2475 */ 2476 synchronizing = data < tsc_exp + tsc_hz && 2477 data + tsc_hz > tsc_exp; 2478 } 2479 } 2480 2481 /* 2482 * For a reliable TSC, we can match TSC offsets, and for an unstable 2483 * TSC, we add elapsed time in this computation. We could let the 2484 * compensation code attempt to catch up if we fall behind, but 2485 * it's better to try to match offsets from the beginning. 2486 */ 2487 if (synchronizing && 2488 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) { 2489 if (!kvm_check_tsc_unstable()) { 2490 offset = kvm->arch.cur_tsc_offset; 2491 } else { 2492 u64 delta = nsec_to_cycles(vcpu, elapsed); 2493 data += delta; 2494 offset = kvm_compute_l1_tsc_offset(vcpu, data); 2495 } 2496 matched = true; 2497 already_matched = (vcpu->arch.this_tsc_generation == kvm->arch.cur_tsc_generation); 2498 } else { 2499 /* 2500 * We split periods of matched TSC writes into generations. 2501 * For each generation, we track the original measured 2502 * nanosecond time, offset, and write, so if TSCs are in 2503 * sync, we can match exact offset, and if not, we can match 2504 * exact software computation in compute_guest_tsc() 2505 * 2506 * These values are tracked in kvm->arch.cur_xxx variables. 2507 */ 2508 kvm->arch.cur_tsc_generation++; 2509 kvm->arch.cur_tsc_nsec = ns; 2510 kvm->arch.cur_tsc_write = data; 2511 kvm->arch.cur_tsc_offset = offset; 2512 matched = false; 2513 } 2514 2515 /* 2516 * We also track th most recent recorded KHZ, write and time to 2517 * allow the matching interval to be extended at each write. 2518 */ 2519 kvm->arch.last_tsc_nsec = ns; 2520 kvm->arch.last_tsc_write = data; 2521 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz; 2522 2523 vcpu->arch.last_guest_tsc = data; 2524 2525 /* Keep track of which generation this VCPU has synchronized to */ 2526 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation; 2527 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec; 2528 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write; 2529 2530 kvm_vcpu_write_tsc_offset(vcpu, offset); 2531 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags); 2532 2533 spin_lock_irqsave(&kvm->arch.pvclock_gtod_sync_lock, flags); 2534 if (!matched) { 2535 kvm->arch.nr_vcpus_matched_tsc = 0; 2536 } else if (!already_matched) { 2537 kvm->arch.nr_vcpus_matched_tsc++; 2538 } 2539 2540 kvm_track_tsc_matching(vcpu); 2541 spin_unlock_irqrestore(&kvm->arch.pvclock_gtod_sync_lock, flags); 2542 } 2543 2544 static inline void adjust_tsc_offset_guest(struct kvm_vcpu *vcpu, 2545 s64 adjustment) 2546 { 2547 u64 tsc_offset = vcpu->arch.l1_tsc_offset; 2548 kvm_vcpu_write_tsc_offset(vcpu, tsc_offset + adjustment); 2549 } 2550 2551 static inline void adjust_tsc_offset_host(struct kvm_vcpu *vcpu, s64 adjustment) 2552 { 2553 if (vcpu->arch.l1_tsc_scaling_ratio != kvm_default_tsc_scaling_ratio) 2554 WARN_ON(adjustment < 0); 2555 adjustment = kvm_scale_tsc(vcpu, (u64) adjustment, 2556 vcpu->arch.l1_tsc_scaling_ratio); 2557 adjust_tsc_offset_guest(vcpu, adjustment); 2558 } 2559 2560 #ifdef CONFIG_X86_64 2561 2562 static u64 read_tsc(void) 2563 { 2564 u64 ret = (u64)rdtsc_ordered(); 2565 u64 last = pvclock_gtod_data.clock.cycle_last; 2566 2567 if (likely(ret >= last)) 2568 return ret; 2569 2570 /* 2571 * GCC likes to generate cmov here, but this branch is extremely 2572 * predictable (it's just a function of time and the likely is 2573 * very likely) and there's a data dependence, so force GCC 2574 * to generate a branch instead. I don't barrier() because 2575 * we don't actually need a barrier, and if this function 2576 * ever gets inlined it will generate worse code. 2577 */ 2578 asm volatile (""); 2579 return last; 2580 } 2581 2582 static inline u64 vgettsc(struct pvclock_clock *clock, u64 *tsc_timestamp, 2583 int *mode) 2584 { 2585 long v; 2586 u64 tsc_pg_val; 2587 2588 switch (clock->vclock_mode) { 2589 case VDSO_CLOCKMODE_HVCLOCK: 2590 tsc_pg_val = hv_read_tsc_page_tsc(hv_get_tsc_page(), 2591 tsc_timestamp); 2592 if (tsc_pg_val != U64_MAX) { 2593 /* TSC page valid */ 2594 *mode = VDSO_CLOCKMODE_HVCLOCK; 2595 v = (tsc_pg_val - clock->cycle_last) & 2596 clock->mask; 2597 } else { 2598 /* TSC page invalid */ 2599 *mode = VDSO_CLOCKMODE_NONE; 2600 } 2601 break; 2602 case VDSO_CLOCKMODE_TSC: 2603 *mode = VDSO_CLOCKMODE_TSC; 2604 *tsc_timestamp = read_tsc(); 2605 v = (*tsc_timestamp - clock->cycle_last) & 2606 clock->mask; 2607 break; 2608 default: 2609 *mode = VDSO_CLOCKMODE_NONE; 2610 } 2611 2612 if (*mode == VDSO_CLOCKMODE_NONE) 2613 *tsc_timestamp = v = 0; 2614 2615 return v * clock->mult; 2616 } 2617 2618 static int do_monotonic_raw(s64 *t, u64 *tsc_timestamp) 2619 { 2620 struct pvclock_gtod_data *gtod = &pvclock_gtod_data; 2621 unsigned long seq; 2622 int mode; 2623 u64 ns; 2624 2625 do { 2626 seq = read_seqcount_begin(>od->seq); 2627 ns = gtod->raw_clock.base_cycles; 2628 ns += vgettsc(>od->raw_clock, tsc_timestamp, &mode); 2629 ns >>= gtod->raw_clock.shift; 2630 ns += ktime_to_ns(ktime_add(gtod->raw_clock.offset, gtod->offs_boot)); 2631 } while (unlikely(read_seqcount_retry(>od->seq, seq))); 2632 *t = ns; 2633 2634 return mode; 2635 } 2636 2637 static int do_realtime(struct timespec64 *ts, u64 *tsc_timestamp) 2638 { 2639 struct pvclock_gtod_data *gtod = &pvclock_gtod_data; 2640 unsigned long seq; 2641 int mode; 2642 u64 ns; 2643 2644 do { 2645 seq = read_seqcount_begin(>od->seq); 2646 ts->tv_sec = gtod->wall_time_sec; 2647 ns = gtod->clock.base_cycles; 2648 ns += vgettsc(>od->clock, tsc_timestamp, &mode); 2649 ns >>= gtod->clock.shift; 2650 } while (unlikely(read_seqcount_retry(>od->seq, seq))); 2651 2652 ts->tv_sec += __iter_div_u64_rem(ns, NSEC_PER_SEC, &ns); 2653 ts->tv_nsec = ns; 2654 2655 return mode; 2656 } 2657 2658 /* returns true if host is using TSC based clocksource */ 2659 static bool kvm_get_time_and_clockread(s64 *kernel_ns, u64 *tsc_timestamp) 2660 { 2661 /* checked again under seqlock below */ 2662 if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode)) 2663 return false; 2664 2665 return gtod_is_based_on_tsc(do_monotonic_raw(kernel_ns, 2666 tsc_timestamp)); 2667 } 2668 2669 /* returns true if host is using TSC based clocksource */ 2670 static bool kvm_get_walltime_and_clockread(struct timespec64 *ts, 2671 u64 *tsc_timestamp) 2672 { 2673 /* checked again under seqlock below */ 2674 if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode)) 2675 return false; 2676 2677 return gtod_is_based_on_tsc(do_realtime(ts, tsc_timestamp)); 2678 } 2679 #endif 2680 2681 /* 2682 * 2683 * Assuming a stable TSC across physical CPUS, and a stable TSC 2684 * across virtual CPUs, the following condition is possible. 2685 * Each numbered line represents an event visible to both 2686 * CPUs at the next numbered event. 2687 * 2688 * "timespecX" represents host monotonic time. "tscX" represents 2689 * RDTSC value. 2690 * 2691 * VCPU0 on CPU0 | VCPU1 on CPU1 2692 * 2693 * 1. read timespec0,tsc0 2694 * 2. | timespec1 = timespec0 + N 2695 * | tsc1 = tsc0 + M 2696 * 3. transition to guest | transition to guest 2697 * 4. ret0 = timespec0 + (rdtsc - tsc0) | 2698 * 5. | ret1 = timespec1 + (rdtsc - tsc1) 2699 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M)) 2700 * 2701 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity: 2702 * 2703 * - ret0 < ret1 2704 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M)) 2705 * ... 2706 * - 0 < N - M => M < N 2707 * 2708 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not 2709 * always the case (the difference between two distinct xtime instances 2710 * might be smaller then the difference between corresponding TSC reads, 2711 * when updating guest vcpus pvclock areas). 2712 * 2713 * To avoid that problem, do not allow visibility of distinct 2714 * system_timestamp/tsc_timestamp values simultaneously: use a master 2715 * copy of host monotonic time values. Update that master copy 2716 * in lockstep. 2717 * 2718 * Rely on synchronization of host TSCs and guest TSCs for monotonicity. 2719 * 2720 */ 2721 2722 static void pvclock_update_vm_gtod_copy(struct kvm *kvm) 2723 { 2724 #ifdef CONFIG_X86_64 2725 struct kvm_arch *ka = &kvm->arch; 2726 int vclock_mode; 2727 bool host_tsc_clocksource, vcpus_matched; 2728 2729 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 == 2730 atomic_read(&kvm->online_vcpus)); 2731 2732 /* 2733 * If the host uses TSC clock, then passthrough TSC as stable 2734 * to the guest. 2735 */ 2736 host_tsc_clocksource = kvm_get_time_and_clockread( 2737 &ka->master_kernel_ns, 2738 &ka->master_cycle_now); 2739 2740 ka->use_master_clock = host_tsc_clocksource && vcpus_matched 2741 && !ka->backwards_tsc_observed 2742 && !ka->boot_vcpu_runs_old_kvmclock; 2743 2744 if (ka->use_master_clock) 2745 atomic_set(&kvm_guest_has_master_clock, 1); 2746 2747 vclock_mode = pvclock_gtod_data.clock.vclock_mode; 2748 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode, 2749 vcpus_matched); 2750 #endif 2751 } 2752 2753 void kvm_make_mclock_inprogress_request(struct kvm *kvm) 2754 { 2755 kvm_make_all_cpus_request(kvm, KVM_REQ_MCLOCK_INPROGRESS); 2756 } 2757 2758 static void kvm_gen_update_masterclock(struct kvm *kvm) 2759 { 2760 #ifdef CONFIG_X86_64 2761 int i; 2762 struct kvm_vcpu *vcpu; 2763 struct kvm_arch *ka = &kvm->arch; 2764 unsigned long flags; 2765 2766 kvm_hv_invalidate_tsc_page(kvm); 2767 2768 kvm_make_mclock_inprogress_request(kvm); 2769 2770 /* no guest entries from this point */ 2771 spin_lock_irqsave(&ka->pvclock_gtod_sync_lock, flags); 2772 pvclock_update_vm_gtod_copy(kvm); 2773 spin_unlock_irqrestore(&ka->pvclock_gtod_sync_lock, flags); 2774 2775 kvm_for_each_vcpu(i, vcpu, kvm) 2776 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 2777 2778 /* guest entries allowed */ 2779 kvm_for_each_vcpu(i, vcpu, kvm) 2780 kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu); 2781 #endif 2782 } 2783 2784 u64 get_kvmclock_ns(struct kvm *kvm) 2785 { 2786 struct kvm_arch *ka = &kvm->arch; 2787 struct pvclock_vcpu_time_info hv_clock; 2788 unsigned long flags; 2789 u64 ret; 2790 2791 spin_lock_irqsave(&ka->pvclock_gtod_sync_lock, flags); 2792 if (!ka->use_master_clock) { 2793 spin_unlock_irqrestore(&ka->pvclock_gtod_sync_lock, flags); 2794 return get_kvmclock_base_ns() + ka->kvmclock_offset; 2795 } 2796 2797 hv_clock.tsc_timestamp = ka->master_cycle_now; 2798 hv_clock.system_time = ka->master_kernel_ns + ka->kvmclock_offset; 2799 spin_unlock_irqrestore(&ka->pvclock_gtod_sync_lock, flags); 2800 2801 /* both __this_cpu_read() and rdtsc() should be on the same cpu */ 2802 get_cpu(); 2803 2804 if (__this_cpu_read(cpu_tsc_khz)) { 2805 kvm_get_time_scale(NSEC_PER_SEC, __this_cpu_read(cpu_tsc_khz) * 1000LL, 2806 &hv_clock.tsc_shift, 2807 &hv_clock.tsc_to_system_mul); 2808 ret = __pvclock_read_cycles(&hv_clock, rdtsc()); 2809 } else 2810 ret = get_kvmclock_base_ns() + ka->kvmclock_offset; 2811 2812 put_cpu(); 2813 2814 return ret; 2815 } 2816 2817 static void kvm_setup_pvclock_page(struct kvm_vcpu *v, 2818 struct gfn_to_hva_cache *cache, 2819 unsigned int offset) 2820 { 2821 struct kvm_vcpu_arch *vcpu = &v->arch; 2822 struct pvclock_vcpu_time_info guest_hv_clock; 2823 2824 if (unlikely(kvm_read_guest_offset_cached(v->kvm, cache, 2825 &guest_hv_clock, offset, sizeof(guest_hv_clock)))) 2826 return; 2827 2828 /* This VCPU is paused, but it's legal for a guest to read another 2829 * VCPU's kvmclock, so we really have to follow the specification where 2830 * it says that version is odd if data is being modified, and even after 2831 * it is consistent. 2832 * 2833 * Version field updates must be kept separate. This is because 2834 * kvm_write_guest_cached might use a "rep movs" instruction, and 2835 * writes within a string instruction are weakly ordered. So there 2836 * are three writes overall. 2837 * 2838 * As a small optimization, only write the version field in the first 2839 * and third write. The vcpu->pv_time cache is still valid, because the 2840 * version field is the first in the struct. 2841 */ 2842 BUILD_BUG_ON(offsetof(struct pvclock_vcpu_time_info, version) != 0); 2843 2844 if (guest_hv_clock.version & 1) 2845 ++guest_hv_clock.version; /* first time write, random junk */ 2846 2847 vcpu->hv_clock.version = guest_hv_clock.version + 1; 2848 kvm_write_guest_offset_cached(v->kvm, cache, 2849 &vcpu->hv_clock, offset, 2850 sizeof(vcpu->hv_clock.version)); 2851 2852 smp_wmb(); 2853 2854 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */ 2855 vcpu->hv_clock.flags |= (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED); 2856 2857 if (vcpu->pvclock_set_guest_stopped_request) { 2858 vcpu->hv_clock.flags |= PVCLOCK_GUEST_STOPPED; 2859 vcpu->pvclock_set_guest_stopped_request = false; 2860 } 2861 2862 trace_kvm_pvclock_update(v->vcpu_id, &vcpu->hv_clock); 2863 2864 kvm_write_guest_offset_cached(v->kvm, cache, 2865 &vcpu->hv_clock, offset, 2866 sizeof(vcpu->hv_clock)); 2867 2868 smp_wmb(); 2869 2870 vcpu->hv_clock.version++; 2871 kvm_write_guest_offset_cached(v->kvm, cache, 2872 &vcpu->hv_clock, offset, 2873 sizeof(vcpu->hv_clock.version)); 2874 } 2875 2876 static int kvm_guest_time_update(struct kvm_vcpu *v) 2877 { 2878 unsigned long flags, tgt_tsc_khz; 2879 struct kvm_vcpu_arch *vcpu = &v->arch; 2880 struct kvm_arch *ka = &v->kvm->arch; 2881 s64 kernel_ns; 2882 u64 tsc_timestamp, host_tsc; 2883 u8 pvclock_flags; 2884 bool use_master_clock; 2885 2886 kernel_ns = 0; 2887 host_tsc = 0; 2888 2889 /* 2890 * If the host uses TSC clock, then passthrough TSC as stable 2891 * to the guest. 2892 */ 2893 spin_lock_irqsave(&ka->pvclock_gtod_sync_lock, flags); 2894 use_master_clock = ka->use_master_clock; 2895 if (use_master_clock) { 2896 host_tsc = ka->master_cycle_now; 2897 kernel_ns = ka->master_kernel_ns; 2898 } 2899 spin_unlock_irqrestore(&ka->pvclock_gtod_sync_lock, flags); 2900 2901 /* Keep irq disabled to prevent changes to the clock */ 2902 local_irq_save(flags); 2903 tgt_tsc_khz = __this_cpu_read(cpu_tsc_khz); 2904 if (unlikely(tgt_tsc_khz == 0)) { 2905 local_irq_restore(flags); 2906 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v); 2907 return 1; 2908 } 2909 if (!use_master_clock) { 2910 host_tsc = rdtsc(); 2911 kernel_ns = get_kvmclock_base_ns(); 2912 } 2913 2914 tsc_timestamp = kvm_read_l1_tsc(v, host_tsc); 2915 2916 /* 2917 * We may have to catch up the TSC to match elapsed wall clock 2918 * time for two reasons, even if kvmclock is used. 2919 * 1) CPU could have been running below the maximum TSC rate 2920 * 2) Broken TSC compensation resets the base at each VCPU 2921 * entry to avoid unknown leaps of TSC even when running 2922 * again on the same CPU. This may cause apparent elapsed 2923 * time to disappear, and the guest to stand still or run 2924 * very slowly. 2925 */ 2926 if (vcpu->tsc_catchup) { 2927 u64 tsc = compute_guest_tsc(v, kernel_ns); 2928 if (tsc > tsc_timestamp) { 2929 adjust_tsc_offset_guest(v, tsc - tsc_timestamp); 2930 tsc_timestamp = tsc; 2931 } 2932 } 2933 2934 local_irq_restore(flags); 2935 2936 /* With all the info we got, fill in the values */ 2937 2938 if (kvm_has_tsc_control) 2939 tgt_tsc_khz = kvm_scale_tsc(v, tgt_tsc_khz, 2940 v->arch.l1_tsc_scaling_ratio); 2941 2942 if (unlikely(vcpu->hw_tsc_khz != tgt_tsc_khz)) { 2943 kvm_get_time_scale(NSEC_PER_SEC, tgt_tsc_khz * 1000LL, 2944 &vcpu->hv_clock.tsc_shift, 2945 &vcpu->hv_clock.tsc_to_system_mul); 2946 vcpu->hw_tsc_khz = tgt_tsc_khz; 2947 } 2948 2949 vcpu->hv_clock.tsc_timestamp = tsc_timestamp; 2950 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset; 2951 vcpu->last_guest_tsc = tsc_timestamp; 2952 2953 /* If the host uses TSC clocksource, then it is stable */ 2954 pvclock_flags = 0; 2955 if (use_master_clock) 2956 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT; 2957 2958 vcpu->hv_clock.flags = pvclock_flags; 2959 2960 if (vcpu->pv_time_enabled) 2961 kvm_setup_pvclock_page(v, &vcpu->pv_time, 0); 2962 if (vcpu->xen.vcpu_info_set) 2963 kvm_setup_pvclock_page(v, &vcpu->xen.vcpu_info_cache, 2964 offsetof(struct compat_vcpu_info, time)); 2965 if (vcpu->xen.vcpu_time_info_set) 2966 kvm_setup_pvclock_page(v, &vcpu->xen.vcpu_time_info_cache, 0); 2967 if (v == kvm_get_vcpu(v->kvm, 0)) 2968 kvm_hv_setup_tsc_page(v->kvm, &vcpu->hv_clock); 2969 return 0; 2970 } 2971 2972 /* 2973 * kvmclock updates which are isolated to a given vcpu, such as 2974 * vcpu->cpu migration, should not allow system_timestamp from 2975 * the rest of the vcpus to remain static. Otherwise ntp frequency 2976 * correction applies to one vcpu's system_timestamp but not 2977 * the others. 2978 * 2979 * So in those cases, request a kvmclock update for all vcpus. 2980 * We need to rate-limit these requests though, as they can 2981 * considerably slow guests that have a large number of vcpus. 2982 * The time for a remote vcpu to update its kvmclock is bound 2983 * by the delay we use to rate-limit the updates. 2984 */ 2985 2986 #define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100) 2987 2988 static void kvmclock_update_fn(struct work_struct *work) 2989 { 2990 int i; 2991 struct delayed_work *dwork = to_delayed_work(work); 2992 struct kvm_arch *ka = container_of(dwork, struct kvm_arch, 2993 kvmclock_update_work); 2994 struct kvm *kvm = container_of(ka, struct kvm, arch); 2995 struct kvm_vcpu *vcpu; 2996 2997 kvm_for_each_vcpu(i, vcpu, kvm) { 2998 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 2999 kvm_vcpu_kick(vcpu); 3000 } 3001 } 3002 3003 static void kvm_gen_kvmclock_update(struct kvm_vcpu *v) 3004 { 3005 struct kvm *kvm = v->kvm; 3006 3007 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v); 3008 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 3009 KVMCLOCK_UPDATE_DELAY); 3010 } 3011 3012 #define KVMCLOCK_SYNC_PERIOD (300 * HZ) 3013 3014 static void kvmclock_sync_fn(struct work_struct *work) 3015 { 3016 struct delayed_work *dwork = to_delayed_work(work); 3017 struct kvm_arch *ka = container_of(dwork, struct kvm_arch, 3018 kvmclock_sync_work); 3019 struct kvm *kvm = container_of(ka, struct kvm, arch); 3020 3021 if (!kvmclock_periodic_sync) 3022 return; 3023 3024 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0); 3025 schedule_delayed_work(&kvm->arch.kvmclock_sync_work, 3026 KVMCLOCK_SYNC_PERIOD); 3027 } 3028 3029 /* 3030 * On AMD, HWCR[McStatusWrEn] controls whether setting MCi_STATUS results in #GP. 3031 */ 3032 static bool can_set_mci_status(struct kvm_vcpu *vcpu) 3033 { 3034 /* McStatusWrEn enabled? */ 3035 if (guest_cpuid_is_amd_or_hygon(vcpu)) 3036 return !!(vcpu->arch.msr_hwcr & BIT_ULL(18)); 3037 3038 return false; 3039 } 3040 3041 static int set_msr_mce(struct kvm_vcpu *vcpu, struct msr_data *msr_info) 3042 { 3043 u64 mcg_cap = vcpu->arch.mcg_cap; 3044 unsigned bank_num = mcg_cap & 0xff; 3045 u32 msr = msr_info->index; 3046 u64 data = msr_info->data; 3047 3048 switch (msr) { 3049 case MSR_IA32_MCG_STATUS: 3050 vcpu->arch.mcg_status = data; 3051 break; 3052 case MSR_IA32_MCG_CTL: 3053 if (!(mcg_cap & MCG_CTL_P) && 3054 (data || !msr_info->host_initiated)) 3055 return 1; 3056 if (data != 0 && data != ~(u64)0) 3057 return 1; 3058 vcpu->arch.mcg_ctl = data; 3059 break; 3060 default: 3061 if (msr >= MSR_IA32_MC0_CTL && 3062 msr < MSR_IA32_MCx_CTL(bank_num)) { 3063 u32 offset = array_index_nospec( 3064 msr - MSR_IA32_MC0_CTL, 3065 MSR_IA32_MCx_CTL(bank_num) - MSR_IA32_MC0_CTL); 3066 3067 /* only 0 or all 1s can be written to IA32_MCi_CTL 3068 * some Linux kernels though clear bit 10 in bank 4 to 3069 * workaround a BIOS/GART TBL issue on AMD K8s, ignore 3070 * this to avoid an uncatched #GP in the guest 3071 */ 3072 if ((offset & 0x3) == 0 && 3073 data != 0 && (data | (1 << 10)) != ~(u64)0) 3074 return -1; 3075 3076 /* MCi_STATUS */ 3077 if (!msr_info->host_initiated && 3078 (offset & 0x3) == 1 && data != 0) { 3079 if (!can_set_mci_status(vcpu)) 3080 return -1; 3081 } 3082 3083 vcpu->arch.mce_banks[offset] = data; 3084 break; 3085 } 3086 return 1; 3087 } 3088 return 0; 3089 } 3090 3091 static inline bool kvm_pv_async_pf_enabled(struct kvm_vcpu *vcpu) 3092 { 3093 u64 mask = KVM_ASYNC_PF_ENABLED | KVM_ASYNC_PF_DELIVERY_AS_INT; 3094 3095 return (vcpu->arch.apf.msr_en_val & mask) == mask; 3096 } 3097 3098 static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data) 3099 { 3100 gpa_t gpa = data & ~0x3f; 3101 3102 /* Bits 4:5 are reserved, Should be zero */ 3103 if (data & 0x30) 3104 return 1; 3105 3106 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_VMEXIT) && 3107 (data & KVM_ASYNC_PF_DELIVERY_AS_PF_VMEXIT)) 3108 return 1; 3109 3110 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_INT) && 3111 (data & KVM_ASYNC_PF_DELIVERY_AS_INT)) 3112 return 1; 3113 3114 if (!lapic_in_kernel(vcpu)) 3115 return data ? 1 : 0; 3116 3117 vcpu->arch.apf.msr_en_val = data; 3118 3119 if (!kvm_pv_async_pf_enabled(vcpu)) { 3120 kvm_clear_async_pf_completion_queue(vcpu); 3121 kvm_async_pf_hash_reset(vcpu); 3122 return 0; 3123 } 3124 3125 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa, 3126 sizeof(u64))) 3127 return 1; 3128 3129 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS); 3130 vcpu->arch.apf.delivery_as_pf_vmexit = data & KVM_ASYNC_PF_DELIVERY_AS_PF_VMEXIT; 3131 3132 kvm_async_pf_wakeup_all(vcpu); 3133 3134 return 0; 3135 } 3136 3137 static int kvm_pv_enable_async_pf_int(struct kvm_vcpu *vcpu, u64 data) 3138 { 3139 /* Bits 8-63 are reserved */ 3140 if (data >> 8) 3141 return 1; 3142 3143 if (!lapic_in_kernel(vcpu)) 3144 return 1; 3145 3146 vcpu->arch.apf.msr_int_val = data; 3147 3148 vcpu->arch.apf.vec = data & KVM_ASYNC_PF_VEC_MASK; 3149 3150 return 0; 3151 } 3152 3153 static void kvmclock_reset(struct kvm_vcpu *vcpu) 3154 { 3155 vcpu->arch.pv_time_enabled = false; 3156 vcpu->arch.time = 0; 3157 } 3158 3159 static void kvm_vcpu_flush_tlb_all(struct kvm_vcpu *vcpu) 3160 { 3161 ++vcpu->stat.tlb_flush; 3162 static_call(kvm_x86_tlb_flush_all)(vcpu); 3163 } 3164 3165 static void kvm_vcpu_flush_tlb_guest(struct kvm_vcpu *vcpu) 3166 { 3167 ++vcpu->stat.tlb_flush; 3168 3169 if (!tdp_enabled) { 3170 /* 3171 * A TLB flush on behalf of the guest is equivalent to 3172 * INVPCID(all), toggling CR4.PGE, etc., which requires 3173 * a forced sync of the shadow page tables. Unload the 3174 * entire MMU here and the subsequent load will sync the 3175 * shadow page tables, and also flush the TLB. 3176 */ 3177 kvm_mmu_unload(vcpu); 3178 return; 3179 } 3180 3181 static_call(kvm_x86_tlb_flush_guest)(vcpu); 3182 } 3183 3184 static void record_steal_time(struct kvm_vcpu *vcpu) 3185 { 3186 struct kvm_host_map map; 3187 struct kvm_steal_time *st; 3188 3189 if (kvm_xen_msr_enabled(vcpu->kvm)) { 3190 kvm_xen_runstate_set_running(vcpu); 3191 return; 3192 } 3193 3194 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED)) 3195 return; 3196 3197 /* -EAGAIN is returned in atomic context so we can just return. */ 3198 if (kvm_map_gfn(vcpu, vcpu->arch.st.msr_val >> PAGE_SHIFT, 3199 &map, &vcpu->arch.st.cache, false)) 3200 return; 3201 3202 st = map.hva + 3203 offset_in_page(vcpu->arch.st.msr_val & KVM_STEAL_VALID_BITS); 3204 3205 /* 3206 * Doing a TLB flush here, on the guest's behalf, can avoid 3207 * expensive IPIs. 3208 */ 3209 if (guest_pv_has(vcpu, KVM_FEATURE_PV_TLB_FLUSH)) { 3210 u8 st_preempted = xchg(&st->preempted, 0); 3211 3212 trace_kvm_pv_tlb_flush(vcpu->vcpu_id, 3213 st_preempted & KVM_VCPU_FLUSH_TLB); 3214 if (st_preempted & KVM_VCPU_FLUSH_TLB) 3215 kvm_vcpu_flush_tlb_guest(vcpu); 3216 } else { 3217 st->preempted = 0; 3218 } 3219 3220 vcpu->arch.st.preempted = 0; 3221 3222 if (st->version & 1) 3223 st->version += 1; /* first time write, random junk */ 3224 3225 st->version += 1; 3226 3227 smp_wmb(); 3228 3229 st->steal += current->sched_info.run_delay - 3230 vcpu->arch.st.last_steal; 3231 vcpu->arch.st.last_steal = current->sched_info.run_delay; 3232 3233 smp_wmb(); 3234 3235 st->version += 1; 3236 3237 kvm_unmap_gfn(vcpu, &map, &vcpu->arch.st.cache, true, false); 3238 } 3239 3240 int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info) 3241 { 3242 bool pr = false; 3243 u32 msr = msr_info->index; 3244 u64 data = msr_info->data; 3245 3246 if (msr && msr == vcpu->kvm->arch.xen_hvm_config.msr) 3247 return kvm_xen_write_hypercall_page(vcpu, data); 3248 3249 switch (msr) { 3250 case MSR_AMD64_NB_CFG: 3251 case MSR_IA32_UCODE_WRITE: 3252 case MSR_VM_HSAVE_PA: 3253 case MSR_AMD64_PATCH_LOADER: 3254 case MSR_AMD64_BU_CFG2: 3255 case MSR_AMD64_DC_CFG: 3256 case MSR_F15H_EX_CFG: 3257 break; 3258 3259 case MSR_IA32_UCODE_REV: 3260 if (msr_info->host_initiated) 3261 vcpu->arch.microcode_version = data; 3262 break; 3263 case MSR_IA32_ARCH_CAPABILITIES: 3264 if (!msr_info->host_initiated) 3265 return 1; 3266 vcpu->arch.arch_capabilities = data; 3267 break; 3268 case MSR_IA32_PERF_CAPABILITIES: { 3269 struct kvm_msr_entry msr_ent = {.index = msr, .data = 0}; 3270 3271 if (!msr_info->host_initiated) 3272 return 1; 3273 if (guest_cpuid_has(vcpu, X86_FEATURE_PDCM) && kvm_get_msr_feature(&msr_ent)) 3274 return 1; 3275 if (data & ~msr_ent.data) 3276 return 1; 3277 3278 vcpu->arch.perf_capabilities = data; 3279 3280 return 0; 3281 } 3282 case MSR_EFER: 3283 return set_efer(vcpu, msr_info); 3284 case MSR_K7_HWCR: 3285 data &= ~(u64)0x40; /* ignore flush filter disable */ 3286 data &= ~(u64)0x100; /* ignore ignne emulation enable */ 3287 data &= ~(u64)0x8; /* ignore TLB cache disable */ 3288 3289 /* Handle McStatusWrEn */ 3290 if (data == BIT_ULL(18)) { 3291 vcpu->arch.msr_hwcr = data; 3292 } else if (data != 0) { 3293 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n", 3294 data); 3295 return 1; 3296 } 3297 break; 3298 case MSR_FAM10H_MMIO_CONF_BASE: 3299 if (data != 0) { 3300 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: " 3301 "0x%llx\n", data); 3302 return 1; 3303 } 3304 break; 3305 case 0x200 ... 0x2ff: 3306 return kvm_mtrr_set_msr(vcpu, msr, data); 3307 case MSR_IA32_APICBASE: 3308 return kvm_set_apic_base(vcpu, msr_info); 3309 case APIC_BASE_MSR ... APIC_BASE_MSR + 0xff: 3310 return kvm_x2apic_msr_write(vcpu, msr, data); 3311 case MSR_IA32_TSC_DEADLINE: 3312 kvm_set_lapic_tscdeadline_msr(vcpu, data); 3313 break; 3314 case MSR_IA32_TSC_ADJUST: 3315 if (guest_cpuid_has(vcpu, X86_FEATURE_TSC_ADJUST)) { 3316 if (!msr_info->host_initiated) { 3317 s64 adj = data - vcpu->arch.ia32_tsc_adjust_msr; 3318 adjust_tsc_offset_guest(vcpu, adj); 3319 } 3320 vcpu->arch.ia32_tsc_adjust_msr = data; 3321 } 3322 break; 3323 case MSR_IA32_MISC_ENABLE: 3324 if (!kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_MISC_ENABLE_NO_MWAIT) && 3325 ((vcpu->arch.ia32_misc_enable_msr ^ data) & MSR_IA32_MISC_ENABLE_MWAIT)) { 3326 if (!guest_cpuid_has(vcpu, X86_FEATURE_XMM3)) 3327 return 1; 3328 vcpu->arch.ia32_misc_enable_msr = data; 3329 kvm_update_cpuid_runtime(vcpu); 3330 } else { 3331 vcpu->arch.ia32_misc_enable_msr = data; 3332 } 3333 break; 3334 case MSR_IA32_SMBASE: 3335 if (!msr_info->host_initiated) 3336 return 1; 3337 vcpu->arch.smbase = data; 3338 break; 3339 case MSR_IA32_POWER_CTL: 3340 vcpu->arch.msr_ia32_power_ctl = data; 3341 break; 3342 case MSR_IA32_TSC: 3343 if (msr_info->host_initiated) { 3344 kvm_synchronize_tsc(vcpu, data); 3345 } else { 3346 u64 adj = kvm_compute_l1_tsc_offset(vcpu, data) - vcpu->arch.l1_tsc_offset; 3347 adjust_tsc_offset_guest(vcpu, adj); 3348 vcpu->arch.ia32_tsc_adjust_msr += adj; 3349 } 3350 break; 3351 case MSR_IA32_XSS: 3352 if (!msr_info->host_initiated && 3353 !guest_cpuid_has(vcpu, X86_FEATURE_XSAVES)) 3354 return 1; 3355 /* 3356 * KVM supports exposing PT to the guest, but does not support 3357 * IA32_XSS[bit 8]. Guests have to use RDMSR/WRMSR rather than 3358 * XSAVES/XRSTORS to save/restore PT MSRs. 3359 */ 3360 if (data & ~supported_xss) 3361 return 1; 3362 vcpu->arch.ia32_xss = data; 3363 break; 3364 case MSR_SMI_COUNT: 3365 if (!msr_info->host_initiated) 3366 return 1; 3367 vcpu->arch.smi_count = data; 3368 break; 3369 case MSR_KVM_WALL_CLOCK_NEW: 3370 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE2)) 3371 return 1; 3372 3373 vcpu->kvm->arch.wall_clock = data; 3374 kvm_write_wall_clock(vcpu->kvm, data, 0); 3375 break; 3376 case MSR_KVM_WALL_CLOCK: 3377 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE)) 3378 return 1; 3379 3380 vcpu->kvm->arch.wall_clock = data; 3381 kvm_write_wall_clock(vcpu->kvm, data, 0); 3382 break; 3383 case MSR_KVM_SYSTEM_TIME_NEW: 3384 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE2)) 3385 return 1; 3386 3387 kvm_write_system_time(vcpu, data, false, msr_info->host_initiated); 3388 break; 3389 case MSR_KVM_SYSTEM_TIME: 3390 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE)) 3391 return 1; 3392 3393 kvm_write_system_time(vcpu, data, true, msr_info->host_initiated); 3394 break; 3395 case MSR_KVM_ASYNC_PF_EN: 3396 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF)) 3397 return 1; 3398 3399 if (kvm_pv_enable_async_pf(vcpu, data)) 3400 return 1; 3401 break; 3402 case MSR_KVM_ASYNC_PF_INT: 3403 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_INT)) 3404 return 1; 3405 3406 if (kvm_pv_enable_async_pf_int(vcpu, data)) 3407 return 1; 3408 break; 3409 case MSR_KVM_ASYNC_PF_ACK: 3410 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF)) 3411 return 1; 3412 if (data & 0x1) { 3413 vcpu->arch.apf.pageready_pending = false; 3414 kvm_check_async_pf_completion(vcpu); 3415 } 3416 break; 3417 case MSR_KVM_STEAL_TIME: 3418 if (!guest_pv_has(vcpu, KVM_FEATURE_STEAL_TIME)) 3419 return 1; 3420 3421 if (unlikely(!sched_info_on())) 3422 return 1; 3423 3424 if (data & KVM_STEAL_RESERVED_MASK) 3425 return 1; 3426 3427 vcpu->arch.st.msr_val = data; 3428 3429 if (!(data & KVM_MSR_ENABLED)) 3430 break; 3431 3432 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu); 3433 3434 break; 3435 case MSR_KVM_PV_EOI_EN: 3436 if (!guest_pv_has(vcpu, KVM_FEATURE_PV_EOI)) 3437 return 1; 3438 3439 if (kvm_lapic_enable_pv_eoi(vcpu, data, sizeof(u8))) 3440 return 1; 3441 break; 3442 3443 case MSR_KVM_POLL_CONTROL: 3444 if (!guest_pv_has(vcpu, KVM_FEATURE_POLL_CONTROL)) 3445 return 1; 3446 3447 /* only enable bit supported */ 3448 if (data & (-1ULL << 1)) 3449 return 1; 3450 3451 vcpu->arch.msr_kvm_poll_control = data; 3452 break; 3453 3454 case MSR_IA32_MCG_CTL: 3455 case MSR_IA32_MCG_STATUS: 3456 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1: 3457 return set_msr_mce(vcpu, msr_info); 3458 3459 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3: 3460 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1: 3461 pr = true; 3462 fallthrough; 3463 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3: 3464 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1: 3465 if (kvm_pmu_is_valid_msr(vcpu, msr)) 3466 return kvm_pmu_set_msr(vcpu, msr_info); 3467 3468 if (pr || data != 0) 3469 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: " 3470 "0x%x data 0x%llx\n", msr, data); 3471 break; 3472 case MSR_K7_CLK_CTL: 3473 /* 3474 * Ignore all writes to this no longer documented MSR. 3475 * Writes are only relevant for old K7 processors, 3476 * all pre-dating SVM, but a recommended workaround from 3477 * AMD for these chips. It is possible to specify the 3478 * affected processor models on the command line, hence 3479 * the need to ignore the workaround. 3480 */ 3481 break; 3482 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15: 3483 case HV_X64_MSR_SYNDBG_CONTROL ... HV_X64_MSR_SYNDBG_PENDING_BUFFER: 3484 case HV_X64_MSR_SYNDBG_OPTIONS: 3485 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4: 3486 case HV_X64_MSR_CRASH_CTL: 3487 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT: 3488 case HV_X64_MSR_REENLIGHTENMENT_CONTROL: 3489 case HV_X64_MSR_TSC_EMULATION_CONTROL: 3490 case HV_X64_MSR_TSC_EMULATION_STATUS: 3491 return kvm_hv_set_msr_common(vcpu, msr, data, 3492 msr_info->host_initiated); 3493 case MSR_IA32_BBL_CR_CTL3: 3494 /* Drop writes to this legacy MSR -- see rdmsr 3495 * counterpart for further detail. 3496 */ 3497 if (report_ignored_msrs) 3498 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data 0x%llx\n", 3499 msr, data); 3500 break; 3501 case MSR_AMD64_OSVW_ID_LENGTH: 3502 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW)) 3503 return 1; 3504 vcpu->arch.osvw.length = data; 3505 break; 3506 case MSR_AMD64_OSVW_STATUS: 3507 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW)) 3508 return 1; 3509 vcpu->arch.osvw.status = data; 3510 break; 3511 case MSR_PLATFORM_INFO: 3512 if (!msr_info->host_initiated || 3513 (!(data & MSR_PLATFORM_INFO_CPUID_FAULT) && 3514 cpuid_fault_enabled(vcpu))) 3515 return 1; 3516 vcpu->arch.msr_platform_info = data; 3517 break; 3518 case MSR_MISC_FEATURES_ENABLES: 3519 if (data & ~MSR_MISC_FEATURES_ENABLES_CPUID_FAULT || 3520 (data & MSR_MISC_FEATURES_ENABLES_CPUID_FAULT && 3521 !supports_cpuid_fault(vcpu))) 3522 return 1; 3523 vcpu->arch.msr_misc_features_enables = data; 3524 break; 3525 default: 3526 if (kvm_pmu_is_valid_msr(vcpu, msr)) 3527 return kvm_pmu_set_msr(vcpu, msr_info); 3528 return KVM_MSR_RET_INVALID; 3529 } 3530 return 0; 3531 } 3532 EXPORT_SYMBOL_GPL(kvm_set_msr_common); 3533 3534 static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata, bool host) 3535 { 3536 u64 data; 3537 u64 mcg_cap = vcpu->arch.mcg_cap; 3538 unsigned bank_num = mcg_cap & 0xff; 3539 3540 switch (msr) { 3541 case MSR_IA32_P5_MC_ADDR: 3542 case MSR_IA32_P5_MC_TYPE: 3543 data = 0; 3544 break; 3545 case MSR_IA32_MCG_CAP: 3546 data = vcpu->arch.mcg_cap; 3547 break; 3548 case MSR_IA32_MCG_CTL: 3549 if (!(mcg_cap & MCG_CTL_P) && !host) 3550 return 1; 3551 data = vcpu->arch.mcg_ctl; 3552 break; 3553 case MSR_IA32_MCG_STATUS: 3554 data = vcpu->arch.mcg_status; 3555 break; 3556 default: 3557 if (msr >= MSR_IA32_MC0_CTL && 3558 msr < MSR_IA32_MCx_CTL(bank_num)) { 3559 u32 offset = array_index_nospec( 3560 msr - MSR_IA32_MC0_CTL, 3561 MSR_IA32_MCx_CTL(bank_num) - MSR_IA32_MC0_CTL); 3562 3563 data = vcpu->arch.mce_banks[offset]; 3564 break; 3565 } 3566 return 1; 3567 } 3568 *pdata = data; 3569 return 0; 3570 } 3571 3572 int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info) 3573 { 3574 switch (msr_info->index) { 3575 case MSR_IA32_PLATFORM_ID: 3576 case MSR_IA32_EBL_CR_POWERON: 3577 case MSR_IA32_LASTBRANCHFROMIP: 3578 case MSR_IA32_LASTBRANCHTOIP: 3579 case MSR_IA32_LASTINTFROMIP: 3580 case MSR_IA32_LASTINTTOIP: 3581 case MSR_AMD64_SYSCFG: 3582 case MSR_K8_TSEG_ADDR: 3583 case MSR_K8_TSEG_MASK: 3584 case MSR_VM_HSAVE_PA: 3585 case MSR_K8_INT_PENDING_MSG: 3586 case MSR_AMD64_NB_CFG: 3587 case MSR_FAM10H_MMIO_CONF_BASE: 3588 case MSR_AMD64_BU_CFG2: 3589 case MSR_IA32_PERF_CTL: 3590 case MSR_AMD64_DC_CFG: 3591 case MSR_F15H_EX_CFG: 3592 /* 3593 * Intel Sandy Bridge CPUs must support the RAPL (running average power 3594 * limit) MSRs. Just return 0, as we do not want to expose the host 3595 * data here. Do not conditionalize this on CPUID, as KVM does not do 3596 * so for existing CPU-specific MSRs. 3597 */ 3598 case MSR_RAPL_POWER_UNIT: 3599 case MSR_PP0_ENERGY_STATUS: /* Power plane 0 (core) */ 3600 case MSR_PP1_ENERGY_STATUS: /* Power plane 1 (graphics uncore) */ 3601 case MSR_PKG_ENERGY_STATUS: /* Total package */ 3602 case MSR_DRAM_ENERGY_STATUS: /* DRAM controller */ 3603 msr_info->data = 0; 3604 break; 3605 case MSR_F15H_PERF_CTL0 ... MSR_F15H_PERF_CTR5: 3606 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index)) 3607 return kvm_pmu_get_msr(vcpu, msr_info); 3608 if (!msr_info->host_initiated) 3609 return 1; 3610 msr_info->data = 0; 3611 break; 3612 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3: 3613 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3: 3614 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1: 3615 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1: 3616 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index)) 3617 return kvm_pmu_get_msr(vcpu, msr_info); 3618 msr_info->data = 0; 3619 break; 3620 case MSR_IA32_UCODE_REV: 3621 msr_info->data = vcpu->arch.microcode_version; 3622 break; 3623 case MSR_IA32_ARCH_CAPABILITIES: 3624 if (!msr_info->host_initiated && 3625 !guest_cpuid_has(vcpu, X86_FEATURE_ARCH_CAPABILITIES)) 3626 return 1; 3627 msr_info->data = vcpu->arch.arch_capabilities; 3628 break; 3629 case MSR_IA32_PERF_CAPABILITIES: 3630 if (!msr_info->host_initiated && 3631 !guest_cpuid_has(vcpu, X86_FEATURE_PDCM)) 3632 return 1; 3633 msr_info->data = vcpu->arch.perf_capabilities; 3634 break; 3635 case MSR_IA32_POWER_CTL: 3636 msr_info->data = vcpu->arch.msr_ia32_power_ctl; 3637 break; 3638 case MSR_IA32_TSC: { 3639 /* 3640 * Intel SDM states that MSR_IA32_TSC read adds the TSC offset 3641 * even when not intercepted. AMD manual doesn't explicitly 3642 * state this but appears to behave the same. 3643 * 3644 * On userspace reads and writes, however, we unconditionally 3645 * return L1's TSC value to ensure backwards-compatible 3646 * behavior for migration. 3647 */ 3648 u64 offset, ratio; 3649 3650 if (msr_info->host_initiated) { 3651 offset = vcpu->arch.l1_tsc_offset; 3652 ratio = vcpu->arch.l1_tsc_scaling_ratio; 3653 } else { 3654 offset = vcpu->arch.tsc_offset; 3655 ratio = vcpu->arch.tsc_scaling_ratio; 3656 } 3657 3658 msr_info->data = kvm_scale_tsc(vcpu, rdtsc(), ratio) + offset; 3659 break; 3660 } 3661 case MSR_MTRRcap: 3662 case 0x200 ... 0x2ff: 3663 return kvm_mtrr_get_msr(vcpu, msr_info->index, &msr_info->data); 3664 case 0xcd: /* fsb frequency */ 3665 msr_info->data = 3; 3666 break; 3667 /* 3668 * MSR_EBC_FREQUENCY_ID 3669 * Conservative value valid for even the basic CPU models. 3670 * Models 0,1: 000 in bits 23:21 indicating a bus speed of 3671 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz, 3672 * and 266MHz for model 3, or 4. Set Core Clock 3673 * Frequency to System Bus Frequency Ratio to 1 (bits 3674 * 31:24) even though these are only valid for CPU 3675 * models > 2, however guests may end up dividing or 3676 * multiplying by zero otherwise. 3677 */ 3678 case MSR_EBC_FREQUENCY_ID: 3679 msr_info->data = 1 << 24; 3680 break; 3681 case MSR_IA32_APICBASE: 3682 msr_info->data = kvm_get_apic_base(vcpu); 3683 break; 3684 case APIC_BASE_MSR ... APIC_BASE_MSR + 0xff: 3685 return kvm_x2apic_msr_read(vcpu, msr_info->index, &msr_info->data); 3686 case MSR_IA32_TSC_DEADLINE: 3687 msr_info->data = kvm_get_lapic_tscdeadline_msr(vcpu); 3688 break; 3689 case MSR_IA32_TSC_ADJUST: 3690 msr_info->data = (u64)vcpu->arch.ia32_tsc_adjust_msr; 3691 break; 3692 case MSR_IA32_MISC_ENABLE: 3693 msr_info->data = vcpu->arch.ia32_misc_enable_msr; 3694 break; 3695 case MSR_IA32_SMBASE: 3696 if (!msr_info->host_initiated) 3697 return 1; 3698 msr_info->data = vcpu->arch.smbase; 3699 break; 3700 case MSR_SMI_COUNT: 3701 msr_info->data = vcpu->arch.smi_count; 3702 break; 3703 case MSR_IA32_PERF_STATUS: 3704 /* TSC increment by tick */ 3705 msr_info->data = 1000ULL; 3706 /* CPU multiplier */ 3707 msr_info->data |= (((uint64_t)4ULL) << 40); 3708 break; 3709 case MSR_EFER: 3710 msr_info->data = vcpu->arch.efer; 3711 break; 3712 case MSR_KVM_WALL_CLOCK: 3713 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE)) 3714 return 1; 3715 3716 msr_info->data = vcpu->kvm->arch.wall_clock; 3717 break; 3718 case MSR_KVM_WALL_CLOCK_NEW: 3719 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE2)) 3720 return 1; 3721 3722 msr_info->data = vcpu->kvm->arch.wall_clock; 3723 break; 3724 case MSR_KVM_SYSTEM_TIME: 3725 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE)) 3726 return 1; 3727 3728 msr_info->data = vcpu->arch.time; 3729 break; 3730 case MSR_KVM_SYSTEM_TIME_NEW: 3731 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE2)) 3732 return 1; 3733 3734 msr_info->data = vcpu->arch.time; 3735 break; 3736 case MSR_KVM_ASYNC_PF_EN: 3737 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF)) 3738 return 1; 3739 3740 msr_info->data = vcpu->arch.apf.msr_en_val; 3741 break; 3742 case MSR_KVM_ASYNC_PF_INT: 3743 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_INT)) 3744 return 1; 3745 3746 msr_info->data = vcpu->arch.apf.msr_int_val; 3747 break; 3748 case MSR_KVM_ASYNC_PF_ACK: 3749 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF)) 3750 return 1; 3751 3752 msr_info->data = 0; 3753 break; 3754 case MSR_KVM_STEAL_TIME: 3755 if (!guest_pv_has(vcpu, KVM_FEATURE_STEAL_TIME)) 3756 return 1; 3757 3758 msr_info->data = vcpu->arch.st.msr_val; 3759 break; 3760 case MSR_KVM_PV_EOI_EN: 3761 if (!guest_pv_has(vcpu, KVM_FEATURE_PV_EOI)) 3762 return 1; 3763 3764 msr_info->data = vcpu->arch.pv_eoi.msr_val; 3765 break; 3766 case MSR_KVM_POLL_CONTROL: 3767 if (!guest_pv_has(vcpu, KVM_FEATURE_POLL_CONTROL)) 3768 return 1; 3769 3770 msr_info->data = vcpu->arch.msr_kvm_poll_control; 3771 break; 3772 case MSR_IA32_P5_MC_ADDR: 3773 case MSR_IA32_P5_MC_TYPE: 3774 case MSR_IA32_MCG_CAP: 3775 case MSR_IA32_MCG_CTL: 3776 case MSR_IA32_MCG_STATUS: 3777 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1: 3778 return get_msr_mce(vcpu, msr_info->index, &msr_info->data, 3779 msr_info->host_initiated); 3780 case MSR_IA32_XSS: 3781 if (!msr_info->host_initiated && 3782 !guest_cpuid_has(vcpu, X86_FEATURE_XSAVES)) 3783 return 1; 3784 msr_info->data = vcpu->arch.ia32_xss; 3785 break; 3786 case MSR_K7_CLK_CTL: 3787 /* 3788 * Provide expected ramp-up count for K7. All other 3789 * are set to zero, indicating minimum divisors for 3790 * every field. 3791 * 3792 * This prevents guest kernels on AMD host with CPU 3793 * type 6, model 8 and higher from exploding due to 3794 * the rdmsr failing. 3795 */ 3796 msr_info->data = 0x20000000; 3797 break; 3798 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15: 3799 case HV_X64_MSR_SYNDBG_CONTROL ... HV_X64_MSR_SYNDBG_PENDING_BUFFER: 3800 case HV_X64_MSR_SYNDBG_OPTIONS: 3801 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4: 3802 case HV_X64_MSR_CRASH_CTL: 3803 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT: 3804 case HV_X64_MSR_REENLIGHTENMENT_CONTROL: 3805 case HV_X64_MSR_TSC_EMULATION_CONTROL: 3806 case HV_X64_MSR_TSC_EMULATION_STATUS: 3807 return kvm_hv_get_msr_common(vcpu, 3808 msr_info->index, &msr_info->data, 3809 msr_info->host_initiated); 3810 case MSR_IA32_BBL_CR_CTL3: 3811 /* This legacy MSR exists but isn't fully documented in current 3812 * silicon. It is however accessed by winxp in very narrow 3813 * scenarios where it sets bit #19, itself documented as 3814 * a "reserved" bit. Best effort attempt to source coherent 3815 * read data here should the balance of the register be 3816 * interpreted by the guest: 3817 * 3818 * L2 cache control register 3: 64GB range, 256KB size, 3819 * enabled, latency 0x1, configured 3820 */ 3821 msr_info->data = 0xbe702111; 3822 break; 3823 case MSR_AMD64_OSVW_ID_LENGTH: 3824 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW)) 3825 return 1; 3826 msr_info->data = vcpu->arch.osvw.length; 3827 break; 3828 case MSR_AMD64_OSVW_STATUS: 3829 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW)) 3830 return 1; 3831 msr_info->data = vcpu->arch.osvw.status; 3832 break; 3833 case MSR_PLATFORM_INFO: 3834 if (!msr_info->host_initiated && 3835 !vcpu->kvm->arch.guest_can_read_msr_platform_info) 3836 return 1; 3837 msr_info->data = vcpu->arch.msr_platform_info; 3838 break; 3839 case MSR_MISC_FEATURES_ENABLES: 3840 msr_info->data = vcpu->arch.msr_misc_features_enables; 3841 break; 3842 case MSR_K7_HWCR: 3843 msr_info->data = vcpu->arch.msr_hwcr; 3844 break; 3845 default: 3846 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index)) 3847 return kvm_pmu_get_msr(vcpu, msr_info); 3848 return KVM_MSR_RET_INVALID; 3849 } 3850 return 0; 3851 } 3852 EXPORT_SYMBOL_GPL(kvm_get_msr_common); 3853 3854 /* 3855 * Read or write a bunch of msrs. All parameters are kernel addresses. 3856 * 3857 * @return number of msrs set successfully. 3858 */ 3859 static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs, 3860 struct kvm_msr_entry *entries, 3861 int (*do_msr)(struct kvm_vcpu *vcpu, 3862 unsigned index, u64 *data)) 3863 { 3864 int i; 3865 3866 for (i = 0; i < msrs->nmsrs; ++i) 3867 if (do_msr(vcpu, entries[i].index, &entries[i].data)) 3868 break; 3869 3870 return i; 3871 } 3872 3873 /* 3874 * Read or write a bunch of msrs. Parameters are user addresses. 3875 * 3876 * @return number of msrs set successfully. 3877 */ 3878 static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs, 3879 int (*do_msr)(struct kvm_vcpu *vcpu, 3880 unsigned index, u64 *data), 3881 int writeback) 3882 { 3883 struct kvm_msrs msrs; 3884 struct kvm_msr_entry *entries; 3885 int r, n; 3886 unsigned size; 3887 3888 r = -EFAULT; 3889 if (copy_from_user(&msrs, user_msrs, sizeof(msrs))) 3890 goto out; 3891 3892 r = -E2BIG; 3893 if (msrs.nmsrs >= MAX_IO_MSRS) 3894 goto out; 3895 3896 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs; 3897 entries = memdup_user(user_msrs->entries, size); 3898 if (IS_ERR(entries)) { 3899 r = PTR_ERR(entries); 3900 goto out; 3901 } 3902 3903 r = n = __msr_io(vcpu, &msrs, entries, do_msr); 3904 if (r < 0) 3905 goto out_free; 3906 3907 r = -EFAULT; 3908 if (writeback && copy_to_user(user_msrs->entries, entries, size)) 3909 goto out_free; 3910 3911 r = n; 3912 3913 out_free: 3914 kfree(entries); 3915 out: 3916 return r; 3917 } 3918 3919 static inline bool kvm_can_mwait_in_guest(void) 3920 { 3921 return boot_cpu_has(X86_FEATURE_MWAIT) && 3922 !boot_cpu_has_bug(X86_BUG_MONITOR) && 3923 boot_cpu_has(X86_FEATURE_ARAT); 3924 } 3925 3926 static int kvm_ioctl_get_supported_hv_cpuid(struct kvm_vcpu *vcpu, 3927 struct kvm_cpuid2 __user *cpuid_arg) 3928 { 3929 struct kvm_cpuid2 cpuid; 3930 int r; 3931 3932 r = -EFAULT; 3933 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid))) 3934 return r; 3935 3936 r = kvm_get_hv_cpuid(vcpu, &cpuid, cpuid_arg->entries); 3937 if (r) 3938 return r; 3939 3940 r = -EFAULT; 3941 if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid))) 3942 return r; 3943 3944 return 0; 3945 } 3946 3947 int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext) 3948 { 3949 int r = 0; 3950 3951 switch (ext) { 3952 case KVM_CAP_IRQCHIP: 3953 case KVM_CAP_HLT: 3954 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL: 3955 case KVM_CAP_SET_TSS_ADDR: 3956 case KVM_CAP_EXT_CPUID: 3957 case KVM_CAP_EXT_EMUL_CPUID: 3958 case KVM_CAP_CLOCKSOURCE: 3959 case KVM_CAP_PIT: 3960 case KVM_CAP_NOP_IO_DELAY: 3961 case KVM_CAP_MP_STATE: 3962 case KVM_CAP_SYNC_MMU: 3963 case KVM_CAP_USER_NMI: 3964 case KVM_CAP_REINJECT_CONTROL: 3965 case KVM_CAP_IRQ_INJECT_STATUS: 3966 case KVM_CAP_IOEVENTFD: 3967 case KVM_CAP_IOEVENTFD_NO_LENGTH: 3968 case KVM_CAP_PIT2: 3969 case KVM_CAP_PIT_STATE2: 3970 case KVM_CAP_SET_IDENTITY_MAP_ADDR: 3971 case KVM_CAP_VCPU_EVENTS: 3972 case KVM_CAP_HYPERV: 3973 case KVM_CAP_HYPERV_VAPIC: 3974 case KVM_CAP_HYPERV_SPIN: 3975 case KVM_CAP_HYPERV_SYNIC: 3976 case KVM_CAP_HYPERV_SYNIC2: 3977 case KVM_CAP_HYPERV_VP_INDEX: 3978 case KVM_CAP_HYPERV_EVENTFD: 3979 case KVM_CAP_HYPERV_TLBFLUSH: 3980 case KVM_CAP_HYPERV_SEND_IPI: 3981 case KVM_CAP_HYPERV_CPUID: 3982 case KVM_CAP_HYPERV_ENFORCE_CPUID: 3983 case KVM_CAP_SYS_HYPERV_CPUID: 3984 case KVM_CAP_PCI_SEGMENT: 3985 case KVM_CAP_DEBUGREGS: 3986 case KVM_CAP_X86_ROBUST_SINGLESTEP: 3987 case KVM_CAP_XSAVE: 3988 case KVM_CAP_ASYNC_PF: 3989 case KVM_CAP_ASYNC_PF_INT: 3990 case KVM_CAP_GET_TSC_KHZ: 3991 case KVM_CAP_KVMCLOCK_CTRL: 3992 case KVM_CAP_READONLY_MEM: 3993 case KVM_CAP_HYPERV_TIME: 3994 case KVM_CAP_IOAPIC_POLARITY_IGNORED: 3995 case KVM_CAP_TSC_DEADLINE_TIMER: 3996 case KVM_CAP_DISABLE_QUIRKS: 3997 case KVM_CAP_SET_BOOT_CPU_ID: 3998 case KVM_CAP_SPLIT_IRQCHIP: 3999 case KVM_CAP_IMMEDIATE_EXIT: 4000 case KVM_CAP_PMU_EVENT_FILTER: 4001 case KVM_CAP_GET_MSR_FEATURES: 4002 case KVM_CAP_MSR_PLATFORM_INFO: 4003 case KVM_CAP_EXCEPTION_PAYLOAD: 4004 case KVM_CAP_SET_GUEST_DEBUG: 4005 case KVM_CAP_LAST_CPU: 4006 case KVM_CAP_X86_USER_SPACE_MSR: 4007 case KVM_CAP_X86_MSR_FILTER: 4008 case KVM_CAP_ENFORCE_PV_FEATURE_CPUID: 4009 #ifdef CONFIG_X86_SGX_KVM 4010 case KVM_CAP_SGX_ATTRIBUTE: 4011 #endif 4012 case KVM_CAP_VM_COPY_ENC_CONTEXT_FROM: 4013 case KVM_CAP_SREGS2: 4014 case KVM_CAP_EXIT_ON_EMULATION_FAILURE: 4015 r = 1; 4016 break; 4017 case KVM_CAP_EXIT_HYPERCALL: 4018 r = KVM_EXIT_HYPERCALL_VALID_MASK; 4019 break; 4020 case KVM_CAP_SET_GUEST_DEBUG2: 4021 return KVM_GUESTDBG_VALID_MASK; 4022 #ifdef CONFIG_KVM_XEN 4023 case KVM_CAP_XEN_HVM: 4024 r = KVM_XEN_HVM_CONFIG_HYPERCALL_MSR | 4025 KVM_XEN_HVM_CONFIG_INTERCEPT_HCALL | 4026 KVM_XEN_HVM_CONFIG_SHARED_INFO; 4027 if (sched_info_on()) 4028 r |= KVM_XEN_HVM_CONFIG_RUNSTATE; 4029 break; 4030 #endif 4031 case KVM_CAP_SYNC_REGS: 4032 r = KVM_SYNC_X86_VALID_FIELDS; 4033 break; 4034 case KVM_CAP_ADJUST_CLOCK: 4035 r = KVM_CLOCK_TSC_STABLE; 4036 break; 4037 case KVM_CAP_X86_DISABLE_EXITS: 4038 r |= KVM_X86_DISABLE_EXITS_HLT | KVM_X86_DISABLE_EXITS_PAUSE | 4039 KVM_X86_DISABLE_EXITS_CSTATE; 4040 if(kvm_can_mwait_in_guest()) 4041 r |= KVM_X86_DISABLE_EXITS_MWAIT; 4042 break; 4043 case KVM_CAP_X86_SMM: 4044 /* SMBASE is usually relocated above 1M on modern chipsets, 4045 * and SMM handlers might indeed rely on 4G segment limits, 4046 * so do not report SMM to be available if real mode is 4047 * emulated via vm86 mode. Still, do not go to great lengths 4048 * to avoid userspace's usage of the feature, because it is a 4049 * fringe case that is not enabled except via specific settings 4050 * of the module parameters. 4051 */ 4052 r = static_call(kvm_x86_has_emulated_msr)(kvm, MSR_IA32_SMBASE); 4053 break; 4054 case KVM_CAP_VAPIC: 4055 r = !static_call(kvm_x86_cpu_has_accelerated_tpr)(); 4056 break; 4057 case KVM_CAP_NR_VCPUS: 4058 r = KVM_SOFT_MAX_VCPUS; 4059 break; 4060 case KVM_CAP_MAX_VCPUS: 4061 r = KVM_MAX_VCPUS; 4062 break; 4063 case KVM_CAP_MAX_VCPU_ID: 4064 r = KVM_MAX_VCPU_ID; 4065 break; 4066 case KVM_CAP_PV_MMU: /* obsolete */ 4067 r = 0; 4068 break; 4069 case KVM_CAP_MCE: 4070 r = KVM_MAX_MCE_BANKS; 4071 break; 4072 case KVM_CAP_XCRS: 4073 r = boot_cpu_has(X86_FEATURE_XSAVE); 4074 break; 4075 case KVM_CAP_TSC_CONTROL: 4076 r = kvm_has_tsc_control; 4077 break; 4078 case KVM_CAP_X2APIC_API: 4079 r = KVM_X2APIC_API_VALID_FLAGS; 4080 break; 4081 case KVM_CAP_NESTED_STATE: 4082 r = kvm_x86_ops.nested_ops->get_state ? 4083 kvm_x86_ops.nested_ops->get_state(NULL, NULL, 0) : 0; 4084 break; 4085 case KVM_CAP_HYPERV_DIRECT_TLBFLUSH: 4086 r = kvm_x86_ops.enable_direct_tlbflush != NULL; 4087 break; 4088 case KVM_CAP_HYPERV_ENLIGHTENED_VMCS: 4089 r = kvm_x86_ops.nested_ops->enable_evmcs != NULL; 4090 break; 4091 case KVM_CAP_SMALLER_MAXPHYADDR: 4092 r = (int) allow_smaller_maxphyaddr; 4093 break; 4094 case KVM_CAP_STEAL_TIME: 4095 r = sched_info_on(); 4096 break; 4097 case KVM_CAP_X86_BUS_LOCK_EXIT: 4098 if (kvm_has_bus_lock_exit) 4099 r = KVM_BUS_LOCK_DETECTION_OFF | 4100 KVM_BUS_LOCK_DETECTION_EXIT; 4101 else 4102 r = 0; 4103 break; 4104 default: 4105 break; 4106 } 4107 return r; 4108 4109 } 4110 4111 long kvm_arch_dev_ioctl(struct file *filp, 4112 unsigned int ioctl, unsigned long arg) 4113 { 4114 void __user *argp = (void __user *)arg; 4115 long r; 4116 4117 switch (ioctl) { 4118 case KVM_GET_MSR_INDEX_LIST: { 4119 struct kvm_msr_list __user *user_msr_list = argp; 4120 struct kvm_msr_list msr_list; 4121 unsigned n; 4122 4123 r = -EFAULT; 4124 if (copy_from_user(&msr_list, user_msr_list, sizeof(msr_list))) 4125 goto out; 4126 n = msr_list.nmsrs; 4127 msr_list.nmsrs = num_msrs_to_save + num_emulated_msrs; 4128 if (copy_to_user(user_msr_list, &msr_list, sizeof(msr_list))) 4129 goto out; 4130 r = -E2BIG; 4131 if (n < msr_list.nmsrs) 4132 goto out; 4133 r = -EFAULT; 4134 if (copy_to_user(user_msr_list->indices, &msrs_to_save, 4135 num_msrs_to_save * sizeof(u32))) 4136 goto out; 4137 if (copy_to_user(user_msr_list->indices + num_msrs_to_save, 4138 &emulated_msrs, 4139 num_emulated_msrs * sizeof(u32))) 4140 goto out; 4141 r = 0; 4142 break; 4143 } 4144 case KVM_GET_SUPPORTED_CPUID: 4145 case KVM_GET_EMULATED_CPUID: { 4146 struct kvm_cpuid2 __user *cpuid_arg = argp; 4147 struct kvm_cpuid2 cpuid; 4148 4149 r = -EFAULT; 4150 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid))) 4151 goto out; 4152 4153 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries, 4154 ioctl); 4155 if (r) 4156 goto out; 4157 4158 r = -EFAULT; 4159 if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid))) 4160 goto out; 4161 r = 0; 4162 break; 4163 } 4164 case KVM_X86_GET_MCE_CAP_SUPPORTED: 4165 r = -EFAULT; 4166 if (copy_to_user(argp, &kvm_mce_cap_supported, 4167 sizeof(kvm_mce_cap_supported))) 4168 goto out; 4169 r = 0; 4170 break; 4171 case KVM_GET_MSR_FEATURE_INDEX_LIST: { 4172 struct kvm_msr_list __user *user_msr_list = argp; 4173 struct kvm_msr_list msr_list; 4174 unsigned int n; 4175 4176 r = -EFAULT; 4177 if (copy_from_user(&msr_list, user_msr_list, sizeof(msr_list))) 4178 goto out; 4179 n = msr_list.nmsrs; 4180 msr_list.nmsrs = num_msr_based_features; 4181 if (copy_to_user(user_msr_list, &msr_list, sizeof(msr_list))) 4182 goto out; 4183 r = -E2BIG; 4184 if (n < msr_list.nmsrs) 4185 goto out; 4186 r = -EFAULT; 4187 if (copy_to_user(user_msr_list->indices, &msr_based_features, 4188 num_msr_based_features * sizeof(u32))) 4189 goto out; 4190 r = 0; 4191 break; 4192 } 4193 case KVM_GET_MSRS: 4194 r = msr_io(NULL, argp, do_get_msr_feature, 1); 4195 break; 4196 case KVM_GET_SUPPORTED_HV_CPUID: 4197 r = kvm_ioctl_get_supported_hv_cpuid(NULL, argp); 4198 break; 4199 default: 4200 r = -EINVAL; 4201 break; 4202 } 4203 out: 4204 return r; 4205 } 4206 4207 static void wbinvd_ipi(void *garbage) 4208 { 4209 wbinvd(); 4210 } 4211 4212 static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu) 4213 { 4214 return kvm_arch_has_noncoherent_dma(vcpu->kvm); 4215 } 4216 4217 void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu) 4218 { 4219 /* Address WBINVD may be executed by guest */ 4220 if (need_emulate_wbinvd(vcpu)) { 4221 if (static_call(kvm_x86_has_wbinvd_exit)()) 4222 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask); 4223 else if (vcpu->cpu != -1 && vcpu->cpu != cpu) 4224 smp_call_function_single(vcpu->cpu, 4225 wbinvd_ipi, NULL, 1); 4226 } 4227 4228 static_call(kvm_x86_vcpu_load)(vcpu, cpu); 4229 4230 /* Save host pkru register if supported */ 4231 vcpu->arch.host_pkru = read_pkru(); 4232 4233 /* Apply any externally detected TSC adjustments (due to suspend) */ 4234 if (unlikely(vcpu->arch.tsc_offset_adjustment)) { 4235 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment); 4236 vcpu->arch.tsc_offset_adjustment = 0; 4237 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 4238 } 4239 4240 if (unlikely(vcpu->cpu != cpu) || kvm_check_tsc_unstable()) { 4241 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 : 4242 rdtsc() - vcpu->arch.last_host_tsc; 4243 if (tsc_delta < 0) 4244 mark_tsc_unstable("KVM discovered backwards TSC"); 4245 4246 if (kvm_check_tsc_unstable()) { 4247 u64 offset = kvm_compute_l1_tsc_offset(vcpu, 4248 vcpu->arch.last_guest_tsc); 4249 kvm_vcpu_write_tsc_offset(vcpu, offset); 4250 vcpu->arch.tsc_catchup = 1; 4251 } 4252 4253 if (kvm_lapic_hv_timer_in_use(vcpu)) 4254 kvm_lapic_restart_hv_timer(vcpu); 4255 4256 /* 4257 * On a host with synchronized TSC, there is no need to update 4258 * kvmclock on vcpu->cpu migration 4259 */ 4260 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1) 4261 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu); 4262 if (vcpu->cpu != cpu) 4263 kvm_make_request(KVM_REQ_MIGRATE_TIMER, vcpu); 4264 vcpu->cpu = cpu; 4265 } 4266 4267 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu); 4268 } 4269 4270 static void kvm_steal_time_set_preempted(struct kvm_vcpu *vcpu) 4271 { 4272 struct kvm_host_map map; 4273 struct kvm_steal_time *st; 4274 4275 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED)) 4276 return; 4277 4278 if (vcpu->arch.st.preempted) 4279 return; 4280 4281 if (kvm_map_gfn(vcpu, vcpu->arch.st.msr_val >> PAGE_SHIFT, &map, 4282 &vcpu->arch.st.cache, true)) 4283 return; 4284 4285 st = map.hva + 4286 offset_in_page(vcpu->arch.st.msr_val & KVM_STEAL_VALID_BITS); 4287 4288 st->preempted = vcpu->arch.st.preempted = KVM_VCPU_PREEMPTED; 4289 4290 kvm_unmap_gfn(vcpu, &map, &vcpu->arch.st.cache, true, true); 4291 } 4292 4293 void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu) 4294 { 4295 int idx; 4296 4297 if (vcpu->preempted && !vcpu->arch.guest_state_protected) 4298 vcpu->arch.preempted_in_kernel = !static_call(kvm_x86_get_cpl)(vcpu); 4299 4300 /* 4301 * Take the srcu lock as memslots will be accessed to check the gfn 4302 * cache generation against the memslots generation. 4303 */ 4304 idx = srcu_read_lock(&vcpu->kvm->srcu); 4305 if (kvm_xen_msr_enabled(vcpu->kvm)) 4306 kvm_xen_runstate_set_preempted(vcpu); 4307 else 4308 kvm_steal_time_set_preempted(vcpu); 4309 srcu_read_unlock(&vcpu->kvm->srcu, idx); 4310 4311 static_call(kvm_x86_vcpu_put)(vcpu); 4312 vcpu->arch.last_host_tsc = rdtsc(); 4313 /* 4314 * If userspace has set any breakpoints or watchpoints, dr6 is restored 4315 * on every vmexit, but if not, we might have a stale dr6 from the 4316 * guest. do_debug expects dr6 to be cleared after it runs, do the same. 4317 */ 4318 set_debugreg(0, 6); 4319 } 4320 4321 static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu, 4322 struct kvm_lapic_state *s) 4323 { 4324 if (vcpu->arch.apicv_active) 4325 static_call(kvm_x86_sync_pir_to_irr)(vcpu); 4326 4327 return kvm_apic_get_state(vcpu, s); 4328 } 4329 4330 static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu, 4331 struct kvm_lapic_state *s) 4332 { 4333 int r; 4334 4335 r = kvm_apic_set_state(vcpu, s); 4336 if (r) 4337 return r; 4338 update_cr8_intercept(vcpu); 4339 4340 return 0; 4341 } 4342 4343 static int kvm_cpu_accept_dm_intr(struct kvm_vcpu *vcpu) 4344 { 4345 /* 4346 * We can accept userspace's request for interrupt injection 4347 * as long as we have a place to store the interrupt number. 4348 * The actual injection will happen when the CPU is able to 4349 * deliver the interrupt. 4350 */ 4351 if (kvm_cpu_has_extint(vcpu)) 4352 return false; 4353 4354 /* Acknowledging ExtINT does not happen if LINT0 is masked. */ 4355 return (!lapic_in_kernel(vcpu) || 4356 kvm_apic_accept_pic_intr(vcpu)); 4357 } 4358 4359 static int kvm_vcpu_ready_for_interrupt_injection(struct kvm_vcpu *vcpu) 4360 { 4361 return kvm_arch_interrupt_allowed(vcpu) && 4362 kvm_cpu_accept_dm_intr(vcpu); 4363 } 4364 4365 static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu, 4366 struct kvm_interrupt *irq) 4367 { 4368 if (irq->irq >= KVM_NR_INTERRUPTS) 4369 return -EINVAL; 4370 4371 if (!irqchip_in_kernel(vcpu->kvm)) { 4372 kvm_queue_interrupt(vcpu, irq->irq, false); 4373 kvm_make_request(KVM_REQ_EVENT, vcpu); 4374 return 0; 4375 } 4376 4377 /* 4378 * With in-kernel LAPIC, we only use this to inject EXTINT, so 4379 * fail for in-kernel 8259. 4380 */ 4381 if (pic_in_kernel(vcpu->kvm)) 4382 return -ENXIO; 4383 4384 if (vcpu->arch.pending_external_vector != -1) 4385 return -EEXIST; 4386 4387 vcpu->arch.pending_external_vector = irq->irq; 4388 kvm_make_request(KVM_REQ_EVENT, vcpu); 4389 return 0; 4390 } 4391 4392 static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu) 4393 { 4394 kvm_inject_nmi(vcpu); 4395 4396 return 0; 4397 } 4398 4399 static int kvm_vcpu_ioctl_smi(struct kvm_vcpu *vcpu) 4400 { 4401 kvm_make_request(KVM_REQ_SMI, vcpu); 4402 4403 return 0; 4404 } 4405 4406 static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu, 4407 struct kvm_tpr_access_ctl *tac) 4408 { 4409 if (tac->flags) 4410 return -EINVAL; 4411 vcpu->arch.tpr_access_reporting = !!tac->enabled; 4412 return 0; 4413 } 4414 4415 static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu, 4416 u64 mcg_cap) 4417 { 4418 int r; 4419 unsigned bank_num = mcg_cap & 0xff, bank; 4420 4421 r = -EINVAL; 4422 if (!bank_num || bank_num > KVM_MAX_MCE_BANKS) 4423 goto out; 4424 if (mcg_cap & ~(kvm_mce_cap_supported | 0xff | 0xff0000)) 4425 goto out; 4426 r = 0; 4427 vcpu->arch.mcg_cap = mcg_cap; 4428 /* Init IA32_MCG_CTL to all 1s */ 4429 if (mcg_cap & MCG_CTL_P) 4430 vcpu->arch.mcg_ctl = ~(u64)0; 4431 /* Init IA32_MCi_CTL to all 1s */ 4432 for (bank = 0; bank < bank_num; bank++) 4433 vcpu->arch.mce_banks[bank*4] = ~(u64)0; 4434 4435 static_call(kvm_x86_setup_mce)(vcpu); 4436 out: 4437 return r; 4438 } 4439 4440 static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu, 4441 struct kvm_x86_mce *mce) 4442 { 4443 u64 mcg_cap = vcpu->arch.mcg_cap; 4444 unsigned bank_num = mcg_cap & 0xff; 4445 u64 *banks = vcpu->arch.mce_banks; 4446 4447 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL)) 4448 return -EINVAL; 4449 /* 4450 * if IA32_MCG_CTL is not all 1s, the uncorrected error 4451 * reporting is disabled 4452 */ 4453 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) && 4454 vcpu->arch.mcg_ctl != ~(u64)0) 4455 return 0; 4456 banks += 4 * mce->bank; 4457 /* 4458 * if IA32_MCi_CTL is not all 1s, the uncorrected error 4459 * reporting is disabled for the bank 4460 */ 4461 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0) 4462 return 0; 4463 if (mce->status & MCI_STATUS_UC) { 4464 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) || 4465 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) { 4466 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); 4467 return 0; 4468 } 4469 if (banks[1] & MCI_STATUS_VAL) 4470 mce->status |= MCI_STATUS_OVER; 4471 banks[2] = mce->addr; 4472 banks[3] = mce->misc; 4473 vcpu->arch.mcg_status = mce->mcg_status; 4474 banks[1] = mce->status; 4475 kvm_queue_exception(vcpu, MC_VECTOR); 4476 } else if (!(banks[1] & MCI_STATUS_VAL) 4477 || !(banks[1] & MCI_STATUS_UC)) { 4478 if (banks[1] & MCI_STATUS_VAL) 4479 mce->status |= MCI_STATUS_OVER; 4480 banks[2] = mce->addr; 4481 banks[3] = mce->misc; 4482 banks[1] = mce->status; 4483 } else 4484 banks[1] |= MCI_STATUS_OVER; 4485 return 0; 4486 } 4487 4488 static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu, 4489 struct kvm_vcpu_events *events) 4490 { 4491 process_nmi(vcpu); 4492 4493 if (kvm_check_request(KVM_REQ_SMI, vcpu)) 4494 process_smi(vcpu); 4495 4496 /* 4497 * In guest mode, payload delivery should be deferred, 4498 * so that the L1 hypervisor can intercept #PF before 4499 * CR2 is modified (or intercept #DB before DR6 is 4500 * modified under nVMX). Unless the per-VM capability, 4501 * KVM_CAP_EXCEPTION_PAYLOAD, is set, we may not defer the delivery of 4502 * an exception payload and handle after a KVM_GET_VCPU_EVENTS. Since we 4503 * opportunistically defer the exception payload, deliver it if the 4504 * capability hasn't been requested before processing a 4505 * KVM_GET_VCPU_EVENTS. 4506 */ 4507 if (!vcpu->kvm->arch.exception_payload_enabled && 4508 vcpu->arch.exception.pending && vcpu->arch.exception.has_payload) 4509 kvm_deliver_exception_payload(vcpu); 4510 4511 /* 4512 * The API doesn't provide the instruction length for software 4513 * exceptions, so don't report them. As long as the guest RIP 4514 * isn't advanced, we should expect to encounter the exception 4515 * again. 4516 */ 4517 if (kvm_exception_is_soft(vcpu->arch.exception.nr)) { 4518 events->exception.injected = 0; 4519 events->exception.pending = 0; 4520 } else { 4521 events->exception.injected = vcpu->arch.exception.injected; 4522 events->exception.pending = vcpu->arch.exception.pending; 4523 /* 4524 * For ABI compatibility, deliberately conflate 4525 * pending and injected exceptions when 4526 * KVM_CAP_EXCEPTION_PAYLOAD isn't enabled. 4527 */ 4528 if (!vcpu->kvm->arch.exception_payload_enabled) 4529 events->exception.injected |= 4530 vcpu->arch.exception.pending; 4531 } 4532 events->exception.nr = vcpu->arch.exception.nr; 4533 events->exception.has_error_code = vcpu->arch.exception.has_error_code; 4534 events->exception.error_code = vcpu->arch.exception.error_code; 4535 events->exception_has_payload = vcpu->arch.exception.has_payload; 4536 events->exception_payload = vcpu->arch.exception.payload; 4537 4538 events->interrupt.injected = 4539 vcpu->arch.interrupt.injected && !vcpu->arch.interrupt.soft; 4540 events->interrupt.nr = vcpu->arch.interrupt.nr; 4541 events->interrupt.soft = 0; 4542 events->interrupt.shadow = static_call(kvm_x86_get_interrupt_shadow)(vcpu); 4543 4544 events->nmi.injected = vcpu->arch.nmi_injected; 4545 events->nmi.pending = vcpu->arch.nmi_pending != 0; 4546 events->nmi.masked = static_call(kvm_x86_get_nmi_mask)(vcpu); 4547 events->nmi.pad = 0; 4548 4549 events->sipi_vector = 0; /* never valid when reporting to user space */ 4550 4551 events->smi.smm = is_smm(vcpu); 4552 events->smi.pending = vcpu->arch.smi_pending; 4553 events->smi.smm_inside_nmi = 4554 !!(vcpu->arch.hflags & HF_SMM_INSIDE_NMI_MASK); 4555 events->smi.latched_init = kvm_lapic_latched_init(vcpu); 4556 4557 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING 4558 | KVM_VCPUEVENT_VALID_SHADOW 4559 | KVM_VCPUEVENT_VALID_SMM); 4560 if (vcpu->kvm->arch.exception_payload_enabled) 4561 events->flags |= KVM_VCPUEVENT_VALID_PAYLOAD; 4562 4563 memset(&events->reserved, 0, sizeof(events->reserved)); 4564 } 4565 4566 static void kvm_smm_changed(struct kvm_vcpu *vcpu, bool entering_smm); 4567 4568 static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu, 4569 struct kvm_vcpu_events *events) 4570 { 4571 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING 4572 | KVM_VCPUEVENT_VALID_SIPI_VECTOR 4573 | KVM_VCPUEVENT_VALID_SHADOW 4574 | KVM_VCPUEVENT_VALID_SMM 4575 | KVM_VCPUEVENT_VALID_PAYLOAD)) 4576 return -EINVAL; 4577 4578 if (events->flags & KVM_VCPUEVENT_VALID_PAYLOAD) { 4579 if (!vcpu->kvm->arch.exception_payload_enabled) 4580 return -EINVAL; 4581 if (events->exception.pending) 4582 events->exception.injected = 0; 4583 else 4584 events->exception_has_payload = 0; 4585 } else { 4586 events->exception.pending = 0; 4587 events->exception_has_payload = 0; 4588 } 4589 4590 if ((events->exception.injected || events->exception.pending) && 4591 (events->exception.nr > 31 || events->exception.nr == NMI_VECTOR)) 4592 return -EINVAL; 4593 4594 /* INITs are latched while in SMM */ 4595 if (events->flags & KVM_VCPUEVENT_VALID_SMM && 4596 (events->smi.smm || events->smi.pending) && 4597 vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) 4598 return -EINVAL; 4599 4600 process_nmi(vcpu); 4601 vcpu->arch.exception.injected = events->exception.injected; 4602 vcpu->arch.exception.pending = events->exception.pending; 4603 vcpu->arch.exception.nr = events->exception.nr; 4604 vcpu->arch.exception.has_error_code = events->exception.has_error_code; 4605 vcpu->arch.exception.error_code = events->exception.error_code; 4606 vcpu->arch.exception.has_payload = events->exception_has_payload; 4607 vcpu->arch.exception.payload = events->exception_payload; 4608 4609 vcpu->arch.interrupt.injected = events->interrupt.injected; 4610 vcpu->arch.interrupt.nr = events->interrupt.nr; 4611 vcpu->arch.interrupt.soft = events->interrupt.soft; 4612 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW) 4613 static_call(kvm_x86_set_interrupt_shadow)(vcpu, 4614 events->interrupt.shadow); 4615 4616 vcpu->arch.nmi_injected = events->nmi.injected; 4617 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING) 4618 vcpu->arch.nmi_pending = events->nmi.pending; 4619 static_call(kvm_x86_set_nmi_mask)(vcpu, events->nmi.masked); 4620 4621 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR && 4622 lapic_in_kernel(vcpu)) 4623 vcpu->arch.apic->sipi_vector = events->sipi_vector; 4624 4625 if (events->flags & KVM_VCPUEVENT_VALID_SMM) { 4626 if (!!(vcpu->arch.hflags & HF_SMM_MASK) != events->smi.smm) 4627 kvm_smm_changed(vcpu, events->smi.smm); 4628 4629 vcpu->arch.smi_pending = events->smi.pending; 4630 4631 if (events->smi.smm) { 4632 if (events->smi.smm_inside_nmi) 4633 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK; 4634 else 4635 vcpu->arch.hflags &= ~HF_SMM_INSIDE_NMI_MASK; 4636 } 4637 4638 if (lapic_in_kernel(vcpu)) { 4639 if (events->smi.latched_init) 4640 set_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events); 4641 else 4642 clear_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events); 4643 } 4644 } 4645 4646 kvm_make_request(KVM_REQ_EVENT, vcpu); 4647 4648 return 0; 4649 } 4650 4651 static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu, 4652 struct kvm_debugregs *dbgregs) 4653 { 4654 unsigned long val; 4655 4656 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db)); 4657 kvm_get_dr(vcpu, 6, &val); 4658 dbgregs->dr6 = val; 4659 dbgregs->dr7 = vcpu->arch.dr7; 4660 dbgregs->flags = 0; 4661 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved)); 4662 } 4663 4664 static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu, 4665 struct kvm_debugregs *dbgregs) 4666 { 4667 if (dbgregs->flags) 4668 return -EINVAL; 4669 4670 if (!kvm_dr6_valid(dbgregs->dr6)) 4671 return -EINVAL; 4672 if (!kvm_dr7_valid(dbgregs->dr7)) 4673 return -EINVAL; 4674 4675 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db)); 4676 kvm_update_dr0123(vcpu); 4677 vcpu->arch.dr6 = dbgregs->dr6; 4678 vcpu->arch.dr7 = dbgregs->dr7; 4679 kvm_update_dr7(vcpu); 4680 4681 return 0; 4682 } 4683 4684 #define XSTATE_COMPACTION_ENABLED (1ULL << 63) 4685 4686 static void fill_xsave(u8 *dest, struct kvm_vcpu *vcpu) 4687 { 4688 struct xregs_state *xsave = &vcpu->arch.guest_fpu->state.xsave; 4689 u64 xstate_bv = xsave->header.xfeatures; 4690 u64 valid; 4691 4692 /* 4693 * Copy legacy XSAVE area, to avoid complications with CPUID 4694 * leaves 0 and 1 in the loop below. 4695 */ 4696 memcpy(dest, xsave, XSAVE_HDR_OFFSET); 4697 4698 /* Set XSTATE_BV */ 4699 xstate_bv &= vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FPSSE; 4700 *(u64 *)(dest + XSAVE_HDR_OFFSET) = xstate_bv; 4701 4702 /* 4703 * Copy each region from the possibly compacted offset to the 4704 * non-compacted offset. 4705 */ 4706 valid = xstate_bv & ~XFEATURE_MASK_FPSSE; 4707 while (valid) { 4708 u32 size, offset, ecx, edx; 4709 u64 xfeature_mask = valid & -valid; 4710 int xfeature_nr = fls64(xfeature_mask) - 1; 4711 void *src; 4712 4713 cpuid_count(XSTATE_CPUID, xfeature_nr, 4714 &size, &offset, &ecx, &edx); 4715 4716 if (xfeature_nr == XFEATURE_PKRU) { 4717 memcpy(dest + offset, &vcpu->arch.pkru, 4718 sizeof(vcpu->arch.pkru)); 4719 } else { 4720 src = get_xsave_addr(xsave, xfeature_nr); 4721 if (src) 4722 memcpy(dest + offset, src, size); 4723 } 4724 4725 valid -= xfeature_mask; 4726 } 4727 } 4728 4729 static void load_xsave(struct kvm_vcpu *vcpu, u8 *src) 4730 { 4731 struct xregs_state *xsave = &vcpu->arch.guest_fpu->state.xsave; 4732 u64 xstate_bv = *(u64 *)(src + XSAVE_HDR_OFFSET); 4733 u64 valid; 4734 4735 /* 4736 * Copy legacy XSAVE area, to avoid complications with CPUID 4737 * leaves 0 and 1 in the loop below. 4738 */ 4739 memcpy(xsave, src, XSAVE_HDR_OFFSET); 4740 4741 /* Set XSTATE_BV and possibly XCOMP_BV. */ 4742 xsave->header.xfeatures = xstate_bv; 4743 if (boot_cpu_has(X86_FEATURE_XSAVES)) 4744 xsave->header.xcomp_bv = host_xcr0 | XSTATE_COMPACTION_ENABLED; 4745 4746 /* 4747 * Copy each region from the non-compacted offset to the 4748 * possibly compacted offset. 4749 */ 4750 valid = xstate_bv & ~XFEATURE_MASK_FPSSE; 4751 while (valid) { 4752 u32 size, offset, ecx, edx; 4753 u64 xfeature_mask = valid & -valid; 4754 int xfeature_nr = fls64(xfeature_mask) - 1; 4755 4756 cpuid_count(XSTATE_CPUID, xfeature_nr, 4757 &size, &offset, &ecx, &edx); 4758 4759 if (xfeature_nr == XFEATURE_PKRU) { 4760 memcpy(&vcpu->arch.pkru, src + offset, 4761 sizeof(vcpu->arch.pkru)); 4762 } else { 4763 void *dest = get_xsave_addr(xsave, xfeature_nr); 4764 4765 if (dest) 4766 memcpy(dest, src + offset, size); 4767 } 4768 4769 valid -= xfeature_mask; 4770 } 4771 } 4772 4773 static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu, 4774 struct kvm_xsave *guest_xsave) 4775 { 4776 if (!vcpu->arch.guest_fpu) 4777 return; 4778 4779 if (boot_cpu_has(X86_FEATURE_XSAVE)) { 4780 memset(guest_xsave, 0, sizeof(struct kvm_xsave)); 4781 fill_xsave((u8 *) guest_xsave->region, vcpu); 4782 } else { 4783 memcpy(guest_xsave->region, 4784 &vcpu->arch.guest_fpu->state.fxsave, 4785 sizeof(struct fxregs_state)); 4786 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] = 4787 XFEATURE_MASK_FPSSE; 4788 } 4789 } 4790 4791 #define XSAVE_MXCSR_OFFSET 24 4792 4793 static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu, 4794 struct kvm_xsave *guest_xsave) 4795 { 4796 u64 xstate_bv; 4797 u32 mxcsr; 4798 4799 if (!vcpu->arch.guest_fpu) 4800 return 0; 4801 4802 xstate_bv = *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)]; 4803 mxcsr = *(u32 *)&guest_xsave->region[XSAVE_MXCSR_OFFSET / sizeof(u32)]; 4804 4805 if (boot_cpu_has(X86_FEATURE_XSAVE)) { 4806 /* 4807 * Here we allow setting states that are not present in 4808 * CPUID leaf 0xD, index 0, EDX:EAX. This is for compatibility 4809 * with old userspace. 4810 */ 4811 if (xstate_bv & ~supported_xcr0 || mxcsr & ~mxcsr_feature_mask) 4812 return -EINVAL; 4813 load_xsave(vcpu, (u8 *)guest_xsave->region); 4814 } else { 4815 if (xstate_bv & ~XFEATURE_MASK_FPSSE || 4816 mxcsr & ~mxcsr_feature_mask) 4817 return -EINVAL; 4818 memcpy(&vcpu->arch.guest_fpu->state.fxsave, 4819 guest_xsave->region, sizeof(struct fxregs_state)); 4820 } 4821 return 0; 4822 } 4823 4824 static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu, 4825 struct kvm_xcrs *guest_xcrs) 4826 { 4827 if (!boot_cpu_has(X86_FEATURE_XSAVE)) { 4828 guest_xcrs->nr_xcrs = 0; 4829 return; 4830 } 4831 4832 guest_xcrs->nr_xcrs = 1; 4833 guest_xcrs->flags = 0; 4834 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK; 4835 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0; 4836 } 4837 4838 static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu, 4839 struct kvm_xcrs *guest_xcrs) 4840 { 4841 int i, r = 0; 4842 4843 if (!boot_cpu_has(X86_FEATURE_XSAVE)) 4844 return -EINVAL; 4845 4846 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags) 4847 return -EINVAL; 4848 4849 for (i = 0; i < guest_xcrs->nr_xcrs; i++) 4850 /* Only support XCR0 currently */ 4851 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) { 4852 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK, 4853 guest_xcrs->xcrs[i].value); 4854 break; 4855 } 4856 if (r) 4857 r = -EINVAL; 4858 return r; 4859 } 4860 4861 /* 4862 * kvm_set_guest_paused() indicates to the guest kernel that it has been 4863 * stopped by the hypervisor. This function will be called from the host only. 4864 * EINVAL is returned when the host attempts to set the flag for a guest that 4865 * does not support pv clocks. 4866 */ 4867 static int kvm_set_guest_paused(struct kvm_vcpu *vcpu) 4868 { 4869 if (!vcpu->arch.pv_time_enabled) 4870 return -EINVAL; 4871 vcpu->arch.pvclock_set_guest_stopped_request = true; 4872 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 4873 return 0; 4874 } 4875 4876 static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu, 4877 struct kvm_enable_cap *cap) 4878 { 4879 int r; 4880 uint16_t vmcs_version; 4881 void __user *user_ptr; 4882 4883 if (cap->flags) 4884 return -EINVAL; 4885 4886 switch (cap->cap) { 4887 case KVM_CAP_HYPERV_SYNIC2: 4888 if (cap->args[0]) 4889 return -EINVAL; 4890 fallthrough; 4891 4892 case KVM_CAP_HYPERV_SYNIC: 4893 if (!irqchip_in_kernel(vcpu->kvm)) 4894 return -EINVAL; 4895 return kvm_hv_activate_synic(vcpu, cap->cap == 4896 KVM_CAP_HYPERV_SYNIC2); 4897 case KVM_CAP_HYPERV_ENLIGHTENED_VMCS: 4898 if (!kvm_x86_ops.nested_ops->enable_evmcs) 4899 return -ENOTTY; 4900 r = kvm_x86_ops.nested_ops->enable_evmcs(vcpu, &vmcs_version); 4901 if (!r) { 4902 user_ptr = (void __user *)(uintptr_t)cap->args[0]; 4903 if (copy_to_user(user_ptr, &vmcs_version, 4904 sizeof(vmcs_version))) 4905 r = -EFAULT; 4906 } 4907 return r; 4908 case KVM_CAP_HYPERV_DIRECT_TLBFLUSH: 4909 if (!kvm_x86_ops.enable_direct_tlbflush) 4910 return -ENOTTY; 4911 4912 return static_call(kvm_x86_enable_direct_tlbflush)(vcpu); 4913 4914 case KVM_CAP_HYPERV_ENFORCE_CPUID: 4915 return kvm_hv_set_enforce_cpuid(vcpu, cap->args[0]); 4916 4917 case KVM_CAP_ENFORCE_PV_FEATURE_CPUID: 4918 vcpu->arch.pv_cpuid.enforce = cap->args[0]; 4919 if (vcpu->arch.pv_cpuid.enforce) 4920 kvm_update_pv_runtime(vcpu); 4921 4922 return 0; 4923 default: 4924 return -EINVAL; 4925 } 4926 } 4927 4928 long kvm_arch_vcpu_ioctl(struct file *filp, 4929 unsigned int ioctl, unsigned long arg) 4930 { 4931 struct kvm_vcpu *vcpu = filp->private_data; 4932 void __user *argp = (void __user *)arg; 4933 int r; 4934 union { 4935 struct kvm_sregs2 *sregs2; 4936 struct kvm_lapic_state *lapic; 4937 struct kvm_xsave *xsave; 4938 struct kvm_xcrs *xcrs; 4939 void *buffer; 4940 } u; 4941 4942 vcpu_load(vcpu); 4943 4944 u.buffer = NULL; 4945 switch (ioctl) { 4946 case KVM_GET_LAPIC: { 4947 r = -EINVAL; 4948 if (!lapic_in_kernel(vcpu)) 4949 goto out; 4950 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), 4951 GFP_KERNEL_ACCOUNT); 4952 4953 r = -ENOMEM; 4954 if (!u.lapic) 4955 goto out; 4956 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic); 4957 if (r) 4958 goto out; 4959 r = -EFAULT; 4960 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state))) 4961 goto out; 4962 r = 0; 4963 break; 4964 } 4965 case KVM_SET_LAPIC: { 4966 r = -EINVAL; 4967 if (!lapic_in_kernel(vcpu)) 4968 goto out; 4969 u.lapic = memdup_user(argp, sizeof(*u.lapic)); 4970 if (IS_ERR(u.lapic)) { 4971 r = PTR_ERR(u.lapic); 4972 goto out_nofree; 4973 } 4974 4975 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic); 4976 break; 4977 } 4978 case KVM_INTERRUPT: { 4979 struct kvm_interrupt irq; 4980 4981 r = -EFAULT; 4982 if (copy_from_user(&irq, argp, sizeof(irq))) 4983 goto out; 4984 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq); 4985 break; 4986 } 4987 case KVM_NMI: { 4988 r = kvm_vcpu_ioctl_nmi(vcpu); 4989 break; 4990 } 4991 case KVM_SMI: { 4992 r = kvm_vcpu_ioctl_smi(vcpu); 4993 break; 4994 } 4995 case KVM_SET_CPUID: { 4996 struct kvm_cpuid __user *cpuid_arg = argp; 4997 struct kvm_cpuid cpuid; 4998 4999 r = -EFAULT; 5000 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid))) 5001 goto out; 5002 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries); 5003 break; 5004 } 5005 case KVM_SET_CPUID2: { 5006 struct kvm_cpuid2 __user *cpuid_arg = argp; 5007 struct kvm_cpuid2 cpuid; 5008 5009 r = -EFAULT; 5010 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid))) 5011 goto out; 5012 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid, 5013 cpuid_arg->entries); 5014 break; 5015 } 5016 case KVM_GET_CPUID2: { 5017 struct kvm_cpuid2 __user *cpuid_arg = argp; 5018 struct kvm_cpuid2 cpuid; 5019 5020 r = -EFAULT; 5021 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid))) 5022 goto out; 5023 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid, 5024 cpuid_arg->entries); 5025 if (r) 5026 goto out; 5027 r = -EFAULT; 5028 if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid))) 5029 goto out; 5030 r = 0; 5031 break; 5032 } 5033 case KVM_GET_MSRS: { 5034 int idx = srcu_read_lock(&vcpu->kvm->srcu); 5035 r = msr_io(vcpu, argp, do_get_msr, 1); 5036 srcu_read_unlock(&vcpu->kvm->srcu, idx); 5037 break; 5038 } 5039 case KVM_SET_MSRS: { 5040 int idx = srcu_read_lock(&vcpu->kvm->srcu); 5041 r = msr_io(vcpu, argp, do_set_msr, 0); 5042 srcu_read_unlock(&vcpu->kvm->srcu, idx); 5043 break; 5044 } 5045 case KVM_TPR_ACCESS_REPORTING: { 5046 struct kvm_tpr_access_ctl tac; 5047 5048 r = -EFAULT; 5049 if (copy_from_user(&tac, argp, sizeof(tac))) 5050 goto out; 5051 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac); 5052 if (r) 5053 goto out; 5054 r = -EFAULT; 5055 if (copy_to_user(argp, &tac, sizeof(tac))) 5056 goto out; 5057 r = 0; 5058 break; 5059 }; 5060 case KVM_SET_VAPIC_ADDR: { 5061 struct kvm_vapic_addr va; 5062 int idx; 5063 5064 r = -EINVAL; 5065 if (!lapic_in_kernel(vcpu)) 5066 goto out; 5067 r = -EFAULT; 5068 if (copy_from_user(&va, argp, sizeof(va))) 5069 goto out; 5070 idx = srcu_read_lock(&vcpu->kvm->srcu); 5071 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr); 5072 srcu_read_unlock(&vcpu->kvm->srcu, idx); 5073 break; 5074 } 5075 case KVM_X86_SETUP_MCE: { 5076 u64 mcg_cap; 5077 5078 r = -EFAULT; 5079 if (copy_from_user(&mcg_cap, argp, sizeof(mcg_cap))) 5080 goto out; 5081 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap); 5082 break; 5083 } 5084 case KVM_X86_SET_MCE: { 5085 struct kvm_x86_mce mce; 5086 5087 r = -EFAULT; 5088 if (copy_from_user(&mce, argp, sizeof(mce))) 5089 goto out; 5090 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce); 5091 break; 5092 } 5093 case KVM_GET_VCPU_EVENTS: { 5094 struct kvm_vcpu_events events; 5095 5096 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events); 5097 5098 r = -EFAULT; 5099 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events))) 5100 break; 5101 r = 0; 5102 break; 5103 } 5104 case KVM_SET_VCPU_EVENTS: { 5105 struct kvm_vcpu_events events; 5106 5107 r = -EFAULT; 5108 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events))) 5109 break; 5110 5111 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events); 5112 break; 5113 } 5114 case KVM_GET_DEBUGREGS: { 5115 struct kvm_debugregs dbgregs; 5116 5117 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs); 5118 5119 r = -EFAULT; 5120 if (copy_to_user(argp, &dbgregs, 5121 sizeof(struct kvm_debugregs))) 5122 break; 5123 r = 0; 5124 break; 5125 } 5126 case KVM_SET_DEBUGREGS: { 5127 struct kvm_debugregs dbgregs; 5128 5129 r = -EFAULT; 5130 if (copy_from_user(&dbgregs, argp, 5131 sizeof(struct kvm_debugregs))) 5132 break; 5133 5134 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs); 5135 break; 5136 } 5137 case KVM_GET_XSAVE: { 5138 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL_ACCOUNT); 5139 r = -ENOMEM; 5140 if (!u.xsave) 5141 break; 5142 5143 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave); 5144 5145 r = -EFAULT; 5146 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave))) 5147 break; 5148 r = 0; 5149 break; 5150 } 5151 case KVM_SET_XSAVE: { 5152 u.xsave = memdup_user(argp, sizeof(*u.xsave)); 5153 if (IS_ERR(u.xsave)) { 5154 r = PTR_ERR(u.xsave); 5155 goto out_nofree; 5156 } 5157 5158 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave); 5159 break; 5160 } 5161 case KVM_GET_XCRS: { 5162 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL_ACCOUNT); 5163 r = -ENOMEM; 5164 if (!u.xcrs) 5165 break; 5166 5167 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs); 5168 5169 r = -EFAULT; 5170 if (copy_to_user(argp, u.xcrs, 5171 sizeof(struct kvm_xcrs))) 5172 break; 5173 r = 0; 5174 break; 5175 } 5176 case KVM_SET_XCRS: { 5177 u.xcrs = memdup_user(argp, sizeof(*u.xcrs)); 5178 if (IS_ERR(u.xcrs)) { 5179 r = PTR_ERR(u.xcrs); 5180 goto out_nofree; 5181 } 5182 5183 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs); 5184 break; 5185 } 5186 case KVM_SET_TSC_KHZ: { 5187 u32 user_tsc_khz; 5188 5189 r = -EINVAL; 5190 user_tsc_khz = (u32)arg; 5191 5192 if (kvm_has_tsc_control && 5193 user_tsc_khz >= kvm_max_guest_tsc_khz) 5194 goto out; 5195 5196 if (user_tsc_khz == 0) 5197 user_tsc_khz = tsc_khz; 5198 5199 if (!kvm_set_tsc_khz(vcpu, user_tsc_khz)) 5200 r = 0; 5201 5202 goto out; 5203 } 5204 case KVM_GET_TSC_KHZ: { 5205 r = vcpu->arch.virtual_tsc_khz; 5206 goto out; 5207 } 5208 case KVM_KVMCLOCK_CTRL: { 5209 r = kvm_set_guest_paused(vcpu); 5210 goto out; 5211 } 5212 case KVM_ENABLE_CAP: { 5213 struct kvm_enable_cap cap; 5214 5215 r = -EFAULT; 5216 if (copy_from_user(&cap, argp, sizeof(cap))) 5217 goto out; 5218 r = kvm_vcpu_ioctl_enable_cap(vcpu, &cap); 5219 break; 5220 } 5221 case KVM_GET_NESTED_STATE: { 5222 struct kvm_nested_state __user *user_kvm_nested_state = argp; 5223 u32 user_data_size; 5224 5225 r = -EINVAL; 5226 if (!kvm_x86_ops.nested_ops->get_state) 5227 break; 5228 5229 BUILD_BUG_ON(sizeof(user_data_size) != sizeof(user_kvm_nested_state->size)); 5230 r = -EFAULT; 5231 if (get_user(user_data_size, &user_kvm_nested_state->size)) 5232 break; 5233 5234 r = kvm_x86_ops.nested_ops->get_state(vcpu, user_kvm_nested_state, 5235 user_data_size); 5236 if (r < 0) 5237 break; 5238 5239 if (r > user_data_size) { 5240 if (put_user(r, &user_kvm_nested_state->size)) 5241 r = -EFAULT; 5242 else 5243 r = -E2BIG; 5244 break; 5245 } 5246 5247 r = 0; 5248 break; 5249 } 5250 case KVM_SET_NESTED_STATE: { 5251 struct kvm_nested_state __user *user_kvm_nested_state = argp; 5252 struct kvm_nested_state kvm_state; 5253 int idx; 5254 5255 r = -EINVAL; 5256 if (!kvm_x86_ops.nested_ops->set_state) 5257 break; 5258 5259 r = -EFAULT; 5260 if (copy_from_user(&kvm_state, user_kvm_nested_state, sizeof(kvm_state))) 5261 break; 5262 5263 r = -EINVAL; 5264 if (kvm_state.size < sizeof(kvm_state)) 5265 break; 5266 5267 if (kvm_state.flags & 5268 ~(KVM_STATE_NESTED_RUN_PENDING | KVM_STATE_NESTED_GUEST_MODE 5269 | KVM_STATE_NESTED_EVMCS | KVM_STATE_NESTED_MTF_PENDING 5270 | KVM_STATE_NESTED_GIF_SET)) 5271 break; 5272 5273 /* nested_run_pending implies guest_mode. */ 5274 if ((kvm_state.flags & KVM_STATE_NESTED_RUN_PENDING) 5275 && !(kvm_state.flags & KVM_STATE_NESTED_GUEST_MODE)) 5276 break; 5277 5278 idx = srcu_read_lock(&vcpu->kvm->srcu); 5279 r = kvm_x86_ops.nested_ops->set_state(vcpu, user_kvm_nested_state, &kvm_state); 5280 srcu_read_unlock(&vcpu->kvm->srcu, idx); 5281 break; 5282 } 5283 case KVM_GET_SUPPORTED_HV_CPUID: 5284 r = kvm_ioctl_get_supported_hv_cpuid(vcpu, argp); 5285 break; 5286 #ifdef CONFIG_KVM_XEN 5287 case KVM_XEN_VCPU_GET_ATTR: { 5288 struct kvm_xen_vcpu_attr xva; 5289 5290 r = -EFAULT; 5291 if (copy_from_user(&xva, argp, sizeof(xva))) 5292 goto out; 5293 r = kvm_xen_vcpu_get_attr(vcpu, &xva); 5294 if (!r && copy_to_user(argp, &xva, sizeof(xva))) 5295 r = -EFAULT; 5296 break; 5297 } 5298 case KVM_XEN_VCPU_SET_ATTR: { 5299 struct kvm_xen_vcpu_attr xva; 5300 5301 r = -EFAULT; 5302 if (copy_from_user(&xva, argp, sizeof(xva))) 5303 goto out; 5304 r = kvm_xen_vcpu_set_attr(vcpu, &xva); 5305 break; 5306 } 5307 #endif 5308 case KVM_GET_SREGS2: { 5309 u.sregs2 = kzalloc(sizeof(struct kvm_sregs2), GFP_KERNEL); 5310 r = -ENOMEM; 5311 if (!u.sregs2) 5312 goto out; 5313 __get_sregs2(vcpu, u.sregs2); 5314 r = -EFAULT; 5315 if (copy_to_user(argp, u.sregs2, sizeof(struct kvm_sregs2))) 5316 goto out; 5317 r = 0; 5318 break; 5319 } 5320 case KVM_SET_SREGS2: { 5321 u.sregs2 = memdup_user(argp, sizeof(struct kvm_sregs2)); 5322 if (IS_ERR(u.sregs2)) { 5323 r = PTR_ERR(u.sregs2); 5324 u.sregs2 = NULL; 5325 goto out; 5326 } 5327 r = __set_sregs2(vcpu, u.sregs2); 5328 break; 5329 } 5330 default: 5331 r = -EINVAL; 5332 } 5333 out: 5334 kfree(u.buffer); 5335 out_nofree: 5336 vcpu_put(vcpu); 5337 return r; 5338 } 5339 5340 vm_fault_t kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf) 5341 { 5342 return VM_FAULT_SIGBUS; 5343 } 5344 5345 static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr) 5346 { 5347 int ret; 5348 5349 if (addr > (unsigned int)(-3 * PAGE_SIZE)) 5350 return -EINVAL; 5351 ret = static_call(kvm_x86_set_tss_addr)(kvm, addr); 5352 return ret; 5353 } 5354 5355 static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm, 5356 u64 ident_addr) 5357 { 5358 return static_call(kvm_x86_set_identity_map_addr)(kvm, ident_addr); 5359 } 5360 5361 static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm, 5362 unsigned long kvm_nr_mmu_pages) 5363 { 5364 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES) 5365 return -EINVAL; 5366 5367 mutex_lock(&kvm->slots_lock); 5368 5369 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages); 5370 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages; 5371 5372 mutex_unlock(&kvm->slots_lock); 5373 return 0; 5374 } 5375 5376 static unsigned long kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm) 5377 { 5378 return kvm->arch.n_max_mmu_pages; 5379 } 5380 5381 static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip) 5382 { 5383 struct kvm_pic *pic = kvm->arch.vpic; 5384 int r; 5385 5386 r = 0; 5387 switch (chip->chip_id) { 5388 case KVM_IRQCHIP_PIC_MASTER: 5389 memcpy(&chip->chip.pic, &pic->pics[0], 5390 sizeof(struct kvm_pic_state)); 5391 break; 5392 case KVM_IRQCHIP_PIC_SLAVE: 5393 memcpy(&chip->chip.pic, &pic->pics[1], 5394 sizeof(struct kvm_pic_state)); 5395 break; 5396 case KVM_IRQCHIP_IOAPIC: 5397 kvm_get_ioapic(kvm, &chip->chip.ioapic); 5398 break; 5399 default: 5400 r = -EINVAL; 5401 break; 5402 } 5403 return r; 5404 } 5405 5406 static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip) 5407 { 5408 struct kvm_pic *pic = kvm->arch.vpic; 5409 int r; 5410 5411 r = 0; 5412 switch (chip->chip_id) { 5413 case KVM_IRQCHIP_PIC_MASTER: 5414 spin_lock(&pic->lock); 5415 memcpy(&pic->pics[0], &chip->chip.pic, 5416 sizeof(struct kvm_pic_state)); 5417 spin_unlock(&pic->lock); 5418 break; 5419 case KVM_IRQCHIP_PIC_SLAVE: 5420 spin_lock(&pic->lock); 5421 memcpy(&pic->pics[1], &chip->chip.pic, 5422 sizeof(struct kvm_pic_state)); 5423 spin_unlock(&pic->lock); 5424 break; 5425 case KVM_IRQCHIP_IOAPIC: 5426 kvm_set_ioapic(kvm, &chip->chip.ioapic); 5427 break; 5428 default: 5429 r = -EINVAL; 5430 break; 5431 } 5432 kvm_pic_update_irq(pic); 5433 return r; 5434 } 5435 5436 static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps) 5437 { 5438 struct kvm_kpit_state *kps = &kvm->arch.vpit->pit_state; 5439 5440 BUILD_BUG_ON(sizeof(*ps) != sizeof(kps->channels)); 5441 5442 mutex_lock(&kps->lock); 5443 memcpy(ps, &kps->channels, sizeof(*ps)); 5444 mutex_unlock(&kps->lock); 5445 return 0; 5446 } 5447 5448 static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps) 5449 { 5450 int i; 5451 struct kvm_pit *pit = kvm->arch.vpit; 5452 5453 mutex_lock(&pit->pit_state.lock); 5454 memcpy(&pit->pit_state.channels, ps, sizeof(*ps)); 5455 for (i = 0; i < 3; i++) 5456 kvm_pit_load_count(pit, i, ps->channels[i].count, 0); 5457 mutex_unlock(&pit->pit_state.lock); 5458 return 0; 5459 } 5460 5461 static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps) 5462 { 5463 mutex_lock(&kvm->arch.vpit->pit_state.lock); 5464 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels, 5465 sizeof(ps->channels)); 5466 ps->flags = kvm->arch.vpit->pit_state.flags; 5467 mutex_unlock(&kvm->arch.vpit->pit_state.lock); 5468 memset(&ps->reserved, 0, sizeof(ps->reserved)); 5469 return 0; 5470 } 5471 5472 static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps) 5473 { 5474 int start = 0; 5475 int i; 5476 u32 prev_legacy, cur_legacy; 5477 struct kvm_pit *pit = kvm->arch.vpit; 5478 5479 mutex_lock(&pit->pit_state.lock); 5480 prev_legacy = pit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY; 5481 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY; 5482 if (!prev_legacy && cur_legacy) 5483 start = 1; 5484 memcpy(&pit->pit_state.channels, &ps->channels, 5485 sizeof(pit->pit_state.channels)); 5486 pit->pit_state.flags = ps->flags; 5487 for (i = 0; i < 3; i++) 5488 kvm_pit_load_count(pit, i, pit->pit_state.channels[i].count, 5489 start && i == 0); 5490 mutex_unlock(&pit->pit_state.lock); 5491 return 0; 5492 } 5493 5494 static int kvm_vm_ioctl_reinject(struct kvm *kvm, 5495 struct kvm_reinject_control *control) 5496 { 5497 struct kvm_pit *pit = kvm->arch.vpit; 5498 5499 /* pit->pit_state.lock was overloaded to prevent userspace from getting 5500 * an inconsistent state after running multiple KVM_REINJECT_CONTROL 5501 * ioctls in parallel. Use a separate lock if that ioctl isn't rare. 5502 */ 5503 mutex_lock(&pit->pit_state.lock); 5504 kvm_pit_set_reinject(pit, control->pit_reinject); 5505 mutex_unlock(&pit->pit_state.lock); 5506 5507 return 0; 5508 } 5509 5510 void kvm_arch_sync_dirty_log(struct kvm *kvm, struct kvm_memory_slot *memslot) 5511 { 5512 5513 /* 5514 * Flush all CPUs' dirty log buffers to the dirty_bitmap. Called 5515 * before reporting dirty_bitmap to userspace. KVM flushes the buffers 5516 * on all VM-Exits, thus we only need to kick running vCPUs to force a 5517 * VM-Exit. 5518 */ 5519 struct kvm_vcpu *vcpu; 5520 int i; 5521 5522 kvm_for_each_vcpu(i, vcpu, kvm) 5523 kvm_vcpu_kick(vcpu); 5524 } 5525 5526 int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event, 5527 bool line_status) 5528 { 5529 if (!irqchip_in_kernel(kvm)) 5530 return -ENXIO; 5531 5532 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID, 5533 irq_event->irq, irq_event->level, 5534 line_status); 5535 return 0; 5536 } 5537 5538 int kvm_vm_ioctl_enable_cap(struct kvm *kvm, 5539 struct kvm_enable_cap *cap) 5540 { 5541 int r; 5542 5543 if (cap->flags) 5544 return -EINVAL; 5545 5546 switch (cap->cap) { 5547 case KVM_CAP_DISABLE_QUIRKS: 5548 kvm->arch.disabled_quirks = cap->args[0]; 5549 r = 0; 5550 break; 5551 case KVM_CAP_SPLIT_IRQCHIP: { 5552 mutex_lock(&kvm->lock); 5553 r = -EINVAL; 5554 if (cap->args[0] > MAX_NR_RESERVED_IOAPIC_PINS) 5555 goto split_irqchip_unlock; 5556 r = -EEXIST; 5557 if (irqchip_in_kernel(kvm)) 5558 goto split_irqchip_unlock; 5559 if (kvm->created_vcpus) 5560 goto split_irqchip_unlock; 5561 r = kvm_setup_empty_irq_routing(kvm); 5562 if (r) 5563 goto split_irqchip_unlock; 5564 /* Pairs with irqchip_in_kernel. */ 5565 smp_wmb(); 5566 kvm->arch.irqchip_mode = KVM_IRQCHIP_SPLIT; 5567 kvm->arch.nr_reserved_ioapic_pins = cap->args[0]; 5568 r = 0; 5569 split_irqchip_unlock: 5570 mutex_unlock(&kvm->lock); 5571 break; 5572 } 5573 case KVM_CAP_X2APIC_API: 5574 r = -EINVAL; 5575 if (cap->args[0] & ~KVM_X2APIC_API_VALID_FLAGS) 5576 break; 5577 5578 if (cap->args[0] & KVM_X2APIC_API_USE_32BIT_IDS) 5579 kvm->arch.x2apic_format = true; 5580 if (cap->args[0] & KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK) 5581 kvm->arch.x2apic_broadcast_quirk_disabled = true; 5582 5583 r = 0; 5584 break; 5585 case KVM_CAP_X86_DISABLE_EXITS: 5586 r = -EINVAL; 5587 if (cap->args[0] & ~KVM_X86_DISABLE_VALID_EXITS) 5588 break; 5589 5590 if ((cap->args[0] & KVM_X86_DISABLE_EXITS_MWAIT) && 5591 kvm_can_mwait_in_guest()) 5592 kvm->arch.mwait_in_guest = true; 5593 if (cap->args[0] & KVM_X86_DISABLE_EXITS_HLT) 5594 kvm->arch.hlt_in_guest = true; 5595 if (cap->args[0] & KVM_X86_DISABLE_EXITS_PAUSE) 5596 kvm->arch.pause_in_guest = true; 5597 if (cap->args[0] & KVM_X86_DISABLE_EXITS_CSTATE) 5598 kvm->arch.cstate_in_guest = true; 5599 r = 0; 5600 break; 5601 case KVM_CAP_MSR_PLATFORM_INFO: 5602 kvm->arch.guest_can_read_msr_platform_info = cap->args[0]; 5603 r = 0; 5604 break; 5605 case KVM_CAP_EXCEPTION_PAYLOAD: 5606 kvm->arch.exception_payload_enabled = cap->args[0]; 5607 r = 0; 5608 break; 5609 case KVM_CAP_X86_USER_SPACE_MSR: 5610 kvm->arch.user_space_msr_mask = cap->args[0]; 5611 r = 0; 5612 break; 5613 case KVM_CAP_X86_BUS_LOCK_EXIT: 5614 r = -EINVAL; 5615 if (cap->args[0] & ~KVM_BUS_LOCK_DETECTION_VALID_MODE) 5616 break; 5617 5618 if ((cap->args[0] & KVM_BUS_LOCK_DETECTION_OFF) && 5619 (cap->args[0] & KVM_BUS_LOCK_DETECTION_EXIT)) 5620 break; 5621 5622 if (kvm_has_bus_lock_exit && 5623 cap->args[0] & KVM_BUS_LOCK_DETECTION_EXIT) 5624 kvm->arch.bus_lock_detection_enabled = true; 5625 r = 0; 5626 break; 5627 #ifdef CONFIG_X86_SGX_KVM 5628 case KVM_CAP_SGX_ATTRIBUTE: { 5629 unsigned long allowed_attributes = 0; 5630 5631 r = sgx_set_attribute(&allowed_attributes, cap->args[0]); 5632 if (r) 5633 break; 5634 5635 /* KVM only supports the PROVISIONKEY privileged attribute. */ 5636 if ((allowed_attributes & SGX_ATTR_PROVISIONKEY) && 5637 !(allowed_attributes & ~SGX_ATTR_PROVISIONKEY)) 5638 kvm->arch.sgx_provisioning_allowed = true; 5639 else 5640 r = -EINVAL; 5641 break; 5642 } 5643 #endif 5644 case KVM_CAP_VM_COPY_ENC_CONTEXT_FROM: 5645 r = -EINVAL; 5646 if (kvm_x86_ops.vm_copy_enc_context_from) 5647 r = kvm_x86_ops.vm_copy_enc_context_from(kvm, cap->args[0]); 5648 return r; 5649 case KVM_CAP_EXIT_HYPERCALL: 5650 if (cap->args[0] & ~KVM_EXIT_HYPERCALL_VALID_MASK) { 5651 r = -EINVAL; 5652 break; 5653 } 5654 kvm->arch.hypercall_exit_enabled = cap->args[0]; 5655 r = 0; 5656 break; 5657 case KVM_CAP_EXIT_ON_EMULATION_FAILURE: 5658 r = -EINVAL; 5659 if (cap->args[0] & ~1) 5660 break; 5661 kvm->arch.exit_on_emulation_error = cap->args[0]; 5662 r = 0; 5663 break; 5664 default: 5665 r = -EINVAL; 5666 break; 5667 } 5668 return r; 5669 } 5670 5671 static struct kvm_x86_msr_filter *kvm_alloc_msr_filter(bool default_allow) 5672 { 5673 struct kvm_x86_msr_filter *msr_filter; 5674 5675 msr_filter = kzalloc(sizeof(*msr_filter), GFP_KERNEL_ACCOUNT); 5676 if (!msr_filter) 5677 return NULL; 5678 5679 msr_filter->default_allow = default_allow; 5680 return msr_filter; 5681 } 5682 5683 static void kvm_free_msr_filter(struct kvm_x86_msr_filter *msr_filter) 5684 { 5685 u32 i; 5686 5687 if (!msr_filter) 5688 return; 5689 5690 for (i = 0; i < msr_filter->count; i++) 5691 kfree(msr_filter->ranges[i].bitmap); 5692 5693 kfree(msr_filter); 5694 } 5695 5696 static int kvm_add_msr_filter(struct kvm_x86_msr_filter *msr_filter, 5697 struct kvm_msr_filter_range *user_range) 5698 { 5699 unsigned long *bitmap = NULL; 5700 size_t bitmap_size; 5701 5702 if (!user_range->nmsrs) 5703 return 0; 5704 5705 if (user_range->flags & ~(KVM_MSR_FILTER_READ | KVM_MSR_FILTER_WRITE)) 5706 return -EINVAL; 5707 5708 if (!user_range->flags) 5709 return -EINVAL; 5710 5711 bitmap_size = BITS_TO_LONGS(user_range->nmsrs) * sizeof(long); 5712 if (!bitmap_size || bitmap_size > KVM_MSR_FILTER_MAX_BITMAP_SIZE) 5713 return -EINVAL; 5714 5715 bitmap = memdup_user((__user u8*)user_range->bitmap, bitmap_size); 5716 if (IS_ERR(bitmap)) 5717 return PTR_ERR(bitmap); 5718 5719 msr_filter->ranges[msr_filter->count] = (struct msr_bitmap_range) { 5720 .flags = user_range->flags, 5721 .base = user_range->base, 5722 .nmsrs = user_range->nmsrs, 5723 .bitmap = bitmap, 5724 }; 5725 5726 msr_filter->count++; 5727 return 0; 5728 } 5729 5730 static int kvm_vm_ioctl_set_msr_filter(struct kvm *kvm, void __user *argp) 5731 { 5732 struct kvm_msr_filter __user *user_msr_filter = argp; 5733 struct kvm_x86_msr_filter *new_filter, *old_filter; 5734 struct kvm_msr_filter filter; 5735 bool default_allow; 5736 bool empty = true; 5737 int r = 0; 5738 u32 i; 5739 5740 if (copy_from_user(&filter, user_msr_filter, sizeof(filter))) 5741 return -EFAULT; 5742 5743 for (i = 0; i < ARRAY_SIZE(filter.ranges); i++) 5744 empty &= !filter.ranges[i].nmsrs; 5745 5746 default_allow = !(filter.flags & KVM_MSR_FILTER_DEFAULT_DENY); 5747 if (empty && !default_allow) 5748 return -EINVAL; 5749 5750 new_filter = kvm_alloc_msr_filter(default_allow); 5751 if (!new_filter) 5752 return -ENOMEM; 5753 5754 for (i = 0; i < ARRAY_SIZE(filter.ranges); i++) { 5755 r = kvm_add_msr_filter(new_filter, &filter.ranges[i]); 5756 if (r) { 5757 kvm_free_msr_filter(new_filter); 5758 return r; 5759 } 5760 } 5761 5762 mutex_lock(&kvm->lock); 5763 5764 /* The per-VM filter is protected by kvm->lock... */ 5765 old_filter = srcu_dereference_check(kvm->arch.msr_filter, &kvm->srcu, 1); 5766 5767 rcu_assign_pointer(kvm->arch.msr_filter, new_filter); 5768 synchronize_srcu(&kvm->srcu); 5769 5770 kvm_free_msr_filter(old_filter); 5771 5772 kvm_make_all_cpus_request(kvm, KVM_REQ_MSR_FILTER_CHANGED); 5773 mutex_unlock(&kvm->lock); 5774 5775 return 0; 5776 } 5777 5778 #ifdef CONFIG_HAVE_KVM_PM_NOTIFIER 5779 static int kvm_arch_suspend_notifier(struct kvm *kvm) 5780 { 5781 struct kvm_vcpu *vcpu; 5782 int i, ret = 0; 5783 5784 mutex_lock(&kvm->lock); 5785 kvm_for_each_vcpu(i, vcpu, kvm) { 5786 if (!vcpu->arch.pv_time_enabled) 5787 continue; 5788 5789 ret = kvm_set_guest_paused(vcpu); 5790 if (ret) { 5791 kvm_err("Failed to pause guest VCPU%d: %d\n", 5792 vcpu->vcpu_id, ret); 5793 break; 5794 } 5795 } 5796 mutex_unlock(&kvm->lock); 5797 5798 return ret ? NOTIFY_BAD : NOTIFY_DONE; 5799 } 5800 5801 int kvm_arch_pm_notifier(struct kvm *kvm, unsigned long state) 5802 { 5803 switch (state) { 5804 case PM_HIBERNATION_PREPARE: 5805 case PM_SUSPEND_PREPARE: 5806 return kvm_arch_suspend_notifier(kvm); 5807 } 5808 5809 return NOTIFY_DONE; 5810 } 5811 #endif /* CONFIG_HAVE_KVM_PM_NOTIFIER */ 5812 5813 long kvm_arch_vm_ioctl(struct file *filp, 5814 unsigned int ioctl, unsigned long arg) 5815 { 5816 struct kvm *kvm = filp->private_data; 5817 void __user *argp = (void __user *)arg; 5818 int r = -ENOTTY; 5819 /* 5820 * This union makes it completely explicit to gcc-3.x 5821 * that these two variables' stack usage should be 5822 * combined, not added together. 5823 */ 5824 union { 5825 struct kvm_pit_state ps; 5826 struct kvm_pit_state2 ps2; 5827 struct kvm_pit_config pit_config; 5828 } u; 5829 5830 switch (ioctl) { 5831 case KVM_SET_TSS_ADDR: 5832 r = kvm_vm_ioctl_set_tss_addr(kvm, arg); 5833 break; 5834 case KVM_SET_IDENTITY_MAP_ADDR: { 5835 u64 ident_addr; 5836 5837 mutex_lock(&kvm->lock); 5838 r = -EINVAL; 5839 if (kvm->created_vcpus) 5840 goto set_identity_unlock; 5841 r = -EFAULT; 5842 if (copy_from_user(&ident_addr, argp, sizeof(ident_addr))) 5843 goto set_identity_unlock; 5844 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr); 5845 set_identity_unlock: 5846 mutex_unlock(&kvm->lock); 5847 break; 5848 } 5849 case KVM_SET_NR_MMU_PAGES: 5850 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg); 5851 break; 5852 case KVM_GET_NR_MMU_PAGES: 5853 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm); 5854 break; 5855 case KVM_CREATE_IRQCHIP: { 5856 mutex_lock(&kvm->lock); 5857 5858 r = -EEXIST; 5859 if (irqchip_in_kernel(kvm)) 5860 goto create_irqchip_unlock; 5861 5862 r = -EINVAL; 5863 if (kvm->created_vcpus) 5864 goto create_irqchip_unlock; 5865 5866 r = kvm_pic_init(kvm); 5867 if (r) 5868 goto create_irqchip_unlock; 5869 5870 r = kvm_ioapic_init(kvm); 5871 if (r) { 5872 kvm_pic_destroy(kvm); 5873 goto create_irqchip_unlock; 5874 } 5875 5876 r = kvm_setup_default_irq_routing(kvm); 5877 if (r) { 5878 kvm_ioapic_destroy(kvm); 5879 kvm_pic_destroy(kvm); 5880 goto create_irqchip_unlock; 5881 } 5882 /* Write kvm->irq_routing before enabling irqchip_in_kernel. */ 5883 smp_wmb(); 5884 kvm->arch.irqchip_mode = KVM_IRQCHIP_KERNEL; 5885 create_irqchip_unlock: 5886 mutex_unlock(&kvm->lock); 5887 break; 5888 } 5889 case KVM_CREATE_PIT: 5890 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY; 5891 goto create_pit; 5892 case KVM_CREATE_PIT2: 5893 r = -EFAULT; 5894 if (copy_from_user(&u.pit_config, argp, 5895 sizeof(struct kvm_pit_config))) 5896 goto out; 5897 create_pit: 5898 mutex_lock(&kvm->lock); 5899 r = -EEXIST; 5900 if (kvm->arch.vpit) 5901 goto create_pit_unlock; 5902 r = -ENOMEM; 5903 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags); 5904 if (kvm->arch.vpit) 5905 r = 0; 5906 create_pit_unlock: 5907 mutex_unlock(&kvm->lock); 5908 break; 5909 case KVM_GET_IRQCHIP: { 5910 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */ 5911 struct kvm_irqchip *chip; 5912 5913 chip = memdup_user(argp, sizeof(*chip)); 5914 if (IS_ERR(chip)) { 5915 r = PTR_ERR(chip); 5916 goto out; 5917 } 5918 5919 r = -ENXIO; 5920 if (!irqchip_kernel(kvm)) 5921 goto get_irqchip_out; 5922 r = kvm_vm_ioctl_get_irqchip(kvm, chip); 5923 if (r) 5924 goto get_irqchip_out; 5925 r = -EFAULT; 5926 if (copy_to_user(argp, chip, sizeof(*chip))) 5927 goto get_irqchip_out; 5928 r = 0; 5929 get_irqchip_out: 5930 kfree(chip); 5931 break; 5932 } 5933 case KVM_SET_IRQCHIP: { 5934 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */ 5935 struct kvm_irqchip *chip; 5936 5937 chip = memdup_user(argp, sizeof(*chip)); 5938 if (IS_ERR(chip)) { 5939 r = PTR_ERR(chip); 5940 goto out; 5941 } 5942 5943 r = -ENXIO; 5944 if (!irqchip_kernel(kvm)) 5945 goto set_irqchip_out; 5946 r = kvm_vm_ioctl_set_irqchip(kvm, chip); 5947 set_irqchip_out: 5948 kfree(chip); 5949 break; 5950 } 5951 case KVM_GET_PIT: { 5952 r = -EFAULT; 5953 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state))) 5954 goto out; 5955 r = -ENXIO; 5956 if (!kvm->arch.vpit) 5957 goto out; 5958 r = kvm_vm_ioctl_get_pit(kvm, &u.ps); 5959 if (r) 5960 goto out; 5961 r = -EFAULT; 5962 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state))) 5963 goto out; 5964 r = 0; 5965 break; 5966 } 5967 case KVM_SET_PIT: { 5968 r = -EFAULT; 5969 if (copy_from_user(&u.ps, argp, sizeof(u.ps))) 5970 goto out; 5971 mutex_lock(&kvm->lock); 5972 r = -ENXIO; 5973 if (!kvm->arch.vpit) 5974 goto set_pit_out; 5975 r = kvm_vm_ioctl_set_pit(kvm, &u.ps); 5976 set_pit_out: 5977 mutex_unlock(&kvm->lock); 5978 break; 5979 } 5980 case KVM_GET_PIT2: { 5981 r = -ENXIO; 5982 if (!kvm->arch.vpit) 5983 goto out; 5984 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2); 5985 if (r) 5986 goto out; 5987 r = -EFAULT; 5988 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2))) 5989 goto out; 5990 r = 0; 5991 break; 5992 } 5993 case KVM_SET_PIT2: { 5994 r = -EFAULT; 5995 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2))) 5996 goto out; 5997 mutex_lock(&kvm->lock); 5998 r = -ENXIO; 5999 if (!kvm->arch.vpit) 6000 goto set_pit2_out; 6001 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2); 6002 set_pit2_out: 6003 mutex_unlock(&kvm->lock); 6004 break; 6005 } 6006 case KVM_REINJECT_CONTROL: { 6007 struct kvm_reinject_control control; 6008 r = -EFAULT; 6009 if (copy_from_user(&control, argp, sizeof(control))) 6010 goto out; 6011 r = -ENXIO; 6012 if (!kvm->arch.vpit) 6013 goto out; 6014 r = kvm_vm_ioctl_reinject(kvm, &control); 6015 break; 6016 } 6017 case KVM_SET_BOOT_CPU_ID: 6018 r = 0; 6019 mutex_lock(&kvm->lock); 6020 if (kvm->created_vcpus) 6021 r = -EBUSY; 6022 else 6023 kvm->arch.bsp_vcpu_id = arg; 6024 mutex_unlock(&kvm->lock); 6025 break; 6026 #ifdef CONFIG_KVM_XEN 6027 case KVM_XEN_HVM_CONFIG: { 6028 struct kvm_xen_hvm_config xhc; 6029 r = -EFAULT; 6030 if (copy_from_user(&xhc, argp, sizeof(xhc))) 6031 goto out; 6032 r = kvm_xen_hvm_config(kvm, &xhc); 6033 break; 6034 } 6035 case KVM_XEN_HVM_GET_ATTR: { 6036 struct kvm_xen_hvm_attr xha; 6037 6038 r = -EFAULT; 6039 if (copy_from_user(&xha, argp, sizeof(xha))) 6040 goto out; 6041 r = kvm_xen_hvm_get_attr(kvm, &xha); 6042 if (!r && copy_to_user(argp, &xha, sizeof(xha))) 6043 r = -EFAULT; 6044 break; 6045 } 6046 case KVM_XEN_HVM_SET_ATTR: { 6047 struct kvm_xen_hvm_attr xha; 6048 6049 r = -EFAULT; 6050 if (copy_from_user(&xha, argp, sizeof(xha))) 6051 goto out; 6052 r = kvm_xen_hvm_set_attr(kvm, &xha); 6053 break; 6054 } 6055 #endif 6056 case KVM_SET_CLOCK: { 6057 struct kvm_arch *ka = &kvm->arch; 6058 struct kvm_clock_data user_ns; 6059 u64 now_ns; 6060 6061 r = -EFAULT; 6062 if (copy_from_user(&user_ns, argp, sizeof(user_ns))) 6063 goto out; 6064 6065 r = -EINVAL; 6066 if (user_ns.flags) 6067 goto out; 6068 6069 r = 0; 6070 /* 6071 * TODO: userspace has to take care of races with VCPU_RUN, so 6072 * kvm_gen_update_masterclock() can be cut down to locked 6073 * pvclock_update_vm_gtod_copy(). 6074 */ 6075 kvm_gen_update_masterclock(kvm); 6076 6077 /* 6078 * This pairs with kvm_guest_time_update(): when masterclock is 6079 * in use, we use master_kernel_ns + kvmclock_offset to set 6080 * unsigned 'system_time' so if we use get_kvmclock_ns() (which 6081 * is slightly ahead) here we risk going negative on unsigned 6082 * 'system_time' when 'user_ns.clock' is very small. 6083 */ 6084 spin_lock_irq(&ka->pvclock_gtod_sync_lock); 6085 if (kvm->arch.use_master_clock) 6086 now_ns = ka->master_kernel_ns; 6087 else 6088 now_ns = get_kvmclock_base_ns(); 6089 ka->kvmclock_offset = user_ns.clock - now_ns; 6090 spin_unlock_irq(&ka->pvclock_gtod_sync_lock); 6091 6092 kvm_make_all_cpus_request(kvm, KVM_REQ_CLOCK_UPDATE); 6093 break; 6094 } 6095 case KVM_GET_CLOCK: { 6096 struct kvm_clock_data user_ns; 6097 u64 now_ns; 6098 6099 now_ns = get_kvmclock_ns(kvm); 6100 user_ns.clock = now_ns; 6101 user_ns.flags = kvm->arch.use_master_clock ? KVM_CLOCK_TSC_STABLE : 0; 6102 memset(&user_ns.pad, 0, sizeof(user_ns.pad)); 6103 6104 r = -EFAULT; 6105 if (copy_to_user(argp, &user_ns, sizeof(user_ns))) 6106 goto out; 6107 r = 0; 6108 break; 6109 } 6110 case KVM_MEMORY_ENCRYPT_OP: { 6111 r = -ENOTTY; 6112 if (kvm_x86_ops.mem_enc_op) 6113 r = static_call(kvm_x86_mem_enc_op)(kvm, argp); 6114 break; 6115 } 6116 case KVM_MEMORY_ENCRYPT_REG_REGION: { 6117 struct kvm_enc_region region; 6118 6119 r = -EFAULT; 6120 if (copy_from_user(®ion, argp, sizeof(region))) 6121 goto out; 6122 6123 r = -ENOTTY; 6124 if (kvm_x86_ops.mem_enc_reg_region) 6125 r = static_call(kvm_x86_mem_enc_reg_region)(kvm, ®ion); 6126 break; 6127 } 6128 case KVM_MEMORY_ENCRYPT_UNREG_REGION: { 6129 struct kvm_enc_region region; 6130 6131 r = -EFAULT; 6132 if (copy_from_user(®ion, argp, sizeof(region))) 6133 goto out; 6134 6135 r = -ENOTTY; 6136 if (kvm_x86_ops.mem_enc_unreg_region) 6137 r = static_call(kvm_x86_mem_enc_unreg_region)(kvm, ®ion); 6138 break; 6139 } 6140 case KVM_HYPERV_EVENTFD: { 6141 struct kvm_hyperv_eventfd hvevfd; 6142 6143 r = -EFAULT; 6144 if (copy_from_user(&hvevfd, argp, sizeof(hvevfd))) 6145 goto out; 6146 r = kvm_vm_ioctl_hv_eventfd(kvm, &hvevfd); 6147 break; 6148 } 6149 case KVM_SET_PMU_EVENT_FILTER: 6150 r = kvm_vm_ioctl_set_pmu_event_filter(kvm, argp); 6151 break; 6152 case KVM_X86_SET_MSR_FILTER: 6153 r = kvm_vm_ioctl_set_msr_filter(kvm, argp); 6154 break; 6155 default: 6156 r = -ENOTTY; 6157 } 6158 out: 6159 return r; 6160 } 6161 6162 static void kvm_init_msr_list(void) 6163 { 6164 struct x86_pmu_capability x86_pmu; 6165 u32 dummy[2]; 6166 unsigned i; 6167 6168 BUILD_BUG_ON_MSG(INTEL_PMC_MAX_FIXED != 4, 6169 "Please update the fixed PMCs in msrs_to_saved_all[]"); 6170 6171 perf_get_x86_pmu_capability(&x86_pmu); 6172 6173 num_msrs_to_save = 0; 6174 num_emulated_msrs = 0; 6175 num_msr_based_features = 0; 6176 6177 for (i = 0; i < ARRAY_SIZE(msrs_to_save_all); i++) { 6178 if (rdmsr_safe(msrs_to_save_all[i], &dummy[0], &dummy[1]) < 0) 6179 continue; 6180 6181 /* 6182 * Even MSRs that are valid in the host may not be exposed 6183 * to the guests in some cases. 6184 */ 6185 switch (msrs_to_save_all[i]) { 6186 case MSR_IA32_BNDCFGS: 6187 if (!kvm_mpx_supported()) 6188 continue; 6189 break; 6190 case MSR_TSC_AUX: 6191 if (!kvm_cpu_cap_has(X86_FEATURE_RDTSCP) && 6192 !kvm_cpu_cap_has(X86_FEATURE_RDPID)) 6193 continue; 6194 break; 6195 case MSR_IA32_UMWAIT_CONTROL: 6196 if (!kvm_cpu_cap_has(X86_FEATURE_WAITPKG)) 6197 continue; 6198 break; 6199 case MSR_IA32_RTIT_CTL: 6200 case MSR_IA32_RTIT_STATUS: 6201 if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT)) 6202 continue; 6203 break; 6204 case MSR_IA32_RTIT_CR3_MATCH: 6205 if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT) || 6206 !intel_pt_validate_hw_cap(PT_CAP_cr3_filtering)) 6207 continue; 6208 break; 6209 case MSR_IA32_RTIT_OUTPUT_BASE: 6210 case MSR_IA32_RTIT_OUTPUT_MASK: 6211 if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT) || 6212 (!intel_pt_validate_hw_cap(PT_CAP_topa_output) && 6213 !intel_pt_validate_hw_cap(PT_CAP_single_range_output))) 6214 continue; 6215 break; 6216 case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B: 6217 if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT) || 6218 msrs_to_save_all[i] - MSR_IA32_RTIT_ADDR0_A >= 6219 intel_pt_validate_hw_cap(PT_CAP_num_address_ranges) * 2) 6220 continue; 6221 break; 6222 case MSR_ARCH_PERFMON_PERFCTR0 ... MSR_ARCH_PERFMON_PERFCTR0 + 17: 6223 if (msrs_to_save_all[i] - MSR_ARCH_PERFMON_PERFCTR0 >= 6224 min(INTEL_PMC_MAX_GENERIC, x86_pmu.num_counters_gp)) 6225 continue; 6226 break; 6227 case MSR_ARCH_PERFMON_EVENTSEL0 ... MSR_ARCH_PERFMON_EVENTSEL0 + 17: 6228 if (msrs_to_save_all[i] - MSR_ARCH_PERFMON_EVENTSEL0 >= 6229 min(INTEL_PMC_MAX_GENERIC, x86_pmu.num_counters_gp)) 6230 continue; 6231 break; 6232 default: 6233 break; 6234 } 6235 6236 msrs_to_save[num_msrs_to_save++] = msrs_to_save_all[i]; 6237 } 6238 6239 for (i = 0; i < ARRAY_SIZE(emulated_msrs_all); i++) { 6240 if (!static_call(kvm_x86_has_emulated_msr)(NULL, emulated_msrs_all[i])) 6241 continue; 6242 6243 emulated_msrs[num_emulated_msrs++] = emulated_msrs_all[i]; 6244 } 6245 6246 for (i = 0; i < ARRAY_SIZE(msr_based_features_all); i++) { 6247 struct kvm_msr_entry msr; 6248 6249 msr.index = msr_based_features_all[i]; 6250 if (kvm_get_msr_feature(&msr)) 6251 continue; 6252 6253 msr_based_features[num_msr_based_features++] = msr_based_features_all[i]; 6254 } 6255 } 6256 6257 static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len, 6258 const void *v) 6259 { 6260 int handled = 0; 6261 int n; 6262 6263 do { 6264 n = min(len, 8); 6265 if (!(lapic_in_kernel(vcpu) && 6266 !kvm_iodevice_write(vcpu, &vcpu->arch.apic->dev, addr, n, v)) 6267 && kvm_io_bus_write(vcpu, KVM_MMIO_BUS, addr, n, v)) 6268 break; 6269 handled += n; 6270 addr += n; 6271 len -= n; 6272 v += n; 6273 } while (len); 6274 6275 return handled; 6276 } 6277 6278 static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v) 6279 { 6280 int handled = 0; 6281 int n; 6282 6283 do { 6284 n = min(len, 8); 6285 if (!(lapic_in_kernel(vcpu) && 6286 !kvm_iodevice_read(vcpu, &vcpu->arch.apic->dev, 6287 addr, n, v)) 6288 && kvm_io_bus_read(vcpu, KVM_MMIO_BUS, addr, n, v)) 6289 break; 6290 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, v); 6291 handled += n; 6292 addr += n; 6293 len -= n; 6294 v += n; 6295 } while (len); 6296 6297 return handled; 6298 } 6299 6300 static void kvm_set_segment(struct kvm_vcpu *vcpu, 6301 struct kvm_segment *var, int seg) 6302 { 6303 static_call(kvm_x86_set_segment)(vcpu, var, seg); 6304 } 6305 6306 void kvm_get_segment(struct kvm_vcpu *vcpu, 6307 struct kvm_segment *var, int seg) 6308 { 6309 static_call(kvm_x86_get_segment)(vcpu, var, seg); 6310 } 6311 6312 gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access, 6313 struct x86_exception *exception) 6314 { 6315 gpa_t t_gpa; 6316 6317 BUG_ON(!mmu_is_nested(vcpu)); 6318 6319 /* NPT walks are always user-walks */ 6320 access |= PFERR_USER_MASK; 6321 t_gpa = vcpu->arch.mmu->gva_to_gpa(vcpu, gpa, access, exception); 6322 6323 return t_gpa; 6324 } 6325 6326 gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva, 6327 struct x86_exception *exception) 6328 { 6329 u32 access = (static_call(kvm_x86_get_cpl)(vcpu) == 3) ? PFERR_USER_MASK : 0; 6330 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception); 6331 } 6332 EXPORT_SYMBOL_GPL(kvm_mmu_gva_to_gpa_read); 6333 6334 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva, 6335 struct x86_exception *exception) 6336 { 6337 u32 access = (static_call(kvm_x86_get_cpl)(vcpu) == 3) ? PFERR_USER_MASK : 0; 6338 access |= PFERR_FETCH_MASK; 6339 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception); 6340 } 6341 6342 gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva, 6343 struct x86_exception *exception) 6344 { 6345 u32 access = (static_call(kvm_x86_get_cpl)(vcpu) == 3) ? PFERR_USER_MASK : 0; 6346 access |= PFERR_WRITE_MASK; 6347 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception); 6348 } 6349 EXPORT_SYMBOL_GPL(kvm_mmu_gva_to_gpa_write); 6350 6351 /* uses this to access any guest's mapped memory without checking CPL */ 6352 gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva, 6353 struct x86_exception *exception) 6354 { 6355 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception); 6356 } 6357 6358 static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes, 6359 struct kvm_vcpu *vcpu, u32 access, 6360 struct x86_exception *exception) 6361 { 6362 void *data = val; 6363 int r = X86EMUL_CONTINUE; 6364 6365 while (bytes) { 6366 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access, 6367 exception); 6368 unsigned offset = addr & (PAGE_SIZE-1); 6369 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset); 6370 int ret; 6371 6372 if (gpa == UNMAPPED_GVA) 6373 return X86EMUL_PROPAGATE_FAULT; 6374 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, data, 6375 offset, toread); 6376 if (ret < 0) { 6377 r = X86EMUL_IO_NEEDED; 6378 goto out; 6379 } 6380 6381 bytes -= toread; 6382 data += toread; 6383 addr += toread; 6384 } 6385 out: 6386 return r; 6387 } 6388 6389 /* used for instruction fetching */ 6390 static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt, 6391 gva_t addr, void *val, unsigned int bytes, 6392 struct x86_exception *exception) 6393 { 6394 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 6395 u32 access = (static_call(kvm_x86_get_cpl)(vcpu) == 3) ? PFERR_USER_MASK : 0; 6396 unsigned offset; 6397 int ret; 6398 6399 /* Inline kvm_read_guest_virt_helper for speed. */ 6400 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access|PFERR_FETCH_MASK, 6401 exception); 6402 if (unlikely(gpa == UNMAPPED_GVA)) 6403 return X86EMUL_PROPAGATE_FAULT; 6404 6405 offset = addr & (PAGE_SIZE-1); 6406 if (WARN_ON(offset + bytes > PAGE_SIZE)) 6407 bytes = (unsigned)PAGE_SIZE - offset; 6408 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, val, 6409 offset, bytes); 6410 if (unlikely(ret < 0)) 6411 return X86EMUL_IO_NEEDED; 6412 6413 return X86EMUL_CONTINUE; 6414 } 6415 6416 int kvm_read_guest_virt(struct kvm_vcpu *vcpu, 6417 gva_t addr, void *val, unsigned int bytes, 6418 struct x86_exception *exception) 6419 { 6420 u32 access = (static_call(kvm_x86_get_cpl)(vcpu) == 3) ? PFERR_USER_MASK : 0; 6421 6422 /* 6423 * FIXME: this should call handle_emulation_failure if X86EMUL_IO_NEEDED 6424 * is returned, but our callers are not ready for that and they blindly 6425 * call kvm_inject_page_fault. Ensure that they at least do not leak 6426 * uninitialized kernel stack memory into cr2 and error code. 6427 */ 6428 memset(exception, 0, sizeof(*exception)); 6429 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access, 6430 exception); 6431 } 6432 EXPORT_SYMBOL_GPL(kvm_read_guest_virt); 6433 6434 static int emulator_read_std(struct x86_emulate_ctxt *ctxt, 6435 gva_t addr, void *val, unsigned int bytes, 6436 struct x86_exception *exception, bool system) 6437 { 6438 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 6439 u32 access = 0; 6440 6441 if (!system && static_call(kvm_x86_get_cpl)(vcpu) == 3) 6442 access |= PFERR_USER_MASK; 6443 6444 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access, exception); 6445 } 6446 6447 static int kvm_read_guest_phys_system(struct x86_emulate_ctxt *ctxt, 6448 unsigned long addr, void *val, unsigned int bytes) 6449 { 6450 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 6451 int r = kvm_vcpu_read_guest(vcpu, addr, val, bytes); 6452 6453 return r < 0 ? X86EMUL_IO_NEEDED : X86EMUL_CONTINUE; 6454 } 6455 6456 static int kvm_write_guest_virt_helper(gva_t addr, void *val, unsigned int bytes, 6457 struct kvm_vcpu *vcpu, u32 access, 6458 struct x86_exception *exception) 6459 { 6460 void *data = val; 6461 int r = X86EMUL_CONTINUE; 6462 6463 while (bytes) { 6464 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, 6465 access, 6466 exception); 6467 unsigned offset = addr & (PAGE_SIZE-1); 6468 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset); 6469 int ret; 6470 6471 if (gpa == UNMAPPED_GVA) 6472 return X86EMUL_PROPAGATE_FAULT; 6473 ret = kvm_vcpu_write_guest(vcpu, gpa, data, towrite); 6474 if (ret < 0) { 6475 r = X86EMUL_IO_NEEDED; 6476 goto out; 6477 } 6478 6479 bytes -= towrite; 6480 data += towrite; 6481 addr += towrite; 6482 } 6483 out: 6484 return r; 6485 } 6486 6487 static int emulator_write_std(struct x86_emulate_ctxt *ctxt, gva_t addr, void *val, 6488 unsigned int bytes, struct x86_exception *exception, 6489 bool system) 6490 { 6491 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 6492 u32 access = PFERR_WRITE_MASK; 6493 6494 if (!system && static_call(kvm_x86_get_cpl)(vcpu) == 3) 6495 access |= PFERR_USER_MASK; 6496 6497 return kvm_write_guest_virt_helper(addr, val, bytes, vcpu, 6498 access, exception); 6499 } 6500 6501 int kvm_write_guest_virt_system(struct kvm_vcpu *vcpu, gva_t addr, void *val, 6502 unsigned int bytes, struct x86_exception *exception) 6503 { 6504 /* kvm_write_guest_virt_system can pull in tons of pages. */ 6505 vcpu->arch.l1tf_flush_l1d = true; 6506 6507 return kvm_write_guest_virt_helper(addr, val, bytes, vcpu, 6508 PFERR_WRITE_MASK, exception); 6509 } 6510 EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system); 6511 6512 int handle_ud(struct kvm_vcpu *vcpu) 6513 { 6514 static const char kvm_emulate_prefix[] = { __KVM_EMULATE_PREFIX }; 6515 int emul_type = EMULTYPE_TRAP_UD; 6516 char sig[5]; /* ud2; .ascii "kvm" */ 6517 struct x86_exception e; 6518 6519 if (unlikely(!static_call(kvm_x86_can_emulate_instruction)(vcpu, NULL, 0))) 6520 return 1; 6521 6522 if (force_emulation_prefix && 6523 kvm_read_guest_virt(vcpu, kvm_get_linear_rip(vcpu), 6524 sig, sizeof(sig), &e) == 0 && 6525 memcmp(sig, kvm_emulate_prefix, sizeof(sig)) == 0) { 6526 kvm_rip_write(vcpu, kvm_rip_read(vcpu) + sizeof(sig)); 6527 emul_type = EMULTYPE_TRAP_UD_FORCED; 6528 } 6529 6530 return kvm_emulate_instruction(vcpu, emul_type); 6531 } 6532 EXPORT_SYMBOL_GPL(handle_ud); 6533 6534 static int vcpu_is_mmio_gpa(struct kvm_vcpu *vcpu, unsigned long gva, 6535 gpa_t gpa, bool write) 6536 { 6537 /* For APIC access vmexit */ 6538 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE) 6539 return 1; 6540 6541 if (vcpu_match_mmio_gpa(vcpu, gpa)) { 6542 trace_vcpu_match_mmio(gva, gpa, write, true); 6543 return 1; 6544 } 6545 6546 return 0; 6547 } 6548 6549 static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva, 6550 gpa_t *gpa, struct x86_exception *exception, 6551 bool write) 6552 { 6553 u32 access = ((static_call(kvm_x86_get_cpl)(vcpu) == 3) ? PFERR_USER_MASK : 0) 6554 | (write ? PFERR_WRITE_MASK : 0); 6555 6556 /* 6557 * currently PKRU is only applied to ept enabled guest so 6558 * there is no pkey in EPT page table for L1 guest or EPT 6559 * shadow page table for L2 guest. 6560 */ 6561 if (vcpu_match_mmio_gva(vcpu, gva) 6562 && !permission_fault(vcpu, vcpu->arch.walk_mmu, 6563 vcpu->arch.mmio_access, 0, access)) { 6564 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT | 6565 (gva & (PAGE_SIZE - 1)); 6566 trace_vcpu_match_mmio(gva, *gpa, write, false); 6567 return 1; 6568 } 6569 6570 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception); 6571 6572 if (*gpa == UNMAPPED_GVA) 6573 return -1; 6574 6575 return vcpu_is_mmio_gpa(vcpu, gva, *gpa, write); 6576 } 6577 6578 int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa, 6579 const void *val, int bytes) 6580 { 6581 int ret; 6582 6583 ret = kvm_vcpu_write_guest(vcpu, gpa, val, bytes); 6584 if (ret < 0) 6585 return 0; 6586 kvm_page_track_write(vcpu, gpa, val, bytes); 6587 return 1; 6588 } 6589 6590 struct read_write_emulator_ops { 6591 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val, 6592 int bytes); 6593 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa, 6594 void *val, int bytes); 6595 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa, 6596 int bytes, void *val); 6597 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa, 6598 void *val, int bytes); 6599 bool write; 6600 }; 6601 6602 static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes) 6603 { 6604 if (vcpu->mmio_read_completed) { 6605 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes, 6606 vcpu->mmio_fragments[0].gpa, val); 6607 vcpu->mmio_read_completed = 0; 6608 return 1; 6609 } 6610 6611 return 0; 6612 } 6613 6614 static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa, 6615 void *val, int bytes) 6616 { 6617 return !kvm_vcpu_read_guest(vcpu, gpa, val, bytes); 6618 } 6619 6620 static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa, 6621 void *val, int bytes) 6622 { 6623 return emulator_write_phys(vcpu, gpa, val, bytes); 6624 } 6625 6626 static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val) 6627 { 6628 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, val); 6629 return vcpu_mmio_write(vcpu, gpa, bytes, val); 6630 } 6631 6632 static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, 6633 void *val, int bytes) 6634 { 6635 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, NULL); 6636 return X86EMUL_IO_NEEDED; 6637 } 6638 6639 static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, 6640 void *val, int bytes) 6641 { 6642 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0]; 6643 6644 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len)); 6645 return X86EMUL_CONTINUE; 6646 } 6647 6648 static const struct read_write_emulator_ops read_emultor = { 6649 .read_write_prepare = read_prepare, 6650 .read_write_emulate = read_emulate, 6651 .read_write_mmio = vcpu_mmio_read, 6652 .read_write_exit_mmio = read_exit_mmio, 6653 }; 6654 6655 static const struct read_write_emulator_ops write_emultor = { 6656 .read_write_emulate = write_emulate, 6657 .read_write_mmio = write_mmio, 6658 .read_write_exit_mmio = write_exit_mmio, 6659 .write = true, 6660 }; 6661 6662 static int emulator_read_write_onepage(unsigned long addr, void *val, 6663 unsigned int bytes, 6664 struct x86_exception *exception, 6665 struct kvm_vcpu *vcpu, 6666 const struct read_write_emulator_ops *ops) 6667 { 6668 gpa_t gpa; 6669 int handled, ret; 6670 bool write = ops->write; 6671 struct kvm_mmio_fragment *frag; 6672 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt; 6673 6674 /* 6675 * If the exit was due to a NPF we may already have a GPA. 6676 * If the GPA is present, use it to avoid the GVA to GPA table walk. 6677 * Note, this cannot be used on string operations since string 6678 * operation using rep will only have the initial GPA from the NPF 6679 * occurred. 6680 */ 6681 if (ctxt->gpa_available && emulator_can_use_gpa(ctxt) && 6682 (addr & ~PAGE_MASK) == (ctxt->gpa_val & ~PAGE_MASK)) { 6683 gpa = ctxt->gpa_val; 6684 ret = vcpu_is_mmio_gpa(vcpu, addr, gpa, write); 6685 } else { 6686 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write); 6687 if (ret < 0) 6688 return X86EMUL_PROPAGATE_FAULT; 6689 } 6690 6691 if (!ret && ops->read_write_emulate(vcpu, gpa, val, bytes)) 6692 return X86EMUL_CONTINUE; 6693 6694 /* 6695 * Is this MMIO handled locally? 6696 */ 6697 handled = ops->read_write_mmio(vcpu, gpa, bytes, val); 6698 if (handled == bytes) 6699 return X86EMUL_CONTINUE; 6700 6701 gpa += handled; 6702 bytes -= handled; 6703 val += handled; 6704 6705 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS); 6706 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++]; 6707 frag->gpa = gpa; 6708 frag->data = val; 6709 frag->len = bytes; 6710 return X86EMUL_CONTINUE; 6711 } 6712 6713 static int emulator_read_write(struct x86_emulate_ctxt *ctxt, 6714 unsigned long addr, 6715 void *val, unsigned int bytes, 6716 struct x86_exception *exception, 6717 const struct read_write_emulator_ops *ops) 6718 { 6719 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 6720 gpa_t gpa; 6721 int rc; 6722 6723 if (ops->read_write_prepare && 6724 ops->read_write_prepare(vcpu, val, bytes)) 6725 return X86EMUL_CONTINUE; 6726 6727 vcpu->mmio_nr_fragments = 0; 6728 6729 /* Crossing a page boundary? */ 6730 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) { 6731 int now; 6732 6733 now = -addr & ~PAGE_MASK; 6734 rc = emulator_read_write_onepage(addr, val, now, exception, 6735 vcpu, ops); 6736 6737 if (rc != X86EMUL_CONTINUE) 6738 return rc; 6739 addr += now; 6740 if (ctxt->mode != X86EMUL_MODE_PROT64) 6741 addr = (u32)addr; 6742 val += now; 6743 bytes -= now; 6744 } 6745 6746 rc = emulator_read_write_onepage(addr, val, bytes, exception, 6747 vcpu, ops); 6748 if (rc != X86EMUL_CONTINUE) 6749 return rc; 6750 6751 if (!vcpu->mmio_nr_fragments) 6752 return rc; 6753 6754 gpa = vcpu->mmio_fragments[0].gpa; 6755 6756 vcpu->mmio_needed = 1; 6757 vcpu->mmio_cur_fragment = 0; 6758 6759 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len); 6760 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write; 6761 vcpu->run->exit_reason = KVM_EXIT_MMIO; 6762 vcpu->run->mmio.phys_addr = gpa; 6763 6764 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes); 6765 } 6766 6767 static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt, 6768 unsigned long addr, 6769 void *val, 6770 unsigned int bytes, 6771 struct x86_exception *exception) 6772 { 6773 return emulator_read_write(ctxt, addr, val, bytes, 6774 exception, &read_emultor); 6775 } 6776 6777 static int emulator_write_emulated(struct x86_emulate_ctxt *ctxt, 6778 unsigned long addr, 6779 const void *val, 6780 unsigned int bytes, 6781 struct x86_exception *exception) 6782 { 6783 return emulator_read_write(ctxt, addr, (void *)val, bytes, 6784 exception, &write_emultor); 6785 } 6786 6787 #define CMPXCHG_TYPE(t, ptr, old, new) \ 6788 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old)) 6789 6790 #ifdef CONFIG_X86_64 6791 # define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new) 6792 #else 6793 # define CMPXCHG64(ptr, old, new) \ 6794 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old)) 6795 #endif 6796 6797 static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt, 6798 unsigned long addr, 6799 const void *old, 6800 const void *new, 6801 unsigned int bytes, 6802 struct x86_exception *exception) 6803 { 6804 struct kvm_host_map map; 6805 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 6806 u64 page_line_mask; 6807 gpa_t gpa; 6808 char *kaddr; 6809 bool exchanged; 6810 6811 /* guests cmpxchg8b have to be emulated atomically */ 6812 if (bytes > 8 || (bytes & (bytes - 1))) 6813 goto emul_write; 6814 6815 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL); 6816 6817 if (gpa == UNMAPPED_GVA || 6818 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE) 6819 goto emul_write; 6820 6821 /* 6822 * Emulate the atomic as a straight write to avoid #AC if SLD is 6823 * enabled in the host and the access splits a cache line. 6824 */ 6825 if (boot_cpu_has(X86_FEATURE_SPLIT_LOCK_DETECT)) 6826 page_line_mask = ~(cache_line_size() - 1); 6827 else 6828 page_line_mask = PAGE_MASK; 6829 6830 if (((gpa + bytes - 1) & page_line_mask) != (gpa & page_line_mask)) 6831 goto emul_write; 6832 6833 if (kvm_vcpu_map(vcpu, gpa_to_gfn(gpa), &map)) 6834 goto emul_write; 6835 6836 kaddr = map.hva + offset_in_page(gpa); 6837 6838 switch (bytes) { 6839 case 1: 6840 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new); 6841 break; 6842 case 2: 6843 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new); 6844 break; 6845 case 4: 6846 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new); 6847 break; 6848 case 8: 6849 exchanged = CMPXCHG64(kaddr, old, new); 6850 break; 6851 default: 6852 BUG(); 6853 } 6854 6855 kvm_vcpu_unmap(vcpu, &map, true); 6856 6857 if (!exchanged) 6858 return X86EMUL_CMPXCHG_FAILED; 6859 6860 kvm_page_track_write(vcpu, gpa, new, bytes); 6861 6862 return X86EMUL_CONTINUE; 6863 6864 emul_write: 6865 printk_once(KERN_WARNING "kvm: emulating exchange as write\n"); 6866 6867 return emulator_write_emulated(ctxt, addr, new, bytes, exception); 6868 } 6869 6870 static int kernel_pio(struct kvm_vcpu *vcpu, void *pd) 6871 { 6872 int r = 0, i; 6873 6874 for (i = 0; i < vcpu->arch.pio.count; i++) { 6875 if (vcpu->arch.pio.in) 6876 r = kvm_io_bus_read(vcpu, KVM_PIO_BUS, vcpu->arch.pio.port, 6877 vcpu->arch.pio.size, pd); 6878 else 6879 r = kvm_io_bus_write(vcpu, KVM_PIO_BUS, 6880 vcpu->arch.pio.port, vcpu->arch.pio.size, 6881 pd); 6882 if (r) 6883 break; 6884 pd += vcpu->arch.pio.size; 6885 } 6886 return r; 6887 } 6888 6889 static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size, 6890 unsigned short port, void *val, 6891 unsigned int count, bool in) 6892 { 6893 vcpu->arch.pio.port = port; 6894 vcpu->arch.pio.in = in; 6895 vcpu->arch.pio.count = count; 6896 vcpu->arch.pio.size = size; 6897 6898 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) { 6899 vcpu->arch.pio.count = 0; 6900 return 1; 6901 } 6902 6903 vcpu->run->exit_reason = KVM_EXIT_IO; 6904 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT; 6905 vcpu->run->io.size = size; 6906 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE; 6907 vcpu->run->io.count = count; 6908 vcpu->run->io.port = port; 6909 6910 return 0; 6911 } 6912 6913 static int emulator_pio_in(struct kvm_vcpu *vcpu, int size, 6914 unsigned short port, void *val, unsigned int count) 6915 { 6916 int ret; 6917 6918 if (vcpu->arch.pio.count) 6919 goto data_avail; 6920 6921 memset(vcpu->arch.pio_data, 0, size * count); 6922 6923 ret = emulator_pio_in_out(vcpu, size, port, val, count, true); 6924 if (ret) { 6925 data_avail: 6926 memcpy(val, vcpu->arch.pio_data, size * count); 6927 trace_kvm_pio(KVM_PIO_IN, port, size, count, vcpu->arch.pio_data); 6928 vcpu->arch.pio.count = 0; 6929 return 1; 6930 } 6931 6932 return 0; 6933 } 6934 6935 static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt, 6936 int size, unsigned short port, void *val, 6937 unsigned int count) 6938 { 6939 return emulator_pio_in(emul_to_vcpu(ctxt), size, port, val, count); 6940 6941 } 6942 6943 static int emulator_pio_out(struct kvm_vcpu *vcpu, int size, 6944 unsigned short port, const void *val, 6945 unsigned int count) 6946 { 6947 memcpy(vcpu->arch.pio_data, val, size * count); 6948 trace_kvm_pio(KVM_PIO_OUT, port, size, count, vcpu->arch.pio_data); 6949 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false); 6950 } 6951 6952 static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt, 6953 int size, unsigned short port, 6954 const void *val, unsigned int count) 6955 { 6956 return emulator_pio_out(emul_to_vcpu(ctxt), size, port, val, count); 6957 } 6958 6959 static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg) 6960 { 6961 return static_call(kvm_x86_get_segment_base)(vcpu, seg); 6962 } 6963 6964 static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address) 6965 { 6966 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address); 6967 } 6968 6969 static int kvm_emulate_wbinvd_noskip(struct kvm_vcpu *vcpu) 6970 { 6971 if (!need_emulate_wbinvd(vcpu)) 6972 return X86EMUL_CONTINUE; 6973 6974 if (static_call(kvm_x86_has_wbinvd_exit)()) { 6975 int cpu = get_cpu(); 6976 6977 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask); 6978 on_each_cpu_mask(vcpu->arch.wbinvd_dirty_mask, 6979 wbinvd_ipi, NULL, 1); 6980 put_cpu(); 6981 cpumask_clear(vcpu->arch.wbinvd_dirty_mask); 6982 } else 6983 wbinvd(); 6984 return X86EMUL_CONTINUE; 6985 } 6986 6987 int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu) 6988 { 6989 kvm_emulate_wbinvd_noskip(vcpu); 6990 return kvm_skip_emulated_instruction(vcpu); 6991 } 6992 EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd); 6993 6994 6995 6996 static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt) 6997 { 6998 kvm_emulate_wbinvd_noskip(emul_to_vcpu(ctxt)); 6999 } 7000 7001 static void emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr, 7002 unsigned long *dest) 7003 { 7004 kvm_get_dr(emul_to_vcpu(ctxt), dr, dest); 7005 } 7006 7007 static int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr, 7008 unsigned long value) 7009 { 7010 7011 return kvm_set_dr(emul_to_vcpu(ctxt), dr, value); 7012 } 7013 7014 static u64 mk_cr_64(u64 curr_cr, u32 new_val) 7015 { 7016 return (curr_cr & ~((1ULL << 32) - 1)) | new_val; 7017 } 7018 7019 static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr) 7020 { 7021 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 7022 unsigned long value; 7023 7024 switch (cr) { 7025 case 0: 7026 value = kvm_read_cr0(vcpu); 7027 break; 7028 case 2: 7029 value = vcpu->arch.cr2; 7030 break; 7031 case 3: 7032 value = kvm_read_cr3(vcpu); 7033 break; 7034 case 4: 7035 value = kvm_read_cr4(vcpu); 7036 break; 7037 case 8: 7038 value = kvm_get_cr8(vcpu); 7039 break; 7040 default: 7041 kvm_err("%s: unexpected cr %u\n", __func__, cr); 7042 return 0; 7043 } 7044 7045 return value; 7046 } 7047 7048 static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val) 7049 { 7050 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 7051 int res = 0; 7052 7053 switch (cr) { 7054 case 0: 7055 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val)); 7056 break; 7057 case 2: 7058 vcpu->arch.cr2 = val; 7059 break; 7060 case 3: 7061 res = kvm_set_cr3(vcpu, val); 7062 break; 7063 case 4: 7064 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val)); 7065 break; 7066 case 8: 7067 res = kvm_set_cr8(vcpu, val); 7068 break; 7069 default: 7070 kvm_err("%s: unexpected cr %u\n", __func__, cr); 7071 res = -1; 7072 } 7073 7074 return res; 7075 } 7076 7077 static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt) 7078 { 7079 return static_call(kvm_x86_get_cpl)(emul_to_vcpu(ctxt)); 7080 } 7081 7082 static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt) 7083 { 7084 static_call(kvm_x86_get_gdt)(emul_to_vcpu(ctxt), dt); 7085 } 7086 7087 static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt) 7088 { 7089 static_call(kvm_x86_get_idt)(emul_to_vcpu(ctxt), dt); 7090 } 7091 7092 static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt) 7093 { 7094 static_call(kvm_x86_set_gdt)(emul_to_vcpu(ctxt), dt); 7095 } 7096 7097 static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt) 7098 { 7099 static_call(kvm_x86_set_idt)(emul_to_vcpu(ctxt), dt); 7100 } 7101 7102 static unsigned long emulator_get_cached_segment_base( 7103 struct x86_emulate_ctxt *ctxt, int seg) 7104 { 7105 return get_segment_base(emul_to_vcpu(ctxt), seg); 7106 } 7107 7108 static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector, 7109 struct desc_struct *desc, u32 *base3, 7110 int seg) 7111 { 7112 struct kvm_segment var; 7113 7114 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg); 7115 *selector = var.selector; 7116 7117 if (var.unusable) { 7118 memset(desc, 0, sizeof(*desc)); 7119 if (base3) 7120 *base3 = 0; 7121 return false; 7122 } 7123 7124 if (var.g) 7125 var.limit >>= 12; 7126 set_desc_limit(desc, var.limit); 7127 set_desc_base(desc, (unsigned long)var.base); 7128 #ifdef CONFIG_X86_64 7129 if (base3) 7130 *base3 = var.base >> 32; 7131 #endif 7132 desc->type = var.type; 7133 desc->s = var.s; 7134 desc->dpl = var.dpl; 7135 desc->p = var.present; 7136 desc->avl = var.avl; 7137 desc->l = var.l; 7138 desc->d = var.db; 7139 desc->g = var.g; 7140 7141 return true; 7142 } 7143 7144 static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector, 7145 struct desc_struct *desc, u32 base3, 7146 int seg) 7147 { 7148 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 7149 struct kvm_segment var; 7150 7151 var.selector = selector; 7152 var.base = get_desc_base(desc); 7153 #ifdef CONFIG_X86_64 7154 var.base |= ((u64)base3) << 32; 7155 #endif 7156 var.limit = get_desc_limit(desc); 7157 if (desc->g) 7158 var.limit = (var.limit << 12) | 0xfff; 7159 var.type = desc->type; 7160 var.dpl = desc->dpl; 7161 var.db = desc->d; 7162 var.s = desc->s; 7163 var.l = desc->l; 7164 var.g = desc->g; 7165 var.avl = desc->avl; 7166 var.present = desc->p; 7167 var.unusable = !var.present; 7168 var.padding = 0; 7169 7170 kvm_set_segment(vcpu, &var, seg); 7171 return; 7172 } 7173 7174 static int emulator_get_msr(struct x86_emulate_ctxt *ctxt, 7175 u32 msr_index, u64 *pdata) 7176 { 7177 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 7178 int r; 7179 7180 r = kvm_get_msr(vcpu, msr_index, pdata); 7181 7182 if (r && kvm_get_msr_user_space(vcpu, msr_index, r)) { 7183 /* Bounce to user space */ 7184 return X86EMUL_IO_NEEDED; 7185 } 7186 7187 return r; 7188 } 7189 7190 static int emulator_set_msr(struct x86_emulate_ctxt *ctxt, 7191 u32 msr_index, u64 data) 7192 { 7193 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 7194 int r; 7195 7196 r = kvm_set_msr(vcpu, msr_index, data); 7197 7198 if (r && kvm_set_msr_user_space(vcpu, msr_index, data, r)) { 7199 /* Bounce to user space */ 7200 return X86EMUL_IO_NEEDED; 7201 } 7202 7203 return r; 7204 } 7205 7206 static u64 emulator_get_smbase(struct x86_emulate_ctxt *ctxt) 7207 { 7208 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 7209 7210 return vcpu->arch.smbase; 7211 } 7212 7213 static void emulator_set_smbase(struct x86_emulate_ctxt *ctxt, u64 smbase) 7214 { 7215 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 7216 7217 vcpu->arch.smbase = smbase; 7218 } 7219 7220 static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt, 7221 u32 pmc) 7222 { 7223 return kvm_pmu_is_valid_rdpmc_ecx(emul_to_vcpu(ctxt), pmc); 7224 } 7225 7226 static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt, 7227 u32 pmc, u64 *pdata) 7228 { 7229 return kvm_pmu_rdpmc(emul_to_vcpu(ctxt), pmc, pdata); 7230 } 7231 7232 static void emulator_halt(struct x86_emulate_ctxt *ctxt) 7233 { 7234 emul_to_vcpu(ctxt)->arch.halt_request = 1; 7235 } 7236 7237 static int emulator_intercept(struct x86_emulate_ctxt *ctxt, 7238 struct x86_instruction_info *info, 7239 enum x86_intercept_stage stage) 7240 { 7241 return static_call(kvm_x86_check_intercept)(emul_to_vcpu(ctxt), info, stage, 7242 &ctxt->exception); 7243 } 7244 7245 static bool emulator_get_cpuid(struct x86_emulate_ctxt *ctxt, 7246 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx, 7247 bool exact_only) 7248 { 7249 return kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx, exact_only); 7250 } 7251 7252 static bool emulator_guest_has_long_mode(struct x86_emulate_ctxt *ctxt) 7253 { 7254 return guest_cpuid_has(emul_to_vcpu(ctxt), X86_FEATURE_LM); 7255 } 7256 7257 static bool emulator_guest_has_movbe(struct x86_emulate_ctxt *ctxt) 7258 { 7259 return guest_cpuid_has(emul_to_vcpu(ctxt), X86_FEATURE_MOVBE); 7260 } 7261 7262 static bool emulator_guest_has_fxsr(struct x86_emulate_ctxt *ctxt) 7263 { 7264 return guest_cpuid_has(emul_to_vcpu(ctxt), X86_FEATURE_FXSR); 7265 } 7266 7267 static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg) 7268 { 7269 return kvm_register_read_raw(emul_to_vcpu(ctxt), reg); 7270 } 7271 7272 static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val) 7273 { 7274 kvm_register_write_raw(emul_to_vcpu(ctxt), reg, val); 7275 } 7276 7277 static void emulator_set_nmi_mask(struct x86_emulate_ctxt *ctxt, bool masked) 7278 { 7279 static_call(kvm_x86_set_nmi_mask)(emul_to_vcpu(ctxt), masked); 7280 } 7281 7282 static unsigned emulator_get_hflags(struct x86_emulate_ctxt *ctxt) 7283 { 7284 return emul_to_vcpu(ctxt)->arch.hflags; 7285 } 7286 7287 static void emulator_exiting_smm(struct x86_emulate_ctxt *ctxt) 7288 { 7289 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 7290 7291 kvm_smm_changed(vcpu, false); 7292 } 7293 7294 static int emulator_leave_smm(struct x86_emulate_ctxt *ctxt, 7295 const char *smstate) 7296 { 7297 return static_call(kvm_x86_leave_smm)(emul_to_vcpu(ctxt), smstate); 7298 } 7299 7300 static void emulator_triple_fault(struct x86_emulate_ctxt *ctxt) 7301 { 7302 kvm_make_request(KVM_REQ_TRIPLE_FAULT, emul_to_vcpu(ctxt)); 7303 } 7304 7305 static int emulator_set_xcr(struct x86_emulate_ctxt *ctxt, u32 index, u64 xcr) 7306 { 7307 return __kvm_set_xcr(emul_to_vcpu(ctxt), index, xcr); 7308 } 7309 7310 static const struct x86_emulate_ops emulate_ops = { 7311 .read_gpr = emulator_read_gpr, 7312 .write_gpr = emulator_write_gpr, 7313 .read_std = emulator_read_std, 7314 .write_std = emulator_write_std, 7315 .read_phys = kvm_read_guest_phys_system, 7316 .fetch = kvm_fetch_guest_virt, 7317 .read_emulated = emulator_read_emulated, 7318 .write_emulated = emulator_write_emulated, 7319 .cmpxchg_emulated = emulator_cmpxchg_emulated, 7320 .invlpg = emulator_invlpg, 7321 .pio_in_emulated = emulator_pio_in_emulated, 7322 .pio_out_emulated = emulator_pio_out_emulated, 7323 .get_segment = emulator_get_segment, 7324 .set_segment = emulator_set_segment, 7325 .get_cached_segment_base = emulator_get_cached_segment_base, 7326 .get_gdt = emulator_get_gdt, 7327 .get_idt = emulator_get_idt, 7328 .set_gdt = emulator_set_gdt, 7329 .set_idt = emulator_set_idt, 7330 .get_cr = emulator_get_cr, 7331 .set_cr = emulator_set_cr, 7332 .cpl = emulator_get_cpl, 7333 .get_dr = emulator_get_dr, 7334 .set_dr = emulator_set_dr, 7335 .get_smbase = emulator_get_smbase, 7336 .set_smbase = emulator_set_smbase, 7337 .set_msr = emulator_set_msr, 7338 .get_msr = emulator_get_msr, 7339 .check_pmc = emulator_check_pmc, 7340 .read_pmc = emulator_read_pmc, 7341 .halt = emulator_halt, 7342 .wbinvd = emulator_wbinvd, 7343 .fix_hypercall = emulator_fix_hypercall, 7344 .intercept = emulator_intercept, 7345 .get_cpuid = emulator_get_cpuid, 7346 .guest_has_long_mode = emulator_guest_has_long_mode, 7347 .guest_has_movbe = emulator_guest_has_movbe, 7348 .guest_has_fxsr = emulator_guest_has_fxsr, 7349 .set_nmi_mask = emulator_set_nmi_mask, 7350 .get_hflags = emulator_get_hflags, 7351 .exiting_smm = emulator_exiting_smm, 7352 .leave_smm = emulator_leave_smm, 7353 .triple_fault = emulator_triple_fault, 7354 .set_xcr = emulator_set_xcr, 7355 }; 7356 7357 static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask) 7358 { 7359 u32 int_shadow = static_call(kvm_x86_get_interrupt_shadow)(vcpu); 7360 /* 7361 * an sti; sti; sequence only disable interrupts for the first 7362 * instruction. So, if the last instruction, be it emulated or 7363 * not, left the system with the INT_STI flag enabled, it 7364 * means that the last instruction is an sti. We should not 7365 * leave the flag on in this case. The same goes for mov ss 7366 */ 7367 if (int_shadow & mask) 7368 mask = 0; 7369 if (unlikely(int_shadow || mask)) { 7370 static_call(kvm_x86_set_interrupt_shadow)(vcpu, mask); 7371 if (!mask) 7372 kvm_make_request(KVM_REQ_EVENT, vcpu); 7373 } 7374 } 7375 7376 static bool inject_emulated_exception(struct kvm_vcpu *vcpu) 7377 { 7378 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt; 7379 if (ctxt->exception.vector == PF_VECTOR) 7380 return kvm_inject_emulated_page_fault(vcpu, &ctxt->exception); 7381 7382 if (ctxt->exception.error_code_valid) 7383 kvm_queue_exception_e(vcpu, ctxt->exception.vector, 7384 ctxt->exception.error_code); 7385 else 7386 kvm_queue_exception(vcpu, ctxt->exception.vector); 7387 return false; 7388 } 7389 7390 static struct x86_emulate_ctxt *alloc_emulate_ctxt(struct kvm_vcpu *vcpu) 7391 { 7392 struct x86_emulate_ctxt *ctxt; 7393 7394 ctxt = kmem_cache_zalloc(x86_emulator_cache, GFP_KERNEL_ACCOUNT); 7395 if (!ctxt) { 7396 pr_err("kvm: failed to allocate vcpu's emulator\n"); 7397 return NULL; 7398 } 7399 7400 ctxt->vcpu = vcpu; 7401 ctxt->ops = &emulate_ops; 7402 vcpu->arch.emulate_ctxt = ctxt; 7403 7404 return ctxt; 7405 } 7406 7407 static void init_emulate_ctxt(struct kvm_vcpu *vcpu) 7408 { 7409 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt; 7410 int cs_db, cs_l; 7411 7412 static_call(kvm_x86_get_cs_db_l_bits)(vcpu, &cs_db, &cs_l); 7413 7414 ctxt->gpa_available = false; 7415 ctxt->eflags = kvm_get_rflags(vcpu); 7416 ctxt->tf = (ctxt->eflags & X86_EFLAGS_TF) != 0; 7417 7418 ctxt->eip = kvm_rip_read(vcpu); 7419 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL : 7420 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 : 7421 (cs_l && is_long_mode(vcpu)) ? X86EMUL_MODE_PROT64 : 7422 cs_db ? X86EMUL_MODE_PROT32 : 7423 X86EMUL_MODE_PROT16; 7424 BUILD_BUG_ON(HF_GUEST_MASK != X86EMUL_GUEST_MASK); 7425 BUILD_BUG_ON(HF_SMM_MASK != X86EMUL_SMM_MASK); 7426 BUILD_BUG_ON(HF_SMM_INSIDE_NMI_MASK != X86EMUL_SMM_INSIDE_NMI_MASK); 7427 7428 ctxt->interruptibility = 0; 7429 ctxt->have_exception = false; 7430 ctxt->exception.vector = -1; 7431 ctxt->perm_ok = false; 7432 7433 init_decode_cache(ctxt); 7434 vcpu->arch.emulate_regs_need_sync_from_vcpu = false; 7435 } 7436 7437 void kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip) 7438 { 7439 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt; 7440 int ret; 7441 7442 init_emulate_ctxt(vcpu); 7443 7444 ctxt->op_bytes = 2; 7445 ctxt->ad_bytes = 2; 7446 ctxt->_eip = ctxt->eip + inc_eip; 7447 ret = emulate_int_real(ctxt, irq); 7448 7449 if (ret != X86EMUL_CONTINUE) { 7450 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); 7451 } else { 7452 ctxt->eip = ctxt->_eip; 7453 kvm_rip_write(vcpu, ctxt->eip); 7454 kvm_set_rflags(vcpu, ctxt->eflags); 7455 } 7456 } 7457 EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt); 7458 7459 static void prepare_emulation_failure_exit(struct kvm_vcpu *vcpu) 7460 { 7461 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt; 7462 u32 insn_size = ctxt->fetch.end - ctxt->fetch.data; 7463 struct kvm_run *run = vcpu->run; 7464 7465 run->exit_reason = KVM_EXIT_INTERNAL_ERROR; 7466 run->emulation_failure.suberror = KVM_INTERNAL_ERROR_EMULATION; 7467 run->emulation_failure.ndata = 0; 7468 run->emulation_failure.flags = 0; 7469 7470 if (insn_size) { 7471 run->emulation_failure.ndata = 3; 7472 run->emulation_failure.flags |= 7473 KVM_INTERNAL_ERROR_EMULATION_FLAG_INSTRUCTION_BYTES; 7474 run->emulation_failure.insn_size = insn_size; 7475 memset(run->emulation_failure.insn_bytes, 0x90, 7476 sizeof(run->emulation_failure.insn_bytes)); 7477 memcpy(run->emulation_failure.insn_bytes, 7478 ctxt->fetch.data, insn_size); 7479 } 7480 } 7481 7482 static int handle_emulation_failure(struct kvm_vcpu *vcpu, int emulation_type) 7483 { 7484 struct kvm *kvm = vcpu->kvm; 7485 7486 ++vcpu->stat.insn_emulation_fail; 7487 trace_kvm_emulate_insn_failed(vcpu); 7488 7489 if (emulation_type & EMULTYPE_VMWARE_GP) { 7490 kvm_queue_exception_e(vcpu, GP_VECTOR, 0); 7491 return 1; 7492 } 7493 7494 if (kvm->arch.exit_on_emulation_error || 7495 (emulation_type & EMULTYPE_SKIP)) { 7496 prepare_emulation_failure_exit(vcpu); 7497 return 0; 7498 } 7499 7500 kvm_queue_exception(vcpu, UD_VECTOR); 7501 7502 if (!is_guest_mode(vcpu) && static_call(kvm_x86_get_cpl)(vcpu) == 0) { 7503 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR; 7504 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION; 7505 vcpu->run->internal.ndata = 0; 7506 return 0; 7507 } 7508 7509 return 1; 7510 } 7511 7512 static bool reexecute_instruction(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa, 7513 bool write_fault_to_shadow_pgtable, 7514 int emulation_type) 7515 { 7516 gpa_t gpa = cr2_or_gpa; 7517 kvm_pfn_t pfn; 7518 7519 if (!(emulation_type & EMULTYPE_ALLOW_RETRY_PF)) 7520 return false; 7521 7522 if (WARN_ON_ONCE(is_guest_mode(vcpu)) || 7523 WARN_ON_ONCE(!(emulation_type & EMULTYPE_PF))) 7524 return false; 7525 7526 if (!vcpu->arch.mmu->direct_map) { 7527 /* 7528 * Write permission should be allowed since only 7529 * write access need to be emulated. 7530 */ 7531 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2_or_gpa, NULL); 7532 7533 /* 7534 * If the mapping is invalid in guest, let cpu retry 7535 * it to generate fault. 7536 */ 7537 if (gpa == UNMAPPED_GVA) 7538 return true; 7539 } 7540 7541 /* 7542 * Do not retry the unhandleable instruction if it faults on the 7543 * readonly host memory, otherwise it will goto a infinite loop: 7544 * retry instruction -> write #PF -> emulation fail -> retry 7545 * instruction -> ... 7546 */ 7547 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa)); 7548 7549 /* 7550 * If the instruction failed on the error pfn, it can not be fixed, 7551 * report the error to userspace. 7552 */ 7553 if (is_error_noslot_pfn(pfn)) 7554 return false; 7555 7556 kvm_release_pfn_clean(pfn); 7557 7558 /* The instructions are well-emulated on direct mmu. */ 7559 if (vcpu->arch.mmu->direct_map) { 7560 unsigned int indirect_shadow_pages; 7561 7562 write_lock(&vcpu->kvm->mmu_lock); 7563 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages; 7564 write_unlock(&vcpu->kvm->mmu_lock); 7565 7566 if (indirect_shadow_pages) 7567 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa)); 7568 7569 return true; 7570 } 7571 7572 /* 7573 * if emulation was due to access to shadowed page table 7574 * and it failed try to unshadow page and re-enter the 7575 * guest to let CPU execute the instruction. 7576 */ 7577 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa)); 7578 7579 /* 7580 * If the access faults on its page table, it can not 7581 * be fixed by unprotecting shadow page and it should 7582 * be reported to userspace. 7583 */ 7584 return !write_fault_to_shadow_pgtable; 7585 } 7586 7587 static bool retry_instruction(struct x86_emulate_ctxt *ctxt, 7588 gpa_t cr2_or_gpa, int emulation_type) 7589 { 7590 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 7591 unsigned long last_retry_eip, last_retry_addr, gpa = cr2_or_gpa; 7592 7593 last_retry_eip = vcpu->arch.last_retry_eip; 7594 last_retry_addr = vcpu->arch.last_retry_addr; 7595 7596 /* 7597 * If the emulation is caused by #PF and it is non-page_table 7598 * writing instruction, it means the VM-EXIT is caused by shadow 7599 * page protected, we can zap the shadow page and retry this 7600 * instruction directly. 7601 * 7602 * Note: if the guest uses a non-page-table modifying instruction 7603 * on the PDE that points to the instruction, then we will unmap 7604 * the instruction and go to an infinite loop. So, we cache the 7605 * last retried eip and the last fault address, if we meet the eip 7606 * and the address again, we can break out of the potential infinite 7607 * loop. 7608 */ 7609 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0; 7610 7611 if (!(emulation_type & EMULTYPE_ALLOW_RETRY_PF)) 7612 return false; 7613 7614 if (WARN_ON_ONCE(is_guest_mode(vcpu)) || 7615 WARN_ON_ONCE(!(emulation_type & EMULTYPE_PF))) 7616 return false; 7617 7618 if (x86_page_table_writing_insn(ctxt)) 7619 return false; 7620 7621 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2_or_gpa) 7622 return false; 7623 7624 vcpu->arch.last_retry_eip = ctxt->eip; 7625 vcpu->arch.last_retry_addr = cr2_or_gpa; 7626 7627 if (!vcpu->arch.mmu->direct_map) 7628 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2_or_gpa, NULL); 7629 7630 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa)); 7631 7632 return true; 7633 } 7634 7635 static int complete_emulated_mmio(struct kvm_vcpu *vcpu); 7636 static int complete_emulated_pio(struct kvm_vcpu *vcpu); 7637 7638 static void kvm_smm_changed(struct kvm_vcpu *vcpu, bool entering_smm) 7639 { 7640 trace_kvm_smm_transition(vcpu->vcpu_id, vcpu->arch.smbase, entering_smm); 7641 7642 if (entering_smm) { 7643 vcpu->arch.hflags |= HF_SMM_MASK; 7644 } else { 7645 vcpu->arch.hflags &= ~(HF_SMM_MASK | HF_SMM_INSIDE_NMI_MASK); 7646 7647 /* Process a latched INIT or SMI, if any. */ 7648 kvm_make_request(KVM_REQ_EVENT, vcpu); 7649 } 7650 7651 kvm_mmu_reset_context(vcpu); 7652 } 7653 7654 static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7, 7655 unsigned long *db) 7656 { 7657 u32 dr6 = 0; 7658 int i; 7659 u32 enable, rwlen; 7660 7661 enable = dr7; 7662 rwlen = dr7 >> 16; 7663 for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4) 7664 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr) 7665 dr6 |= (1 << i); 7666 return dr6; 7667 } 7668 7669 static int kvm_vcpu_do_singlestep(struct kvm_vcpu *vcpu) 7670 { 7671 struct kvm_run *kvm_run = vcpu->run; 7672 7673 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) { 7674 kvm_run->debug.arch.dr6 = DR6_BS | DR6_ACTIVE_LOW; 7675 kvm_run->debug.arch.pc = kvm_get_linear_rip(vcpu); 7676 kvm_run->debug.arch.exception = DB_VECTOR; 7677 kvm_run->exit_reason = KVM_EXIT_DEBUG; 7678 return 0; 7679 } 7680 kvm_queue_exception_p(vcpu, DB_VECTOR, DR6_BS); 7681 return 1; 7682 } 7683 7684 int kvm_skip_emulated_instruction(struct kvm_vcpu *vcpu) 7685 { 7686 unsigned long rflags = static_call(kvm_x86_get_rflags)(vcpu); 7687 int r; 7688 7689 r = static_call(kvm_x86_skip_emulated_instruction)(vcpu); 7690 if (unlikely(!r)) 7691 return 0; 7692 7693 /* 7694 * rflags is the old, "raw" value of the flags. The new value has 7695 * not been saved yet. 7696 * 7697 * This is correct even for TF set by the guest, because "the 7698 * processor will not generate this exception after the instruction 7699 * that sets the TF flag". 7700 */ 7701 if (unlikely(rflags & X86_EFLAGS_TF)) 7702 r = kvm_vcpu_do_singlestep(vcpu); 7703 return r; 7704 } 7705 EXPORT_SYMBOL_GPL(kvm_skip_emulated_instruction); 7706 7707 static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r) 7708 { 7709 if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) && 7710 (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) { 7711 struct kvm_run *kvm_run = vcpu->run; 7712 unsigned long eip = kvm_get_linear_rip(vcpu); 7713 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0, 7714 vcpu->arch.guest_debug_dr7, 7715 vcpu->arch.eff_db); 7716 7717 if (dr6 != 0) { 7718 kvm_run->debug.arch.dr6 = dr6 | DR6_ACTIVE_LOW; 7719 kvm_run->debug.arch.pc = eip; 7720 kvm_run->debug.arch.exception = DB_VECTOR; 7721 kvm_run->exit_reason = KVM_EXIT_DEBUG; 7722 *r = 0; 7723 return true; 7724 } 7725 } 7726 7727 if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) && 7728 !(kvm_get_rflags(vcpu) & X86_EFLAGS_RF)) { 7729 unsigned long eip = kvm_get_linear_rip(vcpu); 7730 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0, 7731 vcpu->arch.dr7, 7732 vcpu->arch.db); 7733 7734 if (dr6 != 0) { 7735 kvm_queue_exception_p(vcpu, DB_VECTOR, dr6); 7736 *r = 1; 7737 return true; 7738 } 7739 } 7740 7741 return false; 7742 } 7743 7744 static bool is_vmware_backdoor_opcode(struct x86_emulate_ctxt *ctxt) 7745 { 7746 switch (ctxt->opcode_len) { 7747 case 1: 7748 switch (ctxt->b) { 7749 case 0xe4: /* IN */ 7750 case 0xe5: 7751 case 0xec: 7752 case 0xed: 7753 case 0xe6: /* OUT */ 7754 case 0xe7: 7755 case 0xee: 7756 case 0xef: 7757 case 0x6c: /* INS */ 7758 case 0x6d: 7759 case 0x6e: /* OUTS */ 7760 case 0x6f: 7761 return true; 7762 } 7763 break; 7764 case 2: 7765 switch (ctxt->b) { 7766 case 0x33: /* RDPMC */ 7767 return true; 7768 } 7769 break; 7770 } 7771 7772 return false; 7773 } 7774 7775 /* 7776 * Decode to be emulated instruction. Return EMULATION_OK if success. 7777 */ 7778 int x86_decode_emulated_instruction(struct kvm_vcpu *vcpu, int emulation_type, 7779 void *insn, int insn_len) 7780 { 7781 int r = EMULATION_OK; 7782 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt; 7783 7784 init_emulate_ctxt(vcpu); 7785 7786 /* 7787 * We will reenter on the same instruction since we do not set 7788 * complete_userspace_io. This does not handle watchpoints yet, 7789 * those would be handled in the emulate_ops. 7790 */ 7791 if (!(emulation_type & EMULTYPE_SKIP) && 7792 kvm_vcpu_check_breakpoint(vcpu, &r)) 7793 return r; 7794 7795 r = x86_decode_insn(ctxt, insn, insn_len, emulation_type); 7796 7797 trace_kvm_emulate_insn_start(vcpu); 7798 ++vcpu->stat.insn_emulation; 7799 7800 return r; 7801 } 7802 EXPORT_SYMBOL_GPL(x86_decode_emulated_instruction); 7803 7804 int x86_emulate_instruction(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa, 7805 int emulation_type, void *insn, int insn_len) 7806 { 7807 int r; 7808 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt; 7809 bool writeback = true; 7810 bool write_fault_to_spt; 7811 7812 if (unlikely(!static_call(kvm_x86_can_emulate_instruction)(vcpu, insn, insn_len))) 7813 return 1; 7814 7815 vcpu->arch.l1tf_flush_l1d = true; 7816 7817 /* 7818 * Clear write_fault_to_shadow_pgtable here to ensure it is 7819 * never reused. 7820 */ 7821 write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable; 7822 vcpu->arch.write_fault_to_shadow_pgtable = false; 7823 7824 if (!(emulation_type & EMULTYPE_NO_DECODE)) { 7825 kvm_clear_exception_queue(vcpu); 7826 7827 r = x86_decode_emulated_instruction(vcpu, emulation_type, 7828 insn, insn_len); 7829 if (r != EMULATION_OK) { 7830 if ((emulation_type & EMULTYPE_TRAP_UD) || 7831 (emulation_type & EMULTYPE_TRAP_UD_FORCED)) { 7832 kvm_queue_exception(vcpu, UD_VECTOR); 7833 return 1; 7834 } 7835 if (reexecute_instruction(vcpu, cr2_or_gpa, 7836 write_fault_to_spt, 7837 emulation_type)) 7838 return 1; 7839 if (ctxt->have_exception) { 7840 /* 7841 * #UD should result in just EMULATION_FAILED, and trap-like 7842 * exception should not be encountered during decode. 7843 */ 7844 WARN_ON_ONCE(ctxt->exception.vector == UD_VECTOR || 7845 exception_type(ctxt->exception.vector) == EXCPT_TRAP); 7846 inject_emulated_exception(vcpu); 7847 return 1; 7848 } 7849 return handle_emulation_failure(vcpu, emulation_type); 7850 } 7851 } 7852 7853 if ((emulation_type & EMULTYPE_VMWARE_GP) && 7854 !is_vmware_backdoor_opcode(ctxt)) { 7855 kvm_queue_exception_e(vcpu, GP_VECTOR, 0); 7856 return 1; 7857 } 7858 7859 /* 7860 * Note, EMULTYPE_SKIP is intended for use *only* by vendor callbacks 7861 * for kvm_skip_emulated_instruction(). The caller is responsible for 7862 * updating interruptibility state and injecting single-step #DBs. 7863 */ 7864 if (emulation_type & EMULTYPE_SKIP) { 7865 kvm_rip_write(vcpu, ctxt->_eip); 7866 if (ctxt->eflags & X86_EFLAGS_RF) 7867 kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF); 7868 return 1; 7869 } 7870 7871 if (retry_instruction(ctxt, cr2_or_gpa, emulation_type)) 7872 return 1; 7873 7874 /* this is needed for vmware backdoor interface to work since it 7875 changes registers values during IO operation */ 7876 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) { 7877 vcpu->arch.emulate_regs_need_sync_from_vcpu = false; 7878 emulator_invalidate_register_cache(ctxt); 7879 } 7880 7881 restart: 7882 if (emulation_type & EMULTYPE_PF) { 7883 /* Save the faulting GPA (cr2) in the address field */ 7884 ctxt->exception.address = cr2_or_gpa; 7885 7886 /* With shadow page tables, cr2 contains a GVA or nGPA. */ 7887 if (vcpu->arch.mmu->direct_map) { 7888 ctxt->gpa_available = true; 7889 ctxt->gpa_val = cr2_or_gpa; 7890 } 7891 } else { 7892 /* Sanitize the address out of an abundance of paranoia. */ 7893 ctxt->exception.address = 0; 7894 } 7895 7896 r = x86_emulate_insn(ctxt); 7897 7898 if (r == EMULATION_INTERCEPTED) 7899 return 1; 7900 7901 if (r == EMULATION_FAILED) { 7902 if (reexecute_instruction(vcpu, cr2_or_gpa, write_fault_to_spt, 7903 emulation_type)) 7904 return 1; 7905 7906 return handle_emulation_failure(vcpu, emulation_type); 7907 } 7908 7909 if (ctxt->have_exception) { 7910 r = 1; 7911 if (inject_emulated_exception(vcpu)) 7912 return r; 7913 } else if (vcpu->arch.pio.count) { 7914 if (!vcpu->arch.pio.in) { 7915 /* FIXME: return into emulator if single-stepping. */ 7916 vcpu->arch.pio.count = 0; 7917 } else { 7918 writeback = false; 7919 vcpu->arch.complete_userspace_io = complete_emulated_pio; 7920 } 7921 r = 0; 7922 } else if (vcpu->mmio_needed) { 7923 ++vcpu->stat.mmio_exits; 7924 7925 if (!vcpu->mmio_is_write) 7926 writeback = false; 7927 r = 0; 7928 vcpu->arch.complete_userspace_io = complete_emulated_mmio; 7929 } else if (r == EMULATION_RESTART) 7930 goto restart; 7931 else 7932 r = 1; 7933 7934 if (writeback) { 7935 unsigned long rflags = static_call(kvm_x86_get_rflags)(vcpu); 7936 toggle_interruptibility(vcpu, ctxt->interruptibility); 7937 vcpu->arch.emulate_regs_need_sync_to_vcpu = false; 7938 if (!ctxt->have_exception || 7939 exception_type(ctxt->exception.vector) == EXCPT_TRAP) { 7940 kvm_rip_write(vcpu, ctxt->eip); 7941 if (r && (ctxt->tf || (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP))) 7942 r = kvm_vcpu_do_singlestep(vcpu); 7943 if (kvm_x86_ops.update_emulated_instruction) 7944 static_call(kvm_x86_update_emulated_instruction)(vcpu); 7945 __kvm_set_rflags(vcpu, ctxt->eflags); 7946 } 7947 7948 /* 7949 * For STI, interrupts are shadowed; so KVM_REQ_EVENT will 7950 * do nothing, and it will be requested again as soon as 7951 * the shadow expires. But we still need to check here, 7952 * because POPF has no interrupt shadow. 7953 */ 7954 if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF)) 7955 kvm_make_request(KVM_REQ_EVENT, vcpu); 7956 } else 7957 vcpu->arch.emulate_regs_need_sync_to_vcpu = true; 7958 7959 return r; 7960 } 7961 7962 int kvm_emulate_instruction(struct kvm_vcpu *vcpu, int emulation_type) 7963 { 7964 return x86_emulate_instruction(vcpu, 0, emulation_type, NULL, 0); 7965 } 7966 EXPORT_SYMBOL_GPL(kvm_emulate_instruction); 7967 7968 int kvm_emulate_instruction_from_buffer(struct kvm_vcpu *vcpu, 7969 void *insn, int insn_len) 7970 { 7971 return x86_emulate_instruction(vcpu, 0, 0, insn, insn_len); 7972 } 7973 EXPORT_SYMBOL_GPL(kvm_emulate_instruction_from_buffer); 7974 7975 static int complete_fast_pio_out_port_0x7e(struct kvm_vcpu *vcpu) 7976 { 7977 vcpu->arch.pio.count = 0; 7978 return 1; 7979 } 7980 7981 static int complete_fast_pio_out(struct kvm_vcpu *vcpu) 7982 { 7983 vcpu->arch.pio.count = 0; 7984 7985 if (unlikely(!kvm_is_linear_rip(vcpu, vcpu->arch.pio.linear_rip))) 7986 return 1; 7987 7988 return kvm_skip_emulated_instruction(vcpu); 7989 } 7990 7991 static int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, 7992 unsigned short port) 7993 { 7994 unsigned long val = kvm_rax_read(vcpu); 7995 int ret = emulator_pio_out(vcpu, size, port, &val, 1); 7996 7997 if (ret) 7998 return ret; 7999 8000 /* 8001 * Workaround userspace that relies on old KVM behavior of %rip being 8002 * incremented prior to exiting to userspace to handle "OUT 0x7e". 8003 */ 8004 if (port == 0x7e && 8005 kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_OUT_7E_INC_RIP)) { 8006 vcpu->arch.complete_userspace_io = 8007 complete_fast_pio_out_port_0x7e; 8008 kvm_skip_emulated_instruction(vcpu); 8009 } else { 8010 vcpu->arch.pio.linear_rip = kvm_get_linear_rip(vcpu); 8011 vcpu->arch.complete_userspace_io = complete_fast_pio_out; 8012 } 8013 return 0; 8014 } 8015 8016 static int complete_fast_pio_in(struct kvm_vcpu *vcpu) 8017 { 8018 unsigned long val; 8019 8020 /* We should only ever be called with arch.pio.count equal to 1 */ 8021 BUG_ON(vcpu->arch.pio.count != 1); 8022 8023 if (unlikely(!kvm_is_linear_rip(vcpu, vcpu->arch.pio.linear_rip))) { 8024 vcpu->arch.pio.count = 0; 8025 return 1; 8026 } 8027 8028 /* For size less than 4 we merge, else we zero extend */ 8029 val = (vcpu->arch.pio.size < 4) ? kvm_rax_read(vcpu) : 0; 8030 8031 /* 8032 * Since vcpu->arch.pio.count == 1 let emulator_pio_in perform 8033 * the copy and tracing 8034 */ 8035 emulator_pio_in(vcpu, vcpu->arch.pio.size, vcpu->arch.pio.port, &val, 1); 8036 kvm_rax_write(vcpu, val); 8037 8038 return kvm_skip_emulated_instruction(vcpu); 8039 } 8040 8041 static int kvm_fast_pio_in(struct kvm_vcpu *vcpu, int size, 8042 unsigned short port) 8043 { 8044 unsigned long val; 8045 int ret; 8046 8047 /* For size less than 4 we merge, else we zero extend */ 8048 val = (size < 4) ? kvm_rax_read(vcpu) : 0; 8049 8050 ret = emulator_pio_in(vcpu, size, port, &val, 1); 8051 if (ret) { 8052 kvm_rax_write(vcpu, val); 8053 return ret; 8054 } 8055 8056 vcpu->arch.pio.linear_rip = kvm_get_linear_rip(vcpu); 8057 vcpu->arch.complete_userspace_io = complete_fast_pio_in; 8058 8059 return 0; 8060 } 8061 8062 int kvm_fast_pio(struct kvm_vcpu *vcpu, int size, unsigned short port, int in) 8063 { 8064 int ret; 8065 8066 if (in) 8067 ret = kvm_fast_pio_in(vcpu, size, port); 8068 else 8069 ret = kvm_fast_pio_out(vcpu, size, port); 8070 return ret && kvm_skip_emulated_instruction(vcpu); 8071 } 8072 EXPORT_SYMBOL_GPL(kvm_fast_pio); 8073 8074 static int kvmclock_cpu_down_prep(unsigned int cpu) 8075 { 8076 __this_cpu_write(cpu_tsc_khz, 0); 8077 return 0; 8078 } 8079 8080 static void tsc_khz_changed(void *data) 8081 { 8082 struct cpufreq_freqs *freq = data; 8083 unsigned long khz = 0; 8084 8085 if (data) 8086 khz = freq->new; 8087 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) 8088 khz = cpufreq_quick_get(raw_smp_processor_id()); 8089 if (!khz) 8090 khz = tsc_khz; 8091 __this_cpu_write(cpu_tsc_khz, khz); 8092 } 8093 8094 #ifdef CONFIG_X86_64 8095 static void kvm_hyperv_tsc_notifier(void) 8096 { 8097 struct kvm *kvm; 8098 struct kvm_vcpu *vcpu; 8099 int cpu; 8100 unsigned long flags; 8101 8102 mutex_lock(&kvm_lock); 8103 list_for_each_entry(kvm, &vm_list, vm_list) 8104 kvm_make_mclock_inprogress_request(kvm); 8105 8106 hyperv_stop_tsc_emulation(); 8107 8108 /* TSC frequency always matches when on Hyper-V */ 8109 for_each_present_cpu(cpu) 8110 per_cpu(cpu_tsc_khz, cpu) = tsc_khz; 8111 kvm_max_guest_tsc_khz = tsc_khz; 8112 8113 list_for_each_entry(kvm, &vm_list, vm_list) { 8114 struct kvm_arch *ka = &kvm->arch; 8115 8116 spin_lock_irqsave(&ka->pvclock_gtod_sync_lock, flags); 8117 pvclock_update_vm_gtod_copy(kvm); 8118 spin_unlock_irqrestore(&ka->pvclock_gtod_sync_lock, flags); 8119 8120 kvm_for_each_vcpu(cpu, vcpu, kvm) 8121 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 8122 8123 kvm_for_each_vcpu(cpu, vcpu, kvm) 8124 kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu); 8125 } 8126 mutex_unlock(&kvm_lock); 8127 } 8128 #endif 8129 8130 static void __kvmclock_cpufreq_notifier(struct cpufreq_freqs *freq, int cpu) 8131 { 8132 struct kvm *kvm; 8133 struct kvm_vcpu *vcpu; 8134 int i, send_ipi = 0; 8135 8136 /* 8137 * We allow guests to temporarily run on slowing clocks, 8138 * provided we notify them after, or to run on accelerating 8139 * clocks, provided we notify them before. Thus time never 8140 * goes backwards. 8141 * 8142 * However, we have a problem. We can't atomically update 8143 * the frequency of a given CPU from this function; it is 8144 * merely a notifier, which can be called from any CPU. 8145 * Changing the TSC frequency at arbitrary points in time 8146 * requires a recomputation of local variables related to 8147 * the TSC for each VCPU. We must flag these local variables 8148 * to be updated and be sure the update takes place with the 8149 * new frequency before any guests proceed. 8150 * 8151 * Unfortunately, the combination of hotplug CPU and frequency 8152 * change creates an intractable locking scenario; the order 8153 * of when these callouts happen is undefined with respect to 8154 * CPU hotplug, and they can race with each other. As such, 8155 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is 8156 * undefined; you can actually have a CPU frequency change take 8157 * place in between the computation of X and the setting of the 8158 * variable. To protect against this problem, all updates of 8159 * the per_cpu tsc_khz variable are done in an interrupt 8160 * protected IPI, and all callers wishing to update the value 8161 * must wait for a synchronous IPI to complete (which is trivial 8162 * if the caller is on the CPU already). This establishes the 8163 * necessary total order on variable updates. 8164 * 8165 * Note that because a guest time update may take place 8166 * anytime after the setting of the VCPU's request bit, the 8167 * correct TSC value must be set before the request. However, 8168 * to ensure the update actually makes it to any guest which 8169 * starts running in hardware virtualization between the set 8170 * and the acquisition of the spinlock, we must also ping the 8171 * CPU after setting the request bit. 8172 * 8173 */ 8174 8175 smp_call_function_single(cpu, tsc_khz_changed, freq, 1); 8176 8177 mutex_lock(&kvm_lock); 8178 list_for_each_entry(kvm, &vm_list, vm_list) { 8179 kvm_for_each_vcpu(i, vcpu, kvm) { 8180 if (vcpu->cpu != cpu) 8181 continue; 8182 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 8183 if (vcpu->cpu != raw_smp_processor_id()) 8184 send_ipi = 1; 8185 } 8186 } 8187 mutex_unlock(&kvm_lock); 8188 8189 if (freq->old < freq->new && send_ipi) { 8190 /* 8191 * We upscale the frequency. Must make the guest 8192 * doesn't see old kvmclock values while running with 8193 * the new frequency, otherwise we risk the guest sees 8194 * time go backwards. 8195 * 8196 * In case we update the frequency for another cpu 8197 * (which might be in guest context) send an interrupt 8198 * to kick the cpu out of guest context. Next time 8199 * guest context is entered kvmclock will be updated, 8200 * so the guest will not see stale values. 8201 */ 8202 smp_call_function_single(cpu, tsc_khz_changed, freq, 1); 8203 } 8204 } 8205 8206 static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val, 8207 void *data) 8208 { 8209 struct cpufreq_freqs *freq = data; 8210 int cpu; 8211 8212 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new) 8213 return 0; 8214 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new) 8215 return 0; 8216 8217 for_each_cpu(cpu, freq->policy->cpus) 8218 __kvmclock_cpufreq_notifier(freq, cpu); 8219 8220 return 0; 8221 } 8222 8223 static struct notifier_block kvmclock_cpufreq_notifier_block = { 8224 .notifier_call = kvmclock_cpufreq_notifier 8225 }; 8226 8227 static int kvmclock_cpu_online(unsigned int cpu) 8228 { 8229 tsc_khz_changed(NULL); 8230 return 0; 8231 } 8232 8233 static void kvm_timer_init(void) 8234 { 8235 max_tsc_khz = tsc_khz; 8236 8237 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) { 8238 #ifdef CONFIG_CPU_FREQ 8239 struct cpufreq_policy *policy; 8240 int cpu; 8241 8242 cpu = get_cpu(); 8243 policy = cpufreq_cpu_get(cpu); 8244 if (policy) { 8245 if (policy->cpuinfo.max_freq) 8246 max_tsc_khz = policy->cpuinfo.max_freq; 8247 cpufreq_cpu_put(policy); 8248 } 8249 put_cpu(); 8250 #endif 8251 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block, 8252 CPUFREQ_TRANSITION_NOTIFIER); 8253 } 8254 8255 cpuhp_setup_state(CPUHP_AP_X86_KVM_CLK_ONLINE, "x86/kvm/clk:online", 8256 kvmclock_cpu_online, kvmclock_cpu_down_prep); 8257 } 8258 8259 DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu); 8260 EXPORT_PER_CPU_SYMBOL_GPL(current_vcpu); 8261 8262 int kvm_is_in_guest(void) 8263 { 8264 return __this_cpu_read(current_vcpu) != NULL; 8265 } 8266 8267 static int kvm_is_user_mode(void) 8268 { 8269 int user_mode = 3; 8270 8271 if (__this_cpu_read(current_vcpu)) 8272 user_mode = static_call(kvm_x86_get_cpl)(__this_cpu_read(current_vcpu)); 8273 8274 return user_mode != 0; 8275 } 8276 8277 static unsigned long kvm_get_guest_ip(void) 8278 { 8279 unsigned long ip = 0; 8280 8281 if (__this_cpu_read(current_vcpu)) 8282 ip = kvm_rip_read(__this_cpu_read(current_vcpu)); 8283 8284 return ip; 8285 } 8286 8287 static void kvm_handle_intel_pt_intr(void) 8288 { 8289 struct kvm_vcpu *vcpu = __this_cpu_read(current_vcpu); 8290 8291 kvm_make_request(KVM_REQ_PMI, vcpu); 8292 __set_bit(MSR_CORE_PERF_GLOBAL_OVF_CTRL_TRACE_TOPA_PMI_BIT, 8293 (unsigned long *)&vcpu->arch.pmu.global_status); 8294 } 8295 8296 static struct perf_guest_info_callbacks kvm_guest_cbs = { 8297 .is_in_guest = kvm_is_in_guest, 8298 .is_user_mode = kvm_is_user_mode, 8299 .get_guest_ip = kvm_get_guest_ip, 8300 .handle_intel_pt_intr = kvm_handle_intel_pt_intr, 8301 }; 8302 8303 #ifdef CONFIG_X86_64 8304 static void pvclock_gtod_update_fn(struct work_struct *work) 8305 { 8306 struct kvm *kvm; 8307 8308 struct kvm_vcpu *vcpu; 8309 int i; 8310 8311 mutex_lock(&kvm_lock); 8312 list_for_each_entry(kvm, &vm_list, vm_list) 8313 kvm_for_each_vcpu(i, vcpu, kvm) 8314 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu); 8315 atomic_set(&kvm_guest_has_master_clock, 0); 8316 mutex_unlock(&kvm_lock); 8317 } 8318 8319 static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn); 8320 8321 /* 8322 * Indirection to move queue_work() out of the tk_core.seq write held 8323 * region to prevent possible deadlocks against time accessors which 8324 * are invoked with work related locks held. 8325 */ 8326 static void pvclock_irq_work_fn(struct irq_work *w) 8327 { 8328 queue_work(system_long_wq, &pvclock_gtod_work); 8329 } 8330 8331 static DEFINE_IRQ_WORK(pvclock_irq_work, pvclock_irq_work_fn); 8332 8333 /* 8334 * Notification about pvclock gtod data update. 8335 */ 8336 static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused, 8337 void *priv) 8338 { 8339 struct pvclock_gtod_data *gtod = &pvclock_gtod_data; 8340 struct timekeeper *tk = priv; 8341 8342 update_pvclock_gtod(tk); 8343 8344 /* 8345 * Disable master clock if host does not trust, or does not use, 8346 * TSC based clocksource. Delegate queue_work() to irq_work as 8347 * this is invoked with tk_core.seq write held. 8348 */ 8349 if (!gtod_is_based_on_tsc(gtod->clock.vclock_mode) && 8350 atomic_read(&kvm_guest_has_master_clock) != 0) 8351 irq_work_queue(&pvclock_irq_work); 8352 return 0; 8353 } 8354 8355 static struct notifier_block pvclock_gtod_notifier = { 8356 .notifier_call = pvclock_gtod_notify, 8357 }; 8358 #endif 8359 8360 int kvm_arch_init(void *opaque) 8361 { 8362 struct kvm_x86_init_ops *ops = opaque; 8363 int r; 8364 8365 if (kvm_x86_ops.hardware_enable) { 8366 printk(KERN_ERR "kvm: already loaded the other module\n"); 8367 r = -EEXIST; 8368 goto out; 8369 } 8370 8371 if (!ops->cpu_has_kvm_support()) { 8372 pr_err_ratelimited("kvm: no hardware support\n"); 8373 r = -EOPNOTSUPP; 8374 goto out; 8375 } 8376 if (ops->disabled_by_bios()) { 8377 pr_err_ratelimited("kvm: disabled by bios\n"); 8378 r = -EOPNOTSUPP; 8379 goto out; 8380 } 8381 8382 /* 8383 * KVM explicitly assumes that the guest has an FPU and 8384 * FXSAVE/FXRSTOR. For example, the KVM_GET_FPU explicitly casts the 8385 * vCPU's FPU state as a fxregs_state struct. 8386 */ 8387 if (!boot_cpu_has(X86_FEATURE_FPU) || !boot_cpu_has(X86_FEATURE_FXSR)) { 8388 printk(KERN_ERR "kvm: inadequate fpu\n"); 8389 r = -EOPNOTSUPP; 8390 goto out; 8391 } 8392 8393 r = -ENOMEM; 8394 x86_fpu_cache = kmem_cache_create("x86_fpu", sizeof(struct fpu), 8395 __alignof__(struct fpu), SLAB_ACCOUNT, 8396 NULL); 8397 if (!x86_fpu_cache) { 8398 printk(KERN_ERR "kvm: failed to allocate cache for x86 fpu\n"); 8399 goto out; 8400 } 8401 8402 x86_emulator_cache = kvm_alloc_emulator_cache(); 8403 if (!x86_emulator_cache) { 8404 pr_err("kvm: failed to allocate cache for x86 emulator\n"); 8405 goto out_free_x86_fpu_cache; 8406 } 8407 8408 user_return_msrs = alloc_percpu(struct kvm_user_return_msrs); 8409 if (!user_return_msrs) { 8410 printk(KERN_ERR "kvm: failed to allocate percpu kvm_user_return_msrs\n"); 8411 goto out_free_x86_emulator_cache; 8412 } 8413 kvm_nr_uret_msrs = 0; 8414 8415 r = kvm_mmu_module_init(); 8416 if (r) 8417 goto out_free_percpu; 8418 8419 kvm_timer_init(); 8420 8421 perf_register_guest_info_callbacks(&kvm_guest_cbs); 8422 8423 if (boot_cpu_has(X86_FEATURE_XSAVE)) { 8424 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK); 8425 supported_xcr0 = host_xcr0 & KVM_SUPPORTED_XCR0; 8426 } 8427 8428 if (pi_inject_timer == -1) 8429 pi_inject_timer = housekeeping_enabled(HK_FLAG_TIMER); 8430 #ifdef CONFIG_X86_64 8431 pvclock_gtod_register_notifier(&pvclock_gtod_notifier); 8432 8433 if (hypervisor_is_type(X86_HYPER_MS_HYPERV)) 8434 set_hv_tscchange_cb(kvm_hyperv_tsc_notifier); 8435 #endif 8436 8437 return 0; 8438 8439 out_free_percpu: 8440 free_percpu(user_return_msrs); 8441 out_free_x86_emulator_cache: 8442 kmem_cache_destroy(x86_emulator_cache); 8443 out_free_x86_fpu_cache: 8444 kmem_cache_destroy(x86_fpu_cache); 8445 out: 8446 return r; 8447 } 8448 8449 void kvm_arch_exit(void) 8450 { 8451 #ifdef CONFIG_X86_64 8452 if (hypervisor_is_type(X86_HYPER_MS_HYPERV)) 8453 clear_hv_tscchange_cb(); 8454 #endif 8455 kvm_lapic_exit(); 8456 perf_unregister_guest_info_callbacks(&kvm_guest_cbs); 8457 8458 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) 8459 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block, 8460 CPUFREQ_TRANSITION_NOTIFIER); 8461 cpuhp_remove_state_nocalls(CPUHP_AP_X86_KVM_CLK_ONLINE); 8462 #ifdef CONFIG_X86_64 8463 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier); 8464 irq_work_sync(&pvclock_irq_work); 8465 cancel_work_sync(&pvclock_gtod_work); 8466 #endif 8467 kvm_x86_ops.hardware_enable = NULL; 8468 kvm_mmu_module_exit(); 8469 free_percpu(user_return_msrs); 8470 kmem_cache_destroy(x86_emulator_cache); 8471 kmem_cache_destroy(x86_fpu_cache); 8472 #ifdef CONFIG_KVM_XEN 8473 static_key_deferred_flush(&kvm_xen_enabled); 8474 WARN_ON(static_branch_unlikely(&kvm_xen_enabled.key)); 8475 #endif 8476 } 8477 8478 static int __kvm_vcpu_halt(struct kvm_vcpu *vcpu, int state, int reason) 8479 { 8480 ++vcpu->stat.halt_exits; 8481 if (lapic_in_kernel(vcpu)) { 8482 vcpu->arch.mp_state = state; 8483 return 1; 8484 } else { 8485 vcpu->run->exit_reason = reason; 8486 return 0; 8487 } 8488 } 8489 8490 int kvm_vcpu_halt(struct kvm_vcpu *vcpu) 8491 { 8492 return __kvm_vcpu_halt(vcpu, KVM_MP_STATE_HALTED, KVM_EXIT_HLT); 8493 } 8494 EXPORT_SYMBOL_GPL(kvm_vcpu_halt); 8495 8496 int kvm_emulate_halt(struct kvm_vcpu *vcpu) 8497 { 8498 int ret = kvm_skip_emulated_instruction(vcpu); 8499 /* 8500 * TODO: we might be squashing a GUESTDBG_SINGLESTEP-triggered 8501 * KVM_EXIT_DEBUG here. 8502 */ 8503 return kvm_vcpu_halt(vcpu) && ret; 8504 } 8505 EXPORT_SYMBOL_GPL(kvm_emulate_halt); 8506 8507 int kvm_emulate_ap_reset_hold(struct kvm_vcpu *vcpu) 8508 { 8509 int ret = kvm_skip_emulated_instruction(vcpu); 8510 8511 return __kvm_vcpu_halt(vcpu, KVM_MP_STATE_AP_RESET_HOLD, KVM_EXIT_AP_RESET_HOLD) && ret; 8512 } 8513 EXPORT_SYMBOL_GPL(kvm_emulate_ap_reset_hold); 8514 8515 #ifdef CONFIG_X86_64 8516 static int kvm_pv_clock_pairing(struct kvm_vcpu *vcpu, gpa_t paddr, 8517 unsigned long clock_type) 8518 { 8519 struct kvm_clock_pairing clock_pairing; 8520 struct timespec64 ts; 8521 u64 cycle; 8522 int ret; 8523 8524 if (clock_type != KVM_CLOCK_PAIRING_WALLCLOCK) 8525 return -KVM_EOPNOTSUPP; 8526 8527 if (!kvm_get_walltime_and_clockread(&ts, &cycle)) 8528 return -KVM_EOPNOTSUPP; 8529 8530 clock_pairing.sec = ts.tv_sec; 8531 clock_pairing.nsec = ts.tv_nsec; 8532 clock_pairing.tsc = kvm_read_l1_tsc(vcpu, cycle); 8533 clock_pairing.flags = 0; 8534 memset(&clock_pairing.pad, 0, sizeof(clock_pairing.pad)); 8535 8536 ret = 0; 8537 if (kvm_write_guest(vcpu->kvm, paddr, &clock_pairing, 8538 sizeof(struct kvm_clock_pairing))) 8539 ret = -KVM_EFAULT; 8540 8541 return ret; 8542 } 8543 #endif 8544 8545 /* 8546 * kvm_pv_kick_cpu_op: Kick a vcpu. 8547 * 8548 * @apicid - apicid of vcpu to be kicked. 8549 */ 8550 static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid) 8551 { 8552 struct kvm_lapic_irq lapic_irq; 8553 8554 lapic_irq.shorthand = APIC_DEST_NOSHORT; 8555 lapic_irq.dest_mode = APIC_DEST_PHYSICAL; 8556 lapic_irq.level = 0; 8557 lapic_irq.dest_id = apicid; 8558 lapic_irq.msi_redir_hint = false; 8559 8560 lapic_irq.delivery_mode = APIC_DM_REMRD; 8561 kvm_irq_delivery_to_apic(kvm, NULL, &lapic_irq, NULL); 8562 } 8563 8564 bool kvm_apicv_activated(struct kvm *kvm) 8565 { 8566 return (READ_ONCE(kvm->arch.apicv_inhibit_reasons) == 0); 8567 } 8568 EXPORT_SYMBOL_GPL(kvm_apicv_activated); 8569 8570 static void kvm_apicv_init(struct kvm *kvm) 8571 { 8572 if (enable_apicv) 8573 clear_bit(APICV_INHIBIT_REASON_DISABLE, 8574 &kvm->arch.apicv_inhibit_reasons); 8575 else 8576 set_bit(APICV_INHIBIT_REASON_DISABLE, 8577 &kvm->arch.apicv_inhibit_reasons); 8578 } 8579 8580 static void kvm_sched_yield(struct kvm_vcpu *vcpu, unsigned long dest_id) 8581 { 8582 struct kvm_vcpu *target = NULL; 8583 struct kvm_apic_map *map; 8584 8585 vcpu->stat.directed_yield_attempted++; 8586 8587 if (single_task_running()) 8588 goto no_yield; 8589 8590 rcu_read_lock(); 8591 map = rcu_dereference(vcpu->kvm->arch.apic_map); 8592 8593 if (likely(map) && dest_id <= map->max_apic_id && map->phys_map[dest_id]) 8594 target = map->phys_map[dest_id]->vcpu; 8595 8596 rcu_read_unlock(); 8597 8598 if (!target || !READ_ONCE(target->ready)) 8599 goto no_yield; 8600 8601 /* Ignore requests to yield to self */ 8602 if (vcpu == target) 8603 goto no_yield; 8604 8605 if (kvm_vcpu_yield_to(target) <= 0) 8606 goto no_yield; 8607 8608 vcpu->stat.directed_yield_successful++; 8609 8610 no_yield: 8611 return; 8612 } 8613 8614 static int complete_hypercall_exit(struct kvm_vcpu *vcpu) 8615 { 8616 u64 ret = vcpu->run->hypercall.ret; 8617 8618 if (!is_64_bit_mode(vcpu)) 8619 ret = (u32)ret; 8620 kvm_rax_write(vcpu, ret); 8621 ++vcpu->stat.hypercalls; 8622 return kvm_skip_emulated_instruction(vcpu); 8623 } 8624 8625 int kvm_emulate_hypercall(struct kvm_vcpu *vcpu) 8626 { 8627 unsigned long nr, a0, a1, a2, a3, ret; 8628 int op_64_bit; 8629 8630 if (kvm_xen_hypercall_enabled(vcpu->kvm)) 8631 return kvm_xen_hypercall(vcpu); 8632 8633 if (kvm_hv_hypercall_enabled(vcpu)) 8634 return kvm_hv_hypercall(vcpu); 8635 8636 nr = kvm_rax_read(vcpu); 8637 a0 = kvm_rbx_read(vcpu); 8638 a1 = kvm_rcx_read(vcpu); 8639 a2 = kvm_rdx_read(vcpu); 8640 a3 = kvm_rsi_read(vcpu); 8641 8642 trace_kvm_hypercall(nr, a0, a1, a2, a3); 8643 8644 op_64_bit = is_64_bit_mode(vcpu); 8645 if (!op_64_bit) { 8646 nr &= 0xFFFFFFFF; 8647 a0 &= 0xFFFFFFFF; 8648 a1 &= 0xFFFFFFFF; 8649 a2 &= 0xFFFFFFFF; 8650 a3 &= 0xFFFFFFFF; 8651 } 8652 8653 if (static_call(kvm_x86_get_cpl)(vcpu) != 0) { 8654 ret = -KVM_EPERM; 8655 goto out; 8656 } 8657 8658 ret = -KVM_ENOSYS; 8659 8660 switch (nr) { 8661 case KVM_HC_VAPIC_POLL_IRQ: 8662 ret = 0; 8663 break; 8664 case KVM_HC_KICK_CPU: 8665 if (!guest_pv_has(vcpu, KVM_FEATURE_PV_UNHALT)) 8666 break; 8667 8668 kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1); 8669 kvm_sched_yield(vcpu, a1); 8670 ret = 0; 8671 break; 8672 #ifdef CONFIG_X86_64 8673 case KVM_HC_CLOCK_PAIRING: 8674 ret = kvm_pv_clock_pairing(vcpu, a0, a1); 8675 break; 8676 #endif 8677 case KVM_HC_SEND_IPI: 8678 if (!guest_pv_has(vcpu, KVM_FEATURE_PV_SEND_IPI)) 8679 break; 8680 8681 ret = kvm_pv_send_ipi(vcpu->kvm, a0, a1, a2, a3, op_64_bit); 8682 break; 8683 case KVM_HC_SCHED_YIELD: 8684 if (!guest_pv_has(vcpu, KVM_FEATURE_PV_SCHED_YIELD)) 8685 break; 8686 8687 kvm_sched_yield(vcpu, a0); 8688 ret = 0; 8689 break; 8690 case KVM_HC_MAP_GPA_RANGE: { 8691 u64 gpa = a0, npages = a1, attrs = a2; 8692 8693 ret = -KVM_ENOSYS; 8694 if (!(vcpu->kvm->arch.hypercall_exit_enabled & (1 << KVM_HC_MAP_GPA_RANGE))) 8695 break; 8696 8697 if (!PAGE_ALIGNED(gpa) || !npages || 8698 gpa_to_gfn(gpa) + npages <= gpa_to_gfn(gpa)) { 8699 ret = -KVM_EINVAL; 8700 break; 8701 } 8702 8703 vcpu->run->exit_reason = KVM_EXIT_HYPERCALL; 8704 vcpu->run->hypercall.nr = KVM_HC_MAP_GPA_RANGE; 8705 vcpu->run->hypercall.args[0] = gpa; 8706 vcpu->run->hypercall.args[1] = npages; 8707 vcpu->run->hypercall.args[2] = attrs; 8708 vcpu->run->hypercall.longmode = op_64_bit; 8709 vcpu->arch.complete_userspace_io = complete_hypercall_exit; 8710 return 0; 8711 } 8712 default: 8713 ret = -KVM_ENOSYS; 8714 break; 8715 } 8716 out: 8717 if (!op_64_bit) 8718 ret = (u32)ret; 8719 kvm_rax_write(vcpu, ret); 8720 8721 ++vcpu->stat.hypercalls; 8722 return kvm_skip_emulated_instruction(vcpu); 8723 } 8724 EXPORT_SYMBOL_GPL(kvm_emulate_hypercall); 8725 8726 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt) 8727 { 8728 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 8729 char instruction[3]; 8730 unsigned long rip = kvm_rip_read(vcpu); 8731 8732 static_call(kvm_x86_patch_hypercall)(vcpu, instruction); 8733 8734 return emulator_write_emulated(ctxt, rip, instruction, 3, 8735 &ctxt->exception); 8736 } 8737 8738 static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu) 8739 { 8740 return vcpu->run->request_interrupt_window && 8741 likely(!pic_in_kernel(vcpu->kvm)); 8742 } 8743 8744 static void post_kvm_run_save(struct kvm_vcpu *vcpu) 8745 { 8746 struct kvm_run *kvm_run = vcpu->run; 8747 8748 /* 8749 * if_flag is obsolete and useless, so do not bother 8750 * setting it for SEV-ES guests. Userspace can just 8751 * use kvm_run->ready_for_interrupt_injection. 8752 */ 8753 kvm_run->if_flag = !vcpu->arch.guest_state_protected 8754 && (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0; 8755 8756 kvm_run->cr8 = kvm_get_cr8(vcpu); 8757 kvm_run->apic_base = kvm_get_apic_base(vcpu); 8758 kvm_run->ready_for_interrupt_injection = 8759 pic_in_kernel(vcpu->kvm) || 8760 kvm_vcpu_ready_for_interrupt_injection(vcpu); 8761 8762 if (is_smm(vcpu)) 8763 kvm_run->flags |= KVM_RUN_X86_SMM; 8764 } 8765 8766 static void update_cr8_intercept(struct kvm_vcpu *vcpu) 8767 { 8768 int max_irr, tpr; 8769 8770 if (!kvm_x86_ops.update_cr8_intercept) 8771 return; 8772 8773 if (!lapic_in_kernel(vcpu)) 8774 return; 8775 8776 if (vcpu->arch.apicv_active) 8777 return; 8778 8779 if (!vcpu->arch.apic->vapic_addr) 8780 max_irr = kvm_lapic_find_highest_irr(vcpu); 8781 else 8782 max_irr = -1; 8783 8784 if (max_irr != -1) 8785 max_irr >>= 4; 8786 8787 tpr = kvm_lapic_get_cr8(vcpu); 8788 8789 static_call(kvm_x86_update_cr8_intercept)(vcpu, tpr, max_irr); 8790 } 8791 8792 8793 int kvm_check_nested_events(struct kvm_vcpu *vcpu) 8794 { 8795 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) { 8796 kvm_x86_ops.nested_ops->triple_fault(vcpu); 8797 return 1; 8798 } 8799 8800 return kvm_x86_ops.nested_ops->check_events(vcpu); 8801 } 8802 8803 static void kvm_inject_exception(struct kvm_vcpu *vcpu) 8804 { 8805 if (vcpu->arch.exception.error_code && !is_protmode(vcpu)) 8806 vcpu->arch.exception.error_code = false; 8807 static_call(kvm_x86_queue_exception)(vcpu); 8808 } 8809 8810 static int inject_pending_event(struct kvm_vcpu *vcpu, bool *req_immediate_exit) 8811 { 8812 int r; 8813 bool can_inject = true; 8814 8815 /* try to reinject previous events if any */ 8816 8817 if (vcpu->arch.exception.injected) { 8818 kvm_inject_exception(vcpu); 8819 can_inject = false; 8820 } 8821 /* 8822 * Do not inject an NMI or interrupt if there is a pending 8823 * exception. Exceptions and interrupts are recognized at 8824 * instruction boundaries, i.e. the start of an instruction. 8825 * Trap-like exceptions, e.g. #DB, have higher priority than 8826 * NMIs and interrupts, i.e. traps are recognized before an 8827 * NMI/interrupt that's pending on the same instruction. 8828 * Fault-like exceptions, e.g. #GP and #PF, are the lowest 8829 * priority, but are only generated (pended) during instruction 8830 * execution, i.e. a pending fault-like exception means the 8831 * fault occurred on the *previous* instruction and must be 8832 * serviced prior to recognizing any new events in order to 8833 * fully complete the previous instruction. 8834 */ 8835 else if (!vcpu->arch.exception.pending) { 8836 if (vcpu->arch.nmi_injected) { 8837 static_call(kvm_x86_set_nmi)(vcpu); 8838 can_inject = false; 8839 } else if (vcpu->arch.interrupt.injected) { 8840 static_call(kvm_x86_set_irq)(vcpu); 8841 can_inject = false; 8842 } 8843 } 8844 8845 WARN_ON_ONCE(vcpu->arch.exception.injected && 8846 vcpu->arch.exception.pending); 8847 8848 /* 8849 * Call check_nested_events() even if we reinjected a previous event 8850 * in order for caller to determine if it should require immediate-exit 8851 * from L2 to L1 due to pending L1 events which require exit 8852 * from L2 to L1. 8853 */ 8854 if (is_guest_mode(vcpu)) { 8855 r = kvm_check_nested_events(vcpu); 8856 if (r < 0) 8857 goto out; 8858 } 8859 8860 /* try to inject new event if pending */ 8861 if (vcpu->arch.exception.pending) { 8862 trace_kvm_inj_exception(vcpu->arch.exception.nr, 8863 vcpu->arch.exception.has_error_code, 8864 vcpu->arch.exception.error_code); 8865 8866 vcpu->arch.exception.pending = false; 8867 vcpu->arch.exception.injected = true; 8868 8869 if (exception_type(vcpu->arch.exception.nr) == EXCPT_FAULT) 8870 __kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) | 8871 X86_EFLAGS_RF); 8872 8873 if (vcpu->arch.exception.nr == DB_VECTOR) { 8874 kvm_deliver_exception_payload(vcpu); 8875 if (vcpu->arch.dr7 & DR7_GD) { 8876 vcpu->arch.dr7 &= ~DR7_GD; 8877 kvm_update_dr7(vcpu); 8878 } 8879 } 8880 8881 kvm_inject_exception(vcpu); 8882 can_inject = false; 8883 } 8884 8885 /* 8886 * Finally, inject interrupt events. If an event cannot be injected 8887 * due to architectural conditions (e.g. IF=0) a window-open exit 8888 * will re-request KVM_REQ_EVENT. Sometimes however an event is pending 8889 * and can architecturally be injected, but we cannot do it right now: 8890 * an interrupt could have arrived just now and we have to inject it 8891 * as a vmexit, or there could already an event in the queue, which is 8892 * indicated by can_inject. In that case we request an immediate exit 8893 * in order to make progress and get back here for another iteration. 8894 * The kvm_x86_ops hooks communicate this by returning -EBUSY. 8895 */ 8896 if (vcpu->arch.smi_pending) { 8897 r = can_inject ? static_call(kvm_x86_smi_allowed)(vcpu, true) : -EBUSY; 8898 if (r < 0) 8899 goto out; 8900 if (r) { 8901 vcpu->arch.smi_pending = false; 8902 ++vcpu->arch.smi_count; 8903 enter_smm(vcpu); 8904 can_inject = false; 8905 } else 8906 static_call(kvm_x86_enable_smi_window)(vcpu); 8907 } 8908 8909 if (vcpu->arch.nmi_pending) { 8910 r = can_inject ? static_call(kvm_x86_nmi_allowed)(vcpu, true) : -EBUSY; 8911 if (r < 0) 8912 goto out; 8913 if (r) { 8914 --vcpu->arch.nmi_pending; 8915 vcpu->arch.nmi_injected = true; 8916 static_call(kvm_x86_set_nmi)(vcpu); 8917 can_inject = false; 8918 WARN_ON(static_call(kvm_x86_nmi_allowed)(vcpu, true) < 0); 8919 } 8920 if (vcpu->arch.nmi_pending) 8921 static_call(kvm_x86_enable_nmi_window)(vcpu); 8922 } 8923 8924 if (kvm_cpu_has_injectable_intr(vcpu)) { 8925 r = can_inject ? static_call(kvm_x86_interrupt_allowed)(vcpu, true) : -EBUSY; 8926 if (r < 0) 8927 goto out; 8928 if (r) { 8929 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu), false); 8930 static_call(kvm_x86_set_irq)(vcpu); 8931 WARN_ON(static_call(kvm_x86_interrupt_allowed)(vcpu, true) < 0); 8932 } 8933 if (kvm_cpu_has_injectable_intr(vcpu)) 8934 static_call(kvm_x86_enable_irq_window)(vcpu); 8935 } 8936 8937 if (is_guest_mode(vcpu) && 8938 kvm_x86_ops.nested_ops->hv_timer_pending && 8939 kvm_x86_ops.nested_ops->hv_timer_pending(vcpu)) 8940 *req_immediate_exit = true; 8941 8942 WARN_ON(vcpu->arch.exception.pending); 8943 return 0; 8944 8945 out: 8946 if (r == -EBUSY) { 8947 *req_immediate_exit = true; 8948 r = 0; 8949 } 8950 return r; 8951 } 8952 8953 static void process_nmi(struct kvm_vcpu *vcpu) 8954 { 8955 unsigned limit = 2; 8956 8957 /* 8958 * x86 is limited to one NMI running, and one NMI pending after it. 8959 * If an NMI is already in progress, limit further NMIs to just one. 8960 * Otherwise, allow two (and we'll inject the first one immediately). 8961 */ 8962 if (static_call(kvm_x86_get_nmi_mask)(vcpu) || vcpu->arch.nmi_injected) 8963 limit = 1; 8964 8965 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0); 8966 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit); 8967 kvm_make_request(KVM_REQ_EVENT, vcpu); 8968 } 8969 8970 static u32 enter_smm_get_segment_flags(struct kvm_segment *seg) 8971 { 8972 u32 flags = 0; 8973 flags |= seg->g << 23; 8974 flags |= seg->db << 22; 8975 flags |= seg->l << 21; 8976 flags |= seg->avl << 20; 8977 flags |= seg->present << 15; 8978 flags |= seg->dpl << 13; 8979 flags |= seg->s << 12; 8980 flags |= seg->type << 8; 8981 return flags; 8982 } 8983 8984 static void enter_smm_save_seg_32(struct kvm_vcpu *vcpu, char *buf, int n) 8985 { 8986 struct kvm_segment seg; 8987 int offset; 8988 8989 kvm_get_segment(vcpu, &seg, n); 8990 put_smstate(u32, buf, 0x7fa8 + n * 4, seg.selector); 8991 8992 if (n < 3) 8993 offset = 0x7f84 + n * 12; 8994 else 8995 offset = 0x7f2c + (n - 3) * 12; 8996 8997 put_smstate(u32, buf, offset + 8, seg.base); 8998 put_smstate(u32, buf, offset + 4, seg.limit); 8999 put_smstate(u32, buf, offset, enter_smm_get_segment_flags(&seg)); 9000 } 9001 9002 #ifdef CONFIG_X86_64 9003 static void enter_smm_save_seg_64(struct kvm_vcpu *vcpu, char *buf, int n) 9004 { 9005 struct kvm_segment seg; 9006 int offset; 9007 u16 flags; 9008 9009 kvm_get_segment(vcpu, &seg, n); 9010 offset = 0x7e00 + n * 16; 9011 9012 flags = enter_smm_get_segment_flags(&seg) >> 8; 9013 put_smstate(u16, buf, offset, seg.selector); 9014 put_smstate(u16, buf, offset + 2, flags); 9015 put_smstate(u32, buf, offset + 4, seg.limit); 9016 put_smstate(u64, buf, offset + 8, seg.base); 9017 } 9018 #endif 9019 9020 static void enter_smm_save_state_32(struct kvm_vcpu *vcpu, char *buf) 9021 { 9022 struct desc_ptr dt; 9023 struct kvm_segment seg; 9024 unsigned long val; 9025 int i; 9026 9027 put_smstate(u32, buf, 0x7ffc, kvm_read_cr0(vcpu)); 9028 put_smstate(u32, buf, 0x7ff8, kvm_read_cr3(vcpu)); 9029 put_smstate(u32, buf, 0x7ff4, kvm_get_rflags(vcpu)); 9030 put_smstate(u32, buf, 0x7ff0, kvm_rip_read(vcpu)); 9031 9032 for (i = 0; i < 8; i++) 9033 put_smstate(u32, buf, 0x7fd0 + i * 4, kvm_register_read_raw(vcpu, i)); 9034 9035 kvm_get_dr(vcpu, 6, &val); 9036 put_smstate(u32, buf, 0x7fcc, (u32)val); 9037 kvm_get_dr(vcpu, 7, &val); 9038 put_smstate(u32, buf, 0x7fc8, (u32)val); 9039 9040 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR); 9041 put_smstate(u32, buf, 0x7fc4, seg.selector); 9042 put_smstate(u32, buf, 0x7f64, seg.base); 9043 put_smstate(u32, buf, 0x7f60, seg.limit); 9044 put_smstate(u32, buf, 0x7f5c, enter_smm_get_segment_flags(&seg)); 9045 9046 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR); 9047 put_smstate(u32, buf, 0x7fc0, seg.selector); 9048 put_smstate(u32, buf, 0x7f80, seg.base); 9049 put_smstate(u32, buf, 0x7f7c, seg.limit); 9050 put_smstate(u32, buf, 0x7f78, enter_smm_get_segment_flags(&seg)); 9051 9052 static_call(kvm_x86_get_gdt)(vcpu, &dt); 9053 put_smstate(u32, buf, 0x7f74, dt.address); 9054 put_smstate(u32, buf, 0x7f70, dt.size); 9055 9056 static_call(kvm_x86_get_idt)(vcpu, &dt); 9057 put_smstate(u32, buf, 0x7f58, dt.address); 9058 put_smstate(u32, buf, 0x7f54, dt.size); 9059 9060 for (i = 0; i < 6; i++) 9061 enter_smm_save_seg_32(vcpu, buf, i); 9062 9063 put_smstate(u32, buf, 0x7f14, kvm_read_cr4(vcpu)); 9064 9065 /* revision id */ 9066 put_smstate(u32, buf, 0x7efc, 0x00020000); 9067 put_smstate(u32, buf, 0x7ef8, vcpu->arch.smbase); 9068 } 9069 9070 #ifdef CONFIG_X86_64 9071 static void enter_smm_save_state_64(struct kvm_vcpu *vcpu, char *buf) 9072 { 9073 struct desc_ptr dt; 9074 struct kvm_segment seg; 9075 unsigned long val; 9076 int i; 9077 9078 for (i = 0; i < 16; i++) 9079 put_smstate(u64, buf, 0x7ff8 - i * 8, kvm_register_read_raw(vcpu, i)); 9080 9081 put_smstate(u64, buf, 0x7f78, kvm_rip_read(vcpu)); 9082 put_smstate(u32, buf, 0x7f70, kvm_get_rflags(vcpu)); 9083 9084 kvm_get_dr(vcpu, 6, &val); 9085 put_smstate(u64, buf, 0x7f68, val); 9086 kvm_get_dr(vcpu, 7, &val); 9087 put_smstate(u64, buf, 0x7f60, val); 9088 9089 put_smstate(u64, buf, 0x7f58, kvm_read_cr0(vcpu)); 9090 put_smstate(u64, buf, 0x7f50, kvm_read_cr3(vcpu)); 9091 put_smstate(u64, buf, 0x7f48, kvm_read_cr4(vcpu)); 9092 9093 put_smstate(u32, buf, 0x7f00, vcpu->arch.smbase); 9094 9095 /* revision id */ 9096 put_smstate(u32, buf, 0x7efc, 0x00020064); 9097 9098 put_smstate(u64, buf, 0x7ed0, vcpu->arch.efer); 9099 9100 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR); 9101 put_smstate(u16, buf, 0x7e90, seg.selector); 9102 put_smstate(u16, buf, 0x7e92, enter_smm_get_segment_flags(&seg) >> 8); 9103 put_smstate(u32, buf, 0x7e94, seg.limit); 9104 put_smstate(u64, buf, 0x7e98, seg.base); 9105 9106 static_call(kvm_x86_get_idt)(vcpu, &dt); 9107 put_smstate(u32, buf, 0x7e84, dt.size); 9108 put_smstate(u64, buf, 0x7e88, dt.address); 9109 9110 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR); 9111 put_smstate(u16, buf, 0x7e70, seg.selector); 9112 put_smstate(u16, buf, 0x7e72, enter_smm_get_segment_flags(&seg) >> 8); 9113 put_smstate(u32, buf, 0x7e74, seg.limit); 9114 put_smstate(u64, buf, 0x7e78, seg.base); 9115 9116 static_call(kvm_x86_get_gdt)(vcpu, &dt); 9117 put_smstate(u32, buf, 0x7e64, dt.size); 9118 put_smstate(u64, buf, 0x7e68, dt.address); 9119 9120 for (i = 0; i < 6; i++) 9121 enter_smm_save_seg_64(vcpu, buf, i); 9122 } 9123 #endif 9124 9125 static void enter_smm(struct kvm_vcpu *vcpu) 9126 { 9127 struct kvm_segment cs, ds; 9128 struct desc_ptr dt; 9129 unsigned long cr0; 9130 char buf[512]; 9131 9132 memset(buf, 0, 512); 9133 #ifdef CONFIG_X86_64 9134 if (guest_cpuid_has(vcpu, X86_FEATURE_LM)) 9135 enter_smm_save_state_64(vcpu, buf); 9136 else 9137 #endif 9138 enter_smm_save_state_32(vcpu, buf); 9139 9140 /* 9141 * Give enter_smm() a chance to make ISA-specific changes to the vCPU 9142 * state (e.g. leave guest mode) after we've saved the state into the 9143 * SMM state-save area. 9144 */ 9145 static_call(kvm_x86_enter_smm)(vcpu, buf); 9146 9147 kvm_smm_changed(vcpu, true); 9148 kvm_vcpu_write_guest(vcpu, vcpu->arch.smbase + 0xfe00, buf, sizeof(buf)); 9149 9150 if (static_call(kvm_x86_get_nmi_mask)(vcpu)) 9151 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK; 9152 else 9153 static_call(kvm_x86_set_nmi_mask)(vcpu, true); 9154 9155 kvm_set_rflags(vcpu, X86_EFLAGS_FIXED); 9156 kvm_rip_write(vcpu, 0x8000); 9157 9158 cr0 = vcpu->arch.cr0 & ~(X86_CR0_PE | X86_CR0_EM | X86_CR0_TS | X86_CR0_PG); 9159 static_call(kvm_x86_set_cr0)(vcpu, cr0); 9160 vcpu->arch.cr0 = cr0; 9161 9162 static_call(kvm_x86_set_cr4)(vcpu, 0); 9163 9164 /* Undocumented: IDT limit is set to zero on entry to SMM. */ 9165 dt.address = dt.size = 0; 9166 static_call(kvm_x86_set_idt)(vcpu, &dt); 9167 9168 kvm_set_dr(vcpu, 7, DR7_FIXED_1); 9169 9170 cs.selector = (vcpu->arch.smbase >> 4) & 0xffff; 9171 cs.base = vcpu->arch.smbase; 9172 9173 ds.selector = 0; 9174 ds.base = 0; 9175 9176 cs.limit = ds.limit = 0xffffffff; 9177 cs.type = ds.type = 0x3; 9178 cs.dpl = ds.dpl = 0; 9179 cs.db = ds.db = 0; 9180 cs.s = ds.s = 1; 9181 cs.l = ds.l = 0; 9182 cs.g = ds.g = 1; 9183 cs.avl = ds.avl = 0; 9184 cs.present = ds.present = 1; 9185 cs.unusable = ds.unusable = 0; 9186 cs.padding = ds.padding = 0; 9187 9188 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS); 9189 kvm_set_segment(vcpu, &ds, VCPU_SREG_DS); 9190 kvm_set_segment(vcpu, &ds, VCPU_SREG_ES); 9191 kvm_set_segment(vcpu, &ds, VCPU_SREG_FS); 9192 kvm_set_segment(vcpu, &ds, VCPU_SREG_GS); 9193 kvm_set_segment(vcpu, &ds, VCPU_SREG_SS); 9194 9195 #ifdef CONFIG_X86_64 9196 if (guest_cpuid_has(vcpu, X86_FEATURE_LM)) 9197 static_call(kvm_x86_set_efer)(vcpu, 0); 9198 #endif 9199 9200 kvm_update_cpuid_runtime(vcpu); 9201 kvm_mmu_reset_context(vcpu); 9202 } 9203 9204 static void process_smi(struct kvm_vcpu *vcpu) 9205 { 9206 vcpu->arch.smi_pending = true; 9207 kvm_make_request(KVM_REQ_EVENT, vcpu); 9208 } 9209 9210 void kvm_make_scan_ioapic_request_mask(struct kvm *kvm, 9211 unsigned long *vcpu_bitmap) 9212 { 9213 cpumask_var_t cpus; 9214 9215 zalloc_cpumask_var(&cpus, GFP_ATOMIC); 9216 9217 kvm_make_vcpus_request_mask(kvm, KVM_REQ_SCAN_IOAPIC, 9218 NULL, vcpu_bitmap, cpus); 9219 9220 free_cpumask_var(cpus); 9221 } 9222 9223 void kvm_make_scan_ioapic_request(struct kvm *kvm) 9224 { 9225 kvm_make_all_cpus_request(kvm, KVM_REQ_SCAN_IOAPIC); 9226 } 9227 9228 void kvm_vcpu_update_apicv(struct kvm_vcpu *vcpu) 9229 { 9230 if (!lapic_in_kernel(vcpu)) 9231 return; 9232 9233 vcpu->arch.apicv_active = kvm_apicv_activated(vcpu->kvm); 9234 kvm_apic_update_apicv(vcpu); 9235 static_call(kvm_x86_refresh_apicv_exec_ctrl)(vcpu); 9236 9237 /* 9238 * When APICv gets disabled, we may still have injected interrupts 9239 * pending. At the same time, KVM_REQ_EVENT may not be set as APICv was 9240 * still active when the interrupt got accepted. Make sure 9241 * inject_pending_event() is called to check for that. 9242 */ 9243 if (!vcpu->arch.apicv_active) 9244 kvm_make_request(KVM_REQ_EVENT, vcpu); 9245 } 9246 EXPORT_SYMBOL_GPL(kvm_vcpu_update_apicv); 9247 9248 /* 9249 * NOTE: Do not hold any lock prior to calling this. 9250 * 9251 * In particular, kvm_request_apicv_update() expects kvm->srcu not to be 9252 * locked, because it calls __x86_set_memory_region() which does 9253 * synchronize_srcu(&kvm->srcu). 9254 */ 9255 void kvm_request_apicv_update(struct kvm *kvm, bool activate, ulong bit) 9256 { 9257 struct kvm_vcpu *except; 9258 unsigned long old, new, expected; 9259 9260 if (!kvm_x86_ops.check_apicv_inhibit_reasons || 9261 !static_call(kvm_x86_check_apicv_inhibit_reasons)(bit)) 9262 return; 9263 9264 old = READ_ONCE(kvm->arch.apicv_inhibit_reasons); 9265 do { 9266 expected = new = old; 9267 if (activate) 9268 __clear_bit(bit, &new); 9269 else 9270 __set_bit(bit, &new); 9271 if (new == old) 9272 break; 9273 old = cmpxchg(&kvm->arch.apicv_inhibit_reasons, expected, new); 9274 } while (old != expected); 9275 9276 if (!!old == !!new) 9277 return; 9278 9279 trace_kvm_apicv_update_request(activate, bit); 9280 if (kvm_x86_ops.pre_update_apicv_exec_ctrl) 9281 static_call(kvm_x86_pre_update_apicv_exec_ctrl)(kvm, activate); 9282 9283 /* 9284 * Sending request to update APICV for all other vcpus, 9285 * while update the calling vcpu immediately instead of 9286 * waiting for another #VMEXIT to handle the request. 9287 */ 9288 except = kvm_get_running_vcpu(); 9289 kvm_make_all_cpus_request_except(kvm, KVM_REQ_APICV_UPDATE, 9290 except); 9291 if (except) 9292 kvm_vcpu_update_apicv(except); 9293 } 9294 EXPORT_SYMBOL_GPL(kvm_request_apicv_update); 9295 9296 static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu) 9297 { 9298 if (!kvm_apic_present(vcpu)) 9299 return; 9300 9301 bitmap_zero(vcpu->arch.ioapic_handled_vectors, 256); 9302 9303 if (irqchip_split(vcpu->kvm)) 9304 kvm_scan_ioapic_routes(vcpu, vcpu->arch.ioapic_handled_vectors); 9305 else { 9306 if (vcpu->arch.apicv_active) 9307 static_call(kvm_x86_sync_pir_to_irr)(vcpu); 9308 if (ioapic_in_kernel(vcpu->kvm)) 9309 kvm_ioapic_scan_entry(vcpu, vcpu->arch.ioapic_handled_vectors); 9310 } 9311 9312 if (is_guest_mode(vcpu)) 9313 vcpu->arch.load_eoi_exitmap_pending = true; 9314 else 9315 kvm_make_request(KVM_REQ_LOAD_EOI_EXITMAP, vcpu); 9316 } 9317 9318 static void vcpu_load_eoi_exitmap(struct kvm_vcpu *vcpu) 9319 { 9320 u64 eoi_exit_bitmap[4]; 9321 9322 if (!kvm_apic_hw_enabled(vcpu->arch.apic)) 9323 return; 9324 9325 if (to_hv_vcpu(vcpu)) 9326 bitmap_or((ulong *)eoi_exit_bitmap, 9327 vcpu->arch.ioapic_handled_vectors, 9328 to_hv_synic(vcpu)->vec_bitmap, 256); 9329 9330 static_call(kvm_x86_load_eoi_exitmap)(vcpu, eoi_exit_bitmap); 9331 } 9332 9333 void kvm_arch_mmu_notifier_invalidate_range(struct kvm *kvm, 9334 unsigned long start, unsigned long end) 9335 { 9336 unsigned long apic_address; 9337 9338 /* 9339 * The physical address of apic access page is stored in the VMCS. 9340 * Update it when it becomes invalid. 9341 */ 9342 apic_address = gfn_to_hva(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT); 9343 if (start <= apic_address && apic_address < end) 9344 kvm_make_all_cpus_request(kvm, KVM_REQ_APIC_PAGE_RELOAD); 9345 } 9346 9347 void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu) 9348 { 9349 if (!lapic_in_kernel(vcpu)) 9350 return; 9351 9352 if (!kvm_x86_ops.set_apic_access_page_addr) 9353 return; 9354 9355 static_call(kvm_x86_set_apic_access_page_addr)(vcpu); 9356 } 9357 9358 void __kvm_request_immediate_exit(struct kvm_vcpu *vcpu) 9359 { 9360 smp_send_reschedule(vcpu->cpu); 9361 } 9362 EXPORT_SYMBOL_GPL(__kvm_request_immediate_exit); 9363 9364 /* 9365 * Returns 1 to let vcpu_run() continue the guest execution loop without 9366 * exiting to the userspace. Otherwise, the value will be returned to the 9367 * userspace. 9368 */ 9369 static int vcpu_enter_guest(struct kvm_vcpu *vcpu) 9370 { 9371 int r; 9372 bool req_int_win = 9373 dm_request_for_irq_injection(vcpu) && 9374 kvm_cpu_accept_dm_intr(vcpu); 9375 fastpath_t exit_fastpath; 9376 9377 bool req_immediate_exit = false; 9378 9379 /* Forbid vmenter if vcpu dirty ring is soft-full */ 9380 if (unlikely(vcpu->kvm->dirty_ring_size && 9381 kvm_dirty_ring_soft_full(&vcpu->dirty_ring))) { 9382 vcpu->run->exit_reason = KVM_EXIT_DIRTY_RING_FULL; 9383 trace_kvm_dirty_ring_exit(vcpu); 9384 r = 0; 9385 goto out; 9386 } 9387 9388 if (kvm_request_pending(vcpu)) { 9389 if (kvm_check_request(KVM_REQ_GET_NESTED_STATE_PAGES, vcpu)) { 9390 if (unlikely(!kvm_x86_ops.nested_ops->get_nested_state_pages(vcpu))) { 9391 r = 0; 9392 goto out; 9393 } 9394 } 9395 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu)) 9396 kvm_mmu_unload(vcpu); 9397 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu)) 9398 __kvm_migrate_timers(vcpu); 9399 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu)) 9400 kvm_gen_update_masterclock(vcpu->kvm); 9401 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu)) 9402 kvm_gen_kvmclock_update(vcpu); 9403 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) { 9404 r = kvm_guest_time_update(vcpu); 9405 if (unlikely(r)) 9406 goto out; 9407 } 9408 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu)) 9409 kvm_mmu_sync_roots(vcpu); 9410 if (kvm_check_request(KVM_REQ_LOAD_MMU_PGD, vcpu)) 9411 kvm_mmu_load_pgd(vcpu); 9412 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu)) { 9413 kvm_vcpu_flush_tlb_all(vcpu); 9414 9415 /* Flushing all ASIDs flushes the current ASID... */ 9416 kvm_clear_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu); 9417 } 9418 if (kvm_check_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu)) 9419 kvm_vcpu_flush_tlb_current(vcpu); 9420 if (kvm_check_request(KVM_REQ_TLB_FLUSH_GUEST, vcpu)) 9421 kvm_vcpu_flush_tlb_guest(vcpu); 9422 9423 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) { 9424 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS; 9425 r = 0; 9426 goto out; 9427 } 9428 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) { 9429 if (is_guest_mode(vcpu)) { 9430 kvm_x86_ops.nested_ops->triple_fault(vcpu); 9431 } else { 9432 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN; 9433 vcpu->mmio_needed = 0; 9434 r = 0; 9435 goto out; 9436 } 9437 } 9438 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) { 9439 /* Page is swapped out. Do synthetic halt */ 9440 vcpu->arch.apf.halted = true; 9441 r = 1; 9442 goto out; 9443 } 9444 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu)) 9445 record_steal_time(vcpu); 9446 if (kvm_check_request(KVM_REQ_SMI, vcpu)) 9447 process_smi(vcpu); 9448 if (kvm_check_request(KVM_REQ_NMI, vcpu)) 9449 process_nmi(vcpu); 9450 if (kvm_check_request(KVM_REQ_PMU, vcpu)) 9451 kvm_pmu_handle_event(vcpu); 9452 if (kvm_check_request(KVM_REQ_PMI, vcpu)) 9453 kvm_pmu_deliver_pmi(vcpu); 9454 if (kvm_check_request(KVM_REQ_IOAPIC_EOI_EXIT, vcpu)) { 9455 BUG_ON(vcpu->arch.pending_ioapic_eoi > 255); 9456 if (test_bit(vcpu->arch.pending_ioapic_eoi, 9457 vcpu->arch.ioapic_handled_vectors)) { 9458 vcpu->run->exit_reason = KVM_EXIT_IOAPIC_EOI; 9459 vcpu->run->eoi.vector = 9460 vcpu->arch.pending_ioapic_eoi; 9461 r = 0; 9462 goto out; 9463 } 9464 } 9465 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu)) 9466 vcpu_scan_ioapic(vcpu); 9467 if (kvm_check_request(KVM_REQ_LOAD_EOI_EXITMAP, vcpu)) 9468 vcpu_load_eoi_exitmap(vcpu); 9469 if (kvm_check_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu)) 9470 kvm_vcpu_reload_apic_access_page(vcpu); 9471 if (kvm_check_request(KVM_REQ_HV_CRASH, vcpu)) { 9472 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT; 9473 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_CRASH; 9474 r = 0; 9475 goto out; 9476 } 9477 if (kvm_check_request(KVM_REQ_HV_RESET, vcpu)) { 9478 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT; 9479 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_RESET; 9480 r = 0; 9481 goto out; 9482 } 9483 if (kvm_check_request(KVM_REQ_HV_EXIT, vcpu)) { 9484 struct kvm_vcpu_hv *hv_vcpu = to_hv_vcpu(vcpu); 9485 9486 vcpu->run->exit_reason = KVM_EXIT_HYPERV; 9487 vcpu->run->hyperv = hv_vcpu->exit; 9488 r = 0; 9489 goto out; 9490 } 9491 9492 /* 9493 * KVM_REQ_HV_STIMER has to be processed after 9494 * KVM_REQ_CLOCK_UPDATE, because Hyper-V SynIC timers 9495 * depend on the guest clock being up-to-date 9496 */ 9497 if (kvm_check_request(KVM_REQ_HV_STIMER, vcpu)) 9498 kvm_hv_process_stimers(vcpu); 9499 if (kvm_check_request(KVM_REQ_APICV_UPDATE, vcpu)) 9500 kvm_vcpu_update_apicv(vcpu); 9501 if (kvm_check_request(KVM_REQ_APF_READY, vcpu)) 9502 kvm_check_async_pf_completion(vcpu); 9503 if (kvm_check_request(KVM_REQ_MSR_FILTER_CHANGED, vcpu)) 9504 static_call(kvm_x86_msr_filter_changed)(vcpu); 9505 9506 if (kvm_check_request(KVM_REQ_UPDATE_CPU_DIRTY_LOGGING, vcpu)) 9507 static_call(kvm_x86_update_cpu_dirty_logging)(vcpu); 9508 } 9509 9510 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win || 9511 kvm_xen_has_interrupt(vcpu)) { 9512 ++vcpu->stat.req_event; 9513 r = kvm_apic_accept_events(vcpu); 9514 if (r < 0) { 9515 r = 0; 9516 goto out; 9517 } 9518 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) { 9519 r = 1; 9520 goto out; 9521 } 9522 9523 r = inject_pending_event(vcpu, &req_immediate_exit); 9524 if (r < 0) { 9525 r = 0; 9526 goto out; 9527 } 9528 if (req_int_win) 9529 static_call(kvm_x86_enable_irq_window)(vcpu); 9530 9531 if (kvm_lapic_enabled(vcpu)) { 9532 update_cr8_intercept(vcpu); 9533 kvm_lapic_sync_to_vapic(vcpu); 9534 } 9535 } 9536 9537 r = kvm_mmu_reload(vcpu); 9538 if (unlikely(r)) { 9539 goto cancel_injection; 9540 } 9541 9542 preempt_disable(); 9543 9544 static_call(kvm_x86_prepare_guest_switch)(vcpu); 9545 9546 /* 9547 * Disable IRQs before setting IN_GUEST_MODE. Posted interrupt 9548 * IPI are then delayed after guest entry, which ensures that they 9549 * result in virtual interrupt delivery. 9550 */ 9551 local_irq_disable(); 9552 vcpu->mode = IN_GUEST_MODE; 9553 9554 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx); 9555 9556 /* 9557 * 1) We should set ->mode before checking ->requests. Please see 9558 * the comment in kvm_vcpu_exiting_guest_mode(). 9559 * 9560 * 2) For APICv, we should set ->mode before checking PID.ON. This 9561 * pairs with the memory barrier implicit in pi_test_and_set_on 9562 * (see vmx_deliver_posted_interrupt). 9563 * 9564 * 3) This also orders the write to mode from any reads to the page 9565 * tables done while the VCPU is running. Please see the comment 9566 * in kvm_flush_remote_tlbs. 9567 */ 9568 smp_mb__after_srcu_read_unlock(); 9569 9570 /* 9571 * This handles the case where a posted interrupt was 9572 * notified with kvm_vcpu_kick. 9573 */ 9574 if (kvm_lapic_enabled(vcpu) && vcpu->arch.apicv_active) 9575 static_call(kvm_x86_sync_pir_to_irr)(vcpu); 9576 9577 if (kvm_vcpu_exit_request(vcpu)) { 9578 vcpu->mode = OUTSIDE_GUEST_MODE; 9579 smp_wmb(); 9580 local_irq_enable(); 9581 preempt_enable(); 9582 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu); 9583 r = 1; 9584 goto cancel_injection; 9585 } 9586 9587 if (req_immediate_exit) { 9588 kvm_make_request(KVM_REQ_EVENT, vcpu); 9589 static_call(kvm_x86_request_immediate_exit)(vcpu); 9590 } 9591 9592 fpregs_assert_state_consistent(); 9593 if (test_thread_flag(TIF_NEED_FPU_LOAD)) 9594 switch_fpu_return(); 9595 9596 if (unlikely(vcpu->arch.switch_db_regs)) { 9597 set_debugreg(0, 7); 9598 set_debugreg(vcpu->arch.eff_db[0], 0); 9599 set_debugreg(vcpu->arch.eff_db[1], 1); 9600 set_debugreg(vcpu->arch.eff_db[2], 2); 9601 set_debugreg(vcpu->arch.eff_db[3], 3); 9602 set_debugreg(vcpu->arch.dr6, 6); 9603 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD; 9604 } 9605 9606 for (;;) { 9607 exit_fastpath = static_call(kvm_x86_run)(vcpu); 9608 if (likely(exit_fastpath != EXIT_FASTPATH_REENTER_GUEST)) 9609 break; 9610 9611 if (unlikely(kvm_vcpu_exit_request(vcpu))) { 9612 exit_fastpath = EXIT_FASTPATH_EXIT_HANDLED; 9613 break; 9614 } 9615 9616 if (vcpu->arch.apicv_active) 9617 static_call(kvm_x86_sync_pir_to_irr)(vcpu); 9618 } 9619 9620 /* 9621 * Do this here before restoring debug registers on the host. And 9622 * since we do this before handling the vmexit, a DR access vmexit 9623 * can (a) read the correct value of the debug registers, (b) set 9624 * KVM_DEBUGREG_WONT_EXIT again. 9625 */ 9626 if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) { 9627 WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP); 9628 static_call(kvm_x86_sync_dirty_debug_regs)(vcpu); 9629 kvm_update_dr0123(vcpu); 9630 kvm_update_dr7(vcpu); 9631 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD; 9632 } 9633 9634 /* 9635 * If the guest has used debug registers, at least dr7 9636 * will be disabled while returning to the host. 9637 * If we don't have active breakpoints in the host, we don't 9638 * care about the messed up debug address registers. But if 9639 * we have some of them active, restore the old state. 9640 */ 9641 if (hw_breakpoint_active()) 9642 hw_breakpoint_restore(); 9643 9644 vcpu->arch.last_vmentry_cpu = vcpu->cpu; 9645 vcpu->arch.last_guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc()); 9646 9647 vcpu->mode = OUTSIDE_GUEST_MODE; 9648 smp_wmb(); 9649 9650 static_call(kvm_x86_handle_exit_irqoff)(vcpu); 9651 9652 /* 9653 * Consume any pending interrupts, including the possible source of 9654 * VM-Exit on SVM and any ticks that occur between VM-Exit and now. 9655 * An instruction is required after local_irq_enable() to fully unblock 9656 * interrupts on processors that implement an interrupt shadow, the 9657 * stat.exits increment will do nicely. 9658 */ 9659 kvm_before_interrupt(vcpu); 9660 local_irq_enable(); 9661 ++vcpu->stat.exits; 9662 local_irq_disable(); 9663 kvm_after_interrupt(vcpu); 9664 9665 /* 9666 * Wait until after servicing IRQs to account guest time so that any 9667 * ticks that occurred while running the guest are properly accounted 9668 * to the guest. Waiting until IRQs are enabled degrades the accuracy 9669 * of accounting via context tracking, but the loss of accuracy is 9670 * acceptable for all known use cases. 9671 */ 9672 vtime_account_guest_exit(); 9673 9674 if (lapic_in_kernel(vcpu)) { 9675 s64 delta = vcpu->arch.apic->lapic_timer.advance_expire_delta; 9676 if (delta != S64_MIN) { 9677 trace_kvm_wait_lapic_expire(vcpu->vcpu_id, delta); 9678 vcpu->arch.apic->lapic_timer.advance_expire_delta = S64_MIN; 9679 } 9680 } 9681 9682 local_irq_enable(); 9683 preempt_enable(); 9684 9685 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu); 9686 9687 /* 9688 * Profile KVM exit RIPs: 9689 */ 9690 if (unlikely(prof_on == KVM_PROFILING)) { 9691 unsigned long rip = kvm_rip_read(vcpu); 9692 profile_hit(KVM_PROFILING, (void *)rip); 9693 } 9694 9695 if (unlikely(vcpu->arch.tsc_always_catchup)) 9696 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 9697 9698 if (vcpu->arch.apic_attention) 9699 kvm_lapic_sync_from_vapic(vcpu); 9700 9701 r = static_call(kvm_x86_handle_exit)(vcpu, exit_fastpath); 9702 return r; 9703 9704 cancel_injection: 9705 if (req_immediate_exit) 9706 kvm_make_request(KVM_REQ_EVENT, vcpu); 9707 static_call(kvm_x86_cancel_injection)(vcpu); 9708 if (unlikely(vcpu->arch.apic_attention)) 9709 kvm_lapic_sync_from_vapic(vcpu); 9710 out: 9711 return r; 9712 } 9713 9714 static inline int vcpu_block(struct kvm *kvm, struct kvm_vcpu *vcpu) 9715 { 9716 if (!kvm_arch_vcpu_runnable(vcpu) && 9717 (!kvm_x86_ops.pre_block || static_call(kvm_x86_pre_block)(vcpu) == 0)) { 9718 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx); 9719 kvm_vcpu_block(vcpu); 9720 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu); 9721 9722 if (kvm_x86_ops.post_block) 9723 static_call(kvm_x86_post_block)(vcpu); 9724 9725 if (!kvm_check_request(KVM_REQ_UNHALT, vcpu)) 9726 return 1; 9727 } 9728 9729 if (kvm_apic_accept_events(vcpu) < 0) 9730 return 0; 9731 switch(vcpu->arch.mp_state) { 9732 case KVM_MP_STATE_HALTED: 9733 case KVM_MP_STATE_AP_RESET_HOLD: 9734 vcpu->arch.pv.pv_unhalted = false; 9735 vcpu->arch.mp_state = 9736 KVM_MP_STATE_RUNNABLE; 9737 fallthrough; 9738 case KVM_MP_STATE_RUNNABLE: 9739 vcpu->arch.apf.halted = false; 9740 break; 9741 case KVM_MP_STATE_INIT_RECEIVED: 9742 break; 9743 default: 9744 return -EINTR; 9745 } 9746 return 1; 9747 } 9748 9749 static inline bool kvm_vcpu_running(struct kvm_vcpu *vcpu) 9750 { 9751 if (is_guest_mode(vcpu)) 9752 kvm_check_nested_events(vcpu); 9753 9754 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE && 9755 !vcpu->arch.apf.halted); 9756 } 9757 9758 static int vcpu_run(struct kvm_vcpu *vcpu) 9759 { 9760 int r; 9761 struct kvm *kvm = vcpu->kvm; 9762 9763 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu); 9764 vcpu->arch.l1tf_flush_l1d = true; 9765 9766 for (;;) { 9767 if (kvm_vcpu_running(vcpu)) { 9768 r = vcpu_enter_guest(vcpu); 9769 } else { 9770 r = vcpu_block(kvm, vcpu); 9771 } 9772 9773 if (r <= 0) 9774 break; 9775 9776 kvm_clear_request(KVM_REQ_UNBLOCK, vcpu); 9777 if (kvm_cpu_has_pending_timer(vcpu)) 9778 kvm_inject_pending_timer_irqs(vcpu); 9779 9780 if (dm_request_for_irq_injection(vcpu) && 9781 kvm_vcpu_ready_for_interrupt_injection(vcpu)) { 9782 r = 0; 9783 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN; 9784 ++vcpu->stat.request_irq_exits; 9785 break; 9786 } 9787 9788 if (__xfer_to_guest_mode_work_pending()) { 9789 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx); 9790 r = xfer_to_guest_mode_handle_work(vcpu); 9791 if (r) 9792 return r; 9793 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu); 9794 } 9795 } 9796 9797 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx); 9798 9799 return r; 9800 } 9801 9802 static inline int complete_emulated_io(struct kvm_vcpu *vcpu) 9803 { 9804 int r; 9805 9806 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu); 9807 r = kvm_emulate_instruction(vcpu, EMULTYPE_NO_DECODE); 9808 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx); 9809 return r; 9810 } 9811 9812 static int complete_emulated_pio(struct kvm_vcpu *vcpu) 9813 { 9814 BUG_ON(!vcpu->arch.pio.count); 9815 9816 return complete_emulated_io(vcpu); 9817 } 9818 9819 /* 9820 * Implements the following, as a state machine: 9821 * 9822 * read: 9823 * for each fragment 9824 * for each mmio piece in the fragment 9825 * write gpa, len 9826 * exit 9827 * copy data 9828 * execute insn 9829 * 9830 * write: 9831 * for each fragment 9832 * for each mmio piece in the fragment 9833 * write gpa, len 9834 * copy data 9835 * exit 9836 */ 9837 static int complete_emulated_mmio(struct kvm_vcpu *vcpu) 9838 { 9839 struct kvm_run *run = vcpu->run; 9840 struct kvm_mmio_fragment *frag; 9841 unsigned len; 9842 9843 BUG_ON(!vcpu->mmio_needed); 9844 9845 /* Complete previous fragment */ 9846 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment]; 9847 len = min(8u, frag->len); 9848 if (!vcpu->mmio_is_write) 9849 memcpy(frag->data, run->mmio.data, len); 9850 9851 if (frag->len <= 8) { 9852 /* Switch to the next fragment. */ 9853 frag++; 9854 vcpu->mmio_cur_fragment++; 9855 } else { 9856 /* Go forward to the next mmio piece. */ 9857 frag->data += len; 9858 frag->gpa += len; 9859 frag->len -= len; 9860 } 9861 9862 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) { 9863 vcpu->mmio_needed = 0; 9864 9865 /* FIXME: return into emulator if single-stepping. */ 9866 if (vcpu->mmio_is_write) 9867 return 1; 9868 vcpu->mmio_read_completed = 1; 9869 return complete_emulated_io(vcpu); 9870 } 9871 9872 run->exit_reason = KVM_EXIT_MMIO; 9873 run->mmio.phys_addr = frag->gpa; 9874 if (vcpu->mmio_is_write) 9875 memcpy(run->mmio.data, frag->data, min(8u, frag->len)); 9876 run->mmio.len = min(8u, frag->len); 9877 run->mmio.is_write = vcpu->mmio_is_write; 9878 vcpu->arch.complete_userspace_io = complete_emulated_mmio; 9879 return 0; 9880 } 9881 9882 static void kvm_save_current_fpu(struct fpu *fpu) 9883 { 9884 /* 9885 * If the target FPU state is not resident in the CPU registers, just 9886 * memcpy() from current, else save CPU state directly to the target. 9887 */ 9888 if (test_thread_flag(TIF_NEED_FPU_LOAD)) 9889 memcpy(&fpu->state, ¤t->thread.fpu.state, 9890 fpu_kernel_xstate_size); 9891 else 9892 save_fpregs_to_fpstate(fpu); 9893 } 9894 9895 /* Swap (qemu) user FPU context for the guest FPU context. */ 9896 static void kvm_load_guest_fpu(struct kvm_vcpu *vcpu) 9897 { 9898 fpregs_lock(); 9899 9900 kvm_save_current_fpu(vcpu->arch.user_fpu); 9901 9902 /* 9903 * Guests with protected state can't have it set by the hypervisor, 9904 * so skip trying to set it. 9905 */ 9906 if (vcpu->arch.guest_fpu) 9907 /* PKRU is separately restored in kvm_x86_ops.run. */ 9908 __restore_fpregs_from_fpstate(&vcpu->arch.guest_fpu->state, 9909 ~XFEATURE_MASK_PKRU); 9910 9911 fpregs_mark_activate(); 9912 fpregs_unlock(); 9913 9914 trace_kvm_fpu(1); 9915 } 9916 9917 /* When vcpu_run ends, restore user space FPU context. */ 9918 static void kvm_put_guest_fpu(struct kvm_vcpu *vcpu) 9919 { 9920 fpregs_lock(); 9921 9922 /* 9923 * Guests with protected state can't have it read by the hypervisor, 9924 * so skip trying to save it. 9925 */ 9926 if (vcpu->arch.guest_fpu) 9927 kvm_save_current_fpu(vcpu->arch.guest_fpu); 9928 9929 restore_fpregs_from_fpstate(&vcpu->arch.user_fpu->state); 9930 9931 fpregs_mark_activate(); 9932 fpregs_unlock(); 9933 9934 ++vcpu->stat.fpu_reload; 9935 trace_kvm_fpu(0); 9936 } 9937 9938 int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu) 9939 { 9940 struct kvm_run *kvm_run = vcpu->run; 9941 int r; 9942 9943 vcpu_load(vcpu); 9944 kvm_sigset_activate(vcpu); 9945 kvm_run->flags = 0; 9946 kvm_load_guest_fpu(vcpu); 9947 9948 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) { 9949 if (kvm_run->immediate_exit) { 9950 r = -EINTR; 9951 goto out; 9952 } 9953 kvm_vcpu_block(vcpu); 9954 if (kvm_apic_accept_events(vcpu) < 0) { 9955 r = 0; 9956 goto out; 9957 } 9958 kvm_clear_request(KVM_REQ_UNHALT, vcpu); 9959 r = -EAGAIN; 9960 if (signal_pending(current)) { 9961 r = -EINTR; 9962 kvm_run->exit_reason = KVM_EXIT_INTR; 9963 ++vcpu->stat.signal_exits; 9964 } 9965 goto out; 9966 } 9967 9968 if (kvm_run->kvm_valid_regs & ~KVM_SYNC_X86_VALID_FIELDS) { 9969 r = -EINVAL; 9970 goto out; 9971 } 9972 9973 if (kvm_run->kvm_dirty_regs) { 9974 r = sync_regs(vcpu); 9975 if (r != 0) 9976 goto out; 9977 } 9978 9979 /* re-sync apic's tpr */ 9980 if (!lapic_in_kernel(vcpu)) { 9981 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) { 9982 r = -EINVAL; 9983 goto out; 9984 } 9985 } 9986 9987 if (unlikely(vcpu->arch.complete_userspace_io)) { 9988 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io; 9989 vcpu->arch.complete_userspace_io = NULL; 9990 r = cui(vcpu); 9991 if (r <= 0) 9992 goto out; 9993 } else 9994 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed); 9995 9996 if (kvm_run->immediate_exit) 9997 r = -EINTR; 9998 else 9999 r = vcpu_run(vcpu); 10000 10001 out: 10002 kvm_put_guest_fpu(vcpu); 10003 if (kvm_run->kvm_valid_regs) 10004 store_regs(vcpu); 10005 post_kvm_run_save(vcpu); 10006 kvm_sigset_deactivate(vcpu); 10007 10008 vcpu_put(vcpu); 10009 return r; 10010 } 10011 10012 static void __get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) 10013 { 10014 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) { 10015 /* 10016 * We are here if userspace calls get_regs() in the middle of 10017 * instruction emulation. Registers state needs to be copied 10018 * back from emulation context to vcpu. Userspace shouldn't do 10019 * that usually, but some bad designed PV devices (vmware 10020 * backdoor interface) need this to work 10021 */ 10022 emulator_writeback_register_cache(vcpu->arch.emulate_ctxt); 10023 vcpu->arch.emulate_regs_need_sync_to_vcpu = false; 10024 } 10025 regs->rax = kvm_rax_read(vcpu); 10026 regs->rbx = kvm_rbx_read(vcpu); 10027 regs->rcx = kvm_rcx_read(vcpu); 10028 regs->rdx = kvm_rdx_read(vcpu); 10029 regs->rsi = kvm_rsi_read(vcpu); 10030 regs->rdi = kvm_rdi_read(vcpu); 10031 regs->rsp = kvm_rsp_read(vcpu); 10032 regs->rbp = kvm_rbp_read(vcpu); 10033 #ifdef CONFIG_X86_64 10034 regs->r8 = kvm_r8_read(vcpu); 10035 regs->r9 = kvm_r9_read(vcpu); 10036 regs->r10 = kvm_r10_read(vcpu); 10037 regs->r11 = kvm_r11_read(vcpu); 10038 regs->r12 = kvm_r12_read(vcpu); 10039 regs->r13 = kvm_r13_read(vcpu); 10040 regs->r14 = kvm_r14_read(vcpu); 10041 regs->r15 = kvm_r15_read(vcpu); 10042 #endif 10043 10044 regs->rip = kvm_rip_read(vcpu); 10045 regs->rflags = kvm_get_rflags(vcpu); 10046 } 10047 10048 int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) 10049 { 10050 vcpu_load(vcpu); 10051 __get_regs(vcpu, regs); 10052 vcpu_put(vcpu); 10053 return 0; 10054 } 10055 10056 static void __set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) 10057 { 10058 vcpu->arch.emulate_regs_need_sync_from_vcpu = true; 10059 vcpu->arch.emulate_regs_need_sync_to_vcpu = false; 10060 10061 kvm_rax_write(vcpu, regs->rax); 10062 kvm_rbx_write(vcpu, regs->rbx); 10063 kvm_rcx_write(vcpu, regs->rcx); 10064 kvm_rdx_write(vcpu, regs->rdx); 10065 kvm_rsi_write(vcpu, regs->rsi); 10066 kvm_rdi_write(vcpu, regs->rdi); 10067 kvm_rsp_write(vcpu, regs->rsp); 10068 kvm_rbp_write(vcpu, regs->rbp); 10069 #ifdef CONFIG_X86_64 10070 kvm_r8_write(vcpu, regs->r8); 10071 kvm_r9_write(vcpu, regs->r9); 10072 kvm_r10_write(vcpu, regs->r10); 10073 kvm_r11_write(vcpu, regs->r11); 10074 kvm_r12_write(vcpu, regs->r12); 10075 kvm_r13_write(vcpu, regs->r13); 10076 kvm_r14_write(vcpu, regs->r14); 10077 kvm_r15_write(vcpu, regs->r15); 10078 #endif 10079 10080 kvm_rip_write(vcpu, regs->rip); 10081 kvm_set_rflags(vcpu, regs->rflags | X86_EFLAGS_FIXED); 10082 10083 vcpu->arch.exception.pending = false; 10084 10085 kvm_make_request(KVM_REQ_EVENT, vcpu); 10086 } 10087 10088 int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) 10089 { 10090 vcpu_load(vcpu); 10091 __set_regs(vcpu, regs); 10092 vcpu_put(vcpu); 10093 return 0; 10094 } 10095 10096 void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l) 10097 { 10098 struct kvm_segment cs; 10099 10100 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS); 10101 *db = cs.db; 10102 *l = cs.l; 10103 } 10104 EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits); 10105 10106 static void __get_sregs_common(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs) 10107 { 10108 struct desc_ptr dt; 10109 10110 if (vcpu->arch.guest_state_protected) 10111 goto skip_protected_regs; 10112 10113 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS); 10114 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS); 10115 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES); 10116 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS); 10117 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS); 10118 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS); 10119 10120 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR); 10121 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR); 10122 10123 static_call(kvm_x86_get_idt)(vcpu, &dt); 10124 sregs->idt.limit = dt.size; 10125 sregs->idt.base = dt.address; 10126 static_call(kvm_x86_get_gdt)(vcpu, &dt); 10127 sregs->gdt.limit = dt.size; 10128 sregs->gdt.base = dt.address; 10129 10130 sregs->cr2 = vcpu->arch.cr2; 10131 sregs->cr3 = kvm_read_cr3(vcpu); 10132 10133 skip_protected_regs: 10134 sregs->cr0 = kvm_read_cr0(vcpu); 10135 sregs->cr4 = kvm_read_cr4(vcpu); 10136 sregs->cr8 = kvm_get_cr8(vcpu); 10137 sregs->efer = vcpu->arch.efer; 10138 sregs->apic_base = kvm_get_apic_base(vcpu); 10139 } 10140 10141 static void __get_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs) 10142 { 10143 __get_sregs_common(vcpu, sregs); 10144 10145 if (vcpu->arch.guest_state_protected) 10146 return; 10147 10148 if (vcpu->arch.interrupt.injected && !vcpu->arch.interrupt.soft) 10149 set_bit(vcpu->arch.interrupt.nr, 10150 (unsigned long *)sregs->interrupt_bitmap); 10151 } 10152 10153 static void __get_sregs2(struct kvm_vcpu *vcpu, struct kvm_sregs2 *sregs2) 10154 { 10155 int i; 10156 10157 __get_sregs_common(vcpu, (struct kvm_sregs *)sregs2); 10158 10159 if (vcpu->arch.guest_state_protected) 10160 return; 10161 10162 if (is_pae_paging(vcpu)) { 10163 for (i = 0 ; i < 4 ; i++) 10164 sregs2->pdptrs[i] = kvm_pdptr_read(vcpu, i); 10165 sregs2->flags |= KVM_SREGS2_FLAGS_PDPTRS_VALID; 10166 } 10167 } 10168 10169 int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu, 10170 struct kvm_sregs *sregs) 10171 { 10172 vcpu_load(vcpu); 10173 __get_sregs(vcpu, sregs); 10174 vcpu_put(vcpu); 10175 return 0; 10176 } 10177 10178 int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu, 10179 struct kvm_mp_state *mp_state) 10180 { 10181 int r; 10182 10183 vcpu_load(vcpu); 10184 if (kvm_mpx_supported()) 10185 kvm_load_guest_fpu(vcpu); 10186 10187 r = kvm_apic_accept_events(vcpu); 10188 if (r < 0) 10189 goto out; 10190 r = 0; 10191 10192 if ((vcpu->arch.mp_state == KVM_MP_STATE_HALTED || 10193 vcpu->arch.mp_state == KVM_MP_STATE_AP_RESET_HOLD) && 10194 vcpu->arch.pv.pv_unhalted) 10195 mp_state->mp_state = KVM_MP_STATE_RUNNABLE; 10196 else 10197 mp_state->mp_state = vcpu->arch.mp_state; 10198 10199 out: 10200 if (kvm_mpx_supported()) 10201 kvm_put_guest_fpu(vcpu); 10202 vcpu_put(vcpu); 10203 return r; 10204 } 10205 10206 int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu, 10207 struct kvm_mp_state *mp_state) 10208 { 10209 int ret = -EINVAL; 10210 10211 vcpu_load(vcpu); 10212 10213 if (!lapic_in_kernel(vcpu) && 10214 mp_state->mp_state != KVM_MP_STATE_RUNNABLE) 10215 goto out; 10216 10217 /* 10218 * KVM_MP_STATE_INIT_RECEIVED means the processor is in 10219 * INIT state; latched init should be reported using 10220 * KVM_SET_VCPU_EVENTS, so reject it here. 10221 */ 10222 if ((kvm_vcpu_latch_init(vcpu) || vcpu->arch.smi_pending) && 10223 (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED || 10224 mp_state->mp_state == KVM_MP_STATE_INIT_RECEIVED)) 10225 goto out; 10226 10227 if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) { 10228 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED; 10229 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events); 10230 } else 10231 vcpu->arch.mp_state = mp_state->mp_state; 10232 kvm_make_request(KVM_REQ_EVENT, vcpu); 10233 10234 ret = 0; 10235 out: 10236 vcpu_put(vcpu); 10237 return ret; 10238 } 10239 10240 int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index, 10241 int reason, bool has_error_code, u32 error_code) 10242 { 10243 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt; 10244 int ret; 10245 10246 init_emulate_ctxt(vcpu); 10247 10248 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason, 10249 has_error_code, error_code); 10250 if (ret) { 10251 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR; 10252 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION; 10253 vcpu->run->internal.ndata = 0; 10254 return 0; 10255 } 10256 10257 kvm_rip_write(vcpu, ctxt->eip); 10258 kvm_set_rflags(vcpu, ctxt->eflags); 10259 return 1; 10260 } 10261 EXPORT_SYMBOL_GPL(kvm_task_switch); 10262 10263 static bool kvm_is_valid_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs) 10264 { 10265 if ((sregs->efer & EFER_LME) && (sregs->cr0 & X86_CR0_PG)) { 10266 /* 10267 * When EFER.LME and CR0.PG are set, the processor is in 10268 * 64-bit mode (though maybe in a 32-bit code segment). 10269 * CR4.PAE and EFER.LMA must be set. 10270 */ 10271 if (!(sregs->cr4 & X86_CR4_PAE) || !(sregs->efer & EFER_LMA)) 10272 return false; 10273 if (kvm_vcpu_is_illegal_gpa(vcpu, sregs->cr3)) 10274 return false; 10275 } else { 10276 /* 10277 * Not in 64-bit mode: EFER.LMA is clear and the code 10278 * segment cannot be 64-bit. 10279 */ 10280 if (sregs->efer & EFER_LMA || sregs->cs.l) 10281 return false; 10282 } 10283 10284 return kvm_is_valid_cr4(vcpu, sregs->cr4); 10285 } 10286 10287 static int __set_sregs_common(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs, 10288 int *mmu_reset_needed, bool update_pdptrs) 10289 { 10290 struct msr_data apic_base_msr; 10291 int idx; 10292 struct desc_ptr dt; 10293 10294 if (!kvm_is_valid_sregs(vcpu, sregs)) 10295 return -EINVAL; 10296 10297 apic_base_msr.data = sregs->apic_base; 10298 apic_base_msr.host_initiated = true; 10299 if (kvm_set_apic_base(vcpu, &apic_base_msr)) 10300 return -EINVAL; 10301 10302 if (vcpu->arch.guest_state_protected) 10303 return 0; 10304 10305 dt.size = sregs->idt.limit; 10306 dt.address = sregs->idt.base; 10307 static_call(kvm_x86_set_idt)(vcpu, &dt); 10308 dt.size = sregs->gdt.limit; 10309 dt.address = sregs->gdt.base; 10310 static_call(kvm_x86_set_gdt)(vcpu, &dt); 10311 10312 vcpu->arch.cr2 = sregs->cr2; 10313 *mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3; 10314 vcpu->arch.cr3 = sregs->cr3; 10315 kvm_register_mark_available(vcpu, VCPU_EXREG_CR3); 10316 10317 kvm_set_cr8(vcpu, sregs->cr8); 10318 10319 *mmu_reset_needed |= vcpu->arch.efer != sregs->efer; 10320 static_call(kvm_x86_set_efer)(vcpu, sregs->efer); 10321 10322 *mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0; 10323 static_call(kvm_x86_set_cr0)(vcpu, sregs->cr0); 10324 vcpu->arch.cr0 = sregs->cr0; 10325 10326 *mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4; 10327 static_call(kvm_x86_set_cr4)(vcpu, sregs->cr4); 10328 10329 if (update_pdptrs) { 10330 idx = srcu_read_lock(&vcpu->kvm->srcu); 10331 if (is_pae_paging(vcpu)) { 10332 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu)); 10333 *mmu_reset_needed = 1; 10334 } 10335 srcu_read_unlock(&vcpu->kvm->srcu, idx); 10336 } 10337 10338 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS); 10339 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS); 10340 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES); 10341 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS); 10342 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS); 10343 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS); 10344 10345 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR); 10346 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR); 10347 10348 update_cr8_intercept(vcpu); 10349 10350 /* Older userspace won't unhalt the vcpu on reset. */ 10351 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 && 10352 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 && 10353 !is_protmode(vcpu)) 10354 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; 10355 10356 return 0; 10357 } 10358 10359 static int __set_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs) 10360 { 10361 int pending_vec, max_bits; 10362 int mmu_reset_needed = 0; 10363 int ret = __set_sregs_common(vcpu, sregs, &mmu_reset_needed, true); 10364 10365 if (ret) 10366 return ret; 10367 10368 if (mmu_reset_needed) 10369 kvm_mmu_reset_context(vcpu); 10370 10371 max_bits = KVM_NR_INTERRUPTS; 10372 pending_vec = find_first_bit( 10373 (const unsigned long *)sregs->interrupt_bitmap, max_bits); 10374 10375 if (pending_vec < max_bits) { 10376 kvm_queue_interrupt(vcpu, pending_vec, false); 10377 pr_debug("Set back pending irq %d\n", pending_vec); 10378 kvm_make_request(KVM_REQ_EVENT, vcpu); 10379 } 10380 return 0; 10381 } 10382 10383 static int __set_sregs2(struct kvm_vcpu *vcpu, struct kvm_sregs2 *sregs2) 10384 { 10385 int mmu_reset_needed = 0; 10386 bool valid_pdptrs = sregs2->flags & KVM_SREGS2_FLAGS_PDPTRS_VALID; 10387 bool pae = (sregs2->cr0 & X86_CR0_PG) && (sregs2->cr4 & X86_CR4_PAE) && 10388 !(sregs2->efer & EFER_LMA); 10389 int i, ret; 10390 10391 if (sregs2->flags & ~KVM_SREGS2_FLAGS_PDPTRS_VALID) 10392 return -EINVAL; 10393 10394 if (valid_pdptrs && (!pae || vcpu->arch.guest_state_protected)) 10395 return -EINVAL; 10396 10397 ret = __set_sregs_common(vcpu, (struct kvm_sregs *)sregs2, 10398 &mmu_reset_needed, !valid_pdptrs); 10399 if (ret) 10400 return ret; 10401 10402 if (valid_pdptrs) { 10403 for (i = 0; i < 4 ; i++) 10404 kvm_pdptr_write(vcpu, i, sregs2->pdptrs[i]); 10405 10406 kvm_register_mark_dirty(vcpu, VCPU_EXREG_PDPTR); 10407 mmu_reset_needed = 1; 10408 vcpu->arch.pdptrs_from_userspace = true; 10409 } 10410 if (mmu_reset_needed) 10411 kvm_mmu_reset_context(vcpu); 10412 return 0; 10413 } 10414 10415 int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu, 10416 struct kvm_sregs *sregs) 10417 { 10418 int ret; 10419 10420 vcpu_load(vcpu); 10421 ret = __set_sregs(vcpu, sregs); 10422 vcpu_put(vcpu); 10423 return ret; 10424 } 10425 10426 int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu, 10427 struct kvm_guest_debug *dbg) 10428 { 10429 unsigned long rflags; 10430 int i, r; 10431 10432 if (vcpu->arch.guest_state_protected) 10433 return -EINVAL; 10434 10435 vcpu_load(vcpu); 10436 10437 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) { 10438 r = -EBUSY; 10439 if (vcpu->arch.exception.pending) 10440 goto out; 10441 if (dbg->control & KVM_GUESTDBG_INJECT_DB) 10442 kvm_queue_exception(vcpu, DB_VECTOR); 10443 else 10444 kvm_queue_exception(vcpu, BP_VECTOR); 10445 } 10446 10447 /* 10448 * Read rflags as long as potentially injected trace flags are still 10449 * filtered out. 10450 */ 10451 rflags = kvm_get_rflags(vcpu); 10452 10453 vcpu->guest_debug = dbg->control; 10454 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE)) 10455 vcpu->guest_debug = 0; 10456 10457 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) { 10458 for (i = 0; i < KVM_NR_DB_REGS; ++i) 10459 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i]; 10460 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7]; 10461 } else { 10462 for (i = 0; i < KVM_NR_DB_REGS; i++) 10463 vcpu->arch.eff_db[i] = vcpu->arch.db[i]; 10464 } 10465 kvm_update_dr7(vcpu); 10466 10467 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) 10468 vcpu->arch.singlestep_rip = kvm_get_linear_rip(vcpu); 10469 10470 /* 10471 * Trigger an rflags update that will inject or remove the trace 10472 * flags. 10473 */ 10474 kvm_set_rflags(vcpu, rflags); 10475 10476 static_call(kvm_x86_update_exception_bitmap)(vcpu); 10477 10478 r = 0; 10479 10480 out: 10481 vcpu_put(vcpu); 10482 return r; 10483 } 10484 10485 /* 10486 * Translate a guest virtual address to a guest physical address. 10487 */ 10488 int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu, 10489 struct kvm_translation *tr) 10490 { 10491 unsigned long vaddr = tr->linear_address; 10492 gpa_t gpa; 10493 int idx; 10494 10495 vcpu_load(vcpu); 10496 10497 idx = srcu_read_lock(&vcpu->kvm->srcu); 10498 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL); 10499 srcu_read_unlock(&vcpu->kvm->srcu, idx); 10500 tr->physical_address = gpa; 10501 tr->valid = gpa != UNMAPPED_GVA; 10502 tr->writeable = 1; 10503 tr->usermode = 0; 10504 10505 vcpu_put(vcpu); 10506 return 0; 10507 } 10508 10509 int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu) 10510 { 10511 struct fxregs_state *fxsave; 10512 10513 if (!vcpu->arch.guest_fpu) 10514 return 0; 10515 10516 vcpu_load(vcpu); 10517 10518 fxsave = &vcpu->arch.guest_fpu->state.fxsave; 10519 memcpy(fpu->fpr, fxsave->st_space, 128); 10520 fpu->fcw = fxsave->cwd; 10521 fpu->fsw = fxsave->swd; 10522 fpu->ftwx = fxsave->twd; 10523 fpu->last_opcode = fxsave->fop; 10524 fpu->last_ip = fxsave->rip; 10525 fpu->last_dp = fxsave->rdp; 10526 memcpy(fpu->xmm, fxsave->xmm_space, sizeof(fxsave->xmm_space)); 10527 10528 vcpu_put(vcpu); 10529 return 0; 10530 } 10531 10532 int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu) 10533 { 10534 struct fxregs_state *fxsave; 10535 10536 if (!vcpu->arch.guest_fpu) 10537 return 0; 10538 10539 vcpu_load(vcpu); 10540 10541 fxsave = &vcpu->arch.guest_fpu->state.fxsave; 10542 10543 memcpy(fxsave->st_space, fpu->fpr, 128); 10544 fxsave->cwd = fpu->fcw; 10545 fxsave->swd = fpu->fsw; 10546 fxsave->twd = fpu->ftwx; 10547 fxsave->fop = fpu->last_opcode; 10548 fxsave->rip = fpu->last_ip; 10549 fxsave->rdp = fpu->last_dp; 10550 memcpy(fxsave->xmm_space, fpu->xmm, sizeof(fxsave->xmm_space)); 10551 10552 vcpu_put(vcpu); 10553 return 0; 10554 } 10555 10556 static void store_regs(struct kvm_vcpu *vcpu) 10557 { 10558 BUILD_BUG_ON(sizeof(struct kvm_sync_regs) > SYNC_REGS_SIZE_BYTES); 10559 10560 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_REGS) 10561 __get_regs(vcpu, &vcpu->run->s.regs.regs); 10562 10563 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_SREGS) 10564 __get_sregs(vcpu, &vcpu->run->s.regs.sregs); 10565 10566 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_EVENTS) 10567 kvm_vcpu_ioctl_x86_get_vcpu_events( 10568 vcpu, &vcpu->run->s.regs.events); 10569 } 10570 10571 static int sync_regs(struct kvm_vcpu *vcpu) 10572 { 10573 if (vcpu->run->kvm_dirty_regs & ~KVM_SYNC_X86_VALID_FIELDS) 10574 return -EINVAL; 10575 10576 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_REGS) { 10577 __set_regs(vcpu, &vcpu->run->s.regs.regs); 10578 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_REGS; 10579 } 10580 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_SREGS) { 10581 if (__set_sregs(vcpu, &vcpu->run->s.regs.sregs)) 10582 return -EINVAL; 10583 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_SREGS; 10584 } 10585 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_EVENTS) { 10586 if (kvm_vcpu_ioctl_x86_set_vcpu_events( 10587 vcpu, &vcpu->run->s.regs.events)) 10588 return -EINVAL; 10589 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_EVENTS; 10590 } 10591 10592 return 0; 10593 } 10594 10595 static void fx_init(struct kvm_vcpu *vcpu) 10596 { 10597 if (!vcpu->arch.guest_fpu) 10598 return; 10599 10600 fpstate_init(&vcpu->arch.guest_fpu->state); 10601 if (boot_cpu_has(X86_FEATURE_XSAVES)) 10602 vcpu->arch.guest_fpu->state.xsave.header.xcomp_bv = 10603 host_xcr0 | XSTATE_COMPACTION_ENABLED; 10604 10605 /* 10606 * Ensure guest xcr0 is valid for loading 10607 */ 10608 vcpu->arch.xcr0 = XFEATURE_MASK_FP; 10609 10610 vcpu->arch.cr0 |= X86_CR0_ET; 10611 } 10612 10613 void kvm_free_guest_fpu(struct kvm_vcpu *vcpu) 10614 { 10615 if (vcpu->arch.guest_fpu) { 10616 kmem_cache_free(x86_fpu_cache, vcpu->arch.guest_fpu); 10617 vcpu->arch.guest_fpu = NULL; 10618 } 10619 } 10620 EXPORT_SYMBOL_GPL(kvm_free_guest_fpu); 10621 10622 int kvm_arch_vcpu_precreate(struct kvm *kvm, unsigned int id) 10623 { 10624 if (kvm_check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0) 10625 pr_warn_once("kvm: SMP vm created on host with unstable TSC; " 10626 "guest TSC will not be reliable\n"); 10627 10628 return 0; 10629 } 10630 10631 int kvm_arch_vcpu_create(struct kvm_vcpu *vcpu) 10632 { 10633 struct page *page; 10634 int r; 10635 10636 vcpu->arch.last_vmentry_cpu = -1; 10637 10638 if (!irqchip_in_kernel(vcpu->kvm) || kvm_vcpu_is_reset_bsp(vcpu)) 10639 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; 10640 else 10641 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED; 10642 10643 r = kvm_mmu_create(vcpu); 10644 if (r < 0) 10645 return r; 10646 10647 if (irqchip_in_kernel(vcpu->kvm)) { 10648 r = kvm_create_lapic(vcpu, lapic_timer_advance_ns); 10649 if (r < 0) 10650 goto fail_mmu_destroy; 10651 if (kvm_apicv_activated(vcpu->kvm)) 10652 vcpu->arch.apicv_active = true; 10653 } else 10654 static_branch_inc(&kvm_has_noapic_vcpu); 10655 10656 r = -ENOMEM; 10657 10658 page = alloc_page(GFP_KERNEL_ACCOUNT | __GFP_ZERO); 10659 if (!page) 10660 goto fail_free_lapic; 10661 vcpu->arch.pio_data = page_address(page); 10662 10663 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4, 10664 GFP_KERNEL_ACCOUNT); 10665 if (!vcpu->arch.mce_banks) 10666 goto fail_free_pio_data; 10667 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS; 10668 10669 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, 10670 GFP_KERNEL_ACCOUNT)) 10671 goto fail_free_mce_banks; 10672 10673 if (!alloc_emulate_ctxt(vcpu)) 10674 goto free_wbinvd_dirty_mask; 10675 10676 vcpu->arch.user_fpu = kmem_cache_zalloc(x86_fpu_cache, 10677 GFP_KERNEL_ACCOUNT); 10678 if (!vcpu->arch.user_fpu) { 10679 pr_err("kvm: failed to allocate userspace's fpu\n"); 10680 goto free_emulate_ctxt; 10681 } 10682 10683 vcpu->arch.guest_fpu = kmem_cache_zalloc(x86_fpu_cache, 10684 GFP_KERNEL_ACCOUNT); 10685 if (!vcpu->arch.guest_fpu) { 10686 pr_err("kvm: failed to allocate vcpu's fpu\n"); 10687 goto free_user_fpu; 10688 } 10689 fx_init(vcpu); 10690 10691 vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu); 10692 vcpu->arch.reserved_gpa_bits = kvm_vcpu_reserved_gpa_bits_raw(vcpu); 10693 10694 vcpu->arch.pat = MSR_IA32_CR_PAT_DEFAULT; 10695 10696 kvm_async_pf_hash_reset(vcpu); 10697 kvm_pmu_init(vcpu); 10698 10699 vcpu->arch.pending_external_vector = -1; 10700 vcpu->arch.preempted_in_kernel = false; 10701 10702 #if IS_ENABLED(CONFIG_HYPERV) 10703 vcpu->arch.hv_root_tdp = INVALID_PAGE; 10704 #endif 10705 10706 r = static_call(kvm_x86_vcpu_create)(vcpu); 10707 if (r) 10708 goto free_guest_fpu; 10709 10710 vcpu->arch.arch_capabilities = kvm_get_arch_capabilities(); 10711 vcpu->arch.msr_platform_info = MSR_PLATFORM_INFO_CPUID_FAULT; 10712 kvm_vcpu_mtrr_init(vcpu); 10713 vcpu_load(vcpu); 10714 kvm_set_tsc_khz(vcpu, max_tsc_khz); 10715 kvm_vcpu_reset(vcpu, false); 10716 kvm_init_mmu(vcpu); 10717 vcpu_put(vcpu); 10718 return 0; 10719 10720 free_guest_fpu: 10721 kvm_free_guest_fpu(vcpu); 10722 free_user_fpu: 10723 kmem_cache_free(x86_fpu_cache, vcpu->arch.user_fpu); 10724 free_emulate_ctxt: 10725 kmem_cache_free(x86_emulator_cache, vcpu->arch.emulate_ctxt); 10726 free_wbinvd_dirty_mask: 10727 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask); 10728 fail_free_mce_banks: 10729 kfree(vcpu->arch.mce_banks); 10730 fail_free_pio_data: 10731 free_page((unsigned long)vcpu->arch.pio_data); 10732 fail_free_lapic: 10733 kvm_free_lapic(vcpu); 10734 fail_mmu_destroy: 10735 kvm_mmu_destroy(vcpu); 10736 return r; 10737 } 10738 10739 void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu) 10740 { 10741 struct kvm *kvm = vcpu->kvm; 10742 10743 if (mutex_lock_killable(&vcpu->mutex)) 10744 return; 10745 vcpu_load(vcpu); 10746 kvm_synchronize_tsc(vcpu, 0); 10747 vcpu_put(vcpu); 10748 10749 /* poll control enabled by default */ 10750 vcpu->arch.msr_kvm_poll_control = 1; 10751 10752 mutex_unlock(&vcpu->mutex); 10753 10754 if (kvmclock_periodic_sync && vcpu->vcpu_idx == 0) 10755 schedule_delayed_work(&kvm->arch.kvmclock_sync_work, 10756 KVMCLOCK_SYNC_PERIOD); 10757 } 10758 10759 void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu) 10760 { 10761 struct gfn_to_pfn_cache *cache = &vcpu->arch.st.cache; 10762 int idx; 10763 10764 kvm_release_pfn(cache->pfn, cache->dirty, cache); 10765 10766 kvmclock_reset(vcpu); 10767 10768 static_call(kvm_x86_vcpu_free)(vcpu); 10769 10770 kmem_cache_free(x86_emulator_cache, vcpu->arch.emulate_ctxt); 10771 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask); 10772 kmem_cache_free(x86_fpu_cache, vcpu->arch.user_fpu); 10773 kvm_free_guest_fpu(vcpu); 10774 10775 kvm_hv_vcpu_uninit(vcpu); 10776 kvm_pmu_destroy(vcpu); 10777 kfree(vcpu->arch.mce_banks); 10778 kvm_free_lapic(vcpu); 10779 idx = srcu_read_lock(&vcpu->kvm->srcu); 10780 kvm_mmu_destroy(vcpu); 10781 srcu_read_unlock(&vcpu->kvm->srcu, idx); 10782 free_page((unsigned long)vcpu->arch.pio_data); 10783 kvfree(vcpu->arch.cpuid_entries); 10784 if (!lapic_in_kernel(vcpu)) 10785 static_branch_dec(&kvm_has_noapic_vcpu); 10786 } 10787 10788 void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event) 10789 { 10790 unsigned long old_cr0 = kvm_read_cr0(vcpu); 10791 10792 kvm_lapic_reset(vcpu, init_event); 10793 10794 vcpu->arch.hflags = 0; 10795 10796 vcpu->arch.smi_pending = 0; 10797 vcpu->arch.smi_count = 0; 10798 atomic_set(&vcpu->arch.nmi_queued, 0); 10799 vcpu->arch.nmi_pending = 0; 10800 vcpu->arch.nmi_injected = false; 10801 kvm_clear_interrupt_queue(vcpu); 10802 kvm_clear_exception_queue(vcpu); 10803 10804 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db)); 10805 kvm_update_dr0123(vcpu); 10806 vcpu->arch.dr6 = DR6_ACTIVE_LOW; 10807 vcpu->arch.dr7 = DR7_FIXED_1; 10808 kvm_update_dr7(vcpu); 10809 10810 vcpu->arch.cr2 = 0; 10811 10812 kvm_make_request(KVM_REQ_EVENT, vcpu); 10813 vcpu->arch.apf.msr_en_val = 0; 10814 vcpu->arch.apf.msr_int_val = 0; 10815 vcpu->arch.st.msr_val = 0; 10816 10817 kvmclock_reset(vcpu); 10818 10819 kvm_clear_async_pf_completion_queue(vcpu); 10820 kvm_async_pf_hash_reset(vcpu); 10821 vcpu->arch.apf.halted = false; 10822 10823 if (vcpu->arch.guest_fpu && kvm_mpx_supported()) { 10824 void *mpx_state_buffer; 10825 10826 /* 10827 * To avoid have the INIT path from kvm_apic_has_events() that be 10828 * called with loaded FPU and does not let userspace fix the state. 10829 */ 10830 if (init_event) 10831 kvm_put_guest_fpu(vcpu); 10832 mpx_state_buffer = get_xsave_addr(&vcpu->arch.guest_fpu->state.xsave, 10833 XFEATURE_BNDREGS); 10834 if (mpx_state_buffer) 10835 memset(mpx_state_buffer, 0, sizeof(struct mpx_bndreg_state)); 10836 mpx_state_buffer = get_xsave_addr(&vcpu->arch.guest_fpu->state.xsave, 10837 XFEATURE_BNDCSR); 10838 if (mpx_state_buffer) 10839 memset(mpx_state_buffer, 0, sizeof(struct mpx_bndcsr)); 10840 if (init_event) 10841 kvm_load_guest_fpu(vcpu); 10842 } 10843 10844 if (!init_event) { 10845 kvm_pmu_reset(vcpu); 10846 vcpu->arch.smbase = 0x30000; 10847 10848 vcpu->arch.msr_misc_features_enables = 0; 10849 10850 vcpu->arch.xcr0 = XFEATURE_MASK_FP; 10851 } 10852 10853 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs)); 10854 vcpu->arch.regs_avail = ~0; 10855 vcpu->arch.regs_dirty = ~0; 10856 10857 vcpu->arch.ia32_xss = 0; 10858 10859 static_call(kvm_x86_vcpu_reset)(vcpu, init_event); 10860 10861 /* 10862 * Reset the MMU context if paging was enabled prior to INIT (which is 10863 * implied if CR0.PG=1 as CR0 will be '0' prior to RESET). Unlike the 10864 * standard CR0/CR4/EFER modification paths, only CR0.PG needs to be 10865 * checked because it is unconditionally cleared on INIT and all other 10866 * paging related bits are ignored if paging is disabled, i.e. CR0.WP, 10867 * CR4, and EFER changes are all irrelevant if CR0.PG was '0'. 10868 */ 10869 if (old_cr0 & X86_CR0_PG) 10870 kvm_mmu_reset_context(vcpu); 10871 } 10872 10873 void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector) 10874 { 10875 struct kvm_segment cs; 10876 10877 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS); 10878 cs.selector = vector << 8; 10879 cs.base = vector << 12; 10880 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS); 10881 kvm_rip_write(vcpu, 0); 10882 } 10883 EXPORT_SYMBOL_GPL(kvm_vcpu_deliver_sipi_vector); 10884 10885 int kvm_arch_hardware_enable(void) 10886 { 10887 struct kvm *kvm; 10888 struct kvm_vcpu *vcpu; 10889 int i; 10890 int ret; 10891 u64 local_tsc; 10892 u64 max_tsc = 0; 10893 bool stable, backwards_tsc = false; 10894 10895 kvm_user_return_msr_cpu_online(); 10896 ret = static_call(kvm_x86_hardware_enable)(); 10897 if (ret != 0) 10898 return ret; 10899 10900 local_tsc = rdtsc(); 10901 stable = !kvm_check_tsc_unstable(); 10902 list_for_each_entry(kvm, &vm_list, vm_list) { 10903 kvm_for_each_vcpu(i, vcpu, kvm) { 10904 if (!stable && vcpu->cpu == smp_processor_id()) 10905 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 10906 if (stable && vcpu->arch.last_host_tsc > local_tsc) { 10907 backwards_tsc = true; 10908 if (vcpu->arch.last_host_tsc > max_tsc) 10909 max_tsc = vcpu->arch.last_host_tsc; 10910 } 10911 } 10912 } 10913 10914 /* 10915 * Sometimes, even reliable TSCs go backwards. This happens on 10916 * platforms that reset TSC during suspend or hibernate actions, but 10917 * maintain synchronization. We must compensate. Fortunately, we can 10918 * detect that condition here, which happens early in CPU bringup, 10919 * before any KVM threads can be running. Unfortunately, we can't 10920 * bring the TSCs fully up to date with real time, as we aren't yet far 10921 * enough into CPU bringup that we know how much real time has actually 10922 * elapsed; our helper function, ktime_get_boottime_ns() will be using boot 10923 * variables that haven't been updated yet. 10924 * 10925 * So we simply find the maximum observed TSC above, then record the 10926 * adjustment to TSC in each VCPU. When the VCPU later gets loaded, 10927 * the adjustment will be applied. Note that we accumulate 10928 * adjustments, in case multiple suspend cycles happen before some VCPU 10929 * gets a chance to run again. In the event that no KVM threads get a 10930 * chance to run, we will miss the entire elapsed period, as we'll have 10931 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may 10932 * loose cycle time. This isn't too big a deal, since the loss will be 10933 * uniform across all VCPUs (not to mention the scenario is extremely 10934 * unlikely). It is possible that a second hibernate recovery happens 10935 * much faster than a first, causing the observed TSC here to be 10936 * smaller; this would require additional padding adjustment, which is 10937 * why we set last_host_tsc to the local tsc observed here. 10938 * 10939 * N.B. - this code below runs only on platforms with reliable TSC, 10940 * as that is the only way backwards_tsc is set above. Also note 10941 * that this runs for ALL vcpus, which is not a bug; all VCPUs should 10942 * have the same delta_cyc adjustment applied if backwards_tsc 10943 * is detected. Note further, this adjustment is only done once, 10944 * as we reset last_host_tsc on all VCPUs to stop this from being 10945 * called multiple times (one for each physical CPU bringup). 10946 * 10947 * Platforms with unreliable TSCs don't have to deal with this, they 10948 * will be compensated by the logic in vcpu_load, which sets the TSC to 10949 * catchup mode. This will catchup all VCPUs to real time, but cannot 10950 * guarantee that they stay in perfect synchronization. 10951 */ 10952 if (backwards_tsc) { 10953 u64 delta_cyc = max_tsc - local_tsc; 10954 list_for_each_entry(kvm, &vm_list, vm_list) { 10955 kvm->arch.backwards_tsc_observed = true; 10956 kvm_for_each_vcpu(i, vcpu, kvm) { 10957 vcpu->arch.tsc_offset_adjustment += delta_cyc; 10958 vcpu->arch.last_host_tsc = local_tsc; 10959 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu); 10960 } 10961 10962 /* 10963 * We have to disable TSC offset matching.. if you were 10964 * booting a VM while issuing an S4 host suspend.... 10965 * you may have some problem. Solving this issue is 10966 * left as an exercise to the reader. 10967 */ 10968 kvm->arch.last_tsc_nsec = 0; 10969 kvm->arch.last_tsc_write = 0; 10970 } 10971 10972 } 10973 return 0; 10974 } 10975 10976 void kvm_arch_hardware_disable(void) 10977 { 10978 static_call(kvm_x86_hardware_disable)(); 10979 drop_user_return_notifiers(); 10980 } 10981 10982 int kvm_arch_hardware_setup(void *opaque) 10983 { 10984 struct kvm_x86_init_ops *ops = opaque; 10985 int r; 10986 10987 rdmsrl_safe(MSR_EFER, &host_efer); 10988 if (WARN_ON_ONCE(boot_cpu_has(X86_FEATURE_NX) && 10989 !(host_efer & EFER_NX))) 10990 return -EIO; 10991 10992 if (boot_cpu_has(X86_FEATURE_XSAVES)) 10993 rdmsrl(MSR_IA32_XSS, host_xss); 10994 10995 r = ops->hardware_setup(); 10996 if (r != 0) 10997 return r; 10998 10999 memcpy(&kvm_x86_ops, ops->runtime_ops, sizeof(kvm_x86_ops)); 11000 kvm_ops_static_call_update(); 11001 11002 if (!kvm_cpu_cap_has(X86_FEATURE_XSAVES)) 11003 supported_xss = 0; 11004 11005 #define __kvm_cpu_cap_has(UNUSED_, f) kvm_cpu_cap_has(f) 11006 cr4_reserved_bits = __cr4_reserved_bits(__kvm_cpu_cap_has, UNUSED_); 11007 #undef __kvm_cpu_cap_has 11008 11009 if (kvm_has_tsc_control) { 11010 /* 11011 * Make sure the user can only configure tsc_khz values that 11012 * fit into a signed integer. 11013 * A min value is not calculated because it will always 11014 * be 1 on all machines. 11015 */ 11016 u64 max = min(0x7fffffffULL, 11017 __scale_tsc(kvm_max_tsc_scaling_ratio, tsc_khz)); 11018 kvm_max_guest_tsc_khz = max; 11019 11020 kvm_default_tsc_scaling_ratio = 1ULL << kvm_tsc_scaling_ratio_frac_bits; 11021 } 11022 11023 kvm_init_msr_list(); 11024 return 0; 11025 } 11026 11027 void kvm_arch_hardware_unsetup(void) 11028 { 11029 static_call(kvm_x86_hardware_unsetup)(); 11030 } 11031 11032 int kvm_arch_check_processor_compat(void *opaque) 11033 { 11034 struct cpuinfo_x86 *c = &cpu_data(smp_processor_id()); 11035 struct kvm_x86_init_ops *ops = opaque; 11036 11037 WARN_ON(!irqs_disabled()); 11038 11039 if (__cr4_reserved_bits(cpu_has, c) != 11040 __cr4_reserved_bits(cpu_has, &boot_cpu_data)) 11041 return -EIO; 11042 11043 return ops->check_processor_compatibility(); 11044 } 11045 11046 bool kvm_vcpu_is_reset_bsp(struct kvm_vcpu *vcpu) 11047 { 11048 return vcpu->kvm->arch.bsp_vcpu_id == vcpu->vcpu_id; 11049 } 11050 EXPORT_SYMBOL_GPL(kvm_vcpu_is_reset_bsp); 11051 11052 bool kvm_vcpu_is_bsp(struct kvm_vcpu *vcpu) 11053 { 11054 return (vcpu->arch.apic_base & MSR_IA32_APICBASE_BSP) != 0; 11055 } 11056 11057 __read_mostly DEFINE_STATIC_KEY_FALSE(kvm_has_noapic_vcpu); 11058 EXPORT_SYMBOL_GPL(kvm_has_noapic_vcpu); 11059 11060 void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu) 11061 { 11062 struct kvm_pmu *pmu = vcpu_to_pmu(vcpu); 11063 11064 vcpu->arch.l1tf_flush_l1d = true; 11065 if (pmu->version && unlikely(pmu->event_count)) { 11066 pmu->need_cleanup = true; 11067 kvm_make_request(KVM_REQ_PMU, vcpu); 11068 } 11069 static_call(kvm_x86_sched_in)(vcpu, cpu); 11070 } 11071 11072 void kvm_arch_free_vm(struct kvm *kvm) 11073 { 11074 kfree(to_kvm_hv(kvm)->hv_pa_pg); 11075 vfree(kvm); 11076 } 11077 11078 11079 int kvm_arch_init_vm(struct kvm *kvm, unsigned long type) 11080 { 11081 if (type) 11082 return -EINVAL; 11083 11084 INIT_HLIST_HEAD(&kvm->arch.mask_notifier_list); 11085 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages); 11086 INIT_LIST_HEAD(&kvm->arch.zapped_obsolete_pages); 11087 INIT_LIST_HEAD(&kvm->arch.lpage_disallowed_mmu_pages); 11088 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head); 11089 atomic_set(&kvm->arch.noncoherent_dma_count, 0); 11090 11091 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */ 11092 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap); 11093 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */ 11094 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID, 11095 &kvm->arch.irq_sources_bitmap); 11096 11097 raw_spin_lock_init(&kvm->arch.tsc_write_lock); 11098 mutex_init(&kvm->arch.apic_map_lock); 11099 spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock); 11100 11101 kvm->arch.kvmclock_offset = -get_kvmclock_base_ns(); 11102 pvclock_update_vm_gtod_copy(kvm); 11103 11104 kvm->arch.guest_can_read_msr_platform_info = true; 11105 11106 #if IS_ENABLED(CONFIG_HYPERV) 11107 spin_lock_init(&kvm->arch.hv_root_tdp_lock); 11108 kvm->arch.hv_root_tdp = INVALID_PAGE; 11109 #endif 11110 11111 INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn); 11112 INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn); 11113 11114 kvm_apicv_init(kvm); 11115 kvm_hv_init_vm(kvm); 11116 kvm_page_track_init(kvm); 11117 kvm_mmu_init_vm(kvm); 11118 11119 return static_call(kvm_x86_vm_init)(kvm); 11120 } 11121 11122 int kvm_arch_post_init_vm(struct kvm *kvm) 11123 { 11124 return kvm_mmu_post_init_vm(kvm); 11125 } 11126 11127 static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu) 11128 { 11129 vcpu_load(vcpu); 11130 kvm_mmu_unload(vcpu); 11131 vcpu_put(vcpu); 11132 } 11133 11134 static void kvm_free_vcpus(struct kvm *kvm) 11135 { 11136 unsigned int i; 11137 struct kvm_vcpu *vcpu; 11138 11139 /* 11140 * Unpin any mmu pages first. 11141 */ 11142 kvm_for_each_vcpu(i, vcpu, kvm) { 11143 kvm_clear_async_pf_completion_queue(vcpu); 11144 kvm_unload_vcpu_mmu(vcpu); 11145 } 11146 kvm_for_each_vcpu(i, vcpu, kvm) 11147 kvm_vcpu_destroy(vcpu); 11148 11149 mutex_lock(&kvm->lock); 11150 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++) 11151 kvm->vcpus[i] = NULL; 11152 11153 atomic_set(&kvm->online_vcpus, 0); 11154 mutex_unlock(&kvm->lock); 11155 } 11156 11157 void kvm_arch_sync_events(struct kvm *kvm) 11158 { 11159 cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work); 11160 cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work); 11161 kvm_free_pit(kvm); 11162 } 11163 11164 #define ERR_PTR_USR(e) ((void __user *)ERR_PTR(e)) 11165 11166 /** 11167 * __x86_set_memory_region: Setup KVM internal memory slot 11168 * 11169 * @kvm: the kvm pointer to the VM. 11170 * @id: the slot ID to setup. 11171 * @gpa: the GPA to install the slot (unused when @size == 0). 11172 * @size: the size of the slot. Set to zero to uninstall a slot. 11173 * 11174 * This function helps to setup a KVM internal memory slot. Specify 11175 * @size > 0 to install a new slot, while @size == 0 to uninstall a 11176 * slot. The return code can be one of the following: 11177 * 11178 * HVA: on success (uninstall will return a bogus HVA) 11179 * -errno: on error 11180 * 11181 * The caller should always use IS_ERR() to check the return value 11182 * before use. Note, the KVM internal memory slots are guaranteed to 11183 * remain valid and unchanged until the VM is destroyed, i.e., the 11184 * GPA->HVA translation will not change. However, the HVA is a user 11185 * address, i.e. its accessibility is not guaranteed, and must be 11186 * accessed via __copy_{to,from}_user(). 11187 */ 11188 void __user * __x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, 11189 u32 size) 11190 { 11191 int i, r; 11192 unsigned long hva, old_npages; 11193 struct kvm_memslots *slots = kvm_memslots(kvm); 11194 struct kvm_memory_slot *slot; 11195 11196 /* Called with kvm->slots_lock held. */ 11197 if (WARN_ON(id >= KVM_MEM_SLOTS_NUM)) 11198 return ERR_PTR_USR(-EINVAL); 11199 11200 slot = id_to_memslot(slots, id); 11201 if (size) { 11202 if (slot && slot->npages) 11203 return ERR_PTR_USR(-EEXIST); 11204 11205 /* 11206 * MAP_SHARED to prevent internal slot pages from being moved 11207 * by fork()/COW. 11208 */ 11209 hva = vm_mmap(NULL, 0, size, PROT_READ | PROT_WRITE, 11210 MAP_SHARED | MAP_ANONYMOUS, 0); 11211 if (IS_ERR((void *)hva)) 11212 return (void __user *)hva; 11213 } else { 11214 if (!slot || !slot->npages) 11215 return NULL; 11216 11217 old_npages = slot->npages; 11218 hva = slot->userspace_addr; 11219 } 11220 11221 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) { 11222 struct kvm_userspace_memory_region m; 11223 11224 m.slot = id | (i << 16); 11225 m.flags = 0; 11226 m.guest_phys_addr = gpa; 11227 m.userspace_addr = hva; 11228 m.memory_size = size; 11229 r = __kvm_set_memory_region(kvm, &m); 11230 if (r < 0) 11231 return ERR_PTR_USR(r); 11232 } 11233 11234 if (!size) 11235 vm_munmap(hva, old_npages * PAGE_SIZE); 11236 11237 return (void __user *)hva; 11238 } 11239 EXPORT_SYMBOL_GPL(__x86_set_memory_region); 11240 11241 void kvm_arch_pre_destroy_vm(struct kvm *kvm) 11242 { 11243 kvm_mmu_pre_destroy_vm(kvm); 11244 } 11245 11246 void kvm_arch_destroy_vm(struct kvm *kvm) 11247 { 11248 if (current->mm == kvm->mm) { 11249 /* 11250 * Free memory regions allocated on behalf of userspace, 11251 * unless the the memory map has changed due to process exit 11252 * or fd copying. 11253 */ 11254 mutex_lock(&kvm->slots_lock); 11255 __x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT, 11256 0, 0); 11257 __x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT, 11258 0, 0); 11259 __x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, 0, 0); 11260 mutex_unlock(&kvm->slots_lock); 11261 } 11262 static_call_cond(kvm_x86_vm_destroy)(kvm); 11263 kvm_free_msr_filter(srcu_dereference_check(kvm->arch.msr_filter, &kvm->srcu, 1)); 11264 kvm_pic_destroy(kvm); 11265 kvm_ioapic_destroy(kvm); 11266 kvm_free_vcpus(kvm); 11267 kvfree(rcu_dereference_check(kvm->arch.apic_map, 1)); 11268 kfree(srcu_dereference_check(kvm->arch.pmu_event_filter, &kvm->srcu, 1)); 11269 kvm_mmu_uninit_vm(kvm); 11270 kvm_page_track_cleanup(kvm); 11271 kvm_xen_destroy_vm(kvm); 11272 kvm_hv_destroy_vm(kvm); 11273 } 11274 11275 static void memslot_rmap_free(struct kvm_memory_slot *slot) 11276 { 11277 int i; 11278 11279 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) { 11280 kvfree(slot->arch.rmap[i]); 11281 slot->arch.rmap[i] = NULL; 11282 } 11283 } 11284 11285 void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *slot) 11286 { 11287 int i; 11288 11289 memslot_rmap_free(slot); 11290 11291 for (i = 1; i < KVM_NR_PAGE_SIZES; ++i) { 11292 kvfree(slot->arch.lpage_info[i - 1]); 11293 slot->arch.lpage_info[i - 1] = NULL; 11294 } 11295 11296 kvm_page_track_free_memslot(slot); 11297 } 11298 11299 static int memslot_rmap_alloc(struct kvm_memory_slot *slot, 11300 unsigned long npages) 11301 { 11302 const int sz = sizeof(*slot->arch.rmap[0]); 11303 int i; 11304 11305 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) { 11306 int level = i + 1; 11307 int lpages = gfn_to_index(slot->base_gfn + npages - 1, 11308 slot->base_gfn, level) + 1; 11309 11310 WARN_ON(slot->arch.rmap[i]); 11311 11312 slot->arch.rmap[i] = kvcalloc(lpages, sz, GFP_KERNEL_ACCOUNT); 11313 if (!slot->arch.rmap[i]) { 11314 memslot_rmap_free(slot); 11315 return -ENOMEM; 11316 } 11317 } 11318 11319 return 0; 11320 } 11321 11322 int alloc_all_memslots_rmaps(struct kvm *kvm) 11323 { 11324 struct kvm_memslots *slots; 11325 struct kvm_memory_slot *slot; 11326 int r, i; 11327 11328 /* 11329 * Check if memslots alreday have rmaps early before acquiring 11330 * the slots_arch_lock below. 11331 */ 11332 if (kvm_memslots_have_rmaps(kvm)) 11333 return 0; 11334 11335 mutex_lock(&kvm->slots_arch_lock); 11336 11337 /* 11338 * Read memslots_have_rmaps again, under the slots arch lock, 11339 * before allocating the rmaps 11340 */ 11341 if (kvm_memslots_have_rmaps(kvm)) { 11342 mutex_unlock(&kvm->slots_arch_lock); 11343 return 0; 11344 } 11345 11346 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) { 11347 slots = __kvm_memslots(kvm, i); 11348 kvm_for_each_memslot(slot, slots) { 11349 r = memslot_rmap_alloc(slot, slot->npages); 11350 if (r) { 11351 mutex_unlock(&kvm->slots_arch_lock); 11352 return r; 11353 } 11354 } 11355 } 11356 11357 /* 11358 * Ensure that memslots_have_rmaps becomes true strictly after 11359 * all the rmap pointers are set. 11360 */ 11361 smp_store_release(&kvm->arch.memslots_have_rmaps, true); 11362 mutex_unlock(&kvm->slots_arch_lock); 11363 return 0; 11364 } 11365 11366 static int kvm_alloc_memslot_metadata(struct kvm *kvm, 11367 struct kvm_memory_slot *slot, 11368 unsigned long npages) 11369 { 11370 int i, r; 11371 11372 /* 11373 * Clear out the previous array pointers for the KVM_MR_MOVE case. The 11374 * old arrays will be freed by __kvm_set_memory_region() if installing 11375 * the new memslot is successful. 11376 */ 11377 memset(&slot->arch, 0, sizeof(slot->arch)); 11378 11379 if (kvm_memslots_have_rmaps(kvm)) { 11380 r = memslot_rmap_alloc(slot, npages); 11381 if (r) 11382 return r; 11383 } 11384 11385 for (i = 1; i < KVM_NR_PAGE_SIZES; ++i) { 11386 struct kvm_lpage_info *linfo; 11387 unsigned long ugfn; 11388 int lpages; 11389 int level = i + 1; 11390 11391 lpages = gfn_to_index(slot->base_gfn + npages - 1, 11392 slot->base_gfn, level) + 1; 11393 11394 linfo = kvcalloc(lpages, sizeof(*linfo), GFP_KERNEL_ACCOUNT); 11395 if (!linfo) 11396 goto out_free; 11397 11398 slot->arch.lpage_info[i - 1] = linfo; 11399 11400 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1)) 11401 linfo[0].disallow_lpage = 1; 11402 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1)) 11403 linfo[lpages - 1].disallow_lpage = 1; 11404 ugfn = slot->userspace_addr >> PAGE_SHIFT; 11405 /* 11406 * If the gfn and userspace address are not aligned wrt each 11407 * other, disable large page support for this slot. 11408 */ 11409 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1)) { 11410 unsigned long j; 11411 11412 for (j = 0; j < lpages; ++j) 11413 linfo[j].disallow_lpage = 1; 11414 } 11415 } 11416 11417 if (kvm_page_track_create_memslot(slot, npages)) 11418 goto out_free; 11419 11420 return 0; 11421 11422 out_free: 11423 memslot_rmap_free(slot); 11424 11425 for (i = 1; i < KVM_NR_PAGE_SIZES; ++i) { 11426 kvfree(slot->arch.lpage_info[i - 1]); 11427 slot->arch.lpage_info[i - 1] = NULL; 11428 } 11429 return -ENOMEM; 11430 } 11431 11432 void kvm_arch_memslots_updated(struct kvm *kvm, u64 gen) 11433 { 11434 struct kvm_vcpu *vcpu; 11435 int i; 11436 11437 /* 11438 * memslots->generation has been incremented. 11439 * mmio generation may have reached its maximum value. 11440 */ 11441 kvm_mmu_invalidate_mmio_sptes(kvm, gen); 11442 11443 /* Force re-initialization of steal_time cache */ 11444 kvm_for_each_vcpu(i, vcpu, kvm) 11445 kvm_vcpu_kick(vcpu); 11446 } 11447 11448 int kvm_arch_prepare_memory_region(struct kvm *kvm, 11449 struct kvm_memory_slot *memslot, 11450 const struct kvm_userspace_memory_region *mem, 11451 enum kvm_mr_change change) 11452 { 11453 if (change == KVM_MR_CREATE || change == KVM_MR_MOVE) 11454 return kvm_alloc_memslot_metadata(kvm, memslot, 11455 mem->memory_size >> PAGE_SHIFT); 11456 return 0; 11457 } 11458 11459 11460 static void kvm_mmu_update_cpu_dirty_logging(struct kvm *kvm, bool enable) 11461 { 11462 struct kvm_arch *ka = &kvm->arch; 11463 11464 if (!kvm_x86_ops.cpu_dirty_log_size) 11465 return; 11466 11467 if ((enable && ++ka->cpu_dirty_logging_count == 1) || 11468 (!enable && --ka->cpu_dirty_logging_count == 0)) 11469 kvm_make_all_cpus_request(kvm, KVM_REQ_UPDATE_CPU_DIRTY_LOGGING); 11470 11471 WARN_ON_ONCE(ka->cpu_dirty_logging_count < 0); 11472 } 11473 11474 static void kvm_mmu_slot_apply_flags(struct kvm *kvm, 11475 struct kvm_memory_slot *old, 11476 struct kvm_memory_slot *new, 11477 enum kvm_mr_change change) 11478 { 11479 bool log_dirty_pages = new->flags & KVM_MEM_LOG_DIRTY_PAGES; 11480 11481 /* 11482 * Update CPU dirty logging if dirty logging is being toggled. This 11483 * applies to all operations. 11484 */ 11485 if ((old->flags ^ new->flags) & KVM_MEM_LOG_DIRTY_PAGES) 11486 kvm_mmu_update_cpu_dirty_logging(kvm, log_dirty_pages); 11487 11488 /* 11489 * Nothing more to do for RO slots (which can't be dirtied and can't be 11490 * made writable) or CREATE/MOVE/DELETE of a slot. 11491 * 11492 * For a memslot with dirty logging disabled: 11493 * CREATE: No dirty mappings will already exist. 11494 * MOVE/DELETE: The old mappings will already have been cleaned up by 11495 * kvm_arch_flush_shadow_memslot() 11496 * 11497 * For a memslot with dirty logging enabled: 11498 * CREATE: No shadow pages exist, thus nothing to write-protect 11499 * and no dirty bits to clear. 11500 * MOVE/DELETE: The old mappings will already have been cleaned up by 11501 * kvm_arch_flush_shadow_memslot(). 11502 */ 11503 if ((change != KVM_MR_FLAGS_ONLY) || (new->flags & KVM_MEM_READONLY)) 11504 return; 11505 11506 /* 11507 * READONLY and non-flags changes were filtered out above, and the only 11508 * other flag is LOG_DIRTY_PAGES, i.e. something is wrong if dirty 11509 * logging isn't being toggled on or off. 11510 */ 11511 if (WARN_ON_ONCE(!((old->flags ^ new->flags) & KVM_MEM_LOG_DIRTY_PAGES))) 11512 return; 11513 11514 if (!log_dirty_pages) { 11515 /* 11516 * Dirty logging tracks sptes in 4k granularity, meaning that 11517 * large sptes have to be split. If live migration succeeds, 11518 * the guest in the source machine will be destroyed and large 11519 * sptes will be created in the destination. However, if the 11520 * guest continues to run in the source machine (for example if 11521 * live migration fails), small sptes will remain around and 11522 * cause bad performance. 11523 * 11524 * Scan sptes if dirty logging has been stopped, dropping those 11525 * which can be collapsed into a single large-page spte. Later 11526 * page faults will create the large-page sptes. 11527 */ 11528 kvm_mmu_zap_collapsible_sptes(kvm, new); 11529 } else { 11530 /* 11531 * Initially-all-set does not require write protecting any page, 11532 * because they're all assumed to be dirty. 11533 */ 11534 if (kvm_dirty_log_manual_protect_and_init_set(kvm)) 11535 return; 11536 11537 if (kvm_x86_ops.cpu_dirty_log_size) { 11538 kvm_mmu_slot_leaf_clear_dirty(kvm, new); 11539 kvm_mmu_slot_remove_write_access(kvm, new, PG_LEVEL_2M); 11540 } else { 11541 kvm_mmu_slot_remove_write_access(kvm, new, PG_LEVEL_4K); 11542 } 11543 } 11544 } 11545 11546 void kvm_arch_commit_memory_region(struct kvm *kvm, 11547 const struct kvm_userspace_memory_region *mem, 11548 struct kvm_memory_slot *old, 11549 const struct kvm_memory_slot *new, 11550 enum kvm_mr_change change) 11551 { 11552 if (!kvm->arch.n_requested_mmu_pages) 11553 kvm_mmu_change_mmu_pages(kvm, 11554 kvm_mmu_calculate_default_mmu_pages(kvm)); 11555 11556 /* 11557 * FIXME: const-ify all uses of struct kvm_memory_slot. 11558 */ 11559 kvm_mmu_slot_apply_flags(kvm, old, (struct kvm_memory_slot *) new, change); 11560 11561 /* Free the arrays associated with the old memslot. */ 11562 if (change == KVM_MR_MOVE) 11563 kvm_arch_free_memslot(kvm, old); 11564 } 11565 11566 void kvm_arch_flush_shadow_all(struct kvm *kvm) 11567 { 11568 kvm_mmu_zap_all(kvm); 11569 } 11570 11571 void kvm_arch_flush_shadow_memslot(struct kvm *kvm, 11572 struct kvm_memory_slot *slot) 11573 { 11574 kvm_page_track_flush_slot(kvm, slot); 11575 } 11576 11577 static inline bool kvm_guest_apic_has_interrupt(struct kvm_vcpu *vcpu) 11578 { 11579 return (is_guest_mode(vcpu) && 11580 kvm_x86_ops.guest_apic_has_interrupt && 11581 static_call(kvm_x86_guest_apic_has_interrupt)(vcpu)); 11582 } 11583 11584 static inline bool kvm_vcpu_has_events(struct kvm_vcpu *vcpu) 11585 { 11586 if (!list_empty_careful(&vcpu->async_pf.done)) 11587 return true; 11588 11589 if (kvm_apic_has_events(vcpu)) 11590 return true; 11591 11592 if (vcpu->arch.pv.pv_unhalted) 11593 return true; 11594 11595 if (vcpu->arch.exception.pending) 11596 return true; 11597 11598 if (kvm_test_request(KVM_REQ_NMI, vcpu) || 11599 (vcpu->arch.nmi_pending && 11600 static_call(kvm_x86_nmi_allowed)(vcpu, false))) 11601 return true; 11602 11603 if (kvm_test_request(KVM_REQ_SMI, vcpu) || 11604 (vcpu->arch.smi_pending && 11605 static_call(kvm_x86_smi_allowed)(vcpu, false))) 11606 return true; 11607 11608 if (kvm_arch_interrupt_allowed(vcpu) && 11609 (kvm_cpu_has_interrupt(vcpu) || 11610 kvm_guest_apic_has_interrupt(vcpu))) 11611 return true; 11612 11613 if (kvm_hv_has_stimer_pending(vcpu)) 11614 return true; 11615 11616 if (is_guest_mode(vcpu) && 11617 kvm_x86_ops.nested_ops->hv_timer_pending && 11618 kvm_x86_ops.nested_ops->hv_timer_pending(vcpu)) 11619 return true; 11620 11621 return false; 11622 } 11623 11624 int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu) 11625 { 11626 return kvm_vcpu_running(vcpu) || kvm_vcpu_has_events(vcpu); 11627 } 11628 11629 bool kvm_arch_dy_has_pending_interrupt(struct kvm_vcpu *vcpu) 11630 { 11631 if (vcpu->arch.apicv_active && static_call(kvm_x86_dy_apicv_has_pending_interrupt)(vcpu)) 11632 return true; 11633 11634 return false; 11635 } 11636 11637 bool kvm_arch_dy_runnable(struct kvm_vcpu *vcpu) 11638 { 11639 if (READ_ONCE(vcpu->arch.pv.pv_unhalted)) 11640 return true; 11641 11642 if (kvm_test_request(KVM_REQ_NMI, vcpu) || 11643 kvm_test_request(KVM_REQ_SMI, vcpu) || 11644 kvm_test_request(KVM_REQ_EVENT, vcpu)) 11645 return true; 11646 11647 return kvm_arch_dy_has_pending_interrupt(vcpu); 11648 } 11649 11650 bool kvm_arch_vcpu_in_kernel(struct kvm_vcpu *vcpu) 11651 { 11652 if (vcpu->arch.guest_state_protected) 11653 return true; 11654 11655 return vcpu->arch.preempted_in_kernel; 11656 } 11657 11658 int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu) 11659 { 11660 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE; 11661 } 11662 11663 int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu) 11664 { 11665 return static_call(kvm_x86_interrupt_allowed)(vcpu, false); 11666 } 11667 11668 unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu) 11669 { 11670 /* Can't read the RIP when guest state is protected, just return 0 */ 11671 if (vcpu->arch.guest_state_protected) 11672 return 0; 11673 11674 if (is_64_bit_mode(vcpu)) 11675 return kvm_rip_read(vcpu); 11676 return (u32)(get_segment_base(vcpu, VCPU_SREG_CS) + 11677 kvm_rip_read(vcpu)); 11678 } 11679 EXPORT_SYMBOL_GPL(kvm_get_linear_rip); 11680 11681 bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip) 11682 { 11683 return kvm_get_linear_rip(vcpu) == linear_rip; 11684 } 11685 EXPORT_SYMBOL_GPL(kvm_is_linear_rip); 11686 11687 unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu) 11688 { 11689 unsigned long rflags; 11690 11691 rflags = static_call(kvm_x86_get_rflags)(vcpu); 11692 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) 11693 rflags &= ~X86_EFLAGS_TF; 11694 return rflags; 11695 } 11696 EXPORT_SYMBOL_GPL(kvm_get_rflags); 11697 11698 static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags) 11699 { 11700 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP && 11701 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip)) 11702 rflags |= X86_EFLAGS_TF; 11703 static_call(kvm_x86_set_rflags)(vcpu, rflags); 11704 } 11705 11706 void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags) 11707 { 11708 __kvm_set_rflags(vcpu, rflags); 11709 kvm_make_request(KVM_REQ_EVENT, vcpu); 11710 } 11711 EXPORT_SYMBOL_GPL(kvm_set_rflags); 11712 11713 void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work) 11714 { 11715 int r; 11716 11717 if ((vcpu->arch.mmu->direct_map != work->arch.direct_map) || 11718 work->wakeup_all) 11719 return; 11720 11721 r = kvm_mmu_reload(vcpu); 11722 if (unlikely(r)) 11723 return; 11724 11725 if (!vcpu->arch.mmu->direct_map && 11726 work->arch.cr3 != vcpu->arch.mmu->get_guest_pgd(vcpu)) 11727 return; 11728 11729 kvm_mmu_do_page_fault(vcpu, work->cr2_or_gpa, 0, true); 11730 } 11731 11732 static inline u32 kvm_async_pf_hash_fn(gfn_t gfn) 11733 { 11734 BUILD_BUG_ON(!is_power_of_2(ASYNC_PF_PER_VCPU)); 11735 11736 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU)); 11737 } 11738 11739 static inline u32 kvm_async_pf_next_probe(u32 key) 11740 { 11741 return (key + 1) & (ASYNC_PF_PER_VCPU - 1); 11742 } 11743 11744 static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn) 11745 { 11746 u32 key = kvm_async_pf_hash_fn(gfn); 11747 11748 while (vcpu->arch.apf.gfns[key] != ~0) 11749 key = kvm_async_pf_next_probe(key); 11750 11751 vcpu->arch.apf.gfns[key] = gfn; 11752 } 11753 11754 static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn) 11755 { 11756 int i; 11757 u32 key = kvm_async_pf_hash_fn(gfn); 11758 11759 for (i = 0; i < ASYNC_PF_PER_VCPU && 11760 (vcpu->arch.apf.gfns[key] != gfn && 11761 vcpu->arch.apf.gfns[key] != ~0); i++) 11762 key = kvm_async_pf_next_probe(key); 11763 11764 return key; 11765 } 11766 11767 bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn) 11768 { 11769 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn; 11770 } 11771 11772 static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn) 11773 { 11774 u32 i, j, k; 11775 11776 i = j = kvm_async_pf_gfn_slot(vcpu, gfn); 11777 11778 if (WARN_ON_ONCE(vcpu->arch.apf.gfns[i] != gfn)) 11779 return; 11780 11781 while (true) { 11782 vcpu->arch.apf.gfns[i] = ~0; 11783 do { 11784 j = kvm_async_pf_next_probe(j); 11785 if (vcpu->arch.apf.gfns[j] == ~0) 11786 return; 11787 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]); 11788 /* 11789 * k lies cyclically in ]i,j] 11790 * | i.k.j | 11791 * |....j i.k.| or |.k..j i...| 11792 */ 11793 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j)); 11794 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j]; 11795 i = j; 11796 } 11797 } 11798 11799 static inline int apf_put_user_notpresent(struct kvm_vcpu *vcpu) 11800 { 11801 u32 reason = KVM_PV_REASON_PAGE_NOT_PRESENT; 11802 11803 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &reason, 11804 sizeof(reason)); 11805 } 11806 11807 static inline int apf_put_user_ready(struct kvm_vcpu *vcpu, u32 token) 11808 { 11809 unsigned int offset = offsetof(struct kvm_vcpu_pv_apf_data, token); 11810 11811 return kvm_write_guest_offset_cached(vcpu->kvm, &vcpu->arch.apf.data, 11812 &token, offset, sizeof(token)); 11813 } 11814 11815 static inline bool apf_pageready_slot_free(struct kvm_vcpu *vcpu) 11816 { 11817 unsigned int offset = offsetof(struct kvm_vcpu_pv_apf_data, token); 11818 u32 val; 11819 11820 if (kvm_read_guest_offset_cached(vcpu->kvm, &vcpu->arch.apf.data, 11821 &val, offset, sizeof(val))) 11822 return false; 11823 11824 return !val; 11825 } 11826 11827 static bool kvm_can_deliver_async_pf(struct kvm_vcpu *vcpu) 11828 { 11829 if (!vcpu->arch.apf.delivery_as_pf_vmexit && is_guest_mode(vcpu)) 11830 return false; 11831 11832 if (!kvm_pv_async_pf_enabled(vcpu) || 11833 (vcpu->arch.apf.send_user_only && static_call(kvm_x86_get_cpl)(vcpu) == 0)) 11834 return false; 11835 11836 return true; 11837 } 11838 11839 bool kvm_can_do_async_pf(struct kvm_vcpu *vcpu) 11840 { 11841 if (unlikely(!lapic_in_kernel(vcpu) || 11842 kvm_event_needs_reinjection(vcpu) || 11843 vcpu->arch.exception.pending)) 11844 return false; 11845 11846 if (kvm_hlt_in_guest(vcpu->kvm) && !kvm_can_deliver_async_pf(vcpu)) 11847 return false; 11848 11849 /* 11850 * If interrupts are off we cannot even use an artificial 11851 * halt state. 11852 */ 11853 return kvm_arch_interrupt_allowed(vcpu); 11854 } 11855 11856 bool kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu, 11857 struct kvm_async_pf *work) 11858 { 11859 struct x86_exception fault; 11860 11861 trace_kvm_async_pf_not_present(work->arch.token, work->cr2_or_gpa); 11862 kvm_add_async_pf_gfn(vcpu, work->arch.gfn); 11863 11864 if (kvm_can_deliver_async_pf(vcpu) && 11865 !apf_put_user_notpresent(vcpu)) { 11866 fault.vector = PF_VECTOR; 11867 fault.error_code_valid = true; 11868 fault.error_code = 0; 11869 fault.nested_page_fault = false; 11870 fault.address = work->arch.token; 11871 fault.async_page_fault = true; 11872 kvm_inject_page_fault(vcpu, &fault); 11873 return true; 11874 } else { 11875 /* 11876 * It is not possible to deliver a paravirtualized asynchronous 11877 * page fault, but putting the guest in an artificial halt state 11878 * can be beneficial nevertheless: if an interrupt arrives, we 11879 * can deliver it timely and perhaps the guest will schedule 11880 * another process. When the instruction that triggered a page 11881 * fault is retried, hopefully the page will be ready in the host. 11882 */ 11883 kvm_make_request(KVM_REQ_APF_HALT, vcpu); 11884 return false; 11885 } 11886 } 11887 11888 void kvm_arch_async_page_present(struct kvm_vcpu *vcpu, 11889 struct kvm_async_pf *work) 11890 { 11891 struct kvm_lapic_irq irq = { 11892 .delivery_mode = APIC_DM_FIXED, 11893 .vector = vcpu->arch.apf.vec 11894 }; 11895 11896 if (work->wakeup_all) 11897 work->arch.token = ~0; /* broadcast wakeup */ 11898 else 11899 kvm_del_async_pf_gfn(vcpu, work->arch.gfn); 11900 trace_kvm_async_pf_ready(work->arch.token, work->cr2_or_gpa); 11901 11902 if ((work->wakeup_all || work->notpresent_injected) && 11903 kvm_pv_async_pf_enabled(vcpu) && 11904 !apf_put_user_ready(vcpu, work->arch.token)) { 11905 vcpu->arch.apf.pageready_pending = true; 11906 kvm_apic_set_irq(vcpu, &irq, NULL); 11907 } 11908 11909 vcpu->arch.apf.halted = false; 11910 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; 11911 } 11912 11913 void kvm_arch_async_page_present_queued(struct kvm_vcpu *vcpu) 11914 { 11915 kvm_make_request(KVM_REQ_APF_READY, vcpu); 11916 if (!vcpu->arch.apf.pageready_pending) 11917 kvm_vcpu_kick(vcpu); 11918 } 11919 11920 bool kvm_arch_can_dequeue_async_page_present(struct kvm_vcpu *vcpu) 11921 { 11922 if (!kvm_pv_async_pf_enabled(vcpu)) 11923 return true; 11924 else 11925 return kvm_lapic_enabled(vcpu) && apf_pageready_slot_free(vcpu); 11926 } 11927 11928 void kvm_arch_start_assignment(struct kvm *kvm) 11929 { 11930 if (atomic_inc_return(&kvm->arch.assigned_device_count) == 1) 11931 static_call_cond(kvm_x86_start_assignment)(kvm); 11932 } 11933 EXPORT_SYMBOL_GPL(kvm_arch_start_assignment); 11934 11935 void kvm_arch_end_assignment(struct kvm *kvm) 11936 { 11937 atomic_dec(&kvm->arch.assigned_device_count); 11938 } 11939 EXPORT_SYMBOL_GPL(kvm_arch_end_assignment); 11940 11941 bool kvm_arch_has_assigned_device(struct kvm *kvm) 11942 { 11943 return atomic_read(&kvm->arch.assigned_device_count); 11944 } 11945 EXPORT_SYMBOL_GPL(kvm_arch_has_assigned_device); 11946 11947 void kvm_arch_register_noncoherent_dma(struct kvm *kvm) 11948 { 11949 atomic_inc(&kvm->arch.noncoherent_dma_count); 11950 } 11951 EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma); 11952 11953 void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm) 11954 { 11955 atomic_dec(&kvm->arch.noncoherent_dma_count); 11956 } 11957 EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma); 11958 11959 bool kvm_arch_has_noncoherent_dma(struct kvm *kvm) 11960 { 11961 return atomic_read(&kvm->arch.noncoherent_dma_count); 11962 } 11963 EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma); 11964 11965 bool kvm_arch_has_irq_bypass(void) 11966 { 11967 return true; 11968 } 11969 11970 int kvm_arch_irq_bypass_add_producer(struct irq_bypass_consumer *cons, 11971 struct irq_bypass_producer *prod) 11972 { 11973 struct kvm_kernel_irqfd *irqfd = 11974 container_of(cons, struct kvm_kernel_irqfd, consumer); 11975 int ret; 11976 11977 irqfd->producer = prod; 11978 kvm_arch_start_assignment(irqfd->kvm); 11979 ret = static_call(kvm_x86_update_pi_irte)(irqfd->kvm, 11980 prod->irq, irqfd->gsi, 1); 11981 11982 if (ret) 11983 kvm_arch_end_assignment(irqfd->kvm); 11984 11985 return ret; 11986 } 11987 11988 void kvm_arch_irq_bypass_del_producer(struct irq_bypass_consumer *cons, 11989 struct irq_bypass_producer *prod) 11990 { 11991 int ret; 11992 struct kvm_kernel_irqfd *irqfd = 11993 container_of(cons, struct kvm_kernel_irqfd, consumer); 11994 11995 WARN_ON(irqfd->producer != prod); 11996 irqfd->producer = NULL; 11997 11998 /* 11999 * When producer of consumer is unregistered, we change back to 12000 * remapped mode, so we can re-use the current implementation 12001 * when the irq is masked/disabled or the consumer side (KVM 12002 * int this case doesn't want to receive the interrupts. 12003 */ 12004 ret = static_call(kvm_x86_update_pi_irte)(irqfd->kvm, prod->irq, irqfd->gsi, 0); 12005 if (ret) 12006 printk(KERN_INFO "irq bypass consumer (token %p) unregistration" 12007 " fails: %d\n", irqfd->consumer.token, ret); 12008 12009 kvm_arch_end_assignment(irqfd->kvm); 12010 } 12011 12012 int kvm_arch_update_irqfd_routing(struct kvm *kvm, unsigned int host_irq, 12013 uint32_t guest_irq, bool set) 12014 { 12015 return static_call(kvm_x86_update_pi_irte)(kvm, host_irq, guest_irq, set); 12016 } 12017 12018 bool kvm_vector_hashing_enabled(void) 12019 { 12020 return vector_hashing; 12021 } 12022 12023 bool kvm_arch_no_poll(struct kvm_vcpu *vcpu) 12024 { 12025 return (vcpu->arch.msr_kvm_poll_control & 1) == 0; 12026 } 12027 EXPORT_SYMBOL_GPL(kvm_arch_no_poll); 12028 12029 12030 int kvm_spec_ctrl_test_value(u64 value) 12031 { 12032 /* 12033 * test that setting IA32_SPEC_CTRL to given value 12034 * is allowed by the host processor 12035 */ 12036 12037 u64 saved_value; 12038 unsigned long flags; 12039 int ret = 0; 12040 12041 local_irq_save(flags); 12042 12043 if (rdmsrl_safe(MSR_IA32_SPEC_CTRL, &saved_value)) 12044 ret = 1; 12045 else if (wrmsrl_safe(MSR_IA32_SPEC_CTRL, value)) 12046 ret = 1; 12047 else 12048 wrmsrl(MSR_IA32_SPEC_CTRL, saved_value); 12049 12050 local_irq_restore(flags); 12051 12052 return ret; 12053 } 12054 EXPORT_SYMBOL_GPL(kvm_spec_ctrl_test_value); 12055 12056 void kvm_fixup_and_inject_pf_error(struct kvm_vcpu *vcpu, gva_t gva, u16 error_code) 12057 { 12058 struct x86_exception fault; 12059 u32 access = error_code & 12060 (PFERR_WRITE_MASK | PFERR_FETCH_MASK | PFERR_USER_MASK); 12061 12062 if (!(error_code & PFERR_PRESENT_MASK) || 12063 vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, &fault) != UNMAPPED_GVA) { 12064 /* 12065 * If vcpu->arch.walk_mmu->gva_to_gpa succeeded, the page 12066 * tables probably do not match the TLB. Just proceed 12067 * with the error code that the processor gave. 12068 */ 12069 fault.vector = PF_VECTOR; 12070 fault.error_code_valid = true; 12071 fault.error_code = error_code; 12072 fault.nested_page_fault = false; 12073 fault.address = gva; 12074 } 12075 vcpu->arch.walk_mmu->inject_page_fault(vcpu, &fault); 12076 } 12077 EXPORT_SYMBOL_GPL(kvm_fixup_and_inject_pf_error); 12078 12079 /* 12080 * Handles kvm_read/write_guest_virt*() result and either injects #PF or returns 12081 * KVM_EXIT_INTERNAL_ERROR for cases not currently handled by KVM. Return value 12082 * indicates whether exit to userspace is needed. 12083 */ 12084 int kvm_handle_memory_failure(struct kvm_vcpu *vcpu, int r, 12085 struct x86_exception *e) 12086 { 12087 if (r == X86EMUL_PROPAGATE_FAULT) { 12088 kvm_inject_emulated_page_fault(vcpu, e); 12089 return 1; 12090 } 12091 12092 /* 12093 * In case kvm_read/write_guest_virt*() failed with X86EMUL_IO_NEEDED 12094 * while handling a VMX instruction KVM could've handled the request 12095 * correctly by exiting to userspace and performing I/O but there 12096 * doesn't seem to be a real use-case behind such requests, just return 12097 * KVM_EXIT_INTERNAL_ERROR for now. 12098 */ 12099 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR; 12100 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION; 12101 vcpu->run->internal.ndata = 0; 12102 12103 return 0; 12104 } 12105 EXPORT_SYMBOL_GPL(kvm_handle_memory_failure); 12106 12107 int kvm_handle_invpcid(struct kvm_vcpu *vcpu, unsigned long type, gva_t gva) 12108 { 12109 bool pcid_enabled; 12110 struct x86_exception e; 12111 struct { 12112 u64 pcid; 12113 u64 gla; 12114 } operand; 12115 int r; 12116 12117 r = kvm_read_guest_virt(vcpu, gva, &operand, sizeof(operand), &e); 12118 if (r != X86EMUL_CONTINUE) 12119 return kvm_handle_memory_failure(vcpu, r, &e); 12120 12121 if (operand.pcid >> 12 != 0) { 12122 kvm_inject_gp(vcpu, 0); 12123 return 1; 12124 } 12125 12126 pcid_enabled = kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE); 12127 12128 switch (type) { 12129 case INVPCID_TYPE_INDIV_ADDR: 12130 if ((!pcid_enabled && (operand.pcid != 0)) || 12131 is_noncanonical_address(operand.gla, vcpu)) { 12132 kvm_inject_gp(vcpu, 0); 12133 return 1; 12134 } 12135 kvm_mmu_invpcid_gva(vcpu, operand.gla, operand.pcid); 12136 return kvm_skip_emulated_instruction(vcpu); 12137 12138 case INVPCID_TYPE_SINGLE_CTXT: 12139 if (!pcid_enabled && (operand.pcid != 0)) { 12140 kvm_inject_gp(vcpu, 0); 12141 return 1; 12142 } 12143 12144 kvm_invalidate_pcid(vcpu, operand.pcid); 12145 return kvm_skip_emulated_instruction(vcpu); 12146 12147 case INVPCID_TYPE_ALL_NON_GLOBAL: 12148 /* 12149 * Currently, KVM doesn't mark global entries in the shadow 12150 * page tables, so a non-global flush just degenerates to a 12151 * global flush. If needed, we could optimize this later by 12152 * keeping track of global entries in shadow page tables. 12153 */ 12154 12155 fallthrough; 12156 case INVPCID_TYPE_ALL_INCL_GLOBAL: 12157 kvm_make_request(KVM_REQ_TLB_FLUSH_GUEST, vcpu); 12158 return kvm_skip_emulated_instruction(vcpu); 12159 12160 default: 12161 BUG(); /* We have already checked above that type <= 3 */ 12162 } 12163 } 12164 EXPORT_SYMBOL_GPL(kvm_handle_invpcid); 12165 12166 static int complete_sev_es_emulated_mmio(struct kvm_vcpu *vcpu) 12167 { 12168 struct kvm_run *run = vcpu->run; 12169 struct kvm_mmio_fragment *frag; 12170 unsigned int len; 12171 12172 BUG_ON(!vcpu->mmio_needed); 12173 12174 /* Complete previous fragment */ 12175 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment]; 12176 len = min(8u, frag->len); 12177 if (!vcpu->mmio_is_write) 12178 memcpy(frag->data, run->mmio.data, len); 12179 12180 if (frag->len <= 8) { 12181 /* Switch to the next fragment. */ 12182 frag++; 12183 vcpu->mmio_cur_fragment++; 12184 } else { 12185 /* Go forward to the next mmio piece. */ 12186 frag->data += len; 12187 frag->gpa += len; 12188 frag->len -= len; 12189 } 12190 12191 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) { 12192 vcpu->mmio_needed = 0; 12193 12194 // VMG change, at this point, we're always done 12195 // RIP has already been advanced 12196 return 1; 12197 } 12198 12199 // More MMIO is needed 12200 run->mmio.phys_addr = frag->gpa; 12201 run->mmio.len = min(8u, frag->len); 12202 run->mmio.is_write = vcpu->mmio_is_write; 12203 if (run->mmio.is_write) 12204 memcpy(run->mmio.data, frag->data, min(8u, frag->len)); 12205 run->exit_reason = KVM_EXIT_MMIO; 12206 12207 vcpu->arch.complete_userspace_io = complete_sev_es_emulated_mmio; 12208 12209 return 0; 12210 } 12211 12212 int kvm_sev_es_mmio_write(struct kvm_vcpu *vcpu, gpa_t gpa, unsigned int bytes, 12213 void *data) 12214 { 12215 int handled; 12216 struct kvm_mmio_fragment *frag; 12217 12218 if (!data) 12219 return -EINVAL; 12220 12221 handled = write_emultor.read_write_mmio(vcpu, gpa, bytes, data); 12222 if (handled == bytes) 12223 return 1; 12224 12225 bytes -= handled; 12226 gpa += handled; 12227 data += handled; 12228 12229 /*TODO: Check if need to increment number of frags */ 12230 frag = vcpu->mmio_fragments; 12231 vcpu->mmio_nr_fragments = 1; 12232 frag->len = bytes; 12233 frag->gpa = gpa; 12234 frag->data = data; 12235 12236 vcpu->mmio_needed = 1; 12237 vcpu->mmio_cur_fragment = 0; 12238 12239 vcpu->run->mmio.phys_addr = gpa; 12240 vcpu->run->mmio.len = min(8u, frag->len); 12241 vcpu->run->mmio.is_write = 1; 12242 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len)); 12243 vcpu->run->exit_reason = KVM_EXIT_MMIO; 12244 12245 vcpu->arch.complete_userspace_io = complete_sev_es_emulated_mmio; 12246 12247 return 0; 12248 } 12249 EXPORT_SYMBOL_GPL(kvm_sev_es_mmio_write); 12250 12251 int kvm_sev_es_mmio_read(struct kvm_vcpu *vcpu, gpa_t gpa, unsigned int bytes, 12252 void *data) 12253 { 12254 int handled; 12255 struct kvm_mmio_fragment *frag; 12256 12257 if (!data) 12258 return -EINVAL; 12259 12260 handled = read_emultor.read_write_mmio(vcpu, gpa, bytes, data); 12261 if (handled == bytes) 12262 return 1; 12263 12264 bytes -= handled; 12265 gpa += handled; 12266 data += handled; 12267 12268 /*TODO: Check if need to increment number of frags */ 12269 frag = vcpu->mmio_fragments; 12270 vcpu->mmio_nr_fragments = 1; 12271 frag->len = bytes; 12272 frag->gpa = gpa; 12273 frag->data = data; 12274 12275 vcpu->mmio_needed = 1; 12276 vcpu->mmio_cur_fragment = 0; 12277 12278 vcpu->run->mmio.phys_addr = gpa; 12279 vcpu->run->mmio.len = min(8u, frag->len); 12280 vcpu->run->mmio.is_write = 0; 12281 vcpu->run->exit_reason = KVM_EXIT_MMIO; 12282 12283 vcpu->arch.complete_userspace_io = complete_sev_es_emulated_mmio; 12284 12285 return 0; 12286 } 12287 EXPORT_SYMBOL_GPL(kvm_sev_es_mmio_read); 12288 12289 static int complete_sev_es_emulated_ins(struct kvm_vcpu *vcpu) 12290 { 12291 memcpy(vcpu->arch.guest_ins_data, vcpu->arch.pio_data, 12292 vcpu->arch.pio.count * vcpu->arch.pio.size); 12293 vcpu->arch.pio.count = 0; 12294 12295 return 1; 12296 } 12297 12298 static int kvm_sev_es_outs(struct kvm_vcpu *vcpu, unsigned int size, 12299 unsigned int port, void *data, unsigned int count) 12300 { 12301 int ret; 12302 12303 ret = emulator_pio_out_emulated(vcpu->arch.emulate_ctxt, size, port, 12304 data, count); 12305 if (ret) 12306 return ret; 12307 12308 vcpu->arch.pio.count = 0; 12309 12310 return 0; 12311 } 12312 12313 static int kvm_sev_es_ins(struct kvm_vcpu *vcpu, unsigned int size, 12314 unsigned int port, void *data, unsigned int count) 12315 { 12316 int ret; 12317 12318 ret = emulator_pio_in_emulated(vcpu->arch.emulate_ctxt, size, port, 12319 data, count); 12320 if (ret) { 12321 vcpu->arch.pio.count = 0; 12322 } else { 12323 vcpu->arch.guest_ins_data = data; 12324 vcpu->arch.complete_userspace_io = complete_sev_es_emulated_ins; 12325 } 12326 12327 return 0; 12328 } 12329 12330 int kvm_sev_es_string_io(struct kvm_vcpu *vcpu, unsigned int size, 12331 unsigned int port, void *data, unsigned int count, 12332 int in) 12333 { 12334 return in ? kvm_sev_es_ins(vcpu, size, port, data, count) 12335 : kvm_sev_es_outs(vcpu, size, port, data, count); 12336 } 12337 EXPORT_SYMBOL_GPL(kvm_sev_es_string_io); 12338 12339 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_entry); 12340 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit); 12341 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_fast_mmio); 12342 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq); 12343 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault); 12344 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr); 12345 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr); 12346 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun); 12347 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit); 12348 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject); 12349 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit); 12350 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmenter_failed); 12351 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga); 12352 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit); 12353 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts); 12354 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset); 12355 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_ple_window_update); 12356 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pml_full); 12357 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pi_irte_update); 12358 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_unaccelerated_access); 12359 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_incomplete_ipi); 12360 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_ga_log); 12361 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_apicv_update_request); 12362 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_vmgexit_enter); 12363 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_vmgexit_exit); 12364 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_vmgexit_msr_protocol_enter); 12365 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_vmgexit_msr_protocol_exit); 12366