1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Kernel-based Virtual Machine driver for Linux 4 * 5 * derived from drivers/kvm/kvm_main.c 6 * 7 * Copyright (C) 2006 Qumranet, Inc. 8 * Copyright (C) 2008 Qumranet, Inc. 9 * Copyright IBM Corporation, 2008 10 * Copyright 2010 Red Hat, Inc. and/or its affiliates. 11 * 12 * Authors: 13 * Avi Kivity <avi@qumranet.com> 14 * Yaniv Kamay <yaniv@qumranet.com> 15 * Amit Shah <amit.shah@qumranet.com> 16 * Ben-Ami Yassour <benami@il.ibm.com> 17 */ 18 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 19 20 #include <linux/kvm_host.h> 21 #include "irq.h" 22 #include "ioapic.h" 23 #include "mmu.h" 24 #include "i8254.h" 25 #include "tss.h" 26 #include "kvm_cache_regs.h" 27 #include "kvm_emulate.h" 28 #include "mmu/page_track.h" 29 #include "x86.h" 30 #include "cpuid.h" 31 #include "pmu.h" 32 #include "hyperv.h" 33 #include "lapic.h" 34 #include "xen.h" 35 #include "smm.h" 36 37 #include <linux/clocksource.h> 38 #include <linux/interrupt.h> 39 #include <linux/kvm.h> 40 #include <linux/fs.h> 41 #include <linux/vmalloc.h> 42 #include <linux/export.h> 43 #include <linux/moduleparam.h> 44 #include <linux/mman.h> 45 #include <linux/highmem.h> 46 #include <linux/iommu.h> 47 #include <linux/cpufreq.h> 48 #include <linux/user-return-notifier.h> 49 #include <linux/srcu.h> 50 #include <linux/slab.h> 51 #include <linux/perf_event.h> 52 #include <linux/uaccess.h> 53 #include <linux/hash.h> 54 #include <linux/pci.h> 55 #include <linux/timekeeper_internal.h> 56 #include <linux/pvclock_gtod.h> 57 #include <linux/kvm_irqfd.h> 58 #include <linux/irqbypass.h> 59 #include <linux/sched/stat.h> 60 #include <linux/sched/isolation.h> 61 #include <linux/mem_encrypt.h> 62 #include <linux/entry-kvm.h> 63 #include <linux/suspend.h> 64 #include <linux/smp.h> 65 66 #include <trace/events/ipi.h> 67 #include <trace/events/kvm.h> 68 69 #include <asm/debugreg.h> 70 #include <asm/msr.h> 71 #include <asm/desc.h> 72 #include <asm/mce.h> 73 #include <asm/pkru.h> 74 #include <linux/kernel_stat.h> 75 #include <asm/fpu/api.h> 76 #include <asm/fpu/xcr.h> 77 #include <asm/fpu/xstate.h> 78 #include <asm/pvclock.h> 79 #include <asm/div64.h> 80 #include <asm/irq_remapping.h> 81 #include <asm/mshyperv.h> 82 #include <asm/hypervisor.h> 83 #include <asm/tlbflush.h> 84 #include <asm/intel_pt.h> 85 #include <asm/emulate_prefix.h> 86 #include <asm/sgx.h> 87 #include <clocksource/hyperv_timer.h> 88 89 #define CREATE_TRACE_POINTS 90 #include "trace.h" 91 92 #define MAX_IO_MSRS 256 93 #define KVM_MAX_MCE_BANKS 32 94 95 /* 96 * Note, kvm_caps fields should *never* have default values, all fields must be 97 * recomputed from scratch during vendor module load, e.g. to account for a 98 * vendor module being reloaded with different module parameters. 99 */ 100 struct kvm_caps kvm_caps __read_mostly; 101 EXPORT_SYMBOL_GPL(kvm_caps); 102 103 struct kvm_host_values kvm_host __read_mostly; 104 EXPORT_SYMBOL_GPL(kvm_host); 105 106 #define ERR_PTR_USR(e) ((void __user *)ERR_PTR(e)) 107 108 #define emul_to_vcpu(ctxt) \ 109 ((struct kvm_vcpu *)(ctxt)->vcpu) 110 111 /* EFER defaults: 112 * - enable syscall per default because its emulated by KVM 113 * - enable LME and LMA per default on 64 bit KVM 114 */ 115 #ifdef CONFIG_X86_64 116 static 117 u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA)); 118 #else 119 static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE); 120 #endif 121 122 #define KVM_EXIT_HYPERCALL_VALID_MASK (1 << KVM_HC_MAP_GPA_RANGE) 123 124 #define KVM_CAP_PMU_VALID_MASK KVM_PMU_CAP_DISABLE 125 126 #define KVM_X2APIC_API_VALID_FLAGS (KVM_X2APIC_API_USE_32BIT_IDS | \ 127 KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK) 128 129 static void update_cr8_intercept(struct kvm_vcpu *vcpu); 130 static void process_nmi(struct kvm_vcpu *vcpu); 131 static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags); 132 static void store_regs(struct kvm_vcpu *vcpu); 133 static int sync_regs(struct kvm_vcpu *vcpu); 134 static int kvm_vcpu_do_singlestep(struct kvm_vcpu *vcpu); 135 136 static int __set_sregs2(struct kvm_vcpu *vcpu, struct kvm_sregs2 *sregs2); 137 static void __get_sregs2(struct kvm_vcpu *vcpu, struct kvm_sregs2 *sregs2); 138 139 static DEFINE_MUTEX(vendor_module_lock); 140 struct kvm_x86_ops kvm_x86_ops __read_mostly; 141 142 #define KVM_X86_OP(func) \ 143 DEFINE_STATIC_CALL_NULL(kvm_x86_##func, \ 144 *(((struct kvm_x86_ops *)0)->func)); 145 #define KVM_X86_OP_OPTIONAL KVM_X86_OP 146 #define KVM_X86_OP_OPTIONAL_RET0 KVM_X86_OP 147 #include <asm/kvm-x86-ops.h> 148 EXPORT_STATIC_CALL_GPL(kvm_x86_get_cs_db_l_bits); 149 EXPORT_STATIC_CALL_GPL(kvm_x86_cache_reg); 150 151 static bool __read_mostly ignore_msrs = 0; 152 module_param(ignore_msrs, bool, 0644); 153 154 bool __read_mostly report_ignored_msrs = true; 155 module_param(report_ignored_msrs, bool, 0644); 156 EXPORT_SYMBOL_GPL(report_ignored_msrs); 157 158 unsigned int min_timer_period_us = 200; 159 module_param(min_timer_period_us, uint, 0644); 160 161 static bool __read_mostly kvmclock_periodic_sync = true; 162 module_param(kvmclock_periodic_sync, bool, 0444); 163 164 /* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */ 165 static u32 __read_mostly tsc_tolerance_ppm = 250; 166 module_param(tsc_tolerance_ppm, uint, 0644); 167 168 static bool __read_mostly vector_hashing = true; 169 module_param(vector_hashing, bool, 0444); 170 171 bool __read_mostly enable_vmware_backdoor = false; 172 module_param(enable_vmware_backdoor, bool, 0444); 173 EXPORT_SYMBOL_GPL(enable_vmware_backdoor); 174 175 /* 176 * Flags to manipulate forced emulation behavior (any non-zero value will 177 * enable forced emulation). 178 */ 179 #define KVM_FEP_CLEAR_RFLAGS_RF BIT(1) 180 static int __read_mostly force_emulation_prefix; 181 module_param(force_emulation_prefix, int, 0644); 182 183 int __read_mostly pi_inject_timer = -1; 184 module_param(pi_inject_timer, bint, 0644); 185 186 /* Enable/disable PMU virtualization */ 187 bool __read_mostly enable_pmu = true; 188 EXPORT_SYMBOL_GPL(enable_pmu); 189 module_param(enable_pmu, bool, 0444); 190 191 bool __read_mostly eager_page_split = true; 192 module_param(eager_page_split, bool, 0644); 193 194 /* Enable/disable SMT_RSB bug mitigation */ 195 static bool __read_mostly mitigate_smt_rsb; 196 module_param(mitigate_smt_rsb, bool, 0444); 197 198 /* 199 * Restoring the host value for MSRs that are only consumed when running in 200 * usermode, e.g. SYSCALL MSRs and TSC_AUX, can be deferred until the CPU 201 * returns to userspace, i.e. the kernel can run with the guest's value. 202 */ 203 #define KVM_MAX_NR_USER_RETURN_MSRS 16 204 205 struct kvm_user_return_msrs { 206 struct user_return_notifier urn; 207 bool registered; 208 struct kvm_user_return_msr_values { 209 u64 host; 210 u64 curr; 211 } values[KVM_MAX_NR_USER_RETURN_MSRS]; 212 }; 213 214 u32 __read_mostly kvm_nr_uret_msrs; 215 EXPORT_SYMBOL_GPL(kvm_nr_uret_msrs); 216 static u32 __read_mostly kvm_uret_msrs_list[KVM_MAX_NR_USER_RETURN_MSRS]; 217 static struct kvm_user_return_msrs __percpu *user_return_msrs; 218 219 #define KVM_SUPPORTED_XCR0 (XFEATURE_MASK_FP | XFEATURE_MASK_SSE \ 220 | XFEATURE_MASK_YMM | XFEATURE_MASK_BNDREGS \ 221 | XFEATURE_MASK_BNDCSR | XFEATURE_MASK_AVX512 \ 222 | XFEATURE_MASK_PKRU | XFEATURE_MASK_XTILE) 223 224 bool __read_mostly allow_smaller_maxphyaddr = 0; 225 EXPORT_SYMBOL_GPL(allow_smaller_maxphyaddr); 226 227 bool __read_mostly enable_apicv = true; 228 EXPORT_SYMBOL_GPL(enable_apicv); 229 230 const struct _kvm_stats_desc kvm_vm_stats_desc[] = { 231 KVM_GENERIC_VM_STATS(), 232 STATS_DESC_COUNTER(VM, mmu_shadow_zapped), 233 STATS_DESC_COUNTER(VM, mmu_pte_write), 234 STATS_DESC_COUNTER(VM, mmu_pde_zapped), 235 STATS_DESC_COUNTER(VM, mmu_flooded), 236 STATS_DESC_COUNTER(VM, mmu_recycled), 237 STATS_DESC_COUNTER(VM, mmu_cache_miss), 238 STATS_DESC_ICOUNTER(VM, mmu_unsync), 239 STATS_DESC_ICOUNTER(VM, pages_4k), 240 STATS_DESC_ICOUNTER(VM, pages_2m), 241 STATS_DESC_ICOUNTER(VM, pages_1g), 242 STATS_DESC_ICOUNTER(VM, nx_lpage_splits), 243 STATS_DESC_PCOUNTER(VM, max_mmu_rmap_size), 244 STATS_DESC_PCOUNTER(VM, max_mmu_page_hash_collisions) 245 }; 246 247 const struct kvm_stats_header kvm_vm_stats_header = { 248 .name_size = KVM_STATS_NAME_SIZE, 249 .num_desc = ARRAY_SIZE(kvm_vm_stats_desc), 250 .id_offset = sizeof(struct kvm_stats_header), 251 .desc_offset = sizeof(struct kvm_stats_header) + KVM_STATS_NAME_SIZE, 252 .data_offset = sizeof(struct kvm_stats_header) + KVM_STATS_NAME_SIZE + 253 sizeof(kvm_vm_stats_desc), 254 }; 255 256 const struct _kvm_stats_desc kvm_vcpu_stats_desc[] = { 257 KVM_GENERIC_VCPU_STATS(), 258 STATS_DESC_COUNTER(VCPU, pf_taken), 259 STATS_DESC_COUNTER(VCPU, pf_fixed), 260 STATS_DESC_COUNTER(VCPU, pf_emulate), 261 STATS_DESC_COUNTER(VCPU, pf_spurious), 262 STATS_DESC_COUNTER(VCPU, pf_fast), 263 STATS_DESC_COUNTER(VCPU, pf_mmio_spte_created), 264 STATS_DESC_COUNTER(VCPU, pf_guest), 265 STATS_DESC_COUNTER(VCPU, tlb_flush), 266 STATS_DESC_COUNTER(VCPU, invlpg), 267 STATS_DESC_COUNTER(VCPU, exits), 268 STATS_DESC_COUNTER(VCPU, io_exits), 269 STATS_DESC_COUNTER(VCPU, mmio_exits), 270 STATS_DESC_COUNTER(VCPU, signal_exits), 271 STATS_DESC_COUNTER(VCPU, irq_window_exits), 272 STATS_DESC_COUNTER(VCPU, nmi_window_exits), 273 STATS_DESC_COUNTER(VCPU, l1d_flush), 274 STATS_DESC_COUNTER(VCPU, halt_exits), 275 STATS_DESC_COUNTER(VCPU, request_irq_exits), 276 STATS_DESC_COUNTER(VCPU, irq_exits), 277 STATS_DESC_COUNTER(VCPU, host_state_reload), 278 STATS_DESC_COUNTER(VCPU, fpu_reload), 279 STATS_DESC_COUNTER(VCPU, insn_emulation), 280 STATS_DESC_COUNTER(VCPU, insn_emulation_fail), 281 STATS_DESC_COUNTER(VCPU, hypercalls), 282 STATS_DESC_COUNTER(VCPU, irq_injections), 283 STATS_DESC_COUNTER(VCPU, nmi_injections), 284 STATS_DESC_COUNTER(VCPU, req_event), 285 STATS_DESC_COUNTER(VCPU, nested_run), 286 STATS_DESC_COUNTER(VCPU, directed_yield_attempted), 287 STATS_DESC_COUNTER(VCPU, directed_yield_successful), 288 STATS_DESC_COUNTER(VCPU, preemption_reported), 289 STATS_DESC_COUNTER(VCPU, preemption_other), 290 STATS_DESC_IBOOLEAN(VCPU, guest_mode), 291 STATS_DESC_COUNTER(VCPU, notify_window_exits), 292 }; 293 294 const struct kvm_stats_header kvm_vcpu_stats_header = { 295 .name_size = KVM_STATS_NAME_SIZE, 296 .num_desc = ARRAY_SIZE(kvm_vcpu_stats_desc), 297 .id_offset = sizeof(struct kvm_stats_header), 298 .desc_offset = sizeof(struct kvm_stats_header) + KVM_STATS_NAME_SIZE, 299 .data_offset = sizeof(struct kvm_stats_header) + KVM_STATS_NAME_SIZE + 300 sizeof(kvm_vcpu_stats_desc), 301 }; 302 303 static struct kmem_cache *x86_emulator_cache; 304 305 /* 306 * The three MSR lists(msrs_to_save, emulated_msrs, msr_based_features) track 307 * the set of MSRs that KVM exposes to userspace through KVM_GET_MSRS, 308 * KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST. msrs_to_save holds MSRs that 309 * require host support, i.e. should be probed via RDMSR. emulated_msrs holds 310 * MSRs that KVM emulates without strictly requiring host support. 311 * msr_based_features holds MSRs that enumerate features, i.e. are effectively 312 * CPUID leafs. Note, msr_based_features isn't mutually exclusive with 313 * msrs_to_save and emulated_msrs. 314 */ 315 316 static const u32 msrs_to_save_base[] = { 317 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP, 318 MSR_STAR, 319 #ifdef CONFIG_X86_64 320 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR, 321 #endif 322 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA, 323 MSR_IA32_FEAT_CTL, MSR_IA32_BNDCFGS, MSR_TSC_AUX, 324 MSR_IA32_SPEC_CTRL, MSR_IA32_TSX_CTRL, 325 MSR_IA32_RTIT_CTL, MSR_IA32_RTIT_STATUS, MSR_IA32_RTIT_CR3_MATCH, 326 MSR_IA32_RTIT_OUTPUT_BASE, MSR_IA32_RTIT_OUTPUT_MASK, 327 MSR_IA32_RTIT_ADDR0_A, MSR_IA32_RTIT_ADDR0_B, 328 MSR_IA32_RTIT_ADDR1_A, MSR_IA32_RTIT_ADDR1_B, 329 MSR_IA32_RTIT_ADDR2_A, MSR_IA32_RTIT_ADDR2_B, 330 MSR_IA32_RTIT_ADDR3_A, MSR_IA32_RTIT_ADDR3_B, 331 MSR_IA32_UMWAIT_CONTROL, 332 333 MSR_IA32_XFD, MSR_IA32_XFD_ERR, 334 }; 335 336 static const u32 msrs_to_save_pmu[] = { 337 MSR_ARCH_PERFMON_FIXED_CTR0, MSR_ARCH_PERFMON_FIXED_CTR1, 338 MSR_ARCH_PERFMON_FIXED_CTR0 + 2, 339 MSR_CORE_PERF_FIXED_CTR_CTRL, MSR_CORE_PERF_GLOBAL_STATUS, 340 MSR_CORE_PERF_GLOBAL_CTRL, 341 MSR_IA32_PEBS_ENABLE, MSR_IA32_DS_AREA, MSR_PEBS_DATA_CFG, 342 343 /* This part of MSRs should match KVM_MAX_NR_INTEL_GP_COUNTERS. */ 344 MSR_ARCH_PERFMON_PERFCTR0, MSR_ARCH_PERFMON_PERFCTR1, 345 MSR_ARCH_PERFMON_PERFCTR0 + 2, MSR_ARCH_PERFMON_PERFCTR0 + 3, 346 MSR_ARCH_PERFMON_PERFCTR0 + 4, MSR_ARCH_PERFMON_PERFCTR0 + 5, 347 MSR_ARCH_PERFMON_PERFCTR0 + 6, MSR_ARCH_PERFMON_PERFCTR0 + 7, 348 MSR_ARCH_PERFMON_EVENTSEL0, MSR_ARCH_PERFMON_EVENTSEL1, 349 MSR_ARCH_PERFMON_EVENTSEL0 + 2, MSR_ARCH_PERFMON_EVENTSEL0 + 3, 350 MSR_ARCH_PERFMON_EVENTSEL0 + 4, MSR_ARCH_PERFMON_EVENTSEL0 + 5, 351 MSR_ARCH_PERFMON_EVENTSEL0 + 6, MSR_ARCH_PERFMON_EVENTSEL0 + 7, 352 353 MSR_K7_EVNTSEL0, MSR_K7_EVNTSEL1, MSR_K7_EVNTSEL2, MSR_K7_EVNTSEL3, 354 MSR_K7_PERFCTR0, MSR_K7_PERFCTR1, MSR_K7_PERFCTR2, MSR_K7_PERFCTR3, 355 356 /* This part of MSRs should match KVM_MAX_NR_AMD_GP_COUNTERS. */ 357 MSR_F15H_PERF_CTL0, MSR_F15H_PERF_CTL1, MSR_F15H_PERF_CTL2, 358 MSR_F15H_PERF_CTL3, MSR_F15H_PERF_CTL4, MSR_F15H_PERF_CTL5, 359 MSR_F15H_PERF_CTR0, MSR_F15H_PERF_CTR1, MSR_F15H_PERF_CTR2, 360 MSR_F15H_PERF_CTR3, MSR_F15H_PERF_CTR4, MSR_F15H_PERF_CTR5, 361 362 MSR_AMD64_PERF_CNTR_GLOBAL_CTL, 363 MSR_AMD64_PERF_CNTR_GLOBAL_STATUS, 364 MSR_AMD64_PERF_CNTR_GLOBAL_STATUS_CLR, 365 }; 366 367 static u32 msrs_to_save[ARRAY_SIZE(msrs_to_save_base) + 368 ARRAY_SIZE(msrs_to_save_pmu)]; 369 static unsigned num_msrs_to_save; 370 371 static const u32 emulated_msrs_all[] = { 372 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK, 373 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW, 374 375 #ifdef CONFIG_KVM_HYPERV 376 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL, 377 HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC, 378 HV_X64_MSR_TSC_FREQUENCY, HV_X64_MSR_APIC_FREQUENCY, 379 HV_X64_MSR_CRASH_P0, HV_X64_MSR_CRASH_P1, HV_X64_MSR_CRASH_P2, 380 HV_X64_MSR_CRASH_P3, HV_X64_MSR_CRASH_P4, HV_X64_MSR_CRASH_CTL, 381 HV_X64_MSR_RESET, 382 HV_X64_MSR_VP_INDEX, 383 HV_X64_MSR_VP_RUNTIME, 384 HV_X64_MSR_SCONTROL, 385 HV_X64_MSR_STIMER0_CONFIG, 386 HV_X64_MSR_VP_ASSIST_PAGE, 387 HV_X64_MSR_REENLIGHTENMENT_CONTROL, HV_X64_MSR_TSC_EMULATION_CONTROL, 388 HV_X64_MSR_TSC_EMULATION_STATUS, HV_X64_MSR_TSC_INVARIANT_CONTROL, 389 HV_X64_MSR_SYNDBG_OPTIONS, 390 HV_X64_MSR_SYNDBG_CONTROL, HV_X64_MSR_SYNDBG_STATUS, 391 HV_X64_MSR_SYNDBG_SEND_BUFFER, HV_X64_MSR_SYNDBG_RECV_BUFFER, 392 HV_X64_MSR_SYNDBG_PENDING_BUFFER, 393 #endif 394 395 MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME, 396 MSR_KVM_PV_EOI_EN, MSR_KVM_ASYNC_PF_INT, MSR_KVM_ASYNC_PF_ACK, 397 398 MSR_IA32_TSC_ADJUST, 399 MSR_IA32_TSC_DEADLINE, 400 MSR_IA32_ARCH_CAPABILITIES, 401 MSR_IA32_PERF_CAPABILITIES, 402 MSR_IA32_MISC_ENABLE, 403 MSR_IA32_MCG_STATUS, 404 MSR_IA32_MCG_CTL, 405 MSR_IA32_MCG_EXT_CTL, 406 MSR_IA32_SMBASE, 407 MSR_SMI_COUNT, 408 MSR_PLATFORM_INFO, 409 MSR_MISC_FEATURES_ENABLES, 410 MSR_AMD64_VIRT_SPEC_CTRL, 411 MSR_AMD64_TSC_RATIO, 412 MSR_IA32_POWER_CTL, 413 MSR_IA32_UCODE_REV, 414 415 /* 416 * KVM always supports the "true" VMX control MSRs, even if the host 417 * does not. The VMX MSRs as a whole are considered "emulated" as KVM 418 * doesn't strictly require them to exist in the host (ignoring that 419 * KVM would refuse to load in the first place if the core set of MSRs 420 * aren't supported). 421 */ 422 MSR_IA32_VMX_BASIC, 423 MSR_IA32_VMX_TRUE_PINBASED_CTLS, 424 MSR_IA32_VMX_TRUE_PROCBASED_CTLS, 425 MSR_IA32_VMX_TRUE_EXIT_CTLS, 426 MSR_IA32_VMX_TRUE_ENTRY_CTLS, 427 MSR_IA32_VMX_MISC, 428 MSR_IA32_VMX_CR0_FIXED0, 429 MSR_IA32_VMX_CR4_FIXED0, 430 MSR_IA32_VMX_VMCS_ENUM, 431 MSR_IA32_VMX_PROCBASED_CTLS2, 432 MSR_IA32_VMX_EPT_VPID_CAP, 433 MSR_IA32_VMX_VMFUNC, 434 435 MSR_K7_HWCR, 436 MSR_KVM_POLL_CONTROL, 437 }; 438 439 static u32 emulated_msrs[ARRAY_SIZE(emulated_msrs_all)]; 440 static unsigned num_emulated_msrs; 441 442 /* 443 * List of MSRs that control the existence of MSR-based features, i.e. MSRs 444 * that are effectively CPUID leafs. VMX MSRs are also included in the set of 445 * feature MSRs, but are handled separately to allow expedited lookups. 446 */ 447 static const u32 msr_based_features_all_except_vmx[] = { 448 MSR_AMD64_DE_CFG, 449 MSR_IA32_UCODE_REV, 450 MSR_IA32_ARCH_CAPABILITIES, 451 MSR_IA32_PERF_CAPABILITIES, 452 MSR_PLATFORM_INFO, 453 }; 454 455 static u32 msr_based_features[ARRAY_SIZE(msr_based_features_all_except_vmx) + 456 (KVM_LAST_EMULATED_VMX_MSR - KVM_FIRST_EMULATED_VMX_MSR + 1)]; 457 static unsigned int num_msr_based_features; 458 459 /* 460 * All feature MSRs except uCode revID, which tracks the currently loaded uCode 461 * patch, are immutable once the vCPU model is defined. 462 */ 463 static bool kvm_is_immutable_feature_msr(u32 msr) 464 { 465 int i; 466 467 if (msr >= KVM_FIRST_EMULATED_VMX_MSR && msr <= KVM_LAST_EMULATED_VMX_MSR) 468 return true; 469 470 for (i = 0; i < ARRAY_SIZE(msr_based_features_all_except_vmx); i++) { 471 if (msr == msr_based_features_all_except_vmx[i]) 472 return msr != MSR_IA32_UCODE_REV; 473 } 474 475 return false; 476 } 477 478 static bool kvm_is_advertised_msr(u32 msr_index) 479 { 480 unsigned int i; 481 482 for (i = 0; i < num_msrs_to_save; i++) { 483 if (msrs_to_save[i] == msr_index) 484 return true; 485 } 486 487 for (i = 0; i < num_emulated_msrs; i++) { 488 if (emulated_msrs[i] == msr_index) 489 return true; 490 } 491 492 return false; 493 } 494 495 typedef int (*msr_access_t)(struct kvm_vcpu *vcpu, u32 index, u64 *data, 496 bool host_initiated); 497 498 static __always_inline int kvm_do_msr_access(struct kvm_vcpu *vcpu, u32 msr, 499 u64 *data, bool host_initiated, 500 enum kvm_msr_access rw, 501 msr_access_t msr_access_fn) 502 { 503 const char *op = rw == MSR_TYPE_W ? "wrmsr" : "rdmsr"; 504 int ret; 505 506 BUILD_BUG_ON(rw != MSR_TYPE_R && rw != MSR_TYPE_W); 507 508 /* 509 * Zero the data on read failures to avoid leaking stack data to the 510 * guest and/or userspace, e.g. if the failure is ignored below. 511 */ 512 ret = msr_access_fn(vcpu, msr, data, host_initiated); 513 if (ret && rw == MSR_TYPE_R) 514 *data = 0; 515 516 if (ret != KVM_MSR_RET_UNSUPPORTED) 517 return ret; 518 519 /* 520 * Userspace is allowed to read MSRs, and write '0' to MSRs, that KVM 521 * advertises to userspace, even if an MSR isn't fully supported. 522 * Simply check that @data is '0', which covers both the write '0' case 523 * and all reads (in which case @data is zeroed on failure; see above). 524 */ 525 if (host_initiated && !*data && kvm_is_advertised_msr(msr)) 526 return 0; 527 528 if (!ignore_msrs) { 529 kvm_debug_ratelimited("unhandled %s: 0x%x data 0x%llx\n", 530 op, msr, *data); 531 return ret; 532 } 533 534 if (report_ignored_msrs) 535 kvm_pr_unimpl("ignored %s: 0x%x data 0x%llx\n", op, msr, *data); 536 537 return 0; 538 } 539 540 static struct kmem_cache *kvm_alloc_emulator_cache(void) 541 { 542 unsigned int useroffset = offsetof(struct x86_emulate_ctxt, src); 543 unsigned int size = sizeof(struct x86_emulate_ctxt); 544 545 return kmem_cache_create_usercopy("x86_emulator", size, 546 __alignof__(struct x86_emulate_ctxt), 547 SLAB_ACCOUNT, useroffset, 548 size - useroffset, NULL); 549 } 550 551 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt); 552 553 static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu) 554 { 555 int i; 556 for (i = 0; i < ASYNC_PF_PER_VCPU; i++) 557 vcpu->arch.apf.gfns[i] = ~0; 558 } 559 560 static void kvm_on_user_return(struct user_return_notifier *urn) 561 { 562 unsigned slot; 563 struct kvm_user_return_msrs *msrs 564 = container_of(urn, struct kvm_user_return_msrs, urn); 565 struct kvm_user_return_msr_values *values; 566 unsigned long flags; 567 568 /* 569 * Disabling irqs at this point since the following code could be 570 * interrupted and executed through kvm_arch_disable_virtualization_cpu() 571 */ 572 local_irq_save(flags); 573 if (msrs->registered) { 574 msrs->registered = false; 575 user_return_notifier_unregister(urn); 576 } 577 local_irq_restore(flags); 578 for (slot = 0; slot < kvm_nr_uret_msrs; ++slot) { 579 values = &msrs->values[slot]; 580 if (values->host != values->curr) { 581 wrmsrl(kvm_uret_msrs_list[slot], values->host); 582 values->curr = values->host; 583 } 584 } 585 } 586 587 static int kvm_probe_user_return_msr(u32 msr) 588 { 589 u64 val; 590 int ret; 591 592 preempt_disable(); 593 ret = rdmsrl_safe(msr, &val); 594 if (ret) 595 goto out; 596 ret = wrmsrl_safe(msr, val); 597 out: 598 preempt_enable(); 599 return ret; 600 } 601 602 int kvm_add_user_return_msr(u32 msr) 603 { 604 BUG_ON(kvm_nr_uret_msrs >= KVM_MAX_NR_USER_RETURN_MSRS); 605 606 if (kvm_probe_user_return_msr(msr)) 607 return -1; 608 609 kvm_uret_msrs_list[kvm_nr_uret_msrs] = msr; 610 return kvm_nr_uret_msrs++; 611 } 612 EXPORT_SYMBOL_GPL(kvm_add_user_return_msr); 613 614 int kvm_find_user_return_msr(u32 msr) 615 { 616 int i; 617 618 for (i = 0; i < kvm_nr_uret_msrs; ++i) { 619 if (kvm_uret_msrs_list[i] == msr) 620 return i; 621 } 622 return -1; 623 } 624 EXPORT_SYMBOL_GPL(kvm_find_user_return_msr); 625 626 static void kvm_user_return_msr_cpu_online(void) 627 { 628 struct kvm_user_return_msrs *msrs = this_cpu_ptr(user_return_msrs); 629 u64 value; 630 int i; 631 632 for (i = 0; i < kvm_nr_uret_msrs; ++i) { 633 rdmsrl_safe(kvm_uret_msrs_list[i], &value); 634 msrs->values[i].host = value; 635 msrs->values[i].curr = value; 636 } 637 } 638 639 int kvm_set_user_return_msr(unsigned slot, u64 value, u64 mask) 640 { 641 struct kvm_user_return_msrs *msrs = this_cpu_ptr(user_return_msrs); 642 int err; 643 644 value = (value & mask) | (msrs->values[slot].host & ~mask); 645 if (value == msrs->values[slot].curr) 646 return 0; 647 err = wrmsrl_safe(kvm_uret_msrs_list[slot], value); 648 if (err) 649 return 1; 650 651 msrs->values[slot].curr = value; 652 if (!msrs->registered) { 653 msrs->urn.on_user_return = kvm_on_user_return; 654 user_return_notifier_register(&msrs->urn); 655 msrs->registered = true; 656 } 657 return 0; 658 } 659 EXPORT_SYMBOL_GPL(kvm_set_user_return_msr); 660 661 static void drop_user_return_notifiers(void) 662 { 663 struct kvm_user_return_msrs *msrs = this_cpu_ptr(user_return_msrs); 664 665 if (msrs->registered) 666 kvm_on_user_return(&msrs->urn); 667 } 668 669 /* 670 * Handle a fault on a hardware virtualization (VMX or SVM) instruction. 671 * 672 * Hardware virtualization extension instructions may fault if a reboot turns 673 * off virtualization while processes are running. Usually after catching the 674 * fault we just panic; during reboot instead the instruction is ignored. 675 */ 676 noinstr void kvm_spurious_fault(void) 677 { 678 /* Fault while not rebooting. We want the trace. */ 679 BUG_ON(!kvm_rebooting); 680 } 681 EXPORT_SYMBOL_GPL(kvm_spurious_fault); 682 683 #define EXCPT_BENIGN 0 684 #define EXCPT_CONTRIBUTORY 1 685 #define EXCPT_PF 2 686 687 static int exception_class(int vector) 688 { 689 switch (vector) { 690 case PF_VECTOR: 691 return EXCPT_PF; 692 case DE_VECTOR: 693 case TS_VECTOR: 694 case NP_VECTOR: 695 case SS_VECTOR: 696 case GP_VECTOR: 697 return EXCPT_CONTRIBUTORY; 698 default: 699 break; 700 } 701 return EXCPT_BENIGN; 702 } 703 704 #define EXCPT_FAULT 0 705 #define EXCPT_TRAP 1 706 #define EXCPT_ABORT 2 707 #define EXCPT_INTERRUPT 3 708 #define EXCPT_DB 4 709 710 static int exception_type(int vector) 711 { 712 unsigned int mask; 713 714 if (WARN_ON(vector > 31 || vector == NMI_VECTOR)) 715 return EXCPT_INTERRUPT; 716 717 mask = 1 << vector; 718 719 /* 720 * #DBs can be trap-like or fault-like, the caller must check other CPU 721 * state, e.g. DR6, to determine whether a #DB is a trap or fault. 722 */ 723 if (mask & (1 << DB_VECTOR)) 724 return EXCPT_DB; 725 726 if (mask & ((1 << BP_VECTOR) | (1 << OF_VECTOR))) 727 return EXCPT_TRAP; 728 729 if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR))) 730 return EXCPT_ABORT; 731 732 /* Reserved exceptions will result in fault */ 733 return EXCPT_FAULT; 734 } 735 736 void kvm_deliver_exception_payload(struct kvm_vcpu *vcpu, 737 struct kvm_queued_exception *ex) 738 { 739 if (!ex->has_payload) 740 return; 741 742 switch (ex->vector) { 743 case DB_VECTOR: 744 /* 745 * "Certain debug exceptions may clear bit 0-3. The 746 * remaining contents of the DR6 register are never 747 * cleared by the processor". 748 */ 749 vcpu->arch.dr6 &= ~DR_TRAP_BITS; 750 /* 751 * In order to reflect the #DB exception payload in guest 752 * dr6, three components need to be considered: active low 753 * bit, FIXED_1 bits and active high bits (e.g. DR6_BD, 754 * DR6_BS and DR6_BT) 755 * DR6_ACTIVE_LOW contains the FIXED_1 and active low bits. 756 * In the target guest dr6: 757 * FIXED_1 bits should always be set. 758 * Active low bits should be cleared if 1-setting in payload. 759 * Active high bits should be set if 1-setting in payload. 760 * 761 * Note, the payload is compatible with the pending debug 762 * exceptions/exit qualification under VMX, that active_low bits 763 * are active high in payload. 764 * So they need to be flipped for DR6. 765 */ 766 vcpu->arch.dr6 |= DR6_ACTIVE_LOW; 767 vcpu->arch.dr6 |= ex->payload; 768 vcpu->arch.dr6 ^= ex->payload & DR6_ACTIVE_LOW; 769 770 /* 771 * The #DB payload is defined as compatible with the 'pending 772 * debug exceptions' field under VMX, not DR6. While bit 12 is 773 * defined in the 'pending debug exceptions' field (enabled 774 * breakpoint), it is reserved and must be zero in DR6. 775 */ 776 vcpu->arch.dr6 &= ~BIT(12); 777 break; 778 case PF_VECTOR: 779 vcpu->arch.cr2 = ex->payload; 780 break; 781 } 782 783 ex->has_payload = false; 784 ex->payload = 0; 785 } 786 EXPORT_SYMBOL_GPL(kvm_deliver_exception_payload); 787 788 static void kvm_queue_exception_vmexit(struct kvm_vcpu *vcpu, unsigned int vector, 789 bool has_error_code, u32 error_code, 790 bool has_payload, unsigned long payload) 791 { 792 struct kvm_queued_exception *ex = &vcpu->arch.exception_vmexit; 793 794 ex->vector = vector; 795 ex->injected = false; 796 ex->pending = true; 797 ex->has_error_code = has_error_code; 798 ex->error_code = error_code; 799 ex->has_payload = has_payload; 800 ex->payload = payload; 801 } 802 803 static void kvm_multiple_exception(struct kvm_vcpu *vcpu, 804 unsigned nr, bool has_error, u32 error_code, 805 bool has_payload, unsigned long payload, bool reinject) 806 { 807 u32 prev_nr; 808 int class1, class2; 809 810 kvm_make_request(KVM_REQ_EVENT, vcpu); 811 812 /* 813 * If the exception is destined for L2 and isn't being reinjected, 814 * morph it to a VM-Exit if L1 wants to intercept the exception. A 815 * previously injected exception is not checked because it was checked 816 * when it was original queued, and re-checking is incorrect if _L1_ 817 * injected the exception, in which case it's exempt from interception. 818 */ 819 if (!reinject && is_guest_mode(vcpu) && 820 kvm_x86_ops.nested_ops->is_exception_vmexit(vcpu, nr, error_code)) { 821 kvm_queue_exception_vmexit(vcpu, nr, has_error, error_code, 822 has_payload, payload); 823 return; 824 } 825 826 if (!vcpu->arch.exception.pending && !vcpu->arch.exception.injected) { 827 queue: 828 if (reinject) { 829 /* 830 * On VM-Entry, an exception can be pending if and only 831 * if event injection was blocked by nested_run_pending. 832 * In that case, however, vcpu_enter_guest() requests an 833 * immediate exit, and the guest shouldn't proceed far 834 * enough to need reinjection. 835 */ 836 WARN_ON_ONCE(kvm_is_exception_pending(vcpu)); 837 vcpu->arch.exception.injected = true; 838 if (WARN_ON_ONCE(has_payload)) { 839 /* 840 * A reinjected event has already 841 * delivered its payload. 842 */ 843 has_payload = false; 844 payload = 0; 845 } 846 } else { 847 vcpu->arch.exception.pending = true; 848 vcpu->arch.exception.injected = false; 849 } 850 vcpu->arch.exception.has_error_code = has_error; 851 vcpu->arch.exception.vector = nr; 852 vcpu->arch.exception.error_code = error_code; 853 vcpu->arch.exception.has_payload = has_payload; 854 vcpu->arch.exception.payload = payload; 855 if (!is_guest_mode(vcpu)) 856 kvm_deliver_exception_payload(vcpu, 857 &vcpu->arch.exception); 858 return; 859 } 860 861 /* to check exception */ 862 prev_nr = vcpu->arch.exception.vector; 863 if (prev_nr == DF_VECTOR) { 864 /* triple fault -> shutdown */ 865 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); 866 return; 867 } 868 class1 = exception_class(prev_nr); 869 class2 = exception_class(nr); 870 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY) || 871 (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) { 872 /* 873 * Synthesize #DF. Clear the previously injected or pending 874 * exception so as not to incorrectly trigger shutdown. 875 */ 876 vcpu->arch.exception.injected = false; 877 vcpu->arch.exception.pending = false; 878 879 kvm_queue_exception_e(vcpu, DF_VECTOR, 0); 880 } else { 881 /* replace previous exception with a new one in a hope 882 that instruction re-execution will regenerate lost 883 exception */ 884 goto queue; 885 } 886 } 887 888 void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr) 889 { 890 kvm_multiple_exception(vcpu, nr, false, 0, false, 0, false); 891 } 892 EXPORT_SYMBOL_GPL(kvm_queue_exception); 893 894 void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr) 895 { 896 kvm_multiple_exception(vcpu, nr, false, 0, false, 0, true); 897 } 898 EXPORT_SYMBOL_GPL(kvm_requeue_exception); 899 900 void kvm_queue_exception_p(struct kvm_vcpu *vcpu, unsigned nr, 901 unsigned long payload) 902 { 903 kvm_multiple_exception(vcpu, nr, false, 0, true, payload, false); 904 } 905 EXPORT_SYMBOL_GPL(kvm_queue_exception_p); 906 907 static void kvm_queue_exception_e_p(struct kvm_vcpu *vcpu, unsigned nr, 908 u32 error_code, unsigned long payload) 909 { 910 kvm_multiple_exception(vcpu, nr, true, error_code, 911 true, payload, false); 912 } 913 914 int kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err) 915 { 916 if (err) 917 kvm_inject_gp(vcpu, 0); 918 else 919 return kvm_skip_emulated_instruction(vcpu); 920 921 return 1; 922 } 923 EXPORT_SYMBOL_GPL(kvm_complete_insn_gp); 924 925 static int complete_emulated_insn_gp(struct kvm_vcpu *vcpu, int err) 926 { 927 if (err) { 928 kvm_inject_gp(vcpu, 0); 929 return 1; 930 } 931 932 return kvm_emulate_instruction(vcpu, EMULTYPE_NO_DECODE | EMULTYPE_SKIP | 933 EMULTYPE_COMPLETE_USER_EXIT); 934 } 935 936 void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault) 937 { 938 ++vcpu->stat.pf_guest; 939 940 /* 941 * Async #PF in L2 is always forwarded to L1 as a VM-Exit regardless of 942 * whether or not L1 wants to intercept "regular" #PF. 943 */ 944 if (is_guest_mode(vcpu) && fault->async_page_fault) 945 kvm_queue_exception_vmexit(vcpu, PF_VECTOR, 946 true, fault->error_code, 947 true, fault->address); 948 else 949 kvm_queue_exception_e_p(vcpu, PF_VECTOR, fault->error_code, 950 fault->address); 951 } 952 953 void kvm_inject_emulated_page_fault(struct kvm_vcpu *vcpu, 954 struct x86_exception *fault) 955 { 956 struct kvm_mmu *fault_mmu; 957 WARN_ON_ONCE(fault->vector != PF_VECTOR); 958 959 fault_mmu = fault->nested_page_fault ? vcpu->arch.mmu : 960 vcpu->arch.walk_mmu; 961 962 /* 963 * Invalidate the TLB entry for the faulting address, if it exists, 964 * else the access will fault indefinitely (and to emulate hardware). 965 */ 966 if ((fault->error_code & PFERR_PRESENT_MASK) && 967 !(fault->error_code & PFERR_RSVD_MASK)) 968 kvm_mmu_invalidate_addr(vcpu, fault_mmu, fault->address, 969 KVM_MMU_ROOT_CURRENT); 970 971 fault_mmu->inject_page_fault(vcpu, fault); 972 } 973 EXPORT_SYMBOL_GPL(kvm_inject_emulated_page_fault); 974 975 void kvm_inject_nmi(struct kvm_vcpu *vcpu) 976 { 977 atomic_inc(&vcpu->arch.nmi_queued); 978 kvm_make_request(KVM_REQ_NMI, vcpu); 979 } 980 981 void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code) 982 { 983 kvm_multiple_exception(vcpu, nr, true, error_code, false, 0, false); 984 } 985 EXPORT_SYMBOL_GPL(kvm_queue_exception_e); 986 987 void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code) 988 { 989 kvm_multiple_exception(vcpu, nr, true, error_code, false, 0, true); 990 } 991 EXPORT_SYMBOL_GPL(kvm_requeue_exception_e); 992 993 /* 994 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue 995 * a #GP and return false. 996 */ 997 bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl) 998 { 999 if (kvm_x86_call(get_cpl)(vcpu) <= required_cpl) 1000 return true; 1001 kvm_queue_exception_e(vcpu, GP_VECTOR, 0); 1002 return false; 1003 } 1004 1005 bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr) 1006 { 1007 if ((dr != 4 && dr != 5) || !kvm_is_cr4_bit_set(vcpu, X86_CR4_DE)) 1008 return true; 1009 1010 kvm_queue_exception(vcpu, UD_VECTOR); 1011 return false; 1012 } 1013 EXPORT_SYMBOL_GPL(kvm_require_dr); 1014 1015 static inline u64 pdptr_rsvd_bits(struct kvm_vcpu *vcpu) 1016 { 1017 return vcpu->arch.reserved_gpa_bits | rsvd_bits(5, 8) | rsvd_bits(1, 2); 1018 } 1019 1020 /* 1021 * Load the pae pdptrs. Return 1 if they are all valid, 0 otherwise. 1022 */ 1023 int load_pdptrs(struct kvm_vcpu *vcpu, unsigned long cr3) 1024 { 1025 struct kvm_mmu *mmu = vcpu->arch.walk_mmu; 1026 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT; 1027 gpa_t real_gpa; 1028 int i; 1029 int ret; 1030 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)]; 1031 1032 /* 1033 * If the MMU is nested, CR3 holds an L2 GPA and needs to be translated 1034 * to an L1 GPA. 1035 */ 1036 real_gpa = kvm_translate_gpa(vcpu, mmu, gfn_to_gpa(pdpt_gfn), 1037 PFERR_USER_MASK | PFERR_WRITE_MASK, NULL); 1038 if (real_gpa == INVALID_GPA) 1039 return 0; 1040 1041 /* Note the offset, PDPTRs are 32 byte aligned when using PAE paging. */ 1042 ret = kvm_vcpu_read_guest_page(vcpu, gpa_to_gfn(real_gpa), pdpte, 1043 cr3 & GENMASK(11, 5), sizeof(pdpte)); 1044 if (ret < 0) 1045 return 0; 1046 1047 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) { 1048 if ((pdpte[i] & PT_PRESENT_MASK) && 1049 (pdpte[i] & pdptr_rsvd_bits(vcpu))) { 1050 return 0; 1051 } 1052 } 1053 1054 /* 1055 * Marking VCPU_EXREG_PDPTR dirty doesn't work for !tdp_enabled. 1056 * Shadow page roots need to be reconstructed instead. 1057 */ 1058 if (!tdp_enabled && memcmp(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs))) 1059 kvm_mmu_free_roots(vcpu->kvm, mmu, KVM_MMU_ROOT_CURRENT); 1060 1061 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs)); 1062 kvm_register_mark_dirty(vcpu, VCPU_EXREG_PDPTR); 1063 kvm_make_request(KVM_REQ_LOAD_MMU_PGD, vcpu); 1064 vcpu->arch.pdptrs_from_userspace = false; 1065 1066 return 1; 1067 } 1068 EXPORT_SYMBOL_GPL(load_pdptrs); 1069 1070 static bool kvm_is_valid_cr0(struct kvm_vcpu *vcpu, unsigned long cr0) 1071 { 1072 #ifdef CONFIG_X86_64 1073 if (cr0 & 0xffffffff00000000UL) 1074 return false; 1075 #endif 1076 1077 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD)) 1078 return false; 1079 1080 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE)) 1081 return false; 1082 1083 return kvm_x86_call(is_valid_cr0)(vcpu, cr0); 1084 } 1085 1086 void kvm_post_set_cr0(struct kvm_vcpu *vcpu, unsigned long old_cr0, unsigned long cr0) 1087 { 1088 /* 1089 * CR0.WP is incorporated into the MMU role, but only for non-nested, 1090 * indirect shadow MMUs. If paging is disabled, no updates are needed 1091 * as there are no permission bits to emulate. If TDP is enabled, the 1092 * MMU's metadata needs to be updated, e.g. so that emulating guest 1093 * translations does the right thing, but there's no need to unload the 1094 * root as CR0.WP doesn't affect SPTEs. 1095 */ 1096 if ((cr0 ^ old_cr0) == X86_CR0_WP) { 1097 if (!(cr0 & X86_CR0_PG)) 1098 return; 1099 1100 if (tdp_enabled) { 1101 kvm_init_mmu(vcpu); 1102 return; 1103 } 1104 } 1105 1106 if ((cr0 ^ old_cr0) & X86_CR0_PG) { 1107 kvm_clear_async_pf_completion_queue(vcpu); 1108 kvm_async_pf_hash_reset(vcpu); 1109 1110 /* 1111 * Clearing CR0.PG is defined to flush the TLB from the guest's 1112 * perspective. 1113 */ 1114 if (!(cr0 & X86_CR0_PG)) 1115 kvm_make_request(KVM_REQ_TLB_FLUSH_GUEST, vcpu); 1116 } 1117 1118 if ((cr0 ^ old_cr0) & KVM_MMU_CR0_ROLE_BITS) 1119 kvm_mmu_reset_context(vcpu); 1120 } 1121 EXPORT_SYMBOL_GPL(kvm_post_set_cr0); 1122 1123 int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0) 1124 { 1125 unsigned long old_cr0 = kvm_read_cr0(vcpu); 1126 1127 if (!kvm_is_valid_cr0(vcpu, cr0)) 1128 return 1; 1129 1130 cr0 |= X86_CR0_ET; 1131 1132 /* Write to CR0 reserved bits are ignored, even on Intel. */ 1133 cr0 &= ~CR0_RESERVED_BITS; 1134 1135 #ifdef CONFIG_X86_64 1136 if ((vcpu->arch.efer & EFER_LME) && !is_paging(vcpu) && 1137 (cr0 & X86_CR0_PG)) { 1138 int cs_db, cs_l; 1139 1140 if (!is_pae(vcpu)) 1141 return 1; 1142 kvm_x86_call(get_cs_db_l_bits)(vcpu, &cs_db, &cs_l); 1143 if (cs_l) 1144 return 1; 1145 } 1146 #endif 1147 if (!(vcpu->arch.efer & EFER_LME) && (cr0 & X86_CR0_PG) && 1148 is_pae(vcpu) && ((cr0 ^ old_cr0) & X86_CR0_PDPTR_BITS) && 1149 !load_pdptrs(vcpu, kvm_read_cr3(vcpu))) 1150 return 1; 1151 1152 if (!(cr0 & X86_CR0_PG) && 1153 (is_64_bit_mode(vcpu) || kvm_is_cr4_bit_set(vcpu, X86_CR4_PCIDE))) 1154 return 1; 1155 1156 kvm_x86_call(set_cr0)(vcpu, cr0); 1157 1158 kvm_post_set_cr0(vcpu, old_cr0, cr0); 1159 1160 return 0; 1161 } 1162 EXPORT_SYMBOL_GPL(kvm_set_cr0); 1163 1164 void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw) 1165 { 1166 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f)); 1167 } 1168 EXPORT_SYMBOL_GPL(kvm_lmsw); 1169 1170 void kvm_load_guest_xsave_state(struct kvm_vcpu *vcpu) 1171 { 1172 if (vcpu->arch.guest_state_protected) 1173 return; 1174 1175 if (kvm_is_cr4_bit_set(vcpu, X86_CR4_OSXSAVE)) { 1176 1177 if (vcpu->arch.xcr0 != kvm_host.xcr0) 1178 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0); 1179 1180 if (guest_cpu_cap_has(vcpu, X86_FEATURE_XSAVES) && 1181 vcpu->arch.ia32_xss != kvm_host.xss) 1182 wrmsrl(MSR_IA32_XSS, vcpu->arch.ia32_xss); 1183 } 1184 1185 if (cpu_feature_enabled(X86_FEATURE_PKU) && 1186 vcpu->arch.pkru != vcpu->arch.host_pkru && 1187 ((vcpu->arch.xcr0 & XFEATURE_MASK_PKRU) || 1188 kvm_is_cr4_bit_set(vcpu, X86_CR4_PKE))) 1189 wrpkru(vcpu->arch.pkru); 1190 } 1191 EXPORT_SYMBOL_GPL(kvm_load_guest_xsave_state); 1192 1193 void kvm_load_host_xsave_state(struct kvm_vcpu *vcpu) 1194 { 1195 if (vcpu->arch.guest_state_protected) 1196 return; 1197 1198 if (cpu_feature_enabled(X86_FEATURE_PKU) && 1199 ((vcpu->arch.xcr0 & XFEATURE_MASK_PKRU) || 1200 kvm_is_cr4_bit_set(vcpu, X86_CR4_PKE))) { 1201 vcpu->arch.pkru = rdpkru(); 1202 if (vcpu->arch.pkru != vcpu->arch.host_pkru) 1203 wrpkru(vcpu->arch.host_pkru); 1204 } 1205 1206 if (kvm_is_cr4_bit_set(vcpu, X86_CR4_OSXSAVE)) { 1207 1208 if (vcpu->arch.xcr0 != kvm_host.xcr0) 1209 xsetbv(XCR_XFEATURE_ENABLED_MASK, kvm_host.xcr0); 1210 1211 if (guest_cpu_cap_has(vcpu, X86_FEATURE_XSAVES) && 1212 vcpu->arch.ia32_xss != kvm_host.xss) 1213 wrmsrl(MSR_IA32_XSS, kvm_host.xss); 1214 } 1215 1216 } 1217 EXPORT_SYMBOL_GPL(kvm_load_host_xsave_state); 1218 1219 #ifdef CONFIG_X86_64 1220 static inline u64 kvm_guest_supported_xfd(struct kvm_vcpu *vcpu) 1221 { 1222 return vcpu->arch.guest_supported_xcr0 & XFEATURE_MASK_USER_DYNAMIC; 1223 } 1224 #endif 1225 1226 static int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr) 1227 { 1228 u64 xcr0 = xcr; 1229 u64 old_xcr0 = vcpu->arch.xcr0; 1230 u64 valid_bits; 1231 1232 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */ 1233 if (index != XCR_XFEATURE_ENABLED_MASK) 1234 return 1; 1235 if (!(xcr0 & XFEATURE_MASK_FP)) 1236 return 1; 1237 if ((xcr0 & XFEATURE_MASK_YMM) && !(xcr0 & XFEATURE_MASK_SSE)) 1238 return 1; 1239 1240 /* 1241 * Do not allow the guest to set bits that we do not support 1242 * saving. However, xcr0 bit 0 is always set, even if the 1243 * emulated CPU does not support XSAVE (see kvm_vcpu_reset()). 1244 */ 1245 valid_bits = vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FP; 1246 if (xcr0 & ~valid_bits) 1247 return 1; 1248 1249 if ((!(xcr0 & XFEATURE_MASK_BNDREGS)) != 1250 (!(xcr0 & XFEATURE_MASK_BNDCSR))) 1251 return 1; 1252 1253 if (xcr0 & XFEATURE_MASK_AVX512) { 1254 if (!(xcr0 & XFEATURE_MASK_YMM)) 1255 return 1; 1256 if ((xcr0 & XFEATURE_MASK_AVX512) != XFEATURE_MASK_AVX512) 1257 return 1; 1258 } 1259 1260 if ((xcr0 & XFEATURE_MASK_XTILE) && 1261 ((xcr0 & XFEATURE_MASK_XTILE) != XFEATURE_MASK_XTILE)) 1262 return 1; 1263 1264 vcpu->arch.xcr0 = xcr0; 1265 1266 if ((xcr0 ^ old_xcr0) & XFEATURE_MASK_EXTEND) 1267 kvm_update_cpuid_runtime(vcpu); 1268 return 0; 1269 } 1270 1271 int kvm_emulate_xsetbv(struct kvm_vcpu *vcpu) 1272 { 1273 /* Note, #UD due to CR4.OSXSAVE=0 has priority over the intercept. */ 1274 if (kvm_x86_call(get_cpl)(vcpu) != 0 || 1275 __kvm_set_xcr(vcpu, kvm_rcx_read(vcpu), kvm_read_edx_eax(vcpu))) { 1276 kvm_inject_gp(vcpu, 0); 1277 return 1; 1278 } 1279 1280 return kvm_skip_emulated_instruction(vcpu); 1281 } 1282 EXPORT_SYMBOL_GPL(kvm_emulate_xsetbv); 1283 1284 static bool kvm_is_valid_cr4(struct kvm_vcpu *vcpu, unsigned long cr4) 1285 { 1286 return __kvm_is_valid_cr4(vcpu, cr4) && 1287 kvm_x86_call(is_valid_cr4)(vcpu, cr4); 1288 } 1289 1290 void kvm_post_set_cr4(struct kvm_vcpu *vcpu, unsigned long old_cr4, unsigned long cr4) 1291 { 1292 if ((cr4 ^ old_cr4) & KVM_MMU_CR4_ROLE_BITS) 1293 kvm_mmu_reset_context(vcpu); 1294 1295 /* 1296 * If CR4.PCIDE is changed 0 -> 1, there is no need to flush the TLB 1297 * according to the SDM; however, stale prev_roots could be reused 1298 * incorrectly in the future after a MOV to CR3 with NOFLUSH=1, so we 1299 * free them all. This is *not* a superset of KVM_REQ_TLB_FLUSH_GUEST 1300 * or KVM_REQ_TLB_FLUSH_CURRENT, because the hardware TLB is not flushed, 1301 * so fall through. 1302 */ 1303 if (!tdp_enabled && 1304 (cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) 1305 kvm_mmu_unload(vcpu); 1306 1307 /* 1308 * The TLB has to be flushed for all PCIDs if any of the following 1309 * (architecturally required) changes happen: 1310 * - CR4.PCIDE is changed from 1 to 0 1311 * - CR4.PGE is toggled 1312 * 1313 * This is a superset of KVM_REQ_TLB_FLUSH_CURRENT. 1314 */ 1315 if (((cr4 ^ old_cr4) & X86_CR4_PGE) || 1316 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE))) 1317 kvm_make_request(KVM_REQ_TLB_FLUSH_GUEST, vcpu); 1318 1319 /* 1320 * The TLB has to be flushed for the current PCID if any of the 1321 * following (architecturally required) changes happen: 1322 * - CR4.SMEP is changed from 0 to 1 1323 * - CR4.PAE is toggled 1324 */ 1325 else if (((cr4 ^ old_cr4) & X86_CR4_PAE) || 1326 ((cr4 & X86_CR4_SMEP) && !(old_cr4 & X86_CR4_SMEP))) 1327 kvm_make_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu); 1328 1329 } 1330 EXPORT_SYMBOL_GPL(kvm_post_set_cr4); 1331 1332 int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4) 1333 { 1334 unsigned long old_cr4 = kvm_read_cr4(vcpu); 1335 1336 if (!kvm_is_valid_cr4(vcpu, cr4)) 1337 return 1; 1338 1339 if (is_long_mode(vcpu)) { 1340 if (!(cr4 & X86_CR4_PAE)) 1341 return 1; 1342 if ((cr4 ^ old_cr4) & X86_CR4_LA57) 1343 return 1; 1344 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE) 1345 && ((cr4 ^ old_cr4) & X86_CR4_PDPTR_BITS) 1346 && !load_pdptrs(vcpu, kvm_read_cr3(vcpu))) 1347 return 1; 1348 1349 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) { 1350 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */ 1351 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu)) 1352 return 1; 1353 } 1354 1355 kvm_x86_call(set_cr4)(vcpu, cr4); 1356 1357 kvm_post_set_cr4(vcpu, old_cr4, cr4); 1358 1359 return 0; 1360 } 1361 EXPORT_SYMBOL_GPL(kvm_set_cr4); 1362 1363 static void kvm_invalidate_pcid(struct kvm_vcpu *vcpu, unsigned long pcid) 1364 { 1365 struct kvm_mmu *mmu = vcpu->arch.mmu; 1366 unsigned long roots_to_free = 0; 1367 int i; 1368 1369 /* 1370 * MOV CR3 and INVPCID are usually not intercepted when using TDP, but 1371 * this is reachable when running EPT=1 and unrestricted_guest=0, and 1372 * also via the emulator. KVM's TDP page tables are not in the scope of 1373 * the invalidation, but the guest's TLB entries need to be flushed as 1374 * the CPU may have cached entries in its TLB for the target PCID. 1375 */ 1376 if (unlikely(tdp_enabled)) { 1377 kvm_make_request(KVM_REQ_TLB_FLUSH_GUEST, vcpu); 1378 return; 1379 } 1380 1381 /* 1382 * If neither the current CR3 nor any of the prev_roots use the given 1383 * PCID, then nothing needs to be done here because a resync will 1384 * happen anyway before switching to any other CR3. 1385 */ 1386 if (kvm_get_active_pcid(vcpu) == pcid) { 1387 kvm_make_request(KVM_REQ_MMU_SYNC, vcpu); 1388 kvm_make_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu); 1389 } 1390 1391 /* 1392 * If PCID is disabled, there is no need to free prev_roots even if the 1393 * PCIDs for them are also 0, because MOV to CR3 always flushes the TLB 1394 * with PCIDE=0. 1395 */ 1396 if (!kvm_is_cr4_bit_set(vcpu, X86_CR4_PCIDE)) 1397 return; 1398 1399 for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++) 1400 if (kvm_get_pcid(vcpu, mmu->prev_roots[i].pgd) == pcid) 1401 roots_to_free |= KVM_MMU_ROOT_PREVIOUS(i); 1402 1403 kvm_mmu_free_roots(vcpu->kvm, mmu, roots_to_free); 1404 } 1405 1406 int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3) 1407 { 1408 bool skip_tlb_flush = false; 1409 unsigned long pcid = 0; 1410 #ifdef CONFIG_X86_64 1411 if (kvm_is_cr4_bit_set(vcpu, X86_CR4_PCIDE)) { 1412 skip_tlb_flush = cr3 & X86_CR3_PCID_NOFLUSH; 1413 cr3 &= ~X86_CR3_PCID_NOFLUSH; 1414 pcid = cr3 & X86_CR3_PCID_MASK; 1415 } 1416 #endif 1417 1418 /* PDPTRs are always reloaded for PAE paging. */ 1419 if (cr3 == kvm_read_cr3(vcpu) && !is_pae_paging(vcpu)) 1420 goto handle_tlb_flush; 1421 1422 /* 1423 * Do not condition the GPA check on long mode, this helper is used to 1424 * stuff CR3, e.g. for RSM emulation, and there is no guarantee that 1425 * the current vCPU mode is accurate. 1426 */ 1427 if (!kvm_vcpu_is_legal_cr3(vcpu, cr3)) 1428 return 1; 1429 1430 if (is_pae_paging(vcpu) && !load_pdptrs(vcpu, cr3)) 1431 return 1; 1432 1433 if (cr3 != kvm_read_cr3(vcpu)) 1434 kvm_mmu_new_pgd(vcpu, cr3); 1435 1436 vcpu->arch.cr3 = cr3; 1437 kvm_register_mark_dirty(vcpu, VCPU_EXREG_CR3); 1438 /* Do not call post_set_cr3, we do not get here for confidential guests. */ 1439 1440 handle_tlb_flush: 1441 /* 1442 * A load of CR3 that flushes the TLB flushes only the current PCID, 1443 * even if PCID is disabled, in which case PCID=0 is flushed. It's a 1444 * moot point in the end because _disabling_ PCID will flush all PCIDs, 1445 * and it's impossible to use a non-zero PCID when PCID is disabled, 1446 * i.e. only PCID=0 can be relevant. 1447 */ 1448 if (!skip_tlb_flush) 1449 kvm_invalidate_pcid(vcpu, pcid); 1450 1451 return 0; 1452 } 1453 EXPORT_SYMBOL_GPL(kvm_set_cr3); 1454 1455 int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8) 1456 { 1457 if (cr8 & CR8_RESERVED_BITS) 1458 return 1; 1459 if (lapic_in_kernel(vcpu)) 1460 kvm_lapic_set_tpr(vcpu, cr8); 1461 else 1462 vcpu->arch.cr8 = cr8; 1463 return 0; 1464 } 1465 EXPORT_SYMBOL_GPL(kvm_set_cr8); 1466 1467 unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu) 1468 { 1469 if (lapic_in_kernel(vcpu)) 1470 return kvm_lapic_get_cr8(vcpu); 1471 else 1472 return vcpu->arch.cr8; 1473 } 1474 EXPORT_SYMBOL_GPL(kvm_get_cr8); 1475 1476 static void kvm_update_dr0123(struct kvm_vcpu *vcpu) 1477 { 1478 int i; 1479 1480 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) { 1481 for (i = 0; i < KVM_NR_DB_REGS; i++) 1482 vcpu->arch.eff_db[i] = vcpu->arch.db[i]; 1483 } 1484 } 1485 1486 void kvm_update_dr7(struct kvm_vcpu *vcpu) 1487 { 1488 unsigned long dr7; 1489 1490 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) 1491 dr7 = vcpu->arch.guest_debug_dr7; 1492 else 1493 dr7 = vcpu->arch.dr7; 1494 kvm_x86_call(set_dr7)(vcpu, dr7); 1495 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED; 1496 if (dr7 & DR7_BP_EN_MASK) 1497 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED; 1498 } 1499 EXPORT_SYMBOL_GPL(kvm_update_dr7); 1500 1501 static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu) 1502 { 1503 u64 fixed = DR6_FIXED_1; 1504 1505 if (!guest_cpu_cap_has(vcpu, X86_FEATURE_RTM)) 1506 fixed |= DR6_RTM; 1507 1508 if (!guest_cpu_cap_has(vcpu, X86_FEATURE_BUS_LOCK_DETECT)) 1509 fixed |= DR6_BUS_LOCK; 1510 return fixed; 1511 } 1512 1513 int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val) 1514 { 1515 size_t size = ARRAY_SIZE(vcpu->arch.db); 1516 1517 switch (dr) { 1518 case 0 ... 3: 1519 vcpu->arch.db[array_index_nospec(dr, size)] = val; 1520 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) 1521 vcpu->arch.eff_db[dr] = val; 1522 break; 1523 case 4: 1524 case 6: 1525 if (!kvm_dr6_valid(val)) 1526 return 1; /* #GP */ 1527 vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu); 1528 break; 1529 case 5: 1530 default: /* 7 */ 1531 if (!kvm_dr7_valid(val)) 1532 return 1; /* #GP */ 1533 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1; 1534 kvm_update_dr7(vcpu); 1535 break; 1536 } 1537 1538 return 0; 1539 } 1540 EXPORT_SYMBOL_GPL(kvm_set_dr); 1541 1542 unsigned long kvm_get_dr(struct kvm_vcpu *vcpu, int dr) 1543 { 1544 size_t size = ARRAY_SIZE(vcpu->arch.db); 1545 1546 switch (dr) { 1547 case 0 ... 3: 1548 return vcpu->arch.db[array_index_nospec(dr, size)]; 1549 case 4: 1550 case 6: 1551 return vcpu->arch.dr6; 1552 case 5: 1553 default: /* 7 */ 1554 return vcpu->arch.dr7; 1555 } 1556 } 1557 EXPORT_SYMBOL_GPL(kvm_get_dr); 1558 1559 int kvm_emulate_rdpmc(struct kvm_vcpu *vcpu) 1560 { 1561 u32 ecx = kvm_rcx_read(vcpu); 1562 u64 data; 1563 1564 if (kvm_pmu_rdpmc(vcpu, ecx, &data)) { 1565 kvm_inject_gp(vcpu, 0); 1566 return 1; 1567 } 1568 1569 kvm_rax_write(vcpu, (u32)data); 1570 kvm_rdx_write(vcpu, data >> 32); 1571 return kvm_skip_emulated_instruction(vcpu); 1572 } 1573 EXPORT_SYMBOL_GPL(kvm_emulate_rdpmc); 1574 1575 /* 1576 * Some IA32_ARCH_CAPABILITIES bits have dependencies on MSRs that KVM 1577 * does not yet virtualize. These include: 1578 * 10 - MISC_PACKAGE_CTRLS 1579 * 11 - ENERGY_FILTERING_CTL 1580 * 12 - DOITM 1581 * 18 - FB_CLEAR_CTRL 1582 * 21 - XAPIC_DISABLE_STATUS 1583 * 23 - OVERCLOCKING_STATUS 1584 */ 1585 1586 #define KVM_SUPPORTED_ARCH_CAP \ 1587 (ARCH_CAP_RDCL_NO | ARCH_CAP_IBRS_ALL | ARCH_CAP_RSBA | \ 1588 ARCH_CAP_SKIP_VMENTRY_L1DFLUSH | ARCH_CAP_SSB_NO | ARCH_CAP_MDS_NO | \ 1589 ARCH_CAP_PSCHANGE_MC_NO | ARCH_CAP_TSX_CTRL_MSR | ARCH_CAP_TAA_NO | \ 1590 ARCH_CAP_SBDR_SSDP_NO | ARCH_CAP_FBSDP_NO | ARCH_CAP_PSDP_NO | \ 1591 ARCH_CAP_FB_CLEAR | ARCH_CAP_RRSBA | ARCH_CAP_PBRSB_NO | ARCH_CAP_GDS_NO | \ 1592 ARCH_CAP_RFDS_NO | ARCH_CAP_RFDS_CLEAR | ARCH_CAP_BHI_NO) 1593 1594 static u64 kvm_get_arch_capabilities(void) 1595 { 1596 u64 data = kvm_host.arch_capabilities & KVM_SUPPORTED_ARCH_CAP; 1597 1598 /* 1599 * If nx_huge_pages is enabled, KVM's shadow paging will ensure that 1600 * the nested hypervisor runs with NX huge pages. If it is not, 1601 * L1 is anyway vulnerable to ITLB_MULTIHIT exploits from other 1602 * L1 guests, so it need not worry about its own (L2) guests. 1603 */ 1604 data |= ARCH_CAP_PSCHANGE_MC_NO; 1605 1606 /* 1607 * If we're doing cache flushes (either "always" or "cond") 1608 * we will do one whenever the guest does a vmlaunch/vmresume. 1609 * If an outer hypervisor is doing the cache flush for us 1610 * (ARCH_CAP_SKIP_VMENTRY_L1DFLUSH), we can safely pass that 1611 * capability to the guest too, and if EPT is disabled we're not 1612 * vulnerable. Overall, only VMENTER_L1D_FLUSH_NEVER will 1613 * require a nested hypervisor to do a flush of its own. 1614 */ 1615 if (l1tf_vmx_mitigation != VMENTER_L1D_FLUSH_NEVER) 1616 data |= ARCH_CAP_SKIP_VMENTRY_L1DFLUSH; 1617 1618 if (!boot_cpu_has_bug(X86_BUG_CPU_MELTDOWN)) 1619 data |= ARCH_CAP_RDCL_NO; 1620 if (!boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS)) 1621 data |= ARCH_CAP_SSB_NO; 1622 if (!boot_cpu_has_bug(X86_BUG_MDS)) 1623 data |= ARCH_CAP_MDS_NO; 1624 if (!boot_cpu_has_bug(X86_BUG_RFDS)) 1625 data |= ARCH_CAP_RFDS_NO; 1626 1627 if (!boot_cpu_has(X86_FEATURE_RTM)) { 1628 /* 1629 * If RTM=0 because the kernel has disabled TSX, the host might 1630 * have TAA_NO or TSX_CTRL. Clear TAA_NO (the guest sees RTM=0 1631 * and therefore knows that there cannot be TAA) but keep 1632 * TSX_CTRL: some buggy userspaces leave it set on tsx=on hosts, 1633 * and we want to allow migrating those guests to tsx=off hosts. 1634 */ 1635 data &= ~ARCH_CAP_TAA_NO; 1636 } else if (!boot_cpu_has_bug(X86_BUG_TAA)) { 1637 data |= ARCH_CAP_TAA_NO; 1638 } else { 1639 /* 1640 * Nothing to do here; we emulate TSX_CTRL if present on the 1641 * host so the guest can choose between disabling TSX or 1642 * using VERW to clear CPU buffers. 1643 */ 1644 } 1645 1646 if (!boot_cpu_has_bug(X86_BUG_GDS) || gds_ucode_mitigated()) 1647 data |= ARCH_CAP_GDS_NO; 1648 1649 return data; 1650 } 1651 1652 static int kvm_get_feature_msr(struct kvm_vcpu *vcpu, u32 index, u64 *data, 1653 bool host_initiated) 1654 { 1655 WARN_ON_ONCE(!host_initiated); 1656 1657 switch (index) { 1658 case MSR_IA32_ARCH_CAPABILITIES: 1659 *data = kvm_get_arch_capabilities(); 1660 break; 1661 case MSR_IA32_PERF_CAPABILITIES: 1662 *data = kvm_caps.supported_perf_cap; 1663 break; 1664 case MSR_PLATFORM_INFO: 1665 *data = MSR_PLATFORM_INFO_CPUID_FAULT; 1666 break; 1667 case MSR_IA32_UCODE_REV: 1668 rdmsrl_safe(index, data); 1669 break; 1670 default: 1671 return kvm_x86_call(get_feature_msr)(index, data); 1672 } 1673 return 0; 1674 } 1675 1676 static int do_get_feature_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data) 1677 { 1678 return kvm_do_msr_access(vcpu, index, data, true, MSR_TYPE_R, 1679 kvm_get_feature_msr); 1680 } 1681 1682 static bool __kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer) 1683 { 1684 if (efer & EFER_AUTOIBRS && !guest_cpu_cap_has(vcpu, X86_FEATURE_AUTOIBRS)) 1685 return false; 1686 1687 if (efer & EFER_FFXSR && !guest_cpu_cap_has(vcpu, X86_FEATURE_FXSR_OPT)) 1688 return false; 1689 1690 if (efer & EFER_SVME && !guest_cpu_cap_has(vcpu, X86_FEATURE_SVM)) 1691 return false; 1692 1693 if (efer & (EFER_LME | EFER_LMA) && 1694 !guest_cpu_cap_has(vcpu, X86_FEATURE_LM)) 1695 return false; 1696 1697 if (efer & EFER_NX && !guest_cpu_cap_has(vcpu, X86_FEATURE_NX)) 1698 return false; 1699 1700 return true; 1701 1702 } 1703 bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer) 1704 { 1705 if (efer & efer_reserved_bits) 1706 return false; 1707 1708 return __kvm_valid_efer(vcpu, efer); 1709 } 1710 EXPORT_SYMBOL_GPL(kvm_valid_efer); 1711 1712 static int set_efer(struct kvm_vcpu *vcpu, struct msr_data *msr_info) 1713 { 1714 u64 old_efer = vcpu->arch.efer; 1715 u64 efer = msr_info->data; 1716 int r; 1717 1718 if (efer & efer_reserved_bits) 1719 return 1; 1720 1721 if (!msr_info->host_initiated) { 1722 if (!__kvm_valid_efer(vcpu, efer)) 1723 return 1; 1724 1725 if (is_paging(vcpu) && 1726 (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME)) 1727 return 1; 1728 } 1729 1730 efer &= ~EFER_LMA; 1731 efer |= vcpu->arch.efer & EFER_LMA; 1732 1733 r = kvm_x86_call(set_efer)(vcpu, efer); 1734 if (r) { 1735 WARN_ON(r > 0); 1736 return r; 1737 } 1738 1739 if ((efer ^ old_efer) & KVM_MMU_EFER_ROLE_BITS) 1740 kvm_mmu_reset_context(vcpu); 1741 1742 if (!static_cpu_has(X86_FEATURE_XSAVES) && 1743 (efer & EFER_SVME)) 1744 kvm_hv_xsaves_xsavec_maybe_warn(vcpu); 1745 1746 return 0; 1747 } 1748 1749 void kvm_enable_efer_bits(u64 mask) 1750 { 1751 efer_reserved_bits &= ~mask; 1752 } 1753 EXPORT_SYMBOL_GPL(kvm_enable_efer_bits); 1754 1755 bool kvm_msr_allowed(struct kvm_vcpu *vcpu, u32 index, u32 type) 1756 { 1757 struct kvm_x86_msr_filter *msr_filter; 1758 struct msr_bitmap_range *ranges; 1759 struct kvm *kvm = vcpu->kvm; 1760 bool allowed; 1761 int idx; 1762 u32 i; 1763 1764 /* x2APIC MSRs do not support filtering. */ 1765 if (index >= 0x800 && index <= 0x8ff) 1766 return true; 1767 1768 idx = srcu_read_lock(&kvm->srcu); 1769 1770 msr_filter = srcu_dereference(kvm->arch.msr_filter, &kvm->srcu); 1771 if (!msr_filter) { 1772 allowed = true; 1773 goto out; 1774 } 1775 1776 allowed = msr_filter->default_allow; 1777 ranges = msr_filter->ranges; 1778 1779 for (i = 0; i < msr_filter->count; i++) { 1780 u32 start = ranges[i].base; 1781 u32 end = start + ranges[i].nmsrs; 1782 u32 flags = ranges[i].flags; 1783 unsigned long *bitmap = ranges[i].bitmap; 1784 1785 if ((index >= start) && (index < end) && (flags & type)) { 1786 allowed = test_bit(index - start, bitmap); 1787 break; 1788 } 1789 } 1790 1791 out: 1792 srcu_read_unlock(&kvm->srcu, idx); 1793 1794 return allowed; 1795 } 1796 EXPORT_SYMBOL_GPL(kvm_msr_allowed); 1797 1798 /* 1799 * Write @data into the MSR specified by @index. Select MSR specific fault 1800 * checks are bypassed if @host_initiated is %true. 1801 * Returns 0 on success, non-0 otherwise. 1802 * Assumes vcpu_load() was already called. 1803 */ 1804 static int __kvm_set_msr(struct kvm_vcpu *vcpu, u32 index, u64 data, 1805 bool host_initiated) 1806 { 1807 struct msr_data msr; 1808 1809 switch (index) { 1810 case MSR_FS_BASE: 1811 case MSR_GS_BASE: 1812 case MSR_KERNEL_GS_BASE: 1813 case MSR_CSTAR: 1814 case MSR_LSTAR: 1815 if (is_noncanonical_msr_address(data, vcpu)) 1816 return 1; 1817 break; 1818 case MSR_IA32_SYSENTER_EIP: 1819 case MSR_IA32_SYSENTER_ESP: 1820 /* 1821 * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if 1822 * non-canonical address is written on Intel but not on 1823 * AMD (which ignores the top 32-bits, because it does 1824 * not implement 64-bit SYSENTER). 1825 * 1826 * 64-bit code should hence be able to write a non-canonical 1827 * value on AMD. Making the address canonical ensures that 1828 * vmentry does not fail on Intel after writing a non-canonical 1829 * value, and that something deterministic happens if the guest 1830 * invokes 64-bit SYSENTER. 1831 */ 1832 data = __canonical_address(data, max_host_virt_addr_bits()); 1833 break; 1834 case MSR_TSC_AUX: 1835 if (!kvm_is_supported_user_return_msr(MSR_TSC_AUX)) 1836 return 1; 1837 1838 if (!host_initiated && 1839 !guest_cpu_cap_has(vcpu, X86_FEATURE_RDTSCP) && 1840 !guest_cpu_cap_has(vcpu, X86_FEATURE_RDPID)) 1841 return 1; 1842 1843 /* 1844 * Per Intel's SDM, bits 63:32 are reserved, but AMD's APM has 1845 * incomplete and conflicting architectural behavior. Current 1846 * AMD CPUs completely ignore bits 63:32, i.e. they aren't 1847 * reserved and always read as zeros. Enforce Intel's reserved 1848 * bits check if the guest CPU is Intel compatible, otherwise 1849 * clear the bits. This ensures cross-vendor migration will 1850 * provide consistent behavior for the guest. 1851 */ 1852 if (guest_cpuid_is_intel_compatible(vcpu) && (data >> 32) != 0) 1853 return 1; 1854 1855 data = (u32)data; 1856 break; 1857 } 1858 1859 msr.data = data; 1860 msr.index = index; 1861 msr.host_initiated = host_initiated; 1862 1863 return kvm_x86_call(set_msr)(vcpu, &msr); 1864 } 1865 1866 static int _kvm_set_msr(struct kvm_vcpu *vcpu, u32 index, u64 *data, 1867 bool host_initiated) 1868 { 1869 return __kvm_set_msr(vcpu, index, *data, host_initiated); 1870 } 1871 1872 static int kvm_set_msr_ignored_check(struct kvm_vcpu *vcpu, 1873 u32 index, u64 data, bool host_initiated) 1874 { 1875 return kvm_do_msr_access(vcpu, index, &data, host_initiated, MSR_TYPE_W, 1876 _kvm_set_msr); 1877 } 1878 1879 /* 1880 * Read the MSR specified by @index into @data. Select MSR specific fault 1881 * checks are bypassed if @host_initiated is %true. 1882 * Returns 0 on success, non-0 otherwise. 1883 * Assumes vcpu_load() was already called. 1884 */ 1885 int __kvm_get_msr(struct kvm_vcpu *vcpu, u32 index, u64 *data, 1886 bool host_initiated) 1887 { 1888 struct msr_data msr; 1889 int ret; 1890 1891 switch (index) { 1892 case MSR_TSC_AUX: 1893 if (!kvm_is_supported_user_return_msr(MSR_TSC_AUX)) 1894 return 1; 1895 1896 if (!host_initiated && 1897 !guest_cpu_cap_has(vcpu, X86_FEATURE_RDTSCP) && 1898 !guest_cpu_cap_has(vcpu, X86_FEATURE_RDPID)) 1899 return 1; 1900 break; 1901 } 1902 1903 msr.index = index; 1904 msr.host_initiated = host_initiated; 1905 1906 ret = kvm_x86_call(get_msr)(vcpu, &msr); 1907 if (!ret) 1908 *data = msr.data; 1909 return ret; 1910 } 1911 1912 static int kvm_get_msr_ignored_check(struct kvm_vcpu *vcpu, 1913 u32 index, u64 *data, bool host_initiated) 1914 { 1915 return kvm_do_msr_access(vcpu, index, data, host_initiated, MSR_TYPE_R, 1916 __kvm_get_msr); 1917 } 1918 1919 int kvm_get_msr_with_filter(struct kvm_vcpu *vcpu, u32 index, u64 *data) 1920 { 1921 if (!kvm_msr_allowed(vcpu, index, KVM_MSR_FILTER_READ)) 1922 return KVM_MSR_RET_FILTERED; 1923 return kvm_get_msr_ignored_check(vcpu, index, data, false); 1924 } 1925 EXPORT_SYMBOL_GPL(kvm_get_msr_with_filter); 1926 1927 int kvm_set_msr_with_filter(struct kvm_vcpu *vcpu, u32 index, u64 data) 1928 { 1929 if (!kvm_msr_allowed(vcpu, index, KVM_MSR_FILTER_WRITE)) 1930 return KVM_MSR_RET_FILTERED; 1931 return kvm_set_msr_ignored_check(vcpu, index, data, false); 1932 } 1933 EXPORT_SYMBOL_GPL(kvm_set_msr_with_filter); 1934 1935 int kvm_get_msr(struct kvm_vcpu *vcpu, u32 index, u64 *data) 1936 { 1937 return kvm_get_msr_ignored_check(vcpu, index, data, false); 1938 } 1939 EXPORT_SYMBOL_GPL(kvm_get_msr); 1940 1941 int kvm_set_msr(struct kvm_vcpu *vcpu, u32 index, u64 data) 1942 { 1943 return kvm_set_msr_ignored_check(vcpu, index, data, false); 1944 } 1945 EXPORT_SYMBOL_GPL(kvm_set_msr); 1946 1947 static void complete_userspace_rdmsr(struct kvm_vcpu *vcpu) 1948 { 1949 if (!vcpu->run->msr.error) { 1950 kvm_rax_write(vcpu, (u32)vcpu->run->msr.data); 1951 kvm_rdx_write(vcpu, vcpu->run->msr.data >> 32); 1952 } 1953 } 1954 1955 static int complete_emulated_msr_access(struct kvm_vcpu *vcpu) 1956 { 1957 return complete_emulated_insn_gp(vcpu, vcpu->run->msr.error); 1958 } 1959 1960 static int complete_emulated_rdmsr(struct kvm_vcpu *vcpu) 1961 { 1962 complete_userspace_rdmsr(vcpu); 1963 return complete_emulated_msr_access(vcpu); 1964 } 1965 1966 static int complete_fast_msr_access(struct kvm_vcpu *vcpu) 1967 { 1968 return kvm_x86_call(complete_emulated_msr)(vcpu, vcpu->run->msr.error); 1969 } 1970 1971 static int complete_fast_rdmsr(struct kvm_vcpu *vcpu) 1972 { 1973 complete_userspace_rdmsr(vcpu); 1974 return complete_fast_msr_access(vcpu); 1975 } 1976 1977 static u64 kvm_msr_reason(int r) 1978 { 1979 switch (r) { 1980 case KVM_MSR_RET_UNSUPPORTED: 1981 return KVM_MSR_EXIT_REASON_UNKNOWN; 1982 case KVM_MSR_RET_FILTERED: 1983 return KVM_MSR_EXIT_REASON_FILTER; 1984 default: 1985 return KVM_MSR_EXIT_REASON_INVAL; 1986 } 1987 } 1988 1989 static int kvm_msr_user_space(struct kvm_vcpu *vcpu, u32 index, 1990 u32 exit_reason, u64 data, 1991 int (*completion)(struct kvm_vcpu *vcpu), 1992 int r) 1993 { 1994 u64 msr_reason = kvm_msr_reason(r); 1995 1996 /* Check if the user wanted to know about this MSR fault */ 1997 if (!(vcpu->kvm->arch.user_space_msr_mask & msr_reason)) 1998 return 0; 1999 2000 vcpu->run->exit_reason = exit_reason; 2001 vcpu->run->msr.error = 0; 2002 memset(vcpu->run->msr.pad, 0, sizeof(vcpu->run->msr.pad)); 2003 vcpu->run->msr.reason = msr_reason; 2004 vcpu->run->msr.index = index; 2005 vcpu->run->msr.data = data; 2006 vcpu->arch.complete_userspace_io = completion; 2007 2008 return 1; 2009 } 2010 2011 int kvm_emulate_rdmsr(struct kvm_vcpu *vcpu) 2012 { 2013 u32 ecx = kvm_rcx_read(vcpu); 2014 u64 data; 2015 int r; 2016 2017 r = kvm_get_msr_with_filter(vcpu, ecx, &data); 2018 2019 if (!r) { 2020 trace_kvm_msr_read(ecx, data); 2021 2022 kvm_rax_write(vcpu, data & -1u); 2023 kvm_rdx_write(vcpu, (data >> 32) & -1u); 2024 } else { 2025 /* MSR read failed? See if we should ask user space */ 2026 if (kvm_msr_user_space(vcpu, ecx, KVM_EXIT_X86_RDMSR, 0, 2027 complete_fast_rdmsr, r)) 2028 return 0; 2029 trace_kvm_msr_read_ex(ecx); 2030 } 2031 2032 return kvm_x86_call(complete_emulated_msr)(vcpu, r); 2033 } 2034 EXPORT_SYMBOL_GPL(kvm_emulate_rdmsr); 2035 2036 int kvm_emulate_wrmsr(struct kvm_vcpu *vcpu) 2037 { 2038 u32 ecx = kvm_rcx_read(vcpu); 2039 u64 data = kvm_read_edx_eax(vcpu); 2040 int r; 2041 2042 r = kvm_set_msr_with_filter(vcpu, ecx, data); 2043 2044 if (!r) { 2045 trace_kvm_msr_write(ecx, data); 2046 } else { 2047 /* MSR write failed? See if we should ask user space */ 2048 if (kvm_msr_user_space(vcpu, ecx, KVM_EXIT_X86_WRMSR, data, 2049 complete_fast_msr_access, r)) 2050 return 0; 2051 /* Signal all other negative errors to userspace */ 2052 if (r < 0) 2053 return r; 2054 trace_kvm_msr_write_ex(ecx, data); 2055 } 2056 2057 return kvm_x86_call(complete_emulated_msr)(vcpu, r); 2058 } 2059 EXPORT_SYMBOL_GPL(kvm_emulate_wrmsr); 2060 2061 int kvm_emulate_as_nop(struct kvm_vcpu *vcpu) 2062 { 2063 return kvm_skip_emulated_instruction(vcpu); 2064 } 2065 2066 int kvm_emulate_invd(struct kvm_vcpu *vcpu) 2067 { 2068 /* Treat an INVD instruction as a NOP and just skip it. */ 2069 return kvm_emulate_as_nop(vcpu); 2070 } 2071 EXPORT_SYMBOL_GPL(kvm_emulate_invd); 2072 2073 int kvm_handle_invalid_op(struct kvm_vcpu *vcpu) 2074 { 2075 kvm_queue_exception(vcpu, UD_VECTOR); 2076 return 1; 2077 } 2078 EXPORT_SYMBOL_GPL(kvm_handle_invalid_op); 2079 2080 2081 static int kvm_emulate_monitor_mwait(struct kvm_vcpu *vcpu, const char *insn) 2082 { 2083 if (!kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_MWAIT_NEVER_UD_FAULTS) && 2084 !guest_cpu_cap_has(vcpu, X86_FEATURE_MWAIT)) 2085 return kvm_handle_invalid_op(vcpu); 2086 2087 pr_warn_once("%s instruction emulated as NOP!\n", insn); 2088 return kvm_emulate_as_nop(vcpu); 2089 } 2090 int kvm_emulate_mwait(struct kvm_vcpu *vcpu) 2091 { 2092 return kvm_emulate_monitor_mwait(vcpu, "MWAIT"); 2093 } 2094 EXPORT_SYMBOL_GPL(kvm_emulate_mwait); 2095 2096 int kvm_emulate_monitor(struct kvm_vcpu *vcpu) 2097 { 2098 return kvm_emulate_monitor_mwait(vcpu, "MONITOR"); 2099 } 2100 EXPORT_SYMBOL_GPL(kvm_emulate_monitor); 2101 2102 static inline bool kvm_vcpu_exit_request(struct kvm_vcpu *vcpu) 2103 { 2104 xfer_to_guest_mode_prepare(); 2105 2106 return READ_ONCE(vcpu->mode) == EXITING_GUEST_MODE || 2107 kvm_request_pending(vcpu) || xfer_to_guest_mode_work_pending(); 2108 } 2109 2110 /* 2111 * The fast path for frequent and performance sensitive wrmsr emulation, 2112 * i.e. the sending of IPI, sending IPI early in the VM-Exit flow reduces 2113 * the latency of virtual IPI by avoiding the expensive bits of transitioning 2114 * from guest to host, e.g. reacquiring KVM's SRCU lock. In contrast to the 2115 * other cases which must be called after interrupts are enabled on the host. 2116 */ 2117 static int handle_fastpath_set_x2apic_icr_irqoff(struct kvm_vcpu *vcpu, u64 data) 2118 { 2119 if (!lapic_in_kernel(vcpu) || !apic_x2apic_mode(vcpu->arch.apic)) 2120 return 1; 2121 2122 if (((data & APIC_SHORT_MASK) == APIC_DEST_NOSHORT) && 2123 ((data & APIC_DEST_MASK) == APIC_DEST_PHYSICAL) && 2124 ((data & APIC_MODE_MASK) == APIC_DM_FIXED) && 2125 ((u32)(data >> 32) != X2APIC_BROADCAST)) 2126 return kvm_x2apic_icr_write(vcpu->arch.apic, data); 2127 2128 return 1; 2129 } 2130 2131 static int handle_fastpath_set_tscdeadline(struct kvm_vcpu *vcpu, u64 data) 2132 { 2133 if (!kvm_can_use_hv_timer(vcpu)) 2134 return 1; 2135 2136 kvm_set_lapic_tscdeadline_msr(vcpu, data); 2137 return 0; 2138 } 2139 2140 fastpath_t handle_fastpath_set_msr_irqoff(struct kvm_vcpu *vcpu) 2141 { 2142 u32 msr = kvm_rcx_read(vcpu); 2143 u64 data; 2144 fastpath_t ret; 2145 bool handled; 2146 2147 kvm_vcpu_srcu_read_lock(vcpu); 2148 2149 switch (msr) { 2150 case APIC_BASE_MSR + (APIC_ICR >> 4): 2151 data = kvm_read_edx_eax(vcpu); 2152 handled = !handle_fastpath_set_x2apic_icr_irqoff(vcpu, data); 2153 break; 2154 case MSR_IA32_TSC_DEADLINE: 2155 data = kvm_read_edx_eax(vcpu); 2156 handled = !handle_fastpath_set_tscdeadline(vcpu, data); 2157 break; 2158 default: 2159 handled = false; 2160 break; 2161 } 2162 2163 if (handled) { 2164 if (!kvm_skip_emulated_instruction(vcpu)) 2165 ret = EXIT_FASTPATH_EXIT_USERSPACE; 2166 else 2167 ret = EXIT_FASTPATH_REENTER_GUEST; 2168 trace_kvm_msr_write(msr, data); 2169 } else { 2170 ret = EXIT_FASTPATH_NONE; 2171 } 2172 2173 kvm_vcpu_srcu_read_unlock(vcpu); 2174 2175 return ret; 2176 } 2177 EXPORT_SYMBOL_GPL(handle_fastpath_set_msr_irqoff); 2178 2179 /* 2180 * Adapt set_msr() to msr_io()'s calling convention 2181 */ 2182 static int do_get_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data) 2183 { 2184 return kvm_get_msr_ignored_check(vcpu, index, data, true); 2185 } 2186 2187 static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data) 2188 { 2189 u64 val; 2190 2191 /* 2192 * Disallow writes to immutable feature MSRs after KVM_RUN. KVM does 2193 * not support modifying the guest vCPU model on the fly, e.g. changing 2194 * the nVMX capabilities while L2 is running is nonsensical. Allow 2195 * writes of the same value, e.g. to allow userspace to blindly stuff 2196 * all MSRs when emulating RESET. 2197 */ 2198 if (kvm_vcpu_has_run(vcpu) && kvm_is_immutable_feature_msr(index) && 2199 (do_get_msr(vcpu, index, &val) || *data != val)) 2200 return -EINVAL; 2201 2202 return kvm_set_msr_ignored_check(vcpu, index, *data, true); 2203 } 2204 2205 #ifdef CONFIG_X86_64 2206 struct pvclock_clock { 2207 int vclock_mode; 2208 u64 cycle_last; 2209 u64 mask; 2210 u32 mult; 2211 u32 shift; 2212 u64 base_cycles; 2213 u64 offset; 2214 }; 2215 2216 struct pvclock_gtod_data { 2217 seqcount_t seq; 2218 2219 struct pvclock_clock clock; /* extract of a clocksource struct */ 2220 struct pvclock_clock raw_clock; /* extract of a clocksource struct */ 2221 2222 ktime_t offs_boot; 2223 u64 wall_time_sec; 2224 }; 2225 2226 static struct pvclock_gtod_data pvclock_gtod_data; 2227 2228 static void update_pvclock_gtod(struct timekeeper *tk) 2229 { 2230 struct pvclock_gtod_data *vdata = &pvclock_gtod_data; 2231 2232 write_seqcount_begin(&vdata->seq); 2233 2234 /* copy pvclock gtod data */ 2235 vdata->clock.vclock_mode = tk->tkr_mono.clock->vdso_clock_mode; 2236 vdata->clock.cycle_last = tk->tkr_mono.cycle_last; 2237 vdata->clock.mask = tk->tkr_mono.mask; 2238 vdata->clock.mult = tk->tkr_mono.mult; 2239 vdata->clock.shift = tk->tkr_mono.shift; 2240 vdata->clock.base_cycles = tk->tkr_mono.xtime_nsec; 2241 vdata->clock.offset = tk->tkr_mono.base; 2242 2243 vdata->raw_clock.vclock_mode = tk->tkr_raw.clock->vdso_clock_mode; 2244 vdata->raw_clock.cycle_last = tk->tkr_raw.cycle_last; 2245 vdata->raw_clock.mask = tk->tkr_raw.mask; 2246 vdata->raw_clock.mult = tk->tkr_raw.mult; 2247 vdata->raw_clock.shift = tk->tkr_raw.shift; 2248 vdata->raw_clock.base_cycles = tk->tkr_raw.xtime_nsec; 2249 vdata->raw_clock.offset = tk->tkr_raw.base; 2250 2251 vdata->wall_time_sec = tk->xtime_sec; 2252 2253 vdata->offs_boot = tk->offs_boot; 2254 2255 write_seqcount_end(&vdata->seq); 2256 } 2257 2258 static s64 get_kvmclock_base_ns(void) 2259 { 2260 /* Count up from boot time, but with the frequency of the raw clock. */ 2261 return ktime_to_ns(ktime_add(ktime_get_raw(), pvclock_gtod_data.offs_boot)); 2262 } 2263 #else 2264 static s64 get_kvmclock_base_ns(void) 2265 { 2266 /* Master clock not used, so we can just use CLOCK_BOOTTIME. */ 2267 return ktime_get_boottime_ns(); 2268 } 2269 #endif 2270 2271 static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock, int sec_hi_ofs) 2272 { 2273 int version; 2274 int r; 2275 struct pvclock_wall_clock wc; 2276 u32 wc_sec_hi; 2277 u64 wall_nsec; 2278 2279 if (!wall_clock) 2280 return; 2281 2282 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version)); 2283 if (r) 2284 return; 2285 2286 if (version & 1) 2287 ++version; /* first time write, random junk */ 2288 2289 ++version; 2290 2291 if (kvm_write_guest(kvm, wall_clock, &version, sizeof(version))) 2292 return; 2293 2294 wall_nsec = kvm_get_wall_clock_epoch(kvm); 2295 2296 wc.nsec = do_div(wall_nsec, NSEC_PER_SEC); 2297 wc.sec = (u32)wall_nsec; /* overflow in 2106 guest time */ 2298 wc.version = version; 2299 2300 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc)); 2301 2302 if (sec_hi_ofs) { 2303 wc_sec_hi = wall_nsec >> 32; 2304 kvm_write_guest(kvm, wall_clock + sec_hi_ofs, 2305 &wc_sec_hi, sizeof(wc_sec_hi)); 2306 } 2307 2308 version++; 2309 kvm_write_guest(kvm, wall_clock, &version, sizeof(version)); 2310 } 2311 2312 static void kvm_write_system_time(struct kvm_vcpu *vcpu, gpa_t system_time, 2313 bool old_msr, bool host_initiated) 2314 { 2315 struct kvm_arch *ka = &vcpu->kvm->arch; 2316 2317 if (vcpu->vcpu_id == 0 && !host_initiated) { 2318 if (ka->boot_vcpu_runs_old_kvmclock != old_msr) 2319 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu); 2320 2321 ka->boot_vcpu_runs_old_kvmclock = old_msr; 2322 } 2323 2324 vcpu->arch.time = system_time; 2325 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu); 2326 2327 /* we verify if the enable bit is set... */ 2328 if (system_time & 1) 2329 kvm_gpc_activate(&vcpu->arch.pv_time, system_time & ~1ULL, 2330 sizeof(struct pvclock_vcpu_time_info)); 2331 else 2332 kvm_gpc_deactivate(&vcpu->arch.pv_time); 2333 2334 return; 2335 } 2336 2337 static uint32_t div_frac(uint32_t dividend, uint32_t divisor) 2338 { 2339 do_shl32_div32(dividend, divisor); 2340 return dividend; 2341 } 2342 2343 static void kvm_get_time_scale(uint64_t scaled_hz, uint64_t base_hz, 2344 s8 *pshift, u32 *pmultiplier) 2345 { 2346 uint64_t scaled64; 2347 int32_t shift = 0; 2348 uint64_t tps64; 2349 uint32_t tps32; 2350 2351 tps64 = base_hz; 2352 scaled64 = scaled_hz; 2353 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) { 2354 tps64 >>= 1; 2355 shift--; 2356 } 2357 2358 tps32 = (uint32_t)tps64; 2359 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) { 2360 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000) 2361 scaled64 >>= 1; 2362 else 2363 tps32 <<= 1; 2364 shift++; 2365 } 2366 2367 *pshift = shift; 2368 *pmultiplier = div_frac(scaled64, tps32); 2369 } 2370 2371 #ifdef CONFIG_X86_64 2372 static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0); 2373 #endif 2374 2375 static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz); 2376 static unsigned long max_tsc_khz; 2377 2378 static u32 adjust_tsc_khz(u32 khz, s32 ppm) 2379 { 2380 u64 v = (u64)khz * (1000000 + ppm); 2381 do_div(v, 1000000); 2382 return v; 2383 } 2384 2385 static void kvm_vcpu_write_tsc_multiplier(struct kvm_vcpu *vcpu, u64 l1_multiplier); 2386 2387 static int set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale) 2388 { 2389 u64 ratio; 2390 2391 /* Guest TSC same frequency as host TSC? */ 2392 if (!scale) { 2393 kvm_vcpu_write_tsc_multiplier(vcpu, kvm_caps.default_tsc_scaling_ratio); 2394 return 0; 2395 } 2396 2397 /* TSC scaling supported? */ 2398 if (!kvm_caps.has_tsc_control) { 2399 if (user_tsc_khz > tsc_khz) { 2400 vcpu->arch.tsc_catchup = 1; 2401 vcpu->arch.tsc_always_catchup = 1; 2402 return 0; 2403 } else { 2404 pr_warn_ratelimited("user requested TSC rate below hardware speed\n"); 2405 return -1; 2406 } 2407 } 2408 2409 /* TSC scaling required - calculate ratio */ 2410 ratio = mul_u64_u32_div(1ULL << kvm_caps.tsc_scaling_ratio_frac_bits, 2411 user_tsc_khz, tsc_khz); 2412 2413 if (ratio == 0 || ratio >= kvm_caps.max_tsc_scaling_ratio) { 2414 pr_warn_ratelimited("Invalid TSC scaling ratio - virtual-tsc-khz=%u\n", 2415 user_tsc_khz); 2416 return -1; 2417 } 2418 2419 kvm_vcpu_write_tsc_multiplier(vcpu, ratio); 2420 return 0; 2421 } 2422 2423 static int kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz) 2424 { 2425 u32 thresh_lo, thresh_hi; 2426 int use_scaling = 0; 2427 2428 /* tsc_khz can be zero if TSC calibration fails */ 2429 if (user_tsc_khz == 0) { 2430 /* set tsc_scaling_ratio to a safe value */ 2431 kvm_vcpu_write_tsc_multiplier(vcpu, kvm_caps.default_tsc_scaling_ratio); 2432 return -1; 2433 } 2434 2435 /* Compute a scale to convert nanoseconds in TSC cycles */ 2436 kvm_get_time_scale(user_tsc_khz * 1000LL, NSEC_PER_SEC, 2437 &vcpu->arch.virtual_tsc_shift, 2438 &vcpu->arch.virtual_tsc_mult); 2439 vcpu->arch.virtual_tsc_khz = user_tsc_khz; 2440 2441 /* 2442 * Compute the variation in TSC rate which is acceptable 2443 * within the range of tolerance and decide if the 2444 * rate being applied is within that bounds of the hardware 2445 * rate. If so, no scaling or compensation need be done. 2446 */ 2447 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm); 2448 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm); 2449 if (user_tsc_khz < thresh_lo || user_tsc_khz > thresh_hi) { 2450 pr_debug("requested TSC rate %u falls outside tolerance [%u,%u]\n", 2451 user_tsc_khz, thresh_lo, thresh_hi); 2452 use_scaling = 1; 2453 } 2454 return set_tsc_khz(vcpu, user_tsc_khz, use_scaling); 2455 } 2456 2457 static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns) 2458 { 2459 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec, 2460 vcpu->arch.virtual_tsc_mult, 2461 vcpu->arch.virtual_tsc_shift); 2462 tsc += vcpu->arch.this_tsc_write; 2463 return tsc; 2464 } 2465 2466 #ifdef CONFIG_X86_64 2467 static inline bool gtod_is_based_on_tsc(int mode) 2468 { 2469 return mode == VDSO_CLOCKMODE_TSC || mode == VDSO_CLOCKMODE_HVCLOCK; 2470 } 2471 #endif 2472 2473 static void kvm_track_tsc_matching(struct kvm_vcpu *vcpu, bool new_generation) 2474 { 2475 #ifdef CONFIG_X86_64 2476 struct kvm_arch *ka = &vcpu->kvm->arch; 2477 struct pvclock_gtod_data *gtod = &pvclock_gtod_data; 2478 2479 /* 2480 * To use the masterclock, the host clocksource must be based on TSC 2481 * and all vCPUs must have matching TSCs. Note, the count for matching 2482 * vCPUs doesn't include the reference vCPU, hence "+1". 2483 */ 2484 bool use_master_clock = (ka->nr_vcpus_matched_tsc + 1 == 2485 atomic_read(&vcpu->kvm->online_vcpus)) && 2486 gtod_is_based_on_tsc(gtod->clock.vclock_mode); 2487 2488 /* 2489 * Request a masterclock update if the masterclock needs to be toggled 2490 * on/off, or when starting a new generation and the masterclock is 2491 * enabled (compute_guest_tsc() requires the masterclock snapshot to be 2492 * taken _after_ the new generation is created). 2493 */ 2494 if ((ka->use_master_clock && new_generation) || 2495 (ka->use_master_clock != use_master_clock)) 2496 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu); 2497 2498 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc, 2499 atomic_read(&vcpu->kvm->online_vcpus), 2500 ka->use_master_clock, gtod->clock.vclock_mode); 2501 #endif 2502 } 2503 2504 /* 2505 * Multiply tsc by a fixed point number represented by ratio. 2506 * 2507 * The most significant 64-N bits (mult) of ratio represent the 2508 * integral part of the fixed point number; the remaining N bits 2509 * (frac) represent the fractional part, ie. ratio represents a fixed 2510 * point number (mult + frac * 2^(-N)). 2511 * 2512 * N equals to kvm_caps.tsc_scaling_ratio_frac_bits. 2513 */ 2514 static inline u64 __scale_tsc(u64 ratio, u64 tsc) 2515 { 2516 return mul_u64_u64_shr(tsc, ratio, kvm_caps.tsc_scaling_ratio_frac_bits); 2517 } 2518 2519 u64 kvm_scale_tsc(u64 tsc, u64 ratio) 2520 { 2521 u64 _tsc = tsc; 2522 2523 if (ratio != kvm_caps.default_tsc_scaling_ratio) 2524 _tsc = __scale_tsc(ratio, tsc); 2525 2526 return _tsc; 2527 } 2528 2529 static u64 kvm_compute_l1_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc) 2530 { 2531 u64 tsc; 2532 2533 tsc = kvm_scale_tsc(rdtsc(), vcpu->arch.l1_tsc_scaling_ratio); 2534 2535 return target_tsc - tsc; 2536 } 2537 2538 u64 kvm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc) 2539 { 2540 return vcpu->arch.l1_tsc_offset + 2541 kvm_scale_tsc(host_tsc, vcpu->arch.l1_tsc_scaling_ratio); 2542 } 2543 EXPORT_SYMBOL_GPL(kvm_read_l1_tsc); 2544 2545 u64 kvm_calc_nested_tsc_offset(u64 l1_offset, u64 l2_offset, u64 l2_multiplier) 2546 { 2547 u64 nested_offset; 2548 2549 if (l2_multiplier == kvm_caps.default_tsc_scaling_ratio) 2550 nested_offset = l1_offset; 2551 else 2552 nested_offset = mul_s64_u64_shr((s64) l1_offset, l2_multiplier, 2553 kvm_caps.tsc_scaling_ratio_frac_bits); 2554 2555 nested_offset += l2_offset; 2556 return nested_offset; 2557 } 2558 EXPORT_SYMBOL_GPL(kvm_calc_nested_tsc_offset); 2559 2560 u64 kvm_calc_nested_tsc_multiplier(u64 l1_multiplier, u64 l2_multiplier) 2561 { 2562 if (l2_multiplier != kvm_caps.default_tsc_scaling_ratio) 2563 return mul_u64_u64_shr(l1_multiplier, l2_multiplier, 2564 kvm_caps.tsc_scaling_ratio_frac_bits); 2565 2566 return l1_multiplier; 2567 } 2568 EXPORT_SYMBOL_GPL(kvm_calc_nested_tsc_multiplier); 2569 2570 static void kvm_vcpu_write_tsc_offset(struct kvm_vcpu *vcpu, u64 l1_offset) 2571 { 2572 trace_kvm_write_tsc_offset(vcpu->vcpu_id, 2573 vcpu->arch.l1_tsc_offset, 2574 l1_offset); 2575 2576 vcpu->arch.l1_tsc_offset = l1_offset; 2577 2578 /* 2579 * If we are here because L1 chose not to trap WRMSR to TSC then 2580 * according to the spec this should set L1's TSC (as opposed to 2581 * setting L1's offset for L2). 2582 */ 2583 if (is_guest_mode(vcpu)) 2584 vcpu->arch.tsc_offset = kvm_calc_nested_tsc_offset( 2585 l1_offset, 2586 kvm_x86_call(get_l2_tsc_offset)(vcpu), 2587 kvm_x86_call(get_l2_tsc_multiplier)(vcpu)); 2588 else 2589 vcpu->arch.tsc_offset = l1_offset; 2590 2591 kvm_x86_call(write_tsc_offset)(vcpu); 2592 } 2593 2594 static void kvm_vcpu_write_tsc_multiplier(struct kvm_vcpu *vcpu, u64 l1_multiplier) 2595 { 2596 vcpu->arch.l1_tsc_scaling_ratio = l1_multiplier; 2597 2598 /* Userspace is changing the multiplier while L2 is active */ 2599 if (is_guest_mode(vcpu)) 2600 vcpu->arch.tsc_scaling_ratio = kvm_calc_nested_tsc_multiplier( 2601 l1_multiplier, 2602 kvm_x86_call(get_l2_tsc_multiplier)(vcpu)); 2603 else 2604 vcpu->arch.tsc_scaling_ratio = l1_multiplier; 2605 2606 if (kvm_caps.has_tsc_control) 2607 kvm_x86_call(write_tsc_multiplier)(vcpu); 2608 } 2609 2610 static inline bool kvm_check_tsc_unstable(void) 2611 { 2612 #ifdef CONFIG_X86_64 2613 /* 2614 * TSC is marked unstable when we're running on Hyper-V, 2615 * 'TSC page' clocksource is good. 2616 */ 2617 if (pvclock_gtod_data.clock.vclock_mode == VDSO_CLOCKMODE_HVCLOCK) 2618 return false; 2619 #endif 2620 return check_tsc_unstable(); 2621 } 2622 2623 /* 2624 * Infers attempts to synchronize the guest's tsc from host writes. Sets the 2625 * offset for the vcpu and tracks the TSC matching generation that the vcpu 2626 * participates in. 2627 */ 2628 static void __kvm_synchronize_tsc(struct kvm_vcpu *vcpu, u64 offset, u64 tsc, 2629 u64 ns, bool matched) 2630 { 2631 struct kvm *kvm = vcpu->kvm; 2632 2633 lockdep_assert_held(&kvm->arch.tsc_write_lock); 2634 2635 /* 2636 * We also track th most recent recorded KHZ, write and time to 2637 * allow the matching interval to be extended at each write. 2638 */ 2639 kvm->arch.last_tsc_nsec = ns; 2640 kvm->arch.last_tsc_write = tsc; 2641 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz; 2642 kvm->arch.last_tsc_offset = offset; 2643 2644 vcpu->arch.last_guest_tsc = tsc; 2645 2646 kvm_vcpu_write_tsc_offset(vcpu, offset); 2647 2648 if (!matched) { 2649 /* 2650 * We split periods of matched TSC writes into generations. 2651 * For each generation, we track the original measured 2652 * nanosecond time, offset, and write, so if TSCs are in 2653 * sync, we can match exact offset, and if not, we can match 2654 * exact software computation in compute_guest_tsc() 2655 * 2656 * These values are tracked in kvm->arch.cur_xxx variables. 2657 */ 2658 kvm->arch.cur_tsc_generation++; 2659 kvm->arch.cur_tsc_nsec = ns; 2660 kvm->arch.cur_tsc_write = tsc; 2661 kvm->arch.cur_tsc_offset = offset; 2662 kvm->arch.nr_vcpus_matched_tsc = 0; 2663 } else if (vcpu->arch.this_tsc_generation != kvm->arch.cur_tsc_generation) { 2664 kvm->arch.nr_vcpus_matched_tsc++; 2665 } 2666 2667 /* Keep track of which generation this VCPU has synchronized to */ 2668 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation; 2669 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec; 2670 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write; 2671 2672 kvm_track_tsc_matching(vcpu, !matched); 2673 } 2674 2675 static void kvm_synchronize_tsc(struct kvm_vcpu *vcpu, u64 *user_value) 2676 { 2677 u64 data = user_value ? *user_value : 0; 2678 struct kvm *kvm = vcpu->kvm; 2679 u64 offset, ns, elapsed; 2680 unsigned long flags; 2681 bool matched = false; 2682 bool synchronizing = false; 2683 2684 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags); 2685 offset = kvm_compute_l1_tsc_offset(vcpu, data); 2686 ns = get_kvmclock_base_ns(); 2687 elapsed = ns - kvm->arch.last_tsc_nsec; 2688 2689 if (vcpu->arch.virtual_tsc_khz) { 2690 if (data == 0) { 2691 /* 2692 * Force synchronization when creating a vCPU, or when 2693 * userspace explicitly writes a zero value. 2694 */ 2695 synchronizing = true; 2696 } else if (kvm->arch.user_set_tsc) { 2697 u64 tsc_exp = kvm->arch.last_tsc_write + 2698 nsec_to_cycles(vcpu, elapsed); 2699 u64 tsc_hz = vcpu->arch.virtual_tsc_khz * 1000LL; 2700 /* 2701 * Here lies UAPI baggage: when a user-initiated TSC write has 2702 * a small delta (1 second) of virtual cycle time against the 2703 * previously set vCPU, we assume that they were intended to be 2704 * in sync and the delta was only due to the racy nature of the 2705 * legacy API. 2706 * 2707 * This trick falls down when restoring a guest which genuinely 2708 * has been running for less time than the 1 second of imprecision 2709 * which we allow for in the legacy API. In this case, the first 2710 * value written by userspace (on any vCPU) should not be subject 2711 * to this 'correction' to make it sync up with values that only 2712 * come from the kernel's default vCPU creation. Make the 1-second 2713 * slop hack only trigger if the user_set_tsc flag is already set. 2714 */ 2715 synchronizing = data < tsc_exp + tsc_hz && 2716 data + tsc_hz > tsc_exp; 2717 } 2718 } 2719 2720 if (user_value) 2721 kvm->arch.user_set_tsc = true; 2722 2723 /* 2724 * For a reliable TSC, we can match TSC offsets, and for an unstable 2725 * TSC, we add elapsed time in this computation. We could let the 2726 * compensation code attempt to catch up if we fall behind, but 2727 * it's better to try to match offsets from the beginning. 2728 */ 2729 if (synchronizing && 2730 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) { 2731 if (!kvm_check_tsc_unstable()) { 2732 offset = kvm->arch.cur_tsc_offset; 2733 } else { 2734 u64 delta = nsec_to_cycles(vcpu, elapsed); 2735 data += delta; 2736 offset = kvm_compute_l1_tsc_offset(vcpu, data); 2737 } 2738 matched = true; 2739 } 2740 2741 __kvm_synchronize_tsc(vcpu, offset, data, ns, matched); 2742 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags); 2743 } 2744 2745 static inline void adjust_tsc_offset_guest(struct kvm_vcpu *vcpu, 2746 s64 adjustment) 2747 { 2748 u64 tsc_offset = vcpu->arch.l1_tsc_offset; 2749 kvm_vcpu_write_tsc_offset(vcpu, tsc_offset + adjustment); 2750 } 2751 2752 static inline void adjust_tsc_offset_host(struct kvm_vcpu *vcpu, s64 adjustment) 2753 { 2754 if (vcpu->arch.l1_tsc_scaling_ratio != kvm_caps.default_tsc_scaling_ratio) 2755 WARN_ON(adjustment < 0); 2756 adjustment = kvm_scale_tsc((u64) adjustment, 2757 vcpu->arch.l1_tsc_scaling_ratio); 2758 adjust_tsc_offset_guest(vcpu, adjustment); 2759 } 2760 2761 #ifdef CONFIG_X86_64 2762 2763 static u64 read_tsc(void) 2764 { 2765 u64 ret = (u64)rdtsc_ordered(); 2766 u64 last = pvclock_gtod_data.clock.cycle_last; 2767 2768 if (likely(ret >= last)) 2769 return ret; 2770 2771 /* 2772 * GCC likes to generate cmov here, but this branch is extremely 2773 * predictable (it's just a function of time and the likely is 2774 * very likely) and there's a data dependence, so force GCC 2775 * to generate a branch instead. I don't barrier() because 2776 * we don't actually need a barrier, and if this function 2777 * ever gets inlined it will generate worse code. 2778 */ 2779 asm volatile (""); 2780 return last; 2781 } 2782 2783 static inline u64 vgettsc(struct pvclock_clock *clock, u64 *tsc_timestamp, 2784 int *mode) 2785 { 2786 u64 tsc_pg_val; 2787 long v; 2788 2789 switch (clock->vclock_mode) { 2790 case VDSO_CLOCKMODE_HVCLOCK: 2791 if (hv_read_tsc_page_tsc(hv_get_tsc_page(), 2792 tsc_timestamp, &tsc_pg_val)) { 2793 /* TSC page valid */ 2794 *mode = VDSO_CLOCKMODE_HVCLOCK; 2795 v = (tsc_pg_val - clock->cycle_last) & 2796 clock->mask; 2797 } else { 2798 /* TSC page invalid */ 2799 *mode = VDSO_CLOCKMODE_NONE; 2800 } 2801 break; 2802 case VDSO_CLOCKMODE_TSC: 2803 *mode = VDSO_CLOCKMODE_TSC; 2804 *tsc_timestamp = read_tsc(); 2805 v = (*tsc_timestamp - clock->cycle_last) & 2806 clock->mask; 2807 break; 2808 default: 2809 *mode = VDSO_CLOCKMODE_NONE; 2810 } 2811 2812 if (*mode == VDSO_CLOCKMODE_NONE) 2813 *tsc_timestamp = v = 0; 2814 2815 return v * clock->mult; 2816 } 2817 2818 /* 2819 * As with get_kvmclock_base_ns(), this counts from boot time, at the 2820 * frequency of CLOCK_MONOTONIC_RAW (hence adding gtos->offs_boot). 2821 */ 2822 static int do_kvmclock_base(s64 *t, u64 *tsc_timestamp) 2823 { 2824 struct pvclock_gtod_data *gtod = &pvclock_gtod_data; 2825 unsigned long seq; 2826 int mode; 2827 u64 ns; 2828 2829 do { 2830 seq = read_seqcount_begin(>od->seq); 2831 ns = gtod->raw_clock.base_cycles; 2832 ns += vgettsc(>od->raw_clock, tsc_timestamp, &mode); 2833 ns >>= gtod->raw_clock.shift; 2834 ns += ktime_to_ns(ktime_add(gtod->raw_clock.offset, gtod->offs_boot)); 2835 } while (unlikely(read_seqcount_retry(>od->seq, seq))); 2836 *t = ns; 2837 2838 return mode; 2839 } 2840 2841 /* 2842 * This calculates CLOCK_MONOTONIC at the time of the TSC snapshot, with 2843 * no boot time offset. 2844 */ 2845 static int do_monotonic(s64 *t, u64 *tsc_timestamp) 2846 { 2847 struct pvclock_gtod_data *gtod = &pvclock_gtod_data; 2848 unsigned long seq; 2849 int mode; 2850 u64 ns; 2851 2852 do { 2853 seq = read_seqcount_begin(>od->seq); 2854 ns = gtod->clock.base_cycles; 2855 ns += vgettsc(>od->clock, tsc_timestamp, &mode); 2856 ns >>= gtod->clock.shift; 2857 ns += ktime_to_ns(gtod->clock.offset); 2858 } while (unlikely(read_seqcount_retry(>od->seq, seq))); 2859 *t = ns; 2860 2861 return mode; 2862 } 2863 2864 static int do_realtime(struct timespec64 *ts, u64 *tsc_timestamp) 2865 { 2866 struct pvclock_gtod_data *gtod = &pvclock_gtod_data; 2867 unsigned long seq; 2868 int mode; 2869 u64 ns; 2870 2871 do { 2872 seq = read_seqcount_begin(>od->seq); 2873 ts->tv_sec = gtod->wall_time_sec; 2874 ns = gtod->clock.base_cycles; 2875 ns += vgettsc(>od->clock, tsc_timestamp, &mode); 2876 ns >>= gtod->clock.shift; 2877 } while (unlikely(read_seqcount_retry(>od->seq, seq))); 2878 2879 ts->tv_sec += __iter_div_u64_rem(ns, NSEC_PER_SEC, &ns); 2880 ts->tv_nsec = ns; 2881 2882 return mode; 2883 } 2884 2885 /* 2886 * Calculates the kvmclock_base_ns (CLOCK_MONOTONIC_RAW + boot time) and 2887 * reports the TSC value from which it do so. Returns true if host is 2888 * using TSC based clocksource. 2889 */ 2890 static bool kvm_get_time_and_clockread(s64 *kernel_ns, u64 *tsc_timestamp) 2891 { 2892 /* checked again under seqlock below */ 2893 if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode)) 2894 return false; 2895 2896 return gtod_is_based_on_tsc(do_kvmclock_base(kernel_ns, 2897 tsc_timestamp)); 2898 } 2899 2900 /* 2901 * Calculates CLOCK_MONOTONIC and reports the TSC value from which it did 2902 * so. Returns true if host is using TSC based clocksource. 2903 */ 2904 bool kvm_get_monotonic_and_clockread(s64 *kernel_ns, u64 *tsc_timestamp) 2905 { 2906 /* checked again under seqlock below */ 2907 if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode)) 2908 return false; 2909 2910 return gtod_is_based_on_tsc(do_monotonic(kernel_ns, 2911 tsc_timestamp)); 2912 } 2913 2914 /* 2915 * Calculates CLOCK_REALTIME and reports the TSC value from which it did 2916 * so. Returns true if host is using TSC based clocksource. 2917 * 2918 * DO NOT USE this for anything related to migration. You want CLOCK_TAI 2919 * for that. 2920 */ 2921 static bool kvm_get_walltime_and_clockread(struct timespec64 *ts, 2922 u64 *tsc_timestamp) 2923 { 2924 /* checked again under seqlock below */ 2925 if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode)) 2926 return false; 2927 2928 return gtod_is_based_on_tsc(do_realtime(ts, tsc_timestamp)); 2929 } 2930 #endif 2931 2932 /* 2933 * 2934 * Assuming a stable TSC across physical CPUS, and a stable TSC 2935 * across virtual CPUs, the following condition is possible. 2936 * Each numbered line represents an event visible to both 2937 * CPUs at the next numbered event. 2938 * 2939 * "timespecX" represents host monotonic time. "tscX" represents 2940 * RDTSC value. 2941 * 2942 * VCPU0 on CPU0 | VCPU1 on CPU1 2943 * 2944 * 1. read timespec0,tsc0 2945 * 2. | timespec1 = timespec0 + N 2946 * | tsc1 = tsc0 + M 2947 * 3. transition to guest | transition to guest 2948 * 4. ret0 = timespec0 + (rdtsc - tsc0) | 2949 * 5. | ret1 = timespec1 + (rdtsc - tsc1) 2950 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M)) 2951 * 2952 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity: 2953 * 2954 * - ret0 < ret1 2955 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M)) 2956 * ... 2957 * - 0 < N - M => M < N 2958 * 2959 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not 2960 * always the case (the difference between two distinct xtime instances 2961 * might be smaller then the difference between corresponding TSC reads, 2962 * when updating guest vcpus pvclock areas). 2963 * 2964 * To avoid that problem, do not allow visibility of distinct 2965 * system_timestamp/tsc_timestamp values simultaneously: use a master 2966 * copy of host monotonic time values. Update that master copy 2967 * in lockstep. 2968 * 2969 * Rely on synchronization of host TSCs and guest TSCs for monotonicity. 2970 * 2971 */ 2972 2973 static void pvclock_update_vm_gtod_copy(struct kvm *kvm) 2974 { 2975 #ifdef CONFIG_X86_64 2976 struct kvm_arch *ka = &kvm->arch; 2977 int vclock_mode; 2978 bool host_tsc_clocksource, vcpus_matched; 2979 2980 lockdep_assert_held(&kvm->arch.tsc_write_lock); 2981 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 == 2982 atomic_read(&kvm->online_vcpus)); 2983 2984 /* 2985 * If the host uses TSC clock, then passthrough TSC as stable 2986 * to the guest. 2987 */ 2988 host_tsc_clocksource = kvm_get_time_and_clockread( 2989 &ka->master_kernel_ns, 2990 &ka->master_cycle_now); 2991 2992 ka->use_master_clock = host_tsc_clocksource && vcpus_matched 2993 && !ka->backwards_tsc_observed 2994 && !ka->boot_vcpu_runs_old_kvmclock; 2995 2996 if (ka->use_master_clock) 2997 atomic_set(&kvm_guest_has_master_clock, 1); 2998 2999 vclock_mode = pvclock_gtod_data.clock.vclock_mode; 3000 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode, 3001 vcpus_matched); 3002 #endif 3003 } 3004 3005 static void kvm_make_mclock_inprogress_request(struct kvm *kvm) 3006 { 3007 kvm_make_all_cpus_request(kvm, KVM_REQ_MCLOCK_INPROGRESS); 3008 } 3009 3010 static void __kvm_start_pvclock_update(struct kvm *kvm) 3011 { 3012 raw_spin_lock_irq(&kvm->arch.tsc_write_lock); 3013 write_seqcount_begin(&kvm->arch.pvclock_sc); 3014 } 3015 3016 static void kvm_start_pvclock_update(struct kvm *kvm) 3017 { 3018 kvm_make_mclock_inprogress_request(kvm); 3019 3020 /* no guest entries from this point */ 3021 __kvm_start_pvclock_update(kvm); 3022 } 3023 3024 static void kvm_end_pvclock_update(struct kvm *kvm) 3025 { 3026 struct kvm_arch *ka = &kvm->arch; 3027 struct kvm_vcpu *vcpu; 3028 unsigned long i; 3029 3030 write_seqcount_end(&ka->pvclock_sc); 3031 raw_spin_unlock_irq(&ka->tsc_write_lock); 3032 kvm_for_each_vcpu(i, vcpu, kvm) 3033 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 3034 3035 /* guest entries allowed */ 3036 kvm_for_each_vcpu(i, vcpu, kvm) 3037 kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu); 3038 } 3039 3040 static void kvm_update_masterclock(struct kvm *kvm) 3041 { 3042 kvm_hv_request_tsc_page_update(kvm); 3043 kvm_start_pvclock_update(kvm); 3044 pvclock_update_vm_gtod_copy(kvm); 3045 kvm_end_pvclock_update(kvm); 3046 } 3047 3048 /* 3049 * Use the kernel's tsc_khz directly if the TSC is constant, otherwise use KVM's 3050 * per-CPU value (which may be zero if a CPU is going offline). Note, tsc_khz 3051 * can change during boot even if the TSC is constant, as it's possible for KVM 3052 * to be loaded before TSC calibration completes. Ideally, KVM would get a 3053 * notification when calibration completes, but practically speaking calibration 3054 * will complete before userspace is alive enough to create VMs. 3055 */ 3056 static unsigned long get_cpu_tsc_khz(void) 3057 { 3058 if (static_cpu_has(X86_FEATURE_CONSTANT_TSC)) 3059 return tsc_khz; 3060 else 3061 return __this_cpu_read(cpu_tsc_khz); 3062 } 3063 3064 /* Called within read_seqcount_begin/retry for kvm->pvclock_sc. */ 3065 static void __get_kvmclock(struct kvm *kvm, struct kvm_clock_data *data) 3066 { 3067 struct kvm_arch *ka = &kvm->arch; 3068 struct pvclock_vcpu_time_info hv_clock; 3069 3070 /* both __this_cpu_read() and rdtsc() should be on the same cpu */ 3071 get_cpu(); 3072 3073 data->flags = 0; 3074 if (ka->use_master_clock && 3075 (static_cpu_has(X86_FEATURE_CONSTANT_TSC) || __this_cpu_read(cpu_tsc_khz))) { 3076 #ifdef CONFIG_X86_64 3077 struct timespec64 ts; 3078 3079 if (kvm_get_walltime_and_clockread(&ts, &data->host_tsc)) { 3080 data->realtime = ts.tv_nsec + NSEC_PER_SEC * ts.tv_sec; 3081 data->flags |= KVM_CLOCK_REALTIME | KVM_CLOCK_HOST_TSC; 3082 } else 3083 #endif 3084 data->host_tsc = rdtsc(); 3085 3086 data->flags |= KVM_CLOCK_TSC_STABLE; 3087 hv_clock.tsc_timestamp = ka->master_cycle_now; 3088 hv_clock.system_time = ka->master_kernel_ns + ka->kvmclock_offset; 3089 kvm_get_time_scale(NSEC_PER_SEC, get_cpu_tsc_khz() * 1000LL, 3090 &hv_clock.tsc_shift, 3091 &hv_clock.tsc_to_system_mul); 3092 data->clock = __pvclock_read_cycles(&hv_clock, data->host_tsc); 3093 } else { 3094 data->clock = get_kvmclock_base_ns() + ka->kvmclock_offset; 3095 } 3096 3097 put_cpu(); 3098 } 3099 3100 static void get_kvmclock(struct kvm *kvm, struct kvm_clock_data *data) 3101 { 3102 struct kvm_arch *ka = &kvm->arch; 3103 unsigned seq; 3104 3105 do { 3106 seq = read_seqcount_begin(&ka->pvclock_sc); 3107 __get_kvmclock(kvm, data); 3108 } while (read_seqcount_retry(&ka->pvclock_sc, seq)); 3109 } 3110 3111 u64 get_kvmclock_ns(struct kvm *kvm) 3112 { 3113 struct kvm_clock_data data; 3114 3115 get_kvmclock(kvm, &data); 3116 return data.clock; 3117 } 3118 3119 static void kvm_setup_guest_pvclock(struct kvm_vcpu *v, 3120 struct gfn_to_pfn_cache *gpc, 3121 unsigned int offset, 3122 bool force_tsc_unstable) 3123 { 3124 struct kvm_vcpu_arch *vcpu = &v->arch; 3125 struct pvclock_vcpu_time_info *guest_hv_clock; 3126 unsigned long flags; 3127 3128 read_lock_irqsave(&gpc->lock, flags); 3129 while (!kvm_gpc_check(gpc, offset + sizeof(*guest_hv_clock))) { 3130 read_unlock_irqrestore(&gpc->lock, flags); 3131 3132 if (kvm_gpc_refresh(gpc, offset + sizeof(*guest_hv_clock))) 3133 return; 3134 3135 read_lock_irqsave(&gpc->lock, flags); 3136 } 3137 3138 guest_hv_clock = (void *)(gpc->khva + offset); 3139 3140 /* 3141 * This VCPU is paused, but it's legal for a guest to read another 3142 * VCPU's kvmclock, so we really have to follow the specification where 3143 * it says that version is odd if data is being modified, and even after 3144 * it is consistent. 3145 */ 3146 3147 guest_hv_clock->version = vcpu->hv_clock.version = (guest_hv_clock->version + 1) | 1; 3148 smp_wmb(); 3149 3150 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */ 3151 vcpu->hv_clock.flags |= (guest_hv_clock->flags & PVCLOCK_GUEST_STOPPED); 3152 3153 if (vcpu->pvclock_set_guest_stopped_request) { 3154 vcpu->hv_clock.flags |= PVCLOCK_GUEST_STOPPED; 3155 vcpu->pvclock_set_guest_stopped_request = false; 3156 } 3157 3158 memcpy(guest_hv_clock, &vcpu->hv_clock, sizeof(*guest_hv_clock)); 3159 3160 if (force_tsc_unstable) 3161 guest_hv_clock->flags &= ~PVCLOCK_TSC_STABLE_BIT; 3162 3163 smp_wmb(); 3164 3165 guest_hv_clock->version = ++vcpu->hv_clock.version; 3166 3167 kvm_gpc_mark_dirty_in_slot(gpc); 3168 read_unlock_irqrestore(&gpc->lock, flags); 3169 3170 trace_kvm_pvclock_update(v->vcpu_id, &vcpu->hv_clock); 3171 } 3172 3173 static int kvm_guest_time_update(struct kvm_vcpu *v) 3174 { 3175 unsigned long flags, tgt_tsc_khz; 3176 unsigned seq; 3177 struct kvm_vcpu_arch *vcpu = &v->arch; 3178 struct kvm_arch *ka = &v->kvm->arch; 3179 s64 kernel_ns; 3180 u64 tsc_timestamp, host_tsc; 3181 u8 pvclock_flags; 3182 bool use_master_clock; 3183 #ifdef CONFIG_KVM_XEN 3184 /* 3185 * For Xen guests we may need to override PVCLOCK_TSC_STABLE_BIT as unless 3186 * explicitly told to use TSC as its clocksource Xen will not set this bit. 3187 * This default behaviour led to bugs in some guest kernels which cause 3188 * problems if they observe PVCLOCK_TSC_STABLE_BIT in the pvclock flags. 3189 */ 3190 bool xen_pvclock_tsc_unstable = 3191 ka->xen_hvm_config.flags & KVM_XEN_HVM_CONFIG_PVCLOCK_TSC_UNSTABLE; 3192 #endif 3193 3194 kernel_ns = 0; 3195 host_tsc = 0; 3196 3197 /* 3198 * If the host uses TSC clock, then passthrough TSC as stable 3199 * to the guest. 3200 */ 3201 do { 3202 seq = read_seqcount_begin(&ka->pvclock_sc); 3203 use_master_clock = ka->use_master_clock; 3204 if (use_master_clock) { 3205 host_tsc = ka->master_cycle_now; 3206 kernel_ns = ka->master_kernel_ns; 3207 } 3208 } while (read_seqcount_retry(&ka->pvclock_sc, seq)); 3209 3210 /* Keep irq disabled to prevent changes to the clock */ 3211 local_irq_save(flags); 3212 tgt_tsc_khz = get_cpu_tsc_khz(); 3213 if (unlikely(tgt_tsc_khz == 0)) { 3214 local_irq_restore(flags); 3215 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v); 3216 return 1; 3217 } 3218 if (!use_master_clock) { 3219 host_tsc = rdtsc(); 3220 kernel_ns = get_kvmclock_base_ns(); 3221 } 3222 3223 tsc_timestamp = kvm_read_l1_tsc(v, host_tsc); 3224 3225 /* 3226 * We may have to catch up the TSC to match elapsed wall clock 3227 * time for two reasons, even if kvmclock is used. 3228 * 1) CPU could have been running below the maximum TSC rate 3229 * 2) Broken TSC compensation resets the base at each VCPU 3230 * entry to avoid unknown leaps of TSC even when running 3231 * again on the same CPU. This may cause apparent elapsed 3232 * time to disappear, and the guest to stand still or run 3233 * very slowly. 3234 */ 3235 if (vcpu->tsc_catchup) { 3236 u64 tsc = compute_guest_tsc(v, kernel_ns); 3237 if (tsc > tsc_timestamp) { 3238 adjust_tsc_offset_guest(v, tsc - tsc_timestamp); 3239 tsc_timestamp = tsc; 3240 } 3241 } 3242 3243 local_irq_restore(flags); 3244 3245 /* With all the info we got, fill in the values */ 3246 3247 if (kvm_caps.has_tsc_control) 3248 tgt_tsc_khz = kvm_scale_tsc(tgt_tsc_khz, 3249 v->arch.l1_tsc_scaling_ratio); 3250 3251 if (unlikely(vcpu->hw_tsc_khz != tgt_tsc_khz)) { 3252 kvm_get_time_scale(NSEC_PER_SEC, tgt_tsc_khz * 1000LL, 3253 &vcpu->hv_clock.tsc_shift, 3254 &vcpu->hv_clock.tsc_to_system_mul); 3255 vcpu->hw_tsc_khz = tgt_tsc_khz; 3256 kvm_xen_update_tsc_info(v); 3257 } 3258 3259 vcpu->hv_clock.tsc_timestamp = tsc_timestamp; 3260 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset; 3261 vcpu->last_guest_tsc = tsc_timestamp; 3262 3263 /* If the host uses TSC clocksource, then it is stable */ 3264 pvclock_flags = 0; 3265 if (use_master_clock) 3266 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT; 3267 3268 vcpu->hv_clock.flags = pvclock_flags; 3269 3270 if (vcpu->pv_time.active) 3271 kvm_setup_guest_pvclock(v, &vcpu->pv_time, 0, false); 3272 #ifdef CONFIG_KVM_XEN 3273 if (vcpu->xen.vcpu_info_cache.active) 3274 kvm_setup_guest_pvclock(v, &vcpu->xen.vcpu_info_cache, 3275 offsetof(struct compat_vcpu_info, time), 3276 xen_pvclock_tsc_unstable); 3277 if (vcpu->xen.vcpu_time_info_cache.active) 3278 kvm_setup_guest_pvclock(v, &vcpu->xen.vcpu_time_info_cache, 0, 3279 xen_pvclock_tsc_unstable); 3280 #endif 3281 kvm_hv_setup_tsc_page(v->kvm, &vcpu->hv_clock); 3282 return 0; 3283 } 3284 3285 /* 3286 * The pvclock_wall_clock ABI tells the guest the wall clock time at 3287 * which it started (i.e. its epoch, when its kvmclock was zero). 3288 * 3289 * In fact those clocks are subtly different; wall clock frequency is 3290 * adjusted by NTP and has leap seconds, while the kvmclock is a 3291 * simple function of the TSC without any such adjustment. 3292 * 3293 * Perhaps the ABI should have exposed CLOCK_TAI and a ratio between 3294 * that and kvmclock, but even that would be subject to change over 3295 * time. 3296 * 3297 * Attempt to calculate the epoch at a given moment using the *same* 3298 * TSC reading via kvm_get_walltime_and_clockread() to obtain both 3299 * wallclock and kvmclock times, and subtracting one from the other. 3300 * 3301 * Fall back to using their values at slightly different moments by 3302 * calling ktime_get_real_ns() and get_kvmclock_ns() separately. 3303 */ 3304 uint64_t kvm_get_wall_clock_epoch(struct kvm *kvm) 3305 { 3306 #ifdef CONFIG_X86_64 3307 struct pvclock_vcpu_time_info hv_clock; 3308 struct kvm_arch *ka = &kvm->arch; 3309 unsigned long seq, local_tsc_khz; 3310 struct timespec64 ts; 3311 uint64_t host_tsc; 3312 3313 do { 3314 seq = read_seqcount_begin(&ka->pvclock_sc); 3315 3316 local_tsc_khz = 0; 3317 if (!ka->use_master_clock) 3318 break; 3319 3320 /* 3321 * The TSC read and the call to get_cpu_tsc_khz() must happen 3322 * on the same CPU. 3323 */ 3324 get_cpu(); 3325 3326 local_tsc_khz = get_cpu_tsc_khz(); 3327 3328 if (local_tsc_khz && 3329 !kvm_get_walltime_and_clockread(&ts, &host_tsc)) 3330 local_tsc_khz = 0; /* Fall back to old method */ 3331 3332 put_cpu(); 3333 3334 /* 3335 * These values must be snapshotted within the seqcount loop. 3336 * After that, it's just mathematics which can happen on any 3337 * CPU at any time. 3338 */ 3339 hv_clock.tsc_timestamp = ka->master_cycle_now; 3340 hv_clock.system_time = ka->master_kernel_ns + ka->kvmclock_offset; 3341 3342 } while (read_seqcount_retry(&ka->pvclock_sc, seq)); 3343 3344 /* 3345 * If the conditions were right, and obtaining the wallclock+TSC was 3346 * successful, calculate the KVM clock at the corresponding time and 3347 * subtract one from the other to get the guest's epoch in nanoseconds 3348 * since 1970-01-01. 3349 */ 3350 if (local_tsc_khz) { 3351 kvm_get_time_scale(NSEC_PER_SEC, local_tsc_khz * NSEC_PER_USEC, 3352 &hv_clock.tsc_shift, 3353 &hv_clock.tsc_to_system_mul); 3354 return ts.tv_nsec + NSEC_PER_SEC * ts.tv_sec - 3355 __pvclock_read_cycles(&hv_clock, host_tsc); 3356 } 3357 #endif 3358 return ktime_get_real_ns() - get_kvmclock_ns(kvm); 3359 } 3360 3361 /* 3362 * kvmclock updates which are isolated to a given vcpu, such as 3363 * vcpu->cpu migration, should not allow system_timestamp from 3364 * the rest of the vcpus to remain static. Otherwise ntp frequency 3365 * correction applies to one vcpu's system_timestamp but not 3366 * the others. 3367 * 3368 * So in those cases, request a kvmclock update for all vcpus. 3369 * We need to rate-limit these requests though, as they can 3370 * considerably slow guests that have a large number of vcpus. 3371 * The time for a remote vcpu to update its kvmclock is bound 3372 * by the delay we use to rate-limit the updates. 3373 */ 3374 3375 #define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100) 3376 3377 static void kvmclock_update_fn(struct work_struct *work) 3378 { 3379 unsigned long i; 3380 struct delayed_work *dwork = to_delayed_work(work); 3381 struct kvm_arch *ka = container_of(dwork, struct kvm_arch, 3382 kvmclock_update_work); 3383 struct kvm *kvm = container_of(ka, struct kvm, arch); 3384 struct kvm_vcpu *vcpu; 3385 3386 kvm_for_each_vcpu(i, vcpu, kvm) { 3387 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 3388 kvm_vcpu_kick(vcpu); 3389 } 3390 } 3391 3392 static void kvm_gen_kvmclock_update(struct kvm_vcpu *v) 3393 { 3394 struct kvm *kvm = v->kvm; 3395 3396 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v); 3397 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 3398 KVMCLOCK_UPDATE_DELAY); 3399 } 3400 3401 #define KVMCLOCK_SYNC_PERIOD (300 * HZ) 3402 3403 static void kvmclock_sync_fn(struct work_struct *work) 3404 { 3405 struct delayed_work *dwork = to_delayed_work(work); 3406 struct kvm_arch *ka = container_of(dwork, struct kvm_arch, 3407 kvmclock_sync_work); 3408 struct kvm *kvm = container_of(ka, struct kvm, arch); 3409 3410 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0); 3411 schedule_delayed_work(&kvm->arch.kvmclock_sync_work, 3412 KVMCLOCK_SYNC_PERIOD); 3413 } 3414 3415 /* These helpers are safe iff @msr is known to be an MCx bank MSR. */ 3416 static bool is_mci_control_msr(u32 msr) 3417 { 3418 return (msr & 3) == 0; 3419 } 3420 static bool is_mci_status_msr(u32 msr) 3421 { 3422 return (msr & 3) == 1; 3423 } 3424 3425 /* 3426 * On AMD, HWCR[McStatusWrEn] controls whether setting MCi_STATUS results in #GP. 3427 */ 3428 static bool can_set_mci_status(struct kvm_vcpu *vcpu) 3429 { 3430 /* McStatusWrEn enabled? */ 3431 if (guest_cpuid_is_amd_compatible(vcpu)) 3432 return !!(vcpu->arch.msr_hwcr & BIT_ULL(18)); 3433 3434 return false; 3435 } 3436 3437 static int set_msr_mce(struct kvm_vcpu *vcpu, struct msr_data *msr_info) 3438 { 3439 u64 mcg_cap = vcpu->arch.mcg_cap; 3440 unsigned bank_num = mcg_cap & 0xff; 3441 u32 msr = msr_info->index; 3442 u64 data = msr_info->data; 3443 u32 offset, last_msr; 3444 3445 switch (msr) { 3446 case MSR_IA32_MCG_STATUS: 3447 vcpu->arch.mcg_status = data; 3448 break; 3449 case MSR_IA32_MCG_CTL: 3450 if (!(mcg_cap & MCG_CTL_P) && 3451 (data || !msr_info->host_initiated)) 3452 return 1; 3453 if (data != 0 && data != ~(u64)0) 3454 return 1; 3455 vcpu->arch.mcg_ctl = data; 3456 break; 3457 case MSR_IA32_MC0_CTL2 ... MSR_IA32_MCx_CTL2(KVM_MAX_MCE_BANKS) - 1: 3458 last_msr = MSR_IA32_MCx_CTL2(bank_num) - 1; 3459 if (msr > last_msr) 3460 return 1; 3461 3462 if (!(mcg_cap & MCG_CMCI_P) && (data || !msr_info->host_initiated)) 3463 return 1; 3464 /* An attempt to write a 1 to a reserved bit raises #GP */ 3465 if (data & ~(MCI_CTL2_CMCI_EN | MCI_CTL2_CMCI_THRESHOLD_MASK)) 3466 return 1; 3467 offset = array_index_nospec(msr - MSR_IA32_MC0_CTL2, 3468 last_msr + 1 - MSR_IA32_MC0_CTL2); 3469 vcpu->arch.mci_ctl2_banks[offset] = data; 3470 break; 3471 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1: 3472 last_msr = MSR_IA32_MCx_CTL(bank_num) - 1; 3473 if (msr > last_msr) 3474 return 1; 3475 3476 /* 3477 * Only 0 or all 1s can be written to IA32_MCi_CTL, all other 3478 * values are architecturally undefined. But, some Linux 3479 * kernels clear bit 10 in bank 4 to workaround a BIOS/GART TLB 3480 * issue on AMD K8s, allow bit 10 to be clear when setting all 3481 * other bits in order to avoid an uncaught #GP in the guest. 3482 * 3483 * UNIXWARE clears bit 0 of MC1_CTL to ignore correctable, 3484 * single-bit ECC data errors. 3485 */ 3486 if (is_mci_control_msr(msr) && 3487 data != 0 && (data | (1 << 10) | 1) != ~(u64)0) 3488 return 1; 3489 3490 /* 3491 * All CPUs allow writing 0 to MCi_STATUS MSRs to clear the MSR. 3492 * AMD-based CPUs allow non-zero values, but if and only if 3493 * HWCR[McStatusWrEn] is set. 3494 */ 3495 if (!msr_info->host_initiated && is_mci_status_msr(msr) && 3496 data != 0 && !can_set_mci_status(vcpu)) 3497 return 1; 3498 3499 offset = array_index_nospec(msr - MSR_IA32_MC0_CTL, 3500 last_msr + 1 - MSR_IA32_MC0_CTL); 3501 vcpu->arch.mce_banks[offset] = data; 3502 break; 3503 default: 3504 return 1; 3505 } 3506 return 0; 3507 } 3508 3509 static inline bool kvm_pv_async_pf_enabled(struct kvm_vcpu *vcpu) 3510 { 3511 u64 mask = KVM_ASYNC_PF_ENABLED | KVM_ASYNC_PF_DELIVERY_AS_INT; 3512 3513 return (vcpu->arch.apf.msr_en_val & mask) == mask; 3514 } 3515 3516 static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data) 3517 { 3518 gpa_t gpa = data & ~0x3f; 3519 3520 /* Bits 4:5 are reserved, Should be zero */ 3521 if (data & 0x30) 3522 return 1; 3523 3524 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_VMEXIT) && 3525 (data & KVM_ASYNC_PF_DELIVERY_AS_PF_VMEXIT)) 3526 return 1; 3527 3528 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_INT) && 3529 (data & KVM_ASYNC_PF_DELIVERY_AS_INT)) 3530 return 1; 3531 3532 if (!lapic_in_kernel(vcpu)) 3533 return data ? 1 : 0; 3534 3535 vcpu->arch.apf.msr_en_val = data; 3536 3537 if (!kvm_pv_async_pf_enabled(vcpu)) { 3538 kvm_clear_async_pf_completion_queue(vcpu); 3539 kvm_async_pf_hash_reset(vcpu); 3540 return 0; 3541 } 3542 3543 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa, 3544 sizeof(u64))) 3545 return 1; 3546 3547 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS); 3548 vcpu->arch.apf.delivery_as_pf_vmexit = data & KVM_ASYNC_PF_DELIVERY_AS_PF_VMEXIT; 3549 3550 kvm_async_pf_wakeup_all(vcpu); 3551 3552 return 0; 3553 } 3554 3555 static int kvm_pv_enable_async_pf_int(struct kvm_vcpu *vcpu, u64 data) 3556 { 3557 /* Bits 8-63 are reserved */ 3558 if (data >> 8) 3559 return 1; 3560 3561 if (!lapic_in_kernel(vcpu)) 3562 return 1; 3563 3564 vcpu->arch.apf.msr_int_val = data; 3565 3566 vcpu->arch.apf.vec = data & KVM_ASYNC_PF_VEC_MASK; 3567 3568 return 0; 3569 } 3570 3571 static void kvmclock_reset(struct kvm_vcpu *vcpu) 3572 { 3573 kvm_gpc_deactivate(&vcpu->arch.pv_time); 3574 vcpu->arch.time = 0; 3575 } 3576 3577 static void kvm_vcpu_flush_tlb_all(struct kvm_vcpu *vcpu) 3578 { 3579 ++vcpu->stat.tlb_flush; 3580 kvm_x86_call(flush_tlb_all)(vcpu); 3581 3582 /* Flushing all ASIDs flushes the current ASID... */ 3583 kvm_clear_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu); 3584 } 3585 3586 static void kvm_vcpu_flush_tlb_guest(struct kvm_vcpu *vcpu) 3587 { 3588 ++vcpu->stat.tlb_flush; 3589 3590 if (!tdp_enabled) { 3591 /* 3592 * A TLB flush on behalf of the guest is equivalent to 3593 * INVPCID(all), toggling CR4.PGE, etc., which requires 3594 * a forced sync of the shadow page tables. Ensure all the 3595 * roots are synced and the guest TLB in hardware is clean. 3596 */ 3597 kvm_mmu_sync_roots(vcpu); 3598 kvm_mmu_sync_prev_roots(vcpu); 3599 } 3600 3601 kvm_x86_call(flush_tlb_guest)(vcpu); 3602 3603 /* 3604 * Flushing all "guest" TLB is always a superset of Hyper-V's fine 3605 * grained flushing. 3606 */ 3607 kvm_hv_vcpu_purge_flush_tlb(vcpu); 3608 } 3609 3610 3611 static inline void kvm_vcpu_flush_tlb_current(struct kvm_vcpu *vcpu) 3612 { 3613 ++vcpu->stat.tlb_flush; 3614 kvm_x86_call(flush_tlb_current)(vcpu); 3615 } 3616 3617 /* 3618 * Service "local" TLB flush requests, which are specific to the current MMU 3619 * context. In addition to the generic event handling in vcpu_enter_guest(), 3620 * TLB flushes that are targeted at an MMU context also need to be serviced 3621 * prior before nested VM-Enter/VM-Exit. 3622 */ 3623 void kvm_service_local_tlb_flush_requests(struct kvm_vcpu *vcpu) 3624 { 3625 if (kvm_check_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu)) 3626 kvm_vcpu_flush_tlb_current(vcpu); 3627 3628 if (kvm_check_request(KVM_REQ_TLB_FLUSH_GUEST, vcpu)) 3629 kvm_vcpu_flush_tlb_guest(vcpu); 3630 } 3631 EXPORT_SYMBOL_GPL(kvm_service_local_tlb_flush_requests); 3632 3633 static void record_steal_time(struct kvm_vcpu *vcpu) 3634 { 3635 struct gfn_to_hva_cache *ghc = &vcpu->arch.st.cache; 3636 struct kvm_steal_time __user *st; 3637 struct kvm_memslots *slots; 3638 gpa_t gpa = vcpu->arch.st.msr_val & KVM_STEAL_VALID_BITS; 3639 u64 steal; 3640 u32 version; 3641 3642 if (kvm_xen_msr_enabled(vcpu->kvm)) { 3643 kvm_xen_runstate_set_running(vcpu); 3644 return; 3645 } 3646 3647 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED)) 3648 return; 3649 3650 if (WARN_ON_ONCE(current->mm != vcpu->kvm->mm)) 3651 return; 3652 3653 slots = kvm_memslots(vcpu->kvm); 3654 3655 if (unlikely(slots->generation != ghc->generation || 3656 gpa != ghc->gpa || 3657 kvm_is_error_hva(ghc->hva) || !ghc->memslot)) { 3658 /* We rely on the fact that it fits in a single page. */ 3659 BUILD_BUG_ON((sizeof(*st) - 1) & KVM_STEAL_VALID_BITS); 3660 3661 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, ghc, gpa, sizeof(*st)) || 3662 kvm_is_error_hva(ghc->hva) || !ghc->memslot) 3663 return; 3664 } 3665 3666 st = (struct kvm_steal_time __user *)ghc->hva; 3667 /* 3668 * Doing a TLB flush here, on the guest's behalf, can avoid 3669 * expensive IPIs. 3670 */ 3671 if (guest_pv_has(vcpu, KVM_FEATURE_PV_TLB_FLUSH)) { 3672 u8 st_preempted = 0; 3673 int err = -EFAULT; 3674 3675 if (!user_access_begin(st, sizeof(*st))) 3676 return; 3677 3678 asm volatile("1: xchgb %0, %2\n" 3679 "xor %1, %1\n" 3680 "2:\n" 3681 _ASM_EXTABLE_UA(1b, 2b) 3682 : "+q" (st_preempted), 3683 "+&r" (err), 3684 "+m" (st->preempted)); 3685 if (err) 3686 goto out; 3687 3688 user_access_end(); 3689 3690 vcpu->arch.st.preempted = 0; 3691 3692 trace_kvm_pv_tlb_flush(vcpu->vcpu_id, 3693 st_preempted & KVM_VCPU_FLUSH_TLB); 3694 if (st_preempted & KVM_VCPU_FLUSH_TLB) 3695 kvm_vcpu_flush_tlb_guest(vcpu); 3696 3697 if (!user_access_begin(st, sizeof(*st))) 3698 goto dirty; 3699 } else { 3700 if (!user_access_begin(st, sizeof(*st))) 3701 return; 3702 3703 unsafe_put_user(0, &st->preempted, out); 3704 vcpu->arch.st.preempted = 0; 3705 } 3706 3707 unsafe_get_user(version, &st->version, out); 3708 if (version & 1) 3709 version += 1; /* first time write, random junk */ 3710 3711 version += 1; 3712 unsafe_put_user(version, &st->version, out); 3713 3714 smp_wmb(); 3715 3716 unsafe_get_user(steal, &st->steal, out); 3717 steal += current->sched_info.run_delay - 3718 vcpu->arch.st.last_steal; 3719 vcpu->arch.st.last_steal = current->sched_info.run_delay; 3720 unsafe_put_user(steal, &st->steal, out); 3721 3722 version += 1; 3723 unsafe_put_user(version, &st->version, out); 3724 3725 out: 3726 user_access_end(); 3727 dirty: 3728 mark_page_dirty_in_slot(vcpu->kvm, ghc->memslot, gpa_to_gfn(ghc->gpa)); 3729 } 3730 3731 int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info) 3732 { 3733 u32 msr = msr_info->index; 3734 u64 data = msr_info->data; 3735 3736 if (msr && msr == vcpu->kvm->arch.xen_hvm_config.msr) 3737 return kvm_xen_write_hypercall_page(vcpu, data); 3738 3739 switch (msr) { 3740 case MSR_AMD64_NB_CFG: 3741 case MSR_IA32_UCODE_WRITE: 3742 case MSR_VM_HSAVE_PA: 3743 case MSR_AMD64_PATCH_LOADER: 3744 case MSR_AMD64_BU_CFG2: 3745 case MSR_AMD64_DC_CFG: 3746 case MSR_AMD64_TW_CFG: 3747 case MSR_F15H_EX_CFG: 3748 break; 3749 3750 case MSR_IA32_UCODE_REV: 3751 if (msr_info->host_initiated) 3752 vcpu->arch.microcode_version = data; 3753 break; 3754 case MSR_IA32_ARCH_CAPABILITIES: 3755 if (!msr_info->host_initiated || 3756 !guest_cpu_cap_has(vcpu, X86_FEATURE_ARCH_CAPABILITIES)) 3757 return KVM_MSR_RET_UNSUPPORTED; 3758 vcpu->arch.arch_capabilities = data; 3759 break; 3760 case MSR_IA32_PERF_CAPABILITIES: 3761 if (!msr_info->host_initiated || 3762 !guest_cpu_cap_has(vcpu, X86_FEATURE_PDCM)) 3763 return KVM_MSR_RET_UNSUPPORTED; 3764 3765 if (data & ~kvm_caps.supported_perf_cap) 3766 return 1; 3767 3768 /* 3769 * Note, this is not just a performance optimization! KVM 3770 * disallows changing feature MSRs after the vCPU has run; PMU 3771 * refresh will bug the VM if called after the vCPU has run. 3772 */ 3773 if (vcpu->arch.perf_capabilities == data) 3774 break; 3775 3776 vcpu->arch.perf_capabilities = data; 3777 kvm_pmu_refresh(vcpu); 3778 break; 3779 case MSR_IA32_PRED_CMD: { 3780 u64 reserved_bits = ~(PRED_CMD_IBPB | PRED_CMD_SBPB); 3781 3782 if (!msr_info->host_initiated) { 3783 if ((!guest_has_pred_cmd_msr(vcpu))) 3784 return 1; 3785 3786 if (!guest_cpu_cap_has(vcpu, X86_FEATURE_SPEC_CTRL) && 3787 !guest_cpu_cap_has(vcpu, X86_FEATURE_AMD_IBPB)) 3788 reserved_bits |= PRED_CMD_IBPB; 3789 3790 if (!guest_cpu_cap_has(vcpu, X86_FEATURE_SBPB)) 3791 reserved_bits |= PRED_CMD_SBPB; 3792 } 3793 3794 if (!boot_cpu_has(X86_FEATURE_IBPB)) 3795 reserved_bits |= PRED_CMD_IBPB; 3796 3797 if (!boot_cpu_has(X86_FEATURE_SBPB)) 3798 reserved_bits |= PRED_CMD_SBPB; 3799 3800 if (data & reserved_bits) 3801 return 1; 3802 3803 if (!data) 3804 break; 3805 3806 wrmsrl(MSR_IA32_PRED_CMD, data); 3807 break; 3808 } 3809 case MSR_IA32_FLUSH_CMD: 3810 if (!msr_info->host_initiated && 3811 !guest_cpu_cap_has(vcpu, X86_FEATURE_FLUSH_L1D)) 3812 return 1; 3813 3814 if (!boot_cpu_has(X86_FEATURE_FLUSH_L1D) || (data & ~L1D_FLUSH)) 3815 return 1; 3816 if (!data) 3817 break; 3818 3819 wrmsrl(MSR_IA32_FLUSH_CMD, L1D_FLUSH); 3820 break; 3821 case MSR_EFER: 3822 return set_efer(vcpu, msr_info); 3823 case MSR_K7_HWCR: 3824 data &= ~(u64)0x40; /* ignore flush filter disable */ 3825 data &= ~(u64)0x100; /* ignore ignne emulation enable */ 3826 data &= ~(u64)0x8; /* ignore TLB cache disable */ 3827 3828 /* 3829 * Allow McStatusWrEn and TscFreqSel. (Linux guests from v3.2 3830 * through at least v6.6 whine if TscFreqSel is clear, 3831 * depending on F/M/S. 3832 */ 3833 if (data & ~(BIT_ULL(18) | BIT_ULL(24))) { 3834 kvm_pr_unimpl_wrmsr(vcpu, msr, data); 3835 return 1; 3836 } 3837 vcpu->arch.msr_hwcr = data; 3838 break; 3839 case MSR_FAM10H_MMIO_CONF_BASE: 3840 if (data != 0) { 3841 kvm_pr_unimpl_wrmsr(vcpu, msr, data); 3842 return 1; 3843 } 3844 break; 3845 case MSR_IA32_CR_PAT: 3846 if (!kvm_pat_valid(data)) 3847 return 1; 3848 3849 vcpu->arch.pat = data; 3850 break; 3851 case MTRRphysBase_MSR(0) ... MSR_MTRRfix4K_F8000: 3852 case MSR_MTRRdefType: 3853 return kvm_mtrr_set_msr(vcpu, msr, data); 3854 case MSR_IA32_APICBASE: 3855 return kvm_apic_set_base(vcpu, data, msr_info->host_initiated); 3856 case APIC_BASE_MSR ... APIC_BASE_MSR + 0xff: 3857 return kvm_x2apic_msr_write(vcpu, msr, data); 3858 case MSR_IA32_TSC_DEADLINE: 3859 kvm_set_lapic_tscdeadline_msr(vcpu, data); 3860 break; 3861 case MSR_IA32_TSC_ADJUST: 3862 if (guest_cpu_cap_has(vcpu, X86_FEATURE_TSC_ADJUST)) { 3863 if (!msr_info->host_initiated) { 3864 s64 adj = data - vcpu->arch.ia32_tsc_adjust_msr; 3865 adjust_tsc_offset_guest(vcpu, adj); 3866 /* Before back to guest, tsc_timestamp must be adjusted 3867 * as well, otherwise guest's percpu pvclock time could jump. 3868 */ 3869 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 3870 } 3871 vcpu->arch.ia32_tsc_adjust_msr = data; 3872 } 3873 break; 3874 case MSR_IA32_MISC_ENABLE: { 3875 u64 old_val = vcpu->arch.ia32_misc_enable_msr; 3876 3877 if (!msr_info->host_initiated) { 3878 /* RO bits */ 3879 if ((old_val ^ data) & MSR_IA32_MISC_ENABLE_PMU_RO_MASK) 3880 return 1; 3881 3882 /* R bits, i.e. writes are ignored, but don't fault. */ 3883 data = data & ~MSR_IA32_MISC_ENABLE_EMON; 3884 data |= old_val & MSR_IA32_MISC_ENABLE_EMON; 3885 } 3886 3887 if (!kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_MISC_ENABLE_NO_MWAIT) && 3888 ((old_val ^ data) & MSR_IA32_MISC_ENABLE_MWAIT)) { 3889 if (!guest_cpu_cap_has(vcpu, X86_FEATURE_XMM3)) 3890 return 1; 3891 vcpu->arch.ia32_misc_enable_msr = data; 3892 kvm_update_cpuid_runtime(vcpu); 3893 } else { 3894 vcpu->arch.ia32_misc_enable_msr = data; 3895 } 3896 break; 3897 } 3898 case MSR_IA32_SMBASE: 3899 if (!IS_ENABLED(CONFIG_KVM_SMM) || !msr_info->host_initiated) 3900 return 1; 3901 vcpu->arch.smbase = data; 3902 break; 3903 case MSR_IA32_POWER_CTL: 3904 vcpu->arch.msr_ia32_power_ctl = data; 3905 break; 3906 case MSR_IA32_TSC: 3907 if (msr_info->host_initiated) { 3908 kvm_synchronize_tsc(vcpu, &data); 3909 } else { 3910 u64 adj = kvm_compute_l1_tsc_offset(vcpu, data) - vcpu->arch.l1_tsc_offset; 3911 adjust_tsc_offset_guest(vcpu, adj); 3912 vcpu->arch.ia32_tsc_adjust_msr += adj; 3913 } 3914 break; 3915 case MSR_IA32_XSS: 3916 if (!msr_info->host_initiated && 3917 !guest_cpuid_has(vcpu, X86_FEATURE_XSAVES)) 3918 return 1; 3919 /* 3920 * KVM supports exposing PT to the guest, but does not support 3921 * IA32_XSS[bit 8]. Guests have to use RDMSR/WRMSR rather than 3922 * XSAVES/XRSTORS to save/restore PT MSRs. 3923 */ 3924 if (data & ~kvm_caps.supported_xss) 3925 return 1; 3926 vcpu->arch.ia32_xss = data; 3927 kvm_update_cpuid_runtime(vcpu); 3928 break; 3929 case MSR_SMI_COUNT: 3930 if (!msr_info->host_initiated) 3931 return 1; 3932 vcpu->arch.smi_count = data; 3933 break; 3934 case MSR_KVM_WALL_CLOCK_NEW: 3935 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE2)) 3936 return 1; 3937 3938 vcpu->kvm->arch.wall_clock = data; 3939 kvm_write_wall_clock(vcpu->kvm, data, 0); 3940 break; 3941 case MSR_KVM_WALL_CLOCK: 3942 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE)) 3943 return 1; 3944 3945 vcpu->kvm->arch.wall_clock = data; 3946 kvm_write_wall_clock(vcpu->kvm, data, 0); 3947 break; 3948 case MSR_KVM_SYSTEM_TIME_NEW: 3949 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE2)) 3950 return 1; 3951 3952 kvm_write_system_time(vcpu, data, false, msr_info->host_initiated); 3953 break; 3954 case MSR_KVM_SYSTEM_TIME: 3955 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE)) 3956 return 1; 3957 3958 kvm_write_system_time(vcpu, data, true, msr_info->host_initiated); 3959 break; 3960 case MSR_KVM_ASYNC_PF_EN: 3961 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF)) 3962 return 1; 3963 3964 if (kvm_pv_enable_async_pf(vcpu, data)) 3965 return 1; 3966 break; 3967 case MSR_KVM_ASYNC_PF_INT: 3968 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_INT)) 3969 return 1; 3970 3971 if (kvm_pv_enable_async_pf_int(vcpu, data)) 3972 return 1; 3973 break; 3974 case MSR_KVM_ASYNC_PF_ACK: 3975 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_INT)) 3976 return 1; 3977 if (data & 0x1) { 3978 vcpu->arch.apf.pageready_pending = false; 3979 kvm_check_async_pf_completion(vcpu); 3980 } 3981 break; 3982 case MSR_KVM_STEAL_TIME: 3983 if (!guest_pv_has(vcpu, KVM_FEATURE_STEAL_TIME)) 3984 return 1; 3985 3986 if (unlikely(!sched_info_on())) 3987 return 1; 3988 3989 if (data & KVM_STEAL_RESERVED_MASK) 3990 return 1; 3991 3992 vcpu->arch.st.msr_val = data; 3993 3994 if (!(data & KVM_MSR_ENABLED)) 3995 break; 3996 3997 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu); 3998 3999 break; 4000 case MSR_KVM_PV_EOI_EN: 4001 if (!guest_pv_has(vcpu, KVM_FEATURE_PV_EOI)) 4002 return 1; 4003 4004 if (kvm_lapic_set_pv_eoi(vcpu, data, sizeof(u8))) 4005 return 1; 4006 break; 4007 4008 case MSR_KVM_POLL_CONTROL: 4009 if (!guest_pv_has(vcpu, KVM_FEATURE_POLL_CONTROL)) 4010 return 1; 4011 4012 /* only enable bit supported */ 4013 if (data & (-1ULL << 1)) 4014 return 1; 4015 4016 vcpu->arch.msr_kvm_poll_control = data; 4017 break; 4018 4019 case MSR_IA32_MCG_CTL: 4020 case MSR_IA32_MCG_STATUS: 4021 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1: 4022 case MSR_IA32_MC0_CTL2 ... MSR_IA32_MCx_CTL2(KVM_MAX_MCE_BANKS) - 1: 4023 return set_msr_mce(vcpu, msr_info); 4024 4025 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3: 4026 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1: 4027 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3: 4028 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1: 4029 if (kvm_pmu_is_valid_msr(vcpu, msr)) 4030 return kvm_pmu_set_msr(vcpu, msr_info); 4031 4032 if (data) 4033 kvm_pr_unimpl_wrmsr(vcpu, msr, data); 4034 break; 4035 case MSR_K7_CLK_CTL: 4036 /* 4037 * Ignore all writes to this no longer documented MSR. 4038 * Writes are only relevant for old K7 processors, 4039 * all pre-dating SVM, but a recommended workaround from 4040 * AMD for these chips. It is possible to specify the 4041 * affected processor models on the command line, hence 4042 * the need to ignore the workaround. 4043 */ 4044 break; 4045 #ifdef CONFIG_KVM_HYPERV 4046 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15: 4047 case HV_X64_MSR_SYNDBG_CONTROL ... HV_X64_MSR_SYNDBG_PENDING_BUFFER: 4048 case HV_X64_MSR_SYNDBG_OPTIONS: 4049 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4: 4050 case HV_X64_MSR_CRASH_CTL: 4051 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT: 4052 case HV_X64_MSR_REENLIGHTENMENT_CONTROL: 4053 case HV_X64_MSR_TSC_EMULATION_CONTROL: 4054 case HV_X64_MSR_TSC_EMULATION_STATUS: 4055 case HV_X64_MSR_TSC_INVARIANT_CONTROL: 4056 return kvm_hv_set_msr_common(vcpu, msr, data, 4057 msr_info->host_initiated); 4058 #endif 4059 case MSR_IA32_BBL_CR_CTL3: 4060 /* Drop writes to this legacy MSR -- see rdmsr 4061 * counterpart for further detail. 4062 */ 4063 kvm_pr_unimpl_wrmsr(vcpu, msr, data); 4064 break; 4065 case MSR_AMD64_OSVW_ID_LENGTH: 4066 if (!guest_cpu_cap_has(vcpu, X86_FEATURE_OSVW)) 4067 return 1; 4068 vcpu->arch.osvw.length = data; 4069 break; 4070 case MSR_AMD64_OSVW_STATUS: 4071 if (!guest_cpu_cap_has(vcpu, X86_FEATURE_OSVW)) 4072 return 1; 4073 vcpu->arch.osvw.status = data; 4074 break; 4075 case MSR_PLATFORM_INFO: 4076 if (!msr_info->host_initiated) 4077 return 1; 4078 vcpu->arch.msr_platform_info = data; 4079 break; 4080 case MSR_MISC_FEATURES_ENABLES: 4081 if (data & ~MSR_MISC_FEATURES_ENABLES_CPUID_FAULT || 4082 (data & MSR_MISC_FEATURES_ENABLES_CPUID_FAULT && 4083 !supports_cpuid_fault(vcpu))) 4084 return 1; 4085 vcpu->arch.msr_misc_features_enables = data; 4086 break; 4087 #ifdef CONFIG_X86_64 4088 case MSR_IA32_XFD: 4089 if (!msr_info->host_initiated && 4090 !guest_cpu_cap_has(vcpu, X86_FEATURE_XFD)) 4091 return 1; 4092 4093 if (data & ~kvm_guest_supported_xfd(vcpu)) 4094 return 1; 4095 4096 fpu_update_guest_xfd(&vcpu->arch.guest_fpu, data); 4097 break; 4098 case MSR_IA32_XFD_ERR: 4099 if (!msr_info->host_initiated && 4100 !guest_cpu_cap_has(vcpu, X86_FEATURE_XFD)) 4101 return 1; 4102 4103 if (data & ~kvm_guest_supported_xfd(vcpu)) 4104 return 1; 4105 4106 vcpu->arch.guest_fpu.xfd_err = data; 4107 break; 4108 #endif 4109 default: 4110 if (kvm_pmu_is_valid_msr(vcpu, msr)) 4111 return kvm_pmu_set_msr(vcpu, msr_info); 4112 4113 return KVM_MSR_RET_UNSUPPORTED; 4114 } 4115 return 0; 4116 } 4117 EXPORT_SYMBOL_GPL(kvm_set_msr_common); 4118 4119 static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata, bool host) 4120 { 4121 u64 data; 4122 u64 mcg_cap = vcpu->arch.mcg_cap; 4123 unsigned bank_num = mcg_cap & 0xff; 4124 u32 offset, last_msr; 4125 4126 switch (msr) { 4127 case MSR_IA32_P5_MC_ADDR: 4128 case MSR_IA32_P5_MC_TYPE: 4129 data = 0; 4130 break; 4131 case MSR_IA32_MCG_CAP: 4132 data = vcpu->arch.mcg_cap; 4133 break; 4134 case MSR_IA32_MCG_CTL: 4135 if (!(mcg_cap & MCG_CTL_P) && !host) 4136 return 1; 4137 data = vcpu->arch.mcg_ctl; 4138 break; 4139 case MSR_IA32_MCG_STATUS: 4140 data = vcpu->arch.mcg_status; 4141 break; 4142 case MSR_IA32_MC0_CTL2 ... MSR_IA32_MCx_CTL2(KVM_MAX_MCE_BANKS) - 1: 4143 last_msr = MSR_IA32_MCx_CTL2(bank_num) - 1; 4144 if (msr > last_msr) 4145 return 1; 4146 4147 if (!(mcg_cap & MCG_CMCI_P) && !host) 4148 return 1; 4149 offset = array_index_nospec(msr - MSR_IA32_MC0_CTL2, 4150 last_msr + 1 - MSR_IA32_MC0_CTL2); 4151 data = vcpu->arch.mci_ctl2_banks[offset]; 4152 break; 4153 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1: 4154 last_msr = MSR_IA32_MCx_CTL(bank_num) - 1; 4155 if (msr > last_msr) 4156 return 1; 4157 4158 offset = array_index_nospec(msr - MSR_IA32_MC0_CTL, 4159 last_msr + 1 - MSR_IA32_MC0_CTL); 4160 data = vcpu->arch.mce_banks[offset]; 4161 break; 4162 default: 4163 return 1; 4164 } 4165 *pdata = data; 4166 return 0; 4167 } 4168 4169 int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info) 4170 { 4171 switch (msr_info->index) { 4172 case MSR_IA32_PLATFORM_ID: 4173 case MSR_IA32_EBL_CR_POWERON: 4174 case MSR_IA32_LASTBRANCHFROMIP: 4175 case MSR_IA32_LASTBRANCHTOIP: 4176 case MSR_IA32_LASTINTFROMIP: 4177 case MSR_IA32_LASTINTTOIP: 4178 case MSR_AMD64_SYSCFG: 4179 case MSR_K8_TSEG_ADDR: 4180 case MSR_K8_TSEG_MASK: 4181 case MSR_VM_HSAVE_PA: 4182 case MSR_K8_INT_PENDING_MSG: 4183 case MSR_AMD64_NB_CFG: 4184 case MSR_FAM10H_MMIO_CONF_BASE: 4185 case MSR_AMD64_BU_CFG2: 4186 case MSR_IA32_PERF_CTL: 4187 case MSR_AMD64_DC_CFG: 4188 case MSR_AMD64_TW_CFG: 4189 case MSR_F15H_EX_CFG: 4190 /* 4191 * Intel Sandy Bridge CPUs must support the RAPL (running average power 4192 * limit) MSRs. Just return 0, as we do not want to expose the host 4193 * data here. Do not conditionalize this on CPUID, as KVM does not do 4194 * so for existing CPU-specific MSRs. 4195 */ 4196 case MSR_RAPL_POWER_UNIT: 4197 case MSR_PP0_ENERGY_STATUS: /* Power plane 0 (core) */ 4198 case MSR_PP1_ENERGY_STATUS: /* Power plane 1 (graphics uncore) */ 4199 case MSR_PKG_ENERGY_STATUS: /* Total package */ 4200 case MSR_DRAM_ENERGY_STATUS: /* DRAM controller */ 4201 msr_info->data = 0; 4202 break; 4203 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3: 4204 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3: 4205 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1: 4206 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1: 4207 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index)) 4208 return kvm_pmu_get_msr(vcpu, msr_info); 4209 msr_info->data = 0; 4210 break; 4211 case MSR_IA32_UCODE_REV: 4212 msr_info->data = vcpu->arch.microcode_version; 4213 break; 4214 case MSR_IA32_ARCH_CAPABILITIES: 4215 if (!guest_cpu_cap_has(vcpu, X86_FEATURE_ARCH_CAPABILITIES)) 4216 return KVM_MSR_RET_UNSUPPORTED; 4217 msr_info->data = vcpu->arch.arch_capabilities; 4218 break; 4219 case MSR_IA32_PERF_CAPABILITIES: 4220 if (!guest_cpu_cap_has(vcpu, X86_FEATURE_PDCM)) 4221 return KVM_MSR_RET_UNSUPPORTED; 4222 msr_info->data = vcpu->arch.perf_capabilities; 4223 break; 4224 case MSR_IA32_POWER_CTL: 4225 msr_info->data = vcpu->arch.msr_ia32_power_ctl; 4226 break; 4227 case MSR_IA32_TSC: { 4228 /* 4229 * Intel SDM states that MSR_IA32_TSC read adds the TSC offset 4230 * even when not intercepted. AMD manual doesn't explicitly 4231 * state this but appears to behave the same. 4232 * 4233 * On userspace reads and writes, however, we unconditionally 4234 * return L1's TSC value to ensure backwards-compatible 4235 * behavior for migration. 4236 */ 4237 u64 offset, ratio; 4238 4239 if (msr_info->host_initiated) { 4240 offset = vcpu->arch.l1_tsc_offset; 4241 ratio = vcpu->arch.l1_tsc_scaling_ratio; 4242 } else { 4243 offset = vcpu->arch.tsc_offset; 4244 ratio = vcpu->arch.tsc_scaling_ratio; 4245 } 4246 4247 msr_info->data = kvm_scale_tsc(rdtsc(), ratio) + offset; 4248 break; 4249 } 4250 case MSR_IA32_CR_PAT: 4251 msr_info->data = vcpu->arch.pat; 4252 break; 4253 case MSR_MTRRcap: 4254 case MTRRphysBase_MSR(0) ... MSR_MTRRfix4K_F8000: 4255 case MSR_MTRRdefType: 4256 return kvm_mtrr_get_msr(vcpu, msr_info->index, &msr_info->data); 4257 case 0xcd: /* fsb frequency */ 4258 msr_info->data = 3; 4259 break; 4260 /* 4261 * MSR_EBC_FREQUENCY_ID 4262 * Conservative value valid for even the basic CPU models. 4263 * Models 0,1: 000 in bits 23:21 indicating a bus speed of 4264 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz, 4265 * and 266MHz for model 3, or 4. Set Core Clock 4266 * Frequency to System Bus Frequency Ratio to 1 (bits 4267 * 31:24) even though these are only valid for CPU 4268 * models > 2, however guests may end up dividing or 4269 * multiplying by zero otherwise. 4270 */ 4271 case MSR_EBC_FREQUENCY_ID: 4272 msr_info->data = 1 << 24; 4273 break; 4274 case MSR_IA32_APICBASE: 4275 msr_info->data = vcpu->arch.apic_base; 4276 break; 4277 case APIC_BASE_MSR ... APIC_BASE_MSR + 0xff: 4278 return kvm_x2apic_msr_read(vcpu, msr_info->index, &msr_info->data); 4279 case MSR_IA32_TSC_DEADLINE: 4280 msr_info->data = kvm_get_lapic_tscdeadline_msr(vcpu); 4281 break; 4282 case MSR_IA32_TSC_ADJUST: 4283 msr_info->data = (u64)vcpu->arch.ia32_tsc_adjust_msr; 4284 break; 4285 case MSR_IA32_MISC_ENABLE: 4286 msr_info->data = vcpu->arch.ia32_misc_enable_msr; 4287 break; 4288 case MSR_IA32_SMBASE: 4289 if (!IS_ENABLED(CONFIG_KVM_SMM) || !msr_info->host_initiated) 4290 return 1; 4291 msr_info->data = vcpu->arch.smbase; 4292 break; 4293 case MSR_SMI_COUNT: 4294 msr_info->data = vcpu->arch.smi_count; 4295 break; 4296 case MSR_IA32_PERF_STATUS: 4297 /* TSC increment by tick */ 4298 msr_info->data = 1000ULL; 4299 /* CPU multiplier */ 4300 msr_info->data |= (((uint64_t)4ULL) << 40); 4301 break; 4302 case MSR_EFER: 4303 msr_info->data = vcpu->arch.efer; 4304 break; 4305 case MSR_KVM_WALL_CLOCK: 4306 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE)) 4307 return 1; 4308 4309 msr_info->data = vcpu->kvm->arch.wall_clock; 4310 break; 4311 case MSR_KVM_WALL_CLOCK_NEW: 4312 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE2)) 4313 return 1; 4314 4315 msr_info->data = vcpu->kvm->arch.wall_clock; 4316 break; 4317 case MSR_KVM_SYSTEM_TIME: 4318 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE)) 4319 return 1; 4320 4321 msr_info->data = vcpu->arch.time; 4322 break; 4323 case MSR_KVM_SYSTEM_TIME_NEW: 4324 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE2)) 4325 return 1; 4326 4327 msr_info->data = vcpu->arch.time; 4328 break; 4329 case MSR_KVM_ASYNC_PF_EN: 4330 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF)) 4331 return 1; 4332 4333 msr_info->data = vcpu->arch.apf.msr_en_val; 4334 break; 4335 case MSR_KVM_ASYNC_PF_INT: 4336 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_INT)) 4337 return 1; 4338 4339 msr_info->data = vcpu->arch.apf.msr_int_val; 4340 break; 4341 case MSR_KVM_ASYNC_PF_ACK: 4342 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_INT)) 4343 return 1; 4344 4345 msr_info->data = 0; 4346 break; 4347 case MSR_KVM_STEAL_TIME: 4348 if (!guest_pv_has(vcpu, KVM_FEATURE_STEAL_TIME)) 4349 return 1; 4350 4351 msr_info->data = vcpu->arch.st.msr_val; 4352 break; 4353 case MSR_KVM_PV_EOI_EN: 4354 if (!guest_pv_has(vcpu, KVM_FEATURE_PV_EOI)) 4355 return 1; 4356 4357 msr_info->data = vcpu->arch.pv_eoi.msr_val; 4358 break; 4359 case MSR_KVM_POLL_CONTROL: 4360 if (!guest_pv_has(vcpu, KVM_FEATURE_POLL_CONTROL)) 4361 return 1; 4362 4363 msr_info->data = vcpu->arch.msr_kvm_poll_control; 4364 break; 4365 case MSR_IA32_P5_MC_ADDR: 4366 case MSR_IA32_P5_MC_TYPE: 4367 case MSR_IA32_MCG_CAP: 4368 case MSR_IA32_MCG_CTL: 4369 case MSR_IA32_MCG_STATUS: 4370 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1: 4371 case MSR_IA32_MC0_CTL2 ... MSR_IA32_MCx_CTL2(KVM_MAX_MCE_BANKS) - 1: 4372 return get_msr_mce(vcpu, msr_info->index, &msr_info->data, 4373 msr_info->host_initiated); 4374 case MSR_IA32_XSS: 4375 if (!msr_info->host_initiated && 4376 !guest_cpuid_has(vcpu, X86_FEATURE_XSAVES)) 4377 return 1; 4378 msr_info->data = vcpu->arch.ia32_xss; 4379 break; 4380 case MSR_K7_CLK_CTL: 4381 /* 4382 * Provide expected ramp-up count for K7. All other 4383 * are set to zero, indicating minimum divisors for 4384 * every field. 4385 * 4386 * This prevents guest kernels on AMD host with CPU 4387 * type 6, model 8 and higher from exploding due to 4388 * the rdmsr failing. 4389 */ 4390 msr_info->data = 0x20000000; 4391 break; 4392 #ifdef CONFIG_KVM_HYPERV 4393 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15: 4394 case HV_X64_MSR_SYNDBG_CONTROL ... HV_X64_MSR_SYNDBG_PENDING_BUFFER: 4395 case HV_X64_MSR_SYNDBG_OPTIONS: 4396 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4: 4397 case HV_X64_MSR_CRASH_CTL: 4398 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT: 4399 case HV_X64_MSR_REENLIGHTENMENT_CONTROL: 4400 case HV_X64_MSR_TSC_EMULATION_CONTROL: 4401 case HV_X64_MSR_TSC_EMULATION_STATUS: 4402 case HV_X64_MSR_TSC_INVARIANT_CONTROL: 4403 return kvm_hv_get_msr_common(vcpu, 4404 msr_info->index, &msr_info->data, 4405 msr_info->host_initiated); 4406 #endif 4407 case MSR_IA32_BBL_CR_CTL3: 4408 /* This legacy MSR exists but isn't fully documented in current 4409 * silicon. It is however accessed by winxp in very narrow 4410 * scenarios where it sets bit #19, itself documented as 4411 * a "reserved" bit. Best effort attempt to source coherent 4412 * read data here should the balance of the register be 4413 * interpreted by the guest: 4414 * 4415 * L2 cache control register 3: 64GB range, 256KB size, 4416 * enabled, latency 0x1, configured 4417 */ 4418 msr_info->data = 0xbe702111; 4419 break; 4420 case MSR_AMD64_OSVW_ID_LENGTH: 4421 if (!guest_cpu_cap_has(vcpu, X86_FEATURE_OSVW)) 4422 return 1; 4423 msr_info->data = vcpu->arch.osvw.length; 4424 break; 4425 case MSR_AMD64_OSVW_STATUS: 4426 if (!guest_cpu_cap_has(vcpu, X86_FEATURE_OSVW)) 4427 return 1; 4428 msr_info->data = vcpu->arch.osvw.status; 4429 break; 4430 case MSR_PLATFORM_INFO: 4431 if (!msr_info->host_initiated && 4432 !vcpu->kvm->arch.guest_can_read_msr_platform_info) 4433 return 1; 4434 msr_info->data = vcpu->arch.msr_platform_info; 4435 break; 4436 case MSR_MISC_FEATURES_ENABLES: 4437 msr_info->data = vcpu->arch.msr_misc_features_enables; 4438 break; 4439 case MSR_K7_HWCR: 4440 msr_info->data = vcpu->arch.msr_hwcr; 4441 break; 4442 #ifdef CONFIG_X86_64 4443 case MSR_IA32_XFD: 4444 if (!msr_info->host_initiated && 4445 !guest_cpu_cap_has(vcpu, X86_FEATURE_XFD)) 4446 return 1; 4447 4448 msr_info->data = vcpu->arch.guest_fpu.fpstate->xfd; 4449 break; 4450 case MSR_IA32_XFD_ERR: 4451 if (!msr_info->host_initiated && 4452 !guest_cpu_cap_has(vcpu, X86_FEATURE_XFD)) 4453 return 1; 4454 4455 msr_info->data = vcpu->arch.guest_fpu.xfd_err; 4456 break; 4457 #endif 4458 default: 4459 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index)) 4460 return kvm_pmu_get_msr(vcpu, msr_info); 4461 4462 return KVM_MSR_RET_UNSUPPORTED; 4463 } 4464 return 0; 4465 } 4466 EXPORT_SYMBOL_GPL(kvm_get_msr_common); 4467 4468 /* 4469 * Read or write a bunch of msrs. All parameters are kernel addresses. 4470 * 4471 * @return number of msrs set successfully. 4472 */ 4473 static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs, 4474 struct kvm_msr_entry *entries, 4475 int (*do_msr)(struct kvm_vcpu *vcpu, 4476 unsigned index, u64 *data)) 4477 { 4478 int i; 4479 4480 for (i = 0; i < msrs->nmsrs; ++i) 4481 if (do_msr(vcpu, entries[i].index, &entries[i].data)) 4482 break; 4483 4484 return i; 4485 } 4486 4487 /* 4488 * Read or write a bunch of msrs. Parameters are user addresses. 4489 * 4490 * @return number of msrs set successfully. 4491 */ 4492 static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs, 4493 int (*do_msr)(struct kvm_vcpu *vcpu, 4494 unsigned index, u64 *data), 4495 int writeback) 4496 { 4497 struct kvm_msrs msrs; 4498 struct kvm_msr_entry *entries; 4499 unsigned size; 4500 int r; 4501 4502 r = -EFAULT; 4503 if (copy_from_user(&msrs, user_msrs, sizeof(msrs))) 4504 goto out; 4505 4506 r = -E2BIG; 4507 if (msrs.nmsrs >= MAX_IO_MSRS) 4508 goto out; 4509 4510 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs; 4511 entries = memdup_user(user_msrs->entries, size); 4512 if (IS_ERR(entries)) { 4513 r = PTR_ERR(entries); 4514 goto out; 4515 } 4516 4517 r = __msr_io(vcpu, &msrs, entries, do_msr); 4518 4519 if (writeback && copy_to_user(user_msrs->entries, entries, size)) 4520 r = -EFAULT; 4521 4522 kfree(entries); 4523 out: 4524 return r; 4525 } 4526 4527 static inline bool kvm_can_mwait_in_guest(void) 4528 { 4529 return boot_cpu_has(X86_FEATURE_MWAIT) && 4530 !boot_cpu_has_bug(X86_BUG_MONITOR) && 4531 boot_cpu_has(X86_FEATURE_ARAT); 4532 } 4533 4534 static u64 kvm_get_allowed_disable_exits(void) 4535 { 4536 u64 r = KVM_X86_DISABLE_EXITS_PAUSE; 4537 4538 if (!mitigate_smt_rsb) { 4539 r |= KVM_X86_DISABLE_EXITS_HLT | 4540 KVM_X86_DISABLE_EXITS_CSTATE; 4541 4542 if (kvm_can_mwait_in_guest()) 4543 r |= KVM_X86_DISABLE_EXITS_MWAIT; 4544 } 4545 return r; 4546 } 4547 4548 #ifdef CONFIG_KVM_HYPERV 4549 static int kvm_ioctl_get_supported_hv_cpuid(struct kvm_vcpu *vcpu, 4550 struct kvm_cpuid2 __user *cpuid_arg) 4551 { 4552 struct kvm_cpuid2 cpuid; 4553 int r; 4554 4555 r = -EFAULT; 4556 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid))) 4557 return r; 4558 4559 r = kvm_get_hv_cpuid(vcpu, &cpuid, cpuid_arg->entries); 4560 if (r) 4561 return r; 4562 4563 r = -EFAULT; 4564 if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid))) 4565 return r; 4566 4567 return 0; 4568 } 4569 #endif 4570 4571 static bool kvm_is_vm_type_supported(unsigned long type) 4572 { 4573 return type < 32 && (kvm_caps.supported_vm_types & BIT(type)); 4574 } 4575 4576 int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext) 4577 { 4578 int r = 0; 4579 4580 switch (ext) { 4581 case KVM_CAP_IRQCHIP: 4582 case KVM_CAP_HLT: 4583 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL: 4584 case KVM_CAP_SET_TSS_ADDR: 4585 case KVM_CAP_EXT_CPUID: 4586 case KVM_CAP_EXT_EMUL_CPUID: 4587 case KVM_CAP_CLOCKSOURCE: 4588 case KVM_CAP_PIT: 4589 case KVM_CAP_NOP_IO_DELAY: 4590 case KVM_CAP_MP_STATE: 4591 case KVM_CAP_SYNC_MMU: 4592 case KVM_CAP_USER_NMI: 4593 case KVM_CAP_REINJECT_CONTROL: 4594 case KVM_CAP_IRQ_INJECT_STATUS: 4595 case KVM_CAP_IOEVENTFD: 4596 case KVM_CAP_IOEVENTFD_NO_LENGTH: 4597 case KVM_CAP_PIT2: 4598 case KVM_CAP_PIT_STATE2: 4599 case KVM_CAP_SET_IDENTITY_MAP_ADDR: 4600 case KVM_CAP_VCPU_EVENTS: 4601 #ifdef CONFIG_KVM_HYPERV 4602 case KVM_CAP_HYPERV: 4603 case KVM_CAP_HYPERV_VAPIC: 4604 case KVM_CAP_HYPERV_SPIN: 4605 case KVM_CAP_HYPERV_TIME: 4606 case KVM_CAP_HYPERV_SYNIC: 4607 case KVM_CAP_HYPERV_SYNIC2: 4608 case KVM_CAP_HYPERV_VP_INDEX: 4609 case KVM_CAP_HYPERV_EVENTFD: 4610 case KVM_CAP_HYPERV_TLBFLUSH: 4611 case KVM_CAP_HYPERV_SEND_IPI: 4612 case KVM_CAP_HYPERV_CPUID: 4613 case KVM_CAP_HYPERV_ENFORCE_CPUID: 4614 case KVM_CAP_SYS_HYPERV_CPUID: 4615 #endif 4616 case KVM_CAP_PCI_SEGMENT: 4617 case KVM_CAP_DEBUGREGS: 4618 case KVM_CAP_X86_ROBUST_SINGLESTEP: 4619 case KVM_CAP_XSAVE: 4620 case KVM_CAP_ASYNC_PF: 4621 case KVM_CAP_ASYNC_PF_INT: 4622 case KVM_CAP_GET_TSC_KHZ: 4623 case KVM_CAP_KVMCLOCK_CTRL: 4624 case KVM_CAP_IOAPIC_POLARITY_IGNORED: 4625 case KVM_CAP_TSC_DEADLINE_TIMER: 4626 case KVM_CAP_DISABLE_QUIRKS: 4627 case KVM_CAP_SET_BOOT_CPU_ID: 4628 case KVM_CAP_SPLIT_IRQCHIP: 4629 case KVM_CAP_IMMEDIATE_EXIT: 4630 case KVM_CAP_PMU_EVENT_FILTER: 4631 case KVM_CAP_PMU_EVENT_MASKED_EVENTS: 4632 case KVM_CAP_GET_MSR_FEATURES: 4633 case KVM_CAP_MSR_PLATFORM_INFO: 4634 case KVM_CAP_EXCEPTION_PAYLOAD: 4635 case KVM_CAP_X86_TRIPLE_FAULT_EVENT: 4636 case KVM_CAP_SET_GUEST_DEBUG: 4637 case KVM_CAP_LAST_CPU: 4638 case KVM_CAP_X86_USER_SPACE_MSR: 4639 case KVM_CAP_X86_MSR_FILTER: 4640 case KVM_CAP_ENFORCE_PV_FEATURE_CPUID: 4641 #ifdef CONFIG_X86_SGX_KVM 4642 case KVM_CAP_SGX_ATTRIBUTE: 4643 #endif 4644 case KVM_CAP_VM_COPY_ENC_CONTEXT_FROM: 4645 case KVM_CAP_VM_MOVE_ENC_CONTEXT_FROM: 4646 case KVM_CAP_SREGS2: 4647 case KVM_CAP_EXIT_ON_EMULATION_FAILURE: 4648 case KVM_CAP_VCPU_ATTRIBUTES: 4649 case KVM_CAP_SYS_ATTRIBUTES: 4650 case KVM_CAP_VAPIC: 4651 case KVM_CAP_ENABLE_CAP: 4652 case KVM_CAP_VM_DISABLE_NX_HUGE_PAGES: 4653 case KVM_CAP_IRQFD_RESAMPLE: 4654 case KVM_CAP_MEMORY_FAULT_INFO: 4655 case KVM_CAP_X86_GUEST_MODE: 4656 r = 1; 4657 break; 4658 case KVM_CAP_PRE_FAULT_MEMORY: 4659 r = tdp_enabled; 4660 break; 4661 case KVM_CAP_X86_APIC_BUS_CYCLES_NS: 4662 r = APIC_BUS_CYCLE_NS_DEFAULT; 4663 break; 4664 case KVM_CAP_EXIT_HYPERCALL: 4665 r = KVM_EXIT_HYPERCALL_VALID_MASK; 4666 break; 4667 case KVM_CAP_SET_GUEST_DEBUG2: 4668 return KVM_GUESTDBG_VALID_MASK; 4669 #ifdef CONFIG_KVM_XEN 4670 case KVM_CAP_XEN_HVM: 4671 r = KVM_XEN_HVM_CONFIG_HYPERCALL_MSR | 4672 KVM_XEN_HVM_CONFIG_INTERCEPT_HCALL | 4673 KVM_XEN_HVM_CONFIG_SHARED_INFO | 4674 KVM_XEN_HVM_CONFIG_EVTCHN_2LEVEL | 4675 KVM_XEN_HVM_CONFIG_EVTCHN_SEND | 4676 KVM_XEN_HVM_CONFIG_PVCLOCK_TSC_UNSTABLE | 4677 KVM_XEN_HVM_CONFIG_SHARED_INFO_HVA; 4678 if (sched_info_on()) 4679 r |= KVM_XEN_HVM_CONFIG_RUNSTATE | 4680 KVM_XEN_HVM_CONFIG_RUNSTATE_UPDATE_FLAG; 4681 break; 4682 #endif 4683 case KVM_CAP_SYNC_REGS: 4684 r = KVM_SYNC_X86_VALID_FIELDS; 4685 break; 4686 case KVM_CAP_ADJUST_CLOCK: 4687 r = KVM_CLOCK_VALID_FLAGS; 4688 break; 4689 case KVM_CAP_X86_DISABLE_EXITS: 4690 r = kvm_get_allowed_disable_exits(); 4691 break; 4692 case KVM_CAP_X86_SMM: 4693 if (!IS_ENABLED(CONFIG_KVM_SMM)) 4694 break; 4695 4696 /* SMBASE is usually relocated above 1M on modern chipsets, 4697 * and SMM handlers might indeed rely on 4G segment limits, 4698 * so do not report SMM to be available if real mode is 4699 * emulated via vm86 mode. Still, do not go to great lengths 4700 * to avoid userspace's usage of the feature, because it is a 4701 * fringe case that is not enabled except via specific settings 4702 * of the module parameters. 4703 */ 4704 r = kvm_x86_call(has_emulated_msr)(kvm, MSR_IA32_SMBASE); 4705 break; 4706 case KVM_CAP_NR_VCPUS: 4707 r = min_t(unsigned int, num_online_cpus(), KVM_MAX_VCPUS); 4708 break; 4709 case KVM_CAP_MAX_VCPUS: 4710 r = KVM_MAX_VCPUS; 4711 break; 4712 case KVM_CAP_MAX_VCPU_ID: 4713 r = KVM_MAX_VCPU_IDS; 4714 break; 4715 case KVM_CAP_PV_MMU: /* obsolete */ 4716 r = 0; 4717 break; 4718 case KVM_CAP_MCE: 4719 r = KVM_MAX_MCE_BANKS; 4720 break; 4721 case KVM_CAP_XCRS: 4722 r = boot_cpu_has(X86_FEATURE_XSAVE); 4723 break; 4724 case KVM_CAP_TSC_CONTROL: 4725 case KVM_CAP_VM_TSC_CONTROL: 4726 r = kvm_caps.has_tsc_control; 4727 break; 4728 case KVM_CAP_X2APIC_API: 4729 r = KVM_X2APIC_API_VALID_FLAGS; 4730 break; 4731 case KVM_CAP_NESTED_STATE: 4732 r = kvm_x86_ops.nested_ops->get_state ? 4733 kvm_x86_ops.nested_ops->get_state(NULL, NULL, 0) : 0; 4734 break; 4735 #ifdef CONFIG_KVM_HYPERV 4736 case KVM_CAP_HYPERV_DIRECT_TLBFLUSH: 4737 r = kvm_x86_ops.enable_l2_tlb_flush != NULL; 4738 break; 4739 case KVM_CAP_HYPERV_ENLIGHTENED_VMCS: 4740 r = kvm_x86_ops.nested_ops->enable_evmcs != NULL; 4741 break; 4742 #endif 4743 case KVM_CAP_SMALLER_MAXPHYADDR: 4744 r = (int) allow_smaller_maxphyaddr; 4745 break; 4746 case KVM_CAP_STEAL_TIME: 4747 r = sched_info_on(); 4748 break; 4749 case KVM_CAP_X86_BUS_LOCK_EXIT: 4750 if (kvm_caps.has_bus_lock_exit) 4751 r = KVM_BUS_LOCK_DETECTION_OFF | 4752 KVM_BUS_LOCK_DETECTION_EXIT; 4753 else 4754 r = 0; 4755 break; 4756 case KVM_CAP_XSAVE2: { 4757 r = xstate_required_size(kvm_get_filtered_xcr0(), false); 4758 if (r < sizeof(struct kvm_xsave)) 4759 r = sizeof(struct kvm_xsave); 4760 break; 4761 } 4762 case KVM_CAP_PMU_CAPABILITY: 4763 r = enable_pmu ? KVM_CAP_PMU_VALID_MASK : 0; 4764 break; 4765 case KVM_CAP_DISABLE_QUIRKS2: 4766 r = KVM_X86_VALID_QUIRKS; 4767 break; 4768 case KVM_CAP_X86_NOTIFY_VMEXIT: 4769 r = kvm_caps.has_notify_vmexit; 4770 break; 4771 case KVM_CAP_VM_TYPES: 4772 r = kvm_caps.supported_vm_types; 4773 break; 4774 case KVM_CAP_READONLY_MEM: 4775 r = kvm ? kvm_arch_has_readonly_mem(kvm) : 1; 4776 break; 4777 default: 4778 break; 4779 } 4780 return r; 4781 } 4782 4783 static int __kvm_x86_dev_get_attr(struct kvm_device_attr *attr, u64 *val) 4784 { 4785 if (attr->group) { 4786 if (kvm_x86_ops.dev_get_attr) 4787 return kvm_x86_call(dev_get_attr)(attr->group, attr->attr, val); 4788 return -ENXIO; 4789 } 4790 4791 switch (attr->attr) { 4792 case KVM_X86_XCOMP_GUEST_SUPP: 4793 *val = kvm_caps.supported_xcr0; 4794 return 0; 4795 default: 4796 return -ENXIO; 4797 } 4798 } 4799 4800 static int kvm_x86_dev_get_attr(struct kvm_device_attr *attr) 4801 { 4802 u64 __user *uaddr = u64_to_user_ptr(attr->addr); 4803 int r; 4804 u64 val; 4805 4806 r = __kvm_x86_dev_get_attr(attr, &val); 4807 if (r < 0) 4808 return r; 4809 4810 if (put_user(val, uaddr)) 4811 return -EFAULT; 4812 4813 return 0; 4814 } 4815 4816 static int kvm_x86_dev_has_attr(struct kvm_device_attr *attr) 4817 { 4818 u64 val; 4819 4820 return __kvm_x86_dev_get_attr(attr, &val); 4821 } 4822 4823 long kvm_arch_dev_ioctl(struct file *filp, 4824 unsigned int ioctl, unsigned long arg) 4825 { 4826 void __user *argp = (void __user *)arg; 4827 long r; 4828 4829 switch (ioctl) { 4830 case KVM_GET_MSR_INDEX_LIST: { 4831 struct kvm_msr_list __user *user_msr_list = argp; 4832 struct kvm_msr_list msr_list; 4833 unsigned n; 4834 4835 r = -EFAULT; 4836 if (copy_from_user(&msr_list, user_msr_list, sizeof(msr_list))) 4837 goto out; 4838 n = msr_list.nmsrs; 4839 msr_list.nmsrs = num_msrs_to_save + num_emulated_msrs; 4840 if (copy_to_user(user_msr_list, &msr_list, sizeof(msr_list))) 4841 goto out; 4842 r = -E2BIG; 4843 if (n < msr_list.nmsrs) 4844 goto out; 4845 r = -EFAULT; 4846 if (copy_to_user(user_msr_list->indices, &msrs_to_save, 4847 num_msrs_to_save * sizeof(u32))) 4848 goto out; 4849 if (copy_to_user(user_msr_list->indices + num_msrs_to_save, 4850 &emulated_msrs, 4851 num_emulated_msrs * sizeof(u32))) 4852 goto out; 4853 r = 0; 4854 break; 4855 } 4856 case KVM_GET_SUPPORTED_CPUID: 4857 case KVM_GET_EMULATED_CPUID: { 4858 struct kvm_cpuid2 __user *cpuid_arg = argp; 4859 struct kvm_cpuid2 cpuid; 4860 4861 r = -EFAULT; 4862 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid))) 4863 goto out; 4864 4865 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries, 4866 ioctl); 4867 if (r) 4868 goto out; 4869 4870 r = -EFAULT; 4871 if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid))) 4872 goto out; 4873 r = 0; 4874 break; 4875 } 4876 case KVM_X86_GET_MCE_CAP_SUPPORTED: 4877 r = -EFAULT; 4878 if (copy_to_user(argp, &kvm_caps.supported_mce_cap, 4879 sizeof(kvm_caps.supported_mce_cap))) 4880 goto out; 4881 r = 0; 4882 break; 4883 case KVM_GET_MSR_FEATURE_INDEX_LIST: { 4884 struct kvm_msr_list __user *user_msr_list = argp; 4885 struct kvm_msr_list msr_list; 4886 unsigned int n; 4887 4888 r = -EFAULT; 4889 if (copy_from_user(&msr_list, user_msr_list, sizeof(msr_list))) 4890 goto out; 4891 n = msr_list.nmsrs; 4892 msr_list.nmsrs = num_msr_based_features; 4893 if (copy_to_user(user_msr_list, &msr_list, sizeof(msr_list))) 4894 goto out; 4895 r = -E2BIG; 4896 if (n < msr_list.nmsrs) 4897 goto out; 4898 r = -EFAULT; 4899 if (copy_to_user(user_msr_list->indices, &msr_based_features, 4900 num_msr_based_features * sizeof(u32))) 4901 goto out; 4902 r = 0; 4903 break; 4904 } 4905 case KVM_GET_MSRS: 4906 r = msr_io(NULL, argp, do_get_feature_msr, 1); 4907 break; 4908 #ifdef CONFIG_KVM_HYPERV 4909 case KVM_GET_SUPPORTED_HV_CPUID: 4910 r = kvm_ioctl_get_supported_hv_cpuid(NULL, argp); 4911 break; 4912 #endif 4913 case KVM_GET_DEVICE_ATTR: { 4914 struct kvm_device_attr attr; 4915 r = -EFAULT; 4916 if (copy_from_user(&attr, (void __user *)arg, sizeof(attr))) 4917 break; 4918 r = kvm_x86_dev_get_attr(&attr); 4919 break; 4920 } 4921 case KVM_HAS_DEVICE_ATTR: { 4922 struct kvm_device_attr attr; 4923 r = -EFAULT; 4924 if (copy_from_user(&attr, (void __user *)arg, sizeof(attr))) 4925 break; 4926 r = kvm_x86_dev_has_attr(&attr); 4927 break; 4928 } 4929 default: 4930 r = -EINVAL; 4931 break; 4932 } 4933 out: 4934 return r; 4935 } 4936 4937 static void wbinvd_ipi(void *garbage) 4938 { 4939 wbinvd(); 4940 } 4941 4942 static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu) 4943 { 4944 return kvm_arch_has_noncoherent_dma(vcpu->kvm); 4945 } 4946 4947 void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu) 4948 { 4949 struct kvm_pmu *pmu = vcpu_to_pmu(vcpu); 4950 4951 vcpu->arch.l1tf_flush_l1d = true; 4952 4953 if (vcpu->scheduled_out && pmu->version && pmu->event_count) { 4954 pmu->need_cleanup = true; 4955 kvm_make_request(KVM_REQ_PMU, vcpu); 4956 } 4957 4958 /* Address WBINVD may be executed by guest */ 4959 if (need_emulate_wbinvd(vcpu)) { 4960 if (kvm_x86_call(has_wbinvd_exit)()) 4961 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask); 4962 else if (vcpu->cpu != -1 && vcpu->cpu != cpu) 4963 smp_call_function_single(vcpu->cpu, 4964 wbinvd_ipi, NULL, 1); 4965 } 4966 4967 kvm_x86_call(vcpu_load)(vcpu, cpu); 4968 4969 /* Save host pkru register if supported */ 4970 vcpu->arch.host_pkru = read_pkru(); 4971 4972 /* Apply any externally detected TSC adjustments (due to suspend) */ 4973 if (unlikely(vcpu->arch.tsc_offset_adjustment)) { 4974 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment); 4975 vcpu->arch.tsc_offset_adjustment = 0; 4976 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 4977 } 4978 4979 if (unlikely(vcpu->cpu != cpu) || kvm_check_tsc_unstable()) { 4980 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 : 4981 rdtsc() - vcpu->arch.last_host_tsc; 4982 if (tsc_delta < 0) 4983 mark_tsc_unstable("KVM discovered backwards TSC"); 4984 4985 if (kvm_check_tsc_unstable()) { 4986 u64 offset = kvm_compute_l1_tsc_offset(vcpu, 4987 vcpu->arch.last_guest_tsc); 4988 kvm_vcpu_write_tsc_offset(vcpu, offset); 4989 vcpu->arch.tsc_catchup = 1; 4990 } 4991 4992 if (kvm_lapic_hv_timer_in_use(vcpu)) 4993 kvm_lapic_restart_hv_timer(vcpu); 4994 4995 /* 4996 * On a host with synchronized TSC, there is no need to update 4997 * kvmclock on vcpu->cpu migration 4998 */ 4999 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1) 5000 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu); 5001 if (vcpu->cpu != cpu) 5002 kvm_make_request(KVM_REQ_MIGRATE_TIMER, vcpu); 5003 vcpu->cpu = cpu; 5004 } 5005 5006 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu); 5007 } 5008 5009 static void kvm_steal_time_set_preempted(struct kvm_vcpu *vcpu) 5010 { 5011 struct gfn_to_hva_cache *ghc = &vcpu->arch.st.cache; 5012 struct kvm_steal_time __user *st; 5013 struct kvm_memslots *slots; 5014 static const u8 preempted = KVM_VCPU_PREEMPTED; 5015 gpa_t gpa = vcpu->arch.st.msr_val & KVM_STEAL_VALID_BITS; 5016 5017 /* 5018 * The vCPU can be marked preempted if and only if the VM-Exit was on 5019 * an instruction boundary and will not trigger guest emulation of any 5020 * kind (see vcpu_run). Vendor specific code controls (conservatively) 5021 * when this is true, for example allowing the vCPU to be marked 5022 * preempted if and only if the VM-Exit was due to a host interrupt. 5023 */ 5024 if (!vcpu->arch.at_instruction_boundary) { 5025 vcpu->stat.preemption_other++; 5026 return; 5027 } 5028 5029 vcpu->stat.preemption_reported++; 5030 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED)) 5031 return; 5032 5033 if (vcpu->arch.st.preempted) 5034 return; 5035 5036 /* This happens on process exit */ 5037 if (unlikely(current->mm != vcpu->kvm->mm)) 5038 return; 5039 5040 slots = kvm_memslots(vcpu->kvm); 5041 5042 if (unlikely(slots->generation != ghc->generation || 5043 gpa != ghc->gpa || 5044 kvm_is_error_hva(ghc->hva) || !ghc->memslot)) 5045 return; 5046 5047 st = (struct kvm_steal_time __user *)ghc->hva; 5048 BUILD_BUG_ON(sizeof(st->preempted) != sizeof(preempted)); 5049 5050 if (!copy_to_user_nofault(&st->preempted, &preempted, sizeof(preempted))) 5051 vcpu->arch.st.preempted = KVM_VCPU_PREEMPTED; 5052 5053 mark_page_dirty_in_slot(vcpu->kvm, ghc->memslot, gpa_to_gfn(ghc->gpa)); 5054 } 5055 5056 void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu) 5057 { 5058 int idx; 5059 5060 if (vcpu->preempted) { 5061 /* 5062 * Assume protected guests are in-kernel. Inefficient yielding 5063 * due to false positives is preferable to never yielding due 5064 * to false negatives. 5065 */ 5066 vcpu->arch.preempted_in_kernel = vcpu->arch.guest_state_protected || 5067 !kvm_x86_call(get_cpl_no_cache)(vcpu); 5068 5069 /* 5070 * Take the srcu lock as memslots will be accessed to check the gfn 5071 * cache generation against the memslots generation. 5072 */ 5073 idx = srcu_read_lock(&vcpu->kvm->srcu); 5074 if (kvm_xen_msr_enabled(vcpu->kvm)) 5075 kvm_xen_runstate_set_preempted(vcpu); 5076 else 5077 kvm_steal_time_set_preempted(vcpu); 5078 srcu_read_unlock(&vcpu->kvm->srcu, idx); 5079 } 5080 5081 kvm_x86_call(vcpu_put)(vcpu); 5082 vcpu->arch.last_host_tsc = rdtsc(); 5083 } 5084 5085 static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu, 5086 struct kvm_lapic_state *s) 5087 { 5088 kvm_x86_call(sync_pir_to_irr)(vcpu); 5089 5090 return kvm_apic_get_state(vcpu, s); 5091 } 5092 5093 static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu, 5094 struct kvm_lapic_state *s) 5095 { 5096 int r; 5097 5098 r = kvm_apic_set_state(vcpu, s); 5099 if (r) 5100 return r; 5101 update_cr8_intercept(vcpu); 5102 5103 return 0; 5104 } 5105 5106 static int kvm_cpu_accept_dm_intr(struct kvm_vcpu *vcpu) 5107 { 5108 /* 5109 * We can accept userspace's request for interrupt injection 5110 * as long as we have a place to store the interrupt number. 5111 * The actual injection will happen when the CPU is able to 5112 * deliver the interrupt. 5113 */ 5114 if (kvm_cpu_has_extint(vcpu)) 5115 return false; 5116 5117 /* Acknowledging ExtINT does not happen if LINT0 is masked. */ 5118 return (!lapic_in_kernel(vcpu) || 5119 kvm_apic_accept_pic_intr(vcpu)); 5120 } 5121 5122 static int kvm_vcpu_ready_for_interrupt_injection(struct kvm_vcpu *vcpu) 5123 { 5124 /* 5125 * Do not cause an interrupt window exit if an exception 5126 * is pending or an event needs reinjection; userspace 5127 * might want to inject the interrupt manually using KVM_SET_REGS 5128 * or KVM_SET_SREGS. For that to work, we must be at an 5129 * instruction boundary and with no events half-injected. 5130 */ 5131 return (kvm_arch_interrupt_allowed(vcpu) && 5132 kvm_cpu_accept_dm_intr(vcpu) && 5133 !kvm_event_needs_reinjection(vcpu) && 5134 !kvm_is_exception_pending(vcpu)); 5135 } 5136 5137 static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu, 5138 struct kvm_interrupt *irq) 5139 { 5140 if (irq->irq >= KVM_NR_INTERRUPTS) 5141 return -EINVAL; 5142 5143 if (!irqchip_in_kernel(vcpu->kvm)) { 5144 kvm_queue_interrupt(vcpu, irq->irq, false); 5145 kvm_make_request(KVM_REQ_EVENT, vcpu); 5146 return 0; 5147 } 5148 5149 /* 5150 * With in-kernel LAPIC, we only use this to inject EXTINT, so 5151 * fail for in-kernel 8259. 5152 */ 5153 if (pic_in_kernel(vcpu->kvm)) 5154 return -ENXIO; 5155 5156 if (vcpu->arch.pending_external_vector != -1) 5157 return -EEXIST; 5158 5159 vcpu->arch.pending_external_vector = irq->irq; 5160 kvm_make_request(KVM_REQ_EVENT, vcpu); 5161 return 0; 5162 } 5163 5164 static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu) 5165 { 5166 kvm_inject_nmi(vcpu); 5167 5168 return 0; 5169 } 5170 5171 static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu, 5172 struct kvm_tpr_access_ctl *tac) 5173 { 5174 if (tac->flags) 5175 return -EINVAL; 5176 vcpu->arch.tpr_access_reporting = !!tac->enabled; 5177 return 0; 5178 } 5179 5180 static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu, 5181 u64 mcg_cap) 5182 { 5183 int r; 5184 unsigned bank_num = mcg_cap & 0xff, bank; 5185 5186 r = -EINVAL; 5187 if (!bank_num || bank_num > KVM_MAX_MCE_BANKS) 5188 goto out; 5189 if (mcg_cap & ~(kvm_caps.supported_mce_cap | 0xff | 0xff0000)) 5190 goto out; 5191 r = 0; 5192 vcpu->arch.mcg_cap = mcg_cap; 5193 /* Init IA32_MCG_CTL to all 1s */ 5194 if (mcg_cap & MCG_CTL_P) 5195 vcpu->arch.mcg_ctl = ~(u64)0; 5196 /* Init IA32_MCi_CTL to all 1s, IA32_MCi_CTL2 to all 0s */ 5197 for (bank = 0; bank < bank_num; bank++) { 5198 vcpu->arch.mce_banks[bank*4] = ~(u64)0; 5199 if (mcg_cap & MCG_CMCI_P) 5200 vcpu->arch.mci_ctl2_banks[bank] = 0; 5201 } 5202 5203 kvm_apic_after_set_mcg_cap(vcpu); 5204 5205 kvm_x86_call(setup_mce)(vcpu); 5206 out: 5207 return r; 5208 } 5209 5210 /* 5211 * Validate this is an UCNA (uncorrectable no action) error by checking the 5212 * MCG_STATUS and MCi_STATUS registers: 5213 * - none of the bits for Machine Check Exceptions are set 5214 * - both the VAL (valid) and UC (uncorrectable) bits are set 5215 * MCI_STATUS_PCC - Processor Context Corrupted 5216 * MCI_STATUS_S - Signaled as a Machine Check Exception 5217 * MCI_STATUS_AR - Software recoverable Action Required 5218 */ 5219 static bool is_ucna(struct kvm_x86_mce *mce) 5220 { 5221 return !mce->mcg_status && 5222 !(mce->status & (MCI_STATUS_PCC | MCI_STATUS_S | MCI_STATUS_AR)) && 5223 (mce->status & MCI_STATUS_VAL) && 5224 (mce->status & MCI_STATUS_UC); 5225 } 5226 5227 static int kvm_vcpu_x86_set_ucna(struct kvm_vcpu *vcpu, struct kvm_x86_mce *mce, u64* banks) 5228 { 5229 u64 mcg_cap = vcpu->arch.mcg_cap; 5230 5231 banks[1] = mce->status; 5232 banks[2] = mce->addr; 5233 banks[3] = mce->misc; 5234 vcpu->arch.mcg_status = mce->mcg_status; 5235 5236 if (!(mcg_cap & MCG_CMCI_P) || 5237 !(vcpu->arch.mci_ctl2_banks[mce->bank] & MCI_CTL2_CMCI_EN)) 5238 return 0; 5239 5240 if (lapic_in_kernel(vcpu)) 5241 kvm_apic_local_deliver(vcpu->arch.apic, APIC_LVTCMCI); 5242 5243 return 0; 5244 } 5245 5246 static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu, 5247 struct kvm_x86_mce *mce) 5248 { 5249 u64 mcg_cap = vcpu->arch.mcg_cap; 5250 unsigned bank_num = mcg_cap & 0xff; 5251 u64 *banks = vcpu->arch.mce_banks; 5252 5253 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL)) 5254 return -EINVAL; 5255 5256 banks += array_index_nospec(4 * mce->bank, 4 * bank_num); 5257 5258 if (is_ucna(mce)) 5259 return kvm_vcpu_x86_set_ucna(vcpu, mce, banks); 5260 5261 /* 5262 * if IA32_MCG_CTL is not all 1s, the uncorrected error 5263 * reporting is disabled 5264 */ 5265 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) && 5266 vcpu->arch.mcg_ctl != ~(u64)0) 5267 return 0; 5268 /* 5269 * if IA32_MCi_CTL is not all 1s, the uncorrected error 5270 * reporting is disabled for the bank 5271 */ 5272 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0) 5273 return 0; 5274 if (mce->status & MCI_STATUS_UC) { 5275 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) || 5276 !kvm_is_cr4_bit_set(vcpu, X86_CR4_MCE)) { 5277 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); 5278 return 0; 5279 } 5280 if (banks[1] & MCI_STATUS_VAL) 5281 mce->status |= MCI_STATUS_OVER; 5282 banks[2] = mce->addr; 5283 banks[3] = mce->misc; 5284 vcpu->arch.mcg_status = mce->mcg_status; 5285 banks[1] = mce->status; 5286 kvm_queue_exception(vcpu, MC_VECTOR); 5287 } else if (!(banks[1] & MCI_STATUS_VAL) 5288 || !(banks[1] & MCI_STATUS_UC)) { 5289 if (banks[1] & MCI_STATUS_VAL) 5290 mce->status |= MCI_STATUS_OVER; 5291 banks[2] = mce->addr; 5292 banks[3] = mce->misc; 5293 banks[1] = mce->status; 5294 } else 5295 banks[1] |= MCI_STATUS_OVER; 5296 return 0; 5297 } 5298 5299 static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu, 5300 struct kvm_vcpu_events *events) 5301 { 5302 struct kvm_queued_exception *ex; 5303 5304 process_nmi(vcpu); 5305 5306 #ifdef CONFIG_KVM_SMM 5307 if (kvm_check_request(KVM_REQ_SMI, vcpu)) 5308 process_smi(vcpu); 5309 #endif 5310 5311 /* 5312 * KVM's ABI only allows for one exception to be migrated. Luckily, 5313 * the only time there can be two queued exceptions is if there's a 5314 * non-exiting _injected_ exception, and a pending exiting exception. 5315 * In that case, ignore the VM-Exiting exception as it's an extension 5316 * of the injected exception. 5317 */ 5318 if (vcpu->arch.exception_vmexit.pending && 5319 !vcpu->arch.exception.pending && 5320 !vcpu->arch.exception.injected) 5321 ex = &vcpu->arch.exception_vmexit; 5322 else 5323 ex = &vcpu->arch.exception; 5324 5325 /* 5326 * In guest mode, payload delivery should be deferred if the exception 5327 * will be intercepted by L1, e.g. KVM should not modifying CR2 if L1 5328 * intercepts #PF, ditto for DR6 and #DBs. If the per-VM capability, 5329 * KVM_CAP_EXCEPTION_PAYLOAD, is not set, userspace may or may not 5330 * propagate the payload and so it cannot be safely deferred. Deliver 5331 * the payload if the capability hasn't been requested. 5332 */ 5333 if (!vcpu->kvm->arch.exception_payload_enabled && 5334 ex->pending && ex->has_payload) 5335 kvm_deliver_exception_payload(vcpu, ex); 5336 5337 memset(events, 0, sizeof(*events)); 5338 5339 /* 5340 * The API doesn't provide the instruction length for software 5341 * exceptions, so don't report them. As long as the guest RIP 5342 * isn't advanced, we should expect to encounter the exception 5343 * again. 5344 */ 5345 if (!kvm_exception_is_soft(ex->vector)) { 5346 events->exception.injected = ex->injected; 5347 events->exception.pending = ex->pending; 5348 /* 5349 * For ABI compatibility, deliberately conflate 5350 * pending and injected exceptions when 5351 * KVM_CAP_EXCEPTION_PAYLOAD isn't enabled. 5352 */ 5353 if (!vcpu->kvm->arch.exception_payload_enabled) 5354 events->exception.injected |= ex->pending; 5355 } 5356 events->exception.nr = ex->vector; 5357 events->exception.has_error_code = ex->has_error_code; 5358 events->exception.error_code = ex->error_code; 5359 events->exception_has_payload = ex->has_payload; 5360 events->exception_payload = ex->payload; 5361 5362 events->interrupt.injected = 5363 vcpu->arch.interrupt.injected && !vcpu->arch.interrupt.soft; 5364 events->interrupt.nr = vcpu->arch.interrupt.nr; 5365 events->interrupt.shadow = kvm_x86_call(get_interrupt_shadow)(vcpu); 5366 5367 events->nmi.injected = vcpu->arch.nmi_injected; 5368 events->nmi.pending = kvm_get_nr_pending_nmis(vcpu); 5369 events->nmi.masked = kvm_x86_call(get_nmi_mask)(vcpu); 5370 5371 /* events->sipi_vector is never valid when reporting to user space */ 5372 5373 #ifdef CONFIG_KVM_SMM 5374 events->smi.smm = is_smm(vcpu); 5375 events->smi.pending = vcpu->arch.smi_pending; 5376 events->smi.smm_inside_nmi = 5377 !!(vcpu->arch.hflags & HF_SMM_INSIDE_NMI_MASK); 5378 #endif 5379 events->smi.latched_init = kvm_lapic_latched_init(vcpu); 5380 5381 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING 5382 | KVM_VCPUEVENT_VALID_SHADOW 5383 | KVM_VCPUEVENT_VALID_SMM); 5384 if (vcpu->kvm->arch.exception_payload_enabled) 5385 events->flags |= KVM_VCPUEVENT_VALID_PAYLOAD; 5386 if (vcpu->kvm->arch.triple_fault_event) { 5387 events->triple_fault.pending = kvm_test_request(KVM_REQ_TRIPLE_FAULT, vcpu); 5388 events->flags |= KVM_VCPUEVENT_VALID_TRIPLE_FAULT; 5389 } 5390 } 5391 5392 static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu, 5393 struct kvm_vcpu_events *events) 5394 { 5395 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING 5396 | KVM_VCPUEVENT_VALID_SIPI_VECTOR 5397 | KVM_VCPUEVENT_VALID_SHADOW 5398 | KVM_VCPUEVENT_VALID_SMM 5399 | KVM_VCPUEVENT_VALID_PAYLOAD 5400 | KVM_VCPUEVENT_VALID_TRIPLE_FAULT)) 5401 return -EINVAL; 5402 5403 if (events->flags & KVM_VCPUEVENT_VALID_PAYLOAD) { 5404 if (!vcpu->kvm->arch.exception_payload_enabled) 5405 return -EINVAL; 5406 if (events->exception.pending) 5407 events->exception.injected = 0; 5408 else 5409 events->exception_has_payload = 0; 5410 } else { 5411 events->exception.pending = 0; 5412 events->exception_has_payload = 0; 5413 } 5414 5415 if ((events->exception.injected || events->exception.pending) && 5416 (events->exception.nr > 31 || events->exception.nr == NMI_VECTOR)) 5417 return -EINVAL; 5418 5419 /* INITs are latched while in SMM */ 5420 if (events->flags & KVM_VCPUEVENT_VALID_SMM && 5421 (events->smi.smm || events->smi.pending) && 5422 vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) 5423 return -EINVAL; 5424 5425 process_nmi(vcpu); 5426 5427 /* 5428 * Flag that userspace is stuffing an exception, the next KVM_RUN will 5429 * morph the exception to a VM-Exit if appropriate. Do this only for 5430 * pending exceptions, already-injected exceptions are not subject to 5431 * intercpetion. Note, userspace that conflates pending and injected 5432 * is hosed, and will incorrectly convert an injected exception into a 5433 * pending exception, which in turn may cause a spurious VM-Exit. 5434 */ 5435 vcpu->arch.exception_from_userspace = events->exception.pending; 5436 5437 vcpu->arch.exception_vmexit.pending = false; 5438 5439 vcpu->arch.exception.injected = events->exception.injected; 5440 vcpu->arch.exception.pending = events->exception.pending; 5441 vcpu->arch.exception.vector = events->exception.nr; 5442 vcpu->arch.exception.has_error_code = events->exception.has_error_code; 5443 vcpu->arch.exception.error_code = events->exception.error_code; 5444 vcpu->arch.exception.has_payload = events->exception_has_payload; 5445 vcpu->arch.exception.payload = events->exception_payload; 5446 5447 vcpu->arch.interrupt.injected = events->interrupt.injected; 5448 vcpu->arch.interrupt.nr = events->interrupt.nr; 5449 vcpu->arch.interrupt.soft = events->interrupt.soft; 5450 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW) 5451 kvm_x86_call(set_interrupt_shadow)(vcpu, 5452 events->interrupt.shadow); 5453 5454 vcpu->arch.nmi_injected = events->nmi.injected; 5455 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING) { 5456 vcpu->arch.nmi_pending = 0; 5457 atomic_set(&vcpu->arch.nmi_queued, events->nmi.pending); 5458 if (events->nmi.pending) 5459 kvm_make_request(KVM_REQ_NMI, vcpu); 5460 } 5461 kvm_x86_call(set_nmi_mask)(vcpu, events->nmi.masked); 5462 5463 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR && 5464 lapic_in_kernel(vcpu)) 5465 vcpu->arch.apic->sipi_vector = events->sipi_vector; 5466 5467 if (events->flags & KVM_VCPUEVENT_VALID_SMM) { 5468 #ifdef CONFIG_KVM_SMM 5469 if (!!(vcpu->arch.hflags & HF_SMM_MASK) != events->smi.smm) { 5470 kvm_leave_nested(vcpu); 5471 kvm_smm_changed(vcpu, events->smi.smm); 5472 } 5473 5474 vcpu->arch.smi_pending = events->smi.pending; 5475 5476 if (events->smi.smm) { 5477 if (events->smi.smm_inside_nmi) 5478 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK; 5479 else 5480 vcpu->arch.hflags &= ~HF_SMM_INSIDE_NMI_MASK; 5481 } 5482 5483 #else 5484 if (events->smi.smm || events->smi.pending || 5485 events->smi.smm_inside_nmi) 5486 return -EINVAL; 5487 #endif 5488 5489 if (lapic_in_kernel(vcpu)) { 5490 if (events->smi.latched_init) 5491 set_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events); 5492 else 5493 clear_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events); 5494 } 5495 } 5496 5497 if (events->flags & KVM_VCPUEVENT_VALID_TRIPLE_FAULT) { 5498 if (!vcpu->kvm->arch.triple_fault_event) 5499 return -EINVAL; 5500 if (events->triple_fault.pending) 5501 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); 5502 else 5503 kvm_clear_request(KVM_REQ_TRIPLE_FAULT, vcpu); 5504 } 5505 5506 kvm_make_request(KVM_REQ_EVENT, vcpu); 5507 5508 return 0; 5509 } 5510 5511 static int kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu, 5512 struct kvm_debugregs *dbgregs) 5513 { 5514 unsigned int i; 5515 5516 if (vcpu->kvm->arch.has_protected_state && 5517 vcpu->arch.guest_state_protected) 5518 return -EINVAL; 5519 5520 memset(dbgregs, 0, sizeof(*dbgregs)); 5521 5522 BUILD_BUG_ON(ARRAY_SIZE(vcpu->arch.db) != ARRAY_SIZE(dbgregs->db)); 5523 for (i = 0; i < ARRAY_SIZE(vcpu->arch.db); i++) 5524 dbgregs->db[i] = vcpu->arch.db[i]; 5525 5526 dbgregs->dr6 = vcpu->arch.dr6; 5527 dbgregs->dr7 = vcpu->arch.dr7; 5528 return 0; 5529 } 5530 5531 static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu, 5532 struct kvm_debugregs *dbgregs) 5533 { 5534 unsigned int i; 5535 5536 if (vcpu->kvm->arch.has_protected_state && 5537 vcpu->arch.guest_state_protected) 5538 return -EINVAL; 5539 5540 if (dbgregs->flags) 5541 return -EINVAL; 5542 5543 if (!kvm_dr6_valid(dbgregs->dr6)) 5544 return -EINVAL; 5545 if (!kvm_dr7_valid(dbgregs->dr7)) 5546 return -EINVAL; 5547 5548 for (i = 0; i < ARRAY_SIZE(vcpu->arch.db); i++) 5549 vcpu->arch.db[i] = dbgregs->db[i]; 5550 5551 kvm_update_dr0123(vcpu); 5552 vcpu->arch.dr6 = dbgregs->dr6; 5553 vcpu->arch.dr7 = dbgregs->dr7; 5554 kvm_update_dr7(vcpu); 5555 5556 return 0; 5557 } 5558 5559 5560 static int kvm_vcpu_ioctl_x86_get_xsave2(struct kvm_vcpu *vcpu, 5561 u8 *state, unsigned int size) 5562 { 5563 /* 5564 * Only copy state for features that are enabled for the guest. The 5565 * state itself isn't problematic, but setting bits in the header for 5566 * features that are supported in *this* host but not exposed to the 5567 * guest can result in KVM_SET_XSAVE failing when live migrating to a 5568 * compatible host without the features that are NOT exposed to the 5569 * guest. 5570 * 5571 * FP+SSE can always be saved/restored via KVM_{G,S}ET_XSAVE, even if 5572 * XSAVE/XCRO are not exposed to the guest, and even if XSAVE isn't 5573 * supported by the host. 5574 */ 5575 u64 supported_xcr0 = vcpu->arch.guest_supported_xcr0 | 5576 XFEATURE_MASK_FPSSE; 5577 5578 if (fpstate_is_confidential(&vcpu->arch.guest_fpu)) 5579 return vcpu->kvm->arch.has_protected_state ? -EINVAL : 0; 5580 5581 fpu_copy_guest_fpstate_to_uabi(&vcpu->arch.guest_fpu, state, size, 5582 supported_xcr0, vcpu->arch.pkru); 5583 return 0; 5584 } 5585 5586 static int kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu, 5587 struct kvm_xsave *guest_xsave) 5588 { 5589 return kvm_vcpu_ioctl_x86_get_xsave2(vcpu, (void *)guest_xsave->region, 5590 sizeof(guest_xsave->region)); 5591 } 5592 5593 static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu, 5594 struct kvm_xsave *guest_xsave) 5595 { 5596 if (fpstate_is_confidential(&vcpu->arch.guest_fpu)) 5597 return vcpu->kvm->arch.has_protected_state ? -EINVAL : 0; 5598 5599 return fpu_copy_uabi_to_guest_fpstate(&vcpu->arch.guest_fpu, 5600 guest_xsave->region, 5601 kvm_caps.supported_xcr0, 5602 &vcpu->arch.pkru); 5603 } 5604 5605 static int kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu, 5606 struct kvm_xcrs *guest_xcrs) 5607 { 5608 if (vcpu->kvm->arch.has_protected_state && 5609 vcpu->arch.guest_state_protected) 5610 return -EINVAL; 5611 5612 if (!boot_cpu_has(X86_FEATURE_XSAVE)) { 5613 guest_xcrs->nr_xcrs = 0; 5614 return 0; 5615 } 5616 5617 guest_xcrs->nr_xcrs = 1; 5618 guest_xcrs->flags = 0; 5619 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK; 5620 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0; 5621 return 0; 5622 } 5623 5624 static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu, 5625 struct kvm_xcrs *guest_xcrs) 5626 { 5627 int i, r = 0; 5628 5629 if (vcpu->kvm->arch.has_protected_state && 5630 vcpu->arch.guest_state_protected) 5631 return -EINVAL; 5632 5633 if (!boot_cpu_has(X86_FEATURE_XSAVE)) 5634 return -EINVAL; 5635 5636 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags) 5637 return -EINVAL; 5638 5639 for (i = 0; i < guest_xcrs->nr_xcrs; i++) 5640 /* Only support XCR0 currently */ 5641 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) { 5642 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK, 5643 guest_xcrs->xcrs[i].value); 5644 break; 5645 } 5646 if (r) 5647 r = -EINVAL; 5648 return r; 5649 } 5650 5651 /* 5652 * kvm_set_guest_paused() indicates to the guest kernel that it has been 5653 * stopped by the hypervisor. This function will be called from the host only. 5654 * EINVAL is returned when the host attempts to set the flag for a guest that 5655 * does not support pv clocks. 5656 */ 5657 static int kvm_set_guest_paused(struct kvm_vcpu *vcpu) 5658 { 5659 if (!vcpu->arch.pv_time.active) 5660 return -EINVAL; 5661 vcpu->arch.pvclock_set_guest_stopped_request = true; 5662 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 5663 return 0; 5664 } 5665 5666 static int kvm_arch_tsc_has_attr(struct kvm_vcpu *vcpu, 5667 struct kvm_device_attr *attr) 5668 { 5669 int r; 5670 5671 switch (attr->attr) { 5672 case KVM_VCPU_TSC_OFFSET: 5673 r = 0; 5674 break; 5675 default: 5676 r = -ENXIO; 5677 } 5678 5679 return r; 5680 } 5681 5682 static int kvm_arch_tsc_get_attr(struct kvm_vcpu *vcpu, 5683 struct kvm_device_attr *attr) 5684 { 5685 u64 __user *uaddr = u64_to_user_ptr(attr->addr); 5686 int r; 5687 5688 switch (attr->attr) { 5689 case KVM_VCPU_TSC_OFFSET: 5690 r = -EFAULT; 5691 if (put_user(vcpu->arch.l1_tsc_offset, uaddr)) 5692 break; 5693 r = 0; 5694 break; 5695 default: 5696 r = -ENXIO; 5697 } 5698 5699 return r; 5700 } 5701 5702 static int kvm_arch_tsc_set_attr(struct kvm_vcpu *vcpu, 5703 struct kvm_device_attr *attr) 5704 { 5705 u64 __user *uaddr = u64_to_user_ptr(attr->addr); 5706 struct kvm *kvm = vcpu->kvm; 5707 int r; 5708 5709 switch (attr->attr) { 5710 case KVM_VCPU_TSC_OFFSET: { 5711 u64 offset, tsc, ns; 5712 unsigned long flags; 5713 bool matched; 5714 5715 r = -EFAULT; 5716 if (get_user(offset, uaddr)) 5717 break; 5718 5719 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags); 5720 5721 matched = (vcpu->arch.virtual_tsc_khz && 5722 kvm->arch.last_tsc_khz == vcpu->arch.virtual_tsc_khz && 5723 kvm->arch.last_tsc_offset == offset); 5724 5725 tsc = kvm_scale_tsc(rdtsc(), vcpu->arch.l1_tsc_scaling_ratio) + offset; 5726 ns = get_kvmclock_base_ns(); 5727 5728 kvm->arch.user_set_tsc = true; 5729 __kvm_synchronize_tsc(vcpu, offset, tsc, ns, matched); 5730 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags); 5731 5732 r = 0; 5733 break; 5734 } 5735 default: 5736 r = -ENXIO; 5737 } 5738 5739 return r; 5740 } 5741 5742 static int kvm_vcpu_ioctl_device_attr(struct kvm_vcpu *vcpu, 5743 unsigned int ioctl, 5744 void __user *argp) 5745 { 5746 struct kvm_device_attr attr; 5747 int r; 5748 5749 if (copy_from_user(&attr, argp, sizeof(attr))) 5750 return -EFAULT; 5751 5752 if (attr.group != KVM_VCPU_TSC_CTRL) 5753 return -ENXIO; 5754 5755 switch (ioctl) { 5756 case KVM_HAS_DEVICE_ATTR: 5757 r = kvm_arch_tsc_has_attr(vcpu, &attr); 5758 break; 5759 case KVM_GET_DEVICE_ATTR: 5760 r = kvm_arch_tsc_get_attr(vcpu, &attr); 5761 break; 5762 case KVM_SET_DEVICE_ATTR: 5763 r = kvm_arch_tsc_set_attr(vcpu, &attr); 5764 break; 5765 } 5766 5767 return r; 5768 } 5769 5770 static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu, 5771 struct kvm_enable_cap *cap) 5772 { 5773 if (cap->flags) 5774 return -EINVAL; 5775 5776 switch (cap->cap) { 5777 #ifdef CONFIG_KVM_HYPERV 5778 case KVM_CAP_HYPERV_SYNIC2: 5779 if (cap->args[0]) 5780 return -EINVAL; 5781 fallthrough; 5782 5783 case KVM_CAP_HYPERV_SYNIC: 5784 if (!irqchip_in_kernel(vcpu->kvm)) 5785 return -EINVAL; 5786 return kvm_hv_activate_synic(vcpu, cap->cap == 5787 KVM_CAP_HYPERV_SYNIC2); 5788 case KVM_CAP_HYPERV_ENLIGHTENED_VMCS: 5789 { 5790 int r; 5791 uint16_t vmcs_version; 5792 void __user *user_ptr; 5793 5794 if (!kvm_x86_ops.nested_ops->enable_evmcs) 5795 return -ENOTTY; 5796 r = kvm_x86_ops.nested_ops->enable_evmcs(vcpu, &vmcs_version); 5797 if (!r) { 5798 user_ptr = (void __user *)(uintptr_t)cap->args[0]; 5799 if (copy_to_user(user_ptr, &vmcs_version, 5800 sizeof(vmcs_version))) 5801 r = -EFAULT; 5802 } 5803 return r; 5804 } 5805 case KVM_CAP_HYPERV_DIRECT_TLBFLUSH: 5806 if (!kvm_x86_ops.enable_l2_tlb_flush) 5807 return -ENOTTY; 5808 5809 return kvm_x86_call(enable_l2_tlb_flush)(vcpu); 5810 5811 case KVM_CAP_HYPERV_ENFORCE_CPUID: 5812 return kvm_hv_set_enforce_cpuid(vcpu, cap->args[0]); 5813 #endif 5814 5815 case KVM_CAP_ENFORCE_PV_FEATURE_CPUID: 5816 vcpu->arch.pv_cpuid.enforce = cap->args[0]; 5817 return 0; 5818 default: 5819 return -EINVAL; 5820 } 5821 } 5822 5823 long kvm_arch_vcpu_ioctl(struct file *filp, 5824 unsigned int ioctl, unsigned long arg) 5825 { 5826 struct kvm_vcpu *vcpu = filp->private_data; 5827 void __user *argp = (void __user *)arg; 5828 int r; 5829 union { 5830 struct kvm_sregs2 *sregs2; 5831 struct kvm_lapic_state *lapic; 5832 struct kvm_xsave *xsave; 5833 struct kvm_xcrs *xcrs; 5834 void *buffer; 5835 } u; 5836 5837 vcpu_load(vcpu); 5838 5839 u.buffer = NULL; 5840 switch (ioctl) { 5841 case KVM_GET_LAPIC: { 5842 r = -EINVAL; 5843 if (!lapic_in_kernel(vcpu)) 5844 goto out; 5845 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL); 5846 5847 r = -ENOMEM; 5848 if (!u.lapic) 5849 goto out; 5850 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic); 5851 if (r) 5852 goto out; 5853 r = -EFAULT; 5854 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state))) 5855 goto out; 5856 r = 0; 5857 break; 5858 } 5859 case KVM_SET_LAPIC: { 5860 r = -EINVAL; 5861 if (!lapic_in_kernel(vcpu)) 5862 goto out; 5863 u.lapic = memdup_user(argp, sizeof(*u.lapic)); 5864 if (IS_ERR(u.lapic)) { 5865 r = PTR_ERR(u.lapic); 5866 goto out_nofree; 5867 } 5868 5869 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic); 5870 break; 5871 } 5872 case KVM_INTERRUPT: { 5873 struct kvm_interrupt irq; 5874 5875 r = -EFAULT; 5876 if (copy_from_user(&irq, argp, sizeof(irq))) 5877 goto out; 5878 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq); 5879 break; 5880 } 5881 case KVM_NMI: { 5882 r = kvm_vcpu_ioctl_nmi(vcpu); 5883 break; 5884 } 5885 case KVM_SMI: { 5886 r = kvm_inject_smi(vcpu); 5887 break; 5888 } 5889 case KVM_SET_CPUID: { 5890 struct kvm_cpuid __user *cpuid_arg = argp; 5891 struct kvm_cpuid cpuid; 5892 5893 r = -EFAULT; 5894 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid))) 5895 goto out; 5896 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries); 5897 break; 5898 } 5899 case KVM_SET_CPUID2: { 5900 struct kvm_cpuid2 __user *cpuid_arg = argp; 5901 struct kvm_cpuid2 cpuid; 5902 5903 r = -EFAULT; 5904 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid))) 5905 goto out; 5906 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid, 5907 cpuid_arg->entries); 5908 break; 5909 } 5910 case KVM_GET_CPUID2: { 5911 struct kvm_cpuid2 __user *cpuid_arg = argp; 5912 struct kvm_cpuid2 cpuid; 5913 5914 r = -EFAULT; 5915 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid))) 5916 goto out; 5917 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid, 5918 cpuid_arg->entries); 5919 if (r) 5920 goto out; 5921 r = -EFAULT; 5922 if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid))) 5923 goto out; 5924 r = 0; 5925 break; 5926 } 5927 case KVM_GET_MSRS: { 5928 int idx = srcu_read_lock(&vcpu->kvm->srcu); 5929 r = msr_io(vcpu, argp, do_get_msr, 1); 5930 srcu_read_unlock(&vcpu->kvm->srcu, idx); 5931 break; 5932 } 5933 case KVM_SET_MSRS: { 5934 int idx = srcu_read_lock(&vcpu->kvm->srcu); 5935 r = msr_io(vcpu, argp, do_set_msr, 0); 5936 srcu_read_unlock(&vcpu->kvm->srcu, idx); 5937 break; 5938 } 5939 case KVM_TPR_ACCESS_REPORTING: { 5940 struct kvm_tpr_access_ctl tac; 5941 5942 r = -EFAULT; 5943 if (copy_from_user(&tac, argp, sizeof(tac))) 5944 goto out; 5945 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac); 5946 if (r) 5947 goto out; 5948 r = -EFAULT; 5949 if (copy_to_user(argp, &tac, sizeof(tac))) 5950 goto out; 5951 r = 0; 5952 break; 5953 }; 5954 case KVM_SET_VAPIC_ADDR: { 5955 struct kvm_vapic_addr va; 5956 int idx; 5957 5958 r = -EINVAL; 5959 if (!lapic_in_kernel(vcpu)) 5960 goto out; 5961 r = -EFAULT; 5962 if (copy_from_user(&va, argp, sizeof(va))) 5963 goto out; 5964 idx = srcu_read_lock(&vcpu->kvm->srcu); 5965 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr); 5966 srcu_read_unlock(&vcpu->kvm->srcu, idx); 5967 break; 5968 } 5969 case KVM_X86_SETUP_MCE: { 5970 u64 mcg_cap; 5971 5972 r = -EFAULT; 5973 if (copy_from_user(&mcg_cap, argp, sizeof(mcg_cap))) 5974 goto out; 5975 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap); 5976 break; 5977 } 5978 case KVM_X86_SET_MCE: { 5979 struct kvm_x86_mce mce; 5980 5981 r = -EFAULT; 5982 if (copy_from_user(&mce, argp, sizeof(mce))) 5983 goto out; 5984 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce); 5985 break; 5986 } 5987 case KVM_GET_VCPU_EVENTS: { 5988 struct kvm_vcpu_events events; 5989 5990 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events); 5991 5992 r = -EFAULT; 5993 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events))) 5994 break; 5995 r = 0; 5996 break; 5997 } 5998 case KVM_SET_VCPU_EVENTS: { 5999 struct kvm_vcpu_events events; 6000 6001 r = -EFAULT; 6002 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events))) 6003 break; 6004 6005 kvm_vcpu_srcu_read_lock(vcpu); 6006 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events); 6007 kvm_vcpu_srcu_read_unlock(vcpu); 6008 break; 6009 } 6010 case KVM_GET_DEBUGREGS: { 6011 struct kvm_debugregs dbgregs; 6012 6013 r = kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs); 6014 if (r < 0) 6015 break; 6016 6017 r = -EFAULT; 6018 if (copy_to_user(argp, &dbgregs, 6019 sizeof(struct kvm_debugregs))) 6020 break; 6021 r = 0; 6022 break; 6023 } 6024 case KVM_SET_DEBUGREGS: { 6025 struct kvm_debugregs dbgregs; 6026 6027 r = -EFAULT; 6028 if (copy_from_user(&dbgregs, argp, 6029 sizeof(struct kvm_debugregs))) 6030 break; 6031 6032 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs); 6033 break; 6034 } 6035 case KVM_GET_XSAVE: { 6036 r = -EINVAL; 6037 if (vcpu->arch.guest_fpu.uabi_size > sizeof(struct kvm_xsave)) 6038 break; 6039 6040 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL); 6041 r = -ENOMEM; 6042 if (!u.xsave) 6043 break; 6044 6045 r = kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave); 6046 if (r < 0) 6047 break; 6048 6049 r = -EFAULT; 6050 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave))) 6051 break; 6052 r = 0; 6053 break; 6054 } 6055 case KVM_SET_XSAVE: { 6056 int size = vcpu->arch.guest_fpu.uabi_size; 6057 6058 u.xsave = memdup_user(argp, size); 6059 if (IS_ERR(u.xsave)) { 6060 r = PTR_ERR(u.xsave); 6061 goto out_nofree; 6062 } 6063 6064 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave); 6065 break; 6066 } 6067 6068 case KVM_GET_XSAVE2: { 6069 int size = vcpu->arch.guest_fpu.uabi_size; 6070 6071 u.xsave = kzalloc(size, GFP_KERNEL); 6072 r = -ENOMEM; 6073 if (!u.xsave) 6074 break; 6075 6076 r = kvm_vcpu_ioctl_x86_get_xsave2(vcpu, u.buffer, size); 6077 if (r < 0) 6078 break; 6079 6080 r = -EFAULT; 6081 if (copy_to_user(argp, u.xsave, size)) 6082 break; 6083 6084 r = 0; 6085 break; 6086 } 6087 6088 case KVM_GET_XCRS: { 6089 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL); 6090 r = -ENOMEM; 6091 if (!u.xcrs) 6092 break; 6093 6094 r = kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs); 6095 if (r < 0) 6096 break; 6097 6098 r = -EFAULT; 6099 if (copy_to_user(argp, u.xcrs, 6100 sizeof(struct kvm_xcrs))) 6101 break; 6102 r = 0; 6103 break; 6104 } 6105 case KVM_SET_XCRS: { 6106 u.xcrs = memdup_user(argp, sizeof(*u.xcrs)); 6107 if (IS_ERR(u.xcrs)) { 6108 r = PTR_ERR(u.xcrs); 6109 goto out_nofree; 6110 } 6111 6112 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs); 6113 break; 6114 } 6115 case KVM_SET_TSC_KHZ: { 6116 u32 user_tsc_khz; 6117 6118 r = -EINVAL; 6119 user_tsc_khz = (u32)arg; 6120 6121 if (kvm_caps.has_tsc_control && 6122 user_tsc_khz >= kvm_caps.max_guest_tsc_khz) 6123 goto out; 6124 6125 if (user_tsc_khz == 0) 6126 user_tsc_khz = tsc_khz; 6127 6128 if (!kvm_set_tsc_khz(vcpu, user_tsc_khz)) 6129 r = 0; 6130 6131 goto out; 6132 } 6133 case KVM_GET_TSC_KHZ: { 6134 r = vcpu->arch.virtual_tsc_khz; 6135 goto out; 6136 } 6137 case KVM_KVMCLOCK_CTRL: { 6138 r = kvm_set_guest_paused(vcpu); 6139 goto out; 6140 } 6141 case KVM_ENABLE_CAP: { 6142 struct kvm_enable_cap cap; 6143 6144 r = -EFAULT; 6145 if (copy_from_user(&cap, argp, sizeof(cap))) 6146 goto out; 6147 r = kvm_vcpu_ioctl_enable_cap(vcpu, &cap); 6148 break; 6149 } 6150 case KVM_GET_NESTED_STATE: { 6151 struct kvm_nested_state __user *user_kvm_nested_state = argp; 6152 u32 user_data_size; 6153 6154 r = -EINVAL; 6155 if (!kvm_x86_ops.nested_ops->get_state) 6156 break; 6157 6158 BUILD_BUG_ON(sizeof(user_data_size) != sizeof(user_kvm_nested_state->size)); 6159 r = -EFAULT; 6160 if (get_user(user_data_size, &user_kvm_nested_state->size)) 6161 break; 6162 6163 r = kvm_x86_ops.nested_ops->get_state(vcpu, user_kvm_nested_state, 6164 user_data_size); 6165 if (r < 0) 6166 break; 6167 6168 if (r > user_data_size) { 6169 if (put_user(r, &user_kvm_nested_state->size)) 6170 r = -EFAULT; 6171 else 6172 r = -E2BIG; 6173 break; 6174 } 6175 6176 r = 0; 6177 break; 6178 } 6179 case KVM_SET_NESTED_STATE: { 6180 struct kvm_nested_state __user *user_kvm_nested_state = argp; 6181 struct kvm_nested_state kvm_state; 6182 int idx; 6183 6184 r = -EINVAL; 6185 if (!kvm_x86_ops.nested_ops->set_state) 6186 break; 6187 6188 r = -EFAULT; 6189 if (copy_from_user(&kvm_state, user_kvm_nested_state, sizeof(kvm_state))) 6190 break; 6191 6192 r = -EINVAL; 6193 if (kvm_state.size < sizeof(kvm_state)) 6194 break; 6195 6196 if (kvm_state.flags & 6197 ~(KVM_STATE_NESTED_RUN_PENDING | KVM_STATE_NESTED_GUEST_MODE 6198 | KVM_STATE_NESTED_EVMCS | KVM_STATE_NESTED_MTF_PENDING 6199 | KVM_STATE_NESTED_GIF_SET)) 6200 break; 6201 6202 /* nested_run_pending implies guest_mode. */ 6203 if ((kvm_state.flags & KVM_STATE_NESTED_RUN_PENDING) 6204 && !(kvm_state.flags & KVM_STATE_NESTED_GUEST_MODE)) 6205 break; 6206 6207 idx = srcu_read_lock(&vcpu->kvm->srcu); 6208 r = kvm_x86_ops.nested_ops->set_state(vcpu, user_kvm_nested_state, &kvm_state); 6209 srcu_read_unlock(&vcpu->kvm->srcu, idx); 6210 break; 6211 } 6212 #ifdef CONFIG_KVM_HYPERV 6213 case KVM_GET_SUPPORTED_HV_CPUID: 6214 r = kvm_ioctl_get_supported_hv_cpuid(vcpu, argp); 6215 break; 6216 #endif 6217 #ifdef CONFIG_KVM_XEN 6218 case KVM_XEN_VCPU_GET_ATTR: { 6219 struct kvm_xen_vcpu_attr xva; 6220 6221 r = -EFAULT; 6222 if (copy_from_user(&xva, argp, sizeof(xva))) 6223 goto out; 6224 r = kvm_xen_vcpu_get_attr(vcpu, &xva); 6225 if (!r && copy_to_user(argp, &xva, sizeof(xva))) 6226 r = -EFAULT; 6227 break; 6228 } 6229 case KVM_XEN_VCPU_SET_ATTR: { 6230 struct kvm_xen_vcpu_attr xva; 6231 6232 r = -EFAULT; 6233 if (copy_from_user(&xva, argp, sizeof(xva))) 6234 goto out; 6235 r = kvm_xen_vcpu_set_attr(vcpu, &xva); 6236 break; 6237 } 6238 #endif 6239 case KVM_GET_SREGS2: { 6240 r = -EINVAL; 6241 if (vcpu->kvm->arch.has_protected_state && 6242 vcpu->arch.guest_state_protected) 6243 goto out; 6244 6245 u.sregs2 = kzalloc(sizeof(struct kvm_sregs2), GFP_KERNEL); 6246 r = -ENOMEM; 6247 if (!u.sregs2) 6248 goto out; 6249 __get_sregs2(vcpu, u.sregs2); 6250 r = -EFAULT; 6251 if (copy_to_user(argp, u.sregs2, sizeof(struct kvm_sregs2))) 6252 goto out; 6253 r = 0; 6254 break; 6255 } 6256 case KVM_SET_SREGS2: { 6257 r = -EINVAL; 6258 if (vcpu->kvm->arch.has_protected_state && 6259 vcpu->arch.guest_state_protected) 6260 goto out; 6261 6262 u.sregs2 = memdup_user(argp, sizeof(struct kvm_sregs2)); 6263 if (IS_ERR(u.sregs2)) { 6264 r = PTR_ERR(u.sregs2); 6265 u.sregs2 = NULL; 6266 goto out; 6267 } 6268 r = __set_sregs2(vcpu, u.sregs2); 6269 break; 6270 } 6271 case KVM_HAS_DEVICE_ATTR: 6272 case KVM_GET_DEVICE_ATTR: 6273 case KVM_SET_DEVICE_ATTR: 6274 r = kvm_vcpu_ioctl_device_attr(vcpu, ioctl, argp); 6275 break; 6276 default: 6277 r = -EINVAL; 6278 } 6279 out: 6280 kfree(u.buffer); 6281 out_nofree: 6282 vcpu_put(vcpu); 6283 return r; 6284 } 6285 6286 vm_fault_t kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf) 6287 { 6288 return VM_FAULT_SIGBUS; 6289 } 6290 6291 static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr) 6292 { 6293 int ret; 6294 6295 if (addr > (unsigned int)(-3 * PAGE_SIZE)) 6296 return -EINVAL; 6297 ret = kvm_x86_call(set_tss_addr)(kvm, addr); 6298 return ret; 6299 } 6300 6301 static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm, 6302 u64 ident_addr) 6303 { 6304 return kvm_x86_call(set_identity_map_addr)(kvm, ident_addr); 6305 } 6306 6307 static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm, 6308 unsigned long kvm_nr_mmu_pages) 6309 { 6310 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES) 6311 return -EINVAL; 6312 6313 mutex_lock(&kvm->slots_lock); 6314 6315 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages); 6316 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages; 6317 6318 mutex_unlock(&kvm->slots_lock); 6319 return 0; 6320 } 6321 6322 static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip) 6323 { 6324 struct kvm_pic *pic = kvm->arch.vpic; 6325 int r; 6326 6327 r = 0; 6328 switch (chip->chip_id) { 6329 case KVM_IRQCHIP_PIC_MASTER: 6330 memcpy(&chip->chip.pic, &pic->pics[0], 6331 sizeof(struct kvm_pic_state)); 6332 break; 6333 case KVM_IRQCHIP_PIC_SLAVE: 6334 memcpy(&chip->chip.pic, &pic->pics[1], 6335 sizeof(struct kvm_pic_state)); 6336 break; 6337 case KVM_IRQCHIP_IOAPIC: 6338 kvm_get_ioapic(kvm, &chip->chip.ioapic); 6339 break; 6340 default: 6341 r = -EINVAL; 6342 break; 6343 } 6344 return r; 6345 } 6346 6347 static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip) 6348 { 6349 struct kvm_pic *pic = kvm->arch.vpic; 6350 int r; 6351 6352 r = 0; 6353 switch (chip->chip_id) { 6354 case KVM_IRQCHIP_PIC_MASTER: 6355 spin_lock(&pic->lock); 6356 memcpy(&pic->pics[0], &chip->chip.pic, 6357 sizeof(struct kvm_pic_state)); 6358 spin_unlock(&pic->lock); 6359 break; 6360 case KVM_IRQCHIP_PIC_SLAVE: 6361 spin_lock(&pic->lock); 6362 memcpy(&pic->pics[1], &chip->chip.pic, 6363 sizeof(struct kvm_pic_state)); 6364 spin_unlock(&pic->lock); 6365 break; 6366 case KVM_IRQCHIP_IOAPIC: 6367 kvm_set_ioapic(kvm, &chip->chip.ioapic); 6368 break; 6369 default: 6370 r = -EINVAL; 6371 break; 6372 } 6373 kvm_pic_update_irq(pic); 6374 return r; 6375 } 6376 6377 static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps) 6378 { 6379 struct kvm_kpit_state *kps = &kvm->arch.vpit->pit_state; 6380 6381 BUILD_BUG_ON(sizeof(*ps) != sizeof(kps->channels)); 6382 6383 mutex_lock(&kps->lock); 6384 memcpy(ps, &kps->channels, sizeof(*ps)); 6385 mutex_unlock(&kps->lock); 6386 return 0; 6387 } 6388 6389 static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps) 6390 { 6391 int i; 6392 struct kvm_pit *pit = kvm->arch.vpit; 6393 6394 mutex_lock(&pit->pit_state.lock); 6395 memcpy(&pit->pit_state.channels, ps, sizeof(*ps)); 6396 for (i = 0; i < 3; i++) 6397 kvm_pit_load_count(pit, i, ps->channels[i].count, 0); 6398 mutex_unlock(&pit->pit_state.lock); 6399 return 0; 6400 } 6401 6402 static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps) 6403 { 6404 mutex_lock(&kvm->arch.vpit->pit_state.lock); 6405 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels, 6406 sizeof(ps->channels)); 6407 ps->flags = kvm->arch.vpit->pit_state.flags; 6408 mutex_unlock(&kvm->arch.vpit->pit_state.lock); 6409 memset(&ps->reserved, 0, sizeof(ps->reserved)); 6410 return 0; 6411 } 6412 6413 static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps) 6414 { 6415 int start = 0; 6416 int i; 6417 u32 prev_legacy, cur_legacy; 6418 struct kvm_pit *pit = kvm->arch.vpit; 6419 6420 mutex_lock(&pit->pit_state.lock); 6421 prev_legacy = pit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY; 6422 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY; 6423 if (!prev_legacy && cur_legacy) 6424 start = 1; 6425 memcpy(&pit->pit_state.channels, &ps->channels, 6426 sizeof(pit->pit_state.channels)); 6427 pit->pit_state.flags = ps->flags; 6428 for (i = 0; i < 3; i++) 6429 kvm_pit_load_count(pit, i, pit->pit_state.channels[i].count, 6430 start && i == 0); 6431 mutex_unlock(&pit->pit_state.lock); 6432 return 0; 6433 } 6434 6435 static int kvm_vm_ioctl_reinject(struct kvm *kvm, 6436 struct kvm_reinject_control *control) 6437 { 6438 struct kvm_pit *pit = kvm->arch.vpit; 6439 6440 /* pit->pit_state.lock was overloaded to prevent userspace from getting 6441 * an inconsistent state after running multiple KVM_REINJECT_CONTROL 6442 * ioctls in parallel. Use a separate lock if that ioctl isn't rare. 6443 */ 6444 mutex_lock(&pit->pit_state.lock); 6445 kvm_pit_set_reinject(pit, control->pit_reinject); 6446 mutex_unlock(&pit->pit_state.lock); 6447 6448 return 0; 6449 } 6450 6451 void kvm_arch_sync_dirty_log(struct kvm *kvm, struct kvm_memory_slot *memslot) 6452 { 6453 6454 /* 6455 * Flush all CPUs' dirty log buffers to the dirty_bitmap. Called 6456 * before reporting dirty_bitmap to userspace. KVM flushes the buffers 6457 * on all VM-Exits, thus we only need to kick running vCPUs to force a 6458 * VM-Exit. 6459 */ 6460 struct kvm_vcpu *vcpu; 6461 unsigned long i; 6462 6463 if (!kvm_x86_ops.cpu_dirty_log_size) 6464 return; 6465 6466 kvm_for_each_vcpu(i, vcpu, kvm) 6467 kvm_vcpu_kick(vcpu); 6468 } 6469 6470 int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event, 6471 bool line_status) 6472 { 6473 if (!irqchip_in_kernel(kvm)) 6474 return -ENXIO; 6475 6476 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID, 6477 irq_event->irq, irq_event->level, 6478 line_status); 6479 return 0; 6480 } 6481 6482 int kvm_vm_ioctl_enable_cap(struct kvm *kvm, 6483 struct kvm_enable_cap *cap) 6484 { 6485 int r; 6486 6487 if (cap->flags) 6488 return -EINVAL; 6489 6490 switch (cap->cap) { 6491 case KVM_CAP_DISABLE_QUIRKS2: 6492 r = -EINVAL; 6493 if (cap->args[0] & ~KVM_X86_VALID_QUIRKS) 6494 break; 6495 fallthrough; 6496 case KVM_CAP_DISABLE_QUIRKS: 6497 kvm->arch.disabled_quirks = cap->args[0]; 6498 r = 0; 6499 break; 6500 case KVM_CAP_SPLIT_IRQCHIP: { 6501 mutex_lock(&kvm->lock); 6502 r = -EINVAL; 6503 if (cap->args[0] > MAX_NR_RESERVED_IOAPIC_PINS) 6504 goto split_irqchip_unlock; 6505 r = -EEXIST; 6506 if (irqchip_in_kernel(kvm)) 6507 goto split_irqchip_unlock; 6508 if (kvm->created_vcpus) 6509 goto split_irqchip_unlock; 6510 /* Pairs with irqchip_in_kernel. */ 6511 smp_wmb(); 6512 kvm->arch.irqchip_mode = KVM_IRQCHIP_SPLIT; 6513 kvm->arch.nr_reserved_ioapic_pins = cap->args[0]; 6514 kvm_clear_apicv_inhibit(kvm, APICV_INHIBIT_REASON_ABSENT); 6515 r = 0; 6516 split_irqchip_unlock: 6517 mutex_unlock(&kvm->lock); 6518 break; 6519 } 6520 case KVM_CAP_X2APIC_API: 6521 r = -EINVAL; 6522 if (cap->args[0] & ~KVM_X2APIC_API_VALID_FLAGS) 6523 break; 6524 6525 if (cap->args[0] & KVM_X2APIC_API_USE_32BIT_IDS) 6526 kvm->arch.x2apic_format = true; 6527 if (cap->args[0] & KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK) 6528 kvm->arch.x2apic_broadcast_quirk_disabled = true; 6529 6530 r = 0; 6531 break; 6532 case KVM_CAP_X86_DISABLE_EXITS: 6533 r = -EINVAL; 6534 if (cap->args[0] & ~kvm_get_allowed_disable_exits()) 6535 break; 6536 6537 mutex_lock(&kvm->lock); 6538 if (kvm->created_vcpus) 6539 goto disable_exits_unlock; 6540 6541 #define SMT_RSB_MSG "This processor is affected by the Cross-Thread Return Predictions vulnerability. " \ 6542 "KVM_CAP_X86_DISABLE_EXITS should only be used with SMT disabled or trusted guests." 6543 6544 if (!mitigate_smt_rsb && boot_cpu_has_bug(X86_BUG_SMT_RSB) && 6545 cpu_smt_possible() && 6546 (cap->args[0] & ~KVM_X86_DISABLE_EXITS_PAUSE)) 6547 pr_warn_once(SMT_RSB_MSG); 6548 6549 if (cap->args[0] & KVM_X86_DISABLE_EXITS_PAUSE) 6550 kvm->arch.pause_in_guest = true; 6551 if (cap->args[0] & KVM_X86_DISABLE_EXITS_MWAIT) 6552 kvm->arch.mwait_in_guest = true; 6553 if (cap->args[0] & KVM_X86_DISABLE_EXITS_HLT) 6554 kvm->arch.hlt_in_guest = true; 6555 if (cap->args[0] & KVM_X86_DISABLE_EXITS_CSTATE) 6556 kvm->arch.cstate_in_guest = true; 6557 r = 0; 6558 disable_exits_unlock: 6559 mutex_unlock(&kvm->lock); 6560 break; 6561 case KVM_CAP_MSR_PLATFORM_INFO: 6562 kvm->arch.guest_can_read_msr_platform_info = cap->args[0]; 6563 r = 0; 6564 break; 6565 case KVM_CAP_EXCEPTION_PAYLOAD: 6566 kvm->arch.exception_payload_enabled = cap->args[0]; 6567 r = 0; 6568 break; 6569 case KVM_CAP_X86_TRIPLE_FAULT_EVENT: 6570 kvm->arch.triple_fault_event = cap->args[0]; 6571 r = 0; 6572 break; 6573 case KVM_CAP_X86_USER_SPACE_MSR: 6574 r = -EINVAL; 6575 if (cap->args[0] & ~KVM_MSR_EXIT_REASON_VALID_MASK) 6576 break; 6577 kvm->arch.user_space_msr_mask = cap->args[0]; 6578 r = 0; 6579 break; 6580 case KVM_CAP_X86_BUS_LOCK_EXIT: 6581 r = -EINVAL; 6582 if (cap->args[0] & ~KVM_BUS_LOCK_DETECTION_VALID_MODE) 6583 break; 6584 6585 if ((cap->args[0] & KVM_BUS_LOCK_DETECTION_OFF) && 6586 (cap->args[0] & KVM_BUS_LOCK_DETECTION_EXIT)) 6587 break; 6588 6589 if (kvm_caps.has_bus_lock_exit && 6590 cap->args[0] & KVM_BUS_LOCK_DETECTION_EXIT) 6591 kvm->arch.bus_lock_detection_enabled = true; 6592 r = 0; 6593 break; 6594 #ifdef CONFIG_X86_SGX_KVM 6595 case KVM_CAP_SGX_ATTRIBUTE: { 6596 unsigned long allowed_attributes = 0; 6597 6598 r = sgx_set_attribute(&allowed_attributes, cap->args[0]); 6599 if (r) 6600 break; 6601 6602 /* KVM only supports the PROVISIONKEY privileged attribute. */ 6603 if ((allowed_attributes & SGX_ATTR_PROVISIONKEY) && 6604 !(allowed_attributes & ~SGX_ATTR_PROVISIONKEY)) 6605 kvm->arch.sgx_provisioning_allowed = true; 6606 else 6607 r = -EINVAL; 6608 break; 6609 } 6610 #endif 6611 case KVM_CAP_VM_COPY_ENC_CONTEXT_FROM: 6612 r = -EINVAL; 6613 if (!kvm_x86_ops.vm_copy_enc_context_from) 6614 break; 6615 6616 r = kvm_x86_call(vm_copy_enc_context_from)(kvm, cap->args[0]); 6617 break; 6618 case KVM_CAP_VM_MOVE_ENC_CONTEXT_FROM: 6619 r = -EINVAL; 6620 if (!kvm_x86_ops.vm_move_enc_context_from) 6621 break; 6622 6623 r = kvm_x86_call(vm_move_enc_context_from)(kvm, cap->args[0]); 6624 break; 6625 case KVM_CAP_EXIT_HYPERCALL: 6626 if (cap->args[0] & ~KVM_EXIT_HYPERCALL_VALID_MASK) { 6627 r = -EINVAL; 6628 break; 6629 } 6630 kvm->arch.hypercall_exit_enabled = cap->args[0]; 6631 r = 0; 6632 break; 6633 case KVM_CAP_EXIT_ON_EMULATION_FAILURE: 6634 r = -EINVAL; 6635 if (cap->args[0] & ~1) 6636 break; 6637 kvm->arch.exit_on_emulation_error = cap->args[0]; 6638 r = 0; 6639 break; 6640 case KVM_CAP_PMU_CAPABILITY: 6641 r = -EINVAL; 6642 if (!enable_pmu || (cap->args[0] & ~KVM_CAP_PMU_VALID_MASK)) 6643 break; 6644 6645 mutex_lock(&kvm->lock); 6646 if (!kvm->created_vcpus) { 6647 kvm->arch.enable_pmu = !(cap->args[0] & KVM_PMU_CAP_DISABLE); 6648 r = 0; 6649 } 6650 mutex_unlock(&kvm->lock); 6651 break; 6652 case KVM_CAP_MAX_VCPU_ID: 6653 r = -EINVAL; 6654 if (cap->args[0] > KVM_MAX_VCPU_IDS) 6655 break; 6656 6657 mutex_lock(&kvm->lock); 6658 if (kvm->arch.bsp_vcpu_id > cap->args[0]) { 6659 ; 6660 } else if (kvm->arch.max_vcpu_ids == cap->args[0]) { 6661 r = 0; 6662 } else if (!kvm->arch.max_vcpu_ids) { 6663 kvm->arch.max_vcpu_ids = cap->args[0]; 6664 r = 0; 6665 } 6666 mutex_unlock(&kvm->lock); 6667 break; 6668 case KVM_CAP_X86_NOTIFY_VMEXIT: 6669 r = -EINVAL; 6670 if ((u32)cap->args[0] & ~KVM_X86_NOTIFY_VMEXIT_VALID_BITS) 6671 break; 6672 if (!kvm_caps.has_notify_vmexit) 6673 break; 6674 if (!((u32)cap->args[0] & KVM_X86_NOTIFY_VMEXIT_ENABLED)) 6675 break; 6676 mutex_lock(&kvm->lock); 6677 if (!kvm->created_vcpus) { 6678 kvm->arch.notify_window = cap->args[0] >> 32; 6679 kvm->arch.notify_vmexit_flags = (u32)cap->args[0]; 6680 r = 0; 6681 } 6682 mutex_unlock(&kvm->lock); 6683 break; 6684 case KVM_CAP_VM_DISABLE_NX_HUGE_PAGES: 6685 r = -EINVAL; 6686 6687 /* 6688 * Since the risk of disabling NX hugepages is a guest crashing 6689 * the system, ensure the userspace process has permission to 6690 * reboot the system. 6691 * 6692 * Note that unlike the reboot() syscall, the process must have 6693 * this capability in the root namespace because exposing 6694 * /dev/kvm into a container does not limit the scope of the 6695 * iTLB multihit bug to that container. In other words, 6696 * this must use capable(), not ns_capable(). 6697 */ 6698 if (!capable(CAP_SYS_BOOT)) { 6699 r = -EPERM; 6700 break; 6701 } 6702 6703 if (cap->args[0]) 6704 break; 6705 6706 mutex_lock(&kvm->lock); 6707 if (!kvm->created_vcpus) { 6708 kvm->arch.disable_nx_huge_pages = true; 6709 r = 0; 6710 } 6711 mutex_unlock(&kvm->lock); 6712 break; 6713 case KVM_CAP_X86_APIC_BUS_CYCLES_NS: { 6714 u64 bus_cycle_ns = cap->args[0]; 6715 u64 unused; 6716 6717 /* 6718 * Guard against overflow in tmict_to_ns(). 128 is the highest 6719 * divide value that can be programmed in APIC_TDCR. 6720 */ 6721 r = -EINVAL; 6722 if (!bus_cycle_ns || 6723 check_mul_overflow((u64)U32_MAX * 128, bus_cycle_ns, &unused)) 6724 break; 6725 6726 r = 0; 6727 mutex_lock(&kvm->lock); 6728 if (!irqchip_in_kernel(kvm)) 6729 r = -ENXIO; 6730 else if (kvm->created_vcpus) 6731 r = -EINVAL; 6732 else 6733 kvm->arch.apic_bus_cycle_ns = bus_cycle_ns; 6734 mutex_unlock(&kvm->lock); 6735 break; 6736 } 6737 default: 6738 r = -EINVAL; 6739 break; 6740 } 6741 return r; 6742 } 6743 6744 static struct kvm_x86_msr_filter *kvm_alloc_msr_filter(bool default_allow) 6745 { 6746 struct kvm_x86_msr_filter *msr_filter; 6747 6748 msr_filter = kzalloc(sizeof(*msr_filter), GFP_KERNEL_ACCOUNT); 6749 if (!msr_filter) 6750 return NULL; 6751 6752 msr_filter->default_allow = default_allow; 6753 return msr_filter; 6754 } 6755 6756 static void kvm_free_msr_filter(struct kvm_x86_msr_filter *msr_filter) 6757 { 6758 u32 i; 6759 6760 if (!msr_filter) 6761 return; 6762 6763 for (i = 0; i < msr_filter->count; i++) 6764 kfree(msr_filter->ranges[i].bitmap); 6765 6766 kfree(msr_filter); 6767 } 6768 6769 static int kvm_add_msr_filter(struct kvm_x86_msr_filter *msr_filter, 6770 struct kvm_msr_filter_range *user_range) 6771 { 6772 unsigned long *bitmap; 6773 size_t bitmap_size; 6774 6775 if (!user_range->nmsrs) 6776 return 0; 6777 6778 if (user_range->flags & ~KVM_MSR_FILTER_RANGE_VALID_MASK) 6779 return -EINVAL; 6780 6781 if (!user_range->flags) 6782 return -EINVAL; 6783 6784 bitmap_size = BITS_TO_LONGS(user_range->nmsrs) * sizeof(long); 6785 if (!bitmap_size || bitmap_size > KVM_MSR_FILTER_MAX_BITMAP_SIZE) 6786 return -EINVAL; 6787 6788 bitmap = memdup_user((__user u8*)user_range->bitmap, bitmap_size); 6789 if (IS_ERR(bitmap)) 6790 return PTR_ERR(bitmap); 6791 6792 msr_filter->ranges[msr_filter->count] = (struct msr_bitmap_range) { 6793 .flags = user_range->flags, 6794 .base = user_range->base, 6795 .nmsrs = user_range->nmsrs, 6796 .bitmap = bitmap, 6797 }; 6798 6799 msr_filter->count++; 6800 return 0; 6801 } 6802 6803 static int kvm_vm_ioctl_set_msr_filter(struct kvm *kvm, 6804 struct kvm_msr_filter *filter) 6805 { 6806 struct kvm_x86_msr_filter *new_filter, *old_filter; 6807 bool default_allow; 6808 bool empty = true; 6809 int r; 6810 u32 i; 6811 6812 if (filter->flags & ~KVM_MSR_FILTER_VALID_MASK) 6813 return -EINVAL; 6814 6815 for (i = 0; i < ARRAY_SIZE(filter->ranges); i++) 6816 empty &= !filter->ranges[i].nmsrs; 6817 6818 default_allow = !(filter->flags & KVM_MSR_FILTER_DEFAULT_DENY); 6819 if (empty && !default_allow) 6820 return -EINVAL; 6821 6822 new_filter = kvm_alloc_msr_filter(default_allow); 6823 if (!new_filter) 6824 return -ENOMEM; 6825 6826 for (i = 0; i < ARRAY_SIZE(filter->ranges); i++) { 6827 r = kvm_add_msr_filter(new_filter, &filter->ranges[i]); 6828 if (r) { 6829 kvm_free_msr_filter(new_filter); 6830 return r; 6831 } 6832 } 6833 6834 mutex_lock(&kvm->lock); 6835 old_filter = rcu_replace_pointer(kvm->arch.msr_filter, new_filter, 6836 mutex_is_locked(&kvm->lock)); 6837 mutex_unlock(&kvm->lock); 6838 synchronize_srcu(&kvm->srcu); 6839 6840 kvm_free_msr_filter(old_filter); 6841 6842 kvm_make_all_cpus_request(kvm, KVM_REQ_MSR_FILTER_CHANGED); 6843 6844 return 0; 6845 } 6846 6847 #ifdef CONFIG_KVM_COMPAT 6848 /* for KVM_X86_SET_MSR_FILTER */ 6849 struct kvm_msr_filter_range_compat { 6850 __u32 flags; 6851 __u32 nmsrs; 6852 __u32 base; 6853 __u32 bitmap; 6854 }; 6855 6856 struct kvm_msr_filter_compat { 6857 __u32 flags; 6858 struct kvm_msr_filter_range_compat ranges[KVM_MSR_FILTER_MAX_RANGES]; 6859 }; 6860 6861 #define KVM_X86_SET_MSR_FILTER_COMPAT _IOW(KVMIO, 0xc6, struct kvm_msr_filter_compat) 6862 6863 long kvm_arch_vm_compat_ioctl(struct file *filp, unsigned int ioctl, 6864 unsigned long arg) 6865 { 6866 void __user *argp = (void __user *)arg; 6867 struct kvm *kvm = filp->private_data; 6868 long r = -ENOTTY; 6869 6870 switch (ioctl) { 6871 case KVM_X86_SET_MSR_FILTER_COMPAT: { 6872 struct kvm_msr_filter __user *user_msr_filter = argp; 6873 struct kvm_msr_filter_compat filter_compat; 6874 struct kvm_msr_filter filter; 6875 int i; 6876 6877 if (copy_from_user(&filter_compat, user_msr_filter, 6878 sizeof(filter_compat))) 6879 return -EFAULT; 6880 6881 filter.flags = filter_compat.flags; 6882 for (i = 0; i < ARRAY_SIZE(filter.ranges); i++) { 6883 struct kvm_msr_filter_range_compat *cr; 6884 6885 cr = &filter_compat.ranges[i]; 6886 filter.ranges[i] = (struct kvm_msr_filter_range) { 6887 .flags = cr->flags, 6888 .nmsrs = cr->nmsrs, 6889 .base = cr->base, 6890 .bitmap = (__u8 *)(ulong)cr->bitmap, 6891 }; 6892 } 6893 6894 r = kvm_vm_ioctl_set_msr_filter(kvm, &filter); 6895 break; 6896 } 6897 } 6898 6899 return r; 6900 } 6901 #endif 6902 6903 #ifdef CONFIG_HAVE_KVM_PM_NOTIFIER 6904 static int kvm_arch_suspend_notifier(struct kvm *kvm) 6905 { 6906 struct kvm_vcpu *vcpu; 6907 unsigned long i; 6908 int ret = 0; 6909 6910 mutex_lock(&kvm->lock); 6911 kvm_for_each_vcpu(i, vcpu, kvm) { 6912 if (!vcpu->arch.pv_time.active) 6913 continue; 6914 6915 ret = kvm_set_guest_paused(vcpu); 6916 if (ret) { 6917 kvm_err("Failed to pause guest VCPU%d: %d\n", 6918 vcpu->vcpu_id, ret); 6919 break; 6920 } 6921 } 6922 mutex_unlock(&kvm->lock); 6923 6924 return ret ? NOTIFY_BAD : NOTIFY_DONE; 6925 } 6926 6927 int kvm_arch_pm_notifier(struct kvm *kvm, unsigned long state) 6928 { 6929 switch (state) { 6930 case PM_HIBERNATION_PREPARE: 6931 case PM_SUSPEND_PREPARE: 6932 return kvm_arch_suspend_notifier(kvm); 6933 } 6934 6935 return NOTIFY_DONE; 6936 } 6937 #endif /* CONFIG_HAVE_KVM_PM_NOTIFIER */ 6938 6939 static int kvm_vm_ioctl_get_clock(struct kvm *kvm, void __user *argp) 6940 { 6941 struct kvm_clock_data data = { 0 }; 6942 6943 get_kvmclock(kvm, &data); 6944 if (copy_to_user(argp, &data, sizeof(data))) 6945 return -EFAULT; 6946 6947 return 0; 6948 } 6949 6950 static int kvm_vm_ioctl_set_clock(struct kvm *kvm, void __user *argp) 6951 { 6952 struct kvm_arch *ka = &kvm->arch; 6953 struct kvm_clock_data data; 6954 u64 now_raw_ns; 6955 6956 if (copy_from_user(&data, argp, sizeof(data))) 6957 return -EFAULT; 6958 6959 /* 6960 * Only KVM_CLOCK_REALTIME is used, but allow passing the 6961 * result of KVM_GET_CLOCK back to KVM_SET_CLOCK. 6962 */ 6963 if (data.flags & ~KVM_CLOCK_VALID_FLAGS) 6964 return -EINVAL; 6965 6966 kvm_hv_request_tsc_page_update(kvm); 6967 kvm_start_pvclock_update(kvm); 6968 pvclock_update_vm_gtod_copy(kvm); 6969 6970 /* 6971 * This pairs with kvm_guest_time_update(): when masterclock is 6972 * in use, we use master_kernel_ns + kvmclock_offset to set 6973 * unsigned 'system_time' so if we use get_kvmclock_ns() (which 6974 * is slightly ahead) here we risk going negative on unsigned 6975 * 'system_time' when 'data.clock' is very small. 6976 */ 6977 if (data.flags & KVM_CLOCK_REALTIME) { 6978 u64 now_real_ns = ktime_get_real_ns(); 6979 6980 /* 6981 * Avoid stepping the kvmclock backwards. 6982 */ 6983 if (now_real_ns > data.realtime) 6984 data.clock += now_real_ns - data.realtime; 6985 } 6986 6987 if (ka->use_master_clock) 6988 now_raw_ns = ka->master_kernel_ns; 6989 else 6990 now_raw_ns = get_kvmclock_base_ns(); 6991 ka->kvmclock_offset = data.clock - now_raw_ns; 6992 kvm_end_pvclock_update(kvm); 6993 return 0; 6994 } 6995 6996 int kvm_arch_vm_ioctl(struct file *filp, unsigned int ioctl, unsigned long arg) 6997 { 6998 struct kvm *kvm = filp->private_data; 6999 void __user *argp = (void __user *)arg; 7000 int r = -ENOTTY; 7001 /* 7002 * This union makes it completely explicit to gcc-3.x 7003 * that these two variables' stack usage should be 7004 * combined, not added together. 7005 */ 7006 union { 7007 struct kvm_pit_state ps; 7008 struct kvm_pit_state2 ps2; 7009 struct kvm_pit_config pit_config; 7010 } u; 7011 7012 switch (ioctl) { 7013 case KVM_SET_TSS_ADDR: 7014 r = kvm_vm_ioctl_set_tss_addr(kvm, arg); 7015 break; 7016 case KVM_SET_IDENTITY_MAP_ADDR: { 7017 u64 ident_addr; 7018 7019 mutex_lock(&kvm->lock); 7020 r = -EINVAL; 7021 if (kvm->created_vcpus) 7022 goto set_identity_unlock; 7023 r = -EFAULT; 7024 if (copy_from_user(&ident_addr, argp, sizeof(ident_addr))) 7025 goto set_identity_unlock; 7026 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr); 7027 set_identity_unlock: 7028 mutex_unlock(&kvm->lock); 7029 break; 7030 } 7031 case KVM_SET_NR_MMU_PAGES: 7032 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg); 7033 break; 7034 case KVM_CREATE_IRQCHIP: { 7035 mutex_lock(&kvm->lock); 7036 7037 r = -EEXIST; 7038 if (irqchip_in_kernel(kvm)) 7039 goto create_irqchip_unlock; 7040 7041 r = -EINVAL; 7042 if (kvm->created_vcpus) 7043 goto create_irqchip_unlock; 7044 7045 r = kvm_pic_init(kvm); 7046 if (r) 7047 goto create_irqchip_unlock; 7048 7049 r = kvm_ioapic_init(kvm); 7050 if (r) { 7051 kvm_pic_destroy(kvm); 7052 goto create_irqchip_unlock; 7053 } 7054 7055 r = kvm_setup_default_irq_routing(kvm); 7056 if (r) { 7057 kvm_ioapic_destroy(kvm); 7058 kvm_pic_destroy(kvm); 7059 goto create_irqchip_unlock; 7060 } 7061 /* Write kvm->irq_routing before enabling irqchip_in_kernel. */ 7062 smp_wmb(); 7063 kvm->arch.irqchip_mode = KVM_IRQCHIP_KERNEL; 7064 kvm_clear_apicv_inhibit(kvm, APICV_INHIBIT_REASON_ABSENT); 7065 create_irqchip_unlock: 7066 mutex_unlock(&kvm->lock); 7067 break; 7068 } 7069 case KVM_CREATE_PIT: 7070 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY; 7071 goto create_pit; 7072 case KVM_CREATE_PIT2: 7073 r = -EFAULT; 7074 if (copy_from_user(&u.pit_config, argp, 7075 sizeof(struct kvm_pit_config))) 7076 goto out; 7077 create_pit: 7078 mutex_lock(&kvm->lock); 7079 r = -EEXIST; 7080 if (kvm->arch.vpit) 7081 goto create_pit_unlock; 7082 r = -ENOENT; 7083 if (!pic_in_kernel(kvm)) 7084 goto create_pit_unlock; 7085 r = -ENOMEM; 7086 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags); 7087 if (kvm->arch.vpit) 7088 r = 0; 7089 create_pit_unlock: 7090 mutex_unlock(&kvm->lock); 7091 break; 7092 case KVM_GET_IRQCHIP: { 7093 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */ 7094 struct kvm_irqchip *chip; 7095 7096 chip = memdup_user(argp, sizeof(*chip)); 7097 if (IS_ERR(chip)) { 7098 r = PTR_ERR(chip); 7099 goto out; 7100 } 7101 7102 r = -ENXIO; 7103 if (!irqchip_kernel(kvm)) 7104 goto get_irqchip_out; 7105 r = kvm_vm_ioctl_get_irqchip(kvm, chip); 7106 if (r) 7107 goto get_irqchip_out; 7108 r = -EFAULT; 7109 if (copy_to_user(argp, chip, sizeof(*chip))) 7110 goto get_irqchip_out; 7111 r = 0; 7112 get_irqchip_out: 7113 kfree(chip); 7114 break; 7115 } 7116 case KVM_SET_IRQCHIP: { 7117 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */ 7118 struct kvm_irqchip *chip; 7119 7120 chip = memdup_user(argp, sizeof(*chip)); 7121 if (IS_ERR(chip)) { 7122 r = PTR_ERR(chip); 7123 goto out; 7124 } 7125 7126 r = -ENXIO; 7127 if (!irqchip_kernel(kvm)) 7128 goto set_irqchip_out; 7129 r = kvm_vm_ioctl_set_irqchip(kvm, chip); 7130 set_irqchip_out: 7131 kfree(chip); 7132 break; 7133 } 7134 case KVM_GET_PIT: { 7135 r = -EFAULT; 7136 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state))) 7137 goto out; 7138 r = -ENXIO; 7139 if (!kvm->arch.vpit) 7140 goto out; 7141 r = kvm_vm_ioctl_get_pit(kvm, &u.ps); 7142 if (r) 7143 goto out; 7144 r = -EFAULT; 7145 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state))) 7146 goto out; 7147 r = 0; 7148 break; 7149 } 7150 case KVM_SET_PIT: { 7151 r = -EFAULT; 7152 if (copy_from_user(&u.ps, argp, sizeof(u.ps))) 7153 goto out; 7154 mutex_lock(&kvm->lock); 7155 r = -ENXIO; 7156 if (!kvm->arch.vpit) 7157 goto set_pit_out; 7158 r = kvm_vm_ioctl_set_pit(kvm, &u.ps); 7159 set_pit_out: 7160 mutex_unlock(&kvm->lock); 7161 break; 7162 } 7163 case KVM_GET_PIT2: { 7164 r = -ENXIO; 7165 if (!kvm->arch.vpit) 7166 goto out; 7167 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2); 7168 if (r) 7169 goto out; 7170 r = -EFAULT; 7171 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2))) 7172 goto out; 7173 r = 0; 7174 break; 7175 } 7176 case KVM_SET_PIT2: { 7177 r = -EFAULT; 7178 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2))) 7179 goto out; 7180 mutex_lock(&kvm->lock); 7181 r = -ENXIO; 7182 if (!kvm->arch.vpit) 7183 goto set_pit2_out; 7184 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2); 7185 set_pit2_out: 7186 mutex_unlock(&kvm->lock); 7187 break; 7188 } 7189 case KVM_REINJECT_CONTROL: { 7190 struct kvm_reinject_control control; 7191 r = -EFAULT; 7192 if (copy_from_user(&control, argp, sizeof(control))) 7193 goto out; 7194 r = -ENXIO; 7195 if (!kvm->arch.vpit) 7196 goto out; 7197 r = kvm_vm_ioctl_reinject(kvm, &control); 7198 break; 7199 } 7200 case KVM_SET_BOOT_CPU_ID: 7201 r = 0; 7202 mutex_lock(&kvm->lock); 7203 if (kvm->created_vcpus) 7204 r = -EBUSY; 7205 else if (arg > KVM_MAX_VCPU_IDS || 7206 (kvm->arch.max_vcpu_ids && arg > kvm->arch.max_vcpu_ids)) 7207 r = -EINVAL; 7208 else 7209 kvm->arch.bsp_vcpu_id = arg; 7210 mutex_unlock(&kvm->lock); 7211 break; 7212 #ifdef CONFIG_KVM_XEN 7213 case KVM_XEN_HVM_CONFIG: { 7214 struct kvm_xen_hvm_config xhc; 7215 r = -EFAULT; 7216 if (copy_from_user(&xhc, argp, sizeof(xhc))) 7217 goto out; 7218 r = kvm_xen_hvm_config(kvm, &xhc); 7219 break; 7220 } 7221 case KVM_XEN_HVM_GET_ATTR: { 7222 struct kvm_xen_hvm_attr xha; 7223 7224 r = -EFAULT; 7225 if (copy_from_user(&xha, argp, sizeof(xha))) 7226 goto out; 7227 r = kvm_xen_hvm_get_attr(kvm, &xha); 7228 if (!r && copy_to_user(argp, &xha, sizeof(xha))) 7229 r = -EFAULT; 7230 break; 7231 } 7232 case KVM_XEN_HVM_SET_ATTR: { 7233 struct kvm_xen_hvm_attr xha; 7234 7235 r = -EFAULT; 7236 if (copy_from_user(&xha, argp, sizeof(xha))) 7237 goto out; 7238 r = kvm_xen_hvm_set_attr(kvm, &xha); 7239 break; 7240 } 7241 case KVM_XEN_HVM_EVTCHN_SEND: { 7242 struct kvm_irq_routing_xen_evtchn uxe; 7243 7244 r = -EFAULT; 7245 if (copy_from_user(&uxe, argp, sizeof(uxe))) 7246 goto out; 7247 r = kvm_xen_hvm_evtchn_send(kvm, &uxe); 7248 break; 7249 } 7250 #endif 7251 case KVM_SET_CLOCK: 7252 r = kvm_vm_ioctl_set_clock(kvm, argp); 7253 break; 7254 case KVM_GET_CLOCK: 7255 r = kvm_vm_ioctl_get_clock(kvm, argp); 7256 break; 7257 case KVM_SET_TSC_KHZ: { 7258 u32 user_tsc_khz; 7259 7260 r = -EINVAL; 7261 user_tsc_khz = (u32)arg; 7262 7263 if (kvm_caps.has_tsc_control && 7264 user_tsc_khz >= kvm_caps.max_guest_tsc_khz) 7265 goto out; 7266 7267 if (user_tsc_khz == 0) 7268 user_tsc_khz = tsc_khz; 7269 7270 WRITE_ONCE(kvm->arch.default_tsc_khz, user_tsc_khz); 7271 r = 0; 7272 7273 goto out; 7274 } 7275 case KVM_GET_TSC_KHZ: { 7276 r = READ_ONCE(kvm->arch.default_tsc_khz); 7277 goto out; 7278 } 7279 case KVM_MEMORY_ENCRYPT_OP: { 7280 r = -ENOTTY; 7281 if (!kvm_x86_ops.mem_enc_ioctl) 7282 goto out; 7283 7284 r = kvm_x86_call(mem_enc_ioctl)(kvm, argp); 7285 break; 7286 } 7287 case KVM_MEMORY_ENCRYPT_REG_REGION: { 7288 struct kvm_enc_region region; 7289 7290 r = -EFAULT; 7291 if (copy_from_user(®ion, argp, sizeof(region))) 7292 goto out; 7293 7294 r = -ENOTTY; 7295 if (!kvm_x86_ops.mem_enc_register_region) 7296 goto out; 7297 7298 r = kvm_x86_call(mem_enc_register_region)(kvm, ®ion); 7299 break; 7300 } 7301 case KVM_MEMORY_ENCRYPT_UNREG_REGION: { 7302 struct kvm_enc_region region; 7303 7304 r = -EFAULT; 7305 if (copy_from_user(®ion, argp, sizeof(region))) 7306 goto out; 7307 7308 r = -ENOTTY; 7309 if (!kvm_x86_ops.mem_enc_unregister_region) 7310 goto out; 7311 7312 r = kvm_x86_call(mem_enc_unregister_region)(kvm, ®ion); 7313 break; 7314 } 7315 #ifdef CONFIG_KVM_HYPERV 7316 case KVM_HYPERV_EVENTFD: { 7317 struct kvm_hyperv_eventfd hvevfd; 7318 7319 r = -EFAULT; 7320 if (copy_from_user(&hvevfd, argp, sizeof(hvevfd))) 7321 goto out; 7322 r = kvm_vm_ioctl_hv_eventfd(kvm, &hvevfd); 7323 break; 7324 } 7325 #endif 7326 case KVM_SET_PMU_EVENT_FILTER: 7327 r = kvm_vm_ioctl_set_pmu_event_filter(kvm, argp); 7328 break; 7329 case KVM_X86_SET_MSR_FILTER: { 7330 struct kvm_msr_filter __user *user_msr_filter = argp; 7331 struct kvm_msr_filter filter; 7332 7333 if (copy_from_user(&filter, user_msr_filter, sizeof(filter))) 7334 return -EFAULT; 7335 7336 r = kvm_vm_ioctl_set_msr_filter(kvm, &filter); 7337 break; 7338 } 7339 default: 7340 r = -ENOTTY; 7341 } 7342 out: 7343 return r; 7344 } 7345 7346 static void kvm_probe_feature_msr(u32 msr_index) 7347 { 7348 u64 data; 7349 7350 if (kvm_get_feature_msr(NULL, msr_index, &data, true)) 7351 return; 7352 7353 msr_based_features[num_msr_based_features++] = msr_index; 7354 } 7355 7356 static void kvm_probe_msr_to_save(u32 msr_index) 7357 { 7358 u32 dummy[2]; 7359 7360 if (rdmsr_safe(msr_index, &dummy[0], &dummy[1])) 7361 return; 7362 7363 /* 7364 * Even MSRs that are valid in the host may not be exposed to guests in 7365 * some cases. 7366 */ 7367 switch (msr_index) { 7368 case MSR_IA32_BNDCFGS: 7369 if (!kvm_mpx_supported()) 7370 return; 7371 break; 7372 case MSR_TSC_AUX: 7373 if (!kvm_cpu_cap_has(X86_FEATURE_RDTSCP) && 7374 !kvm_cpu_cap_has(X86_FEATURE_RDPID)) 7375 return; 7376 break; 7377 case MSR_IA32_UMWAIT_CONTROL: 7378 if (!kvm_cpu_cap_has(X86_FEATURE_WAITPKG)) 7379 return; 7380 break; 7381 case MSR_IA32_RTIT_CTL: 7382 case MSR_IA32_RTIT_STATUS: 7383 if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT)) 7384 return; 7385 break; 7386 case MSR_IA32_RTIT_CR3_MATCH: 7387 if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT) || 7388 !intel_pt_validate_hw_cap(PT_CAP_cr3_filtering)) 7389 return; 7390 break; 7391 case MSR_IA32_RTIT_OUTPUT_BASE: 7392 case MSR_IA32_RTIT_OUTPUT_MASK: 7393 if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT) || 7394 (!intel_pt_validate_hw_cap(PT_CAP_topa_output) && 7395 !intel_pt_validate_hw_cap(PT_CAP_single_range_output))) 7396 return; 7397 break; 7398 case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B: 7399 if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT) || 7400 (msr_index - MSR_IA32_RTIT_ADDR0_A >= 7401 intel_pt_validate_hw_cap(PT_CAP_num_address_ranges) * 2)) 7402 return; 7403 break; 7404 case MSR_ARCH_PERFMON_PERFCTR0 ... 7405 MSR_ARCH_PERFMON_PERFCTR0 + KVM_MAX_NR_GP_COUNTERS - 1: 7406 if (msr_index - MSR_ARCH_PERFMON_PERFCTR0 >= 7407 kvm_pmu_cap.num_counters_gp) 7408 return; 7409 break; 7410 case MSR_ARCH_PERFMON_EVENTSEL0 ... 7411 MSR_ARCH_PERFMON_EVENTSEL0 + KVM_MAX_NR_GP_COUNTERS - 1: 7412 if (msr_index - MSR_ARCH_PERFMON_EVENTSEL0 >= 7413 kvm_pmu_cap.num_counters_gp) 7414 return; 7415 break; 7416 case MSR_ARCH_PERFMON_FIXED_CTR0 ... 7417 MSR_ARCH_PERFMON_FIXED_CTR0 + KVM_MAX_NR_FIXED_COUNTERS - 1: 7418 if (msr_index - MSR_ARCH_PERFMON_FIXED_CTR0 >= 7419 kvm_pmu_cap.num_counters_fixed) 7420 return; 7421 break; 7422 case MSR_AMD64_PERF_CNTR_GLOBAL_CTL: 7423 case MSR_AMD64_PERF_CNTR_GLOBAL_STATUS: 7424 case MSR_AMD64_PERF_CNTR_GLOBAL_STATUS_CLR: 7425 if (!kvm_cpu_cap_has(X86_FEATURE_PERFMON_V2)) 7426 return; 7427 break; 7428 case MSR_IA32_XFD: 7429 case MSR_IA32_XFD_ERR: 7430 if (!kvm_cpu_cap_has(X86_FEATURE_XFD)) 7431 return; 7432 break; 7433 case MSR_IA32_TSX_CTRL: 7434 if (!(kvm_get_arch_capabilities() & ARCH_CAP_TSX_CTRL_MSR)) 7435 return; 7436 break; 7437 default: 7438 break; 7439 } 7440 7441 msrs_to_save[num_msrs_to_save++] = msr_index; 7442 } 7443 7444 static void kvm_init_msr_lists(void) 7445 { 7446 unsigned i; 7447 7448 BUILD_BUG_ON_MSG(KVM_MAX_NR_FIXED_COUNTERS != 3, 7449 "Please update the fixed PMCs in msrs_to_save_pmu[]"); 7450 7451 num_msrs_to_save = 0; 7452 num_emulated_msrs = 0; 7453 num_msr_based_features = 0; 7454 7455 for (i = 0; i < ARRAY_SIZE(msrs_to_save_base); i++) 7456 kvm_probe_msr_to_save(msrs_to_save_base[i]); 7457 7458 if (enable_pmu) { 7459 for (i = 0; i < ARRAY_SIZE(msrs_to_save_pmu); i++) 7460 kvm_probe_msr_to_save(msrs_to_save_pmu[i]); 7461 } 7462 7463 for (i = 0; i < ARRAY_SIZE(emulated_msrs_all); i++) { 7464 if (!kvm_x86_call(has_emulated_msr)(NULL, 7465 emulated_msrs_all[i])) 7466 continue; 7467 7468 emulated_msrs[num_emulated_msrs++] = emulated_msrs_all[i]; 7469 } 7470 7471 for (i = KVM_FIRST_EMULATED_VMX_MSR; i <= KVM_LAST_EMULATED_VMX_MSR; i++) 7472 kvm_probe_feature_msr(i); 7473 7474 for (i = 0; i < ARRAY_SIZE(msr_based_features_all_except_vmx); i++) 7475 kvm_probe_feature_msr(msr_based_features_all_except_vmx[i]); 7476 } 7477 7478 static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len, 7479 const void *v) 7480 { 7481 int handled = 0; 7482 int n; 7483 7484 do { 7485 n = min(len, 8); 7486 if (!(lapic_in_kernel(vcpu) && 7487 !kvm_iodevice_write(vcpu, &vcpu->arch.apic->dev, addr, n, v)) 7488 && kvm_io_bus_write(vcpu, KVM_MMIO_BUS, addr, n, v)) 7489 break; 7490 handled += n; 7491 addr += n; 7492 len -= n; 7493 v += n; 7494 } while (len); 7495 7496 return handled; 7497 } 7498 7499 static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v) 7500 { 7501 int handled = 0; 7502 int n; 7503 7504 do { 7505 n = min(len, 8); 7506 if (!(lapic_in_kernel(vcpu) && 7507 !kvm_iodevice_read(vcpu, &vcpu->arch.apic->dev, 7508 addr, n, v)) 7509 && kvm_io_bus_read(vcpu, KVM_MMIO_BUS, addr, n, v)) 7510 break; 7511 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, v); 7512 handled += n; 7513 addr += n; 7514 len -= n; 7515 v += n; 7516 } while (len); 7517 7518 return handled; 7519 } 7520 7521 void kvm_set_segment(struct kvm_vcpu *vcpu, 7522 struct kvm_segment *var, int seg) 7523 { 7524 kvm_x86_call(set_segment)(vcpu, var, seg); 7525 } 7526 7527 void kvm_get_segment(struct kvm_vcpu *vcpu, 7528 struct kvm_segment *var, int seg) 7529 { 7530 kvm_x86_call(get_segment)(vcpu, var, seg); 7531 } 7532 7533 gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u64 access, 7534 struct x86_exception *exception) 7535 { 7536 struct kvm_mmu *mmu = vcpu->arch.mmu; 7537 gpa_t t_gpa; 7538 7539 BUG_ON(!mmu_is_nested(vcpu)); 7540 7541 /* NPT walks are always user-walks */ 7542 access |= PFERR_USER_MASK; 7543 t_gpa = mmu->gva_to_gpa(vcpu, mmu, gpa, access, exception); 7544 7545 return t_gpa; 7546 } 7547 7548 gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva, 7549 struct x86_exception *exception) 7550 { 7551 struct kvm_mmu *mmu = vcpu->arch.walk_mmu; 7552 7553 u64 access = (kvm_x86_call(get_cpl)(vcpu) == 3) ? PFERR_USER_MASK : 0; 7554 return mmu->gva_to_gpa(vcpu, mmu, gva, access, exception); 7555 } 7556 EXPORT_SYMBOL_GPL(kvm_mmu_gva_to_gpa_read); 7557 7558 gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva, 7559 struct x86_exception *exception) 7560 { 7561 struct kvm_mmu *mmu = vcpu->arch.walk_mmu; 7562 7563 u64 access = (kvm_x86_call(get_cpl)(vcpu) == 3) ? PFERR_USER_MASK : 0; 7564 access |= PFERR_WRITE_MASK; 7565 return mmu->gva_to_gpa(vcpu, mmu, gva, access, exception); 7566 } 7567 EXPORT_SYMBOL_GPL(kvm_mmu_gva_to_gpa_write); 7568 7569 /* uses this to access any guest's mapped memory without checking CPL */ 7570 gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva, 7571 struct x86_exception *exception) 7572 { 7573 struct kvm_mmu *mmu = vcpu->arch.walk_mmu; 7574 7575 return mmu->gva_to_gpa(vcpu, mmu, gva, 0, exception); 7576 } 7577 7578 static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes, 7579 struct kvm_vcpu *vcpu, u64 access, 7580 struct x86_exception *exception) 7581 { 7582 struct kvm_mmu *mmu = vcpu->arch.walk_mmu; 7583 void *data = val; 7584 int r = X86EMUL_CONTINUE; 7585 7586 while (bytes) { 7587 gpa_t gpa = mmu->gva_to_gpa(vcpu, mmu, addr, access, exception); 7588 unsigned offset = addr & (PAGE_SIZE-1); 7589 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset); 7590 int ret; 7591 7592 if (gpa == INVALID_GPA) 7593 return X86EMUL_PROPAGATE_FAULT; 7594 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, data, 7595 offset, toread); 7596 if (ret < 0) { 7597 r = X86EMUL_IO_NEEDED; 7598 goto out; 7599 } 7600 7601 bytes -= toread; 7602 data += toread; 7603 addr += toread; 7604 } 7605 out: 7606 return r; 7607 } 7608 7609 /* used for instruction fetching */ 7610 static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt, 7611 gva_t addr, void *val, unsigned int bytes, 7612 struct x86_exception *exception) 7613 { 7614 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 7615 struct kvm_mmu *mmu = vcpu->arch.walk_mmu; 7616 u64 access = (kvm_x86_call(get_cpl)(vcpu) == 3) ? PFERR_USER_MASK : 0; 7617 unsigned offset; 7618 int ret; 7619 7620 /* Inline kvm_read_guest_virt_helper for speed. */ 7621 gpa_t gpa = mmu->gva_to_gpa(vcpu, mmu, addr, access|PFERR_FETCH_MASK, 7622 exception); 7623 if (unlikely(gpa == INVALID_GPA)) 7624 return X86EMUL_PROPAGATE_FAULT; 7625 7626 offset = addr & (PAGE_SIZE-1); 7627 if (WARN_ON(offset + bytes > PAGE_SIZE)) 7628 bytes = (unsigned)PAGE_SIZE - offset; 7629 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, val, 7630 offset, bytes); 7631 if (unlikely(ret < 0)) 7632 return X86EMUL_IO_NEEDED; 7633 7634 return X86EMUL_CONTINUE; 7635 } 7636 7637 int kvm_read_guest_virt(struct kvm_vcpu *vcpu, 7638 gva_t addr, void *val, unsigned int bytes, 7639 struct x86_exception *exception) 7640 { 7641 u64 access = (kvm_x86_call(get_cpl)(vcpu) == 3) ? PFERR_USER_MASK : 0; 7642 7643 /* 7644 * FIXME: this should call handle_emulation_failure if X86EMUL_IO_NEEDED 7645 * is returned, but our callers are not ready for that and they blindly 7646 * call kvm_inject_page_fault. Ensure that they at least do not leak 7647 * uninitialized kernel stack memory into cr2 and error code. 7648 */ 7649 memset(exception, 0, sizeof(*exception)); 7650 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access, 7651 exception); 7652 } 7653 EXPORT_SYMBOL_GPL(kvm_read_guest_virt); 7654 7655 static int emulator_read_std(struct x86_emulate_ctxt *ctxt, 7656 gva_t addr, void *val, unsigned int bytes, 7657 struct x86_exception *exception, bool system) 7658 { 7659 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 7660 u64 access = 0; 7661 7662 if (system) 7663 access |= PFERR_IMPLICIT_ACCESS; 7664 else if (kvm_x86_call(get_cpl)(vcpu) == 3) 7665 access |= PFERR_USER_MASK; 7666 7667 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access, exception); 7668 } 7669 7670 static int kvm_write_guest_virt_helper(gva_t addr, void *val, unsigned int bytes, 7671 struct kvm_vcpu *vcpu, u64 access, 7672 struct x86_exception *exception) 7673 { 7674 struct kvm_mmu *mmu = vcpu->arch.walk_mmu; 7675 void *data = val; 7676 int r = X86EMUL_CONTINUE; 7677 7678 while (bytes) { 7679 gpa_t gpa = mmu->gva_to_gpa(vcpu, mmu, addr, access, exception); 7680 unsigned offset = addr & (PAGE_SIZE-1); 7681 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset); 7682 int ret; 7683 7684 if (gpa == INVALID_GPA) 7685 return X86EMUL_PROPAGATE_FAULT; 7686 ret = kvm_vcpu_write_guest(vcpu, gpa, data, towrite); 7687 if (ret < 0) { 7688 r = X86EMUL_IO_NEEDED; 7689 goto out; 7690 } 7691 7692 bytes -= towrite; 7693 data += towrite; 7694 addr += towrite; 7695 } 7696 out: 7697 return r; 7698 } 7699 7700 static int emulator_write_std(struct x86_emulate_ctxt *ctxt, gva_t addr, void *val, 7701 unsigned int bytes, struct x86_exception *exception, 7702 bool system) 7703 { 7704 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 7705 u64 access = PFERR_WRITE_MASK; 7706 7707 if (system) 7708 access |= PFERR_IMPLICIT_ACCESS; 7709 else if (kvm_x86_call(get_cpl)(vcpu) == 3) 7710 access |= PFERR_USER_MASK; 7711 7712 return kvm_write_guest_virt_helper(addr, val, bytes, vcpu, 7713 access, exception); 7714 } 7715 7716 int kvm_write_guest_virt_system(struct kvm_vcpu *vcpu, gva_t addr, void *val, 7717 unsigned int bytes, struct x86_exception *exception) 7718 { 7719 /* kvm_write_guest_virt_system can pull in tons of pages. */ 7720 vcpu->arch.l1tf_flush_l1d = true; 7721 7722 return kvm_write_guest_virt_helper(addr, val, bytes, vcpu, 7723 PFERR_WRITE_MASK, exception); 7724 } 7725 EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system); 7726 7727 static int kvm_check_emulate_insn(struct kvm_vcpu *vcpu, int emul_type, 7728 void *insn, int insn_len) 7729 { 7730 return kvm_x86_call(check_emulate_instruction)(vcpu, emul_type, 7731 insn, insn_len); 7732 } 7733 7734 int handle_ud(struct kvm_vcpu *vcpu) 7735 { 7736 static const char kvm_emulate_prefix[] = { __KVM_EMULATE_PREFIX }; 7737 int fep_flags = READ_ONCE(force_emulation_prefix); 7738 int emul_type = EMULTYPE_TRAP_UD; 7739 char sig[5]; /* ud2; .ascii "kvm" */ 7740 struct x86_exception e; 7741 int r; 7742 7743 r = kvm_check_emulate_insn(vcpu, emul_type, NULL, 0); 7744 if (r != X86EMUL_CONTINUE) 7745 return 1; 7746 7747 if (fep_flags && 7748 kvm_read_guest_virt(vcpu, kvm_get_linear_rip(vcpu), 7749 sig, sizeof(sig), &e) == 0 && 7750 memcmp(sig, kvm_emulate_prefix, sizeof(sig)) == 0) { 7751 if (fep_flags & KVM_FEP_CLEAR_RFLAGS_RF) 7752 kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) & ~X86_EFLAGS_RF); 7753 kvm_rip_write(vcpu, kvm_rip_read(vcpu) + sizeof(sig)); 7754 emul_type = EMULTYPE_TRAP_UD_FORCED; 7755 } 7756 7757 return kvm_emulate_instruction(vcpu, emul_type); 7758 } 7759 EXPORT_SYMBOL_GPL(handle_ud); 7760 7761 static int vcpu_is_mmio_gpa(struct kvm_vcpu *vcpu, unsigned long gva, 7762 gpa_t gpa, bool write) 7763 { 7764 /* For APIC access vmexit */ 7765 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE) 7766 return 1; 7767 7768 if (vcpu_match_mmio_gpa(vcpu, gpa)) { 7769 trace_vcpu_match_mmio(gva, gpa, write, true); 7770 return 1; 7771 } 7772 7773 return 0; 7774 } 7775 7776 static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva, 7777 gpa_t *gpa, struct x86_exception *exception, 7778 bool write) 7779 { 7780 struct kvm_mmu *mmu = vcpu->arch.walk_mmu; 7781 u64 access = ((kvm_x86_call(get_cpl)(vcpu) == 3) ? PFERR_USER_MASK : 0) 7782 | (write ? PFERR_WRITE_MASK : 0); 7783 7784 /* 7785 * currently PKRU is only applied to ept enabled guest so 7786 * there is no pkey in EPT page table for L1 guest or EPT 7787 * shadow page table for L2 guest. 7788 */ 7789 if (vcpu_match_mmio_gva(vcpu, gva) && (!is_paging(vcpu) || 7790 !permission_fault(vcpu, vcpu->arch.walk_mmu, 7791 vcpu->arch.mmio_access, 0, access))) { 7792 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT | 7793 (gva & (PAGE_SIZE - 1)); 7794 trace_vcpu_match_mmio(gva, *gpa, write, false); 7795 return 1; 7796 } 7797 7798 *gpa = mmu->gva_to_gpa(vcpu, mmu, gva, access, exception); 7799 7800 if (*gpa == INVALID_GPA) 7801 return -1; 7802 7803 return vcpu_is_mmio_gpa(vcpu, gva, *gpa, write); 7804 } 7805 7806 int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa, 7807 const void *val, int bytes) 7808 { 7809 int ret; 7810 7811 ret = kvm_vcpu_write_guest(vcpu, gpa, val, bytes); 7812 if (ret < 0) 7813 return 0; 7814 kvm_page_track_write(vcpu, gpa, val, bytes); 7815 return 1; 7816 } 7817 7818 struct read_write_emulator_ops { 7819 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val, 7820 int bytes); 7821 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa, 7822 void *val, int bytes); 7823 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa, 7824 int bytes, void *val); 7825 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa, 7826 void *val, int bytes); 7827 bool write; 7828 }; 7829 7830 static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes) 7831 { 7832 if (vcpu->mmio_read_completed) { 7833 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes, 7834 vcpu->mmio_fragments[0].gpa, val); 7835 vcpu->mmio_read_completed = 0; 7836 return 1; 7837 } 7838 7839 return 0; 7840 } 7841 7842 static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa, 7843 void *val, int bytes) 7844 { 7845 return !kvm_vcpu_read_guest(vcpu, gpa, val, bytes); 7846 } 7847 7848 static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa, 7849 void *val, int bytes) 7850 { 7851 return emulator_write_phys(vcpu, gpa, val, bytes); 7852 } 7853 7854 static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val) 7855 { 7856 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, val); 7857 return vcpu_mmio_write(vcpu, gpa, bytes, val); 7858 } 7859 7860 static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, 7861 void *val, int bytes) 7862 { 7863 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, NULL); 7864 return X86EMUL_IO_NEEDED; 7865 } 7866 7867 static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, 7868 void *val, int bytes) 7869 { 7870 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0]; 7871 7872 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len)); 7873 return X86EMUL_CONTINUE; 7874 } 7875 7876 static const struct read_write_emulator_ops read_emultor = { 7877 .read_write_prepare = read_prepare, 7878 .read_write_emulate = read_emulate, 7879 .read_write_mmio = vcpu_mmio_read, 7880 .read_write_exit_mmio = read_exit_mmio, 7881 }; 7882 7883 static const struct read_write_emulator_ops write_emultor = { 7884 .read_write_emulate = write_emulate, 7885 .read_write_mmio = write_mmio, 7886 .read_write_exit_mmio = write_exit_mmio, 7887 .write = true, 7888 }; 7889 7890 static int emulator_read_write_onepage(unsigned long addr, void *val, 7891 unsigned int bytes, 7892 struct x86_exception *exception, 7893 struct kvm_vcpu *vcpu, 7894 const struct read_write_emulator_ops *ops) 7895 { 7896 gpa_t gpa; 7897 int handled, ret; 7898 bool write = ops->write; 7899 struct kvm_mmio_fragment *frag; 7900 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt; 7901 7902 /* 7903 * If the exit was due to a NPF we may already have a GPA. 7904 * If the GPA is present, use it to avoid the GVA to GPA table walk. 7905 * Note, this cannot be used on string operations since string 7906 * operation using rep will only have the initial GPA from the NPF 7907 * occurred. 7908 */ 7909 if (ctxt->gpa_available && emulator_can_use_gpa(ctxt) && 7910 (addr & ~PAGE_MASK) == (ctxt->gpa_val & ~PAGE_MASK)) { 7911 gpa = ctxt->gpa_val; 7912 ret = vcpu_is_mmio_gpa(vcpu, addr, gpa, write); 7913 } else { 7914 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write); 7915 if (ret < 0) 7916 return X86EMUL_PROPAGATE_FAULT; 7917 } 7918 7919 if (!ret && ops->read_write_emulate(vcpu, gpa, val, bytes)) 7920 return X86EMUL_CONTINUE; 7921 7922 /* 7923 * Is this MMIO handled locally? 7924 */ 7925 handled = ops->read_write_mmio(vcpu, gpa, bytes, val); 7926 if (handled == bytes) 7927 return X86EMUL_CONTINUE; 7928 7929 gpa += handled; 7930 bytes -= handled; 7931 val += handled; 7932 7933 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS); 7934 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++]; 7935 frag->gpa = gpa; 7936 frag->data = val; 7937 frag->len = bytes; 7938 return X86EMUL_CONTINUE; 7939 } 7940 7941 static int emulator_read_write(struct x86_emulate_ctxt *ctxt, 7942 unsigned long addr, 7943 void *val, unsigned int bytes, 7944 struct x86_exception *exception, 7945 const struct read_write_emulator_ops *ops) 7946 { 7947 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 7948 gpa_t gpa; 7949 int rc; 7950 7951 if (ops->read_write_prepare && 7952 ops->read_write_prepare(vcpu, val, bytes)) 7953 return X86EMUL_CONTINUE; 7954 7955 vcpu->mmio_nr_fragments = 0; 7956 7957 /* Crossing a page boundary? */ 7958 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) { 7959 int now; 7960 7961 now = -addr & ~PAGE_MASK; 7962 rc = emulator_read_write_onepage(addr, val, now, exception, 7963 vcpu, ops); 7964 7965 if (rc != X86EMUL_CONTINUE) 7966 return rc; 7967 addr += now; 7968 if (ctxt->mode != X86EMUL_MODE_PROT64) 7969 addr = (u32)addr; 7970 val += now; 7971 bytes -= now; 7972 } 7973 7974 rc = emulator_read_write_onepage(addr, val, bytes, exception, 7975 vcpu, ops); 7976 if (rc != X86EMUL_CONTINUE) 7977 return rc; 7978 7979 if (!vcpu->mmio_nr_fragments) 7980 return rc; 7981 7982 gpa = vcpu->mmio_fragments[0].gpa; 7983 7984 vcpu->mmio_needed = 1; 7985 vcpu->mmio_cur_fragment = 0; 7986 7987 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len); 7988 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write; 7989 vcpu->run->exit_reason = KVM_EXIT_MMIO; 7990 vcpu->run->mmio.phys_addr = gpa; 7991 7992 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes); 7993 } 7994 7995 static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt, 7996 unsigned long addr, 7997 void *val, 7998 unsigned int bytes, 7999 struct x86_exception *exception) 8000 { 8001 return emulator_read_write(ctxt, addr, val, bytes, 8002 exception, &read_emultor); 8003 } 8004 8005 static int emulator_write_emulated(struct x86_emulate_ctxt *ctxt, 8006 unsigned long addr, 8007 const void *val, 8008 unsigned int bytes, 8009 struct x86_exception *exception) 8010 { 8011 return emulator_read_write(ctxt, addr, (void *)val, bytes, 8012 exception, &write_emultor); 8013 } 8014 8015 #define emulator_try_cmpxchg_user(t, ptr, old, new) \ 8016 (__try_cmpxchg_user((t __user *)(ptr), (t *)(old), *(t *)(new), efault ## t)) 8017 8018 static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt, 8019 unsigned long addr, 8020 const void *old, 8021 const void *new, 8022 unsigned int bytes, 8023 struct x86_exception *exception) 8024 { 8025 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 8026 u64 page_line_mask; 8027 unsigned long hva; 8028 gpa_t gpa; 8029 int r; 8030 8031 /* guests cmpxchg8b have to be emulated atomically */ 8032 if (bytes > 8 || (bytes & (bytes - 1))) 8033 goto emul_write; 8034 8035 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL); 8036 8037 if (gpa == INVALID_GPA || 8038 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE) 8039 goto emul_write; 8040 8041 /* 8042 * Emulate the atomic as a straight write to avoid #AC if SLD is 8043 * enabled in the host and the access splits a cache line. 8044 */ 8045 if (boot_cpu_has(X86_FEATURE_SPLIT_LOCK_DETECT)) 8046 page_line_mask = ~(cache_line_size() - 1); 8047 else 8048 page_line_mask = PAGE_MASK; 8049 8050 if (((gpa + bytes - 1) & page_line_mask) != (gpa & page_line_mask)) 8051 goto emul_write; 8052 8053 hva = kvm_vcpu_gfn_to_hva(vcpu, gpa_to_gfn(gpa)); 8054 if (kvm_is_error_hva(hva)) 8055 goto emul_write; 8056 8057 hva += offset_in_page(gpa); 8058 8059 switch (bytes) { 8060 case 1: 8061 r = emulator_try_cmpxchg_user(u8, hva, old, new); 8062 break; 8063 case 2: 8064 r = emulator_try_cmpxchg_user(u16, hva, old, new); 8065 break; 8066 case 4: 8067 r = emulator_try_cmpxchg_user(u32, hva, old, new); 8068 break; 8069 case 8: 8070 r = emulator_try_cmpxchg_user(u64, hva, old, new); 8071 break; 8072 default: 8073 BUG(); 8074 } 8075 8076 if (r < 0) 8077 return X86EMUL_UNHANDLEABLE; 8078 8079 /* 8080 * Mark the page dirty _before_ checking whether or not the CMPXCHG was 8081 * successful, as the old value is written back on failure. Note, for 8082 * live migration, this is unnecessarily conservative as CMPXCHG writes 8083 * back the original value and the access is atomic, but KVM's ABI is 8084 * that all writes are dirty logged, regardless of the value written. 8085 */ 8086 kvm_vcpu_mark_page_dirty(vcpu, gpa_to_gfn(gpa)); 8087 8088 if (r) 8089 return X86EMUL_CMPXCHG_FAILED; 8090 8091 kvm_page_track_write(vcpu, gpa, new, bytes); 8092 8093 return X86EMUL_CONTINUE; 8094 8095 emul_write: 8096 pr_warn_once("emulating exchange as write\n"); 8097 8098 return emulator_write_emulated(ctxt, addr, new, bytes, exception); 8099 } 8100 8101 static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size, 8102 unsigned short port, void *data, 8103 unsigned int count, bool in) 8104 { 8105 unsigned i; 8106 int r; 8107 8108 WARN_ON_ONCE(vcpu->arch.pio.count); 8109 for (i = 0; i < count; i++) { 8110 if (in) 8111 r = kvm_io_bus_read(vcpu, KVM_PIO_BUS, port, size, data); 8112 else 8113 r = kvm_io_bus_write(vcpu, KVM_PIO_BUS, port, size, data); 8114 8115 if (r) { 8116 if (i == 0) 8117 goto userspace_io; 8118 8119 /* 8120 * Userspace must have unregistered the device while PIO 8121 * was running. Drop writes / read as 0. 8122 */ 8123 if (in) 8124 memset(data, 0, size * (count - i)); 8125 break; 8126 } 8127 8128 data += size; 8129 } 8130 return 1; 8131 8132 userspace_io: 8133 vcpu->arch.pio.port = port; 8134 vcpu->arch.pio.in = in; 8135 vcpu->arch.pio.count = count; 8136 vcpu->arch.pio.size = size; 8137 8138 if (in) 8139 memset(vcpu->arch.pio_data, 0, size * count); 8140 else 8141 memcpy(vcpu->arch.pio_data, data, size * count); 8142 8143 vcpu->run->exit_reason = KVM_EXIT_IO; 8144 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT; 8145 vcpu->run->io.size = size; 8146 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE; 8147 vcpu->run->io.count = count; 8148 vcpu->run->io.port = port; 8149 return 0; 8150 } 8151 8152 static int emulator_pio_in(struct kvm_vcpu *vcpu, int size, 8153 unsigned short port, void *val, unsigned int count) 8154 { 8155 int r = emulator_pio_in_out(vcpu, size, port, val, count, true); 8156 if (r) 8157 trace_kvm_pio(KVM_PIO_IN, port, size, count, val); 8158 8159 return r; 8160 } 8161 8162 static void complete_emulator_pio_in(struct kvm_vcpu *vcpu, void *val) 8163 { 8164 int size = vcpu->arch.pio.size; 8165 unsigned int count = vcpu->arch.pio.count; 8166 memcpy(val, vcpu->arch.pio_data, size * count); 8167 trace_kvm_pio(KVM_PIO_IN, vcpu->arch.pio.port, size, count, vcpu->arch.pio_data); 8168 vcpu->arch.pio.count = 0; 8169 } 8170 8171 static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt, 8172 int size, unsigned short port, void *val, 8173 unsigned int count) 8174 { 8175 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 8176 if (vcpu->arch.pio.count) { 8177 /* 8178 * Complete a previous iteration that required userspace I/O. 8179 * Note, @count isn't guaranteed to match pio.count as userspace 8180 * can modify ECX before rerunning the vCPU. Ignore any such 8181 * shenanigans as KVM doesn't support modifying the rep count, 8182 * and the emulator ensures @count doesn't overflow the buffer. 8183 */ 8184 complete_emulator_pio_in(vcpu, val); 8185 return 1; 8186 } 8187 8188 return emulator_pio_in(vcpu, size, port, val, count); 8189 } 8190 8191 static int emulator_pio_out(struct kvm_vcpu *vcpu, int size, 8192 unsigned short port, const void *val, 8193 unsigned int count) 8194 { 8195 trace_kvm_pio(KVM_PIO_OUT, port, size, count, val); 8196 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false); 8197 } 8198 8199 static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt, 8200 int size, unsigned short port, 8201 const void *val, unsigned int count) 8202 { 8203 return emulator_pio_out(emul_to_vcpu(ctxt), size, port, val, count); 8204 } 8205 8206 static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg) 8207 { 8208 return kvm_x86_call(get_segment_base)(vcpu, seg); 8209 } 8210 8211 static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address) 8212 { 8213 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address); 8214 } 8215 8216 static int kvm_emulate_wbinvd_noskip(struct kvm_vcpu *vcpu) 8217 { 8218 if (!need_emulate_wbinvd(vcpu)) 8219 return X86EMUL_CONTINUE; 8220 8221 if (kvm_x86_call(has_wbinvd_exit)()) { 8222 int cpu = get_cpu(); 8223 8224 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask); 8225 on_each_cpu_mask(vcpu->arch.wbinvd_dirty_mask, 8226 wbinvd_ipi, NULL, 1); 8227 put_cpu(); 8228 cpumask_clear(vcpu->arch.wbinvd_dirty_mask); 8229 } else 8230 wbinvd(); 8231 return X86EMUL_CONTINUE; 8232 } 8233 8234 int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu) 8235 { 8236 kvm_emulate_wbinvd_noskip(vcpu); 8237 return kvm_skip_emulated_instruction(vcpu); 8238 } 8239 EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd); 8240 8241 8242 8243 static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt) 8244 { 8245 kvm_emulate_wbinvd_noskip(emul_to_vcpu(ctxt)); 8246 } 8247 8248 static unsigned long emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr) 8249 { 8250 return kvm_get_dr(emul_to_vcpu(ctxt), dr); 8251 } 8252 8253 static int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr, 8254 unsigned long value) 8255 { 8256 8257 return kvm_set_dr(emul_to_vcpu(ctxt), dr, value); 8258 } 8259 8260 static u64 mk_cr_64(u64 curr_cr, u32 new_val) 8261 { 8262 return (curr_cr & ~((1ULL << 32) - 1)) | new_val; 8263 } 8264 8265 static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr) 8266 { 8267 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 8268 unsigned long value; 8269 8270 switch (cr) { 8271 case 0: 8272 value = kvm_read_cr0(vcpu); 8273 break; 8274 case 2: 8275 value = vcpu->arch.cr2; 8276 break; 8277 case 3: 8278 value = kvm_read_cr3(vcpu); 8279 break; 8280 case 4: 8281 value = kvm_read_cr4(vcpu); 8282 break; 8283 case 8: 8284 value = kvm_get_cr8(vcpu); 8285 break; 8286 default: 8287 kvm_err("%s: unexpected cr %u\n", __func__, cr); 8288 return 0; 8289 } 8290 8291 return value; 8292 } 8293 8294 static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val) 8295 { 8296 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 8297 int res = 0; 8298 8299 switch (cr) { 8300 case 0: 8301 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val)); 8302 break; 8303 case 2: 8304 vcpu->arch.cr2 = val; 8305 break; 8306 case 3: 8307 res = kvm_set_cr3(vcpu, val); 8308 break; 8309 case 4: 8310 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val)); 8311 break; 8312 case 8: 8313 res = kvm_set_cr8(vcpu, val); 8314 break; 8315 default: 8316 kvm_err("%s: unexpected cr %u\n", __func__, cr); 8317 res = -1; 8318 } 8319 8320 return res; 8321 } 8322 8323 static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt) 8324 { 8325 return kvm_x86_call(get_cpl)(emul_to_vcpu(ctxt)); 8326 } 8327 8328 static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt) 8329 { 8330 kvm_x86_call(get_gdt)(emul_to_vcpu(ctxt), dt); 8331 } 8332 8333 static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt) 8334 { 8335 kvm_x86_call(get_idt)(emul_to_vcpu(ctxt), dt); 8336 } 8337 8338 static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt) 8339 { 8340 kvm_x86_call(set_gdt)(emul_to_vcpu(ctxt), dt); 8341 } 8342 8343 static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt) 8344 { 8345 kvm_x86_call(set_idt)(emul_to_vcpu(ctxt), dt); 8346 } 8347 8348 static unsigned long emulator_get_cached_segment_base( 8349 struct x86_emulate_ctxt *ctxt, int seg) 8350 { 8351 return get_segment_base(emul_to_vcpu(ctxt), seg); 8352 } 8353 8354 static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector, 8355 struct desc_struct *desc, u32 *base3, 8356 int seg) 8357 { 8358 struct kvm_segment var; 8359 8360 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg); 8361 *selector = var.selector; 8362 8363 if (var.unusable) { 8364 memset(desc, 0, sizeof(*desc)); 8365 if (base3) 8366 *base3 = 0; 8367 return false; 8368 } 8369 8370 if (var.g) 8371 var.limit >>= 12; 8372 set_desc_limit(desc, var.limit); 8373 set_desc_base(desc, (unsigned long)var.base); 8374 #ifdef CONFIG_X86_64 8375 if (base3) 8376 *base3 = var.base >> 32; 8377 #endif 8378 desc->type = var.type; 8379 desc->s = var.s; 8380 desc->dpl = var.dpl; 8381 desc->p = var.present; 8382 desc->avl = var.avl; 8383 desc->l = var.l; 8384 desc->d = var.db; 8385 desc->g = var.g; 8386 8387 return true; 8388 } 8389 8390 static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector, 8391 struct desc_struct *desc, u32 base3, 8392 int seg) 8393 { 8394 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 8395 struct kvm_segment var; 8396 8397 var.selector = selector; 8398 var.base = get_desc_base(desc); 8399 #ifdef CONFIG_X86_64 8400 var.base |= ((u64)base3) << 32; 8401 #endif 8402 var.limit = get_desc_limit(desc); 8403 if (desc->g) 8404 var.limit = (var.limit << 12) | 0xfff; 8405 var.type = desc->type; 8406 var.dpl = desc->dpl; 8407 var.db = desc->d; 8408 var.s = desc->s; 8409 var.l = desc->l; 8410 var.g = desc->g; 8411 var.avl = desc->avl; 8412 var.present = desc->p; 8413 var.unusable = !var.present; 8414 var.padding = 0; 8415 8416 kvm_set_segment(vcpu, &var, seg); 8417 return; 8418 } 8419 8420 static int emulator_get_msr_with_filter(struct x86_emulate_ctxt *ctxt, 8421 u32 msr_index, u64 *pdata) 8422 { 8423 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 8424 int r; 8425 8426 r = kvm_get_msr_with_filter(vcpu, msr_index, pdata); 8427 if (r < 0) 8428 return X86EMUL_UNHANDLEABLE; 8429 8430 if (r) { 8431 if (kvm_msr_user_space(vcpu, msr_index, KVM_EXIT_X86_RDMSR, 0, 8432 complete_emulated_rdmsr, r)) 8433 return X86EMUL_IO_NEEDED; 8434 8435 trace_kvm_msr_read_ex(msr_index); 8436 return X86EMUL_PROPAGATE_FAULT; 8437 } 8438 8439 trace_kvm_msr_read(msr_index, *pdata); 8440 return X86EMUL_CONTINUE; 8441 } 8442 8443 static int emulator_set_msr_with_filter(struct x86_emulate_ctxt *ctxt, 8444 u32 msr_index, u64 data) 8445 { 8446 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 8447 int r; 8448 8449 r = kvm_set_msr_with_filter(vcpu, msr_index, data); 8450 if (r < 0) 8451 return X86EMUL_UNHANDLEABLE; 8452 8453 if (r) { 8454 if (kvm_msr_user_space(vcpu, msr_index, KVM_EXIT_X86_WRMSR, data, 8455 complete_emulated_msr_access, r)) 8456 return X86EMUL_IO_NEEDED; 8457 8458 trace_kvm_msr_write_ex(msr_index, data); 8459 return X86EMUL_PROPAGATE_FAULT; 8460 } 8461 8462 trace_kvm_msr_write(msr_index, data); 8463 return X86EMUL_CONTINUE; 8464 } 8465 8466 static int emulator_get_msr(struct x86_emulate_ctxt *ctxt, 8467 u32 msr_index, u64 *pdata) 8468 { 8469 return kvm_get_msr(emul_to_vcpu(ctxt), msr_index, pdata); 8470 } 8471 8472 static int emulator_check_rdpmc_early(struct x86_emulate_ctxt *ctxt, u32 pmc) 8473 { 8474 return kvm_pmu_check_rdpmc_early(emul_to_vcpu(ctxt), pmc); 8475 } 8476 8477 static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt, 8478 u32 pmc, u64 *pdata) 8479 { 8480 return kvm_pmu_rdpmc(emul_to_vcpu(ctxt), pmc, pdata); 8481 } 8482 8483 static void emulator_halt(struct x86_emulate_ctxt *ctxt) 8484 { 8485 emul_to_vcpu(ctxt)->arch.halt_request = 1; 8486 } 8487 8488 static int emulator_intercept(struct x86_emulate_ctxt *ctxt, 8489 struct x86_instruction_info *info, 8490 enum x86_intercept_stage stage) 8491 { 8492 return kvm_x86_call(check_intercept)(emul_to_vcpu(ctxt), info, stage, 8493 &ctxt->exception); 8494 } 8495 8496 static bool emulator_get_cpuid(struct x86_emulate_ctxt *ctxt, 8497 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx, 8498 bool exact_only) 8499 { 8500 return kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx, exact_only); 8501 } 8502 8503 static bool emulator_guest_has_movbe(struct x86_emulate_ctxt *ctxt) 8504 { 8505 return guest_cpu_cap_has(emul_to_vcpu(ctxt), X86_FEATURE_MOVBE); 8506 } 8507 8508 static bool emulator_guest_has_fxsr(struct x86_emulate_ctxt *ctxt) 8509 { 8510 return guest_cpu_cap_has(emul_to_vcpu(ctxt), X86_FEATURE_FXSR); 8511 } 8512 8513 static bool emulator_guest_has_rdpid(struct x86_emulate_ctxt *ctxt) 8514 { 8515 return guest_cpu_cap_has(emul_to_vcpu(ctxt), X86_FEATURE_RDPID); 8516 } 8517 8518 static bool emulator_guest_cpuid_is_intel_compatible(struct x86_emulate_ctxt *ctxt) 8519 { 8520 return guest_cpuid_is_intel_compatible(emul_to_vcpu(ctxt)); 8521 } 8522 8523 static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg) 8524 { 8525 return kvm_register_read_raw(emul_to_vcpu(ctxt), reg); 8526 } 8527 8528 static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val) 8529 { 8530 kvm_register_write_raw(emul_to_vcpu(ctxt), reg, val); 8531 } 8532 8533 static void emulator_set_nmi_mask(struct x86_emulate_ctxt *ctxt, bool masked) 8534 { 8535 kvm_x86_call(set_nmi_mask)(emul_to_vcpu(ctxt), masked); 8536 } 8537 8538 static bool emulator_is_smm(struct x86_emulate_ctxt *ctxt) 8539 { 8540 return is_smm(emul_to_vcpu(ctxt)); 8541 } 8542 8543 static bool emulator_is_guest_mode(struct x86_emulate_ctxt *ctxt) 8544 { 8545 return is_guest_mode(emul_to_vcpu(ctxt)); 8546 } 8547 8548 #ifndef CONFIG_KVM_SMM 8549 static int emulator_leave_smm(struct x86_emulate_ctxt *ctxt) 8550 { 8551 WARN_ON_ONCE(1); 8552 return X86EMUL_UNHANDLEABLE; 8553 } 8554 #endif 8555 8556 static void emulator_triple_fault(struct x86_emulate_ctxt *ctxt) 8557 { 8558 kvm_make_request(KVM_REQ_TRIPLE_FAULT, emul_to_vcpu(ctxt)); 8559 } 8560 8561 static int emulator_set_xcr(struct x86_emulate_ctxt *ctxt, u32 index, u64 xcr) 8562 { 8563 return __kvm_set_xcr(emul_to_vcpu(ctxt), index, xcr); 8564 } 8565 8566 static void emulator_vm_bugged(struct x86_emulate_ctxt *ctxt) 8567 { 8568 struct kvm *kvm = emul_to_vcpu(ctxt)->kvm; 8569 8570 if (!kvm->vm_bugged) 8571 kvm_vm_bugged(kvm); 8572 } 8573 8574 static gva_t emulator_get_untagged_addr(struct x86_emulate_ctxt *ctxt, 8575 gva_t addr, unsigned int flags) 8576 { 8577 if (!kvm_x86_ops.get_untagged_addr) 8578 return addr; 8579 8580 return kvm_x86_call(get_untagged_addr)(emul_to_vcpu(ctxt), 8581 addr, flags); 8582 } 8583 8584 static bool emulator_is_canonical_addr(struct x86_emulate_ctxt *ctxt, 8585 gva_t addr, unsigned int flags) 8586 { 8587 return !is_noncanonical_address(addr, emul_to_vcpu(ctxt), flags); 8588 } 8589 8590 static const struct x86_emulate_ops emulate_ops = { 8591 .vm_bugged = emulator_vm_bugged, 8592 .read_gpr = emulator_read_gpr, 8593 .write_gpr = emulator_write_gpr, 8594 .read_std = emulator_read_std, 8595 .write_std = emulator_write_std, 8596 .fetch = kvm_fetch_guest_virt, 8597 .read_emulated = emulator_read_emulated, 8598 .write_emulated = emulator_write_emulated, 8599 .cmpxchg_emulated = emulator_cmpxchg_emulated, 8600 .invlpg = emulator_invlpg, 8601 .pio_in_emulated = emulator_pio_in_emulated, 8602 .pio_out_emulated = emulator_pio_out_emulated, 8603 .get_segment = emulator_get_segment, 8604 .set_segment = emulator_set_segment, 8605 .get_cached_segment_base = emulator_get_cached_segment_base, 8606 .get_gdt = emulator_get_gdt, 8607 .get_idt = emulator_get_idt, 8608 .set_gdt = emulator_set_gdt, 8609 .set_idt = emulator_set_idt, 8610 .get_cr = emulator_get_cr, 8611 .set_cr = emulator_set_cr, 8612 .cpl = emulator_get_cpl, 8613 .get_dr = emulator_get_dr, 8614 .set_dr = emulator_set_dr, 8615 .set_msr_with_filter = emulator_set_msr_with_filter, 8616 .get_msr_with_filter = emulator_get_msr_with_filter, 8617 .get_msr = emulator_get_msr, 8618 .check_rdpmc_early = emulator_check_rdpmc_early, 8619 .read_pmc = emulator_read_pmc, 8620 .halt = emulator_halt, 8621 .wbinvd = emulator_wbinvd, 8622 .fix_hypercall = emulator_fix_hypercall, 8623 .intercept = emulator_intercept, 8624 .get_cpuid = emulator_get_cpuid, 8625 .guest_has_movbe = emulator_guest_has_movbe, 8626 .guest_has_fxsr = emulator_guest_has_fxsr, 8627 .guest_has_rdpid = emulator_guest_has_rdpid, 8628 .guest_cpuid_is_intel_compatible = emulator_guest_cpuid_is_intel_compatible, 8629 .set_nmi_mask = emulator_set_nmi_mask, 8630 .is_smm = emulator_is_smm, 8631 .is_guest_mode = emulator_is_guest_mode, 8632 .leave_smm = emulator_leave_smm, 8633 .triple_fault = emulator_triple_fault, 8634 .set_xcr = emulator_set_xcr, 8635 .get_untagged_addr = emulator_get_untagged_addr, 8636 .is_canonical_addr = emulator_is_canonical_addr, 8637 }; 8638 8639 static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask) 8640 { 8641 u32 int_shadow = kvm_x86_call(get_interrupt_shadow)(vcpu); 8642 /* 8643 * an sti; sti; sequence only disable interrupts for the first 8644 * instruction. So, if the last instruction, be it emulated or 8645 * not, left the system with the INT_STI flag enabled, it 8646 * means that the last instruction is an sti. We should not 8647 * leave the flag on in this case. The same goes for mov ss 8648 */ 8649 if (int_shadow & mask) 8650 mask = 0; 8651 if (unlikely(int_shadow || mask)) { 8652 kvm_x86_call(set_interrupt_shadow)(vcpu, mask); 8653 if (!mask) 8654 kvm_make_request(KVM_REQ_EVENT, vcpu); 8655 } 8656 } 8657 8658 static void inject_emulated_exception(struct kvm_vcpu *vcpu) 8659 { 8660 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt; 8661 8662 if (ctxt->exception.vector == PF_VECTOR) 8663 kvm_inject_emulated_page_fault(vcpu, &ctxt->exception); 8664 else if (ctxt->exception.error_code_valid) 8665 kvm_queue_exception_e(vcpu, ctxt->exception.vector, 8666 ctxt->exception.error_code); 8667 else 8668 kvm_queue_exception(vcpu, ctxt->exception.vector); 8669 } 8670 8671 static struct x86_emulate_ctxt *alloc_emulate_ctxt(struct kvm_vcpu *vcpu) 8672 { 8673 struct x86_emulate_ctxt *ctxt; 8674 8675 ctxt = kmem_cache_zalloc(x86_emulator_cache, GFP_KERNEL_ACCOUNT); 8676 if (!ctxt) { 8677 pr_err("failed to allocate vcpu's emulator\n"); 8678 return NULL; 8679 } 8680 8681 ctxt->vcpu = vcpu; 8682 ctxt->ops = &emulate_ops; 8683 vcpu->arch.emulate_ctxt = ctxt; 8684 8685 return ctxt; 8686 } 8687 8688 static void init_emulate_ctxt(struct kvm_vcpu *vcpu) 8689 { 8690 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt; 8691 int cs_db, cs_l; 8692 8693 kvm_x86_call(get_cs_db_l_bits)(vcpu, &cs_db, &cs_l); 8694 8695 ctxt->gpa_available = false; 8696 ctxt->eflags = kvm_get_rflags(vcpu); 8697 ctxt->tf = (ctxt->eflags & X86_EFLAGS_TF) != 0; 8698 8699 ctxt->eip = kvm_rip_read(vcpu); 8700 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL : 8701 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 : 8702 (cs_l && is_long_mode(vcpu)) ? X86EMUL_MODE_PROT64 : 8703 cs_db ? X86EMUL_MODE_PROT32 : 8704 X86EMUL_MODE_PROT16; 8705 ctxt->interruptibility = 0; 8706 ctxt->have_exception = false; 8707 ctxt->exception.vector = -1; 8708 ctxt->perm_ok = false; 8709 8710 init_decode_cache(ctxt); 8711 vcpu->arch.emulate_regs_need_sync_from_vcpu = false; 8712 } 8713 8714 void kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip) 8715 { 8716 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt; 8717 int ret; 8718 8719 init_emulate_ctxt(vcpu); 8720 8721 ctxt->op_bytes = 2; 8722 ctxt->ad_bytes = 2; 8723 ctxt->_eip = ctxt->eip + inc_eip; 8724 ret = emulate_int_real(ctxt, irq); 8725 8726 if (ret != X86EMUL_CONTINUE) { 8727 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); 8728 } else { 8729 ctxt->eip = ctxt->_eip; 8730 kvm_rip_write(vcpu, ctxt->eip); 8731 kvm_set_rflags(vcpu, ctxt->eflags); 8732 } 8733 } 8734 EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt); 8735 8736 static void prepare_emulation_failure_exit(struct kvm_vcpu *vcpu, u64 *data, 8737 u8 ndata, u8 *insn_bytes, u8 insn_size) 8738 { 8739 struct kvm_run *run = vcpu->run; 8740 u64 info[5]; 8741 u8 info_start; 8742 8743 /* 8744 * Zero the whole array used to retrieve the exit info, as casting to 8745 * u32 for select entries will leave some chunks uninitialized. 8746 */ 8747 memset(&info, 0, sizeof(info)); 8748 8749 kvm_x86_call(get_exit_info)(vcpu, (u32 *)&info[0], &info[1], &info[2], 8750 (u32 *)&info[3], (u32 *)&info[4]); 8751 8752 run->exit_reason = KVM_EXIT_INTERNAL_ERROR; 8753 run->emulation_failure.suberror = KVM_INTERNAL_ERROR_EMULATION; 8754 8755 /* 8756 * There's currently space for 13 entries, but 5 are used for the exit 8757 * reason and info. Restrict to 4 to reduce the maintenance burden 8758 * when expanding kvm_run.emulation_failure in the future. 8759 */ 8760 if (WARN_ON_ONCE(ndata > 4)) 8761 ndata = 4; 8762 8763 /* Always include the flags as a 'data' entry. */ 8764 info_start = 1; 8765 run->emulation_failure.flags = 0; 8766 8767 if (insn_size) { 8768 BUILD_BUG_ON((sizeof(run->emulation_failure.insn_size) + 8769 sizeof(run->emulation_failure.insn_bytes) != 16)); 8770 info_start += 2; 8771 run->emulation_failure.flags |= 8772 KVM_INTERNAL_ERROR_EMULATION_FLAG_INSTRUCTION_BYTES; 8773 run->emulation_failure.insn_size = insn_size; 8774 memset(run->emulation_failure.insn_bytes, 0x90, 8775 sizeof(run->emulation_failure.insn_bytes)); 8776 memcpy(run->emulation_failure.insn_bytes, insn_bytes, insn_size); 8777 } 8778 8779 memcpy(&run->internal.data[info_start], info, sizeof(info)); 8780 memcpy(&run->internal.data[info_start + ARRAY_SIZE(info)], data, 8781 ndata * sizeof(data[0])); 8782 8783 run->emulation_failure.ndata = info_start + ARRAY_SIZE(info) + ndata; 8784 } 8785 8786 static void prepare_emulation_ctxt_failure_exit(struct kvm_vcpu *vcpu) 8787 { 8788 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt; 8789 8790 prepare_emulation_failure_exit(vcpu, NULL, 0, ctxt->fetch.data, 8791 ctxt->fetch.end - ctxt->fetch.data); 8792 } 8793 8794 void __kvm_prepare_emulation_failure_exit(struct kvm_vcpu *vcpu, u64 *data, 8795 u8 ndata) 8796 { 8797 prepare_emulation_failure_exit(vcpu, data, ndata, NULL, 0); 8798 } 8799 EXPORT_SYMBOL_GPL(__kvm_prepare_emulation_failure_exit); 8800 8801 void kvm_prepare_emulation_failure_exit(struct kvm_vcpu *vcpu) 8802 { 8803 __kvm_prepare_emulation_failure_exit(vcpu, NULL, 0); 8804 } 8805 EXPORT_SYMBOL_GPL(kvm_prepare_emulation_failure_exit); 8806 8807 void kvm_prepare_event_vectoring_exit(struct kvm_vcpu *vcpu, gpa_t gpa) 8808 { 8809 u32 reason, intr_info, error_code; 8810 struct kvm_run *run = vcpu->run; 8811 u64 info1, info2; 8812 int ndata = 0; 8813 8814 kvm_x86_call(get_exit_info)(vcpu, &reason, &info1, &info2, 8815 &intr_info, &error_code); 8816 8817 run->internal.data[ndata++] = info2; 8818 run->internal.data[ndata++] = reason; 8819 run->internal.data[ndata++] = info1; 8820 run->internal.data[ndata++] = gpa; 8821 run->internal.data[ndata++] = vcpu->arch.last_vmentry_cpu; 8822 8823 run->exit_reason = KVM_EXIT_INTERNAL_ERROR; 8824 run->internal.suberror = KVM_INTERNAL_ERROR_DELIVERY_EV; 8825 run->internal.ndata = ndata; 8826 } 8827 EXPORT_SYMBOL_GPL(kvm_prepare_event_vectoring_exit); 8828 8829 static int handle_emulation_failure(struct kvm_vcpu *vcpu, int emulation_type) 8830 { 8831 struct kvm *kvm = vcpu->kvm; 8832 8833 ++vcpu->stat.insn_emulation_fail; 8834 trace_kvm_emulate_insn_failed(vcpu); 8835 8836 if (emulation_type & EMULTYPE_VMWARE_GP) { 8837 kvm_queue_exception_e(vcpu, GP_VECTOR, 0); 8838 return 1; 8839 } 8840 8841 if (kvm->arch.exit_on_emulation_error || 8842 (emulation_type & EMULTYPE_SKIP)) { 8843 prepare_emulation_ctxt_failure_exit(vcpu); 8844 return 0; 8845 } 8846 8847 kvm_queue_exception(vcpu, UD_VECTOR); 8848 8849 if (!is_guest_mode(vcpu) && kvm_x86_call(get_cpl)(vcpu) == 0) { 8850 prepare_emulation_ctxt_failure_exit(vcpu); 8851 return 0; 8852 } 8853 8854 return 1; 8855 } 8856 8857 static bool kvm_unprotect_and_retry_on_failure(struct kvm_vcpu *vcpu, 8858 gpa_t cr2_or_gpa, 8859 int emulation_type) 8860 { 8861 if (!(emulation_type & EMULTYPE_ALLOW_RETRY_PF)) 8862 return false; 8863 8864 /* 8865 * If the failed instruction faulted on an access to page tables that 8866 * are used to translate any part of the instruction, KVM can't resolve 8867 * the issue by unprotecting the gfn, as zapping the shadow page will 8868 * result in the instruction taking a !PRESENT page fault and thus put 8869 * the vCPU into an infinite loop of page faults. E.g. KVM will create 8870 * a SPTE and write-protect the gfn to resolve the !PRESENT fault, and 8871 * then zap the SPTE to unprotect the gfn, and then do it all over 8872 * again. Report the error to userspace. 8873 */ 8874 if (emulation_type & EMULTYPE_WRITE_PF_TO_SP) 8875 return false; 8876 8877 /* 8878 * If emulation may have been triggered by a write to a shadowed page 8879 * table, unprotect the gfn (zap any relevant SPTEs) and re-enter the 8880 * guest to let the CPU re-execute the instruction in the hope that the 8881 * CPU can cleanly execute the instruction that KVM failed to emulate. 8882 */ 8883 __kvm_mmu_unprotect_gfn_and_retry(vcpu, cr2_or_gpa, true); 8884 8885 /* 8886 * Retry even if _this_ vCPU didn't unprotect the gfn, as it's possible 8887 * all SPTEs were already zapped by a different task. The alternative 8888 * is to report the error to userspace and likely terminate the guest, 8889 * and the last_retry_{eip,addr} checks will prevent retrying the page 8890 * fault indefinitely, i.e. there's nothing to lose by retrying. 8891 */ 8892 return true; 8893 } 8894 8895 static int complete_emulated_mmio(struct kvm_vcpu *vcpu); 8896 static int complete_emulated_pio(struct kvm_vcpu *vcpu); 8897 8898 static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7, 8899 unsigned long *db) 8900 { 8901 u32 dr6 = 0; 8902 int i; 8903 u32 enable, rwlen; 8904 8905 enable = dr7; 8906 rwlen = dr7 >> 16; 8907 for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4) 8908 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr) 8909 dr6 |= (1 << i); 8910 return dr6; 8911 } 8912 8913 static int kvm_vcpu_do_singlestep(struct kvm_vcpu *vcpu) 8914 { 8915 struct kvm_run *kvm_run = vcpu->run; 8916 8917 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) { 8918 kvm_run->debug.arch.dr6 = DR6_BS | DR6_ACTIVE_LOW; 8919 kvm_run->debug.arch.pc = kvm_get_linear_rip(vcpu); 8920 kvm_run->debug.arch.exception = DB_VECTOR; 8921 kvm_run->exit_reason = KVM_EXIT_DEBUG; 8922 return 0; 8923 } 8924 kvm_queue_exception_p(vcpu, DB_VECTOR, DR6_BS); 8925 return 1; 8926 } 8927 8928 int kvm_skip_emulated_instruction(struct kvm_vcpu *vcpu) 8929 { 8930 unsigned long rflags = kvm_x86_call(get_rflags)(vcpu); 8931 int r; 8932 8933 r = kvm_x86_call(skip_emulated_instruction)(vcpu); 8934 if (unlikely(!r)) 8935 return 0; 8936 8937 kvm_pmu_trigger_event(vcpu, kvm_pmu_eventsel.INSTRUCTIONS_RETIRED); 8938 8939 /* 8940 * rflags is the old, "raw" value of the flags. The new value has 8941 * not been saved yet. 8942 * 8943 * This is correct even for TF set by the guest, because "the 8944 * processor will not generate this exception after the instruction 8945 * that sets the TF flag". 8946 */ 8947 if (unlikely(rflags & X86_EFLAGS_TF)) 8948 r = kvm_vcpu_do_singlestep(vcpu); 8949 return r; 8950 } 8951 EXPORT_SYMBOL_GPL(kvm_skip_emulated_instruction); 8952 8953 static bool kvm_is_code_breakpoint_inhibited(struct kvm_vcpu *vcpu) 8954 { 8955 if (kvm_get_rflags(vcpu) & X86_EFLAGS_RF) 8956 return true; 8957 8958 /* 8959 * Intel compatible CPUs inhibit code #DBs when MOV/POP SS blocking is 8960 * active, but AMD compatible CPUs do not. 8961 */ 8962 if (!guest_cpuid_is_intel_compatible(vcpu)) 8963 return false; 8964 8965 return kvm_x86_call(get_interrupt_shadow)(vcpu) & KVM_X86_SHADOW_INT_MOV_SS; 8966 } 8967 8968 static bool kvm_vcpu_check_code_breakpoint(struct kvm_vcpu *vcpu, 8969 int emulation_type, int *r) 8970 { 8971 WARN_ON_ONCE(emulation_type & EMULTYPE_NO_DECODE); 8972 8973 /* 8974 * Do not check for code breakpoints if hardware has already done the 8975 * checks, as inferred from the emulation type. On NO_DECODE and SKIP, 8976 * the instruction has passed all exception checks, and all intercepted 8977 * exceptions that trigger emulation have lower priority than code 8978 * breakpoints, i.e. the fact that the intercepted exception occurred 8979 * means any code breakpoints have already been serviced. 8980 * 8981 * Note, KVM needs to check for code #DBs on EMULTYPE_TRAP_UD_FORCED as 8982 * hardware has checked the RIP of the magic prefix, but not the RIP of 8983 * the instruction being emulated. The intent of forced emulation is 8984 * to behave as if KVM intercepted the instruction without an exception 8985 * and without a prefix. 8986 */ 8987 if (emulation_type & (EMULTYPE_NO_DECODE | EMULTYPE_SKIP | 8988 EMULTYPE_TRAP_UD | EMULTYPE_VMWARE_GP | EMULTYPE_PF)) 8989 return false; 8990 8991 if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) && 8992 (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) { 8993 struct kvm_run *kvm_run = vcpu->run; 8994 unsigned long eip = kvm_get_linear_rip(vcpu); 8995 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0, 8996 vcpu->arch.guest_debug_dr7, 8997 vcpu->arch.eff_db); 8998 8999 if (dr6 != 0) { 9000 kvm_run->debug.arch.dr6 = dr6 | DR6_ACTIVE_LOW; 9001 kvm_run->debug.arch.pc = eip; 9002 kvm_run->debug.arch.exception = DB_VECTOR; 9003 kvm_run->exit_reason = KVM_EXIT_DEBUG; 9004 *r = 0; 9005 return true; 9006 } 9007 } 9008 9009 if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) && 9010 !kvm_is_code_breakpoint_inhibited(vcpu)) { 9011 unsigned long eip = kvm_get_linear_rip(vcpu); 9012 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0, 9013 vcpu->arch.dr7, 9014 vcpu->arch.db); 9015 9016 if (dr6 != 0) { 9017 kvm_queue_exception_p(vcpu, DB_VECTOR, dr6); 9018 *r = 1; 9019 return true; 9020 } 9021 } 9022 9023 return false; 9024 } 9025 9026 static bool is_vmware_backdoor_opcode(struct x86_emulate_ctxt *ctxt) 9027 { 9028 switch (ctxt->opcode_len) { 9029 case 1: 9030 switch (ctxt->b) { 9031 case 0xe4: /* IN */ 9032 case 0xe5: 9033 case 0xec: 9034 case 0xed: 9035 case 0xe6: /* OUT */ 9036 case 0xe7: 9037 case 0xee: 9038 case 0xef: 9039 case 0x6c: /* INS */ 9040 case 0x6d: 9041 case 0x6e: /* OUTS */ 9042 case 0x6f: 9043 return true; 9044 } 9045 break; 9046 case 2: 9047 switch (ctxt->b) { 9048 case 0x33: /* RDPMC */ 9049 return true; 9050 } 9051 break; 9052 } 9053 9054 return false; 9055 } 9056 9057 /* 9058 * Decode an instruction for emulation. The caller is responsible for handling 9059 * code breakpoints. Note, manually detecting code breakpoints is unnecessary 9060 * (and wrong) when emulating on an intercepted fault-like exception[*], as 9061 * code breakpoints have higher priority and thus have already been done by 9062 * hardware. 9063 * 9064 * [*] Except #MC, which is higher priority, but KVM should never emulate in 9065 * response to a machine check. 9066 */ 9067 int x86_decode_emulated_instruction(struct kvm_vcpu *vcpu, int emulation_type, 9068 void *insn, int insn_len) 9069 { 9070 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt; 9071 int r; 9072 9073 init_emulate_ctxt(vcpu); 9074 9075 r = x86_decode_insn(ctxt, insn, insn_len, emulation_type); 9076 9077 trace_kvm_emulate_insn_start(vcpu); 9078 ++vcpu->stat.insn_emulation; 9079 9080 return r; 9081 } 9082 EXPORT_SYMBOL_GPL(x86_decode_emulated_instruction); 9083 9084 int x86_emulate_instruction(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa, 9085 int emulation_type, void *insn, int insn_len) 9086 { 9087 int r; 9088 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt; 9089 bool writeback = true; 9090 9091 if ((emulation_type & EMULTYPE_ALLOW_RETRY_PF) && 9092 (WARN_ON_ONCE(is_guest_mode(vcpu)) || 9093 WARN_ON_ONCE(!(emulation_type & EMULTYPE_PF)))) 9094 emulation_type &= ~EMULTYPE_ALLOW_RETRY_PF; 9095 9096 r = kvm_check_emulate_insn(vcpu, emulation_type, insn, insn_len); 9097 if (r != X86EMUL_CONTINUE) { 9098 if (r == X86EMUL_RETRY_INSTR || r == X86EMUL_PROPAGATE_FAULT) 9099 return 1; 9100 9101 if (kvm_unprotect_and_retry_on_failure(vcpu, cr2_or_gpa, 9102 emulation_type)) 9103 return 1; 9104 9105 if (r == X86EMUL_UNHANDLEABLE_VECTORING) { 9106 kvm_prepare_event_vectoring_exit(vcpu, cr2_or_gpa); 9107 return 0; 9108 } 9109 9110 WARN_ON_ONCE(r != X86EMUL_UNHANDLEABLE); 9111 return handle_emulation_failure(vcpu, emulation_type); 9112 } 9113 9114 vcpu->arch.l1tf_flush_l1d = true; 9115 9116 if (!(emulation_type & EMULTYPE_NO_DECODE)) { 9117 kvm_clear_exception_queue(vcpu); 9118 9119 /* 9120 * Return immediately if RIP hits a code breakpoint, such #DBs 9121 * are fault-like and are higher priority than any faults on 9122 * the code fetch itself. 9123 */ 9124 if (kvm_vcpu_check_code_breakpoint(vcpu, emulation_type, &r)) 9125 return r; 9126 9127 r = x86_decode_emulated_instruction(vcpu, emulation_type, 9128 insn, insn_len); 9129 if (r != EMULATION_OK) { 9130 if ((emulation_type & EMULTYPE_TRAP_UD) || 9131 (emulation_type & EMULTYPE_TRAP_UD_FORCED)) { 9132 kvm_queue_exception(vcpu, UD_VECTOR); 9133 return 1; 9134 } 9135 if (kvm_unprotect_and_retry_on_failure(vcpu, cr2_or_gpa, 9136 emulation_type)) 9137 return 1; 9138 9139 if (ctxt->have_exception && 9140 !(emulation_type & EMULTYPE_SKIP)) { 9141 /* 9142 * #UD should result in just EMULATION_FAILED, and trap-like 9143 * exception should not be encountered during decode. 9144 */ 9145 WARN_ON_ONCE(ctxt->exception.vector == UD_VECTOR || 9146 exception_type(ctxt->exception.vector) == EXCPT_TRAP); 9147 inject_emulated_exception(vcpu); 9148 return 1; 9149 } 9150 return handle_emulation_failure(vcpu, emulation_type); 9151 } 9152 } 9153 9154 if ((emulation_type & EMULTYPE_VMWARE_GP) && 9155 !is_vmware_backdoor_opcode(ctxt)) { 9156 kvm_queue_exception_e(vcpu, GP_VECTOR, 0); 9157 return 1; 9158 } 9159 9160 /* 9161 * EMULTYPE_SKIP without EMULTYPE_COMPLETE_USER_EXIT is intended for 9162 * use *only* by vendor callbacks for kvm_skip_emulated_instruction(). 9163 * The caller is responsible for updating interruptibility state and 9164 * injecting single-step #DBs. 9165 */ 9166 if (emulation_type & EMULTYPE_SKIP) { 9167 if (ctxt->mode != X86EMUL_MODE_PROT64) 9168 ctxt->eip = (u32)ctxt->_eip; 9169 else 9170 ctxt->eip = ctxt->_eip; 9171 9172 if (emulation_type & EMULTYPE_COMPLETE_USER_EXIT) { 9173 r = 1; 9174 goto writeback; 9175 } 9176 9177 kvm_rip_write(vcpu, ctxt->eip); 9178 if (ctxt->eflags & X86_EFLAGS_RF) 9179 kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF); 9180 return 1; 9181 } 9182 9183 /* 9184 * If emulation was caused by a write-protection #PF on a non-page_table 9185 * writing instruction, try to unprotect the gfn, i.e. zap shadow pages, 9186 * and retry the instruction, as the vCPU is likely no longer using the 9187 * gfn as a page table. 9188 */ 9189 if ((emulation_type & EMULTYPE_ALLOW_RETRY_PF) && 9190 !x86_page_table_writing_insn(ctxt) && 9191 kvm_mmu_unprotect_gfn_and_retry(vcpu, cr2_or_gpa)) 9192 return 1; 9193 9194 /* this is needed for vmware backdoor interface to work since it 9195 changes registers values during IO operation */ 9196 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) { 9197 vcpu->arch.emulate_regs_need_sync_from_vcpu = false; 9198 emulator_invalidate_register_cache(ctxt); 9199 } 9200 9201 restart: 9202 if (emulation_type & EMULTYPE_PF) { 9203 /* Save the faulting GPA (cr2) in the address field */ 9204 ctxt->exception.address = cr2_or_gpa; 9205 9206 /* With shadow page tables, cr2 contains a GVA or nGPA. */ 9207 if (vcpu->arch.mmu->root_role.direct) { 9208 ctxt->gpa_available = true; 9209 ctxt->gpa_val = cr2_or_gpa; 9210 } 9211 } else { 9212 /* Sanitize the address out of an abundance of paranoia. */ 9213 ctxt->exception.address = 0; 9214 } 9215 9216 r = x86_emulate_insn(ctxt); 9217 9218 if (r == EMULATION_INTERCEPTED) 9219 return 1; 9220 9221 if (r == EMULATION_FAILED) { 9222 if (kvm_unprotect_and_retry_on_failure(vcpu, cr2_or_gpa, 9223 emulation_type)) 9224 return 1; 9225 9226 return handle_emulation_failure(vcpu, emulation_type); 9227 } 9228 9229 if (ctxt->have_exception) { 9230 WARN_ON_ONCE(vcpu->mmio_needed && !vcpu->mmio_is_write); 9231 vcpu->mmio_needed = false; 9232 r = 1; 9233 inject_emulated_exception(vcpu); 9234 } else if (vcpu->arch.pio.count) { 9235 if (!vcpu->arch.pio.in) { 9236 /* FIXME: return into emulator if single-stepping. */ 9237 vcpu->arch.pio.count = 0; 9238 } else { 9239 writeback = false; 9240 vcpu->arch.complete_userspace_io = complete_emulated_pio; 9241 } 9242 r = 0; 9243 } else if (vcpu->mmio_needed) { 9244 ++vcpu->stat.mmio_exits; 9245 9246 if (!vcpu->mmio_is_write) 9247 writeback = false; 9248 r = 0; 9249 vcpu->arch.complete_userspace_io = complete_emulated_mmio; 9250 } else if (vcpu->arch.complete_userspace_io) { 9251 writeback = false; 9252 r = 0; 9253 } else if (r == EMULATION_RESTART) 9254 goto restart; 9255 else 9256 r = 1; 9257 9258 writeback: 9259 if (writeback) { 9260 unsigned long rflags = kvm_x86_call(get_rflags)(vcpu); 9261 toggle_interruptibility(vcpu, ctxt->interruptibility); 9262 vcpu->arch.emulate_regs_need_sync_to_vcpu = false; 9263 9264 /* 9265 * Note, EXCPT_DB is assumed to be fault-like as the emulator 9266 * only supports code breakpoints and general detect #DB, both 9267 * of which are fault-like. 9268 */ 9269 if (!ctxt->have_exception || 9270 exception_type(ctxt->exception.vector) == EXCPT_TRAP) { 9271 kvm_pmu_trigger_event(vcpu, kvm_pmu_eventsel.INSTRUCTIONS_RETIRED); 9272 if (ctxt->is_branch) 9273 kvm_pmu_trigger_event(vcpu, kvm_pmu_eventsel.BRANCH_INSTRUCTIONS_RETIRED); 9274 kvm_rip_write(vcpu, ctxt->eip); 9275 if (r && (ctxt->tf || (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP))) 9276 r = kvm_vcpu_do_singlestep(vcpu); 9277 kvm_x86_call(update_emulated_instruction)(vcpu); 9278 __kvm_set_rflags(vcpu, ctxt->eflags); 9279 } 9280 9281 /* 9282 * For STI, interrupts are shadowed; so KVM_REQ_EVENT will 9283 * do nothing, and it will be requested again as soon as 9284 * the shadow expires. But we still need to check here, 9285 * because POPF has no interrupt shadow. 9286 */ 9287 if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF)) 9288 kvm_make_request(KVM_REQ_EVENT, vcpu); 9289 } else 9290 vcpu->arch.emulate_regs_need_sync_to_vcpu = true; 9291 9292 return r; 9293 } 9294 9295 int kvm_emulate_instruction(struct kvm_vcpu *vcpu, int emulation_type) 9296 { 9297 return x86_emulate_instruction(vcpu, 0, emulation_type, NULL, 0); 9298 } 9299 EXPORT_SYMBOL_GPL(kvm_emulate_instruction); 9300 9301 int kvm_emulate_instruction_from_buffer(struct kvm_vcpu *vcpu, 9302 void *insn, int insn_len) 9303 { 9304 return x86_emulate_instruction(vcpu, 0, 0, insn, insn_len); 9305 } 9306 EXPORT_SYMBOL_GPL(kvm_emulate_instruction_from_buffer); 9307 9308 static int complete_fast_pio_out_port_0x7e(struct kvm_vcpu *vcpu) 9309 { 9310 vcpu->arch.pio.count = 0; 9311 return 1; 9312 } 9313 9314 static int complete_fast_pio_out(struct kvm_vcpu *vcpu) 9315 { 9316 vcpu->arch.pio.count = 0; 9317 9318 if (unlikely(!kvm_is_linear_rip(vcpu, vcpu->arch.pio.linear_rip))) 9319 return 1; 9320 9321 return kvm_skip_emulated_instruction(vcpu); 9322 } 9323 9324 static int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, 9325 unsigned short port) 9326 { 9327 unsigned long val = kvm_rax_read(vcpu); 9328 int ret = emulator_pio_out(vcpu, size, port, &val, 1); 9329 9330 if (ret) 9331 return ret; 9332 9333 /* 9334 * Workaround userspace that relies on old KVM behavior of %rip being 9335 * incremented prior to exiting to userspace to handle "OUT 0x7e". 9336 */ 9337 if (port == 0x7e && 9338 kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_OUT_7E_INC_RIP)) { 9339 vcpu->arch.complete_userspace_io = 9340 complete_fast_pio_out_port_0x7e; 9341 kvm_skip_emulated_instruction(vcpu); 9342 } else { 9343 vcpu->arch.pio.linear_rip = kvm_get_linear_rip(vcpu); 9344 vcpu->arch.complete_userspace_io = complete_fast_pio_out; 9345 } 9346 return 0; 9347 } 9348 9349 static int complete_fast_pio_in(struct kvm_vcpu *vcpu) 9350 { 9351 unsigned long val; 9352 9353 /* We should only ever be called with arch.pio.count equal to 1 */ 9354 BUG_ON(vcpu->arch.pio.count != 1); 9355 9356 if (unlikely(!kvm_is_linear_rip(vcpu, vcpu->arch.pio.linear_rip))) { 9357 vcpu->arch.pio.count = 0; 9358 return 1; 9359 } 9360 9361 /* For size less than 4 we merge, else we zero extend */ 9362 val = (vcpu->arch.pio.size < 4) ? kvm_rax_read(vcpu) : 0; 9363 9364 complete_emulator_pio_in(vcpu, &val); 9365 kvm_rax_write(vcpu, val); 9366 9367 return kvm_skip_emulated_instruction(vcpu); 9368 } 9369 9370 static int kvm_fast_pio_in(struct kvm_vcpu *vcpu, int size, 9371 unsigned short port) 9372 { 9373 unsigned long val; 9374 int ret; 9375 9376 /* For size less than 4 we merge, else we zero extend */ 9377 val = (size < 4) ? kvm_rax_read(vcpu) : 0; 9378 9379 ret = emulator_pio_in(vcpu, size, port, &val, 1); 9380 if (ret) { 9381 kvm_rax_write(vcpu, val); 9382 return ret; 9383 } 9384 9385 vcpu->arch.pio.linear_rip = kvm_get_linear_rip(vcpu); 9386 vcpu->arch.complete_userspace_io = complete_fast_pio_in; 9387 9388 return 0; 9389 } 9390 9391 int kvm_fast_pio(struct kvm_vcpu *vcpu, int size, unsigned short port, int in) 9392 { 9393 int ret; 9394 9395 if (in) 9396 ret = kvm_fast_pio_in(vcpu, size, port); 9397 else 9398 ret = kvm_fast_pio_out(vcpu, size, port); 9399 return ret && kvm_skip_emulated_instruction(vcpu); 9400 } 9401 EXPORT_SYMBOL_GPL(kvm_fast_pio); 9402 9403 static int kvmclock_cpu_down_prep(unsigned int cpu) 9404 { 9405 __this_cpu_write(cpu_tsc_khz, 0); 9406 return 0; 9407 } 9408 9409 static void tsc_khz_changed(void *data) 9410 { 9411 struct cpufreq_freqs *freq = data; 9412 unsigned long khz; 9413 9414 WARN_ON_ONCE(boot_cpu_has(X86_FEATURE_CONSTANT_TSC)); 9415 9416 if (data) 9417 khz = freq->new; 9418 else 9419 khz = cpufreq_quick_get(raw_smp_processor_id()); 9420 if (!khz) 9421 khz = tsc_khz; 9422 __this_cpu_write(cpu_tsc_khz, khz); 9423 } 9424 9425 #ifdef CONFIG_X86_64 9426 static void kvm_hyperv_tsc_notifier(void) 9427 { 9428 struct kvm *kvm; 9429 int cpu; 9430 9431 mutex_lock(&kvm_lock); 9432 list_for_each_entry(kvm, &vm_list, vm_list) 9433 kvm_make_mclock_inprogress_request(kvm); 9434 9435 /* no guest entries from this point */ 9436 hyperv_stop_tsc_emulation(); 9437 9438 /* TSC frequency always matches when on Hyper-V */ 9439 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) { 9440 for_each_present_cpu(cpu) 9441 per_cpu(cpu_tsc_khz, cpu) = tsc_khz; 9442 } 9443 kvm_caps.max_guest_tsc_khz = tsc_khz; 9444 9445 list_for_each_entry(kvm, &vm_list, vm_list) { 9446 __kvm_start_pvclock_update(kvm); 9447 pvclock_update_vm_gtod_copy(kvm); 9448 kvm_end_pvclock_update(kvm); 9449 } 9450 9451 mutex_unlock(&kvm_lock); 9452 } 9453 #endif 9454 9455 static void __kvmclock_cpufreq_notifier(struct cpufreq_freqs *freq, int cpu) 9456 { 9457 struct kvm *kvm; 9458 struct kvm_vcpu *vcpu; 9459 int send_ipi = 0; 9460 unsigned long i; 9461 9462 /* 9463 * We allow guests to temporarily run on slowing clocks, 9464 * provided we notify them after, or to run on accelerating 9465 * clocks, provided we notify them before. Thus time never 9466 * goes backwards. 9467 * 9468 * However, we have a problem. We can't atomically update 9469 * the frequency of a given CPU from this function; it is 9470 * merely a notifier, which can be called from any CPU. 9471 * Changing the TSC frequency at arbitrary points in time 9472 * requires a recomputation of local variables related to 9473 * the TSC for each VCPU. We must flag these local variables 9474 * to be updated and be sure the update takes place with the 9475 * new frequency before any guests proceed. 9476 * 9477 * Unfortunately, the combination of hotplug CPU and frequency 9478 * change creates an intractable locking scenario; the order 9479 * of when these callouts happen is undefined with respect to 9480 * CPU hotplug, and they can race with each other. As such, 9481 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is 9482 * undefined; you can actually have a CPU frequency change take 9483 * place in between the computation of X and the setting of the 9484 * variable. To protect against this problem, all updates of 9485 * the per_cpu tsc_khz variable are done in an interrupt 9486 * protected IPI, and all callers wishing to update the value 9487 * must wait for a synchronous IPI to complete (which is trivial 9488 * if the caller is on the CPU already). This establishes the 9489 * necessary total order on variable updates. 9490 * 9491 * Note that because a guest time update may take place 9492 * anytime after the setting of the VCPU's request bit, the 9493 * correct TSC value must be set before the request. However, 9494 * to ensure the update actually makes it to any guest which 9495 * starts running in hardware virtualization between the set 9496 * and the acquisition of the spinlock, we must also ping the 9497 * CPU after setting the request bit. 9498 * 9499 */ 9500 9501 smp_call_function_single(cpu, tsc_khz_changed, freq, 1); 9502 9503 mutex_lock(&kvm_lock); 9504 list_for_each_entry(kvm, &vm_list, vm_list) { 9505 kvm_for_each_vcpu(i, vcpu, kvm) { 9506 if (vcpu->cpu != cpu) 9507 continue; 9508 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 9509 if (vcpu->cpu != raw_smp_processor_id()) 9510 send_ipi = 1; 9511 } 9512 } 9513 mutex_unlock(&kvm_lock); 9514 9515 if (freq->old < freq->new && send_ipi) { 9516 /* 9517 * We upscale the frequency. Must make the guest 9518 * doesn't see old kvmclock values while running with 9519 * the new frequency, otherwise we risk the guest sees 9520 * time go backwards. 9521 * 9522 * In case we update the frequency for another cpu 9523 * (which might be in guest context) send an interrupt 9524 * to kick the cpu out of guest context. Next time 9525 * guest context is entered kvmclock will be updated, 9526 * so the guest will not see stale values. 9527 */ 9528 smp_call_function_single(cpu, tsc_khz_changed, freq, 1); 9529 } 9530 } 9531 9532 static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val, 9533 void *data) 9534 { 9535 struct cpufreq_freqs *freq = data; 9536 int cpu; 9537 9538 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new) 9539 return 0; 9540 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new) 9541 return 0; 9542 9543 for_each_cpu(cpu, freq->policy->cpus) 9544 __kvmclock_cpufreq_notifier(freq, cpu); 9545 9546 return 0; 9547 } 9548 9549 static struct notifier_block kvmclock_cpufreq_notifier_block = { 9550 .notifier_call = kvmclock_cpufreq_notifier 9551 }; 9552 9553 static int kvmclock_cpu_online(unsigned int cpu) 9554 { 9555 tsc_khz_changed(NULL); 9556 return 0; 9557 } 9558 9559 static void kvm_timer_init(void) 9560 { 9561 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) { 9562 max_tsc_khz = tsc_khz; 9563 9564 if (IS_ENABLED(CONFIG_CPU_FREQ)) { 9565 struct cpufreq_policy *policy; 9566 int cpu; 9567 9568 cpu = get_cpu(); 9569 policy = cpufreq_cpu_get(cpu); 9570 if (policy) { 9571 if (policy->cpuinfo.max_freq) 9572 max_tsc_khz = policy->cpuinfo.max_freq; 9573 cpufreq_cpu_put(policy); 9574 } 9575 put_cpu(); 9576 } 9577 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block, 9578 CPUFREQ_TRANSITION_NOTIFIER); 9579 9580 cpuhp_setup_state(CPUHP_AP_X86_KVM_CLK_ONLINE, "x86/kvm/clk:online", 9581 kvmclock_cpu_online, kvmclock_cpu_down_prep); 9582 } 9583 } 9584 9585 #ifdef CONFIG_X86_64 9586 static void pvclock_gtod_update_fn(struct work_struct *work) 9587 { 9588 struct kvm *kvm; 9589 struct kvm_vcpu *vcpu; 9590 unsigned long i; 9591 9592 mutex_lock(&kvm_lock); 9593 list_for_each_entry(kvm, &vm_list, vm_list) 9594 kvm_for_each_vcpu(i, vcpu, kvm) 9595 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu); 9596 atomic_set(&kvm_guest_has_master_clock, 0); 9597 mutex_unlock(&kvm_lock); 9598 } 9599 9600 static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn); 9601 9602 /* 9603 * Indirection to move queue_work() out of the tk_core.seq write held 9604 * region to prevent possible deadlocks against time accessors which 9605 * are invoked with work related locks held. 9606 */ 9607 static void pvclock_irq_work_fn(struct irq_work *w) 9608 { 9609 queue_work(system_long_wq, &pvclock_gtod_work); 9610 } 9611 9612 static DEFINE_IRQ_WORK(pvclock_irq_work, pvclock_irq_work_fn); 9613 9614 /* 9615 * Notification about pvclock gtod data update. 9616 */ 9617 static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused, 9618 void *priv) 9619 { 9620 struct pvclock_gtod_data *gtod = &pvclock_gtod_data; 9621 struct timekeeper *tk = priv; 9622 9623 update_pvclock_gtod(tk); 9624 9625 /* 9626 * Disable master clock if host does not trust, or does not use, 9627 * TSC based clocksource. Delegate queue_work() to irq_work as 9628 * this is invoked with tk_core.seq write held. 9629 */ 9630 if (!gtod_is_based_on_tsc(gtod->clock.vclock_mode) && 9631 atomic_read(&kvm_guest_has_master_clock) != 0) 9632 irq_work_queue(&pvclock_irq_work); 9633 return 0; 9634 } 9635 9636 static struct notifier_block pvclock_gtod_notifier = { 9637 .notifier_call = pvclock_gtod_notify, 9638 }; 9639 #endif 9640 9641 static inline void kvm_ops_update(struct kvm_x86_init_ops *ops) 9642 { 9643 memcpy(&kvm_x86_ops, ops->runtime_ops, sizeof(kvm_x86_ops)); 9644 9645 #define __KVM_X86_OP(func) \ 9646 static_call_update(kvm_x86_##func, kvm_x86_ops.func); 9647 #define KVM_X86_OP(func) \ 9648 WARN_ON(!kvm_x86_ops.func); __KVM_X86_OP(func) 9649 #define KVM_X86_OP_OPTIONAL __KVM_X86_OP 9650 #define KVM_X86_OP_OPTIONAL_RET0(func) \ 9651 static_call_update(kvm_x86_##func, (void *)kvm_x86_ops.func ? : \ 9652 (void *)__static_call_return0); 9653 #include <asm/kvm-x86-ops.h> 9654 #undef __KVM_X86_OP 9655 9656 kvm_pmu_ops_update(ops->pmu_ops); 9657 } 9658 9659 static int kvm_x86_check_processor_compatibility(void) 9660 { 9661 int cpu = smp_processor_id(); 9662 struct cpuinfo_x86 *c = &cpu_data(cpu); 9663 9664 /* 9665 * Compatibility checks are done when loading KVM and when enabling 9666 * hardware, e.g. during CPU hotplug, to ensure all online CPUs are 9667 * compatible, i.e. KVM should never perform a compatibility check on 9668 * an offline CPU. 9669 */ 9670 WARN_ON(!cpu_online(cpu)); 9671 9672 if (__cr4_reserved_bits(cpu_has, c) != 9673 __cr4_reserved_bits(cpu_has, &boot_cpu_data)) 9674 return -EIO; 9675 9676 return kvm_x86_call(check_processor_compatibility)(); 9677 } 9678 9679 static void kvm_x86_check_cpu_compat(void *ret) 9680 { 9681 *(int *)ret = kvm_x86_check_processor_compatibility(); 9682 } 9683 9684 int kvm_x86_vendor_init(struct kvm_x86_init_ops *ops) 9685 { 9686 u64 host_pat; 9687 int r, cpu; 9688 9689 guard(mutex)(&vendor_module_lock); 9690 9691 if (kvm_x86_ops.enable_virtualization_cpu) { 9692 pr_err("already loaded vendor module '%s'\n", kvm_x86_ops.name); 9693 return -EEXIST; 9694 } 9695 9696 /* 9697 * KVM explicitly assumes that the guest has an FPU and 9698 * FXSAVE/FXRSTOR. For example, the KVM_GET_FPU explicitly casts the 9699 * vCPU's FPU state as a fxregs_state struct. 9700 */ 9701 if (!boot_cpu_has(X86_FEATURE_FPU) || !boot_cpu_has(X86_FEATURE_FXSR)) { 9702 pr_err("inadequate fpu\n"); 9703 return -EOPNOTSUPP; 9704 } 9705 9706 if (IS_ENABLED(CONFIG_PREEMPT_RT) && !boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) { 9707 pr_err("RT requires X86_FEATURE_CONSTANT_TSC\n"); 9708 return -EOPNOTSUPP; 9709 } 9710 9711 /* 9712 * KVM assumes that PAT entry '0' encodes WB memtype and simply zeroes 9713 * the PAT bits in SPTEs. Bail if PAT[0] is programmed to something 9714 * other than WB. Note, EPT doesn't utilize the PAT, but don't bother 9715 * with an exception. PAT[0] is set to WB on RESET and also by the 9716 * kernel, i.e. failure indicates a kernel bug or broken firmware. 9717 */ 9718 if (rdmsrl_safe(MSR_IA32_CR_PAT, &host_pat) || 9719 (host_pat & GENMASK(2, 0)) != 6) { 9720 pr_err("host PAT[0] is not WB\n"); 9721 return -EIO; 9722 } 9723 9724 memset(&kvm_caps, 0, sizeof(kvm_caps)); 9725 9726 x86_emulator_cache = kvm_alloc_emulator_cache(); 9727 if (!x86_emulator_cache) { 9728 pr_err("failed to allocate cache for x86 emulator\n"); 9729 return -ENOMEM; 9730 } 9731 9732 user_return_msrs = alloc_percpu(struct kvm_user_return_msrs); 9733 if (!user_return_msrs) { 9734 pr_err("failed to allocate percpu kvm_user_return_msrs\n"); 9735 r = -ENOMEM; 9736 goto out_free_x86_emulator_cache; 9737 } 9738 kvm_nr_uret_msrs = 0; 9739 9740 r = kvm_mmu_vendor_module_init(); 9741 if (r) 9742 goto out_free_percpu; 9743 9744 kvm_caps.supported_vm_types = BIT(KVM_X86_DEFAULT_VM); 9745 kvm_caps.supported_mce_cap = MCG_CTL_P | MCG_SER_P; 9746 9747 if (boot_cpu_has(X86_FEATURE_XSAVE)) { 9748 kvm_host.xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK); 9749 kvm_caps.supported_xcr0 = kvm_host.xcr0 & KVM_SUPPORTED_XCR0; 9750 } 9751 9752 rdmsrl_safe(MSR_EFER, &kvm_host.efer); 9753 9754 if (boot_cpu_has(X86_FEATURE_XSAVES)) 9755 rdmsrl(MSR_IA32_XSS, kvm_host.xss); 9756 9757 kvm_init_pmu_capability(ops->pmu_ops); 9758 9759 if (boot_cpu_has(X86_FEATURE_ARCH_CAPABILITIES)) 9760 rdmsrl(MSR_IA32_ARCH_CAPABILITIES, kvm_host.arch_capabilities); 9761 9762 r = ops->hardware_setup(); 9763 if (r != 0) 9764 goto out_mmu_exit; 9765 9766 kvm_ops_update(ops); 9767 9768 for_each_online_cpu(cpu) { 9769 smp_call_function_single(cpu, kvm_x86_check_cpu_compat, &r, 1); 9770 if (r < 0) 9771 goto out_unwind_ops; 9772 } 9773 9774 /* 9775 * Point of no return! DO NOT add error paths below this point unless 9776 * absolutely necessary, as most operations from this point forward 9777 * require unwinding. 9778 */ 9779 kvm_timer_init(); 9780 9781 if (pi_inject_timer == -1) 9782 pi_inject_timer = housekeeping_enabled(HK_TYPE_TIMER); 9783 #ifdef CONFIG_X86_64 9784 pvclock_gtod_register_notifier(&pvclock_gtod_notifier); 9785 9786 if (hypervisor_is_type(X86_HYPER_MS_HYPERV)) 9787 set_hv_tscchange_cb(kvm_hyperv_tsc_notifier); 9788 #endif 9789 9790 kvm_register_perf_callbacks(ops->handle_intel_pt_intr); 9791 9792 if (IS_ENABLED(CONFIG_KVM_SW_PROTECTED_VM) && tdp_mmu_enabled) 9793 kvm_caps.supported_vm_types |= BIT(KVM_X86_SW_PROTECTED_VM); 9794 9795 if (!kvm_cpu_cap_has(X86_FEATURE_XSAVES)) 9796 kvm_caps.supported_xss = 0; 9797 9798 if (kvm_caps.has_tsc_control) { 9799 /* 9800 * Make sure the user can only configure tsc_khz values that 9801 * fit into a signed integer. 9802 * A min value is not calculated because it will always 9803 * be 1 on all machines. 9804 */ 9805 u64 max = min(0x7fffffffULL, 9806 __scale_tsc(kvm_caps.max_tsc_scaling_ratio, tsc_khz)); 9807 kvm_caps.max_guest_tsc_khz = max; 9808 } 9809 kvm_caps.default_tsc_scaling_ratio = 1ULL << kvm_caps.tsc_scaling_ratio_frac_bits; 9810 kvm_init_msr_lists(); 9811 return 0; 9812 9813 out_unwind_ops: 9814 kvm_x86_ops.enable_virtualization_cpu = NULL; 9815 kvm_x86_call(hardware_unsetup)(); 9816 out_mmu_exit: 9817 kvm_mmu_vendor_module_exit(); 9818 out_free_percpu: 9819 free_percpu(user_return_msrs); 9820 out_free_x86_emulator_cache: 9821 kmem_cache_destroy(x86_emulator_cache); 9822 return r; 9823 } 9824 EXPORT_SYMBOL_GPL(kvm_x86_vendor_init); 9825 9826 void kvm_x86_vendor_exit(void) 9827 { 9828 kvm_unregister_perf_callbacks(); 9829 9830 #ifdef CONFIG_X86_64 9831 if (hypervisor_is_type(X86_HYPER_MS_HYPERV)) 9832 clear_hv_tscchange_cb(); 9833 #endif 9834 kvm_lapic_exit(); 9835 9836 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) { 9837 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block, 9838 CPUFREQ_TRANSITION_NOTIFIER); 9839 cpuhp_remove_state_nocalls(CPUHP_AP_X86_KVM_CLK_ONLINE); 9840 } 9841 #ifdef CONFIG_X86_64 9842 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier); 9843 irq_work_sync(&pvclock_irq_work); 9844 cancel_work_sync(&pvclock_gtod_work); 9845 #endif 9846 kvm_x86_call(hardware_unsetup)(); 9847 kvm_mmu_vendor_module_exit(); 9848 free_percpu(user_return_msrs); 9849 kmem_cache_destroy(x86_emulator_cache); 9850 #ifdef CONFIG_KVM_XEN 9851 static_key_deferred_flush(&kvm_xen_enabled); 9852 WARN_ON(static_branch_unlikely(&kvm_xen_enabled.key)); 9853 #endif 9854 mutex_lock(&vendor_module_lock); 9855 kvm_x86_ops.enable_virtualization_cpu = NULL; 9856 mutex_unlock(&vendor_module_lock); 9857 } 9858 EXPORT_SYMBOL_GPL(kvm_x86_vendor_exit); 9859 9860 #ifdef CONFIG_X86_64 9861 static int kvm_pv_clock_pairing(struct kvm_vcpu *vcpu, gpa_t paddr, 9862 unsigned long clock_type) 9863 { 9864 struct kvm_clock_pairing clock_pairing; 9865 struct timespec64 ts; 9866 u64 cycle; 9867 int ret; 9868 9869 if (clock_type != KVM_CLOCK_PAIRING_WALLCLOCK) 9870 return -KVM_EOPNOTSUPP; 9871 9872 /* 9873 * When tsc is in permanent catchup mode guests won't be able to use 9874 * pvclock_read_retry loop to get consistent view of pvclock 9875 */ 9876 if (vcpu->arch.tsc_always_catchup) 9877 return -KVM_EOPNOTSUPP; 9878 9879 if (!kvm_get_walltime_and_clockread(&ts, &cycle)) 9880 return -KVM_EOPNOTSUPP; 9881 9882 clock_pairing.sec = ts.tv_sec; 9883 clock_pairing.nsec = ts.tv_nsec; 9884 clock_pairing.tsc = kvm_read_l1_tsc(vcpu, cycle); 9885 clock_pairing.flags = 0; 9886 memset(&clock_pairing.pad, 0, sizeof(clock_pairing.pad)); 9887 9888 ret = 0; 9889 if (kvm_write_guest(vcpu->kvm, paddr, &clock_pairing, 9890 sizeof(struct kvm_clock_pairing))) 9891 ret = -KVM_EFAULT; 9892 9893 return ret; 9894 } 9895 #endif 9896 9897 /* 9898 * kvm_pv_kick_cpu_op: Kick a vcpu. 9899 * 9900 * @apicid - apicid of vcpu to be kicked. 9901 */ 9902 static void kvm_pv_kick_cpu_op(struct kvm *kvm, int apicid) 9903 { 9904 /* 9905 * All other fields are unused for APIC_DM_REMRD, but may be consumed by 9906 * common code, e.g. for tracing. Defer initialization to the compiler. 9907 */ 9908 struct kvm_lapic_irq lapic_irq = { 9909 .delivery_mode = APIC_DM_REMRD, 9910 .dest_mode = APIC_DEST_PHYSICAL, 9911 .shorthand = APIC_DEST_NOSHORT, 9912 .dest_id = apicid, 9913 }; 9914 9915 kvm_irq_delivery_to_apic(kvm, NULL, &lapic_irq, NULL); 9916 } 9917 9918 bool kvm_apicv_activated(struct kvm *kvm) 9919 { 9920 return (READ_ONCE(kvm->arch.apicv_inhibit_reasons) == 0); 9921 } 9922 EXPORT_SYMBOL_GPL(kvm_apicv_activated); 9923 9924 bool kvm_vcpu_apicv_activated(struct kvm_vcpu *vcpu) 9925 { 9926 ulong vm_reasons = READ_ONCE(vcpu->kvm->arch.apicv_inhibit_reasons); 9927 ulong vcpu_reasons = 9928 kvm_x86_call(vcpu_get_apicv_inhibit_reasons)(vcpu); 9929 9930 return (vm_reasons | vcpu_reasons) == 0; 9931 } 9932 EXPORT_SYMBOL_GPL(kvm_vcpu_apicv_activated); 9933 9934 static void set_or_clear_apicv_inhibit(unsigned long *inhibits, 9935 enum kvm_apicv_inhibit reason, bool set) 9936 { 9937 const struct trace_print_flags apicv_inhibits[] = { APICV_INHIBIT_REASONS }; 9938 9939 BUILD_BUG_ON(ARRAY_SIZE(apicv_inhibits) != NR_APICV_INHIBIT_REASONS); 9940 9941 if (set) 9942 __set_bit(reason, inhibits); 9943 else 9944 __clear_bit(reason, inhibits); 9945 9946 trace_kvm_apicv_inhibit_changed(reason, set, *inhibits); 9947 } 9948 9949 static void kvm_apicv_init(struct kvm *kvm) 9950 { 9951 enum kvm_apicv_inhibit reason = enable_apicv ? APICV_INHIBIT_REASON_ABSENT : 9952 APICV_INHIBIT_REASON_DISABLED; 9953 9954 set_or_clear_apicv_inhibit(&kvm->arch.apicv_inhibit_reasons, reason, true); 9955 9956 init_rwsem(&kvm->arch.apicv_update_lock); 9957 } 9958 9959 static void kvm_sched_yield(struct kvm_vcpu *vcpu, unsigned long dest_id) 9960 { 9961 struct kvm_vcpu *target = NULL; 9962 struct kvm_apic_map *map; 9963 9964 vcpu->stat.directed_yield_attempted++; 9965 9966 if (single_task_running()) 9967 goto no_yield; 9968 9969 rcu_read_lock(); 9970 map = rcu_dereference(vcpu->kvm->arch.apic_map); 9971 9972 if (likely(map) && dest_id <= map->max_apic_id && map->phys_map[dest_id]) 9973 target = map->phys_map[dest_id]->vcpu; 9974 9975 rcu_read_unlock(); 9976 9977 if (!target || !READ_ONCE(target->ready)) 9978 goto no_yield; 9979 9980 /* Ignore requests to yield to self */ 9981 if (vcpu == target) 9982 goto no_yield; 9983 9984 if (kvm_vcpu_yield_to(target) <= 0) 9985 goto no_yield; 9986 9987 vcpu->stat.directed_yield_successful++; 9988 9989 no_yield: 9990 return; 9991 } 9992 9993 static int complete_hypercall_exit(struct kvm_vcpu *vcpu) 9994 { 9995 u64 ret = vcpu->run->hypercall.ret; 9996 9997 if (!is_64_bit_hypercall(vcpu)) 9998 ret = (u32)ret; 9999 kvm_rax_write(vcpu, ret); 10000 return kvm_skip_emulated_instruction(vcpu); 10001 } 10002 10003 int ____kvm_emulate_hypercall(struct kvm_vcpu *vcpu, unsigned long nr, 10004 unsigned long a0, unsigned long a1, 10005 unsigned long a2, unsigned long a3, 10006 int op_64_bit, int cpl, 10007 int (*complete_hypercall)(struct kvm_vcpu *)) 10008 { 10009 unsigned long ret; 10010 10011 ++vcpu->stat.hypercalls; 10012 10013 trace_kvm_hypercall(nr, a0, a1, a2, a3); 10014 10015 if (!op_64_bit) { 10016 nr &= 0xFFFFFFFF; 10017 a0 &= 0xFFFFFFFF; 10018 a1 &= 0xFFFFFFFF; 10019 a2 &= 0xFFFFFFFF; 10020 a3 &= 0xFFFFFFFF; 10021 } 10022 10023 if (cpl) { 10024 ret = -KVM_EPERM; 10025 goto out; 10026 } 10027 10028 ret = -KVM_ENOSYS; 10029 10030 switch (nr) { 10031 case KVM_HC_VAPIC_POLL_IRQ: 10032 ret = 0; 10033 break; 10034 case KVM_HC_KICK_CPU: 10035 if (!guest_pv_has(vcpu, KVM_FEATURE_PV_UNHALT)) 10036 break; 10037 10038 kvm_pv_kick_cpu_op(vcpu->kvm, a1); 10039 kvm_sched_yield(vcpu, a1); 10040 ret = 0; 10041 break; 10042 #ifdef CONFIG_X86_64 10043 case KVM_HC_CLOCK_PAIRING: 10044 ret = kvm_pv_clock_pairing(vcpu, a0, a1); 10045 break; 10046 #endif 10047 case KVM_HC_SEND_IPI: 10048 if (!guest_pv_has(vcpu, KVM_FEATURE_PV_SEND_IPI)) 10049 break; 10050 10051 ret = kvm_pv_send_ipi(vcpu->kvm, a0, a1, a2, a3, op_64_bit); 10052 break; 10053 case KVM_HC_SCHED_YIELD: 10054 if (!guest_pv_has(vcpu, KVM_FEATURE_PV_SCHED_YIELD)) 10055 break; 10056 10057 kvm_sched_yield(vcpu, a0); 10058 ret = 0; 10059 break; 10060 case KVM_HC_MAP_GPA_RANGE: { 10061 u64 gpa = a0, npages = a1, attrs = a2; 10062 10063 ret = -KVM_ENOSYS; 10064 if (!user_exit_on_hypercall(vcpu->kvm, KVM_HC_MAP_GPA_RANGE)) 10065 break; 10066 10067 if (!PAGE_ALIGNED(gpa) || !npages || 10068 gpa_to_gfn(gpa) + npages <= gpa_to_gfn(gpa)) { 10069 ret = -KVM_EINVAL; 10070 break; 10071 } 10072 10073 vcpu->run->exit_reason = KVM_EXIT_HYPERCALL; 10074 vcpu->run->hypercall.nr = KVM_HC_MAP_GPA_RANGE; 10075 /* 10076 * In principle this should have been -KVM_ENOSYS, but userspace (QEMU <=9.2) 10077 * assumed that vcpu->run->hypercall.ret is never changed by KVM and thus that 10078 * it was always zero on KVM_EXIT_HYPERCALL. Since KVM is now overwriting 10079 * vcpu->run->hypercall.ret, ensuring that it is zero to not break QEMU. 10080 */ 10081 vcpu->run->hypercall.ret = 0; 10082 vcpu->run->hypercall.args[0] = gpa; 10083 vcpu->run->hypercall.args[1] = npages; 10084 vcpu->run->hypercall.args[2] = attrs; 10085 vcpu->run->hypercall.flags = 0; 10086 if (op_64_bit) 10087 vcpu->run->hypercall.flags |= KVM_EXIT_HYPERCALL_LONG_MODE; 10088 10089 WARN_ON_ONCE(vcpu->run->hypercall.flags & KVM_EXIT_HYPERCALL_MBZ); 10090 vcpu->arch.complete_userspace_io = complete_hypercall; 10091 return 0; 10092 } 10093 default: 10094 ret = -KVM_ENOSYS; 10095 break; 10096 } 10097 10098 out: 10099 vcpu->run->hypercall.ret = ret; 10100 return 1; 10101 } 10102 EXPORT_SYMBOL_GPL(____kvm_emulate_hypercall); 10103 10104 int kvm_emulate_hypercall(struct kvm_vcpu *vcpu) 10105 { 10106 if (kvm_xen_hypercall_enabled(vcpu->kvm)) 10107 return kvm_xen_hypercall(vcpu); 10108 10109 if (kvm_hv_hypercall_enabled(vcpu)) 10110 return kvm_hv_hypercall(vcpu); 10111 10112 return __kvm_emulate_hypercall(vcpu, rax, rbx, rcx, rdx, rsi, 10113 is_64_bit_hypercall(vcpu), 10114 kvm_x86_call(get_cpl)(vcpu), 10115 complete_hypercall_exit); 10116 } 10117 EXPORT_SYMBOL_GPL(kvm_emulate_hypercall); 10118 10119 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt) 10120 { 10121 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 10122 char instruction[3]; 10123 unsigned long rip = kvm_rip_read(vcpu); 10124 10125 /* 10126 * If the quirk is disabled, synthesize a #UD and let the guest pick up 10127 * the pieces. 10128 */ 10129 if (!kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_FIX_HYPERCALL_INSN)) { 10130 ctxt->exception.error_code_valid = false; 10131 ctxt->exception.vector = UD_VECTOR; 10132 ctxt->have_exception = true; 10133 return X86EMUL_PROPAGATE_FAULT; 10134 } 10135 10136 kvm_x86_call(patch_hypercall)(vcpu, instruction); 10137 10138 return emulator_write_emulated(ctxt, rip, instruction, 3, 10139 &ctxt->exception); 10140 } 10141 10142 static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu) 10143 { 10144 return vcpu->run->request_interrupt_window && 10145 likely(!pic_in_kernel(vcpu->kvm)); 10146 } 10147 10148 /* Called within kvm->srcu read side. */ 10149 static void post_kvm_run_save(struct kvm_vcpu *vcpu) 10150 { 10151 struct kvm_run *kvm_run = vcpu->run; 10152 10153 kvm_run->if_flag = kvm_x86_call(get_if_flag)(vcpu); 10154 kvm_run->cr8 = kvm_get_cr8(vcpu); 10155 kvm_run->apic_base = vcpu->arch.apic_base; 10156 10157 kvm_run->ready_for_interrupt_injection = 10158 pic_in_kernel(vcpu->kvm) || 10159 kvm_vcpu_ready_for_interrupt_injection(vcpu); 10160 10161 if (is_smm(vcpu)) 10162 kvm_run->flags |= KVM_RUN_X86_SMM; 10163 if (is_guest_mode(vcpu)) 10164 kvm_run->flags |= KVM_RUN_X86_GUEST_MODE; 10165 } 10166 10167 static void update_cr8_intercept(struct kvm_vcpu *vcpu) 10168 { 10169 int max_irr, tpr; 10170 10171 if (!kvm_x86_ops.update_cr8_intercept) 10172 return; 10173 10174 if (!lapic_in_kernel(vcpu)) 10175 return; 10176 10177 if (vcpu->arch.apic->apicv_active) 10178 return; 10179 10180 if (!vcpu->arch.apic->vapic_addr) 10181 max_irr = kvm_lapic_find_highest_irr(vcpu); 10182 else 10183 max_irr = -1; 10184 10185 if (max_irr != -1) 10186 max_irr >>= 4; 10187 10188 tpr = kvm_lapic_get_cr8(vcpu); 10189 10190 kvm_x86_call(update_cr8_intercept)(vcpu, tpr, max_irr); 10191 } 10192 10193 10194 int kvm_check_nested_events(struct kvm_vcpu *vcpu) 10195 { 10196 if (kvm_test_request(KVM_REQ_TRIPLE_FAULT, vcpu)) { 10197 kvm_x86_ops.nested_ops->triple_fault(vcpu); 10198 return 1; 10199 } 10200 10201 return kvm_x86_ops.nested_ops->check_events(vcpu); 10202 } 10203 10204 static void kvm_inject_exception(struct kvm_vcpu *vcpu) 10205 { 10206 /* 10207 * Suppress the error code if the vCPU is in Real Mode, as Real Mode 10208 * exceptions don't report error codes. The presence of an error code 10209 * is carried with the exception and only stripped when the exception 10210 * is injected as intercepted #PF VM-Exits for AMD's Paged Real Mode do 10211 * report an error code despite the CPU being in Real Mode. 10212 */ 10213 vcpu->arch.exception.has_error_code &= is_protmode(vcpu); 10214 10215 trace_kvm_inj_exception(vcpu->arch.exception.vector, 10216 vcpu->arch.exception.has_error_code, 10217 vcpu->arch.exception.error_code, 10218 vcpu->arch.exception.injected); 10219 10220 kvm_x86_call(inject_exception)(vcpu); 10221 } 10222 10223 /* 10224 * Check for any event (interrupt or exception) that is ready to be injected, 10225 * and if there is at least one event, inject the event with the highest 10226 * priority. This handles both "pending" events, i.e. events that have never 10227 * been injected into the guest, and "injected" events, i.e. events that were 10228 * injected as part of a previous VM-Enter, but weren't successfully delivered 10229 * and need to be re-injected. 10230 * 10231 * Note, this is not guaranteed to be invoked on a guest instruction boundary, 10232 * i.e. doesn't guarantee that there's an event window in the guest. KVM must 10233 * be able to inject exceptions in the "middle" of an instruction, and so must 10234 * also be able to re-inject NMIs and IRQs in the middle of an instruction. 10235 * I.e. for exceptions and re-injected events, NOT invoking this on instruction 10236 * boundaries is necessary and correct. 10237 * 10238 * For simplicity, KVM uses a single path to inject all events (except events 10239 * that are injected directly from L1 to L2) and doesn't explicitly track 10240 * instruction boundaries for asynchronous events. However, because VM-Exits 10241 * that can occur during instruction execution typically result in KVM skipping 10242 * the instruction or injecting an exception, e.g. instruction and exception 10243 * intercepts, and because pending exceptions have higher priority than pending 10244 * interrupts, KVM still honors instruction boundaries in most scenarios. 10245 * 10246 * But, if a VM-Exit occurs during instruction execution, and KVM does NOT skip 10247 * the instruction or inject an exception, then KVM can incorrecty inject a new 10248 * asynchronous event if the event became pending after the CPU fetched the 10249 * instruction (in the guest). E.g. if a page fault (#PF, #NPF, EPT violation) 10250 * occurs and is resolved by KVM, a coincident NMI, SMI, IRQ, etc... can be 10251 * injected on the restarted instruction instead of being deferred until the 10252 * instruction completes. 10253 * 10254 * In practice, this virtualization hole is unlikely to be observed by the 10255 * guest, and even less likely to cause functional problems. To detect the 10256 * hole, the guest would have to trigger an event on a side effect of an early 10257 * phase of instruction execution, e.g. on the instruction fetch from memory. 10258 * And for it to be a functional problem, the guest would need to depend on the 10259 * ordering between that side effect, the instruction completing, _and_ the 10260 * delivery of the asynchronous event. 10261 */ 10262 static int kvm_check_and_inject_events(struct kvm_vcpu *vcpu, 10263 bool *req_immediate_exit) 10264 { 10265 bool can_inject; 10266 int r; 10267 10268 /* 10269 * Process nested events first, as nested VM-Exit supersedes event 10270 * re-injection. If there's an event queued for re-injection, it will 10271 * be saved into the appropriate vmc{b,s}12 fields on nested VM-Exit. 10272 */ 10273 if (is_guest_mode(vcpu)) 10274 r = kvm_check_nested_events(vcpu); 10275 else 10276 r = 0; 10277 10278 /* 10279 * Re-inject exceptions and events *especially* if immediate entry+exit 10280 * to/from L2 is needed, as any event that has already been injected 10281 * into L2 needs to complete its lifecycle before injecting a new event. 10282 * 10283 * Don't re-inject an NMI or interrupt if there is a pending exception. 10284 * This collision arises if an exception occurred while vectoring the 10285 * injected event, KVM intercepted said exception, and KVM ultimately 10286 * determined the fault belongs to the guest and queues the exception 10287 * for injection back into the guest. 10288 * 10289 * "Injected" interrupts can also collide with pending exceptions if 10290 * userspace ignores the "ready for injection" flag and blindly queues 10291 * an interrupt. In that case, prioritizing the exception is correct, 10292 * as the exception "occurred" before the exit to userspace. Trap-like 10293 * exceptions, e.g. most #DBs, have higher priority than interrupts. 10294 * And while fault-like exceptions, e.g. #GP and #PF, are the lowest 10295 * priority, they're only generated (pended) during instruction 10296 * execution, and interrupts are recognized at instruction boundaries. 10297 * Thus a pending fault-like exception means the fault occurred on the 10298 * *previous* instruction and must be serviced prior to recognizing any 10299 * new events in order to fully complete the previous instruction. 10300 */ 10301 if (vcpu->arch.exception.injected) 10302 kvm_inject_exception(vcpu); 10303 else if (kvm_is_exception_pending(vcpu)) 10304 ; /* see above */ 10305 else if (vcpu->arch.nmi_injected) 10306 kvm_x86_call(inject_nmi)(vcpu); 10307 else if (vcpu->arch.interrupt.injected) 10308 kvm_x86_call(inject_irq)(vcpu, true); 10309 10310 /* 10311 * Exceptions that morph to VM-Exits are handled above, and pending 10312 * exceptions on top of injected exceptions that do not VM-Exit should 10313 * either morph to #DF or, sadly, override the injected exception. 10314 */ 10315 WARN_ON_ONCE(vcpu->arch.exception.injected && 10316 vcpu->arch.exception.pending); 10317 10318 /* 10319 * Bail if immediate entry+exit to/from the guest is needed to complete 10320 * nested VM-Enter or event re-injection so that a different pending 10321 * event can be serviced (or if KVM needs to exit to userspace). 10322 * 10323 * Otherwise, continue processing events even if VM-Exit occurred. The 10324 * VM-Exit will have cleared exceptions that were meant for L2, but 10325 * there may now be events that can be injected into L1. 10326 */ 10327 if (r < 0) 10328 goto out; 10329 10330 /* 10331 * A pending exception VM-Exit should either result in nested VM-Exit 10332 * or force an immediate re-entry and exit to/from L2, and exception 10333 * VM-Exits cannot be injected (flag should _never_ be set). 10334 */ 10335 WARN_ON_ONCE(vcpu->arch.exception_vmexit.injected || 10336 vcpu->arch.exception_vmexit.pending); 10337 10338 /* 10339 * New events, other than exceptions, cannot be injected if KVM needs 10340 * to re-inject a previous event. See above comments on re-injecting 10341 * for why pending exceptions get priority. 10342 */ 10343 can_inject = !kvm_event_needs_reinjection(vcpu); 10344 10345 if (vcpu->arch.exception.pending) { 10346 /* 10347 * Fault-class exceptions, except #DBs, set RF=1 in the RFLAGS 10348 * value pushed on the stack. Trap-like exception and all #DBs 10349 * leave RF as-is (KVM follows Intel's behavior in this regard; 10350 * AMD states that code breakpoint #DBs excplitly clear RF=0). 10351 * 10352 * Note, most versions of Intel's SDM and AMD's APM incorrectly 10353 * describe the behavior of General Detect #DBs, which are 10354 * fault-like. They do _not_ set RF, a la code breakpoints. 10355 */ 10356 if (exception_type(vcpu->arch.exception.vector) == EXCPT_FAULT) 10357 __kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) | 10358 X86_EFLAGS_RF); 10359 10360 if (vcpu->arch.exception.vector == DB_VECTOR) { 10361 kvm_deliver_exception_payload(vcpu, &vcpu->arch.exception); 10362 if (vcpu->arch.dr7 & DR7_GD) { 10363 vcpu->arch.dr7 &= ~DR7_GD; 10364 kvm_update_dr7(vcpu); 10365 } 10366 } 10367 10368 kvm_inject_exception(vcpu); 10369 10370 vcpu->arch.exception.pending = false; 10371 vcpu->arch.exception.injected = true; 10372 10373 can_inject = false; 10374 } 10375 10376 /* Don't inject interrupts if the user asked to avoid doing so */ 10377 if (vcpu->guest_debug & KVM_GUESTDBG_BLOCKIRQ) 10378 return 0; 10379 10380 /* 10381 * Finally, inject interrupt events. If an event cannot be injected 10382 * due to architectural conditions (e.g. IF=0) a window-open exit 10383 * will re-request KVM_REQ_EVENT. Sometimes however an event is pending 10384 * and can architecturally be injected, but we cannot do it right now: 10385 * an interrupt could have arrived just now and we have to inject it 10386 * as a vmexit, or there could already an event in the queue, which is 10387 * indicated by can_inject. In that case we request an immediate exit 10388 * in order to make progress and get back here for another iteration. 10389 * The kvm_x86_ops hooks communicate this by returning -EBUSY. 10390 */ 10391 #ifdef CONFIG_KVM_SMM 10392 if (vcpu->arch.smi_pending) { 10393 r = can_inject ? kvm_x86_call(smi_allowed)(vcpu, true) : 10394 -EBUSY; 10395 if (r < 0) 10396 goto out; 10397 if (r) { 10398 vcpu->arch.smi_pending = false; 10399 ++vcpu->arch.smi_count; 10400 enter_smm(vcpu); 10401 can_inject = false; 10402 } else 10403 kvm_x86_call(enable_smi_window)(vcpu); 10404 } 10405 #endif 10406 10407 if (vcpu->arch.nmi_pending) { 10408 r = can_inject ? kvm_x86_call(nmi_allowed)(vcpu, true) : 10409 -EBUSY; 10410 if (r < 0) 10411 goto out; 10412 if (r) { 10413 --vcpu->arch.nmi_pending; 10414 vcpu->arch.nmi_injected = true; 10415 kvm_x86_call(inject_nmi)(vcpu); 10416 can_inject = false; 10417 WARN_ON(kvm_x86_call(nmi_allowed)(vcpu, true) < 0); 10418 } 10419 if (vcpu->arch.nmi_pending) 10420 kvm_x86_call(enable_nmi_window)(vcpu); 10421 } 10422 10423 if (kvm_cpu_has_injectable_intr(vcpu)) { 10424 r = can_inject ? kvm_x86_call(interrupt_allowed)(vcpu, true) : 10425 -EBUSY; 10426 if (r < 0) 10427 goto out; 10428 if (r) { 10429 int irq = kvm_cpu_get_interrupt(vcpu); 10430 10431 if (!WARN_ON_ONCE(irq == -1)) { 10432 kvm_queue_interrupt(vcpu, irq, false); 10433 kvm_x86_call(inject_irq)(vcpu, false); 10434 WARN_ON(kvm_x86_call(interrupt_allowed)(vcpu, true) < 0); 10435 } 10436 } 10437 if (kvm_cpu_has_injectable_intr(vcpu)) 10438 kvm_x86_call(enable_irq_window)(vcpu); 10439 } 10440 10441 if (is_guest_mode(vcpu) && 10442 kvm_x86_ops.nested_ops->has_events && 10443 kvm_x86_ops.nested_ops->has_events(vcpu, true)) 10444 *req_immediate_exit = true; 10445 10446 /* 10447 * KVM must never queue a new exception while injecting an event; KVM 10448 * is done emulating and should only propagate the to-be-injected event 10449 * to the VMCS/VMCB. Queueing a new exception can put the vCPU into an 10450 * infinite loop as KVM will bail from VM-Enter to inject the pending 10451 * exception and start the cycle all over. 10452 * 10453 * Exempt triple faults as they have special handling and won't put the 10454 * vCPU into an infinite loop. Triple fault can be queued when running 10455 * VMX without unrestricted guest, as that requires KVM to emulate Real 10456 * Mode events (see kvm_inject_realmode_interrupt()). 10457 */ 10458 WARN_ON_ONCE(vcpu->arch.exception.pending || 10459 vcpu->arch.exception_vmexit.pending); 10460 return 0; 10461 10462 out: 10463 if (r == -EBUSY) { 10464 *req_immediate_exit = true; 10465 r = 0; 10466 } 10467 return r; 10468 } 10469 10470 static void process_nmi(struct kvm_vcpu *vcpu) 10471 { 10472 unsigned int limit; 10473 10474 /* 10475 * x86 is limited to one NMI pending, but because KVM can't react to 10476 * incoming NMIs as quickly as bare metal, e.g. if the vCPU is 10477 * scheduled out, KVM needs to play nice with two queued NMIs showing 10478 * up at the same time. To handle this scenario, allow two NMIs to be 10479 * (temporarily) pending so long as NMIs are not blocked and KVM is not 10480 * waiting for a previous NMI injection to complete (which effectively 10481 * blocks NMIs). KVM will immediately inject one of the two NMIs, and 10482 * will request an NMI window to handle the second NMI. 10483 */ 10484 if (kvm_x86_call(get_nmi_mask)(vcpu) || vcpu->arch.nmi_injected) 10485 limit = 1; 10486 else 10487 limit = 2; 10488 10489 /* 10490 * Adjust the limit to account for pending virtual NMIs, which aren't 10491 * tracked in vcpu->arch.nmi_pending. 10492 */ 10493 if (kvm_x86_call(is_vnmi_pending)(vcpu)) 10494 limit--; 10495 10496 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0); 10497 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit); 10498 10499 if (vcpu->arch.nmi_pending && 10500 (kvm_x86_call(set_vnmi_pending)(vcpu))) 10501 vcpu->arch.nmi_pending--; 10502 10503 if (vcpu->arch.nmi_pending) 10504 kvm_make_request(KVM_REQ_EVENT, vcpu); 10505 } 10506 10507 /* Return total number of NMIs pending injection to the VM */ 10508 int kvm_get_nr_pending_nmis(struct kvm_vcpu *vcpu) 10509 { 10510 return vcpu->arch.nmi_pending + 10511 kvm_x86_call(is_vnmi_pending)(vcpu); 10512 } 10513 10514 void kvm_make_scan_ioapic_request_mask(struct kvm *kvm, 10515 unsigned long *vcpu_bitmap) 10516 { 10517 kvm_make_vcpus_request_mask(kvm, KVM_REQ_SCAN_IOAPIC, vcpu_bitmap); 10518 } 10519 10520 void kvm_make_scan_ioapic_request(struct kvm *kvm) 10521 { 10522 kvm_make_all_cpus_request(kvm, KVM_REQ_SCAN_IOAPIC); 10523 } 10524 10525 void __kvm_vcpu_update_apicv(struct kvm_vcpu *vcpu) 10526 { 10527 struct kvm_lapic *apic = vcpu->arch.apic; 10528 bool activate; 10529 10530 if (!lapic_in_kernel(vcpu)) 10531 return; 10532 10533 down_read(&vcpu->kvm->arch.apicv_update_lock); 10534 preempt_disable(); 10535 10536 /* Do not activate APICV when APIC is disabled */ 10537 activate = kvm_vcpu_apicv_activated(vcpu) && 10538 (kvm_get_apic_mode(vcpu) != LAPIC_MODE_DISABLED); 10539 10540 if (apic->apicv_active == activate) 10541 goto out; 10542 10543 apic->apicv_active = activate; 10544 kvm_apic_update_apicv(vcpu); 10545 kvm_x86_call(refresh_apicv_exec_ctrl)(vcpu); 10546 10547 /* 10548 * When APICv gets disabled, we may still have injected interrupts 10549 * pending. At the same time, KVM_REQ_EVENT may not be set as APICv was 10550 * still active when the interrupt got accepted. Make sure 10551 * kvm_check_and_inject_events() is called to check for that. 10552 */ 10553 if (!apic->apicv_active) 10554 kvm_make_request(KVM_REQ_EVENT, vcpu); 10555 10556 out: 10557 preempt_enable(); 10558 up_read(&vcpu->kvm->arch.apicv_update_lock); 10559 } 10560 EXPORT_SYMBOL_GPL(__kvm_vcpu_update_apicv); 10561 10562 static void kvm_vcpu_update_apicv(struct kvm_vcpu *vcpu) 10563 { 10564 if (!lapic_in_kernel(vcpu)) 10565 return; 10566 10567 /* 10568 * Due to sharing page tables across vCPUs, the xAPIC memslot must be 10569 * deleted if any vCPU has xAPIC virtualization and x2APIC enabled, but 10570 * and hardware doesn't support x2APIC virtualization. E.g. some AMD 10571 * CPUs support AVIC but not x2APIC. KVM still allows enabling AVIC in 10572 * this case so that KVM can use the AVIC doorbell to inject interrupts 10573 * to running vCPUs, but KVM must not create SPTEs for the APIC base as 10574 * the vCPU would incorrectly be able to access the vAPIC page via MMIO 10575 * despite being in x2APIC mode. For simplicity, inhibiting the APIC 10576 * access page is sticky. 10577 */ 10578 if (apic_x2apic_mode(vcpu->arch.apic) && 10579 kvm_x86_ops.allow_apicv_in_x2apic_without_x2apic_virtualization) 10580 kvm_inhibit_apic_access_page(vcpu); 10581 10582 __kvm_vcpu_update_apicv(vcpu); 10583 } 10584 10585 void __kvm_set_or_clear_apicv_inhibit(struct kvm *kvm, 10586 enum kvm_apicv_inhibit reason, bool set) 10587 { 10588 unsigned long old, new; 10589 10590 lockdep_assert_held_write(&kvm->arch.apicv_update_lock); 10591 10592 if (!(kvm_x86_ops.required_apicv_inhibits & BIT(reason))) 10593 return; 10594 10595 old = new = kvm->arch.apicv_inhibit_reasons; 10596 10597 set_or_clear_apicv_inhibit(&new, reason, set); 10598 10599 if (!!old != !!new) { 10600 /* 10601 * Kick all vCPUs before setting apicv_inhibit_reasons to avoid 10602 * false positives in the sanity check WARN in vcpu_enter_guest(). 10603 * This task will wait for all vCPUs to ack the kick IRQ before 10604 * updating apicv_inhibit_reasons, and all other vCPUs will 10605 * block on acquiring apicv_update_lock so that vCPUs can't 10606 * redo vcpu_enter_guest() without seeing the new inhibit state. 10607 * 10608 * Note, holding apicv_update_lock and taking it in the read 10609 * side (handling the request) also prevents other vCPUs from 10610 * servicing the request with a stale apicv_inhibit_reasons. 10611 */ 10612 kvm_make_all_cpus_request(kvm, KVM_REQ_APICV_UPDATE); 10613 kvm->arch.apicv_inhibit_reasons = new; 10614 if (new) { 10615 unsigned long gfn = gpa_to_gfn(APIC_DEFAULT_PHYS_BASE); 10616 int idx = srcu_read_lock(&kvm->srcu); 10617 10618 kvm_zap_gfn_range(kvm, gfn, gfn+1); 10619 srcu_read_unlock(&kvm->srcu, idx); 10620 } 10621 } else { 10622 kvm->arch.apicv_inhibit_reasons = new; 10623 } 10624 } 10625 10626 void kvm_set_or_clear_apicv_inhibit(struct kvm *kvm, 10627 enum kvm_apicv_inhibit reason, bool set) 10628 { 10629 if (!enable_apicv) 10630 return; 10631 10632 down_write(&kvm->arch.apicv_update_lock); 10633 __kvm_set_or_clear_apicv_inhibit(kvm, reason, set); 10634 up_write(&kvm->arch.apicv_update_lock); 10635 } 10636 EXPORT_SYMBOL_GPL(kvm_set_or_clear_apicv_inhibit); 10637 10638 static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu) 10639 { 10640 if (!kvm_apic_present(vcpu)) 10641 return; 10642 10643 bitmap_zero(vcpu->arch.ioapic_handled_vectors, 256); 10644 10645 kvm_x86_call(sync_pir_to_irr)(vcpu); 10646 10647 if (irqchip_split(vcpu->kvm)) 10648 kvm_scan_ioapic_routes(vcpu, vcpu->arch.ioapic_handled_vectors); 10649 else if (ioapic_in_kernel(vcpu->kvm)) 10650 kvm_ioapic_scan_entry(vcpu, vcpu->arch.ioapic_handled_vectors); 10651 10652 if (is_guest_mode(vcpu)) 10653 vcpu->arch.load_eoi_exitmap_pending = true; 10654 else 10655 kvm_make_request(KVM_REQ_LOAD_EOI_EXITMAP, vcpu); 10656 } 10657 10658 static void vcpu_load_eoi_exitmap(struct kvm_vcpu *vcpu) 10659 { 10660 if (!kvm_apic_hw_enabled(vcpu->arch.apic)) 10661 return; 10662 10663 #ifdef CONFIG_KVM_HYPERV 10664 if (to_hv_vcpu(vcpu)) { 10665 u64 eoi_exit_bitmap[4]; 10666 10667 bitmap_or((ulong *)eoi_exit_bitmap, 10668 vcpu->arch.ioapic_handled_vectors, 10669 to_hv_synic(vcpu)->vec_bitmap, 256); 10670 kvm_x86_call(load_eoi_exitmap)(vcpu, eoi_exit_bitmap); 10671 return; 10672 } 10673 #endif 10674 kvm_x86_call(load_eoi_exitmap)( 10675 vcpu, (u64 *)vcpu->arch.ioapic_handled_vectors); 10676 } 10677 10678 void kvm_arch_guest_memory_reclaimed(struct kvm *kvm) 10679 { 10680 kvm_x86_call(guest_memory_reclaimed)(kvm); 10681 } 10682 10683 static void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu) 10684 { 10685 if (!lapic_in_kernel(vcpu)) 10686 return; 10687 10688 kvm_x86_call(set_apic_access_page_addr)(vcpu); 10689 } 10690 10691 /* 10692 * Called within kvm->srcu read side. 10693 * Returns 1 to let vcpu_run() continue the guest execution loop without 10694 * exiting to the userspace. Otherwise, the value will be returned to the 10695 * userspace. 10696 */ 10697 static int vcpu_enter_guest(struct kvm_vcpu *vcpu) 10698 { 10699 int r; 10700 bool req_int_win = 10701 dm_request_for_irq_injection(vcpu) && 10702 kvm_cpu_accept_dm_intr(vcpu); 10703 fastpath_t exit_fastpath; 10704 10705 bool req_immediate_exit = false; 10706 10707 if (kvm_request_pending(vcpu)) { 10708 if (kvm_check_request(KVM_REQ_VM_DEAD, vcpu)) { 10709 r = -EIO; 10710 goto out; 10711 } 10712 10713 if (kvm_dirty_ring_check_request(vcpu)) { 10714 r = 0; 10715 goto out; 10716 } 10717 10718 if (kvm_check_request(KVM_REQ_GET_NESTED_STATE_PAGES, vcpu)) { 10719 if (unlikely(!kvm_x86_ops.nested_ops->get_nested_state_pages(vcpu))) { 10720 r = 0; 10721 goto out; 10722 } 10723 } 10724 if (kvm_check_request(KVM_REQ_MMU_FREE_OBSOLETE_ROOTS, vcpu)) 10725 kvm_mmu_free_obsolete_roots(vcpu); 10726 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu)) 10727 __kvm_migrate_timers(vcpu); 10728 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu)) 10729 kvm_update_masterclock(vcpu->kvm); 10730 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu)) 10731 kvm_gen_kvmclock_update(vcpu); 10732 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) { 10733 r = kvm_guest_time_update(vcpu); 10734 if (unlikely(r)) 10735 goto out; 10736 } 10737 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu)) 10738 kvm_mmu_sync_roots(vcpu); 10739 if (kvm_check_request(KVM_REQ_LOAD_MMU_PGD, vcpu)) 10740 kvm_mmu_load_pgd(vcpu); 10741 10742 /* 10743 * Note, the order matters here, as flushing "all" TLB entries 10744 * also flushes the "current" TLB entries, i.e. servicing the 10745 * flush "all" will clear any request to flush "current". 10746 */ 10747 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu)) 10748 kvm_vcpu_flush_tlb_all(vcpu); 10749 10750 kvm_service_local_tlb_flush_requests(vcpu); 10751 10752 /* 10753 * Fall back to a "full" guest flush if Hyper-V's precise 10754 * flushing fails. Note, Hyper-V's flushing is per-vCPU, but 10755 * the flushes are considered "remote" and not "local" because 10756 * the requests can be initiated from other vCPUs. 10757 */ 10758 #ifdef CONFIG_KVM_HYPERV 10759 if (kvm_check_request(KVM_REQ_HV_TLB_FLUSH, vcpu) && 10760 kvm_hv_vcpu_flush_tlb(vcpu)) 10761 kvm_vcpu_flush_tlb_guest(vcpu); 10762 #endif 10763 10764 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) { 10765 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS; 10766 r = 0; 10767 goto out; 10768 } 10769 if (kvm_test_request(KVM_REQ_TRIPLE_FAULT, vcpu)) { 10770 if (is_guest_mode(vcpu)) 10771 kvm_x86_ops.nested_ops->triple_fault(vcpu); 10772 10773 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) { 10774 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN; 10775 vcpu->mmio_needed = 0; 10776 r = 0; 10777 goto out; 10778 } 10779 } 10780 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) { 10781 /* Page is swapped out. Do synthetic halt */ 10782 vcpu->arch.apf.halted = true; 10783 r = 1; 10784 goto out; 10785 } 10786 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu)) 10787 record_steal_time(vcpu); 10788 if (kvm_check_request(KVM_REQ_PMU, vcpu)) 10789 kvm_pmu_handle_event(vcpu); 10790 if (kvm_check_request(KVM_REQ_PMI, vcpu)) 10791 kvm_pmu_deliver_pmi(vcpu); 10792 #ifdef CONFIG_KVM_SMM 10793 if (kvm_check_request(KVM_REQ_SMI, vcpu)) 10794 process_smi(vcpu); 10795 #endif 10796 if (kvm_check_request(KVM_REQ_NMI, vcpu)) 10797 process_nmi(vcpu); 10798 if (kvm_check_request(KVM_REQ_IOAPIC_EOI_EXIT, vcpu)) { 10799 BUG_ON(vcpu->arch.pending_ioapic_eoi > 255); 10800 if (test_bit(vcpu->arch.pending_ioapic_eoi, 10801 vcpu->arch.ioapic_handled_vectors)) { 10802 vcpu->run->exit_reason = KVM_EXIT_IOAPIC_EOI; 10803 vcpu->run->eoi.vector = 10804 vcpu->arch.pending_ioapic_eoi; 10805 r = 0; 10806 goto out; 10807 } 10808 } 10809 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu)) 10810 vcpu_scan_ioapic(vcpu); 10811 if (kvm_check_request(KVM_REQ_LOAD_EOI_EXITMAP, vcpu)) 10812 vcpu_load_eoi_exitmap(vcpu); 10813 if (kvm_check_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu)) 10814 kvm_vcpu_reload_apic_access_page(vcpu); 10815 #ifdef CONFIG_KVM_HYPERV 10816 if (kvm_check_request(KVM_REQ_HV_CRASH, vcpu)) { 10817 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT; 10818 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_CRASH; 10819 vcpu->run->system_event.ndata = 0; 10820 r = 0; 10821 goto out; 10822 } 10823 if (kvm_check_request(KVM_REQ_HV_RESET, vcpu)) { 10824 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT; 10825 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_RESET; 10826 vcpu->run->system_event.ndata = 0; 10827 r = 0; 10828 goto out; 10829 } 10830 if (kvm_check_request(KVM_REQ_HV_EXIT, vcpu)) { 10831 struct kvm_vcpu_hv *hv_vcpu = to_hv_vcpu(vcpu); 10832 10833 vcpu->run->exit_reason = KVM_EXIT_HYPERV; 10834 vcpu->run->hyperv = hv_vcpu->exit; 10835 r = 0; 10836 goto out; 10837 } 10838 10839 /* 10840 * KVM_REQ_HV_STIMER has to be processed after 10841 * KVM_REQ_CLOCK_UPDATE, because Hyper-V SynIC timers 10842 * depend on the guest clock being up-to-date 10843 */ 10844 if (kvm_check_request(KVM_REQ_HV_STIMER, vcpu)) 10845 kvm_hv_process_stimers(vcpu); 10846 #endif 10847 if (kvm_check_request(KVM_REQ_APICV_UPDATE, vcpu)) 10848 kvm_vcpu_update_apicv(vcpu); 10849 if (kvm_check_request(KVM_REQ_APF_READY, vcpu)) 10850 kvm_check_async_pf_completion(vcpu); 10851 if (kvm_check_request(KVM_REQ_MSR_FILTER_CHANGED, vcpu)) 10852 kvm_x86_call(msr_filter_changed)(vcpu); 10853 10854 if (kvm_check_request(KVM_REQ_UPDATE_CPU_DIRTY_LOGGING, vcpu)) 10855 kvm_x86_call(update_cpu_dirty_logging)(vcpu); 10856 10857 if (kvm_check_request(KVM_REQ_UPDATE_PROTECTED_GUEST_STATE, vcpu)) { 10858 kvm_vcpu_reset(vcpu, true); 10859 if (vcpu->arch.mp_state != KVM_MP_STATE_RUNNABLE) { 10860 r = 1; 10861 goto out; 10862 } 10863 } 10864 } 10865 10866 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win || 10867 kvm_xen_has_interrupt(vcpu)) { 10868 ++vcpu->stat.req_event; 10869 r = kvm_apic_accept_events(vcpu); 10870 if (r < 0) { 10871 r = 0; 10872 goto out; 10873 } 10874 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) { 10875 r = 1; 10876 goto out; 10877 } 10878 10879 r = kvm_check_and_inject_events(vcpu, &req_immediate_exit); 10880 if (r < 0) { 10881 r = 0; 10882 goto out; 10883 } 10884 if (req_int_win) 10885 kvm_x86_call(enable_irq_window)(vcpu); 10886 10887 if (kvm_lapic_enabled(vcpu)) { 10888 update_cr8_intercept(vcpu); 10889 kvm_lapic_sync_to_vapic(vcpu); 10890 } 10891 } 10892 10893 r = kvm_mmu_reload(vcpu); 10894 if (unlikely(r)) { 10895 goto cancel_injection; 10896 } 10897 10898 preempt_disable(); 10899 10900 kvm_x86_call(prepare_switch_to_guest)(vcpu); 10901 10902 /* 10903 * Disable IRQs before setting IN_GUEST_MODE. Posted interrupt 10904 * IPI are then delayed after guest entry, which ensures that they 10905 * result in virtual interrupt delivery. 10906 */ 10907 local_irq_disable(); 10908 10909 /* Store vcpu->apicv_active before vcpu->mode. */ 10910 smp_store_release(&vcpu->mode, IN_GUEST_MODE); 10911 10912 kvm_vcpu_srcu_read_unlock(vcpu); 10913 10914 /* 10915 * 1) We should set ->mode before checking ->requests. Please see 10916 * the comment in kvm_vcpu_exiting_guest_mode(). 10917 * 10918 * 2) For APICv, we should set ->mode before checking PID.ON. This 10919 * pairs with the memory barrier implicit in pi_test_and_set_on 10920 * (see vmx_deliver_posted_interrupt). 10921 * 10922 * 3) This also orders the write to mode from any reads to the page 10923 * tables done while the VCPU is running. Please see the comment 10924 * in kvm_flush_remote_tlbs. 10925 */ 10926 smp_mb__after_srcu_read_unlock(); 10927 10928 /* 10929 * Process pending posted interrupts to handle the case where the 10930 * notification IRQ arrived in the host, or was never sent (because the 10931 * target vCPU wasn't running). Do this regardless of the vCPU's APICv 10932 * status, KVM doesn't update assigned devices when APICv is inhibited, 10933 * i.e. they can post interrupts even if APICv is temporarily disabled. 10934 */ 10935 if (kvm_lapic_enabled(vcpu)) 10936 kvm_x86_call(sync_pir_to_irr)(vcpu); 10937 10938 if (kvm_vcpu_exit_request(vcpu)) { 10939 vcpu->mode = OUTSIDE_GUEST_MODE; 10940 smp_wmb(); 10941 local_irq_enable(); 10942 preempt_enable(); 10943 kvm_vcpu_srcu_read_lock(vcpu); 10944 r = 1; 10945 goto cancel_injection; 10946 } 10947 10948 if (req_immediate_exit) 10949 kvm_make_request(KVM_REQ_EVENT, vcpu); 10950 10951 fpregs_assert_state_consistent(); 10952 if (test_thread_flag(TIF_NEED_FPU_LOAD)) 10953 switch_fpu_return(); 10954 10955 if (vcpu->arch.guest_fpu.xfd_err) 10956 wrmsrl(MSR_IA32_XFD_ERR, vcpu->arch.guest_fpu.xfd_err); 10957 10958 if (unlikely(vcpu->arch.switch_db_regs)) { 10959 set_debugreg(0, 7); 10960 set_debugreg(vcpu->arch.eff_db[0], 0); 10961 set_debugreg(vcpu->arch.eff_db[1], 1); 10962 set_debugreg(vcpu->arch.eff_db[2], 2); 10963 set_debugreg(vcpu->arch.eff_db[3], 3); 10964 } else if (unlikely(hw_breakpoint_active())) { 10965 set_debugreg(0, 7); 10966 } 10967 10968 guest_timing_enter_irqoff(); 10969 10970 for (;;) { 10971 /* 10972 * Assert that vCPU vs. VM APICv state is consistent. An APICv 10973 * update must kick and wait for all vCPUs before toggling the 10974 * per-VM state, and responding vCPUs must wait for the update 10975 * to complete before servicing KVM_REQ_APICV_UPDATE. 10976 */ 10977 WARN_ON_ONCE((kvm_vcpu_apicv_activated(vcpu) != kvm_vcpu_apicv_active(vcpu)) && 10978 (kvm_get_apic_mode(vcpu) != LAPIC_MODE_DISABLED)); 10979 10980 exit_fastpath = kvm_x86_call(vcpu_run)(vcpu, 10981 req_immediate_exit); 10982 if (likely(exit_fastpath != EXIT_FASTPATH_REENTER_GUEST)) 10983 break; 10984 10985 if (kvm_lapic_enabled(vcpu)) 10986 kvm_x86_call(sync_pir_to_irr)(vcpu); 10987 10988 if (unlikely(kvm_vcpu_exit_request(vcpu))) { 10989 exit_fastpath = EXIT_FASTPATH_EXIT_HANDLED; 10990 break; 10991 } 10992 10993 /* Note, VM-Exits that go down the "slow" path are accounted below. */ 10994 ++vcpu->stat.exits; 10995 } 10996 10997 /* 10998 * Do this here before restoring debug registers on the host. And 10999 * since we do this before handling the vmexit, a DR access vmexit 11000 * can (a) read the correct value of the debug registers, (b) set 11001 * KVM_DEBUGREG_WONT_EXIT again. 11002 */ 11003 if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) { 11004 WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP); 11005 kvm_x86_call(sync_dirty_debug_regs)(vcpu); 11006 kvm_update_dr0123(vcpu); 11007 kvm_update_dr7(vcpu); 11008 } 11009 11010 /* 11011 * If the guest has used debug registers, at least dr7 11012 * will be disabled while returning to the host. 11013 * If we don't have active breakpoints in the host, we don't 11014 * care about the messed up debug address registers. But if 11015 * we have some of them active, restore the old state. 11016 */ 11017 if (hw_breakpoint_active()) 11018 hw_breakpoint_restore(); 11019 11020 vcpu->arch.last_vmentry_cpu = vcpu->cpu; 11021 vcpu->arch.last_guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc()); 11022 11023 vcpu->mode = OUTSIDE_GUEST_MODE; 11024 smp_wmb(); 11025 11026 /* 11027 * Sync xfd before calling handle_exit_irqoff() which may 11028 * rely on the fact that guest_fpu::xfd is up-to-date (e.g. 11029 * in #NM irqoff handler). 11030 */ 11031 if (vcpu->arch.xfd_no_write_intercept) 11032 fpu_sync_guest_vmexit_xfd_state(); 11033 11034 kvm_x86_call(handle_exit_irqoff)(vcpu); 11035 11036 if (vcpu->arch.guest_fpu.xfd_err) 11037 wrmsrl(MSR_IA32_XFD_ERR, 0); 11038 11039 /* 11040 * Consume any pending interrupts, including the possible source of 11041 * VM-Exit on SVM and any ticks that occur between VM-Exit and now. 11042 * An instruction is required after local_irq_enable() to fully unblock 11043 * interrupts on processors that implement an interrupt shadow, the 11044 * stat.exits increment will do nicely. 11045 */ 11046 kvm_before_interrupt(vcpu, KVM_HANDLING_IRQ); 11047 local_irq_enable(); 11048 ++vcpu->stat.exits; 11049 local_irq_disable(); 11050 kvm_after_interrupt(vcpu); 11051 11052 /* 11053 * Wait until after servicing IRQs to account guest time so that any 11054 * ticks that occurred while running the guest are properly accounted 11055 * to the guest. Waiting until IRQs are enabled degrades the accuracy 11056 * of accounting via context tracking, but the loss of accuracy is 11057 * acceptable for all known use cases. 11058 */ 11059 guest_timing_exit_irqoff(); 11060 11061 local_irq_enable(); 11062 preempt_enable(); 11063 11064 kvm_vcpu_srcu_read_lock(vcpu); 11065 11066 /* 11067 * Call this to ensure WC buffers in guest are evicted after each VM 11068 * Exit, so that the evicted WC writes can be snooped across all cpus 11069 */ 11070 smp_mb__after_srcu_read_lock(); 11071 11072 /* 11073 * Profile KVM exit RIPs: 11074 */ 11075 if (unlikely(prof_on == KVM_PROFILING)) { 11076 unsigned long rip = kvm_rip_read(vcpu); 11077 profile_hit(KVM_PROFILING, (void *)rip); 11078 } 11079 11080 if (unlikely(vcpu->arch.tsc_always_catchup)) 11081 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 11082 11083 if (vcpu->arch.apic_attention) 11084 kvm_lapic_sync_from_vapic(vcpu); 11085 11086 if (unlikely(exit_fastpath == EXIT_FASTPATH_EXIT_USERSPACE)) 11087 return 0; 11088 11089 r = kvm_x86_call(handle_exit)(vcpu, exit_fastpath); 11090 return r; 11091 11092 cancel_injection: 11093 if (req_immediate_exit) 11094 kvm_make_request(KVM_REQ_EVENT, vcpu); 11095 kvm_x86_call(cancel_injection)(vcpu); 11096 if (unlikely(vcpu->arch.apic_attention)) 11097 kvm_lapic_sync_from_vapic(vcpu); 11098 out: 11099 return r; 11100 } 11101 11102 static bool kvm_vcpu_running(struct kvm_vcpu *vcpu) 11103 { 11104 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE && 11105 !vcpu->arch.apf.halted); 11106 } 11107 11108 static bool kvm_vcpu_has_events(struct kvm_vcpu *vcpu) 11109 { 11110 if (!list_empty_careful(&vcpu->async_pf.done)) 11111 return true; 11112 11113 if (kvm_apic_has_pending_init_or_sipi(vcpu) && 11114 kvm_apic_init_sipi_allowed(vcpu)) 11115 return true; 11116 11117 if (vcpu->arch.pv.pv_unhalted) 11118 return true; 11119 11120 if (kvm_is_exception_pending(vcpu)) 11121 return true; 11122 11123 if (kvm_test_request(KVM_REQ_NMI, vcpu) || 11124 (vcpu->arch.nmi_pending && 11125 kvm_x86_call(nmi_allowed)(vcpu, false))) 11126 return true; 11127 11128 #ifdef CONFIG_KVM_SMM 11129 if (kvm_test_request(KVM_REQ_SMI, vcpu) || 11130 (vcpu->arch.smi_pending && 11131 kvm_x86_call(smi_allowed)(vcpu, false))) 11132 return true; 11133 #endif 11134 11135 if (kvm_test_request(KVM_REQ_PMI, vcpu)) 11136 return true; 11137 11138 if (kvm_test_request(KVM_REQ_UPDATE_PROTECTED_GUEST_STATE, vcpu)) 11139 return true; 11140 11141 if (kvm_arch_interrupt_allowed(vcpu) && kvm_cpu_has_interrupt(vcpu)) 11142 return true; 11143 11144 if (kvm_hv_has_stimer_pending(vcpu)) 11145 return true; 11146 11147 if (is_guest_mode(vcpu) && 11148 kvm_x86_ops.nested_ops->has_events && 11149 kvm_x86_ops.nested_ops->has_events(vcpu, false)) 11150 return true; 11151 11152 if (kvm_xen_has_pending_events(vcpu)) 11153 return true; 11154 11155 return false; 11156 } 11157 11158 int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu) 11159 { 11160 return kvm_vcpu_running(vcpu) || kvm_vcpu_has_events(vcpu); 11161 } 11162 11163 /* Called within kvm->srcu read side. */ 11164 static inline int vcpu_block(struct kvm_vcpu *vcpu) 11165 { 11166 bool hv_timer; 11167 11168 if (!kvm_arch_vcpu_runnable(vcpu)) { 11169 /* 11170 * Switch to the software timer before halt-polling/blocking as 11171 * the guest's timer may be a break event for the vCPU, and the 11172 * hypervisor timer runs only when the CPU is in guest mode. 11173 * Switch before halt-polling so that KVM recognizes an expired 11174 * timer before blocking. 11175 */ 11176 hv_timer = kvm_lapic_hv_timer_in_use(vcpu); 11177 if (hv_timer) 11178 kvm_lapic_switch_to_sw_timer(vcpu); 11179 11180 kvm_vcpu_srcu_read_unlock(vcpu); 11181 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED) 11182 kvm_vcpu_halt(vcpu); 11183 else 11184 kvm_vcpu_block(vcpu); 11185 kvm_vcpu_srcu_read_lock(vcpu); 11186 11187 if (hv_timer) 11188 kvm_lapic_switch_to_hv_timer(vcpu); 11189 11190 /* 11191 * If the vCPU is not runnable, a signal or another host event 11192 * of some kind is pending; service it without changing the 11193 * vCPU's activity state. 11194 */ 11195 if (!kvm_arch_vcpu_runnable(vcpu)) 11196 return 1; 11197 } 11198 11199 /* 11200 * Evaluate nested events before exiting the halted state. This allows 11201 * the halt state to be recorded properly in the VMCS12's activity 11202 * state field (AMD does not have a similar field and a VM-Exit always 11203 * causes a spurious wakeup from HLT). 11204 */ 11205 if (is_guest_mode(vcpu)) { 11206 int r = kvm_check_nested_events(vcpu); 11207 11208 WARN_ON_ONCE(r == -EBUSY); 11209 if (r < 0) 11210 return 0; 11211 } 11212 11213 if (kvm_apic_accept_events(vcpu) < 0) 11214 return 0; 11215 switch(vcpu->arch.mp_state) { 11216 case KVM_MP_STATE_HALTED: 11217 case KVM_MP_STATE_AP_RESET_HOLD: 11218 vcpu->arch.pv.pv_unhalted = false; 11219 vcpu->arch.mp_state = 11220 KVM_MP_STATE_RUNNABLE; 11221 fallthrough; 11222 case KVM_MP_STATE_RUNNABLE: 11223 vcpu->arch.apf.halted = false; 11224 break; 11225 case KVM_MP_STATE_INIT_RECEIVED: 11226 break; 11227 default: 11228 WARN_ON_ONCE(1); 11229 break; 11230 } 11231 return 1; 11232 } 11233 11234 /* Called within kvm->srcu read side. */ 11235 static int vcpu_run(struct kvm_vcpu *vcpu) 11236 { 11237 int r; 11238 11239 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN; 11240 11241 for (;;) { 11242 /* 11243 * If another guest vCPU requests a PV TLB flush in the middle 11244 * of instruction emulation, the rest of the emulation could 11245 * use a stale page translation. Assume that any code after 11246 * this point can start executing an instruction. 11247 */ 11248 vcpu->arch.at_instruction_boundary = false; 11249 if (kvm_vcpu_running(vcpu)) { 11250 r = vcpu_enter_guest(vcpu); 11251 } else { 11252 r = vcpu_block(vcpu); 11253 } 11254 11255 if (r <= 0) 11256 break; 11257 11258 kvm_clear_request(KVM_REQ_UNBLOCK, vcpu); 11259 if (kvm_xen_has_pending_events(vcpu)) 11260 kvm_xen_inject_pending_events(vcpu); 11261 11262 if (kvm_cpu_has_pending_timer(vcpu)) 11263 kvm_inject_pending_timer_irqs(vcpu); 11264 11265 if (dm_request_for_irq_injection(vcpu) && 11266 kvm_vcpu_ready_for_interrupt_injection(vcpu)) { 11267 r = 0; 11268 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN; 11269 ++vcpu->stat.request_irq_exits; 11270 break; 11271 } 11272 11273 if (__xfer_to_guest_mode_work_pending()) { 11274 kvm_vcpu_srcu_read_unlock(vcpu); 11275 r = xfer_to_guest_mode_handle_work(vcpu); 11276 kvm_vcpu_srcu_read_lock(vcpu); 11277 if (r) 11278 return r; 11279 } 11280 } 11281 11282 return r; 11283 } 11284 11285 static int __kvm_emulate_halt(struct kvm_vcpu *vcpu, int state, int reason) 11286 { 11287 /* 11288 * The vCPU has halted, e.g. executed HLT. Update the run state if the 11289 * local APIC is in-kernel, the run loop will detect the non-runnable 11290 * state and halt the vCPU. Exit to userspace if the local APIC is 11291 * managed by userspace, in which case userspace is responsible for 11292 * handling wake events. 11293 */ 11294 ++vcpu->stat.halt_exits; 11295 if (lapic_in_kernel(vcpu)) { 11296 if (kvm_vcpu_has_events(vcpu)) 11297 vcpu->arch.pv.pv_unhalted = false; 11298 else 11299 vcpu->arch.mp_state = state; 11300 return 1; 11301 } else { 11302 vcpu->run->exit_reason = reason; 11303 return 0; 11304 } 11305 } 11306 11307 int kvm_emulate_halt_noskip(struct kvm_vcpu *vcpu) 11308 { 11309 return __kvm_emulate_halt(vcpu, KVM_MP_STATE_HALTED, KVM_EXIT_HLT); 11310 } 11311 EXPORT_SYMBOL_GPL(kvm_emulate_halt_noskip); 11312 11313 int kvm_emulate_halt(struct kvm_vcpu *vcpu) 11314 { 11315 int ret = kvm_skip_emulated_instruction(vcpu); 11316 /* 11317 * TODO: we might be squashing a GUESTDBG_SINGLESTEP-triggered 11318 * KVM_EXIT_DEBUG here. 11319 */ 11320 return kvm_emulate_halt_noskip(vcpu) && ret; 11321 } 11322 EXPORT_SYMBOL_GPL(kvm_emulate_halt); 11323 11324 fastpath_t handle_fastpath_hlt(struct kvm_vcpu *vcpu) 11325 { 11326 int ret; 11327 11328 kvm_vcpu_srcu_read_lock(vcpu); 11329 ret = kvm_emulate_halt(vcpu); 11330 kvm_vcpu_srcu_read_unlock(vcpu); 11331 11332 if (!ret) 11333 return EXIT_FASTPATH_EXIT_USERSPACE; 11334 11335 if (kvm_vcpu_running(vcpu)) 11336 return EXIT_FASTPATH_REENTER_GUEST; 11337 11338 return EXIT_FASTPATH_EXIT_HANDLED; 11339 } 11340 EXPORT_SYMBOL_GPL(handle_fastpath_hlt); 11341 11342 int kvm_emulate_ap_reset_hold(struct kvm_vcpu *vcpu) 11343 { 11344 int ret = kvm_skip_emulated_instruction(vcpu); 11345 11346 return __kvm_emulate_halt(vcpu, KVM_MP_STATE_AP_RESET_HOLD, 11347 KVM_EXIT_AP_RESET_HOLD) && ret; 11348 } 11349 EXPORT_SYMBOL_GPL(kvm_emulate_ap_reset_hold); 11350 11351 bool kvm_arch_dy_has_pending_interrupt(struct kvm_vcpu *vcpu) 11352 { 11353 return kvm_vcpu_apicv_active(vcpu) && 11354 kvm_x86_call(dy_apicv_has_pending_interrupt)(vcpu); 11355 } 11356 11357 bool kvm_arch_vcpu_preempted_in_kernel(struct kvm_vcpu *vcpu) 11358 { 11359 return vcpu->arch.preempted_in_kernel; 11360 } 11361 11362 bool kvm_arch_dy_runnable(struct kvm_vcpu *vcpu) 11363 { 11364 if (READ_ONCE(vcpu->arch.pv.pv_unhalted)) 11365 return true; 11366 11367 if (kvm_test_request(KVM_REQ_NMI, vcpu) || 11368 #ifdef CONFIG_KVM_SMM 11369 kvm_test_request(KVM_REQ_SMI, vcpu) || 11370 #endif 11371 kvm_test_request(KVM_REQ_EVENT, vcpu)) 11372 return true; 11373 11374 return kvm_arch_dy_has_pending_interrupt(vcpu); 11375 } 11376 11377 static inline int complete_emulated_io(struct kvm_vcpu *vcpu) 11378 { 11379 return kvm_emulate_instruction(vcpu, EMULTYPE_NO_DECODE); 11380 } 11381 11382 static int complete_emulated_pio(struct kvm_vcpu *vcpu) 11383 { 11384 BUG_ON(!vcpu->arch.pio.count); 11385 11386 return complete_emulated_io(vcpu); 11387 } 11388 11389 /* 11390 * Implements the following, as a state machine: 11391 * 11392 * read: 11393 * for each fragment 11394 * for each mmio piece in the fragment 11395 * write gpa, len 11396 * exit 11397 * copy data 11398 * execute insn 11399 * 11400 * write: 11401 * for each fragment 11402 * for each mmio piece in the fragment 11403 * write gpa, len 11404 * copy data 11405 * exit 11406 */ 11407 static int complete_emulated_mmio(struct kvm_vcpu *vcpu) 11408 { 11409 struct kvm_run *run = vcpu->run; 11410 struct kvm_mmio_fragment *frag; 11411 unsigned len; 11412 11413 BUG_ON(!vcpu->mmio_needed); 11414 11415 /* Complete previous fragment */ 11416 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment]; 11417 len = min(8u, frag->len); 11418 if (!vcpu->mmio_is_write) 11419 memcpy(frag->data, run->mmio.data, len); 11420 11421 if (frag->len <= 8) { 11422 /* Switch to the next fragment. */ 11423 frag++; 11424 vcpu->mmio_cur_fragment++; 11425 } else { 11426 /* Go forward to the next mmio piece. */ 11427 frag->data += len; 11428 frag->gpa += len; 11429 frag->len -= len; 11430 } 11431 11432 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) { 11433 vcpu->mmio_needed = 0; 11434 11435 /* FIXME: return into emulator if single-stepping. */ 11436 if (vcpu->mmio_is_write) 11437 return 1; 11438 vcpu->mmio_read_completed = 1; 11439 return complete_emulated_io(vcpu); 11440 } 11441 11442 run->exit_reason = KVM_EXIT_MMIO; 11443 run->mmio.phys_addr = frag->gpa; 11444 if (vcpu->mmio_is_write) 11445 memcpy(run->mmio.data, frag->data, min(8u, frag->len)); 11446 run->mmio.len = min(8u, frag->len); 11447 run->mmio.is_write = vcpu->mmio_is_write; 11448 vcpu->arch.complete_userspace_io = complete_emulated_mmio; 11449 return 0; 11450 } 11451 11452 /* Swap (qemu) user FPU context for the guest FPU context. */ 11453 static void kvm_load_guest_fpu(struct kvm_vcpu *vcpu) 11454 { 11455 /* Exclude PKRU, it's restored separately immediately after VM-Exit. */ 11456 fpu_swap_kvm_fpstate(&vcpu->arch.guest_fpu, true); 11457 trace_kvm_fpu(1); 11458 } 11459 11460 /* When vcpu_run ends, restore user space FPU context. */ 11461 static void kvm_put_guest_fpu(struct kvm_vcpu *vcpu) 11462 { 11463 fpu_swap_kvm_fpstate(&vcpu->arch.guest_fpu, false); 11464 ++vcpu->stat.fpu_reload; 11465 trace_kvm_fpu(0); 11466 } 11467 11468 int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu) 11469 { 11470 struct kvm_queued_exception *ex = &vcpu->arch.exception; 11471 struct kvm_run *kvm_run = vcpu->run; 11472 int r; 11473 11474 r = kvm_mmu_post_init_vm(vcpu->kvm); 11475 if (r) 11476 return r; 11477 11478 vcpu_load(vcpu); 11479 kvm_sigset_activate(vcpu); 11480 kvm_run->flags = 0; 11481 kvm_load_guest_fpu(vcpu); 11482 11483 kvm_vcpu_srcu_read_lock(vcpu); 11484 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) { 11485 if (!vcpu->wants_to_run) { 11486 r = -EINTR; 11487 goto out; 11488 } 11489 11490 /* 11491 * Don't bother switching APIC timer emulation from the 11492 * hypervisor timer to the software timer, the only way for the 11493 * APIC timer to be active is if userspace stuffed vCPU state, 11494 * i.e. put the vCPU into a nonsensical state. Only an INIT 11495 * will transition the vCPU out of UNINITIALIZED (without more 11496 * state stuffing from userspace), which will reset the local 11497 * APIC and thus cancel the timer or drop the IRQ (if the timer 11498 * already expired). 11499 */ 11500 kvm_vcpu_srcu_read_unlock(vcpu); 11501 kvm_vcpu_block(vcpu); 11502 kvm_vcpu_srcu_read_lock(vcpu); 11503 11504 if (kvm_apic_accept_events(vcpu) < 0) { 11505 r = 0; 11506 goto out; 11507 } 11508 r = -EAGAIN; 11509 if (signal_pending(current)) { 11510 r = -EINTR; 11511 kvm_run->exit_reason = KVM_EXIT_INTR; 11512 ++vcpu->stat.signal_exits; 11513 } 11514 goto out; 11515 } 11516 11517 if ((kvm_run->kvm_valid_regs & ~KVM_SYNC_X86_VALID_FIELDS) || 11518 (kvm_run->kvm_dirty_regs & ~KVM_SYNC_X86_VALID_FIELDS)) { 11519 r = -EINVAL; 11520 goto out; 11521 } 11522 11523 if (kvm_run->kvm_dirty_regs) { 11524 r = sync_regs(vcpu); 11525 if (r != 0) 11526 goto out; 11527 } 11528 11529 /* re-sync apic's tpr */ 11530 if (!lapic_in_kernel(vcpu)) { 11531 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) { 11532 r = -EINVAL; 11533 goto out; 11534 } 11535 } 11536 11537 /* 11538 * If userspace set a pending exception and L2 is active, convert it to 11539 * a pending VM-Exit if L1 wants to intercept the exception. 11540 */ 11541 if (vcpu->arch.exception_from_userspace && is_guest_mode(vcpu) && 11542 kvm_x86_ops.nested_ops->is_exception_vmexit(vcpu, ex->vector, 11543 ex->error_code)) { 11544 kvm_queue_exception_vmexit(vcpu, ex->vector, 11545 ex->has_error_code, ex->error_code, 11546 ex->has_payload, ex->payload); 11547 ex->injected = false; 11548 ex->pending = false; 11549 } 11550 vcpu->arch.exception_from_userspace = false; 11551 11552 if (unlikely(vcpu->arch.complete_userspace_io)) { 11553 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io; 11554 vcpu->arch.complete_userspace_io = NULL; 11555 r = cui(vcpu); 11556 if (r <= 0) 11557 goto out; 11558 } else { 11559 WARN_ON_ONCE(vcpu->arch.pio.count); 11560 WARN_ON_ONCE(vcpu->mmio_needed); 11561 } 11562 11563 if (!vcpu->wants_to_run) { 11564 r = -EINTR; 11565 goto out; 11566 } 11567 11568 r = kvm_x86_call(vcpu_pre_run)(vcpu); 11569 if (r <= 0) 11570 goto out; 11571 11572 r = vcpu_run(vcpu); 11573 11574 out: 11575 kvm_put_guest_fpu(vcpu); 11576 if (kvm_run->kvm_valid_regs) 11577 store_regs(vcpu); 11578 post_kvm_run_save(vcpu); 11579 kvm_vcpu_srcu_read_unlock(vcpu); 11580 11581 kvm_sigset_deactivate(vcpu); 11582 vcpu_put(vcpu); 11583 return r; 11584 } 11585 11586 static void __get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) 11587 { 11588 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) { 11589 /* 11590 * We are here if userspace calls get_regs() in the middle of 11591 * instruction emulation. Registers state needs to be copied 11592 * back from emulation context to vcpu. Userspace shouldn't do 11593 * that usually, but some bad designed PV devices (vmware 11594 * backdoor interface) need this to work 11595 */ 11596 emulator_writeback_register_cache(vcpu->arch.emulate_ctxt); 11597 vcpu->arch.emulate_regs_need_sync_to_vcpu = false; 11598 } 11599 regs->rax = kvm_rax_read(vcpu); 11600 regs->rbx = kvm_rbx_read(vcpu); 11601 regs->rcx = kvm_rcx_read(vcpu); 11602 regs->rdx = kvm_rdx_read(vcpu); 11603 regs->rsi = kvm_rsi_read(vcpu); 11604 regs->rdi = kvm_rdi_read(vcpu); 11605 regs->rsp = kvm_rsp_read(vcpu); 11606 regs->rbp = kvm_rbp_read(vcpu); 11607 #ifdef CONFIG_X86_64 11608 regs->r8 = kvm_r8_read(vcpu); 11609 regs->r9 = kvm_r9_read(vcpu); 11610 regs->r10 = kvm_r10_read(vcpu); 11611 regs->r11 = kvm_r11_read(vcpu); 11612 regs->r12 = kvm_r12_read(vcpu); 11613 regs->r13 = kvm_r13_read(vcpu); 11614 regs->r14 = kvm_r14_read(vcpu); 11615 regs->r15 = kvm_r15_read(vcpu); 11616 #endif 11617 11618 regs->rip = kvm_rip_read(vcpu); 11619 regs->rflags = kvm_get_rflags(vcpu); 11620 } 11621 11622 int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) 11623 { 11624 if (vcpu->kvm->arch.has_protected_state && 11625 vcpu->arch.guest_state_protected) 11626 return -EINVAL; 11627 11628 vcpu_load(vcpu); 11629 __get_regs(vcpu, regs); 11630 vcpu_put(vcpu); 11631 return 0; 11632 } 11633 11634 static void __set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) 11635 { 11636 vcpu->arch.emulate_regs_need_sync_from_vcpu = true; 11637 vcpu->arch.emulate_regs_need_sync_to_vcpu = false; 11638 11639 kvm_rax_write(vcpu, regs->rax); 11640 kvm_rbx_write(vcpu, regs->rbx); 11641 kvm_rcx_write(vcpu, regs->rcx); 11642 kvm_rdx_write(vcpu, regs->rdx); 11643 kvm_rsi_write(vcpu, regs->rsi); 11644 kvm_rdi_write(vcpu, regs->rdi); 11645 kvm_rsp_write(vcpu, regs->rsp); 11646 kvm_rbp_write(vcpu, regs->rbp); 11647 #ifdef CONFIG_X86_64 11648 kvm_r8_write(vcpu, regs->r8); 11649 kvm_r9_write(vcpu, regs->r9); 11650 kvm_r10_write(vcpu, regs->r10); 11651 kvm_r11_write(vcpu, regs->r11); 11652 kvm_r12_write(vcpu, regs->r12); 11653 kvm_r13_write(vcpu, regs->r13); 11654 kvm_r14_write(vcpu, regs->r14); 11655 kvm_r15_write(vcpu, regs->r15); 11656 #endif 11657 11658 kvm_rip_write(vcpu, regs->rip); 11659 kvm_set_rflags(vcpu, regs->rflags | X86_EFLAGS_FIXED); 11660 11661 vcpu->arch.exception.pending = false; 11662 vcpu->arch.exception_vmexit.pending = false; 11663 11664 kvm_make_request(KVM_REQ_EVENT, vcpu); 11665 } 11666 11667 int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) 11668 { 11669 if (vcpu->kvm->arch.has_protected_state && 11670 vcpu->arch.guest_state_protected) 11671 return -EINVAL; 11672 11673 vcpu_load(vcpu); 11674 __set_regs(vcpu, regs); 11675 vcpu_put(vcpu); 11676 return 0; 11677 } 11678 11679 static void __get_sregs_common(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs) 11680 { 11681 struct desc_ptr dt; 11682 11683 if (vcpu->arch.guest_state_protected) 11684 goto skip_protected_regs; 11685 11686 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS); 11687 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS); 11688 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES); 11689 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS); 11690 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS); 11691 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS); 11692 11693 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR); 11694 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR); 11695 11696 kvm_x86_call(get_idt)(vcpu, &dt); 11697 sregs->idt.limit = dt.size; 11698 sregs->idt.base = dt.address; 11699 kvm_x86_call(get_gdt)(vcpu, &dt); 11700 sregs->gdt.limit = dt.size; 11701 sregs->gdt.base = dt.address; 11702 11703 sregs->cr2 = vcpu->arch.cr2; 11704 sregs->cr3 = kvm_read_cr3(vcpu); 11705 11706 skip_protected_regs: 11707 sregs->cr0 = kvm_read_cr0(vcpu); 11708 sregs->cr4 = kvm_read_cr4(vcpu); 11709 sregs->cr8 = kvm_get_cr8(vcpu); 11710 sregs->efer = vcpu->arch.efer; 11711 sregs->apic_base = vcpu->arch.apic_base; 11712 } 11713 11714 static void __get_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs) 11715 { 11716 __get_sregs_common(vcpu, sregs); 11717 11718 if (vcpu->arch.guest_state_protected) 11719 return; 11720 11721 if (vcpu->arch.interrupt.injected && !vcpu->arch.interrupt.soft) 11722 set_bit(vcpu->arch.interrupt.nr, 11723 (unsigned long *)sregs->interrupt_bitmap); 11724 } 11725 11726 static void __get_sregs2(struct kvm_vcpu *vcpu, struct kvm_sregs2 *sregs2) 11727 { 11728 int i; 11729 11730 __get_sregs_common(vcpu, (struct kvm_sregs *)sregs2); 11731 11732 if (vcpu->arch.guest_state_protected) 11733 return; 11734 11735 if (is_pae_paging(vcpu)) { 11736 for (i = 0 ; i < 4 ; i++) 11737 sregs2->pdptrs[i] = kvm_pdptr_read(vcpu, i); 11738 sregs2->flags |= KVM_SREGS2_FLAGS_PDPTRS_VALID; 11739 } 11740 } 11741 11742 int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu, 11743 struct kvm_sregs *sregs) 11744 { 11745 if (vcpu->kvm->arch.has_protected_state && 11746 vcpu->arch.guest_state_protected) 11747 return -EINVAL; 11748 11749 vcpu_load(vcpu); 11750 __get_sregs(vcpu, sregs); 11751 vcpu_put(vcpu); 11752 return 0; 11753 } 11754 11755 int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu, 11756 struct kvm_mp_state *mp_state) 11757 { 11758 int r; 11759 11760 vcpu_load(vcpu); 11761 if (kvm_mpx_supported()) 11762 kvm_load_guest_fpu(vcpu); 11763 11764 r = kvm_apic_accept_events(vcpu); 11765 if (r < 0) 11766 goto out; 11767 r = 0; 11768 11769 if ((vcpu->arch.mp_state == KVM_MP_STATE_HALTED || 11770 vcpu->arch.mp_state == KVM_MP_STATE_AP_RESET_HOLD) && 11771 vcpu->arch.pv.pv_unhalted) 11772 mp_state->mp_state = KVM_MP_STATE_RUNNABLE; 11773 else 11774 mp_state->mp_state = vcpu->arch.mp_state; 11775 11776 out: 11777 if (kvm_mpx_supported()) 11778 kvm_put_guest_fpu(vcpu); 11779 vcpu_put(vcpu); 11780 return r; 11781 } 11782 11783 int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu, 11784 struct kvm_mp_state *mp_state) 11785 { 11786 int ret = -EINVAL; 11787 11788 vcpu_load(vcpu); 11789 11790 switch (mp_state->mp_state) { 11791 case KVM_MP_STATE_UNINITIALIZED: 11792 case KVM_MP_STATE_HALTED: 11793 case KVM_MP_STATE_AP_RESET_HOLD: 11794 case KVM_MP_STATE_INIT_RECEIVED: 11795 case KVM_MP_STATE_SIPI_RECEIVED: 11796 if (!lapic_in_kernel(vcpu)) 11797 goto out; 11798 break; 11799 11800 case KVM_MP_STATE_RUNNABLE: 11801 break; 11802 11803 default: 11804 goto out; 11805 } 11806 11807 /* 11808 * Pending INITs are reported using KVM_SET_VCPU_EVENTS, disallow 11809 * forcing the guest into INIT/SIPI if those events are supposed to be 11810 * blocked. KVM prioritizes SMI over INIT, so reject INIT/SIPI state 11811 * if an SMI is pending as well. 11812 */ 11813 if ((!kvm_apic_init_sipi_allowed(vcpu) || vcpu->arch.smi_pending) && 11814 (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED || 11815 mp_state->mp_state == KVM_MP_STATE_INIT_RECEIVED)) 11816 goto out; 11817 11818 if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) { 11819 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED; 11820 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events); 11821 } else 11822 vcpu->arch.mp_state = mp_state->mp_state; 11823 kvm_make_request(KVM_REQ_EVENT, vcpu); 11824 11825 ret = 0; 11826 out: 11827 vcpu_put(vcpu); 11828 return ret; 11829 } 11830 11831 int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index, 11832 int reason, bool has_error_code, u32 error_code) 11833 { 11834 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt; 11835 int ret; 11836 11837 init_emulate_ctxt(vcpu); 11838 11839 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason, 11840 has_error_code, error_code); 11841 11842 /* 11843 * Report an error userspace if MMIO is needed, as KVM doesn't support 11844 * MMIO during a task switch (or any other complex operation). 11845 */ 11846 if (ret || vcpu->mmio_needed) { 11847 vcpu->mmio_needed = false; 11848 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR; 11849 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION; 11850 vcpu->run->internal.ndata = 0; 11851 return 0; 11852 } 11853 11854 kvm_rip_write(vcpu, ctxt->eip); 11855 kvm_set_rflags(vcpu, ctxt->eflags); 11856 return 1; 11857 } 11858 EXPORT_SYMBOL_GPL(kvm_task_switch); 11859 11860 static bool kvm_is_valid_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs) 11861 { 11862 if ((sregs->efer & EFER_LME) && (sregs->cr0 & X86_CR0_PG)) { 11863 /* 11864 * When EFER.LME and CR0.PG are set, the processor is in 11865 * 64-bit mode (though maybe in a 32-bit code segment). 11866 * CR4.PAE and EFER.LMA must be set. 11867 */ 11868 if (!(sregs->cr4 & X86_CR4_PAE) || !(sregs->efer & EFER_LMA)) 11869 return false; 11870 if (!kvm_vcpu_is_legal_cr3(vcpu, sregs->cr3)) 11871 return false; 11872 } else { 11873 /* 11874 * Not in 64-bit mode: EFER.LMA is clear and the code 11875 * segment cannot be 64-bit. 11876 */ 11877 if (sregs->efer & EFER_LMA || sregs->cs.l) 11878 return false; 11879 } 11880 11881 return kvm_is_valid_cr4(vcpu, sregs->cr4) && 11882 kvm_is_valid_cr0(vcpu, sregs->cr0); 11883 } 11884 11885 static int __set_sregs_common(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs, 11886 int *mmu_reset_needed, bool update_pdptrs) 11887 { 11888 int idx; 11889 struct desc_ptr dt; 11890 11891 if (!kvm_is_valid_sregs(vcpu, sregs)) 11892 return -EINVAL; 11893 11894 if (kvm_apic_set_base(vcpu, sregs->apic_base, true)) 11895 return -EINVAL; 11896 11897 if (vcpu->arch.guest_state_protected) 11898 return 0; 11899 11900 dt.size = sregs->idt.limit; 11901 dt.address = sregs->idt.base; 11902 kvm_x86_call(set_idt)(vcpu, &dt); 11903 dt.size = sregs->gdt.limit; 11904 dt.address = sregs->gdt.base; 11905 kvm_x86_call(set_gdt)(vcpu, &dt); 11906 11907 vcpu->arch.cr2 = sregs->cr2; 11908 *mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3; 11909 vcpu->arch.cr3 = sregs->cr3; 11910 kvm_register_mark_dirty(vcpu, VCPU_EXREG_CR3); 11911 kvm_x86_call(post_set_cr3)(vcpu, sregs->cr3); 11912 11913 kvm_set_cr8(vcpu, sregs->cr8); 11914 11915 *mmu_reset_needed |= vcpu->arch.efer != sregs->efer; 11916 kvm_x86_call(set_efer)(vcpu, sregs->efer); 11917 11918 *mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0; 11919 kvm_x86_call(set_cr0)(vcpu, sregs->cr0); 11920 11921 *mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4; 11922 kvm_x86_call(set_cr4)(vcpu, sregs->cr4); 11923 11924 if (update_pdptrs) { 11925 idx = srcu_read_lock(&vcpu->kvm->srcu); 11926 if (is_pae_paging(vcpu)) { 11927 load_pdptrs(vcpu, kvm_read_cr3(vcpu)); 11928 *mmu_reset_needed = 1; 11929 } 11930 srcu_read_unlock(&vcpu->kvm->srcu, idx); 11931 } 11932 11933 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS); 11934 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS); 11935 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES); 11936 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS); 11937 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS); 11938 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS); 11939 11940 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR); 11941 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR); 11942 11943 update_cr8_intercept(vcpu); 11944 11945 /* Older userspace won't unhalt the vcpu on reset. */ 11946 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 && 11947 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 && 11948 !is_protmode(vcpu)) 11949 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; 11950 11951 return 0; 11952 } 11953 11954 static int __set_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs) 11955 { 11956 int pending_vec, max_bits; 11957 int mmu_reset_needed = 0; 11958 int ret = __set_sregs_common(vcpu, sregs, &mmu_reset_needed, true); 11959 11960 if (ret) 11961 return ret; 11962 11963 if (mmu_reset_needed) { 11964 kvm_mmu_reset_context(vcpu); 11965 kvm_make_request(KVM_REQ_TLB_FLUSH_GUEST, vcpu); 11966 } 11967 11968 max_bits = KVM_NR_INTERRUPTS; 11969 pending_vec = find_first_bit( 11970 (const unsigned long *)sregs->interrupt_bitmap, max_bits); 11971 11972 if (pending_vec < max_bits) { 11973 kvm_queue_interrupt(vcpu, pending_vec, false); 11974 pr_debug("Set back pending irq %d\n", pending_vec); 11975 kvm_make_request(KVM_REQ_EVENT, vcpu); 11976 } 11977 return 0; 11978 } 11979 11980 static int __set_sregs2(struct kvm_vcpu *vcpu, struct kvm_sregs2 *sregs2) 11981 { 11982 int mmu_reset_needed = 0; 11983 bool valid_pdptrs = sregs2->flags & KVM_SREGS2_FLAGS_PDPTRS_VALID; 11984 bool pae = (sregs2->cr0 & X86_CR0_PG) && (sregs2->cr4 & X86_CR4_PAE) && 11985 !(sregs2->efer & EFER_LMA); 11986 int i, ret; 11987 11988 if (sregs2->flags & ~KVM_SREGS2_FLAGS_PDPTRS_VALID) 11989 return -EINVAL; 11990 11991 if (valid_pdptrs && (!pae || vcpu->arch.guest_state_protected)) 11992 return -EINVAL; 11993 11994 ret = __set_sregs_common(vcpu, (struct kvm_sregs *)sregs2, 11995 &mmu_reset_needed, !valid_pdptrs); 11996 if (ret) 11997 return ret; 11998 11999 if (valid_pdptrs) { 12000 for (i = 0; i < 4 ; i++) 12001 kvm_pdptr_write(vcpu, i, sregs2->pdptrs[i]); 12002 12003 kvm_register_mark_dirty(vcpu, VCPU_EXREG_PDPTR); 12004 mmu_reset_needed = 1; 12005 vcpu->arch.pdptrs_from_userspace = true; 12006 } 12007 if (mmu_reset_needed) { 12008 kvm_mmu_reset_context(vcpu); 12009 kvm_make_request(KVM_REQ_TLB_FLUSH_GUEST, vcpu); 12010 } 12011 return 0; 12012 } 12013 12014 int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu, 12015 struct kvm_sregs *sregs) 12016 { 12017 int ret; 12018 12019 if (vcpu->kvm->arch.has_protected_state && 12020 vcpu->arch.guest_state_protected) 12021 return -EINVAL; 12022 12023 vcpu_load(vcpu); 12024 ret = __set_sregs(vcpu, sregs); 12025 vcpu_put(vcpu); 12026 return ret; 12027 } 12028 12029 static void kvm_arch_vcpu_guestdbg_update_apicv_inhibit(struct kvm *kvm) 12030 { 12031 bool set = false; 12032 struct kvm_vcpu *vcpu; 12033 unsigned long i; 12034 12035 if (!enable_apicv) 12036 return; 12037 12038 down_write(&kvm->arch.apicv_update_lock); 12039 12040 kvm_for_each_vcpu(i, vcpu, kvm) { 12041 if (vcpu->guest_debug & KVM_GUESTDBG_BLOCKIRQ) { 12042 set = true; 12043 break; 12044 } 12045 } 12046 __kvm_set_or_clear_apicv_inhibit(kvm, APICV_INHIBIT_REASON_BLOCKIRQ, set); 12047 up_write(&kvm->arch.apicv_update_lock); 12048 } 12049 12050 int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu, 12051 struct kvm_guest_debug *dbg) 12052 { 12053 unsigned long rflags; 12054 int i, r; 12055 12056 if (vcpu->arch.guest_state_protected) 12057 return -EINVAL; 12058 12059 vcpu_load(vcpu); 12060 12061 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) { 12062 r = -EBUSY; 12063 if (kvm_is_exception_pending(vcpu)) 12064 goto out; 12065 if (dbg->control & KVM_GUESTDBG_INJECT_DB) 12066 kvm_queue_exception(vcpu, DB_VECTOR); 12067 else 12068 kvm_queue_exception(vcpu, BP_VECTOR); 12069 } 12070 12071 /* 12072 * Read rflags as long as potentially injected trace flags are still 12073 * filtered out. 12074 */ 12075 rflags = kvm_get_rflags(vcpu); 12076 12077 vcpu->guest_debug = dbg->control; 12078 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE)) 12079 vcpu->guest_debug = 0; 12080 12081 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) { 12082 for (i = 0; i < KVM_NR_DB_REGS; ++i) 12083 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i]; 12084 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7]; 12085 } else { 12086 for (i = 0; i < KVM_NR_DB_REGS; i++) 12087 vcpu->arch.eff_db[i] = vcpu->arch.db[i]; 12088 } 12089 kvm_update_dr7(vcpu); 12090 12091 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) 12092 vcpu->arch.singlestep_rip = kvm_get_linear_rip(vcpu); 12093 12094 /* 12095 * Trigger an rflags update that will inject or remove the trace 12096 * flags. 12097 */ 12098 kvm_set_rflags(vcpu, rflags); 12099 12100 kvm_x86_call(update_exception_bitmap)(vcpu); 12101 12102 kvm_arch_vcpu_guestdbg_update_apicv_inhibit(vcpu->kvm); 12103 12104 r = 0; 12105 12106 out: 12107 vcpu_put(vcpu); 12108 return r; 12109 } 12110 12111 /* 12112 * Translate a guest virtual address to a guest physical address. 12113 */ 12114 int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu, 12115 struct kvm_translation *tr) 12116 { 12117 unsigned long vaddr = tr->linear_address; 12118 gpa_t gpa; 12119 int idx; 12120 12121 vcpu_load(vcpu); 12122 12123 idx = srcu_read_lock(&vcpu->kvm->srcu); 12124 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL); 12125 srcu_read_unlock(&vcpu->kvm->srcu, idx); 12126 tr->physical_address = gpa; 12127 tr->valid = gpa != INVALID_GPA; 12128 tr->writeable = 1; 12129 tr->usermode = 0; 12130 12131 vcpu_put(vcpu); 12132 return 0; 12133 } 12134 12135 int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu) 12136 { 12137 struct fxregs_state *fxsave; 12138 12139 if (fpstate_is_confidential(&vcpu->arch.guest_fpu)) 12140 return vcpu->kvm->arch.has_protected_state ? -EINVAL : 0; 12141 12142 vcpu_load(vcpu); 12143 12144 fxsave = &vcpu->arch.guest_fpu.fpstate->regs.fxsave; 12145 memcpy(fpu->fpr, fxsave->st_space, 128); 12146 fpu->fcw = fxsave->cwd; 12147 fpu->fsw = fxsave->swd; 12148 fpu->ftwx = fxsave->twd; 12149 fpu->last_opcode = fxsave->fop; 12150 fpu->last_ip = fxsave->rip; 12151 fpu->last_dp = fxsave->rdp; 12152 memcpy(fpu->xmm, fxsave->xmm_space, sizeof(fxsave->xmm_space)); 12153 12154 vcpu_put(vcpu); 12155 return 0; 12156 } 12157 12158 int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu) 12159 { 12160 struct fxregs_state *fxsave; 12161 12162 if (fpstate_is_confidential(&vcpu->arch.guest_fpu)) 12163 return vcpu->kvm->arch.has_protected_state ? -EINVAL : 0; 12164 12165 vcpu_load(vcpu); 12166 12167 fxsave = &vcpu->arch.guest_fpu.fpstate->regs.fxsave; 12168 12169 memcpy(fxsave->st_space, fpu->fpr, 128); 12170 fxsave->cwd = fpu->fcw; 12171 fxsave->swd = fpu->fsw; 12172 fxsave->twd = fpu->ftwx; 12173 fxsave->fop = fpu->last_opcode; 12174 fxsave->rip = fpu->last_ip; 12175 fxsave->rdp = fpu->last_dp; 12176 memcpy(fxsave->xmm_space, fpu->xmm, sizeof(fxsave->xmm_space)); 12177 12178 vcpu_put(vcpu); 12179 return 0; 12180 } 12181 12182 static void store_regs(struct kvm_vcpu *vcpu) 12183 { 12184 BUILD_BUG_ON(sizeof(struct kvm_sync_regs) > SYNC_REGS_SIZE_BYTES); 12185 12186 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_REGS) 12187 __get_regs(vcpu, &vcpu->run->s.regs.regs); 12188 12189 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_SREGS) 12190 __get_sregs(vcpu, &vcpu->run->s.regs.sregs); 12191 12192 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_EVENTS) 12193 kvm_vcpu_ioctl_x86_get_vcpu_events( 12194 vcpu, &vcpu->run->s.regs.events); 12195 } 12196 12197 static int sync_regs(struct kvm_vcpu *vcpu) 12198 { 12199 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_REGS) { 12200 __set_regs(vcpu, &vcpu->run->s.regs.regs); 12201 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_REGS; 12202 } 12203 12204 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_SREGS) { 12205 struct kvm_sregs sregs = vcpu->run->s.regs.sregs; 12206 12207 if (__set_sregs(vcpu, &sregs)) 12208 return -EINVAL; 12209 12210 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_SREGS; 12211 } 12212 12213 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_EVENTS) { 12214 struct kvm_vcpu_events events = vcpu->run->s.regs.events; 12215 12216 if (kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events)) 12217 return -EINVAL; 12218 12219 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_EVENTS; 12220 } 12221 12222 return 0; 12223 } 12224 12225 int kvm_arch_vcpu_precreate(struct kvm *kvm, unsigned int id) 12226 { 12227 if (kvm_check_tsc_unstable() && kvm->created_vcpus) 12228 pr_warn_once("SMP vm created on host with unstable TSC; " 12229 "guest TSC will not be reliable\n"); 12230 12231 if (!kvm->arch.max_vcpu_ids) 12232 kvm->arch.max_vcpu_ids = KVM_MAX_VCPU_IDS; 12233 12234 if (id >= kvm->arch.max_vcpu_ids) 12235 return -EINVAL; 12236 12237 return kvm_x86_call(vcpu_precreate)(kvm); 12238 } 12239 12240 int kvm_arch_vcpu_create(struct kvm_vcpu *vcpu) 12241 { 12242 struct page *page; 12243 int r; 12244 12245 vcpu->arch.last_vmentry_cpu = -1; 12246 vcpu->arch.regs_avail = ~0; 12247 vcpu->arch.regs_dirty = ~0; 12248 12249 kvm_gpc_init(&vcpu->arch.pv_time, vcpu->kvm); 12250 12251 if (!irqchip_in_kernel(vcpu->kvm) || kvm_vcpu_is_reset_bsp(vcpu)) 12252 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; 12253 else 12254 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED; 12255 12256 r = kvm_mmu_create(vcpu); 12257 if (r < 0) 12258 return r; 12259 12260 r = kvm_create_lapic(vcpu); 12261 if (r < 0) 12262 goto fail_mmu_destroy; 12263 12264 r = -ENOMEM; 12265 12266 page = alloc_page(GFP_KERNEL_ACCOUNT | __GFP_ZERO); 12267 if (!page) 12268 goto fail_free_lapic; 12269 vcpu->arch.pio_data = page_address(page); 12270 12271 vcpu->arch.mce_banks = kcalloc(KVM_MAX_MCE_BANKS * 4, sizeof(u64), 12272 GFP_KERNEL_ACCOUNT); 12273 vcpu->arch.mci_ctl2_banks = kcalloc(KVM_MAX_MCE_BANKS, sizeof(u64), 12274 GFP_KERNEL_ACCOUNT); 12275 if (!vcpu->arch.mce_banks || !vcpu->arch.mci_ctl2_banks) 12276 goto fail_free_mce_banks; 12277 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS; 12278 12279 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, 12280 GFP_KERNEL_ACCOUNT)) 12281 goto fail_free_mce_banks; 12282 12283 if (!alloc_emulate_ctxt(vcpu)) 12284 goto free_wbinvd_dirty_mask; 12285 12286 if (!fpu_alloc_guest_fpstate(&vcpu->arch.guest_fpu)) { 12287 pr_err("failed to allocate vcpu's fpu\n"); 12288 goto free_emulate_ctxt; 12289 } 12290 12291 kvm_async_pf_hash_reset(vcpu); 12292 12293 if (kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_STUFF_FEATURE_MSRS)) { 12294 vcpu->arch.arch_capabilities = kvm_get_arch_capabilities(); 12295 vcpu->arch.msr_platform_info = MSR_PLATFORM_INFO_CPUID_FAULT; 12296 vcpu->arch.perf_capabilities = kvm_caps.supported_perf_cap; 12297 } 12298 kvm_pmu_init(vcpu); 12299 12300 vcpu->arch.pending_external_vector = -1; 12301 vcpu->arch.preempted_in_kernel = false; 12302 12303 #if IS_ENABLED(CONFIG_HYPERV) 12304 vcpu->arch.hv_root_tdp = INVALID_PAGE; 12305 #endif 12306 12307 r = kvm_x86_call(vcpu_create)(vcpu); 12308 if (r) 12309 goto free_guest_fpu; 12310 12311 kvm_xen_init_vcpu(vcpu); 12312 vcpu_load(vcpu); 12313 kvm_vcpu_after_set_cpuid(vcpu); 12314 kvm_set_tsc_khz(vcpu, vcpu->kvm->arch.default_tsc_khz); 12315 kvm_vcpu_reset(vcpu, false); 12316 kvm_init_mmu(vcpu); 12317 vcpu_put(vcpu); 12318 return 0; 12319 12320 free_guest_fpu: 12321 fpu_free_guest_fpstate(&vcpu->arch.guest_fpu); 12322 free_emulate_ctxt: 12323 kmem_cache_free(x86_emulator_cache, vcpu->arch.emulate_ctxt); 12324 free_wbinvd_dirty_mask: 12325 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask); 12326 fail_free_mce_banks: 12327 kfree(vcpu->arch.mce_banks); 12328 kfree(vcpu->arch.mci_ctl2_banks); 12329 free_page((unsigned long)vcpu->arch.pio_data); 12330 fail_free_lapic: 12331 kvm_free_lapic(vcpu); 12332 fail_mmu_destroy: 12333 kvm_mmu_destroy(vcpu); 12334 return r; 12335 } 12336 12337 void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu) 12338 { 12339 struct kvm *kvm = vcpu->kvm; 12340 12341 if (mutex_lock_killable(&vcpu->mutex)) 12342 return; 12343 vcpu_load(vcpu); 12344 kvm_synchronize_tsc(vcpu, NULL); 12345 vcpu_put(vcpu); 12346 12347 /* poll control enabled by default */ 12348 vcpu->arch.msr_kvm_poll_control = 1; 12349 12350 mutex_unlock(&vcpu->mutex); 12351 12352 if (kvmclock_periodic_sync && vcpu->vcpu_idx == 0) 12353 schedule_delayed_work(&kvm->arch.kvmclock_sync_work, 12354 KVMCLOCK_SYNC_PERIOD); 12355 } 12356 12357 void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu) 12358 { 12359 int idx; 12360 12361 kvmclock_reset(vcpu); 12362 12363 kvm_x86_call(vcpu_free)(vcpu); 12364 12365 kmem_cache_free(x86_emulator_cache, vcpu->arch.emulate_ctxt); 12366 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask); 12367 fpu_free_guest_fpstate(&vcpu->arch.guest_fpu); 12368 12369 kvm_xen_destroy_vcpu(vcpu); 12370 kvm_hv_vcpu_uninit(vcpu); 12371 kvm_pmu_destroy(vcpu); 12372 kfree(vcpu->arch.mce_banks); 12373 kfree(vcpu->arch.mci_ctl2_banks); 12374 kvm_free_lapic(vcpu); 12375 idx = srcu_read_lock(&vcpu->kvm->srcu); 12376 kvm_mmu_destroy(vcpu); 12377 srcu_read_unlock(&vcpu->kvm->srcu, idx); 12378 free_page((unsigned long)vcpu->arch.pio_data); 12379 kvfree(vcpu->arch.cpuid_entries); 12380 } 12381 12382 void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event) 12383 { 12384 struct kvm_cpuid_entry2 *cpuid_0x1; 12385 unsigned long old_cr0 = kvm_read_cr0(vcpu); 12386 unsigned long new_cr0; 12387 12388 /* 12389 * Several of the "set" flows, e.g. ->set_cr0(), read other registers 12390 * to handle side effects. RESET emulation hits those flows and relies 12391 * on emulated/virtualized registers, including those that are loaded 12392 * into hardware, to be zeroed at vCPU creation. Use CRs as a sentinel 12393 * to detect improper or missing initialization. 12394 */ 12395 WARN_ON_ONCE(!init_event && 12396 (old_cr0 || kvm_read_cr3(vcpu) || kvm_read_cr4(vcpu))); 12397 12398 /* 12399 * SVM doesn't unconditionally VM-Exit on INIT and SHUTDOWN, thus it's 12400 * possible to INIT the vCPU while L2 is active. Force the vCPU back 12401 * into L1 as EFER.SVME is cleared on INIT (along with all other EFER 12402 * bits), i.e. virtualization is disabled. 12403 */ 12404 if (is_guest_mode(vcpu)) 12405 kvm_leave_nested(vcpu); 12406 12407 kvm_lapic_reset(vcpu, init_event); 12408 12409 WARN_ON_ONCE(is_guest_mode(vcpu) || is_smm(vcpu)); 12410 vcpu->arch.hflags = 0; 12411 12412 vcpu->arch.smi_pending = 0; 12413 vcpu->arch.smi_count = 0; 12414 atomic_set(&vcpu->arch.nmi_queued, 0); 12415 vcpu->arch.nmi_pending = 0; 12416 vcpu->arch.nmi_injected = false; 12417 kvm_clear_interrupt_queue(vcpu); 12418 kvm_clear_exception_queue(vcpu); 12419 12420 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db)); 12421 kvm_update_dr0123(vcpu); 12422 vcpu->arch.dr6 = DR6_ACTIVE_LOW; 12423 vcpu->arch.dr7 = DR7_FIXED_1; 12424 kvm_update_dr7(vcpu); 12425 12426 vcpu->arch.cr2 = 0; 12427 12428 kvm_make_request(KVM_REQ_EVENT, vcpu); 12429 vcpu->arch.apf.msr_en_val = 0; 12430 vcpu->arch.apf.msr_int_val = 0; 12431 vcpu->arch.st.msr_val = 0; 12432 12433 kvmclock_reset(vcpu); 12434 12435 kvm_clear_async_pf_completion_queue(vcpu); 12436 kvm_async_pf_hash_reset(vcpu); 12437 vcpu->arch.apf.halted = false; 12438 12439 if (vcpu->arch.guest_fpu.fpstate && kvm_mpx_supported()) { 12440 struct fpstate *fpstate = vcpu->arch.guest_fpu.fpstate; 12441 12442 /* 12443 * All paths that lead to INIT are required to load the guest's 12444 * FPU state (because most paths are buried in KVM_RUN). 12445 */ 12446 if (init_event) 12447 kvm_put_guest_fpu(vcpu); 12448 12449 fpstate_clear_xstate_component(fpstate, XFEATURE_BNDREGS); 12450 fpstate_clear_xstate_component(fpstate, XFEATURE_BNDCSR); 12451 12452 if (init_event) 12453 kvm_load_guest_fpu(vcpu); 12454 } 12455 12456 if (!init_event) { 12457 vcpu->arch.smbase = 0x30000; 12458 12459 vcpu->arch.pat = MSR_IA32_CR_PAT_DEFAULT; 12460 12461 vcpu->arch.msr_misc_features_enables = 0; 12462 vcpu->arch.ia32_misc_enable_msr = MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL | 12463 MSR_IA32_MISC_ENABLE_BTS_UNAVAIL; 12464 12465 __kvm_set_xcr(vcpu, 0, XFEATURE_MASK_FP); 12466 __kvm_set_msr(vcpu, MSR_IA32_XSS, 0, true); 12467 } 12468 12469 /* All GPRs except RDX (handled below) are zeroed on RESET/INIT. */ 12470 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs)); 12471 kvm_register_mark_dirty(vcpu, VCPU_REGS_RSP); 12472 12473 /* 12474 * Fall back to KVM's default Family/Model/Stepping of 0x600 (P6/Athlon) 12475 * if no CPUID match is found. Note, it's impossible to get a match at 12476 * RESET since KVM emulates RESET before exposing the vCPU to userspace, 12477 * i.e. it's impossible for kvm_find_cpuid_entry() to find a valid entry 12478 * on RESET. But, go through the motions in case that's ever remedied. 12479 */ 12480 cpuid_0x1 = kvm_find_cpuid_entry(vcpu, 1); 12481 kvm_rdx_write(vcpu, cpuid_0x1 ? cpuid_0x1->eax : 0x600); 12482 12483 kvm_x86_call(vcpu_reset)(vcpu, init_event); 12484 12485 kvm_set_rflags(vcpu, X86_EFLAGS_FIXED); 12486 kvm_rip_write(vcpu, 0xfff0); 12487 12488 vcpu->arch.cr3 = 0; 12489 kvm_register_mark_dirty(vcpu, VCPU_EXREG_CR3); 12490 12491 /* 12492 * CR0.CD/NW are set on RESET, preserved on INIT. Note, some versions 12493 * of Intel's SDM list CD/NW as being set on INIT, but they contradict 12494 * (or qualify) that with a footnote stating that CD/NW are preserved. 12495 */ 12496 new_cr0 = X86_CR0_ET; 12497 if (init_event) 12498 new_cr0 |= (old_cr0 & (X86_CR0_NW | X86_CR0_CD)); 12499 else 12500 new_cr0 |= X86_CR0_NW | X86_CR0_CD; 12501 12502 kvm_x86_call(set_cr0)(vcpu, new_cr0); 12503 kvm_x86_call(set_cr4)(vcpu, 0); 12504 kvm_x86_call(set_efer)(vcpu, 0); 12505 kvm_x86_call(update_exception_bitmap)(vcpu); 12506 12507 /* 12508 * On the standard CR0/CR4/EFER modification paths, there are several 12509 * complex conditions determining whether the MMU has to be reset and/or 12510 * which PCIDs have to be flushed. However, CR0.WP and the paging-related 12511 * bits in CR4 and EFER are irrelevant if CR0.PG was '0'; and a reset+flush 12512 * is needed anyway if CR0.PG was '1' (which can only happen for INIT, as 12513 * CR0 will be '0' prior to RESET). So we only need to check CR0.PG here. 12514 */ 12515 if (old_cr0 & X86_CR0_PG) { 12516 kvm_make_request(KVM_REQ_TLB_FLUSH_GUEST, vcpu); 12517 kvm_mmu_reset_context(vcpu); 12518 } 12519 12520 /* 12521 * Intel's SDM states that all TLB entries are flushed on INIT. AMD's 12522 * APM states the TLBs are untouched by INIT, but it also states that 12523 * the TLBs are flushed on "External initialization of the processor." 12524 * Flush the guest TLB regardless of vendor, there is no meaningful 12525 * benefit in relying on the guest to flush the TLB immediately after 12526 * INIT. A spurious TLB flush is benign and likely negligible from a 12527 * performance perspective. 12528 */ 12529 if (init_event) 12530 kvm_make_request(KVM_REQ_TLB_FLUSH_GUEST, vcpu); 12531 } 12532 EXPORT_SYMBOL_GPL(kvm_vcpu_reset); 12533 12534 void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector) 12535 { 12536 struct kvm_segment cs; 12537 12538 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS); 12539 cs.selector = vector << 8; 12540 cs.base = vector << 12; 12541 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS); 12542 kvm_rip_write(vcpu, 0); 12543 } 12544 EXPORT_SYMBOL_GPL(kvm_vcpu_deliver_sipi_vector); 12545 12546 void kvm_arch_enable_virtualization(void) 12547 { 12548 cpu_emergency_register_virt_callback(kvm_x86_ops.emergency_disable_virtualization_cpu); 12549 } 12550 12551 void kvm_arch_disable_virtualization(void) 12552 { 12553 cpu_emergency_unregister_virt_callback(kvm_x86_ops.emergency_disable_virtualization_cpu); 12554 } 12555 12556 int kvm_arch_enable_virtualization_cpu(void) 12557 { 12558 struct kvm *kvm; 12559 struct kvm_vcpu *vcpu; 12560 unsigned long i; 12561 int ret; 12562 u64 local_tsc; 12563 u64 max_tsc = 0; 12564 bool stable, backwards_tsc = false; 12565 12566 kvm_user_return_msr_cpu_online(); 12567 12568 ret = kvm_x86_check_processor_compatibility(); 12569 if (ret) 12570 return ret; 12571 12572 ret = kvm_x86_call(enable_virtualization_cpu)(); 12573 if (ret != 0) 12574 return ret; 12575 12576 local_tsc = rdtsc(); 12577 stable = !kvm_check_tsc_unstable(); 12578 list_for_each_entry(kvm, &vm_list, vm_list) { 12579 kvm_for_each_vcpu(i, vcpu, kvm) { 12580 if (!stable && vcpu->cpu == smp_processor_id()) 12581 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 12582 if (stable && vcpu->arch.last_host_tsc > local_tsc) { 12583 backwards_tsc = true; 12584 if (vcpu->arch.last_host_tsc > max_tsc) 12585 max_tsc = vcpu->arch.last_host_tsc; 12586 } 12587 } 12588 } 12589 12590 /* 12591 * Sometimes, even reliable TSCs go backwards. This happens on 12592 * platforms that reset TSC during suspend or hibernate actions, but 12593 * maintain synchronization. We must compensate. Fortunately, we can 12594 * detect that condition here, which happens early in CPU bringup, 12595 * before any KVM threads can be running. Unfortunately, we can't 12596 * bring the TSCs fully up to date with real time, as we aren't yet far 12597 * enough into CPU bringup that we know how much real time has actually 12598 * elapsed; our helper function, ktime_get_boottime_ns() will be using boot 12599 * variables that haven't been updated yet. 12600 * 12601 * So we simply find the maximum observed TSC above, then record the 12602 * adjustment to TSC in each VCPU. When the VCPU later gets loaded, 12603 * the adjustment will be applied. Note that we accumulate 12604 * adjustments, in case multiple suspend cycles happen before some VCPU 12605 * gets a chance to run again. In the event that no KVM threads get a 12606 * chance to run, we will miss the entire elapsed period, as we'll have 12607 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may 12608 * loose cycle time. This isn't too big a deal, since the loss will be 12609 * uniform across all VCPUs (not to mention the scenario is extremely 12610 * unlikely). It is possible that a second hibernate recovery happens 12611 * much faster than a first, causing the observed TSC here to be 12612 * smaller; this would require additional padding adjustment, which is 12613 * why we set last_host_tsc to the local tsc observed here. 12614 * 12615 * N.B. - this code below runs only on platforms with reliable TSC, 12616 * as that is the only way backwards_tsc is set above. Also note 12617 * that this runs for ALL vcpus, which is not a bug; all VCPUs should 12618 * have the same delta_cyc adjustment applied if backwards_tsc 12619 * is detected. Note further, this adjustment is only done once, 12620 * as we reset last_host_tsc on all VCPUs to stop this from being 12621 * called multiple times (one for each physical CPU bringup). 12622 * 12623 * Platforms with unreliable TSCs don't have to deal with this, they 12624 * will be compensated by the logic in vcpu_load, which sets the TSC to 12625 * catchup mode. This will catchup all VCPUs to real time, but cannot 12626 * guarantee that they stay in perfect synchronization. 12627 */ 12628 if (backwards_tsc) { 12629 u64 delta_cyc = max_tsc - local_tsc; 12630 list_for_each_entry(kvm, &vm_list, vm_list) { 12631 kvm->arch.backwards_tsc_observed = true; 12632 kvm_for_each_vcpu(i, vcpu, kvm) { 12633 vcpu->arch.tsc_offset_adjustment += delta_cyc; 12634 vcpu->arch.last_host_tsc = local_tsc; 12635 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu); 12636 } 12637 12638 /* 12639 * We have to disable TSC offset matching.. if you were 12640 * booting a VM while issuing an S4 host suspend.... 12641 * you may have some problem. Solving this issue is 12642 * left as an exercise to the reader. 12643 */ 12644 kvm->arch.last_tsc_nsec = 0; 12645 kvm->arch.last_tsc_write = 0; 12646 } 12647 12648 } 12649 return 0; 12650 } 12651 12652 void kvm_arch_disable_virtualization_cpu(void) 12653 { 12654 kvm_x86_call(disable_virtualization_cpu)(); 12655 drop_user_return_notifiers(); 12656 } 12657 12658 bool kvm_vcpu_is_reset_bsp(struct kvm_vcpu *vcpu) 12659 { 12660 return vcpu->kvm->arch.bsp_vcpu_id == vcpu->vcpu_id; 12661 } 12662 12663 bool kvm_vcpu_is_bsp(struct kvm_vcpu *vcpu) 12664 { 12665 return (vcpu->arch.apic_base & MSR_IA32_APICBASE_BSP) != 0; 12666 } 12667 12668 void kvm_arch_free_vm(struct kvm *kvm) 12669 { 12670 #if IS_ENABLED(CONFIG_HYPERV) 12671 kfree(kvm->arch.hv_pa_pg); 12672 #endif 12673 __kvm_arch_free_vm(kvm); 12674 } 12675 12676 12677 int kvm_arch_init_vm(struct kvm *kvm, unsigned long type) 12678 { 12679 int ret; 12680 unsigned long flags; 12681 12682 if (!kvm_is_vm_type_supported(type)) 12683 return -EINVAL; 12684 12685 kvm->arch.vm_type = type; 12686 kvm->arch.has_private_mem = 12687 (type == KVM_X86_SW_PROTECTED_VM); 12688 /* Decided by the vendor code for other VM types. */ 12689 kvm->arch.pre_fault_allowed = 12690 type == KVM_X86_DEFAULT_VM || type == KVM_X86_SW_PROTECTED_VM; 12691 12692 ret = kvm_page_track_init(kvm); 12693 if (ret) 12694 goto out; 12695 12696 kvm_mmu_init_vm(kvm); 12697 12698 ret = kvm_x86_call(vm_init)(kvm); 12699 if (ret) 12700 goto out_uninit_mmu; 12701 12702 INIT_HLIST_HEAD(&kvm->arch.mask_notifier_list); 12703 atomic_set(&kvm->arch.noncoherent_dma_count, 0); 12704 12705 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */ 12706 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap); 12707 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */ 12708 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID, 12709 &kvm->arch.irq_sources_bitmap); 12710 12711 raw_spin_lock_init(&kvm->arch.tsc_write_lock); 12712 mutex_init(&kvm->arch.apic_map_lock); 12713 seqcount_raw_spinlock_init(&kvm->arch.pvclock_sc, &kvm->arch.tsc_write_lock); 12714 kvm->arch.kvmclock_offset = -get_kvmclock_base_ns(); 12715 12716 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags); 12717 pvclock_update_vm_gtod_copy(kvm); 12718 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags); 12719 12720 kvm->arch.default_tsc_khz = max_tsc_khz ? : tsc_khz; 12721 kvm->arch.apic_bus_cycle_ns = APIC_BUS_CYCLE_NS_DEFAULT; 12722 kvm->arch.guest_can_read_msr_platform_info = true; 12723 kvm->arch.enable_pmu = enable_pmu; 12724 12725 #if IS_ENABLED(CONFIG_HYPERV) 12726 spin_lock_init(&kvm->arch.hv_root_tdp_lock); 12727 kvm->arch.hv_root_tdp = INVALID_PAGE; 12728 #endif 12729 12730 INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn); 12731 INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn); 12732 12733 kvm_apicv_init(kvm); 12734 kvm_hv_init_vm(kvm); 12735 kvm_xen_init_vm(kvm); 12736 12737 if (ignore_msrs && !report_ignored_msrs) { 12738 pr_warn_once("Running KVM with ignore_msrs=1 and report_ignored_msrs=0 is not a\n" 12739 "a supported configuration. Lying to the guest about the existence of MSRs\n" 12740 "may cause the guest operating system to hang or produce errors. If a guest\n" 12741 "does not run without ignore_msrs=1, please report it to kvm@vger.kernel.org.\n"); 12742 } 12743 12744 return 0; 12745 12746 out_uninit_mmu: 12747 kvm_mmu_uninit_vm(kvm); 12748 kvm_page_track_cleanup(kvm); 12749 out: 12750 return ret; 12751 } 12752 12753 int kvm_arch_post_init_vm(struct kvm *kvm) 12754 { 12755 once_init(&kvm->arch.nx_once); 12756 return 0; 12757 } 12758 12759 static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu) 12760 { 12761 vcpu_load(vcpu); 12762 kvm_mmu_unload(vcpu); 12763 vcpu_put(vcpu); 12764 } 12765 12766 static void kvm_unload_vcpu_mmus(struct kvm *kvm) 12767 { 12768 unsigned long i; 12769 struct kvm_vcpu *vcpu; 12770 12771 kvm_for_each_vcpu(i, vcpu, kvm) { 12772 kvm_clear_async_pf_completion_queue(vcpu); 12773 kvm_unload_vcpu_mmu(vcpu); 12774 } 12775 } 12776 12777 void kvm_arch_sync_events(struct kvm *kvm) 12778 { 12779 cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work); 12780 cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work); 12781 kvm_free_pit(kvm); 12782 } 12783 12784 /** 12785 * __x86_set_memory_region: Setup KVM internal memory slot 12786 * 12787 * @kvm: the kvm pointer to the VM. 12788 * @id: the slot ID to setup. 12789 * @gpa: the GPA to install the slot (unused when @size == 0). 12790 * @size: the size of the slot. Set to zero to uninstall a slot. 12791 * 12792 * This function helps to setup a KVM internal memory slot. Specify 12793 * @size > 0 to install a new slot, while @size == 0 to uninstall a 12794 * slot. The return code can be one of the following: 12795 * 12796 * HVA: on success (uninstall will return a bogus HVA) 12797 * -errno: on error 12798 * 12799 * The caller should always use IS_ERR() to check the return value 12800 * before use. Note, the KVM internal memory slots are guaranteed to 12801 * remain valid and unchanged until the VM is destroyed, i.e., the 12802 * GPA->HVA translation will not change. However, the HVA is a user 12803 * address, i.e. its accessibility is not guaranteed, and must be 12804 * accessed via __copy_{to,from}_user(). 12805 */ 12806 void __user * __x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, 12807 u32 size) 12808 { 12809 int i, r; 12810 unsigned long hva, old_npages; 12811 struct kvm_memslots *slots = kvm_memslots(kvm); 12812 struct kvm_memory_slot *slot; 12813 12814 lockdep_assert_held(&kvm->slots_lock); 12815 12816 if (WARN_ON(id >= KVM_MEM_SLOTS_NUM)) 12817 return ERR_PTR_USR(-EINVAL); 12818 12819 slot = id_to_memslot(slots, id); 12820 if (size) { 12821 if (slot && slot->npages) 12822 return ERR_PTR_USR(-EEXIST); 12823 12824 /* 12825 * MAP_SHARED to prevent internal slot pages from being moved 12826 * by fork()/COW. 12827 */ 12828 hva = vm_mmap(NULL, 0, size, PROT_READ | PROT_WRITE, 12829 MAP_SHARED | MAP_ANONYMOUS, 0); 12830 if (IS_ERR_VALUE(hva)) 12831 return (void __user *)hva; 12832 } else { 12833 if (!slot || !slot->npages) 12834 return NULL; 12835 12836 old_npages = slot->npages; 12837 hva = slot->userspace_addr; 12838 } 12839 12840 for (i = 0; i < kvm_arch_nr_memslot_as_ids(kvm); i++) { 12841 struct kvm_userspace_memory_region2 m; 12842 12843 m.slot = id | (i << 16); 12844 m.flags = 0; 12845 m.guest_phys_addr = gpa; 12846 m.userspace_addr = hva; 12847 m.memory_size = size; 12848 r = kvm_set_internal_memslot(kvm, &m); 12849 if (r < 0) 12850 return ERR_PTR_USR(r); 12851 } 12852 12853 if (!size) 12854 vm_munmap(hva, old_npages * PAGE_SIZE); 12855 12856 return (void __user *)hva; 12857 } 12858 EXPORT_SYMBOL_GPL(__x86_set_memory_region); 12859 12860 void kvm_arch_pre_destroy_vm(struct kvm *kvm) 12861 { 12862 kvm_mmu_pre_destroy_vm(kvm); 12863 } 12864 12865 void kvm_arch_destroy_vm(struct kvm *kvm) 12866 { 12867 if (current->mm == kvm->mm) { 12868 /* 12869 * Free memory regions allocated on behalf of userspace, 12870 * unless the memory map has changed due to process exit 12871 * or fd copying. 12872 */ 12873 mutex_lock(&kvm->slots_lock); 12874 __x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT, 12875 0, 0); 12876 __x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT, 12877 0, 0); 12878 __x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, 0, 0); 12879 mutex_unlock(&kvm->slots_lock); 12880 } 12881 kvm_unload_vcpu_mmus(kvm); 12882 kvm_x86_call(vm_destroy)(kvm); 12883 kvm_free_msr_filter(srcu_dereference_check(kvm->arch.msr_filter, &kvm->srcu, 1)); 12884 kvm_pic_destroy(kvm); 12885 kvm_ioapic_destroy(kvm); 12886 kvm_destroy_vcpus(kvm); 12887 kvfree(rcu_dereference_check(kvm->arch.apic_map, 1)); 12888 kfree(srcu_dereference_check(kvm->arch.pmu_event_filter, &kvm->srcu, 1)); 12889 kvm_mmu_uninit_vm(kvm); 12890 kvm_page_track_cleanup(kvm); 12891 kvm_xen_destroy_vm(kvm); 12892 kvm_hv_destroy_vm(kvm); 12893 } 12894 12895 static void memslot_rmap_free(struct kvm_memory_slot *slot) 12896 { 12897 int i; 12898 12899 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) { 12900 vfree(slot->arch.rmap[i]); 12901 slot->arch.rmap[i] = NULL; 12902 } 12903 } 12904 12905 void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *slot) 12906 { 12907 int i; 12908 12909 memslot_rmap_free(slot); 12910 12911 for (i = 1; i < KVM_NR_PAGE_SIZES; ++i) { 12912 vfree(slot->arch.lpage_info[i - 1]); 12913 slot->arch.lpage_info[i - 1] = NULL; 12914 } 12915 12916 kvm_page_track_free_memslot(slot); 12917 } 12918 12919 int memslot_rmap_alloc(struct kvm_memory_slot *slot, unsigned long npages) 12920 { 12921 const int sz = sizeof(*slot->arch.rmap[0]); 12922 int i; 12923 12924 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) { 12925 int level = i + 1; 12926 int lpages = __kvm_mmu_slot_lpages(slot, npages, level); 12927 12928 if (slot->arch.rmap[i]) 12929 continue; 12930 12931 slot->arch.rmap[i] = __vcalloc(lpages, sz, GFP_KERNEL_ACCOUNT); 12932 if (!slot->arch.rmap[i]) { 12933 memslot_rmap_free(slot); 12934 return -ENOMEM; 12935 } 12936 } 12937 12938 return 0; 12939 } 12940 12941 static int kvm_alloc_memslot_metadata(struct kvm *kvm, 12942 struct kvm_memory_slot *slot) 12943 { 12944 unsigned long npages = slot->npages; 12945 int i, r; 12946 12947 /* 12948 * Clear out the previous array pointers for the KVM_MR_MOVE case. The 12949 * old arrays will be freed by kvm_set_memory_region() if installing 12950 * the new memslot is successful. 12951 */ 12952 memset(&slot->arch, 0, sizeof(slot->arch)); 12953 12954 if (kvm_memslots_have_rmaps(kvm)) { 12955 r = memslot_rmap_alloc(slot, npages); 12956 if (r) 12957 return r; 12958 } 12959 12960 for (i = 1; i < KVM_NR_PAGE_SIZES; ++i) { 12961 struct kvm_lpage_info *linfo; 12962 unsigned long ugfn; 12963 int lpages; 12964 int level = i + 1; 12965 12966 lpages = __kvm_mmu_slot_lpages(slot, npages, level); 12967 12968 linfo = __vcalloc(lpages, sizeof(*linfo), GFP_KERNEL_ACCOUNT); 12969 if (!linfo) 12970 goto out_free; 12971 12972 slot->arch.lpage_info[i - 1] = linfo; 12973 12974 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1)) 12975 linfo[0].disallow_lpage = 1; 12976 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1)) 12977 linfo[lpages - 1].disallow_lpage = 1; 12978 ugfn = slot->userspace_addr >> PAGE_SHIFT; 12979 /* 12980 * If the gfn and userspace address are not aligned wrt each 12981 * other, disable large page support for this slot. 12982 */ 12983 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1)) { 12984 unsigned long j; 12985 12986 for (j = 0; j < lpages; ++j) 12987 linfo[j].disallow_lpage = 1; 12988 } 12989 } 12990 12991 #ifdef CONFIG_KVM_GENERIC_MEMORY_ATTRIBUTES 12992 kvm_mmu_init_memslot_memory_attributes(kvm, slot); 12993 #endif 12994 12995 if (kvm_page_track_create_memslot(kvm, slot, npages)) 12996 goto out_free; 12997 12998 return 0; 12999 13000 out_free: 13001 memslot_rmap_free(slot); 13002 13003 for (i = 1; i < KVM_NR_PAGE_SIZES; ++i) { 13004 vfree(slot->arch.lpage_info[i - 1]); 13005 slot->arch.lpage_info[i - 1] = NULL; 13006 } 13007 return -ENOMEM; 13008 } 13009 13010 void kvm_arch_memslots_updated(struct kvm *kvm, u64 gen) 13011 { 13012 struct kvm_vcpu *vcpu; 13013 unsigned long i; 13014 13015 /* 13016 * memslots->generation has been incremented. 13017 * mmio generation may have reached its maximum value. 13018 */ 13019 kvm_mmu_invalidate_mmio_sptes(kvm, gen); 13020 13021 /* Force re-initialization of steal_time cache */ 13022 kvm_for_each_vcpu(i, vcpu, kvm) 13023 kvm_vcpu_kick(vcpu); 13024 } 13025 13026 int kvm_arch_prepare_memory_region(struct kvm *kvm, 13027 const struct kvm_memory_slot *old, 13028 struct kvm_memory_slot *new, 13029 enum kvm_mr_change change) 13030 { 13031 /* 13032 * KVM doesn't support moving memslots when there are external page 13033 * trackers attached to the VM, i.e. if KVMGT is in use. 13034 */ 13035 if (change == KVM_MR_MOVE && kvm_page_track_has_external_user(kvm)) 13036 return -EINVAL; 13037 13038 if (change == KVM_MR_CREATE || change == KVM_MR_MOVE) { 13039 if ((new->base_gfn + new->npages - 1) > kvm_mmu_max_gfn()) 13040 return -EINVAL; 13041 13042 if (kvm_is_gfn_alias(kvm, new->base_gfn + new->npages - 1)) 13043 return -EINVAL; 13044 13045 return kvm_alloc_memslot_metadata(kvm, new); 13046 } 13047 13048 if (change == KVM_MR_FLAGS_ONLY) 13049 memcpy(&new->arch, &old->arch, sizeof(old->arch)); 13050 else if (WARN_ON_ONCE(change != KVM_MR_DELETE)) 13051 return -EIO; 13052 13053 return 0; 13054 } 13055 13056 13057 static void kvm_mmu_update_cpu_dirty_logging(struct kvm *kvm, bool enable) 13058 { 13059 int nr_slots; 13060 13061 if (!kvm_x86_ops.cpu_dirty_log_size) 13062 return; 13063 13064 nr_slots = atomic_read(&kvm->nr_memslots_dirty_logging); 13065 if ((enable && nr_slots == 1) || !nr_slots) 13066 kvm_make_all_cpus_request(kvm, KVM_REQ_UPDATE_CPU_DIRTY_LOGGING); 13067 } 13068 13069 static void kvm_mmu_slot_apply_flags(struct kvm *kvm, 13070 struct kvm_memory_slot *old, 13071 const struct kvm_memory_slot *new, 13072 enum kvm_mr_change change) 13073 { 13074 u32 old_flags = old ? old->flags : 0; 13075 u32 new_flags = new ? new->flags : 0; 13076 bool log_dirty_pages = new_flags & KVM_MEM_LOG_DIRTY_PAGES; 13077 13078 /* 13079 * Update CPU dirty logging if dirty logging is being toggled. This 13080 * applies to all operations. 13081 */ 13082 if ((old_flags ^ new_flags) & KVM_MEM_LOG_DIRTY_PAGES) 13083 kvm_mmu_update_cpu_dirty_logging(kvm, log_dirty_pages); 13084 13085 /* 13086 * Nothing more to do for RO slots (which can't be dirtied and can't be 13087 * made writable) or CREATE/MOVE/DELETE of a slot. 13088 * 13089 * For a memslot with dirty logging disabled: 13090 * CREATE: No dirty mappings will already exist. 13091 * MOVE/DELETE: The old mappings will already have been cleaned up by 13092 * kvm_arch_flush_shadow_memslot() 13093 * 13094 * For a memslot with dirty logging enabled: 13095 * CREATE: No shadow pages exist, thus nothing to write-protect 13096 * and no dirty bits to clear. 13097 * MOVE/DELETE: The old mappings will already have been cleaned up by 13098 * kvm_arch_flush_shadow_memslot(). 13099 */ 13100 if ((change != KVM_MR_FLAGS_ONLY) || (new_flags & KVM_MEM_READONLY)) 13101 return; 13102 13103 /* 13104 * READONLY and non-flags changes were filtered out above, and the only 13105 * other flag is LOG_DIRTY_PAGES, i.e. something is wrong if dirty 13106 * logging isn't being toggled on or off. 13107 */ 13108 if (WARN_ON_ONCE(!((old_flags ^ new_flags) & KVM_MEM_LOG_DIRTY_PAGES))) 13109 return; 13110 13111 if (!log_dirty_pages) { 13112 /* 13113 * Recover huge page mappings in the slot now that dirty logging 13114 * is disabled, i.e. now that KVM does not have to track guest 13115 * writes at 4KiB granularity. 13116 * 13117 * Dirty logging might be disabled by userspace if an ongoing VM 13118 * live migration is cancelled and the VM must continue running 13119 * on the source. 13120 */ 13121 kvm_mmu_recover_huge_pages(kvm, new); 13122 } else { 13123 /* 13124 * Initially-all-set does not require write protecting any page, 13125 * because they're all assumed to be dirty. 13126 */ 13127 if (kvm_dirty_log_manual_protect_and_init_set(kvm)) 13128 return; 13129 13130 if (READ_ONCE(eager_page_split)) 13131 kvm_mmu_slot_try_split_huge_pages(kvm, new, PG_LEVEL_4K); 13132 13133 if (kvm_x86_ops.cpu_dirty_log_size) { 13134 kvm_mmu_slot_leaf_clear_dirty(kvm, new); 13135 kvm_mmu_slot_remove_write_access(kvm, new, PG_LEVEL_2M); 13136 } else { 13137 kvm_mmu_slot_remove_write_access(kvm, new, PG_LEVEL_4K); 13138 } 13139 13140 /* 13141 * Unconditionally flush the TLBs after enabling dirty logging. 13142 * A flush is almost always going to be necessary (see below), 13143 * and unconditionally flushing allows the helpers to omit 13144 * the subtly complex checks when removing write access. 13145 * 13146 * Do the flush outside of mmu_lock to reduce the amount of 13147 * time mmu_lock is held. Flushing after dropping mmu_lock is 13148 * safe as KVM only needs to guarantee the slot is fully 13149 * write-protected before returning to userspace, i.e. before 13150 * userspace can consume the dirty status. 13151 * 13152 * Flushing outside of mmu_lock requires KVM to be careful when 13153 * making decisions based on writable status of an SPTE, e.g. a 13154 * !writable SPTE doesn't guarantee a CPU can't perform writes. 13155 * 13156 * Specifically, KVM also write-protects guest page tables to 13157 * monitor changes when using shadow paging, and must guarantee 13158 * no CPUs can write to those page before mmu_lock is dropped. 13159 * Because CPUs may have stale TLB entries at this point, a 13160 * !writable SPTE doesn't guarantee CPUs can't perform writes. 13161 * 13162 * KVM also allows making SPTES writable outside of mmu_lock, 13163 * e.g. to allow dirty logging without taking mmu_lock. 13164 * 13165 * To handle these scenarios, KVM uses a separate software-only 13166 * bit (MMU-writable) to track if a SPTE is !writable due to 13167 * a guest page table being write-protected (KVM clears the 13168 * MMU-writable flag when write-protecting for shadow paging). 13169 * 13170 * The use of MMU-writable is also the primary motivation for 13171 * the unconditional flush. Because KVM must guarantee that a 13172 * CPU doesn't contain stale, writable TLB entries for a 13173 * !MMU-writable SPTE, KVM must flush if it encounters any 13174 * MMU-writable SPTE regardless of whether the actual hardware 13175 * writable bit was set. I.e. KVM is almost guaranteed to need 13176 * to flush, while unconditionally flushing allows the "remove 13177 * write access" helpers to ignore MMU-writable entirely. 13178 * 13179 * See is_writable_pte() for more details (the case involving 13180 * access-tracked SPTEs is particularly relevant). 13181 */ 13182 kvm_flush_remote_tlbs_memslot(kvm, new); 13183 } 13184 } 13185 13186 void kvm_arch_commit_memory_region(struct kvm *kvm, 13187 struct kvm_memory_slot *old, 13188 const struct kvm_memory_slot *new, 13189 enum kvm_mr_change change) 13190 { 13191 if (change == KVM_MR_DELETE) 13192 kvm_page_track_delete_slot(kvm, old); 13193 13194 if (!kvm->arch.n_requested_mmu_pages && 13195 (change == KVM_MR_CREATE || change == KVM_MR_DELETE)) { 13196 unsigned long nr_mmu_pages; 13197 13198 nr_mmu_pages = kvm->nr_memslot_pages / KVM_MEMSLOT_PAGES_TO_MMU_PAGES_RATIO; 13199 nr_mmu_pages = max(nr_mmu_pages, KVM_MIN_ALLOC_MMU_PAGES); 13200 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages); 13201 } 13202 13203 kvm_mmu_slot_apply_flags(kvm, old, new, change); 13204 13205 /* Free the arrays associated with the old memslot. */ 13206 if (change == KVM_MR_MOVE) 13207 kvm_arch_free_memslot(kvm, old); 13208 } 13209 13210 bool kvm_arch_vcpu_in_kernel(struct kvm_vcpu *vcpu) 13211 { 13212 WARN_ON_ONCE(!kvm_arch_pmi_in_guest(vcpu)); 13213 13214 if (vcpu->arch.guest_state_protected) 13215 return true; 13216 13217 return kvm_x86_call(get_cpl)(vcpu) == 0; 13218 } 13219 13220 unsigned long kvm_arch_vcpu_get_ip(struct kvm_vcpu *vcpu) 13221 { 13222 WARN_ON_ONCE(!kvm_arch_pmi_in_guest(vcpu)); 13223 13224 if (vcpu->arch.guest_state_protected) 13225 return 0; 13226 13227 return kvm_rip_read(vcpu); 13228 } 13229 13230 int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu) 13231 { 13232 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE; 13233 } 13234 13235 int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu) 13236 { 13237 return kvm_x86_call(interrupt_allowed)(vcpu, false); 13238 } 13239 13240 unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu) 13241 { 13242 /* Can't read the RIP when guest state is protected, just return 0 */ 13243 if (vcpu->arch.guest_state_protected) 13244 return 0; 13245 13246 if (is_64_bit_mode(vcpu)) 13247 return kvm_rip_read(vcpu); 13248 return (u32)(get_segment_base(vcpu, VCPU_SREG_CS) + 13249 kvm_rip_read(vcpu)); 13250 } 13251 EXPORT_SYMBOL_GPL(kvm_get_linear_rip); 13252 13253 bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip) 13254 { 13255 return kvm_get_linear_rip(vcpu) == linear_rip; 13256 } 13257 EXPORT_SYMBOL_GPL(kvm_is_linear_rip); 13258 13259 unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu) 13260 { 13261 unsigned long rflags; 13262 13263 rflags = kvm_x86_call(get_rflags)(vcpu); 13264 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) 13265 rflags &= ~X86_EFLAGS_TF; 13266 return rflags; 13267 } 13268 EXPORT_SYMBOL_GPL(kvm_get_rflags); 13269 13270 static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags) 13271 { 13272 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP && 13273 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip)) 13274 rflags |= X86_EFLAGS_TF; 13275 kvm_x86_call(set_rflags)(vcpu, rflags); 13276 } 13277 13278 void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags) 13279 { 13280 __kvm_set_rflags(vcpu, rflags); 13281 kvm_make_request(KVM_REQ_EVENT, vcpu); 13282 } 13283 EXPORT_SYMBOL_GPL(kvm_set_rflags); 13284 13285 static inline u32 kvm_async_pf_hash_fn(gfn_t gfn) 13286 { 13287 BUILD_BUG_ON(!is_power_of_2(ASYNC_PF_PER_VCPU)); 13288 13289 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU)); 13290 } 13291 13292 static inline u32 kvm_async_pf_next_probe(u32 key) 13293 { 13294 return (key + 1) & (ASYNC_PF_PER_VCPU - 1); 13295 } 13296 13297 static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn) 13298 { 13299 u32 key = kvm_async_pf_hash_fn(gfn); 13300 13301 while (vcpu->arch.apf.gfns[key] != ~0) 13302 key = kvm_async_pf_next_probe(key); 13303 13304 vcpu->arch.apf.gfns[key] = gfn; 13305 } 13306 13307 static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn) 13308 { 13309 int i; 13310 u32 key = kvm_async_pf_hash_fn(gfn); 13311 13312 for (i = 0; i < ASYNC_PF_PER_VCPU && 13313 (vcpu->arch.apf.gfns[key] != gfn && 13314 vcpu->arch.apf.gfns[key] != ~0); i++) 13315 key = kvm_async_pf_next_probe(key); 13316 13317 return key; 13318 } 13319 13320 bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn) 13321 { 13322 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn; 13323 } 13324 13325 static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn) 13326 { 13327 u32 i, j, k; 13328 13329 i = j = kvm_async_pf_gfn_slot(vcpu, gfn); 13330 13331 if (WARN_ON_ONCE(vcpu->arch.apf.gfns[i] != gfn)) 13332 return; 13333 13334 while (true) { 13335 vcpu->arch.apf.gfns[i] = ~0; 13336 do { 13337 j = kvm_async_pf_next_probe(j); 13338 if (vcpu->arch.apf.gfns[j] == ~0) 13339 return; 13340 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]); 13341 /* 13342 * k lies cyclically in ]i,j] 13343 * | i.k.j | 13344 * |....j i.k.| or |.k..j i...| 13345 */ 13346 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j)); 13347 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j]; 13348 i = j; 13349 } 13350 } 13351 13352 static inline int apf_put_user_notpresent(struct kvm_vcpu *vcpu) 13353 { 13354 u32 reason = KVM_PV_REASON_PAGE_NOT_PRESENT; 13355 13356 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &reason, 13357 sizeof(reason)); 13358 } 13359 13360 static inline int apf_put_user_ready(struct kvm_vcpu *vcpu, u32 token) 13361 { 13362 unsigned int offset = offsetof(struct kvm_vcpu_pv_apf_data, token); 13363 13364 return kvm_write_guest_offset_cached(vcpu->kvm, &vcpu->arch.apf.data, 13365 &token, offset, sizeof(token)); 13366 } 13367 13368 static inline bool apf_pageready_slot_free(struct kvm_vcpu *vcpu) 13369 { 13370 unsigned int offset = offsetof(struct kvm_vcpu_pv_apf_data, token); 13371 u32 val; 13372 13373 if (kvm_read_guest_offset_cached(vcpu->kvm, &vcpu->arch.apf.data, 13374 &val, offset, sizeof(val))) 13375 return false; 13376 13377 return !val; 13378 } 13379 13380 static bool kvm_can_deliver_async_pf(struct kvm_vcpu *vcpu) 13381 { 13382 13383 if (!kvm_pv_async_pf_enabled(vcpu)) 13384 return false; 13385 13386 if (vcpu->arch.apf.send_user_only && 13387 kvm_x86_call(get_cpl)(vcpu) == 0) 13388 return false; 13389 13390 if (is_guest_mode(vcpu)) { 13391 /* 13392 * L1 needs to opt into the special #PF vmexits that are 13393 * used to deliver async page faults. 13394 */ 13395 return vcpu->arch.apf.delivery_as_pf_vmexit; 13396 } else { 13397 /* 13398 * Play it safe in case the guest temporarily disables paging. 13399 * The real mode IDT in particular is unlikely to have a #PF 13400 * exception setup. 13401 */ 13402 return is_paging(vcpu); 13403 } 13404 } 13405 13406 bool kvm_can_do_async_pf(struct kvm_vcpu *vcpu) 13407 { 13408 if (unlikely(!lapic_in_kernel(vcpu) || 13409 kvm_event_needs_reinjection(vcpu) || 13410 kvm_is_exception_pending(vcpu))) 13411 return false; 13412 13413 if (kvm_hlt_in_guest(vcpu->kvm) && !kvm_can_deliver_async_pf(vcpu)) 13414 return false; 13415 13416 /* 13417 * If interrupts are off we cannot even use an artificial 13418 * halt state. 13419 */ 13420 return kvm_arch_interrupt_allowed(vcpu); 13421 } 13422 13423 bool kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu, 13424 struct kvm_async_pf *work) 13425 { 13426 struct x86_exception fault; 13427 13428 trace_kvm_async_pf_not_present(work->arch.token, work->cr2_or_gpa); 13429 kvm_add_async_pf_gfn(vcpu, work->arch.gfn); 13430 13431 if (kvm_can_deliver_async_pf(vcpu) && 13432 !apf_put_user_notpresent(vcpu)) { 13433 fault.vector = PF_VECTOR; 13434 fault.error_code_valid = true; 13435 fault.error_code = 0; 13436 fault.nested_page_fault = false; 13437 fault.address = work->arch.token; 13438 fault.async_page_fault = true; 13439 kvm_inject_page_fault(vcpu, &fault); 13440 return true; 13441 } else { 13442 /* 13443 * It is not possible to deliver a paravirtualized asynchronous 13444 * page fault, but putting the guest in an artificial halt state 13445 * can be beneficial nevertheless: if an interrupt arrives, we 13446 * can deliver it timely and perhaps the guest will schedule 13447 * another process. When the instruction that triggered a page 13448 * fault is retried, hopefully the page will be ready in the host. 13449 */ 13450 kvm_make_request(KVM_REQ_APF_HALT, vcpu); 13451 return false; 13452 } 13453 } 13454 13455 void kvm_arch_async_page_present(struct kvm_vcpu *vcpu, 13456 struct kvm_async_pf *work) 13457 { 13458 struct kvm_lapic_irq irq = { 13459 .delivery_mode = APIC_DM_FIXED, 13460 .vector = vcpu->arch.apf.vec 13461 }; 13462 13463 if (work->wakeup_all) 13464 work->arch.token = ~0; /* broadcast wakeup */ 13465 else 13466 kvm_del_async_pf_gfn(vcpu, work->arch.gfn); 13467 trace_kvm_async_pf_ready(work->arch.token, work->cr2_or_gpa); 13468 13469 if ((work->wakeup_all || work->notpresent_injected) && 13470 kvm_pv_async_pf_enabled(vcpu) && 13471 !apf_put_user_ready(vcpu, work->arch.token)) { 13472 vcpu->arch.apf.pageready_pending = true; 13473 kvm_apic_set_irq(vcpu, &irq, NULL); 13474 } 13475 13476 vcpu->arch.apf.halted = false; 13477 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; 13478 } 13479 13480 void kvm_arch_async_page_present_queued(struct kvm_vcpu *vcpu) 13481 { 13482 kvm_make_request(KVM_REQ_APF_READY, vcpu); 13483 if (!vcpu->arch.apf.pageready_pending) 13484 kvm_vcpu_kick(vcpu); 13485 } 13486 13487 bool kvm_arch_can_dequeue_async_page_present(struct kvm_vcpu *vcpu) 13488 { 13489 if (!kvm_pv_async_pf_enabled(vcpu)) 13490 return true; 13491 else 13492 return kvm_lapic_enabled(vcpu) && apf_pageready_slot_free(vcpu); 13493 } 13494 13495 void kvm_arch_start_assignment(struct kvm *kvm) 13496 { 13497 if (atomic_inc_return(&kvm->arch.assigned_device_count) == 1) 13498 kvm_x86_call(pi_start_assignment)(kvm); 13499 } 13500 EXPORT_SYMBOL_GPL(kvm_arch_start_assignment); 13501 13502 void kvm_arch_end_assignment(struct kvm *kvm) 13503 { 13504 atomic_dec(&kvm->arch.assigned_device_count); 13505 } 13506 EXPORT_SYMBOL_GPL(kvm_arch_end_assignment); 13507 13508 bool noinstr kvm_arch_has_assigned_device(struct kvm *kvm) 13509 { 13510 return raw_atomic_read(&kvm->arch.assigned_device_count); 13511 } 13512 EXPORT_SYMBOL_GPL(kvm_arch_has_assigned_device); 13513 13514 static void kvm_noncoherent_dma_assignment_start_or_stop(struct kvm *kvm) 13515 { 13516 /* 13517 * Non-coherent DMA assignment and de-assignment may affect whether or 13518 * not KVM honors guest PAT, and thus may cause changes in EPT SPTEs 13519 * due to toggling the "ignore PAT" bit. Zap all SPTEs when the first 13520 * (or last) non-coherent device is (un)registered to so that new SPTEs 13521 * with the correct "ignore guest PAT" setting are created. 13522 */ 13523 if (kvm_mmu_may_ignore_guest_pat()) 13524 kvm_zap_gfn_range(kvm, gpa_to_gfn(0), gpa_to_gfn(~0ULL)); 13525 } 13526 13527 void kvm_arch_register_noncoherent_dma(struct kvm *kvm) 13528 { 13529 if (atomic_inc_return(&kvm->arch.noncoherent_dma_count) == 1) 13530 kvm_noncoherent_dma_assignment_start_or_stop(kvm); 13531 } 13532 EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma); 13533 13534 void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm) 13535 { 13536 if (!atomic_dec_return(&kvm->arch.noncoherent_dma_count)) 13537 kvm_noncoherent_dma_assignment_start_or_stop(kvm); 13538 } 13539 EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma); 13540 13541 bool kvm_arch_has_noncoherent_dma(struct kvm *kvm) 13542 { 13543 return atomic_read(&kvm->arch.noncoherent_dma_count); 13544 } 13545 EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma); 13546 13547 bool kvm_arch_has_irq_bypass(void) 13548 { 13549 return enable_apicv && irq_remapping_cap(IRQ_POSTING_CAP); 13550 } 13551 13552 int kvm_arch_irq_bypass_add_producer(struct irq_bypass_consumer *cons, 13553 struct irq_bypass_producer *prod) 13554 { 13555 struct kvm_kernel_irqfd *irqfd = 13556 container_of(cons, struct kvm_kernel_irqfd, consumer); 13557 int ret; 13558 13559 irqfd->producer = prod; 13560 kvm_arch_start_assignment(irqfd->kvm); 13561 ret = kvm_x86_call(pi_update_irte)(irqfd->kvm, 13562 prod->irq, irqfd->gsi, 1); 13563 if (ret) 13564 kvm_arch_end_assignment(irqfd->kvm); 13565 13566 return ret; 13567 } 13568 13569 void kvm_arch_irq_bypass_del_producer(struct irq_bypass_consumer *cons, 13570 struct irq_bypass_producer *prod) 13571 { 13572 int ret; 13573 struct kvm_kernel_irqfd *irqfd = 13574 container_of(cons, struct kvm_kernel_irqfd, consumer); 13575 13576 WARN_ON(irqfd->producer != prod); 13577 irqfd->producer = NULL; 13578 13579 /* 13580 * When producer of consumer is unregistered, we change back to 13581 * remapped mode, so we can re-use the current implementation 13582 * when the irq is masked/disabled or the consumer side (KVM 13583 * int this case doesn't want to receive the interrupts. 13584 */ 13585 ret = kvm_x86_call(pi_update_irte)(irqfd->kvm, 13586 prod->irq, irqfd->gsi, 0); 13587 if (ret) 13588 printk(KERN_INFO "irq bypass consumer (token %p) unregistration" 13589 " fails: %d\n", irqfd->consumer.token, ret); 13590 13591 kvm_arch_end_assignment(irqfd->kvm); 13592 } 13593 13594 int kvm_arch_update_irqfd_routing(struct kvm *kvm, unsigned int host_irq, 13595 uint32_t guest_irq, bool set) 13596 { 13597 return kvm_x86_call(pi_update_irte)(kvm, host_irq, guest_irq, set); 13598 } 13599 13600 bool kvm_arch_irqfd_route_changed(struct kvm_kernel_irq_routing_entry *old, 13601 struct kvm_kernel_irq_routing_entry *new) 13602 { 13603 if (new->type != KVM_IRQ_ROUTING_MSI) 13604 return true; 13605 13606 return !!memcmp(&old->msi, &new->msi, sizeof(new->msi)); 13607 } 13608 13609 bool kvm_vector_hashing_enabled(void) 13610 { 13611 return vector_hashing; 13612 } 13613 13614 bool kvm_arch_no_poll(struct kvm_vcpu *vcpu) 13615 { 13616 return (vcpu->arch.msr_kvm_poll_control & 1) == 0; 13617 } 13618 EXPORT_SYMBOL_GPL(kvm_arch_no_poll); 13619 13620 #ifdef CONFIG_HAVE_KVM_ARCH_GMEM_PREPARE 13621 int kvm_arch_gmem_prepare(struct kvm *kvm, gfn_t gfn, kvm_pfn_t pfn, int max_order) 13622 { 13623 return kvm_x86_call(gmem_prepare)(kvm, pfn, gfn, max_order); 13624 } 13625 #endif 13626 13627 #ifdef CONFIG_HAVE_KVM_ARCH_GMEM_INVALIDATE 13628 void kvm_arch_gmem_invalidate(kvm_pfn_t start, kvm_pfn_t end) 13629 { 13630 kvm_x86_call(gmem_invalidate)(start, end); 13631 } 13632 #endif 13633 13634 int kvm_spec_ctrl_test_value(u64 value) 13635 { 13636 /* 13637 * test that setting IA32_SPEC_CTRL to given value 13638 * is allowed by the host processor 13639 */ 13640 13641 u64 saved_value; 13642 unsigned long flags; 13643 int ret = 0; 13644 13645 local_irq_save(flags); 13646 13647 if (rdmsrl_safe(MSR_IA32_SPEC_CTRL, &saved_value)) 13648 ret = 1; 13649 else if (wrmsrl_safe(MSR_IA32_SPEC_CTRL, value)) 13650 ret = 1; 13651 else 13652 wrmsrl(MSR_IA32_SPEC_CTRL, saved_value); 13653 13654 local_irq_restore(flags); 13655 13656 return ret; 13657 } 13658 EXPORT_SYMBOL_GPL(kvm_spec_ctrl_test_value); 13659 13660 void kvm_fixup_and_inject_pf_error(struct kvm_vcpu *vcpu, gva_t gva, u16 error_code) 13661 { 13662 struct kvm_mmu *mmu = vcpu->arch.walk_mmu; 13663 struct x86_exception fault; 13664 u64 access = error_code & 13665 (PFERR_WRITE_MASK | PFERR_FETCH_MASK | PFERR_USER_MASK); 13666 13667 if (!(error_code & PFERR_PRESENT_MASK) || 13668 mmu->gva_to_gpa(vcpu, mmu, gva, access, &fault) != INVALID_GPA) { 13669 /* 13670 * If vcpu->arch.walk_mmu->gva_to_gpa succeeded, the page 13671 * tables probably do not match the TLB. Just proceed 13672 * with the error code that the processor gave. 13673 */ 13674 fault.vector = PF_VECTOR; 13675 fault.error_code_valid = true; 13676 fault.error_code = error_code; 13677 fault.nested_page_fault = false; 13678 fault.address = gva; 13679 fault.async_page_fault = false; 13680 } 13681 vcpu->arch.walk_mmu->inject_page_fault(vcpu, &fault); 13682 } 13683 EXPORT_SYMBOL_GPL(kvm_fixup_and_inject_pf_error); 13684 13685 /* 13686 * Handles kvm_read/write_guest_virt*() result and either injects #PF or returns 13687 * KVM_EXIT_INTERNAL_ERROR for cases not currently handled by KVM. Return value 13688 * indicates whether exit to userspace is needed. 13689 */ 13690 int kvm_handle_memory_failure(struct kvm_vcpu *vcpu, int r, 13691 struct x86_exception *e) 13692 { 13693 if (r == X86EMUL_PROPAGATE_FAULT) { 13694 if (KVM_BUG_ON(!e, vcpu->kvm)) 13695 return -EIO; 13696 13697 kvm_inject_emulated_page_fault(vcpu, e); 13698 return 1; 13699 } 13700 13701 /* 13702 * In case kvm_read/write_guest_virt*() failed with X86EMUL_IO_NEEDED 13703 * while handling a VMX instruction KVM could've handled the request 13704 * correctly by exiting to userspace and performing I/O but there 13705 * doesn't seem to be a real use-case behind such requests, just return 13706 * KVM_EXIT_INTERNAL_ERROR for now. 13707 */ 13708 kvm_prepare_emulation_failure_exit(vcpu); 13709 13710 return 0; 13711 } 13712 EXPORT_SYMBOL_GPL(kvm_handle_memory_failure); 13713 13714 int kvm_handle_invpcid(struct kvm_vcpu *vcpu, unsigned long type, gva_t gva) 13715 { 13716 bool pcid_enabled; 13717 struct x86_exception e; 13718 struct { 13719 u64 pcid; 13720 u64 gla; 13721 } operand; 13722 int r; 13723 13724 r = kvm_read_guest_virt(vcpu, gva, &operand, sizeof(operand), &e); 13725 if (r != X86EMUL_CONTINUE) 13726 return kvm_handle_memory_failure(vcpu, r, &e); 13727 13728 if (operand.pcid >> 12 != 0) { 13729 kvm_inject_gp(vcpu, 0); 13730 return 1; 13731 } 13732 13733 pcid_enabled = kvm_is_cr4_bit_set(vcpu, X86_CR4_PCIDE); 13734 13735 switch (type) { 13736 case INVPCID_TYPE_INDIV_ADDR: 13737 /* 13738 * LAM doesn't apply to addresses that are inputs to TLB 13739 * invalidation. 13740 */ 13741 if ((!pcid_enabled && (operand.pcid != 0)) || 13742 is_noncanonical_invlpg_address(operand.gla, vcpu)) { 13743 kvm_inject_gp(vcpu, 0); 13744 return 1; 13745 } 13746 kvm_mmu_invpcid_gva(vcpu, operand.gla, operand.pcid); 13747 return kvm_skip_emulated_instruction(vcpu); 13748 13749 case INVPCID_TYPE_SINGLE_CTXT: 13750 if (!pcid_enabled && (operand.pcid != 0)) { 13751 kvm_inject_gp(vcpu, 0); 13752 return 1; 13753 } 13754 13755 kvm_invalidate_pcid(vcpu, operand.pcid); 13756 return kvm_skip_emulated_instruction(vcpu); 13757 13758 case INVPCID_TYPE_ALL_NON_GLOBAL: 13759 /* 13760 * Currently, KVM doesn't mark global entries in the shadow 13761 * page tables, so a non-global flush just degenerates to a 13762 * global flush. If needed, we could optimize this later by 13763 * keeping track of global entries in shadow page tables. 13764 */ 13765 13766 fallthrough; 13767 case INVPCID_TYPE_ALL_INCL_GLOBAL: 13768 kvm_make_request(KVM_REQ_TLB_FLUSH_GUEST, vcpu); 13769 return kvm_skip_emulated_instruction(vcpu); 13770 13771 default: 13772 kvm_inject_gp(vcpu, 0); 13773 return 1; 13774 } 13775 } 13776 EXPORT_SYMBOL_GPL(kvm_handle_invpcid); 13777 13778 static int complete_sev_es_emulated_mmio(struct kvm_vcpu *vcpu) 13779 { 13780 struct kvm_run *run = vcpu->run; 13781 struct kvm_mmio_fragment *frag; 13782 unsigned int len; 13783 13784 BUG_ON(!vcpu->mmio_needed); 13785 13786 /* Complete previous fragment */ 13787 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment]; 13788 len = min(8u, frag->len); 13789 if (!vcpu->mmio_is_write) 13790 memcpy(frag->data, run->mmio.data, len); 13791 13792 if (frag->len <= 8) { 13793 /* Switch to the next fragment. */ 13794 frag++; 13795 vcpu->mmio_cur_fragment++; 13796 } else { 13797 /* Go forward to the next mmio piece. */ 13798 frag->data += len; 13799 frag->gpa += len; 13800 frag->len -= len; 13801 } 13802 13803 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) { 13804 vcpu->mmio_needed = 0; 13805 13806 // VMG change, at this point, we're always done 13807 // RIP has already been advanced 13808 return 1; 13809 } 13810 13811 // More MMIO is needed 13812 run->mmio.phys_addr = frag->gpa; 13813 run->mmio.len = min(8u, frag->len); 13814 run->mmio.is_write = vcpu->mmio_is_write; 13815 if (run->mmio.is_write) 13816 memcpy(run->mmio.data, frag->data, min(8u, frag->len)); 13817 run->exit_reason = KVM_EXIT_MMIO; 13818 13819 vcpu->arch.complete_userspace_io = complete_sev_es_emulated_mmio; 13820 13821 return 0; 13822 } 13823 13824 int kvm_sev_es_mmio_write(struct kvm_vcpu *vcpu, gpa_t gpa, unsigned int bytes, 13825 void *data) 13826 { 13827 int handled; 13828 struct kvm_mmio_fragment *frag; 13829 13830 if (!data) 13831 return -EINVAL; 13832 13833 handled = write_emultor.read_write_mmio(vcpu, gpa, bytes, data); 13834 if (handled == bytes) 13835 return 1; 13836 13837 bytes -= handled; 13838 gpa += handled; 13839 data += handled; 13840 13841 /*TODO: Check if need to increment number of frags */ 13842 frag = vcpu->mmio_fragments; 13843 vcpu->mmio_nr_fragments = 1; 13844 frag->len = bytes; 13845 frag->gpa = gpa; 13846 frag->data = data; 13847 13848 vcpu->mmio_needed = 1; 13849 vcpu->mmio_cur_fragment = 0; 13850 13851 vcpu->run->mmio.phys_addr = gpa; 13852 vcpu->run->mmio.len = min(8u, frag->len); 13853 vcpu->run->mmio.is_write = 1; 13854 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len)); 13855 vcpu->run->exit_reason = KVM_EXIT_MMIO; 13856 13857 vcpu->arch.complete_userspace_io = complete_sev_es_emulated_mmio; 13858 13859 return 0; 13860 } 13861 EXPORT_SYMBOL_GPL(kvm_sev_es_mmio_write); 13862 13863 int kvm_sev_es_mmio_read(struct kvm_vcpu *vcpu, gpa_t gpa, unsigned int bytes, 13864 void *data) 13865 { 13866 int handled; 13867 struct kvm_mmio_fragment *frag; 13868 13869 if (!data) 13870 return -EINVAL; 13871 13872 handled = read_emultor.read_write_mmio(vcpu, gpa, bytes, data); 13873 if (handled == bytes) 13874 return 1; 13875 13876 bytes -= handled; 13877 gpa += handled; 13878 data += handled; 13879 13880 /*TODO: Check if need to increment number of frags */ 13881 frag = vcpu->mmio_fragments; 13882 vcpu->mmio_nr_fragments = 1; 13883 frag->len = bytes; 13884 frag->gpa = gpa; 13885 frag->data = data; 13886 13887 vcpu->mmio_needed = 1; 13888 vcpu->mmio_cur_fragment = 0; 13889 13890 vcpu->run->mmio.phys_addr = gpa; 13891 vcpu->run->mmio.len = min(8u, frag->len); 13892 vcpu->run->mmio.is_write = 0; 13893 vcpu->run->exit_reason = KVM_EXIT_MMIO; 13894 13895 vcpu->arch.complete_userspace_io = complete_sev_es_emulated_mmio; 13896 13897 return 0; 13898 } 13899 EXPORT_SYMBOL_GPL(kvm_sev_es_mmio_read); 13900 13901 static void advance_sev_es_emulated_pio(struct kvm_vcpu *vcpu, unsigned count, int size) 13902 { 13903 vcpu->arch.sev_pio_count -= count; 13904 vcpu->arch.sev_pio_data += count * size; 13905 } 13906 13907 static int kvm_sev_es_outs(struct kvm_vcpu *vcpu, unsigned int size, 13908 unsigned int port); 13909 13910 static int complete_sev_es_emulated_outs(struct kvm_vcpu *vcpu) 13911 { 13912 int size = vcpu->arch.pio.size; 13913 int port = vcpu->arch.pio.port; 13914 13915 vcpu->arch.pio.count = 0; 13916 if (vcpu->arch.sev_pio_count) 13917 return kvm_sev_es_outs(vcpu, size, port); 13918 return 1; 13919 } 13920 13921 static int kvm_sev_es_outs(struct kvm_vcpu *vcpu, unsigned int size, 13922 unsigned int port) 13923 { 13924 for (;;) { 13925 unsigned int count = 13926 min_t(unsigned int, PAGE_SIZE / size, vcpu->arch.sev_pio_count); 13927 int ret = emulator_pio_out(vcpu, size, port, vcpu->arch.sev_pio_data, count); 13928 13929 /* memcpy done already by emulator_pio_out. */ 13930 advance_sev_es_emulated_pio(vcpu, count, size); 13931 if (!ret) 13932 break; 13933 13934 /* Emulation done by the kernel. */ 13935 if (!vcpu->arch.sev_pio_count) 13936 return 1; 13937 } 13938 13939 vcpu->arch.complete_userspace_io = complete_sev_es_emulated_outs; 13940 return 0; 13941 } 13942 13943 static int kvm_sev_es_ins(struct kvm_vcpu *vcpu, unsigned int size, 13944 unsigned int port); 13945 13946 static int complete_sev_es_emulated_ins(struct kvm_vcpu *vcpu) 13947 { 13948 unsigned count = vcpu->arch.pio.count; 13949 int size = vcpu->arch.pio.size; 13950 int port = vcpu->arch.pio.port; 13951 13952 complete_emulator_pio_in(vcpu, vcpu->arch.sev_pio_data); 13953 advance_sev_es_emulated_pio(vcpu, count, size); 13954 if (vcpu->arch.sev_pio_count) 13955 return kvm_sev_es_ins(vcpu, size, port); 13956 return 1; 13957 } 13958 13959 static int kvm_sev_es_ins(struct kvm_vcpu *vcpu, unsigned int size, 13960 unsigned int port) 13961 { 13962 for (;;) { 13963 unsigned int count = 13964 min_t(unsigned int, PAGE_SIZE / size, vcpu->arch.sev_pio_count); 13965 if (!emulator_pio_in(vcpu, size, port, vcpu->arch.sev_pio_data, count)) 13966 break; 13967 13968 /* Emulation done by the kernel. */ 13969 advance_sev_es_emulated_pio(vcpu, count, size); 13970 if (!vcpu->arch.sev_pio_count) 13971 return 1; 13972 } 13973 13974 vcpu->arch.complete_userspace_io = complete_sev_es_emulated_ins; 13975 return 0; 13976 } 13977 13978 int kvm_sev_es_string_io(struct kvm_vcpu *vcpu, unsigned int size, 13979 unsigned int port, void *data, unsigned int count, 13980 int in) 13981 { 13982 vcpu->arch.sev_pio_data = data; 13983 vcpu->arch.sev_pio_count = count; 13984 return in ? kvm_sev_es_ins(vcpu, size, port) 13985 : kvm_sev_es_outs(vcpu, size, port); 13986 } 13987 EXPORT_SYMBOL_GPL(kvm_sev_es_string_io); 13988 13989 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_entry); 13990 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit); 13991 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_fast_mmio); 13992 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq); 13993 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault); 13994 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr); 13995 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr); 13996 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmenter); 13997 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit); 13998 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject); 13999 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit); 14000 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmenter_failed); 14001 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga); 14002 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit); 14003 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts); 14004 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset); 14005 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_ple_window_update); 14006 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pml_full); 14007 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pi_irte_update); 14008 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_unaccelerated_access); 14009 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_incomplete_ipi); 14010 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_ga_log); 14011 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_kick_vcpu_slowpath); 14012 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_doorbell); 14013 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_apicv_accept_irq); 14014 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_vmgexit_enter); 14015 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_vmgexit_exit); 14016 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_vmgexit_msr_protocol_enter); 14017 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_vmgexit_msr_protocol_exit); 14018 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_rmp_fault); 14019 14020 static int __init kvm_x86_init(void) 14021 { 14022 kvm_init_xstate_sizes(); 14023 14024 kvm_mmu_x86_module_init(); 14025 mitigate_smt_rsb &= boot_cpu_has_bug(X86_BUG_SMT_RSB) && cpu_smt_possible(); 14026 return 0; 14027 } 14028 module_init(kvm_x86_init); 14029 14030 static void __exit kvm_x86_exit(void) 14031 { 14032 WARN_ON_ONCE(static_branch_unlikely(&kvm_has_noapic_vcpu)); 14033 } 14034 module_exit(kvm_x86_exit); 14035