1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Kernel-based Virtual Machine driver for Linux 4 * 5 * derived from drivers/kvm/kvm_main.c 6 * 7 * Copyright (C) 2006 Qumranet, Inc. 8 * Copyright (C) 2008 Qumranet, Inc. 9 * Copyright IBM Corporation, 2008 10 * Copyright 2010 Red Hat, Inc. and/or its affiliates. 11 * 12 * Authors: 13 * Avi Kivity <avi@qumranet.com> 14 * Yaniv Kamay <yaniv@qumranet.com> 15 * Amit Shah <amit.shah@qumranet.com> 16 * Ben-Ami Yassour <benami@il.ibm.com> 17 */ 18 19 #include <linux/kvm_host.h> 20 #include "irq.h" 21 #include "ioapic.h" 22 #include "mmu.h" 23 #include "i8254.h" 24 #include "tss.h" 25 #include "kvm_cache_regs.h" 26 #include "kvm_emulate.h" 27 #include "x86.h" 28 #include "cpuid.h" 29 #include "pmu.h" 30 #include "hyperv.h" 31 #include "lapic.h" 32 #include "xen.h" 33 34 #include <linux/clocksource.h> 35 #include <linux/interrupt.h> 36 #include <linux/kvm.h> 37 #include <linux/fs.h> 38 #include <linux/vmalloc.h> 39 #include <linux/export.h> 40 #include <linux/moduleparam.h> 41 #include <linux/mman.h> 42 #include <linux/highmem.h> 43 #include <linux/iommu.h> 44 #include <linux/intel-iommu.h> 45 #include <linux/cpufreq.h> 46 #include <linux/user-return-notifier.h> 47 #include <linux/srcu.h> 48 #include <linux/slab.h> 49 #include <linux/perf_event.h> 50 #include <linux/uaccess.h> 51 #include <linux/hash.h> 52 #include <linux/pci.h> 53 #include <linux/timekeeper_internal.h> 54 #include <linux/pvclock_gtod.h> 55 #include <linux/kvm_irqfd.h> 56 #include <linux/irqbypass.h> 57 #include <linux/sched/stat.h> 58 #include <linux/sched/isolation.h> 59 #include <linux/mem_encrypt.h> 60 #include <linux/entry-kvm.h> 61 #include <linux/suspend.h> 62 63 #include <trace/events/kvm.h> 64 65 #include <asm/debugreg.h> 66 #include <asm/msr.h> 67 #include <asm/desc.h> 68 #include <asm/mce.h> 69 #include <asm/pkru.h> 70 #include <linux/kernel_stat.h> 71 #include <asm/fpu/api.h> 72 #include <asm/fpu/xcr.h> 73 #include <asm/fpu/xstate.h> 74 #include <asm/pvclock.h> 75 #include <asm/div64.h> 76 #include <asm/irq_remapping.h> 77 #include <asm/mshyperv.h> 78 #include <asm/hypervisor.h> 79 #include <asm/tlbflush.h> 80 #include <asm/intel_pt.h> 81 #include <asm/emulate_prefix.h> 82 #include <asm/sgx.h> 83 #include <clocksource/hyperv_timer.h> 84 85 #define CREATE_TRACE_POINTS 86 #include "trace.h" 87 88 #define MAX_IO_MSRS 256 89 #define KVM_MAX_MCE_BANKS 32 90 u64 __read_mostly kvm_mce_cap_supported = MCG_CTL_P | MCG_SER_P; 91 EXPORT_SYMBOL_GPL(kvm_mce_cap_supported); 92 93 #define emul_to_vcpu(ctxt) \ 94 ((struct kvm_vcpu *)(ctxt)->vcpu) 95 96 /* EFER defaults: 97 * - enable syscall per default because its emulated by KVM 98 * - enable LME and LMA per default on 64 bit KVM 99 */ 100 #ifdef CONFIG_X86_64 101 static 102 u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA)); 103 #else 104 static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE); 105 #endif 106 107 static u64 __read_mostly cr4_reserved_bits = CR4_RESERVED_BITS; 108 109 #define KVM_EXIT_HYPERCALL_VALID_MASK (1 << KVM_HC_MAP_GPA_RANGE) 110 111 #define KVM_X2APIC_API_VALID_FLAGS (KVM_X2APIC_API_USE_32BIT_IDS | \ 112 KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK) 113 114 static void update_cr8_intercept(struct kvm_vcpu *vcpu); 115 static void process_nmi(struct kvm_vcpu *vcpu); 116 static void process_smi(struct kvm_vcpu *vcpu); 117 static void enter_smm(struct kvm_vcpu *vcpu); 118 static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags); 119 static void store_regs(struct kvm_vcpu *vcpu); 120 static int sync_regs(struct kvm_vcpu *vcpu); 121 122 static int __set_sregs2(struct kvm_vcpu *vcpu, struct kvm_sregs2 *sregs2); 123 static void __get_sregs2(struct kvm_vcpu *vcpu, struct kvm_sregs2 *sregs2); 124 125 struct kvm_x86_ops kvm_x86_ops __read_mostly; 126 EXPORT_SYMBOL_GPL(kvm_x86_ops); 127 128 #define KVM_X86_OP(func) \ 129 DEFINE_STATIC_CALL_NULL(kvm_x86_##func, \ 130 *(((struct kvm_x86_ops *)0)->func)); 131 #define KVM_X86_OP_NULL KVM_X86_OP 132 #include <asm/kvm-x86-ops.h> 133 EXPORT_STATIC_CALL_GPL(kvm_x86_get_cs_db_l_bits); 134 EXPORT_STATIC_CALL_GPL(kvm_x86_cache_reg); 135 EXPORT_STATIC_CALL_GPL(kvm_x86_tlb_flush_current); 136 137 static bool __read_mostly ignore_msrs = 0; 138 module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR); 139 140 bool __read_mostly report_ignored_msrs = true; 141 module_param(report_ignored_msrs, bool, S_IRUGO | S_IWUSR); 142 EXPORT_SYMBOL_GPL(report_ignored_msrs); 143 144 unsigned int min_timer_period_us = 200; 145 module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR); 146 147 static bool __read_mostly kvmclock_periodic_sync = true; 148 module_param(kvmclock_periodic_sync, bool, S_IRUGO); 149 150 bool __read_mostly kvm_has_tsc_control; 151 EXPORT_SYMBOL_GPL(kvm_has_tsc_control); 152 u32 __read_mostly kvm_max_guest_tsc_khz; 153 EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz); 154 u8 __read_mostly kvm_tsc_scaling_ratio_frac_bits; 155 EXPORT_SYMBOL_GPL(kvm_tsc_scaling_ratio_frac_bits); 156 u64 __read_mostly kvm_max_tsc_scaling_ratio; 157 EXPORT_SYMBOL_GPL(kvm_max_tsc_scaling_ratio); 158 u64 __read_mostly kvm_default_tsc_scaling_ratio; 159 EXPORT_SYMBOL_GPL(kvm_default_tsc_scaling_ratio); 160 bool __read_mostly kvm_has_bus_lock_exit; 161 EXPORT_SYMBOL_GPL(kvm_has_bus_lock_exit); 162 163 /* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */ 164 static u32 __read_mostly tsc_tolerance_ppm = 250; 165 module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR); 166 167 /* 168 * lapic timer advance (tscdeadline mode only) in nanoseconds. '-1' enables 169 * adaptive tuning starting from default advancement of 1000ns. '0' disables 170 * advancement entirely. Any other value is used as-is and disables adaptive 171 * tuning, i.e. allows privileged userspace to set an exact advancement time. 172 */ 173 static int __read_mostly lapic_timer_advance_ns = -1; 174 module_param(lapic_timer_advance_ns, int, S_IRUGO | S_IWUSR); 175 176 static bool __read_mostly vector_hashing = true; 177 module_param(vector_hashing, bool, S_IRUGO); 178 179 bool __read_mostly enable_vmware_backdoor = false; 180 module_param(enable_vmware_backdoor, bool, S_IRUGO); 181 EXPORT_SYMBOL_GPL(enable_vmware_backdoor); 182 183 static bool __read_mostly force_emulation_prefix = false; 184 module_param(force_emulation_prefix, bool, S_IRUGO); 185 186 int __read_mostly pi_inject_timer = -1; 187 module_param(pi_inject_timer, bint, S_IRUGO | S_IWUSR); 188 189 /* 190 * Restoring the host value for MSRs that are only consumed when running in 191 * usermode, e.g. SYSCALL MSRs and TSC_AUX, can be deferred until the CPU 192 * returns to userspace, i.e. the kernel can run with the guest's value. 193 */ 194 #define KVM_MAX_NR_USER_RETURN_MSRS 16 195 196 struct kvm_user_return_msrs { 197 struct user_return_notifier urn; 198 bool registered; 199 struct kvm_user_return_msr_values { 200 u64 host; 201 u64 curr; 202 } values[KVM_MAX_NR_USER_RETURN_MSRS]; 203 }; 204 205 u32 __read_mostly kvm_nr_uret_msrs; 206 EXPORT_SYMBOL_GPL(kvm_nr_uret_msrs); 207 static u32 __read_mostly kvm_uret_msrs_list[KVM_MAX_NR_USER_RETURN_MSRS]; 208 static struct kvm_user_return_msrs __percpu *user_return_msrs; 209 210 #define KVM_SUPPORTED_XCR0 (XFEATURE_MASK_FP | XFEATURE_MASK_SSE \ 211 | XFEATURE_MASK_YMM | XFEATURE_MASK_BNDREGS \ 212 | XFEATURE_MASK_BNDCSR | XFEATURE_MASK_AVX512 \ 213 | XFEATURE_MASK_PKRU) 214 215 u64 __read_mostly host_efer; 216 EXPORT_SYMBOL_GPL(host_efer); 217 218 bool __read_mostly allow_smaller_maxphyaddr = 0; 219 EXPORT_SYMBOL_GPL(allow_smaller_maxphyaddr); 220 221 bool __read_mostly enable_apicv = true; 222 EXPORT_SYMBOL_GPL(enable_apicv); 223 224 u64 __read_mostly host_xss; 225 EXPORT_SYMBOL_GPL(host_xss); 226 u64 __read_mostly supported_xss; 227 EXPORT_SYMBOL_GPL(supported_xss); 228 229 const struct _kvm_stats_desc kvm_vm_stats_desc[] = { 230 KVM_GENERIC_VM_STATS(), 231 STATS_DESC_COUNTER(VM, mmu_shadow_zapped), 232 STATS_DESC_COUNTER(VM, mmu_pte_write), 233 STATS_DESC_COUNTER(VM, mmu_pde_zapped), 234 STATS_DESC_COUNTER(VM, mmu_flooded), 235 STATS_DESC_COUNTER(VM, mmu_recycled), 236 STATS_DESC_COUNTER(VM, mmu_cache_miss), 237 STATS_DESC_ICOUNTER(VM, mmu_unsync), 238 STATS_DESC_ICOUNTER(VM, pages_4k), 239 STATS_DESC_ICOUNTER(VM, pages_2m), 240 STATS_DESC_ICOUNTER(VM, pages_1g), 241 STATS_DESC_ICOUNTER(VM, nx_lpage_splits), 242 STATS_DESC_PCOUNTER(VM, max_mmu_rmap_size), 243 STATS_DESC_PCOUNTER(VM, max_mmu_page_hash_collisions) 244 }; 245 246 const struct kvm_stats_header kvm_vm_stats_header = { 247 .name_size = KVM_STATS_NAME_SIZE, 248 .num_desc = ARRAY_SIZE(kvm_vm_stats_desc), 249 .id_offset = sizeof(struct kvm_stats_header), 250 .desc_offset = sizeof(struct kvm_stats_header) + KVM_STATS_NAME_SIZE, 251 .data_offset = sizeof(struct kvm_stats_header) + KVM_STATS_NAME_SIZE + 252 sizeof(kvm_vm_stats_desc), 253 }; 254 255 const struct _kvm_stats_desc kvm_vcpu_stats_desc[] = { 256 KVM_GENERIC_VCPU_STATS(), 257 STATS_DESC_COUNTER(VCPU, pf_fixed), 258 STATS_DESC_COUNTER(VCPU, pf_guest), 259 STATS_DESC_COUNTER(VCPU, tlb_flush), 260 STATS_DESC_COUNTER(VCPU, invlpg), 261 STATS_DESC_COUNTER(VCPU, exits), 262 STATS_DESC_COUNTER(VCPU, io_exits), 263 STATS_DESC_COUNTER(VCPU, mmio_exits), 264 STATS_DESC_COUNTER(VCPU, signal_exits), 265 STATS_DESC_COUNTER(VCPU, irq_window_exits), 266 STATS_DESC_COUNTER(VCPU, nmi_window_exits), 267 STATS_DESC_COUNTER(VCPU, l1d_flush), 268 STATS_DESC_COUNTER(VCPU, halt_exits), 269 STATS_DESC_COUNTER(VCPU, request_irq_exits), 270 STATS_DESC_COUNTER(VCPU, irq_exits), 271 STATS_DESC_COUNTER(VCPU, host_state_reload), 272 STATS_DESC_COUNTER(VCPU, fpu_reload), 273 STATS_DESC_COUNTER(VCPU, insn_emulation), 274 STATS_DESC_COUNTER(VCPU, insn_emulation_fail), 275 STATS_DESC_COUNTER(VCPU, hypercalls), 276 STATS_DESC_COUNTER(VCPU, irq_injections), 277 STATS_DESC_COUNTER(VCPU, nmi_injections), 278 STATS_DESC_COUNTER(VCPU, req_event), 279 STATS_DESC_COUNTER(VCPU, nested_run), 280 STATS_DESC_COUNTER(VCPU, directed_yield_attempted), 281 STATS_DESC_COUNTER(VCPU, directed_yield_successful), 282 STATS_DESC_ICOUNTER(VCPU, guest_mode) 283 }; 284 285 const struct kvm_stats_header kvm_vcpu_stats_header = { 286 .name_size = KVM_STATS_NAME_SIZE, 287 .num_desc = ARRAY_SIZE(kvm_vcpu_stats_desc), 288 .id_offset = sizeof(struct kvm_stats_header), 289 .desc_offset = sizeof(struct kvm_stats_header) + KVM_STATS_NAME_SIZE, 290 .data_offset = sizeof(struct kvm_stats_header) + KVM_STATS_NAME_SIZE + 291 sizeof(kvm_vcpu_stats_desc), 292 }; 293 294 u64 __read_mostly host_xcr0; 295 u64 __read_mostly supported_xcr0; 296 EXPORT_SYMBOL_GPL(supported_xcr0); 297 298 static struct kmem_cache *x86_emulator_cache; 299 300 /* 301 * When called, it means the previous get/set msr reached an invalid msr. 302 * Return true if we want to ignore/silent this failed msr access. 303 */ 304 static bool kvm_msr_ignored_check(u32 msr, u64 data, bool write) 305 { 306 const char *op = write ? "wrmsr" : "rdmsr"; 307 308 if (ignore_msrs) { 309 if (report_ignored_msrs) 310 kvm_pr_unimpl("ignored %s: 0x%x data 0x%llx\n", 311 op, msr, data); 312 /* Mask the error */ 313 return true; 314 } else { 315 kvm_debug_ratelimited("unhandled %s: 0x%x data 0x%llx\n", 316 op, msr, data); 317 return false; 318 } 319 } 320 321 static struct kmem_cache *kvm_alloc_emulator_cache(void) 322 { 323 unsigned int useroffset = offsetof(struct x86_emulate_ctxt, src); 324 unsigned int size = sizeof(struct x86_emulate_ctxt); 325 326 return kmem_cache_create_usercopy("x86_emulator", size, 327 __alignof__(struct x86_emulate_ctxt), 328 SLAB_ACCOUNT, useroffset, 329 size - useroffset, NULL); 330 } 331 332 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt); 333 334 static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu) 335 { 336 int i; 337 for (i = 0; i < ASYNC_PF_PER_VCPU; i++) 338 vcpu->arch.apf.gfns[i] = ~0; 339 } 340 341 static void kvm_on_user_return(struct user_return_notifier *urn) 342 { 343 unsigned slot; 344 struct kvm_user_return_msrs *msrs 345 = container_of(urn, struct kvm_user_return_msrs, urn); 346 struct kvm_user_return_msr_values *values; 347 unsigned long flags; 348 349 /* 350 * Disabling irqs at this point since the following code could be 351 * interrupted and executed through kvm_arch_hardware_disable() 352 */ 353 local_irq_save(flags); 354 if (msrs->registered) { 355 msrs->registered = false; 356 user_return_notifier_unregister(urn); 357 } 358 local_irq_restore(flags); 359 for (slot = 0; slot < kvm_nr_uret_msrs; ++slot) { 360 values = &msrs->values[slot]; 361 if (values->host != values->curr) { 362 wrmsrl(kvm_uret_msrs_list[slot], values->host); 363 values->curr = values->host; 364 } 365 } 366 } 367 368 static int kvm_probe_user_return_msr(u32 msr) 369 { 370 u64 val; 371 int ret; 372 373 preempt_disable(); 374 ret = rdmsrl_safe(msr, &val); 375 if (ret) 376 goto out; 377 ret = wrmsrl_safe(msr, val); 378 out: 379 preempt_enable(); 380 return ret; 381 } 382 383 int kvm_add_user_return_msr(u32 msr) 384 { 385 BUG_ON(kvm_nr_uret_msrs >= KVM_MAX_NR_USER_RETURN_MSRS); 386 387 if (kvm_probe_user_return_msr(msr)) 388 return -1; 389 390 kvm_uret_msrs_list[kvm_nr_uret_msrs] = msr; 391 return kvm_nr_uret_msrs++; 392 } 393 EXPORT_SYMBOL_GPL(kvm_add_user_return_msr); 394 395 int kvm_find_user_return_msr(u32 msr) 396 { 397 int i; 398 399 for (i = 0; i < kvm_nr_uret_msrs; ++i) { 400 if (kvm_uret_msrs_list[i] == msr) 401 return i; 402 } 403 return -1; 404 } 405 EXPORT_SYMBOL_GPL(kvm_find_user_return_msr); 406 407 static void kvm_user_return_msr_cpu_online(void) 408 { 409 unsigned int cpu = smp_processor_id(); 410 struct kvm_user_return_msrs *msrs = per_cpu_ptr(user_return_msrs, cpu); 411 u64 value; 412 int i; 413 414 for (i = 0; i < kvm_nr_uret_msrs; ++i) { 415 rdmsrl_safe(kvm_uret_msrs_list[i], &value); 416 msrs->values[i].host = value; 417 msrs->values[i].curr = value; 418 } 419 } 420 421 int kvm_set_user_return_msr(unsigned slot, u64 value, u64 mask) 422 { 423 unsigned int cpu = smp_processor_id(); 424 struct kvm_user_return_msrs *msrs = per_cpu_ptr(user_return_msrs, cpu); 425 int err; 426 427 value = (value & mask) | (msrs->values[slot].host & ~mask); 428 if (value == msrs->values[slot].curr) 429 return 0; 430 err = wrmsrl_safe(kvm_uret_msrs_list[slot], value); 431 if (err) 432 return 1; 433 434 msrs->values[slot].curr = value; 435 if (!msrs->registered) { 436 msrs->urn.on_user_return = kvm_on_user_return; 437 user_return_notifier_register(&msrs->urn); 438 msrs->registered = true; 439 } 440 return 0; 441 } 442 EXPORT_SYMBOL_GPL(kvm_set_user_return_msr); 443 444 static void drop_user_return_notifiers(void) 445 { 446 unsigned int cpu = smp_processor_id(); 447 struct kvm_user_return_msrs *msrs = per_cpu_ptr(user_return_msrs, cpu); 448 449 if (msrs->registered) 450 kvm_on_user_return(&msrs->urn); 451 } 452 453 u64 kvm_get_apic_base(struct kvm_vcpu *vcpu) 454 { 455 return vcpu->arch.apic_base; 456 } 457 EXPORT_SYMBOL_GPL(kvm_get_apic_base); 458 459 enum lapic_mode kvm_get_apic_mode(struct kvm_vcpu *vcpu) 460 { 461 return kvm_apic_mode(kvm_get_apic_base(vcpu)); 462 } 463 EXPORT_SYMBOL_GPL(kvm_get_apic_mode); 464 465 int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info) 466 { 467 enum lapic_mode old_mode = kvm_get_apic_mode(vcpu); 468 enum lapic_mode new_mode = kvm_apic_mode(msr_info->data); 469 u64 reserved_bits = kvm_vcpu_reserved_gpa_bits_raw(vcpu) | 0x2ff | 470 (guest_cpuid_has(vcpu, X86_FEATURE_X2APIC) ? 0 : X2APIC_ENABLE); 471 472 if ((msr_info->data & reserved_bits) != 0 || new_mode == LAPIC_MODE_INVALID) 473 return 1; 474 if (!msr_info->host_initiated) { 475 if (old_mode == LAPIC_MODE_X2APIC && new_mode == LAPIC_MODE_XAPIC) 476 return 1; 477 if (old_mode == LAPIC_MODE_DISABLED && new_mode == LAPIC_MODE_X2APIC) 478 return 1; 479 } 480 481 kvm_lapic_set_base(vcpu, msr_info->data); 482 kvm_recalculate_apic_map(vcpu->kvm); 483 return 0; 484 } 485 EXPORT_SYMBOL_GPL(kvm_set_apic_base); 486 487 /* 488 * Handle a fault on a hardware virtualization (VMX or SVM) instruction. 489 * 490 * Hardware virtualization extension instructions may fault if a reboot turns 491 * off virtualization while processes are running. Usually after catching the 492 * fault we just panic; during reboot instead the instruction is ignored. 493 */ 494 noinstr void kvm_spurious_fault(void) 495 { 496 /* Fault while not rebooting. We want the trace. */ 497 BUG_ON(!kvm_rebooting); 498 } 499 EXPORT_SYMBOL_GPL(kvm_spurious_fault); 500 501 #define EXCPT_BENIGN 0 502 #define EXCPT_CONTRIBUTORY 1 503 #define EXCPT_PF 2 504 505 static int exception_class(int vector) 506 { 507 switch (vector) { 508 case PF_VECTOR: 509 return EXCPT_PF; 510 case DE_VECTOR: 511 case TS_VECTOR: 512 case NP_VECTOR: 513 case SS_VECTOR: 514 case GP_VECTOR: 515 return EXCPT_CONTRIBUTORY; 516 default: 517 break; 518 } 519 return EXCPT_BENIGN; 520 } 521 522 #define EXCPT_FAULT 0 523 #define EXCPT_TRAP 1 524 #define EXCPT_ABORT 2 525 #define EXCPT_INTERRUPT 3 526 527 static int exception_type(int vector) 528 { 529 unsigned int mask; 530 531 if (WARN_ON(vector > 31 || vector == NMI_VECTOR)) 532 return EXCPT_INTERRUPT; 533 534 mask = 1 << vector; 535 536 /* #DB is trap, as instruction watchpoints are handled elsewhere */ 537 if (mask & ((1 << DB_VECTOR) | (1 << BP_VECTOR) | (1 << OF_VECTOR))) 538 return EXCPT_TRAP; 539 540 if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR))) 541 return EXCPT_ABORT; 542 543 /* Reserved exceptions will result in fault */ 544 return EXCPT_FAULT; 545 } 546 547 void kvm_deliver_exception_payload(struct kvm_vcpu *vcpu) 548 { 549 unsigned nr = vcpu->arch.exception.nr; 550 bool has_payload = vcpu->arch.exception.has_payload; 551 unsigned long payload = vcpu->arch.exception.payload; 552 553 if (!has_payload) 554 return; 555 556 switch (nr) { 557 case DB_VECTOR: 558 /* 559 * "Certain debug exceptions may clear bit 0-3. The 560 * remaining contents of the DR6 register are never 561 * cleared by the processor". 562 */ 563 vcpu->arch.dr6 &= ~DR_TRAP_BITS; 564 /* 565 * In order to reflect the #DB exception payload in guest 566 * dr6, three components need to be considered: active low 567 * bit, FIXED_1 bits and active high bits (e.g. DR6_BD, 568 * DR6_BS and DR6_BT) 569 * DR6_ACTIVE_LOW contains the FIXED_1 and active low bits. 570 * In the target guest dr6: 571 * FIXED_1 bits should always be set. 572 * Active low bits should be cleared if 1-setting in payload. 573 * Active high bits should be set if 1-setting in payload. 574 * 575 * Note, the payload is compatible with the pending debug 576 * exceptions/exit qualification under VMX, that active_low bits 577 * are active high in payload. 578 * So they need to be flipped for DR6. 579 */ 580 vcpu->arch.dr6 |= DR6_ACTIVE_LOW; 581 vcpu->arch.dr6 |= payload; 582 vcpu->arch.dr6 ^= payload & DR6_ACTIVE_LOW; 583 584 /* 585 * The #DB payload is defined as compatible with the 'pending 586 * debug exceptions' field under VMX, not DR6. While bit 12 is 587 * defined in the 'pending debug exceptions' field (enabled 588 * breakpoint), it is reserved and must be zero in DR6. 589 */ 590 vcpu->arch.dr6 &= ~BIT(12); 591 break; 592 case PF_VECTOR: 593 vcpu->arch.cr2 = payload; 594 break; 595 } 596 597 vcpu->arch.exception.has_payload = false; 598 vcpu->arch.exception.payload = 0; 599 } 600 EXPORT_SYMBOL_GPL(kvm_deliver_exception_payload); 601 602 static void kvm_multiple_exception(struct kvm_vcpu *vcpu, 603 unsigned nr, bool has_error, u32 error_code, 604 bool has_payload, unsigned long payload, bool reinject) 605 { 606 u32 prev_nr; 607 int class1, class2; 608 609 kvm_make_request(KVM_REQ_EVENT, vcpu); 610 611 if (!vcpu->arch.exception.pending && !vcpu->arch.exception.injected) { 612 queue: 613 if (reinject) { 614 /* 615 * On vmentry, vcpu->arch.exception.pending is only 616 * true if an event injection was blocked by 617 * nested_run_pending. In that case, however, 618 * vcpu_enter_guest requests an immediate exit, 619 * and the guest shouldn't proceed far enough to 620 * need reinjection. 621 */ 622 WARN_ON_ONCE(vcpu->arch.exception.pending); 623 vcpu->arch.exception.injected = true; 624 if (WARN_ON_ONCE(has_payload)) { 625 /* 626 * A reinjected event has already 627 * delivered its payload. 628 */ 629 has_payload = false; 630 payload = 0; 631 } 632 } else { 633 vcpu->arch.exception.pending = true; 634 vcpu->arch.exception.injected = false; 635 } 636 vcpu->arch.exception.has_error_code = has_error; 637 vcpu->arch.exception.nr = nr; 638 vcpu->arch.exception.error_code = error_code; 639 vcpu->arch.exception.has_payload = has_payload; 640 vcpu->arch.exception.payload = payload; 641 if (!is_guest_mode(vcpu)) 642 kvm_deliver_exception_payload(vcpu); 643 return; 644 } 645 646 /* to check exception */ 647 prev_nr = vcpu->arch.exception.nr; 648 if (prev_nr == DF_VECTOR) { 649 /* triple fault -> shutdown */ 650 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); 651 return; 652 } 653 class1 = exception_class(prev_nr); 654 class2 = exception_class(nr); 655 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY) 656 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) { 657 /* 658 * Generate double fault per SDM Table 5-5. Set 659 * exception.pending = true so that the double fault 660 * can trigger a nested vmexit. 661 */ 662 vcpu->arch.exception.pending = true; 663 vcpu->arch.exception.injected = false; 664 vcpu->arch.exception.has_error_code = true; 665 vcpu->arch.exception.nr = DF_VECTOR; 666 vcpu->arch.exception.error_code = 0; 667 vcpu->arch.exception.has_payload = false; 668 vcpu->arch.exception.payload = 0; 669 } else 670 /* replace previous exception with a new one in a hope 671 that instruction re-execution will regenerate lost 672 exception */ 673 goto queue; 674 } 675 676 void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr) 677 { 678 kvm_multiple_exception(vcpu, nr, false, 0, false, 0, false); 679 } 680 EXPORT_SYMBOL_GPL(kvm_queue_exception); 681 682 void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr) 683 { 684 kvm_multiple_exception(vcpu, nr, false, 0, false, 0, true); 685 } 686 EXPORT_SYMBOL_GPL(kvm_requeue_exception); 687 688 void kvm_queue_exception_p(struct kvm_vcpu *vcpu, unsigned nr, 689 unsigned long payload) 690 { 691 kvm_multiple_exception(vcpu, nr, false, 0, true, payload, false); 692 } 693 EXPORT_SYMBOL_GPL(kvm_queue_exception_p); 694 695 static void kvm_queue_exception_e_p(struct kvm_vcpu *vcpu, unsigned nr, 696 u32 error_code, unsigned long payload) 697 { 698 kvm_multiple_exception(vcpu, nr, true, error_code, 699 true, payload, false); 700 } 701 702 int kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err) 703 { 704 if (err) 705 kvm_inject_gp(vcpu, 0); 706 else 707 return kvm_skip_emulated_instruction(vcpu); 708 709 return 1; 710 } 711 EXPORT_SYMBOL_GPL(kvm_complete_insn_gp); 712 713 void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault) 714 { 715 ++vcpu->stat.pf_guest; 716 vcpu->arch.exception.nested_apf = 717 is_guest_mode(vcpu) && fault->async_page_fault; 718 if (vcpu->arch.exception.nested_apf) { 719 vcpu->arch.apf.nested_apf_token = fault->address; 720 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code); 721 } else { 722 kvm_queue_exception_e_p(vcpu, PF_VECTOR, fault->error_code, 723 fault->address); 724 } 725 } 726 EXPORT_SYMBOL_GPL(kvm_inject_page_fault); 727 728 bool kvm_inject_emulated_page_fault(struct kvm_vcpu *vcpu, 729 struct x86_exception *fault) 730 { 731 struct kvm_mmu *fault_mmu; 732 WARN_ON_ONCE(fault->vector != PF_VECTOR); 733 734 fault_mmu = fault->nested_page_fault ? vcpu->arch.mmu : 735 vcpu->arch.walk_mmu; 736 737 /* 738 * Invalidate the TLB entry for the faulting address, if it exists, 739 * else the access will fault indefinitely (and to emulate hardware). 740 */ 741 if ((fault->error_code & PFERR_PRESENT_MASK) && 742 !(fault->error_code & PFERR_RSVD_MASK)) 743 kvm_mmu_invalidate_gva(vcpu, fault_mmu, fault->address, 744 fault_mmu->root_hpa); 745 746 fault_mmu->inject_page_fault(vcpu, fault); 747 return fault->nested_page_fault; 748 } 749 EXPORT_SYMBOL_GPL(kvm_inject_emulated_page_fault); 750 751 void kvm_inject_nmi(struct kvm_vcpu *vcpu) 752 { 753 atomic_inc(&vcpu->arch.nmi_queued); 754 kvm_make_request(KVM_REQ_NMI, vcpu); 755 } 756 EXPORT_SYMBOL_GPL(kvm_inject_nmi); 757 758 void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code) 759 { 760 kvm_multiple_exception(vcpu, nr, true, error_code, false, 0, false); 761 } 762 EXPORT_SYMBOL_GPL(kvm_queue_exception_e); 763 764 void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code) 765 { 766 kvm_multiple_exception(vcpu, nr, true, error_code, false, 0, true); 767 } 768 EXPORT_SYMBOL_GPL(kvm_requeue_exception_e); 769 770 /* 771 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue 772 * a #GP and return false. 773 */ 774 bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl) 775 { 776 if (static_call(kvm_x86_get_cpl)(vcpu) <= required_cpl) 777 return true; 778 kvm_queue_exception_e(vcpu, GP_VECTOR, 0); 779 return false; 780 } 781 EXPORT_SYMBOL_GPL(kvm_require_cpl); 782 783 bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr) 784 { 785 if ((dr != 4 && dr != 5) || !kvm_read_cr4_bits(vcpu, X86_CR4_DE)) 786 return true; 787 788 kvm_queue_exception(vcpu, UD_VECTOR); 789 return false; 790 } 791 EXPORT_SYMBOL_GPL(kvm_require_dr); 792 793 static inline u64 pdptr_rsvd_bits(struct kvm_vcpu *vcpu) 794 { 795 return vcpu->arch.reserved_gpa_bits | rsvd_bits(5, 8) | rsvd_bits(1, 2); 796 } 797 798 /* 799 * Load the pae pdptrs. Return 1 if they are all valid, 0 otherwise. 800 */ 801 int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3) 802 { 803 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT; 804 gpa_t real_gpa; 805 int i; 806 int ret; 807 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)]; 808 809 /* 810 * If the MMU is nested, CR3 holds an L2 GPA and needs to be translated 811 * to an L1 GPA. 812 */ 813 real_gpa = mmu->translate_gpa(vcpu, gfn_to_gpa(pdpt_gfn), 814 PFERR_USER_MASK | PFERR_WRITE_MASK, NULL); 815 if (real_gpa == UNMAPPED_GVA) 816 return 0; 817 818 /* Note the offset, PDPTRs are 32 byte aligned when using PAE paging. */ 819 ret = kvm_vcpu_read_guest_page(vcpu, gpa_to_gfn(real_gpa), pdpte, 820 cr3 & GENMASK(11, 5), sizeof(pdpte)); 821 if (ret < 0) 822 return 0; 823 824 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) { 825 if ((pdpte[i] & PT_PRESENT_MASK) && 826 (pdpte[i] & pdptr_rsvd_bits(vcpu))) { 827 return 0; 828 } 829 } 830 831 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs)); 832 kvm_register_mark_dirty(vcpu, VCPU_EXREG_PDPTR); 833 vcpu->arch.pdptrs_from_userspace = false; 834 835 return 1; 836 } 837 EXPORT_SYMBOL_GPL(load_pdptrs); 838 839 void kvm_post_set_cr0(struct kvm_vcpu *vcpu, unsigned long old_cr0, unsigned long cr0) 840 { 841 if ((cr0 ^ old_cr0) & X86_CR0_PG) { 842 kvm_clear_async_pf_completion_queue(vcpu); 843 kvm_async_pf_hash_reset(vcpu); 844 } 845 846 if ((cr0 ^ old_cr0) & KVM_MMU_CR0_ROLE_BITS) 847 kvm_mmu_reset_context(vcpu); 848 849 if (((cr0 ^ old_cr0) & X86_CR0_CD) && 850 kvm_arch_has_noncoherent_dma(vcpu->kvm) && 851 !kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED)) 852 kvm_zap_gfn_range(vcpu->kvm, 0, ~0ULL); 853 } 854 EXPORT_SYMBOL_GPL(kvm_post_set_cr0); 855 856 int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0) 857 { 858 unsigned long old_cr0 = kvm_read_cr0(vcpu); 859 unsigned long pdptr_bits = X86_CR0_CD | X86_CR0_NW | X86_CR0_PG; 860 861 cr0 |= X86_CR0_ET; 862 863 #ifdef CONFIG_X86_64 864 if (cr0 & 0xffffffff00000000UL) 865 return 1; 866 #endif 867 868 cr0 &= ~CR0_RESERVED_BITS; 869 870 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD)) 871 return 1; 872 873 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE)) 874 return 1; 875 876 #ifdef CONFIG_X86_64 877 if ((vcpu->arch.efer & EFER_LME) && !is_paging(vcpu) && 878 (cr0 & X86_CR0_PG)) { 879 int cs_db, cs_l; 880 881 if (!is_pae(vcpu)) 882 return 1; 883 static_call(kvm_x86_get_cs_db_l_bits)(vcpu, &cs_db, &cs_l); 884 if (cs_l) 885 return 1; 886 } 887 #endif 888 if (!(vcpu->arch.efer & EFER_LME) && (cr0 & X86_CR0_PG) && 889 is_pae(vcpu) && ((cr0 ^ old_cr0) & pdptr_bits) && 890 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu))) 891 return 1; 892 893 if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE)) 894 return 1; 895 896 static_call(kvm_x86_set_cr0)(vcpu, cr0); 897 898 kvm_post_set_cr0(vcpu, old_cr0, cr0); 899 900 return 0; 901 } 902 EXPORT_SYMBOL_GPL(kvm_set_cr0); 903 904 void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw) 905 { 906 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f)); 907 } 908 EXPORT_SYMBOL_GPL(kvm_lmsw); 909 910 void kvm_load_guest_xsave_state(struct kvm_vcpu *vcpu) 911 { 912 if (vcpu->arch.guest_state_protected) 913 return; 914 915 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE)) { 916 917 if (vcpu->arch.xcr0 != host_xcr0) 918 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0); 919 920 if (vcpu->arch.xsaves_enabled && 921 vcpu->arch.ia32_xss != host_xss) 922 wrmsrl(MSR_IA32_XSS, vcpu->arch.ia32_xss); 923 } 924 925 if (static_cpu_has(X86_FEATURE_PKU) && 926 (kvm_read_cr4_bits(vcpu, X86_CR4_PKE) || 927 (vcpu->arch.xcr0 & XFEATURE_MASK_PKRU)) && 928 vcpu->arch.pkru != vcpu->arch.host_pkru) 929 write_pkru(vcpu->arch.pkru); 930 } 931 EXPORT_SYMBOL_GPL(kvm_load_guest_xsave_state); 932 933 void kvm_load_host_xsave_state(struct kvm_vcpu *vcpu) 934 { 935 if (vcpu->arch.guest_state_protected) 936 return; 937 938 if (static_cpu_has(X86_FEATURE_PKU) && 939 (kvm_read_cr4_bits(vcpu, X86_CR4_PKE) || 940 (vcpu->arch.xcr0 & XFEATURE_MASK_PKRU))) { 941 vcpu->arch.pkru = rdpkru(); 942 if (vcpu->arch.pkru != vcpu->arch.host_pkru) 943 write_pkru(vcpu->arch.host_pkru); 944 } 945 946 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE)) { 947 948 if (vcpu->arch.xcr0 != host_xcr0) 949 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0); 950 951 if (vcpu->arch.xsaves_enabled && 952 vcpu->arch.ia32_xss != host_xss) 953 wrmsrl(MSR_IA32_XSS, host_xss); 954 } 955 956 } 957 EXPORT_SYMBOL_GPL(kvm_load_host_xsave_state); 958 959 static int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr) 960 { 961 u64 xcr0 = xcr; 962 u64 old_xcr0 = vcpu->arch.xcr0; 963 u64 valid_bits; 964 965 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */ 966 if (index != XCR_XFEATURE_ENABLED_MASK) 967 return 1; 968 if (!(xcr0 & XFEATURE_MASK_FP)) 969 return 1; 970 if ((xcr0 & XFEATURE_MASK_YMM) && !(xcr0 & XFEATURE_MASK_SSE)) 971 return 1; 972 973 /* 974 * Do not allow the guest to set bits that we do not support 975 * saving. However, xcr0 bit 0 is always set, even if the 976 * emulated CPU does not support XSAVE (see kvm_vcpu_reset()). 977 */ 978 valid_bits = vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FP; 979 if (xcr0 & ~valid_bits) 980 return 1; 981 982 if ((!(xcr0 & XFEATURE_MASK_BNDREGS)) != 983 (!(xcr0 & XFEATURE_MASK_BNDCSR))) 984 return 1; 985 986 if (xcr0 & XFEATURE_MASK_AVX512) { 987 if (!(xcr0 & XFEATURE_MASK_YMM)) 988 return 1; 989 if ((xcr0 & XFEATURE_MASK_AVX512) != XFEATURE_MASK_AVX512) 990 return 1; 991 } 992 vcpu->arch.xcr0 = xcr0; 993 994 if ((xcr0 ^ old_xcr0) & XFEATURE_MASK_EXTEND) 995 kvm_update_cpuid_runtime(vcpu); 996 return 0; 997 } 998 999 int kvm_emulate_xsetbv(struct kvm_vcpu *vcpu) 1000 { 1001 if (static_call(kvm_x86_get_cpl)(vcpu) != 0 || 1002 __kvm_set_xcr(vcpu, kvm_rcx_read(vcpu), kvm_read_edx_eax(vcpu))) { 1003 kvm_inject_gp(vcpu, 0); 1004 return 1; 1005 } 1006 1007 return kvm_skip_emulated_instruction(vcpu); 1008 } 1009 EXPORT_SYMBOL_GPL(kvm_emulate_xsetbv); 1010 1011 bool kvm_is_valid_cr4(struct kvm_vcpu *vcpu, unsigned long cr4) 1012 { 1013 if (cr4 & cr4_reserved_bits) 1014 return false; 1015 1016 if (cr4 & vcpu->arch.cr4_guest_rsvd_bits) 1017 return false; 1018 1019 return static_call(kvm_x86_is_valid_cr4)(vcpu, cr4); 1020 } 1021 EXPORT_SYMBOL_GPL(kvm_is_valid_cr4); 1022 1023 void kvm_post_set_cr4(struct kvm_vcpu *vcpu, unsigned long old_cr4, unsigned long cr4) 1024 { 1025 /* 1026 * If any role bit is changed, the MMU needs to be reset. 1027 * 1028 * If CR4.PCIDE is changed 1 -> 0, the guest TLB must be flushed. 1029 * If CR4.PCIDE is changed 0 -> 1, there is no need to flush the TLB 1030 * according to the SDM; however, stale prev_roots could be reused 1031 * incorrectly in the future after a MOV to CR3 with NOFLUSH=1, so we 1032 * free them all. KVM_REQ_MMU_RELOAD is fit for the both cases; it 1033 * is slow, but changing CR4.PCIDE is a rare case. 1034 * 1035 * If CR4.PGE is changed, the guest TLB must be flushed. 1036 * 1037 * Note: resetting MMU is a superset of KVM_REQ_MMU_RELOAD and 1038 * KVM_REQ_MMU_RELOAD is a superset of KVM_REQ_TLB_FLUSH_GUEST, hence 1039 * the usage of "else if". 1040 */ 1041 if ((cr4 ^ old_cr4) & KVM_MMU_CR4_ROLE_BITS) 1042 kvm_mmu_reset_context(vcpu); 1043 else if ((cr4 ^ old_cr4) & X86_CR4_PCIDE) 1044 kvm_make_request(KVM_REQ_MMU_RELOAD, vcpu); 1045 else if ((cr4 ^ old_cr4) & X86_CR4_PGE) 1046 kvm_make_request(KVM_REQ_TLB_FLUSH_GUEST, vcpu); 1047 } 1048 EXPORT_SYMBOL_GPL(kvm_post_set_cr4); 1049 1050 int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4) 1051 { 1052 unsigned long old_cr4 = kvm_read_cr4(vcpu); 1053 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE | 1054 X86_CR4_SMEP; 1055 1056 if (!kvm_is_valid_cr4(vcpu, cr4)) 1057 return 1; 1058 1059 if (is_long_mode(vcpu)) { 1060 if (!(cr4 & X86_CR4_PAE)) 1061 return 1; 1062 if ((cr4 ^ old_cr4) & X86_CR4_LA57) 1063 return 1; 1064 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE) 1065 && ((cr4 ^ old_cr4) & pdptr_bits) 1066 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu, 1067 kvm_read_cr3(vcpu))) 1068 return 1; 1069 1070 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) { 1071 if (!guest_cpuid_has(vcpu, X86_FEATURE_PCID)) 1072 return 1; 1073 1074 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */ 1075 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu)) 1076 return 1; 1077 } 1078 1079 static_call(kvm_x86_set_cr4)(vcpu, cr4); 1080 1081 kvm_post_set_cr4(vcpu, old_cr4, cr4); 1082 1083 return 0; 1084 } 1085 EXPORT_SYMBOL_GPL(kvm_set_cr4); 1086 1087 static void kvm_invalidate_pcid(struct kvm_vcpu *vcpu, unsigned long pcid) 1088 { 1089 struct kvm_mmu *mmu = vcpu->arch.mmu; 1090 unsigned long roots_to_free = 0; 1091 int i; 1092 1093 /* 1094 * MOV CR3 and INVPCID are usually not intercepted when using TDP, but 1095 * this is reachable when running EPT=1 and unrestricted_guest=0, and 1096 * also via the emulator. KVM's TDP page tables are not in the scope of 1097 * the invalidation, but the guest's TLB entries need to be flushed as 1098 * the CPU may have cached entries in its TLB for the target PCID. 1099 */ 1100 if (unlikely(tdp_enabled)) { 1101 kvm_make_request(KVM_REQ_TLB_FLUSH_GUEST, vcpu); 1102 return; 1103 } 1104 1105 /* 1106 * If neither the current CR3 nor any of the prev_roots use the given 1107 * PCID, then nothing needs to be done here because a resync will 1108 * happen anyway before switching to any other CR3. 1109 */ 1110 if (kvm_get_active_pcid(vcpu) == pcid) { 1111 kvm_make_request(KVM_REQ_MMU_SYNC, vcpu); 1112 kvm_make_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu); 1113 } 1114 1115 /* 1116 * If PCID is disabled, there is no need to free prev_roots even if the 1117 * PCIDs for them are also 0, because MOV to CR3 always flushes the TLB 1118 * with PCIDE=0. 1119 */ 1120 if (!kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE)) 1121 return; 1122 1123 for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++) 1124 if (kvm_get_pcid(vcpu, mmu->prev_roots[i].pgd) == pcid) 1125 roots_to_free |= KVM_MMU_ROOT_PREVIOUS(i); 1126 1127 kvm_mmu_free_roots(vcpu, mmu, roots_to_free); 1128 } 1129 1130 int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3) 1131 { 1132 bool skip_tlb_flush = false; 1133 unsigned long pcid = 0; 1134 #ifdef CONFIG_X86_64 1135 bool pcid_enabled = kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE); 1136 1137 if (pcid_enabled) { 1138 skip_tlb_flush = cr3 & X86_CR3_PCID_NOFLUSH; 1139 cr3 &= ~X86_CR3_PCID_NOFLUSH; 1140 pcid = cr3 & X86_CR3_PCID_MASK; 1141 } 1142 #endif 1143 1144 /* PDPTRs are always reloaded for PAE paging. */ 1145 if (cr3 == kvm_read_cr3(vcpu) && !is_pae_paging(vcpu)) 1146 goto handle_tlb_flush; 1147 1148 /* 1149 * Do not condition the GPA check on long mode, this helper is used to 1150 * stuff CR3, e.g. for RSM emulation, and there is no guarantee that 1151 * the current vCPU mode is accurate. 1152 */ 1153 if (kvm_vcpu_is_illegal_gpa(vcpu, cr3)) 1154 return 1; 1155 1156 if (is_pae_paging(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3)) 1157 return 1; 1158 1159 if (cr3 != kvm_read_cr3(vcpu)) 1160 kvm_mmu_new_pgd(vcpu, cr3); 1161 1162 vcpu->arch.cr3 = cr3; 1163 kvm_register_mark_available(vcpu, VCPU_EXREG_CR3); 1164 1165 handle_tlb_flush: 1166 /* 1167 * A load of CR3 that flushes the TLB flushes only the current PCID, 1168 * even if PCID is disabled, in which case PCID=0 is flushed. It's a 1169 * moot point in the end because _disabling_ PCID will flush all PCIDs, 1170 * and it's impossible to use a non-zero PCID when PCID is disabled, 1171 * i.e. only PCID=0 can be relevant. 1172 */ 1173 if (!skip_tlb_flush) 1174 kvm_invalidate_pcid(vcpu, pcid); 1175 1176 return 0; 1177 } 1178 EXPORT_SYMBOL_GPL(kvm_set_cr3); 1179 1180 int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8) 1181 { 1182 if (cr8 & CR8_RESERVED_BITS) 1183 return 1; 1184 if (lapic_in_kernel(vcpu)) 1185 kvm_lapic_set_tpr(vcpu, cr8); 1186 else 1187 vcpu->arch.cr8 = cr8; 1188 return 0; 1189 } 1190 EXPORT_SYMBOL_GPL(kvm_set_cr8); 1191 1192 unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu) 1193 { 1194 if (lapic_in_kernel(vcpu)) 1195 return kvm_lapic_get_cr8(vcpu); 1196 else 1197 return vcpu->arch.cr8; 1198 } 1199 EXPORT_SYMBOL_GPL(kvm_get_cr8); 1200 1201 static void kvm_update_dr0123(struct kvm_vcpu *vcpu) 1202 { 1203 int i; 1204 1205 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) { 1206 for (i = 0; i < KVM_NR_DB_REGS; i++) 1207 vcpu->arch.eff_db[i] = vcpu->arch.db[i]; 1208 } 1209 } 1210 1211 void kvm_update_dr7(struct kvm_vcpu *vcpu) 1212 { 1213 unsigned long dr7; 1214 1215 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) 1216 dr7 = vcpu->arch.guest_debug_dr7; 1217 else 1218 dr7 = vcpu->arch.dr7; 1219 static_call(kvm_x86_set_dr7)(vcpu, dr7); 1220 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED; 1221 if (dr7 & DR7_BP_EN_MASK) 1222 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED; 1223 } 1224 EXPORT_SYMBOL_GPL(kvm_update_dr7); 1225 1226 static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu) 1227 { 1228 u64 fixed = DR6_FIXED_1; 1229 1230 if (!guest_cpuid_has(vcpu, X86_FEATURE_RTM)) 1231 fixed |= DR6_RTM; 1232 1233 if (!guest_cpuid_has(vcpu, X86_FEATURE_BUS_LOCK_DETECT)) 1234 fixed |= DR6_BUS_LOCK; 1235 return fixed; 1236 } 1237 1238 int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val) 1239 { 1240 size_t size = ARRAY_SIZE(vcpu->arch.db); 1241 1242 switch (dr) { 1243 case 0 ... 3: 1244 vcpu->arch.db[array_index_nospec(dr, size)] = val; 1245 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) 1246 vcpu->arch.eff_db[dr] = val; 1247 break; 1248 case 4: 1249 case 6: 1250 if (!kvm_dr6_valid(val)) 1251 return 1; /* #GP */ 1252 vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu); 1253 break; 1254 case 5: 1255 default: /* 7 */ 1256 if (!kvm_dr7_valid(val)) 1257 return 1; /* #GP */ 1258 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1; 1259 kvm_update_dr7(vcpu); 1260 break; 1261 } 1262 1263 return 0; 1264 } 1265 EXPORT_SYMBOL_GPL(kvm_set_dr); 1266 1267 void kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val) 1268 { 1269 size_t size = ARRAY_SIZE(vcpu->arch.db); 1270 1271 switch (dr) { 1272 case 0 ... 3: 1273 *val = vcpu->arch.db[array_index_nospec(dr, size)]; 1274 break; 1275 case 4: 1276 case 6: 1277 *val = vcpu->arch.dr6; 1278 break; 1279 case 5: 1280 default: /* 7 */ 1281 *val = vcpu->arch.dr7; 1282 break; 1283 } 1284 } 1285 EXPORT_SYMBOL_GPL(kvm_get_dr); 1286 1287 int kvm_emulate_rdpmc(struct kvm_vcpu *vcpu) 1288 { 1289 u32 ecx = kvm_rcx_read(vcpu); 1290 u64 data; 1291 1292 if (kvm_pmu_rdpmc(vcpu, ecx, &data)) { 1293 kvm_inject_gp(vcpu, 0); 1294 return 1; 1295 } 1296 1297 kvm_rax_write(vcpu, (u32)data); 1298 kvm_rdx_write(vcpu, data >> 32); 1299 return kvm_skip_emulated_instruction(vcpu); 1300 } 1301 EXPORT_SYMBOL_GPL(kvm_emulate_rdpmc); 1302 1303 /* 1304 * List of msr numbers which we expose to userspace through KVM_GET_MSRS 1305 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST. 1306 * 1307 * The three MSR lists(msrs_to_save, emulated_msrs, msr_based_features) 1308 * extract the supported MSRs from the related const lists. 1309 * msrs_to_save is selected from the msrs_to_save_all to reflect the 1310 * capabilities of the host cpu. This capabilities test skips MSRs that are 1311 * kvm-specific. Those are put in emulated_msrs_all; filtering of emulated_msrs 1312 * may depend on host virtualization features rather than host cpu features. 1313 */ 1314 1315 static const u32 msrs_to_save_all[] = { 1316 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP, 1317 MSR_STAR, 1318 #ifdef CONFIG_X86_64 1319 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR, 1320 #endif 1321 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA, 1322 MSR_IA32_FEAT_CTL, MSR_IA32_BNDCFGS, MSR_TSC_AUX, 1323 MSR_IA32_SPEC_CTRL, 1324 MSR_IA32_RTIT_CTL, MSR_IA32_RTIT_STATUS, MSR_IA32_RTIT_CR3_MATCH, 1325 MSR_IA32_RTIT_OUTPUT_BASE, MSR_IA32_RTIT_OUTPUT_MASK, 1326 MSR_IA32_RTIT_ADDR0_A, MSR_IA32_RTIT_ADDR0_B, 1327 MSR_IA32_RTIT_ADDR1_A, MSR_IA32_RTIT_ADDR1_B, 1328 MSR_IA32_RTIT_ADDR2_A, MSR_IA32_RTIT_ADDR2_B, 1329 MSR_IA32_RTIT_ADDR3_A, MSR_IA32_RTIT_ADDR3_B, 1330 MSR_IA32_UMWAIT_CONTROL, 1331 1332 MSR_ARCH_PERFMON_FIXED_CTR0, MSR_ARCH_PERFMON_FIXED_CTR1, 1333 MSR_ARCH_PERFMON_FIXED_CTR0 + 2, MSR_ARCH_PERFMON_FIXED_CTR0 + 3, 1334 MSR_CORE_PERF_FIXED_CTR_CTRL, MSR_CORE_PERF_GLOBAL_STATUS, 1335 MSR_CORE_PERF_GLOBAL_CTRL, MSR_CORE_PERF_GLOBAL_OVF_CTRL, 1336 MSR_ARCH_PERFMON_PERFCTR0, MSR_ARCH_PERFMON_PERFCTR1, 1337 MSR_ARCH_PERFMON_PERFCTR0 + 2, MSR_ARCH_PERFMON_PERFCTR0 + 3, 1338 MSR_ARCH_PERFMON_PERFCTR0 + 4, MSR_ARCH_PERFMON_PERFCTR0 + 5, 1339 MSR_ARCH_PERFMON_PERFCTR0 + 6, MSR_ARCH_PERFMON_PERFCTR0 + 7, 1340 MSR_ARCH_PERFMON_PERFCTR0 + 8, MSR_ARCH_PERFMON_PERFCTR0 + 9, 1341 MSR_ARCH_PERFMON_PERFCTR0 + 10, MSR_ARCH_PERFMON_PERFCTR0 + 11, 1342 MSR_ARCH_PERFMON_PERFCTR0 + 12, MSR_ARCH_PERFMON_PERFCTR0 + 13, 1343 MSR_ARCH_PERFMON_PERFCTR0 + 14, MSR_ARCH_PERFMON_PERFCTR0 + 15, 1344 MSR_ARCH_PERFMON_PERFCTR0 + 16, MSR_ARCH_PERFMON_PERFCTR0 + 17, 1345 MSR_ARCH_PERFMON_EVENTSEL0, MSR_ARCH_PERFMON_EVENTSEL1, 1346 MSR_ARCH_PERFMON_EVENTSEL0 + 2, MSR_ARCH_PERFMON_EVENTSEL0 + 3, 1347 MSR_ARCH_PERFMON_EVENTSEL0 + 4, MSR_ARCH_PERFMON_EVENTSEL0 + 5, 1348 MSR_ARCH_PERFMON_EVENTSEL0 + 6, MSR_ARCH_PERFMON_EVENTSEL0 + 7, 1349 MSR_ARCH_PERFMON_EVENTSEL0 + 8, MSR_ARCH_PERFMON_EVENTSEL0 + 9, 1350 MSR_ARCH_PERFMON_EVENTSEL0 + 10, MSR_ARCH_PERFMON_EVENTSEL0 + 11, 1351 MSR_ARCH_PERFMON_EVENTSEL0 + 12, MSR_ARCH_PERFMON_EVENTSEL0 + 13, 1352 MSR_ARCH_PERFMON_EVENTSEL0 + 14, MSR_ARCH_PERFMON_EVENTSEL0 + 15, 1353 MSR_ARCH_PERFMON_EVENTSEL0 + 16, MSR_ARCH_PERFMON_EVENTSEL0 + 17, 1354 1355 MSR_K7_EVNTSEL0, MSR_K7_EVNTSEL1, MSR_K7_EVNTSEL2, MSR_K7_EVNTSEL3, 1356 MSR_K7_PERFCTR0, MSR_K7_PERFCTR1, MSR_K7_PERFCTR2, MSR_K7_PERFCTR3, 1357 MSR_F15H_PERF_CTL0, MSR_F15H_PERF_CTL1, MSR_F15H_PERF_CTL2, 1358 MSR_F15H_PERF_CTL3, MSR_F15H_PERF_CTL4, MSR_F15H_PERF_CTL5, 1359 MSR_F15H_PERF_CTR0, MSR_F15H_PERF_CTR1, MSR_F15H_PERF_CTR2, 1360 MSR_F15H_PERF_CTR3, MSR_F15H_PERF_CTR4, MSR_F15H_PERF_CTR5, 1361 }; 1362 1363 static u32 msrs_to_save[ARRAY_SIZE(msrs_to_save_all)]; 1364 static unsigned num_msrs_to_save; 1365 1366 static const u32 emulated_msrs_all[] = { 1367 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK, 1368 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW, 1369 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL, 1370 HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC, 1371 HV_X64_MSR_TSC_FREQUENCY, HV_X64_MSR_APIC_FREQUENCY, 1372 HV_X64_MSR_CRASH_P0, HV_X64_MSR_CRASH_P1, HV_X64_MSR_CRASH_P2, 1373 HV_X64_MSR_CRASH_P3, HV_X64_MSR_CRASH_P4, HV_X64_MSR_CRASH_CTL, 1374 HV_X64_MSR_RESET, 1375 HV_X64_MSR_VP_INDEX, 1376 HV_X64_MSR_VP_RUNTIME, 1377 HV_X64_MSR_SCONTROL, 1378 HV_X64_MSR_STIMER0_CONFIG, 1379 HV_X64_MSR_VP_ASSIST_PAGE, 1380 HV_X64_MSR_REENLIGHTENMENT_CONTROL, HV_X64_MSR_TSC_EMULATION_CONTROL, 1381 HV_X64_MSR_TSC_EMULATION_STATUS, 1382 HV_X64_MSR_SYNDBG_OPTIONS, 1383 HV_X64_MSR_SYNDBG_CONTROL, HV_X64_MSR_SYNDBG_STATUS, 1384 HV_X64_MSR_SYNDBG_SEND_BUFFER, HV_X64_MSR_SYNDBG_RECV_BUFFER, 1385 HV_X64_MSR_SYNDBG_PENDING_BUFFER, 1386 1387 MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME, 1388 MSR_KVM_PV_EOI_EN, MSR_KVM_ASYNC_PF_INT, MSR_KVM_ASYNC_PF_ACK, 1389 1390 MSR_IA32_TSC_ADJUST, 1391 MSR_IA32_TSC_DEADLINE, 1392 MSR_IA32_ARCH_CAPABILITIES, 1393 MSR_IA32_PERF_CAPABILITIES, 1394 MSR_IA32_MISC_ENABLE, 1395 MSR_IA32_MCG_STATUS, 1396 MSR_IA32_MCG_CTL, 1397 MSR_IA32_MCG_EXT_CTL, 1398 MSR_IA32_SMBASE, 1399 MSR_SMI_COUNT, 1400 MSR_PLATFORM_INFO, 1401 MSR_MISC_FEATURES_ENABLES, 1402 MSR_AMD64_VIRT_SPEC_CTRL, 1403 MSR_AMD64_TSC_RATIO, 1404 MSR_IA32_POWER_CTL, 1405 MSR_IA32_UCODE_REV, 1406 1407 /* 1408 * The following list leaves out MSRs whose values are determined 1409 * by arch/x86/kvm/vmx/nested.c based on CPUID or other MSRs. 1410 * We always support the "true" VMX control MSRs, even if the host 1411 * processor does not, so I am putting these registers here rather 1412 * than in msrs_to_save_all. 1413 */ 1414 MSR_IA32_VMX_BASIC, 1415 MSR_IA32_VMX_TRUE_PINBASED_CTLS, 1416 MSR_IA32_VMX_TRUE_PROCBASED_CTLS, 1417 MSR_IA32_VMX_TRUE_EXIT_CTLS, 1418 MSR_IA32_VMX_TRUE_ENTRY_CTLS, 1419 MSR_IA32_VMX_MISC, 1420 MSR_IA32_VMX_CR0_FIXED0, 1421 MSR_IA32_VMX_CR4_FIXED0, 1422 MSR_IA32_VMX_VMCS_ENUM, 1423 MSR_IA32_VMX_PROCBASED_CTLS2, 1424 MSR_IA32_VMX_EPT_VPID_CAP, 1425 MSR_IA32_VMX_VMFUNC, 1426 1427 MSR_K7_HWCR, 1428 MSR_KVM_POLL_CONTROL, 1429 }; 1430 1431 static u32 emulated_msrs[ARRAY_SIZE(emulated_msrs_all)]; 1432 static unsigned num_emulated_msrs; 1433 1434 /* 1435 * List of msr numbers which are used to expose MSR-based features that 1436 * can be used by a hypervisor to validate requested CPU features. 1437 */ 1438 static const u32 msr_based_features_all[] = { 1439 MSR_IA32_VMX_BASIC, 1440 MSR_IA32_VMX_TRUE_PINBASED_CTLS, 1441 MSR_IA32_VMX_PINBASED_CTLS, 1442 MSR_IA32_VMX_TRUE_PROCBASED_CTLS, 1443 MSR_IA32_VMX_PROCBASED_CTLS, 1444 MSR_IA32_VMX_TRUE_EXIT_CTLS, 1445 MSR_IA32_VMX_EXIT_CTLS, 1446 MSR_IA32_VMX_TRUE_ENTRY_CTLS, 1447 MSR_IA32_VMX_ENTRY_CTLS, 1448 MSR_IA32_VMX_MISC, 1449 MSR_IA32_VMX_CR0_FIXED0, 1450 MSR_IA32_VMX_CR0_FIXED1, 1451 MSR_IA32_VMX_CR4_FIXED0, 1452 MSR_IA32_VMX_CR4_FIXED1, 1453 MSR_IA32_VMX_VMCS_ENUM, 1454 MSR_IA32_VMX_PROCBASED_CTLS2, 1455 MSR_IA32_VMX_EPT_VPID_CAP, 1456 MSR_IA32_VMX_VMFUNC, 1457 1458 MSR_F10H_DECFG, 1459 MSR_IA32_UCODE_REV, 1460 MSR_IA32_ARCH_CAPABILITIES, 1461 MSR_IA32_PERF_CAPABILITIES, 1462 }; 1463 1464 static u32 msr_based_features[ARRAY_SIZE(msr_based_features_all)]; 1465 static unsigned int num_msr_based_features; 1466 1467 static u64 kvm_get_arch_capabilities(void) 1468 { 1469 u64 data = 0; 1470 1471 if (boot_cpu_has(X86_FEATURE_ARCH_CAPABILITIES)) 1472 rdmsrl(MSR_IA32_ARCH_CAPABILITIES, data); 1473 1474 /* 1475 * If nx_huge_pages is enabled, KVM's shadow paging will ensure that 1476 * the nested hypervisor runs with NX huge pages. If it is not, 1477 * L1 is anyway vulnerable to ITLB_MULTIHIT exploits from other 1478 * L1 guests, so it need not worry about its own (L2) guests. 1479 */ 1480 data |= ARCH_CAP_PSCHANGE_MC_NO; 1481 1482 /* 1483 * If we're doing cache flushes (either "always" or "cond") 1484 * we will do one whenever the guest does a vmlaunch/vmresume. 1485 * If an outer hypervisor is doing the cache flush for us 1486 * (VMENTER_L1D_FLUSH_NESTED_VM), we can safely pass that 1487 * capability to the guest too, and if EPT is disabled we're not 1488 * vulnerable. Overall, only VMENTER_L1D_FLUSH_NEVER will 1489 * require a nested hypervisor to do a flush of its own. 1490 */ 1491 if (l1tf_vmx_mitigation != VMENTER_L1D_FLUSH_NEVER) 1492 data |= ARCH_CAP_SKIP_VMENTRY_L1DFLUSH; 1493 1494 if (!boot_cpu_has_bug(X86_BUG_CPU_MELTDOWN)) 1495 data |= ARCH_CAP_RDCL_NO; 1496 if (!boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS)) 1497 data |= ARCH_CAP_SSB_NO; 1498 if (!boot_cpu_has_bug(X86_BUG_MDS)) 1499 data |= ARCH_CAP_MDS_NO; 1500 1501 if (!boot_cpu_has(X86_FEATURE_RTM)) { 1502 /* 1503 * If RTM=0 because the kernel has disabled TSX, the host might 1504 * have TAA_NO or TSX_CTRL. Clear TAA_NO (the guest sees RTM=0 1505 * and therefore knows that there cannot be TAA) but keep 1506 * TSX_CTRL: some buggy userspaces leave it set on tsx=on hosts, 1507 * and we want to allow migrating those guests to tsx=off hosts. 1508 */ 1509 data &= ~ARCH_CAP_TAA_NO; 1510 } else if (!boot_cpu_has_bug(X86_BUG_TAA)) { 1511 data |= ARCH_CAP_TAA_NO; 1512 } else { 1513 /* 1514 * Nothing to do here; we emulate TSX_CTRL if present on the 1515 * host so the guest can choose between disabling TSX or 1516 * using VERW to clear CPU buffers. 1517 */ 1518 } 1519 1520 return data; 1521 } 1522 1523 static int kvm_get_msr_feature(struct kvm_msr_entry *msr) 1524 { 1525 switch (msr->index) { 1526 case MSR_IA32_ARCH_CAPABILITIES: 1527 msr->data = kvm_get_arch_capabilities(); 1528 break; 1529 case MSR_IA32_UCODE_REV: 1530 rdmsrl_safe(msr->index, &msr->data); 1531 break; 1532 default: 1533 return static_call(kvm_x86_get_msr_feature)(msr); 1534 } 1535 return 0; 1536 } 1537 1538 static int do_get_msr_feature(struct kvm_vcpu *vcpu, unsigned index, u64 *data) 1539 { 1540 struct kvm_msr_entry msr; 1541 int r; 1542 1543 msr.index = index; 1544 r = kvm_get_msr_feature(&msr); 1545 1546 if (r == KVM_MSR_RET_INVALID) { 1547 /* Unconditionally clear the output for simplicity */ 1548 *data = 0; 1549 if (kvm_msr_ignored_check(index, 0, false)) 1550 r = 0; 1551 } 1552 1553 if (r) 1554 return r; 1555 1556 *data = msr.data; 1557 1558 return 0; 1559 } 1560 1561 static bool __kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer) 1562 { 1563 if (efer & EFER_FFXSR && !guest_cpuid_has(vcpu, X86_FEATURE_FXSR_OPT)) 1564 return false; 1565 1566 if (efer & EFER_SVME && !guest_cpuid_has(vcpu, X86_FEATURE_SVM)) 1567 return false; 1568 1569 if (efer & (EFER_LME | EFER_LMA) && 1570 !guest_cpuid_has(vcpu, X86_FEATURE_LM)) 1571 return false; 1572 1573 if (efer & EFER_NX && !guest_cpuid_has(vcpu, X86_FEATURE_NX)) 1574 return false; 1575 1576 return true; 1577 1578 } 1579 bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer) 1580 { 1581 if (efer & efer_reserved_bits) 1582 return false; 1583 1584 return __kvm_valid_efer(vcpu, efer); 1585 } 1586 EXPORT_SYMBOL_GPL(kvm_valid_efer); 1587 1588 static int set_efer(struct kvm_vcpu *vcpu, struct msr_data *msr_info) 1589 { 1590 u64 old_efer = vcpu->arch.efer; 1591 u64 efer = msr_info->data; 1592 int r; 1593 1594 if (efer & efer_reserved_bits) 1595 return 1; 1596 1597 if (!msr_info->host_initiated) { 1598 if (!__kvm_valid_efer(vcpu, efer)) 1599 return 1; 1600 1601 if (is_paging(vcpu) && 1602 (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME)) 1603 return 1; 1604 } 1605 1606 efer &= ~EFER_LMA; 1607 efer |= vcpu->arch.efer & EFER_LMA; 1608 1609 r = static_call(kvm_x86_set_efer)(vcpu, efer); 1610 if (r) { 1611 WARN_ON(r > 0); 1612 return r; 1613 } 1614 1615 /* Update reserved bits */ 1616 if ((efer ^ old_efer) & EFER_NX) 1617 kvm_mmu_reset_context(vcpu); 1618 1619 return 0; 1620 } 1621 1622 void kvm_enable_efer_bits(u64 mask) 1623 { 1624 efer_reserved_bits &= ~mask; 1625 } 1626 EXPORT_SYMBOL_GPL(kvm_enable_efer_bits); 1627 1628 bool kvm_msr_allowed(struct kvm_vcpu *vcpu, u32 index, u32 type) 1629 { 1630 struct kvm_x86_msr_filter *msr_filter; 1631 struct msr_bitmap_range *ranges; 1632 struct kvm *kvm = vcpu->kvm; 1633 bool allowed; 1634 int idx; 1635 u32 i; 1636 1637 /* x2APIC MSRs do not support filtering. */ 1638 if (index >= 0x800 && index <= 0x8ff) 1639 return true; 1640 1641 idx = srcu_read_lock(&kvm->srcu); 1642 1643 msr_filter = srcu_dereference(kvm->arch.msr_filter, &kvm->srcu); 1644 if (!msr_filter) { 1645 allowed = true; 1646 goto out; 1647 } 1648 1649 allowed = msr_filter->default_allow; 1650 ranges = msr_filter->ranges; 1651 1652 for (i = 0; i < msr_filter->count; i++) { 1653 u32 start = ranges[i].base; 1654 u32 end = start + ranges[i].nmsrs; 1655 u32 flags = ranges[i].flags; 1656 unsigned long *bitmap = ranges[i].bitmap; 1657 1658 if ((index >= start) && (index < end) && (flags & type)) { 1659 allowed = !!test_bit(index - start, bitmap); 1660 break; 1661 } 1662 } 1663 1664 out: 1665 srcu_read_unlock(&kvm->srcu, idx); 1666 1667 return allowed; 1668 } 1669 EXPORT_SYMBOL_GPL(kvm_msr_allowed); 1670 1671 /* 1672 * Write @data into the MSR specified by @index. Select MSR specific fault 1673 * checks are bypassed if @host_initiated is %true. 1674 * Returns 0 on success, non-0 otherwise. 1675 * Assumes vcpu_load() was already called. 1676 */ 1677 static int __kvm_set_msr(struct kvm_vcpu *vcpu, u32 index, u64 data, 1678 bool host_initiated) 1679 { 1680 struct msr_data msr; 1681 1682 if (!host_initiated && !kvm_msr_allowed(vcpu, index, KVM_MSR_FILTER_WRITE)) 1683 return KVM_MSR_RET_FILTERED; 1684 1685 switch (index) { 1686 case MSR_FS_BASE: 1687 case MSR_GS_BASE: 1688 case MSR_KERNEL_GS_BASE: 1689 case MSR_CSTAR: 1690 case MSR_LSTAR: 1691 if (is_noncanonical_address(data, vcpu)) 1692 return 1; 1693 break; 1694 case MSR_IA32_SYSENTER_EIP: 1695 case MSR_IA32_SYSENTER_ESP: 1696 /* 1697 * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if 1698 * non-canonical address is written on Intel but not on 1699 * AMD (which ignores the top 32-bits, because it does 1700 * not implement 64-bit SYSENTER). 1701 * 1702 * 64-bit code should hence be able to write a non-canonical 1703 * value on AMD. Making the address canonical ensures that 1704 * vmentry does not fail on Intel after writing a non-canonical 1705 * value, and that something deterministic happens if the guest 1706 * invokes 64-bit SYSENTER. 1707 */ 1708 data = get_canonical(data, vcpu_virt_addr_bits(vcpu)); 1709 break; 1710 case MSR_TSC_AUX: 1711 if (!kvm_is_supported_user_return_msr(MSR_TSC_AUX)) 1712 return 1; 1713 1714 if (!host_initiated && 1715 !guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP) && 1716 !guest_cpuid_has(vcpu, X86_FEATURE_RDPID)) 1717 return 1; 1718 1719 /* 1720 * Per Intel's SDM, bits 63:32 are reserved, but AMD's APM has 1721 * incomplete and conflicting architectural behavior. Current 1722 * AMD CPUs completely ignore bits 63:32, i.e. they aren't 1723 * reserved and always read as zeros. Enforce Intel's reserved 1724 * bits check if and only if the guest CPU is Intel, and clear 1725 * the bits in all other cases. This ensures cross-vendor 1726 * migration will provide consistent behavior for the guest. 1727 */ 1728 if (guest_cpuid_is_intel(vcpu) && (data >> 32) != 0) 1729 return 1; 1730 1731 data = (u32)data; 1732 break; 1733 } 1734 1735 msr.data = data; 1736 msr.index = index; 1737 msr.host_initiated = host_initiated; 1738 1739 return static_call(kvm_x86_set_msr)(vcpu, &msr); 1740 } 1741 1742 static int kvm_set_msr_ignored_check(struct kvm_vcpu *vcpu, 1743 u32 index, u64 data, bool host_initiated) 1744 { 1745 int ret = __kvm_set_msr(vcpu, index, data, host_initiated); 1746 1747 if (ret == KVM_MSR_RET_INVALID) 1748 if (kvm_msr_ignored_check(index, data, true)) 1749 ret = 0; 1750 1751 return ret; 1752 } 1753 1754 /* 1755 * Read the MSR specified by @index into @data. Select MSR specific fault 1756 * checks are bypassed if @host_initiated is %true. 1757 * Returns 0 on success, non-0 otherwise. 1758 * Assumes vcpu_load() was already called. 1759 */ 1760 int __kvm_get_msr(struct kvm_vcpu *vcpu, u32 index, u64 *data, 1761 bool host_initiated) 1762 { 1763 struct msr_data msr; 1764 int ret; 1765 1766 if (!host_initiated && !kvm_msr_allowed(vcpu, index, KVM_MSR_FILTER_READ)) 1767 return KVM_MSR_RET_FILTERED; 1768 1769 switch (index) { 1770 case MSR_TSC_AUX: 1771 if (!kvm_is_supported_user_return_msr(MSR_TSC_AUX)) 1772 return 1; 1773 1774 if (!host_initiated && 1775 !guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP) && 1776 !guest_cpuid_has(vcpu, X86_FEATURE_RDPID)) 1777 return 1; 1778 break; 1779 } 1780 1781 msr.index = index; 1782 msr.host_initiated = host_initiated; 1783 1784 ret = static_call(kvm_x86_get_msr)(vcpu, &msr); 1785 if (!ret) 1786 *data = msr.data; 1787 return ret; 1788 } 1789 1790 static int kvm_get_msr_ignored_check(struct kvm_vcpu *vcpu, 1791 u32 index, u64 *data, bool host_initiated) 1792 { 1793 int ret = __kvm_get_msr(vcpu, index, data, host_initiated); 1794 1795 if (ret == KVM_MSR_RET_INVALID) { 1796 /* Unconditionally clear *data for simplicity */ 1797 *data = 0; 1798 if (kvm_msr_ignored_check(index, 0, false)) 1799 ret = 0; 1800 } 1801 1802 return ret; 1803 } 1804 1805 int kvm_get_msr(struct kvm_vcpu *vcpu, u32 index, u64 *data) 1806 { 1807 return kvm_get_msr_ignored_check(vcpu, index, data, false); 1808 } 1809 EXPORT_SYMBOL_GPL(kvm_get_msr); 1810 1811 int kvm_set_msr(struct kvm_vcpu *vcpu, u32 index, u64 data) 1812 { 1813 return kvm_set_msr_ignored_check(vcpu, index, data, false); 1814 } 1815 EXPORT_SYMBOL_GPL(kvm_set_msr); 1816 1817 static int complete_emulated_rdmsr(struct kvm_vcpu *vcpu) 1818 { 1819 int err = vcpu->run->msr.error; 1820 if (!err) { 1821 kvm_rax_write(vcpu, (u32)vcpu->run->msr.data); 1822 kvm_rdx_write(vcpu, vcpu->run->msr.data >> 32); 1823 } 1824 1825 return static_call(kvm_x86_complete_emulated_msr)(vcpu, err); 1826 } 1827 1828 static int complete_emulated_wrmsr(struct kvm_vcpu *vcpu) 1829 { 1830 return static_call(kvm_x86_complete_emulated_msr)(vcpu, vcpu->run->msr.error); 1831 } 1832 1833 static u64 kvm_msr_reason(int r) 1834 { 1835 switch (r) { 1836 case KVM_MSR_RET_INVALID: 1837 return KVM_MSR_EXIT_REASON_UNKNOWN; 1838 case KVM_MSR_RET_FILTERED: 1839 return KVM_MSR_EXIT_REASON_FILTER; 1840 default: 1841 return KVM_MSR_EXIT_REASON_INVAL; 1842 } 1843 } 1844 1845 static int kvm_msr_user_space(struct kvm_vcpu *vcpu, u32 index, 1846 u32 exit_reason, u64 data, 1847 int (*completion)(struct kvm_vcpu *vcpu), 1848 int r) 1849 { 1850 u64 msr_reason = kvm_msr_reason(r); 1851 1852 /* Check if the user wanted to know about this MSR fault */ 1853 if (!(vcpu->kvm->arch.user_space_msr_mask & msr_reason)) 1854 return 0; 1855 1856 vcpu->run->exit_reason = exit_reason; 1857 vcpu->run->msr.error = 0; 1858 memset(vcpu->run->msr.pad, 0, sizeof(vcpu->run->msr.pad)); 1859 vcpu->run->msr.reason = msr_reason; 1860 vcpu->run->msr.index = index; 1861 vcpu->run->msr.data = data; 1862 vcpu->arch.complete_userspace_io = completion; 1863 1864 return 1; 1865 } 1866 1867 static int kvm_get_msr_user_space(struct kvm_vcpu *vcpu, u32 index, int r) 1868 { 1869 return kvm_msr_user_space(vcpu, index, KVM_EXIT_X86_RDMSR, 0, 1870 complete_emulated_rdmsr, r); 1871 } 1872 1873 static int kvm_set_msr_user_space(struct kvm_vcpu *vcpu, u32 index, u64 data, int r) 1874 { 1875 return kvm_msr_user_space(vcpu, index, KVM_EXIT_X86_WRMSR, data, 1876 complete_emulated_wrmsr, r); 1877 } 1878 1879 int kvm_emulate_rdmsr(struct kvm_vcpu *vcpu) 1880 { 1881 u32 ecx = kvm_rcx_read(vcpu); 1882 u64 data; 1883 int r; 1884 1885 r = kvm_get_msr(vcpu, ecx, &data); 1886 1887 /* MSR read failed? See if we should ask user space */ 1888 if (r && kvm_get_msr_user_space(vcpu, ecx, r)) { 1889 /* Bounce to user space */ 1890 return 0; 1891 } 1892 1893 if (!r) { 1894 trace_kvm_msr_read(ecx, data); 1895 1896 kvm_rax_write(vcpu, data & -1u); 1897 kvm_rdx_write(vcpu, (data >> 32) & -1u); 1898 } else { 1899 trace_kvm_msr_read_ex(ecx); 1900 } 1901 1902 return static_call(kvm_x86_complete_emulated_msr)(vcpu, r); 1903 } 1904 EXPORT_SYMBOL_GPL(kvm_emulate_rdmsr); 1905 1906 int kvm_emulate_wrmsr(struct kvm_vcpu *vcpu) 1907 { 1908 u32 ecx = kvm_rcx_read(vcpu); 1909 u64 data = kvm_read_edx_eax(vcpu); 1910 int r; 1911 1912 r = kvm_set_msr(vcpu, ecx, data); 1913 1914 /* MSR write failed? See if we should ask user space */ 1915 if (r && kvm_set_msr_user_space(vcpu, ecx, data, r)) 1916 /* Bounce to user space */ 1917 return 0; 1918 1919 /* Signal all other negative errors to userspace */ 1920 if (r < 0) 1921 return r; 1922 1923 if (!r) 1924 trace_kvm_msr_write(ecx, data); 1925 else 1926 trace_kvm_msr_write_ex(ecx, data); 1927 1928 return static_call(kvm_x86_complete_emulated_msr)(vcpu, r); 1929 } 1930 EXPORT_SYMBOL_GPL(kvm_emulate_wrmsr); 1931 1932 int kvm_emulate_as_nop(struct kvm_vcpu *vcpu) 1933 { 1934 return kvm_skip_emulated_instruction(vcpu); 1935 } 1936 EXPORT_SYMBOL_GPL(kvm_emulate_as_nop); 1937 1938 int kvm_emulate_invd(struct kvm_vcpu *vcpu) 1939 { 1940 /* Treat an INVD instruction as a NOP and just skip it. */ 1941 return kvm_emulate_as_nop(vcpu); 1942 } 1943 EXPORT_SYMBOL_GPL(kvm_emulate_invd); 1944 1945 int kvm_emulate_mwait(struct kvm_vcpu *vcpu) 1946 { 1947 pr_warn_once("kvm: MWAIT instruction emulated as NOP!\n"); 1948 return kvm_emulate_as_nop(vcpu); 1949 } 1950 EXPORT_SYMBOL_GPL(kvm_emulate_mwait); 1951 1952 int kvm_handle_invalid_op(struct kvm_vcpu *vcpu) 1953 { 1954 kvm_queue_exception(vcpu, UD_VECTOR); 1955 return 1; 1956 } 1957 EXPORT_SYMBOL_GPL(kvm_handle_invalid_op); 1958 1959 int kvm_emulate_monitor(struct kvm_vcpu *vcpu) 1960 { 1961 pr_warn_once("kvm: MONITOR instruction emulated as NOP!\n"); 1962 return kvm_emulate_as_nop(vcpu); 1963 } 1964 EXPORT_SYMBOL_GPL(kvm_emulate_monitor); 1965 1966 static inline bool kvm_vcpu_exit_request(struct kvm_vcpu *vcpu) 1967 { 1968 xfer_to_guest_mode_prepare(); 1969 return vcpu->mode == EXITING_GUEST_MODE || kvm_request_pending(vcpu) || 1970 xfer_to_guest_mode_work_pending(); 1971 } 1972 1973 /* 1974 * The fast path for frequent and performance sensitive wrmsr emulation, 1975 * i.e. the sending of IPI, sending IPI early in the VM-Exit flow reduces 1976 * the latency of virtual IPI by avoiding the expensive bits of transitioning 1977 * from guest to host, e.g. reacquiring KVM's SRCU lock. In contrast to the 1978 * other cases which must be called after interrupts are enabled on the host. 1979 */ 1980 static int handle_fastpath_set_x2apic_icr_irqoff(struct kvm_vcpu *vcpu, u64 data) 1981 { 1982 if (!lapic_in_kernel(vcpu) || !apic_x2apic_mode(vcpu->arch.apic)) 1983 return 1; 1984 1985 if (((data & APIC_SHORT_MASK) == APIC_DEST_NOSHORT) && 1986 ((data & APIC_DEST_MASK) == APIC_DEST_PHYSICAL) && 1987 ((data & APIC_MODE_MASK) == APIC_DM_FIXED) && 1988 ((u32)(data >> 32) != X2APIC_BROADCAST)) { 1989 1990 data &= ~(1 << 12); 1991 kvm_apic_send_ipi(vcpu->arch.apic, (u32)data, (u32)(data >> 32)); 1992 kvm_lapic_set_reg(vcpu->arch.apic, APIC_ICR2, (u32)(data >> 32)); 1993 kvm_lapic_set_reg(vcpu->arch.apic, APIC_ICR, (u32)data); 1994 trace_kvm_apic_write(APIC_ICR, (u32)data); 1995 return 0; 1996 } 1997 1998 return 1; 1999 } 2000 2001 static int handle_fastpath_set_tscdeadline(struct kvm_vcpu *vcpu, u64 data) 2002 { 2003 if (!kvm_can_use_hv_timer(vcpu)) 2004 return 1; 2005 2006 kvm_set_lapic_tscdeadline_msr(vcpu, data); 2007 return 0; 2008 } 2009 2010 fastpath_t handle_fastpath_set_msr_irqoff(struct kvm_vcpu *vcpu) 2011 { 2012 u32 msr = kvm_rcx_read(vcpu); 2013 u64 data; 2014 fastpath_t ret = EXIT_FASTPATH_NONE; 2015 2016 switch (msr) { 2017 case APIC_BASE_MSR + (APIC_ICR >> 4): 2018 data = kvm_read_edx_eax(vcpu); 2019 if (!handle_fastpath_set_x2apic_icr_irqoff(vcpu, data)) { 2020 kvm_skip_emulated_instruction(vcpu); 2021 ret = EXIT_FASTPATH_EXIT_HANDLED; 2022 } 2023 break; 2024 case MSR_IA32_TSC_DEADLINE: 2025 data = kvm_read_edx_eax(vcpu); 2026 if (!handle_fastpath_set_tscdeadline(vcpu, data)) { 2027 kvm_skip_emulated_instruction(vcpu); 2028 ret = EXIT_FASTPATH_REENTER_GUEST; 2029 } 2030 break; 2031 default: 2032 break; 2033 } 2034 2035 if (ret != EXIT_FASTPATH_NONE) 2036 trace_kvm_msr_write(msr, data); 2037 2038 return ret; 2039 } 2040 EXPORT_SYMBOL_GPL(handle_fastpath_set_msr_irqoff); 2041 2042 /* 2043 * Adapt set_msr() to msr_io()'s calling convention 2044 */ 2045 static int do_get_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data) 2046 { 2047 return kvm_get_msr_ignored_check(vcpu, index, data, true); 2048 } 2049 2050 static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data) 2051 { 2052 return kvm_set_msr_ignored_check(vcpu, index, *data, true); 2053 } 2054 2055 #ifdef CONFIG_X86_64 2056 struct pvclock_clock { 2057 int vclock_mode; 2058 u64 cycle_last; 2059 u64 mask; 2060 u32 mult; 2061 u32 shift; 2062 u64 base_cycles; 2063 u64 offset; 2064 }; 2065 2066 struct pvclock_gtod_data { 2067 seqcount_t seq; 2068 2069 struct pvclock_clock clock; /* extract of a clocksource struct */ 2070 struct pvclock_clock raw_clock; /* extract of a clocksource struct */ 2071 2072 ktime_t offs_boot; 2073 u64 wall_time_sec; 2074 }; 2075 2076 static struct pvclock_gtod_data pvclock_gtod_data; 2077 2078 static void update_pvclock_gtod(struct timekeeper *tk) 2079 { 2080 struct pvclock_gtod_data *vdata = &pvclock_gtod_data; 2081 2082 write_seqcount_begin(&vdata->seq); 2083 2084 /* copy pvclock gtod data */ 2085 vdata->clock.vclock_mode = tk->tkr_mono.clock->vdso_clock_mode; 2086 vdata->clock.cycle_last = tk->tkr_mono.cycle_last; 2087 vdata->clock.mask = tk->tkr_mono.mask; 2088 vdata->clock.mult = tk->tkr_mono.mult; 2089 vdata->clock.shift = tk->tkr_mono.shift; 2090 vdata->clock.base_cycles = tk->tkr_mono.xtime_nsec; 2091 vdata->clock.offset = tk->tkr_mono.base; 2092 2093 vdata->raw_clock.vclock_mode = tk->tkr_raw.clock->vdso_clock_mode; 2094 vdata->raw_clock.cycle_last = tk->tkr_raw.cycle_last; 2095 vdata->raw_clock.mask = tk->tkr_raw.mask; 2096 vdata->raw_clock.mult = tk->tkr_raw.mult; 2097 vdata->raw_clock.shift = tk->tkr_raw.shift; 2098 vdata->raw_clock.base_cycles = tk->tkr_raw.xtime_nsec; 2099 vdata->raw_clock.offset = tk->tkr_raw.base; 2100 2101 vdata->wall_time_sec = tk->xtime_sec; 2102 2103 vdata->offs_boot = tk->offs_boot; 2104 2105 write_seqcount_end(&vdata->seq); 2106 } 2107 2108 static s64 get_kvmclock_base_ns(void) 2109 { 2110 /* Count up from boot time, but with the frequency of the raw clock. */ 2111 return ktime_to_ns(ktime_add(ktime_get_raw(), pvclock_gtod_data.offs_boot)); 2112 } 2113 #else 2114 static s64 get_kvmclock_base_ns(void) 2115 { 2116 /* Master clock not used, so we can just use CLOCK_BOOTTIME. */ 2117 return ktime_get_boottime_ns(); 2118 } 2119 #endif 2120 2121 void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock, int sec_hi_ofs) 2122 { 2123 int version; 2124 int r; 2125 struct pvclock_wall_clock wc; 2126 u32 wc_sec_hi; 2127 u64 wall_nsec; 2128 2129 if (!wall_clock) 2130 return; 2131 2132 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version)); 2133 if (r) 2134 return; 2135 2136 if (version & 1) 2137 ++version; /* first time write, random junk */ 2138 2139 ++version; 2140 2141 if (kvm_write_guest(kvm, wall_clock, &version, sizeof(version))) 2142 return; 2143 2144 /* 2145 * The guest calculates current wall clock time by adding 2146 * system time (updated by kvm_guest_time_update below) to the 2147 * wall clock specified here. We do the reverse here. 2148 */ 2149 wall_nsec = ktime_get_real_ns() - get_kvmclock_ns(kvm); 2150 2151 wc.nsec = do_div(wall_nsec, 1000000000); 2152 wc.sec = (u32)wall_nsec; /* overflow in 2106 guest time */ 2153 wc.version = version; 2154 2155 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc)); 2156 2157 if (sec_hi_ofs) { 2158 wc_sec_hi = wall_nsec >> 32; 2159 kvm_write_guest(kvm, wall_clock + sec_hi_ofs, 2160 &wc_sec_hi, sizeof(wc_sec_hi)); 2161 } 2162 2163 version++; 2164 kvm_write_guest(kvm, wall_clock, &version, sizeof(version)); 2165 } 2166 2167 static void kvm_write_system_time(struct kvm_vcpu *vcpu, gpa_t system_time, 2168 bool old_msr, bool host_initiated) 2169 { 2170 struct kvm_arch *ka = &vcpu->kvm->arch; 2171 2172 if (vcpu->vcpu_id == 0 && !host_initiated) { 2173 if (ka->boot_vcpu_runs_old_kvmclock != old_msr) 2174 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu); 2175 2176 ka->boot_vcpu_runs_old_kvmclock = old_msr; 2177 } 2178 2179 vcpu->arch.time = system_time; 2180 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu); 2181 2182 /* we verify if the enable bit is set... */ 2183 vcpu->arch.pv_time_enabled = false; 2184 if (!(system_time & 1)) 2185 return; 2186 2187 if (!kvm_gfn_to_hva_cache_init(vcpu->kvm, 2188 &vcpu->arch.pv_time, system_time & ~1ULL, 2189 sizeof(struct pvclock_vcpu_time_info))) 2190 vcpu->arch.pv_time_enabled = true; 2191 2192 return; 2193 } 2194 2195 static uint32_t div_frac(uint32_t dividend, uint32_t divisor) 2196 { 2197 do_shl32_div32(dividend, divisor); 2198 return dividend; 2199 } 2200 2201 static void kvm_get_time_scale(uint64_t scaled_hz, uint64_t base_hz, 2202 s8 *pshift, u32 *pmultiplier) 2203 { 2204 uint64_t scaled64; 2205 int32_t shift = 0; 2206 uint64_t tps64; 2207 uint32_t tps32; 2208 2209 tps64 = base_hz; 2210 scaled64 = scaled_hz; 2211 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) { 2212 tps64 >>= 1; 2213 shift--; 2214 } 2215 2216 tps32 = (uint32_t)tps64; 2217 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) { 2218 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000) 2219 scaled64 >>= 1; 2220 else 2221 tps32 <<= 1; 2222 shift++; 2223 } 2224 2225 *pshift = shift; 2226 *pmultiplier = div_frac(scaled64, tps32); 2227 } 2228 2229 #ifdef CONFIG_X86_64 2230 static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0); 2231 #endif 2232 2233 static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz); 2234 static unsigned long max_tsc_khz; 2235 2236 static u32 adjust_tsc_khz(u32 khz, s32 ppm) 2237 { 2238 u64 v = (u64)khz * (1000000 + ppm); 2239 do_div(v, 1000000); 2240 return v; 2241 } 2242 2243 static void kvm_vcpu_write_tsc_multiplier(struct kvm_vcpu *vcpu, u64 l1_multiplier); 2244 2245 static int set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale) 2246 { 2247 u64 ratio; 2248 2249 /* Guest TSC same frequency as host TSC? */ 2250 if (!scale) { 2251 kvm_vcpu_write_tsc_multiplier(vcpu, kvm_default_tsc_scaling_ratio); 2252 return 0; 2253 } 2254 2255 /* TSC scaling supported? */ 2256 if (!kvm_has_tsc_control) { 2257 if (user_tsc_khz > tsc_khz) { 2258 vcpu->arch.tsc_catchup = 1; 2259 vcpu->arch.tsc_always_catchup = 1; 2260 return 0; 2261 } else { 2262 pr_warn_ratelimited("user requested TSC rate below hardware speed\n"); 2263 return -1; 2264 } 2265 } 2266 2267 /* TSC scaling required - calculate ratio */ 2268 ratio = mul_u64_u32_div(1ULL << kvm_tsc_scaling_ratio_frac_bits, 2269 user_tsc_khz, tsc_khz); 2270 2271 if (ratio == 0 || ratio >= kvm_max_tsc_scaling_ratio) { 2272 pr_warn_ratelimited("Invalid TSC scaling ratio - virtual-tsc-khz=%u\n", 2273 user_tsc_khz); 2274 return -1; 2275 } 2276 2277 kvm_vcpu_write_tsc_multiplier(vcpu, ratio); 2278 return 0; 2279 } 2280 2281 static int kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz) 2282 { 2283 u32 thresh_lo, thresh_hi; 2284 int use_scaling = 0; 2285 2286 /* tsc_khz can be zero if TSC calibration fails */ 2287 if (user_tsc_khz == 0) { 2288 /* set tsc_scaling_ratio to a safe value */ 2289 kvm_vcpu_write_tsc_multiplier(vcpu, kvm_default_tsc_scaling_ratio); 2290 return -1; 2291 } 2292 2293 /* Compute a scale to convert nanoseconds in TSC cycles */ 2294 kvm_get_time_scale(user_tsc_khz * 1000LL, NSEC_PER_SEC, 2295 &vcpu->arch.virtual_tsc_shift, 2296 &vcpu->arch.virtual_tsc_mult); 2297 vcpu->arch.virtual_tsc_khz = user_tsc_khz; 2298 2299 /* 2300 * Compute the variation in TSC rate which is acceptable 2301 * within the range of tolerance and decide if the 2302 * rate being applied is within that bounds of the hardware 2303 * rate. If so, no scaling or compensation need be done. 2304 */ 2305 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm); 2306 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm); 2307 if (user_tsc_khz < thresh_lo || user_tsc_khz > thresh_hi) { 2308 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", user_tsc_khz, thresh_lo, thresh_hi); 2309 use_scaling = 1; 2310 } 2311 return set_tsc_khz(vcpu, user_tsc_khz, use_scaling); 2312 } 2313 2314 static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns) 2315 { 2316 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec, 2317 vcpu->arch.virtual_tsc_mult, 2318 vcpu->arch.virtual_tsc_shift); 2319 tsc += vcpu->arch.this_tsc_write; 2320 return tsc; 2321 } 2322 2323 static inline int gtod_is_based_on_tsc(int mode) 2324 { 2325 return mode == VDSO_CLOCKMODE_TSC || mode == VDSO_CLOCKMODE_HVCLOCK; 2326 } 2327 2328 static void kvm_track_tsc_matching(struct kvm_vcpu *vcpu) 2329 { 2330 #ifdef CONFIG_X86_64 2331 bool vcpus_matched; 2332 struct kvm_arch *ka = &vcpu->kvm->arch; 2333 struct pvclock_gtod_data *gtod = &pvclock_gtod_data; 2334 2335 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 == 2336 atomic_read(&vcpu->kvm->online_vcpus)); 2337 2338 /* 2339 * Once the masterclock is enabled, always perform request in 2340 * order to update it. 2341 * 2342 * In order to enable masterclock, the host clocksource must be TSC 2343 * and the vcpus need to have matched TSCs. When that happens, 2344 * perform request to enable masterclock. 2345 */ 2346 if (ka->use_master_clock || 2347 (gtod_is_based_on_tsc(gtod->clock.vclock_mode) && vcpus_matched)) 2348 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu); 2349 2350 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc, 2351 atomic_read(&vcpu->kvm->online_vcpus), 2352 ka->use_master_clock, gtod->clock.vclock_mode); 2353 #endif 2354 } 2355 2356 /* 2357 * Multiply tsc by a fixed point number represented by ratio. 2358 * 2359 * The most significant 64-N bits (mult) of ratio represent the 2360 * integral part of the fixed point number; the remaining N bits 2361 * (frac) represent the fractional part, ie. ratio represents a fixed 2362 * point number (mult + frac * 2^(-N)). 2363 * 2364 * N equals to kvm_tsc_scaling_ratio_frac_bits. 2365 */ 2366 static inline u64 __scale_tsc(u64 ratio, u64 tsc) 2367 { 2368 return mul_u64_u64_shr(tsc, ratio, kvm_tsc_scaling_ratio_frac_bits); 2369 } 2370 2371 u64 kvm_scale_tsc(struct kvm_vcpu *vcpu, u64 tsc, u64 ratio) 2372 { 2373 u64 _tsc = tsc; 2374 2375 if (ratio != kvm_default_tsc_scaling_ratio) 2376 _tsc = __scale_tsc(ratio, tsc); 2377 2378 return _tsc; 2379 } 2380 EXPORT_SYMBOL_GPL(kvm_scale_tsc); 2381 2382 static u64 kvm_compute_l1_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc) 2383 { 2384 u64 tsc; 2385 2386 tsc = kvm_scale_tsc(vcpu, rdtsc(), vcpu->arch.l1_tsc_scaling_ratio); 2387 2388 return target_tsc - tsc; 2389 } 2390 2391 u64 kvm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc) 2392 { 2393 return vcpu->arch.l1_tsc_offset + 2394 kvm_scale_tsc(vcpu, host_tsc, vcpu->arch.l1_tsc_scaling_ratio); 2395 } 2396 EXPORT_SYMBOL_GPL(kvm_read_l1_tsc); 2397 2398 u64 kvm_calc_nested_tsc_offset(u64 l1_offset, u64 l2_offset, u64 l2_multiplier) 2399 { 2400 u64 nested_offset; 2401 2402 if (l2_multiplier == kvm_default_tsc_scaling_ratio) 2403 nested_offset = l1_offset; 2404 else 2405 nested_offset = mul_s64_u64_shr((s64) l1_offset, l2_multiplier, 2406 kvm_tsc_scaling_ratio_frac_bits); 2407 2408 nested_offset += l2_offset; 2409 return nested_offset; 2410 } 2411 EXPORT_SYMBOL_GPL(kvm_calc_nested_tsc_offset); 2412 2413 u64 kvm_calc_nested_tsc_multiplier(u64 l1_multiplier, u64 l2_multiplier) 2414 { 2415 if (l2_multiplier != kvm_default_tsc_scaling_ratio) 2416 return mul_u64_u64_shr(l1_multiplier, l2_multiplier, 2417 kvm_tsc_scaling_ratio_frac_bits); 2418 2419 return l1_multiplier; 2420 } 2421 EXPORT_SYMBOL_GPL(kvm_calc_nested_tsc_multiplier); 2422 2423 static void kvm_vcpu_write_tsc_offset(struct kvm_vcpu *vcpu, u64 l1_offset) 2424 { 2425 trace_kvm_write_tsc_offset(vcpu->vcpu_id, 2426 vcpu->arch.l1_tsc_offset, 2427 l1_offset); 2428 2429 vcpu->arch.l1_tsc_offset = l1_offset; 2430 2431 /* 2432 * If we are here because L1 chose not to trap WRMSR to TSC then 2433 * according to the spec this should set L1's TSC (as opposed to 2434 * setting L1's offset for L2). 2435 */ 2436 if (is_guest_mode(vcpu)) 2437 vcpu->arch.tsc_offset = kvm_calc_nested_tsc_offset( 2438 l1_offset, 2439 static_call(kvm_x86_get_l2_tsc_offset)(vcpu), 2440 static_call(kvm_x86_get_l2_tsc_multiplier)(vcpu)); 2441 else 2442 vcpu->arch.tsc_offset = l1_offset; 2443 2444 static_call(kvm_x86_write_tsc_offset)(vcpu, vcpu->arch.tsc_offset); 2445 } 2446 2447 static void kvm_vcpu_write_tsc_multiplier(struct kvm_vcpu *vcpu, u64 l1_multiplier) 2448 { 2449 vcpu->arch.l1_tsc_scaling_ratio = l1_multiplier; 2450 2451 /* Userspace is changing the multiplier while L2 is active */ 2452 if (is_guest_mode(vcpu)) 2453 vcpu->arch.tsc_scaling_ratio = kvm_calc_nested_tsc_multiplier( 2454 l1_multiplier, 2455 static_call(kvm_x86_get_l2_tsc_multiplier)(vcpu)); 2456 else 2457 vcpu->arch.tsc_scaling_ratio = l1_multiplier; 2458 2459 if (kvm_has_tsc_control) 2460 static_call(kvm_x86_write_tsc_multiplier)( 2461 vcpu, vcpu->arch.tsc_scaling_ratio); 2462 } 2463 2464 static inline bool kvm_check_tsc_unstable(void) 2465 { 2466 #ifdef CONFIG_X86_64 2467 /* 2468 * TSC is marked unstable when we're running on Hyper-V, 2469 * 'TSC page' clocksource is good. 2470 */ 2471 if (pvclock_gtod_data.clock.vclock_mode == VDSO_CLOCKMODE_HVCLOCK) 2472 return false; 2473 #endif 2474 return check_tsc_unstable(); 2475 } 2476 2477 /* 2478 * Infers attempts to synchronize the guest's tsc from host writes. Sets the 2479 * offset for the vcpu and tracks the TSC matching generation that the vcpu 2480 * participates in. 2481 */ 2482 static void __kvm_synchronize_tsc(struct kvm_vcpu *vcpu, u64 offset, u64 tsc, 2483 u64 ns, bool matched) 2484 { 2485 struct kvm *kvm = vcpu->kvm; 2486 2487 lockdep_assert_held(&kvm->arch.tsc_write_lock); 2488 2489 /* 2490 * We also track th most recent recorded KHZ, write and time to 2491 * allow the matching interval to be extended at each write. 2492 */ 2493 kvm->arch.last_tsc_nsec = ns; 2494 kvm->arch.last_tsc_write = tsc; 2495 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz; 2496 kvm->arch.last_tsc_offset = offset; 2497 2498 vcpu->arch.last_guest_tsc = tsc; 2499 2500 kvm_vcpu_write_tsc_offset(vcpu, offset); 2501 2502 if (!matched) { 2503 /* 2504 * We split periods of matched TSC writes into generations. 2505 * For each generation, we track the original measured 2506 * nanosecond time, offset, and write, so if TSCs are in 2507 * sync, we can match exact offset, and if not, we can match 2508 * exact software computation in compute_guest_tsc() 2509 * 2510 * These values are tracked in kvm->arch.cur_xxx variables. 2511 */ 2512 kvm->arch.cur_tsc_generation++; 2513 kvm->arch.cur_tsc_nsec = ns; 2514 kvm->arch.cur_tsc_write = tsc; 2515 kvm->arch.cur_tsc_offset = offset; 2516 kvm->arch.nr_vcpus_matched_tsc = 0; 2517 } else if (vcpu->arch.this_tsc_generation != kvm->arch.cur_tsc_generation) { 2518 kvm->arch.nr_vcpus_matched_tsc++; 2519 } 2520 2521 /* Keep track of which generation this VCPU has synchronized to */ 2522 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation; 2523 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec; 2524 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write; 2525 2526 kvm_track_tsc_matching(vcpu); 2527 } 2528 2529 static void kvm_synchronize_tsc(struct kvm_vcpu *vcpu, u64 data) 2530 { 2531 struct kvm *kvm = vcpu->kvm; 2532 u64 offset, ns, elapsed; 2533 unsigned long flags; 2534 bool matched = false; 2535 bool synchronizing = false; 2536 2537 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags); 2538 offset = kvm_compute_l1_tsc_offset(vcpu, data); 2539 ns = get_kvmclock_base_ns(); 2540 elapsed = ns - kvm->arch.last_tsc_nsec; 2541 2542 if (vcpu->arch.virtual_tsc_khz) { 2543 if (data == 0) { 2544 /* 2545 * detection of vcpu initialization -- need to sync 2546 * with other vCPUs. This particularly helps to keep 2547 * kvm_clock stable after CPU hotplug 2548 */ 2549 synchronizing = true; 2550 } else { 2551 u64 tsc_exp = kvm->arch.last_tsc_write + 2552 nsec_to_cycles(vcpu, elapsed); 2553 u64 tsc_hz = vcpu->arch.virtual_tsc_khz * 1000LL; 2554 /* 2555 * Special case: TSC write with a small delta (1 second) 2556 * of virtual cycle time against real time is 2557 * interpreted as an attempt to synchronize the CPU. 2558 */ 2559 synchronizing = data < tsc_exp + tsc_hz && 2560 data + tsc_hz > tsc_exp; 2561 } 2562 } 2563 2564 /* 2565 * For a reliable TSC, we can match TSC offsets, and for an unstable 2566 * TSC, we add elapsed time in this computation. We could let the 2567 * compensation code attempt to catch up if we fall behind, but 2568 * it's better to try to match offsets from the beginning. 2569 */ 2570 if (synchronizing && 2571 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) { 2572 if (!kvm_check_tsc_unstable()) { 2573 offset = kvm->arch.cur_tsc_offset; 2574 } else { 2575 u64 delta = nsec_to_cycles(vcpu, elapsed); 2576 data += delta; 2577 offset = kvm_compute_l1_tsc_offset(vcpu, data); 2578 } 2579 matched = true; 2580 } 2581 2582 __kvm_synchronize_tsc(vcpu, offset, data, ns, matched); 2583 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags); 2584 } 2585 2586 static inline void adjust_tsc_offset_guest(struct kvm_vcpu *vcpu, 2587 s64 adjustment) 2588 { 2589 u64 tsc_offset = vcpu->arch.l1_tsc_offset; 2590 kvm_vcpu_write_tsc_offset(vcpu, tsc_offset + adjustment); 2591 } 2592 2593 static inline void adjust_tsc_offset_host(struct kvm_vcpu *vcpu, s64 adjustment) 2594 { 2595 if (vcpu->arch.l1_tsc_scaling_ratio != kvm_default_tsc_scaling_ratio) 2596 WARN_ON(adjustment < 0); 2597 adjustment = kvm_scale_tsc(vcpu, (u64) adjustment, 2598 vcpu->arch.l1_tsc_scaling_ratio); 2599 adjust_tsc_offset_guest(vcpu, adjustment); 2600 } 2601 2602 #ifdef CONFIG_X86_64 2603 2604 static u64 read_tsc(void) 2605 { 2606 u64 ret = (u64)rdtsc_ordered(); 2607 u64 last = pvclock_gtod_data.clock.cycle_last; 2608 2609 if (likely(ret >= last)) 2610 return ret; 2611 2612 /* 2613 * GCC likes to generate cmov here, but this branch is extremely 2614 * predictable (it's just a function of time and the likely is 2615 * very likely) and there's a data dependence, so force GCC 2616 * to generate a branch instead. I don't barrier() because 2617 * we don't actually need a barrier, and if this function 2618 * ever gets inlined it will generate worse code. 2619 */ 2620 asm volatile (""); 2621 return last; 2622 } 2623 2624 static inline u64 vgettsc(struct pvclock_clock *clock, u64 *tsc_timestamp, 2625 int *mode) 2626 { 2627 long v; 2628 u64 tsc_pg_val; 2629 2630 switch (clock->vclock_mode) { 2631 case VDSO_CLOCKMODE_HVCLOCK: 2632 tsc_pg_val = hv_read_tsc_page_tsc(hv_get_tsc_page(), 2633 tsc_timestamp); 2634 if (tsc_pg_val != U64_MAX) { 2635 /* TSC page valid */ 2636 *mode = VDSO_CLOCKMODE_HVCLOCK; 2637 v = (tsc_pg_val - clock->cycle_last) & 2638 clock->mask; 2639 } else { 2640 /* TSC page invalid */ 2641 *mode = VDSO_CLOCKMODE_NONE; 2642 } 2643 break; 2644 case VDSO_CLOCKMODE_TSC: 2645 *mode = VDSO_CLOCKMODE_TSC; 2646 *tsc_timestamp = read_tsc(); 2647 v = (*tsc_timestamp - clock->cycle_last) & 2648 clock->mask; 2649 break; 2650 default: 2651 *mode = VDSO_CLOCKMODE_NONE; 2652 } 2653 2654 if (*mode == VDSO_CLOCKMODE_NONE) 2655 *tsc_timestamp = v = 0; 2656 2657 return v * clock->mult; 2658 } 2659 2660 static int do_monotonic_raw(s64 *t, u64 *tsc_timestamp) 2661 { 2662 struct pvclock_gtod_data *gtod = &pvclock_gtod_data; 2663 unsigned long seq; 2664 int mode; 2665 u64 ns; 2666 2667 do { 2668 seq = read_seqcount_begin(>od->seq); 2669 ns = gtod->raw_clock.base_cycles; 2670 ns += vgettsc(>od->raw_clock, tsc_timestamp, &mode); 2671 ns >>= gtod->raw_clock.shift; 2672 ns += ktime_to_ns(ktime_add(gtod->raw_clock.offset, gtod->offs_boot)); 2673 } while (unlikely(read_seqcount_retry(>od->seq, seq))); 2674 *t = ns; 2675 2676 return mode; 2677 } 2678 2679 static int do_realtime(struct timespec64 *ts, u64 *tsc_timestamp) 2680 { 2681 struct pvclock_gtod_data *gtod = &pvclock_gtod_data; 2682 unsigned long seq; 2683 int mode; 2684 u64 ns; 2685 2686 do { 2687 seq = read_seqcount_begin(>od->seq); 2688 ts->tv_sec = gtod->wall_time_sec; 2689 ns = gtod->clock.base_cycles; 2690 ns += vgettsc(>od->clock, tsc_timestamp, &mode); 2691 ns >>= gtod->clock.shift; 2692 } while (unlikely(read_seqcount_retry(>od->seq, seq))); 2693 2694 ts->tv_sec += __iter_div_u64_rem(ns, NSEC_PER_SEC, &ns); 2695 ts->tv_nsec = ns; 2696 2697 return mode; 2698 } 2699 2700 /* returns true if host is using TSC based clocksource */ 2701 static bool kvm_get_time_and_clockread(s64 *kernel_ns, u64 *tsc_timestamp) 2702 { 2703 /* checked again under seqlock below */ 2704 if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode)) 2705 return false; 2706 2707 return gtod_is_based_on_tsc(do_monotonic_raw(kernel_ns, 2708 tsc_timestamp)); 2709 } 2710 2711 /* returns true if host is using TSC based clocksource */ 2712 static bool kvm_get_walltime_and_clockread(struct timespec64 *ts, 2713 u64 *tsc_timestamp) 2714 { 2715 /* checked again under seqlock below */ 2716 if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode)) 2717 return false; 2718 2719 return gtod_is_based_on_tsc(do_realtime(ts, tsc_timestamp)); 2720 } 2721 #endif 2722 2723 /* 2724 * 2725 * Assuming a stable TSC across physical CPUS, and a stable TSC 2726 * across virtual CPUs, the following condition is possible. 2727 * Each numbered line represents an event visible to both 2728 * CPUs at the next numbered event. 2729 * 2730 * "timespecX" represents host monotonic time. "tscX" represents 2731 * RDTSC value. 2732 * 2733 * VCPU0 on CPU0 | VCPU1 on CPU1 2734 * 2735 * 1. read timespec0,tsc0 2736 * 2. | timespec1 = timespec0 + N 2737 * | tsc1 = tsc0 + M 2738 * 3. transition to guest | transition to guest 2739 * 4. ret0 = timespec0 + (rdtsc - tsc0) | 2740 * 5. | ret1 = timespec1 + (rdtsc - tsc1) 2741 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M)) 2742 * 2743 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity: 2744 * 2745 * - ret0 < ret1 2746 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M)) 2747 * ... 2748 * - 0 < N - M => M < N 2749 * 2750 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not 2751 * always the case (the difference between two distinct xtime instances 2752 * might be smaller then the difference between corresponding TSC reads, 2753 * when updating guest vcpus pvclock areas). 2754 * 2755 * To avoid that problem, do not allow visibility of distinct 2756 * system_timestamp/tsc_timestamp values simultaneously: use a master 2757 * copy of host monotonic time values. Update that master copy 2758 * in lockstep. 2759 * 2760 * Rely on synchronization of host TSCs and guest TSCs for monotonicity. 2761 * 2762 */ 2763 2764 static void pvclock_update_vm_gtod_copy(struct kvm *kvm) 2765 { 2766 #ifdef CONFIG_X86_64 2767 struct kvm_arch *ka = &kvm->arch; 2768 int vclock_mode; 2769 bool host_tsc_clocksource, vcpus_matched; 2770 2771 lockdep_assert_held(&kvm->arch.tsc_write_lock); 2772 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 == 2773 atomic_read(&kvm->online_vcpus)); 2774 2775 /* 2776 * If the host uses TSC clock, then passthrough TSC as stable 2777 * to the guest. 2778 */ 2779 host_tsc_clocksource = kvm_get_time_and_clockread( 2780 &ka->master_kernel_ns, 2781 &ka->master_cycle_now); 2782 2783 ka->use_master_clock = host_tsc_clocksource && vcpus_matched 2784 && !ka->backwards_tsc_observed 2785 && !ka->boot_vcpu_runs_old_kvmclock; 2786 2787 if (ka->use_master_clock) 2788 atomic_set(&kvm_guest_has_master_clock, 1); 2789 2790 vclock_mode = pvclock_gtod_data.clock.vclock_mode; 2791 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode, 2792 vcpus_matched); 2793 #endif 2794 } 2795 2796 static void kvm_make_mclock_inprogress_request(struct kvm *kvm) 2797 { 2798 kvm_make_all_cpus_request(kvm, KVM_REQ_MCLOCK_INPROGRESS); 2799 } 2800 2801 static void __kvm_start_pvclock_update(struct kvm *kvm) 2802 { 2803 raw_spin_lock_irq(&kvm->arch.tsc_write_lock); 2804 write_seqcount_begin(&kvm->arch.pvclock_sc); 2805 } 2806 2807 static void kvm_start_pvclock_update(struct kvm *kvm) 2808 { 2809 kvm_make_mclock_inprogress_request(kvm); 2810 2811 /* no guest entries from this point */ 2812 __kvm_start_pvclock_update(kvm); 2813 } 2814 2815 static void kvm_end_pvclock_update(struct kvm *kvm) 2816 { 2817 struct kvm_arch *ka = &kvm->arch; 2818 struct kvm_vcpu *vcpu; 2819 int i; 2820 2821 write_seqcount_end(&ka->pvclock_sc); 2822 raw_spin_unlock_irq(&ka->tsc_write_lock); 2823 kvm_for_each_vcpu(i, vcpu, kvm) 2824 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 2825 2826 /* guest entries allowed */ 2827 kvm_for_each_vcpu(i, vcpu, kvm) 2828 kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu); 2829 } 2830 2831 static void kvm_update_masterclock(struct kvm *kvm) 2832 { 2833 kvm_hv_invalidate_tsc_page(kvm); 2834 kvm_start_pvclock_update(kvm); 2835 pvclock_update_vm_gtod_copy(kvm); 2836 kvm_end_pvclock_update(kvm); 2837 } 2838 2839 /* Called within read_seqcount_begin/retry for kvm->pvclock_sc. */ 2840 static void __get_kvmclock(struct kvm *kvm, struct kvm_clock_data *data) 2841 { 2842 struct kvm_arch *ka = &kvm->arch; 2843 struct pvclock_vcpu_time_info hv_clock; 2844 2845 /* both __this_cpu_read() and rdtsc() should be on the same cpu */ 2846 get_cpu(); 2847 2848 data->flags = 0; 2849 if (ka->use_master_clock && __this_cpu_read(cpu_tsc_khz)) { 2850 #ifdef CONFIG_X86_64 2851 struct timespec64 ts; 2852 2853 if (kvm_get_walltime_and_clockread(&ts, &data->host_tsc)) { 2854 data->realtime = ts.tv_nsec + NSEC_PER_SEC * ts.tv_sec; 2855 data->flags |= KVM_CLOCK_REALTIME | KVM_CLOCK_HOST_TSC; 2856 } else 2857 #endif 2858 data->host_tsc = rdtsc(); 2859 2860 data->flags |= KVM_CLOCK_TSC_STABLE; 2861 hv_clock.tsc_timestamp = ka->master_cycle_now; 2862 hv_clock.system_time = ka->master_kernel_ns + ka->kvmclock_offset; 2863 kvm_get_time_scale(NSEC_PER_SEC, __this_cpu_read(cpu_tsc_khz) * 1000LL, 2864 &hv_clock.tsc_shift, 2865 &hv_clock.tsc_to_system_mul); 2866 data->clock = __pvclock_read_cycles(&hv_clock, data->host_tsc); 2867 } else { 2868 data->clock = get_kvmclock_base_ns() + ka->kvmclock_offset; 2869 } 2870 2871 put_cpu(); 2872 } 2873 2874 static void get_kvmclock(struct kvm *kvm, struct kvm_clock_data *data) 2875 { 2876 struct kvm_arch *ka = &kvm->arch; 2877 unsigned seq; 2878 2879 do { 2880 seq = read_seqcount_begin(&ka->pvclock_sc); 2881 __get_kvmclock(kvm, data); 2882 } while (read_seqcount_retry(&ka->pvclock_sc, seq)); 2883 } 2884 2885 u64 get_kvmclock_ns(struct kvm *kvm) 2886 { 2887 struct kvm_clock_data data; 2888 2889 get_kvmclock(kvm, &data); 2890 return data.clock; 2891 } 2892 2893 static void kvm_setup_pvclock_page(struct kvm_vcpu *v, 2894 struct gfn_to_hva_cache *cache, 2895 unsigned int offset) 2896 { 2897 struct kvm_vcpu_arch *vcpu = &v->arch; 2898 struct pvclock_vcpu_time_info guest_hv_clock; 2899 2900 if (unlikely(kvm_read_guest_offset_cached(v->kvm, cache, 2901 &guest_hv_clock, offset, sizeof(guest_hv_clock)))) 2902 return; 2903 2904 /* This VCPU is paused, but it's legal for a guest to read another 2905 * VCPU's kvmclock, so we really have to follow the specification where 2906 * it says that version is odd if data is being modified, and even after 2907 * it is consistent. 2908 * 2909 * Version field updates must be kept separate. This is because 2910 * kvm_write_guest_cached might use a "rep movs" instruction, and 2911 * writes within a string instruction are weakly ordered. So there 2912 * are three writes overall. 2913 * 2914 * As a small optimization, only write the version field in the first 2915 * and third write. The vcpu->pv_time cache is still valid, because the 2916 * version field is the first in the struct. 2917 */ 2918 BUILD_BUG_ON(offsetof(struct pvclock_vcpu_time_info, version) != 0); 2919 2920 if (guest_hv_clock.version & 1) 2921 ++guest_hv_clock.version; /* first time write, random junk */ 2922 2923 vcpu->hv_clock.version = guest_hv_clock.version + 1; 2924 kvm_write_guest_offset_cached(v->kvm, cache, 2925 &vcpu->hv_clock, offset, 2926 sizeof(vcpu->hv_clock.version)); 2927 2928 smp_wmb(); 2929 2930 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */ 2931 vcpu->hv_clock.flags |= (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED); 2932 2933 if (vcpu->pvclock_set_guest_stopped_request) { 2934 vcpu->hv_clock.flags |= PVCLOCK_GUEST_STOPPED; 2935 vcpu->pvclock_set_guest_stopped_request = false; 2936 } 2937 2938 trace_kvm_pvclock_update(v->vcpu_id, &vcpu->hv_clock); 2939 2940 kvm_write_guest_offset_cached(v->kvm, cache, 2941 &vcpu->hv_clock, offset, 2942 sizeof(vcpu->hv_clock)); 2943 2944 smp_wmb(); 2945 2946 vcpu->hv_clock.version++; 2947 kvm_write_guest_offset_cached(v->kvm, cache, 2948 &vcpu->hv_clock, offset, 2949 sizeof(vcpu->hv_clock.version)); 2950 } 2951 2952 static int kvm_guest_time_update(struct kvm_vcpu *v) 2953 { 2954 unsigned long flags, tgt_tsc_khz; 2955 unsigned seq; 2956 struct kvm_vcpu_arch *vcpu = &v->arch; 2957 struct kvm_arch *ka = &v->kvm->arch; 2958 s64 kernel_ns; 2959 u64 tsc_timestamp, host_tsc; 2960 u8 pvclock_flags; 2961 bool use_master_clock; 2962 2963 kernel_ns = 0; 2964 host_tsc = 0; 2965 2966 /* 2967 * If the host uses TSC clock, then passthrough TSC as stable 2968 * to the guest. 2969 */ 2970 do { 2971 seq = read_seqcount_begin(&ka->pvclock_sc); 2972 use_master_clock = ka->use_master_clock; 2973 if (use_master_clock) { 2974 host_tsc = ka->master_cycle_now; 2975 kernel_ns = ka->master_kernel_ns; 2976 } 2977 } while (read_seqcount_retry(&ka->pvclock_sc, seq)); 2978 2979 /* Keep irq disabled to prevent changes to the clock */ 2980 local_irq_save(flags); 2981 tgt_tsc_khz = __this_cpu_read(cpu_tsc_khz); 2982 if (unlikely(tgt_tsc_khz == 0)) { 2983 local_irq_restore(flags); 2984 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v); 2985 return 1; 2986 } 2987 if (!use_master_clock) { 2988 host_tsc = rdtsc(); 2989 kernel_ns = get_kvmclock_base_ns(); 2990 } 2991 2992 tsc_timestamp = kvm_read_l1_tsc(v, host_tsc); 2993 2994 /* 2995 * We may have to catch up the TSC to match elapsed wall clock 2996 * time for two reasons, even if kvmclock is used. 2997 * 1) CPU could have been running below the maximum TSC rate 2998 * 2) Broken TSC compensation resets the base at each VCPU 2999 * entry to avoid unknown leaps of TSC even when running 3000 * again on the same CPU. This may cause apparent elapsed 3001 * time to disappear, and the guest to stand still or run 3002 * very slowly. 3003 */ 3004 if (vcpu->tsc_catchup) { 3005 u64 tsc = compute_guest_tsc(v, kernel_ns); 3006 if (tsc > tsc_timestamp) { 3007 adjust_tsc_offset_guest(v, tsc - tsc_timestamp); 3008 tsc_timestamp = tsc; 3009 } 3010 } 3011 3012 local_irq_restore(flags); 3013 3014 /* With all the info we got, fill in the values */ 3015 3016 if (kvm_has_tsc_control) 3017 tgt_tsc_khz = kvm_scale_tsc(v, tgt_tsc_khz, 3018 v->arch.l1_tsc_scaling_ratio); 3019 3020 if (unlikely(vcpu->hw_tsc_khz != tgt_tsc_khz)) { 3021 kvm_get_time_scale(NSEC_PER_SEC, tgt_tsc_khz * 1000LL, 3022 &vcpu->hv_clock.tsc_shift, 3023 &vcpu->hv_clock.tsc_to_system_mul); 3024 vcpu->hw_tsc_khz = tgt_tsc_khz; 3025 } 3026 3027 vcpu->hv_clock.tsc_timestamp = tsc_timestamp; 3028 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset; 3029 vcpu->last_guest_tsc = tsc_timestamp; 3030 3031 /* If the host uses TSC clocksource, then it is stable */ 3032 pvclock_flags = 0; 3033 if (use_master_clock) 3034 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT; 3035 3036 vcpu->hv_clock.flags = pvclock_flags; 3037 3038 if (vcpu->pv_time_enabled) 3039 kvm_setup_pvclock_page(v, &vcpu->pv_time, 0); 3040 if (vcpu->xen.vcpu_info_set) 3041 kvm_setup_pvclock_page(v, &vcpu->xen.vcpu_info_cache, 3042 offsetof(struct compat_vcpu_info, time)); 3043 if (vcpu->xen.vcpu_time_info_set) 3044 kvm_setup_pvclock_page(v, &vcpu->xen.vcpu_time_info_cache, 0); 3045 if (!v->vcpu_idx) 3046 kvm_hv_setup_tsc_page(v->kvm, &vcpu->hv_clock); 3047 return 0; 3048 } 3049 3050 /* 3051 * kvmclock updates which are isolated to a given vcpu, such as 3052 * vcpu->cpu migration, should not allow system_timestamp from 3053 * the rest of the vcpus to remain static. Otherwise ntp frequency 3054 * correction applies to one vcpu's system_timestamp but not 3055 * the others. 3056 * 3057 * So in those cases, request a kvmclock update for all vcpus. 3058 * We need to rate-limit these requests though, as they can 3059 * considerably slow guests that have a large number of vcpus. 3060 * The time for a remote vcpu to update its kvmclock is bound 3061 * by the delay we use to rate-limit the updates. 3062 */ 3063 3064 #define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100) 3065 3066 static void kvmclock_update_fn(struct work_struct *work) 3067 { 3068 int i; 3069 struct delayed_work *dwork = to_delayed_work(work); 3070 struct kvm_arch *ka = container_of(dwork, struct kvm_arch, 3071 kvmclock_update_work); 3072 struct kvm *kvm = container_of(ka, struct kvm, arch); 3073 struct kvm_vcpu *vcpu; 3074 3075 kvm_for_each_vcpu(i, vcpu, kvm) { 3076 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 3077 kvm_vcpu_kick(vcpu); 3078 } 3079 } 3080 3081 static void kvm_gen_kvmclock_update(struct kvm_vcpu *v) 3082 { 3083 struct kvm *kvm = v->kvm; 3084 3085 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v); 3086 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 3087 KVMCLOCK_UPDATE_DELAY); 3088 } 3089 3090 #define KVMCLOCK_SYNC_PERIOD (300 * HZ) 3091 3092 static void kvmclock_sync_fn(struct work_struct *work) 3093 { 3094 struct delayed_work *dwork = to_delayed_work(work); 3095 struct kvm_arch *ka = container_of(dwork, struct kvm_arch, 3096 kvmclock_sync_work); 3097 struct kvm *kvm = container_of(ka, struct kvm, arch); 3098 3099 if (!kvmclock_periodic_sync) 3100 return; 3101 3102 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0); 3103 schedule_delayed_work(&kvm->arch.kvmclock_sync_work, 3104 KVMCLOCK_SYNC_PERIOD); 3105 } 3106 3107 /* 3108 * On AMD, HWCR[McStatusWrEn] controls whether setting MCi_STATUS results in #GP. 3109 */ 3110 static bool can_set_mci_status(struct kvm_vcpu *vcpu) 3111 { 3112 /* McStatusWrEn enabled? */ 3113 if (guest_cpuid_is_amd_or_hygon(vcpu)) 3114 return !!(vcpu->arch.msr_hwcr & BIT_ULL(18)); 3115 3116 return false; 3117 } 3118 3119 static int set_msr_mce(struct kvm_vcpu *vcpu, struct msr_data *msr_info) 3120 { 3121 u64 mcg_cap = vcpu->arch.mcg_cap; 3122 unsigned bank_num = mcg_cap & 0xff; 3123 u32 msr = msr_info->index; 3124 u64 data = msr_info->data; 3125 3126 switch (msr) { 3127 case MSR_IA32_MCG_STATUS: 3128 vcpu->arch.mcg_status = data; 3129 break; 3130 case MSR_IA32_MCG_CTL: 3131 if (!(mcg_cap & MCG_CTL_P) && 3132 (data || !msr_info->host_initiated)) 3133 return 1; 3134 if (data != 0 && data != ~(u64)0) 3135 return 1; 3136 vcpu->arch.mcg_ctl = data; 3137 break; 3138 default: 3139 if (msr >= MSR_IA32_MC0_CTL && 3140 msr < MSR_IA32_MCx_CTL(bank_num)) { 3141 u32 offset = array_index_nospec( 3142 msr - MSR_IA32_MC0_CTL, 3143 MSR_IA32_MCx_CTL(bank_num) - MSR_IA32_MC0_CTL); 3144 3145 /* only 0 or all 1s can be written to IA32_MCi_CTL 3146 * some Linux kernels though clear bit 10 in bank 4 to 3147 * workaround a BIOS/GART TBL issue on AMD K8s, ignore 3148 * this to avoid an uncatched #GP in the guest 3149 */ 3150 if ((offset & 0x3) == 0 && 3151 data != 0 && (data | (1 << 10)) != ~(u64)0) 3152 return -1; 3153 3154 /* MCi_STATUS */ 3155 if (!msr_info->host_initiated && 3156 (offset & 0x3) == 1 && data != 0) { 3157 if (!can_set_mci_status(vcpu)) 3158 return -1; 3159 } 3160 3161 vcpu->arch.mce_banks[offset] = data; 3162 break; 3163 } 3164 return 1; 3165 } 3166 return 0; 3167 } 3168 3169 static inline bool kvm_pv_async_pf_enabled(struct kvm_vcpu *vcpu) 3170 { 3171 u64 mask = KVM_ASYNC_PF_ENABLED | KVM_ASYNC_PF_DELIVERY_AS_INT; 3172 3173 return (vcpu->arch.apf.msr_en_val & mask) == mask; 3174 } 3175 3176 static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data) 3177 { 3178 gpa_t gpa = data & ~0x3f; 3179 3180 /* Bits 4:5 are reserved, Should be zero */ 3181 if (data & 0x30) 3182 return 1; 3183 3184 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_VMEXIT) && 3185 (data & KVM_ASYNC_PF_DELIVERY_AS_PF_VMEXIT)) 3186 return 1; 3187 3188 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_INT) && 3189 (data & KVM_ASYNC_PF_DELIVERY_AS_INT)) 3190 return 1; 3191 3192 if (!lapic_in_kernel(vcpu)) 3193 return data ? 1 : 0; 3194 3195 vcpu->arch.apf.msr_en_val = data; 3196 3197 if (!kvm_pv_async_pf_enabled(vcpu)) { 3198 kvm_clear_async_pf_completion_queue(vcpu); 3199 kvm_async_pf_hash_reset(vcpu); 3200 return 0; 3201 } 3202 3203 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa, 3204 sizeof(u64))) 3205 return 1; 3206 3207 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS); 3208 vcpu->arch.apf.delivery_as_pf_vmexit = data & KVM_ASYNC_PF_DELIVERY_AS_PF_VMEXIT; 3209 3210 kvm_async_pf_wakeup_all(vcpu); 3211 3212 return 0; 3213 } 3214 3215 static int kvm_pv_enable_async_pf_int(struct kvm_vcpu *vcpu, u64 data) 3216 { 3217 /* Bits 8-63 are reserved */ 3218 if (data >> 8) 3219 return 1; 3220 3221 if (!lapic_in_kernel(vcpu)) 3222 return 1; 3223 3224 vcpu->arch.apf.msr_int_val = data; 3225 3226 vcpu->arch.apf.vec = data & KVM_ASYNC_PF_VEC_MASK; 3227 3228 return 0; 3229 } 3230 3231 static void kvmclock_reset(struct kvm_vcpu *vcpu) 3232 { 3233 vcpu->arch.pv_time_enabled = false; 3234 vcpu->arch.time = 0; 3235 } 3236 3237 static void kvm_vcpu_flush_tlb_all(struct kvm_vcpu *vcpu) 3238 { 3239 ++vcpu->stat.tlb_flush; 3240 static_call(kvm_x86_tlb_flush_all)(vcpu); 3241 } 3242 3243 static void kvm_vcpu_flush_tlb_guest(struct kvm_vcpu *vcpu) 3244 { 3245 ++vcpu->stat.tlb_flush; 3246 3247 if (!tdp_enabled) { 3248 /* 3249 * A TLB flush on behalf of the guest is equivalent to 3250 * INVPCID(all), toggling CR4.PGE, etc., which requires 3251 * a forced sync of the shadow page tables. Ensure all the 3252 * roots are synced and the guest TLB in hardware is clean. 3253 */ 3254 kvm_mmu_sync_roots(vcpu); 3255 kvm_mmu_sync_prev_roots(vcpu); 3256 } 3257 3258 static_call(kvm_x86_tlb_flush_guest)(vcpu); 3259 } 3260 3261 3262 static inline void kvm_vcpu_flush_tlb_current(struct kvm_vcpu *vcpu) 3263 { 3264 ++vcpu->stat.tlb_flush; 3265 static_call(kvm_x86_tlb_flush_current)(vcpu); 3266 } 3267 3268 /* 3269 * Service "local" TLB flush requests, which are specific to the current MMU 3270 * context. In addition to the generic event handling in vcpu_enter_guest(), 3271 * TLB flushes that are targeted at an MMU context also need to be serviced 3272 * prior before nested VM-Enter/VM-Exit. 3273 */ 3274 void kvm_service_local_tlb_flush_requests(struct kvm_vcpu *vcpu) 3275 { 3276 if (kvm_check_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu)) 3277 kvm_vcpu_flush_tlb_current(vcpu); 3278 3279 if (kvm_check_request(KVM_REQ_TLB_FLUSH_GUEST, vcpu)) 3280 kvm_vcpu_flush_tlb_guest(vcpu); 3281 } 3282 EXPORT_SYMBOL_GPL(kvm_service_local_tlb_flush_requests); 3283 3284 static void record_steal_time(struct kvm_vcpu *vcpu) 3285 { 3286 struct gfn_to_hva_cache *ghc = &vcpu->arch.st.cache; 3287 struct kvm_steal_time __user *st; 3288 struct kvm_memslots *slots; 3289 u64 steal; 3290 u32 version; 3291 3292 if (kvm_xen_msr_enabled(vcpu->kvm)) { 3293 kvm_xen_runstate_set_running(vcpu); 3294 return; 3295 } 3296 3297 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED)) 3298 return; 3299 3300 if (WARN_ON_ONCE(current->mm != vcpu->kvm->mm)) 3301 return; 3302 3303 slots = kvm_memslots(vcpu->kvm); 3304 3305 if (unlikely(slots->generation != ghc->generation || 3306 kvm_is_error_hva(ghc->hva) || !ghc->memslot)) { 3307 gfn_t gfn = vcpu->arch.st.msr_val & KVM_STEAL_VALID_BITS; 3308 3309 /* We rely on the fact that it fits in a single page. */ 3310 BUILD_BUG_ON((sizeof(*st) - 1) & KVM_STEAL_VALID_BITS); 3311 3312 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, ghc, gfn, sizeof(*st)) || 3313 kvm_is_error_hva(ghc->hva) || !ghc->memslot) 3314 return; 3315 } 3316 3317 st = (struct kvm_steal_time __user *)ghc->hva; 3318 /* 3319 * Doing a TLB flush here, on the guest's behalf, can avoid 3320 * expensive IPIs. 3321 */ 3322 if (guest_pv_has(vcpu, KVM_FEATURE_PV_TLB_FLUSH)) { 3323 u8 st_preempted = 0; 3324 int err = -EFAULT; 3325 3326 if (!user_access_begin(st, sizeof(*st))) 3327 return; 3328 3329 asm volatile("1: xchgb %0, %2\n" 3330 "xor %1, %1\n" 3331 "2:\n" 3332 _ASM_EXTABLE_UA(1b, 2b) 3333 : "+q" (st_preempted), 3334 "+&r" (err), 3335 "+m" (st->preempted)); 3336 if (err) 3337 goto out; 3338 3339 user_access_end(); 3340 3341 vcpu->arch.st.preempted = 0; 3342 3343 trace_kvm_pv_tlb_flush(vcpu->vcpu_id, 3344 st_preempted & KVM_VCPU_FLUSH_TLB); 3345 if (st_preempted & KVM_VCPU_FLUSH_TLB) 3346 kvm_vcpu_flush_tlb_guest(vcpu); 3347 3348 if (!user_access_begin(st, sizeof(*st))) 3349 goto dirty; 3350 } else { 3351 if (!user_access_begin(st, sizeof(*st))) 3352 return; 3353 3354 unsafe_put_user(0, &st->preempted, out); 3355 vcpu->arch.st.preempted = 0; 3356 } 3357 3358 unsafe_get_user(version, &st->version, out); 3359 if (version & 1) 3360 version += 1; /* first time write, random junk */ 3361 3362 version += 1; 3363 unsafe_put_user(version, &st->version, out); 3364 3365 smp_wmb(); 3366 3367 unsafe_get_user(steal, &st->steal, out); 3368 steal += current->sched_info.run_delay - 3369 vcpu->arch.st.last_steal; 3370 vcpu->arch.st.last_steal = current->sched_info.run_delay; 3371 unsafe_put_user(steal, &st->steal, out); 3372 3373 version += 1; 3374 unsafe_put_user(version, &st->version, out); 3375 3376 out: 3377 user_access_end(); 3378 dirty: 3379 mark_page_dirty_in_slot(vcpu->kvm, ghc->memslot, gpa_to_gfn(ghc->gpa)); 3380 } 3381 3382 int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info) 3383 { 3384 bool pr = false; 3385 u32 msr = msr_info->index; 3386 u64 data = msr_info->data; 3387 3388 if (msr && msr == vcpu->kvm->arch.xen_hvm_config.msr) 3389 return kvm_xen_write_hypercall_page(vcpu, data); 3390 3391 switch (msr) { 3392 case MSR_AMD64_NB_CFG: 3393 case MSR_IA32_UCODE_WRITE: 3394 case MSR_VM_HSAVE_PA: 3395 case MSR_AMD64_PATCH_LOADER: 3396 case MSR_AMD64_BU_CFG2: 3397 case MSR_AMD64_DC_CFG: 3398 case MSR_F15H_EX_CFG: 3399 break; 3400 3401 case MSR_IA32_UCODE_REV: 3402 if (msr_info->host_initiated) 3403 vcpu->arch.microcode_version = data; 3404 break; 3405 case MSR_IA32_ARCH_CAPABILITIES: 3406 if (!msr_info->host_initiated) 3407 return 1; 3408 vcpu->arch.arch_capabilities = data; 3409 break; 3410 case MSR_IA32_PERF_CAPABILITIES: { 3411 struct kvm_msr_entry msr_ent = {.index = msr, .data = 0}; 3412 3413 if (!msr_info->host_initiated) 3414 return 1; 3415 if (guest_cpuid_has(vcpu, X86_FEATURE_PDCM) && kvm_get_msr_feature(&msr_ent)) 3416 return 1; 3417 if (data & ~msr_ent.data) 3418 return 1; 3419 3420 vcpu->arch.perf_capabilities = data; 3421 3422 return 0; 3423 } 3424 case MSR_EFER: 3425 return set_efer(vcpu, msr_info); 3426 case MSR_K7_HWCR: 3427 data &= ~(u64)0x40; /* ignore flush filter disable */ 3428 data &= ~(u64)0x100; /* ignore ignne emulation enable */ 3429 data &= ~(u64)0x8; /* ignore TLB cache disable */ 3430 3431 /* Handle McStatusWrEn */ 3432 if (data == BIT_ULL(18)) { 3433 vcpu->arch.msr_hwcr = data; 3434 } else if (data != 0) { 3435 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n", 3436 data); 3437 return 1; 3438 } 3439 break; 3440 case MSR_FAM10H_MMIO_CONF_BASE: 3441 if (data != 0) { 3442 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: " 3443 "0x%llx\n", data); 3444 return 1; 3445 } 3446 break; 3447 case 0x200 ... 0x2ff: 3448 return kvm_mtrr_set_msr(vcpu, msr, data); 3449 case MSR_IA32_APICBASE: 3450 return kvm_set_apic_base(vcpu, msr_info); 3451 case APIC_BASE_MSR ... APIC_BASE_MSR + 0xff: 3452 return kvm_x2apic_msr_write(vcpu, msr, data); 3453 case MSR_IA32_TSC_DEADLINE: 3454 kvm_set_lapic_tscdeadline_msr(vcpu, data); 3455 break; 3456 case MSR_IA32_TSC_ADJUST: 3457 if (guest_cpuid_has(vcpu, X86_FEATURE_TSC_ADJUST)) { 3458 if (!msr_info->host_initiated) { 3459 s64 adj = data - vcpu->arch.ia32_tsc_adjust_msr; 3460 adjust_tsc_offset_guest(vcpu, adj); 3461 /* Before back to guest, tsc_timestamp must be adjusted 3462 * as well, otherwise guest's percpu pvclock time could jump. 3463 */ 3464 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 3465 } 3466 vcpu->arch.ia32_tsc_adjust_msr = data; 3467 } 3468 break; 3469 case MSR_IA32_MISC_ENABLE: 3470 if (!kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_MISC_ENABLE_NO_MWAIT) && 3471 ((vcpu->arch.ia32_misc_enable_msr ^ data) & MSR_IA32_MISC_ENABLE_MWAIT)) { 3472 if (!guest_cpuid_has(vcpu, X86_FEATURE_XMM3)) 3473 return 1; 3474 vcpu->arch.ia32_misc_enable_msr = data; 3475 kvm_update_cpuid_runtime(vcpu); 3476 } else { 3477 vcpu->arch.ia32_misc_enable_msr = data; 3478 } 3479 break; 3480 case MSR_IA32_SMBASE: 3481 if (!msr_info->host_initiated) 3482 return 1; 3483 vcpu->arch.smbase = data; 3484 break; 3485 case MSR_IA32_POWER_CTL: 3486 vcpu->arch.msr_ia32_power_ctl = data; 3487 break; 3488 case MSR_IA32_TSC: 3489 if (msr_info->host_initiated) { 3490 kvm_synchronize_tsc(vcpu, data); 3491 } else { 3492 u64 adj = kvm_compute_l1_tsc_offset(vcpu, data) - vcpu->arch.l1_tsc_offset; 3493 adjust_tsc_offset_guest(vcpu, adj); 3494 vcpu->arch.ia32_tsc_adjust_msr += adj; 3495 } 3496 break; 3497 case MSR_IA32_XSS: 3498 if (!msr_info->host_initiated && 3499 !guest_cpuid_has(vcpu, X86_FEATURE_XSAVES)) 3500 return 1; 3501 /* 3502 * KVM supports exposing PT to the guest, but does not support 3503 * IA32_XSS[bit 8]. Guests have to use RDMSR/WRMSR rather than 3504 * XSAVES/XRSTORS to save/restore PT MSRs. 3505 */ 3506 if (data & ~supported_xss) 3507 return 1; 3508 vcpu->arch.ia32_xss = data; 3509 break; 3510 case MSR_SMI_COUNT: 3511 if (!msr_info->host_initiated) 3512 return 1; 3513 vcpu->arch.smi_count = data; 3514 break; 3515 case MSR_KVM_WALL_CLOCK_NEW: 3516 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE2)) 3517 return 1; 3518 3519 vcpu->kvm->arch.wall_clock = data; 3520 kvm_write_wall_clock(vcpu->kvm, data, 0); 3521 break; 3522 case MSR_KVM_WALL_CLOCK: 3523 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE)) 3524 return 1; 3525 3526 vcpu->kvm->arch.wall_clock = data; 3527 kvm_write_wall_clock(vcpu->kvm, data, 0); 3528 break; 3529 case MSR_KVM_SYSTEM_TIME_NEW: 3530 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE2)) 3531 return 1; 3532 3533 kvm_write_system_time(vcpu, data, false, msr_info->host_initiated); 3534 break; 3535 case MSR_KVM_SYSTEM_TIME: 3536 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE)) 3537 return 1; 3538 3539 kvm_write_system_time(vcpu, data, true, msr_info->host_initiated); 3540 break; 3541 case MSR_KVM_ASYNC_PF_EN: 3542 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF)) 3543 return 1; 3544 3545 if (kvm_pv_enable_async_pf(vcpu, data)) 3546 return 1; 3547 break; 3548 case MSR_KVM_ASYNC_PF_INT: 3549 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_INT)) 3550 return 1; 3551 3552 if (kvm_pv_enable_async_pf_int(vcpu, data)) 3553 return 1; 3554 break; 3555 case MSR_KVM_ASYNC_PF_ACK: 3556 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_INT)) 3557 return 1; 3558 if (data & 0x1) { 3559 vcpu->arch.apf.pageready_pending = false; 3560 kvm_check_async_pf_completion(vcpu); 3561 } 3562 break; 3563 case MSR_KVM_STEAL_TIME: 3564 if (!guest_pv_has(vcpu, KVM_FEATURE_STEAL_TIME)) 3565 return 1; 3566 3567 if (unlikely(!sched_info_on())) 3568 return 1; 3569 3570 if (data & KVM_STEAL_RESERVED_MASK) 3571 return 1; 3572 3573 vcpu->arch.st.msr_val = data; 3574 3575 if (!(data & KVM_MSR_ENABLED)) 3576 break; 3577 3578 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu); 3579 3580 break; 3581 case MSR_KVM_PV_EOI_EN: 3582 if (!guest_pv_has(vcpu, KVM_FEATURE_PV_EOI)) 3583 return 1; 3584 3585 if (kvm_lapic_set_pv_eoi(vcpu, data, sizeof(u8))) 3586 return 1; 3587 break; 3588 3589 case MSR_KVM_POLL_CONTROL: 3590 if (!guest_pv_has(vcpu, KVM_FEATURE_POLL_CONTROL)) 3591 return 1; 3592 3593 /* only enable bit supported */ 3594 if (data & (-1ULL << 1)) 3595 return 1; 3596 3597 vcpu->arch.msr_kvm_poll_control = data; 3598 break; 3599 3600 case MSR_IA32_MCG_CTL: 3601 case MSR_IA32_MCG_STATUS: 3602 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1: 3603 return set_msr_mce(vcpu, msr_info); 3604 3605 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3: 3606 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1: 3607 pr = true; 3608 fallthrough; 3609 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3: 3610 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1: 3611 if (kvm_pmu_is_valid_msr(vcpu, msr)) 3612 return kvm_pmu_set_msr(vcpu, msr_info); 3613 3614 if (pr || data != 0) 3615 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: " 3616 "0x%x data 0x%llx\n", msr, data); 3617 break; 3618 case MSR_K7_CLK_CTL: 3619 /* 3620 * Ignore all writes to this no longer documented MSR. 3621 * Writes are only relevant for old K7 processors, 3622 * all pre-dating SVM, but a recommended workaround from 3623 * AMD for these chips. It is possible to specify the 3624 * affected processor models on the command line, hence 3625 * the need to ignore the workaround. 3626 */ 3627 break; 3628 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15: 3629 case HV_X64_MSR_SYNDBG_CONTROL ... HV_X64_MSR_SYNDBG_PENDING_BUFFER: 3630 case HV_X64_MSR_SYNDBG_OPTIONS: 3631 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4: 3632 case HV_X64_MSR_CRASH_CTL: 3633 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT: 3634 case HV_X64_MSR_REENLIGHTENMENT_CONTROL: 3635 case HV_X64_MSR_TSC_EMULATION_CONTROL: 3636 case HV_X64_MSR_TSC_EMULATION_STATUS: 3637 return kvm_hv_set_msr_common(vcpu, msr, data, 3638 msr_info->host_initiated); 3639 case MSR_IA32_BBL_CR_CTL3: 3640 /* Drop writes to this legacy MSR -- see rdmsr 3641 * counterpart for further detail. 3642 */ 3643 if (report_ignored_msrs) 3644 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data 0x%llx\n", 3645 msr, data); 3646 break; 3647 case MSR_AMD64_OSVW_ID_LENGTH: 3648 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW)) 3649 return 1; 3650 vcpu->arch.osvw.length = data; 3651 break; 3652 case MSR_AMD64_OSVW_STATUS: 3653 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW)) 3654 return 1; 3655 vcpu->arch.osvw.status = data; 3656 break; 3657 case MSR_PLATFORM_INFO: 3658 if (!msr_info->host_initiated || 3659 (!(data & MSR_PLATFORM_INFO_CPUID_FAULT) && 3660 cpuid_fault_enabled(vcpu))) 3661 return 1; 3662 vcpu->arch.msr_platform_info = data; 3663 break; 3664 case MSR_MISC_FEATURES_ENABLES: 3665 if (data & ~MSR_MISC_FEATURES_ENABLES_CPUID_FAULT || 3666 (data & MSR_MISC_FEATURES_ENABLES_CPUID_FAULT && 3667 !supports_cpuid_fault(vcpu))) 3668 return 1; 3669 vcpu->arch.msr_misc_features_enables = data; 3670 break; 3671 default: 3672 if (kvm_pmu_is_valid_msr(vcpu, msr)) 3673 return kvm_pmu_set_msr(vcpu, msr_info); 3674 return KVM_MSR_RET_INVALID; 3675 } 3676 return 0; 3677 } 3678 EXPORT_SYMBOL_GPL(kvm_set_msr_common); 3679 3680 static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata, bool host) 3681 { 3682 u64 data; 3683 u64 mcg_cap = vcpu->arch.mcg_cap; 3684 unsigned bank_num = mcg_cap & 0xff; 3685 3686 switch (msr) { 3687 case MSR_IA32_P5_MC_ADDR: 3688 case MSR_IA32_P5_MC_TYPE: 3689 data = 0; 3690 break; 3691 case MSR_IA32_MCG_CAP: 3692 data = vcpu->arch.mcg_cap; 3693 break; 3694 case MSR_IA32_MCG_CTL: 3695 if (!(mcg_cap & MCG_CTL_P) && !host) 3696 return 1; 3697 data = vcpu->arch.mcg_ctl; 3698 break; 3699 case MSR_IA32_MCG_STATUS: 3700 data = vcpu->arch.mcg_status; 3701 break; 3702 default: 3703 if (msr >= MSR_IA32_MC0_CTL && 3704 msr < MSR_IA32_MCx_CTL(bank_num)) { 3705 u32 offset = array_index_nospec( 3706 msr - MSR_IA32_MC0_CTL, 3707 MSR_IA32_MCx_CTL(bank_num) - MSR_IA32_MC0_CTL); 3708 3709 data = vcpu->arch.mce_banks[offset]; 3710 break; 3711 } 3712 return 1; 3713 } 3714 *pdata = data; 3715 return 0; 3716 } 3717 3718 int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info) 3719 { 3720 switch (msr_info->index) { 3721 case MSR_IA32_PLATFORM_ID: 3722 case MSR_IA32_EBL_CR_POWERON: 3723 case MSR_IA32_LASTBRANCHFROMIP: 3724 case MSR_IA32_LASTBRANCHTOIP: 3725 case MSR_IA32_LASTINTFROMIP: 3726 case MSR_IA32_LASTINTTOIP: 3727 case MSR_AMD64_SYSCFG: 3728 case MSR_K8_TSEG_ADDR: 3729 case MSR_K8_TSEG_MASK: 3730 case MSR_VM_HSAVE_PA: 3731 case MSR_K8_INT_PENDING_MSG: 3732 case MSR_AMD64_NB_CFG: 3733 case MSR_FAM10H_MMIO_CONF_BASE: 3734 case MSR_AMD64_BU_CFG2: 3735 case MSR_IA32_PERF_CTL: 3736 case MSR_AMD64_DC_CFG: 3737 case MSR_F15H_EX_CFG: 3738 /* 3739 * Intel Sandy Bridge CPUs must support the RAPL (running average power 3740 * limit) MSRs. Just return 0, as we do not want to expose the host 3741 * data here. Do not conditionalize this on CPUID, as KVM does not do 3742 * so for existing CPU-specific MSRs. 3743 */ 3744 case MSR_RAPL_POWER_UNIT: 3745 case MSR_PP0_ENERGY_STATUS: /* Power plane 0 (core) */ 3746 case MSR_PP1_ENERGY_STATUS: /* Power plane 1 (graphics uncore) */ 3747 case MSR_PKG_ENERGY_STATUS: /* Total package */ 3748 case MSR_DRAM_ENERGY_STATUS: /* DRAM controller */ 3749 msr_info->data = 0; 3750 break; 3751 case MSR_F15H_PERF_CTL0 ... MSR_F15H_PERF_CTR5: 3752 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index)) 3753 return kvm_pmu_get_msr(vcpu, msr_info); 3754 if (!msr_info->host_initiated) 3755 return 1; 3756 msr_info->data = 0; 3757 break; 3758 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3: 3759 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3: 3760 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1: 3761 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1: 3762 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index)) 3763 return kvm_pmu_get_msr(vcpu, msr_info); 3764 msr_info->data = 0; 3765 break; 3766 case MSR_IA32_UCODE_REV: 3767 msr_info->data = vcpu->arch.microcode_version; 3768 break; 3769 case MSR_IA32_ARCH_CAPABILITIES: 3770 if (!msr_info->host_initiated && 3771 !guest_cpuid_has(vcpu, X86_FEATURE_ARCH_CAPABILITIES)) 3772 return 1; 3773 msr_info->data = vcpu->arch.arch_capabilities; 3774 break; 3775 case MSR_IA32_PERF_CAPABILITIES: 3776 if (!msr_info->host_initiated && 3777 !guest_cpuid_has(vcpu, X86_FEATURE_PDCM)) 3778 return 1; 3779 msr_info->data = vcpu->arch.perf_capabilities; 3780 break; 3781 case MSR_IA32_POWER_CTL: 3782 msr_info->data = vcpu->arch.msr_ia32_power_ctl; 3783 break; 3784 case MSR_IA32_TSC: { 3785 /* 3786 * Intel SDM states that MSR_IA32_TSC read adds the TSC offset 3787 * even when not intercepted. AMD manual doesn't explicitly 3788 * state this but appears to behave the same. 3789 * 3790 * On userspace reads and writes, however, we unconditionally 3791 * return L1's TSC value to ensure backwards-compatible 3792 * behavior for migration. 3793 */ 3794 u64 offset, ratio; 3795 3796 if (msr_info->host_initiated) { 3797 offset = vcpu->arch.l1_tsc_offset; 3798 ratio = vcpu->arch.l1_tsc_scaling_ratio; 3799 } else { 3800 offset = vcpu->arch.tsc_offset; 3801 ratio = vcpu->arch.tsc_scaling_ratio; 3802 } 3803 3804 msr_info->data = kvm_scale_tsc(vcpu, rdtsc(), ratio) + offset; 3805 break; 3806 } 3807 case MSR_MTRRcap: 3808 case 0x200 ... 0x2ff: 3809 return kvm_mtrr_get_msr(vcpu, msr_info->index, &msr_info->data); 3810 case 0xcd: /* fsb frequency */ 3811 msr_info->data = 3; 3812 break; 3813 /* 3814 * MSR_EBC_FREQUENCY_ID 3815 * Conservative value valid for even the basic CPU models. 3816 * Models 0,1: 000 in bits 23:21 indicating a bus speed of 3817 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz, 3818 * and 266MHz for model 3, or 4. Set Core Clock 3819 * Frequency to System Bus Frequency Ratio to 1 (bits 3820 * 31:24) even though these are only valid for CPU 3821 * models > 2, however guests may end up dividing or 3822 * multiplying by zero otherwise. 3823 */ 3824 case MSR_EBC_FREQUENCY_ID: 3825 msr_info->data = 1 << 24; 3826 break; 3827 case MSR_IA32_APICBASE: 3828 msr_info->data = kvm_get_apic_base(vcpu); 3829 break; 3830 case APIC_BASE_MSR ... APIC_BASE_MSR + 0xff: 3831 return kvm_x2apic_msr_read(vcpu, msr_info->index, &msr_info->data); 3832 case MSR_IA32_TSC_DEADLINE: 3833 msr_info->data = kvm_get_lapic_tscdeadline_msr(vcpu); 3834 break; 3835 case MSR_IA32_TSC_ADJUST: 3836 msr_info->data = (u64)vcpu->arch.ia32_tsc_adjust_msr; 3837 break; 3838 case MSR_IA32_MISC_ENABLE: 3839 msr_info->data = vcpu->arch.ia32_misc_enable_msr; 3840 break; 3841 case MSR_IA32_SMBASE: 3842 if (!msr_info->host_initiated) 3843 return 1; 3844 msr_info->data = vcpu->arch.smbase; 3845 break; 3846 case MSR_SMI_COUNT: 3847 msr_info->data = vcpu->arch.smi_count; 3848 break; 3849 case MSR_IA32_PERF_STATUS: 3850 /* TSC increment by tick */ 3851 msr_info->data = 1000ULL; 3852 /* CPU multiplier */ 3853 msr_info->data |= (((uint64_t)4ULL) << 40); 3854 break; 3855 case MSR_EFER: 3856 msr_info->data = vcpu->arch.efer; 3857 break; 3858 case MSR_KVM_WALL_CLOCK: 3859 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE)) 3860 return 1; 3861 3862 msr_info->data = vcpu->kvm->arch.wall_clock; 3863 break; 3864 case MSR_KVM_WALL_CLOCK_NEW: 3865 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE2)) 3866 return 1; 3867 3868 msr_info->data = vcpu->kvm->arch.wall_clock; 3869 break; 3870 case MSR_KVM_SYSTEM_TIME: 3871 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE)) 3872 return 1; 3873 3874 msr_info->data = vcpu->arch.time; 3875 break; 3876 case MSR_KVM_SYSTEM_TIME_NEW: 3877 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE2)) 3878 return 1; 3879 3880 msr_info->data = vcpu->arch.time; 3881 break; 3882 case MSR_KVM_ASYNC_PF_EN: 3883 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF)) 3884 return 1; 3885 3886 msr_info->data = vcpu->arch.apf.msr_en_val; 3887 break; 3888 case MSR_KVM_ASYNC_PF_INT: 3889 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_INT)) 3890 return 1; 3891 3892 msr_info->data = vcpu->arch.apf.msr_int_val; 3893 break; 3894 case MSR_KVM_ASYNC_PF_ACK: 3895 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_INT)) 3896 return 1; 3897 3898 msr_info->data = 0; 3899 break; 3900 case MSR_KVM_STEAL_TIME: 3901 if (!guest_pv_has(vcpu, KVM_FEATURE_STEAL_TIME)) 3902 return 1; 3903 3904 msr_info->data = vcpu->arch.st.msr_val; 3905 break; 3906 case MSR_KVM_PV_EOI_EN: 3907 if (!guest_pv_has(vcpu, KVM_FEATURE_PV_EOI)) 3908 return 1; 3909 3910 msr_info->data = vcpu->arch.pv_eoi.msr_val; 3911 break; 3912 case MSR_KVM_POLL_CONTROL: 3913 if (!guest_pv_has(vcpu, KVM_FEATURE_POLL_CONTROL)) 3914 return 1; 3915 3916 msr_info->data = vcpu->arch.msr_kvm_poll_control; 3917 break; 3918 case MSR_IA32_P5_MC_ADDR: 3919 case MSR_IA32_P5_MC_TYPE: 3920 case MSR_IA32_MCG_CAP: 3921 case MSR_IA32_MCG_CTL: 3922 case MSR_IA32_MCG_STATUS: 3923 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1: 3924 return get_msr_mce(vcpu, msr_info->index, &msr_info->data, 3925 msr_info->host_initiated); 3926 case MSR_IA32_XSS: 3927 if (!msr_info->host_initiated && 3928 !guest_cpuid_has(vcpu, X86_FEATURE_XSAVES)) 3929 return 1; 3930 msr_info->data = vcpu->arch.ia32_xss; 3931 break; 3932 case MSR_K7_CLK_CTL: 3933 /* 3934 * Provide expected ramp-up count for K7. All other 3935 * are set to zero, indicating minimum divisors for 3936 * every field. 3937 * 3938 * This prevents guest kernels on AMD host with CPU 3939 * type 6, model 8 and higher from exploding due to 3940 * the rdmsr failing. 3941 */ 3942 msr_info->data = 0x20000000; 3943 break; 3944 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15: 3945 case HV_X64_MSR_SYNDBG_CONTROL ... HV_X64_MSR_SYNDBG_PENDING_BUFFER: 3946 case HV_X64_MSR_SYNDBG_OPTIONS: 3947 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4: 3948 case HV_X64_MSR_CRASH_CTL: 3949 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT: 3950 case HV_X64_MSR_REENLIGHTENMENT_CONTROL: 3951 case HV_X64_MSR_TSC_EMULATION_CONTROL: 3952 case HV_X64_MSR_TSC_EMULATION_STATUS: 3953 return kvm_hv_get_msr_common(vcpu, 3954 msr_info->index, &msr_info->data, 3955 msr_info->host_initiated); 3956 case MSR_IA32_BBL_CR_CTL3: 3957 /* This legacy MSR exists but isn't fully documented in current 3958 * silicon. It is however accessed by winxp in very narrow 3959 * scenarios where it sets bit #19, itself documented as 3960 * a "reserved" bit. Best effort attempt to source coherent 3961 * read data here should the balance of the register be 3962 * interpreted by the guest: 3963 * 3964 * L2 cache control register 3: 64GB range, 256KB size, 3965 * enabled, latency 0x1, configured 3966 */ 3967 msr_info->data = 0xbe702111; 3968 break; 3969 case MSR_AMD64_OSVW_ID_LENGTH: 3970 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW)) 3971 return 1; 3972 msr_info->data = vcpu->arch.osvw.length; 3973 break; 3974 case MSR_AMD64_OSVW_STATUS: 3975 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW)) 3976 return 1; 3977 msr_info->data = vcpu->arch.osvw.status; 3978 break; 3979 case MSR_PLATFORM_INFO: 3980 if (!msr_info->host_initiated && 3981 !vcpu->kvm->arch.guest_can_read_msr_platform_info) 3982 return 1; 3983 msr_info->data = vcpu->arch.msr_platform_info; 3984 break; 3985 case MSR_MISC_FEATURES_ENABLES: 3986 msr_info->data = vcpu->arch.msr_misc_features_enables; 3987 break; 3988 case MSR_K7_HWCR: 3989 msr_info->data = vcpu->arch.msr_hwcr; 3990 break; 3991 default: 3992 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index)) 3993 return kvm_pmu_get_msr(vcpu, msr_info); 3994 return KVM_MSR_RET_INVALID; 3995 } 3996 return 0; 3997 } 3998 EXPORT_SYMBOL_GPL(kvm_get_msr_common); 3999 4000 /* 4001 * Read or write a bunch of msrs. All parameters are kernel addresses. 4002 * 4003 * @return number of msrs set successfully. 4004 */ 4005 static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs, 4006 struct kvm_msr_entry *entries, 4007 int (*do_msr)(struct kvm_vcpu *vcpu, 4008 unsigned index, u64 *data)) 4009 { 4010 int i; 4011 4012 for (i = 0; i < msrs->nmsrs; ++i) 4013 if (do_msr(vcpu, entries[i].index, &entries[i].data)) 4014 break; 4015 4016 return i; 4017 } 4018 4019 /* 4020 * Read or write a bunch of msrs. Parameters are user addresses. 4021 * 4022 * @return number of msrs set successfully. 4023 */ 4024 static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs, 4025 int (*do_msr)(struct kvm_vcpu *vcpu, 4026 unsigned index, u64 *data), 4027 int writeback) 4028 { 4029 struct kvm_msrs msrs; 4030 struct kvm_msr_entry *entries; 4031 int r, n; 4032 unsigned size; 4033 4034 r = -EFAULT; 4035 if (copy_from_user(&msrs, user_msrs, sizeof(msrs))) 4036 goto out; 4037 4038 r = -E2BIG; 4039 if (msrs.nmsrs >= MAX_IO_MSRS) 4040 goto out; 4041 4042 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs; 4043 entries = memdup_user(user_msrs->entries, size); 4044 if (IS_ERR(entries)) { 4045 r = PTR_ERR(entries); 4046 goto out; 4047 } 4048 4049 r = n = __msr_io(vcpu, &msrs, entries, do_msr); 4050 if (r < 0) 4051 goto out_free; 4052 4053 r = -EFAULT; 4054 if (writeback && copy_to_user(user_msrs->entries, entries, size)) 4055 goto out_free; 4056 4057 r = n; 4058 4059 out_free: 4060 kfree(entries); 4061 out: 4062 return r; 4063 } 4064 4065 static inline bool kvm_can_mwait_in_guest(void) 4066 { 4067 return boot_cpu_has(X86_FEATURE_MWAIT) && 4068 !boot_cpu_has_bug(X86_BUG_MONITOR) && 4069 boot_cpu_has(X86_FEATURE_ARAT); 4070 } 4071 4072 static int kvm_ioctl_get_supported_hv_cpuid(struct kvm_vcpu *vcpu, 4073 struct kvm_cpuid2 __user *cpuid_arg) 4074 { 4075 struct kvm_cpuid2 cpuid; 4076 int r; 4077 4078 r = -EFAULT; 4079 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid))) 4080 return r; 4081 4082 r = kvm_get_hv_cpuid(vcpu, &cpuid, cpuid_arg->entries); 4083 if (r) 4084 return r; 4085 4086 r = -EFAULT; 4087 if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid))) 4088 return r; 4089 4090 return 0; 4091 } 4092 4093 int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext) 4094 { 4095 int r = 0; 4096 4097 switch (ext) { 4098 case KVM_CAP_IRQCHIP: 4099 case KVM_CAP_HLT: 4100 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL: 4101 case KVM_CAP_SET_TSS_ADDR: 4102 case KVM_CAP_EXT_CPUID: 4103 case KVM_CAP_EXT_EMUL_CPUID: 4104 case KVM_CAP_CLOCKSOURCE: 4105 case KVM_CAP_PIT: 4106 case KVM_CAP_NOP_IO_DELAY: 4107 case KVM_CAP_MP_STATE: 4108 case KVM_CAP_SYNC_MMU: 4109 case KVM_CAP_USER_NMI: 4110 case KVM_CAP_REINJECT_CONTROL: 4111 case KVM_CAP_IRQ_INJECT_STATUS: 4112 case KVM_CAP_IOEVENTFD: 4113 case KVM_CAP_IOEVENTFD_NO_LENGTH: 4114 case KVM_CAP_PIT2: 4115 case KVM_CAP_PIT_STATE2: 4116 case KVM_CAP_SET_IDENTITY_MAP_ADDR: 4117 case KVM_CAP_VCPU_EVENTS: 4118 case KVM_CAP_HYPERV: 4119 case KVM_CAP_HYPERV_VAPIC: 4120 case KVM_CAP_HYPERV_SPIN: 4121 case KVM_CAP_HYPERV_SYNIC: 4122 case KVM_CAP_HYPERV_SYNIC2: 4123 case KVM_CAP_HYPERV_VP_INDEX: 4124 case KVM_CAP_HYPERV_EVENTFD: 4125 case KVM_CAP_HYPERV_TLBFLUSH: 4126 case KVM_CAP_HYPERV_SEND_IPI: 4127 case KVM_CAP_HYPERV_CPUID: 4128 case KVM_CAP_HYPERV_ENFORCE_CPUID: 4129 case KVM_CAP_SYS_HYPERV_CPUID: 4130 case KVM_CAP_PCI_SEGMENT: 4131 case KVM_CAP_DEBUGREGS: 4132 case KVM_CAP_X86_ROBUST_SINGLESTEP: 4133 case KVM_CAP_XSAVE: 4134 case KVM_CAP_ASYNC_PF: 4135 case KVM_CAP_ASYNC_PF_INT: 4136 case KVM_CAP_GET_TSC_KHZ: 4137 case KVM_CAP_KVMCLOCK_CTRL: 4138 case KVM_CAP_READONLY_MEM: 4139 case KVM_CAP_HYPERV_TIME: 4140 case KVM_CAP_IOAPIC_POLARITY_IGNORED: 4141 case KVM_CAP_TSC_DEADLINE_TIMER: 4142 case KVM_CAP_DISABLE_QUIRKS: 4143 case KVM_CAP_SET_BOOT_CPU_ID: 4144 case KVM_CAP_SPLIT_IRQCHIP: 4145 case KVM_CAP_IMMEDIATE_EXIT: 4146 case KVM_CAP_PMU_EVENT_FILTER: 4147 case KVM_CAP_GET_MSR_FEATURES: 4148 case KVM_CAP_MSR_PLATFORM_INFO: 4149 case KVM_CAP_EXCEPTION_PAYLOAD: 4150 case KVM_CAP_SET_GUEST_DEBUG: 4151 case KVM_CAP_LAST_CPU: 4152 case KVM_CAP_X86_USER_SPACE_MSR: 4153 case KVM_CAP_X86_MSR_FILTER: 4154 case KVM_CAP_ENFORCE_PV_FEATURE_CPUID: 4155 #ifdef CONFIG_X86_SGX_KVM 4156 case KVM_CAP_SGX_ATTRIBUTE: 4157 #endif 4158 case KVM_CAP_VM_COPY_ENC_CONTEXT_FROM: 4159 case KVM_CAP_VM_MOVE_ENC_CONTEXT_FROM: 4160 case KVM_CAP_SREGS2: 4161 case KVM_CAP_EXIT_ON_EMULATION_FAILURE: 4162 case KVM_CAP_VCPU_ATTRIBUTES: 4163 r = 1; 4164 break; 4165 case KVM_CAP_EXIT_HYPERCALL: 4166 r = KVM_EXIT_HYPERCALL_VALID_MASK; 4167 break; 4168 case KVM_CAP_SET_GUEST_DEBUG2: 4169 return KVM_GUESTDBG_VALID_MASK; 4170 #ifdef CONFIG_KVM_XEN 4171 case KVM_CAP_XEN_HVM: 4172 r = KVM_XEN_HVM_CONFIG_HYPERCALL_MSR | 4173 KVM_XEN_HVM_CONFIG_INTERCEPT_HCALL | 4174 KVM_XEN_HVM_CONFIG_SHARED_INFO; 4175 if (sched_info_on()) 4176 r |= KVM_XEN_HVM_CONFIG_RUNSTATE; 4177 break; 4178 #endif 4179 case KVM_CAP_SYNC_REGS: 4180 r = KVM_SYNC_X86_VALID_FIELDS; 4181 break; 4182 case KVM_CAP_ADJUST_CLOCK: 4183 r = KVM_CLOCK_VALID_FLAGS; 4184 break; 4185 case KVM_CAP_X86_DISABLE_EXITS: 4186 r |= KVM_X86_DISABLE_EXITS_HLT | KVM_X86_DISABLE_EXITS_PAUSE | 4187 KVM_X86_DISABLE_EXITS_CSTATE; 4188 if(kvm_can_mwait_in_guest()) 4189 r |= KVM_X86_DISABLE_EXITS_MWAIT; 4190 break; 4191 case KVM_CAP_X86_SMM: 4192 /* SMBASE is usually relocated above 1M on modern chipsets, 4193 * and SMM handlers might indeed rely on 4G segment limits, 4194 * so do not report SMM to be available if real mode is 4195 * emulated via vm86 mode. Still, do not go to great lengths 4196 * to avoid userspace's usage of the feature, because it is a 4197 * fringe case that is not enabled except via specific settings 4198 * of the module parameters. 4199 */ 4200 r = static_call(kvm_x86_has_emulated_msr)(kvm, MSR_IA32_SMBASE); 4201 break; 4202 case KVM_CAP_VAPIC: 4203 r = !static_call(kvm_x86_cpu_has_accelerated_tpr)(); 4204 break; 4205 case KVM_CAP_NR_VCPUS: 4206 r = min_t(unsigned int, num_online_cpus(), KVM_MAX_VCPUS); 4207 break; 4208 case KVM_CAP_MAX_VCPUS: 4209 r = KVM_MAX_VCPUS; 4210 break; 4211 case KVM_CAP_MAX_VCPU_ID: 4212 r = KVM_MAX_VCPU_IDS; 4213 break; 4214 case KVM_CAP_PV_MMU: /* obsolete */ 4215 r = 0; 4216 break; 4217 case KVM_CAP_MCE: 4218 r = KVM_MAX_MCE_BANKS; 4219 break; 4220 case KVM_CAP_XCRS: 4221 r = boot_cpu_has(X86_FEATURE_XSAVE); 4222 break; 4223 case KVM_CAP_TSC_CONTROL: 4224 r = kvm_has_tsc_control; 4225 break; 4226 case KVM_CAP_X2APIC_API: 4227 r = KVM_X2APIC_API_VALID_FLAGS; 4228 break; 4229 case KVM_CAP_NESTED_STATE: 4230 r = kvm_x86_ops.nested_ops->get_state ? 4231 kvm_x86_ops.nested_ops->get_state(NULL, NULL, 0) : 0; 4232 break; 4233 case KVM_CAP_HYPERV_DIRECT_TLBFLUSH: 4234 r = kvm_x86_ops.enable_direct_tlbflush != NULL; 4235 break; 4236 case KVM_CAP_HYPERV_ENLIGHTENED_VMCS: 4237 r = kvm_x86_ops.nested_ops->enable_evmcs != NULL; 4238 break; 4239 case KVM_CAP_SMALLER_MAXPHYADDR: 4240 r = (int) allow_smaller_maxphyaddr; 4241 break; 4242 case KVM_CAP_STEAL_TIME: 4243 r = sched_info_on(); 4244 break; 4245 case KVM_CAP_X86_BUS_LOCK_EXIT: 4246 if (kvm_has_bus_lock_exit) 4247 r = KVM_BUS_LOCK_DETECTION_OFF | 4248 KVM_BUS_LOCK_DETECTION_EXIT; 4249 else 4250 r = 0; 4251 break; 4252 default: 4253 break; 4254 } 4255 return r; 4256 4257 } 4258 4259 long kvm_arch_dev_ioctl(struct file *filp, 4260 unsigned int ioctl, unsigned long arg) 4261 { 4262 void __user *argp = (void __user *)arg; 4263 long r; 4264 4265 switch (ioctl) { 4266 case KVM_GET_MSR_INDEX_LIST: { 4267 struct kvm_msr_list __user *user_msr_list = argp; 4268 struct kvm_msr_list msr_list; 4269 unsigned n; 4270 4271 r = -EFAULT; 4272 if (copy_from_user(&msr_list, user_msr_list, sizeof(msr_list))) 4273 goto out; 4274 n = msr_list.nmsrs; 4275 msr_list.nmsrs = num_msrs_to_save + num_emulated_msrs; 4276 if (copy_to_user(user_msr_list, &msr_list, sizeof(msr_list))) 4277 goto out; 4278 r = -E2BIG; 4279 if (n < msr_list.nmsrs) 4280 goto out; 4281 r = -EFAULT; 4282 if (copy_to_user(user_msr_list->indices, &msrs_to_save, 4283 num_msrs_to_save * sizeof(u32))) 4284 goto out; 4285 if (copy_to_user(user_msr_list->indices + num_msrs_to_save, 4286 &emulated_msrs, 4287 num_emulated_msrs * sizeof(u32))) 4288 goto out; 4289 r = 0; 4290 break; 4291 } 4292 case KVM_GET_SUPPORTED_CPUID: 4293 case KVM_GET_EMULATED_CPUID: { 4294 struct kvm_cpuid2 __user *cpuid_arg = argp; 4295 struct kvm_cpuid2 cpuid; 4296 4297 r = -EFAULT; 4298 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid))) 4299 goto out; 4300 4301 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries, 4302 ioctl); 4303 if (r) 4304 goto out; 4305 4306 r = -EFAULT; 4307 if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid))) 4308 goto out; 4309 r = 0; 4310 break; 4311 } 4312 case KVM_X86_GET_MCE_CAP_SUPPORTED: 4313 r = -EFAULT; 4314 if (copy_to_user(argp, &kvm_mce_cap_supported, 4315 sizeof(kvm_mce_cap_supported))) 4316 goto out; 4317 r = 0; 4318 break; 4319 case KVM_GET_MSR_FEATURE_INDEX_LIST: { 4320 struct kvm_msr_list __user *user_msr_list = argp; 4321 struct kvm_msr_list msr_list; 4322 unsigned int n; 4323 4324 r = -EFAULT; 4325 if (copy_from_user(&msr_list, user_msr_list, sizeof(msr_list))) 4326 goto out; 4327 n = msr_list.nmsrs; 4328 msr_list.nmsrs = num_msr_based_features; 4329 if (copy_to_user(user_msr_list, &msr_list, sizeof(msr_list))) 4330 goto out; 4331 r = -E2BIG; 4332 if (n < msr_list.nmsrs) 4333 goto out; 4334 r = -EFAULT; 4335 if (copy_to_user(user_msr_list->indices, &msr_based_features, 4336 num_msr_based_features * sizeof(u32))) 4337 goto out; 4338 r = 0; 4339 break; 4340 } 4341 case KVM_GET_MSRS: 4342 r = msr_io(NULL, argp, do_get_msr_feature, 1); 4343 break; 4344 case KVM_GET_SUPPORTED_HV_CPUID: 4345 r = kvm_ioctl_get_supported_hv_cpuid(NULL, argp); 4346 break; 4347 default: 4348 r = -EINVAL; 4349 break; 4350 } 4351 out: 4352 return r; 4353 } 4354 4355 static void wbinvd_ipi(void *garbage) 4356 { 4357 wbinvd(); 4358 } 4359 4360 static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu) 4361 { 4362 return kvm_arch_has_noncoherent_dma(vcpu->kvm); 4363 } 4364 4365 void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu) 4366 { 4367 /* Address WBINVD may be executed by guest */ 4368 if (need_emulate_wbinvd(vcpu)) { 4369 if (static_call(kvm_x86_has_wbinvd_exit)()) 4370 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask); 4371 else if (vcpu->cpu != -1 && vcpu->cpu != cpu) 4372 smp_call_function_single(vcpu->cpu, 4373 wbinvd_ipi, NULL, 1); 4374 } 4375 4376 static_call(kvm_x86_vcpu_load)(vcpu, cpu); 4377 4378 /* Save host pkru register if supported */ 4379 vcpu->arch.host_pkru = read_pkru(); 4380 4381 /* Apply any externally detected TSC adjustments (due to suspend) */ 4382 if (unlikely(vcpu->arch.tsc_offset_adjustment)) { 4383 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment); 4384 vcpu->arch.tsc_offset_adjustment = 0; 4385 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 4386 } 4387 4388 if (unlikely(vcpu->cpu != cpu) || kvm_check_tsc_unstable()) { 4389 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 : 4390 rdtsc() - vcpu->arch.last_host_tsc; 4391 if (tsc_delta < 0) 4392 mark_tsc_unstable("KVM discovered backwards TSC"); 4393 4394 if (kvm_check_tsc_unstable()) { 4395 u64 offset = kvm_compute_l1_tsc_offset(vcpu, 4396 vcpu->arch.last_guest_tsc); 4397 kvm_vcpu_write_tsc_offset(vcpu, offset); 4398 vcpu->arch.tsc_catchup = 1; 4399 } 4400 4401 if (kvm_lapic_hv_timer_in_use(vcpu)) 4402 kvm_lapic_restart_hv_timer(vcpu); 4403 4404 /* 4405 * On a host with synchronized TSC, there is no need to update 4406 * kvmclock on vcpu->cpu migration 4407 */ 4408 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1) 4409 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu); 4410 if (vcpu->cpu != cpu) 4411 kvm_make_request(KVM_REQ_MIGRATE_TIMER, vcpu); 4412 vcpu->cpu = cpu; 4413 } 4414 4415 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu); 4416 } 4417 4418 static void kvm_steal_time_set_preempted(struct kvm_vcpu *vcpu) 4419 { 4420 struct gfn_to_hva_cache *ghc = &vcpu->arch.st.cache; 4421 struct kvm_steal_time __user *st; 4422 struct kvm_memslots *slots; 4423 static const u8 preempted = KVM_VCPU_PREEMPTED; 4424 4425 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED)) 4426 return; 4427 4428 if (vcpu->arch.st.preempted) 4429 return; 4430 4431 /* This happens on process exit */ 4432 if (unlikely(current->mm != vcpu->kvm->mm)) 4433 return; 4434 4435 slots = kvm_memslots(vcpu->kvm); 4436 4437 if (unlikely(slots->generation != ghc->generation || 4438 kvm_is_error_hva(ghc->hva) || !ghc->memslot)) 4439 return; 4440 4441 st = (struct kvm_steal_time __user *)ghc->hva; 4442 BUILD_BUG_ON(sizeof(st->preempted) != sizeof(preempted)); 4443 4444 if (!copy_to_user_nofault(&st->preempted, &preempted, sizeof(preempted))) 4445 vcpu->arch.st.preempted = KVM_VCPU_PREEMPTED; 4446 4447 mark_page_dirty_in_slot(vcpu->kvm, ghc->memslot, gpa_to_gfn(ghc->gpa)); 4448 } 4449 4450 void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu) 4451 { 4452 int idx; 4453 4454 if (vcpu->preempted && !vcpu->arch.guest_state_protected) 4455 vcpu->arch.preempted_in_kernel = !static_call(kvm_x86_get_cpl)(vcpu); 4456 4457 /* 4458 * Take the srcu lock as memslots will be accessed to check the gfn 4459 * cache generation against the memslots generation. 4460 */ 4461 idx = srcu_read_lock(&vcpu->kvm->srcu); 4462 if (kvm_xen_msr_enabled(vcpu->kvm)) 4463 kvm_xen_runstate_set_preempted(vcpu); 4464 else 4465 kvm_steal_time_set_preempted(vcpu); 4466 srcu_read_unlock(&vcpu->kvm->srcu, idx); 4467 4468 static_call(kvm_x86_vcpu_put)(vcpu); 4469 vcpu->arch.last_host_tsc = rdtsc(); 4470 } 4471 4472 static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu, 4473 struct kvm_lapic_state *s) 4474 { 4475 static_call_cond(kvm_x86_sync_pir_to_irr)(vcpu); 4476 4477 return kvm_apic_get_state(vcpu, s); 4478 } 4479 4480 static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu, 4481 struct kvm_lapic_state *s) 4482 { 4483 int r; 4484 4485 r = kvm_apic_set_state(vcpu, s); 4486 if (r) 4487 return r; 4488 update_cr8_intercept(vcpu); 4489 4490 return 0; 4491 } 4492 4493 static int kvm_cpu_accept_dm_intr(struct kvm_vcpu *vcpu) 4494 { 4495 /* 4496 * We can accept userspace's request for interrupt injection 4497 * as long as we have a place to store the interrupt number. 4498 * The actual injection will happen when the CPU is able to 4499 * deliver the interrupt. 4500 */ 4501 if (kvm_cpu_has_extint(vcpu)) 4502 return false; 4503 4504 /* Acknowledging ExtINT does not happen if LINT0 is masked. */ 4505 return (!lapic_in_kernel(vcpu) || 4506 kvm_apic_accept_pic_intr(vcpu)); 4507 } 4508 4509 static int kvm_vcpu_ready_for_interrupt_injection(struct kvm_vcpu *vcpu) 4510 { 4511 /* 4512 * Do not cause an interrupt window exit if an exception 4513 * is pending or an event needs reinjection; userspace 4514 * might want to inject the interrupt manually using KVM_SET_REGS 4515 * or KVM_SET_SREGS. For that to work, we must be at an 4516 * instruction boundary and with no events half-injected. 4517 */ 4518 return (kvm_arch_interrupt_allowed(vcpu) && 4519 kvm_cpu_accept_dm_intr(vcpu) && 4520 !kvm_event_needs_reinjection(vcpu) && 4521 !vcpu->arch.exception.pending); 4522 } 4523 4524 static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu, 4525 struct kvm_interrupt *irq) 4526 { 4527 if (irq->irq >= KVM_NR_INTERRUPTS) 4528 return -EINVAL; 4529 4530 if (!irqchip_in_kernel(vcpu->kvm)) { 4531 kvm_queue_interrupt(vcpu, irq->irq, false); 4532 kvm_make_request(KVM_REQ_EVENT, vcpu); 4533 return 0; 4534 } 4535 4536 /* 4537 * With in-kernel LAPIC, we only use this to inject EXTINT, so 4538 * fail for in-kernel 8259. 4539 */ 4540 if (pic_in_kernel(vcpu->kvm)) 4541 return -ENXIO; 4542 4543 if (vcpu->arch.pending_external_vector != -1) 4544 return -EEXIST; 4545 4546 vcpu->arch.pending_external_vector = irq->irq; 4547 kvm_make_request(KVM_REQ_EVENT, vcpu); 4548 return 0; 4549 } 4550 4551 static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu) 4552 { 4553 kvm_inject_nmi(vcpu); 4554 4555 return 0; 4556 } 4557 4558 static int kvm_vcpu_ioctl_smi(struct kvm_vcpu *vcpu) 4559 { 4560 kvm_make_request(KVM_REQ_SMI, vcpu); 4561 4562 return 0; 4563 } 4564 4565 static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu, 4566 struct kvm_tpr_access_ctl *tac) 4567 { 4568 if (tac->flags) 4569 return -EINVAL; 4570 vcpu->arch.tpr_access_reporting = !!tac->enabled; 4571 return 0; 4572 } 4573 4574 static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu, 4575 u64 mcg_cap) 4576 { 4577 int r; 4578 unsigned bank_num = mcg_cap & 0xff, bank; 4579 4580 r = -EINVAL; 4581 if (!bank_num || bank_num > KVM_MAX_MCE_BANKS) 4582 goto out; 4583 if (mcg_cap & ~(kvm_mce_cap_supported | 0xff | 0xff0000)) 4584 goto out; 4585 r = 0; 4586 vcpu->arch.mcg_cap = mcg_cap; 4587 /* Init IA32_MCG_CTL to all 1s */ 4588 if (mcg_cap & MCG_CTL_P) 4589 vcpu->arch.mcg_ctl = ~(u64)0; 4590 /* Init IA32_MCi_CTL to all 1s */ 4591 for (bank = 0; bank < bank_num; bank++) 4592 vcpu->arch.mce_banks[bank*4] = ~(u64)0; 4593 4594 static_call(kvm_x86_setup_mce)(vcpu); 4595 out: 4596 return r; 4597 } 4598 4599 static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu, 4600 struct kvm_x86_mce *mce) 4601 { 4602 u64 mcg_cap = vcpu->arch.mcg_cap; 4603 unsigned bank_num = mcg_cap & 0xff; 4604 u64 *banks = vcpu->arch.mce_banks; 4605 4606 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL)) 4607 return -EINVAL; 4608 /* 4609 * if IA32_MCG_CTL is not all 1s, the uncorrected error 4610 * reporting is disabled 4611 */ 4612 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) && 4613 vcpu->arch.mcg_ctl != ~(u64)0) 4614 return 0; 4615 banks += 4 * mce->bank; 4616 /* 4617 * if IA32_MCi_CTL is not all 1s, the uncorrected error 4618 * reporting is disabled for the bank 4619 */ 4620 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0) 4621 return 0; 4622 if (mce->status & MCI_STATUS_UC) { 4623 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) || 4624 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) { 4625 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); 4626 return 0; 4627 } 4628 if (banks[1] & MCI_STATUS_VAL) 4629 mce->status |= MCI_STATUS_OVER; 4630 banks[2] = mce->addr; 4631 banks[3] = mce->misc; 4632 vcpu->arch.mcg_status = mce->mcg_status; 4633 banks[1] = mce->status; 4634 kvm_queue_exception(vcpu, MC_VECTOR); 4635 } else if (!(banks[1] & MCI_STATUS_VAL) 4636 || !(banks[1] & MCI_STATUS_UC)) { 4637 if (banks[1] & MCI_STATUS_VAL) 4638 mce->status |= MCI_STATUS_OVER; 4639 banks[2] = mce->addr; 4640 banks[3] = mce->misc; 4641 banks[1] = mce->status; 4642 } else 4643 banks[1] |= MCI_STATUS_OVER; 4644 return 0; 4645 } 4646 4647 static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu, 4648 struct kvm_vcpu_events *events) 4649 { 4650 process_nmi(vcpu); 4651 4652 if (kvm_check_request(KVM_REQ_SMI, vcpu)) 4653 process_smi(vcpu); 4654 4655 /* 4656 * In guest mode, payload delivery should be deferred, 4657 * so that the L1 hypervisor can intercept #PF before 4658 * CR2 is modified (or intercept #DB before DR6 is 4659 * modified under nVMX). Unless the per-VM capability, 4660 * KVM_CAP_EXCEPTION_PAYLOAD, is set, we may not defer the delivery of 4661 * an exception payload and handle after a KVM_GET_VCPU_EVENTS. Since we 4662 * opportunistically defer the exception payload, deliver it if the 4663 * capability hasn't been requested before processing a 4664 * KVM_GET_VCPU_EVENTS. 4665 */ 4666 if (!vcpu->kvm->arch.exception_payload_enabled && 4667 vcpu->arch.exception.pending && vcpu->arch.exception.has_payload) 4668 kvm_deliver_exception_payload(vcpu); 4669 4670 /* 4671 * The API doesn't provide the instruction length for software 4672 * exceptions, so don't report them. As long as the guest RIP 4673 * isn't advanced, we should expect to encounter the exception 4674 * again. 4675 */ 4676 if (kvm_exception_is_soft(vcpu->arch.exception.nr)) { 4677 events->exception.injected = 0; 4678 events->exception.pending = 0; 4679 } else { 4680 events->exception.injected = vcpu->arch.exception.injected; 4681 events->exception.pending = vcpu->arch.exception.pending; 4682 /* 4683 * For ABI compatibility, deliberately conflate 4684 * pending and injected exceptions when 4685 * KVM_CAP_EXCEPTION_PAYLOAD isn't enabled. 4686 */ 4687 if (!vcpu->kvm->arch.exception_payload_enabled) 4688 events->exception.injected |= 4689 vcpu->arch.exception.pending; 4690 } 4691 events->exception.nr = vcpu->arch.exception.nr; 4692 events->exception.has_error_code = vcpu->arch.exception.has_error_code; 4693 events->exception.error_code = vcpu->arch.exception.error_code; 4694 events->exception_has_payload = vcpu->arch.exception.has_payload; 4695 events->exception_payload = vcpu->arch.exception.payload; 4696 4697 events->interrupt.injected = 4698 vcpu->arch.interrupt.injected && !vcpu->arch.interrupt.soft; 4699 events->interrupt.nr = vcpu->arch.interrupt.nr; 4700 events->interrupt.soft = 0; 4701 events->interrupt.shadow = static_call(kvm_x86_get_interrupt_shadow)(vcpu); 4702 4703 events->nmi.injected = vcpu->arch.nmi_injected; 4704 events->nmi.pending = vcpu->arch.nmi_pending != 0; 4705 events->nmi.masked = static_call(kvm_x86_get_nmi_mask)(vcpu); 4706 events->nmi.pad = 0; 4707 4708 events->sipi_vector = 0; /* never valid when reporting to user space */ 4709 4710 events->smi.smm = is_smm(vcpu); 4711 events->smi.pending = vcpu->arch.smi_pending; 4712 events->smi.smm_inside_nmi = 4713 !!(vcpu->arch.hflags & HF_SMM_INSIDE_NMI_MASK); 4714 events->smi.latched_init = kvm_lapic_latched_init(vcpu); 4715 4716 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING 4717 | KVM_VCPUEVENT_VALID_SHADOW 4718 | KVM_VCPUEVENT_VALID_SMM); 4719 if (vcpu->kvm->arch.exception_payload_enabled) 4720 events->flags |= KVM_VCPUEVENT_VALID_PAYLOAD; 4721 4722 memset(&events->reserved, 0, sizeof(events->reserved)); 4723 } 4724 4725 static void kvm_smm_changed(struct kvm_vcpu *vcpu, bool entering_smm); 4726 4727 static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu, 4728 struct kvm_vcpu_events *events) 4729 { 4730 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING 4731 | KVM_VCPUEVENT_VALID_SIPI_VECTOR 4732 | KVM_VCPUEVENT_VALID_SHADOW 4733 | KVM_VCPUEVENT_VALID_SMM 4734 | KVM_VCPUEVENT_VALID_PAYLOAD)) 4735 return -EINVAL; 4736 4737 if (events->flags & KVM_VCPUEVENT_VALID_PAYLOAD) { 4738 if (!vcpu->kvm->arch.exception_payload_enabled) 4739 return -EINVAL; 4740 if (events->exception.pending) 4741 events->exception.injected = 0; 4742 else 4743 events->exception_has_payload = 0; 4744 } else { 4745 events->exception.pending = 0; 4746 events->exception_has_payload = 0; 4747 } 4748 4749 if ((events->exception.injected || events->exception.pending) && 4750 (events->exception.nr > 31 || events->exception.nr == NMI_VECTOR)) 4751 return -EINVAL; 4752 4753 /* INITs are latched while in SMM */ 4754 if (events->flags & KVM_VCPUEVENT_VALID_SMM && 4755 (events->smi.smm || events->smi.pending) && 4756 vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) 4757 return -EINVAL; 4758 4759 process_nmi(vcpu); 4760 vcpu->arch.exception.injected = events->exception.injected; 4761 vcpu->arch.exception.pending = events->exception.pending; 4762 vcpu->arch.exception.nr = events->exception.nr; 4763 vcpu->arch.exception.has_error_code = events->exception.has_error_code; 4764 vcpu->arch.exception.error_code = events->exception.error_code; 4765 vcpu->arch.exception.has_payload = events->exception_has_payload; 4766 vcpu->arch.exception.payload = events->exception_payload; 4767 4768 vcpu->arch.interrupt.injected = events->interrupt.injected; 4769 vcpu->arch.interrupt.nr = events->interrupt.nr; 4770 vcpu->arch.interrupt.soft = events->interrupt.soft; 4771 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW) 4772 static_call(kvm_x86_set_interrupt_shadow)(vcpu, 4773 events->interrupt.shadow); 4774 4775 vcpu->arch.nmi_injected = events->nmi.injected; 4776 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING) 4777 vcpu->arch.nmi_pending = events->nmi.pending; 4778 static_call(kvm_x86_set_nmi_mask)(vcpu, events->nmi.masked); 4779 4780 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR && 4781 lapic_in_kernel(vcpu)) 4782 vcpu->arch.apic->sipi_vector = events->sipi_vector; 4783 4784 if (events->flags & KVM_VCPUEVENT_VALID_SMM) { 4785 if (!!(vcpu->arch.hflags & HF_SMM_MASK) != events->smi.smm) 4786 kvm_smm_changed(vcpu, events->smi.smm); 4787 4788 vcpu->arch.smi_pending = events->smi.pending; 4789 4790 if (events->smi.smm) { 4791 if (events->smi.smm_inside_nmi) 4792 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK; 4793 else 4794 vcpu->arch.hflags &= ~HF_SMM_INSIDE_NMI_MASK; 4795 } 4796 4797 if (lapic_in_kernel(vcpu)) { 4798 if (events->smi.latched_init) 4799 set_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events); 4800 else 4801 clear_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events); 4802 } 4803 } 4804 4805 kvm_make_request(KVM_REQ_EVENT, vcpu); 4806 4807 return 0; 4808 } 4809 4810 static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu, 4811 struct kvm_debugregs *dbgregs) 4812 { 4813 unsigned long val; 4814 4815 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db)); 4816 kvm_get_dr(vcpu, 6, &val); 4817 dbgregs->dr6 = val; 4818 dbgregs->dr7 = vcpu->arch.dr7; 4819 dbgregs->flags = 0; 4820 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved)); 4821 } 4822 4823 static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu, 4824 struct kvm_debugregs *dbgregs) 4825 { 4826 if (dbgregs->flags) 4827 return -EINVAL; 4828 4829 if (!kvm_dr6_valid(dbgregs->dr6)) 4830 return -EINVAL; 4831 if (!kvm_dr7_valid(dbgregs->dr7)) 4832 return -EINVAL; 4833 4834 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db)); 4835 kvm_update_dr0123(vcpu); 4836 vcpu->arch.dr6 = dbgregs->dr6; 4837 vcpu->arch.dr7 = dbgregs->dr7; 4838 kvm_update_dr7(vcpu); 4839 4840 return 0; 4841 } 4842 4843 static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu, 4844 struct kvm_xsave *guest_xsave) 4845 { 4846 if (fpstate_is_confidential(&vcpu->arch.guest_fpu)) 4847 return; 4848 4849 fpu_copy_guest_fpstate_to_uabi(&vcpu->arch.guest_fpu, 4850 guest_xsave->region, 4851 sizeof(guest_xsave->region), 4852 vcpu->arch.pkru); 4853 } 4854 4855 static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu, 4856 struct kvm_xsave *guest_xsave) 4857 { 4858 if (fpstate_is_confidential(&vcpu->arch.guest_fpu)) 4859 return 0; 4860 4861 return fpu_copy_uabi_to_guest_fpstate(&vcpu->arch.guest_fpu, 4862 guest_xsave->region, 4863 supported_xcr0, &vcpu->arch.pkru); 4864 } 4865 4866 static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu, 4867 struct kvm_xcrs *guest_xcrs) 4868 { 4869 if (!boot_cpu_has(X86_FEATURE_XSAVE)) { 4870 guest_xcrs->nr_xcrs = 0; 4871 return; 4872 } 4873 4874 guest_xcrs->nr_xcrs = 1; 4875 guest_xcrs->flags = 0; 4876 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK; 4877 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0; 4878 } 4879 4880 static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu, 4881 struct kvm_xcrs *guest_xcrs) 4882 { 4883 int i, r = 0; 4884 4885 if (!boot_cpu_has(X86_FEATURE_XSAVE)) 4886 return -EINVAL; 4887 4888 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags) 4889 return -EINVAL; 4890 4891 for (i = 0; i < guest_xcrs->nr_xcrs; i++) 4892 /* Only support XCR0 currently */ 4893 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) { 4894 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK, 4895 guest_xcrs->xcrs[i].value); 4896 break; 4897 } 4898 if (r) 4899 r = -EINVAL; 4900 return r; 4901 } 4902 4903 /* 4904 * kvm_set_guest_paused() indicates to the guest kernel that it has been 4905 * stopped by the hypervisor. This function will be called from the host only. 4906 * EINVAL is returned when the host attempts to set the flag for a guest that 4907 * does not support pv clocks. 4908 */ 4909 static int kvm_set_guest_paused(struct kvm_vcpu *vcpu) 4910 { 4911 if (!vcpu->arch.pv_time_enabled) 4912 return -EINVAL; 4913 vcpu->arch.pvclock_set_guest_stopped_request = true; 4914 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 4915 return 0; 4916 } 4917 4918 static int kvm_arch_tsc_has_attr(struct kvm_vcpu *vcpu, 4919 struct kvm_device_attr *attr) 4920 { 4921 int r; 4922 4923 switch (attr->attr) { 4924 case KVM_VCPU_TSC_OFFSET: 4925 r = 0; 4926 break; 4927 default: 4928 r = -ENXIO; 4929 } 4930 4931 return r; 4932 } 4933 4934 static int kvm_arch_tsc_get_attr(struct kvm_vcpu *vcpu, 4935 struct kvm_device_attr *attr) 4936 { 4937 u64 __user *uaddr = (u64 __user *)(unsigned long)attr->addr; 4938 int r; 4939 4940 if ((u64)(unsigned long)uaddr != attr->addr) 4941 return -EFAULT; 4942 4943 switch (attr->attr) { 4944 case KVM_VCPU_TSC_OFFSET: 4945 r = -EFAULT; 4946 if (put_user(vcpu->arch.l1_tsc_offset, uaddr)) 4947 break; 4948 r = 0; 4949 break; 4950 default: 4951 r = -ENXIO; 4952 } 4953 4954 return r; 4955 } 4956 4957 static int kvm_arch_tsc_set_attr(struct kvm_vcpu *vcpu, 4958 struct kvm_device_attr *attr) 4959 { 4960 u64 __user *uaddr = (u64 __user *)(unsigned long)attr->addr; 4961 struct kvm *kvm = vcpu->kvm; 4962 int r; 4963 4964 if ((u64)(unsigned long)uaddr != attr->addr) 4965 return -EFAULT; 4966 4967 switch (attr->attr) { 4968 case KVM_VCPU_TSC_OFFSET: { 4969 u64 offset, tsc, ns; 4970 unsigned long flags; 4971 bool matched; 4972 4973 r = -EFAULT; 4974 if (get_user(offset, uaddr)) 4975 break; 4976 4977 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags); 4978 4979 matched = (vcpu->arch.virtual_tsc_khz && 4980 kvm->arch.last_tsc_khz == vcpu->arch.virtual_tsc_khz && 4981 kvm->arch.last_tsc_offset == offset); 4982 4983 tsc = kvm_scale_tsc(vcpu, rdtsc(), vcpu->arch.l1_tsc_scaling_ratio) + offset; 4984 ns = get_kvmclock_base_ns(); 4985 4986 __kvm_synchronize_tsc(vcpu, offset, tsc, ns, matched); 4987 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags); 4988 4989 r = 0; 4990 break; 4991 } 4992 default: 4993 r = -ENXIO; 4994 } 4995 4996 return r; 4997 } 4998 4999 static int kvm_vcpu_ioctl_device_attr(struct kvm_vcpu *vcpu, 5000 unsigned int ioctl, 5001 void __user *argp) 5002 { 5003 struct kvm_device_attr attr; 5004 int r; 5005 5006 if (copy_from_user(&attr, argp, sizeof(attr))) 5007 return -EFAULT; 5008 5009 if (attr.group != KVM_VCPU_TSC_CTRL) 5010 return -ENXIO; 5011 5012 switch (ioctl) { 5013 case KVM_HAS_DEVICE_ATTR: 5014 r = kvm_arch_tsc_has_attr(vcpu, &attr); 5015 break; 5016 case KVM_GET_DEVICE_ATTR: 5017 r = kvm_arch_tsc_get_attr(vcpu, &attr); 5018 break; 5019 case KVM_SET_DEVICE_ATTR: 5020 r = kvm_arch_tsc_set_attr(vcpu, &attr); 5021 break; 5022 } 5023 5024 return r; 5025 } 5026 5027 static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu, 5028 struct kvm_enable_cap *cap) 5029 { 5030 int r; 5031 uint16_t vmcs_version; 5032 void __user *user_ptr; 5033 5034 if (cap->flags) 5035 return -EINVAL; 5036 5037 switch (cap->cap) { 5038 case KVM_CAP_HYPERV_SYNIC2: 5039 if (cap->args[0]) 5040 return -EINVAL; 5041 fallthrough; 5042 5043 case KVM_CAP_HYPERV_SYNIC: 5044 if (!irqchip_in_kernel(vcpu->kvm)) 5045 return -EINVAL; 5046 return kvm_hv_activate_synic(vcpu, cap->cap == 5047 KVM_CAP_HYPERV_SYNIC2); 5048 case KVM_CAP_HYPERV_ENLIGHTENED_VMCS: 5049 if (!kvm_x86_ops.nested_ops->enable_evmcs) 5050 return -ENOTTY; 5051 r = kvm_x86_ops.nested_ops->enable_evmcs(vcpu, &vmcs_version); 5052 if (!r) { 5053 user_ptr = (void __user *)(uintptr_t)cap->args[0]; 5054 if (copy_to_user(user_ptr, &vmcs_version, 5055 sizeof(vmcs_version))) 5056 r = -EFAULT; 5057 } 5058 return r; 5059 case KVM_CAP_HYPERV_DIRECT_TLBFLUSH: 5060 if (!kvm_x86_ops.enable_direct_tlbflush) 5061 return -ENOTTY; 5062 5063 return static_call(kvm_x86_enable_direct_tlbflush)(vcpu); 5064 5065 case KVM_CAP_HYPERV_ENFORCE_CPUID: 5066 return kvm_hv_set_enforce_cpuid(vcpu, cap->args[0]); 5067 5068 case KVM_CAP_ENFORCE_PV_FEATURE_CPUID: 5069 vcpu->arch.pv_cpuid.enforce = cap->args[0]; 5070 if (vcpu->arch.pv_cpuid.enforce) 5071 kvm_update_pv_runtime(vcpu); 5072 5073 return 0; 5074 default: 5075 return -EINVAL; 5076 } 5077 } 5078 5079 long kvm_arch_vcpu_ioctl(struct file *filp, 5080 unsigned int ioctl, unsigned long arg) 5081 { 5082 struct kvm_vcpu *vcpu = filp->private_data; 5083 void __user *argp = (void __user *)arg; 5084 int r; 5085 union { 5086 struct kvm_sregs2 *sregs2; 5087 struct kvm_lapic_state *lapic; 5088 struct kvm_xsave *xsave; 5089 struct kvm_xcrs *xcrs; 5090 void *buffer; 5091 } u; 5092 5093 vcpu_load(vcpu); 5094 5095 u.buffer = NULL; 5096 switch (ioctl) { 5097 case KVM_GET_LAPIC: { 5098 r = -EINVAL; 5099 if (!lapic_in_kernel(vcpu)) 5100 goto out; 5101 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), 5102 GFP_KERNEL_ACCOUNT); 5103 5104 r = -ENOMEM; 5105 if (!u.lapic) 5106 goto out; 5107 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic); 5108 if (r) 5109 goto out; 5110 r = -EFAULT; 5111 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state))) 5112 goto out; 5113 r = 0; 5114 break; 5115 } 5116 case KVM_SET_LAPIC: { 5117 r = -EINVAL; 5118 if (!lapic_in_kernel(vcpu)) 5119 goto out; 5120 u.lapic = memdup_user(argp, sizeof(*u.lapic)); 5121 if (IS_ERR(u.lapic)) { 5122 r = PTR_ERR(u.lapic); 5123 goto out_nofree; 5124 } 5125 5126 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic); 5127 break; 5128 } 5129 case KVM_INTERRUPT: { 5130 struct kvm_interrupt irq; 5131 5132 r = -EFAULT; 5133 if (copy_from_user(&irq, argp, sizeof(irq))) 5134 goto out; 5135 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq); 5136 break; 5137 } 5138 case KVM_NMI: { 5139 r = kvm_vcpu_ioctl_nmi(vcpu); 5140 break; 5141 } 5142 case KVM_SMI: { 5143 r = kvm_vcpu_ioctl_smi(vcpu); 5144 break; 5145 } 5146 case KVM_SET_CPUID: { 5147 struct kvm_cpuid __user *cpuid_arg = argp; 5148 struct kvm_cpuid cpuid; 5149 5150 /* 5151 * KVM does not correctly handle changing guest CPUID after KVM_RUN, as 5152 * MAXPHYADDR, GBPAGES support, AMD reserved bit behavior, etc.. aren't 5153 * tracked in kvm_mmu_page_role. As a result, KVM may miss guest page 5154 * faults due to reusing SPs/SPTEs. In practice no sane VMM mucks with 5155 * the core vCPU model on the fly, so fail. 5156 */ 5157 r = -EINVAL; 5158 if (vcpu->arch.last_vmentry_cpu != -1) 5159 goto out; 5160 5161 r = -EFAULT; 5162 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid))) 5163 goto out; 5164 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries); 5165 break; 5166 } 5167 case KVM_SET_CPUID2: { 5168 struct kvm_cpuid2 __user *cpuid_arg = argp; 5169 struct kvm_cpuid2 cpuid; 5170 5171 /* 5172 * KVM_SET_CPUID{,2} after KVM_RUN is forbidded, see the comment in 5173 * KVM_SET_CPUID case above. 5174 */ 5175 r = -EINVAL; 5176 if (vcpu->arch.last_vmentry_cpu != -1) 5177 goto out; 5178 5179 r = -EFAULT; 5180 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid))) 5181 goto out; 5182 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid, 5183 cpuid_arg->entries); 5184 break; 5185 } 5186 case KVM_GET_CPUID2: { 5187 struct kvm_cpuid2 __user *cpuid_arg = argp; 5188 struct kvm_cpuid2 cpuid; 5189 5190 r = -EFAULT; 5191 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid))) 5192 goto out; 5193 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid, 5194 cpuid_arg->entries); 5195 if (r) 5196 goto out; 5197 r = -EFAULT; 5198 if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid))) 5199 goto out; 5200 r = 0; 5201 break; 5202 } 5203 case KVM_GET_MSRS: { 5204 int idx = srcu_read_lock(&vcpu->kvm->srcu); 5205 r = msr_io(vcpu, argp, do_get_msr, 1); 5206 srcu_read_unlock(&vcpu->kvm->srcu, idx); 5207 break; 5208 } 5209 case KVM_SET_MSRS: { 5210 int idx = srcu_read_lock(&vcpu->kvm->srcu); 5211 r = msr_io(vcpu, argp, do_set_msr, 0); 5212 srcu_read_unlock(&vcpu->kvm->srcu, idx); 5213 break; 5214 } 5215 case KVM_TPR_ACCESS_REPORTING: { 5216 struct kvm_tpr_access_ctl tac; 5217 5218 r = -EFAULT; 5219 if (copy_from_user(&tac, argp, sizeof(tac))) 5220 goto out; 5221 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac); 5222 if (r) 5223 goto out; 5224 r = -EFAULT; 5225 if (copy_to_user(argp, &tac, sizeof(tac))) 5226 goto out; 5227 r = 0; 5228 break; 5229 }; 5230 case KVM_SET_VAPIC_ADDR: { 5231 struct kvm_vapic_addr va; 5232 int idx; 5233 5234 r = -EINVAL; 5235 if (!lapic_in_kernel(vcpu)) 5236 goto out; 5237 r = -EFAULT; 5238 if (copy_from_user(&va, argp, sizeof(va))) 5239 goto out; 5240 idx = srcu_read_lock(&vcpu->kvm->srcu); 5241 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr); 5242 srcu_read_unlock(&vcpu->kvm->srcu, idx); 5243 break; 5244 } 5245 case KVM_X86_SETUP_MCE: { 5246 u64 mcg_cap; 5247 5248 r = -EFAULT; 5249 if (copy_from_user(&mcg_cap, argp, sizeof(mcg_cap))) 5250 goto out; 5251 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap); 5252 break; 5253 } 5254 case KVM_X86_SET_MCE: { 5255 struct kvm_x86_mce mce; 5256 5257 r = -EFAULT; 5258 if (copy_from_user(&mce, argp, sizeof(mce))) 5259 goto out; 5260 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce); 5261 break; 5262 } 5263 case KVM_GET_VCPU_EVENTS: { 5264 struct kvm_vcpu_events events; 5265 5266 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events); 5267 5268 r = -EFAULT; 5269 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events))) 5270 break; 5271 r = 0; 5272 break; 5273 } 5274 case KVM_SET_VCPU_EVENTS: { 5275 struct kvm_vcpu_events events; 5276 5277 r = -EFAULT; 5278 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events))) 5279 break; 5280 5281 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events); 5282 break; 5283 } 5284 case KVM_GET_DEBUGREGS: { 5285 struct kvm_debugregs dbgregs; 5286 5287 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs); 5288 5289 r = -EFAULT; 5290 if (copy_to_user(argp, &dbgregs, 5291 sizeof(struct kvm_debugregs))) 5292 break; 5293 r = 0; 5294 break; 5295 } 5296 case KVM_SET_DEBUGREGS: { 5297 struct kvm_debugregs dbgregs; 5298 5299 r = -EFAULT; 5300 if (copy_from_user(&dbgregs, argp, 5301 sizeof(struct kvm_debugregs))) 5302 break; 5303 5304 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs); 5305 break; 5306 } 5307 case KVM_GET_XSAVE: { 5308 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL_ACCOUNT); 5309 r = -ENOMEM; 5310 if (!u.xsave) 5311 break; 5312 5313 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave); 5314 5315 r = -EFAULT; 5316 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave))) 5317 break; 5318 r = 0; 5319 break; 5320 } 5321 case KVM_SET_XSAVE: { 5322 u.xsave = memdup_user(argp, sizeof(*u.xsave)); 5323 if (IS_ERR(u.xsave)) { 5324 r = PTR_ERR(u.xsave); 5325 goto out_nofree; 5326 } 5327 5328 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave); 5329 break; 5330 } 5331 case KVM_GET_XCRS: { 5332 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL_ACCOUNT); 5333 r = -ENOMEM; 5334 if (!u.xcrs) 5335 break; 5336 5337 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs); 5338 5339 r = -EFAULT; 5340 if (copy_to_user(argp, u.xcrs, 5341 sizeof(struct kvm_xcrs))) 5342 break; 5343 r = 0; 5344 break; 5345 } 5346 case KVM_SET_XCRS: { 5347 u.xcrs = memdup_user(argp, sizeof(*u.xcrs)); 5348 if (IS_ERR(u.xcrs)) { 5349 r = PTR_ERR(u.xcrs); 5350 goto out_nofree; 5351 } 5352 5353 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs); 5354 break; 5355 } 5356 case KVM_SET_TSC_KHZ: { 5357 u32 user_tsc_khz; 5358 5359 r = -EINVAL; 5360 user_tsc_khz = (u32)arg; 5361 5362 if (kvm_has_tsc_control && 5363 user_tsc_khz >= kvm_max_guest_tsc_khz) 5364 goto out; 5365 5366 if (user_tsc_khz == 0) 5367 user_tsc_khz = tsc_khz; 5368 5369 if (!kvm_set_tsc_khz(vcpu, user_tsc_khz)) 5370 r = 0; 5371 5372 goto out; 5373 } 5374 case KVM_GET_TSC_KHZ: { 5375 r = vcpu->arch.virtual_tsc_khz; 5376 goto out; 5377 } 5378 case KVM_KVMCLOCK_CTRL: { 5379 r = kvm_set_guest_paused(vcpu); 5380 goto out; 5381 } 5382 case KVM_ENABLE_CAP: { 5383 struct kvm_enable_cap cap; 5384 5385 r = -EFAULT; 5386 if (copy_from_user(&cap, argp, sizeof(cap))) 5387 goto out; 5388 r = kvm_vcpu_ioctl_enable_cap(vcpu, &cap); 5389 break; 5390 } 5391 case KVM_GET_NESTED_STATE: { 5392 struct kvm_nested_state __user *user_kvm_nested_state = argp; 5393 u32 user_data_size; 5394 5395 r = -EINVAL; 5396 if (!kvm_x86_ops.nested_ops->get_state) 5397 break; 5398 5399 BUILD_BUG_ON(sizeof(user_data_size) != sizeof(user_kvm_nested_state->size)); 5400 r = -EFAULT; 5401 if (get_user(user_data_size, &user_kvm_nested_state->size)) 5402 break; 5403 5404 r = kvm_x86_ops.nested_ops->get_state(vcpu, user_kvm_nested_state, 5405 user_data_size); 5406 if (r < 0) 5407 break; 5408 5409 if (r > user_data_size) { 5410 if (put_user(r, &user_kvm_nested_state->size)) 5411 r = -EFAULT; 5412 else 5413 r = -E2BIG; 5414 break; 5415 } 5416 5417 r = 0; 5418 break; 5419 } 5420 case KVM_SET_NESTED_STATE: { 5421 struct kvm_nested_state __user *user_kvm_nested_state = argp; 5422 struct kvm_nested_state kvm_state; 5423 int idx; 5424 5425 r = -EINVAL; 5426 if (!kvm_x86_ops.nested_ops->set_state) 5427 break; 5428 5429 r = -EFAULT; 5430 if (copy_from_user(&kvm_state, user_kvm_nested_state, sizeof(kvm_state))) 5431 break; 5432 5433 r = -EINVAL; 5434 if (kvm_state.size < sizeof(kvm_state)) 5435 break; 5436 5437 if (kvm_state.flags & 5438 ~(KVM_STATE_NESTED_RUN_PENDING | KVM_STATE_NESTED_GUEST_MODE 5439 | KVM_STATE_NESTED_EVMCS | KVM_STATE_NESTED_MTF_PENDING 5440 | KVM_STATE_NESTED_GIF_SET)) 5441 break; 5442 5443 /* nested_run_pending implies guest_mode. */ 5444 if ((kvm_state.flags & KVM_STATE_NESTED_RUN_PENDING) 5445 && !(kvm_state.flags & KVM_STATE_NESTED_GUEST_MODE)) 5446 break; 5447 5448 idx = srcu_read_lock(&vcpu->kvm->srcu); 5449 r = kvm_x86_ops.nested_ops->set_state(vcpu, user_kvm_nested_state, &kvm_state); 5450 srcu_read_unlock(&vcpu->kvm->srcu, idx); 5451 break; 5452 } 5453 case KVM_GET_SUPPORTED_HV_CPUID: 5454 r = kvm_ioctl_get_supported_hv_cpuid(vcpu, argp); 5455 break; 5456 #ifdef CONFIG_KVM_XEN 5457 case KVM_XEN_VCPU_GET_ATTR: { 5458 struct kvm_xen_vcpu_attr xva; 5459 5460 r = -EFAULT; 5461 if (copy_from_user(&xva, argp, sizeof(xva))) 5462 goto out; 5463 r = kvm_xen_vcpu_get_attr(vcpu, &xva); 5464 if (!r && copy_to_user(argp, &xva, sizeof(xva))) 5465 r = -EFAULT; 5466 break; 5467 } 5468 case KVM_XEN_VCPU_SET_ATTR: { 5469 struct kvm_xen_vcpu_attr xva; 5470 5471 r = -EFAULT; 5472 if (copy_from_user(&xva, argp, sizeof(xva))) 5473 goto out; 5474 r = kvm_xen_vcpu_set_attr(vcpu, &xva); 5475 break; 5476 } 5477 #endif 5478 case KVM_GET_SREGS2: { 5479 u.sregs2 = kzalloc(sizeof(struct kvm_sregs2), GFP_KERNEL); 5480 r = -ENOMEM; 5481 if (!u.sregs2) 5482 goto out; 5483 __get_sregs2(vcpu, u.sregs2); 5484 r = -EFAULT; 5485 if (copy_to_user(argp, u.sregs2, sizeof(struct kvm_sregs2))) 5486 goto out; 5487 r = 0; 5488 break; 5489 } 5490 case KVM_SET_SREGS2: { 5491 u.sregs2 = memdup_user(argp, sizeof(struct kvm_sregs2)); 5492 if (IS_ERR(u.sregs2)) { 5493 r = PTR_ERR(u.sregs2); 5494 u.sregs2 = NULL; 5495 goto out; 5496 } 5497 r = __set_sregs2(vcpu, u.sregs2); 5498 break; 5499 } 5500 case KVM_HAS_DEVICE_ATTR: 5501 case KVM_GET_DEVICE_ATTR: 5502 case KVM_SET_DEVICE_ATTR: 5503 r = kvm_vcpu_ioctl_device_attr(vcpu, ioctl, argp); 5504 break; 5505 default: 5506 r = -EINVAL; 5507 } 5508 out: 5509 kfree(u.buffer); 5510 out_nofree: 5511 vcpu_put(vcpu); 5512 return r; 5513 } 5514 5515 vm_fault_t kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf) 5516 { 5517 return VM_FAULT_SIGBUS; 5518 } 5519 5520 static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr) 5521 { 5522 int ret; 5523 5524 if (addr > (unsigned int)(-3 * PAGE_SIZE)) 5525 return -EINVAL; 5526 ret = static_call(kvm_x86_set_tss_addr)(kvm, addr); 5527 return ret; 5528 } 5529 5530 static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm, 5531 u64 ident_addr) 5532 { 5533 return static_call(kvm_x86_set_identity_map_addr)(kvm, ident_addr); 5534 } 5535 5536 static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm, 5537 unsigned long kvm_nr_mmu_pages) 5538 { 5539 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES) 5540 return -EINVAL; 5541 5542 mutex_lock(&kvm->slots_lock); 5543 5544 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages); 5545 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages; 5546 5547 mutex_unlock(&kvm->slots_lock); 5548 return 0; 5549 } 5550 5551 static unsigned long kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm) 5552 { 5553 return kvm->arch.n_max_mmu_pages; 5554 } 5555 5556 static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip) 5557 { 5558 struct kvm_pic *pic = kvm->arch.vpic; 5559 int r; 5560 5561 r = 0; 5562 switch (chip->chip_id) { 5563 case KVM_IRQCHIP_PIC_MASTER: 5564 memcpy(&chip->chip.pic, &pic->pics[0], 5565 sizeof(struct kvm_pic_state)); 5566 break; 5567 case KVM_IRQCHIP_PIC_SLAVE: 5568 memcpy(&chip->chip.pic, &pic->pics[1], 5569 sizeof(struct kvm_pic_state)); 5570 break; 5571 case KVM_IRQCHIP_IOAPIC: 5572 kvm_get_ioapic(kvm, &chip->chip.ioapic); 5573 break; 5574 default: 5575 r = -EINVAL; 5576 break; 5577 } 5578 return r; 5579 } 5580 5581 static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip) 5582 { 5583 struct kvm_pic *pic = kvm->arch.vpic; 5584 int r; 5585 5586 r = 0; 5587 switch (chip->chip_id) { 5588 case KVM_IRQCHIP_PIC_MASTER: 5589 spin_lock(&pic->lock); 5590 memcpy(&pic->pics[0], &chip->chip.pic, 5591 sizeof(struct kvm_pic_state)); 5592 spin_unlock(&pic->lock); 5593 break; 5594 case KVM_IRQCHIP_PIC_SLAVE: 5595 spin_lock(&pic->lock); 5596 memcpy(&pic->pics[1], &chip->chip.pic, 5597 sizeof(struct kvm_pic_state)); 5598 spin_unlock(&pic->lock); 5599 break; 5600 case KVM_IRQCHIP_IOAPIC: 5601 kvm_set_ioapic(kvm, &chip->chip.ioapic); 5602 break; 5603 default: 5604 r = -EINVAL; 5605 break; 5606 } 5607 kvm_pic_update_irq(pic); 5608 return r; 5609 } 5610 5611 static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps) 5612 { 5613 struct kvm_kpit_state *kps = &kvm->arch.vpit->pit_state; 5614 5615 BUILD_BUG_ON(sizeof(*ps) != sizeof(kps->channels)); 5616 5617 mutex_lock(&kps->lock); 5618 memcpy(ps, &kps->channels, sizeof(*ps)); 5619 mutex_unlock(&kps->lock); 5620 return 0; 5621 } 5622 5623 static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps) 5624 { 5625 int i; 5626 struct kvm_pit *pit = kvm->arch.vpit; 5627 5628 mutex_lock(&pit->pit_state.lock); 5629 memcpy(&pit->pit_state.channels, ps, sizeof(*ps)); 5630 for (i = 0; i < 3; i++) 5631 kvm_pit_load_count(pit, i, ps->channels[i].count, 0); 5632 mutex_unlock(&pit->pit_state.lock); 5633 return 0; 5634 } 5635 5636 static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps) 5637 { 5638 mutex_lock(&kvm->arch.vpit->pit_state.lock); 5639 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels, 5640 sizeof(ps->channels)); 5641 ps->flags = kvm->arch.vpit->pit_state.flags; 5642 mutex_unlock(&kvm->arch.vpit->pit_state.lock); 5643 memset(&ps->reserved, 0, sizeof(ps->reserved)); 5644 return 0; 5645 } 5646 5647 static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps) 5648 { 5649 int start = 0; 5650 int i; 5651 u32 prev_legacy, cur_legacy; 5652 struct kvm_pit *pit = kvm->arch.vpit; 5653 5654 mutex_lock(&pit->pit_state.lock); 5655 prev_legacy = pit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY; 5656 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY; 5657 if (!prev_legacy && cur_legacy) 5658 start = 1; 5659 memcpy(&pit->pit_state.channels, &ps->channels, 5660 sizeof(pit->pit_state.channels)); 5661 pit->pit_state.flags = ps->flags; 5662 for (i = 0; i < 3; i++) 5663 kvm_pit_load_count(pit, i, pit->pit_state.channels[i].count, 5664 start && i == 0); 5665 mutex_unlock(&pit->pit_state.lock); 5666 return 0; 5667 } 5668 5669 static int kvm_vm_ioctl_reinject(struct kvm *kvm, 5670 struct kvm_reinject_control *control) 5671 { 5672 struct kvm_pit *pit = kvm->arch.vpit; 5673 5674 /* pit->pit_state.lock was overloaded to prevent userspace from getting 5675 * an inconsistent state after running multiple KVM_REINJECT_CONTROL 5676 * ioctls in parallel. Use a separate lock if that ioctl isn't rare. 5677 */ 5678 mutex_lock(&pit->pit_state.lock); 5679 kvm_pit_set_reinject(pit, control->pit_reinject); 5680 mutex_unlock(&pit->pit_state.lock); 5681 5682 return 0; 5683 } 5684 5685 void kvm_arch_sync_dirty_log(struct kvm *kvm, struct kvm_memory_slot *memslot) 5686 { 5687 5688 /* 5689 * Flush all CPUs' dirty log buffers to the dirty_bitmap. Called 5690 * before reporting dirty_bitmap to userspace. KVM flushes the buffers 5691 * on all VM-Exits, thus we only need to kick running vCPUs to force a 5692 * VM-Exit. 5693 */ 5694 struct kvm_vcpu *vcpu; 5695 int i; 5696 5697 kvm_for_each_vcpu(i, vcpu, kvm) 5698 kvm_vcpu_kick(vcpu); 5699 } 5700 5701 int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event, 5702 bool line_status) 5703 { 5704 if (!irqchip_in_kernel(kvm)) 5705 return -ENXIO; 5706 5707 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID, 5708 irq_event->irq, irq_event->level, 5709 line_status); 5710 return 0; 5711 } 5712 5713 int kvm_vm_ioctl_enable_cap(struct kvm *kvm, 5714 struct kvm_enable_cap *cap) 5715 { 5716 int r; 5717 5718 if (cap->flags) 5719 return -EINVAL; 5720 5721 switch (cap->cap) { 5722 case KVM_CAP_DISABLE_QUIRKS: 5723 kvm->arch.disabled_quirks = cap->args[0]; 5724 r = 0; 5725 break; 5726 case KVM_CAP_SPLIT_IRQCHIP: { 5727 mutex_lock(&kvm->lock); 5728 r = -EINVAL; 5729 if (cap->args[0] > MAX_NR_RESERVED_IOAPIC_PINS) 5730 goto split_irqchip_unlock; 5731 r = -EEXIST; 5732 if (irqchip_in_kernel(kvm)) 5733 goto split_irqchip_unlock; 5734 if (kvm->created_vcpus) 5735 goto split_irqchip_unlock; 5736 r = kvm_setup_empty_irq_routing(kvm); 5737 if (r) 5738 goto split_irqchip_unlock; 5739 /* Pairs with irqchip_in_kernel. */ 5740 smp_wmb(); 5741 kvm->arch.irqchip_mode = KVM_IRQCHIP_SPLIT; 5742 kvm->arch.nr_reserved_ioapic_pins = cap->args[0]; 5743 r = 0; 5744 split_irqchip_unlock: 5745 mutex_unlock(&kvm->lock); 5746 break; 5747 } 5748 case KVM_CAP_X2APIC_API: 5749 r = -EINVAL; 5750 if (cap->args[0] & ~KVM_X2APIC_API_VALID_FLAGS) 5751 break; 5752 5753 if (cap->args[0] & KVM_X2APIC_API_USE_32BIT_IDS) 5754 kvm->arch.x2apic_format = true; 5755 if (cap->args[0] & KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK) 5756 kvm->arch.x2apic_broadcast_quirk_disabled = true; 5757 5758 r = 0; 5759 break; 5760 case KVM_CAP_X86_DISABLE_EXITS: 5761 r = -EINVAL; 5762 if (cap->args[0] & ~KVM_X86_DISABLE_VALID_EXITS) 5763 break; 5764 5765 if ((cap->args[0] & KVM_X86_DISABLE_EXITS_MWAIT) && 5766 kvm_can_mwait_in_guest()) 5767 kvm->arch.mwait_in_guest = true; 5768 if (cap->args[0] & KVM_X86_DISABLE_EXITS_HLT) 5769 kvm->arch.hlt_in_guest = true; 5770 if (cap->args[0] & KVM_X86_DISABLE_EXITS_PAUSE) 5771 kvm->arch.pause_in_guest = true; 5772 if (cap->args[0] & KVM_X86_DISABLE_EXITS_CSTATE) 5773 kvm->arch.cstate_in_guest = true; 5774 r = 0; 5775 break; 5776 case KVM_CAP_MSR_PLATFORM_INFO: 5777 kvm->arch.guest_can_read_msr_platform_info = cap->args[0]; 5778 r = 0; 5779 break; 5780 case KVM_CAP_EXCEPTION_PAYLOAD: 5781 kvm->arch.exception_payload_enabled = cap->args[0]; 5782 r = 0; 5783 break; 5784 case KVM_CAP_X86_USER_SPACE_MSR: 5785 kvm->arch.user_space_msr_mask = cap->args[0]; 5786 r = 0; 5787 break; 5788 case KVM_CAP_X86_BUS_LOCK_EXIT: 5789 r = -EINVAL; 5790 if (cap->args[0] & ~KVM_BUS_LOCK_DETECTION_VALID_MODE) 5791 break; 5792 5793 if ((cap->args[0] & KVM_BUS_LOCK_DETECTION_OFF) && 5794 (cap->args[0] & KVM_BUS_LOCK_DETECTION_EXIT)) 5795 break; 5796 5797 if (kvm_has_bus_lock_exit && 5798 cap->args[0] & KVM_BUS_LOCK_DETECTION_EXIT) 5799 kvm->arch.bus_lock_detection_enabled = true; 5800 r = 0; 5801 break; 5802 #ifdef CONFIG_X86_SGX_KVM 5803 case KVM_CAP_SGX_ATTRIBUTE: { 5804 unsigned long allowed_attributes = 0; 5805 5806 r = sgx_set_attribute(&allowed_attributes, cap->args[0]); 5807 if (r) 5808 break; 5809 5810 /* KVM only supports the PROVISIONKEY privileged attribute. */ 5811 if ((allowed_attributes & SGX_ATTR_PROVISIONKEY) && 5812 !(allowed_attributes & ~SGX_ATTR_PROVISIONKEY)) 5813 kvm->arch.sgx_provisioning_allowed = true; 5814 else 5815 r = -EINVAL; 5816 break; 5817 } 5818 #endif 5819 case KVM_CAP_VM_COPY_ENC_CONTEXT_FROM: 5820 r = -EINVAL; 5821 if (kvm_x86_ops.vm_copy_enc_context_from) 5822 r = kvm_x86_ops.vm_copy_enc_context_from(kvm, cap->args[0]); 5823 return r; 5824 case KVM_CAP_VM_MOVE_ENC_CONTEXT_FROM: 5825 r = -EINVAL; 5826 if (kvm_x86_ops.vm_move_enc_context_from) 5827 r = kvm_x86_ops.vm_move_enc_context_from( 5828 kvm, cap->args[0]); 5829 return r; 5830 case KVM_CAP_EXIT_HYPERCALL: 5831 if (cap->args[0] & ~KVM_EXIT_HYPERCALL_VALID_MASK) { 5832 r = -EINVAL; 5833 break; 5834 } 5835 kvm->arch.hypercall_exit_enabled = cap->args[0]; 5836 r = 0; 5837 break; 5838 case KVM_CAP_EXIT_ON_EMULATION_FAILURE: 5839 r = -EINVAL; 5840 if (cap->args[0] & ~1) 5841 break; 5842 kvm->arch.exit_on_emulation_error = cap->args[0]; 5843 r = 0; 5844 break; 5845 default: 5846 r = -EINVAL; 5847 break; 5848 } 5849 return r; 5850 } 5851 5852 static struct kvm_x86_msr_filter *kvm_alloc_msr_filter(bool default_allow) 5853 { 5854 struct kvm_x86_msr_filter *msr_filter; 5855 5856 msr_filter = kzalloc(sizeof(*msr_filter), GFP_KERNEL_ACCOUNT); 5857 if (!msr_filter) 5858 return NULL; 5859 5860 msr_filter->default_allow = default_allow; 5861 return msr_filter; 5862 } 5863 5864 static void kvm_free_msr_filter(struct kvm_x86_msr_filter *msr_filter) 5865 { 5866 u32 i; 5867 5868 if (!msr_filter) 5869 return; 5870 5871 for (i = 0; i < msr_filter->count; i++) 5872 kfree(msr_filter->ranges[i].bitmap); 5873 5874 kfree(msr_filter); 5875 } 5876 5877 static int kvm_add_msr_filter(struct kvm_x86_msr_filter *msr_filter, 5878 struct kvm_msr_filter_range *user_range) 5879 { 5880 unsigned long *bitmap = NULL; 5881 size_t bitmap_size; 5882 5883 if (!user_range->nmsrs) 5884 return 0; 5885 5886 if (user_range->flags & ~(KVM_MSR_FILTER_READ | KVM_MSR_FILTER_WRITE)) 5887 return -EINVAL; 5888 5889 if (!user_range->flags) 5890 return -EINVAL; 5891 5892 bitmap_size = BITS_TO_LONGS(user_range->nmsrs) * sizeof(long); 5893 if (!bitmap_size || bitmap_size > KVM_MSR_FILTER_MAX_BITMAP_SIZE) 5894 return -EINVAL; 5895 5896 bitmap = memdup_user((__user u8*)user_range->bitmap, bitmap_size); 5897 if (IS_ERR(bitmap)) 5898 return PTR_ERR(bitmap); 5899 5900 msr_filter->ranges[msr_filter->count] = (struct msr_bitmap_range) { 5901 .flags = user_range->flags, 5902 .base = user_range->base, 5903 .nmsrs = user_range->nmsrs, 5904 .bitmap = bitmap, 5905 }; 5906 5907 msr_filter->count++; 5908 return 0; 5909 } 5910 5911 static int kvm_vm_ioctl_set_msr_filter(struct kvm *kvm, void __user *argp) 5912 { 5913 struct kvm_msr_filter __user *user_msr_filter = argp; 5914 struct kvm_x86_msr_filter *new_filter, *old_filter; 5915 struct kvm_msr_filter filter; 5916 bool default_allow; 5917 bool empty = true; 5918 int r = 0; 5919 u32 i; 5920 5921 if (copy_from_user(&filter, user_msr_filter, sizeof(filter))) 5922 return -EFAULT; 5923 5924 for (i = 0; i < ARRAY_SIZE(filter.ranges); i++) 5925 empty &= !filter.ranges[i].nmsrs; 5926 5927 default_allow = !(filter.flags & KVM_MSR_FILTER_DEFAULT_DENY); 5928 if (empty && !default_allow) 5929 return -EINVAL; 5930 5931 new_filter = kvm_alloc_msr_filter(default_allow); 5932 if (!new_filter) 5933 return -ENOMEM; 5934 5935 for (i = 0; i < ARRAY_SIZE(filter.ranges); i++) { 5936 r = kvm_add_msr_filter(new_filter, &filter.ranges[i]); 5937 if (r) { 5938 kvm_free_msr_filter(new_filter); 5939 return r; 5940 } 5941 } 5942 5943 mutex_lock(&kvm->lock); 5944 5945 /* The per-VM filter is protected by kvm->lock... */ 5946 old_filter = srcu_dereference_check(kvm->arch.msr_filter, &kvm->srcu, 1); 5947 5948 rcu_assign_pointer(kvm->arch.msr_filter, new_filter); 5949 synchronize_srcu(&kvm->srcu); 5950 5951 kvm_free_msr_filter(old_filter); 5952 5953 kvm_make_all_cpus_request(kvm, KVM_REQ_MSR_FILTER_CHANGED); 5954 mutex_unlock(&kvm->lock); 5955 5956 return 0; 5957 } 5958 5959 #ifdef CONFIG_HAVE_KVM_PM_NOTIFIER 5960 static int kvm_arch_suspend_notifier(struct kvm *kvm) 5961 { 5962 struct kvm_vcpu *vcpu; 5963 int i, ret = 0; 5964 5965 mutex_lock(&kvm->lock); 5966 kvm_for_each_vcpu(i, vcpu, kvm) { 5967 if (!vcpu->arch.pv_time_enabled) 5968 continue; 5969 5970 ret = kvm_set_guest_paused(vcpu); 5971 if (ret) { 5972 kvm_err("Failed to pause guest VCPU%d: %d\n", 5973 vcpu->vcpu_id, ret); 5974 break; 5975 } 5976 } 5977 mutex_unlock(&kvm->lock); 5978 5979 return ret ? NOTIFY_BAD : NOTIFY_DONE; 5980 } 5981 5982 int kvm_arch_pm_notifier(struct kvm *kvm, unsigned long state) 5983 { 5984 switch (state) { 5985 case PM_HIBERNATION_PREPARE: 5986 case PM_SUSPEND_PREPARE: 5987 return kvm_arch_suspend_notifier(kvm); 5988 } 5989 5990 return NOTIFY_DONE; 5991 } 5992 #endif /* CONFIG_HAVE_KVM_PM_NOTIFIER */ 5993 5994 static int kvm_vm_ioctl_get_clock(struct kvm *kvm, void __user *argp) 5995 { 5996 struct kvm_clock_data data = { 0 }; 5997 5998 get_kvmclock(kvm, &data); 5999 if (copy_to_user(argp, &data, sizeof(data))) 6000 return -EFAULT; 6001 6002 return 0; 6003 } 6004 6005 static int kvm_vm_ioctl_set_clock(struct kvm *kvm, void __user *argp) 6006 { 6007 struct kvm_arch *ka = &kvm->arch; 6008 struct kvm_clock_data data; 6009 u64 now_raw_ns; 6010 6011 if (copy_from_user(&data, argp, sizeof(data))) 6012 return -EFAULT; 6013 6014 /* 6015 * Only KVM_CLOCK_REALTIME is used, but allow passing the 6016 * result of KVM_GET_CLOCK back to KVM_SET_CLOCK. 6017 */ 6018 if (data.flags & ~KVM_CLOCK_VALID_FLAGS) 6019 return -EINVAL; 6020 6021 kvm_hv_invalidate_tsc_page(kvm); 6022 kvm_start_pvclock_update(kvm); 6023 pvclock_update_vm_gtod_copy(kvm); 6024 6025 /* 6026 * This pairs with kvm_guest_time_update(): when masterclock is 6027 * in use, we use master_kernel_ns + kvmclock_offset to set 6028 * unsigned 'system_time' so if we use get_kvmclock_ns() (which 6029 * is slightly ahead) here we risk going negative on unsigned 6030 * 'system_time' when 'data.clock' is very small. 6031 */ 6032 if (data.flags & KVM_CLOCK_REALTIME) { 6033 u64 now_real_ns = ktime_get_real_ns(); 6034 6035 /* 6036 * Avoid stepping the kvmclock backwards. 6037 */ 6038 if (now_real_ns > data.realtime) 6039 data.clock += now_real_ns - data.realtime; 6040 } 6041 6042 if (ka->use_master_clock) 6043 now_raw_ns = ka->master_kernel_ns; 6044 else 6045 now_raw_ns = get_kvmclock_base_ns(); 6046 ka->kvmclock_offset = data.clock - now_raw_ns; 6047 kvm_end_pvclock_update(kvm); 6048 return 0; 6049 } 6050 6051 long kvm_arch_vm_ioctl(struct file *filp, 6052 unsigned int ioctl, unsigned long arg) 6053 { 6054 struct kvm *kvm = filp->private_data; 6055 void __user *argp = (void __user *)arg; 6056 int r = -ENOTTY; 6057 /* 6058 * This union makes it completely explicit to gcc-3.x 6059 * that these two variables' stack usage should be 6060 * combined, not added together. 6061 */ 6062 union { 6063 struct kvm_pit_state ps; 6064 struct kvm_pit_state2 ps2; 6065 struct kvm_pit_config pit_config; 6066 } u; 6067 6068 switch (ioctl) { 6069 case KVM_SET_TSS_ADDR: 6070 r = kvm_vm_ioctl_set_tss_addr(kvm, arg); 6071 break; 6072 case KVM_SET_IDENTITY_MAP_ADDR: { 6073 u64 ident_addr; 6074 6075 mutex_lock(&kvm->lock); 6076 r = -EINVAL; 6077 if (kvm->created_vcpus) 6078 goto set_identity_unlock; 6079 r = -EFAULT; 6080 if (copy_from_user(&ident_addr, argp, sizeof(ident_addr))) 6081 goto set_identity_unlock; 6082 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr); 6083 set_identity_unlock: 6084 mutex_unlock(&kvm->lock); 6085 break; 6086 } 6087 case KVM_SET_NR_MMU_PAGES: 6088 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg); 6089 break; 6090 case KVM_GET_NR_MMU_PAGES: 6091 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm); 6092 break; 6093 case KVM_CREATE_IRQCHIP: { 6094 mutex_lock(&kvm->lock); 6095 6096 r = -EEXIST; 6097 if (irqchip_in_kernel(kvm)) 6098 goto create_irqchip_unlock; 6099 6100 r = -EINVAL; 6101 if (kvm->created_vcpus) 6102 goto create_irqchip_unlock; 6103 6104 r = kvm_pic_init(kvm); 6105 if (r) 6106 goto create_irqchip_unlock; 6107 6108 r = kvm_ioapic_init(kvm); 6109 if (r) { 6110 kvm_pic_destroy(kvm); 6111 goto create_irqchip_unlock; 6112 } 6113 6114 r = kvm_setup_default_irq_routing(kvm); 6115 if (r) { 6116 kvm_ioapic_destroy(kvm); 6117 kvm_pic_destroy(kvm); 6118 goto create_irqchip_unlock; 6119 } 6120 /* Write kvm->irq_routing before enabling irqchip_in_kernel. */ 6121 smp_wmb(); 6122 kvm->arch.irqchip_mode = KVM_IRQCHIP_KERNEL; 6123 create_irqchip_unlock: 6124 mutex_unlock(&kvm->lock); 6125 break; 6126 } 6127 case KVM_CREATE_PIT: 6128 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY; 6129 goto create_pit; 6130 case KVM_CREATE_PIT2: 6131 r = -EFAULT; 6132 if (copy_from_user(&u.pit_config, argp, 6133 sizeof(struct kvm_pit_config))) 6134 goto out; 6135 create_pit: 6136 mutex_lock(&kvm->lock); 6137 r = -EEXIST; 6138 if (kvm->arch.vpit) 6139 goto create_pit_unlock; 6140 r = -ENOMEM; 6141 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags); 6142 if (kvm->arch.vpit) 6143 r = 0; 6144 create_pit_unlock: 6145 mutex_unlock(&kvm->lock); 6146 break; 6147 case KVM_GET_IRQCHIP: { 6148 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */ 6149 struct kvm_irqchip *chip; 6150 6151 chip = memdup_user(argp, sizeof(*chip)); 6152 if (IS_ERR(chip)) { 6153 r = PTR_ERR(chip); 6154 goto out; 6155 } 6156 6157 r = -ENXIO; 6158 if (!irqchip_kernel(kvm)) 6159 goto get_irqchip_out; 6160 r = kvm_vm_ioctl_get_irqchip(kvm, chip); 6161 if (r) 6162 goto get_irqchip_out; 6163 r = -EFAULT; 6164 if (copy_to_user(argp, chip, sizeof(*chip))) 6165 goto get_irqchip_out; 6166 r = 0; 6167 get_irqchip_out: 6168 kfree(chip); 6169 break; 6170 } 6171 case KVM_SET_IRQCHIP: { 6172 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */ 6173 struct kvm_irqchip *chip; 6174 6175 chip = memdup_user(argp, sizeof(*chip)); 6176 if (IS_ERR(chip)) { 6177 r = PTR_ERR(chip); 6178 goto out; 6179 } 6180 6181 r = -ENXIO; 6182 if (!irqchip_kernel(kvm)) 6183 goto set_irqchip_out; 6184 r = kvm_vm_ioctl_set_irqchip(kvm, chip); 6185 set_irqchip_out: 6186 kfree(chip); 6187 break; 6188 } 6189 case KVM_GET_PIT: { 6190 r = -EFAULT; 6191 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state))) 6192 goto out; 6193 r = -ENXIO; 6194 if (!kvm->arch.vpit) 6195 goto out; 6196 r = kvm_vm_ioctl_get_pit(kvm, &u.ps); 6197 if (r) 6198 goto out; 6199 r = -EFAULT; 6200 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state))) 6201 goto out; 6202 r = 0; 6203 break; 6204 } 6205 case KVM_SET_PIT: { 6206 r = -EFAULT; 6207 if (copy_from_user(&u.ps, argp, sizeof(u.ps))) 6208 goto out; 6209 mutex_lock(&kvm->lock); 6210 r = -ENXIO; 6211 if (!kvm->arch.vpit) 6212 goto set_pit_out; 6213 r = kvm_vm_ioctl_set_pit(kvm, &u.ps); 6214 set_pit_out: 6215 mutex_unlock(&kvm->lock); 6216 break; 6217 } 6218 case KVM_GET_PIT2: { 6219 r = -ENXIO; 6220 if (!kvm->arch.vpit) 6221 goto out; 6222 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2); 6223 if (r) 6224 goto out; 6225 r = -EFAULT; 6226 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2))) 6227 goto out; 6228 r = 0; 6229 break; 6230 } 6231 case KVM_SET_PIT2: { 6232 r = -EFAULT; 6233 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2))) 6234 goto out; 6235 mutex_lock(&kvm->lock); 6236 r = -ENXIO; 6237 if (!kvm->arch.vpit) 6238 goto set_pit2_out; 6239 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2); 6240 set_pit2_out: 6241 mutex_unlock(&kvm->lock); 6242 break; 6243 } 6244 case KVM_REINJECT_CONTROL: { 6245 struct kvm_reinject_control control; 6246 r = -EFAULT; 6247 if (copy_from_user(&control, argp, sizeof(control))) 6248 goto out; 6249 r = -ENXIO; 6250 if (!kvm->arch.vpit) 6251 goto out; 6252 r = kvm_vm_ioctl_reinject(kvm, &control); 6253 break; 6254 } 6255 case KVM_SET_BOOT_CPU_ID: 6256 r = 0; 6257 mutex_lock(&kvm->lock); 6258 if (kvm->created_vcpus) 6259 r = -EBUSY; 6260 else 6261 kvm->arch.bsp_vcpu_id = arg; 6262 mutex_unlock(&kvm->lock); 6263 break; 6264 #ifdef CONFIG_KVM_XEN 6265 case KVM_XEN_HVM_CONFIG: { 6266 struct kvm_xen_hvm_config xhc; 6267 r = -EFAULT; 6268 if (copy_from_user(&xhc, argp, sizeof(xhc))) 6269 goto out; 6270 r = kvm_xen_hvm_config(kvm, &xhc); 6271 break; 6272 } 6273 case KVM_XEN_HVM_GET_ATTR: { 6274 struct kvm_xen_hvm_attr xha; 6275 6276 r = -EFAULT; 6277 if (copy_from_user(&xha, argp, sizeof(xha))) 6278 goto out; 6279 r = kvm_xen_hvm_get_attr(kvm, &xha); 6280 if (!r && copy_to_user(argp, &xha, sizeof(xha))) 6281 r = -EFAULT; 6282 break; 6283 } 6284 case KVM_XEN_HVM_SET_ATTR: { 6285 struct kvm_xen_hvm_attr xha; 6286 6287 r = -EFAULT; 6288 if (copy_from_user(&xha, argp, sizeof(xha))) 6289 goto out; 6290 r = kvm_xen_hvm_set_attr(kvm, &xha); 6291 break; 6292 } 6293 #endif 6294 case KVM_SET_CLOCK: 6295 r = kvm_vm_ioctl_set_clock(kvm, argp); 6296 break; 6297 case KVM_GET_CLOCK: 6298 r = kvm_vm_ioctl_get_clock(kvm, argp); 6299 break; 6300 case KVM_MEMORY_ENCRYPT_OP: { 6301 r = -ENOTTY; 6302 if (kvm_x86_ops.mem_enc_op) 6303 r = static_call(kvm_x86_mem_enc_op)(kvm, argp); 6304 break; 6305 } 6306 case KVM_MEMORY_ENCRYPT_REG_REGION: { 6307 struct kvm_enc_region region; 6308 6309 r = -EFAULT; 6310 if (copy_from_user(®ion, argp, sizeof(region))) 6311 goto out; 6312 6313 r = -ENOTTY; 6314 if (kvm_x86_ops.mem_enc_reg_region) 6315 r = static_call(kvm_x86_mem_enc_reg_region)(kvm, ®ion); 6316 break; 6317 } 6318 case KVM_MEMORY_ENCRYPT_UNREG_REGION: { 6319 struct kvm_enc_region region; 6320 6321 r = -EFAULT; 6322 if (copy_from_user(®ion, argp, sizeof(region))) 6323 goto out; 6324 6325 r = -ENOTTY; 6326 if (kvm_x86_ops.mem_enc_unreg_region) 6327 r = static_call(kvm_x86_mem_enc_unreg_region)(kvm, ®ion); 6328 break; 6329 } 6330 case KVM_HYPERV_EVENTFD: { 6331 struct kvm_hyperv_eventfd hvevfd; 6332 6333 r = -EFAULT; 6334 if (copy_from_user(&hvevfd, argp, sizeof(hvevfd))) 6335 goto out; 6336 r = kvm_vm_ioctl_hv_eventfd(kvm, &hvevfd); 6337 break; 6338 } 6339 case KVM_SET_PMU_EVENT_FILTER: 6340 r = kvm_vm_ioctl_set_pmu_event_filter(kvm, argp); 6341 break; 6342 case KVM_X86_SET_MSR_FILTER: 6343 r = kvm_vm_ioctl_set_msr_filter(kvm, argp); 6344 break; 6345 default: 6346 r = -ENOTTY; 6347 } 6348 out: 6349 return r; 6350 } 6351 6352 static void kvm_init_msr_list(void) 6353 { 6354 struct x86_pmu_capability x86_pmu; 6355 u32 dummy[2]; 6356 unsigned i; 6357 6358 BUILD_BUG_ON_MSG(INTEL_PMC_MAX_FIXED != 4, 6359 "Please update the fixed PMCs in msrs_to_saved_all[]"); 6360 6361 perf_get_x86_pmu_capability(&x86_pmu); 6362 6363 num_msrs_to_save = 0; 6364 num_emulated_msrs = 0; 6365 num_msr_based_features = 0; 6366 6367 for (i = 0; i < ARRAY_SIZE(msrs_to_save_all); i++) { 6368 if (rdmsr_safe(msrs_to_save_all[i], &dummy[0], &dummy[1]) < 0) 6369 continue; 6370 6371 /* 6372 * Even MSRs that are valid in the host may not be exposed 6373 * to the guests in some cases. 6374 */ 6375 switch (msrs_to_save_all[i]) { 6376 case MSR_IA32_BNDCFGS: 6377 if (!kvm_mpx_supported()) 6378 continue; 6379 break; 6380 case MSR_TSC_AUX: 6381 if (!kvm_cpu_cap_has(X86_FEATURE_RDTSCP) && 6382 !kvm_cpu_cap_has(X86_FEATURE_RDPID)) 6383 continue; 6384 break; 6385 case MSR_IA32_UMWAIT_CONTROL: 6386 if (!kvm_cpu_cap_has(X86_FEATURE_WAITPKG)) 6387 continue; 6388 break; 6389 case MSR_IA32_RTIT_CTL: 6390 case MSR_IA32_RTIT_STATUS: 6391 if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT)) 6392 continue; 6393 break; 6394 case MSR_IA32_RTIT_CR3_MATCH: 6395 if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT) || 6396 !intel_pt_validate_hw_cap(PT_CAP_cr3_filtering)) 6397 continue; 6398 break; 6399 case MSR_IA32_RTIT_OUTPUT_BASE: 6400 case MSR_IA32_RTIT_OUTPUT_MASK: 6401 if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT) || 6402 (!intel_pt_validate_hw_cap(PT_CAP_topa_output) && 6403 !intel_pt_validate_hw_cap(PT_CAP_single_range_output))) 6404 continue; 6405 break; 6406 case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B: 6407 if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT) || 6408 msrs_to_save_all[i] - MSR_IA32_RTIT_ADDR0_A >= 6409 intel_pt_validate_hw_cap(PT_CAP_num_address_ranges) * 2) 6410 continue; 6411 break; 6412 case MSR_ARCH_PERFMON_PERFCTR0 ... MSR_ARCH_PERFMON_PERFCTR0 + 17: 6413 if (msrs_to_save_all[i] - MSR_ARCH_PERFMON_PERFCTR0 >= 6414 min(INTEL_PMC_MAX_GENERIC, x86_pmu.num_counters_gp)) 6415 continue; 6416 break; 6417 case MSR_ARCH_PERFMON_EVENTSEL0 ... MSR_ARCH_PERFMON_EVENTSEL0 + 17: 6418 if (msrs_to_save_all[i] - MSR_ARCH_PERFMON_EVENTSEL0 >= 6419 min(INTEL_PMC_MAX_GENERIC, x86_pmu.num_counters_gp)) 6420 continue; 6421 break; 6422 default: 6423 break; 6424 } 6425 6426 msrs_to_save[num_msrs_to_save++] = msrs_to_save_all[i]; 6427 } 6428 6429 for (i = 0; i < ARRAY_SIZE(emulated_msrs_all); i++) { 6430 if (!static_call(kvm_x86_has_emulated_msr)(NULL, emulated_msrs_all[i])) 6431 continue; 6432 6433 emulated_msrs[num_emulated_msrs++] = emulated_msrs_all[i]; 6434 } 6435 6436 for (i = 0; i < ARRAY_SIZE(msr_based_features_all); i++) { 6437 struct kvm_msr_entry msr; 6438 6439 msr.index = msr_based_features_all[i]; 6440 if (kvm_get_msr_feature(&msr)) 6441 continue; 6442 6443 msr_based_features[num_msr_based_features++] = msr_based_features_all[i]; 6444 } 6445 } 6446 6447 static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len, 6448 const void *v) 6449 { 6450 int handled = 0; 6451 int n; 6452 6453 do { 6454 n = min(len, 8); 6455 if (!(lapic_in_kernel(vcpu) && 6456 !kvm_iodevice_write(vcpu, &vcpu->arch.apic->dev, addr, n, v)) 6457 && kvm_io_bus_write(vcpu, KVM_MMIO_BUS, addr, n, v)) 6458 break; 6459 handled += n; 6460 addr += n; 6461 len -= n; 6462 v += n; 6463 } while (len); 6464 6465 return handled; 6466 } 6467 6468 static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v) 6469 { 6470 int handled = 0; 6471 int n; 6472 6473 do { 6474 n = min(len, 8); 6475 if (!(lapic_in_kernel(vcpu) && 6476 !kvm_iodevice_read(vcpu, &vcpu->arch.apic->dev, 6477 addr, n, v)) 6478 && kvm_io_bus_read(vcpu, KVM_MMIO_BUS, addr, n, v)) 6479 break; 6480 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, v); 6481 handled += n; 6482 addr += n; 6483 len -= n; 6484 v += n; 6485 } while (len); 6486 6487 return handled; 6488 } 6489 6490 static void kvm_set_segment(struct kvm_vcpu *vcpu, 6491 struct kvm_segment *var, int seg) 6492 { 6493 static_call(kvm_x86_set_segment)(vcpu, var, seg); 6494 } 6495 6496 void kvm_get_segment(struct kvm_vcpu *vcpu, 6497 struct kvm_segment *var, int seg) 6498 { 6499 static_call(kvm_x86_get_segment)(vcpu, var, seg); 6500 } 6501 6502 gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access, 6503 struct x86_exception *exception) 6504 { 6505 gpa_t t_gpa; 6506 6507 BUG_ON(!mmu_is_nested(vcpu)); 6508 6509 /* NPT walks are always user-walks */ 6510 access |= PFERR_USER_MASK; 6511 t_gpa = vcpu->arch.mmu->gva_to_gpa(vcpu, gpa, access, exception); 6512 6513 return t_gpa; 6514 } 6515 6516 gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva, 6517 struct x86_exception *exception) 6518 { 6519 u32 access = (static_call(kvm_x86_get_cpl)(vcpu) == 3) ? PFERR_USER_MASK : 0; 6520 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception); 6521 } 6522 EXPORT_SYMBOL_GPL(kvm_mmu_gva_to_gpa_read); 6523 6524 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva, 6525 struct x86_exception *exception) 6526 { 6527 u32 access = (static_call(kvm_x86_get_cpl)(vcpu) == 3) ? PFERR_USER_MASK : 0; 6528 access |= PFERR_FETCH_MASK; 6529 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception); 6530 } 6531 6532 gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva, 6533 struct x86_exception *exception) 6534 { 6535 u32 access = (static_call(kvm_x86_get_cpl)(vcpu) == 3) ? PFERR_USER_MASK : 0; 6536 access |= PFERR_WRITE_MASK; 6537 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception); 6538 } 6539 EXPORT_SYMBOL_GPL(kvm_mmu_gva_to_gpa_write); 6540 6541 /* uses this to access any guest's mapped memory without checking CPL */ 6542 gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva, 6543 struct x86_exception *exception) 6544 { 6545 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception); 6546 } 6547 6548 static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes, 6549 struct kvm_vcpu *vcpu, u32 access, 6550 struct x86_exception *exception) 6551 { 6552 void *data = val; 6553 int r = X86EMUL_CONTINUE; 6554 6555 while (bytes) { 6556 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access, 6557 exception); 6558 unsigned offset = addr & (PAGE_SIZE-1); 6559 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset); 6560 int ret; 6561 6562 if (gpa == UNMAPPED_GVA) 6563 return X86EMUL_PROPAGATE_FAULT; 6564 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, data, 6565 offset, toread); 6566 if (ret < 0) { 6567 r = X86EMUL_IO_NEEDED; 6568 goto out; 6569 } 6570 6571 bytes -= toread; 6572 data += toread; 6573 addr += toread; 6574 } 6575 out: 6576 return r; 6577 } 6578 6579 /* used for instruction fetching */ 6580 static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt, 6581 gva_t addr, void *val, unsigned int bytes, 6582 struct x86_exception *exception) 6583 { 6584 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 6585 u32 access = (static_call(kvm_x86_get_cpl)(vcpu) == 3) ? PFERR_USER_MASK : 0; 6586 unsigned offset; 6587 int ret; 6588 6589 /* Inline kvm_read_guest_virt_helper for speed. */ 6590 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access|PFERR_FETCH_MASK, 6591 exception); 6592 if (unlikely(gpa == UNMAPPED_GVA)) 6593 return X86EMUL_PROPAGATE_FAULT; 6594 6595 offset = addr & (PAGE_SIZE-1); 6596 if (WARN_ON(offset + bytes > PAGE_SIZE)) 6597 bytes = (unsigned)PAGE_SIZE - offset; 6598 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, val, 6599 offset, bytes); 6600 if (unlikely(ret < 0)) 6601 return X86EMUL_IO_NEEDED; 6602 6603 return X86EMUL_CONTINUE; 6604 } 6605 6606 int kvm_read_guest_virt(struct kvm_vcpu *vcpu, 6607 gva_t addr, void *val, unsigned int bytes, 6608 struct x86_exception *exception) 6609 { 6610 u32 access = (static_call(kvm_x86_get_cpl)(vcpu) == 3) ? PFERR_USER_MASK : 0; 6611 6612 /* 6613 * FIXME: this should call handle_emulation_failure if X86EMUL_IO_NEEDED 6614 * is returned, but our callers are not ready for that and they blindly 6615 * call kvm_inject_page_fault. Ensure that they at least do not leak 6616 * uninitialized kernel stack memory into cr2 and error code. 6617 */ 6618 memset(exception, 0, sizeof(*exception)); 6619 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access, 6620 exception); 6621 } 6622 EXPORT_SYMBOL_GPL(kvm_read_guest_virt); 6623 6624 static int emulator_read_std(struct x86_emulate_ctxt *ctxt, 6625 gva_t addr, void *val, unsigned int bytes, 6626 struct x86_exception *exception, bool system) 6627 { 6628 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 6629 u32 access = 0; 6630 6631 if (!system && static_call(kvm_x86_get_cpl)(vcpu) == 3) 6632 access |= PFERR_USER_MASK; 6633 6634 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access, exception); 6635 } 6636 6637 static int kvm_read_guest_phys_system(struct x86_emulate_ctxt *ctxt, 6638 unsigned long addr, void *val, unsigned int bytes) 6639 { 6640 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 6641 int r = kvm_vcpu_read_guest(vcpu, addr, val, bytes); 6642 6643 return r < 0 ? X86EMUL_IO_NEEDED : X86EMUL_CONTINUE; 6644 } 6645 6646 static int kvm_write_guest_virt_helper(gva_t addr, void *val, unsigned int bytes, 6647 struct kvm_vcpu *vcpu, u32 access, 6648 struct x86_exception *exception) 6649 { 6650 void *data = val; 6651 int r = X86EMUL_CONTINUE; 6652 6653 while (bytes) { 6654 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, 6655 access, 6656 exception); 6657 unsigned offset = addr & (PAGE_SIZE-1); 6658 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset); 6659 int ret; 6660 6661 if (gpa == UNMAPPED_GVA) 6662 return X86EMUL_PROPAGATE_FAULT; 6663 ret = kvm_vcpu_write_guest(vcpu, gpa, data, towrite); 6664 if (ret < 0) { 6665 r = X86EMUL_IO_NEEDED; 6666 goto out; 6667 } 6668 6669 bytes -= towrite; 6670 data += towrite; 6671 addr += towrite; 6672 } 6673 out: 6674 return r; 6675 } 6676 6677 static int emulator_write_std(struct x86_emulate_ctxt *ctxt, gva_t addr, void *val, 6678 unsigned int bytes, struct x86_exception *exception, 6679 bool system) 6680 { 6681 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 6682 u32 access = PFERR_WRITE_MASK; 6683 6684 if (!system && static_call(kvm_x86_get_cpl)(vcpu) == 3) 6685 access |= PFERR_USER_MASK; 6686 6687 return kvm_write_guest_virt_helper(addr, val, bytes, vcpu, 6688 access, exception); 6689 } 6690 6691 int kvm_write_guest_virt_system(struct kvm_vcpu *vcpu, gva_t addr, void *val, 6692 unsigned int bytes, struct x86_exception *exception) 6693 { 6694 /* kvm_write_guest_virt_system can pull in tons of pages. */ 6695 vcpu->arch.l1tf_flush_l1d = true; 6696 6697 return kvm_write_guest_virt_helper(addr, val, bytes, vcpu, 6698 PFERR_WRITE_MASK, exception); 6699 } 6700 EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system); 6701 6702 int handle_ud(struct kvm_vcpu *vcpu) 6703 { 6704 static const char kvm_emulate_prefix[] = { __KVM_EMULATE_PREFIX }; 6705 int emul_type = EMULTYPE_TRAP_UD; 6706 char sig[5]; /* ud2; .ascii "kvm" */ 6707 struct x86_exception e; 6708 6709 if (unlikely(!static_call(kvm_x86_can_emulate_instruction)(vcpu, NULL, 0))) 6710 return 1; 6711 6712 if (force_emulation_prefix && 6713 kvm_read_guest_virt(vcpu, kvm_get_linear_rip(vcpu), 6714 sig, sizeof(sig), &e) == 0 && 6715 memcmp(sig, kvm_emulate_prefix, sizeof(sig)) == 0) { 6716 kvm_rip_write(vcpu, kvm_rip_read(vcpu) + sizeof(sig)); 6717 emul_type = EMULTYPE_TRAP_UD_FORCED; 6718 } 6719 6720 return kvm_emulate_instruction(vcpu, emul_type); 6721 } 6722 EXPORT_SYMBOL_GPL(handle_ud); 6723 6724 static int vcpu_is_mmio_gpa(struct kvm_vcpu *vcpu, unsigned long gva, 6725 gpa_t gpa, bool write) 6726 { 6727 /* For APIC access vmexit */ 6728 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE) 6729 return 1; 6730 6731 if (vcpu_match_mmio_gpa(vcpu, gpa)) { 6732 trace_vcpu_match_mmio(gva, gpa, write, true); 6733 return 1; 6734 } 6735 6736 return 0; 6737 } 6738 6739 static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva, 6740 gpa_t *gpa, struct x86_exception *exception, 6741 bool write) 6742 { 6743 u32 access = ((static_call(kvm_x86_get_cpl)(vcpu) == 3) ? PFERR_USER_MASK : 0) 6744 | (write ? PFERR_WRITE_MASK : 0); 6745 6746 /* 6747 * currently PKRU is only applied to ept enabled guest so 6748 * there is no pkey in EPT page table for L1 guest or EPT 6749 * shadow page table for L2 guest. 6750 */ 6751 if (vcpu_match_mmio_gva(vcpu, gva) && (!is_paging(vcpu) || 6752 !permission_fault(vcpu, vcpu->arch.walk_mmu, 6753 vcpu->arch.mmio_access, 0, access))) { 6754 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT | 6755 (gva & (PAGE_SIZE - 1)); 6756 trace_vcpu_match_mmio(gva, *gpa, write, false); 6757 return 1; 6758 } 6759 6760 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception); 6761 6762 if (*gpa == UNMAPPED_GVA) 6763 return -1; 6764 6765 return vcpu_is_mmio_gpa(vcpu, gva, *gpa, write); 6766 } 6767 6768 int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa, 6769 const void *val, int bytes) 6770 { 6771 int ret; 6772 6773 ret = kvm_vcpu_write_guest(vcpu, gpa, val, bytes); 6774 if (ret < 0) 6775 return 0; 6776 kvm_page_track_write(vcpu, gpa, val, bytes); 6777 return 1; 6778 } 6779 6780 struct read_write_emulator_ops { 6781 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val, 6782 int bytes); 6783 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa, 6784 void *val, int bytes); 6785 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa, 6786 int bytes, void *val); 6787 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa, 6788 void *val, int bytes); 6789 bool write; 6790 }; 6791 6792 static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes) 6793 { 6794 if (vcpu->mmio_read_completed) { 6795 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes, 6796 vcpu->mmio_fragments[0].gpa, val); 6797 vcpu->mmio_read_completed = 0; 6798 return 1; 6799 } 6800 6801 return 0; 6802 } 6803 6804 static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa, 6805 void *val, int bytes) 6806 { 6807 return !kvm_vcpu_read_guest(vcpu, gpa, val, bytes); 6808 } 6809 6810 static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa, 6811 void *val, int bytes) 6812 { 6813 return emulator_write_phys(vcpu, gpa, val, bytes); 6814 } 6815 6816 static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val) 6817 { 6818 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, val); 6819 return vcpu_mmio_write(vcpu, gpa, bytes, val); 6820 } 6821 6822 static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, 6823 void *val, int bytes) 6824 { 6825 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, NULL); 6826 return X86EMUL_IO_NEEDED; 6827 } 6828 6829 static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, 6830 void *val, int bytes) 6831 { 6832 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0]; 6833 6834 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len)); 6835 return X86EMUL_CONTINUE; 6836 } 6837 6838 static const struct read_write_emulator_ops read_emultor = { 6839 .read_write_prepare = read_prepare, 6840 .read_write_emulate = read_emulate, 6841 .read_write_mmio = vcpu_mmio_read, 6842 .read_write_exit_mmio = read_exit_mmio, 6843 }; 6844 6845 static const struct read_write_emulator_ops write_emultor = { 6846 .read_write_emulate = write_emulate, 6847 .read_write_mmio = write_mmio, 6848 .read_write_exit_mmio = write_exit_mmio, 6849 .write = true, 6850 }; 6851 6852 static int emulator_read_write_onepage(unsigned long addr, void *val, 6853 unsigned int bytes, 6854 struct x86_exception *exception, 6855 struct kvm_vcpu *vcpu, 6856 const struct read_write_emulator_ops *ops) 6857 { 6858 gpa_t gpa; 6859 int handled, ret; 6860 bool write = ops->write; 6861 struct kvm_mmio_fragment *frag; 6862 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt; 6863 6864 /* 6865 * If the exit was due to a NPF we may already have a GPA. 6866 * If the GPA is present, use it to avoid the GVA to GPA table walk. 6867 * Note, this cannot be used on string operations since string 6868 * operation using rep will only have the initial GPA from the NPF 6869 * occurred. 6870 */ 6871 if (ctxt->gpa_available && emulator_can_use_gpa(ctxt) && 6872 (addr & ~PAGE_MASK) == (ctxt->gpa_val & ~PAGE_MASK)) { 6873 gpa = ctxt->gpa_val; 6874 ret = vcpu_is_mmio_gpa(vcpu, addr, gpa, write); 6875 } else { 6876 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write); 6877 if (ret < 0) 6878 return X86EMUL_PROPAGATE_FAULT; 6879 } 6880 6881 if (!ret && ops->read_write_emulate(vcpu, gpa, val, bytes)) 6882 return X86EMUL_CONTINUE; 6883 6884 /* 6885 * Is this MMIO handled locally? 6886 */ 6887 handled = ops->read_write_mmio(vcpu, gpa, bytes, val); 6888 if (handled == bytes) 6889 return X86EMUL_CONTINUE; 6890 6891 gpa += handled; 6892 bytes -= handled; 6893 val += handled; 6894 6895 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS); 6896 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++]; 6897 frag->gpa = gpa; 6898 frag->data = val; 6899 frag->len = bytes; 6900 return X86EMUL_CONTINUE; 6901 } 6902 6903 static int emulator_read_write(struct x86_emulate_ctxt *ctxt, 6904 unsigned long addr, 6905 void *val, unsigned int bytes, 6906 struct x86_exception *exception, 6907 const struct read_write_emulator_ops *ops) 6908 { 6909 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 6910 gpa_t gpa; 6911 int rc; 6912 6913 if (ops->read_write_prepare && 6914 ops->read_write_prepare(vcpu, val, bytes)) 6915 return X86EMUL_CONTINUE; 6916 6917 vcpu->mmio_nr_fragments = 0; 6918 6919 /* Crossing a page boundary? */ 6920 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) { 6921 int now; 6922 6923 now = -addr & ~PAGE_MASK; 6924 rc = emulator_read_write_onepage(addr, val, now, exception, 6925 vcpu, ops); 6926 6927 if (rc != X86EMUL_CONTINUE) 6928 return rc; 6929 addr += now; 6930 if (ctxt->mode != X86EMUL_MODE_PROT64) 6931 addr = (u32)addr; 6932 val += now; 6933 bytes -= now; 6934 } 6935 6936 rc = emulator_read_write_onepage(addr, val, bytes, exception, 6937 vcpu, ops); 6938 if (rc != X86EMUL_CONTINUE) 6939 return rc; 6940 6941 if (!vcpu->mmio_nr_fragments) 6942 return rc; 6943 6944 gpa = vcpu->mmio_fragments[0].gpa; 6945 6946 vcpu->mmio_needed = 1; 6947 vcpu->mmio_cur_fragment = 0; 6948 6949 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len); 6950 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write; 6951 vcpu->run->exit_reason = KVM_EXIT_MMIO; 6952 vcpu->run->mmio.phys_addr = gpa; 6953 6954 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes); 6955 } 6956 6957 static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt, 6958 unsigned long addr, 6959 void *val, 6960 unsigned int bytes, 6961 struct x86_exception *exception) 6962 { 6963 return emulator_read_write(ctxt, addr, val, bytes, 6964 exception, &read_emultor); 6965 } 6966 6967 static int emulator_write_emulated(struct x86_emulate_ctxt *ctxt, 6968 unsigned long addr, 6969 const void *val, 6970 unsigned int bytes, 6971 struct x86_exception *exception) 6972 { 6973 return emulator_read_write(ctxt, addr, (void *)val, bytes, 6974 exception, &write_emultor); 6975 } 6976 6977 #define CMPXCHG_TYPE(t, ptr, old, new) \ 6978 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old)) 6979 6980 #ifdef CONFIG_X86_64 6981 # define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new) 6982 #else 6983 # define CMPXCHG64(ptr, old, new) \ 6984 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old)) 6985 #endif 6986 6987 static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt, 6988 unsigned long addr, 6989 const void *old, 6990 const void *new, 6991 unsigned int bytes, 6992 struct x86_exception *exception) 6993 { 6994 struct kvm_host_map map; 6995 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 6996 u64 page_line_mask; 6997 gpa_t gpa; 6998 char *kaddr; 6999 bool exchanged; 7000 7001 /* guests cmpxchg8b have to be emulated atomically */ 7002 if (bytes > 8 || (bytes & (bytes - 1))) 7003 goto emul_write; 7004 7005 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL); 7006 7007 if (gpa == UNMAPPED_GVA || 7008 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE) 7009 goto emul_write; 7010 7011 /* 7012 * Emulate the atomic as a straight write to avoid #AC if SLD is 7013 * enabled in the host and the access splits a cache line. 7014 */ 7015 if (boot_cpu_has(X86_FEATURE_SPLIT_LOCK_DETECT)) 7016 page_line_mask = ~(cache_line_size() - 1); 7017 else 7018 page_line_mask = PAGE_MASK; 7019 7020 if (((gpa + bytes - 1) & page_line_mask) != (gpa & page_line_mask)) 7021 goto emul_write; 7022 7023 if (kvm_vcpu_map(vcpu, gpa_to_gfn(gpa), &map)) 7024 goto emul_write; 7025 7026 kaddr = map.hva + offset_in_page(gpa); 7027 7028 switch (bytes) { 7029 case 1: 7030 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new); 7031 break; 7032 case 2: 7033 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new); 7034 break; 7035 case 4: 7036 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new); 7037 break; 7038 case 8: 7039 exchanged = CMPXCHG64(kaddr, old, new); 7040 break; 7041 default: 7042 BUG(); 7043 } 7044 7045 kvm_vcpu_unmap(vcpu, &map, true); 7046 7047 if (!exchanged) 7048 return X86EMUL_CMPXCHG_FAILED; 7049 7050 kvm_page_track_write(vcpu, gpa, new, bytes); 7051 7052 return X86EMUL_CONTINUE; 7053 7054 emul_write: 7055 printk_once(KERN_WARNING "kvm: emulating exchange as write\n"); 7056 7057 return emulator_write_emulated(ctxt, addr, new, bytes, exception); 7058 } 7059 7060 static int kernel_pio(struct kvm_vcpu *vcpu, void *pd) 7061 { 7062 int r = 0, i; 7063 7064 for (i = 0; i < vcpu->arch.pio.count; i++) { 7065 if (vcpu->arch.pio.in) 7066 r = kvm_io_bus_read(vcpu, KVM_PIO_BUS, vcpu->arch.pio.port, 7067 vcpu->arch.pio.size, pd); 7068 else 7069 r = kvm_io_bus_write(vcpu, KVM_PIO_BUS, 7070 vcpu->arch.pio.port, vcpu->arch.pio.size, 7071 pd); 7072 if (r) 7073 break; 7074 pd += vcpu->arch.pio.size; 7075 } 7076 return r; 7077 } 7078 7079 static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size, 7080 unsigned short port, 7081 unsigned int count, bool in) 7082 { 7083 vcpu->arch.pio.port = port; 7084 vcpu->arch.pio.in = in; 7085 vcpu->arch.pio.count = count; 7086 vcpu->arch.pio.size = size; 7087 7088 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) 7089 return 1; 7090 7091 vcpu->run->exit_reason = KVM_EXIT_IO; 7092 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT; 7093 vcpu->run->io.size = size; 7094 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE; 7095 vcpu->run->io.count = count; 7096 vcpu->run->io.port = port; 7097 7098 return 0; 7099 } 7100 7101 static int __emulator_pio_in(struct kvm_vcpu *vcpu, int size, 7102 unsigned short port, unsigned int count) 7103 { 7104 WARN_ON(vcpu->arch.pio.count); 7105 memset(vcpu->arch.pio_data, 0, size * count); 7106 return emulator_pio_in_out(vcpu, size, port, count, true); 7107 } 7108 7109 static void complete_emulator_pio_in(struct kvm_vcpu *vcpu, void *val) 7110 { 7111 int size = vcpu->arch.pio.size; 7112 unsigned count = vcpu->arch.pio.count; 7113 memcpy(val, vcpu->arch.pio_data, size * count); 7114 trace_kvm_pio(KVM_PIO_IN, vcpu->arch.pio.port, size, count, vcpu->arch.pio_data); 7115 vcpu->arch.pio.count = 0; 7116 } 7117 7118 static int emulator_pio_in(struct kvm_vcpu *vcpu, int size, 7119 unsigned short port, void *val, unsigned int count) 7120 { 7121 if (vcpu->arch.pio.count) { 7122 /* Complete previous iteration. */ 7123 } else { 7124 int r = __emulator_pio_in(vcpu, size, port, count); 7125 if (!r) 7126 return r; 7127 7128 /* Results already available, fall through. */ 7129 } 7130 7131 WARN_ON(count != vcpu->arch.pio.count); 7132 complete_emulator_pio_in(vcpu, val); 7133 return 1; 7134 } 7135 7136 static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt, 7137 int size, unsigned short port, void *val, 7138 unsigned int count) 7139 { 7140 return emulator_pio_in(emul_to_vcpu(ctxt), size, port, val, count); 7141 7142 } 7143 7144 static int emulator_pio_out(struct kvm_vcpu *vcpu, int size, 7145 unsigned short port, const void *val, 7146 unsigned int count) 7147 { 7148 int ret; 7149 7150 memcpy(vcpu->arch.pio_data, val, size * count); 7151 trace_kvm_pio(KVM_PIO_OUT, port, size, count, vcpu->arch.pio_data); 7152 ret = emulator_pio_in_out(vcpu, size, port, count, false); 7153 if (ret) 7154 vcpu->arch.pio.count = 0; 7155 7156 return ret; 7157 } 7158 7159 static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt, 7160 int size, unsigned short port, 7161 const void *val, unsigned int count) 7162 { 7163 return emulator_pio_out(emul_to_vcpu(ctxt), size, port, val, count); 7164 } 7165 7166 static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg) 7167 { 7168 return static_call(kvm_x86_get_segment_base)(vcpu, seg); 7169 } 7170 7171 static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address) 7172 { 7173 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address); 7174 } 7175 7176 static int kvm_emulate_wbinvd_noskip(struct kvm_vcpu *vcpu) 7177 { 7178 if (!need_emulate_wbinvd(vcpu)) 7179 return X86EMUL_CONTINUE; 7180 7181 if (static_call(kvm_x86_has_wbinvd_exit)()) { 7182 int cpu = get_cpu(); 7183 7184 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask); 7185 on_each_cpu_mask(vcpu->arch.wbinvd_dirty_mask, 7186 wbinvd_ipi, NULL, 1); 7187 put_cpu(); 7188 cpumask_clear(vcpu->arch.wbinvd_dirty_mask); 7189 } else 7190 wbinvd(); 7191 return X86EMUL_CONTINUE; 7192 } 7193 7194 int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu) 7195 { 7196 kvm_emulate_wbinvd_noskip(vcpu); 7197 return kvm_skip_emulated_instruction(vcpu); 7198 } 7199 EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd); 7200 7201 7202 7203 static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt) 7204 { 7205 kvm_emulate_wbinvd_noskip(emul_to_vcpu(ctxt)); 7206 } 7207 7208 static void emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr, 7209 unsigned long *dest) 7210 { 7211 kvm_get_dr(emul_to_vcpu(ctxt), dr, dest); 7212 } 7213 7214 static int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr, 7215 unsigned long value) 7216 { 7217 7218 return kvm_set_dr(emul_to_vcpu(ctxt), dr, value); 7219 } 7220 7221 static u64 mk_cr_64(u64 curr_cr, u32 new_val) 7222 { 7223 return (curr_cr & ~((1ULL << 32) - 1)) | new_val; 7224 } 7225 7226 static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr) 7227 { 7228 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 7229 unsigned long value; 7230 7231 switch (cr) { 7232 case 0: 7233 value = kvm_read_cr0(vcpu); 7234 break; 7235 case 2: 7236 value = vcpu->arch.cr2; 7237 break; 7238 case 3: 7239 value = kvm_read_cr3(vcpu); 7240 break; 7241 case 4: 7242 value = kvm_read_cr4(vcpu); 7243 break; 7244 case 8: 7245 value = kvm_get_cr8(vcpu); 7246 break; 7247 default: 7248 kvm_err("%s: unexpected cr %u\n", __func__, cr); 7249 return 0; 7250 } 7251 7252 return value; 7253 } 7254 7255 static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val) 7256 { 7257 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 7258 int res = 0; 7259 7260 switch (cr) { 7261 case 0: 7262 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val)); 7263 break; 7264 case 2: 7265 vcpu->arch.cr2 = val; 7266 break; 7267 case 3: 7268 res = kvm_set_cr3(vcpu, val); 7269 break; 7270 case 4: 7271 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val)); 7272 break; 7273 case 8: 7274 res = kvm_set_cr8(vcpu, val); 7275 break; 7276 default: 7277 kvm_err("%s: unexpected cr %u\n", __func__, cr); 7278 res = -1; 7279 } 7280 7281 return res; 7282 } 7283 7284 static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt) 7285 { 7286 return static_call(kvm_x86_get_cpl)(emul_to_vcpu(ctxt)); 7287 } 7288 7289 static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt) 7290 { 7291 static_call(kvm_x86_get_gdt)(emul_to_vcpu(ctxt), dt); 7292 } 7293 7294 static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt) 7295 { 7296 static_call(kvm_x86_get_idt)(emul_to_vcpu(ctxt), dt); 7297 } 7298 7299 static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt) 7300 { 7301 static_call(kvm_x86_set_gdt)(emul_to_vcpu(ctxt), dt); 7302 } 7303 7304 static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt) 7305 { 7306 static_call(kvm_x86_set_idt)(emul_to_vcpu(ctxt), dt); 7307 } 7308 7309 static unsigned long emulator_get_cached_segment_base( 7310 struct x86_emulate_ctxt *ctxt, int seg) 7311 { 7312 return get_segment_base(emul_to_vcpu(ctxt), seg); 7313 } 7314 7315 static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector, 7316 struct desc_struct *desc, u32 *base3, 7317 int seg) 7318 { 7319 struct kvm_segment var; 7320 7321 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg); 7322 *selector = var.selector; 7323 7324 if (var.unusable) { 7325 memset(desc, 0, sizeof(*desc)); 7326 if (base3) 7327 *base3 = 0; 7328 return false; 7329 } 7330 7331 if (var.g) 7332 var.limit >>= 12; 7333 set_desc_limit(desc, var.limit); 7334 set_desc_base(desc, (unsigned long)var.base); 7335 #ifdef CONFIG_X86_64 7336 if (base3) 7337 *base3 = var.base >> 32; 7338 #endif 7339 desc->type = var.type; 7340 desc->s = var.s; 7341 desc->dpl = var.dpl; 7342 desc->p = var.present; 7343 desc->avl = var.avl; 7344 desc->l = var.l; 7345 desc->d = var.db; 7346 desc->g = var.g; 7347 7348 return true; 7349 } 7350 7351 static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector, 7352 struct desc_struct *desc, u32 base3, 7353 int seg) 7354 { 7355 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 7356 struct kvm_segment var; 7357 7358 var.selector = selector; 7359 var.base = get_desc_base(desc); 7360 #ifdef CONFIG_X86_64 7361 var.base |= ((u64)base3) << 32; 7362 #endif 7363 var.limit = get_desc_limit(desc); 7364 if (desc->g) 7365 var.limit = (var.limit << 12) | 0xfff; 7366 var.type = desc->type; 7367 var.dpl = desc->dpl; 7368 var.db = desc->d; 7369 var.s = desc->s; 7370 var.l = desc->l; 7371 var.g = desc->g; 7372 var.avl = desc->avl; 7373 var.present = desc->p; 7374 var.unusable = !var.present; 7375 var.padding = 0; 7376 7377 kvm_set_segment(vcpu, &var, seg); 7378 return; 7379 } 7380 7381 static int emulator_get_msr(struct x86_emulate_ctxt *ctxt, 7382 u32 msr_index, u64 *pdata) 7383 { 7384 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 7385 int r; 7386 7387 r = kvm_get_msr(vcpu, msr_index, pdata); 7388 7389 if (r && kvm_get_msr_user_space(vcpu, msr_index, r)) { 7390 /* Bounce to user space */ 7391 return X86EMUL_IO_NEEDED; 7392 } 7393 7394 return r; 7395 } 7396 7397 static int emulator_set_msr(struct x86_emulate_ctxt *ctxt, 7398 u32 msr_index, u64 data) 7399 { 7400 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 7401 int r; 7402 7403 r = kvm_set_msr(vcpu, msr_index, data); 7404 7405 if (r && kvm_set_msr_user_space(vcpu, msr_index, data, r)) { 7406 /* Bounce to user space */ 7407 return X86EMUL_IO_NEEDED; 7408 } 7409 7410 return r; 7411 } 7412 7413 static u64 emulator_get_smbase(struct x86_emulate_ctxt *ctxt) 7414 { 7415 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 7416 7417 return vcpu->arch.smbase; 7418 } 7419 7420 static void emulator_set_smbase(struct x86_emulate_ctxt *ctxt, u64 smbase) 7421 { 7422 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 7423 7424 vcpu->arch.smbase = smbase; 7425 } 7426 7427 static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt, 7428 u32 pmc) 7429 { 7430 if (kvm_pmu_is_valid_rdpmc_ecx(emul_to_vcpu(ctxt), pmc)) 7431 return 0; 7432 return -EINVAL; 7433 } 7434 7435 static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt, 7436 u32 pmc, u64 *pdata) 7437 { 7438 return kvm_pmu_rdpmc(emul_to_vcpu(ctxt), pmc, pdata); 7439 } 7440 7441 static void emulator_halt(struct x86_emulate_ctxt *ctxt) 7442 { 7443 emul_to_vcpu(ctxt)->arch.halt_request = 1; 7444 } 7445 7446 static int emulator_intercept(struct x86_emulate_ctxt *ctxt, 7447 struct x86_instruction_info *info, 7448 enum x86_intercept_stage stage) 7449 { 7450 return static_call(kvm_x86_check_intercept)(emul_to_vcpu(ctxt), info, stage, 7451 &ctxt->exception); 7452 } 7453 7454 static bool emulator_get_cpuid(struct x86_emulate_ctxt *ctxt, 7455 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx, 7456 bool exact_only) 7457 { 7458 return kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx, exact_only); 7459 } 7460 7461 static bool emulator_guest_has_long_mode(struct x86_emulate_ctxt *ctxt) 7462 { 7463 return guest_cpuid_has(emul_to_vcpu(ctxt), X86_FEATURE_LM); 7464 } 7465 7466 static bool emulator_guest_has_movbe(struct x86_emulate_ctxt *ctxt) 7467 { 7468 return guest_cpuid_has(emul_to_vcpu(ctxt), X86_FEATURE_MOVBE); 7469 } 7470 7471 static bool emulator_guest_has_fxsr(struct x86_emulate_ctxt *ctxt) 7472 { 7473 return guest_cpuid_has(emul_to_vcpu(ctxt), X86_FEATURE_FXSR); 7474 } 7475 7476 static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg) 7477 { 7478 return kvm_register_read_raw(emul_to_vcpu(ctxt), reg); 7479 } 7480 7481 static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val) 7482 { 7483 kvm_register_write_raw(emul_to_vcpu(ctxt), reg, val); 7484 } 7485 7486 static void emulator_set_nmi_mask(struct x86_emulate_ctxt *ctxt, bool masked) 7487 { 7488 static_call(kvm_x86_set_nmi_mask)(emul_to_vcpu(ctxt), masked); 7489 } 7490 7491 static unsigned emulator_get_hflags(struct x86_emulate_ctxt *ctxt) 7492 { 7493 return emul_to_vcpu(ctxt)->arch.hflags; 7494 } 7495 7496 static void emulator_exiting_smm(struct x86_emulate_ctxt *ctxt) 7497 { 7498 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 7499 7500 kvm_smm_changed(vcpu, false); 7501 } 7502 7503 static int emulator_leave_smm(struct x86_emulate_ctxt *ctxt, 7504 const char *smstate) 7505 { 7506 return static_call(kvm_x86_leave_smm)(emul_to_vcpu(ctxt), smstate); 7507 } 7508 7509 static void emulator_triple_fault(struct x86_emulate_ctxt *ctxt) 7510 { 7511 kvm_make_request(KVM_REQ_TRIPLE_FAULT, emul_to_vcpu(ctxt)); 7512 } 7513 7514 static int emulator_set_xcr(struct x86_emulate_ctxt *ctxt, u32 index, u64 xcr) 7515 { 7516 return __kvm_set_xcr(emul_to_vcpu(ctxt), index, xcr); 7517 } 7518 7519 static const struct x86_emulate_ops emulate_ops = { 7520 .read_gpr = emulator_read_gpr, 7521 .write_gpr = emulator_write_gpr, 7522 .read_std = emulator_read_std, 7523 .write_std = emulator_write_std, 7524 .read_phys = kvm_read_guest_phys_system, 7525 .fetch = kvm_fetch_guest_virt, 7526 .read_emulated = emulator_read_emulated, 7527 .write_emulated = emulator_write_emulated, 7528 .cmpxchg_emulated = emulator_cmpxchg_emulated, 7529 .invlpg = emulator_invlpg, 7530 .pio_in_emulated = emulator_pio_in_emulated, 7531 .pio_out_emulated = emulator_pio_out_emulated, 7532 .get_segment = emulator_get_segment, 7533 .set_segment = emulator_set_segment, 7534 .get_cached_segment_base = emulator_get_cached_segment_base, 7535 .get_gdt = emulator_get_gdt, 7536 .get_idt = emulator_get_idt, 7537 .set_gdt = emulator_set_gdt, 7538 .set_idt = emulator_set_idt, 7539 .get_cr = emulator_get_cr, 7540 .set_cr = emulator_set_cr, 7541 .cpl = emulator_get_cpl, 7542 .get_dr = emulator_get_dr, 7543 .set_dr = emulator_set_dr, 7544 .get_smbase = emulator_get_smbase, 7545 .set_smbase = emulator_set_smbase, 7546 .set_msr = emulator_set_msr, 7547 .get_msr = emulator_get_msr, 7548 .check_pmc = emulator_check_pmc, 7549 .read_pmc = emulator_read_pmc, 7550 .halt = emulator_halt, 7551 .wbinvd = emulator_wbinvd, 7552 .fix_hypercall = emulator_fix_hypercall, 7553 .intercept = emulator_intercept, 7554 .get_cpuid = emulator_get_cpuid, 7555 .guest_has_long_mode = emulator_guest_has_long_mode, 7556 .guest_has_movbe = emulator_guest_has_movbe, 7557 .guest_has_fxsr = emulator_guest_has_fxsr, 7558 .set_nmi_mask = emulator_set_nmi_mask, 7559 .get_hflags = emulator_get_hflags, 7560 .exiting_smm = emulator_exiting_smm, 7561 .leave_smm = emulator_leave_smm, 7562 .triple_fault = emulator_triple_fault, 7563 .set_xcr = emulator_set_xcr, 7564 }; 7565 7566 static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask) 7567 { 7568 u32 int_shadow = static_call(kvm_x86_get_interrupt_shadow)(vcpu); 7569 /* 7570 * an sti; sti; sequence only disable interrupts for the first 7571 * instruction. So, if the last instruction, be it emulated or 7572 * not, left the system with the INT_STI flag enabled, it 7573 * means that the last instruction is an sti. We should not 7574 * leave the flag on in this case. The same goes for mov ss 7575 */ 7576 if (int_shadow & mask) 7577 mask = 0; 7578 if (unlikely(int_shadow || mask)) { 7579 static_call(kvm_x86_set_interrupt_shadow)(vcpu, mask); 7580 if (!mask) 7581 kvm_make_request(KVM_REQ_EVENT, vcpu); 7582 } 7583 } 7584 7585 static bool inject_emulated_exception(struct kvm_vcpu *vcpu) 7586 { 7587 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt; 7588 if (ctxt->exception.vector == PF_VECTOR) 7589 return kvm_inject_emulated_page_fault(vcpu, &ctxt->exception); 7590 7591 if (ctxt->exception.error_code_valid) 7592 kvm_queue_exception_e(vcpu, ctxt->exception.vector, 7593 ctxt->exception.error_code); 7594 else 7595 kvm_queue_exception(vcpu, ctxt->exception.vector); 7596 return false; 7597 } 7598 7599 static struct x86_emulate_ctxt *alloc_emulate_ctxt(struct kvm_vcpu *vcpu) 7600 { 7601 struct x86_emulate_ctxt *ctxt; 7602 7603 ctxt = kmem_cache_zalloc(x86_emulator_cache, GFP_KERNEL_ACCOUNT); 7604 if (!ctxt) { 7605 pr_err("kvm: failed to allocate vcpu's emulator\n"); 7606 return NULL; 7607 } 7608 7609 ctxt->vcpu = vcpu; 7610 ctxt->ops = &emulate_ops; 7611 vcpu->arch.emulate_ctxt = ctxt; 7612 7613 return ctxt; 7614 } 7615 7616 static void init_emulate_ctxt(struct kvm_vcpu *vcpu) 7617 { 7618 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt; 7619 int cs_db, cs_l; 7620 7621 static_call(kvm_x86_get_cs_db_l_bits)(vcpu, &cs_db, &cs_l); 7622 7623 ctxt->gpa_available = false; 7624 ctxt->eflags = kvm_get_rflags(vcpu); 7625 ctxt->tf = (ctxt->eflags & X86_EFLAGS_TF) != 0; 7626 7627 ctxt->eip = kvm_rip_read(vcpu); 7628 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL : 7629 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 : 7630 (cs_l && is_long_mode(vcpu)) ? X86EMUL_MODE_PROT64 : 7631 cs_db ? X86EMUL_MODE_PROT32 : 7632 X86EMUL_MODE_PROT16; 7633 BUILD_BUG_ON(HF_GUEST_MASK != X86EMUL_GUEST_MASK); 7634 BUILD_BUG_ON(HF_SMM_MASK != X86EMUL_SMM_MASK); 7635 BUILD_BUG_ON(HF_SMM_INSIDE_NMI_MASK != X86EMUL_SMM_INSIDE_NMI_MASK); 7636 7637 ctxt->interruptibility = 0; 7638 ctxt->have_exception = false; 7639 ctxt->exception.vector = -1; 7640 ctxt->perm_ok = false; 7641 7642 init_decode_cache(ctxt); 7643 vcpu->arch.emulate_regs_need_sync_from_vcpu = false; 7644 } 7645 7646 void kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip) 7647 { 7648 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt; 7649 int ret; 7650 7651 init_emulate_ctxt(vcpu); 7652 7653 ctxt->op_bytes = 2; 7654 ctxt->ad_bytes = 2; 7655 ctxt->_eip = ctxt->eip + inc_eip; 7656 ret = emulate_int_real(ctxt, irq); 7657 7658 if (ret != X86EMUL_CONTINUE) { 7659 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); 7660 } else { 7661 ctxt->eip = ctxt->_eip; 7662 kvm_rip_write(vcpu, ctxt->eip); 7663 kvm_set_rflags(vcpu, ctxt->eflags); 7664 } 7665 } 7666 EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt); 7667 7668 static void prepare_emulation_failure_exit(struct kvm_vcpu *vcpu, u64 *data, 7669 u8 ndata, u8 *insn_bytes, u8 insn_size) 7670 { 7671 struct kvm_run *run = vcpu->run; 7672 u64 info[5]; 7673 u8 info_start; 7674 7675 /* 7676 * Zero the whole array used to retrieve the exit info, as casting to 7677 * u32 for select entries will leave some chunks uninitialized. 7678 */ 7679 memset(&info, 0, sizeof(info)); 7680 7681 static_call(kvm_x86_get_exit_info)(vcpu, (u32 *)&info[0], &info[1], 7682 &info[2], (u32 *)&info[3], 7683 (u32 *)&info[4]); 7684 7685 run->exit_reason = KVM_EXIT_INTERNAL_ERROR; 7686 run->emulation_failure.suberror = KVM_INTERNAL_ERROR_EMULATION; 7687 7688 /* 7689 * There's currently space for 13 entries, but 5 are used for the exit 7690 * reason and info. Restrict to 4 to reduce the maintenance burden 7691 * when expanding kvm_run.emulation_failure in the future. 7692 */ 7693 if (WARN_ON_ONCE(ndata > 4)) 7694 ndata = 4; 7695 7696 /* Always include the flags as a 'data' entry. */ 7697 info_start = 1; 7698 run->emulation_failure.flags = 0; 7699 7700 if (insn_size) { 7701 BUILD_BUG_ON((sizeof(run->emulation_failure.insn_size) + 7702 sizeof(run->emulation_failure.insn_bytes) != 16)); 7703 info_start += 2; 7704 run->emulation_failure.flags |= 7705 KVM_INTERNAL_ERROR_EMULATION_FLAG_INSTRUCTION_BYTES; 7706 run->emulation_failure.insn_size = insn_size; 7707 memset(run->emulation_failure.insn_bytes, 0x90, 7708 sizeof(run->emulation_failure.insn_bytes)); 7709 memcpy(run->emulation_failure.insn_bytes, insn_bytes, insn_size); 7710 } 7711 7712 memcpy(&run->internal.data[info_start], info, sizeof(info)); 7713 memcpy(&run->internal.data[info_start + ARRAY_SIZE(info)], data, 7714 ndata * sizeof(data[0])); 7715 7716 run->emulation_failure.ndata = info_start + ARRAY_SIZE(info) + ndata; 7717 } 7718 7719 static void prepare_emulation_ctxt_failure_exit(struct kvm_vcpu *vcpu) 7720 { 7721 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt; 7722 7723 prepare_emulation_failure_exit(vcpu, NULL, 0, ctxt->fetch.data, 7724 ctxt->fetch.end - ctxt->fetch.data); 7725 } 7726 7727 void __kvm_prepare_emulation_failure_exit(struct kvm_vcpu *vcpu, u64 *data, 7728 u8 ndata) 7729 { 7730 prepare_emulation_failure_exit(vcpu, data, ndata, NULL, 0); 7731 } 7732 EXPORT_SYMBOL_GPL(__kvm_prepare_emulation_failure_exit); 7733 7734 void kvm_prepare_emulation_failure_exit(struct kvm_vcpu *vcpu) 7735 { 7736 __kvm_prepare_emulation_failure_exit(vcpu, NULL, 0); 7737 } 7738 EXPORT_SYMBOL_GPL(kvm_prepare_emulation_failure_exit); 7739 7740 static int handle_emulation_failure(struct kvm_vcpu *vcpu, int emulation_type) 7741 { 7742 struct kvm *kvm = vcpu->kvm; 7743 7744 ++vcpu->stat.insn_emulation_fail; 7745 trace_kvm_emulate_insn_failed(vcpu); 7746 7747 if (emulation_type & EMULTYPE_VMWARE_GP) { 7748 kvm_queue_exception_e(vcpu, GP_VECTOR, 0); 7749 return 1; 7750 } 7751 7752 if (kvm->arch.exit_on_emulation_error || 7753 (emulation_type & EMULTYPE_SKIP)) { 7754 prepare_emulation_ctxt_failure_exit(vcpu); 7755 return 0; 7756 } 7757 7758 kvm_queue_exception(vcpu, UD_VECTOR); 7759 7760 if (!is_guest_mode(vcpu) && static_call(kvm_x86_get_cpl)(vcpu) == 0) { 7761 prepare_emulation_ctxt_failure_exit(vcpu); 7762 return 0; 7763 } 7764 7765 return 1; 7766 } 7767 7768 static bool reexecute_instruction(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa, 7769 bool write_fault_to_shadow_pgtable, 7770 int emulation_type) 7771 { 7772 gpa_t gpa = cr2_or_gpa; 7773 kvm_pfn_t pfn; 7774 7775 if (!(emulation_type & EMULTYPE_ALLOW_RETRY_PF)) 7776 return false; 7777 7778 if (WARN_ON_ONCE(is_guest_mode(vcpu)) || 7779 WARN_ON_ONCE(!(emulation_type & EMULTYPE_PF))) 7780 return false; 7781 7782 if (!vcpu->arch.mmu->direct_map) { 7783 /* 7784 * Write permission should be allowed since only 7785 * write access need to be emulated. 7786 */ 7787 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2_or_gpa, NULL); 7788 7789 /* 7790 * If the mapping is invalid in guest, let cpu retry 7791 * it to generate fault. 7792 */ 7793 if (gpa == UNMAPPED_GVA) 7794 return true; 7795 } 7796 7797 /* 7798 * Do not retry the unhandleable instruction if it faults on the 7799 * readonly host memory, otherwise it will goto a infinite loop: 7800 * retry instruction -> write #PF -> emulation fail -> retry 7801 * instruction -> ... 7802 */ 7803 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa)); 7804 7805 /* 7806 * If the instruction failed on the error pfn, it can not be fixed, 7807 * report the error to userspace. 7808 */ 7809 if (is_error_noslot_pfn(pfn)) 7810 return false; 7811 7812 kvm_release_pfn_clean(pfn); 7813 7814 /* The instructions are well-emulated on direct mmu. */ 7815 if (vcpu->arch.mmu->direct_map) { 7816 unsigned int indirect_shadow_pages; 7817 7818 write_lock(&vcpu->kvm->mmu_lock); 7819 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages; 7820 write_unlock(&vcpu->kvm->mmu_lock); 7821 7822 if (indirect_shadow_pages) 7823 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa)); 7824 7825 return true; 7826 } 7827 7828 /* 7829 * if emulation was due to access to shadowed page table 7830 * and it failed try to unshadow page and re-enter the 7831 * guest to let CPU execute the instruction. 7832 */ 7833 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa)); 7834 7835 /* 7836 * If the access faults on its page table, it can not 7837 * be fixed by unprotecting shadow page and it should 7838 * be reported to userspace. 7839 */ 7840 return !write_fault_to_shadow_pgtable; 7841 } 7842 7843 static bool retry_instruction(struct x86_emulate_ctxt *ctxt, 7844 gpa_t cr2_or_gpa, int emulation_type) 7845 { 7846 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 7847 unsigned long last_retry_eip, last_retry_addr, gpa = cr2_or_gpa; 7848 7849 last_retry_eip = vcpu->arch.last_retry_eip; 7850 last_retry_addr = vcpu->arch.last_retry_addr; 7851 7852 /* 7853 * If the emulation is caused by #PF and it is non-page_table 7854 * writing instruction, it means the VM-EXIT is caused by shadow 7855 * page protected, we can zap the shadow page and retry this 7856 * instruction directly. 7857 * 7858 * Note: if the guest uses a non-page-table modifying instruction 7859 * on the PDE that points to the instruction, then we will unmap 7860 * the instruction and go to an infinite loop. So, we cache the 7861 * last retried eip and the last fault address, if we meet the eip 7862 * and the address again, we can break out of the potential infinite 7863 * loop. 7864 */ 7865 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0; 7866 7867 if (!(emulation_type & EMULTYPE_ALLOW_RETRY_PF)) 7868 return false; 7869 7870 if (WARN_ON_ONCE(is_guest_mode(vcpu)) || 7871 WARN_ON_ONCE(!(emulation_type & EMULTYPE_PF))) 7872 return false; 7873 7874 if (x86_page_table_writing_insn(ctxt)) 7875 return false; 7876 7877 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2_or_gpa) 7878 return false; 7879 7880 vcpu->arch.last_retry_eip = ctxt->eip; 7881 vcpu->arch.last_retry_addr = cr2_or_gpa; 7882 7883 if (!vcpu->arch.mmu->direct_map) 7884 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2_or_gpa, NULL); 7885 7886 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa)); 7887 7888 return true; 7889 } 7890 7891 static int complete_emulated_mmio(struct kvm_vcpu *vcpu); 7892 static int complete_emulated_pio(struct kvm_vcpu *vcpu); 7893 7894 static void kvm_smm_changed(struct kvm_vcpu *vcpu, bool entering_smm) 7895 { 7896 trace_kvm_smm_transition(vcpu->vcpu_id, vcpu->arch.smbase, entering_smm); 7897 7898 if (entering_smm) { 7899 vcpu->arch.hflags |= HF_SMM_MASK; 7900 } else { 7901 vcpu->arch.hflags &= ~(HF_SMM_MASK | HF_SMM_INSIDE_NMI_MASK); 7902 7903 /* Process a latched INIT or SMI, if any. */ 7904 kvm_make_request(KVM_REQ_EVENT, vcpu); 7905 7906 /* 7907 * Even if KVM_SET_SREGS2 loaded PDPTRs out of band, 7908 * on SMM exit we still need to reload them from 7909 * guest memory 7910 */ 7911 vcpu->arch.pdptrs_from_userspace = false; 7912 } 7913 7914 kvm_mmu_reset_context(vcpu); 7915 } 7916 7917 static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7, 7918 unsigned long *db) 7919 { 7920 u32 dr6 = 0; 7921 int i; 7922 u32 enable, rwlen; 7923 7924 enable = dr7; 7925 rwlen = dr7 >> 16; 7926 for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4) 7927 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr) 7928 dr6 |= (1 << i); 7929 return dr6; 7930 } 7931 7932 static int kvm_vcpu_do_singlestep(struct kvm_vcpu *vcpu) 7933 { 7934 struct kvm_run *kvm_run = vcpu->run; 7935 7936 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) { 7937 kvm_run->debug.arch.dr6 = DR6_BS | DR6_ACTIVE_LOW; 7938 kvm_run->debug.arch.pc = kvm_get_linear_rip(vcpu); 7939 kvm_run->debug.arch.exception = DB_VECTOR; 7940 kvm_run->exit_reason = KVM_EXIT_DEBUG; 7941 return 0; 7942 } 7943 kvm_queue_exception_p(vcpu, DB_VECTOR, DR6_BS); 7944 return 1; 7945 } 7946 7947 int kvm_skip_emulated_instruction(struct kvm_vcpu *vcpu) 7948 { 7949 unsigned long rflags = static_call(kvm_x86_get_rflags)(vcpu); 7950 int r; 7951 7952 r = static_call(kvm_x86_skip_emulated_instruction)(vcpu); 7953 if (unlikely(!r)) 7954 return 0; 7955 7956 /* 7957 * rflags is the old, "raw" value of the flags. The new value has 7958 * not been saved yet. 7959 * 7960 * This is correct even for TF set by the guest, because "the 7961 * processor will not generate this exception after the instruction 7962 * that sets the TF flag". 7963 */ 7964 if (unlikely(rflags & X86_EFLAGS_TF)) 7965 r = kvm_vcpu_do_singlestep(vcpu); 7966 return r; 7967 } 7968 EXPORT_SYMBOL_GPL(kvm_skip_emulated_instruction); 7969 7970 static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r) 7971 { 7972 if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) && 7973 (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) { 7974 struct kvm_run *kvm_run = vcpu->run; 7975 unsigned long eip = kvm_get_linear_rip(vcpu); 7976 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0, 7977 vcpu->arch.guest_debug_dr7, 7978 vcpu->arch.eff_db); 7979 7980 if (dr6 != 0) { 7981 kvm_run->debug.arch.dr6 = dr6 | DR6_ACTIVE_LOW; 7982 kvm_run->debug.arch.pc = eip; 7983 kvm_run->debug.arch.exception = DB_VECTOR; 7984 kvm_run->exit_reason = KVM_EXIT_DEBUG; 7985 *r = 0; 7986 return true; 7987 } 7988 } 7989 7990 if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) && 7991 !(kvm_get_rflags(vcpu) & X86_EFLAGS_RF)) { 7992 unsigned long eip = kvm_get_linear_rip(vcpu); 7993 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0, 7994 vcpu->arch.dr7, 7995 vcpu->arch.db); 7996 7997 if (dr6 != 0) { 7998 kvm_queue_exception_p(vcpu, DB_VECTOR, dr6); 7999 *r = 1; 8000 return true; 8001 } 8002 } 8003 8004 return false; 8005 } 8006 8007 static bool is_vmware_backdoor_opcode(struct x86_emulate_ctxt *ctxt) 8008 { 8009 switch (ctxt->opcode_len) { 8010 case 1: 8011 switch (ctxt->b) { 8012 case 0xe4: /* IN */ 8013 case 0xe5: 8014 case 0xec: 8015 case 0xed: 8016 case 0xe6: /* OUT */ 8017 case 0xe7: 8018 case 0xee: 8019 case 0xef: 8020 case 0x6c: /* INS */ 8021 case 0x6d: 8022 case 0x6e: /* OUTS */ 8023 case 0x6f: 8024 return true; 8025 } 8026 break; 8027 case 2: 8028 switch (ctxt->b) { 8029 case 0x33: /* RDPMC */ 8030 return true; 8031 } 8032 break; 8033 } 8034 8035 return false; 8036 } 8037 8038 /* 8039 * Decode to be emulated instruction. Return EMULATION_OK if success. 8040 */ 8041 int x86_decode_emulated_instruction(struct kvm_vcpu *vcpu, int emulation_type, 8042 void *insn, int insn_len) 8043 { 8044 int r = EMULATION_OK; 8045 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt; 8046 8047 init_emulate_ctxt(vcpu); 8048 8049 /* 8050 * We will reenter on the same instruction since we do not set 8051 * complete_userspace_io. This does not handle watchpoints yet, 8052 * those would be handled in the emulate_ops. 8053 */ 8054 if (!(emulation_type & EMULTYPE_SKIP) && 8055 kvm_vcpu_check_breakpoint(vcpu, &r)) 8056 return r; 8057 8058 r = x86_decode_insn(ctxt, insn, insn_len, emulation_type); 8059 8060 trace_kvm_emulate_insn_start(vcpu); 8061 ++vcpu->stat.insn_emulation; 8062 8063 return r; 8064 } 8065 EXPORT_SYMBOL_GPL(x86_decode_emulated_instruction); 8066 8067 int x86_emulate_instruction(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa, 8068 int emulation_type, void *insn, int insn_len) 8069 { 8070 int r; 8071 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt; 8072 bool writeback = true; 8073 bool write_fault_to_spt; 8074 8075 if (unlikely(!static_call(kvm_x86_can_emulate_instruction)(vcpu, insn, insn_len))) 8076 return 1; 8077 8078 vcpu->arch.l1tf_flush_l1d = true; 8079 8080 /* 8081 * Clear write_fault_to_shadow_pgtable here to ensure it is 8082 * never reused. 8083 */ 8084 write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable; 8085 vcpu->arch.write_fault_to_shadow_pgtable = false; 8086 8087 if (!(emulation_type & EMULTYPE_NO_DECODE)) { 8088 kvm_clear_exception_queue(vcpu); 8089 8090 r = x86_decode_emulated_instruction(vcpu, emulation_type, 8091 insn, insn_len); 8092 if (r != EMULATION_OK) { 8093 if ((emulation_type & EMULTYPE_TRAP_UD) || 8094 (emulation_type & EMULTYPE_TRAP_UD_FORCED)) { 8095 kvm_queue_exception(vcpu, UD_VECTOR); 8096 return 1; 8097 } 8098 if (reexecute_instruction(vcpu, cr2_or_gpa, 8099 write_fault_to_spt, 8100 emulation_type)) 8101 return 1; 8102 if (ctxt->have_exception) { 8103 /* 8104 * #UD should result in just EMULATION_FAILED, and trap-like 8105 * exception should not be encountered during decode. 8106 */ 8107 WARN_ON_ONCE(ctxt->exception.vector == UD_VECTOR || 8108 exception_type(ctxt->exception.vector) == EXCPT_TRAP); 8109 inject_emulated_exception(vcpu); 8110 return 1; 8111 } 8112 return handle_emulation_failure(vcpu, emulation_type); 8113 } 8114 } 8115 8116 if ((emulation_type & EMULTYPE_VMWARE_GP) && 8117 !is_vmware_backdoor_opcode(ctxt)) { 8118 kvm_queue_exception_e(vcpu, GP_VECTOR, 0); 8119 return 1; 8120 } 8121 8122 /* 8123 * Note, EMULTYPE_SKIP is intended for use *only* by vendor callbacks 8124 * for kvm_skip_emulated_instruction(). The caller is responsible for 8125 * updating interruptibility state and injecting single-step #DBs. 8126 */ 8127 if (emulation_type & EMULTYPE_SKIP) { 8128 kvm_rip_write(vcpu, ctxt->_eip); 8129 if (ctxt->eflags & X86_EFLAGS_RF) 8130 kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF); 8131 return 1; 8132 } 8133 8134 if (retry_instruction(ctxt, cr2_or_gpa, emulation_type)) 8135 return 1; 8136 8137 /* this is needed for vmware backdoor interface to work since it 8138 changes registers values during IO operation */ 8139 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) { 8140 vcpu->arch.emulate_regs_need_sync_from_vcpu = false; 8141 emulator_invalidate_register_cache(ctxt); 8142 } 8143 8144 restart: 8145 if (emulation_type & EMULTYPE_PF) { 8146 /* Save the faulting GPA (cr2) in the address field */ 8147 ctxt->exception.address = cr2_or_gpa; 8148 8149 /* With shadow page tables, cr2 contains a GVA or nGPA. */ 8150 if (vcpu->arch.mmu->direct_map) { 8151 ctxt->gpa_available = true; 8152 ctxt->gpa_val = cr2_or_gpa; 8153 } 8154 } else { 8155 /* Sanitize the address out of an abundance of paranoia. */ 8156 ctxt->exception.address = 0; 8157 } 8158 8159 r = x86_emulate_insn(ctxt); 8160 8161 if (r == EMULATION_INTERCEPTED) 8162 return 1; 8163 8164 if (r == EMULATION_FAILED) { 8165 if (reexecute_instruction(vcpu, cr2_or_gpa, write_fault_to_spt, 8166 emulation_type)) 8167 return 1; 8168 8169 return handle_emulation_failure(vcpu, emulation_type); 8170 } 8171 8172 if (ctxt->have_exception) { 8173 r = 1; 8174 if (inject_emulated_exception(vcpu)) 8175 return r; 8176 } else if (vcpu->arch.pio.count) { 8177 if (!vcpu->arch.pio.in) { 8178 /* FIXME: return into emulator if single-stepping. */ 8179 vcpu->arch.pio.count = 0; 8180 } else { 8181 writeback = false; 8182 vcpu->arch.complete_userspace_io = complete_emulated_pio; 8183 } 8184 r = 0; 8185 } else if (vcpu->mmio_needed) { 8186 ++vcpu->stat.mmio_exits; 8187 8188 if (!vcpu->mmio_is_write) 8189 writeback = false; 8190 r = 0; 8191 vcpu->arch.complete_userspace_io = complete_emulated_mmio; 8192 } else if (r == EMULATION_RESTART) 8193 goto restart; 8194 else 8195 r = 1; 8196 8197 if (writeback) { 8198 unsigned long rflags = static_call(kvm_x86_get_rflags)(vcpu); 8199 toggle_interruptibility(vcpu, ctxt->interruptibility); 8200 vcpu->arch.emulate_regs_need_sync_to_vcpu = false; 8201 if (!ctxt->have_exception || 8202 exception_type(ctxt->exception.vector) == EXCPT_TRAP) { 8203 kvm_rip_write(vcpu, ctxt->eip); 8204 if (r && (ctxt->tf || (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP))) 8205 r = kvm_vcpu_do_singlestep(vcpu); 8206 if (kvm_x86_ops.update_emulated_instruction) 8207 static_call(kvm_x86_update_emulated_instruction)(vcpu); 8208 __kvm_set_rflags(vcpu, ctxt->eflags); 8209 } 8210 8211 /* 8212 * For STI, interrupts are shadowed; so KVM_REQ_EVENT will 8213 * do nothing, and it will be requested again as soon as 8214 * the shadow expires. But we still need to check here, 8215 * because POPF has no interrupt shadow. 8216 */ 8217 if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF)) 8218 kvm_make_request(KVM_REQ_EVENT, vcpu); 8219 } else 8220 vcpu->arch.emulate_regs_need_sync_to_vcpu = true; 8221 8222 return r; 8223 } 8224 8225 int kvm_emulate_instruction(struct kvm_vcpu *vcpu, int emulation_type) 8226 { 8227 return x86_emulate_instruction(vcpu, 0, emulation_type, NULL, 0); 8228 } 8229 EXPORT_SYMBOL_GPL(kvm_emulate_instruction); 8230 8231 int kvm_emulate_instruction_from_buffer(struct kvm_vcpu *vcpu, 8232 void *insn, int insn_len) 8233 { 8234 return x86_emulate_instruction(vcpu, 0, 0, insn, insn_len); 8235 } 8236 EXPORT_SYMBOL_GPL(kvm_emulate_instruction_from_buffer); 8237 8238 static int complete_fast_pio_out_port_0x7e(struct kvm_vcpu *vcpu) 8239 { 8240 vcpu->arch.pio.count = 0; 8241 return 1; 8242 } 8243 8244 static int complete_fast_pio_out(struct kvm_vcpu *vcpu) 8245 { 8246 vcpu->arch.pio.count = 0; 8247 8248 if (unlikely(!kvm_is_linear_rip(vcpu, vcpu->arch.pio.linear_rip))) 8249 return 1; 8250 8251 return kvm_skip_emulated_instruction(vcpu); 8252 } 8253 8254 static int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, 8255 unsigned short port) 8256 { 8257 unsigned long val = kvm_rax_read(vcpu); 8258 int ret = emulator_pio_out(vcpu, size, port, &val, 1); 8259 8260 if (ret) 8261 return ret; 8262 8263 /* 8264 * Workaround userspace that relies on old KVM behavior of %rip being 8265 * incremented prior to exiting to userspace to handle "OUT 0x7e". 8266 */ 8267 if (port == 0x7e && 8268 kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_OUT_7E_INC_RIP)) { 8269 vcpu->arch.complete_userspace_io = 8270 complete_fast_pio_out_port_0x7e; 8271 kvm_skip_emulated_instruction(vcpu); 8272 } else { 8273 vcpu->arch.pio.linear_rip = kvm_get_linear_rip(vcpu); 8274 vcpu->arch.complete_userspace_io = complete_fast_pio_out; 8275 } 8276 return 0; 8277 } 8278 8279 static int complete_fast_pio_in(struct kvm_vcpu *vcpu) 8280 { 8281 unsigned long val; 8282 8283 /* We should only ever be called with arch.pio.count equal to 1 */ 8284 BUG_ON(vcpu->arch.pio.count != 1); 8285 8286 if (unlikely(!kvm_is_linear_rip(vcpu, vcpu->arch.pio.linear_rip))) { 8287 vcpu->arch.pio.count = 0; 8288 return 1; 8289 } 8290 8291 /* For size less than 4 we merge, else we zero extend */ 8292 val = (vcpu->arch.pio.size < 4) ? kvm_rax_read(vcpu) : 0; 8293 8294 /* 8295 * Since vcpu->arch.pio.count == 1 let emulator_pio_in perform 8296 * the copy and tracing 8297 */ 8298 emulator_pio_in(vcpu, vcpu->arch.pio.size, vcpu->arch.pio.port, &val, 1); 8299 kvm_rax_write(vcpu, val); 8300 8301 return kvm_skip_emulated_instruction(vcpu); 8302 } 8303 8304 static int kvm_fast_pio_in(struct kvm_vcpu *vcpu, int size, 8305 unsigned short port) 8306 { 8307 unsigned long val; 8308 int ret; 8309 8310 /* For size less than 4 we merge, else we zero extend */ 8311 val = (size < 4) ? kvm_rax_read(vcpu) : 0; 8312 8313 ret = emulator_pio_in(vcpu, size, port, &val, 1); 8314 if (ret) { 8315 kvm_rax_write(vcpu, val); 8316 return ret; 8317 } 8318 8319 vcpu->arch.pio.linear_rip = kvm_get_linear_rip(vcpu); 8320 vcpu->arch.complete_userspace_io = complete_fast_pio_in; 8321 8322 return 0; 8323 } 8324 8325 int kvm_fast_pio(struct kvm_vcpu *vcpu, int size, unsigned short port, int in) 8326 { 8327 int ret; 8328 8329 if (in) 8330 ret = kvm_fast_pio_in(vcpu, size, port); 8331 else 8332 ret = kvm_fast_pio_out(vcpu, size, port); 8333 return ret && kvm_skip_emulated_instruction(vcpu); 8334 } 8335 EXPORT_SYMBOL_GPL(kvm_fast_pio); 8336 8337 static int kvmclock_cpu_down_prep(unsigned int cpu) 8338 { 8339 __this_cpu_write(cpu_tsc_khz, 0); 8340 return 0; 8341 } 8342 8343 static void tsc_khz_changed(void *data) 8344 { 8345 struct cpufreq_freqs *freq = data; 8346 unsigned long khz = 0; 8347 8348 if (data) 8349 khz = freq->new; 8350 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) 8351 khz = cpufreq_quick_get(raw_smp_processor_id()); 8352 if (!khz) 8353 khz = tsc_khz; 8354 __this_cpu_write(cpu_tsc_khz, khz); 8355 } 8356 8357 #ifdef CONFIG_X86_64 8358 static void kvm_hyperv_tsc_notifier(void) 8359 { 8360 struct kvm *kvm; 8361 int cpu; 8362 8363 mutex_lock(&kvm_lock); 8364 list_for_each_entry(kvm, &vm_list, vm_list) 8365 kvm_make_mclock_inprogress_request(kvm); 8366 8367 /* no guest entries from this point */ 8368 hyperv_stop_tsc_emulation(); 8369 8370 /* TSC frequency always matches when on Hyper-V */ 8371 for_each_present_cpu(cpu) 8372 per_cpu(cpu_tsc_khz, cpu) = tsc_khz; 8373 kvm_max_guest_tsc_khz = tsc_khz; 8374 8375 list_for_each_entry(kvm, &vm_list, vm_list) { 8376 __kvm_start_pvclock_update(kvm); 8377 pvclock_update_vm_gtod_copy(kvm); 8378 kvm_end_pvclock_update(kvm); 8379 } 8380 8381 mutex_unlock(&kvm_lock); 8382 } 8383 #endif 8384 8385 static void __kvmclock_cpufreq_notifier(struct cpufreq_freqs *freq, int cpu) 8386 { 8387 struct kvm *kvm; 8388 struct kvm_vcpu *vcpu; 8389 int i, send_ipi = 0; 8390 8391 /* 8392 * We allow guests to temporarily run on slowing clocks, 8393 * provided we notify them after, or to run on accelerating 8394 * clocks, provided we notify them before. Thus time never 8395 * goes backwards. 8396 * 8397 * However, we have a problem. We can't atomically update 8398 * the frequency of a given CPU from this function; it is 8399 * merely a notifier, which can be called from any CPU. 8400 * Changing the TSC frequency at arbitrary points in time 8401 * requires a recomputation of local variables related to 8402 * the TSC for each VCPU. We must flag these local variables 8403 * to be updated and be sure the update takes place with the 8404 * new frequency before any guests proceed. 8405 * 8406 * Unfortunately, the combination of hotplug CPU and frequency 8407 * change creates an intractable locking scenario; the order 8408 * of when these callouts happen is undefined with respect to 8409 * CPU hotplug, and they can race with each other. As such, 8410 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is 8411 * undefined; you can actually have a CPU frequency change take 8412 * place in between the computation of X and the setting of the 8413 * variable. To protect against this problem, all updates of 8414 * the per_cpu tsc_khz variable are done in an interrupt 8415 * protected IPI, and all callers wishing to update the value 8416 * must wait for a synchronous IPI to complete (which is trivial 8417 * if the caller is on the CPU already). This establishes the 8418 * necessary total order on variable updates. 8419 * 8420 * Note that because a guest time update may take place 8421 * anytime after the setting of the VCPU's request bit, the 8422 * correct TSC value must be set before the request. However, 8423 * to ensure the update actually makes it to any guest which 8424 * starts running in hardware virtualization between the set 8425 * and the acquisition of the spinlock, we must also ping the 8426 * CPU after setting the request bit. 8427 * 8428 */ 8429 8430 smp_call_function_single(cpu, tsc_khz_changed, freq, 1); 8431 8432 mutex_lock(&kvm_lock); 8433 list_for_each_entry(kvm, &vm_list, vm_list) { 8434 kvm_for_each_vcpu(i, vcpu, kvm) { 8435 if (vcpu->cpu != cpu) 8436 continue; 8437 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 8438 if (vcpu->cpu != raw_smp_processor_id()) 8439 send_ipi = 1; 8440 } 8441 } 8442 mutex_unlock(&kvm_lock); 8443 8444 if (freq->old < freq->new && send_ipi) { 8445 /* 8446 * We upscale the frequency. Must make the guest 8447 * doesn't see old kvmclock values while running with 8448 * the new frequency, otherwise we risk the guest sees 8449 * time go backwards. 8450 * 8451 * In case we update the frequency for another cpu 8452 * (which might be in guest context) send an interrupt 8453 * to kick the cpu out of guest context. Next time 8454 * guest context is entered kvmclock will be updated, 8455 * so the guest will not see stale values. 8456 */ 8457 smp_call_function_single(cpu, tsc_khz_changed, freq, 1); 8458 } 8459 } 8460 8461 static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val, 8462 void *data) 8463 { 8464 struct cpufreq_freqs *freq = data; 8465 int cpu; 8466 8467 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new) 8468 return 0; 8469 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new) 8470 return 0; 8471 8472 for_each_cpu(cpu, freq->policy->cpus) 8473 __kvmclock_cpufreq_notifier(freq, cpu); 8474 8475 return 0; 8476 } 8477 8478 static struct notifier_block kvmclock_cpufreq_notifier_block = { 8479 .notifier_call = kvmclock_cpufreq_notifier 8480 }; 8481 8482 static int kvmclock_cpu_online(unsigned int cpu) 8483 { 8484 tsc_khz_changed(NULL); 8485 return 0; 8486 } 8487 8488 static void kvm_timer_init(void) 8489 { 8490 max_tsc_khz = tsc_khz; 8491 8492 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) { 8493 #ifdef CONFIG_CPU_FREQ 8494 struct cpufreq_policy *policy; 8495 int cpu; 8496 8497 cpu = get_cpu(); 8498 policy = cpufreq_cpu_get(cpu); 8499 if (policy) { 8500 if (policy->cpuinfo.max_freq) 8501 max_tsc_khz = policy->cpuinfo.max_freq; 8502 cpufreq_cpu_put(policy); 8503 } 8504 put_cpu(); 8505 #endif 8506 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block, 8507 CPUFREQ_TRANSITION_NOTIFIER); 8508 } 8509 8510 cpuhp_setup_state(CPUHP_AP_X86_KVM_CLK_ONLINE, "x86/kvm/clk:online", 8511 kvmclock_cpu_online, kvmclock_cpu_down_prep); 8512 } 8513 8514 DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu); 8515 EXPORT_PER_CPU_SYMBOL_GPL(current_vcpu); 8516 8517 int kvm_is_in_guest(void) 8518 { 8519 return __this_cpu_read(current_vcpu) != NULL; 8520 } 8521 8522 static int kvm_is_user_mode(void) 8523 { 8524 int user_mode = 3; 8525 8526 if (__this_cpu_read(current_vcpu)) 8527 user_mode = static_call(kvm_x86_get_cpl)(__this_cpu_read(current_vcpu)); 8528 8529 return user_mode != 0; 8530 } 8531 8532 static unsigned long kvm_get_guest_ip(void) 8533 { 8534 unsigned long ip = 0; 8535 8536 if (__this_cpu_read(current_vcpu)) 8537 ip = kvm_rip_read(__this_cpu_read(current_vcpu)); 8538 8539 return ip; 8540 } 8541 8542 static void kvm_handle_intel_pt_intr(void) 8543 { 8544 struct kvm_vcpu *vcpu = __this_cpu_read(current_vcpu); 8545 8546 kvm_make_request(KVM_REQ_PMI, vcpu); 8547 __set_bit(MSR_CORE_PERF_GLOBAL_OVF_CTRL_TRACE_TOPA_PMI_BIT, 8548 (unsigned long *)&vcpu->arch.pmu.global_status); 8549 } 8550 8551 static struct perf_guest_info_callbacks kvm_guest_cbs = { 8552 .is_in_guest = kvm_is_in_guest, 8553 .is_user_mode = kvm_is_user_mode, 8554 .get_guest_ip = kvm_get_guest_ip, 8555 .handle_intel_pt_intr = kvm_handle_intel_pt_intr, 8556 }; 8557 8558 #ifdef CONFIG_X86_64 8559 static void pvclock_gtod_update_fn(struct work_struct *work) 8560 { 8561 struct kvm *kvm; 8562 8563 struct kvm_vcpu *vcpu; 8564 int i; 8565 8566 mutex_lock(&kvm_lock); 8567 list_for_each_entry(kvm, &vm_list, vm_list) 8568 kvm_for_each_vcpu(i, vcpu, kvm) 8569 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu); 8570 atomic_set(&kvm_guest_has_master_clock, 0); 8571 mutex_unlock(&kvm_lock); 8572 } 8573 8574 static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn); 8575 8576 /* 8577 * Indirection to move queue_work() out of the tk_core.seq write held 8578 * region to prevent possible deadlocks against time accessors which 8579 * are invoked with work related locks held. 8580 */ 8581 static void pvclock_irq_work_fn(struct irq_work *w) 8582 { 8583 queue_work(system_long_wq, &pvclock_gtod_work); 8584 } 8585 8586 static DEFINE_IRQ_WORK(pvclock_irq_work, pvclock_irq_work_fn); 8587 8588 /* 8589 * Notification about pvclock gtod data update. 8590 */ 8591 static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused, 8592 void *priv) 8593 { 8594 struct pvclock_gtod_data *gtod = &pvclock_gtod_data; 8595 struct timekeeper *tk = priv; 8596 8597 update_pvclock_gtod(tk); 8598 8599 /* 8600 * Disable master clock if host does not trust, or does not use, 8601 * TSC based clocksource. Delegate queue_work() to irq_work as 8602 * this is invoked with tk_core.seq write held. 8603 */ 8604 if (!gtod_is_based_on_tsc(gtod->clock.vclock_mode) && 8605 atomic_read(&kvm_guest_has_master_clock) != 0) 8606 irq_work_queue(&pvclock_irq_work); 8607 return 0; 8608 } 8609 8610 static struct notifier_block pvclock_gtod_notifier = { 8611 .notifier_call = pvclock_gtod_notify, 8612 }; 8613 #endif 8614 8615 int kvm_arch_init(void *opaque) 8616 { 8617 struct kvm_x86_init_ops *ops = opaque; 8618 int r; 8619 8620 if (kvm_x86_ops.hardware_enable) { 8621 pr_err("kvm: already loaded vendor module '%s'\n", kvm_x86_ops.name); 8622 r = -EEXIST; 8623 goto out; 8624 } 8625 8626 if (!ops->cpu_has_kvm_support()) { 8627 pr_err_ratelimited("kvm: no hardware support for '%s'\n", 8628 ops->runtime_ops->name); 8629 r = -EOPNOTSUPP; 8630 goto out; 8631 } 8632 if (ops->disabled_by_bios()) { 8633 pr_err_ratelimited("kvm: support for '%s' disabled by bios\n", 8634 ops->runtime_ops->name); 8635 r = -EOPNOTSUPP; 8636 goto out; 8637 } 8638 8639 /* 8640 * KVM explicitly assumes that the guest has an FPU and 8641 * FXSAVE/FXRSTOR. For example, the KVM_GET_FPU explicitly casts the 8642 * vCPU's FPU state as a fxregs_state struct. 8643 */ 8644 if (!boot_cpu_has(X86_FEATURE_FPU) || !boot_cpu_has(X86_FEATURE_FXSR)) { 8645 printk(KERN_ERR "kvm: inadequate fpu\n"); 8646 r = -EOPNOTSUPP; 8647 goto out; 8648 } 8649 8650 r = -ENOMEM; 8651 8652 x86_emulator_cache = kvm_alloc_emulator_cache(); 8653 if (!x86_emulator_cache) { 8654 pr_err("kvm: failed to allocate cache for x86 emulator\n"); 8655 goto out; 8656 } 8657 8658 user_return_msrs = alloc_percpu(struct kvm_user_return_msrs); 8659 if (!user_return_msrs) { 8660 printk(KERN_ERR "kvm: failed to allocate percpu kvm_user_return_msrs\n"); 8661 goto out_free_x86_emulator_cache; 8662 } 8663 kvm_nr_uret_msrs = 0; 8664 8665 r = kvm_mmu_module_init(); 8666 if (r) 8667 goto out_free_percpu; 8668 8669 kvm_timer_init(); 8670 8671 perf_register_guest_info_callbacks(&kvm_guest_cbs); 8672 8673 if (boot_cpu_has(X86_FEATURE_XSAVE)) { 8674 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK); 8675 supported_xcr0 = host_xcr0 & KVM_SUPPORTED_XCR0; 8676 } 8677 8678 if (pi_inject_timer == -1) 8679 pi_inject_timer = housekeeping_enabled(HK_FLAG_TIMER); 8680 #ifdef CONFIG_X86_64 8681 pvclock_gtod_register_notifier(&pvclock_gtod_notifier); 8682 8683 if (hypervisor_is_type(X86_HYPER_MS_HYPERV)) 8684 set_hv_tscchange_cb(kvm_hyperv_tsc_notifier); 8685 #endif 8686 8687 return 0; 8688 8689 out_free_percpu: 8690 free_percpu(user_return_msrs); 8691 out_free_x86_emulator_cache: 8692 kmem_cache_destroy(x86_emulator_cache); 8693 out: 8694 return r; 8695 } 8696 8697 void kvm_arch_exit(void) 8698 { 8699 #ifdef CONFIG_X86_64 8700 if (hypervisor_is_type(X86_HYPER_MS_HYPERV)) 8701 clear_hv_tscchange_cb(); 8702 #endif 8703 kvm_lapic_exit(); 8704 perf_unregister_guest_info_callbacks(&kvm_guest_cbs); 8705 8706 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) 8707 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block, 8708 CPUFREQ_TRANSITION_NOTIFIER); 8709 cpuhp_remove_state_nocalls(CPUHP_AP_X86_KVM_CLK_ONLINE); 8710 #ifdef CONFIG_X86_64 8711 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier); 8712 irq_work_sync(&pvclock_irq_work); 8713 cancel_work_sync(&pvclock_gtod_work); 8714 #endif 8715 kvm_x86_ops.hardware_enable = NULL; 8716 kvm_mmu_module_exit(); 8717 free_percpu(user_return_msrs); 8718 kmem_cache_destroy(x86_emulator_cache); 8719 #ifdef CONFIG_KVM_XEN 8720 static_key_deferred_flush(&kvm_xen_enabled); 8721 WARN_ON(static_branch_unlikely(&kvm_xen_enabled.key)); 8722 #endif 8723 } 8724 8725 static int __kvm_vcpu_halt(struct kvm_vcpu *vcpu, int state, int reason) 8726 { 8727 ++vcpu->stat.halt_exits; 8728 if (lapic_in_kernel(vcpu)) { 8729 vcpu->arch.mp_state = state; 8730 return 1; 8731 } else { 8732 vcpu->run->exit_reason = reason; 8733 return 0; 8734 } 8735 } 8736 8737 int kvm_vcpu_halt(struct kvm_vcpu *vcpu) 8738 { 8739 return __kvm_vcpu_halt(vcpu, KVM_MP_STATE_HALTED, KVM_EXIT_HLT); 8740 } 8741 EXPORT_SYMBOL_GPL(kvm_vcpu_halt); 8742 8743 int kvm_emulate_halt(struct kvm_vcpu *vcpu) 8744 { 8745 int ret = kvm_skip_emulated_instruction(vcpu); 8746 /* 8747 * TODO: we might be squashing a GUESTDBG_SINGLESTEP-triggered 8748 * KVM_EXIT_DEBUG here. 8749 */ 8750 return kvm_vcpu_halt(vcpu) && ret; 8751 } 8752 EXPORT_SYMBOL_GPL(kvm_emulate_halt); 8753 8754 int kvm_emulate_ap_reset_hold(struct kvm_vcpu *vcpu) 8755 { 8756 int ret = kvm_skip_emulated_instruction(vcpu); 8757 8758 return __kvm_vcpu_halt(vcpu, KVM_MP_STATE_AP_RESET_HOLD, KVM_EXIT_AP_RESET_HOLD) && ret; 8759 } 8760 EXPORT_SYMBOL_GPL(kvm_emulate_ap_reset_hold); 8761 8762 #ifdef CONFIG_X86_64 8763 static int kvm_pv_clock_pairing(struct kvm_vcpu *vcpu, gpa_t paddr, 8764 unsigned long clock_type) 8765 { 8766 struct kvm_clock_pairing clock_pairing; 8767 struct timespec64 ts; 8768 u64 cycle; 8769 int ret; 8770 8771 if (clock_type != KVM_CLOCK_PAIRING_WALLCLOCK) 8772 return -KVM_EOPNOTSUPP; 8773 8774 if (!kvm_get_walltime_and_clockread(&ts, &cycle)) 8775 return -KVM_EOPNOTSUPP; 8776 8777 clock_pairing.sec = ts.tv_sec; 8778 clock_pairing.nsec = ts.tv_nsec; 8779 clock_pairing.tsc = kvm_read_l1_tsc(vcpu, cycle); 8780 clock_pairing.flags = 0; 8781 memset(&clock_pairing.pad, 0, sizeof(clock_pairing.pad)); 8782 8783 ret = 0; 8784 if (kvm_write_guest(vcpu->kvm, paddr, &clock_pairing, 8785 sizeof(struct kvm_clock_pairing))) 8786 ret = -KVM_EFAULT; 8787 8788 return ret; 8789 } 8790 #endif 8791 8792 /* 8793 * kvm_pv_kick_cpu_op: Kick a vcpu. 8794 * 8795 * @apicid - apicid of vcpu to be kicked. 8796 */ 8797 static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid) 8798 { 8799 struct kvm_lapic_irq lapic_irq; 8800 8801 lapic_irq.shorthand = APIC_DEST_NOSHORT; 8802 lapic_irq.dest_mode = APIC_DEST_PHYSICAL; 8803 lapic_irq.level = 0; 8804 lapic_irq.dest_id = apicid; 8805 lapic_irq.msi_redir_hint = false; 8806 8807 lapic_irq.delivery_mode = APIC_DM_REMRD; 8808 kvm_irq_delivery_to_apic(kvm, NULL, &lapic_irq, NULL); 8809 } 8810 8811 bool kvm_apicv_activated(struct kvm *kvm) 8812 { 8813 return (READ_ONCE(kvm->arch.apicv_inhibit_reasons) == 0); 8814 } 8815 EXPORT_SYMBOL_GPL(kvm_apicv_activated); 8816 8817 static void kvm_apicv_init(struct kvm *kvm) 8818 { 8819 init_rwsem(&kvm->arch.apicv_update_lock); 8820 8821 if (enable_apicv) 8822 clear_bit(APICV_INHIBIT_REASON_DISABLE, 8823 &kvm->arch.apicv_inhibit_reasons); 8824 else 8825 set_bit(APICV_INHIBIT_REASON_DISABLE, 8826 &kvm->arch.apicv_inhibit_reasons); 8827 } 8828 8829 static void kvm_sched_yield(struct kvm_vcpu *vcpu, unsigned long dest_id) 8830 { 8831 struct kvm_vcpu *target = NULL; 8832 struct kvm_apic_map *map; 8833 8834 vcpu->stat.directed_yield_attempted++; 8835 8836 if (single_task_running()) 8837 goto no_yield; 8838 8839 rcu_read_lock(); 8840 map = rcu_dereference(vcpu->kvm->arch.apic_map); 8841 8842 if (likely(map) && dest_id <= map->max_apic_id && map->phys_map[dest_id]) 8843 target = map->phys_map[dest_id]->vcpu; 8844 8845 rcu_read_unlock(); 8846 8847 if (!target || !READ_ONCE(target->ready)) 8848 goto no_yield; 8849 8850 /* Ignore requests to yield to self */ 8851 if (vcpu == target) 8852 goto no_yield; 8853 8854 if (kvm_vcpu_yield_to(target) <= 0) 8855 goto no_yield; 8856 8857 vcpu->stat.directed_yield_successful++; 8858 8859 no_yield: 8860 return; 8861 } 8862 8863 static int complete_hypercall_exit(struct kvm_vcpu *vcpu) 8864 { 8865 u64 ret = vcpu->run->hypercall.ret; 8866 8867 if (!is_64_bit_mode(vcpu)) 8868 ret = (u32)ret; 8869 kvm_rax_write(vcpu, ret); 8870 ++vcpu->stat.hypercalls; 8871 return kvm_skip_emulated_instruction(vcpu); 8872 } 8873 8874 int kvm_emulate_hypercall(struct kvm_vcpu *vcpu) 8875 { 8876 unsigned long nr, a0, a1, a2, a3, ret; 8877 int op_64_bit; 8878 8879 if (kvm_xen_hypercall_enabled(vcpu->kvm)) 8880 return kvm_xen_hypercall(vcpu); 8881 8882 if (kvm_hv_hypercall_enabled(vcpu)) 8883 return kvm_hv_hypercall(vcpu); 8884 8885 nr = kvm_rax_read(vcpu); 8886 a0 = kvm_rbx_read(vcpu); 8887 a1 = kvm_rcx_read(vcpu); 8888 a2 = kvm_rdx_read(vcpu); 8889 a3 = kvm_rsi_read(vcpu); 8890 8891 trace_kvm_hypercall(nr, a0, a1, a2, a3); 8892 8893 op_64_bit = is_64_bit_hypercall(vcpu); 8894 if (!op_64_bit) { 8895 nr &= 0xFFFFFFFF; 8896 a0 &= 0xFFFFFFFF; 8897 a1 &= 0xFFFFFFFF; 8898 a2 &= 0xFFFFFFFF; 8899 a3 &= 0xFFFFFFFF; 8900 } 8901 8902 if (static_call(kvm_x86_get_cpl)(vcpu) != 0) { 8903 ret = -KVM_EPERM; 8904 goto out; 8905 } 8906 8907 ret = -KVM_ENOSYS; 8908 8909 switch (nr) { 8910 case KVM_HC_VAPIC_POLL_IRQ: 8911 ret = 0; 8912 break; 8913 case KVM_HC_KICK_CPU: 8914 if (!guest_pv_has(vcpu, KVM_FEATURE_PV_UNHALT)) 8915 break; 8916 8917 kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1); 8918 kvm_sched_yield(vcpu, a1); 8919 ret = 0; 8920 break; 8921 #ifdef CONFIG_X86_64 8922 case KVM_HC_CLOCK_PAIRING: 8923 ret = kvm_pv_clock_pairing(vcpu, a0, a1); 8924 break; 8925 #endif 8926 case KVM_HC_SEND_IPI: 8927 if (!guest_pv_has(vcpu, KVM_FEATURE_PV_SEND_IPI)) 8928 break; 8929 8930 ret = kvm_pv_send_ipi(vcpu->kvm, a0, a1, a2, a3, op_64_bit); 8931 break; 8932 case KVM_HC_SCHED_YIELD: 8933 if (!guest_pv_has(vcpu, KVM_FEATURE_PV_SCHED_YIELD)) 8934 break; 8935 8936 kvm_sched_yield(vcpu, a0); 8937 ret = 0; 8938 break; 8939 case KVM_HC_MAP_GPA_RANGE: { 8940 u64 gpa = a0, npages = a1, attrs = a2; 8941 8942 ret = -KVM_ENOSYS; 8943 if (!(vcpu->kvm->arch.hypercall_exit_enabled & (1 << KVM_HC_MAP_GPA_RANGE))) 8944 break; 8945 8946 if (!PAGE_ALIGNED(gpa) || !npages || 8947 gpa_to_gfn(gpa) + npages <= gpa_to_gfn(gpa)) { 8948 ret = -KVM_EINVAL; 8949 break; 8950 } 8951 8952 vcpu->run->exit_reason = KVM_EXIT_HYPERCALL; 8953 vcpu->run->hypercall.nr = KVM_HC_MAP_GPA_RANGE; 8954 vcpu->run->hypercall.args[0] = gpa; 8955 vcpu->run->hypercall.args[1] = npages; 8956 vcpu->run->hypercall.args[2] = attrs; 8957 vcpu->run->hypercall.longmode = op_64_bit; 8958 vcpu->arch.complete_userspace_io = complete_hypercall_exit; 8959 return 0; 8960 } 8961 default: 8962 ret = -KVM_ENOSYS; 8963 break; 8964 } 8965 out: 8966 if (!op_64_bit) 8967 ret = (u32)ret; 8968 kvm_rax_write(vcpu, ret); 8969 8970 ++vcpu->stat.hypercalls; 8971 return kvm_skip_emulated_instruction(vcpu); 8972 } 8973 EXPORT_SYMBOL_GPL(kvm_emulate_hypercall); 8974 8975 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt) 8976 { 8977 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 8978 char instruction[3]; 8979 unsigned long rip = kvm_rip_read(vcpu); 8980 8981 static_call(kvm_x86_patch_hypercall)(vcpu, instruction); 8982 8983 return emulator_write_emulated(ctxt, rip, instruction, 3, 8984 &ctxt->exception); 8985 } 8986 8987 static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu) 8988 { 8989 return vcpu->run->request_interrupt_window && 8990 likely(!pic_in_kernel(vcpu->kvm)); 8991 } 8992 8993 static void post_kvm_run_save(struct kvm_vcpu *vcpu) 8994 { 8995 struct kvm_run *kvm_run = vcpu->run; 8996 8997 /* 8998 * if_flag is obsolete and useless, so do not bother 8999 * setting it for SEV-ES guests. Userspace can just 9000 * use kvm_run->ready_for_interrupt_injection. 9001 */ 9002 kvm_run->if_flag = !vcpu->arch.guest_state_protected 9003 && (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0; 9004 9005 kvm_run->cr8 = kvm_get_cr8(vcpu); 9006 kvm_run->apic_base = kvm_get_apic_base(vcpu); 9007 9008 /* 9009 * The call to kvm_ready_for_interrupt_injection() may end up in 9010 * kvm_xen_has_interrupt() which may require the srcu lock to be 9011 * held, to protect against changes in the vcpu_info address. 9012 */ 9013 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu); 9014 kvm_run->ready_for_interrupt_injection = 9015 pic_in_kernel(vcpu->kvm) || 9016 kvm_vcpu_ready_for_interrupt_injection(vcpu); 9017 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx); 9018 9019 if (is_smm(vcpu)) 9020 kvm_run->flags |= KVM_RUN_X86_SMM; 9021 } 9022 9023 static void update_cr8_intercept(struct kvm_vcpu *vcpu) 9024 { 9025 int max_irr, tpr; 9026 9027 if (!kvm_x86_ops.update_cr8_intercept) 9028 return; 9029 9030 if (!lapic_in_kernel(vcpu)) 9031 return; 9032 9033 if (vcpu->arch.apicv_active) 9034 return; 9035 9036 if (!vcpu->arch.apic->vapic_addr) 9037 max_irr = kvm_lapic_find_highest_irr(vcpu); 9038 else 9039 max_irr = -1; 9040 9041 if (max_irr != -1) 9042 max_irr >>= 4; 9043 9044 tpr = kvm_lapic_get_cr8(vcpu); 9045 9046 static_call(kvm_x86_update_cr8_intercept)(vcpu, tpr, max_irr); 9047 } 9048 9049 9050 int kvm_check_nested_events(struct kvm_vcpu *vcpu) 9051 { 9052 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) { 9053 kvm_x86_ops.nested_ops->triple_fault(vcpu); 9054 return 1; 9055 } 9056 9057 return kvm_x86_ops.nested_ops->check_events(vcpu); 9058 } 9059 9060 static void kvm_inject_exception(struct kvm_vcpu *vcpu) 9061 { 9062 if (vcpu->arch.exception.error_code && !is_protmode(vcpu)) 9063 vcpu->arch.exception.error_code = false; 9064 static_call(kvm_x86_queue_exception)(vcpu); 9065 } 9066 9067 static int inject_pending_event(struct kvm_vcpu *vcpu, bool *req_immediate_exit) 9068 { 9069 int r; 9070 bool can_inject = true; 9071 9072 /* try to reinject previous events if any */ 9073 9074 if (vcpu->arch.exception.injected) { 9075 kvm_inject_exception(vcpu); 9076 can_inject = false; 9077 } 9078 /* 9079 * Do not inject an NMI or interrupt if there is a pending 9080 * exception. Exceptions and interrupts are recognized at 9081 * instruction boundaries, i.e. the start of an instruction. 9082 * Trap-like exceptions, e.g. #DB, have higher priority than 9083 * NMIs and interrupts, i.e. traps are recognized before an 9084 * NMI/interrupt that's pending on the same instruction. 9085 * Fault-like exceptions, e.g. #GP and #PF, are the lowest 9086 * priority, but are only generated (pended) during instruction 9087 * execution, i.e. a pending fault-like exception means the 9088 * fault occurred on the *previous* instruction and must be 9089 * serviced prior to recognizing any new events in order to 9090 * fully complete the previous instruction. 9091 */ 9092 else if (!vcpu->arch.exception.pending) { 9093 if (vcpu->arch.nmi_injected) { 9094 static_call(kvm_x86_set_nmi)(vcpu); 9095 can_inject = false; 9096 } else if (vcpu->arch.interrupt.injected) { 9097 static_call(kvm_x86_set_irq)(vcpu); 9098 can_inject = false; 9099 } 9100 } 9101 9102 WARN_ON_ONCE(vcpu->arch.exception.injected && 9103 vcpu->arch.exception.pending); 9104 9105 /* 9106 * Call check_nested_events() even if we reinjected a previous event 9107 * in order for caller to determine if it should require immediate-exit 9108 * from L2 to L1 due to pending L1 events which require exit 9109 * from L2 to L1. 9110 */ 9111 if (is_guest_mode(vcpu)) { 9112 r = kvm_check_nested_events(vcpu); 9113 if (r < 0) 9114 goto out; 9115 } 9116 9117 /* try to inject new event if pending */ 9118 if (vcpu->arch.exception.pending) { 9119 trace_kvm_inj_exception(vcpu->arch.exception.nr, 9120 vcpu->arch.exception.has_error_code, 9121 vcpu->arch.exception.error_code); 9122 9123 vcpu->arch.exception.pending = false; 9124 vcpu->arch.exception.injected = true; 9125 9126 if (exception_type(vcpu->arch.exception.nr) == EXCPT_FAULT) 9127 __kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) | 9128 X86_EFLAGS_RF); 9129 9130 if (vcpu->arch.exception.nr == DB_VECTOR) { 9131 kvm_deliver_exception_payload(vcpu); 9132 if (vcpu->arch.dr7 & DR7_GD) { 9133 vcpu->arch.dr7 &= ~DR7_GD; 9134 kvm_update_dr7(vcpu); 9135 } 9136 } 9137 9138 kvm_inject_exception(vcpu); 9139 can_inject = false; 9140 } 9141 9142 /* Don't inject interrupts if the user asked to avoid doing so */ 9143 if (vcpu->guest_debug & KVM_GUESTDBG_BLOCKIRQ) 9144 return 0; 9145 9146 /* 9147 * Finally, inject interrupt events. If an event cannot be injected 9148 * due to architectural conditions (e.g. IF=0) a window-open exit 9149 * will re-request KVM_REQ_EVENT. Sometimes however an event is pending 9150 * and can architecturally be injected, but we cannot do it right now: 9151 * an interrupt could have arrived just now and we have to inject it 9152 * as a vmexit, or there could already an event in the queue, which is 9153 * indicated by can_inject. In that case we request an immediate exit 9154 * in order to make progress and get back here for another iteration. 9155 * The kvm_x86_ops hooks communicate this by returning -EBUSY. 9156 */ 9157 if (vcpu->arch.smi_pending) { 9158 r = can_inject ? static_call(kvm_x86_smi_allowed)(vcpu, true) : -EBUSY; 9159 if (r < 0) 9160 goto out; 9161 if (r) { 9162 vcpu->arch.smi_pending = false; 9163 ++vcpu->arch.smi_count; 9164 enter_smm(vcpu); 9165 can_inject = false; 9166 } else 9167 static_call(kvm_x86_enable_smi_window)(vcpu); 9168 } 9169 9170 if (vcpu->arch.nmi_pending) { 9171 r = can_inject ? static_call(kvm_x86_nmi_allowed)(vcpu, true) : -EBUSY; 9172 if (r < 0) 9173 goto out; 9174 if (r) { 9175 --vcpu->arch.nmi_pending; 9176 vcpu->arch.nmi_injected = true; 9177 static_call(kvm_x86_set_nmi)(vcpu); 9178 can_inject = false; 9179 WARN_ON(static_call(kvm_x86_nmi_allowed)(vcpu, true) < 0); 9180 } 9181 if (vcpu->arch.nmi_pending) 9182 static_call(kvm_x86_enable_nmi_window)(vcpu); 9183 } 9184 9185 if (kvm_cpu_has_injectable_intr(vcpu)) { 9186 r = can_inject ? static_call(kvm_x86_interrupt_allowed)(vcpu, true) : -EBUSY; 9187 if (r < 0) 9188 goto out; 9189 if (r) { 9190 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu), false); 9191 static_call(kvm_x86_set_irq)(vcpu); 9192 WARN_ON(static_call(kvm_x86_interrupt_allowed)(vcpu, true) < 0); 9193 } 9194 if (kvm_cpu_has_injectable_intr(vcpu)) 9195 static_call(kvm_x86_enable_irq_window)(vcpu); 9196 } 9197 9198 if (is_guest_mode(vcpu) && 9199 kvm_x86_ops.nested_ops->hv_timer_pending && 9200 kvm_x86_ops.nested_ops->hv_timer_pending(vcpu)) 9201 *req_immediate_exit = true; 9202 9203 WARN_ON(vcpu->arch.exception.pending); 9204 return 0; 9205 9206 out: 9207 if (r == -EBUSY) { 9208 *req_immediate_exit = true; 9209 r = 0; 9210 } 9211 return r; 9212 } 9213 9214 static void process_nmi(struct kvm_vcpu *vcpu) 9215 { 9216 unsigned limit = 2; 9217 9218 /* 9219 * x86 is limited to one NMI running, and one NMI pending after it. 9220 * If an NMI is already in progress, limit further NMIs to just one. 9221 * Otherwise, allow two (and we'll inject the first one immediately). 9222 */ 9223 if (static_call(kvm_x86_get_nmi_mask)(vcpu) || vcpu->arch.nmi_injected) 9224 limit = 1; 9225 9226 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0); 9227 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit); 9228 kvm_make_request(KVM_REQ_EVENT, vcpu); 9229 } 9230 9231 static u32 enter_smm_get_segment_flags(struct kvm_segment *seg) 9232 { 9233 u32 flags = 0; 9234 flags |= seg->g << 23; 9235 flags |= seg->db << 22; 9236 flags |= seg->l << 21; 9237 flags |= seg->avl << 20; 9238 flags |= seg->present << 15; 9239 flags |= seg->dpl << 13; 9240 flags |= seg->s << 12; 9241 flags |= seg->type << 8; 9242 return flags; 9243 } 9244 9245 static void enter_smm_save_seg_32(struct kvm_vcpu *vcpu, char *buf, int n) 9246 { 9247 struct kvm_segment seg; 9248 int offset; 9249 9250 kvm_get_segment(vcpu, &seg, n); 9251 put_smstate(u32, buf, 0x7fa8 + n * 4, seg.selector); 9252 9253 if (n < 3) 9254 offset = 0x7f84 + n * 12; 9255 else 9256 offset = 0x7f2c + (n - 3) * 12; 9257 9258 put_smstate(u32, buf, offset + 8, seg.base); 9259 put_smstate(u32, buf, offset + 4, seg.limit); 9260 put_smstate(u32, buf, offset, enter_smm_get_segment_flags(&seg)); 9261 } 9262 9263 #ifdef CONFIG_X86_64 9264 static void enter_smm_save_seg_64(struct kvm_vcpu *vcpu, char *buf, int n) 9265 { 9266 struct kvm_segment seg; 9267 int offset; 9268 u16 flags; 9269 9270 kvm_get_segment(vcpu, &seg, n); 9271 offset = 0x7e00 + n * 16; 9272 9273 flags = enter_smm_get_segment_flags(&seg) >> 8; 9274 put_smstate(u16, buf, offset, seg.selector); 9275 put_smstate(u16, buf, offset + 2, flags); 9276 put_smstate(u32, buf, offset + 4, seg.limit); 9277 put_smstate(u64, buf, offset + 8, seg.base); 9278 } 9279 #endif 9280 9281 static void enter_smm_save_state_32(struct kvm_vcpu *vcpu, char *buf) 9282 { 9283 struct desc_ptr dt; 9284 struct kvm_segment seg; 9285 unsigned long val; 9286 int i; 9287 9288 put_smstate(u32, buf, 0x7ffc, kvm_read_cr0(vcpu)); 9289 put_smstate(u32, buf, 0x7ff8, kvm_read_cr3(vcpu)); 9290 put_smstate(u32, buf, 0x7ff4, kvm_get_rflags(vcpu)); 9291 put_smstate(u32, buf, 0x7ff0, kvm_rip_read(vcpu)); 9292 9293 for (i = 0; i < 8; i++) 9294 put_smstate(u32, buf, 0x7fd0 + i * 4, kvm_register_read_raw(vcpu, i)); 9295 9296 kvm_get_dr(vcpu, 6, &val); 9297 put_smstate(u32, buf, 0x7fcc, (u32)val); 9298 kvm_get_dr(vcpu, 7, &val); 9299 put_smstate(u32, buf, 0x7fc8, (u32)val); 9300 9301 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR); 9302 put_smstate(u32, buf, 0x7fc4, seg.selector); 9303 put_smstate(u32, buf, 0x7f64, seg.base); 9304 put_smstate(u32, buf, 0x7f60, seg.limit); 9305 put_smstate(u32, buf, 0x7f5c, enter_smm_get_segment_flags(&seg)); 9306 9307 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR); 9308 put_smstate(u32, buf, 0x7fc0, seg.selector); 9309 put_smstate(u32, buf, 0x7f80, seg.base); 9310 put_smstate(u32, buf, 0x7f7c, seg.limit); 9311 put_smstate(u32, buf, 0x7f78, enter_smm_get_segment_flags(&seg)); 9312 9313 static_call(kvm_x86_get_gdt)(vcpu, &dt); 9314 put_smstate(u32, buf, 0x7f74, dt.address); 9315 put_smstate(u32, buf, 0x7f70, dt.size); 9316 9317 static_call(kvm_x86_get_idt)(vcpu, &dt); 9318 put_smstate(u32, buf, 0x7f58, dt.address); 9319 put_smstate(u32, buf, 0x7f54, dt.size); 9320 9321 for (i = 0; i < 6; i++) 9322 enter_smm_save_seg_32(vcpu, buf, i); 9323 9324 put_smstate(u32, buf, 0x7f14, kvm_read_cr4(vcpu)); 9325 9326 /* revision id */ 9327 put_smstate(u32, buf, 0x7efc, 0x00020000); 9328 put_smstate(u32, buf, 0x7ef8, vcpu->arch.smbase); 9329 } 9330 9331 #ifdef CONFIG_X86_64 9332 static void enter_smm_save_state_64(struct kvm_vcpu *vcpu, char *buf) 9333 { 9334 struct desc_ptr dt; 9335 struct kvm_segment seg; 9336 unsigned long val; 9337 int i; 9338 9339 for (i = 0; i < 16; i++) 9340 put_smstate(u64, buf, 0x7ff8 - i * 8, kvm_register_read_raw(vcpu, i)); 9341 9342 put_smstate(u64, buf, 0x7f78, kvm_rip_read(vcpu)); 9343 put_smstate(u32, buf, 0x7f70, kvm_get_rflags(vcpu)); 9344 9345 kvm_get_dr(vcpu, 6, &val); 9346 put_smstate(u64, buf, 0x7f68, val); 9347 kvm_get_dr(vcpu, 7, &val); 9348 put_smstate(u64, buf, 0x7f60, val); 9349 9350 put_smstate(u64, buf, 0x7f58, kvm_read_cr0(vcpu)); 9351 put_smstate(u64, buf, 0x7f50, kvm_read_cr3(vcpu)); 9352 put_smstate(u64, buf, 0x7f48, kvm_read_cr4(vcpu)); 9353 9354 put_smstate(u32, buf, 0x7f00, vcpu->arch.smbase); 9355 9356 /* revision id */ 9357 put_smstate(u32, buf, 0x7efc, 0x00020064); 9358 9359 put_smstate(u64, buf, 0x7ed0, vcpu->arch.efer); 9360 9361 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR); 9362 put_smstate(u16, buf, 0x7e90, seg.selector); 9363 put_smstate(u16, buf, 0x7e92, enter_smm_get_segment_flags(&seg) >> 8); 9364 put_smstate(u32, buf, 0x7e94, seg.limit); 9365 put_smstate(u64, buf, 0x7e98, seg.base); 9366 9367 static_call(kvm_x86_get_idt)(vcpu, &dt); 9368 put_smstate(u32, buf, 0x7e84, dt.size); 9369 put_smstate(u64, buf, 0x7e88, dt.address); 9370 9371 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR); 9372 put_smstate(u16, buf, 0x7e70, seg.selector); 9373 put_smstate(u16, buf, 0x7e72, enter_smm_get_segment_flags(&seg) >> 8); 9374 put_smstate(u32, buf, 0x7e74, seg.limit); 9375 put_smstate(u64, buf, 0x7e78, seg.base); 9376 9377 static_call(kvm_x86_get_gdt)(vcpu, &dt); 9378 put_smstate(u32, buf, 0x7e64, dt.size); 9379 put_smstate(u64, buf, 0x7e68, dt.address); 9380 9381 for (i = 0; i < 6; i++) 9382 enter_smm_save_seg_64(vcpu, buf, i); 9383 } 9384 #endif 9385 9386 static void enter_smm(struct kvm_vcpu *vcpu) 9387 { 9388 struct kvm_segment cs, ds; 9389 struct desc_ptr dt; 9390 unsigned long cr0; 9391 char buf[512]; 9392 9393 memset(buf, 0, 512); 9394 #ifdef CONFIG_X86_64 9395 if (guest_cpuid_has(vcpu, X86_FEATURE_LM)) 9396 enter_smm_save_state_64(vcpu, buf); 9397 else 9398 #endif 9399 enter_smm_save_state_32(vcpu, buf); 9400 9401 /* 9402 * Give enter_smm() a chance to make ISA-specific changes to the vCPU 9403 * state (e.g. leave guest mode) after we've saved the state into the 9404 * SMM state-save area. 9405 */ 9406 static_call(kvm_x86_enter_smm)(vcpu, buf); 9407 9408 kvm_smm_changed(vcpu, true); 9409 kvm_vcpu_write_guest(vcpu, vcpu->arch.smbase + 0xfe00, buf, sizeof(buf)); 9410 9411 if (static_call(kvm_x86_get_nmi_mask)(vcpu)) 9412 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK; 9413 else 9414 static_call(kvm_x86_set_nmi_mask)(vcpu, true); 9415 9416 kvm_set_rflags(vcpu, X86_EFLAGS_FIXED); 9417 kvm_rip_write(vcpu, 0x8000); 9418 9419 cr0 = vcpu->arch.cr0 & ~(X86_CR0_PE | X86_CR0_EM | X86_CR0_TS | X86_CR0_PG); 9420 static_call(kvm_x86_set_cr0)(vcpu, cr0); 9421 vcpu->arch.cr0 = cr0; 9422 9423 static_call(kvm_x86_set_cr4)(vcpu, 0); 9424 9425 /* Undocumented: IDT limit is set to zero on entry to SMM. */ 9426 dt.address = dt.size = 0; 9427 static_call(kvm_x86_set_idt)(vcpu, &dt); 9428 9429 kvm_set_dr(vcpu, 7, DR7_FIXED_1); 9430 9431 cs.selector = (vcpu->arch.smbase >> 4) & 0xffff; 9432 cs.base = vcpu->arch.smbase; 9433 9434 ds.selector = 0; 9435 ds.base = 0; 9436 9437 cs.limit = ds.limit = 0xffffffff; 9438 cs.type = ds.type = 0x3; 9439 cs.dpl = ds.dpl = 0; 9440 cs.db = ds.db = 0; 9441 cs.s = ds.s = 1; 9442 cs.l = ds.l = 0; 9443 cs.g = ds.g = 1; 9444 cs.avl = ds.avl = 0; 9445 cs.present = ds.present = 1; 9446 cs.unusable = ds.unusable = 0; 9447 cs.padding = ds.padding = 0; 9448 9449 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS); 9450 kvm_set_segment(vcpu, &ds, VCPU_SREG_DS); 9451 kvm_set_segment(vcpu, &ds, VCPU_SREG_ES); 9452 kvm_set_segment(vcpu, &ds, VCPU_SREG_FS); 9453 kvm_set_segment(vcpu, &ds, VCPU_SREG_GS); 9454 kvm_set_segment(vcpu, &ds, VCPU_SREG_SS); 9455 9456 #ifdef CONFIG_X86_64 9457 if (guest_cpuid_has(vcpu, X86_FEATURE_LM)) 9458 static_call(kvm_x86_set_efer)(vcpu, 0); 9459 #endif 9460 9461 kvm_update_cpuid_runtime(vcpu); 9462 kvm_mmu_reset_context(vcpu); 9463 } 9464 9465 static void process_smi(struct kvm_vcpu *vcpu) 9466 { 9467 vcpu->arch.smi_pending = true; 9468 kvm_make_request(KVM_REQ_EVENT, vcpu); 9469 } 9470 9471 void kvm_make_scan_ioapic_request_mask(struct kvm *kvm, 9472 unsigned long *vcpu_bitmap) 9473 { 9474 kvm_make_vcpus_request_mask(kvm, KVM_REQ_SCAN_IOAPIC, vcpu_bitmap); 9475 } 9476 9477 void kvm_make_scan_ioapic_request(struct kvm *kvm) 9478 { 9479 kvm_make_all_cpus_request(kvm, KVM_REQ_SCAN_IOAPIC); 9480 } 9481 9482 void kvm_vcpu_update_apicv(struct kvm_vcpu *vcpu) 9483 { 9484 bool activate; 9485 9486 if (!lapic_in_kernel(vcpu)) 9487 return; 9488 9489 down_read(&vcpu->kvm->arch.apicv_update_lock); 9490 9491 activate = kvm_apicv_activated(vcpu->kvm); 9492 if (vcpu->arch.apicv_active == activate) 9493 goto out; 9494 9495 vcpu->arch.apicv_active = activate; 9496 kvm_apic_update_apicv(vcpu); 9497 static_call(kvm_x86_refresh_apicv_exec_ctrl)(vcpu); 9498 9499 /* 9500 * When APICv gets disabled, we may still have injected interrupts 9501 * pending. At the same time, KVM_REQ_EVENT may not be set as APICv was 9502 * still active when the interrupt got accepted. Make sure 9503 * inject_pending_event() is called to check for that. 9504 */ 9505 if (!vcpu->arch.apicv_active) 9506 kvm_make_request(KVM_REQ_EVENT, vcpu); 9507 9508 out: 9509 up_read(&vcpu->kvm->arch.apicv_update_lock); 9510 } 9511 EXPORT_SYMBOL_GPL(kvm_vcpu_update_apicv); 9512 9513 void __kvm_request_apicv_update(struct kvm *kvm, bool activate, ulong bit) 9514 { 9515 unsigned long old, new; 9516 9517 lockdep_assert_held_write(&kvm->arch.apicv_update_lock); 9518 9519 if (!kvm_x86_ops.check_apicv_inhibit_reasons || 9520 !static_call(kvm_x86_check_apicv_inhibit_reasons)(bit)) 9521 return; 9522 9523 old = new = kvm->arch.apicv_inhibit_reasons; 9524 9525 if (activate) 9526 __clear_bit(bit, &new); 9527 else 9528 __set_bit(bit, &new); 9529 9530 if (!!old != !!new) { 9531 trace_kvm_apicv_update_request(activate, bit); 9532 /* 9533 * Kick all vCPUs before setting apicv_inhibit_reasons to avoid 9534 * false positives in the sanity check WARN in svm_vcpu_run(). 9535 * This task will wait for all vCPUs to ack the kick IRQ before 9536 * updating apicv_inhibit_reasons, and all other vCPUs will 9537 * block on acquiring apicv_update_lock so that vCPUs can't 9538 * redo svm_vcpu_run() without seeing the new inhibit state. 9539 * 9540 * Note, holding apicv_update_lock and taking it in the read 9541 * side (handling the request) also prevents other vCPUs from 9542 * servicing the request with a stale apicv_inhibit_reasons. 9543 */ 9544 kvm_make_all_cpus_request(kvm, KVM_REQ_APICV_UPDATE); 9545 kvm->arch.apicv_inhibit_reasons = new; 9546 if (new) { 9547 unsigned long gfn = gpa_to_gfn(APIC_DEFAULT_PHYS_BASE); 9548 kvm_zap_gfn_range(kvm, gfn, gfn+1); 9549 } 9550 } else 9551 kvm->arch.apicv_inhibit_reasons = new; 9552 } 9553 EXPORT_SYMBOL_GPL(__kvm_request_apicv_update); 9554 9555 void kvm_request_apicv_update(struct kvm *kvm, bool activate, ulong bit) 9556 { 9557 down_write(&kvm->arch.apicv_update_lock); 9558 __kvm_request_apicv_update(kvm, activate, bit); 9559 up_write(&kvm->arch.apicv_update_lock); 9560 } 9561 EXPORT_SYMBOL_GPL(kvm_request_apicv_update); 9562 9563 static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu) 9564 { 9565 if (!kvm_apic_present(vcpu)) 9566 return; 9567 9568 bitmap_zero(vcpu->arch.ioapic_handled_vectors, 256); 9569 9570 if (irqchip_split(vcpu->kvm)) 9571 kvm_scan_ioapic_routes(vcpu, vcpu->arch.ioapic_handled_vectors); 9572 else { 9573 static_call_cond(kvm_x86_sync_pir_to_irr)(vcpu); 9574 if (ioapic_in_kernel(vcpu->kvm)) 9575 kvm_ioapic_scan_entry(vcpu, vcpu->arch.ioapic_handled_vectors); 9576 } 9577 9578 if (is_guest_mode(vcpu)) 9579 vcpu->arch.load_eoi_exitmap_pending = true; 9580 else 9581 kvm_make_request(KVM_REQ_LOAD_EOI_EXITMAP, vcpu); 9582 } 9583 9584 static void vcpu_load_eoi_exitmap(struct kvm_vcpu *vcpu) 9585 { 9586 u64 eoi_exit_bitmap[4]; 9587 9588 if (!kvm_apic_hw_enabled(vcpu->arch.apic)) 9589 return; 9590 9591 if (to_hv_vcpu(vcpu)) { 9592 bitmap_or((ulong *)eoi_exit_bitmap, 9593 vcpu->arch.ioapic_handled_vectors, 9594 to_hv_synic(vcpu)->vec_bitmap, 256); 9595 static_call(kvm_x86_load_eoi_exitmap)(vcpu, eoi_exit_bitmap); 9596 return; 9597 } 9598 9599 static_call(kvm_x86_load_eoi_exitmap)( 9600 vcpu, (u64 *)vcpu->arch.ioapic_handled_vectors); 9601 } 9602 9603 void kvm_arch_mmu_notifier_invalidate_range(struct kvm *kvm, 9604 unsigned long start, unsigned long end) 9605 { 9606 unsigned long apic_address; 9607 9608 /* 9609 * The physical address of apic access page is stored in the VMCS. 9610 * Update it when it becomes invalid. 9611 */ 9612 apic_address = gfn_to_hva(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT); 9613 if (start <= apic_address && apic_address < end) 9614 kvm_make_all_cpus_request(kvm, KVM_REQ_APIC_PAGE_RELOAD); 9615 } 9616 9617 void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu) 9618 { 9619 if (!lapic_in_kernel(vcpu)) 9620 return; 9621 9622 if (!kvm_x86_ops.set_apic_access_page_addr) 9623 return; 9624 9625 static_call(kvm_x86_set_apic_access_page_addr)(vcpu); 9626 } 9627 9628 void __kvm_request_immediate_exit(struct kvm_vcpu *vcpu) 9629 { 9630 smp_send_reschedule(vcpu->cpu); 9631 } 9632 EXPORT_SYMBOL_GPL(__kvm_request_immediate_exit); 9633 9634 /* 9635 * Returns 1 to let vcpu_run() continue the guest execution loop without 9636 * exiting to the userspace. Otherwise, the value will be returned to the 9637 * userspace. 9638 */ 9639 static int vcpu_enter_guest(struct kvm_vcpu *vcpu) 9640 { 9641 int r; 9642 bool req_int_win = 9643 dm_request_for_irq_injection(vcpu) && 9644 kvm_cpu_accept_dm_intr(vcpu); 9645 fastpath_t exit_fastpath; 9646 9647 bool req_immediate_exit = false; 9648 9649 /* Forbid vmenter if vcpu dirty ring is soft-full */ 9650 if (unlikely(vcpu->kvm->dirty_ring_size && 9651 kvm_dirty_ring_soft_full(&vcpu->dirty_ring))) { 9652 vcpu->run->exit_reason = KVM_EXIT_DIRTY_RING_FULL; 9653 trace_kvm_dirty_ring_exit(vcpu); 9654 r = 0; 9655 goto out; 9656 } 9657 9658 if (kvm_request_pending(vcpu)) { 9659 if (kvm_check_request(KVM_REQ_VM_DEAD, vcpu)) { 9660 r = -EIO; 9661 goto out; 9662 } 9663 if (kvm_check_request(KVM_REQ_GET_NESTED_STATE_PAGES, vcpu)) { 9664 if (unlikely(!kvm_x86_ops.nested_ops->get_nested_state_pages(vcpu))) { 9665 r = 0; 9666 goto out; 9667 } 9668 } 9669 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu)) 9670 kvm_mmu_unload(vcpu); 9671 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu)) 9672 __kvm_migrate_timers(vcpu); 9673 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu)) 9674 kvm_update_masterclock(vcpu->kvm); 9675 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu)) 9676 kvm_gen_kvmclock_update(vcpu); 9677 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) { 9678 r = kvm_guest_time_update(vcpu); 9679 if (unlikely(r)) 9680 goto out; 9681 } 9682 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu)) 9683 kvm_mmu_sync_roots(vcpu); 9684 if (kvm_check_request(KVM_REQ_LOAD_MMU_PGD, vcpu)) 9685 kvm_mmu_load_pgd(vcpu); 9686 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu)) { 9687 kvm_vcpu_flush_tlb_all(vcpu); 9688 9689 /* Flushing all ASIDs flushes the current ASID... */ 9690 kvm_clear_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu); 9691 } 9692 kvm_service_local_tlb_flush_requests(vcpu); 9693 9694 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) { 9695 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS; 9696 r = 0; 9697 goto out; 9698 } 9699 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) { 9700 if (is_guest_mode(vcpu)) { 9701 kvm_x86_ops.nested_ops->triple_fault(vcpu); 9702 } else { 9703 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN; 9704 vcpu->mmio_needed = 0; 9705 r = 0; 9706 goto out; 9707 } 9708 } 9709 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) { 9710 /* Page is swapped out. Do synthetic halt */ 9711 vcpu->arch.apf.halted = true; 9712 r = 1; 9713 goto out; 9714 } 9715 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu)) 9716 record_steal_time(vcpu); 9717 if (kvm_check_request(KVM_REQ_SMI, vcpu)) 9718 process_smi(vcpu); 9719 if (kvm_check_request(KVM_REQ_NMI, vcpu)) 9720 process_nmi(vcpu); 9721 if (kvm_check_request(KVM_REQ_PMU, vcpu)) 9722 kvm_pmu_handle_event(vcpu); 9723 if (kvm_check_request(KVM_REQ_PMI, vcpu)) 9724 kvm_pmu_deliver_pmi(vcpu); 9725 if (kvm_check_request(KVM_REQ_IOAPIC_EOI_EXIT, vcpu)) { 9726 BUG_ON(vcpu->arch.pending_ioapic_eoi > 255); 9727 if (test_bit(vcpu->arch.pending_ioapic_eoi, 9728 vcpu->arch.ioapic_handled_vectors)) { 9729 vcpu->run->exit_reason = KVM_EXIT_IOAPIC_EOI; 9730 vcpu->run->eoi.vector = 9731 vcpu->arch.pending_ioapic_eoi; 9732 r = 0; 9733 goto out; 9734 } 9735 } 9736 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu)) 9737 vcpu_scan_ioapic(vcpu); 9738 if (kvm_check_request(KVM_REQ_LOAD_EOI_EXITMAP, vcpu)) 9739 vcpu_load_eoi_exitmap(vcpu); 9740 if (kvm_check_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu)) 9741 kvm_vcpu_reload_apic_access_page(vcpu); 9742 if (kvm_check_request(KVM_REQ_HV_CRASH, vcpu)) { 9743 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT; 9744 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_CRASH; 9745 r = 0; 9746 goto out; 9747 } 9748 if (kvm_check_request(KVM_REQ_HV_RESET, vcpu)) { 9749 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT; 9750 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_RESET; 9751 r = 0; 9752 goto out; 9753 } 9754 if (kvm_check_request(KVM_REQ_HV_EXIT, vcpu)) { 9755 struct kvm_vcpu_hv *hv_vcpu = to_hv_vcpu(vcpu); 9756 9757 vcpu->run->exit_reason = KVM_EXIT_HYPERV; 9758 vcpu->run->hyperv = hv_vcpu->exit; 9759 r = 0; 9760 goto out; 9761 } 9762 9763 /* 9764 * KVM_REQ_HV_STIMER has to be processed after 9765 * KVM_REQ_CLOCK_UPDATE, because Hyper-V SynIC timers 9766 * depend on the guest clock being up-to-date 9767 */ 9768 if (kvm_check_request(KVM_REQ_HV_STIMER, vcpu)) 9769 kvm_hv_process_stimers(vcpu); 9770 if (kvm_check_request(KVM_REQ_APICV_UPDATE, vcpu)) 9771 kvm_vcpu_update_apicv(vcpu); 9772 if (kvm_check_request(KVM_REQ_APF_READY, vcpu)) 9773 kvm_check_async_pf_completion(vcpu); 9774 if (kvm_check_request(KVM_REQ_MSR_FILTER_CHANGED, vcpu)) 9775 static_call(kvm_x86_msr_filter_changed)(vcpu); 9776 9777 if (kvm_check_request(KVM_REQ_UPDATE_CPU_DIRTY_LOGGING, vcpu)) 9778 static_call(kvm_x86_update_cpu_dirty_logging)(vcpu); 9779 } 9780 9781 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win || 9782 kvm_xen_has_interrupt(vcpu)) { 9783 ++vcpu->stat.req_event; 9784 r = kvm_apic_accept_events(vcpu); 9785 if (r < 0) { 9786 r = 0; 9787 goto out; 9788 } 9789 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) { 9790 r = 1; 9791 goto out; 9792 } 9793 9794 r = inject_pending_event(vcpu, &req_immediate_exit); 9795 if (r < 0) { 9796 r = 0; 9797 goto out; 9798 } 9799 if (req_int_win) 9800 static_call(kvm_x86_enable_irq_window)(vcpu); 9801 9802 if (kvm_lapic_enabled(vcpu)) { 9803 update_cr8_intercept(vcpu); 9804 kvm_lapic_sync_to_vapic(vcpu); 9805 } 9806 } 9807 9808 r = kvm_mmu_reload(vcpu); 9809 if (unlikely(r)) { 9810 goto cancel_injection; 9811 } 9812 9813 preempt_disable(); 9814 9815 static_call(kvm_x86_prepare_guest_switch)(vcpu); 9816 9817 /* 9818 * Disable IRQs before setting IN_GUEST_MODE. Posted interrupt 9819 * IPI are then delayed after guest entry, which ensures that they 9820 * result in virtual interrupt delivery. 9821 */ 9822 local_irq_disable(); 9823 vcpu->mode = IN_GUEST_MODE; 9824 9825 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx); 9826 9827 /* 9828 * 1) We should set ->mode before checking ->requests. Please see 9829 * the comment in kvm_vcpu_exiting_guest_mode(). 9830 * 9831 * 2) For APICv, we should set ->mode before checking PID.ON. This 9832 * pairs with the memory barrier implicit in pi_test_and_set_on 9833 * (see vmx_deliver_posted_interrupt). 9834 * 9835 * 3) This also orders the write to mode from any reads to the page 9836 * tables done while the VCPU is running. Please see the comment 9837 * in kvm_flush_remote_tlbs. 9838 */ 9839 smp_mb__after_srcu_read_unlock(); 9840 9841 /* 9842 * This handles the case where a posted interrupt was 9843 * notified with kvm_vcpu_kick. Assigned devices can 9844 * use the POSTED_INTR_VECTOR even if APICv is disabled, 9845 * so do it even if APICv is disabled on this vCPU. 9846 */ 9847 if (kvm_lapic_enabled(vcpu)) 9848 static_call_cond(kvm_x86_sync_pir_to_irr)(vcpu); 9849 9850 if (kvm_vcpu_exit_request(vcpu)) { 9851 vcpu->mode = OUTSIDE_GUEST_MODE; 9852 smp_wmb(); 9853 local_irq_enable(); 9854 preempt_enable(); 9855 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu); 9856 r = 1; 9857 goto cancel_injection; 9858 } 9859 9860 if (req_immediate_exit) { 9861 kvm_make_request(KVM_REQ_EVENT, vcpu); 9862 static_call(kvm_x86_request_immediate_exit)(vcpu); 9863 } 9864 9865 fpregs_assert_state_consistent(); 9866 if (test_thread_flag(TIF_NEED_FPU_LOAD)) 9867 switch_fpu_return(); 9868 9869 if (unlikely(vcpu->arch.switch_db_regs)) { 9870 set_debugreg(0, 7); 9871 set_debugreg(vcpu->arch.eff_db[0], 0); 9872 set_debugreg(vcpu->arch.eff_db[1], 1); 9873 set_debugreg(vcpu->arch.eff_db[2], 2); 9874 set_debugreg(vcpu->arch.eff_db[3], 3); 9875 } else if (unlikely(hw_breakpoint_active())) { 9876 set_debugreg(0, 7); 9877 } 9878 9879 for (;;) { 9880 /* 9881 * Assert that vCPU vs. VM APICv state is consistent. An APICv 9882 * update must kick and wait for all vCPUs before toggling the 9883 * per-VM state, and responsing vCPUs must wait for the update 9884 * to complete before servicing KVM_REQ_APICV_UPDATE. 9885 */ 9886 WARN_ON_ONCE(kvm_apicv_activated(vcpu->kvm) != kvm_vcpu_apicv_active(vcpu)); 9887 9888 exit_fastpath = static_call(kvm_x86_run)(vcpu); 9889 if (likely(exit_fastpath != EXIT_FASTPATH_REENTER_GUEST)) 9890 break; 9891 9892 if (kvm_lapic_enabled(vcpu)) 9893 static_call_cond(kvm_x86_sync_pir_to_irr)(vcpu); 9894 9895 if (unlikely(kvm_vcpu_exit_request(vcpu))) { 9896 exit_fastpath = EXIT_FASTPATH_EXIT_HANDLED; 9897 break; 9898 } 9899 } 9900 9901 /* 9902 * Do this here before restoring debug registers on the host. And 9903 * since we do this before handling the vmexit, a DR access vmexit 9904 * can (a) read the correct value of the debug registers, (b) set 9905 * KVM_DEBUGREG_WONT_EXIT again. 9906 */ 9907 if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) { 9908 WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP); 9909 static_call(kvm_x86_sync_dirty_debug_regs)(vcpu); 9910 kvm_update_dr0123(vcpu); 9911 kvm_update_dr7(vcpu); 9912 } 9913 9914 /* 9915 * If the guest has used debug registers, at least dr7 9916 * will be disabled while returning to the host. 9917 * If we don't have active breakpoints in the host, we don't 9918 * care about the messed up debug address registers. But if 9919 * we have some of them active, restore the old state. 9920 */ 9921 if (hw_breakpoint_active()) 9922 hw_breakpoint_restore(); 9923 9924 vcpu->arch.last_vmentry_cpu = vcpu->cpu; 9925 vcpu->arch.last_guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc()); 9926 9927 vcpu->mode = OUTSIDE_GUEST_MODE; 9928 smp_wmb(); 9929 9930 static_call(kvm_x86_handle_exit_irqoff)(vcpu); 9931 9932 /* 9933 * Consume any pending interrupts, including the possible source of 9934 * VM-Exit on SVM and any ticks that occur between VM-Exit and now. 9935 * An instruction is required after local_irq_enable() to fully unblock 9936 * interrupts on processors that implement an interrupt shadow, the 9937 * stat.exits increment will do nicely. 9938 */ 9939 kvm_before_interrupt(vcpu); 9940 local_irq_enable(); 9941 ++vcpu->stat.exits; 9942 local_irq_disable(); 9943 kvm_after_interrupt(vcpu); 9944 9945 /* 9946 * Wait until after servicing IRQs to account guest time so that any 9947 * ticks that occurred while running the guest are properly accounted 9948 * to the guest. Waiting until IRQs are enabled degrades the accuracy 9949 * of accounting via context tracking, but the loss of accuracy is 9950 * acceptable for all known use cases. 9951 */ 9952 vtime_account_guest_exit(); 9953 9954 if (lapic_in_kernel(vcpu)) { 9955 s64 delta = vcpu->arch.apic->lapic_timer.advance_expire_delta; 9956 if (delta != S64_MIN) { 9957 trace_kvm_wait_lapic_expire(vcpu->vcpu_id, delta); 9958 vcpu->arch.apic->lapic_timer.advance_expire_delta = S64_MIN; 9959 } 9960 } 9961 9962 local_irq_enable(); 9963 preempt_enable(); 9964 9965 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu); 9966 9967 /* 9968 * Profile KVM exit RIPs: 9969 */ 9970 if (unlikely(prof_on == KVM_PROFILING)) { 9971 unsigned long rip = kvm_rip_read(vcpu); 9972 profile_hit(KVM_PROFILING, (void *)rip); 9973 } 9974 9975 if (unlikely(vcpu->arch.tsc_always_catchup)) 9976 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 9977 9978 if (vcpu->arch.apic_attention) 9979 kvm_lapic_sync_from_vapic(vcpu); 9980 9981 r = static_call(kvm_x86_handle_exit)(vcpu, exit_fastpath); 9982 return r; 9983 9984 cancel_injection: 9985 if (req_immediate_exit) 9986 kvm_make_request(KVM_REQ_EVENT, vcpu); 9987 static_call(kvm_x86_cancel_injection)(vcpu); 9988 if (unlikely(vcpu->arch.apic_attention)) 9989 kvm_lapic_sync_from_vapic(vcpu); 9990 out: 9991 return r; 9992 } 9993 9994 static inline int vcpu_block(struct kvm *kvm, struct kvm_vcpu *vcpu) 9995 { 9996 if (!kvm_arch_vcpu_runnable(vcpu) && 9997 (!kvm_x86_ops.pre_block || static_call(kvm_x86_pre_block)(vcpu) == 0)) { 9998 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx); 9999 kvm_vcpu_block(vcpu); 10000 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu); 10001 10002 if (kvm_x86_ops.post_block) 10003 static_call(kvm_x86_post_block)(vcpu); 10004 10005 if (!kvm_check_request(KVM_REQ_UNHALT, vcpu)) 10006 return 1; 10007 } 10008 10009 if (kvm_apic_accept_events(vcpu) < 0) 10010 return 0; 10011 switch(vcpu->arch.mp_state) { 10012 case KVM_MP_STATE_HALTED: 10013 case KVM_MP_STATE_AP_RESET_HOLD: 10014 vcpu->arch.pv.pv_unhalted = false; 10015 vcpu->arch.mp_state = 10016 KVM_MP_STATE_RUNNABLE; 10017 fallthrough; 10018 case KVM_MP_STATE_RUNNABLE: 10019 vcpu->arch.apf.halted = false; 10020 break; 10021 case KVM_MP_STATE_INIT_RECEIVED: 10022 break; 10023 default: 10024 return -EINTR; 10025 } 10026 return 1; 10027 } 10028 10029 static inline bool kvm_vcpu_running(struct kvm_vcpu *vcpu) 10030 { 10031 if (is_guest_mode(vcpu)) 10032 kvm_check_nested_events(vcpu); 10033 10034 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE && 10035 !vcpu->arch.apf.halted); 10036 } 10037 10038 static int vcpu_run(struct kvm_vcpu *vcpu) 10039 { 10040 int r; 10041 struct kvm *kvm = vcpu->kvm; 10042 10043 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu); 10044 vcpu->arch.l1tf_flush_l1d = true; 10045 10046 for (;;) { 10047 if (kvm_vcpu_running(vcpu)) { 10048 r = vcpu_enter_guest(vcpu); 10049 } else { 10050 r = vcpu_block(kvm, vcpu); 10051 } 10052 10053 if (r <= 0) 10054 break; 10055 10056 kvm_clear_request(KVM_REQ_UNBLOCK, vcpu); 10057 if (kvm_cpu_has_pending_timer(vcpu)) 10058 kvm_inject_pending_timer_irqs(vcpu); 10059 10060 if (dm_request_for_irq_injection(vcpu) && 10061 kvm_vcpu_ready_for_interrupt_injection(vcpu)) { 10062 r = 0; 10063 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN; 10064 ++vcpu->stat.request_irq_exits; 10065 break; 10066 } 10067 10068 if (__xfer_to_guest_mode_work_pending()) { 10069 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx); 10070 r = xfer_to_guest_mode_handle_work(vcpu); 10071 if (r) 10072 return r; 10073 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu); 10074 } 10075 } 10076 10077 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx); 10078 10079 return r; 10080 } 10081 10082 static inline int complete_emulated_io(struct kvm_vcpu *vcpu) 10083 { 10084 int r; 10085 10086 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu); 10087 r = kvm_emulate_instruction(vcpu, EMULTYPE_NO_DECODE); 10088 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx); 10089 return r; 10090 } 10091 10092 static int complete_emulated_pio(struct kvm_vcpu *vcpu) 10093 { 10094 BUG_ON(!vcpu->arch.pio.count); 10095 10096 return complete_emulated_io(vcpu); 10097 } 10098 10099 /* 10100 * Implements the following, as a state machine: 10101 * 10102 * read: 10103 * for each fragment 10104 * for each mmio piece in the fragment 10105 * write gpa, len 10106 * exit 10107 * copy data 10108 * execute insn 10109 * 10110 * write: 10111 * for each fragment 10112 * for each mmio piece in the fragment 10113 * write gpa, len 10114 * copy data 10115 * exit 10116 */ 10117 static int complete_emulated_mmio(struct kvm_vcpu *vcpu) 10118 { 10119 struct kvm_run *run = vcpu->run; 10120 struct kvm_mmio_fragment *frag; 10121 unsigned len; 10122 10123 BUG_ON(!vcpu->mmio_needed); 10124 10125 /* Complete previous fragment */ 10126 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment]; 10127 len = min(8u, frag->len); 10128 if (!vcpu->mmio_is_write) 10129 memcpy(frag->data, run->mmio.data, len); 10130 10131 if (frag->len <= 8) { 10132 /* Switch to the next fragment. */ 10133 frag++; 10134 vcpu->mmio_cur_fragment++; 10135 } else { 10136 /* Go forward to the next mmio piece. */ 10137 frag->data += len; 10138 frag->gpa += len; 10139 frag->len -= len; 10140 } 10141 10142 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) { 10143 vcpu->mmio_needed = 0; 10144 10145 /* FIXME: return into emulator if single-stepping. */ 10146 if (vcpu->mmio_is_write) 10147 return 1; 10148 vcpu->mmio_read_completed = 1; 10149 return complete_emulated_io(vcpu); 10150 } 10151 10152 run->exit_reason = KVM_EXIT_MMIO; 10153 run->mmio.phys_addr = frag->gpa; 10154 if (vcpu->mmio_is_write) 10155 memcpy(run->mmio.data, frag->data, min(8u, frag->len)); 10156 run->mmio.len = min(8u, frag->len); 10157 run->mmio.is_write = vcpu->mmio_is_write; 10158 vcpu->arch.complete_userspace_io = complete_emulated_mmio; 10159 return 0; 10160 } 10161 10162 /* Swap (qemu) user FPU context for the guest FPU context. */ 10163 static void kvm_load_guest_fpu(struct kvm_vcpu *vcpu) 10164 { 10165 /* 10166 * Exclude PKRU from restore as restored separately in 10167 * kvm_x86_ops.run(). 10168 */ 10169 fpu_swap_kvm_fpstate(&vcpu->arch.guest_fpu, true); 10170 trace_kvm_fpu(1); 10171 } 10172 10173 /* When vcpu_run ends, restore user space FPU context. */ 10174 static void kvm_put_guest_fpu(struct kvm_vcpu *vcpu) 10175 { 10176 fpu_swap_kvm_fpstate(&vcpu->arch.guest_fpu, false); 10177 ++vcpu->stat.fpu_reload; 10178 trace_kvm_fpu(0); 10179 } 10180 10181 int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu) 10182 { 10183 struct kvm_run *kvm_run = vcpu->run; 10184 int r; 10185 10186 vcpu_load(vcpu); 10187 kvm_sigset_activate(vcpu); 10188 kvm_run->flags = 0; 10189 kvm_load_guest_fpu(vcpu); 10190 10191 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) { 10192 if (kvm_run->immediate_exit) { 10193 r = -EINTR; 10194 goto out; 10195 } 10196 kvm_vcpu_block(vcpu); 10197 if (kvm_apic_accept_events(vcpu) < 0) { 10198 r = 0; 10199 goto out; 10200 } 10201 kvm_clear_request(KVM_REQ_UNHALT, vcpu); 10202 r = -EAGAIN; 10203 if (signal_pending(current)) { 10204 r = -EINTR; 10205 kvm_run->exit_reason = KVM_EXIT_INTR; 10206 ++vcpu->stat.signal_exits; 10207 } 10208 goto out; 10209 } 10210 10211 if ((kvm_run->kvm_valid_regs & ~KVM_SYNC_X86_VALID_FIELDS) || 10212 (kvm_run->kvm_dirty_regs & ~KVM_SYNC_X86_VALID_FIELDS)) { 10213 r = -EINVAL; 10214 goto out; 10215 } 10216 10217 if (kvm_run->kvm_dirty_regs) { 10218 r = sync_regs(vcpu); 10219 if (r != 0) 10220 goto out; 10221 } 10222 10223 /* re-sync apic's tpr */ 10224 if (!lapic_in_kernel(vcpu)) { 10225 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) { 10226 r = -EINVAL; 10227 goto out; 10228 } 10229 } 10230 10231 if (unlikely(vcpu->arch.complete_userspace_io)) { 10232 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io; 10233 vcpu->arch.complete_userspace_io = NULL; 10234 r = cui(vcpu); 10235 if (r <= 0) 10236 goto out; 10237 } else 10238 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed); 10239 10240 if (kvm_run->immediate_exit) 10241 r = -EINTR; 10242 else 10243 r = vcpu_run(vcpu); 10244 10245 out: 10246 kvm_put_guest_fpu(vcpu); 10247 if (kvm_run->kvm_valid_regs) 10248 store_regs(vcpu); 10249 post_kvm_run_save(vcpu); 10250 kvm_sigset_deactivate(vcpu); 10251 10252 vcpu_put(vcpu); 10253 return r; 10254 } 10255 10256 static void __get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) 10257 { 10258 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) { 10259 /* 10260 * We are here if userspace calls get_regs() in the middle of 10261 * instruction emulation. Registers state needs to be copied 10262 * back from emulation context to vcpu. Userspace shouldn't do 10263 * that usually, but some bad designed PV devices (vmware 10264 * backdoor interface) need this to work 10265 */ 10266 emulator_writeback_register_cache(vcpu->arch.emulate_ctxt); 10267 vcpu->arch.emulate_regs_need_sync_to_vcpu = false; 10268 } 10269 regs->rax = kvm_rax_read(vcpu); 10270 regs->rbx = kvm_rbx_read(vcpu); 10271 regs->rcx = kvm_rcx_read(vcpu); 10272 regs->rdx = kvm_rdx_read(vcpu); 10273 regs->rsi = kvm_rsi_read(vcpu); 10274 regs->rdi = kvm_rdi_read(vcpu); 10275 regs->rsp = kvm_rsp_read(vcpu); 10276 regs->rbp = kvm_rbp_read(vcpu); 10277 #ifdef CONFIG_X86_64 10278 regs->r8 = kvm_r8_read(vcpu); 10279 regs->r9 = kvm_r9_read(vcpu); 10280 regs->r10 = kvm_r10_read(vcpu); 10281 regs->r11 = kvm_r11_read(vcpu); 10282 regs->r12 = kvm_r12_read(vcpu); 10283 regs->r13 = kvm_r13_read(vcpu); 10284 regs->r14 = kvm_r14_read(vcpu); 10285 regs->r15 = kvm_r15_read(vcpu); 10286 #endif 10287 10288 regs->rip = kvm_rip_read(vcpu); 10289 regs->rflags = kvm_get_rflags(vcpu); 10290 } 10291 10292 int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) 10293 { 10294 vcpu_load(vcpu); 10295 __get_regs(vcpu, regs); 10296 vcpu_put(vcpu); 10297 return 0; 10298 } 10299 10300 static void __set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) 10301 { 10302 vcpu->arch.emulate_regs_need_sync_from_vcpu = true; 10303 vcpu->arch.emulate_regs_need_sync_to_vcpu = false; 10304 10305 kvm_rax_write(vcpu, regs->rax); 10306 kvm_rbx_write(vcpu, regs->rbx); 10307 kvm_rcx_write(vcpu, regs->rcx); 10308 kvm_rdx_write(vcpu, regs->rdx); 10309 kvm_rsi_write(vcpu, regs->rsi); 10310 kvm_rdi_write(vcpu, regs->rdi); 10311 kvm_rsp_write(vcpu, regs->rsp); 10312 kvm_rbp_write(vcpu, regs->rbp); 10313 #ifdef CONFIG_X86_64 10314 kvm_r8_write(vcpu, regs->r8); 10315 kvm_r9_write(vcpu, regs->r9); 10316 kvm_r10_write(vcpu, regs->r10); 10317 kvm_r11_write(vcpu, regs->r11); 10318 kvm_r12_write(vcpu, regs->r12); 10319 kvm_r13_write(vcpu, regs->r13); 10320 kvm_r14_write(vcpu, regs->r14); 10321 kvm_r15_write(vcpu, regs->r15); 10322 #endif 10323 10324 kvm_rip_write(vcpu, regs->rip); 10325 kvm_set_rflags(vcpu, regs->rflags | X86_EFLAGS_FIXED); 10326 10327 vcpu->arch.exception.pending = false; 10328 10329 kvm_make_request(KVM_REQ_EVENT, vcpu); 10330 } 10331 10332 int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) 10333 { 10334 vcpu_load(vcpu); 10335 __set_regs(vcpu, regs); 10336 vcpu_put(vcpu); 10337 return 0; 10338 } 10339 10340 void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l) 10341 { 10342 struct kvm_segment cs; 10343 10344 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS); 10345 *db = cs.db; 10346 *l = cs.l; 10347 } 10348 EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits); 10349 10350 static void __get_sregs_common(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs) 10351 { 10352 struct desc_ptr dt; 10353 10354 if (vcpu->arch.guest_state_protected) 10355 goto skip_protected_regs; 10356 10357 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS); 10358 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS); 10359 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES); 10360 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS); 10361 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS); 10362 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS); 10363 10364 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR); 10365 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR); 10366 10367 static_call(kvm_x86_get_idt)(vcpu, &dt); 10368 sregs->idt.limit = dt.size; 10369 sregs->idt.base = dt.address; 10370 static_call(kvm_x86_get_gdt)(vcpu, &dt); 10371 sregs->gdt.limit = dt.size; 10372 sregs->gdt.base = dt.address; 10373 10374 sregs->cr2 = vcpu->arch.cr2; 10375 sregs->cr3 = kvm_read_cr3(vcpu); 10376 10377 skip_protected_regs: 10378 sregs->cr0 = kvm_read_cr0(vcpu); 10379 sregs->cr4 = kvm_read_cr4(vcpu); 10380 sregs->cr8 = kvm_get_cr8(vcpu); 10381 sregs->efer = vcpu->arch.efer; 10382 sregs->apic_base = kvm_get_apic_base(vcpu); 10383 } 10384 10385 static void __get_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs) 10386 { 10387 __get_sregs_common(vcpu, sregs); 10388 10389 if (vcpu->arch.guest_state_protected) 10390 return; 10391 10392 if (vcpu->arch.interrupt.injected && !vcpu->arch.interrupt.soft) 10393 set_bit(vcpu->arch.interrupt.nr, 10394 (unsigned long *)sregs->interrupt_bitmap); 10395 } 10396 10397 static void __get_sregs2(struct kvm_vcpu *vcpu, struct kvm_sregs2 *sregs2) 10398 { 10399 int i; 10400 10401 __get_sregs_common(vcpu, (struct kvm_sregs *)sregs2); 10402 10403 if (vcpu->arch.guest_state_protected) 10404 return; 10405 10406 if (is_pae_paging(vcpu)) { 10407 for (i = 0 ; i < 4 ; i++) 10408 sregs2->pdptrs[i] = kvm_pdptr_read(vcpu, i); 10409 sregs2->flags |= KVM_SREGS2_FLAGS_PDPTRS_VALID; 10410 } 10411 } 10412 10413 int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu, 10414 struct kvm_sregs *sregs) 10415 { 10416 vcpu_load(vcpu); 10417 __get_sregs(vcpu, sregs); 10418 vcpu_put(vcpu); 10419 return 0; 10420 } 10421 10422 int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu, 10423 struct kvm_mp_state *mp_state) 10424 { 10425 int r; 10426 10427 vcpu_load(vcpu); 10428 if (kvm_mpx_supported()) 10429 kvm_load_guest_fpu(vcpu); 10430 10431 r = kvm_apic_accept_events(vcpu); 10432 if (r < 0) 10433 goto out; 10434 r = 0; 10435 10436 if ((vcpu->arch.mp_state == KVM_MP_STATE_HALTED || 10437 vcpu->arch.mp_state == KVM_MP_STATE_AP_RESET_HOLD) && 10438 vcpu->arch.pv.pv_unhalted) 10439 mp_state->mp_state = KVM_MP_STATE_RUNNABLE; 10440 else 10441 mp_state->mp_state = vcpu->arch.mp_state; 10442 10443 out: 10444 if (kvm_mpx_supported()) 10445 kvm_put_guest_fpu(vcpu); 10446 vcpu_put(vcpu); 10447 return r; 10448 } 10449 10450 int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu, 10451 struct kvm_mp_state *mp_state) 10452 { 10453 int ret = -EINVAL; 10454 10455 vcpu_load(vcpu); 10456 10457 if (!lapic_in_kernel(vcpu) && 10458 mp_state->mp_state != KVM_MP_STATE_RUNNABLE) 10459 goto out; 10460 10461 /* 10462 * KVM_MP_STATE_INIT_RECEIVED means the processor is in 10463 * INIT state; latched init should be reported using 10464 * KVM_SET_VCPU_EVENTS, so reject it here. 10465 */ 10466 if ((kvm_vcpu_latch_init(vcpu) || vcpu->arch.smi_pending) && 10467 (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED || 10468 mp_state->mp_state == KVM_MP_STATE_INIT_RECEIVED)) 10469 goto out; 10470 10471 if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) { 10472 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED; 10473 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events); 10474 } else 10475 vcpu->arch.mp_state = mp_state->mp_state; 10476 kvm_make_request(KVM_REQ_EVENT, vcpu); 10477 10478 ret = 0; 10479 out: 10480 vcpu_put(vcpu); 10481 return ret; 10482 } 10483 10484 int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index, 10485 int reason, bool has_error_code, u32 error_code) 10486 { 10487 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt; 10488 int ret; 10489 10490 init_emulate_ctxt(vcpu); 10491 10492 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason, 10493 has_error_code, error_code); 10494 if (ret) { 10495 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR; 10496 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION; 10497 vcpu->run->internal.ndata = 0; 10498 return 0; 10499 } 10500 10501 kvm_rip_write(vcpu, ctxt->eip); 10502 kvm_set_rflags(vcpu, ctxt->eflags); 10503 return 1; 10504 } 10505 EXPORT_SYMBOL_GPL(kvm_task_switch); 10506 10507 static bool kvm_is_valid_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs) 10508 { 10509 if ((sregs->efer & EFER_LME) && (sregs->cr0 & X86_CR0_PG)) { 10510 /* 10511 * When EFER.LME and CR0.PG are set, the processor is in 10512 * 64-bit mode (though maybe in a 32-bit code segment). 10513 * CR4.PAE and EFER.LMA must be set. 10514 */ 10515 if (!(sregs->cr4 & X86_CR4_PAE) || !(sregs->efer & EFER_LMA)) 10516 return false; 10517 if (kvm_vcpu_is_illegal_gpa(vcpu, sregs->cr3)) 10518 return false; 10519 } else { 10520 /* 10521 * Not in 64-bit mode: EFER.LMA is clear and the code 10522 * segment cannot be 64-bit. 10523 */ 10524 if (sregs->efer & EFER_LMA || sregs->cs.l) 10525 return false; 10526 } 10527 10528 return kvm_is_valid_cr4(vcpu, sregs->cr4); 10529 } 10530 10531 static int __set_sregs_common(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs, 10532 int *mmu_reset_needed, bool update_pdptrs) 10533 { 10534 struct msr_data apic_base_msr; 10535 int idx; 10536 struct desc_ptr dt; 10537 10538 if (!kvm_is_valid_sregs(vcpu, sregs)) 10539 return -EINVAL; 10540 10541 apic_base_msr.data = sregs->apic_base; 10542 apic_base_msr.host_initiated = true; 10543 if (kvm_set_apic_base(vcpu, &apic_base_msr)) 10544 return -EINVAL; 10545 10546 if (vcpu->arch.guest_state_protected) 10547 return 0; 10548 10549 dt.size = sregs->idt.limit; 10550 dt.address = sregs->idt.base; 10551 static_call(kvm_x86_set_idt)(vcpu, &dt); 10552 dt.size = sregs->gdt.limit; 10553 dt.address = sregs->gdt.base; 10554 static_call(kvm_x86_set_gdt)(vcpu, &dt); 10555 10556 vcpu->arch.cr2 = sregs->cr2; 10557 *mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3; 10558 vcpu->arch.cr3 = sregs->cr3; 10559 kvm_register_mark_available(vcpu, VCPU_EXREG_CR3); 10560 10561 kvm_set_cr8(vcpu, sregs->cr8); 10562 10563 *mmu_reset_needed |= vcpu->arch.efer != sregs->efer; 10564 static_call(kvm_x86_set_efer)(vcpu, sregs->efer); 10565 10566 *mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0; 10567 static_call(kvm_x86_set_cr0)(vcpu, sregs->cr0); 10568 vcpu->arch.cr0 = sregs->cr0; 10569 10570 *mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4; 10571 static_call(kvm_x86_set_cr4)(vcpu, sregs->cr4); 10572 10573 if (update_pdptrs) { 10574 idx = srcu_read_lock(&vcpu->kvm->srcu); 10575 if (is_pae_paging(vcpu)) { 10576 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu)); 10577 *mmu_reset_needed = 1; 10578 } 10579 srcu_read_unlock(&vcpu->kvm->srcu, idx); 10580 } 10581 10582 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS); 10583 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS); 10584 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES); 10585 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS); 10586 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS); 10587 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS); 10588 10589 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR); 10590 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR); 10591 10592 update_cr8_intercept(vcpu); 10593 10594 /* Older userspace won't unhalt the vcpu on reset. */ 10595 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 && 10596 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 && 10597 !is_protmode(vcpu)) 10598 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; 10599 10600 return 0; 10601 } 10602 10603 static int __set_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs) 10604 { 10605 int pending_vec, max_bits; 10606 int mmu_reset_needed = 0; 10607 int ret = __set_sregs_common(vcpu, sregs, &mmu_reset_needed, true); 10608 10609 if (ret) 10610 return ret; 10611 10612 if (mmu_reset_needed) 10613 kvm_mmu_reset_context(vcpu); 10614 10615 max_bits = KVM_NR_INTERRUPTS; 10616 pending_vec = find_first_bit( 10617 (const unsigned long *)sregs->interrupt_bitmap, max_bits); 10618 10619 if (pending_vec < max_bits) { 10620 kvm_queue_interrupt(vcpu, pending_vec, false); 10621 pr_debug("Set back pending irq %d\n", pending_vec); 10622 kvm_make_request(KVM_REQ_EVENT, vcpu); 10623 } 10624 return 0; 10625 } 10626 10627 static int __set_sregs2(struct kvm_vcpu *vcpu, struct kvm_sregs2 *sregs2) 10628 { 10629 int mmu_reset_needed = 0; 10630 bool valid_pdptrs = sregs2->flags & KVM_SREGS2_FLAGS_PDPTRS_VALID; 10631 bool pae = (sregs2->cr0 & X86_CR0_PG) && (sregs2->cr4 & X86_CR4_PAE) && 10632 !(sregs2->efer & EFER_LMA); 10633 int i, ret; 10634 10635 if (sregs2->flags & ~KVM_SREGS2_FLAGS_PDPTRS_VALID) 10636 return -EINVAL; 10637 10638 if (valid_pdptrs && (!pae || vcpu->arch.guest_state_protected)) 10639 return -EINVAL; 10640 10641 ret = __set_sregs_common(vcpu, (struct kvm_sregs *)sregs2, 10642 &mmu_reset_needed, !valid_pdptrs); 10643 if (ret) 10644 return ret; 10645 10646 if (valid_pdptrs) { 10647 for (i = 0; i < 4 ; i++) 10648 kvm_pdptr_write(vcpu, i, sregs2->pdptrs[i]); 10649 10650 kvm_register_mark_dirty(vcpu, VCPU_EXREG_PDPTR); 10651 mmu_reset_needed = 1; 10652 vcpu->arch.pdptrs_from_userspace = true; 10653 } 10654 if (mmu_reset_needed) 10655 kvm_mmu_reset_context(vcpu); 10656 return 0; 10657 } 10658 10659 int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu, 10660 struct kvm_sregs *sregs) 10661 { 10662 int ret; 10663 10664 vcpu_load(vcpu); 10665 ret = __set_sregs(vcpu, sregs); 10666 vcpu_put(vcpu); 10667 return ret; 10668 } 10669 10670 static void kvm_arch_vcpu_guestdbg_update_apicv_inhibit(struct kvm *kvm) 10671 { 10672 bool inhibit = false; 10673 struct kvm_vcpu *vcpu; 10674 int i; 10675 10676 down_write(&kvm->arch.apicv_update_lock); 10677 10678 kvm_for_each_vcpu(i, vcpu, kvm) { 10679 if (vcpu->guest_debug & KVM_GUESTDBG_BLOCKIRQ) { 10680 inhibit = true; 10681 break; 10682 } 10683 } 10684 __kvm_request_apicv_update(kvm, !inhibit, APICV_INHIBIT_REASON_BLOCKIRQ); 10685 up_write(&kvm->arch.apicv_update_lock); 10686 } 10687 10688 int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu, 10689 struct kvm_guest_debug *dbg) 10690 { 10691 unsigned long rflags; 10692 int i, r; 10693 10694 if (vcpu->arch.guest_state_protected) 10695 return -EINVAL; 10696 10697 vcpu_load(vcpu); 10698 10699 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) { 10700 r = -EBUSY; 10701 if (vcpu->arch.exception.pending) 10702 goto out; 10703 if (dbg->control & KVM_GUESTDBG_INJECT_DB) 10704 kvm_queue_exception(vcpu, DB_VECTOR); 10705 else 10706 kvm_queue_exception(vcpu, BP_VECTOR); 10707 } 10708 10709 /* 10710 * Read rflags as long as potentially injected trace flags are still 10711 * filtered out. 10712 */ 10713 rflags = kvm_get_rflags(vcpu); 10714 10715 vcpu->guest_debug = dbg->control; 10716 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE)) 10717 vcpu->guest_debug = 0; 10718 10719 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) { 10720 for (i = 0; i < KVM_NR_DB_REGS; ++i) 10721 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i]; 10722 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7]; 10723 } else { 10724 for (i = 0; i < KVM_NR_DB_REGS; i++) 10725 vcpu->arch.eff_db[i] = vcpu->arch.db[i]; 10726 } 10727 kvm_update_dr7(vcpu); 10728 10729 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) 10730 vcpu->arch.singlestep_rip = kvm_get_linear_rip(vcpu); 10731 10732 /* 10733 * Trigger an rflags update that will inject or remove the trace 10734 * flags. 10735 */ 10736 kvm_set_rflags(vcpu, rflags); 10737 10738 static_call(kvm_x86_update_exception_bitmap)(vcpu); 10739 10740 kvm_arch_vcpu_guestdbg_update_apicv_inhibit(vcpu->kvm); 10741 10742 r = 0; 10743 10744 out: 10745 vcpu_put(vcpu); 10746 return r; 10747 } 10748 10749 /* 10750 * Translate a guest virtual address to a guest physical address. 10751 */ 10752 int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu, 10753 struct kvm_translation *tr) 10754 { 10755 unsigned long vaddr = tr->linear_address; 10756 gpa_t gpa; 10757 int idx; 10758 10759 vcpu_load(vcpu); 10760 10761 idx = srcu_read_lock(&vcpu->kvm->srcu); 10762 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL); 10763 srcu_read_unlock(&vcpu->kvm->srcu, idx); 10764 tr->physical_address = gpa; 10765 tr->valid = gpa != UNMAPPED_GVA; 10766 tr->writeable = 1; 10767 tr->usermode = 0; 10768 10769 vcpu_put(vcpu); 10770 return 0; 10771 } 10772 10773 int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu) 10774 { 10775 struct fxregs_state *fxsave; 10776 10777 if (fpstate_is_confidential(&vcpu->arch.guest_fpu)) 10778 return 0; 10779 10780 vcpu_load(vcpu); 10781 10782 fxsave = &vcpu->arch.guest_fpu.fpstate->regs.fxsave; 10783 memcpy(fpu->fpr, fxsave->st_space, 128); 10784 fpu->fcw = fxsave->cwd; 10785 fpu->fsw = fxsave->swd; 10786 fpu->ftwx = fxsave->twd; 10787 fpu->last_opcode = fxsave->fop; 10788 fpu->last_ip = fxsave->rip; 10789 fpu->last_dp = fxsave->rdp; 10790 memcpy(fpu->xmm, fxsave->xmm_space, sizeof(fxsave->xmm_space)); 10791 10792 vcpu_put(vcpu); 10793 return 0; 10794 } 10795 10796 int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu) 10797 { 10798 struct fxregs_state *fxsave; 10799 10800 if (fpstate_is_confidential(&vcpu->arch.guest_fpu)) 10801 return 0; 10802 10803 vcpu_load(vcpu); 10804 10805 fxsave = &vcpu->arch.guest_fpu.fpstate->regs.fxsave; 10806 10807 memcpy(fxsave->st_space, fpu->fpr, 128); 10808 fxsave->cwd = fpu->fcw; 10809 fxsave->swd = fpu->fsw; 10810 fxsave->twd = fpu->ftwx; 10811 fxsave->fop = fpu->last_opcode; 10812 fxsave->rip = fpu->last_ip; 10813 fxsave->rdp = fpu->last_dp; 10814 memcpy(fxsave->xmm_space, fpu->xmm, sizeof(fxsave->xmm_space)); 10815 10816 vcpu_put(vcpu); 10817 return 0; 10818 } 10819 10820 static void store_regs(struct kvm_vcpu *vcpu) 10821 { 10822 BUILD_BUG_ON(sizeof(struct kvm_sync_regs) > SYNC_REGS_SIZE_BYTES); 10823 10824 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_REGS) 10825 __get_regs(vcpu, &vcpu->run->s.regs.regs); 10826 10827 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_SREGS) 10828 __get_sregs(vcpu, &vcpu->run->s.regs.sregs); 10829 10830 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_EVENTS) 10831 kvm_vcpu_ioctl_x86_get_vcpu_events( 10832 vcpu, &vcpu->run->s.regs.events); 10833 } 10834 10835 static int sync_regs(struct kvm_vcpu *vcpu) 10836 { 10837 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_REGS) { 10838 __set_regs(vcpu, &vcpu->run->s.regs.regs); 10839 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_REGS; 10840 } 10841 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_SREGS) { 10842 if (__set_sregs(vcpu, &vcpu->run->s.regs.sregs)) 10843 return -EINVAL; 10844 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_SREGS; 10845 } 10846 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_EVENTS) { 10847 if (kvm_vcpu_ioctl_x86_set_vcpu_events( 10848 vcpu, &vcpu->run->s.regs.events)) 10849 return -EINVAL; 10850 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_EVENTS; 10851 } 10852 10853 return 0; 10854 } 10855 10856 int kvm_arch_vcpu_precreate(struct kvm *kvm, unsigned int id) 10857 { 10858 if (kvm_check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0) 10859 pr_warn_once("kvm: SMP vm created on host with unstable TSC; " 10860 "guest TSC will not be reliable\n"); 10861 10862 return 0; 10863 } 10864 10865 int kvm_arch_vcpu_create(struct kvm_vcpu *vcpu) 10866 { 10867 struct page *page; 10868 int r; 10869 10870 vcpu->arch.last_vmentry_cpu = -1; 10871 vcpu->arch.regs_avail = ~0; 10872 vcpu->arch.regs_dirty = ~0; 10873 10874 if (!irqchip_in_kernel(vcpu->kvm) || kvm_vcpu_is_reset_bsp(vcpu)) 10875 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; 10876 else 10877 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED; 10878 10879 r = kvm_mmu_create(vcpu); 10880 if (r < 0) 10881 return r; 10882 10883 if (irqchip_in_kernel(vcpu->kvm)) { 10884 r = kvm_create_lapic(vcpu, lapic_timer_advance_ns); 10885 if (r < 0) 10886 goto fail_mmu_destroy; 10887 if (kvm_apicv_activated(vcpu->kvm)) 10888 vcpu->arch.apicv_active = true; 10889 } else 10890 static_branch_inc(&kvm_has_noapic_vcpu); 10891 10892 r = -ENOMEM; 10893 10894 page = alloc_page(GFP_KERNEL_ACCOUNT | __GFP_ZERO); 10895 if (!page) 10896 goto fail_free_lapic; 10897 vcpu->arch.pio_data = page_address(page); 10898 10899 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4, 10900 GFP_KERNEL_ACCOUNT); 10901 if (!vcpu->arch.mce_banks) 10902 goto fail_free_pio_data; 10903 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS; 10904 10905 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, 10906 GFP_KERNEL_ACCOUNT)) 10907 goto fail_free_mce_banks; 10908 10909 if (!alloc_emulate_ctxt(vcpu)) 10910 goto free_wbinvd_dirty_mask; 10911 10912 if (!fpu_alloc_guest_fpstate(&vcpu->arch.guest_fpu)) { 10913 pr_err("kvm: failed to allocate vcpu's fpu\n"); 10914 goto free_emulate_ctxt; 10915 } 10916 10917 vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu); 10918 vcpu->arch.reserved_gpa_bits = kvm_vcpu_reserved_gpa_bits_raw(vcpu); 10919 10920 vcpu->arch.pat = MSR_IA32_CR_PAT_DEFAULT; 10921 10922 kvm_async_pf_hash_reset(vcpu); 10923 kvm_pmu_init(vcpu); 10924 10925 vcpu->arch.pending_external_vector = -1; 10926 vcpu->arch.preempted_in_kernel = false; 10927 10928 #if IS_ENABLED(CONFIG_HYPERV) 10929 vcpu->arch.hv_root_tdp = INVALID_PAGE; 10930 #endif 10931 10932 r = static_call(kvm_x86_vcpu_create)(vcpu); 10933 if (r) 10934 goto free_guest_fpu; 10935 10936 vcpu->arch.arch_capabilities = kvm_get_arch_capabilities(); 10937 vcpu->arch.msr_platform_info = MSR_PLATFORM_INFO_CPUID_FAULT; 10938 kvm_vcpu_mtrr_init(vcpu); 10939 vcpu_load(vcpu); 10940 kvm_set_tsc_khz(vcpu, max_tsc_khz); 10941 kvm_vcpu_reset(vcpu, false); 10942 kvm_init_mmu(vcpu); 10943 vcpu_put(vcpu); 10944 return 0; 10945 10946 free_guest_fpu: 10947 fpu_free_guest_fpstate(&vcpu->arch.guest_fpu); 10948 free_emulate_ctxt: 10949 kmem_cache_free(x86_emulator_cache, vcpu->arch.emulate_ctxt); 10950 free_wbinvd_dirty_mask: 10951 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask); 10952 fail_free_mce_banks: 10953 kfree(vcpu->arch.mce_banks); 10954 fail_free_pio_data: 10955 free_page((unsigned long)vcpu->arch.pio_data); 10956 fail_free_lapic: 10957 kvm_free_lapic(vcpu); 10958 fail_mmu_destroy: 10959 kvm_mmu_destroy(vcpu); 10960 return r; 10961 } 10962 10963 void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu) 10964 { 10965 struct kvm *kvm = vcpu->kvm; 10966 10967 if (mutex_lock_killable(&vcpu->mutex)) 10968 return; 10969 vcpu_load(vcpu); 10970 kvm_synchronize_tsc(vcpu, 0); 10971 vcpu_put(vcpu); 10972 10973 /* poll control enabled by default */ 10974 vcpu->arch.msr_kvm_poll_control = 1; 10975 10976 mutex_unlock(&vcpu->mutex); 10977 10978 if (kvmclock_periodic_sync && vcpu->vcpu_idx == 0) 10979 schedule_delayed_work(&kvm->arch.kvmclock_sync_work, 10980 KVMCLOCK_SYNC_PERIOD); 10981 } 10982 10983 void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu) 10984 { 10985 int idx; 10986 10987 kvmclock_reset(vcpu); 10988 10989 static_call(kvm_x86_vcpu_free)(vcpu); 10990 10991 kmem_cache_free(x86_emulator_cache, vcpu->arch.emulate_ctxt); 10992 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask); 10993 fpu_free_guest_fpstate(&vcpu->arch.guest_fpu); 10994 10995 kvm_hv_vcpu_uninit(vcpu); 10996 kvm_pmu_destroy(vcpu); 10997 kfree(vcpu->arch.mce_banks); 10998 kvm_free_lapic(vcpu); 10999 idx = srcu_read_lock(&vcpu->kvm->srcu); 11000 kvm_mmu_destroy(vcpu); 11001 srcu_read_unlock(&vcpu->kvm->srcu, idx); 11002 free_page((unsigned long)vcpu->arch.pio_data); 11003 kvfree(vcpu->arch.cpuid_entries); 11004 if (!lapic_in_kernel(vcpu)) 11005 static_branch_dec(&kvm_has_noapic_vcpu); 11006 } 11007 11008 void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event) 11009 { 11010 struct kvm_cpuid_entry2 *cpuid_0x1; 11011 unsigned long old_cr0 = kvm_read_cr0(vcpu); 11012 unsigned long new_cr0; 11013 11014 /* 11015 * Several of the "set" flows, e.g. ->set_cr0(), read other registers 11016 * to handle side effects. RESET emulation hits those flows and relies 11017 * on emulated/virtualized registers, including those that are loaded 11018 * into hardware, to be zeroed at vCPU creation. Use CRs as a sentinel 11019 * to detect improper or missing initialization. 11020 */ 11021 WARN_ON_ONCE(!init_event && 11022 (old_cr0 || kvm_read_cr3(vcpu) || kvm_read_cr4(vcpu))); 11023 11024 kvm_lapic_reset(vcpu, init_event); 11025 11026 vcpu->arch.hflags = 0; 11027 11028 vcpu->arch.smi_pending = 0; 11029 vcpu->arch.smi_count = 0; 11030 atomic_set(&vcpu->arch.nmi_queued, 0); 11031 vcpu->arch.nmi_pending = 0; 11032 vcpu->arch.nmi_injected = false; 11033 kvm_clear_interrupt_queue(vcpu); 11034 kvm_clear_exception_queue(vcpu); 11035 11036 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db)); 11037 kvm_update_dr0123(vcpu); 11038 vcpu->arch.dr6 = DR6_ACTIVE_LOW; 11039 vcpu->arch.dr7 = DR7_FIXED_1; 11040 kvm_update_dr7(vcpu); 11041 11042 vcpu->arch.cr2 = 0; 11043 11044 kvm_make_request(KVM_REQ_EVENT, vcpu); 11045 vcpu->arch.apf.msr_en_val = 0; 11046 vcpu->arch.apf.msr_int_val = 0; 11047 vcpu->arch.st.msr_val = 0; 11048 11049 kvmclock_reset(vcpu); 11050 11051 kvm_clear_async_pf_completion_queue(vcpu); 11052 kvm_async_pf_hash_reset(vcpu); 11053 vcpu->arch.apf.halted = false; 11054 11055 if (vcpu->arch.guest_fpu.fpstate && kvm_mpx_supported()) { 11056 struct fpstate *fpstate = vcpu->arch.guest_fpu.fpstate; 11057 11058 /* 11059 * To avoid have the INIT path from kvm_apic_has_events() that be 11060 * called with loaded FPU and does not let userspace fix the state. 11061 */ 11062 if (init_event) 11063 kvm_put_guest_fpu(vcpu); 11064 11065 fpstate_clear_xstate_component(fpstate, XFEATURE_BNDREGS); 11066 fpstate_clear_xstate_component(fpstate, XFEATURE_BNDCSR); 11067 11068 if (init_event) 11069 kvm_load_guest_fpu(vcpu); 11070 } 11071 11072 if (!init_event) { 11073 kvm_pmu_reset(vcpu); 11074 vcpu->arch.smbase = 0x30000; 11075 11076 vcpu->arch.msr_misc_features_enables = 0; 11077 11078 vcpu->arch.xcr0 = XFEATURE_MASK_FP; 11079 } 11080 11081 /* All GPRs except RDX (handled below) are zeroed on RESET/INIT. */ 11082 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs)); 11083 kvm_register_mark_dirty(vcpu, VCPU_REGS_RSP); 11084 11085 /* 11086 * Fall back to KVM's default Family/Model/Stepping of 0x600 (P6/Athlon) 11087 * if no CPUID match is found. Note, it's impossible to get a match at 11088 * RESET since KVM emulates RESET before exposing the vCPU to userspace, 11089 * i.e. it's impossible for kvm_find_cpuid_entry() to find a valid entry 11090 * on RESET. But, go through the motions in case that's ever remedied. 11091 */ 11092 cpuid_0x1 = kvm_find_cpuid_entry(vcpu, 1, 0); 11093 kvm_rdx_write(vcpu, cpuid_0x1 ? cpuid_0x1->eax : 0x600); 11094 11095 vcpu->arch.ia32_xss = 0; 11096 11097 static_call(kvm_x86_vcpu_reset)(vcpu, init_event); 11098 11099 kvm_set_rflags(vcpu, X86_EFLAGS_FIXED); 11100 kvm_rip_write(vcpu, 0xfff0); 11101 11102 vcpu->arch.cr3 = 0; 11103 kvm_register_mark_dirty(vcpu, VCPU_EXREG_CR3); 11104 11105 /* 11106 * CR0.CD/NW are set on RESET, preserved on INIT. Note, some versions 11107 * of Intel's SDM list CD/NW as being set on INIT, but they contradict 11108 * (or qualify) that with a footnote stating that CD/NW are preserved. 11109 */ 11110 new_cr0 = X86_CR0_ET; 11111 if (init_event) 11112 new_cr0 |= (old_cr0 & (X86_CR0_NW | X86_CR0_CD)); 11113 else 11114 new_cr0 |= X86_CR0_NW | X86_CR0_CD; 11115 11116 static_call(kvm_x86_set_cr0)(vcpu, new_cr0); 11117 static_call(kvm_x86_set_cr4)(vcpu, 0); 11118 static_call(kvm_x86_set_efer)(vcpu, 0); 11119 static_call(kvm_x86_update_exception_bitmap)(vcpu); 11120 11121 /* 11122 * Reset the MMU context if paging was enabled prior to INIT (which is 11123 * implied if CR0.PG=1 as CR0 will be '0' prior to RESET). Unlike the 11124 * standard CR0/CR4/EFER modification paths, only CR0.PG needs to be 11125 * checked because it is unconditionally cleared on INIT and all other 11126 * paging related bits are ignored if paging is disabled, i.e. CR0.WP, 11127 * CR4, and EFER changes are all irrelevant if CR0.PG was '0'. 11128 */ 11129 if (old_cr0 & X86_CR0_PG) 11130 kvm_mmu_reset_context(vcpu); 11131 11132 /* 11133 * Intel's SDM states that all TLB entries are flushed on INIT. AMD's 11134 * APM states the TLBs are untouched by INIT, but it also states that 11135 * the TLBs are flushed on "External initialization of the processor." 11136 * Flush the guest TLB regardless of vendor, there is no meaningful 11137 * benefit in relying on the guest to flush the TLB immediately after 11138 * INIT. A spurious TLB flush is benign and likely negligible from a 11139 * performance perspective. 11140 */ 11141 if (init_event) 11142 kvm_make_request(KVM_REQ_TLB_FLUSH_GUEST, vcpu); 11143 } 11144 EXPORT_SYMBOL_GPL(kvm_vcpu_reset); 11145 11146 void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector) 11147 { 11148 struct kvm_segment cs; 11149 11150 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS); 11151 cs.selector = vector << 8; 11152 cs.base = vector << 12; 11153 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS); 11154 kvm_rip_write(vcpu, 0); 11155 } 11156 EXPORT_SYMBOL_GPL(kvm_vcpu_deliver_sipi_vector); 11157 11158 int kvm_arch_hardware_enable(void) 11159 { 11160 struct kvm *kvm; 11161 struct kvm_vcpu *vcpu; 11162 int i; 11163 int ret; 11164 u64 local_tsc; 11165 u64 max_tsc = 0; 11166 bool stable, backwards_tsc = false; 11167 11168 kvm_user_return_msr_cpu_online(); 11169 ret = static_call(kvm_x86_hardware_enable)(); 11170 if (ret != 0) 11171 return ret; 11172 11173 local_tsc = rdtsc(); 11174 stable = !kvm_check_tsc_unstable(); 11175 list_for_each_entry(kvm, &vm_list, vm_list) { 11176 kvm_for_each_vcpu(i, vcpu, kvm) { 11177 if (!stable && vcpu->cpu == smp_processor_id()) 11178 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 11179 if (stable && vcpu->arch.last_host_tsc > local_tsc) { 11180 backwards_tsc = true; 11181 if (vcpu->arch.last_host_tsc > max_tsc) 11182 max_tsc = vcpu->arch.last_host_tsc; 11183 } 11184 } 11185 } 11186 11187 /* 11188 * Sometimes, even reliable TSCs go backwards. This happens on 11189 * platforms that reset TSC during suspend or hibernate actions, but 11190 * maintain synchronization. We must compensate. Fortunately, we can 11191 * detect that condition here, which happens early in CPU bringup, 11192 * before any KVM threads can be running. Unfortunately, we can't 11193 * bring the TSCs fully up to date with real time, as we aren't yet far 11194 * enough into CPU bringup that we know how much real time has actually 11195 * elapsed; our helper function, ktime_get_boottime_ns() will be using boot 11196 * variables that haven't been updated yet. 11197 * 11198 * So we simply find the maximum observed TSC above, then record the 11199 * adjustment to TSC in each VCPU. When the VCPU later gets loaded, 11200 * the adjustment will be applied. Note that we accumulate 11201 * adjustments, in case multiple suspend cycles happen before some VCPU 11202 * gets a chance to run again. In the event that no KVM threads get a 11203 * chance to run, we will miss the entire elapsed period, as we'll have 11204 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may 11205 * loose cycle time. This isn't too big a deal, since the loss will be 11206 * uniform across all VCPUs (not to mention the scenario is extremely 11207 * unlikely). It is possible that a second hibernate recovery happens 11208 * much faster than a first, causing the observed TSC here to be 11209 * smaller; this would require additional padding adjustment, which is 11210 * why we set last_host_tsc to the local tsc observed here. 11211 * 11212 * N.B. - this code below runs only on platforms with reliable TSC, 11213 * as that is the only way backwards_tsc is set above. Also note 11214 * that this runs for ALL vcpus, which is not a bug; all VCPUs should 11215 * have the same delta_cyc adjustment applied if backwards_tsc 11216 * is detected. Note further, this adjustment is only done once, 11217 * as we reset last_host_tsc on all VCPUs to stop this from being 11218 * called multiple times (one for each physical CPU bringup). 11219 * 11220 * Platforms with unreliable TSCs don't have to deal with this, they 11221 * will be compensated by the logic in vcpu_load, which sets the TSC to 11222 * catchup mode. This will catchup all VCPUs to real time, but cannot 11223 * guarantee that they stay in perfect synchronization. 11224 */ 11225 if (backwards_tsc) { 11226 u64 delta_cyc = max_tsc - local_tsc; 11227 list_for_each_entry(kvm, &vm_list, vm_list) { 11228 kvm->arch.backwards_tsc_observed = true; 11229 kvm_for_each_vcpu(i, vcpu, kvm) { 11230 vcpu->arch.tsc_offset_adjustment += delta_cyc; 11231 vcpu->arch.last_host_tsc = local_tsc; 11232 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu); 11233 } 11234 11235 /* 11236 * We have to disable TSC offset matching.. if you were 11237 * booting a VM while issuing an S4 host suspend.... 11238 * you may have some problem. Solving this issue is 11239 * left as an exercise to the reader. 11240 */ 11241 kvm->arch.last_tsc_nsec = 0; 11242 kvm->arch.last_tsc_write = 0; 11243 } 11244 11245 } 11246 return 0; 11247 } 11248 11249 void kvm_arch_hardware_disable(void) 11250 { 11251 static_call(kvm_x86_hardware_disable)(); 11252 drop_user_return_notifiers(); 11253 } 11254 11255 int kvm_arch_hardware_setup(void *opaque) 11256 { 11257 struct kvm_x86_init_ops *ops = opaque; 11258 int r; 11259 11260 rdmsrl_safe(MSR_EFER, &host_efer); 11261 11262 if (boot_cpu_has(X86_FEATURE_XSAVES)) 11263 rdmsrl(MSR_IA32_XSS, host_xss); 11264 11265 r = ops->hardware_setup(); 11266 if (r != 0) 11267 return r; 11268 11269 memcpy(&kvm_x86_ops, ops->runtime_ops, sizeof(kvm_x86_ops)); 11270 kvm_ops_static_call_update(); 11271 11272 if (!kvm_cpu_cap_has(X86_FEATURE_XSAVES)) 11273 supported_xss = 0; 11274 11275 #define __kvm_cpu_cap_has(UNUSED_, f) kvm_cpu_cap_has(f) 11276 cr4_reserved_bits = __cr4_reserved_bits(__kvm_cpu_cap_has, UNUSED_); 11277 #undef __kvm_cpu_cap_has 11278 11279 if (kvm_has_tsc_control) { 11280 /* 11281 * Make sure the user can only configure tsc_khz values that 11282 * fit into a signed integer. 11283 * A min value is not calculated because it will always 11284 * be 1 on all machines. 11285 */ 11286 u64 max = min(0x7fffffffULL, 11287 __scale_tsc(kvm_max_tsc_scaling_ratio, tsc_khz)); 11288 kvm_max_guest_tsc_khz = max; 11289 11290 kvm_default_tsc_scaling_ratio = 1ULL << kvm_tsc_scaling_ratio_frac_bits; 11291 } 11292 11293 kvm_init_msr_list(); 11294 return 0; 11295 } 11296 11297 void kvm_arch_hardware_unsetup(void) 11298 { 11299 static_call(kvm_x86_hardware_unsetup)(); 11300 } 11301 11302 int kvm_arch_check_processor_compat(void *opaque) 11303 { 11304 struct cpuinfo_x86 *c = &cpu_data(smp_processor_id()); 11305 struct kvm_x86_init_ops *ops = opaque; 11306 11307 WARN_ON(!irqs_disabled()); 11308 11309 if (__cr4_reserved_bits(cpu_has, c) != 11310 __cr4_reserved_bits(cpu_has, &boot_cpu_data)) 11311 return -EIO; 11312 11313 return ops->check_processor_compatibility(); 11314 } 11315 11316 bool kvm_vcpu_is_reset_bsp(struct kvm_vcpu *vcpu) 11317 { 11318 return vcpu->kvm->arch.bsp_vcpu_id == vcpu->vcpu_id; 11319 } 11320 EXPORT_SYMBOL_GPL(kvm_vcpu_is_reset_bsp); 11321 11322 bool kvm_vcpu_is_bsp(struct kvm_vcpu *vcpu) 11323 { 11324 return (vcpu->arch.apic_base & MSR_IA32_APICBASE_BSP) != 0; 11325 } 11326 11327 __read_mostly DEFINE_STATIC_KEY_FALSE(kvm_has_noapic_vcpu); 11328 EXPORT_SYMBOL_GPL(kvm_has_noapic_vcpu); 11329 11330 void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu) 11331 { 11332 struct kvm_pmu *pmu = vcpu_to_pmu(vcpu); 11333 11334 vcpu->arch.l1tf_flush_l1d = true; 11335 if (pmu->version && unlikely(pmu->event_count)) { 11336 pmu->need_cleanup = true; 11337 kvm_make_request(KVM_REQ_PMU, vcpu); 11338 } 11339 static_call(kvm_x86_sched_in)(vcpu, cpu); 11340 } 11341 11342 void kvm_arch_free_vm(struct kvm *kvm) 11343 { 11344 kfree(to_kvm_hv(kvm)->hv_pa_pg); 11345 __kvm_arch_free_vm(kvm); 11346 } 11347 11348 11349 int kvm_arch_init_vm(struct kvm *kvm, unsigned long type) 11350 { 11351 int ret; 11352 unsigned long flags; 11353 11354 if (type) 11355 return -EINVAL; 11356 11357 ret = kvm_page_track_init(kvm); 11358 if (ret) 11359 return ret; 11360 11361 INIT_HLIST_HEAD(&kvm->arch.mask_notifier_list); 11362 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages); 11363 INIT_LIST_HEAD(&kvm->arch.zapped_obsolete_pages); 11364 INIT_LIST_HEAD(&kvm->arch.lpage_disallowed_mmu_pages); 11365 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head); 11366 atomic_set(&kvm->arch.noncoherent_dma_count, 0); 11367 11368 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */ 11369 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap); 11370 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */ 11371 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID, 11372 &kvm->arch.irq_sources_bitmap); 11373 11374 raw_spin_lock_init(&kvm->arch.tsc_write_lock); 11375 mutex_init(&kvm->arch.apic_map_lock); 11376 seqcount_raw_spinlock_init(&kvm->arch.pvclock_sc, &kvm->arch.tsc_write_lock); 11377 kvm->arch.kvmclock_offset = -get_kvmclock_base_ns(); 11378 11379 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags); 11380 pvclock_update_vm_gtod_copy(kvm); 11381 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags); 11382 11383 kvm->arch.guest_can_read_msr_platform_info = true; 11384 11385 #if IS_ENABLED(CONFIG_HYPERV) 11386 spin_lock_init(&kvm->arch.hv_root_tdp_lock); 11387 kvm->arch.hv_root_tdp = INVALID_PAGE; 11388 #endif 11389 11390 INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn); 11391 INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn); 11392 11393 kvm_apicv_init(kvm); 11394 kvm_hv_init_vm(kvm); 11395 kvm_mmu_init_vm(kvm); 11396 kvm_xen_init_vm(kvm); 11397 11398 return static_call(kvm_x86_vm_init)(kvm); 11399 } 11400 11401 int kvm_arch_post_init_vm(struct kvm *kvm) 11402 { 11403 return kvm_mmu_post_init_vm(kvm); 11404 } 11405 11406 static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu) 11407 { 11408 vcpu_load(vcpu); 11409 kvm_mmu_unload(vcpu); 11410 vcpu_put(vcpu); 11411 } 11412 11413 static void kvm_free_vcpus(struct kvm *kvm) 11414 { 11415 unsigned int i; 11416 struct kvm_vcpu *vcpu; 11417 11418 /* 11419 * Unpin any mmu pages first. 11420 */ 11421 kvm_for_each_vcpu(i, vcpu, kvm) { 11422 kvm_clear_async_pf_completion_queue(vcpu); 11423 kvm_unload_vcpu_mmu(vcpu); 11424 } 11425 kvm_for_each_vcpu(i, vcpu, kvm) 11426 kvm_vcpu_destroy(vcpu); 11427 11428 mutex_lock(&kvm->lock); 11429 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++) 11430 kvm->vcpus[i] = NULL; 11431 11432 atomic_set(&kvm->online_vcpus, 0); 11433 mutex_unlock(&kvm->lock); 11434 } 11435 11436 void kvm_arch_sync_events(struct kvm *kvm) 11437 { 11438 cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work); 11439 cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work); 11440 kvm_free_pit(kvm); 11441 } 11442 11443 #define ERR_PTR_USR(e) ((void __user *)ERR_PTR(e)) 11444 11445 /** 11446 * __x86_set_memory_region: Setup KVM internal memory slot 11447 * 11448 * @kvm: the kvm pointer to the VM. 11449 * @id: the slot ID to setup. 11450 * @gpa: the GPA to install the slot (unused when @size == 0). 11451 * @size: the size of the slot. Set to zero to uninstall a slot. 11452 * 11453 * This function helps to setup a KVM internal memory slot. Specify 11454 * @size > 0 to install a new slot, while @size == 0 to uninstall a 11455 * slot. The return code can be one of the following: 11456 * 11457 * HVA: on success (uninstall will return a bogus HVA) 11458 * -errno: on error 11459 * 11460 * The caller should always use IS_ERR() to check the return value 11461 * before use. Note, the KVM internal memory slots are guaranteed to 11462 * remain valid and unchanged until the VM is destroyed, i.e., the 11463 * GPA->HVA translation will not change. However, the HVA is a user 11464 * address, i.e. its accessibility is not guaranteed, and must be 11465 * accessed via __copy_{to,from}_user(). 11466 */ 11467 void __user * __x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, 11468 u32 size) 11469 { 11470 int i, r; 11471 unsigned long hva, old_npages; 11472 struct kvm_memslots *slots = kvm_memslots(kvm); 11473 struct kvm_memory_slot *slot; 11474 11475 /* Called with kvm->slots_lock held. */ 11476 if (WARN_ON(id >= KVM_MEM_SLOTS_NUM)) 11477 return ERR_PTR_USR(-EINVAL); 11478 11479 slot = id_to_memslot(slots, id); 11480 if (size) { 11481 if (slot && slot->npages) 11482 return ERR_PTR_USR(-EEXIST); 11483 11484 /* 11485 * MAP_SHARED to prevent internal slot pages from being moved 11486 * by fork()/COW. 11487 */ 11488 hva = vm_mmap(NULL, 0, size, PROT_READ | PROT_WRITE, 11489 MAP_SHARED | MAP_ANONYMOUS, 0); 11490 if (IS_ERR((void *)hva)) 11491 return (void __user *)hva; 11492 } else { 11493 if (!slot || !slot->npages) 11494 return NULL; 11495 11496 old_npages = slot->npages; 11497 hva = slot->userspace_addr; 11498 } 11499 11500 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) { 11501 struct kvm_userspace_memory_region m; 11502 11503 m.slot = id | (i << 16); 11504 m.flags = 0; 11505 m.guest_phys_addr = gpa; 11506 m.userspace_addr = hva; 11507 m.memory_size = size; 11508 r = __kvm_set_memory_region(kvm, &m); 11509 if (r < 0) 11510 return ERR_PTR_USR(r); 11511 } 11512 11513 if (!size) 11514 vm_munmap(hva, old_npages * PAGE_SIZE); 11515 11516 return (void __user *)hva; 11517 } 11518 EXPORT_SYMBOL_GPL(__x86_set_memory_region); 11519 11520 void kvm_arch_pre_destroy_vm(struct kvm *kvm) 11521 { 11522 kvm_mmu_pre_destroy_vm(kvm); 11523 } 11524 11525 void kvm_arch_destroy_vm(struct kvm *kvm) 11526 { 11527 if (current->mm == kvm->mm) { 11528 /* 11529 * Free memory regions allocated on behalf of userspace, 11530 * unless the the memory map has changed due to process exit 11531 * or fd copying. 11532 */ 11533 mutex_lock(&kvm->slots_lock); 11534 __x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT, 11535 0, 0); 11536 __x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT, 11537 0, 0); 11538 __x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, 0, 0); 11539 mutex_unlock(&kvm->slots_lock); 11540 } 11541 static_call_cond(kvm_x86_vm_destroy)(kvm); 11542 kvm_free_msr_filter(srcu_dereference_check(kvm->arch.msr_filter, &kvm->srcu, 1)); 11543 kvm_pic_destroy(kvm); 11544 kvm_ioapic_destroy(kvm); 11545 kvm_free_vcpus(kvm); 11546 kvfree(rcu_dereference_check(kvm->arch.apic_map, 1)); 11547 kfree(srcu_dereference_check(kvm->arch.pmu_event_filter, &kvm->srcu, 1)); 11548 kvm_mmu_uninit_vm(kvm); 11549 kvm_page_track_cleanup(kvm); 11550 kvm_xen_destroy_vm(kvm); 11551 kvm_hv_destroy_vm(kvm); 11552 } 11553 11554 static void memslot_rmap_free(struct kvm_memory_slot *slot) 11555 { 11556 int i; 11557 11558 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) { 11559 kvfree(slot->arch.rmap[i]); 11560 slot->arch.rmap[i] = NULL; 11561 } 11562 } 11563 11564 void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *slot) 11565 { 11566 int i; 11567 11568 memslot_rmap_free(slot); 11569 11570 for (i = 1; i < KVM_NR_PAGE_SIZES; ++i) { 11571 kvfree(slot->arch.lpage_info[i - 1]); 11572 slot->arch.lpage_info[i - 1] = NULL; 11573 } 11574 11575 kvm_page_track_free_memslot(slot); 11576 } 11577 11578 int memslot_rmap_alloc(struct kvm_memory_slot *slot, unsigned long npages) 11579 { 11580 const int sz = sizeof(*slot->arch.rmap[0]); 11581 int i; 11582 11583 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) { 11584 int level = i + 1; 11585 int lpages = __kvm_mmu_slot_lpages(slot, npages, level); 11586 11587 if (slot->arch.rmap[i]) 11588 continue; 11589 11590 slot->arch.rmap[i] = kvcalloc(lpages, sz, GFP_KERNEL_ACCOUNT); 11591 if (!slot->arch.rmap[i]) { 11592 memslot_rmap_free(slot); 11593 return -ENOMEM; 11594 } 11595 } 11596 11597 return 0; 11598 } 11599 11600 static int kvm_alloc_memslot_metadata(struct kvm *kvm, 11601 struct kvm_memory_slot *slot, 11602 unsigned long npages) 11603 { 11604 int i, r; 11605 11606 /* 11607 * Clear out the previous array pointers for the KVM_MR_MOVE case. The 11608 * old arrays will be freed by __kvm_set_memory_region() if installing 11609 * the new memslot is successful. 11610 */ 11611 memset(&slot->arch, 0, sizeof(slot->arch)); 11612 11613 if (kvm_memslots_have_rmaps(kvm)) { 11614 r = memslot_rmap_alloc(slot, npages); 11615 if (r) 11616 return r; 11617 } 11618 11619 for (i = 1; i < KVM_NR_PAGE_SIZES; ++i) { 11620 struct kvm_lpage_info *linfo; 11621 unsigned long ugfn; 11622 int lpages; 11623 int level = i + 1; 11624 11625 lpages = __kvm_mmu_slot_lpages(slot, npages, level); 11626 11627 linfo = kvcalloc(lpages, sizeof(*linfo), GFP_KERNEL_ACCOUNT); 11628 if (!linfo) 11629 goto out_free; 11630 11631 slot->arch.lpage_info[i - 1] = linfo; 11632 11633 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1)) 11634 linfo[0].disallow_lpage = 1; 11635 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1)) 11636 linfo[lpages - 1].disallow_lpage = 1; 11637 ugfn = slot->userspace_addr >> PAGE_SHIFT; 11638 /* 11639 * If the gfn and userspace address are not aligned wrt each 11640 * other, disable large page support for this slot. 11641 */ 11642 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1)) { 11643 unsigned long j; 11644 11645 for (j = 0; j < lpages; ++j) 11646 linfo[j].disallow_lpage = 1; 11647 } 11648 } 11649 11650 if (kvm_page_track_create_memslot(kvm, slot, npages)) 11651 goto out_free; 11652 11653 return 0; 11654 11655 out_free: 11656 memslot_rmap_free(slot); 11657 11658 for (i = 1; i < KVM_NR_PAGE_SIZES; ++i) { 11659 kvfree(slot->arch.lpage_info[i - 1]); 11660 slot->arch.lpage_info[i - 1] = NULL; 11661 } 11662 return -ENOMEM; 11663 } 11664 11665 void kvm_arch_memslots_updated(struct kvm *kvm, u64 gen) 11666 { 11667 struct kvm_vcpu *vcpu; 11668 int i; 11669 11670 /* 11671 * memslots->generation has been incremented. 11672 * mmio generation may have reached its maximum value. 11673 */ 11674 kvm_mmu_invalidate_mmio_sptes(kvm, gen); 11675 11676 /* Force re-initialization of steal_time cache */ 11677 kvm_for_each_vcpu(i, vcpu, kvm) 11678 kvm_vcpu_kick(vcpu); 11679 } 11680 11681 int kvm_arch_prepare_memory_region(struct kvm *kvm, 11682 struct kvm_memory_slot *memslot, 11683 const struct kvm_userspace_memory_region *mem, 11684 enum kvm_mr_change change) 11685 { 11686 if (change == KVM_MR_CREATE || change == KVM_MR_MOVE) 11687 return kvm_alloc_memslot_metadata(kvm, memslot, 11688 mem->memory_size >> PAGE_SHIFT); 11689 return 0; 11690 } 11691 11692 11693 static void kvm_mmu_update_cpu_dirty_logging(struct kvm *kvm, bool enable) 11694 { 11695 struct kvm_arch *ka = &kvm->arch; 11696 11697 if (!kvm_x86_ops.cpu_dirty_log_size) 11698 return; 11699 11700 if ((enable && ++ka->cpu_dirty_logging_count == 1) || 11701 (!enable && --ka->cpu_dirty_logging_count == 0)) 11702 kvm_make_all_cpus_request(kvm, KVM_REQ_UPDATE_CPU_DIRTY_LOGGING); 11703 11704 WARN_ON_ONCE(ka->cpu_dirty_logging_count < 0); 11705 } 11706 11707 static void kvm_mmu_slot_apply_flags(struct kvm *kvm, 11708 struct kvm_memory_slot *old, 11709 const struct kvm_memory_slot *new, 11710 enum kvm_mr_change change) 11711 { 11712 bool log_dirty_pages = new->flags & KVM_MEM_LOG_DIRTY_PAGES; 11713 11714 /* 11715 * Update CPU dirty logging if dirty logging is being toggled. This 11716 * applies to all operations. 11717 */ 11718 if ((old->flags ^ new->flags) & KVM_MEM_LOG_DIRTY_PAGES) 11719 kvm_mmu_update_cpu_dirty_logging(kvm, log_dirty_pages); 11720 11721 /* 11722 * Nothing more to do for RO slots (which can't be dirtied and can't be 11723 * made writable) or CREATE/MOVE/DELETE of a slot. 11724 * 11725 * For a memslot with dirty logging disabled: 11726 * CREATE: No dirty mappings will already exist. 11727 * MOVE/DELETE: The old mappings will already have been cleaned up by 11728 * kvm_arch_flush_shadow_memslot() 11729 * 11730 * For a memslot with dirty logging enabled: 11731 * CREATE: No shadow pages exist, thus nothing to write-protect 11732 * and no dirty bits to clear. 11733 * MOVE/DELETE: The old mappings will already have been cleaned up by 11734 * kvm_arch_flush_shadow_memslot(). 11735 */ 11736 if ((change != KVM_MR_FLAGS_ONLY) || (new->flags & KVM_MEM_READONLY)) 11737 return; 11738 11739 /* 11740 * READONLY and non-flags changes were filtered out above, and the only 11741 * other flag is LOG_DIRTY_PAGES, i.e. something is wrong if dirty 11742 * logging isn't being toggled on or off. 11743 */ 11744 if (WARN_ON_ONCE(!((old->flags ^ new->flags) & KVM_MEM_LOG_DIRTY_PAGES))) 11745 return; 11746 11747 if (!log_dirty_pages) { 11748 /* 11749 * Dirty logging tracks sptes in 4k granularity, meaning that 11750 * large sptes have to be split. If live migration succeeds, 11751 * the guest in the source machine will be destroyed and large 11752 * sptes will be created in the destination. However, if the 11753 * guest continues to run in the source machine (for example if 11754 * live migration fails), small sptes will remain around and 11755 * cause bad performance. 11756 * 11757 * Scan sptes if dirty logging has been stopped, dropping those 11758 * which can be collapsed into a single large-page spte. Later 11759 * page faults will create the large-page sptes. 11760 */ 11761 kvm_mmu_zap_collapsible_sptes(kvm, new); 11762 } else { 11763 /* 11764 * Initially-all-set does not require write protecting any page, 11765 * because they're all assumed to be dirty. 11766 */ 11767 if (kvm_dirty_log_manual_protect_and_init_set(kvm)) 11768 return; 11769 11770 if (kvm_x86_ops.cpu_dirty_log_size) { 11771 kvm_mmu_slot_leaf_clear_dirty(kvm, new); 11772 kvm_mmu_slot_remove_write_access(kvm, new, PG_LEVEL_2M); 11773 } else { 11774 kvm_mmu_slot_remove_write_access(kvm, new, PG_LEVEL_4K); 11775 } 11776 } 11777 } 11778 11779 void kvm_arch_commit_memory_region(struct kvm *kvm, 11780 const struct kvm_userspace_memory_region *mem, 11781 struct kvm_memory_slot *old, 11782 const struct kvm_memory_slot *new, 11783 enum kvm_mr_change change) 11784 { 11785 if (!kvm->arch.n_requested_mmu_pages) 11786 kvm_mmu_change_mmu_pages(kvm, 11787 kvm_mmu_calculate_default_mmu_pages(kvm)); 11788 11789 kvm_mmu_slot_apply_flags(kvm, old, new, change); 11790 11791 /* Free the arrays associated with the old memslot. */ 11792 if (change == KVM_MR_MOVE) 11793 kvm_arch_free_memslot(kvm, old); 11794 } 11795 11796 void kvm_arch_flush_shadow_all(struct kvm *kvm) 11797 { 11798 kvm_mmu_zap_all(kvm); 11799 } 11800 11801 void kvm_arch_flush_shadow_memslot(struct kvm *kvm, 11802 struct kvm_memory_slot *slot) 11803 { 11804 kvm_page_track_flush_slot(kvm, slot); 11805 } 11806 11807 static inline bool kvm_guest_apic_has_interrupt(struct kvm_vcpu *vcpu) 11808 { 11809 return (is_guest_mode(vcpu) && 11810 kvm_x86_ops.guest_apic_has_interrupt && 11811 static_call(kvm_x86_guest_apic_has_interrupt)(vcpu)); 11812 } 11813 11814 static inline bool kvm_vcpu_has_events(struct kvm_vcpu *vcpu) 11815 { 11816 if (!list_empty_careful(&vcpu->async_pf.done)) 11817 return true; 11818 11819 if (kvm_apic_has_events(vcpu)) 11820 return true; 11821 11822 if (vcpu->arch.pv.pv_unhalted) 11823 return true; 11824 11825 if (vcpu->arch.exception.pending) 11826 return true; 11827 11828 if (kvm_test_request(KVM_REQ_NMI, vcpu) || 11829 (vcpu->arch.nmi_pending && 11830 static_call(kvm_x86_nmi_allowed)(vcpu, false))) 11831 return true; 11832 11833 if (kvm_test_request(KVM_REQ_SMI, vcpu) || 11834 (vcpu->arch.smi_pending && 11835 static_call(kvm_x86_smi_allowed)(vcpu, false))) 11836 return true; 11837 11838 if (kvm_arch_interrupt_allowed(vcpu) && 11839 (kvm_cpu_has_interrupt(vcpu) || 11840 kvm_guest_apic_has_interrupt(vcpu))) 11841 return true; 11842 11843 if (kvm_hv_has_stimer_pending(vcpu)) 11844 return true; 11845 11846 if (is_guest_mode(vcpu) && 11847 kvm_x86_ops.nested_ops->hv_timer_pending && 11848 kvm_x86_ops.nested_ops->hv_timer_pending(vcpu)) 11849 return true; 11850 11851 return false; 11852 } 11853 11854 int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu) 11855 { 11856 return kvm_vcpu_running(vcpu) || kvm_vcpu_has_events(vcpu); 11857 } 11858 11859 bool kvm_arch_dy_has_pending_interrupt(struct kvm_vcpu *vcpu) 11860 { 11861 if (vcpu->arch.apicv_active && static_call(kvm_x86_dy_apicv_has_pending_interrupt)(vcpu)) 11862 return true; 11863 11864 return false; 11865 } 11866 11867 bool kvm_arch_dy_runnable(struct kvm_vcpu *vcpu) 11868 { 11869 if (READ_ONCE(vcpu->arch.pv.pv_unhalted)) 11870 return true; 11871 11872 if (kvm_test_request(KVM_REQ_NMI, vcpu) || 11873 kvm_test_request(KVM_REQ_SMI, vcpu) || 11874 kvm_test_request(KVM_REQ_EVENT, vcpu)) 11875 return true; 11876 11877 return kvm_arch_dy_has_pending_interrupt(vcpu); 11878 } 11879 11880 bool kvm_arch_vcpu_in_kernel(struct kvm_vcpu *vcpu) 11881 { 11882 if (vcpu->arch.guest_state_protected) 11883 return true; 11884 11885 return vcpu->arch.preempted_in_kernel; 11886 } 11887 11888 int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu) 11889 { 11890 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE; 11891 } 11892 11893 int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu) 11894 { 11895 return static_call(kvm_x86_interrupt_allowed)(vcpu, false); 11896 } 11897 11898 unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu) 11899 { 11900 /* Can't read the RIP when guest state is protected, just return 0 */ 11901 if (vcpu->arch.guest_state_protected) 11902 return 0; 11903 11904 if (is_64_bit_mode(vcpu)) 11905 return kvm_rip_read(vcpu); 11906 return (u32)(get_segment_base(vcpu, VCPU_SREG_CS) + 11907 kvm_rip_read(vcpu)); 11908 } 11909 EXPORT_SYMBOL_GPL(kvm_get_linear_rip); 11910 11911 bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip) 11912 { 11913 return kvm_get_linear_rip(vcpu) == linear_rip; 11914 } 11915 EXPORT_SYMBOL_GPL(kvm_is_linear_rip); 11916 11917 unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu) 11918 { 11919 unsigned long rflags; 11920 11921 rflags = static_call(kvm_x86_get_rflags)(vcpu); 11922 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) 11923 rflags &= ~X86_EFLAGS_TF; 11924 return rflags; 11925 } 11926 EXPORT_SYMBOL_GPL(kvm_get_rflags); 11927 11928 static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags) 11929 { 11930 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP && 11931 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip)) 11932 rflags |= X86_EFLAGS_TF; 11933 static_call(kvm_x86_set_rflags)(vcpu, rflags); 11934 } 11935 11936 void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags) 11937 { 11938 __kvm_set_rflags(vcpu, rflags); 11939 kvm_make_request(KVM_REQ_EVENT, vcpu); 11940 } 11941 EXPORT_SYMBOL_GPL(kvm_set_rflags); 11942 11943 void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work) 11944 { 11945 int r; 11946 11947 if ((vcpu->arch.mmu->direct_map != work->arch.direct_map) || 11948 work->wakeup_all) 11949 return; 11950 11951 r = kvm_mmu_reload(vcpu); 11952 if (unlikely(r)) 11953 return; 11954 11955 if (!vcpu->arch.mmu->direct_map && 11956 work->arch.cr3 != vcpu->arch.mmu->get_guest_pgd(vcpu)) 11957 return; 11958 11959 kvm_mmu_do_page_fault(vcpu, work->cr2_or_gpa, 0, true); 11960 } 11961 11962 static inline u32 kvm_async_pf_hash_fn(gfn_t gfn) 11963 { 11964 BUILD_BUG_ON(!is_power_of_2(ASYNC_PF_PER_VCPU)); 11965 11966 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU)); 11967 } 11968 11969 static inline u32 kvm_async_pf_next_probe(u32 key) 11970 { 11971 return (key + 1) & (ASYNC_PF_PER_VCPU - 1); 11972 } 11973 11974 static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn) 11975 { 11976 u32 key = kvm_async_pf_hash_fn(gfn); 11977 11978 while (vcpu->arch.apf.gfns[key] != ~0) 11979 key = kvm_async_pf_next_probe(key); 11980 11981 vcpu->arch.apf.gfns[key] = gfn; 11982 } 11983 11984 static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn) 11985 { 11986 int i; 11987 u32 key = kvm_async_pf_hash_fn(gfn); 11988 11989 for (i = 0; i < ASYNC_PF_PER_VCPU && 11990 (vcpu->arch.apf.gfns[key] != gfn && 11991 vcpu->arch.apf.gfns[key] != ~0); i++) 11992 key = kvm_async_pf_next_probe(key); 11993 11994 return key; 11995 } 11996 11997 bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn) 11998 { 11999 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn; 12000 } 12001 12002 static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn) 12003 { 12004 u32 i, j, k; 12005 12006 i = j = kvm_async_pf_gfn_slot(vcpu, gfn); 12007 12008 if (WARN_ON_ONCE(vcpu->arch.apf.gfns[i] != gfn)) 12009 return; 12010 12011 while (true) { 12012 vcpu->arch.apf.gfns[i] = ~0; 12013 do { 12014 j = kvm_async_pf_next_probe(j); 12015 if (vcpu->arch.apf.gfns[j] == ~0) 12016 return; 12017 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]); 12018 /* 12019 * k lies cyclically in ]i,j] 12020 * | i.k.j | 12021 * |....j i.k.| or |.k..j i...| 12022 */ 12023 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j)); 12024 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j]; 12025 i = j; 12026 } 12027 } 12028 12029 static inline int apf_put_user_notpresent(struct kvm_vcpu *vcpu) 12030 { 12031 u32 reason = KVM_PV_REASON_PAGE_NOT_PRESENT; 12032 12033 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &reason, 12034 sizeof(reason)); 12035 } 12036 12037 static inline int apf_put_user_ready(struct kvm_vcpu *vcpu, u32 token) 12038 { 12039 unsigned int offset = offsetof(struct kvm_vcpu_pv_apf_data, token); 12040 12041 return kvm_write_guest_offset_cached(vcpu->kvm, &vcpu->arch.apf.data, 12042 &token, offset, sizeof(token)); 12043 } 12044 12045 static inline bool apf_pageready_slot_free(struct kvm_vcpu *vcpu) 12046 { 12047 unsigned int offset = offsetof(struct kvm_vcpu_pv_apf_data, token); 12048 u32 val; 12049 12050 if (kvm_read_guest_offset_cached(vcpu->kvm, &vcpu->arch.apf.data, 12051 &val, offset, sizeof(val))) 12052 return false; 12053 12054 return !val; 12055 } 12056 12057 static bool kvm_can_deliver_async_pf(struct kvm_vcpu *vcpu) 12058 { 12059 if (!vcpu->arch.apf.delivery_as_pf_vmexit && is_guest_mode(vcpu)) 12060 return false; 12061 12062 if (!kvm_pv_async_pf_enabled(vcpu) || 12063 (vcpu->arch.apf.send_user_only && static_call(kvm_x86_get_cpl)(vcpu) == 0)) 12064 return false; 12065 12066 return true; 12067 } 12068 12069 bool kvm_can_do_async_pf(struct kvm_vcpu *vcpu) 12070 { 12071 if (unlikely(!lapic_in_kernel(vcpu) || 12072 kvm_event_needs_reinjection(vcpu) || 12073 vcpu->arch.exception.pending)) 12074 return false; 12075 12076 if (kvm_hlt_in_guest(vcpu->kvm) && !kvm_can_deliver_async_pf(vcpu)) 12077 return false; 12078 12079 /* 12080 * If interrupts are off we cannot even use an artificial 12081 * halt state. 12082 */ 12083 return kvm_arch_interrupt_allowed(vcpu); 12084 } 12085 12086 bool kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu, 12087 struct kvm_async_pf *work) 12088 { 12089 struct x86_exception fault; 12090 12091 trace_kvm_async_pf_not_present(work->arch.token, work->cr2_or_gpa); 12092 kvm_add_async_pf_gfn(vcpu, work->arch.gfn); 12093 12094 if (kvm_can_deliver_async_pf(vcpu) && 12095 !apf_put_user_notpresent(vcpu)) { 12096 fault.vector = PF_VECTOR; 12097 fault.error_code_valid = true; 12098 fault.error_code = 0; 12099 fault.nested_page_fault = false; 12100 fault.address = work->arch.token; 12101 fault.async_page_fault = true; 12102 kvm_inject_page_fault(vcpu, &fault); 12103 return true; 12104 } else { 12105 /* 12106 * It is not possible to deliver a paravirtualized asynchronous 12107 * page fault, but putting the guest in an artificial halt state 12108 * can be beneficial nevertheless: if an interrupt arrives, we 12109 * can deliver it timely and perhaps the guest will schedule 12110 * another process. When the instruction that triggered a page 12111 * fault is retried, hopefully the page will be ready in the host. 12112 */ 12113 kvm_make_request(KVM_REQ_APF_HALT, vcpu); 12114 return false; 12115 } 12116 } 12117 12118 void kvm_arch_async_page_present(struct kvm_vcpu *vcpu, 12119 struct kvm_async_pf *work) 12120 { 12121 struct kvm_lapic_irq irq = { 12122 .delivery_mode = APIC_DM_FIXED, 12123 .vector = vcpu->arch.apf.vec 12124 }; 12125 12126 if (work->wakeup_all) 12127 work->arch.token = ~0; /* broadcast wakeup */ 12128 else 12129 kvm_del_async_pf_gfn(vcpu, work->arch.gfn); 12130 trace_kvm_async_pf_ready(work->arch.token, work->cr2_or_gpa); 12131 12132 if ((work->wakeup_all || work->notpresent_injected) && 12133 kvm_pv_async_pf_enabled(vcpu) && 12134 !apf_put_user_ready(vcpu, work->arch.token)) { 12135 vcpu->arch.apf.pageready_pending = true; 12136 kvm_apic_set_irq(vcpu, &irq, NULL); 12137 } 12138 12139 vcpu->arch.apf.halted = false; 12140 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; 12141 } 12142 12143 void kvm_arch_async_page_present_queued(struct kvm_vcpu *vcpu) 12144 { 12145 kvm_make_request(KVM_REQ_APF_READY, vcpu); 12146 if (!vcpu->arch.apf.pageready_pending) 12147 kvm_vcpu_kick(vcpu); 12148 } 12149 12150 bool kvm_arch_can_dequeue_async_page_present(struct kvm_vcpu *vcpu) 12151 { 12152 if (!kvm_pv_async_pf_enabled(vcpu)) 12153 return true; 12154 else 12155 return kvm_lapic_enabled(vcpu) && apf_pageready_slot_free(vcpu); 12156 } 12157 12158 void kvm_arch_start_assignment(struct kvm *kvm) 12159 { 12160 if (atomic_inc_return(&kvm->arch.assigned_device_count) == 1) 12161 static_call_cond(kvm_x86_start_assignment)(kvm); 12162 } 12163 EXPORT_SYMBOL_GPL(kvm_arch_start_assignment); 12164 12165 void kvm_arch_end_assignment(struct kvm *kvm) 12166 { 12167 atomic_dec(&kvm->arch.assigned_device_count); 12168 } 12169 EXPORT_SYMBOL_GPL(kvm_arch_end_assignment); 12170 12171 bool kvm_arch_has_assigned_device(struct kvm *kvm) 12172 { 12173 return atomic_read(&kvm->arch.assigned_device_count); 12174 } 12175 EXPORT_SYMBOL_GPL(kvm_arch_has_assigned_device); 12176 12177 void kvm_arch_register_noncoherent_dma(struct kvm *kvm) 12178 { 12179 atomic_inc(&kvm->arch.noncoherent_dma_count); 12180 } 12181 EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma); 12182 12183 void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm) 12184 { 12185 atomic_dec(&kvm->arch.noncoherent_dma_count); 12186 } 12187 EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma); 12188 12189 bool kvm_arch_has_noncoherent_dma(struct kvm *kvm) 12190 { 12191 return atomic_read(&kvm->arch.noncoherent_dma_count); 12192 } 12193 EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma); 12194 12195 bool kvm_arch_has_irq_bypass(void) 12196 { 12197 return true; 12198 } 12199 12200 int kvm_arch_irq_bypass_add_producer(struct irq_bypass_consumer *cons, 12201 struct irq_bypass_producer *prod) 12202 { 12203 struct kvm_kernel_irqfd *irqfd = 12204 container_of(cons, struct kvm_kernel_irqfd, consumer); 12205 int ret; 12206 12207 irqfd->producer = prod; 12208 kvm_arch_start_assignment(irqfd->kvm); 12209 ret = static_call(kvm_x86_update_pi_irte)(irqfd->kvm, 12210 prod->irq, irqfd->gsi, 1); 12211 12212 if (ret) 12213 kvm_arch_end_assignment(irqfd->kvm); 12214 12215 return ret; 12216 } 12217 12218 void kvm_arch_irq_bypass_del_producer(struct irq_bypass_consumer *cons, 12219 struct irq_bypass_producer *prod) 12220 { 12221 int ret; 12222 struct kvm_kernel_irqfd *irqfd = 12223 container_of(cons, struct kvm_kernel_irqfd, consumer); 12224 12225 WARN_ON(irqfd->producer != prod); 12226 irqfd->producer = NULL; 12227 12228 /* 12229 * When producer of consumer is unregistered, we change back to 12230 * remapped mode, so we can re-use the current implementation 12231 * when the irq is masked/disabled or the consumer side (KVM 12232 * int this case doesn't want to receive the interrupts. 12233 */ 12234 ret = static_call(kvm_x86_update_pi_irte)(irqfd->kvm, prod->irq, irqfd->gsi, 0); 12235 if (ret) 12236 printk(KERN_INFO "irq bypass consumer (token %p) unregistration" 12237 " fails: %d\n", irqfd->consumer.token, ret); 12238 12239 kvm_arch_end_assignment(irqfd->kvm); 12240 } 12241 12242 int kvm_arch_update_irqfd_routing(struct kvm *kvm, unsigned int host_irq, 12243 uint32_t guest_irq, bool set) 12244 { 12245 return static_call(kvm_x86_update_pi_irte)(kvm, host_irq, guest_irq, set); 12246 } 12247 12248 bool kvm_arch_irqfd_route_changed(struct kvm_kernel_irq_routing_entry *old, 12249 struct kvm_kernel_irq_routing_entry *new) 12250 { 12251 if (new->type != KVM_IRQ_ROUTING_MSI) 12252 return true; 12253 12254 return !!memcmp(&old->msi, &new->msi, sizeof(new->msi)); 12255 } 12256 12257 bool kvm_vector_hashing_enabled(void) 12258 { 12259 return vector_hashing; 12260 } 12261 12262 bool kvm_arch_no_poll(struct kvm_vcpu *vcpu) 12263 { 12264 return (vcpu->arch.msr_kvm_poll_control & 1) == 0; 12265 } 12266 EXPORT_SYMBOL_GPL(kvm_arch_no_poll); 12267 12268 12269 int kvm_spec_ctrl_test_value(u64 value) 12270 { 12271 /* 12272 * test that setting IA32_SPEC_CTRL to given value 12273 * is allowed by the host processor 12274 */ 12275 12276 u64 saved_value; 12277 unsigned long flags; 12278 int ret = 0; 12279 12280 local_irq_save(flags); 12281 12282 if (rdmsrl_safe(MSR_IA32_SPEC_CTRL, &saved_value)) 12283 ret = 1; 12284 else if (wrmsrl_safe(MSR_IA32_SPEC_CTRL, value)) 12285 ret = 1; 12286 else 12287 wrmsrl(MSR_IA32_SPEC_CTRL, saved_value); 12288 12289 local_irq_restore(flags); 12290 12291 return ret; 12292 } 12293 EXPORT_SYMBOL_GPL(kvm_spec_ctrl_test_value); 12294 12295 void kvm_fixup_and_inject_pf_error(struct kvm_vcpu *vcpu, gva_t gva, u16 error_code) 12296 { 12297 struct x86_exception fault; 12298 u32 access = error_code & 12299 (PFERR_WRITE_MASK | PFERR_FETCH_MASK | PFERR_USER_MASK); 12300 12301 if (!(error_code & PFERR_PRESENT_MASK) || 12302 vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, &fault) != UNMAPPED_GVA) { 12303 /* 12304 * If vcpu->arch.walk_mmu->gva_to_gpa succeeded, the page 12305 * tables probably do not match the TLB. Just proceed 12306 * with the error code that the processor gave. 12307 */ 12308 fault.vector = PF_VECTOR; 12309 fault.error_code_valid = true; 12310 fault.error_code = error_code; 12311 fault.nested_page_fault = false; 12312 fault.address = gva; 12313 } 12314 vcpu->arch.walk_mmu->inject_page_fault(vcpu, &fault); 12315 } 12316 EXPORT_SYMBOL_GPL(kvm_fixup_and_inject_pf_error); 12317 12318 /* 12319 * Handles kvm_read/write_guest_virt*() result and either injects #PF or returns 12320 * KVM_EXIT_INTERNAL_ERROR for cases not currently handled by KVM. Return value 12321 * indicates whether exit to userspace is needed. 12322 */ 12323 int kvm_handle_memory_failure(struct kvm_vcpu *vcpu, int r, 12324 struct x86_exception *e) 12325 { 12326 if (r == X86EMUL_PROPAGATE_FAULT) { 12327 kvm_inject_emulated_page_fault(vcpu, e); 12328 return 1; 12329 } 12330 12331 /* 12332 * In case kvm_read/write_guest_virt*() failed with X86EMUL_IO_NEEDED 12333 * while handling a VMX instruction KVM could've handled the request 12334 * correctly by exiting to userspace and performing I/O but there 12335 * doesn't seem to be a real use-case behind such requests, just return 12336 * KVM_EXIT_INTERNAL_ERROR for now. 12337 */ 12338 kvm_prepare_emulation_failure_exit(vcpu); 12339 12340 return 0; 12341 } 12342 EXPORT_SYMBOL_GPL(kvm_handle_memory_failure); 12343 12344 int kvm_handle_invpcid(struct kvm_vcpu *vcpu, unsigned long type, gva_t gva) 12345 { 12346 bool pcid_enabled; 12347 struct x86_exception e; 12348 struct { 12349 u64 pcid; 12350 u64 gla; 12351 } operand; 12352 int r; 12353 12354 r = kvm_read_guest_virt(vcpu, gva, &operand, sizeof(operand), &e); 12355 if (r != X86EMUL_CONTINUE) 12356 return kvm_handle_memory_failure(vcpu, r, &e); 12357 12358 if (operand.pcid >> 12 != 0) { 12359 kvm_inject_gp(vcpu, 0); 12360 return 1; 12361 } 12362 12363 pcid_enabled = kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE); 12364 12365 switch (type) { 12366 case INVPCID_TYPE_INDIV_ADDR: 12367 if ((!pcid_enabled && (operand.pcid != 0)) || 12368 is_noncanonical_address(operand.gla, vcpu)) { 12369 kvm_inject_gp(vcpu, 0); 12370 return 1; 12371 } 12372 kvm_mmu_invpcid_gva(vcpu, operand.gla, operand.pcid); 12373 return kvm_skip_emulated_instruction(vcpu); 12374 12375 case INVPCID_TYPE_SINGLE_CTXT: 12376 if (!pcid_enabled && (operand.pcid != 0)) { 12377 kvm_inject_gp(vcpu, 0); 12378 return 1; 12379 } 12380 12381 kvm_invalidate_pcid(vcpu, operand.pcid); 12382 return kvm_skip_emulated_instruction(vcpu); 12383 12384 case INVPCID_TYPE_ALL_NON_GLOBAL: 12385 /* 12386 * Currently, KVM doesn't mark global entries in the shadow 12387 * page tables, so a non-global flush just degenerates to a 12388 * global flush. If needed, we could optimize this later by 12389 * keeping track of global entries in shadow page tables. 12390 */ 12391 12392 fallthrough; 12393 case INVPCID_TYPE_ALL_INCL_GLOBAL: 12394 kvm_make_request(KVM_REQ_TLB_FLUSH_GUEST, vcpu); 12395 return kvm_skip_emulated_instruction(vcpu); 12396 12397 default: 12398 kvm_inject_gp(vcpu, 0); 12399 return 1; 12400 } 12401 } 12402 EXPORT_SYMBOL_GPL(kvm_handle_invpcid); 12403 12404 static int complete_sev_es_emulated_mmio(struct kvm_vcpu *vcpu) 12405 { 12406 struct kvm_run *run = vcpu->run; 12407 struct kvm_mmio_fragment *frag; 12408 unsigned int len; 12409 12410 BUG_ON(!vcpu->mmio_needed); 12411 12412 /* Complete previous fragment */ 12413 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment]; 12414 len = min(8u, frag->len); 12415 if (!vcpu->mmio_is_write) 12416 memcpy(frag->data, run->mmio.data, len); 12417 12418 if (frag->len <= 8) { 12419 /* Switch to the next fragment. */ 12420 frag++; 12421 vcpu->mmio_cur_fragment++; 12422 } else { 12423 /* Go forward to the next mmio piece. */ 12424 frag->data += len; 12425 frag->gpa += len; 12426 frag->len -= len; 12427 } 12428 12429 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) { 12430 vcpu->mmio_needed = 0; 12431 12432 // VMG change, at this point, we're always done 12433 // RIP has already been advanced 12434 return 1; 12435 } 12436 12437 // More MMIO is needed 12438 run->mmio.phys_addr = frag->gpa; 12439 run->mmio.len = min(8u, frag->len); 12440 run->mmio.is_write = vcpu->mmio_is_write; 12441 if (run->mmio.is_write) 12442 memcpy(run->mmio.data, frag->data, min(8u, frag->len)); 12443 run->exit_reason = KVM_EXIT_MMIO; 12444 12445 vcpu->arch.complete_userspace_io = complete_sev_es_emulated_mmio; 12446 12447 return 0; 12448 } 12449 12450 int kvm_sev_es_mmio_write(struct kvm_vcpu *vcpu, gpa_t gpa, unsigned int bytes, 12451 void *data) 12452 { 12453 int handled; 12454 struct kvm_mmio_fragment *frag; 12455 12456 if (!data) 12457 return -EINVAL; 12458 12459 handled = write_emultor.read_write_mmio(vcpu, gpa, bytes, data); 12460 if (handled == bytes) 12461 return 1; 12462 12463 bytes -= handled; 12464 gpa += handled; 12465 data += handled; 12466 12467 /*TODO: Check if need to increment number of frags */ 12468 frag = vcpu->mmio_fragments; 12469 vcpu->mmio_nr_fragments = 1; 12470 frag->len = bytes; 12471 frag->gpa = gpa; 12472 frag->data = data; 12473 12474 vcpu->mmio_needed = 1; 12475 vcpu->mmio_cur_fragment = 0; 12476 12477 vcpu->run->mmio.phys_addr = gpa; 12478 vcpu->run->mmio.len = min(8u, frag->len); 12479 vcpu->run->mmio.is_write = 1; 12480 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len)); 12481 vcpu->run->exit_reason = KVM_EXIT_MMIO; 12482 12483 vcpu->arch.complete_userspace_io = complete_sev_es_emulated_mmio; 12484 12485 return 0; 12486 } 12487 EXPORT_SYMBOL_GPL(kvm_sev_es_mmio_write); 12488 12489 int kvm_sev_es_mmio_read(struct kvm_vcpu *vcpu, gpa_t gpa, unsigned int bytes, 12490 void *data) 12491 { 12492 int handled; 12493 struct kvm_mmio_fragment *frag; 12494 12495 if (!data) 12496 return -EINVAL; 12497 12498 handled = read_emultor.read_write_mmio(vcpu, gpa, bytes, data); 12499 if (handled == bytes) 12500 return 1; 12501 12502 bytes -= handled; 12503 gpa += handled; 12504 data += handled; 12505 12506 /*TODO: Check if need to increment number of frags */ 12507 frag = vcpu->mmio_fragments; 12508 vcpu->mmio_nr_fragments = 1; 12509 frag->len = bytes; 12510 frag->gpa = gpa; 12511 frag->data = data; 12512 12513 vcpu->mmio_needed = 1; 12514 vcpu->mmio_cur_fragment = 0; 12515 12516 vcpu->run->mmio.phys_addr = gpa; 12517 vcpu->run->mmio.len = min(8u, frag->len); 12518 vcpu->run->mmio.is_write = 0; 12519 vcpu->run->exit_reason = KVM_EXIT_MMIO; 12520 12521 vcpu->arch.complete_userspace_io = complete_sev_es_emulated_mmio; 12522 12523 return 0; 12524 } 12525 EXPORT_SYMBOL_GPL(kvm_sev_es_mmio_read); 12526 12527 static int kvm_sev_es_outs(struct kvm_vcpu *vcpu, unsigned int size, 12528 unsigned int port); 12529 12530 static int complete_sev_es_emulated_outs(struct kvm_vcpu *vcpu) 12531 { 12532 int size = vcpu->arch.pio.size; 12533 int port = vcpu->arch.pio.port; 12534 12535 vcpu->arch.pio.count = 0; 12536 if (vcpu->arch.sev_pio_count) 12537 return kvm_sev_es_outs(vcpu, size, port); 12538 return 1; 12539 } 12540 12541 static int kvm_sev_es_outs(struct kvm_vcpu *vcpu, unsigned int size, 12542 unsigned int port) 12543 { 12544 for (;;) { 12545 unsigned int count = 12546 min_t(unsigned int, PAGE_SIZE / size, vcpu->arch.sev_pio_count); 12547 int ret = emulator_pio_out(vcpu, size, port, vcpu->arch.sev_pio_data, count); 12548 12549 /* memcpy done already by emulator_pio_out. */ 12550 vcpu->arch.sev_pio_count -= count; 12551 vcpu->arch.sev_pio_data += count * vcpu->arch.pio.size; 12552 if (!ret) 12553 break; 12554 12555 /* Emulation done by the kernel. */ 12556 if (!vcpu->arch.sev_pio_count) 12557 return 1; 12558 } 12559 12560 vcpu->arch.complete_userspace_io = complete_sev_es_emulated_outs; 12561 return 0; 12562 } 12563 12564 static int kvm_sev_es_ins(struct kvm_vcpu *vcpu, unsigned int size, 12565 unsigned int port); 12566 12567 static void advance_sev_es_emulated_ins(struct kvm_vcpu *vcpu) 12568 { 12569 unsigned count = vcpu->arch.pio.count; 12570 complete_emulator_pio_in(vcpu, vcpu->arch.sev_pio_data); 12571 vcpu->arch.sev_pio_count -= count; 12572 vcpu->arch.sev_pio_data += count * vcpu->arch.pio.size; 12573 } 12574 12575 static int complete_sev_es_emulated_ins(struct kvm_vcpu *vcpu) 12576 { 12577 int size = vcpu->arch.pio.size; 12578 int port = vcpu->arch.pio.port; 12579 12580 advance_sev_es_emulated_ins(vcpu); 12581 if (vcpu->arch.sev_pio_count) 12582 return kvm_sev_es_ins(vcpu, size, port); 12583 return 1; 12584 } 12585 12586 static int kvm_sev_es_ins(struct kvm_vcpu *vcpu, unsigned int size, 12587 unsigned int port) 12588 { 12589 for (;;) { 12590 unsigned int count = 12591 min_t(unsigned int, PAGE_SIZE / size, vcpu->arch.sev_pio_count); 12592 if (!__emulator_pio_in(vcpu, size, port, count)) 12593 break; 12594 12595 /* Emulation done by the kernel. */ 12596 advance_sev_es_emulated_ins(vcpu); 12597 if (!vcpu->arch.sev_pio_count) 12598 return 1; 12599 } 12600 12601 vcpu->arch.complete_userspace_io = complete_sev_es_emulated_ins; 12602 return 0; 12603 } 12604 12605 int kvm_sev_es_string_io(struct kvm_vcpu *vcpu, unsigned int size, 12606 unsigned int port, void *data, unsigned int count, 12607 int in) 12608 { 12609 vcpu->arch.sev_pio_data = data; 12610 vcpu->arch.sev_pio_count = count; 12611 return in ? kvm_sev_es_ins(vcpu, size, port) 12612 : kvm_sev_es_outs(vcpu, size, port); 12613 } 12614 EXPORT_SYMBOL_GPL(kvm_sev_es_string_io); 12615 12616 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_entry); 12617 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit); 12618 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_fast_mmio); 12619 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq); 12620 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault); 12621 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr); 12622 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr); 12623 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun); 12624 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit); 12625 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject); 12626 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit); 12627 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmenter_failed); 12628 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga); 12629 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit); 12630 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts); 12631 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset); 12632 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_ple_window_update); 12633 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pml_full); 12634 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pi_irte_update); 12635 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_unaccelerated_access); 12636 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_incomplete_ipi); 12637 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_ga_log); 12638 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_apicv_update_request); 12639 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_vmgexit_enter); 12640 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_vmgexit_exit); 12641 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_vmgexit_msr_protocol_enter); 12642 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_vmgexit_msr_protocol_exit); 12643