1 /* 2 * Kernel-based Virtual Machine driver for Linux 3 * 4 * derived from drivers/kvm/kvm_main.c 5 * 6 * Copyright (C) 2006 Qumranet, Inc. 7 * Copyright (C) 2008 Qumranet, Inc. 8 * Copyright IBM Corporation, 2008 9 * Copyright 2010 Red Hat, Inc. and/or its affiliates. 10 * 11 * Authors: 12 * Avi Kivity <avi@qumranet.com> 13 * Yaniv Kamay <yaniv@qumranet.com> 14 * Amit Shah <amit.shah@qumranet.com> 15 * Ben-Ami Yassour <benami@il.ibm.com> 16 * 17 * This work is licensed under the terms of the GNU GPL, version 2. See 18 * the COPYING file in the top-level directory. 19 * 20 */ 21 22 #include <linux/kvm_host.h> 23 #include "irq.h" 24 #include "mmu.h" 25 #include "i8254.h" 26 #include "tss.h" 27 #include "kvm_cache_regs.h" 28 #include "x86.h" 29 #include "cpuid.h" 30 #include "assigned-dev.h" 31 #include "pmu.h" 32 #include "hyperv.h" 33 34 #include <linux/clocksource.h> 35 #include <linux/interrupt.h> 36 #include <linux/kvm.h> 37 #include <linux/fs.h> 38 #include <linux/vmalloc.h> 39 #include <linux/export.h> 40 #include <linux/moduleparam.h> 41 #include <linux/mman.h> 42 #include <linux/highmem.h> 43 #include <linux/iommu.h> 44 #include <linux/intel-iommu.h> 45 #include <linux/cpufreq.h> 46 #include <linux/user-return-notifier.h> 47 #include <linux/srcu.h> 48 #include <linux/slab.h> 49 #include <linux/perf_event.h> 50 #include <linux/uaccess.h> 51 #include <linux/hash.h> 52 #include <linux/pci.h> 53 #include <linux/timekeeper_internal.h> 54 #include <linux/pvclock_gtod.h> 55 #include <linux/kvm_irqfd.h> 56 #include <linux/irqbypass.h> 57 #include <trace/events/kvm.h> 58 59 #include <asm/debugreg.h> 60 #include <asm/msr.h> 61 #include <asm/desc.h> 62 #include <asm/mce.h> 63 #include <linux/kernel_stat.h> 64 #include <asm/fpu/internal.h> /* Ugh! */ 65 #include <asm/pvclock.h> 66 #include <asm/div64.h> 67 #include <asm/irq_remapping.h> 68 69 #define CREATE_TRACE_POINTS 70 #include "trace.h" 71 72 #define MAX_IO_MSRS 256 73 #define KVM_MAX_MCE_BANKS 32 74 u64 __read_mostly kvm_mce_cap_supported = MCG_CTL_P | MCG_SER_P; 75 EXPORT_SYMBOL_GPL(kvm_mce_cap_supported); 76 77 #define emul_to_vcpu(ctxt) \ 78 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt) 79 80 /* EFER defaults: 81 * - enable syscall per default because its emulated by KVM 82 * - enable LME and LMA per default on 64 bit KVM 83 */ 84 #ifdef CONFIG_X86_64 85 static 86 u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA)); 87 #else 88 static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE); 89 #endif 90 91 #define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM 92 #define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU 93 94 #define KVM_X2APIC_API_VALID_FLAGS (KVM_X2APIC_API_USE_32BIT_IDS | \ 95 KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK) 96 97 static void update_cr8_intercept(struct kvm_vcpu *vcpu); 98 static void process_nmi(struct kvm_vcpu *vcpu); 99 static void enter_smm(struct kvm_vcpu *vcpu); 100 static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags); 101 102 struct kvm_x86_ops *kvm_x86_ops __read_mostly; 103 EXPORT_SYMBOL_GPL(kvm_x86_ops); 104 105 static bool __read_mostly ignore_msrs = 0; 106 module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR); 107 108 unsigned int min_timer_period_us = 500; 109 module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR); 110 111 static bool __read_mostly kvmclock_periodic_sync = true; 112 module_param(kvmclock_periodic_sync, bool, S_IRUGO); 113 114 bool __read_mostly kvm_has_tsc_control; 115 EXPORT_SYMBOL_GPL(kvm_has_tsc_control); 116 u32 __read_mostly kvm_max_guest_tsc_khz; 117 EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz); 118 u8 __read_mostly kvm_tsc_scaling_ratio_frac_bits; 119 EXPORT_SYMBOL_GPL(kvm_tsc_scaling_ratio_frac_bits); 120 u64 __read_mostly kvm_max_tsc_scaling_ratio; 121 EXPORT_SYMBOL_GPL(kvm_max_tsc_scaling_ratio); 122 u64 __read_mostly kvm_default_tsc_scaling_ratio; 123 EXPORT_SYMBOL_GPL(kvm_default_tsc_scaling_ratio); 124 125 /* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */ 126 static u32 __read_mostly tsc_tolerance_ppm = 250; 127 module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR); 128 129 /* lapic timer advance (tscdeadline mode only) in nanoseconds */ 130 unsigned int __read_mostly lapic_timer_advance_ns = 0; 131 module_param(lapic_timer_advance_ns, uint, S_IRUGO | S_IWUSR); 132 133 static bool __read_mostly vector_hashing = true; 134 module_param(vector_hashing, bool, S_IRUGO); 135 136 static bool __read_mostly backwards_tsc_observed = false; 137 138 #define KVM_NR_SHARED_MSRS 16 139 140 struct kvm_shared_msrs_global { 141 int nr; 142 u32 msrs[KVM_NR_SHARED_MSRS]; 143 }; 144 145 struct kvm_shared_msrs { 146 struct user_return_notifier urn; 147 bool registered; 148 struct kvm_shared_msr_values { 149 u64 host; 150 u64 curr; 151 } values[KVM_NR_SHARED_MSRS]; 152 }; 153 154 static struct kvm_shared_msrs_global __read_mostly shared_msrs_global; 155 static struct kvm_shared_msrs __percpu *shared_msrs; 156 157 struct kvm_stats_debugfs_item debugfs_entries[] = { 158 { "pf_fixed", VCPU_STAT(pf_fixed) }, 159 { "pf_guest", VCPU_STAT(pf_guest) }, 160 { "tlb_flush", VCPU_STAT(tlb_flush) }, 161 { "invlpg", VCPU_STAT(invlpg) }, 162 { "exits", VCPU_STAT(exits) }, 163 { "io_exits", VCPU_STAT(io_exits) }, 164 { "mmio_exits", VCPU_STAT(mmio_exits) }, 165 { "signal_exits", VCPU_STAT(signal_exits) }, 166 { "irq_window", VCPU_STAT(irq_window_exits) }, 167 { "nmi_window", VCPU_STAT(nmi_window_exits) }, 168 { "halt_exits", VCPU_STAT(halt_exits) }, 169 { "halt_successful_poll", VCPU_STAT(halt_successful_poll) }, 170 { "halt_attempted_poll", VCPU_STAT(halt_attempted_poll) }, 171 { "halt_poll_invalid", VCPU_STAT(halt_poll_invalid) }, 172 { "halt_wakeup", VCPU_STAT(halt_wakeup) }, 173 { "hypercalls", VCPU_STAT(hypercalls) }, 174 { "request_irq", VCPU_STAT(request_irq_exits) }, 175 { "irq_exits", VCPU_STAT(irq_exits) }, 176 { "host_state_reload", VCPU_STAT(host_state_reload) }, 177 { "efer_reload", VCPU_STAT(efer_reload) }, 178 { "fpu_reload", VCPU_STAT(fpu_reload) }, 179 { "insn_emulation", VCPU_STAT(insn_emulation) }, 180 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) }, 181 { "irq_injections", VCPU_STAT(irq_injections) }, 182 { "nmi_injections", VCPU_STAT(nmi_injections) }, 183 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) }, 184 { "mmu_pte_write", VM_STAT(mmu_pte_write) }, 185 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) }, 186 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) }, 187 { "mmu_flooded", VM_STAT(mmu_flooded) }, 188 { "mmu_recycled", VM_STAT(mmu_recycled) }, 189 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) }, 190 { "mmu_unsync", VM_STAT(mmu_unsync) }, 191 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) }, 192 { "largepages", VM_STAT(lpages) }, 193 { NULL } 194 }; 195 196 u64 __read_mostly host_xcr0; 197 198 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt); 199 200 static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu) 201 { 202 int i; 203 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++) 204 vcpu->arch.apf.gfns[i] = ~0; 205 } 206 207 static void kvm_on_user_return(struct user_return_notifier *urn) 208 { 209 unsigned slot; 210 struct kvm_shared_msrs *locals 211 = container_of(urn, struct kvm_shared_msrs, urn); 212 struct kvm_shared_msr_values *values; 213 unsigned long flags; 214 215 /* 216 * Disabling irqs at this point since the following code could be 217 * interrupted and executed through kvm_arch_hardware_disable() 218 */ 219 local_irq_save(flags); 220 if (locals->registered) { 221 locals->registered = false; 222 user_return_notifier_unregister(urn); 223 } 224 local_irq_restore(flags); 225 for (slot = 0; slot < shared_msrs_global.nr; ++slot) { 226 values = &locals->values[slot]; 227 if (values->host != values->curr) { 228 wrmsrl(shared_msrs_global.msrs[slot], values->host); 229 values->curr = values->host; 230 } 231 } 232 } 233 234 static void shared_msr_update(unsigned slot, u32 msr) 235 { 236 u64 value; 237 unsigned int cpu = smp_processor_id(); 238 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu); 239 240 /* only read, and nobody should modify it at this time, 241 * so don't need lock */ 242 if (slot >= shared_msrs_global.nr) { 243 printk(KERN_ERR "kvm: invalid MSR slot!"); 244 return; 245 } 246 rdmsrl_safe(msr, &value); 247 smsr->values[slot].host = value; 248 smsr->values[slot].curr = value; 249 } 250 251 void kvm_define_shared_msr(unsigned slot, u32 msr) 252 { 253 BUG_ON(slot >= KVM_NR_SHARED_MSRS); 254 shared_msrs_global.msrs[slot] = msr; 255 if (slot >= shared_msrs_global.nr) 256 shared_msrs_global.nr = slot + 1; 257 } 258 EXPORT_SYMBOL_GPL(kvm_define_shared_msr); 259 260 static void kvm_shared_msr_cpu_online(void) 261 { 262 unsigned i; 263 264 for (i = 0; i < shared_msrs_global.nr; ++i) 265 shared_msr_update(i, shared_msrs_global.msrs[i]); 266 } 267 268 int kvm_set_shared_msr(unsigned slot, u64 value, u64 mask) 269 { 270 unsigned int cpu = smp_processor_id(); 271 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu); 272 int err; 273 274 if (((value ^ smsr->values[slot].curr) & mask) == 0) 275 return 0; 276 smsr->values[slot].curr = value; 277 err = wrmsrl_safe(shared_msrs_global.msrs[slot], value); 278 if (err) 279 return 1; 280 281 if (!smsr->registered) { 282 smsr->urn.on_user_return = kvm_on_user_return; 283 user_return_notifier_register(&smsr->urn); 284 smsr->registered = true; 285 } 286 return 0; 287 } 288 EXPORT_SYMBOL_GPL(kvm_set_shared_msr); 289 290 static void drop_user_return_notifiers(void) 291 { 292 unsigned int cpu = smp_processor_id(); 293 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu); 294 295 if (smsr->registered) 296 kvm_on_user_return(&smsr->urn); 297 } 298 299 u64 kvm_get_apic_base(struct kvm_vcpu *vcpu) 300 { 301 return vcpu->arch.apic_base; 302 } 303 EXPORT_SYMBOL_GPL(kvm_get_apic_base); 304 305 int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info) 306 { 307 u64 old_state = vcpu->arch.apic_base & 308 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE); 309 u64 new_state = msr_info->data & 310 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE); 311 u64 reserved_bits = ((~0ULL) << cpuid_maxphyaddr(vcpu)) | 312 0x2ff | (guest_cpuid_has_x2apic(vcpu) ? 0 : X2APIC_ENABLE); 313 314 if (!msr_info->host_initiated && 315 ((msr_info->data & reserved_bits) != 0 || 316 new_state == X2APIC_ENABLE || 317 (new_state == MSR_IA32_APICBASE_ENABLE && 318 old_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE)) || 319 (new_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE) && 320 old_state == 0))) 321 return 1; 322 323 kvm_lapic_set_base(vcpu, msr_info->data); 324 return 0; 325 } 326 EXPORT_SYMBOL_GPL(kvm_set_apic_base); 327 328 asmlinkage __visible void kvm_spurious_fault(void) 329 { 330 /* Fault while not rebooting. We want the trace. */ 331 BUG(); 332 } 333 EXPORT_SYMBOL_GPL(kvm_spurious_fault); 334 335 #define EXCPT_BENIGN 0 336 #define EXCPT_CONTRIBUTORY 1 337 #define EXCPT_PF 2 338 339 static int exception_class(int vector) 340 { 341 switch (vector) { 342 case PF_VECTOR: 343 return EXCPT_PF; 344 case DE_VECTOR: 345 case TS_VECTOR: 346 case NP_VECTOR: 347 case SS_VECTOR: 348 case GP_VECTOR: 349 return EXCPT_CONTRIBUTORY; 350 default: 351 break; 352 } 353 return EXCPT_BENIGN; 354 } 355 356 #define EXCPT_FAULT 0 357 #define EXCPT_TRAP 1 358 #define EXCPT_ABORT 2 359 #define EXCPT_INTERRUPT 3 360 361 static int exception_type(int vector) 362 { 363 unsigned int mask; 364 365 if (WARN_ON(vector > 31 || vector == NMI_VECTOR)) 366 return EXCPT_INTERRUPT; 367 368 mask = 1 << vector; 369 370 /* #DB is trap, as instruction watchpoints are handled elsewhere */ 371 if (mask & ((1 << DB_VECTOR) | (1 << BP_VECTOR) | (1 << OF_VECTOR))) 372 return EXCPT_TRAP; 373 374 if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR))) 375 return EXCPT_ABORT; 376 377 /* Reserved exceptions will result in fault */ 378 return EXCPT_FAULT; 379 } 380 381 static void kvm_multiple_exception(struct kvm_vcpu *vcpu, 382 unsigned nr, bool has_error, u32 error_code, 383 bool reinject) 384 { 385 u32 prev_nr; 386 int class1, class2; 387 388 kvm_make_request(KVM_REQ_EVENT, vcpu); 389 390 if (!vcpu->arch.exception.pending) { 391 queue: 392 if (has_error && !is_protmode(vcpu)) 393 has_error = false; 394 vcpu->arch.exception.pending = true; 395 vcpu->arch.exception.has_error_code = has_error; 396 vcpu->arch.exception.nr = nr; 397 vcpu->arch.exception.error_code = error_code; 398 vcpu->arch.exception.reinject = reinject; 399 return; 400 } 401 402 /* to check exception */ 403 prev_nr = vcpu->arch.exception.nr; 404 if (prev_nr == DF_VECTOR) { 405 /* triple fault -> shutdown */ 406 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); 407 return; 408 } 409 class1 = exception_class(prev_nr); 410 class2 = exception_class(nr); 411 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY) 412 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) { 413 /* generate double fault per SDM Table 5-5 */ 414 vcpu->arch.exception.pending = true; 415 vcpu->arch.exception.has_error_code = true; 416 vcpu->arch.exception.nr = DF_VECTOR; 417 vcpu->arch.exception.error_code = 0; 418 } else 419 /* replace previous exception with a new one in a hope 420 that instruction re-execution will regenerate lost 421 exception */ 422 goto queue; 423 } 424 425 void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr) 426 { 427 kvm_multiple_exception(vcpu, nr, false, 0, false); 428 } 429 EXPORT_SYMBOL_GPL(kvm_queue_exception); 430 431 void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr) 432 { 433 kvm_multiple_exception(vcpu, nr, false, 0, true); 434 } 435 EXPORT_SYMBOL_GPL(kvm_requeue_exception); 436 437 int kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err) 438 { 439 if (err) 440 kvm_inject_gp(vcpu, 0); 441 else 442 return kvm_skip_emulated_instruction(vcpu); 443 444 return 1; 445 } 446 EXPORT_SYMBOL_GPL(kvm_complete_insn_gp); 447 448 void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault) 449 { 450 ++vcpu->stat.pf_guest; 451 vcpu->arch.cr2 = fault->address; 452 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code); 453 } 454 EXPORT_SYMBOL_GPL(kvm_inject_page_fault); 455 456 static bool kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault) 457 { 458 if (mmu_is_nested(vcpu) && !fault->nested_page_fault) 459 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault); 460 else 461 vcpu->arch.mmu.inject_page_fault(vcpu, fault); 462 463 return fault->nested_page_fault; 464 } 465 466 void kvm_inject_nmi(struct kvm_vcpu *vcpu) 467 { 468 atomic_inc(&vcpu->arch.nmi_queued); 469 kvm_make_request(KVM_REQ_NMI, vcpu); 470 } 471 EXPORT_SYMBOL_GPL(kvm_inject_nmi); 472 473 void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code) 474 { 475 kvm_multiple_exception(vcpu, nr, true, error_code, false); 476 } 477 EXPORT_SYMBOL_GPL(kvm_queue_exception_e); 478 479 void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code) 480 { 481 kvm_multiple_exception(vcpu, nr, true, error_code, true); 482 } 483 EXPORT_SYMBOL_GPL(kvm_requeue_exception_e); 484 485 /* 486 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue 487 * a #GP and return false. 488 */ 489 bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl) 490 { 491 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl) 492 return true; 493 kvm_queue_exception_e(vcpu, GP_VECTOR, 0); 494 return false; 495 } 496 EXPORT_SYMBOL_GPL(kvm_require_cpl); 497 498 bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr) 499 { 500 if ((dr != 4 && dr != 5) || !kvm_read_cr4_bits(vcpu, X86_CR4_DE)) 501 return true; 502 503 kvm_queue_exception(vcpu, UD_VECTOR); 504 return false; 505 } 506 EXPORT_SYMBOL_GPL(kvm_require_dr); 507 508 /* 509 * This function will be used to read from the physical memory of the currently 510 * running guest. The difference to kvm_vcpu_read_guest_page is that this function 511 * can read from guest physical or from the guest's guest physical memory. 512 */ 513 int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, 514 gfn_t ngfn, void *data, int offset, int len, 515 u32 access) 516 { 517 struct x86_exception exception; 518 gfn_t real_gfn; 519 gpa_t ngpa; 520 521 ngpa = gfn_to_gpa(ngfn); 522 real_gfn = mmu->translate_gpa(vcpu, ngpa, access, &exception); 523 if (real_gfn == UNMAPPED_GVA) 524 return -EFAULT; 525 526 real_gfn = gpa_to_gfn(real_gfn); 527 528 return kvm_vcpu_read_guest_page(vcpu, real_gfn, data, offset, len); 529 } 530 EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu); 531 532 static int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn, 533 void *data, int offset, int len, u32 access) 534 { 535 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn, 536 data, offset, len, access); 537 } 538 539 /* 540 * Load the pae pdptrs. Return true is they are all valid. 541 */ 542 int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3) 543 { 544 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT; 545 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2; 546 int i; 547 int ret; 548 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)]; 549 550 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte, 551 offset * sizeof(u64), sizeof(pdpte), 552 PFERR_USER_MASK|PFERR_WRITE_MASK); 553 if (ret < 0) { 554 ret = 0; 555 goto out; 556 } 557 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) { 558 if ((pdpte[i] & PT_PRESENT_MASK) && 559 (pdpte[i] & 560 vcpu->arch.mmu.guest_rsvd_check.rsvd_bits_mask[0][2])) { 561 ret = 0; 562 goto out; 563 } 564 } 565 ret = 1; 566 567 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs)); 568 __set_bit(VCPU_EXREG_PDPTR, 569 (unsigned long *)&vcpu->arch.regs_avail); 570 __set_bit(VCPU_EXREG_PDPTR, 571 (unsigned long *)&vcpu->arch.regs_dirty); 572 out: 573 574 return ret; 575 } 576 EXPORT_SYMBOL_GPL(load_pdptrs); 577 578 bool pdptrs_changed(struct kvm_vcpu *vcpu) 579 { 580 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)]; 581 bool changed = true; 582 int offset; 583 gfn_t gfn; 584 int r; 585 586 if (is_long_mode(vcpu) || !is_pae(vcpu)) 587 return false; 588 589 if (!test_bit(VCPU_EXREG_PDPTR, 590 (unsigned long *)&vcpu->arch.regs_avail)) 591 return true; 592 593 gfn = (kvm_read_cr3(vcpu) & ~31u) >> PAGE_SHIFT; 594 offset = (kvm_read_cr3(vcpu) & ~31u) & (PAGE_SIZE - 1); 595 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte), 596 PFERR_USER_MASK | PFERR_WRITE_MASK); 597 if (r < 0) 598 goto out; 599 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0; 600 out: 601 602 return changed; 603 } 604 EXPORT_SYMBOL_GPL(pdptrs_changed); 605 606 int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0) 607 { 608 unsigned long old_cr0 = kvm_read_cr0(vcpu); 609 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP; 610 611 cr0 |= X86_CR0_ET; 612 613 #ifdef CONFIG_X86_64 614 if (cr0 & 0xffffffff00000000UL) 615 return 1; 616 #endif 617 618 cr0 &= ~CR0_RESERVED_BITS; 619 620 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD)) 621 return 1; 622 623 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE)) 624 return 1; 625 626 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) { 627 #ifdef CONFIG_X86_64 628 if ((vcpu->arch.efer & EFER_LME)) { 629 int cs_db, cs_l; 630 631 if (!is_pae(vcpu)) 632 return 1; 633 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l); 634 if (cs_l) 635 return 1; 636 } else 637 #endif 638 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu, 639 kvm_read_cr3(vcpu))) 640 return 1; 641 } 642 643 if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE)) 644 return 1; 645 646 kvm_x86_ops->set_cr0(vcpu, cr0); 647 648 if ((cr0 ^ old_cr0) & X86_CR0_PG) { 649 kvm_clear_async_pf_completion_queue(vcpu); 650 kvm_async_pf_hash_reset(vcpu); 651 } 652 653 if ((cr0 ^ old_cr0) & update_bits) 654 kvm_mmu_reset_context(vcpu); 655 656 if (((cr0 ^ old_cr0) & X86_CR0_CD) && 657 kvm_arch_has_noncoherent_dma(vcpu->kvm) && 658 !kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED)) 659 kvm_zap_gfn_range(vcpu->kvm, 0, ~0ULL); 660 661 return 0; 662 } 663 EXPORT_SYMBOL_GPL(kvm_set_cr0); 664 665 void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw) 666 { 667 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f)); 668 } 669 EXPORT_SYMBOL_GPL(kvm_lmsw); 670 671 static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu) 672 { 673 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) && 674 !vcpu->guest_xcr0_loaded) { 675 /* kvm_set_xcr() also depends on this */ 676 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0); 677 vcpu->guest_xcr0_loaded = 1; 678 } 679 } 680 681 static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu) 682 { 683 if (vcpu->guest_xcr0_loaded) { 684 if (vcpu->arch.xcr0 != host_xcr0) 685 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0); 686 vcpu->guest_xcr0_loaded = 0; 687 } 688 } 689 690 static int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr) 691 { 692 u64 xcr0 = xcr; 693 u64 old_xcr0 = vcpu->arch.xcr0; 694 u64 valid_bits; 695 696 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */ 697 if (index != XCR_XFEATURE_ENABLED_MASK) 698 return 1; 699 if (!(xcr0 & XFEATURE_MASK_FP)) 700 return 1; 701 if ((xcr0 & XFEATURE_MASK_YMM) && !(xcr0 & XFEATURE_MASK_SSE)) 702 return 1; 703 704 /* 705 * Do not allow the guest to set bits that we do not support 706 * saving. However, xcr0 bit 0 is always set, even if the 707 * emulated CPU does not support XSAVE (see fx_init). 708 */ 709 valid_bits = vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FP; 710 if (xcr0 & ~valid_bits) 711 return 1; 712 713 if ((!(xcr0 & XFEATURE_MASK_BNDREGS)) != 714 (!(xcr0 & XFEATURE_MASK_BNDCSR))) 715 return 1; 716 717 if (xcr0 & XFEATURE_MASK_AVX512) { 718 if (!(xcr0 & XFEATURE_MASK_YMM)) 719 return 1; 720 if ((xcr0 & XFEATURE_MASK_AVX512) != XFEATURE_MASK_AVX512) 721 return 1; 722 } 723 vcpu->arch.xcr0 = xcr0; 724 725 if ((xcr0 ^ old_xcr0) & XFEATURE_MASK_EXTEND) 726 kvm_update_cpuid(vcpu); 727 return 0; 728 } 729 730 int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr) 731 { 732 if (kvm_x86_ops->get_cpl(vcpu) != 0 || 733 __kvm_set_xcr(vcpu, index, xcr)) { 734 kvm_inject_gp(vcpu, 0); 735 return 1; 736 } 737 return 0; 738 } 739 EXPORT_SYMBOL_GPL(kvm_set_xcr); 740 741 int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4) 742 { 743 unsigned long old_cr4 = kvm_read_cr4(vcpu); 744 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE | 745 X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE; 746 747 if (cr4 & CR4_RESERVED_BITS) 748 return 1; 749 750 if (!guest_cpuid_has_xsave(vcpu) && (cr4 & X86_CR4_OSXSAVE)) 751 return 1; 752 753 if (!guest_cpuid_has_smep(vcpu) && (cr4 & X86_CR4_SMEP)) 754 return 1; 755 756 if (!guest_cpuid_has_smap(vcpu) && (cr4 & X86_CR4_SMAP)) 757 return 1; 758 759 if (!guest_cpuid_has_fsgsbase(vcpu) && (cr4 & X86_CR4_FSGSBASE)) 760 return 1; 761 762 if (!guest_cpuid_has_pku(vcpu) && (cr4 & X86_CR4_PKE)) 763 return 1; 764 765 if (is_long_mode(vcpu)) { 766 if (!(cr4 & X86_CR4_PAE)) 767 return 1; 768 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE) 769 && ((cr4 ^ old_cr4) & pdptr_bits) 770 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu, 771 kvm_read_cr3(vcpu))) 772 return 1; 773 774 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) { 775 if (!guest_cpuid_has_pcid(vcpu)) 776 return 1; 777 778 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */ 779 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu)) 780 return 1; 781 } 782 783 if (kvm_x86_ops->set_cr4(vcpu, cr4)) 784 return 1; 785 786 if (((cr4 ^ old_cr4) & pdptr_bits) || 787 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE))) 788 kvm_mmu_reset_context(vcpu); 789 790 if ((cr4 ^ old_cr4) & (X86_CR4_OSXSAVE | X86_CR4_PKE)) 791 kvm_update_cpuid(vcpu); 792 793 return 0; 794 } 795 EXPORT_SYMBOL_GPL(kvm_set_cr4); 796 797 int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3) 798 { 799 #ifdef CONFIG_X86_64 800 cr3 &= ~CR3_PCID_INVD; 801 #endif 802 803 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) { 804 kvm_mmu_sync_roots(vcpu); 805 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu); 806 return 0; 807 } 808 809 if (is_long_mode(vcpu)) { 810 if (cr3 & CR3_L_MODE_RESERVED_BITS) 811 return 1; 812 } else if (is_pae(vcpu) && is_paging(vcpu) && 813 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3)) 814 return 1; 815 816 vcpu->arch.cr3 = cr3; 817 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail); 818 kvm_mmu_new_cr3(vcpu); 819 return 0; 820 } 821 EXPORT_SYMBOL_GPL(kvm_set_cr3); 822 823 int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8) 824 { 825 if (cr8 & CR8_RESERVED_BITS) 826 return 1; 827 if (lapic_in_kernel(vcpu)) 828 kvm_lapic_set_tpr(vcpu, cr8); 829 else 830 vcpu->arch.cr8 = cr8; 831 return 0; 832 } 833 EXPORT_SYMBOL_GPL(kvm_set_cr8); 834 835 unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu) 836 { 837 if (lapic_in_kernel(vcpu)) 838 return kvm_lapic_get_cr8(vcpu); 839 else 840 return vcpu->arch.cr8; 841 } 842 EXPORT_SYMBOL_GPL(kvm_get_cr8); 843 844 static void kvm_update_dr0123(struct kvm_vcpu *vcpu) 845 { 846 int i; 847 848 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) { 849 for (i = 0; i < KVM_NR_DB_REGS; i++) 850 vcpu->arch.eff_db[i] = vcpu->arch.db[i]; 851 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_RELOAD; 852 } 853 } 854 855 static void kvm_update_dr6(struct kvm_vcpu *vcpu) 856 { 857 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) 858 kvm_x86_ops->set_dr6(vcpu, vcpu->arch.dr6); 859 } 860 861 static void kvm_update_dr7(struct kvm_vcpu *vcpu) 862 { 863 unsigned long dr7; 864 865 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) 866 dr7 = vcpu->arch.guest_debug_dr7; 867 else 868 dr7 = vcpu->arch.dr7; 869 kvm_x86_ops->set_dr7(vcpu, dr7); 870 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED; 871 if (dr7 & DR7_BP_EN_MASK) 872 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED; 873 } 874 875 static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu) 876 { 877 u64 fixed = DR6_FIXED_1; 878 879 if (!guest_cpuid_has_rtm(vcpu)) 880 fixed |= DR6_RTM; 881 return fixed; 882 } 883 884 static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val) 885 { 886 switch (dr) { 887 case 0 ... 3: 888 vcpu->arch.db[dr] = val; 889 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) 890 vcpu->arch.eff_db[dr] = val; 891 break; 892 case 4: 893 /* fall through */ 894 case 6: 895 if (val & 0xffffffff00000000ULL) 896 return -1; /* #GP */ 897 vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu); 898 kvm_update_dr6(vcpu); 899 break; 900 case 5: 901 /* fall through */ 902 default: /* 7 */ 903 if (val & 0xffffffff00000000ULL) 904 return -1; /* #GP */ 905 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1; 906 kvm_update_dr7(vcpu); 907 break; 908 } 909 910 return 0; 911 } 912 913 int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val) 914 { 915 if (__kvm_set_dr(vcpu, dr, val)) { 916 kvm_inject_gp(vcpu, 0); 917 return 1; 918 } 919 return 0; 920 } 921 EXPORT_SYMBOL_GPL(kvm_set_dr); 922 923 int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val) 924 { 925 switch (dr) { 926 case 0 ... 3: 927 *val = vcpu->arch.db[dr]; 928 break; 929 case 4: 930 /* fall through */ 931 case 6: 932 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) 933 *val = vcpu->arch.dr6; 934 else 935 *val = kvm_x86_ops->get_dr6(vcpu); 936 break; 937 case 5: 938 /* fall through */ 939 default: /* 7 */ 940 *val = vcpu->arch.dr7; 941 break; 942 } 943 return 0; 944 } 945 EXPORT_SYMBOL_GPL(kvm_get_dr); 946 947 bool kvm_rdpmc(struct kvm_vcpu *vcpu) 948 { 949 u32 ecx = kvm_register_read(vcpu, VCPU_REGS_RCX); 950 u64 data; 951 int err; 952 953 err = kvm_pmu_rdpmc(vcpu, ecx, &data); 954 if (err) 955 return err; 956 kvm_register_write(vcpu, VCPU_REGS_RAX, (u32)data); 957 kvm_register_write(vcpu, VCPU_REGS_RDX, data >> 32); 958 return err; 959 } 960 EXPORT_SYMBOL_GPL(kvm_rdpmc); 961 962 /* 963 * List of msr numbers which we expose to userspace through KVM_GET_MSRS 964 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST. 965 * 966 * This list is modified at module load time to reflect the 967 * capabilities of the host cpu. This capabilities test skips MSRs that are 968 * kvm-specific. Those are put in emulated_msrs; filtering of emulated_msrs 969 * may depend on host virtualization features rather than host cpu features. 970 */ 971 972 static u32 msrs_to_save[] = { 973 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP, 974 MSR_STAR, 975 #ifdef CONFIG_X86_64 976 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR, 977 #endif 978 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA, 979 MSR_IA32_FEATURE_CONTROL, MSR_IA32_BNDCFGS, MSR_TSC_AUX, 980 }; 981 982 static unsigned num_msrs_to_save; 983 984 static u32 emulated_msrs[] = { 985 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK, 986 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW, 987 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL, 988 HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC, 989 HV_X64_MSR_CRASH_P0, HV_X64_MSR_CRASH_P1, HV_X64_MSR_CRASH_P2, 990 HV_X64_MSR_CRASH_P3, HV_X64_MSR_CRASH_P4, HV_X64_MSR_CRASH_CTL, 991 HV_X64_MSR_RESET, 992 HV_X64_MSR_VP_INDEX, 993 HV_X64_MSR_VP_RUNTIME, 994 HV_X64_MSR_SCONTROL, 995 HV_X64_MSR_STIMER0_CONFIG, 996 HV_X64_MSR_APIC_ASSIST_PAGE, MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME, 997 MSR_KVM_PV_EOI_EN, 998 999 MSR_IA32_TSC_ADJUST, 1000 MSR_IA32_TSCDEADLINE, 1001 MSR_IA32_MISC_ENABLE, 1002 MSR_IA32_MCG_STATUS, 1003 MSR_IA32_MCG_CTL, 1004 MSR_IA32_MCG_EXT_CTL, 1005 MSR_IA32_SMBASE, 1006 }; 1007 1008 static unsigned num_emulated_msrs; 1009 1010 bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer) 1011 { 1012 if (efer & efer_reserved_bits) 1013 return false; 1014 1015 if (efer & EFER_FFXSR) { 1016 struct kvm_cpuid_entry2 *feat; 1017 1018 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0); 1019 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT))) 1020 return false; 1021 } 1022 1023 if (efer & EFER_SVME) { 1024 struct kvm_cpuid_entry2 *feat; 1025 1026 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0); 1027 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM))) 1028 return false; 1029 } 1030 1031 return true; 1032 } 1033 EXPORT_SYMBOL_GPL(kvm_valid_efer); 1034 1035 static int set_efer(struct kvm_vcpu *vcpu, u64 efer) 1036 { 1037 u64 old_efer = vcpu->arch.efer; 1038 1039 if (!kvm_valid_efer(vcpu, efer)) 1040 return 1; 1041 1042 if (is_paging(vcpu) 1043 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME)) 1044 return 1; 1045 1046 efer &= ~EFER_LMA; 1047 efer |= vcpu->arch.efer & EFER_LMA; 1048 1049 kvm_x86_ops->set_efer(vcpu, efer); 1050 1051 /* Update reserved bits */ 1052 if ((efer ^ old_efer) & EFER_NX) 1053 kvm_mmu_reset_context(vcpu); 1054 1055 return 0; 1056 } 1057 1058 void kvm_enable_efer_bits(u64 mask) 1059 { 1060 efer_reserved_bits &= ~mask; 1061 } 1062 EXPORT_SYMBOL_GPL(kvm_enable_efer_bits); 1063 1064 /* 1065 * Writes msr value into into the appropriate "register". 1066 * Returns 0 on success, non-0 otherwise. 1067 * Assumes vcpu_load() was already called. 1068 */ 1069 int kvm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr) 1070 { 1071 switch (msr->index) { 1072 case MSR_FS_BASE: 1073 case MSR_GS_BASE: 1074 case MSR_KERNEL_GS_BASE: 1075 case MSR_CSTAR: 1076 case MSR_LSTAR: 1077 if (is_noncanonical_address(msr->data)) 1078 return 1; 1079 break; 1080 case MSR_IA32_SYSENTER_EIP: 1081 case MSR_IA32_SYSENTER_ESP: 1082 /* 1083 * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if 1084 * non-canonical address is written on Intel but not on 1085 * AMD (which ignores the top 32-bits, because it does 1086 * not implement 64-bit SYSENTER). 1087 * 1088 * 64-bit code should hence be able to write a non-canonical 1089 * value on AMD. Making the address canonical ensures that 1090 * vmentry does not fail on Intel after writing a non-canonical 1091 * value, and that something deterministic happens if the guest 1092 * invokes 64-bit SYSENTER. 1093 */ 1094 msr->data = get_canonical(msr->data); 1095 } 1096 return kvm_x86_ops->set_msr(vcpu, msr); 1097 } 1098 EXPORT_SYMBOL_GPL(kvm_set_msr); 1099 1100 /* 1101 * Adapt set_msr() to msr_io()'s calling convention 1102 */ 1103 static int do_get_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data) 1104 { 1105 struct msr_data msr; 1106 int r; 1107 1108 msr.index = index; 1109 msr.host_initiated = true; 1110 r = kvm_get_msr(vcpu, &msr); 1111 if (r) 1112 return r; 1113 1114 *data = msr.data; 1115 return 0; 1116 } 1117 1118 static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data) 1119 { 1120 struct msr_data msr; 1121 1122 msr.data = *data; 1123 msr.index = index; 1124 msr.host_initiated = true; 1125 return kvm_set_msr(vcpu, &msr); 1126 } 1127 1128 #ifdef CONFIG_X86_64 1129 struct pvclock_gtod_data { 1130 seqcount_t seq; 1131 1132 struct { /* extract of a clocksource struct */ 1133 int vclock_mode; 1134 cycle_t cycle_last; 1135 cycle_t mask; 1136 u32 mult; 1137 u32 shift; 1138 } clock; 1139 1140 u64 boot_ns; 1141 u64 nsec_base; 1142 }; 1143 1144 static struct pvclock_gtod_data pvclock_gtod_data; 1145 1146 static void update_pvclock_gtod(struct timekeeper *tk) 1147 { 1148 struct pvclock_gtod_data *vdata = &pvclock_gtod_data; 1149 u64 boot_ns; 1150 1151 boot_ns = ktime_to_ns(ktime_add(tk->tkr_mono.base, tk->offs_boot)); 1152 1153 write_seqcount_begin(&vdata->seq); 1154 1155 /* copy pvclock gtod data */ 1156 vdata->clock.vclock_mode = tk->tkr_mono.clock->archdata.vclock_mode; 1157 vdata->clock.cycle_last = tk->tkr_mono.cycle_last; 1158 vdata->clock.mask = tk->tkr_mono.mask; 1159 vdata->clock.mult = tk->tkr_mono.mult; 1160 vdata->clock.shift = tk->tkr_mono.shift; 1161 1162 vdata->boot_ns = boot_ns; 1163 vdata->nsec_base = tk->tkr_mono.xtime_nsec; 1164 1165 write_seqcount_end(&vdata->seq); 1166 } 1167 #endif 1168 1169 void kvm_set_pending_timer(struct kvm_vcpu *vcpu) 1170 { 1171 /* 1172 * Note: KVM_REQ_PENDING_TIMER is implicitly checked in 1173 * vcpu_enter_guest. This function is only called from 1174 * the physical CPU that is running vcpu. 1175 */ 1176 kvm_make_request(KVM_REQ_PENDING_TIMER, vcpu); 1177 } 1178 1179 static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock) 1180 { 1181 int version; 1182 int r; 1183 struct pvclock_wall_clock wc; 1184 struct timespec64 boot; 1185 1186 if (!wall_clock) 1187 return; 1188 1189 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version)); 1190 if (r) 1191 return; 1192 1193 if (version & 1) 1194 ++version; /* first time write, random junk */ 1195 1196 ++version; 1197 1198 if (kvm_write_guest(kvm, wall_clock, &version, sizeof(version))) 1199 return; 1200 1201 /* 1202 * The guest calculates current wall clock time by adding 1203 * system time (updated by kvm_guest_time_update below) to the 1204 * wall clock specified here. guest system time equals host 1205 * system time for us, thus we must fill in host boot time here. 1206 */ 1207 getboottime64(&boot); 1208 1209 if (kvm->arch.kvmclock_offset) { 1210 struct timespec64 ts = ns_to_timespec64(kvm->arch.kvmclock_offset); 1211 boot = timespec64_sub(boot, ts); 1212 } 1213 wc.sec = (u32)boot.tv_sec; /* overflow in 2106 guest time */ 1214 wc.nsec = boot.tv_nsec; 1215 wc.version = version; 1216 1217 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc)); 1218 1219 version++; 1220 kvm_write_guest(kvm, wall_clock, &version, sizeof(version)); 1221 } 1222 1223 static uint32_t div_frac(uint32_t dividend, uint32_t divisor) 1224 { 1225 do_shl32_div32(dividend, divisor); 1226 return dividend; 1227 } 1228 1229 static void kvm_get_time_scale(uint64_t scaled_hz, uint64_t base_hz, 1230 s8 *pshift, u32 *pmultiplier) 1231 { 1232 uint64_t scaled64; 1233 int32_t shift = 0; 1234 uint64_t tps64; 1235 uint32_t tps32; 1236 1237 tps64 = base_hz; 1238 scaled64 = scaled_hz; 1239 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) { 1240 tps64 >>= 1; 1241 shift--; 1242 } 1243 1244 tps32 = (uint32_t)tps64; 1245 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) { 1246 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000) 1247 scaled64 >>= 1; 1248 else 1249 tps32 <<= 1; 1250 shift++; 1251 } 1252 1253 *pshift = shift; 1254 *pmultiplier = div_frac(scaled64, tps32); 1255 1256 pr_debug("%s: base_hz %llu => %llu, shift %d, mul %u\n", 1257 __func__, base_hz, scaled_hz, shift, *pmultiplier); 1258 } 1259 1260 #ifdef CONFIG_X86_64 1261 static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0); 1262 #endif 1263 1264 static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz); 1265 static unsigned long max_tsc_khz; 1266 1267 static u32 adjust_tsc_khz(u32 khz, s32 ppm) 1268 { 1269 u64 v = (u64)khz * (1000000 + ppm); 1270 do_div(v, 1000000); 1271 return v; 1272 } 1273 1274 static int set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale) 1275 { 1276 u64 ratio; 1277 1278 /* Guest TSC same frequency as host TSC? */ 1279 if (!scale) { 1280 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio; 1281 return 0; 1282 } 1283 1284 /* TSC scaling supported? */ 1285 if (!kvm_has_tsc_control) { 1286 if (user_tsc_khz > tsc_khz) { 1287 vcpu->arch.tsc_catchup = 1; 1288 vcpu->arch.tsc_always_catchup = 1; 1289 return 0; 1290 } else { 1291 WARN(1, "user requested TSC rate below hardware speed\n"); 1292 return -1; 1293 } 1294 } 1295 1296 /* TSC scaling required - calculate ratio */ 1297 ratio = mul_u64_u32_div(1ULL << kvm_tsc_scaling_ratio_frac_bits, 1298 user_tsc_khz, tsc_khz); 1299 1300 if (ratio == 0 || ratio >= kvm_max_tsc_scaling_ratio) { 1301 WARN_ONCE(1, "Invalid TSC scaling ratio - virtual-tsc-khz=%u\n", 1302 user_tsc_khz); 1303 return -1; 1304 } 1305 1306 vcpu->arch.tsc_scaling_ratio = ratio; 1307 return 0; 1308 } 1309 1310 static int kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz) 1311 { 1312 u32 thresh_lo, thresh_hi; 1313 int use_scaling = 0; 1314 1315 /* tsc_khz can be zero if TSC calibration fails */ 1316 if (user_tsc_khz == 0) { 1317 /* set tsc_scaling_ratio to a safe value */ 1318 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio; 1319 return -1; 1320 } 1321 1322 /* Compute a scale to convert nanoseconds in TSC cycles */ 1323 kvm_get_time_scale(user_tsc_khz * 1000LL, NSEC_PER_SEC, 1324 &vcpu->arch.virtual_tsc_shift, 1325 &vcpu->arch.virtual_tsc_mult); 1326 vcpu->arch.virtual_tsc_khz = user_tsc_khz; 1327 1328 /* 1329 * Compute the variation in TSC rate which is acceptable 1330 * within the range of tolerance and decide if the 1331 * rate being applied is within that bounds of the hardware 1332 * rate. If so, no scaling or compensation need be done. 1333 */ 1334 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm); 1335 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm); 1336 if (user_tsc_khz < thresh_lo || user_tsc_khz > thresh_hi) { 1337 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", user_tsc_khz, thresh_lo, thresh_hi); 1338 use_scaling = 1; 1339 } 1340 return set_tsc_khz(vcpu, user_tsc_khz, use_scaling); 1341 } 1342 1343 static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns) 1344 { 1345 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec, 1346 vcpu->arch.virtual_tsc_mult, 1347 vcpu->arch.virtual_tsc_shift); 1348 tsc += vcpu->arch.this_tsc_write; 1349 return tsc; 1350 } 1351 1352 static void kvm_track_tsc_matching(struct kvm_vcpu *vcpu) 1353 { 1354 #ifdef CONFIG_X86_64 1355 bool vcpus_matched; 1356 struct kvm_arch *ka = &vcpu->kvm->arch; 1357 struct pvclock_gtod_data *gtod = &pvclock_gtod_data; 1358 1359 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 == 1360 atomic_read(&vcpu->kvm->online_vcpus)); 1361 1362 /* 1363 * Once the masterclock is enabled, always perform request in 1364 * order to update it. 1365 * 1366 * In order to enable masterclock, the host clocksource must be TSC 1367 * and the vcpus need to have matched TSCs. When that happens, 1368 * perform request to enable masterclock. 1369 */ 1370 if (ka->use_master_clock || 1371 (gtod->clock.vclock_mode == VCLOCK_TSC && vcpus_matched)) 1372 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu); 1373 1374 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc, 1375 atomic_read(&vcpu->kvm->online_vcpus), 1376 ka->use_master_clock, gtod->clock.vclock_mode); 1377 #endif 1378 } 1379 1380 static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset) 1381 { 1382 u64 curr_offset = vcpu->arch.tsc_offset; 1383 vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset; 1384 } 1385 1386 /* 1387 * Multiply tsc by a fixed point number represented by ratio. 1388 * 1389 * The most significant 64-N bits (mult) of ratio represent the 1390 * integral part of the fixed point number; the remaining N bits 1391 * (frac) represent the fractional part, ie. ratio represents a fixed 1392 * point number (mult + frac * 2^(-N)). 1393 * 1394 * N equals to kvm_tsc_scaling_ratio_frac_bits. 1395 */ 1396 static inline u64 __scale_tsc(u64 ratio, u64 tsc) 1397 { 1398 return mul_u64_u64_shr(tsc, ratio, kvm_tsc_scaling_ratio_frac_bits); 1399 } 1400 1401 u64 kvm_scale_tsc(struct kvm_vcpu *vcpu, u64 tsc) 1402 { 1403 u64 _tsc = tsc; 1404 u64 ratio = vcpu->arch.tsc_scaling_ratio; 1405 1406 if (ratio != kvm_default_tsc_scaling_ratio) 1407 _tsc = __scale_tsc(ratio, tsc); 1408 1409 return _tsc; 1410 } 1411 EXPORT_SYMBOL_GPL(kvm_scale_tsc); 1412 1413 static u64 kvm_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc) 1414 { 1415 u64 tsc; 1416 1417 tsc = kvm_scale_tsc(vcpu, rdtsc()); 1418 1419 return target_tsc - tsc; 1420 } 1421 1422 u64 kvm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc) 1423 { 1424 return vcpu->arch.tsc_offset + kvm_scale_tsc(vcpu, host_tsc); 1425 } 1426 EXPORT_SYMBOL_GPL(kvm_read_l1_tsc); 1427 1428 static void kvm_vcpu_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset) 1429 { 1430 kvm_x86_ops->write_tsc_offset(vcpu, offset); 1431 vcpu->arch.tsc_offset = offset; 1432 } 1433 1434 void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr) 1435 { 1436 struct kvm *kvm = vcpu->kvm; 1437 u64 offset, ns, elapsed; 1438 unsigned long flags; 1439 s64 usdiff; 1440 bool matched; 1441 bool already_matched; 1442 u64 data = msr->data; 1443 1444 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags); 1445 offset = kvm_compute_tsc_offset(vcpu, data); 1446 ns = ktime_get_boot_ns(); 1447 elapsed = ns - kvm->arch.last_tsc_nsec; 1448 1449 if (vcpu->arch.virtual_tsc_khz) { 1450 int faulted = 0; 1451 1452 /* n.b - signed multiplication and division required */ 1453 usdiff = data - kvm->arch.last_tsc_write; 1454 #ifdef CONFIG_X86_64 1455 usdiff = (usdiff * 1000) / vcpu->arch.virtual_tsc_khz; 1456 #else 1457 /* do_div() only does unsigned */ 1458 asm("1: idivl %[divisor]\n" 1459 "2: xor %%edx, %%edx\n" 1460 " movl $0, %[faulted]\n" 1461 "3:\n" 1462 ".section .fixup,\"ax\"\n" 1463 "4: movl $1, %[faulted]\n" 1464 " jmp 3b\n" 1465 ".previous\n" 1466 1467 _ASM_EXTABLE(1b, 4b) 1468 1469 : "=A"(usdiff), [faulted] "=r" (faulted) 1470 : "A"(usdiff * 1000), [divisor] "rm"(vcpu->arch.virtual_tsc_khz)); 1471 1472 #endif 1473 do_div(elapsed, 1000); 1474 usdiff -= elapsed; 1475 if (usdiff < 0) 1476 usdiff = -usdiff; 1477 1478 /* idivl overflow => difference is larger than USEC_PER_SEC */ 1479 if (faulted) 1480 usdiff = USEC_PER_SEC; 1481 } else 1482 usdiff = USEC_PER_SEC; /* disable TSC match window below */ 1483 1484 /* 1485 * Special case: TSC write with a small delta (1 second) of virtual 1486 * cycle time against real time is interpreted as an attempt to 1487 * synchronize the CPU. 1488 * 1489 * For a reliable TSC, we can match TSC offsets, and for an unstable 1490 * TSC, we add elapsed time in this computation. We could let the 1491 * compensation code attempt to catch up if we fall behind, but 1492 * it's better to try to match offsets from the beginning. 1493 */ 1494 if (usdiff < USEC_PER_SEC && 1495 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) { 1496 if (!check_tsc_unstable()) { 1497 offset = kvm->arch.cur_tsc_offset; 1498 pr_debug("kvm: matched tsc offset for %llu\n", data); 1499 } else { 1500 u64 delta = nsec_to_cycles(vcpu, elapsed); 1501 data += delta; 1502 offset = kvm_compute_tsc_offset(vcpu, data); 1503 pr_debug("kvm: adjusted tsc offset by %llu\n", delta); 1504 } 1505 matched = true; 1506 already_matched = (vcpu->arch.this_tsc_generation == kvm->arch.cur_tsc_generation); 1507 } else { 1508 /* 1509 * We split periods of matched TSC writes into generations. 1510 * For each generation, we track the original measured 1511 * nanosecond time, offset, and write, so if TSCs are in 1512 * sync, we can match exact offset, and if not, we can match 1513 * exact software computation in compute_guest_tsc() 1514 * 1515 * These values are tracked in kvm->arch.cur_xxx variables. 1516 */ 1517 kvm->arch.cur_tsc_generation++; 1518 kvm->arch.cur_tsc_nsec = ns; 1519 kvm->arch.cur_tsc_write = data; 1520 kvm->arch.cur_tsc_offset = offset; 1521 matched = false; 1522 pr_debug("kvm: new tsc generation %llu, clock %llu\n", 1523 kvm->arch.cur_tsc_generation, data); 1524 } 1525 1526 /* 1527 * We also track th most recent recorded KHZ, write and time to 1528 * allow the matching interval to be extended at each write. 1529 */ 1530 kvm->arch.last_tsc_nsec = ns; 1531 kvm->arch.last_tsc_write = data; 1532 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz; 1533 1534 vcpu->arch.last_guest_tsc = data; 1535 1536 /* Keep track of which generation this VCPU has synchronized to */ 1537 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation; 1538 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec; 1539 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write; 1540 1541 if (guest_cpuid_has_tsc_adjust(vcpu) && !msr->host_initiated) 1542 update_ia32_tsc_adjust_msr(vcpu, offset); 1543 kvm_vcpu_write_tsc_offset(vcpu, offset); 1544 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags); 1545 1546 spin_lock(&kvm->arch.pvclock_gtod_sync_lock); 1547 if (!matched) { 1548 kvm->arch.nr_vcpus_matched_tsc = 0; 1549 } else if (!already_matched) { 1550 kvm->arch.nr_vcpus_matched_tsc++; 1551 } 1552 1553 kvm_track_tsc_matching(vcpu); 1554 spin_unlock(&kvm->arch.pvclock_gtod_sync_lock); 1555 } 1556 1557 EXPORT_SYMBOL_GPL(kvm_write_tsc); 1558 1559 static inline void adjust_tsc_offset_guest(struct kvm_vcpu *vcpu, 1560 s64 adjustment) 1561 { 1562 kvm_vcpu_write_tsc_offset(vcpu, vcpu->arch.tsc_offset + adjustment); 1563 } 1564 1565 static inline void adjust_tsc_offset_host(struct kvm_vcpu *vcpu, s64 adjustment) 1566 { 1567 if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio) 1568 WARN_ON(adjustment < 0); 1569 adjustment = kvm_scale_tsc(vcpu, (u64) adjustment); 1570 adjust_tsc_offset_guest(vcpu, adjustment); 1571 } 1572 1573 #ifdef CONFIG_X86_64 1574 1575 static cycle_t read_tsc(void) 1576 { 1577 cycle_t ret = (cycle_t)rdtsc_ordered(); 1578 u64 last = pvclock_gtod_data.clock.cycle_last; 1579 1580 if (likely(ret >= last)) 1581 return ret; 1582 1583 /* 1584 * GCC likes to generate cmov here, but this branch is extremely 1585 * predictable (it's just a function of time and the likely is 1586 * very likely) and there's a data dependence, so force GCC 1587 * to generate a branch instead. I don't barrier() because 1588 * we don't actually need a barrier, and if this function 1589 * ever gets inlined it will generate worse code. 1590 */ 1591 asm volatile (""); 1592 return last; 1593 } 1594 1595 static inline u64 vgettsc(cycle_t *cycle_now) 1596 { 1597 long v; 1598 struct pvclock_gtod_data *gtod = &pvclock_gtod_data; 1599 1600 *cycle_now = read_tsc(); 1601 1602 v = (*cycle_now - gtod->clock.cycle_last) & gtod->clock.mask; 1603 return v * gtod->clock.mult; 1604 } 1605 1606 static int do_monotonic_boot(s64 *t, cycle_t *cycle_now) 1607 { 1608 struct pvclock_gtod_data *gtod = &pvclock_gtod_data; 1609 unsigned long seq; 1610 int mode; 1611 u64 ns; 1612 1613 do { 1614 seq = read_seqcount_begin(>od->seq); 1615 mode = gtod->clock.vclock_mode; 1616 ns = gtod->nsec_base; 1617 ns += vgettsc(cycle_now); 1618 ns >>= gtod->clock.shift; 1619 ns += gtod->boot_ns; 1620 } while (unlikely(read_seqcount_retry(>od->seq, seq))); 1621 *t = ns; 1622 1623 return mode; 1624 } 1625 1626 /* returns true if host is using tsc clocksource */ 1627 static bool kvm_get_time_and_clockread(s64 *kernel_ns, cycle_t *cycle_now) 1628 { 1629 /* checked again under seqlock below */ 1630 if (pvclock_gtod_data.clock.vclock_mode != VCLOCK_TSC) 1631 return false; 1632 1633 return do_monotonic_boot(kernel_ns, cycle_now) == VCLOCK_TSC; 1634 } 1635 #endif 1636 1637 /* 1638 * 1639 * Assuming a stable TSC across physical CPUS, and a stable TSC 1640 * across virtual CPUs, the following condition is possible. 1641 * Each numbered line represents an event visible to both 1642 * CPUs at the next numbered event. 1643 * 1644 * "timespecX" represents host monotonic time. "tscX" represents 1645 * RDTSC value. 1646 * 1647 * VCPU0 on CPU0 | VCPU1 on CPU1 1648 * 1649 * 1. read timespec0,tsc0 1650 * 2. | timespec1 = timespec0 + N 1651 * | tsc1 = tsc0 + M 1652 * 3. transition to guest | transition to guest 1653 * 4. ret0 = timespec0 + (rdtsc - tsc0) | 1654 * 5. | ret1 = timespec1 + (rdtsc - tsc1) 1655 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M)) 1656 * 1657 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity: 1658 * 1659 * - ret0 < ret1 1660 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M)) 1661 * ... 1662 * - 0 < N - M => M < N 1663 * 1664 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not 1665 * always the case (the difference between two distinct xtime instances 1666 * might be smaller then the difference between corresponding TSC reads, 1667 * when updating guest vcpus pvclock areas). 1668 * 1669 * To avoid that problem, do not allow visibility of distinct 1670 * system_timestamp/tsc_timestamp values simultaneously: use a master 1671 * copy of host monotonic time values. Update that master copy 1672 * in lockstep. 1673 * 1674 * Rely on synchronization of host TSCs and guest TSCs for monotonicity. 1675 * 1676 */ 1677 1678 static void pvclock_update_vm_gtod_copy(struct kvm *kvm) 1679 { 1680 #ifdef CONFIG_X86_64 1681 struct kvm_arch *ka = &kvm->arch; 1682 int vclock_mode; 1683 bool host_tsc_clocksource, vcpus_matched; 1684 1685 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 == 1686 atomic_read(&kvm->online_vcpus)); 1687 1688 /* 1689 * If the host uses TSC clock, then passthrough TSC as stable 1690 * to the guest. 1691 */ 1692 host_tsc_clocksource = kvm_get_time_and_clockread( 1693 &ka->master_kernel_ns, 1694 &ka->master_cycle_now); 1695 1696 ka->use_master_clock = host_tsc_clocksource && vcpus_matched 1697 && !backwards_tsc_observed 1698 && !ka->boot_vcpu_runs_old_kvmclock; 1699 1700 if (ka->use_master_clock) 1701 atomic_set(&kvm_guest_has_master_clock, 1); 1702 1703 vclock_mode = pvclock_gtod_data.clock.vclock_mode; 1704 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode, 1705 vcpus_matched); 1706 #endif 1707 } 1708 1709 void kvm_make_mclock_inprogress_request(struct kvm *kvm) 1710 { 1711 kvm_make_all_cpus_request(kvm, KVM_REQ_MCLOCK_INPROGRESS); 1712 } 1713 1714 static void kvm_gen_update_masterclock(struct kvm *kvm) 1715 { 1716 #ifdef CONFIG_X86_64 1717 int i; 1718 struct kvm_vcpu *vcpu; 1719 struct kvm_arch *ka = &kvm->arch; 1720 1721 spin_lock(&ka->pvclock_gtod_sync_lock); 1722 kvm_make_mclock_inprogress_request(kvm); 1723 /* no guest entries from this point */ 1724 pvclock_update_vm_gtod_copy(kvm); 1725 1726 kvm_for_each_vcpu(i, vcpu, kvm) 1727 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 1728 1729 /* guest entries allowed */ 1730 kvm_for_each_vcpu(i, vcpu, kvm) 1731 clear_bit(KVM_REQ_MCLOCK_INPROGRESS, &vcpu->requests); 1732 1733 spin_unlock(&ka->pvclock_gtod_sync_lock); 1734 #endif 1735 } 1736 1737 static u64 __get_kvmclock_ns(struct kvm *kvm) 1738 { 1739 struct kvm_arch *ka = &kvm->arch; 1740 struct pvclock_vcpu_time_info hv_clock; 1741 1742 spin_lock(&ka->pvclock_gtod_sync_lock); 1743 if (!ka->use_master_clock) { 1744 spin_unlock(&ka->pvclock_gtod_sync_lock); 1745 return ktime_get_boot_ns() + ka->kvmclock_offset; 1746 } 1747 1748 hv_clock.tsc_timestamp = ka->master_cycle_now; 1749 hv_clock.system_time = ka->master_kernel_ns + ka->kvmclock_offset; 1750 spin_unlock(&ka->pvclock_gtod_sync_lock); 1751 1752 kvm_get_time_scale(NSEC_PER_SEC, __this_cpu_read(cpu_tsc_khz) * 1000LL, 1753 &hv_clock.tsc_shift, 1754 &hv_clock.tsc_to_system_mul); 1755 return __pvclock_read_cycles(&hv_clock, rdtsc()); 1756 } 1757 1758 u64 get_kvmclock_ns(struct kvm *kvm) 1759 { 1760 unsigned long flags; 1761 s64 ns; 1762 1763 local_irq_save(flags); 1764 ns = __get_kvmclock_ns(kvm); 1765 local_irq_restore(flags); 1766 1767 return ns; 1768 } 1769 1770 static void kvm_setup_pvclock_page(struct kvm_vcpu *v) 1771 { 1772 struct kvm_vcpu_arch *vcpu = &v->arch; 1773 struct pvclock_vcpu_time_info guest_hv_clock; 1774 1775 if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time, 1776 &guest_hv_clock, sizeof(guest_hv_clock)))) 1777 return; 1778 1779 /* This VCPU is paused, but it's legal for a guest to read another 1780 * VCPU's kvmclock, so we really have to follow the specification where 1781 * it says that version is odd if data is being modified, and even after 1782 * it is consistent. 1783 * 1784 * Version field updates must be kept separate. This is because 1785 * kvm_write_guest_cached might use a "rep movs" instruction, and 1786 * writes within a string instruction are weakly ordered. So there 1787 * are three writes overall. 1788 * 1789 * As a small optimization, only write the version field in the first 1790 * and third write. The vcpu->pv_time cache is still valid, because the 1791 * version field is the first in the struct. 1792 */ 1793 BUILD_BUG_ON(offsetof(struct pvclock_vcpu_time_info, version) != 0); 1794 1795 vcpu->hv_clock.version = guest_hv_clock.version + 1; 1796 kvm_write_guest_cached(v->kvm, &vcpu->pv_time, 1797 &vcpu->hv_clock, 1798 sizeof(vcpu->hv_clock.version)); 1799 1800 smp_wmb(); 1801 1802 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */ 1803 vcpu->hv_clock.flags |= (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED); 1804 1805 if (vcpu->pvclock_set_guest_stopped_request) { 1806 vcpu->hv_clock.flags |= PVCLOCK_GUEST_STOPPED; 1807 vcpu->pvclock_set_guest_stopped_request = false; 1808 } 1809 1810 trace_kvm_pvclock_update(v->vcpu_id, &vcpu->hv_clock); 1811 1812 kvm_write_guest_cached(v->kvm, &vcpu->pv_time, 1813 &vcpu->hv_clock, 1814 sizeof(vcpu->hv_clock)); 1815 1816 smp_wmb(); 1817 1818 vcpu->hv_clock.version++; 1819 kvm_write_guest_cached(v->kvm, &vcpu->pv_time, 1820 &vcpu->hv_clock, 1821 sizeof(vcpu->hv_clock.version)); 1822 } 1823 1824 static int kvm_guest_time_update(struct kvm_vcpu *v) 1825 { 1826 unsigned long flags, tgt_tsc_khz; 1827 struct kvm_vcpu_arch *vcpu = &v->arch; 1828 struct kvm_arch *ka = &v->kvm->arch; 1829 s64 kernel_ns; 1830 u64 tsc_timestamp, host_tsc; 1831 u8 pvclock_flags; 1832 bool use_master_clock; 1833 1834 kernel_ns = 0; 1835 host_tsc = 0; 1836 1837 /* 1838 * If the host uses TSC clock, then passthrough TSC as stable 1839 * to the guest. 1840 */ 1841 spin_lock(&ka->pvclock_gtod_sync_lock); 1842 use_master_clock = ka->use_master_clock; 1843 if (use_master_clock) { 1844 host_tsc = ka->master_cycle_now; 1845 kernel_ns = ka->master_kernel_ns; 1846 } 1847 spin_unlock(&ka->pvclock_gtod_sync_lock); 1848 1849 /* Keep irq disabled to prevent changes to the clock */ 1850 local_irq_save(flags); 1851 tgt_tsc_khz = __this_cpu_read(cpu_tsc_khz); 1852 if (unlikely(tgt_tsc_khz == 0)) { 1853 local_irq_restore(flags); 1854 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v); 1855 return 1; 1856 } 1857 if (!use_master_clock) { 1858 host_tsc = rdtsc(); 1859 kernel_ns = ktime_get_boot_ns(); 1860 } 1861 1862 tsc_timestamp = kvm_read_l1_tsc(v, host_tsc); 1863 1864 /* 1865 * We may have to catch up the TSC to match elapsed wall clock 1866 * time for two reasons, even if kvmclock is used. 1867 * 1) CPU could have been running below the maximum TSC rate 1868 * 2) Broken TSC compensation resets the base at each VCPU 1869 * entry to avoid unknown leaps of TSC even when running 1870 * again on the same CPU. This may cause apparent elapsed 1871 * time to disappear, and the guest to stand still or run 1872 * very slowly. 1873 */ 1874 if (vcpu->tsc_catchup) { 1875 u64 tsc = compute_guest_tsc(v, kernel_ns); 1876 if (tsc > tsc_timestamp) { 1877 adjust_tsc_offset_guest(v, tsc - tsc_timestamp); 1878 tsc_timestamp = tsc; 1879 } 1880 } 1881 1882 local_irq_restore(flags); 1883 1884 /* With all the info we got, fill in the values */ 1885 1886 if (kvm_has_tsc_control) 1887 tgt_tsc_khz = kvm_scale_tsc(v, tgt_tsc_khz); 1888 1889 if (unlikely(vcpu->hw_tsc_khz != tgt_tsc_khz)) { 1890 kvm_get_time_scale(NSEC_PER_SEC, tgt_tsc_khz * 1000LL, 1891 &vcpu->hv_clock.tsc_shift, 1892 &vcpu->hv_clock.tsc_to_system_mul); 1893 vcpu->hw_tsc_khz = tgt_tsc_khz; 1894 } 1895 1896 vcpu->hv_clock.tsc_timestamp = tsc_timestamp; 1897 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset; 1898 vcpu->last_guest_tsc = tsc_timestamp; 1899 1900 /* If the host uses TSC clocksource, then it is stable */ 1901 pvclock_flags = 0; 1902 if (use_master_clock) 1903 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT; 1904 1905 vcpu->hv_clock.flags = pvclock_flags; 1906 1907 if (vcpu->pv_time_enabled) 1908 kvm_setup_pvclock_page(v); 1909 if (v == kvm_get_vcpu(v->kvm, 0)) 1910 kvm_hv_setup_tsc_page(v->kvm, &vcpu->hv_clock); 1911 return 0; 1912 } 1913 1914 /* 1915 * kvmclock updates which are isolated to a given vcpu, such as 1916 * vcpu->cpu migration, should not allow system_timestamp from 1917 * the rest of the vcpus to remain static. Otherwise ntp frequency 1918 * correction applies to one vcpu's system_timestamp but not 1919 * the others. 1920 * 1921 * So in those cases, request a kvmclock update for all vcpus. 1922 * We need to rate-limit these requests though, as they can 1923 * considerably slow guests that have a large number of vcpus. 1924 * The time for a remote vcpu to update its kvmclock is bound 1925 * by the delay we use to rate-limit the updates. 1926 */ 1927 1928 #define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100) 1929 1930 static void kvmclock_update_fn(struct work_struct *work) 1931 { 1932 int i; 1933 struct delayed_work *dwork = to_delayed_work(work); 1934 struct kvm_arch *ka = container_of(dwork, struct kvm_arch, 1935 kvmclock_update_work); 1936 struct kvm *kvm = container_of(ka, struct kvm, arch); 1937 struct kvm_vcpu *vcpu; 1938 1939 kvm_for_each_vcpu(i, vcpu, kvm) { 1940 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 1941 kvm_vcpu_kick(vcpu); 1942 } 1943 } 1944 1945 static void kvm_gen_kvmclock_update(struct kvm_vcpu *v) 1946 { 1947 struct kvm *kvm = v->kvm; 1948 1949 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v); 1950 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 1951 KVMCLOCK_UPDATE_DELAY); 1952 } 1953 1954 #define KVMCLOCK_SYNC_PERIOD (300 * HZ) 1955 1956 static void kvmclock_sync_fn(struct work_struct *work) 1957 { 1958 struct delayed_work *dwork = to_delayed_work(work); 1959 struct kvm_arch *ka = container_of(dwork, struct kvm_arch, 1960 kvmclock_sync_work); 1961 struct kvm *kvm = container_of(ka, struct kvm, arch); 1962 1963 if (!kvmclock_periodic_sync) 1964 return; 1965 1966 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0); 1967 schedule_delayed_work(&kvm->arch.kvmclock_sync_work, 1968 KVMCLOCK_SYNC_PERIOD); 1969 } 1970 1971 static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data) 1972 { 1973 u64 mcg_cap = vcpu->arch.mcg_cap; 1974 unsigned bank_num = mcg_cap & 0xff; 1975 1976 switch (msr) { 1977 case MSR_IA32_MCG_STATUS: 1978 vcpu->arch.mcg_status = data; 1979 break; 1980 case MSR_IA32_MCG_CTL: 1981 if (!(mcg_cap & MCG_CTL_P)) 1982 return 1; 1983 if (data != 0 && data != ~(u64)0) 1984 return -1; 1985 vcpu->arch.mcg_ctl = data; 1986 break; 1987 default: 1988 if (msr >= MSR_IA32_MC0_CTL && 1989 msr < MSR_IA32_MCx_CTL(bank_num)) { 1990 u32 offset = msr - MSR_IA32_MC0_CTL; 1991 /* only 0 or all 1s can be written to IA32_MCi_CTL 1992 * some Linux kernels though clear bit 10 in bank 4 to 1993 * workaround a BIOS/GART TBL issue on AMD K8s, ignore 1994 * this to avoid an uncatched #GP in the guest 1995 */ 1996 if ((offset & 0x3) == 0 && 1997 data != 0 && (data | (1 << 10)) != ~(u64)0) 1998 return -1; 1999 vcpu->arch.mce_banks[offset] = data; 2000 break; 2001 } 2002 return 1; 2003 } 2004 return 0; 2005 } 2006 2007 static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data) 2008 { 2009 struct kvm *kvm = vcpu->kvm; 2010 int lm = is_long_mode(vcpu); 2011 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64 2012 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32; 2013 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64 2014 : kvm->arch.xen_hvm_config.blob_size_32; 2015 u32 page_num = data & ~PAGE_MASK; 2016 u64 page_addr = data & PAGE_MASK; 2017 u8 *page; 2018 int r; 2019 2020 r = -E2BIG; 2021 if (page_num >= blob_size) 2022 goto out; 2023 r = -ENOMEM; 2024 page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE); 2025 if (IS_ERR(page)) { 2026 r = PTR_ERR(page); 2027 goto out; 2028 } 2029 if (kvm_vcpu_write_guest(vcpu, page_addr, page, PAGE_SIZE)) 2030 goto out_free; 2031 r = 0; 2032 out_free: 2033 kfree(page); 2034 out: 2035 return r; 2036 } 2037 2038 static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data) 2039 { 2040 gpa_t gpa = data & ~0x3f; 2041 2042 /* Bits 2:5 are reserved, Should be zero */ 2043 if (data & 0x3c) 2044 return 1; 2045 2046 vcpu->arch.apf.msr_val = data; 2047 2048 if (!(data & KVM_ASYNC_PF_ENABLED)) { 2049 kvm_clear_async_pf_completion_queue(vcpu); 2050 kvm_async_pf_hash_reset(vcpu); 2051 return 0; 2052 } 2053 2054 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa, 2055 sizeof(u32))) 2056 return 1; 2057 2058 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS); 2059 kvm_async_pf_wakeup_all(vcpu); 2060 return 0; 2061 } 2062 2063 static void kvmclock_reset(struct kvm_vcpu *vcpu) 2064 { 2065 vcpu->arch.pv_time_enabled = false; 2066 } 2067 2068 static void record_steal_time(struct kvm_vcpu *vcpu) 2069 { 2070 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED)) 2071 return; 2072 2073 if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime, 2074 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time)))) 2075 return; 2076 2077 vcpu->arch.st.steal.preempted = 0; 2078 2079 if (vcpu->arch.st.steal.version & 1) 2080 vcpu->arch.st.steal.version += 1; /* first time write, random junk */ 2081 2082 vcpu->arch.st.steal.version += 1; 2083 2084 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime, 2085 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time)); 2086 2087 smp_wmb(); 2088 2089 vcpu->arch.st.steal.steal += current->sched_info.run_delay - 2090 vcpu->arch.st.last_steal; 2091 vcpu->arch.st.last_steal = current->sched_info.run_delay; 2092 2093 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime, 2094 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time)); 2095 2096 smp_wmb(); 2097 2098 vcpu->arch.st.steal.version += 1; 2099 2100 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime, 2101 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time)); 2102 } 2103 2104 int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info) 2105 { 2106 bool pr = false; 2107 u32 msr = msr_info->index; 2108 u64 data = msr_info->data; 2109 2110 switch (msr) { 2111 case MSR_AMD64_NB_CFG: 2112 case MSR_IA32_UCODE_REV: 2113 case MSR_IA32_UCODE_WRITE: 2114 case MSR_VM_HSAVE_PA: 2115 case MSR_AMD64_PATCH_LOADER: 2116 case MSR_AMD64_BU_CFG2: 2117 break; 2118 2119 case MSR_EFER: 2120 return set_efer(vcpu, data); 2121 case MSR_K7_HWCR: 2122 data &= ~(u64)0x40; /* ignore flush filter disable */ 2123 data &= ~(u64)0x100; /* ignore ignne emulation enable */ 2124 data &= ~(u64)0x8; /* ignore TLB cache disable */ 2125 data &= ~(u64)0x40000; /* ignore Mc status write enable */ 2126 if (data != 0) { 2127 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n", 2128 data); 2129 return 1; 2130 } 2131 break; 2132 case MSR_FAM10H_MMIO_CONF_BASE: 2133 if (data != 0) { 2134 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: " 2135 "0x%llx\n", data); 2136 return 1; 2137 } 2138 break; 2139 case MSR_IA32_DEBUGCTLMSR: 2140 if (!data) { 2141 /* We support the non-activated case already */ 2142 break; 2143 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) { 2144 /* Values other than LBR and BTF are vendor-specific, 2145 thus reserved and should throw a #GP */ 2146 return 1; 2147 } 2148 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n", 2149 __func__, data); 2150 break; 2151 case 0x200 ... 0x2ff: 2152 return kvm_mtrr_set_msr(vcpu, msr, data); 2153 case MSR_IA32_APICBASE: 2154 return kvm_set_apic_base(vcpu, msr_info); 2155 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff: 2156 return kvm_x2apic_msr_write(vcpu, msr, data); 2157 case MSR_IA32_TSCDEADLINE: 2158 kvm_set_lapic_tscdeadline_msr(vcpu, data); 2159 break; 2160 case MSR_IA32_TSC_ADJUST: 2161 if (guest_cpuid_has_tsc_adjust(vcpu)) { 2162 if (!msr_info->host_initiated) { 2163 s64 adj = data - vcpu->arch.ia32_tsc_adjust_msr; 2164 adjust_tsc_offset_guest(vcpu, adj); 2165 } 2166 vcpu->arch.ia32_tsc_adjust_msr = data; 2167 } 2168 break; 2169 case MSR_IA32_MISC_ENABLE: 2170 vcpu->arch.ia32_misc_enable_msr = data; 2171 break; 2172 case MSR_IA32_SMBASE: 2173 if (!msr_info->host_initiated) 2174 return 1; 2175 vcpu->arch.smbase = data; 2176 break; 2177 case MSR_KVM_WALL_CLOCK_NEW: 2178 case MSR_KVM_WALL_CLOCK: 2179 vcpu->kvm->arch.wall_clock = data; 2180 kvm_write_wall_clock(vcpu->kvm, data); 2181 break; 2182 case MSR_KVM_SYSTEM_TIME_NEW: 2183 case MSR_KVM_SYSTEM_TIME: { 2184 struct kvm_arch *ka = &vcpu->kvm->arch; 2185 2186 kvmclock_reset(vcpu); 2187 2188 if (vcpu->vcpu_id == 0 && !msr_info->host_initiated) { 2189 bool tmp = (msr == MSR_KVM_SYSTEM_TIME); 2190 2191 if (ka->boot_vcpu_runs_old_kvmclock != tmp) 2192 set_bit(KVM_REQ_MASTERCLOCK_UPDATE, 2193 &vcpu->requests); 2194 2195 ka->boot_vcpu_runs_old_kvmclock = tmp; 2196 } 2197 2198 vcpu->arch.time = data; 2199 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu); 2200 2201 /* we verify if the enable bit is set... */ 2202 if (!(data & 1)) 2203 break; 2204 2205 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, 2206 &vcpu->arch.pv_time, data & ~1ULL, 2207 sizeof(struct pvclock_vcpu_time_info))) 2208 vcpu->arch.pv_time_enabled = false; 2209 else 2210 vcpu->arch.pv_time_enabled = true; 2211 2212 break; 2213 } 2214 case MSR_KVM_ASYNC_PF_EN: 2215 if (kvm_pv_enable_async_pf(vcpu, data)) 2216 return 1; 2217 break; 2218 case MSR_KVM_STEAL_TIME: 2219 2220 if (unlikely(!sched_info_on())) 2221 return 1; 2222 2223 if (data & KVM_STEAL_RESERVED_MASK) 2224 return 1; 2225 2226 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime, 2227 data & KVM_STEAL_VALID_BITS, 2228 sizeof(struct kvm_steal_time))) 2229 return 1; 2230 2231 vcpu->arch.st.msr_val = data; 2232 2233 if (!(data & KVM_MSR_ENABLED)) 2234 break; 2235 2236 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu); 2237 2238 break; 2239 case MSR_KVM_PV_EOI_EN: 2240 if (kvm_lapic_enable_pv_eoi(vcpu, data)) 2241 return 1; 2242 break; 2243 2244 case MSR_IA32_MCG_CTL: 2245 case MSR_IA32_MCG_STATUS: 2246 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1: 2247 return set_msr_mce(vcpu, msr, data); 2248 2249 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3: 2250 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1: 2251 pr = true; /* fall through */ 2252 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3: 2253 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1: 2254 if (kvm_pmu_is_valid_msr(vcpu, msr)) 2255 return kvm_pmu_set_msr(vcpu, msr_info); 2256 2257 if (pr || data != 0) 2258 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: " 2259 "0x%x data 0x%llx\n", msr, data); 2260 break; 2261 case MSR_K7_CLK_CTL: 2262 /* 2263 * Ignore all writes to this no longer documented MSR. 2264 * Writes are only relevant for old K7 processors, 2265 * all pre-dating SVM, but a recommended workaround from 2266 * AMD for these chips. It is possible to specify the 2267 * affected processor models on the command line, hence 2268 * the need to ignore the workaround. 2269 */ 2270 break; 2271 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15: 2272 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4: 2273 case HV_X64_MSR_CRASH_CTL: 2274 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT: 2275 return kvm_hv_set_msr_common(vcpu, msr, data, 2276 msr_info->host_initiated); 2277 case MSR_IA32_BBL_CR_CTL3: 2278 /* Drop writes to this legacy MSR -- see rdmsr 2279 * counterpart for further detail. 2280 */ 2281 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data 0x%llx\n", msr, data); 2282 break; 2283 case MSR_AMD64_OSVW_ID_LENGTH: 2284 if (!guest_cpuid_has_osvw(vcpu)) 2285 return 1; 2286 vcpu->arch.osvw.length = data; 2287 break; 2288 case MSR_AMD64_OSVW_STATUS: 2289 if (!guest_cpuid_has_osvw(vcpu)) 2290 return 1; 2291 vcpu->arch.osvw.status = data; 2292 break; 2293 default: 2294 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr)) 2295 return xen_hvm_config(vcpu, data); 2296 if (kvm_pmu_is_valid_msr(vcpu, msr)) 2297 return kvm_pmu_set_msr(vcpu, msr_info); 2298 if (!ignore_msrs) { 2299 vcpu_debug_ratelimited(vcpu, "unhandled wrmsr: 0x%x data 0x%llx\n", 2300 msr, data); 2301 return 1; 2302 } else { 2303 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data 0x%llx\n", 2304 msr, data); 2305 break; 2306 } 2307 } 2308 return 0; 2309 } 2310 EXPORT_SYMBOL_GPL(kvm_set_msr_common); 2311 2312 2313 /* 2314 * Reads an msr value (of 'msr_index') into 'pdata'. 2315 * Returns 0 on success, non-0 otherwise. 2316 * Assumes vcpu_load() was already called. 2317 */ 2318 int kvm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr) 2319 { 2320 return kvm_x86_ops->get_msr(vcpu, msr); 2321 } 2322 EXPORT_SYMBOL_GPL(kvm_get_msr); 2323 2324 static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata) 2325 { 2326 u64 data; 2327 u64 mcg_cap = vcpu->arch.mcg_cap; 2328 unsigned bank_num = mcg_cap & 0xff; 2329 2330 switch (msr) { 2331 case MSR_IA32_P5_MC_ADDR: 2332 case MSR_IA32_P5_MC_TYPE: 2333 data = 0; 2334 break; 2335 case MSR_IA32_MCG_CAP: 2336 data = vcpu->arch.mcg_cap; 2337 break; 2338 case MSR_IA32_MCG_CTL: 2339 if (!(mcg_cap & MCG_CTL_P)) 2340 return 1; 2341 data = vcpu->arch.mcg_ctl; 2342 break; 2343 case MSR_IA32_MCG_STATUS: 2344 data = vcpu->arch.mcg_status; 2345 break; 2346 default: 2347 if (msr >= MSR_IA32_MC0_CTL && 2348 msr < MSR_IA32_MCx_CTL(bank_num)) { 2349 u32 offset = msr - MSR_IA32_MC0_CTL; 2350 data = vcpu->arch.mce_banks[offset]; 2351 break; 2352 } 2353 return 1; 2354 } 2355 *pdata = data; 2356 return 0; 2357 } 2358 2359 int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info) 2360 { 2361 switch (msr_info->index) { 2362 case MSR_IA32_PLATFORM_ID: 2363 case MSR_IA32_EBL_CR_POWERON: 2364 case MSR_IA32_DEBUGCTLMSR: 2365 case MSR_IA32_LASTBRANCHFROMIP: 2366 case MSR_IA32_LASTBRANCHTOIP: 2367 case MSR_IA32_LASTINTFROMIP: 2368 case MSR_IA32_LASTINTTOIP: 2369 case MSR_K8_SYSCFG: 2370 case MSR_K8_TSEG_ADDR: 2371 case MSR_K8_TSEG_MASK: 2372 case MSR_K7_HWCR: 2373 case MSR_VM_HSAVE_PA: 2374 case MSR_K8_INT_PENDING_MSG: 2375 case MSR_AMD64_NB_CFG: 2376 case MSR_FAM10H_MMIO_CONF_BASE: 2377 case MSR_AMD64_BU_CFG2: 2378 case MSR_IA32_PERF_CTL: 2379 msr_info->data = 0; 2380 break; 2381 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3: 2382 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3: 2383 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1: 2384 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1: 2385 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index)) 2386 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data); 2387 msr_info->data = 0; 2388 break; 2389 case MSR_IA32_UCODE_REV: 2390 msr_info->data = 0x100000000ULL; 2391 break; 2392 case MSR_MTRRcap: 2393 case 0x200 ... 0x2ff: 2394 return kvm_mtrr_get_msr(vcpu, msr_info->index, &msr_info->data); 2395 case 0xcd: /* fsb frequency */ 2396 msr_info->data = 3; 2397 break; 2398 /* 2399 * MSR_EBC_FREQUENCY_ID 2400 * Conservative value valid for even the basic CPU models. 2401 * Models 0,1: 000 in bits 23:21 indicating a bus speed of 2402 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz, 2403 * and 266MHz for model 3, or 4. Set Core Clock 2404 * Frequency to System Bus Frequency Ratio to 1 (bits 2405 * 31:24) even though these are only valid for CPU 2406 * models > 2, however guests may end up dividing or 2407 * multiplying by zero otherwise. 2408 */ 2409 case MSR_EBC_FREQUENCY_ID: 2410 msr_info->data = 1 << 24; 2411 break; 2412 case MSR_IA32_APICBASE: 2413 msr_info->data = kvm_get_apic_base(vcpu); 2414 break; 2415 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff: 2416 return kvm_x2apic_msr_read(vcpu, msr_info->index, &msr_info->data); 2417 break; 2418 case MSR_IA32_TSCDEADLINE: 2419 msr_info->data = kvm_get_lapic_tscdeadline_msr(vcpu); 2420 break; 2421 case MSR_IA32_TSC_ADJUST: 2422 msr_info->data = (u64)vcpu->arch.ia32_tsc_adjust_msr; 2423 break; 2424 case MSR_IA32_MISC_ENABLE: 2425 msr_info->data = vcpu->arch.ia32_misc_enable_msr; 2426 break; 2427 case MSR_IA32_SMBASE: 2428 if (!msr_info->host_initiated) 2429 return 1; 2430 msr_info->data = vcpu->arch.smbase; 2431 break; 2432 case MSR_IA32_PERF_STATUS: 2433 /* TSC increment by tick */ 2434 msr_info->data = 1000ULL; 2435 /* CPU multiplier */ 2436 msr_info->data |= (((uint64_t)4ULL) << 40); 2437 break; 2438 case MSR_EFER: 2439 msr_info->data = vcpu->arch.efer; 2440 break; 2441 case MSR_KVM_WALL_CLOCK: 2442 case MSR_KVM_WALL_CLOCK_NEW: 2443 msr_info->data = vcpu->kvm->arch.wall_clock; 2444 break; 2445 case MSR_KVM_SYSTEM_TIME: 2446 case MSR_KVM_SYSTEM_TIME_NEW: 2447 msr_info->data = vcpu->arch.time; 2448 break; 2449 case MSR_KVM_ASYNC_PF_EN: 2450 msr_info->data = vcpu->arch.apf.msr_val; 2451 break; 2452 case MSR_KVM_STEAL_TIME: 2453 msr_info->data = vcpu->arch.st.msr_val; 2454 break; 2455 case MSR_KVM_PV_EOI_EN: 2456 msr_info->data = vcpu->arch.pv_eoi.msr_val; 2457 break; 2458 case MSR_IA32_P5_MC_ADDR: 2459 case MSR_IA32_P5_MC_TYPE: 2460 case MSR_IA32_MCG_CAP: 2461 case MSR_IA32_MCG_CTL: 2462 case MSR_IA32_MCG_STATUS: 2463 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1: 2464 return get_msr_mce(vcpu, msr_info->index, &msr_info->data); 2465 case MSR_K7_CLK_CTL: 2466 /* 2467 * Provide expected ramp-up count for K7. All other 2468 * are set to zero, indicating minimum divisors for 2469 * every field. 2470 * 2471 * This prevents guest kernels on AMD host with CPU 2472 * type 6, model 8 and higher from exploding due to 2473 * the rdmsr failing. 2474 */ 2475 msr_info->data = 0x20000000; 2476 break; 2477 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15: 2478 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4: 2479 case HV_X64_MSR_CRASH_CTL: 2480 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT: 2481 return kvm_hv_get_msr_common(vcpu, 2482 msr_info->index, &msr_info->data); 2483 break; 2484 case MSR_IA32_BBL_CR_CTL3: 2485 /* This legacy MSR exists but isn't fully documented in current 2486 * silicon. It is however accessed by winxp in very narrow 2487 * scenarios where it sets bit #19, itself documented as 2488 * a "reserved" bit. Best effort attempt to source coherent 2489 * read data here should the balance of the register be 2490 * interpreted by the guest: 2491 * 2492 * L2 cache control register 3: 64GB range, 256KB size, 2493 * enabled, latency 0x1, configured 2494 */ 2495 msr_info->data = 0xbe702111; 2496 break; 2497 case MSR_AMD64_OSVW_ID_LENGTH: 2498 if (!guest_cpuid_has_osvw(vcpu)) 2499 return 1; 2500 msr_info->data = vcpu->arch.osvw.length; 2501 break; 2502 case MSR_AMD64_OSVW_STATUS: 2503 if (!guest_cpuid_has_osvw(vcpu)) 2504 return 1; 2505 msr_info->data = vcpu->arch.osvw.status; 2506 break; 2507 default: 2508 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index)) 2509 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data); 2510 if (!ignore_msrs) { 2511 vcpu_debug_ratelimited(vcpu, "unhandled rdmsr: 0x%x\n", 2512 msr_info->index); 2513 return 1; 2514 } else { 2515 vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr_info->index); 2516 msr_info->data = 0; 2517 } 2518 break; 2519 } 2520 return 0; 2521 } 2522 EXPORT_SYMBOL_GPL(kvm_get_msr_common); 2523 2524 /* 2525 * Read or write a bunch of msrs. All parameters are kernel addresses. 2526 * 2527 * @return number of msrs set successfully. 2528 */ 2529 static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs, 2530 struct kvm_msr_entry *entries, 2531 int (*do_msr)(struct kvm_vcpu *vcpu, 2532 unsigned index, u64 *data)) 2533 { 2534 int i, idx; 2535 2536 idx = srcu_read_lock(&vcpu->kvm->srcu); 2537 for (i = 0; i < msrs->nmsrs; ++i) 2538 if (do_msr(vcpu, entries[i].index, &entries[i].data)) 2539 break; 2540 srcu_read_unlock(&vcpu->kvm->srcu, idx); 2541 2542 return i; 2543 } 2544 2545 /* 2546 * Read or write a bunch of msrs. Parameters are user addresses. 2547 * 2548 * @return number of msrs set successfully. 2549 */ 2550 static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs, 2551 int (*do_msr)(struct kvm_vcpu *vcpu, 2552 unsigned index, u64 *data), 2553 int writeback) 2554 { 2555 struct kvm_msrs msrs; 2556 struct kvm_msr_entry *entries; 2557 int r, n; 2558 unsigned size; 2559 2560 r = -EFAULT; 2561 if (copy_from_user(&msrs, user_msrs, sizeof msrs)) 2562 goto out; 2563 2564 r = -E2BIG; 2565 if (msrs.nmsrs >= MAX_IO_MSRS) 2566 goto out; 2567 2568 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs; 2569 entries = memdup_user(user_msrs->entries, size); 2570 if (IS_ERR(entries)) { 2571 r = PTR_ERR(entries); 2572 goto out; 2573 } 2574 2575 r = n = __msr_io(vcpu, &msrs, entries, do_msr); 2576 if (r < 0) 2577 goto out_free; 2578 2579 r = -EFAULT; 2580 if (writeback && copy_to_user(user_msrs->entries, entries, size)) 2581 goto out_free; 2582 2583 r = n; 2584 2585 out_free: 2586 kfree(entries); 2587 out: 2588 return r; 2589 } 2590 2591 int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext) 2592 { 2593 int r; 2594 2595 switch (ext) { 2596 case KVM_CAP_IRQCHIP: 2597 case KVM_CAP_HLT: 2598 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL: 2599 case KVM_CAP_SET_TSS_ADDR: 2600 case KVM_CAP_EXT_CPUID: 2601 case KVM_CAP_EXT_EMUL_CPUID: 2602 case KVM_CAP_CLOCKSOURCE: 2603 case KVM_CAP_PIT: 2604 case KVM_CAP_NOP_IO_DELAY: 2605 case KVM_CAP_MP_STATE: 2606 case KVM_CAP_SYNC_MMU: 2607 case KVM_CAP_USER_NMI: 2608 case KVM_CAP_REINJECT_CONTROL: 2609 case KVM_CAP_IRQ_INJECT_STATUS: 2610 case KVM_CAP_IOEVENTFD: 2611 case KVM_CAP_IOEVENTFD_NO_LENGTH: 2612 case KVM_CAP_PIT2: 2613 case KVM_CAP_PIT_STATE2: 2614 case KVM_CAP_SET_IDENTITY_MAP_ADDR: 2615 case KVM_CAP_XEN_HVM: 2616 case KVM_CAP_VCPU_EVENTS: 2617 case KVM_CAP_HYPERV: 2618 case KVM_CAP_HYPERV_VAPIC: 2619 case KVM_CAP_HYPERV_SPIN: 2620 case KVM_CAP_HYPERV_SYNIC: 2621 case KVM_CAP_PCI_SEGMENT: 2622 case KVM_CAP_DEBUGREGS: 2623 case KVM_CAP_X86_ROBUST_SINGLESTEP: 2624 case KVM_CAP_XSAVE: 2625 case KVM_CAP_ASYNC_PF: 2626 case KVM_CAP_GET_TSC_KHZ: 2627 case KVM_CAP_KVMCLOCK_CTRL: 2628 case KVM_CAP_READONLY_MEM: 2629 case KVM_CAP_HYPERV_TIME: 2630 case KVM_CAP_IOAPIC_POLARITY_IGNORED: 2631 case KVM_CAP_TSC_DEADLINE_TIMER: 2632 case KVM_CAP_ENABLE_CAP_VM: 2633 case KVM_CAP_DISABLE_QUIRKS: 2634 case KVM_CAP_SET_BOOT_CPU_ID: 2635 case KVM_CAP_SPLIT_IRQCHIP: 2636 #ifdef CONFIG_KVM_DEVICE_ASSIGNMENT 2637 case KVM_CAP_ASSIGN_DEV_IRQ: 2638 case KVM_CAP_PCI_2_3: 2639 #endif 2640 r = 1; 2641 break; 2642 case KVM_CAP_ADJUST_CLOCK: 2643 r = KVM_CLOCK_TSC_STABLE; 2644 break; 2645 case KVM_CAP_X86_SMM: 2646 /* SMBASE is usually relocated above 1M on modern chipsets, 2647 * and SMM handlers might indeed rely on 4G segment limits, 2648 * so do not report SMM to be available if real mode is 2649 * emulated via vm86 mode. Still, do not go to great lengths 2650 * to avoid userspace's usage of the feature, because it is a 2651 * fringe case that is not enabled except via specific settings 2652 * of the module parameters. 2653 */ 2654 r = kvm_x86_ops->cpu_has_high_real_mode_segbase(); 2655 break; 2656 case KVM_CAP_COALESCED_MMIO: 2657 r = KVM_COALESCED_MMIO_PAGE_OFFSET; 2658 break; 2659 case KVM_CAP_VAPIC: 2660 r = !kvm_x86_ops->cpu_has_accelerated_tpr(); 2661 break; 2662 case KVM_CAP_NR_VCPUS: 2663 r = KVM_SOFT_MAX_VCPUS; 2664 break; 2665 case KVM_CAP_MAX_VCPUS: 2666 r = KVM_MAX_VCPUS; 2667 break; 2668 case KVM_CAP_NR_MEMSLOTS: 2669 r = KVM_USER_MEM_SLOTS; 2670 break; 2671 case KVM_CAP_PV_MMU: /* obsolete */ 2672 r = 0; 2673 break; 2674 #ifdef CONFIG_KVM_DEVICE_ASSIGNMENT 2675 case KVM_CAP_IOMMU: 2676 r = iommu_present(&pci_bus_type); 2677 break; 2678 #endif 2679 case KVM_CAP_MCE: 2680 r = KVM_MAX_MCE_BANKS; 2681 break; 2682 case KVM_CAP_XCRS: 2683 r = boot_cpu_has(X86_FEATURE_XSAVE); 2684 break; 2685 case KVM_CAP_TSC_CONTROL: 2686 r = kvm_has_tsc_control; 2687 break; 2688 case KVM_CAP_X2APIC_API: 2689 r = KVM_X2APIC_API_VALID_FLAGS; 2690 break; 2691 default: 2692 r = 0; 2693 break; 2694 } 2695 return r; 2696 2697 } 2698 2699 long kvm_arch_dev_ioctl(struct file *filp, 2700 unsigned int ioctl, unsigned long arg) 2701 { 2702 void __user *argp = (void __user *)arg; 2703 long r; 2704 2705 switch (ioctl) { 2706 case KVM_GET_MSR_INDEX_LIST: { 2707 struct kvm_msr_list __user *user_msr_list = argp; 2708 struct kvm_msr_list msr_list; 2709 unsigned n; 2710 2711 r = -EFAULT; 2712 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list)) 2713 goto out; 2714 n = msr_list.nmsrs; 2715 msr_list.nmsrs = num_msrs_to_save + num_emulated_msrs; 2716 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list)) 2717 goto out; 2718 r = -E2BIG; 2719 if (n < msr_list.nmsrs) 2720 goto out; 2721 r = -EFAULT; 2722 if (copy_to_user(user_msr_list->indices, &msrs_to_save, 2723 num_msrs_to_save * sizeof(u32))) 2724 goto out; 2725 if (copy_to_user(user_msr_list->indices + num_msrs_to_save, 2726 &emulated_msrs, 2727 num_emulated_msrs * sizeof(u32))) 2728 goto out; 2729 r = 0; 2730 break; 2731 } 2732 case KVM_GET_SUPPORTED_CPUID: 2733 case KVM_GET_EMULATED_CPUID: { 2734 struct kvm_cpuid2 __user *cpuid_arg = argp; 2735 struct kvm_cpuid2 cpuid; 2736 2737 r = -EFAULT; 2738 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid)) 2739 goto out; 2740 2741 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries, 2742 ioctl); 2743 if (r) 2744 goto out; 2745 2746 r = -EFAULT; 2747 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid)) 2748 goto out; 2749 r = 0; 2750 break; 2751 } 2752 case KVM_X86_GET_MCE_CAP_SUPPORTED: { 2753 r = -EFAULT; 2754 if (copy_to_user(argp, &kvm_mce_cap_supported, 2755 sizeof(kvm_mce_cap_supported))) 2756 goto out; 2757 r = 0; 2758 break; 2759 } 2760 default: 2761 r = -EINVAL; 2762 } 2763 out: 2764 return r; 2765 } 2766 2767 static void wbinvd_ipi(void *garbage) 2768 { 2769 wbinvd(); 2770 } 2771 2772 static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu) 2773 { 2774 return kvm_arch_has_noncoherent_dma(vcpu->kvm); 2775 } 2776 2777 static inline void kvm_migrate_timers(struct kvm_vcpu *vcpu) 2778 { 2779 set_bit(KVM_REQ_MIGRATE_TIMER, &vcpu->requests); 2780 } 2781 2782 void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu) 2783 { 2784 /* Address WBINVD may be executed by guest */ 2785 if (need_emulate_wbinvd(vcpu)) { 2786 if (kvm_x86_ops->has_wbinvd_exit()) 2787 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask); 2788 else if (vcpu->cpu != -1 && vcpu->cpu != cpu) 2789 smp_call_function_single(vcpu->cpu, 2790 wbinvd_ipi, NULL, 1); 2791 } 2792 2793 kvm_x86_ops->vcpu_load(vcpu, cpu); 2794 2795 /* Apply any externally detected TSC adjustments (due to suspend) */ 2796 if (unlikely(vcpu->arch.tsc_offset_adjustment)) { 2797 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment); 2798 vcpu->arch.tsc_offset_adjustment = 0; 2799 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 2800 } 2801 2802 if (unlikely(vcpu->cpu != cpu) || check_tsc_unstable()) { 2803 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 : 2804 rdtsc() - vcpu->arch.last_host_tsc; 2805 if (tsc_delta < 0) 2806 mark_tsc_unstable("KVM discovered backwards TSC"); 2807 2808 if (check_tsc_unstable()) { 2809 u64 offset = kvm_compute_tsc_offset(vcpu, 2810 vcpu->arch.last_guest_tsc); 2811 kvm_vcpu_write_tsc_offset(vcpu, offset); 2812 vcpu->arch.tsc_catchup = 1; 2813 } 2814 if (kvm_lapic_hv_timer_in_use(vcpu) && 2815 kvm_x86_ops->set_hv_timer(vcpu, 2816 kvm_get_lapic_target_expiration_tsc(vcpu))) 2817 kvm_lapic_switch_to_sw_timer(vcpu); 2818 /* 2819 * On a host with synchronized TSC, there is no need to update 2820 * kvmclock on vcpu->cpu migration 2821 */ 2822 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1) 2823 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu); 2824 if (vcpu->cpu != cpu) 2825 kvm_migrate_timers(vcpu); 2826 vcpu->cpu = cpu; 2827 } 2828 2829 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu); 2830 } 2831 2832 static void kvm_steal_time_set_preempted(struct kvm_vcpu *vcpu) 2833 { 2834 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED)) 2835 return; 2836 2837 vcpu->arch.st.steal.preempted = 1; 2838 2839 kvm_write_guest_offset_cached(vcpu->kvm, &vcpu->arch.st.stime, 2840 &vcpu->arch.st.steal.preempted, 2841 offsetof(struct kvm_steal_time, preempted), 2842 sizeof(vcpu->arch.st.steal.preempted)); 2843 } 2844 2845 void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu) 2846 { 2847 kvm_steal_time_set_preempted(vcpu); 2848 kvm_x86_ops->vcpu_put(vcpu); 2849 kvm_put_guest_fpu(vcpu); 2850 vcpu->arch.last_host_tsc = rdtsc(); 2851 } 2852 2853 static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu, 2854 struct kvm_lapic_state *s) 2855 { 2856 if (vcpu->arch.apicv_active) 2857 kvm_x86_ops->sync_pir_to_irr(vcpu); 2858 2859 return kvm_apic_get_state(vcpu, s); 2860 } 2861 2862 static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu, 2863 struct kvm_lapic_state *s) 2864 { 2865 int r; 2866 2867 r = kvm_apic_set_state(vcpu, s); 2868 if (r) 2869 return r; 2870 update_cr8_intercept(vcpu); 2871 2872 return 0; 2873 } 2874 2875 static int kvm_cpu_accept_dm_intr(struct kvm_vcpu *vcpu) 2876 { 2877 return (!lapic_in_kernel(vcpu) || 2878 kvm_apic_accept_pic_intr(vcpu)); 2879 } 2880 2881 /* 2882 * if userspace requested an interrupt window, check that the 2883 * interrupt window is open. 2884 * 2885 * No need to exit to userspace if we already have an interrupt queued. 2886 */ 2887 static int kvm_vcpu_ready_for_interrupt_injection(struct kvm_vcpu *vcpu) 2888 { 2889 return kvm_arch_interrupt_allowed(vcpu) && 2890 !kvm_cpu_has_interrupt(vcpu) && 2891 !kvm_event_needs_reinjection(vcpu) && 2892 kvm_cpu_accept_dm_intr(vcpu); 2893 } 2894 2895 static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu, 2896 struct kvm_interrupt *irq) 2897 { 2898 if (irq->irq >= KVM_NR_INTERRUPTS) 2899 return -EINVAL; 2900 2901 if (!irqchip_in_kernel(vcpu->kvm)) { 2902 kvm_queue_interrupt(vcpu, irq->irq, false); 2903 kvm_make_request(KVM_REQ_EVENT, vcpu); 2904 return 0; 2905 } 2906 2907 /* 2908 * With in-kernel LAPIC, we only use this to inject EXTINT, so 2909 * fail for in-kernel 8259. 2910 */ 2911 if (pic_in_kernel(vcpu->kvm)) 2912 return -ENXIO; 2913 2914 if (vcpu->arch.pending_external_vector != -1) 2915 return -EEXIST; 2916 2917 vcpu->arch.pending_external_vector = irq->irq; 2918 kvm_make_request(KVM_REQ_EVENT, vcpu); 2919 return 0; 2920 } 2921 2922 static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu) 2923 { 2924 kvm_inject_nmi(vcpu); 2925 2926 return 0; 2927 } 2928 2929 static int kvm_vcpu_ioctl_smi(struct kvm_vcpu *vcpu) 2930 { 2931 kvm_make_request(KVM_REQ_SMI, vcpu); 2932 2933 return 0; 2934 } 2935 2936 static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu, 2937 struct kvm_tpr_access_ctl *tac) 2938 { 2939 if (tac->flags) 2940 return -EINVAL; 2941 vcpu->arch.tpr_access_reporting = !!tac->enabled; 2942 return 0; 2943 } 2944 2945 static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu, 2946 u64 mcg_cap) 2947 { 2948 int r; 2949 unsigned bank_num = mcg_cap & 0xff, bank; 2950 2951 r = -EINVAL; 2952 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS) 2953 goto out; 2954 if (mcg_cap & ~(kvm_mce_cap_supported | 0xff | 0xff0000)) 2955 goto out; 2956 r = 0; 2957 vcpu->arch.mcg_cap = mcg_cap; 2958 /* Init IA32_MCG_CTL to all 1s */ 2959 if (mcg_cap & MCG_CTL_P) 2960 vcpu->arch.mcg_ctl = ~(u64)0; 2961 /* Init IA32_MCi_CTL to all 1s */ 2962 for (bank = 0; bank < bank_num; bank++) 2963 vcpu->arch.mce_banks[bank*4] = ~(u64)0; 2964 2965 if (kvm_x86_ops->setup_mce) 2966 kvm_x86_ops->setup_mce(vcpu); 2967 out: 2968 return r; 2969 } 2970 2971 static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu, 2972 struct kvm_x86_mce *mce) 2973 { 2974 u64 mcg_cap = vcpu->arch.mcg_cap; 2975 unsigned bank_num = mcg_cap & 0xff; 2976 u64 *banks = vcpu->arch.mce_banks; 2977 2978 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL)) 2979 return -EINVAL; 2980 /* 2981 * if IA32_MCG_CTL is not all 1s, the uncorrected error 2982 * reporting is disabled 2983 */ 2984 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) && 2985 vcpu->arch.mcg_ctl != ~(u64)0) 2986 return 0; 2987 banks += 4 * mce->bank; 2988 /* 2989 * if IA32_MCi_CTL is not all 1s, the uncorrected error 2990 * reporting is disabled for the bank 2991 */ 2992 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0) 2993 return 0; 2994 if (mce->status & MCI_STATUS_UC) { 2995 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) || 2996 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) { 2997 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); 2998 return 0; 2999 } 3000 if (banks[1] & MCI_STATUS_VAL) 3001 mce->status |= MCI_STATUS_OVER; 3002 banks[2] = mce->addr; 3003 banks[3] = mce->misc; 3004 vcpu->arch.mcg_status = mce->mcg_status; 3005 banks[1] = mce->status; 3006 kvm_queue_exception(vcpu, MC_VECTOR); 3007 } else if (!(banks[1] & MCI_STATUS_VAL) 3008 || !(banks[1] & MCI_STATUS_UC)) { 3009 if (banks[1] & MCI_STATUS_VAL) 3010 mce->status |= MCI_STATUS_OVER; 3011 banks[2] = mce->addr; 3012 banks[3] = mce->misc; 3013 banks[1] = mce->status; 3014 } else 3015 banks[1] |= MCI_STATUS_OVER; 3016 return 0; 3017 } 3018 3019 static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu, 3020 struct kvm_vcpu_events *events) 3021 { 3022 process_nmi(vcpu); 3023 events->exception.injected = 3024 vcpu->arch.exception.pending && 3025 !kvm_exception_is_soft(vcpu->arch.exception.nr); 3026 events->exception.nr = vcpu->arch.exception.nr; 3027 events->exception.has_error_code = vcpu->arch.exception.has_error_code; 3028 events->exception.pad = 0; 3029 events->exception.error_code = vcpu->arch.exception.error_code; 3030 3031 events->interrupt.injected = 3032 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft; 3033 events->interrupt.nr = vcpu->arch.interrupt.nr; 3034 events->interrupt.soft = 0; 3035 events->interrupt.shadow = kvm_x86_ops->get_interrupt_shadow(vcpu); 3036 3037 events->nmi.injected = vcpu->arch.nmi_injected; 3038 events->nmi.pending = vcpu->arch.nmi_pending != 0; 3039 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu); 3040 events->nmi.pad = 0; 3041 3042 events->sipi_vector = 0; /* never valid when reporting to user space */ 3043 3044 events->smi.smm = is_smm(vcpu); 3045 events->smi.pending = vcpu->arch.smi_pending; 3046 events->smi.smm_inside_nmi = 3047 !!(vcpu->arch.hflags & HF_SMM_INSIDE_NMI_MASK); 3048 events->smi.latched_init = kvm_lapic_latched_init(vcpu); 3049 3050 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING 3051 | KVM_VCPUEVENT_VALID_SHADOW 3052 | KVM_VCPUEVENT_VALID_SMM); 3053 memset(&events->reserved, 0, sizeof(events->reserved)); 3054 } 3055 3056 static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu, 3057 struct kvm_vcpu_events *events) 3058 { 3059 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING 3060 | KVM_VCPUEVENT_VALID_SIPI_VECTOR 3061 | KVM_VCPUEVENT_VALID_SHADOW 3062 | KVM_VCPUEVENT_VALID_SMM)) 3063 return -EINVAL; 3064 3065 if (events->exception.injected && 3066 (events->exception.nr > 31 || events->exception.nr == NMI_VECTOR)) 3067 return -EINVAL; 3068 3069 process_nmi(vcpu); 3070 vcpu->arch.exception.pending = events->exception.injected; 3071 vcpu->arch.exception.nr = events->exception.nr; 3072 vcpu->arch.exception.has_error_code = events->exception.has_error_code; 3073 vcpu->arch.exception.error_code = events->exception.error_code; 3074 3075 vcpu->arch.interrupt.pending = events->interrupt.injected; 3076 vcpu->arch.interrupt.nr = events->interrupt.nr; 3077 vcpu->arch.interrupt.soft = events->interrupt.soft; 3078 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW) 3079 kvm_x86_ops->set_interrupt_shadow(vcpu, 3080 events->interrupt.shadow); 3081 3082 vcpu->arch.nmi_injected = events->nmi.injected; 3083 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING) 3084 vcpu->arch.nmi_pending = events->nmi.pending; 3085 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked); 3086 3087 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR && 3088 lapic_in_kernel(vcpu)) 3089 vcpu->arch.apic->sipi_vector = events->sipi_vector; 3090 3091 if (events->flags & KVM_VCPUEVENT_VALID_SMM) { 3092 if (events->smi.smm) 3093 vcpu->arch.hflags |= HF_SMM_MASK; 3094 else 3095 vcpu->arch.hflags &= ~HF_SMM_MASK; 3096 vcpu->arch.smi_pending = events->smi.pending; 3097 if (events->smi.smm_inside_nmi) 3098 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK; 3099 else 3100 vcpu->arch.hflags &= ~HF_SMM_INSIDE_NMI_MASK; 3101 if (lapic_in_kernel(vcpu)) { 3102 if (events->smi.latched_init) 3103 set_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events); 3104 else 3105 clear_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events); 3106 } 3107 } 3108 3109 kvm_make_request(KVM_REQ_EVENT, vcpu); 3110 3111 return 0; 3112 } 3113 3114 static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu, 3115 struct kvm_debugregs *dbgregs) 3116 { 3117 unsigned long val; 3118 3119 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db)); 3120 kvm_get_dr(vcpu, 6, &val); 3121 dbgregs->dr6 = val; 3122 dbgregs->dr7 = vcpu->arch.dr7; 3123 dbgregs->flags = 0; 3124 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved)); 3125 } 3126 3127 static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu, 3128 struct kvm_debugregs *dbgregs) 3129 { 3130 if (dbgregs->flags) 3131 return -EINVAL; 3132 3133 if (dbgregs->dr6 & ~0xffffffffull) 3134 return -EINVAL; 3135 if (dbgregs->dr7 & ~0xffffffffull) 3136 return -EINVAL; 3137 3138 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db)); 3139 kvm_update_dr0123(vcpu); 3140 vcpu->arch.dr6 = dbgregs->dr6; 3141 kvm_update_dr6(vcpu); 3142 vcpu->arch.dr7 = dbgregs->dr7; 3143 kvm_update_dr7(vcpu); 3144 3145 return 0; 3146 } 3147 3148 #define XSTATE_COMPACTION_ENABLED (1ULL << 63) 3149 3150 static void fill_xsave(u8 *dest, struct kvm_vcpu *vcpu) 3151 { 3152 struct xregs_state *xsave = &vcpu->arch.guest_fpu.state.xsave; 3153 u64 xstate_bv = xsave->header.xfeatures; 3154 u64 valid; 3155 3156 /* 3157 * Copy legacy XSAVE area, to avoid complications with CPUID 3158 * leaves 0 and 1 in the loop below. 3159 */ 3160 memcpy(dest, xsave, XSAVE_HDR_OFFSET); 3161 3162 /* Set XSTATE_BV */ 3163 *(u64 *)(dest + XSAVE_HDR_OFFSET) = xstate_bv; 3164 3165 /* 3166 * Copy each region from the possibly compacted offset to the 3167 * non-compacted offset. 3168 */ 3169 valid = xstate_bv & ~XFEATURE_MASK_FPSSE; 3170 while (valid) { 3171 u64 feature = valid & -valid; 3172 int index = fls64(feature) - 1; 3173 void *src = get_xsave_addr(xsave, feature); 3174 3175 if (src) { 3176 u32 size, offset, ecx, edx; 3177 cpuid_count(XSTATE_CPUID, index, 3178 &size, &offset, &ecx, &edx); 3179 memcpy(dest + offset, src, size); 3180 } 3181 3182 valid -= feature; 3183 } 3184 } 3185 3186 static void load_xsave(struct kvm_vcpu *vcpu, u8 *src) 3187 { 3188 struct xregs_state *xsave = &vcpu->arch.guest_fpu.state.xsave; 3189 u64 xstate_bv = *(u64 *)(src + XSAVE_HDR_OFFSET); 3190 u64 valid; 3191 3192 /* 3193 * Copy legacy XSAVE area, to avoid complications with CPUID 3194 * leaves 0 and 1 in the loop below. 3195 */ 3196 memcpy(xsave, src, XSAVE_HDR_OFFSET); 3197 3198 /* Set XSTATE_BV and possibly XCOMP_BV. */ 3199 xsave->header.xfeatures = xstate_bv; 3200 if (boot_cpu_has(X86_FEATURE_XSAVES)) 3201 xsave->header.xcomp_bv = host_xcr0 | XSTATE_COMPACTION_ENABLED; 3202 3203 /* 3204 * Copy each region from the non-compacted offset to the 3205 * possibly compacted offset. 3206 */ 3207 valid = xstate_bv & ~XFEATURE_MASK_FPSSE; 3208 while (valid) { 3209 u64 feature = valid & -valid; 3210 int index = fls64(feature) - 1; 3211 void *dest = get_xsave_addr(xsave, feature); 3212 3213 if (dest) { 3214 u32 size, offset, ecx, edx; 3215 cpuid_count(XSTATE_CPUID, index, 3216 &size, &offset, &ecx, &edx); 3217 memcpy(dest, src + offset, size); 3218 } 3219 3220 valid -= feature; 3221 } 3222 } 3223 3224 static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu, 3225 struct kvm_xsave *guest_xsave) 3226 { 3227 if (boot_cpu_has(X86_FEATURE_XSAVE)) { 3228 memset(guest_xsave, 0, sizeof(struct kvm_xsave)); 3229 fill_xsave((u8 *) guest_xsave->region, vcpu); 3230 } else { 3231 memcpy(guest_xsave->region, 3232 &vcpu->arch.guest_fpu.state.fxsave, 3233 sizeof(struct fxregs_state)); 3234 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] = 3235 XFEATURE_MASK_FPSSE; 3236 } 3237 } 3238 3239 static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu, 3240 struct kvm_xsave *guest_xsave) 3241 { 3242 u64 xstate_bv = 3243 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)]; 3244 3245 if (boot_cpu_has(X86_FEATURE_XSAVE)) { 3246 /* 3247 * Here we allow setting states that are not present in 3248 * CPUID leaf 0xD, index 0, EDX:EAX. This is for compatibility 3249 * with old userspace. 3250 */ 3251 if (xstate_bv & ~kvm_supported_xcr0()) 3252 return -EINVAL; 3253 load_xsave(vcpu, (u8 *)guest_xsave->region); 3254 } else { 3255 if (xstate_bv & ~XFEATURE_MASK_FPSSE) 3256 return -EINVAL; 3257 memcpy(&vcpu->arch.guest_fpu.state.fxsave, 3258 guest_xsave->region, sizeof(struct fxregs_state)); 3259 } 3260 return 0; 3261 } 3262 3263 static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu, 3264 struct kvm_xcrs *guest_xcrs) 3265 { 3266 if (!boot_cpu_has(X86_FEATURE_XSAVE)) { 3267 guest_xcrs->nr_xcrs = 0; 3268 return; 3269 } 3270 3271 guest_xcrs->nr_xcrs = 1; 3272 guest_xcrs->flags = 0; 3273 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK; 3274 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0; 3275 } 3276 3277 static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu, 3278 struct kvm_xcrs *guest_xcrs) 3279 { 3280 int i, r = 0; 3281 3282 if (!boot_cpu_has(X86_FEATURE_XSAVE)) 3283 return -EINVAL; 3284 3285 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags) 3286 return -EINVAL; 3287 3288 for (i = 0; i < guest_xcrs->nr_xcrs; i++) 3289 /* Only support XCR0 currently */ 3290 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) { 3291 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK, 3292 guest_xcrs->xcrs[i].value); 3293 break; 3294 } 3295 if (r) 3296 r = -EINVAL; 3297 return r; 3298 } 3299 3300 /* 3301 * kvm_set_guest_paused() indicates to the guest kernel that it has been 3302 * stopped by the hypervisor. This function will be called from the host only. 3303 * EINVAL is returned when the host attempts to set the flag for a guest that 3304 * does not support pv clocks. 3305 */ 3306 static int kvm_set_guest_paused(struct kvm_vcpu *vcpu) 3307 { 3308 if (!vcpu->arch.pv_time_enabled) 3309 return -EINVAL; 3310 vcpu->arch.pvclock_set_guest_stopped_request = true; 3311 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 3312 return 0; 3313 } 3314 3315 static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu, 3316 struct kvm_enable_cap *cap) 3317 { 3318 if (cap->flags) 3319 return -EINVAL; 3320 3321 switch (cap->cap) { 3322 case KVM_CAP_HYPERV_SYNIC: 3323 return kvm_hv_activate_synic(vcpu); 3324 default: 3325 return -EINVAL; 3326 } 3327 } 3328 3329 long kvm_arch_vcpu_ioctl(struct file *filp, 3330 unsigned int ioctl, unsigned long arg) 3331 { 3332 struct kvm_vcpu *vcpu = filp->private_data; 3333 void __user *argp = (void __user *)arg; 3334 int r; 3335 union { 3336 struct kvm_lapic_state *lapic; 3337 struct kvm_xsave *xsave; 3338 struct kvm_xcrs *xcrs; 3339 void *buffer; 3340 } u; 3341 3342 u.buffer = NULL; 3343 switch (ioctl) { 3344 case KVM_GET_LAPIC: { 3345 r = -EINVAL; 3346 if (!lapic_in_kernel(vcpu)) 3347 goto out; 3348 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL); 3349 3350 r = -ENOMEM; 3351 if (!u.lapic) 3352 goto out; 3353 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic); 3354 if (r) 3355 goto out; 3356 r = -EFAULT; 3357 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state))) 3358 goto out; 3359 r = 0; 3360 break; 3361 } 3362 case KVM_SET_LAPIC: { 3363 r = -EINVAL; 3364 if (!lapic_in_kernel(vcpu)) 3365 goto out; 3366 u.lapic = memdup_user(argp, sizeof(*u.lapic)); 3367 if (IS_ERR(u.lapic)) 3368 return PTR_ERR(u.lapic); 3369 3370 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic); 3371 break; 3372 } 3373 case KVM_INTERRUPT: { 3374 struct kvm_interrupt irq; 3375 3376 r = -EFAULT; 3377 if (copy_from_user(&irq, argp, sizeof irq)) 3378 goto out; 3379 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq); 3380 break; 3381 } 3382 case KVM_NMI: { 3383 r = kvm_vcpu_ioctl_nmi(vcpu); 3384 break; 3385 } 3386 case KVM_SMI: { 3387 r = kvm_vcpu_ioctl_smi(vcpu); 3388 break; 3389 } 3390 case KVM_SET_CPUID: { 3391 struct kvm_cpuid __user *cpuid_arg = argp; 3392 struct kvm_cpuid cpuid; 3393 3394 r = -EFAULT; 3395 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid)) 3396 goto out; 3397 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries); 3398 break; 3399 } 3400 case KVM_SET_CPUID2: { 3401 struct kvm_cpuid2 __user *cpuid_arg = argp; 3402 struct kvm_cpuid2 cpuid; 3403 3404 r = -EFAULT; 3405 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid)) 3406 goto out; 3407 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid, 3408 cpuid_arg->entries); 3409 break; 3410 } 3411 case KVM_GET_CPUID2: { 3412 struct kvm_cpuid2 __user *cpuid_arg = argp; 3413 struct kvm_cpuid2 cpuid; 3414 3415 r = -EFAULT; 3416 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid)) 3417 goto out; 3418 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid, 3419 cpuid_arg->entries); 3420 if (r) 3421 goto out; 3422 r = -EFAULT; 3423 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid)) 3424 goto out; 3425 r = 0; 3426 break; 3427 } 3428 case KVM_GET_MSRS: 3429 r = msr_io(vcpu, argp, do_get_msr, 1); 3430 break; 3431 case KVM_SET_MSRS: 3432 r = msr_io(vcpu, argp, do_set_msr, 0); 3433 break; 3434 case KVM_TPR_ACCESS_REPORTING: { 3435 struct kvm_tpr_access_ctl tac; 3436 3437 r = -EFAULT; 3438 if (copy_from_user(&tac, argp, sizeof tac)) 3439 goto out; 3440 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac); 3441 if (r) 3442 goto out; 3443 r = -EFAULT; 3444 if (copy_to_user(argp, &tac, sizeof tac)) 3445 goto out; 3446 r = 0; 3447 break; 3448 }; 3449 case KVM_SET_VAPIC_ADDR: { 3450 struct kvm_vapic_addr va; 3451 int idx; 3452 3453 r = -EINVAL; 3454 if (!lapic_in_kernel(vcpu)) 3455 goto out; 3456 r = -EFAULT; 3457 if (copy_from_user(&va, argp, sizeof va)) 3458 goto out; 3459 idx = srcu_read_lock(&vcpu->kvm->srcu); 3460 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr); 3461 srcu_read_unlock(&vcpu->kvm->srcu, idx); 3462 break; 3463 } 3464 case KVM_X86_SETUP_MCE: { 3465 u64 mcg_cap; 3466 3467 r = -EFAULT; 3468 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap)) 3469 goto out; 3470 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap); 3471 break; 3472 } 3473 case KVM_X86_SET_MCE: { 3474 struct kvm_x86_mce mce; 3475 3476 r = -EFAULT; 3477 if (copy_from_user(&mce, argp, sizeof mce)) 3478 goto out; 3479 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce); 3480 break; 3481 } 3482 case KVM_GET_VCPU_EVENTS: { 3483 struct kvm_vcpu_events events; 3484 3485 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events); 3486 3487 r = -EFAULT; 3488 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events))) 3489 break; 3490 r = 0; 3491 break; 3492 } 3493 case KVM_SET_VCPU_EVENTS: { 3494 struct kvm_vcpu_events events; 3495 3496 r = -EFAULT; 3497 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events))) 3498 break; 3499 3500 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events); 3501 break; 3502 } 3503 case KVM_GET_DEBUGREGS: { 3504 struct kvm_debugregs dbgregs; 3505 3506 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs); 3507 3508 r = -EFAULT; 3509 if (copy_to_user(argp, &dbgregs, 3510 sizeof(struct kvm_debugregs))) 3511 break; 3512 r = 0; 3513 break; 3514 } 3515 case KVM_SET_DEBUGREGS: { 3516 struct kvm_debugregs dbgregs; 3517 3518 r = -EFAULT; 3519 if (copy_from_user(&dbgregs, argp, 3520 sizeof(struct kvm_debugregs))) 3521 break; 3522 3523 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs); 3524 break; 3525 } 3526 case KVM_GET_XSAVE: { 3527 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL); 3528 r = -ENOMEM; 3529 if (!u.xsave) 3530 break; 3531 3532 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave); 3533 3534 r = -EFAULT; 3535 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave))) 3536 break; 3537 r = 0; 3538 break; 3539 } 3540 case KVM_SET_XSAVE: { 3541 u.xsave = memdup_user(argp, sizeof(*u.xsave)); 3542 if (IS_ERR(u.xsave)) 3543 return PTR_ERR(u.xsave); 3544 3545 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave); 3546 break; 3547 } 3548 case KVM_GET_XCRS: { 3549 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL); 3550 r = -ENOMEM; 3551 if (!u.xcrs) 3552 break; 3553 3554 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs); 3555 3556 r = -EFAULT; 3557 if (copy_to_user(argp, u.xcrs, 3558 sizeof(struct kvm_xcrs))) 3559 break; 3560 r = 0; 3561 break; 3562 } 3563 case KVM_SET_XCRS: { 3564 u.xcrs = memdup_user(argp, sizeof(*u.xcrs)); 3565 if (IS_ERR(u.xcrs)) 3566 return PTR_ERR(u.xcrs); 3567 3568 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs); 3569 break; 3570 } 3571 case KVM_SET_TSC_KHZ: { 3572 u32 user_tsc_khz; 3573 3574 r = -EINVAL; 3575 user_tsc_khz = (u32)arg; 3576 3577 if (user_tsc_khz >= kvm_max_guest_tsc_khz) 3578 goto out; 3579 3580 if (user_tsc_khz == 0) 3581 user_tsc_khz = tsc_khz; 3582 3583 if (!kvm_set_tsc_khz(vcpu, user_tsc_khz)) 3584 r = 0; 3585 3586 goto out; 3587 } 3588 case KVM_GET_TSC_KHZ: { 3589 r = vcpu->arch.virtual_tsc_khz; 3590 goto out; 3591 } 3592 case KVM_KVMCLOCK_CTRL: { 3593 r = kvm_set_guest_paused(vcpu); 3594 goto out; 3595 } 3596 case KVM_ENABLE_CAP: { 3597 struct kvm_enable_cap cap; 3598 3599 r = -EFAULT; 3600 if (copy_from_user(&cap, argp, sizeof(cap))) 3601 goto out; 3602 r = kvm_vcpu_ioctl_enable_cap(vcpu, &cap); 3603 break; 3604 } 3605 default: 3606 r = -EINVAL; 3607 } 3608 out: 3609 kfree(u.buffer); 3610 return r; 3611 } 3612 3613 int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf) 3614 { 3615 return VM_FAULT_SIGBUS; 3616 } 3617 3618 static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr) 3619 { 3620 int ret; 3621 3622 if (addr > (unsigned int)(-3 * PAGE_SIZE)) 3623 return -EINVAL; 3624 ret = kvm_x86_ops->set_tss_addr(kvm, addr); 3625 return ret; 3626 } 3627 3628 static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm, 3629 u64 ident_addr) 3630 { 3631 kvm->arch.ept_identity_map_addr = ident_addr; 3632 return 0; 3633 } 3634 3635 static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm, 3636 u32 kvm_nr_mmu_pages) 3637 { 3638 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES) 3639 return -EINVAL; 3640 3641 mutex_lock(&kvm->slots_lock); 3642 3643 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages); 3644 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages; 3645 3646 mutex_unlock(&kvm->slots_lock); 3647 return 0; 3648 } 3649 3650 static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm) 3651 { 3652 return kvm->arch.n_max_mmu_pages; 3653 } 3654 3655 static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip) 3656 { 3657 int r; 3658 3659 r = 0; 3660 switch (chip->chip_id) { 3661 case KVM_IRQCHIP_PIC_MASTER: 3662 memcpy(&chip->chip.pic, 3663 &pic_irqchip(kvm)->pics[0], 3664 sizeof(struct kvm_pic_state)); 3665 break; 3666 case KVM_IRQCHIP_PIC_SLAVE: 3667 memcpy(&chip->chip.pic, 3668 &pic_irqchip(kvm)->pics[1], 3669 sizeof(struct kvm_pic_state)); 3670 break; 3671 case KVM_IRQCHIP_IOAPIC: 3672 r = kvm_get_ioapic(kvm, &chip->chip.ioapic); 3673 break; 3674 default: 3675 r = -EINVAL; 3676 break; 3677 } 3678 return r; 3679 } 3680 3681 static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip) 3682 { 3683 int r; 3684 3685 r = 0; 3686 switch (chip->chip_id) { 3687 case KVM_IRQCHIP_PIC_MASTER: 3688 spin_lock(&pic_irqchip(kvm)->lock); 3689 memcpy(&pic_irqchip(kvm)->pics[0], 3690 &chip->chip.pic, 3691 sizeof(struct kvm_pic_state)); 3692 spin_unlock(&pic_irqchip(kvm)->lock); 3693 break; 3694 case KVM_IRQCHIP_PIC_SLAVE: 3695 spin_lock(&pic_irqchip(kvm)->lock); 3696 memcpy(&pic_irqchip(kvm)->pics[1], 3697 &chip->chip.pic, 3698 sizeof(struct kvm_pic_state)); 3699 spin_unlock(&pic_irqchip(kvm)->lock); 3700 break; 3701 case KVM_IRQCHIP_IOAPIC: 3702 r = kvm_set_ioapic(kvm, &chip->chip.ioapic); 3703 break; 3704 default: 3705 r = -EINVAL; 3706 break; 3707 } 3708 kvm_pic_update_irq(pic_irqchip(kvm)); 3709 return r; 3710 } 3711 3712 static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps) 3713 { 3714 struct kvm_kpit_state *kps = &kvm->arch.vpit->pit_state; 3715 3716 BUILD_BUG_ON(sizeof(*ps) != sizeof(kps->channels)); 3717 3718 mutex_lock(&kps->lock); 3719 memcpy(ps, &kps->channels, sizeof(*ps)); 3720 mutex_unlock(&kps->lock); 3721 return 0; 3722 } 3723 3724 static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps) 3725 { 3726 int i; 3727 struct kvm_pit *pit = kvm->arch.vpit; 3728 3729 mutex_lock(&pit->pit_state.lock); 3730 memcpy(&pit->pit_state.channels, ps, sizeof(*ps)); 3731 for (i = 0; i < 3; i++) 3732 kvm_pit_load_count(pit, i, ps->channels[i].count, 0); 3733 mutex_unlock(&pit->pit_state.lock); 3734 return 0; 3735 } 3736 3737 static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps) 3738 { 3739 mutex_lock(&kvm->arch.vpit->pit_state.lock); 3740 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels, 3741 sizeof(ps->channels)); 3742 ps->flags = kvm->arch.vpit->pit_state.flags; 3743 mutex_unlock(&kvm->arch.vpit->pit_state.lock); 3744 memset(&ps->reserved, 0, sizeof(ps->reserved)); 3745 return 0; 3746 } 3747 3748 static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps) 3749 { 3750 int start = 0; 3751 int i; 3752 u32 prev_legacy, cur_legacy; 3753 struct kvm_pit *pit = kvm->arch.vpit; 3754 3755 mutex_lock(&pit->pit_state.lock); 3756 prev_legacy = pit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY; 3757 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY; 3758 if (!prev_legacy && cur_legacy) 3759 start = 1; 3760 memcpy(&pit->pit_state.channels, &ps->channels, 3761 sizeof(pit->pit_state.channels)); 3762 pit->pit_state.flags = ps->flags; 3763 for (i = 0; i < 3; i++) 3764 kvm_pit_load_count(pit, i, pit->pit_state.channels[i].count, 3765 start && i == 0); 3766 mutex_unlock(&pit->pit_state.lock); 3767 return 0; 3768 } 3769 3770 static int kvm_vm_ioctl_reinject(struct kvm *kvm, 3771 struct kvm_reinject_control *control) 3772 { 3773 struct kvm_pit *pit = kvm->arch.vpit; 3774 3775 if (!pit) 3776 return -ENXIO; 3777 3778 /* pit->pit_state.lock was overloaded to prevent userspace from getting 3779 * an inconsistent state after running multiple KVM_REINJECT_CONTROL 3780 * ioctls in parallel. Use a separate lock if that ioctl isn't rare. 3781 */ 3782 mutex_lock(&pit->pit_state.lock); 3783 kvm_pit_set_reinject(pit, control->pit_reinject); 3784 mutex_unlock(&pit->pit_state.lock); 3785 3786 return 0; 3787 } 3788 3789 /** 3790 * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot 3791 * @kvm: kvm instance 3792 * @log: slot id and address to which we copy the log 3793 * 3794 * Steps 1-4 below provide general overview of dirty page logging. See 3795 * kvm_get_dirty_log_protect() function description for additional details. 3796 * 3797 * We call kvm_get_dirty_log_protect() to handle steps 1-3, upon return we 3798 * always flush the TLB (step 4) even if previous step failed and the dirty 3799 * bitmap may be corrupt. Regardless of previous outcome the KVM logging API 3800 * does not preclude user space subsequent dirty log read. Flushing TLB ensures 3801 * writes will be marked dirty for next log read. 3802 * 3803 * 1. Take a snapshot of the bit and clear it if needed. 3804 * 2. Write protect the corresponding page. 3805 * 3. Copy the snapshot to the userspace. 3806 * 4. Flush TLB's if needed. 3807 */ 3808 int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log) 3809 { 3810 bool is_dirty = false; 3811 int r; 3812 3813 mutex_lock(&kvm->slots_lock); 3814 3815 /* 3816 * Flush potentially hardware-cached dirty pages to dirty_bitmap. 3817 */ 3818 if (kvm_x86_ops->flush_log_dirty) 3819 kvm_x86_ops->flush_log_dirty(kvm); 3820 3821 r = kvm_get_dirty_log_protect(kvm, log, &is_dirty); 3822 3823 /* 3824 * All the TLBs can be flushed out of mmu lock, see the comments in 3825 * kvm_mmu_slot_remove_write_access(). 3826 */ 3827 lockdep_assert_held(&kvm->slots_lock); 3828 if (is_dirty) 3829 kvm_flush_remote_tlbs(kvm); 3830 3831 mutex_unlock(&kvm->slots_lock); 3832 return r; 3833 } 3834 3835 int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event, 3836 bool line_status) 3837 { 3838 if (!irqchip_in_kernel(kvm)) 3839 return -ENXIO; 3840 3841 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID, 3842 irq_event->irq, irq_event->level, 3843 line_status); 3844 return 0; 3845 } 3846 3847 static int kvm_vm_ioctl_enable_cap(struct kvm *kvm, 3848 struct kvm_enable_cap *cap) 3849 { 3850 int r; 3851 3852 if (cap->flags) 3853 return -EINVAL; 3854 3855 switch (cap->cap) { 3856 case KVM_CAP_DISABLE_QUIRKS: 3857 kvm->arch.disabled_quirks = cap->args[0]; 3858 r = 0; 3859 break; 3860 case KVM_CAP_SPLIT_IRQCHIP: { 3861 mutex_lock(&kvm->lock); 3862 r = -EINVAL; 3863 if (cap->args[0] > MAX_NR_RESERVED_IOAPIC_PINS) 3864 goto split_irqchip_unlock; 3865 r = -EEXIST; 3866 if (irqchip_in_kernel(kvm)) 3867 goto split_irqchip_unlock; 3868 if (kvm->created_vcpus) 3869 goto split_irqchip_unlock; 3870 r = kvm_setup_empty_irq_routing(kvm); 3871 if (r) 3872 goto split_irqchip_unlock; 3873 /* Pairs with irqchip_in_kernel. */ 3874 smp_wmb(); 3875 kvm->arch.irqchip_split = true; 3876 kvm->arch.nr_reserved_ioapic_pins = cap->args[0]; 3877 r = 0; 3878 split_irqchip_unlock: 3879 mutex_unlock(&kvm->lock); 3880 break; 3881 } 3882 case KVM_CAP_X2APIC_API: 3883 r = -EINVAL; 3884 if (cap->args[0] & ~KVM_X2APIC_API_VALID_FLAGS) 3885 break; 3886 3887 if (cap->args[0] & KVM_X2APIC_API_USE_32BIT_IDS) 3888 kvm->arch.x2apic_format = true; 3889 if (cap->args[0] & KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK) 3890 kvm->arch.x2apic_broadcast_quirk_disabled = true; 3891 3892 r = 0; 3893 break; 3894 default: 3895 r = -EINVAL; 3896 break; 3897 } 3898 return r; 3899 } 3900 3901 long kvm_arch_vm_ioctl(struct file *filp, 3902 unsigned int ioctl, unsigned long arg) 3903 { 3904 struct kvm *kvm = filp->private_data; 3905 void __user *argp = (void __user *)arg; 3906 int r = -ENOTTY; 3907 /* 3908 * This union makes it completely explicit to gcc-3.x 3909 * that these two variables' stack usage should be 3910 * combined, not added together. 3911 */ 3912 union { 3913 struct kvm_pit_state ps; 3914 struct kvm_pit_state2 ps2; 3915 struct kvm_pit_config pit_config; 3916 } u; 3917 3918 switch (ioctl) { 3919 case KVM_SET_TSS_ADDR: 3920 r = kvm_vm_ioctl_set_tss_addr(kvm, arg); 3921 break; 3922 case KVM_SET_IDENTITY_MAP_ADDR: { 3923 u64 ident_addr; 3924 3925 r = -EFAULT; 3926 if (copy_from_user(&ident_addr, argp, sizeof ident_addr)) 3927 goto out; 3928 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr); 3929 break; 3930 } 3931 case KVM_SET_NR_MMU_PAGES: 3932 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg); 3933 break; 3934 case KVM_GET_NR_MMU_PAGES: 3935 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm); 3936 break; 3937 case KVM_CREATE_IRQCHIP: { 3938 struct kvm_pic *vpic; 3939 3940 mutex_lock(&kvm->lock); 3941 r = -EEXIST; 3942 if (kvm->arch.vpic) 3943 goto create_irqchip_unlock; 3944 r = -EINVAL; 3945 if (kvm->created_vcpus) 3946 goto create_irqchip_unlock; 3947 r = -ENOMEM; 3948 vpic = kvm_create_pic(kvm); 3949 if (vpic) { 3950 r = kvm_ioapic_init(kvm); 3951 if (r) { 3952 mutex_lock(&kvm->slots_lock); 3953 kvm_destroy_pic(vpic); 3954 mutex_unlock(&kvm->slots_lock); 3955 goto create_irqchip_unlock; 3956 } 3957 } else 3958 goto create_irqchip_unlock; 3959 r = kvm_setup_default_irq_routing(kvm); 3960 if (r) { 3961 mutex_lock(&kvm->slots_lock); 3962 mutex_lock(&kvm->irq_lock); 3963 kvm_ioapic_destroy(kvm); 3964 kvm_destroy_pic(vpic); 3965 mutex_unlock(&kvm->irq_lock); 3966 mutex_unlock(&kvm->slots_lock); 3967 goto create_irqchip_unlock; 3968 } 3969 /* Write kvm->irq_routing before kvm->arch.vpic. */ 3970 smp_wmb(); 3971 kvm->arch.vpic = vpic; 3972 create_irqchip_unlock: 3973 mutex_unlock(&kvm->lock); 3974 break; 3975 } 3976 case KVM_CREATE_PIT: 3977 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY; 3978 goto create_pit; 3979 case KVM_CREATE_PIT2: 3980 r = -EFAULT; 3981 if (copy_from_user(&u.pit_config, argp, 3982 sizeof(struct kvm_pit_config))) 3983 goto out; 3984 create_pit: 3985 mutex_lock(&kvm->lock); 3986 r = -EEXIST; 3987 if (kvm->arch.vpit) 3988 goto create_pit_unlock; 3989 r = -ENOMEM; 3990 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags); 3991 if (kvm->arch.vpit) 3992 r = 0; 3993 create_pit_unlock: 3994 mutex_unlock(&kvm->lock); 3995 break; 3996 case KVM_GET_IRQCHIP: { 3997 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */ 3998 struct kvm_irqchip *chip; 3999 4000 chip = memdup_user(argp, sizeof(*chip)); 4001 if (IS_ERR(chip)) { 4002 r = PTR_ERR(chip); 4003 goto out; 4004 } 4005 4006 r = -ENXIO; 4007 if (!irqchip_in_kernel(kvm) || irqchip_split(kvm)) 4008 goto get_irqchip_out; 4009 r = kvm_vm_ioctl_get_irqchip(kvm, chip); 4010 if (r) 4011 goto get_irqchip_out; 4012 r = -EFAULT; 4013 if (copy_to_user(argp, chip, sizeof *chip)) 4014 goto get_irqchip_out; 4015 r = 0; 4016 get_irqchip_out: 4017 kfree(chip); 4018 break; 4019 } 4020 case KVM_SET_IRQCHIP: { 4021 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */ 4022 struct kvm_irqchip *chip; 4023 4024 chip = memdup_user(argp, sizeof(*chip)); 4025 if (IS_ERR(chip)) { 4026 r = PTR_ERR(chip); 4027 goto out; 4028 } 4029 4030 r = -ENXIO; 4031 if (!irqchip_in_kernel(kvm) || irqchip_split(kvm)) 4032 goto set_irqchip_out; 4033 r = kvm_vm_ioctl_set_irqchip(kvm, chip); 4034 if (r) 4035 goto set_irqchip_out; 4036 r = 0; 4037 set_irqchip_out: 4038 kfree(chip); 4039 break; 4040 } 4041 case KVM_GET_PIT: { 4042 r = -EFAULT; 4043 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state))) 4044 goto out; 4045 r = -ENXIO; 4046 if (!kvm->arch.vpit) 4047 goto out; 4048 r = kvm_vm_ioctl_get_pit(kvm, &u.ps); 4049 if (r) 4050 goto out; 4051 r = -EFAULT; 4052 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state))) 4053 goto out; 4054 r = 0; 4055 break; 4056 } 4057 case KVM_SET_PIT: { 4058 r = -EFAULT; 4059 if (copy_from_user(&u.ps, argp, sizeof u.ps)) 4060 goto out; 4061 r = -ENXIO; 4062 if (!kvm->arch.vpit) 4063 goto out; 4064 r = kvm_vm_ioctl_set_pit(kvm, &u.ps); 4065 break; 4066 } 4067 case KVM_GET_PIT2: { 4068 r = -ENXIO; 4069 if (!kvm->arch.vpit) 4070 goto out; 4071 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2); 4072 if (r) 4073 goto out; 4074 r = -EFAULT; 4075 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2))) 4076 goto out; 4077 r = 0; 4078 break; 4079 } 4080 case KVM_SET_PIT2: { 4081 r = -EFAULT; 4082 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2))) 4083 goto out; 4084 r = -ENXIO; 4085 if (!kvm->arch.vpit) 4086 goto out; 4087 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2); 4088 break; 4089 } 4090 case KVM_REINJECT_CONTROL: { 4091 struct kvm_reinject_control control; 4092 r = -EFAULT; 4093 if (copy_from_user(&control, argp, sizeof(control))) 4094 goto out; 4095 r = kvm_vm_ioctl_reinject(kvm, &control); 4096 break; 4097 } 4098 case KVM_SET_BOOT_CPU_ID: 4099 r = 0; 4100 mutex_lock(&kvm->lock); 4101 if (kvm->created_vcpus) 4102 r = -EBUSY; 4103 else 4104 kvm->arch.bsp_vcpu_id = arg; 4105 mutex_unlock(&kvm->lock); 4106 break; 4107 case KVM_XEN_HVM_CONFIG: { 4108 r = -EFAULT; 4109 if (copy_from_user(&kvm->arch.xen_hvm_config, argp, 4110 sizeof(struct kvm_xen_hvm_config))) 4111 goto out; 4112 r = -EINVAL; 4113 if (kvm->arch.xen_hvm_config.flags) 4114 goto out; 4115 r = 0; 4116 break; 4117 } 4118 case KVM_SET_CLOCK: { 4119 struct kvm_clock_data user_ns; 4120 u64 now_ns; 4121 4122 r = -EFAULT; 4123 if (copy_from_user(&user_ns, argp, sizeof(user_ns))) 4124 goto out; 4125 4126 r = -EINVAL; 4127 if (user_ns.flags) 4128 goto out; 4129 4130 r = 0; 4131 local_irq_disable(); 4132 now_ns = __get_kvmclock_ns(kvm); 4133 kvm->arch.kvmclock_offset += user_ns.clock - now_ns; 4134 local_irq_enable(); 4135 kvm_gen_update_masterclock(kvm); 4136 break; 4137 } 4138 case KVM_GET_CLOCK: { 4139 struct kvm_clock_data user_ns; 4140 u64 now_ns; 4141 4142 local_irq_disable(); 4143 now_ns = __get_kvmclock_ns(kvm); 4144 user_ns.clock = now_ns; 4145 user_ns.flags = kvm->arch.use_master_clock ? KVM_CLOCK_TSC_STABLE : 0; 4146 local_irq_enable(); 4147 memset(&user_ns.pad, 0, sizeof(user_ns.pad)); 4148 4149 r = -EFAULT; 4150 if (copy_to_user(argp, &user_ns, sizeof(user_ns))) 4151 goto out; 4152 r = 0; 4153 break; 4154 } 4155 case KVM_ENABLE_CAP: { 4156 struct kvm_enable_cap cap; 4157 4158 r = -EFAULT; 4159 if (copy_from_user(&cap, argp, sizeof(cap))) 4160 goto out; 4161 r = kvm_vm_ioctl_enable_cap(kvm, &cap); 4162 break; 4163 } 4164 default: 4165 r = kvm_vm_ioctl_assigned_device(kvm, ioctl, arg); 4166 } 4167 out: 4168 return r; 4169 } 4170 4171 static void kvm_init_msr_list(void) 4172 { 4173 u32 dummy[2]; 4174 unsigned i, j; 4175 4176 for (i = j = 0; i < ARRAY_SIZE(msrs_to_save); i++) { 4177 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0) 4178 continue; 4179 4180 /* 4181 * Even MSRs that are valid in the host may not be exposed 4182 * to the guests in some cases. 4183 */ 4184 switch (msrs_to_save[i]) { 4185 case MSR_IA32_BNDCFGS: 4186 if (!kvm_x86_ops->mpx_supported()) 4187 continue; 4188 break; 4189 case MSR_TSC_AUX: 4190 if (!kvm_x86_ops->rdtscp_supported()) 4191 continue; 4192 break; 4193 default: 4194 break; 4195 } 4196 4197 if (j < i) 4198 msrs_to_save[j] = msrs_to_save[i]; 4199 j++; 4200 } 4201 num_msrs_to_save = j; 4202 4203 for (i = j = 0; i < ARRAY_SIZE(emulated_msrs); i++) { 4204 switch (emulated_msrs[i]) { 4205 case MSR_IA32_SMBASE: 4206 if (!kvm_x86_ops->cpu_has_high_real_mode_segbase()) 4207 continue; 4208 break; 4209 default: 4210 break; 4211 } 4212 4213 if (j < i) 4214 emulated_msrs[j] = emulated_msrs[i]; 4215 j++; 4216 } 4217 num_emulated_msrs = j; 4218 } 4219 4220 static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len, 4221 const void *v) 4222 { 4223 int handled = 0; 4224 int n; 4225 4226 do { 4227 n = min(len, 8); 4228 if (!(lapic_in_kernel(vcpu) && 4229 !kvm_iodevice_write(vcpu, &vcpu->arch.apic->dev, addr, n, v)) 4230 && kvm_io_bus_write(vcpu, KVM_MMIO_BUS, addr, n, v)) 4231 break; 4232 handled += n; 4233 addr += n; 4234 len -= n; 4235 v += n; 4236 } while (len); 4237 4238 return handled; 4239 } 4240 4241 static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v) 4242 { 4243 int handled = 0; 4244 int n; 4245 4246 do { 4247 n = min(len, 8); 4248 if (!(lapic_in_kernel(vcpu) && 4249 !kvm_iodevice_read(vcpu, &vcpu->arch.apic->dev, 4250 addr, n, v)) 4251 && kvm_io_bus_read(vcpu, KVM_MMIO_BUS, addr, n, v)) 4252 break; 4253 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, *(u64 *)v); 4254 handled += n; 4255 addr += n; 4256 len -= n; 4257 v += n; 4258 } while (len); 4259 4260 return handled; 4261 } 4262 4263 static void kvm_set_segment(struct kvm_vcpu *vcpu, 4264 struct kvm_segment *var, int seg) 4265 { 4266 kvm_x86_ops->set_segment(vcpu, var, seg); 4267 } 4268 4269 void kvm_get_segment(struct kvm_vcpu *vcpu, 4270 struct kvm_segment *var, int seg) 4271 { 4272 kvm_x86_ops->get_segment(vcpu, var, seg); 4273 } 4274 4275 gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access, 4276 struct x86_exception *exception) 4277 { 4278 gpa_t t_gpa; 4279 4280 BUG_ON(!mmu_is_nested(vcpu)); 4281 4282 /* NPT walks are always user-walks */ 4283 access |= PFERR_USER_MASK; 4284 t_gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, exception); 4285 4286 return t_gpa; 4287 } 4288 4289 gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva, 4290 struct x86_exception *exception) 4291 { 4292 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0; 4293 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception); 4294 } 4295 4296 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva, 4297 struct x86_exception *exception) 4298 { 4299 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0; 4300 access |= PFERR_FETCH_MASK; 4301 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception); 4302 } 4303 4304 gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva, 4305 struct x86_exception *exception) 4306 { 4307 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0; 4308 access |= PFERR_WRITE_MASK; 4309 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception); 4310 } 4311 4312 /* uses this to access any guest's mapped memory without checking CPL */ 4313 gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva, 4314 struct x86_exception *exception) 4315 { 4316 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception); 4317 } 4318 4319 static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes, 4320 struct kvm_vcpu *vcpu, u32 access, 4321 struct x86_exception *exception) 4322 { 4323 void *data = val; 4324 int r = X86EMUL_CONTINUE; 4325 4326 while (bytes) { 4327 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access, 4328 exception); 4329 unsigned offset = addr & (PAGE_SIZE-1); 4330 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset); 4331 int ret; 4332 4333 if (gpa == UNMAPPED_GVA) 4334 return X86EMUL_PROPAGATE_FAULT; 4335 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, data, 4336 offset, toread); 4337 if (ret < 0) { 4338 r = X86EMUL_IO_NEEDED; 4339 goto out; 4340 } 4341 4342 bytes -= toread; 4343 data += toread; 4344 addr += toread; 4345 } 4346 out: 4347 return r; 4348 } 4349 4350 /* used for instruction fetching */ 4351 static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt, 4352 gva_t addr, void *val, unsigned int bytes, 4353 struct x86_exception *exception) 4354 { 4355 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 4356 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0; 4357 unsigned offset; 4358 int ret; 4359 4360 /* Inline kvm_read_guest_virt_helper for speed. */ 4361 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access|PFERR_FETCH_MASK, 4362 exception); 4363 if (unlikely(gpa == UNMAPPED_GVA)) 4364 return X86EMUL_PROPAGATE_FAULT; 4365 4366 offset = addr & (PAGE_SIZE-1); 4367 if (WARN_ON(offset + bytes > PAGE_SIZE)) 4368 bytes = (unsigned)PAGE_SIZE - offset; 4369 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, val, 4370 offset, bytes); 4371 if (unlikely(ret < 0)) 4372 return X86EMUL_IO_NEEDED; 4373 4374 return X86EMUL_CONTINUE; 4375 } 4376 4377 int kvm_read_guest_virt(struct x86_emulate_ctxt *ctxt, 4378 gva_t addr, void *val, unsigned int bytes, 4379 struct x86_exception *exception) 4380 { 4381 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 4382 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0; 4383 4384 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access, 4385 exception); 4386 } 4387 EXPORT_SYMBOL_GPL(kvm_read_guest_virt); 4388 4389 static int kvm_read_guest_virt_system(struct x86_emulate_ctxt *ctxt, 4390 gva_t addr, void *val, unsigned int bytes, 4391 struct x86_exception *exception) 4392 { 4393 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 4394 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, exception); 4395 } 4396 4397 static int kvm_read_guest_phys_system(struct x86_emulate_ctxt *ctxt, 4398 unsigned long addr, void *val, unsigned int bytes) 4399 { 4400 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 4401 int r = kvm_vcpu_read_guest(vcpu, addr, val, bytes); 4402 4403 return r < 0 ? X86EMUL_IO_NEEDED : X86EMUL_CONTINUE; 4404 } 4405 4406 int kvm_write_guest_virt_system(struct x86_emulate_ctxt *ctxt, 4407 gva_t addr, void *val, 4408 unsigned int bytes, 4409 struct x86_exception *exception) 4410 { 4411 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 4412 void *data = val; 4413 int r = X86EMUL_CONTINUE; 4414 4415 while (bytes) { 4416 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, 4417 PFERR_WRITE_MASK, 4418 exception); 4419 unsigned offset = addr & (PAGE_SIZE-1); 4420 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset); 4421 int ret; 4422 4423 if (gpa == UNMAPPED_GVA) 4424 return X86EMUL_PROPAGATE_FAULT; 4425 ret = kvm_vcpu_write_guest(vcpu, gpa, data, towrite); 4426 if (ret < 0) { 4427 r = X86EMUL_IO_NEEDED; 4428 goto out; 4429 } 4430 4431 bytes -= towrite; 4432 data += towrite; 4433 addr += towrite; 4434 } 4435 out: 4436 return r; 4437 } 4438 EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system); 4439 4440 static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva, 4441 gpa_t *gpa, struct x86_exception *exception, 4442 bool write) 4443 { 4444 u32 access = ((kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0) 4445 | (write ? PFERR_WRITE_MASK : 0); 4446 4447 /* 4448 * currently PKRU is only applied to ept enabled guest so 4449 * there is no pkey in EPT page table for L1 guest or EPT 4450 * shadow page table for L2 guest. 4451 */ 4452 if (vcpu_match_mmio_gva(vcpu, gva) 4453 && !permission_fault(vcpu, vcpu->arch.walk_mmu, 4454 vcpu->arch.access, 0, access)) { 4455 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT | 4456 (gva & (PAGE_SIZE - 1)); 4457 trace_vcpu_match_mmio(gva, *gpa, write, false); 4458 return 1; 4459 } 4460 4461 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception); 4462 4463 if (*gpa == UNMAPPED_GVA) 4464 return -1; 4465 4466 /* For APIC access vmexit */ 4467 if ((*gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE) 4468 return 1; 4469 4470 if (vcpu_match_mmio_gpa(vcpu, *gpa)) { 4471 trace_vcpu_match_mmio(gva, *gpa, write, true); 4472 return 1; 4473 } 4474 4475 return 0; 4476 } 4477 4478 int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa, 4479 const void *val, int bytes) 4480 { 4481 int ret; 4482 4483 ret = kvm_vcpu_write_guest(vcpu, gpa, val, bytes); 4484 if (ret < 0) 4485 return 0; 4486 kvm_page_track_write(vcpu, gpa, val, bytes); 4487 return 1; 4488 } 4489 4490 struct read_write_emulator_ops { 4491 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val, 4492 int bytes); 4493 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa, 4494 void *val, int bytes); 4495 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa, 4496 int bytes, void *val); 4497 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa, 4498 void *val, int bytes); 4499 bool write; 4500 }; 4501 4502 static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes) 4503 { 4504 if (vcpu->mmio_read_completed) { 4505 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes, 4506 vcpu->mmio_fragments[0].gpa, *(u64 *)val); 4507 vcpu->mmio_read_completed = 0; 4508 return 1; 4509 } 4510 4511 return 0; 4512 } 4513 4514 static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa, 4515 void *val, int bytes) 4516 { 4517 return !kvm_vcpu_read_guest(vcpu, gpa, val, bytes); 4518 } 4519 4520 static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa, 4521 void *val, int bytes) 4522 { 4523 return emulator_write_phys(vcpu, gpa, val, bytes); 4524 } 4525 4526 static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val) 4527 { 4528 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val); 4529 return vcpu_mmio_write(vcpu, gpa, bytes, val); 4530 } 4531 4532 static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, 4533 void *val, int bytes) 4534 { 4535 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0); 4536 return X86EMUL_IO_NEEDED; 4537 } 4538 4539 static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, 4540 void *val, int bytes) 4541 { 4542 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0]; 4543 4544 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len)); 4545 return X86EMUL_CONTINUE; 4546 } 4547 4548 static const struct read_write_emulator_ops read_emultor = { 4549 .read_write_prepare = read_prepare, 4550 .read_write_emulate = read_emulate, 4551 .read_write_mmio = vcpu_mmio_read, 4552 .read_write_exit_mmio = read_exit_mmio, 4553 }; 4554 4555 static const struct read_write_emulator_ops write_emultor = { 4556 .read_write_emulate = write_emulate, 4557 .read_write_mmio = write_mmio, 4558 .read_write_exit_mmio = write_exit_mmio, 4559 .write = true, 4560 }; 4561 4562 static int emulator_read_write_onepage(unsigned long addr, void *val, 4563 unsigned int bytes, 4564 struct x86_exception *exception, 4565 struct kvm_vcpu *vcpu, 4566 const struct read_write_emulator_ops *ops) 4567 { 4568 gpa_t gpa; 4569 int handled, ret; 4570 bool write = ops->write; 4571 struct kvm_mmio_fragment *frag; 4572 4573 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write); 4574 4575 if (ret < 0) 4576 return X86EMUL_PROPAGATE_FAULT; 4577 4578 /* For APIC access vmexit */ 4579 if (ret) 4580 goto mmio; 4581 4582 if (ops->read_write_emulate(vcpu, gpa, val, bytes)) 4583 return X86EMUL_CONTINUE; 4584 4585 mmio: 4586 /* 4587 * Is this MMIO handled locally? 4588 */ 4589 handled = ops->read_write_mmio(vcpu, gpa, bytes, val); 4590 if (handled == bytes) 4591 return X86EMUL_CONTINUE; 4592 4593 gpa += handled; 4594 bytes -= handled; 4595 val += handled; 4596 4597 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS); 4598 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++]; 4599 frag->gpa = gpa; 4600 frag->data = val; 4601 frag->len = bytes; 4602 return X86EMUL_CONTINUE; 4603 } 4604 4605 static int emulator_read_write(struct x86_emulate_ctxt *ctxt, 4606 unsigned long addr, 4607 void *val, unsigned int bytes, 4608 struct x86_exception *exception, 4609 const struct read_write_emulator_ops *ops) 4610 { 4611 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 4612 gpa_t gpa; 4613 int rc; 4614 4615 if (ops->read_write_prepare && 4616 ops->read_write_prepare(vcpu, val, bytes)) 4617 return X86EMUL_CONTINUE; 4618 4619 vcpu->mmio_nr_fragments = 0; 4620 4621 /* Crossing a page boundary? */ 4622 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) { 4623 int now; 4624 4625 now = -addr & ~PAGE_MASK; 4626 rc = emulator_read_write_onepage(addr, val, now, exception, 4627 vcpu, ops); 4628 4629 if (rc != X86EMUL_CONTINUE) 4630 return rc; 4631 addr += now; 4632 if (ctxt->mode != X86EMUL_MODE_PROT64) 4633 addr = (u32)addr; 4634 val += now; 4635 bytes -= now; 4636 } 4637 4638 rc = emulator_read_write_onepage(addr, val, bytes, exception, 4639 vcpu, ops); 4640 if (rc != X86EMUL_CONTINUE) 4641 return rc; 4642 4643 if (!vcpu->mmio_nr_fragments) 4644 return rc; 4645 4646 gpa = vcpu->mmio_fragments[0].gpa; 4647 4648 vcpu->mmio_needed = 1; 4649 vcpu->mmio_cur_fragment = 0; 4650 4651 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len); 4652 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write; 4653 vcpu->run->exit_reason = KVM_EXIT_MMIO; 4654 vcpu->run->mmio.phys_addr = gpa; 4655 4656 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes); 4657 } 4658 4659 static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt, 4660 unsigned long addr, 4661 void *val, 4662 unsigned int bytes, 4663 struct x86_exception *exception) 4664 { 4665 return emulator_read_write(ctxt, addr, val, bytes, 4666 exception, &read_emultor); 4667 } 4668 4669 static int emulator_write_emulated(struct x86_emulate_ctxt *ctxt, 4670 unsigned long addr, 4671 const void *val, 4672 unsigned int bytes, 4673 struct x86_exception *exception) 4674 { 4675 return emulator_read_write(ctxt, addr, (void *)val, bytes, 4676 exception, &write_emultor); 4677 } 4678 4679 #define CMPXCHG_TYPE(t, ptr, old, new) \ 4680 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old)) 4681 4682 #ifdef CONFIG_X86_64 4683 # define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new) 4684 #else 4685 # define CMPXCHG64(ptr, old, new) \ 4686 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old)) 4687 #endif 4688 4689 static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt, 4690 unsigned long addr, 4691 const void *old, 4692 const void *new, 4693 unsigned int bytes, 4694 struct x86_exception *exception) 4695 { 4696 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 4697 gpa_t gpa; 4698 struct page *page; 4699 char *kaddr; 4700 bool exchanged; 4701 4702 /* guests cmpxchg8b have to be emulated atomically */ 4703 if (bytes > 8 || (bytes & (bytes - 1))) 4704 goto emul_write; 4705 4706 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL); 4707 4708 if (gpa == UNMAPPED_GVA || 4709 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE) 4710 goto emul_write; 4711 4712 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK)) 4713 goto emul_write; 4714 4715 page = kvm_vcpu_gfn_to_page(vcpu, gpa >> PAGE_SHIFT); 4716 if (is_error_page(page)) 4717 goto emul_write; 4718 4719 kaddr = kmap_atomic(page); 4720 kaddr += offset_in_page(gpa); 4721 switch (bytes) { 4722 case 1: 4723 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new); 4724 break; 4725 case 2: 4726 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new); 4727 break; 4728 case 4: 4729 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new); 4730 break; 4731 case 8: 4732 exchanged = CMPXCHG64(kaddr, old, new); 4733 break; 4734 default: 4735 BUG(); 4736 } 4737 kunmap_atomic(kaddr); 4738 kvm_release_page_dirty(page); 4739 4740 if (!exchanged) 4741 return X86EMUL_CMPXCHG_FAILED; 4742 4743 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT); 4744 kvm_page_track_write(vcpu, gpa, new, bytes); 4745 4746 return X86EMUL_CONTINUE; 4747 4748 emul_write: 4749 printk_once(KERN_WARNING "kvm: emulating exchange as write\n"); 4750 4751 return emulator_write_emulated(ctxt, addr, new, bytes, exception); 4752 } 4753 4754 static int kernel_pio(struct kvm_vcpu *vcpu, void *pd) 4755 { 4756 /* TODO: String I/O for in kernel device */ 4757 int r; 4758 4759 if (vcpu->arch.pio.in) 4760 r = kvm_io_bus_read(vcpu, KVM_PIO_BUS, vcpu->arch.pio.port, 4761 vcpu->arch.pio.size, pd); 4762 else 4763 r = kvm_io_bus_write(vcpu, KVM_PIO_BUS, 4764 vcpu->arch.pio.port, vcpu->arch.pio.size, 4765 pd); 4766 return r; 4767 } 4768 4769 static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size, 4770 unsigned short port, void *val, 4771 unsigned int count, bool in) 4772 { 4773 vcpu->arch.pio.port = port; 4774 vcpu->arch.pio.in = in; 4775 vcpu->arch.pio.count = count; 4776 vcpu->arch.pio.size = size; 4777 4778 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) { 4779 vcpu->arch.pio.count = 0; 4780 return 1; 4781 } 4782 4783 vcpu->run->exit_reason = KVM_EXIT_IO; 4784 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT; 4785 vcpu->run->io.size = size; 4786 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE; 4787 vcpu->run->io.count = count; 4788 vcpu->run->io.port = port; 4789 4790 return 0; 4791 } 4792 4793 static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt, 4794 int size, unsigned short port, void *val, 4795 unsigned int count) 4796 { 4797 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 4798 int ret; 4799 4800 if (vcpu->arch.pio.count) 4801 goto data_avail; 4802 4803 ret = emulator_pio_in_out(vcpu, size, port, val, count, true); 4804 if (ret) { 4805 data_avail: 4806 memcpy(val, vcpu->arch.pio_data, size * count); 4807 trace_kvm_pio(KVM_PIO_IN, port, size, count, vcpu->arch.pio_data); 4808 vcpu->arch.pio.count = 0; 4809 return 1; 4810 } 4811 4812 return 0; 4813 } 4814 4815 static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt, 4816 int size, unsigned short port, 4817 const void *val, unsigned int count) 4818 { 4819 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 4820 4821 memcpy(vcpu->arch.pio_data, val, size * count); 4822 trace_kvm_pio(KVM_PIO_OUT, port, size, count, vcpu->arch.pio_data); 4823 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false); 4824 } 4825 4826 static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg) 4827 { 4828 return kvm_x86_ops->get_segment_base(vcpu, seg); 4829 } 4830 4831 static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address) 4832 { 4833 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address); 4834 } 4835 4836 static int kvm_emulate_wbinvd_noskip(struct kvm_vcpu *vcpu) 4837 { 4838 if (!need_emulate_wbinvd(vcpu)) 4839 return X86EMUL_CONTINUE; 4840 4841 if (kvm_x86_ops->has_wbinvd_exit()) { 4842 int cpu = get_cpu(); 4843 4844 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask); 4845 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask, 4846 wbinvd_ipi, NULL, 1); 4847 put_cpu(); 4848 cpumask_clear(vcpu->arch.wbinvd_dirty_mask); 4849 } else 4850 wbinvd(); 4851 return X86EMUL_CONTINUE; 4852 } 4853 4854 int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu) 4855 { 4856 kvm_emulate_wbinvd_noskip(vcpu); 4857 return kvm_skip_emulated_instruction(vcpu); 4858 } 4859 EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd); 4860 4861 4862 4863 static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt) 4864 { 4865 kvm_emulate_wbinvd_noskip(emul_to_vcpu(ctxt)); 4866 } 4867 4868 static int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr, 4869 unsigned long *dest) 4870 { 4871 return kvm_get_dr(emul_to_vcpu(ctxt), dr, dest); 4872 } 4873 4874 static int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr, 4875 unsigned long value) 4876 { 4877 4878 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value); 4879 } 4880 4881 static u64 mk_cr_64(u64 curr_cr, u32 new_val) 4882 { 4883 return (curr_cr & ~((1ULL << 32) - 1)) | new_val; 4884 } 4885 4886 static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr) 4887 { 4888 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 4889 unsigned long value; 4890 4891 switch (cr) { 4892 case 0: 4893 value = kvm_read_cr0(vcpu); 4894 break; 4895 case 2: 4896 value = vcpu->arch.cr2; 4897 break; 4898 case 3: 4899 value = kvm_read_cr3(vcpu); 4900 break; 4901 case 4: 4902 value = kvm_read_cr4(vcpu); 4903 break; 4904 case 8: 4905 value = kvm_get_cr8(vcpu); 4906 break; 4907 default: 4908 kvm_err("%s: unexpected cr %u\n", __func__, cr); 4909 return 0; 4910 } 4911 4912 return value; 4913 } 4914 4915 static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val) 4916 { 4917 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 4918 int res = 0; 4919 4920 switch (cr) { 4921 case 0: 4922 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val)); 4923 break; 4924 case 2: 4925 vcpu->arch.cr2 = val; 4926 break; 4927 case 3: 4928 res = kvm_set_cr3(vcpu, val); 4929 break; 4930 case 4: 4931 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val)); 4932 break; 4933 case 8: 4934 res = kvm_set_cr8(vcpu, val); 4935 break; 4936 default: 4937 kvm_err("%s: unexpected cr %u\n", __func__, cr); 4938 res = -1; 4939 } 4940 4941 return res; 4942 } 4943 4944 static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt) 4945 { 4946 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt)); 4947 } 4948 4949 static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt) 4950 { 4951 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt); 4952 } 4953 4954 static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt) 4955 { 4956 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt); 4957 } 4958 4959 static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt) 4960 { 4961 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt); 4962 } 4963 4964 static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt) 4965 { 4966 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt); 4967 } 4968 4969 static unsigned long emulator_get_cached_segment_base( 4970 struct x86_emulate_ctxt *ctxt, int seg) 4971 { 4972 return get_segment_base(emul_to_vcpu(ctxt), seg); 4973 } 4974 4975 static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector, 4976 struct desc_struct *desc, u32 *base3, 4977 int seg) 4978 { 4979 struct kvm_segment var; 4980 4981 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg); 4982 *selector = var.selector; 4983 4984 if (var.unusable) { 4985 memset(desc, 0, sizeof(*desc)); 4986 return false; 4987 } 4988 4989 if (var.g) 4990 var.limit >>= 12; 4991 set_desc_limit(desc, var.limit); 4992 set_desc_base(desc, (unsigned long)var.base); 4993 #ifdef CONFIG_X86_64 4994 if (base3) 4995 *base3 = var.base >> 32; 4996 #endif 4997 desc->type = var.type; 4998 desc->s = var.s; 4999 desc->dpl = var.dpl; 5000 desc->p = var.present; 5001 desc->avl = var.avl; 5002 desc->l = var.l; 5003 desc->d = var.db; 5004 desc->g = var.g; 5005 5006 return true; 5007 } 5008 5009 static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector, 5010 struct desc_struct *desc, u32 base3, 5011 int seg) 5012 { 5013 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 5014 struct kvm_segment var; 5015 5016 var.selector = selector; 5017 var.base = get_desc_base(desc); 5018 #ifdef CONFIG_X86_64 5019 var.base |= ((u64)base3) << 32; 5020 #endif 5021 var.limit = get_desc_limit(desc); 5022 if (desc->g) 5023 var.limit = (var.limit << 12) | 0xfff; 5024 var.type = desc->type; 5025 var.dpl = desc->dpl; 5026 var.db = desc->d; 5027 var.s = desc->s; 5028 var.l = desc->l; 5029 var.g = desc->g; 5030 var.avl = desc->avl; 5031 var.present = desc->p; 5032 var.unusable = !var.present; 5033 var.padding = 0; 5034 5035 kvm_set_segment(vcpu, &var, seg); 5036 return; 5037 } 5038 5039 static int emulator_get_msr(struct x86_emulate_ctxt *ctxt, 5040 u32 msr_index, u64 *pdata) 5041 { 5042 struct msr_data msr; 5043 int r; 5044 5045 msr.index = msr_index; 5046 msr.host_initiated = false; 5047 r = kvm_get_msr(emul_to_vcpu(ctxt), &msr); 5048 if (r) 5049 return r; 5050 5051 *pdata = msr.data; 5052 return 0; 5053 } 5054 5055 static int emulator_set_msr(struct x86_emulate_ctxt *ctxt, 5056 u32 msr_index, u64 data) 5057 { 5058 struct msr_data msr; 5059 5060 msr.data = data; 5061 msr.index = msr_index; 5062 msr.host_initiated = false; 5063 return kvm_set_msr(emul_to_vcpu(ctxt), &msr); 5064 } 5065 5066 static u64 emulator_get_smbase(struct x86_emulate_ctxt *ctxt) 5067 { 5068 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 5069 5070 return vcpu->arch.smbase; 5071 } 5072 5073 static void emulator_set_smbase(struct x86_emulate_ctxt *ctxt, u64 smbase) 5074 { 5075 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 5076 5077 vcpu->arch.smbase = smbase; 5078 } 5079 5080 static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt, 5081 u32 pmc) 5082 { 5083 return kvm_pmu_is_valid_msr_idx(emul_to_vcpu(ctxt), pmc); 5084 } 5085 5086 static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt, 5087 u32 pmc, u64 *pdata) 5088 { 5089 return kvm_pmu_rdpmc(emul_to_vcpu(ctxt), pmc, pdata); 5090 } 5091 5092 static void emulator_halt(struct x86_emulate_ctxt *ctxt) 5093 { 5094 emul_to_vcpu(ctxt)->arch.halt_request = 1; 5095 } 5096 5097 static void emulator_get_fpu(struct x86_emulate_ctxt *ctxt) 5098 { 5099 preempt_disable(); 5100 kvm_load_guest_fpu(emul_to_vcpu(ctxt)); 5101 } 5102 5103 static void emulator_put_fpu(struct x86_emulate_ctxt *ctxt) 5104 { 5105 preempt_enable(); 5106 } 5107 5108 static int emulator_intercept(struct x86_emulate_ctxt *ctxt, 5109 struct x86_instruction_info *info, 5110 enum x86_intercept_stage stage) 5111 { 5112 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage); 5113 } 5114 5115 static void emulator_get_cpuid(struct x86_emulate_ctxt *ctxt, 5116 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx) 5117 { 5118 kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx); 5119 } 5120 5121 static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg) 5122 { 5123 return kvm_register_read(emul_to_vcpu(ctxt), reg); 5124 } 5125 5126 static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val) 5127 { 5128 kvm_register_write(emul_to_vcpu(ctxt), reg, val); 5129 } 5130 5131 static void emulator_set_nmi_mask(struct x86_emulate_ctxt *ctxt, bool masked) 5132 { 5133 kvm_x86_ops->set_nmi_mask(emul_to_vcpu(ctxt), masked); 5134 } 5135 5136 static const struct x86_emulate_ops emulate_ops = { 5137 .read_gpr = emulator_read_gpr, 5138 .write_gpr = emulator_write_gpr, 5139 .read_std = kvm_read_guest_virt_system, 5140 .write_std = kvm_write_guest_virt_system, 5141 .read_phys = kvm_read_guest_phys_system, 5142 .fetch = kvm_fetch_guest_virt, 5143 .read_emulated = emulator_read_emulated, 5144 .write_emulated = emulator_write_emulated, 5145 .cmpxchg_emulated = emulator_cmpxchg_emulated, 5146 .invlpg = emulator_invlpg, 5147 .pio_in_emulated = emulator_pio_in_emulated, 5148 .pio_out_emulated = emulator_pio_out_emulated, 5149 .get_segment = emulator_get_segment, 5150 .set_segment = emulator_set_segment, 5151 .get_cached_segment_base = emulator_get_cached_segment_base, 5152 .get_gdt = emulator_get_gdt, 5153 .get_idt = emulator_get_idt, 5154 .set_gdt = emulator_set_gdt, 5155 .set_idt = emulator_set_idt, 5156 .get_cr = emulator_get_cr, 5157 .set_cr = emulator_set_cr, 5158 .cpl = emulator_get_cpl, 5159 .get_dr = emulator_get_dr, 5160 .set_dr = emulator_set_dr, 5161 .get_smbase = emulator_get_smbase, 5162 .set_smbase = emulator_set_smbase, 5163 .set_msr = emulator_set_msr, 5164 .get_msr = emulator_get_msr, 5165 .check_pmc = emulator_check_pmc, 5166 .read_pmc = emulator_read_pmc, 5167 .halt = emulator_halt, 5168 .wbinvd = emulator_wbinvd, 5169 .fix_hypercall = emulator_fix_hypercall, 5170 .get_fpu = emulator_get_fpu, 5171 .put_fpu = emulator_put_fpu, 5172 .intercept = emulator_intercept, 5173 .get_cpuid = emulator_get_cpuid, 5174 .set_nmi_mask = emulator_set_nmi_mask, 5175 }; 5176 5177 static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask) 5178 { 5179 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu); 5180 /* 5181 * an sti; sti; sequence only disable interrupts for the first 5182 * instruction. So, if the last instruction, be it emulated or 5183 * not, left the system with the INT_STI flag enabled, it 5184 * means that the last instruction is an sti. We should not 5185 * leave the flag on in this case. The same goes for mov ss 5186 */ 5187 if (int_shadow & mask) 5188 mask = 0; 5189 if (unlikely(int_shadow || mask)) { 5190 kvm_x86_ops->set_interrupt_shadow(vcpu, mask); 5191 if (!mask) 5192 kvm_make_request(KVM_REQ_EVENT, vcpu); 5193 } 5194 } 5195 5196 static bool inject_emulated_exception(struct kvm_vcpu *vcpu) 5197 { 5198 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt; 5199 if (ctxt->exception.vector == PF_VECTOR) 5200 return kvm_propagate_fault(vcpu, &ctxt->exception); 5201 5202 if (ctxt->exception.error_code_valid) 5203 kvm_queue_exception_e(vcpu, ctxt->exception.vector, 5204 ctxt->exception.error_code); 5205 else 5206 kvm_queue_exception(vcpu, ctxt->exception.vector); 5207 return false; 5208 } 5209 5210 static void init_emulate_ctxt(struct kvm_vcpu *vcpu) 5211 { 5212 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt; 5213 int cs_db, cs_l; 5214 5215 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l); 5216 5217 ctxt->eflags = kvm_get_rflags(vcpu); 5218 ctxt->eip = kvm_rip_read(vcpu); 5219 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL : 5220 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 : 5221 (cs_l && is_long_mode(vcpu)) ? X86EMUL_MODE_PROT64 : 5222 cs_db ? X86EMUL_MODE_PROT32 : 5223 X86EMUL_MODE_PROT16; 5224 BUILD_BUG_ON(HF_GUEST_MASK != X86EMUL_GUEST_MASK); 5225 BUILD_BUG_ON(HF_SMM_MASK != X86EMUL_SMM_MASK); 5226 BUILD_BUG_ON(HF_SMM_INSIDE_NMI_MASK != X86EMUL_SMM_INSIDE_NMI_MASK); 5227 ctxt->emul_flags = vcpu->arch.hflags; 5228 5229 init_decode_cache(ctxt); 5230 vcpu->arch.emulate_regs_need_sync_from_vcpu = false; 5231 } 5232 5233 int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip) 5234 { 5235 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt; 5236 int ret; 5237 5238 init_emulate_ctxt(vcpu); 5239 5240 ctxt->op_bytes = 2; 5241 ctxt->ad_bytes = 2; 5242 ctxt->_eip = ctxt->eip + inc_eip; 5243 ret = emulate_int_real(ctxt, irq); 5244 5245 if (ret != X86EMUL_CONTINUE) 5246 return EMULATE_FAIL; 5247 5248 ctxt->eip = ctxt->_eip; 5249 kvm_rip_write(vcpu, ctxt->eip); 5250 kvm_set_rflags(vcpu, ctxt->eflags); 5251 5252 if (irq == NMI_VECTOR) 5253 vcpu->arch.nmi_pending = 0; 5254 else 5255 vcpu->arch.interrupt.pending = false; 5256 5257 return EMULATE_DONE; 5258 } 5259 EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt); 5260 5261 static int handle_emulation_failure(struct kvm_vcpu *vcpu) 5262 { 5263 int r = EMULATE_DONE; 5264 5265 ++vcpu->stat.insn_emulation_fail; 5266 trace_kvm_emulate_insn_failed(vcpu); 5267 if (!is_guest_mode(vcpu) && kvm_x86_ops->get_cpl(vcpu) == 0) { 5268 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR; 5269 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION; 5270 vcpu->run->internal.ndata = 0; 5271 r = EMULATE_FAIL; 5272 } 5273 kvm_queue_exception(vcpu, UD_VECTOR); 5274 5275 return r; 5276 } 5277 5278 static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t cr2, 5279 bool write_fault_to_shadow_pgtable, 5280 int emulation_type) 5281 { 5282 gpa_t gpa = cr2; 5283 kvm_pfn_t pfn; 5284 5285 if (emulation_type & EMULTYPE_NO_REEXECUTE) 5286 return false; 5287 5288 if (!vcpu->arch.mmu.direct_map) { 5289 /* 5290 * Write permission should be allowed since only 5291 * write access need to be emulated. 5292 */ 5293 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL); 5294 5295 /* 5296 * If the mapping is invalid in guest, let cpu retry 5297 * it to generate fault. 5298 */ 5299 if (gpa == UNMAPPED_GVA) 5300 return true; 5301 } 5302 5303 /* 5304 * Do not retry the unhandleable instruction if it faults on the 5305 * readonly host memory, otherwise it will goto a infinite loop: 5306 * retry instruction -> write #PF -> emulation fail -> retry 5307 * instruction -> ... 5308 */ 5309 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa)); 5310 5311 /* 5312 * If the instruction failed on the error pfn, it can not be fixed, 5313 * report the error to userspace. 5314 */ 5315 if (is_error_noslot_pfn(pfn)) 5316 return false; 5317 5318 kvm_release_pfn_clean(pfn); 5319 5320 /* The instructions are well-emulated on direct mmu. */ 5321 if (vcpu->arch.mmu.direct_map) { 5322 unsigned int indirect_shadow_pages; 5323 5324 spin_lock(&vcpu->kvm->mmu_lock); 5325 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages; 5326 spin_unlock(&vcpu->kvm->mmu_lock); 5327 5328 if (indirect_shadow_pages) 5329 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa)); 5330 5331 return true; 5332 } 5333 5334 /* 5335 * if emulation was due to access to shadowed page table 5336 * and it failed try to unshadow page and re-enter the 5337 * guest to let CPU execute the instruction. 5338 */ 5339 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa)); 5340 5341 /* 5342 * If the access faults on its page table, it can not 5343 * be fixed by unprotecting shadow page and it should 5344 * be reported to userspace. 5345 */ 5346 return !write_fault_to_shadow_pgtable; 5347 } 5348 5349 static bool retry_instruction(struct x86_emulate_ctxt *ctxt, 5350 unsigned long cr2, int emulation_type) 5351 { 5352 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 5353 unsigned long last_retry_eip, last_retry_addr, gpa = cr2; 5354 5355 last_retry_eip = vcpu->arch.last_retry_eip; 5356 last_retry_addr = vcpu->arch.last_retry_addr; 5357 5358 /* 5359 * If the emulation is caused by #PF and it is non-page_table 5360 * writing instruction, it means the VM-EXIT is caused by shadow 5361 * page protected, we can zap the shadow page and retry this 5362 * instruction directly. 5363 * 5364 * Note: if the guest uses a non-page-table modifying instruction 5365 * on the PDE that points to the instruction, then we will unmap 5366 * the instruction and go to an infinite loop. So, we cache the 5367 * last retried eip and the last fault address, if we meet the eip 5368 * and the address again, we can break out of the potential infinite 5369 * loop. 5370 */ 5371 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0; 5372 5373 if (!(emulation_type & EMULTYPE_RETRY)) 5374 return false; 5375 5376 if (x86_page_table_writing_insn(ctxt)) 5377 return false; 5378 5379 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2) 5380 return false; 5381 5382 vcpu->arch.last_retry_eip = ctxt->eip; 5383 vcpu->arch.last_retry_addr = cr2; 5384 5385 if (!vcpu->arch.mmu.direct_map) 5386 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL); 5387 5388 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa)); 5389 5390 return true; 5391 } 5392 5393 static int complete_emulated_mmio(struct kvm_vcpu *vcpu); 5394 static int complete_emulated_pio(struct kvm_vcpu *vcpu); 5395 5396 static void kvm_smm_changed(struct kvm_vcpu *vcpu) 5397 { 5398 if (!(vcpu->arch.hflags & HF_SMM_MASK)) { 5399 /* This is a good place to trace that we are exiting SMM. */ 5400 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, false); 5401 5402 /* Process a latched INIT or SMI, if any. */ 5403 kvm_make_request(KVM_REQ_EVENT, vcpu); 5404 } 5405 5406 kvm_mmu_reset_context(vcpu); 5407 } 5408 5409 static void kvm_set_hflags(struct kvm_vcpu *vcpu, unsigned emul_flags) 5410 { 5411 unsigned changed = vcpu->arch.hflags ^ emul_flags; 5412 5413 vcpu->arch.hflags = emul_flags; 5414 5415 if (changed & HF_SMM_MASK) 5416 kvm_smm_changed(vcpu); 5417 } 5418 5419 static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7, 5420 unsigned long *db) 5421 { 5422 u32 dr6 = 0; 5423 int i; 5424 u32 enable, rwlen; 5425 5426 enable = dr7; 5427 rwlen = dr7 >> 16; 5428 for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4) 5429 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr) 5430 dr6 |= (1 << i); 5431 return dr6; 5432 } 5433 5434 static void kvm_vcpu_check_singlestep(struct kvm_vcpu *vcpu, unsigned long rflags, int *r) 5435 { 5436 struct kvm_run *kvm_run = vcpu->run; 5437 5438 /* 5439 * rflags is the old, "raw" value of the flags. The new value has 5440 * not been saved yet. 5441 * 5442 * This is correct even for TF set by the guest, because "the 5443 * processor will not generate this exception after the instruction 5444 * that sets the TF flag". 5445 */ 5446 if (unlikely(rflags & X86_EFLAGS_TF)) { 5447 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) { 5448 kvm_run->debug.arch.dr6 = DR6_BS | DR6_FIXED_1 | 5449 DR6_RTM; 5450 kvm_run->debug.arch.pc = vcpu->arch.singlestep_rip; 5451 kvm_run->debug.arch.exception = DB_VECTOR; 5452 kvm_run->exit_reason = KVM_EXIT_DEBUG; 5453 *r = EMULATE_USER_EXIT; 5454 } else { 5455 /* 5456 * "Certain debug exceptions may clear bit 0-3. The 5457 * remaining contents of the DR6 register are never 5458 * cleared by the processor". 5459 */ 5460 vcpu->arch.dr6 &= ~15; 5461 vcpu->arch.dr6 |= DR6_BS | DR6_RTM; 5462 kvm_queue_exception(vcpu, DB_VECTOR); 5463 } 5464 } 5465 } 5466 5467 int kvm_skip_emulated_instruction(struct kvm_vcpu *vcpu) 5468 { 5469 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu); 5470 int r = EMULATE_DONE; 5471 5472 kvm_x86_ops->skip_emulated_instruction(vcpu); 5473 kvm_vcpu_check_singlestep(vcpu, rflags, &r); 5474 return r == EMULATE_DONE; 5475 } 5476 EXPORT_SYMBOL_GPL(kvm_skip_emulated_instruction); 5477 5478 static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r) 5479 { 5480 if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) && 5481 (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) { 5482 struct kvm_run *kvm_run = vcpu->run; 5483 unsigned long eip = kvm_get_linear_rip(vcpu); 5484 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0, 5485 vcpu->arch.guest_debug_dr7, 5486 vcpu->arch.eff_db); 5487 5488 if (dr6 != 0) { 5489 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1 | DR6_RTM; 5490 kvm_run->debug.arch.pc = eip; 5491 kvm_run->debug.arch.exception = DB_VECTOR; 5492 kvm_run->exit_reason = KVM_EXIT_DEBUG; 5493 *r = EMULATE_USER_EXIT; 5494 return true; 5495 } 5496 } 5497 5498 if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) && 5499 !(kvm_get_rflags(vcpu) & X86_EFLAGS_RF)) { 5500 unsigned long eip = kvm_get_linear_rip(vcpu); 5501 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0, 5502 vcpu->arch.dr7, 5503 vcpu->arch.db); 5504 5505 if (dr6 != 0) { 5506 vcpu->arch.dr6 &= ~15; 5507 vcpu->arch.dr6 |= dr6 | DR6_RTM; 5508 kvm_queue_exception(vcpu, DB_VECTOR); 5509 *r = EMULATE_DONE; 5510 return true; 5511 } 5512 } 5513 5514 return false; 5515 } 5516 5517 int x86_emulate_instruction(struct kvm_vcpu *vcpu, 5518 unsigned long cr2, 5519 int emulation_type, 5520 void *insn, 5521 int insn_len) 5522 { 5523 int r; 5524 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt; 5525 bool writeback = true; 5526 bool write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable; 5527 5528 /* 5529 * Clear write_fault_to_shadow_pgtable here to ensure it is 5530 * never reused. 5531 */ 5532 vcpu->arch.write_fault_to_shadow_pgtable = false; 5533 kvm_clear_exception_queue(vcpu); 5534 5535 if (!(emulation_type & EMULTYPE_NO_DECODE)) { 5536 init_emulate_ctxt(vcpu); 5537 5538 /* 5539 * We will reenter on the same instruction since 5540 * we do not set complete_userspace_io. This does not 5541 * handle watchpoints yet, those would be handled in 5542 * the emulate_ops. 5543 */ 5544 if (kvm_vcpu_check_breakpoint(vcpu, &r)) 5545 return r; 5546 5547 ctxt->interruptibility = 0; 5548 ctxt->have_exception = false; 5549 ctxt->exception.vector = -1; 5550 ctxt->perm_ok = false; 5551 5552 ctxt->ud = emulation_type & EMULTYPE_TRAP_UD; 5553 5554 r = x86_decode_insn(ctxt, insn, insn_len); 5555 5556 trace_kvm_emulate_insn_start(vcpu); 5557 ++vcpu->stat.insn_emulation; 5558 if (r != EMULATION_OK) { 5559 if (emulation_type & EMULTYPE_TRAP_UD) 5560 return EMULATE_FAIL; 5561 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt, 5562 emulation_type)) 5563 return EMULATE_DONE; 5564 if (emulation_type & EMULTYPE_SKIP) 5565 return EMULATE_FAIL; 5566 return handle_emulation_failure(vcpu); 5567 } 5568 } 5569 5570 if (emulation_type & EMULTYPE_SKIP) { 5571 kvm_rip_write(vcpu, ctxt->_eip); 5572 if (ctxt->eflags & X86_EFLAGS_RF) 5573 kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF); 5574 return EMULATE_DONE; 5575 } 5576 5577 if (retry_instruction(ctxt, cr2, emulation_type)) 5578 return EMULATE_DONE; 5579 5580 /* this is needed for vmware backdoor interface to work since it 5581 changes registers values during IO operation */ 5582 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) { 5583 vcpu->arch.emulate_regs_need_sync_from_vcpu = false; 5584 emulator_invalidate_register_cache(ctxt); 5585 } 5586 5587 restart: 5588 r = x86_emulate_insn(ctxt); 5589 5590 if (r == EMULATION_INTERCEPTED) 5591 return EMULATE_DONE; 5592 5593 if (r == EMULATION_FAILED) { 5594 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt, 5595 emulation_type)) 5596 return EMULATE_DONE; 5597 5598 return handle_emulation_failure(vcpu); 5599 } 5600 5601 if (ctxt->have_exception) { 5602 r = EMULATE_DONE; 5603 if (inject_emulated_exception(vcpu)) 5604 return r; 5605 } else if (vcpu->arch.pio.count) { 5606 if (!vcpu->arch.pio.in) { 5607 /* FIXME: return into emulator if single-stepping. */ 5608 vcpu->arch.pio.count = 0; 5609 } else { 5610 writeback = false; 5611 vcpu->arch.complete_userspace_io = complete_emulated_pio; 5612 } 5613 r = EMULATE_USER_EXIT; 5614 } else if (vcpu->mmio_needed) { 5615 if (!vcpu->mmio_is_write) 5616 writeback = false; 5617 r = EMULATE_USER_EXIT; 5618 vcpu->arch.complete_userspace_io = complete_emulated_mmio; 5619 } else if (r == EMULATION_RESTART) 5620 goto restart; 5621 else 5622 r = EMULATE_DONE; 5623 5624 if (writeback) { 5625 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu); 5626 toggle_interruptibility(vcpu, ctxt->interruptibility); 5627 vcpu->arch.emulate_regs_need_sync_to_vcpu = false; 5628 if (vcpu->arch.hflags != ctxt->emul_flags) 5629 kvm_set_hflags(vcpu, ctxt->emul_flags); 5630 kvm_rip_write(vcpu, ctxt->eip); 5631 if (r == EMULATE_DONE) 5632 kvm_vcpu_check_singlestep(vcpu, rflags, &r); 5633 if (!ctxt->have_exception || 5634 exception_type(ctxt->exception.vector) == EXCPT_TRAP) 5635 __kvm_set_rflags(vcpu, ctxt->eflags); 5636 5637 /* 5638 * For STI, interrupts are shadowed; so KVM_REQ_EVENT will 5639 * do nothing, and it will be requested again as soon as 5640 * the shadow expires. But we still need to check here, 5641 * because POPF has no interrupt shadow. 5642 */ 5643 if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF)) 5644 kvm_make_request(KVM_REQ_EVENT, vcpu); 5645 } else 5646 vcpu->arch.emulate_regs_need_sync_to_vcpu = true; 5647 5648 return r; 5649 } 5650 EXPORT_SYMBOL_GPL(x86_emulate_instruction); 5651 5652 int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port) 5653 { 5654 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX); 5655 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt, 5656 size, port, &val, 1); 5657 /* do not return to emulator after return from userspace */ 5658 vcpu->arch.pio.count = 0; 5659 return ret; 5660 } 5661 EXPORT_SYMBOL_GPL(kvm_fast_pio_out); 5662 5663 static int complete_fast_pio_in(struct kvm_vcpu *vcpu) 5664 { 5665 unsigned long val; 5666 5667 /* We should only ever be called with arch.pio.count equal to 1 */ 5668 BUG_ON(vcpu->arch.pio.count != 1); 5669 5670 /* For size less than 4 we merge, else we zero extend */ 5671 val = (vcpu->arch.pio.size < 4) ? kvm_register_read(vcpu, VCPU_REGS_RAX) 5672 : 0; 5673 5674 /* 5675 * Since vcpu->arch.pio.count == 1 let emulator_pio_in_emulated perform 5676 * the copy and tracing 5677 */ 5678 emulator_pio_in_emulated(&vcpu->arch.emulate_ctxt, vcpu->arch.pio.size, 5679 vcpu->arch.pio.port, &val, 1); 5680 kvm_register_write(vcpu, VCPU_REGS_RAX, val); 5681 5682 return 1; 5683 } 5684 5685 int kvm_fast_pio_in(struct kvm_vcpu *vcpu, int size, unsigned short port) 5686 { 5687 unsigned long val; 5688 int ret; 5689 5690 /* For size less than 4 we merge, else we zero extend */ 5691 val = (size < 4) ? kvm_register_read(vcpu, VCPU_REGS_RAX) : 0; 5692 5693 ret = emulator_pio_in_emulated(&vcpu->arch.emulate_ctxt, size, port, 5694 &val, 1); 5695 if (ret) { 5696 kvm_register_write(vcpu, VCPU_REGS_RAX, val); 5697 return ret; 5698 } 5699 5700 vcpu->arch.complete_userspace_io = complete_fast_pio_in; 5701 5702 return 0; 5703 } 5704 EXPORT_SYMBOL_GPL(kvm_fast_pio_in); 5705 5706 static int kvmclock_cpu_down_prep(unsigned int cpu) 5707 { 5708 __this_cpu_write(cpu_tsc_khz, 0); 5709 return 0; 5710 } 5711 5712 static void tsc_khz_changed(void *data) 5713 { 5714 struct cpufreq_freqs *freq = data; 5715 unsigned long khz = 0; 5716 5717 if (data) 5718 khz = freq->new; 5719 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) 5720 khz = cpufreq_quick_get(raw_smp_processor_id()); 5721 if (!khz) 5722 khz = tsc_khz; 5723 __this_cpu_write(cpu_tsc_khz, khz); 5724 } 5725 5726 static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val, 5727 void *data) 5728 { 5729 struct cpufreq_freqs *freq = data; 5730 struct kvm *kvm; 5731 struct kvm_vcpu *vcpu; 5732 int i, send_ipi = 0; 5733 5734 /* 5735 * We allow guests to temporarily run on slowing clocks, 5736 * provided we notify them after, or to run on accelerating 5737 * clocks, provided we notify them before. Thus time never 5738 * goes backwards. 5739 * 5740 * However, we have a problem. We can't atomically update 5741 * the frequency of a given CPU from this function; it is 5742 * merely a notifier, which can be called from any CPU. 5743 * Changing the TSC frequency at arbitrary points in time 5744 * requires a recomputation of local variables related to 5745 * the TSC for each VCPU. We must flag these local variables 5746 * to be updated and be sure the update takes place with the 5747 * new frequency before any guests proceed. 5748 * 5749 * Unfortunately, the combination of hotplug CPU and frequency 5750 * change creates an intractable locking scenario; the order 5751 * of when these callouts happen is undefined with respect to 5752 * CPU hotplug, and they can race with each other. As such, 5753 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is 5754 * undefined; you can actually have a CPU frequency change take 5755 * place in between the computation of X and the setting of the 5756 * variable. To protect against this problem, all updates of 5757 * the per_cpu tsc_khz variable are done in an interrupt 5758 * protected IPI, and all callers wishing to update the value 5759 * must wait for a synchronous IPI to complete (which is trivial 5760 * if the caller is on the CPU already). This establishes the 5761 * necessary total order on variable updates. 5762 * 5763 * Note that because a guest time update may take place 5764 * anytime after the setting of the VCPU's request bit, the 5765 * correct TSC value must be set before the request. However, 5766 * to ensure the update actually makes it to any guest which 5767 * starts running in hardware virtualization between the set 5768 * and the acquisition of the spinlock, we must also ping the 5769 * CPU after setting the request bit. 5770 * 5771 */ 5772 5773 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new) 5774 return 0; 5775 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new) 5776 return 0; 5777 5778 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1); 5779 5780 spin_lock(&kvm_lock); 5781 list_for_each_entry(kvm, &vm_list, vm_list) { 5782 kvm_for_each_vcpu(i, vcpu, kvm) { 5783 if (vcpu->cpu != freq->cpu) 5784 continue; 5785 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 5786 if (vcpu->cpu != smp_processor_id()) 5787 send_ipi = 1; 5788 } 5789 } 5790 spin_unlock(&kvm_lock); 5791 5792 if (freq->old < freq->new && send_ipi) { 5793 /* 5794 * We upscale the frequency. Must make the guest 5795 * doesn't see old kvmclock values while running with 5796 * the new frequency, otherwise we risk the guest sees 5797 * time go backwards. 5798 * 5799 * In case we update the frequency for another cpu 5800 * (which might be in guest context) send an interrupt 5801 * to kick the cpu out of guest context. Next time 5802 * guest context is entered kvmclock will be updated, 5803 * so the guest will not see stale values. 5804 */ 5805 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1); 5806 } 5807 return 0; 5808 } 5809 5810 static struct notifier_block kvmclock_cpufreq_notifier_block = { 5811 .notifier_call = kvmclock_cpufreq_notifier 5812 }; 5813 5814 static int kvmclock_cpu_online(unsigned int cpu) 5815 { 5816 tsc_khz_changed(NULL); 5817 return 0; 5818 } 5819 5820 static void kvm_timer_init(void) 5821 { 5822 max_tsc_khz = tsc_khz; 5823 5824 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) { 5825 #ifdef CONFIG_CPU_FREQ 5826 struct cpufreq_policy policy; 5827 int cpu; 5828 5829 memset(&policy, 0, sizeof(policy)); 5830 cpu = get_cpu(); 5831 cpufreq_get_policy(&policy, cpu); 5832 if (policy.cpuinfo.max_freq) 5833 max_tsc_khz = policy.cpuinfo.max_freq; 5834 put_cpu(); 5835 #endif 5836 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block, 5837 CPUFREQ_TRANSITION_NOTIFIER); 5838 } 5839 pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz); 5840 5841 cpuhp_setup_state(CPUHP_AP_X86_KVM_CLK_ONLINE, "AP_X86_KVM_CLK_ONLINE", 5842 kvmclock_cpu_online, kvmclock_cpu_down_prep); 5843 } 5844 5845 static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu); 5846 5847 int kvm_is_in_guest(void) 5848 { 5849 return __this_cpu_read(current_vcpu) != NULL; 5850 } 5851 5852 static int kvm_is_user_mode(void) 5853 { 5854 int user_mode = 3; 5855 5856 if (__this_cpu_read(current_vcpu)) 5857 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu)); 5858 5859 return user_mode != 0; 5860 } 5861 5862 static unsigned long kvm_get_guest_ip(void) 5863 { 5864 unsigned long ip = 0; 5865 5866 if (__this_cpu_read(current_vcpu)) 5867 ip = kvm_rip_read(__this_cpu_read(current_vcpu)); 5868 5869 return ip; 5870 } 5871 5872 static struct perf_guest_info_callbacks kvm_guest_cbs = { 5873 .is_in_guest = kvm_is_in_guest, 5874 .is_user_mode = kvm_is_user_mode, 5875 .get_guest_ip = kvm_get_guest_ip, 5876 }; 5877 5878 void kvm_before_handle_nmi(struct kvm_vcpu *vcpu) 5879 { 5880 __this_cpu_write(current_vcpu, vcpu); 5881 } 5882 EXPORT_SYMBOL_GPL(kvm_before_handle_nmi); 5883 5884 void kvm_after_handle_nmi(struct kvm_vcpu *vcpu) 5885 { 5886 __this_cpu_write(current_vcpu, NULL); 5887 } 5888 EXPORT_SYMBOL_GPL(kvm_after_handle_nmi); 5889 5890 static void kvm_set_mmio_spte_mask(void) 5891 { 5892 u64 mask; 5893 int maxphyaddr = boot_cpu_data.x86_phys_bits; 5894 5895 /* 5896 * Set the reserved bits and the present bit of an paging-structure 5897 * entry to generate page fault with PFER.RSV = 1. 5898 */ 5899 /* Mask the reserved physical address bits. */ 5900 mask = rsvd_bits(maxphyaddr, 51); 5901 5902 /* Bit 62 is always reserved for 32bit host. */ 5903 mask |= 0x3ull << 62; 5904 5905 /* Set the present bit. */ 5906 mask |= 1ull; 5907 5908 #ifdef CONFIG_X86_64 5909 /* 5910 * If reserved bit is not supported, clear the present bit to disable 5911 * mmio page fault. 5912 */ 5913 if (maxphyaddr == 52) 5914 mask &= ~1ull; 5915 #endif 5916 5917 kvm_mmu_set_mmio_spte_mask(mask); 5918 } 5919 5920 #ifdef CONFIG_X86_64 5921 static void pvclock_gtod_update_fn(struct work_struct *work) 5922 { 5923 struct kvm *kvm; 5924 5925 struct kvm_vcpu *vcpu; 5926 int i; 5927 5928 spin_lock(&kvm_lock); 5929 list_for_each_entry(kvm, &vm_list, vm_list) 5930 kvm_for_each_vcpu(i, vcpu, kvm) 5931 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu); 5932 atomic_set(&kvm_guest_has_master_clock, 0); 5933 spin_unlock(&kvm_lock); 5934 } 5935 5936 static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn); 5937 5938 /* 5939 * Notification about pvclock gtod data update. 5940 */ 5941 static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused, 5942 void *priv) 5943 { 5944 struct pvclock_gtod_data *gtod = &pvclock_gtod_data; 5945 struct timekeeper *tk = priv; 5946 5947 update_pvclock_gtod(tk); 5948 5949 /* disable master clock if host does not trust, or does not 5950 * use, TSC clocksource 5951 */ 5952 if (gtod->clock.vclock_mode != VCLOCK_TSC && 5953 atomic_read(&kvm_guest_has_master_clock) != 0) 5954 queue_work(system_long_wq, &pvclock_gtod_work); 5955 5956 return 0; 5957 } 5958 5959 static struct notifier_block pvclock_gtod_notifier = { 5960 .notifier_call = pvclock_gtod_notify, 5961 }; 5962 #endif 5963 5964 int kvm_arch_init(void *opaque) 5965 { 5966 int r; 5967 struct kvm_x86_ops *ops = opaque; 5968 5969 if (kvm_x86_ops) { 5970 printk(KERN_ERR "kvm: already loaded the other module\n"); 5971 r = -EEXIST; 5972 goto out; 5973 } 5974 5975 if (!ops->cpu_has_kvm_support()) { 5976 printk(KERN_ERR "kvm: no hardware support\n"); 5977 r = -EOPNOTSUPP; 5978 goto out; 5979 } 5980 if (ops->disabled_by_bios()) { 5981 printk(KERN_ERR "kvm: disabled by bios\n"); 5982 r = -EOPNOTSUPP; 5983 goto out; 5984 } 5985 5986 r = -ENOMEM; 5987 shared_msrs = alloc_percpu(struct kvm_shared_msrs); 5988 if (!shared_msrs) { 5989 printk(KERN_ERR "kvm: failed to allocate percpu kvm_shared_msrs\n"); 5990 goto out; 5991 } 5992 5993 r = kvm_mmu_module_init(); 5994 if (r) 5995 goto out_free_percpu; 5996 5997 kvm_set_mmio_spte_mask(); 5998 5999 kvm_x86_ops = ops; 6000 6001 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK, 6002 PT_DIRTY_MASK, PT64_NX_MASK, 0, 6003 PT_PRESENT_MASK); 6004 kvm_timer_init(); 6005 6006 perf_register_guest_info_callbacks(&kvm_guest_cbs); 6007 6008 if (boot_cpu_has(X86_FEATURE_XSAVE)) 6009 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK); 6010 6011 kvm_lapic_init(); 6012 #ifdef CONFIG_X86_64 6013 pvclock_gtod_register_notifier(&pvclock_gtod_notifier); 6014 #endif 6015 6016 return 0; 6017 6018 out_free_percpu: 6019 free_percpu(shared_msrs); 6020 out: 6021 return r; 6022 } 6023 6024 void kvm_arch_exit(void) 6025 { 6026 perf_unregister_guest_info_callbacks(&kvm_guest_cbs); 6027 6028 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) 6029 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block, 6030 CPUFREQ_TRANSITION_NOTIFIER); 6031 cpuhp_remove_state_nocalls(CPUHP_AP_X86_KVM_CLK_ONLINE); 6032 #ifdef CONFIG_X86_64 6033 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier); 6034 #endif 6035 kvm_x86_ops = NULL; 6036 kvm_mmu_module_exit(); 6037 free_percpu(shared_msrs); 6038 } 6039 6040 int kvm_vcpu_halt(struct kvm_vcpu *vcpu) 6041 { 6042 ++vcpu->stat.halt_exits; 6043 if (lapic_in_kernel(vcpu)) { 6044 vcpu->arch.mp_state = KVM_MP_STATE_HALTED; 6045 return 1; 6046 } else { 6047 vcpu->run->exit_reason = KVM_EXIT_HLT; 6048 return 0; 6049 } 6050 } 6051 EXPORT_SYMBOL_GPL(kvm_vcpu_halt); 6052 6053 int kvm_emulate_halt(struct kvm_vcpu *vcpu) 6054 { 6055 int ret = kvm_skip_emulated_instruction(vcpu); 6056 /* 6057 * TODO: we might be squashing a GUESTDBG_SINGLESTEP-triggered 6058 * KVM_EXIT_DEBUG here. 6059 */ 6060 return kvm_vcpu_halt(vcpu) && ret; 6061 } 6062 EXPORT_SYMBOL_GPL(kvm_emulate_halt); 6063 6064 /* 6065 * kvm_pv_kick_cpu_op: Kick a vcpu. 6066 * 6067 * @apicid - apicid of vcpu to be kicked. 6068 */ 6069 static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid) 6070 { 6071 struct kvm_lapic_irq lapic_irq; 6072 6073 lapic_irq.shorthand = 0; 6074 lapic_irq.dest_mode = 0; 6075 lapic_irq.dest_id = apicid; 6076 lapic_irq.msi_redir_hint = false; 6077 6078 lapic_irq.delivery_mode = APIC_DM_REMRD; 6079 kvm_irq_delivery_to_apic(kvm, NULL, &lapic_irq, NULL); 6080 } 6081 6082 void kvm_vcpu_deactivate_apicv(struct kvm_vcpu *vcpu) 6083 { 6084 vcpu->arch.apicv_active = false; 6085 kvm_x86_ops->refresh_apicv_exec_ctrl(vcpu); 6086 } 6087 6088 int kvm_emulate_hypercall(struct kvm_vcpu *vcpu) 6089 { 6090 unsigned long nr, a0, a1, a2, a3, ret; 6091 int op_64_bit, r; 6092 6093 r = kvm_skip_emulated_instruction(vcpu); 6094 6095 if (kvm_hv_hypercall_enabled(vcpu->kvm)) 6096 return kvm_hv_hypercall(vcpu); 6097 6098 nr = kvm_register_read(vcpu, VCPU_REGS_RAX); 6099 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX); 6100 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX); 6101 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX); 6102 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI); 6103 6104 trace_kvm_hypercall(nr, a0, a1, a2, a3); 6105 6106 op_64_bit = is_64_bit_mode(vcpu); 6107 if (!op_64_bit) { 6108 nr &= 0xFFFFFFFF; 6109 a0 &= 0xFFFFFFFF; 6110 a1 &= 0xFFFFFFFF; 6111 a2 &= 0xFFFFFFFF; 6112 a3 &= 0xFFFFFFFF; 6113 } 6114 6115 if (kvm_x86_ops->get_cpl(vcpu) != 0) { 6116 ret = -KVM_EPERM; 6117 goto out; 6118 } 6119 6120 switch (nr) { 6121 case KVM_HC_VAPIC_POLL_IRQ: 6122 ret = 0; 6123 break; 6124 case KVM_HC_KICK_CPU: 6125 kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1); 6126 ret = 0; 6127 break; 6128 default: 6129 ret = -KVM_ENOSYS; 6130 break; 6131 } 6132 out: 6133 if (!op_64_bit) 6134 ret = (u32)ret; 6135 kvm_register_write(vcpu, VCPU_REGS_RAX, ret); 6136 ++vcpu->stat.hypercalls; 6137 return r; 6138 } 6139 EXPORT_SYMBOL_GPL(kvm_emulate_hypercall); 6140 6141 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt) 6142 { 6143 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 6144 char instruction[3]; 6145 unsigned long rip = kvm_rip_read(vcpu); 6146 6147 kvm_x86_ops->patch_hypercall(vcpu, instruction); 6148 6149 return emulator_write_emulated(ctxt, rip, instruction, 3, NULL); 6150 } 6151 6152 static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu) 6153 { 6154 return vcpu->run->request_interrupt_window && 6155 likely(!pic_in_kernel(vcpu->kvm)); 6156 } 6157 6158 static void post_kvm_run_save(struct kvm_vcpu *vcpu) 6159 { 6160 struct kvm_run *kvm_run = vcpu->run; 6161 6162 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0; 6163 kvm_run->flags = is_smm(vcpu) ? KVM_RUN_X86_SMM : 0; 6164 kvm_run->cr8 = kvm_get_cr8(vcpu); 6165 kvm_run->apic_base = kvm_get_apic_base(vcpu); 6166 kvm_run->ready_for_interrupt_injection = 6167 pic_in_kernel(vcpu->kvm) || 6168 kvm_vcpu_ready_for_interrupt_injection(vcpu); 6169 } 6170 6171 static void update_cr8_intercept(struct kvm_vcpu *vcpu) 6172 { 6173 int max_irr, tpr; 6174 6175 if (!kvm_x86_ops->update_cr8_intercept) 6176 return; 6177 6178 if (!lapic_in_kernel(vcpu)) 6179 return; 6180 6181 if (vcpu->arch.apicv_active) 6182 return; 6183 6184 if (!vcpu->arch.apic->vapic_addr) 6185 max_irr = kvm_lapic_find_highest_irr(vcpu); 6186 else 6187 max_irr = -1; 6188 6189 if (max_irr != -1) 6190 max_irr >>= 4; 6191 6192 tpr = kvm_lapic_get_cr8(vcpu); 6193 6194 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr); 6195 } 6196 6197 static int inject_pending_event(struct kvm_vcpu *vcpu, bool req_int_win) 6198 { 6199 int r; 6200 6201 /* try to reinject previous events if any */ 6202 if (vcpu->arch.exception.pending) { 6203 trace_kvm_inj_exception(vcpu->arch.exception.nr, 6204 vcpu->arch.exception.has_error_code, 6205 vcpu->arch.exception.error_code); 6206 6207 if (exception_type(vcpu->arch.exception.nr) == EXCPT_FAULT) 6208 __kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) | 6209 X86_EFLAGS_RF); 6210 6211 if (vcpu->arch.exception.nr == DB_VECTOR && 6212 (vcpu->arch.dr7 & DR7_GD)) { 6213 vcpu->arch.dr7 &= ~DR7_GD; 6214 kvm_update_dr7(vcpu); 6215 } 6216 6217 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr, 6218 vcpu->arch.exception.has_error_code, 6219 vcpu->arch.exception.error_code, 6220 vcpu->arch.exception.reinject); 6221 return 0; 6222 } 6223 6224 if (vcpu->arch.nmi_injected) { 6225 kvm_x86_ops->set_nmi(vcpu); 6226 return 0; 6227 } 6228 6229 if (vcpu->arch.interrupt.pending) { 6230 kvm_x86_ops->set_irq(vcpu); 6231 return 0; 6232 } 6233 6234 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) { 6235 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win); 6236 if (r != 0) 6237 return r; 6238 } 6239 6240 /* try to inject new event if pending */ 6241 if (vcpu->arch.smi_pending && !is_smm(vcpu)) { 6242 vcpu->arch.smi_pending = false; 6243 enter_smm(vcpu); 6244 } else if (vcpu->arch.nmi_pending && kvm_x86_ops->nmi_allowed(vcpu)) { 6245 --vcpu->arch.nmi_pending; 6246 vcpu->arch.nmi_injected = true; 6247 kvm_x86_ops->set_nmi(vcpu); 6248 } else if (kvm_cpu_has_injectable_intr(vcpu)) { 6249 /* 6250 * Because interrupts can be injected asynchronously, we are 6251 * calling check_nested_events again here to avoid a race condition. 6252 * See https://lkml.org/lkml/2014/7/2/60 for discussion about this 6253 * proposal and current concerns. Perhaps we should be setting 6254 * KVM_REQ_EVENT only on certain events and not unconditionally? 6255 */ 6256 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) { 6257 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win); 6258 if (r != 0) 6259 return r; 6260 } 6261 if (kvm_x86_ops->interrupt_allowed(vcpu)) { 6262 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu), 6263 false); 6264 kvm_x86_ops->set_irq(vcpu); 6265 } 6266 } 6267 6268 return 0; 6269 } 6270 6271 static void process_nmi(struct kvm_vcpu *vcpu) 6272 { 6273 unsigned limit = 2; 6274 6275 /* 6276 * x86 is limited to one NMI running, and one NMI pending after it. 6277 * If an NMI is already in progress, limit further NMIs to just one. 6278 * Otherwise, allow two (and we'll inject the first one immediately). 6279 */ 6280 if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected) 6281 limit = 1; 6282 6283 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0); 6284 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit); 6285 kvm_make_request(KVM_REQ_EVENT, vcpu); 6286 } 6287 6288 #define put_smstate(type, buf, offset, val) \ 6289 *(type *)((buf) + (offset) - 0x7e00) = val 6290 6291 static u32 enter_smm_get_segment_flags(struct kvm_segment *seg) 6292 { 6293 u32 flags = 0; 6294 flags |= seg->g << 23; 6295 flags |= seg->db << 22; 6296 flags |= seg->l << 21; 6297 flags |= seg->avl << 20; 6298 flags |= seg->present << 15; 6299 flags |= seg->dpl << 13; 6300 flags |= seg->s << 12; 6301 flags |= seg->type << 8; 6302 return flags; 6303 } 6304 6305 static void enter_smm_save_seg_32(struct kvm_vcpu *vcpu, char *buf, int n) 6306 { 6307 struct kvm_segment seg; 6308 int offset; 6309 6310 kvm_get_segment(vcpu, &seg, n); 6311 put_smstate(u32, buf, 0x7fa8 + n * 4, seg.selector); 6312 6313 if (n < 3) 6314 offset = 0x7f84 + n * 12; 6315 else 6316 offset = 0x7f2c + (n - 3) * 12; 6317 6318 put_smstate(u32, buf, offset + 8, seg.base); 6319 put_smstate(u32, buf, offset + 4, seg.limit); 6320 put_smstate(u32, buf, offset, enter_smm_get_segment_flags(&seg)); 6321 } 6322 6323 #ifdef CONFIG_X86_64 6324 static void enter_smm_save_seg_64(struct kvm_vcpu *vcpu, char *buf, int n) 6325 { 6326 struct kvm_segment seg; 6327 int offset; 6328 u16 flags; 6329 6330 kvm_get_segment(vcpu, &seg, n); 6331 offset = 0x7e00 + n * 16; 6332 6333 flags = enter_smm_get_segment_flags(&seg) >> 8; 6334 put_smstate(u16, buf, offset, seg.selector); 6335 put_smstate(u16, buf, offset + 2, flags); 6336 put_smstate(u32, buf, offset + 4, seg.limit); 6337 put_smstate(u64, buf, offset + 8, seg.base); 6338 } 6339 #endif 6340 6341 static void enter_smm_save_state_32(struct kvm_vcpu *vcpu, char *buf) 6342 { 6343 struct desc_ptr dt; 6344 struct kvm_segment seg; 6345 unsigned long val; 6346 int i; 6347 6348 put_smstate(u32, buf, 0x7ffc, kvm_read_cr0(vcpu)); 6349 put_smstate(u32, buf, 0x7ff8, kvm_read_cr3(vcpu)); 6350 put_smstate(u32, buf, 0x7ff4, kvm_get_rflags(vcpu)); 6351 put_smstate(u32, buf, 0x7ff0, kvm_rip_read(vcpu)); 6352 6353 for (i = 0; i < 8; i++) 6354 put_smstate(u32, buf, 0x7fd0 + i * 4, kvm_register_read(vcpu, i)); 6355 6356 kvm_get_dr(vcpu, 6, &val); 6357 put_smstate(u32, buf, 0x7fcc, (u32)val); 6358 kvm_get_dr(vcpu, 7, &val); 6359 put_smstate(u32, buf, 0x7fc8, (u32)val); 6360 6361 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR); 6362 put_smstate(u32, buf, 0x7fc4, seg.selector); 6363 put_smstate(u32, buf, 0x7f64, seg.base); 6364 put_smstate(u32, buf, 0x7f60, seg.limit); 6365 put_smstate(u32, buf, 0x7f5c, enter_smm_get_segment_flags(&seg)); 6366 6367 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR); 6368 put_smstate(u32, buf, 0x7fc0, seg.selector); 6369 put_smstate(u32, buf, 0x7f80, seg.base); 6370 put_smstate(u32, buf, 0x7f7c, seg.limit); 6371 put_smstate(u32, buf, 0x7f78, enter_smm_get_segment_flags(&seg)); 6372 6373 kvm_x86_ops->get_gdt(vcpu, &dt); 6374 put_smstate(u32, buf, 0x7f74, dt.address); 6375 put_smstate(u32, buf, 0x7f70, dt.size); 6376 6377 kvm_x86_ops->get_idt(vcpu, &dt); 6378 put_smstate(u32, buf, 0x7f58, dt.address); 6379 put_smstate(u32, buf, 0x7f54, dt.size); 6380 6381 for (i = 0; i < 6; i++) 6382 enter_smm_save_seg_32(vcpu, buf, i); 6383 6384 put_smstate(u32, buf, 0x7f14, kvm_read_cr4(vcpu)); 6385 6386 /* revision id */ 6387 put_smstate(u32, buf, 0x7efc, 0x00020000); 6388 put_smstate(u32, buf, 0x7ef8, vcpu->arch.smbase); 6389 } 6390 6391 static void enter_smm_save_state_64(struct kvm_vcpu *vcpu, char *buf) 6392 { 6393 #ifdef CONFIG_X86_64 6394 struct desc_ptr dt; 6395 struct kvm_segment seg; 6396 unsigned long val; 6397 int i; 6398 6399 for (i = 0; i < 16; i++) 6400 put_smstate(u64, buf, 0x7ff8 - i * 8, kvm_register_read(vcpu, i)); 6401 6402 put_smstate(u64, buf, 0x7f78, kvm_rip_read(vcpu)); 6403 put_smstate(u32, buf, 0x7f70, kvm_get_rflags(vcpu)); 6404 6405 kvm_get_dr(vcpu, 6, &val); 6406 put_smstate(u64, buf, 0x7f68, val); 6407 kvm_get_dr(vcpu, 7, &val); 6408 put_smstate(u64, buf, 0x7f60, val); 6409 6410 put_smstate(u64, buf, 0x7f58, kvm_read_cr0(vcpu)); 6411 put_smstate(u64, buf, 0x7f50, kvm_read_cr3(vcpu)); 6412 put_smstate(u64, buf, 0x7f48, kvm_read_cr4(vcpu)); 6413 6414 put_smstate(u32, buf, 0x7f00, vcpu->arch.smbase); 6415 6416 /* revision id */ 6417 put_smstate(u32, buf, 0x7efc, 0x00020064); 6418 6419 put_smstate(u64, buf, 0x7ed0, vcpu->arch.efer); 6420 6421 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR); 6422 put_smstate(u16, buf, 0x7e90, seg.selector); 6423 put_smstate(u16, buf, 0x7e92, enter_smm_get_segment_flags(&seg) >> 8); 6424 put_smstate(u32, buf, 0x7e94, seg.limit); 6425 put_smstate(u64, buf, 0x7e98, seg.base); 6426 6427 kvm_x86_ops->get_idt(vcpu, &dt); 6428 put_smstate(u32, buf, 0x7e84, dt.size); 6429 put_smstate(u64, buf, 0x7e88, dt.address); 6430 6431 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR); 6432 put_smstate(u16, buf, 0x7e70, seg.selector); 6433 put_smstate(u16, buf, 0x7e72, enter_smm_get_segment_flags(&seg) >> 8); 6434 put_smstate(u32, buf, 0x7e74, seg.limit); 6435 put_smstate(u64, buf, 0x7e78, seg.base); 6436 6437 kvm_x86_ops->get_gdt(vcpu, &dt); 6438 put_smstate(u32, buf, 0x7e64, dt.size); 6439 put_smstate(u64, buf, 0x7e68, dt.address); 6440 6441 for (i = 0; i < 6; i++) 6442 enter_smm_save_seg_64(vcpu, buf, i); 6443 #else 6444 WARN_ON_ONCE(1); 6445 #endif 6446 } 6447 6448 static void enter_smm(struct kvm_vcpu *vcpu) 6449 { 6450 struct kvm_segment cs, ds; 6451 struct desc_ptr dt; 6452 char buf[512]; 6453 u32 cr0; 6454 6455 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, true); 6456 vcpu->arch.hflags |= HF_SMM_MASK; 6457 memset(buf, 0, 512); 6458 if (guest_cpuid_has_longmode(vcpu)) 6459 enter_smm_save_state_64(vcpu, buf); 6460 else 6461 enter_smm_save_state_32(vcpu, buf); 6462 6463 kvm_vcpu_write_guest(vcpu, vcpu->arch.smbase + 0xfe00, buf, sizeof(buf)); 6464 6465 if (kvm_x86_ops->get_nmi_mask(vcpu)) 6466 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK; 6467 else 6468 kvm_x86_ops->set_nmi_mask(vcpu, true); 6469 6470 kvm_set_rflags(vcpu, X86_EFLAGS_FIXED); 6471 kvm_rip_write(vcpu, 0x8000); 6472 6473 cr0 = vcpu->arch.cr0 & ~(X86_CR0_PE | X86_CR0_EM | X86_CR0_TS | X86_CR0_PG); 6474 kvm_x86_ops->set_cr0(vcpu, cr0); 6475 vcpu->arch.cr0 = cr0; 6476 6477 kvm_x86_ops->set_cr4(vcpu, 0); 6478 6479 /* Undocumented: IDT limit is set to zero on entry to SMM. */ 6480 dt.address = dt.size = 0; 6481 kvm_x86_ops->set_idt(vcpu, &dt); 6482 6483 __kvm_set_dr(vcpu, 7, DR7_FIXED_1); 6484 6485 cs.selector = (vcpu->arch.smbase >> 4) & 0xffff; 6486 cs.base = vcpu->arch.smbase; 6487 6488 ds.selector = 0; 6489 ds.base = 0; 6490 6491 cs.limit = ds.limit = 0xffffffff; 6492 cs.type = ds.type = 0x3; 6493 cs.dpl = ds.dpl = 0; 6494 cs.db = ds.db = 0; 6495 cs.s = ds.s = 1; 6496 cs.l = ds.l = 0; 6497 cs.g = ds.g = 1; 6498 cs.avl = ds.avl = 0; 6499 cs.present = ds.present = 1; 6500 cs.unusable = ds.unusable = 0; 6501 cs.padding = ds.padding = 0; 6502 6503 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS); 6504 kvm_set_segment(vcpu, &ds, VCPU_SREG_DS); 6505 kvm_set_segment(vcpu, &ds, VCPU_SREG_ES); 6506 kvm_set_segment(vcpu, &ds, VCPU_SREG_FS); 6507 kvm_set_segment(vcpu, &ds, VCPU_SREG_GS); 6508 kvm_set_segment(vcpu, &ds, VCPU_SREG_SS); 6509 6510 if (guest_cpuid_has_longmode(vcpu)) 6511 kvm_x86_ops->set_efer(vcpu, 0); 6512 6513 kvm_update_cpuid(vcpu); 6514 kvm_mmu_reset_context(vcpu); 6515 } 6516 6517 static void process_smi(struct kvm_vcpu *vcpu) 6518 { 6519 vcpu->arch.smi_pending = true; 6520 kvm_make_request(KVM_REQ_EVENT, vcpu); 6521 } 6522 6523 void kvm_make_scan_ioapic_request(struct kvm *kvm) 6524 { 6525 kvm_make_all_cpus_request(kvm, KVM_REQ_SCAN_IOAPIC); 6526 } 6527 6528 static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu) 6529 { 6530 u64 eoi_exit_bitmap[4]; 6531 6532 if (!kvm_apic_hw_enabled(vcpu->arch.apic)) 6533 return; 6534 6535 bitmap_zero(vcpu->arch.ioapic_handled_vectors, 256); 6536 6537 if (irqchip_split(vcpu->kvm)) 6538 kvm_scan_ioapic_routes(vcpu, vcpu->arch.ioapic_handled_vectors); 6539 else { 6540 if (vcpu->arch.apicv_active) 6541 kvm_x86_ops->sync_pir_to_irr(vcpu); 6542 kvm_ioapic_scan_entry(vcpu, vcpu->arch.ioapic_handled_vectors); 6543 } 6544 bitmap_or((ulong *)eoi_exit_bitmap, vcpu->arch.ioapic_handled_vectors, 6545 vcpu_to_synic(vcpu)->vec_bitmap, 256); 6546 kvm_x86_ops->load_eoi_exitmap(vcpu, eoi_exit_bitmap); 6547 } 6548 6549 static void kvm_vcpu_flush_tlb(struct kvm_vcpu *vcpu) 6550 { 6551 ++vcpu->stat.tlb_flush; 6552 kvm_x86_ops->tlb_flush(vcpu); 6553 } 6554 6555 void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu) 6556 { 6557 struct page *page = NULL; 6558 6559 if (!lapic_in_kernel(vcpu)) 6560 return; 6561 6562 if (!kvm_x86_ops->set_apic_access_page_addr) 6563 return; 6564 6565 page = gfn_to_page(vcpu->kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT); 6566 if (is_error_page(page)) 6567 return; 6568 kvm_x86_ops->set_apic_access_page_addr(vcpu, page_to_phys(page)); 6569 6570 /* 6571 * Do not pin apic access page in memory, the MMU notifier 6572 * will call us again if it is migrated or swapped out. 6573 */ 6574 put_page(page); 6575 } 6576 EXPORT_SYMBOL_GPL(kvm_vcpu_reload_apic_access_page); 6577 6578 void kvm_arch_mmu_notifier_invalidate_page(struct kvm *kvm, 6579 unsigned long address) 6580 { 6581 /* 6582 * The physical address of apic access page is stored in the VMCS. 6583 * Update it when it becomes invalid. 6584 */ 6585 if (address == gfn_to_hva(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT)) 6586 kvm_make_all_cpus_request(kvm, KVM_REQ_APIC_PAGE_RELOAD); 6587 } 6588 6589 /* 6590 * Returns 1 to let vcpu_run() continue the guest execution loop without 6591 * exiting to the userspace. Otherwise, the value will be returned to the 6592 * userspace. 6593 */ 6594 static int vcpu_enter_guest(struct kvm_vcpu *vcpu) 6595 { 6596 int r; 6597 bool req_int_win = 6598 dm_request_for_irq_injection(vcpu) && 6599 kvm_cpu_accept_dm_intr(vcpu); 6600 6601 bool req_immediate_exit = false; 6602 6603 if (vcpu->requests) { 6604 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu)) 6605 kvm_mmu_unload(vcpu); 6606 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu)) 6607 __kvm_migrate_timers(vcpu); 6608 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu)) 6609 kvm_gen_update_masterclock(vcpu->kvm); 6610 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu)) 6611 kvm_gen_kvmclock_update(vcpu); 6612 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) { 6613 r = kvm_guest_time_update(vcpu); 6614 if (unlikely(r)) 6615 goto out; 6616 } 6617 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu)) 6618 kvm_mmu_sync_roots(vcpu); 6619 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu)) 6620 kvm_vcpu_flush_tlb(vcpu); 6621 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) { 6622 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS; 6623 r = 0; 6624 goto out; 6625 } 6626 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) { 6627 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN; 6628 r = 0; 6629 goto out; 6630 } 6631 if (kvm_check_request(KVM_REQ_DEACTIVATE_FPU, vcpu)) { 6632 vcpu->fpu_active = 0; 6633 kvm_x86_ops->fpu_deactivate(vcpu); 6634 } 6635 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) { 6636 /* Page is swapped out. Do synthetic halt */ 6637 vcpu->arch.apf.halted = true; 6638 r = 1; 6639 goto out; 6640 } 6641 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu)) 6642 record_steal_time(vcpu); 6643 if (kvm_check_request(KVM_REQ_SMI, vcpu)) 6644 process_smi(vcpu); 6645 if (kvm_check_request(KVM_REQ_NMI, vcpu)) 6646 process_nmi(vcpu); 6647 if (kvm_check_request(KVM_REQ_PMU, vcpu)) 6648 kvm_pmu_handle_event(vcpu); 6649 if (kvm_check_request(KVM_REQ_PMI, vcpu)) 6650 kvm_pmu_deliver_pmi(vcpu); 6651 if (kvm_check_request(KVM_REQ_IOAPIC_EOI_EXIT, vcpu)) { 6652 BUG_ON(vcpu->arch.pending_ioapic_eoi > 255); 6653 if (test_bit(vcpu->arch.pending_ioapic_eoi, 6654 vcpu->arch.ioapic_handled_vectors)) { 6655 vcpu->run->exit_reason = KVM_EXIT_IOAPIC_EOI; 6656 vcpu->run->eoi.vector = 6657 vcpu->arch.pending_ioapic_eoi; 6658 r = 0; 6659 goto out; 6660 } 6661 } 6662 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu)) 6663 vcpu_scan_ioapic(vcpu); 6664 if (kvm_check_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu)) 6665 kvm_vcpu_reload_apic_access_page(vcpu); 6666 if (kvm_check_request(KVM_REQ_HV_CRASH, vcpu)) { 6667 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT; 6668 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_CRASH; 6669 r = 0; 6670 goto out; 6671 } 6672 if (kvm_check_request(KVM_REQ_HV_RESET, vcpu)) { 6673 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT; 6674 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_RESET; 6675 r = 0; 6676 goto out; 6677 } 6678 if (kvm_check_request(KVM_REQ_HV_EXIT, vcpu)) { 6679 vcpu->run->exit_reason = KVM_EXIT_HYPERV; 6680 vcpu->run->hyperv = vcpu->arch.hyperv.exit; 6681 r = 0; 6682 goto out; 6683 } 6684 6685 /* 6686 * KVM_REQ_HV_STIMER has to be processed after 6687 * KVM_REQ_CLOCK_UPDATE, because Hyper-V SynIC timers 6688 * depend on the guest clock being up-to-date 6689 */ 6690 if (kvm_check_request(KVM_REQ_HV_STIMER, vcpu)) 6691 kvm_hv_process_stimers(vcpu); 6692 } 6693 6694 /* 6695 * KVM_REQ_EVENT is not set when posted interrupts are set by 6696 * VT-d hardware, so we have to update RVI unconditionally. 6697 */ 6698 if (kvm_lapic_enabled(vcpu)) { 6699 /* 6700 * Update architecture specific hints for APIC 6701 * virtual interrupt delivery. 6702 */ 6703 if (vcpu->arch.apicv_active) 6704 kvm_x86_ops->hwapic_irr_update(vcpu, 6705 kvm_lapic_find_highest_irr(vcpu)); 6706 } 6707 6708 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) { 6709 kvm_apic_accept_events(vcpu); 6710 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) { 6711 r = 1; 6712 goto out; 6713 } 6714 6715 if (inject_pending_event(vcpu, req_int_win) != 0) 6716 req_immediate_exit = true; 6717 else { 6718 /* Enable NMI/IRQ window open exits if needed. 6719 * 6720 * SMIs have two cases: 1) they can be nested, and 6721 * then there is nothing to do here because RSM will 6722 * cause a vmexit anyway; 2) or the SMI can be pending 6723 * because inject_pending_event has completed the 6724 * injection of an IRQ or NMI from the previous vmexit, 6725 * and then we request an immediate exit to inject the SMI. 6726 */ 6727 if (vcpu->arch.smi_pending && !is_smm(vcpu)) 6728 req_immediate_exit = true; 6729 if (vcpu->arch.nmi_pending) 6730 kvm_x86_ops->enable_nmi_window(vcpu); 6731 if (kvm_cpu_has_injectable_intr(vcpu) || req_int_win) 6732 kvm_x86_ops->enable_irq_window(vcpu); 6733 } 6734 6735 if (kvm_lapic_enabled(vcpu)) { 6736 update_cr8_intercept(vcpu); 6737 kvm_lapic_sync_to_vapic(vcpu); 6738 } 6739 } 6740 6741 r = kvm_mmu_reload(vcpu); 6742 if (unlikely(r)) { 6743 goto cancel_injection; 6744 } 6745 6746 preempt_disable(); 6747 6748 kvm_x86_ops->prepare_guest_switch(vcpu); 6749 if (vcpu->fpu_active) 6750 kvm_load_guest_fpu(vcpu); 6751 vcpu->mode = IN_GUEST_MODE; 6752 6753 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx); 6754 6755 /* 6756 * We should set ->mode before check ->requests, 6757 * Please see the comment in kvm_make_all_cpus_request. 6758 * This also orders the write to mode from any reads 6759 * to the page tables done while the VCPU is running. 6760 * Please see the comment in kvm_flush_remote_tlbs. 6761 */ 6762 smp_mb__after_srcu_read_unlock(); 6763 6764 local_irq_disable(); 6765 6766 if (vcpu->mode == EXITING_GUEST_MODE || vcpu->requests 6767 || need_resched() || signal_pending(current)) { 6768 vcpu->mode = OUTSIDE_GUEST_MODE; 6769 smp_wmb(); 6770 local_irq_enable(); 6771 preempt_enable(); 6772 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu); 6773 r = 1; 6774 goto cancel_injection; 6775 } 6776 6777 kvm_load_guest_xcr0(vcpu); 6778 6779 if (req_immediate_exit) { 6780 kvm_make_request(KVM_REQ_EVENT, vcpu); 6781 smp_send_reschedule(vcpu->cpu); 6782 } 6783 6784 trace_kvm_entry(vcpu->vcpu_id); 6785 wait_lapic_expire(vcpu); 6786 guest_enter_irqoff(); 6787 6788 if (unlikely(vcpu->arch.switch_db_regs)) { 6789 set_debugreg(0, 7); 6790 set_debugreg(vcpu->arch.eff_db[0], 0); 6791 set_debugreg(vcpu->arch.eff_db[1], 1); 6792 set_debugreg(vcpu->arch.eff_db[2], 2); 6793 set_debugreg(vcpu->arch.eff_db[3], 3); 6794 set_debugreg(vcpu->arch.dr6, 6); 6795 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD; 6796 } 6797 6798 kvm_x86_ops->run(vcpu); 6799 6800 /* 6801 * Do this here before restoring debug registers on the host. And 6802 * since we do this before handling the vmexit, a DR access vmexit 6803 * can (a) read the correct value of the debug registers, (b) set 6804 * KVM_DEBUGREG_WONT_EXIT again. 6805 */ 6806 if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) { 6807 WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP); 6808 kvm_x86_ops->sync_dirty_debug_regs(vcpu); 6809 kvm_update_dr0123(vcpu); 6810 kvm_update_dr6(vcpu); 6811 kvm_update_dr7(vcpu); 6812 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD; 6813 } 6814 6815 /* 6816 * If the guest has used debug registers, at least dr7 6817 * will be disabled while returning to the host. 6818 * If we don't have active breakpoints in the host, we don't 6819 * care about the messed up debug address registers. But if 6820 * we have some of them active, restore the old state. 6821 */ 6822 if (hw_breakpoint_active()) 6823 hw_breakpoint_restore(); 6824 6825 vcpu->arch.last_guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc()); 6826 6827 vcpu->mode = OUTSIDE_GUEST_MODE; 6828 smp_wmb(); 6829 6830 kvm_put_guest_xcr0(vcpu); 6831 6832 kvm_x86_ops->handle_external_intr(vcpu); 6833 6834 ++vcpu->stat.exits; 6835 6836 guest_exit_irqoff(); 6837 6838 local_irq_enable(); 6839 preempt_enable(); 6840 6841 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu); 6842 6843 /* 6844 * Profile KVM exit RIPs: 6845 */ 6846 if (unlikely(prof_on == KVM_PROFILING)) { 6847 unsigned long rip = kvm_rip_read(vcpu); 6848 profile_hit(KVM_PROFILING, (void *)rip); 6849 } 6850 6851 if (unlikely(vcpu->arch.tsc_always_catchup)) 6852 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 6853 6854 if (vcpu->arch.apic_attention) 6855 kvm_lapic_sync_from_vapic(vcpu); 6856 6857 r = kvm_x86_ops->handle_exit(vcpu); 6858 return r; 6859 6860 cancel_injection: 6861 kvm_x86_ops->cancel_injection(vcpu); 6862 if (unlikely(vcpu->arch.apic_attention)) 6863 kvm_lapic_sync_from_vapic(vcpu); 6864 out: 6865 return r; 6866 } 6867 6868 static inline int vcpu_block(struct kvm *kvm, struct kvm_vcpu *vcpu) 6869 { 6870 if (!kvm_arch_vcpu_runnable(vcpu) && 6871 (!kvm_x86_ops->pre_block || kvm_x86_ops->pre_block(vcpu) == 0)) { 6872 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx); 6873 kvm_vcpu_block(vcpu); 6874 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu); 6875 6876 if (kvm_x86_ops->post_block) 6877 kvm_x86_ops->post_block(vcpu); 6878 6879 if (!kvm_check_request(KVM_REQ_UNHALT, vcpu)) 6880 return 1; 6881 } 6882 6883 kvm_apic_accept_events(vcpu); 6884 switch(vcpu->arch.mp_state) { 6885 case KVM_MP_STATE_HALTED: 6886 vcpu->arch.pv.pv_unhalted = false; 6887 vcpu->arch.mp_state = 6888 KVM_MP_STATE_RUNNABLE; 6889 case KVM_MP_STATE_RUNNABLE: 6890 vcpu->arch.apf.halted = false; 6891 break; 6892 case KVM_MP_STATE_INIT_RECEIVED: 6893 break; 6894 default: 6895 return -EINTR; 6896 break; 6897 } 6898 return 1; 6899 } 6900 6901 static inline bool kvm_vcpu_running(struct kvm_vcpu *vcpu) 6902 { 6903 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE && 6904 !vcpu->arch.apf.halted); 6905 } 6906 6907 static int vcpu_run(struct kvm_vcpu *vcpu) 6908 { 6909 int r; 6910 struct kvm *kvm = vcpu->kvm; 6911 6912 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu); 6913 6914 for (;;) { 6915 if (kvm_vcpu_running(vcpu)) { 6916 r = vcpu_enter_guest(vcpu); 6917 } else { 6918 r = vcpu_block(kvm, vcpu); 6919 } 6920 6921 if (r <= 0) 6922 break; 6923 6924 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests); 6925 if (kvm_cpu_has_pending_timer(vcpu)) 6926 kvm_inject_pending_timer_irqs(vcpu); 6927 6928 if (dm_request_for_irq_injection(vcpu) && 6929 kvm_vcpu_ready_for_interrupt_injection(vcpu)) { 6930 r = 0; 6931 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN; 6932 ++vcpu->stat.request_irq_exits; 6933 break; 6934 } 6935 6936 kvm_check_async_pf_completion(vcpu); 6937 6938 if (signal_pending(current)) { 6939 r = -EINTR; 6940 vcpu->run->exit_reason = KVM_EXIT_INTR; 6941 ++vcpu->stat.signal_exits; 6942 break; 6943 } 6944 if (need_resched()) { 6945 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx); 6946 cond_resched(); 6947 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu); 6948 } 6949 } 6950 6951 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx); 6952 6953 return r; 6954 } 6955 6956 static inline int complete_emulated_io(struct kvm_vcpu *vcpu) 6957 { 6958 int r; 6959 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu); 6960 r = emulate_instruction(vcpu, EMULTYPE_NO_DECODE); 6961 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx); 6962 if (r != EMULATE_DONE) 6963 return 0; 6964 return 1; 6965 } 6966 6967 static int complete_emulated_pio(struct kvm_vcpu *vcpu) 6968 { 6969 BUG_ON(!vcpu->arch.pio.count); 6970 6971 return complete_emulated_io(vcpu); 6972 } 6973 6974 /* 6975 * Implements the following, as a state machine: 6976 * 6977 * read: 6978 * for each fragment 6979 * for each mmio piece in the fragment 6980 * write gpa, len 6981 * exit 6982 * copy data 6983 * execute insn 6984 * 6985 * write: 6986 * for each fragment 6987 * for each mmio piece in the fragment 6988 * write gpa, len 6989 * copy data 6990 * exit 6991 */ 6992 static int complete_emulated_mmio(struct kvm_vcpu *vcpu) 6993 { 6994 struct kvm_run *run = vcpu->run; 6995 struct kvm_mmio_fragment *frag; 6996 unsigned len; 6997 6998 BUG_ON(!vcpu->mmio_needed); 6999 7000 /* Complete previous fragment */ 7001 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment]; 7002 len = min(8u, frag->len); 7003 if (!vcpu->mmio_is_write) 7004 memcpy(frag->data, run->mmio.data, len); 7005 7006 if (frag->len <= 8) { 7007 /* Switch to the next fragment. */ 7008 frag++; 7009 vcpu->mmio_cur_fragment++; 7010 } else { 7011 /* Go forward to the next mmio piece. */ 7012 frag->data += len; 7013 frag->gpa += len; 7014 frag->len -= len; 7015 } 7016 7017 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) { 7018 vcpu->mmio_needed = 0; 7019 7020 /* FIXME: return into emulator if single-stepping. */ 7021 if (vcpu->mmio_is_write) 7022 return 1; 7023 vcpu->mmio_read_completed = 1; 7024 return complete_emulated_io(vcpu); 7025 } 7026 7027 run->exit_reason = KVM_EXIT_MMIO; 7028 run->mmio.phys_addr = frag->gpa; 7029 if (vcpu->mmio_is_write) 7030 memcpy(run->mmio.data, frag->data, min(8u, frag->len)); 7031 run->mmio.len = min(8u, frag->len); 7032 run->mmio.is_write = vcpu->mmio_is_write; 7033 vcpu->arch.complete_userspace_io = complete_emulated_mmio; 7034 return 0; 7035 } 7036 7037 7038 int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) 7039 { 7040 struct fpu *fpu = ¤t->thread.fpu; 7041 int r; 7042 sigset_t sigsaved; 7043 7044 fpu__activate_curr(fpu); 7045 7046 if (vcpu->sigset_active) 7047 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved); 7048 7049 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) { 7050 kvm_vcpu_block(vcpu); 7051 kvm_apic_accept_events(vcpu); 7052 clear_bit(KVM_REQ_UNHALT, &vcpu->requests); 7053 r = -EAGAIN; 7054 goto out; 7055 } 7056 7057 /* re-sync apic's tpr */ 7058 if (!lapic_in_kernel(vcpu)) { 7059 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) { 7060 r = -EINVAL; 7061 goto out; 7062 } 7063 } 7064 7065 if (unlikely(vcpu->arch.complete_userspace_io)) { 7066 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io; 7067 vcpu->arch.complete_userspace_io = NULL; 7068 r = cui(vcpu); 7069 if (r <= 0) 7070 goto out; 7071 } else 7072 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed); 7073 7074 r = vcpu_run(vcpu); 7075 7076 out: 7077 post_kvm_run_save(vcpu); 7078 if (vcpu->sigset_active) 7079 sigprocmask(SIG_SETMASK, &sigsaved, NULL); 7080 7081 return r; 7082 } 7083 7084 int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) 7085 { 7086 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) { 7087 /* 7088 * We are here if userspace calls get_regs() in the middle of 7089 * instruction emulation. Registers state needs to be copied 7090 * back from emulation context to vcpu. Userspace shouldn't do 7091 * that usually, but some bad designed PV devices (vmware 7092 * backdoor interface) need this to work 7093 */ 7094 emulator_writeback_register_cache(&vcpu->arch.emulate_ctxt); 7095 vcpu->arch.emulate_regs_need_sync_to_vcpu = false; 7096 } 7097 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX); 7098 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX); 7099 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX); 7100 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX); 7101 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI); 7102 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI); 7103 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP); 7104 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP); 7105 #ifdef CONFIG_X86_64 7106 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8); 7107 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9); 7108 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10); 7109 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11); 7110 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12); 7111 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13); 7112 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14); 7113 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15); 7114 #endif 7115 7116 regs->rip = kvm_rip_read(vcpu); 7117 regs->rflags = kvm_get_rflags(vcpu); 7118 7119 return 0; 7120 } 7121 7122 int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) 7123 { 7124 vcpu->arch.emulate_regs_need_sync_from_vcpu = true; 7125 vcpu->arch.emulate_regs_need_sync_to_vcpu = false; 7126 7127 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax); 7128 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx); 7129 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx); 7130 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx); 7131 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi); 7132 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi); 7133 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp); 7134 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp); 7135 #ifdef CONFIG_X86_64 7136 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8); 7137 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9); 7138 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10); 7139 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11); 7140 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12); 7141 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13); 7142 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14); 7143 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15); 7144 #endif 7145 7146 kvm_rip_write(vcpu, regs->rip); 7147 kvm_set_rflags(vcpu, regs->rflags); 7148 7149 vcpu->arch.exception.pending = false; 7150 7151 kvm_make_request(KVM_REQ_EVENT, vcpu); 7152 7153 return 0; 7154 } 7155 7156 void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l) 7157 { 7158 struct kvm_segment cs; 7159 7160 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS); 7161 *db = cs.db; 7162 *l = cs.l; 7163 } 7164 EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits); 7165 7166 int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu, 7167 struct kvm_sregs *sregs) 7168 { 7169 struct desc_ptr dt; 7170 7171 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS); 7172 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS); 7173 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES); 7174 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS); 7175 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS); 7176 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS); 7177 7178 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR); 7179 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR); 7180 7181 kvm_x86_ops->get_idt(vcpu, &dt); 7182 sregs->idt.limit = dt.size; 7183 sregs->idt.base = dt.address; 7184 kvm_x86_ops->get_gdt(vcpu, &dt); 7185 sregs->gdt.limit = dt.size; 7186 sregs->gdt.base = dt.address; 7187 7188 sregs->cr0 = kvm_read_cr0(vcpu); 7189 sregs->cr2 = vcpu->arch.cr2; 7190 sregs->cr3 = kvm_read_cr3(vcpu); 7191 sregs->cr4 = kvm_read_cr4(vcpu); 7192 sregs->cr8 = kvm_get_cr8(vcpu); 7193 sregs->efer = vcpu->arch.efer; 7194 sregs->apic_base = kvm_get_apic_base(vcpu); 7195 7196 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap); 7197 7198 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft) 7199 set_bit(vcpu->arch.interrupt.nr, 7200 (unsigned long *)sregs->interrupt_bitmap); 7201 7202 return 0; 7203 } 7204 7205 int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu, 7206 struct kvm_mp_state *mp_state) 7207 { 7208 kvm_apic_accept_events(vcpu); 7209 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED && 7210 vcpu->arch.pv.pv_unhalted) 7211 mp_state->mp_state = KVM_MP_STATE_RUNNABLE; 7212 else 7213 mp_state->mp_state = vcpu->arch.mp_state; 7214 7215 return 0; 7216 } 7217 7218 int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu, 7219 struct kvm_mp_state *mp_state) 7220 { 7221 if (!lapic_in_kernel(vcpu) && 7222 mp_state->mp_state != KVM_MP_STATE_RUNNABLE) 7223 return -EINVAL; 7224 7225 if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) { 7226 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED; 7227 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events); 7228 } else 7229 vcpu->arch.mp_state = mp_state->mp_state; 7230 kvm_make_request(KVM_REQ_EVENT, vcpu); 7231 return 0; 7232 } 7233 7234 int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index, 7235 int reason, bool has_error_code, u32 error_code) 7236 { 7237 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt; 7238 int ret; 7239 7240 init_emulate_ctxt(vcpu); 7241 7242 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason, 7243 has_error_code, error_code); 7244 7245 if (ret) 7246 return EMULATE_FAIL; 7247 7248 kvm_rip_write(vcpu, ctxt->eip); 7249 kvm_set_rflags(vcpu, ctxt->eflags); 7250 kvm_make_request(KVM_REQ_EVENT, vcpu); 7251 return EMULATE_DONE; 7252 } 7253 EXPORT_SYMBOL_GPL(kvm_task_switch); 7254 7255 int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu, 7256 struct kvm_sregs *sregs) 7257 { 7258 struct msr_data apic_base_msr; 7259 int mmu_reset_needed = 0; 7260 int pending_vec, max_bits, idx; 7261 struct desc_ptr dt; 7262 7263 if (!guest_cpuid_has_xsave(vcpu) && (sregs->cr4 & X86_CR4_OSXSAVE)) 7264 return -EINVAL; 7265 7266 dt.size = sregs->idt.limit; 7267 dt.address = sregs->idt.base; 7268 kvm_x86_ops->set_idt(vcpu, &dt); 7269 dt.size = sregs->gdt.limit; 7270 dt.address = sregs->gdt.base; 7271 kvm_x86_ops->set_gdt(vcpu, &dt); 7272 7273 vcpu->arch.cr2 = sregs->cr2; 7274 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3; 7275 vcpu->arch.cr3 = sregs->cr3; 7276 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail); 7277 7278 kvm_set_cr8(vcpu, sregs->cr8); 7279 7280 mmu_reset_needed |= vcpu->arch.efer != sregs->efer; 7281 kvm_x86_ops->set_efer(vcpu, sregs->efer); 7282 apic_base_msr.data = sregs->apic_base; 7283 apic_base_msr.host_initiated = true; 7284 kvm_set_apic_base(vcpu, &apic_base_msr); 7285 7286 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0; 7287 kvm_x86_ops->set_cr0(vcpu, sregs->cr0); 7288 vcpu->arch.cr0 = sregs->cr0; 7289 7290 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4; 7291 kvm_x86_ops->set_cr4(vcpu, sregs->cr4); 7292 if (sregs->cr4 & (X86_CR4_OSXSAVE | X86_CR4_PKE)) 7293 kvm_update_cpuid(vcpu); 7294 7295 idx = srcu_read_lock(&vcpu->kvm->srcu); 7296 if (!is_long_mode(vcpu) && is_pae(vcpu)) { 7297 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu)); 7298 mmu_reset_needed = 1; 7299 } 7300 srcu_read_unlock(&vcpu->kvm->srcu, idx); 7301 7302 if (mmu_reset_needed) 7303 kvm_mmu_reset_context(vcpu); 7304 7305 max_bits = KVM_NR_INTERRUPTS; 7306 pending_vec = find_first_bit( 7307 (const unsigned long *)sregs->interrupt_bitmap, max_bits); 7308 if (pending_vec < max_bits) { 7309 kvm_queue_interrupt(vcpu, pending_vec, false); 7310 pr_debug("Set back pending irq %d\n", pending_vec); 7311 } 7312 7313 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS); 7314 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS); 7315 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES); 7316 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS); 7317 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS); 7318 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS); 7319 7320 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR); 7321 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR); 7322 7323 update_cr8_intercept(vcpu); 7324 7325 /* Older userspace won't unhalt the vcpu on reset. */ 7326 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 && 7327 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 && 7328 !is_protmode(vcpu)) 7329 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; 7330 7331 kvm_make_request(KVM_REQ_EVENT, vcpu); 7332 7333 return 0; 7334 } 7335 7336 int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu, 7337 struct kvm_guest_debug *dbg) 7338 { 7339 unsigned long rflags; 7340 int i, r; 7341 7342 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) { 7343 r = -EBUSY; 7344 if (vcpu->arch.exception.pending) 7345 goto out; 7346 if (dbg->control & KVM_GUESTDBG_INJECT_DB) 7347 kvm_queue_exception(vcpu, DB_VECTOR); 7348 else 7349 kvm_queue_exception(vcpu, BP_VECTOR); 7350 } 7351 7352 /* 7353 * Read rflags as long as potentially injected trace flags are still 7354 * filtered out. 7355 */ 7356 rflags = kvm_get_rflags(vcpu); 7357 7358 vcpu->guest_debug = dbg->control; 7359 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE)) 7360 vcpu->guest_debug = 0; 7361 7362 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) { 7363 for (i = 0; i < KVM_NR_DB_REGS; ++i) 7364 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i]; 7365 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7]; 7366 } else { 7367 for (i = 0; i < KVM_NR_DB_REGS; i++) 7368 vcpu->arch.eff_db[i] = vcpu->arch.db[i]; 7369 } 7370 kvm_update_dr7(vcpu); 7371 7372 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) 7373 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) + 7374 get_segment_base(vcpu, VCPU_SREG_CS); 7375 7376 /* 7377 * Trigger an rflags update that will inject or remove the trace 7378 * flags. 7379 */ 7380 kvm_set_rflags(vcpu, rflags); 7381 7382 kvm_x86_ops->update_bp_intercept(vcpu); 7383 7384 r = 0; 7385 7386 out: 7387 7388 return r; 7389 } 7390 7391 /* 7392 * Translate a guest virtual address to a guest physical address. 7393 */ 7394 int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu, 7395 struct kvm_translation *tr) 7396 { 7397 unsigned long vaddr = tr->linear_address; 7398 gpa_t gpa; 7399 int idx; 7400 7401 idx = srcu_read_lock(&vcpu->kvm->srcu); 7402 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL); 7403 srcu_read_unlock(&vcpu->kvm->srcu, idx); 7404 tr->physical_address = gpa; 7405 tr->valid = gpa != UNMAPPED_GVA; 7406 tr->writeable = 1; 7407 tr->usermode = 0; 7408 7409 return 0; 7410 } 7411 7412 int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu) 7413 { 7414 struct fxregs_state *fxsave = 7415 &vcpu->arch.guest_fpu.state.fxsave; 7416 7417 memcpy(fpu->fpr, fxsave->st_space, 128); 7418 fpu->fcw = fxsave->cwd; 7419 fpu->fsw = fxsave->swd; 7420 fpu->ftwx = fxsave->twd; 7421 fpu->last_opcode = fxsave->fop; 7422 fpu->last_ip = fxsave->rip; 7423 fpu->last_dp = fxsave->rdp; 7424 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space); 7425 7426 return 0; 7427 } 7428 7429 int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu) 7430 { 7431 struct fxregs_state *fxsave = 7432 &vcpu->arch.guest_fpu.state.fxsave; 7433 7434 memcpy(fxsave->st_space, fpu->fpr, 128); 7435 fxsave->cwd = fpu->fcw; 7436 fxsave->swd = fpu->fsw; 7437 fxsave->twd = fpu->ftwx; 7438 fxsave->fop = fpu->last_opcode; 7439 fxsave->rip = fpu->last_ip; 7440 fxsave->rdp = fpu->last_dp; 7441 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space); 7442 7443 return 0; 7444 } 7445 7446 static void fx_init(struct kvm_vcpu *vcpu) 7447 { 7448 fpstate_init(&vcpu->arch.guest_fpu.state); 7449 if (boot_cpu_has(X86_FEATURE_XSAVES)) 7450 vcpu->arch.guest_fpu.state.xsave.header.xcomp_bv = 7451 host_xcr0 | XSTATE_COMPACTION_ENABLED; 7452 7453 /* 7454 * Ensure guest xcr0 is valid for loading 7455 */ 7456 vcpu->arch.xcr0 = XFEATURE_MASK_FP; 7457 7458 vcpu->arch.cr0 |= X86_CR0_ET; 7459 } 7460 7461 void kvm_load_guest_fpu(struct kvm_vcpu *vcpu) 7462 { 7463 if (vcpu->guest_fpu_loaded) 7464 return; 7465 7466 /* 7467 * Restore all possible states in the guest, 7468 * and assume host would use all available bits. 7469 * Guest xcr0 would be loaded later. 7470 */ 7471 vcpu->guest_fpu_loaded = 1; 7472 __kernel_fpu_begin(); 7473 __copy_kernel_to_fpregs(&vcpu->arch.guest_fpu.state); 7474 trace_kvm_fpu(1); 7475 } 7476 7477 void kvm_put_guest_fpu(struct kvm_vcpu *vcpu) 7478 { 7479 if (!vcpu->guest_fpu_loaded) 7480 return; 7481 7482 vcpu->guest_fpu_loaded = 0; 7483 copy_fpregs_to_fpstate(&vcpu->arch.guest_fpu); 7484 __kernel_fpu_end(); 7485 ++vcpu->stat.fpu_reload; 7486 trace_kvm_fpu(0); 7487 } 7488 7489 void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu) 7490 { 7491 void *wbinvd_dirty_mask = vcpu->arch.wbinvd_dirty_mask; 7492 7493 kvmclock_reset(vcpu); 7494 7495 kvm_x86_ops->vcpu_free(vcpu); 7496 free_cpumask_var(wbinvd_dirty_mask); 7497 } 7498 7499 struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm, 7500 unsigned int id) 7501 { 7502 struct kvm_vcpu *vcpu; 7503 7504 if (check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0) 7505 printk_once(KERN_WARNING 7506 "kvm: SMP vm created on host with unstable TSC; " 7507 "guest TSC will not be reliable\n"); 7508 7509 vcpu = kvm_x86_ops->vcpu_create(kvm, id); 7510 7511 return vcpu; 7512 } 7513 7514 int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu) 7515 { 7516 int r; 7517 7518 kvm_vcpu_mtrr_init(vcpu); 7519 r = vcpu_load(vcpu); 7520 if (r) 7521 return r; 7522 kvm_vcpu_reset(vcpu, false); 7523 kvm_mmu_setup(vcpu); 7524 vcpu_put(vcpu); 7525 return r; 7526 } 7527 7528 void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu) 7529 { 7530 struct msr_data msr; 7531 struct kvm *kvm = vcpu->kvm; 7532 7533 if (vcpu_load(vcpu)) 7534 return; 7535 msr.data = 0x0; 7536 msr.index = MSR_IA32_TSC; 7537 msr.host_initiated = true; 7538 kvm_write_tsc(vcpu, &msr); 7539 vcpu_put(vcpu); 7540 7541 if (!kvmclock_periodic_sync) 7542 return; 7543 7544 schedule_delayed_work(&kvm->arch.kvmclock_sync_work, 7545 KVMCLOCK_SYNC_PERIOD); 7546 } 7547 7548 void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu) 7549 { 7550 int r; 7551 vcpu->arch.apf.msr_val = 0; 7552 7553 r = vcpu_load(vcpu); 7554 BUG_ON(r); 7555 kvm_mmu_unload(vcpu); 7556 vcpu_put(vcpu); 7557 7558 kvm_x86_ops->vcpu_free(vcpu); 7559 } 7560 7561 void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event) 7562 { 7563 vcpu->arch.hflags = 0; 7564 7565 vcpu->arch.smi_pending = 0; 7566 atomic_set(&vcpu->arch.nmi_queued, 0); 7567 vcpu->arch.nmi_pending = 0; 7568 vcpu->arch.nmi_injected = false; 7569 kvm_clear_interrupt_queue(vcpu); 7570 kvm_clear_exception_queue(vcpu); 7571 7572 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db)); 7573 kvm_update_dr0123(vcpu); 7574 vcpu->arch.dr6 = DR6_INIT; 7575 kvm_update_dr6(vcpu); 7576 vcpu->arch.dr7 = DR7_FIXED_1; 7577 kvm_update_dr7(vcpu); 7578 7579 vcpu->arch.cr2 = 0; 7580 7581 kvm_make_request(KVM_REQ_EVENT, vcpu); 7582 vcpu->arch.apf.msr_val = 0; 7583 vcpu->arch.st.msr_val = 0; 7584 7585 kvmclock_reset(vcpu); 7586 7587 kvm_clear_async_pf_completion_queue(vcpu); 7588 kvm_async_pf_hash_reset(vcpu); 7589 vcpu->arch.apf.halted = false; 7590 7591 if (!init_event) { 7592 kvm_pmu_reset(vcpu); 7593 vcpu->arch.smbase = 0x30000; 7594 } 7595 7596 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs)); 7597 vcpu->arch.regs_avail = ~0; 7598 vcpu->arch.regs_dirty = ~0; 7599 7600 kvm_x86_ops->vcpu_reset(vcpu, init_event); 7601 } 7602 7603 void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector) 7604 { 7605 struct kvm_segment cs; 7606 7607 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS); 7608 cs.selector = vector << 8; 7609 cs.base = vector << 12; 7610 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS); 7611 kvm_rip_write(vcpu, 0); 7612 } 7613 7614 int kvm_arch_hardware_enable(void) 7615 { 7616 struct kvm *kvm; 7617 struct kvm_vcpu *vcpu; 7618 int i; 7619 int ret; 7620 u64 local_tsc; 7621 u64 max_tsc = 0; 7622 bool stable, backwards_tsc = false; 7623 7624 kvm_shared_msr_cpu_online(); 7625 ret = kvm_x86_ops->hardware_enable(); 7626 if (ret != 0) 7627 return ret; 7628 7629 local_tsc = rdtsc(); 7630 stable = !check_tsc_unstable(); 7631 list_for_each_entry(kvm, &vm_list, vm_list) { 7632 kvm_for_each_vcpu(i, vcpu, kvm) { 7633 if (!stable && vcpu->cpu == smp_processor_id()) 7634 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 7635 if (stable && vcpu->arch.last_host_tsc > local_tsc) { 7636 backwards_tsc = true; 7637 if (vcpu->arch.last_host_tsc > max_tsc) 7638 max_tsc = vcpu->arch.last_host_tsc; 7639 } 7640 } 7641 } 7642 7643 /* 7644 * Sometimes, even reliable TSCs go backwards. This happens on 7645 * platforms that reset TSC during suspend or hibernate actions, but 7646 * maintain synchronization. We must compensate. Fortunately, we can 7647 * detect that condition here, which happens early in CPU bringup, 7648 * before any KVM threads can be running. Unfortunately, we can't 7649 * bring the TSCs fully up to date with real time, as we aren't yet far 7650 * enough into CPU bringup that we know how much real time has actually 7651 * elapsed; our helper function, ktime_get_boot_ns() will be using boot 7652 * variables that haven't been updated yet. 7653 * 7654 * So we simply find the maximum observed TSC above, then record the 7655 * adjustment to TSC in each VCPU. When the VCPU later gets loaded, 7656 * the adjustment will be applied. Note that we accumulate 7657 * adjustments, in case multiple suspend cycles happen before some VCPU 7658 * gets a chance to run again. In the event that no KVM threads get a 7659 * chance to run, we will miss the entire elapsed period, as we'll have 7660 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may 7661 * loose cycle time. This isn't too big a deal, since the loss will be 7662 * uniform across all VCPUs (not to mention the scenario is extremely 7663 * unlikely). It is possible that a second hibernate recovery happens 7664 * much faster than a first, causing the observed TSC here to be 7665 * smaller; this would require additional padding adjustment, which is 7666 * why we set last_host_tsc to the local tsc observed here. 7667 * 7668 * N.B. - this code below runs only on platforms with reliable TSC, 7669 * as that is the only way backwards_tsc is set above. Also note 7670 * that this runs for ALL vcpus, which is not a bug; all VCPUs should 7671 * have the same delta_cyc adjustment applied if backwards_tsc 7672 * is detected. Note further, this adjustment is only done once, 7673 * as we reset last_host_tsc on all VCPUs to stop this from being 7674 * called multiple times (one for each physical CPU bringup). 7675 * 7676 * Platforms with unreliable TSCs don't have to deal with this, they 7677 * will be compensated by the logic in vcpu_load, which sets the TSC to 7678 * catchup mode. This will catchup all VCPUs to real time, but cannot 7679 * guarantee that they stay in perfect synchronization. 7680 */ 7681 if (backwards_tsc) { 7682 u64 delta_cyc = max_tsc - local_tsc; 7683 backwards_tsc_observed = true; 7684 list_for_each_entry(kvm, &vm_list, vm_list) { 7685 kvm_for_each_vcpu(i, vcpu, kvm) { 7686 vcpu->arch.tsc_offset_adjustment += delta_cyc; 7687 vcpu->arch.last_host_tsc = local_tsc; 7688 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu); 7689 } 7690 7691 /* 7692 * We have to disable TSC offset matching.. if you were 7693 * booting a VM while issuing an S4 host suspend.... 7694 * you may have some problem. Solving this issue is 7695 * left as an exercise to the reader. 7696 */ 7697 kvm->arch.last_tsc_nsec = 0; 7698 kvm->arch.last_tsc_write = 0; 7699 } 7700 7701 } 7702 return 0; 7703 } 7704 7705 void kvm_arch_hardware_disable(void) 7706 { 7707 kvm_x86_ops->hardware_disable(); 7708 drop_user_return_notifiers(); 7709 } 7710 7711 int kvm_arch_hardware_setup(void) 7712 { 7713 int r; 7714 7715 r = kvm_x86_ops->hardware_setup(); 7716 if (r != 0) 7717 return r; 7718 7719 if (kvm_has_tsc_control) { 7720 /* 7721 * Make sure the user can only configure tsc_khz values that 7722 * fit into a signed integer. 7723 * A min value is not calculated needed because it will always 7724 * be 1 on all machines. 7725 */ 7726 u64 max = min(0x7fffffffULL, 7727 __scale_tsc(kvm_max_tsc_scaling_ratio, tsc_khz)); 7728 kvm_max_guest_tsc_khz = max; 7729 7730 kvm_default_tsc_scaling_ratio = 1ULL << kvm_tsc_scaling_ratio_frac_bits; 7731 } 7732 7733 kvm_init_msr_list(); 7734 return 0; 7735 } 7736 7737 void kvm_arch_hardware_unsetup(void) 7738 { 7739 kvm_x86_ops->hardware_unsetup(); 7740 } 7741 7742 void kvm_arch_check_processor_compat(void *rtn) 7743 { 7744 kvm_x86_ops->check_processor_compatibility(rtn); 7745 } 7746 7747 bool kvm_vcpu_is_reset_bsp(struct kvm_vcpu *vcpu) 7748 { 7749 return vcpu->kvm->arch.bsp_vcpu_id == vcpu->vcpu_id; 7750 } 7751 EXPORT_SYMBOL_GPL(kvm_vcpu_is_reset_bsp); 7752 7753 bool kvm_vcpu_is_bsp(struct kvm_vcpu *vcpu) 7754 { 7755 return (vcpu->arch.apic_base & MSR_IA32_APICBASE_BSP) != 0; 7756 } 7757 7758 struct static_key kvm_no_apic_vcpu __read_mostly; 7759 EXPORT_SYMBOL_GPL(kvm_no_apic_vcpu); 7760 7761 int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu) 7762 { 7763 struct page *page; 7764 struct kvm *kvm; 7765 int r; 7766 7767 BUG_ON(vcpu->kvm == NULL); 7768 kvm = vcpu->kvm; 7769 7770 vcpu->arch.apicv_active = kvm_x86_ops->get_enable_apicv(); 7771 vcpu->arch.pv.pv_unhalted = false; 7772 vcpu->arch.emulate_ctxt.ops = &emulate_ops; 7773 if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_reset_bsp(vcpu)) 7774 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; 7775 else 7776 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED; 7777 7778 page = alloc_page(GFP_KERNEL | __GFP_ZERO); 7779 if (!page) { 7780 r = -ENOMEM; 7781 goto fail; 7782 } 7783 vcpu->arch.pio_data = page_address(page); 7784 7785 kvm_set_tsc_khz(vcpu, max_tsc_khz); 7786 7787 r = kvm_mmu_create(vcpu); 7788 if (r < 0) 7789 goto fail_free_pio_data; 7790 7791 if (irqchip_in_kernel(kvm)) { 7792 r = kvm_create_lapic(vcpu); 7793 if (r < 0) 7794 goto fail_mmu_destroy; 7795 } else 7796 static_key_slow_inc(&kvm_no_apic_vcpu); 7797 7798 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4, 7799 GFP_KERNEL); 7800 if (!vcpu->arch.mce_banks) { 7801 r = -ENOMEM; 7802 goto fail_free_lapic; 7803 } 7804 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS; 7805 7806 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL)) { 7807 r = -ENOMEM; 7808 goto fail_free_mce_banks; 7809 } 7810 7811 fx_init(vcpu); 7812 7813 vcpu->arch.ia32_tsc_adjust_msr = 0x0; 7814 vcpu->arch.pv_time_enabled = false; 7815 7816 vcpu->arch.guest_supported_xcr0 = 0; 7817 vcpu->arch.guest_xstate_size = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET; 7818 7819 vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu); 7820 7821 vcpu->arch.pat = MSR_IA32_CR_PAT_DEFAULT; 7822 7823 kvm_async_pf_hash_reset(vcpu); 7824 kvm_pmu_init(vcpu); 7825 7826 vcpu->arch.pending_external_vector = -1; 7827 7828 kvm_hv_vcpu_init(vcpu); 7829 7830 return 0; 7831 7832 fail_free_mce_banks: 7833 kfree(vcpu->arch.mce_banks); 7834 fail_free_lapic: 7835 kvm_free_lapic(vcpu); 7836 fail_mmu_destroy: 7837 kvm_mmu_destroy(vcpu); 7838 fail_free_pio_data: 7839 free_page((unsigned long)vcpu->arch.pio_data); 7840 fail: 7841 return r; 7842 } 7843 7844 void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu) 7845 { 7846 int idx; 7847 7848 kvm_hv_vcpu_uninit(vcpu); 7849 kvm_pmu_destroy(vcpu); 7850 kfree(vcpu->arch.mce_banks); 7851 kvm_free_lapic(vcpu); 7852 idx = srcu_read_lock(&vcpu->kvm->srcu); 7853 kvm_mmu_destroy(vcpu); 7854 srcu_read_unlock(&vcpu->kvm->srcu, idx); 7855 free_page((unsigned long)vcpu->arch.pio_data); 7856 if (!lapic_in_kernel(vcpu)) 7857 static_key_slow_dec(&kvm_no_apic_vcpu); 7858 } 7859 7860 void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu) 7861 { 7862 kvm_x86_ops->sched_in(vcpu, cpu); 7863 } 7864 7865 int kvm_arch_init_vm(struct kvm *kvm, unsigned long type) 7866 { 7867 if (type) 7868 return -EINVAL; 7869 7870 INIT_HLIST_HEAD(&kvm->arch.mask_notifier_list); 7871 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages); 7872 INIT_LIST_HEAD(&kvm->arch.zapped_obsolete_pages); 7873 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head); 7874 atomic_set(&kvm->arch.noncoherent_dma_count, 0); 7875 7876 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */ 7877 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap); 7878 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */ 7879 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID, 7880 &kvm->arch.irq_sources_bitmap); 7881 7882 raw_spin_lock_init(&kvm->arch.tsc_write_lock); 7883 mutex_init(&kvm->arch.apic_map_lock); 7884 spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock); 7885 7886 kvm->arch.kvmclock_offset = -ktime_get_boot_ns(); 7887 pvclock_update_vm_gtod_copy(kvm); 7888 7889 INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn); 7890 INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn); 7891 7892 kvm_page_track_init(kvm); 7893 kvm_mmu_init_vm(kvm); 7894 7895 if (kvm_x86_ops->vm_init) 7896 return kvm_x86_ops->vm_init(kvm); 7897 7898 return 0; 7899 } 7900 7901 static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu) 7902 { 7903 int r; 7904 r = vcpu_load(vcpu); 7905 BUG_ON(r); 7906 kvm_mmu_unload(vcpu); 7907 vcpu_put(vcpu); 7908 } 7909 7910 static void kvm_free_vcpus(struct kvm *kvm) 7911 { 7912 unsigned int i; 7913 struct kvm_vcpu *vcpu; 7914 7915 /* 7916 * Unpin any mmu pages first. 7917 */ 7918 kvm_for_each_vcpu(i, vcpu, kvm) { 7919 kvm_clear_async_pf_completion_queue(vcpu); 7920 kvm_unload_vcpu_mmu(vcpu); 7921 } 7922 kvm_for_each_vcpu(i, vcpu, kvm) 7923 kvm_arch_vcpu_free(vcpu); 7924 7925 mutex_lock(&kvm->lock); 7926 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++) 7927 kvm->vcpus[i] = NULL; 7928 7929 atomic_set(&kvm->online_vcpus, 0); 7930 mutex_unlock(&kvm->lock); 7931 } 7932 7933 void kvm_arch_sync_events(struct kvm *kvm) 7934 { 7935 cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work); 7936 cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work); 7937 kvm_free_all_assigned_devices(kvm); 7938 kvm_free_pit(kvm); 7939 } 7940 7941 int __x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size) 7942 { 7943 int i, r; 7944 unsigned long hva; 7945 struct kvm_memslots *slots = kvm_memslots(kvm); 7946 struct kvm_memory_slot *slot, old; 7947 7948 /* Called with kvm->slots_lock held. */ 7949 if (WARN_ON(id >= KVM_MEM_SLOTS_NUM)) 7950 return -EINVAL; 7951 7952 slot = id_to_memslot(slots, id); 7953 if (size) { 7954 if (slot->npages) 7955 return -EEXIST; 7956 7957 /* 7958 * MAP_SHARED to prevent internal slot pages from being moved 7959 * by fork()/COW. 7960 */ 7961 hva = vm_mmap(NULL, 0, size, PROT_READ | PROT_WRITE, 7962 MAP_SHARED | MAP_ANONYMOUS, 0); 7963 if (IS_ERR((void *)hva)) 7964 return PTR_ERR((void *)hva); 7965 } else { 7966 if (!slot->npages) 7967 return 0; 7968 7969 hva = 0; 7970 } 7971 7972 old = *slot; 7973 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) { 7974 struct kvm_userspace_memory_region m; 7975 7976 m.slot = id | (i << 16); 7977 m.flags = 0; 7978 m.guest_phys_addr = gpa; 7979 m.userspace_addr = hva; 7980 m.memory_size = size; 7981 r = __kvm_set_memory_region(kvm, &m); 7982 if (r < 0) 7983 return r; 7984 } 7985 7986 if (!size) { 7987 r = vm_munmap(old.userspace_addr, old.npages * PAGE_SIZE); 7988 WARN_ON(r < 0); 7989 } 7990 7991 return 0; 7992 } 7993 EXPORT_SYMBOL_GPL(__x86_set_memory_region); 7994 7995 int x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size) 7996 { 7997 int r; 7998 7999 mutex_lock(&kvm->slots_lock); 8000 r = __x86_set_memory_region(kvm, id, gpa, size); 8001 mutex_unlock(&kvm->slots_lock); 8002 8003 return r; 8004 } 8005 EXPORT_SYMBOL_GPL(x86_set_memory_region); 8006 8007 void kvm_arch_destroy_vm(struct kvm *kvm) 8008 { 8009 if (current->mm == kvm->mm) { 8010 /* 8011 * Free memory regions allocated on behalf of userspace, 8012 * unless the the memory map has changed due to process exit 8013 * or fd copying. 8014 */ 8015 x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT, 0, 0); 8016 x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT, 0, 0); 8017 x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, 0, 0); 8018 } 8019 if (kvm_x86_ops->vm_destroy) 8020 kvm_x86_ops->vm_destroy(kvm); 8021 kvm_iommu_unmap_guest(kvm); 8022 kfree(kvm->arch.vpic); 8023 kfree(kvm->arch.vioapic); 8024 kvm_free_vcpus(kvm); 8025 kvfree(rcu_dereference_check(kvm->arch.apic_map, 1)); 8026 kvm_mmu_uninit_vm(kvm); 8027 } 8028 8029 void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *free, 8030 struct kvm_memory_slot *dont) 8031 { 8032 int i; 8033 8034 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) { 8035 if (!dont || free->arch.rmap[i] != dont->arch.rmap[i]) { 8036 kvfree(free->arch.rmap[i]); 8037 free->arch.rmap[i] = NULL; 8038 } 8039 if (i == 0) 8040 continue; 8041 8042 if (!dont || free->arch.lpage_info[i - 1] != 8043 dont->arch.lpage_info[i - 1]) { 8044 kvfree(free->arch.lpage_info[i - 1]); 8045 free->arch.lpage_info[i - 1] = NULL; 8046 } 8047 } 8048 8049 kvm_page_track_free_memslot(free, dont); 8050 } 8051 8052 int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot, 8053 unsigned long npages) 8054 { 8055 int i; 8056 8057 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) { 8058 struct kvm_lpage_info *linfo; 8059 unsigned long ugfn; 8060 int lpages; 8061 int level = i + 1; 8062 8063 lpages = gfn_to_index(slot->base_gfn + npages - 1, 8064 slot->base_gfn, level) + 1; 8065 8066 slot->arch.rmap[i] = 8067 kvm_kvzalloc(lpages * sizeof(*slot->arch.rmap[i])); 8068 if (!slot->arch.rmap[i]) 8069 goto out_free; 8070 if (i == 0) 8071 continue; 8072 8073 linfo = kvm_kvzalloc(lpages * sizeof(*linfo)); 8074 if (!linfo) 8075 goto out_free; 8076 8077 slot->arch.lpage_info[i - 1] = linfo; 8078 8079 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1)) 8080 linfo[0].disallow_lpage = 1; 8081 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1)) 8082 linfo[lpages - 1].disallow_lpage = 1; 8083 ugfn = slot->userspace_addr >> PAGE_SHIFT; 8084 /* 8085 * If the gfn and userspace address are not aligned wrt each 8086 * other, or if explicitly asked to, disable large page 8087 * support for this slot 8088 */ 8089 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) || 8090 !kvm_largepages_enabled()) { 8091 unsigned long j; 8092 8093 for (j = 0; j < lpages; ++j) 8094 linfo[j].disallow_lpage = 1; 8095 } 8096 } 8097 8098 if (kvm_page_track_create_memslot(slot, npages)) 8099 goto out_free; 8100 8101 return 0; 8102 8103 out_free: 8104 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) { 8105 kvfree(slot->arch.rmap[i]); 8106 slot->arch.rmap[i] = NULL; 8107 if (i == 0) 8108 continue; 8109 8110 kvfree(slot->arch.lpage_info[i - 1]); 8111 slot->arch.lpage_info[i - 1] = NULL; 8112 } 8113 return -ENOMEM; 8114 } 8115 8116 void kvm_arch_memslots_updated(struct kvm *kvm, struct kvm_memslots *slots) 8117 { 8118 /* 8119 * memslots->generation has been incremented. 8120 * mmio generation may have reached its maximum value. 8121 */ 8122 kvm_mmu_invalidate_mmio_sptes(kvm, slots); 8123 } 8124 8125 int kvm_arch_prepare_memory_region(struct kvm *kvm, 8126 struct kvm_memory_slot *memslot, 8127 const struct kvm_userspace_memory_region *mem, 8128 enum kvm_mr_change change) 8129 { 8130 return 0; 8131 } 8132 8133 static void kvm_mmu_slot_apply_flags(struct kvm *kvm, 8134 struct kvm_memory_slot *new) 8135 { 8136 /* Still write protect RO slot */ 8137 if (new->flags & KVM_MEM_READONLY) { 8138 kvm_mmu_slot_remove_write_access(kvm, new); 8139 return; 8140 } 8141 8142 /* 8143 * Call kvm_x86_ops dirty logging hooks when they are valid. 8144 * 8145 * kvm_x86_ops->slot_disable_log_dirty is called when: 8146 * 8147 * - KVM_MR_CREATE with dirty logging is disabled 8148 * - KVM_MR_FLAGS_ONLY with dirty logging is disabled in new flag 8149 * 8150 * The reason is, in case of PML, we need to set D-bit for any slots 8151 * with dirty logging disabled in order to eliminate unnecessary GPA 8152 * logging in PML buffer (and potential PML buffer full VMEXT). This 8153 * guarantees leaving PML enabled during guest's lifetime won't have 8154 * any additonal overhead from PML when guest is running with dirty 8155 * logging disabled for memory slots. 8156 * 8157 * kvm_x86_ops->slot_enable_log_dirty is called when switching new slot 8158 * to dirty logging mode. 8159 * 8160 * If kvm_x86_ops dirty logging hooks are invalid, use write protect. 8161 * 8162 * In case of write protect: 8163 * 8164 * Write protect all pages for dirty logging. 8165 * 8166 * All the sptes including the large sptes which point to this 8167 * slot are set to readonly. We can not create any new large 8168 * spte on this slot until the end of the logging. 8169 * 8170 * See the comments in fast_page_fault(). 8171 */ 8172 if (new->flags & KVM_MEM_LOG_DIRTY_PAGES) { 8173 if (kvm_x86_ops->slot_enable_log_dirty) 8174 kvm_x86_ops->slot_enable_log_dirty(kvm, new); 8175 else 8176 kvm_mmu_slot_remove_write_access(kvm, new); 8177 } else { 8178 if (kvm_x86_ops->slot_disable_log_dirty) 8179 kvm_x86_ops->slot_disable_log_dirty(kvm, new); 8180 } 8181 } 8182 8183 void kvm_arch_commit_memory_region(struct kvm *kvm, 8184 const struct kvm_userspace_memory_region *mem, 8185 const struct kvm_memory_slot *old, 8186 const struct kvm_memory_slot *new, 8187 enum kvm_mr_change change) 8188 { 8189 int nr_mmu_pages = 0; 8190 8191 if (!kvm->arch.n_requested_mmu_pages) 8192 nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm); 8193 8194 if (nr_mmu_pages) 8195 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages); 8196 8197 /* 8198 * Dirty logging tracks sptes in 4k granularity, meaning that large 8199 * sptes have to be split. If live migration is successful, the guest 8200 * in the source machine will be destroyed and large sptes will be 8201 * created in the destination. However, if the guest continues to run 8202 * in the source machine (for example if live migration fails), small 8203 * sptes will remain around and cause bad performance. 8204 * 8205 * Scan sptes if dirty logging has been stopped, dropping those 8206 * which can be collapsed into a single large-page spte. Later 8207 * page faults will create the large-page sptes. 8208 */ 8209 if ((change != KVM_MR_DELETE) && 8210 (old->flags & KVM_MEM_LOG_DIRTY_PAGES) && 8211 !(new->flags & KVM_MEM_LOG_DIRTY_PAGES)) 8212 kvm_mmu_zap_collapsible_sptes(kvm, new); 8213 8214 /* 8215 * Set up write protection and/or dirty logging for the new slot. 8216 * 8217 * For KVM_MR_DELETE and KVM_MR_MOVE, the shadow pages of old slot have 8218 * been zapped so no dirty logging staff is needed for old slot. For 8219 * KVM_MR_FLAGS_ONLY, the old slot is essentially the same one as the 8220 * new and it's also covered when dealing with the new slot. 8221 * 8222 * FIXME: const-ify all uses of struct kvm_memory_slot. 8223 */ 8224 if (change != KVM_MR_DELETE) 8225 kvm_mmu_slot_apply_flags(kvm, (struct kvm_memory_slot *) new); 8226 } 8227 8228 void kvm_arch_flush_shadow_all(struct kvm *kvm) 8229 { 8230 kvm_mmu_invalidate_zap_all_pages(kvm); 8231 } 8232 8233 void kvm_arch_flush_shadow_memslot(struct kvm *kvm, 8234 struct kvm_memory_slot *slot) 8235 { 8236 kvm_page_track_flush_slot(kvm, slot); 8237 } 8238 8239 static inline bool kvm_vcpu_has_events(struct kvm_vcpu *vcpu) 8240 { 8241 if (!list_empty_careful(&vcpu->async_pf.done)) 8242 return true; 8243 8244 if (kvm_apic_has_events(vcpu)) 8245 return true; 8246 8247 if (vcpu->arch.pv.pv_unhalted) 8248 return true; 8249 8250 if (atomic_read(&vcpu->arch.nmi_queued)) 8251 return true; 8252 8253 if (test_bit(KVM_REQ_SMI, &vcpu->requests)) 8254 return true; 8255 8256 if (kvm_arch_interrupt_allowed(vcpu) && 8257 kvm_cpu_has_interrupt(vcpu)) 8258 return true; 8259 8260 if (kvm_hv_has_stimer_pending(vcpu)) 8261 return true; 8262 8263 return false; 8264 } 8265 8266 int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu) 8267 { 8268 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) 8269 kvm_x86_ops->check_nested_events(vcpu, false); 8270 8271 return kvm_vcpu_running(vcpu) || kvm_vcpu_has_events(vcpu); 8272 } 8273 8274 int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu) 8275 { 8276 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE; 8277 } 8278 8279 int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu) 8280 { 8281 return kvm_x86_ops->interrupt_allowed(vcpu); 8282 } 8283 8284 unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu) 8285 { 8286 if (is_64_bit_mode(vcpu)) 8287 return kvm_rip_read(vcpu); 8288 return (u32)(get_segment_base(vcpu, VCPU_SREG_CS) + 8289 kvm_rip_read(vcpu)); 8290 } 8291 EXPORT_SYMBOL_GPL(kvm_get_linear_rip); 8292 8293 bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip) 8294 { 8295 return kvm_get_linear_rip(vcpu) == linear_rip; 8296 } 8297 EXPORT_SYMBOL_GPL(kvm_is_linear_rip); 8298 8299 unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu) 8300 { 8301 unsigned long rflags; 8302 8303 rflags = kvm_x86_ops->get_rflags(vcpu); 8304 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) 8305 rflags &= ~X86_EFLAGS_TF; 8306 return rflags; 8307 } 8308 EXPORT_SYMBOL_GPL(kvm_get_rflags); 8309 8310 static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags) 8311 { 8312 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP && 8313 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip)) 8314 rflags |= X86_EFLAGS_TF; 8315 kvm_x86_ops->set_rflags(vcpu, rflags); 8316 } 8317 8318 void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags) 8319 { 8320 __kvm_set_rflags(vcpu, rflags); 8321 kvm_make_request(KVM_REQ_EVENT, vcpu); 8322 } 8323 EXPORT_SYMBOL_GPL(kvm_set_rflags); 8324 8325 void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work) 8326 { 8327 int r; 8328 8329 if ((vcpu->arch.mmu.direct_map != work->arch.direct_map) || 8330 work->wakeup_all) 8331 return; 8332 8333 r = kvm_mmu_reload(vcpu); 8334 if (unlikely(r)) 8335 return; 8336 8337 if (!vcpu->arch.mmu.direct_map && 8338 work->arch.cr3 != vcpu->arch.mmu.get_cr3(vcpu)) 8339 return; 8340 8341 vcpu->arch.mmu.page_fault(vcpu, work->gva, 0, true); 8342 } 8343 8344 static inline u32 kvm_async_pf_hash_fn(gfn_t gfn) 8345 { 8346 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU)); 8347 } 8348 8349 static inline u32 kvm_async_pf_next_probe(u32 key) 8350 { 8351 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1); 8352 } 8353 8354 static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn) 8355 { 8356 u32 key = kvm_async_pf_hash_fn(gfn); 8357 8358 while (vcpu->arch.apf.gfns[key] != ~0) 8359 key = kvm_async_pf_next_probe(key); 8360 8361 vcpu->arch.apf.gfns[key] = gfn; 8362 } 8363 8364 static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn) 8365 { 8366 int i; 8367 u32 key = kvm_async_pf_hash_fn(gfn); 8368 8369 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) && 8370 (vcpu->arch.apf.gfns[key] != gfn && 8371 vcpu->arch.apf.gfns[key] != ~0); i++) 8372 key = kvm_async_pf_next_probe(key); 8373 8374 return key; 8375 } 8376 8377 bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn) 8378 { 8379 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn; 8380 } 8381 8382 static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn) 8383 { 8384 u32 i, j, k; 8385 8386 i = j = kvm_async_pf_gfn_slot(vcpu, gfn); 8387 while (true) { 8388 vcpu->arch.apf.gfns[i] = ~0; 8389 do { 8390 j = kvm_async_pf_next_probe(j); 8391 if (vcpu->arch.apf.gfns[j] == ~0) 8392 return; 8393 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]); 8394 /* 8395 * k lies cyclically in ]i,j] 8396 * | i.k.j | 8397 * |....j i.k.| or |.k..j i...| 8398 */ 8399 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j)); 8400 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j]; 8401 i = j; 8402 } 8403 } 8404 8405 static int apf_put_user(struct kvm_vcpu *vcpu, u32 val) 8406 { 8407 8408 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val, 8409 sizeof(val)); 8410 } 8411 8412 void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu, 8413 struct kvm_async_pf *work) 8414 { 8415 struct x86_exception fault; 8416 8417 trace_kvm_async_pf_not_present(work->arch.token, work->gva); 8418 kvm_add_async_pf_gfn(vcpu, work->arch.gfn); 8419 8420 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) || 8421 (vcpu->arch.apf.send_user_only && 8422 kvm_x86_ops->get_cpl(vcpu) == 0)) 8423 kvm_make_request(KVM_REQ_APF_HALT, vcpu); 8424 else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) { 8425 fault.vector = PF_VECTOR; 8426 fault.error_code_valid = true; 8427 fault.error_code = 0; 8428 fault.nested_page_fault = false; 8429 fault.address = work->arch.token; 8430 kvm_inject_page_fault(vcpu, &fault); 8431 } 8432 } 8433 8434 void kvm_arch_async_page_present(struct kvm_vcpu *vcpu, 8435 struct kvm_async_pf *work) 8436 { 8437 struct x86_exception fault; 8438 8439 trace_kvm_async_pf_ready(work->arch.token, work->gva); 8440 if (work->wakeup_all) 8441 work->arch.token = ~0; /* broadcast wakeup */ 8442 else 8443 kvm_del_async_pf_gfn(vcpu, work->arch.gfn); 8444 8445 if ((vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) && 8446 !apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) { 8447 fault.vector = PF_VECTOR; 8448 fault.error_code_valid = true; 8449 fault.error_code = 0; 8450 fault.nested_page_fault = false; 8451 fault.address = work->arch.token; 8452 kvm_inject_page_fault(vcpu, &fault); 8453 } 8454 vcpu->arch.apf.halted = false; 8455 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; 8456 } 8457 8458 bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu) 8459 { 8460 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED)) 8461 return true; 8462 else 8463 return !kvm_event_needs_reinjection(vcpu) && 8464 kvm_x86_ops->interrupt_allowed(vcpu); 8465 } 8466 8467 void kvm_arch_start_assignment(struct kvm *kvm) 8468 { 8469 atomic_inc(&kvm->arch.assigned_device_count); 8470 } 8471 EXPORT_SYMBOL_GPL(kvm_arch_start_assignment); 8472 8473 void kvm_arch_end_assignment(struct kvm *kvm) 8474 { 8475 atomic_dec(&kvm->arch.assigned_device_count); 8476 } 8477 EXPORT_SYMBOL_GPL(kvm_arch_end_assignment); 8478 8479 bool kvm_arch_has_assigned_device(struct kvm *kvm) 8480 { 8481 return atomic_read(&kvm->arch.assigned_device_count); 8482 } 8483 EXPORT_SYMBOL_GPL(kvm_arch_has_assigned_device); 8484 8485 void kvm_arch_register_noncoherent_dma(struct kvm *kvm) 8486 { 8487 atomic_inc(&kvm->arch.noncoherent_dma_count); 8488 } 8489 EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma); 8490 8491 void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm) 8492 { 8493 atomic_dec(&kvm->arch.noncoherent_dma_count); 8494 } 8495 EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma); 8496 8497 bool kvm_arch_has_noncoherent_dma(struct kvm *kvm) 8498 { 8499 return atomic_read(&kvm->arch.noncoherent_dma_count); 8500 } 8501 EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma); 8502 8503 bool kvm_arch_has_irq_bypass(void) 8504 { 8505 return kvm_x86_ops->update_pi_irte != NULL; 8506 } 8507 8508 int kvm_arch_irq_bypass_add_producer(struct irq_bypass_consumer *cons, 8509 struct irq_bypass_producer *prod) 8510 { 8511 struct kvm_kernel_irqfd *irqfd = 8512 container_of(cons, struct kvm_kernel_irqfd, consumer); 8513 8514 irqfd->producer = prod; 8515 8516 return kvm_x86_ops->update_pi_irte(irqfd->kvm, 8517 prod->irq, irqfd->gsi, 1); 8518 } 8519 8520 void kvm_arch_irq_bypass_del_producer(struct irq_bypass_consumer *cons, 8521 struct irq_bypass_producer *prod) 8522 { 8523 int ret; 8524 struct kvm_kernel_irqfd *irqfd = 8525 container_of(cons, struct kvm_kernel_irqfd, consumer); 8526 8527 WARN_ON(irqfd->producer != prod); 8528 irqfd->producer = NULL; 8529 8530 /* 8531 * When producer of consumer is unregistered, we change back to 8532 * remapped mode, so we can re-use the current implementation 8533 * when the irq is masked/disabled or the consumer side (KVM 8534 * int this case doesn't want to receive the interrupts. 8535 */ 8536 ret = kvm_x86_ops->update_pi_irte(irqfd->kvm, prod->irq, irqfd->gsi, 0); 8537 if (ret) 8538 printk(KERN_INFO "irq bypass consumer (token %p) unregistration" 8539 " fails: %d\n", irqfd->consumer.token, ret); 8540 } 8541 8542 int kvm_arch_update_irqfd_routing(struct kvm *kvm, unsigned int host_irq, 8543 uint32_t guest_irq, bool set) 8544 { 8545 if (!kvm_x86_ops->update_pi_irte) 8546 return -EINVAL; 8547 8548 return kvm_x86_ops->update_pi_irte(kvm, host_irq, guest_irq, set); 8549 } 8550 8551 bool kvm_vector_hashing_enabled(void) 8552 { 8553 return vector_hashing; 8554 } 8555 EXPORT_SYMBOL_GPL(kvm_vector_hashing_enabled); 8556 8557 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit); 8558 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_fast_mmio); 8559 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq); 8560 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault); 8561 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr); 8562 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr); 8563 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun); 8564 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit); 8565 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject); 8566 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit); 8567 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga); 8568 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit); 8569 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts); 8570 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset); 8571 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_ple_window); 8572 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pml_full); 8573 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pi_irte_update); 8574 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_unaccelerated_access); 8575 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_incomplete_ipi); 8576