1 /* 2 * Kernel-based Virtual Machine driver for Linux 3 * 4 * derived from drivers/kvm/kvm_main.c 5 * 6 * Copyright (C) 2006 Qumranet, Inc. 7 * Copyright (C) 2008 Qumranet, Inc. 8 * Copyright IBM Corporation, 2008 9 * Copyright 2010 Red Hat, Inc. and/or its affiliates. 10 * 11 * Authors: 12 * Avi Kivity <avi@qumranet.com> 13 * Yaniv Kamay <yaniv@qumranet.com> 14 * Amit Shah <amit.shah@qumranet.com> 15 * Ben-Ami Yassour <benami@il.ibm.com> 16 * 17 * This work is licensed under the terms of the GNU GPL, version 2. See 18 * the COPYING file in the top-level directory. 19 * 20 */ 21 22 #include <linux/kvm_host.h> 23 #include "irq.h" 24 #include "mmu.h" 25 #include "i8254.h" 26 #include "tss.h" 27 #include "kvm_cache_regs.h" 28 #include "x86.h" 29 #include "cpuid.h" 30 #include "assigned-dev.h" 31 32 #include <linux/clocksource.h> 33 #include <linux/interrupt.h> 34 #include <linux/kvm.h> 35 #include <linux/fs.h> 36 #include <linux/vmalloc.h> 37 #include <linux/module.h> 38 #include <linux/mman.h> 39 #include <linux/highmem.h> 40 #include <linux/iommu.h> 41 #include <linux/intel-iommu.h> 42 #include <linux/cpufreq.h> 43 #include <linux/user-return-notifier.h> 44 #include <linux/srcu.h> 45 #include <linux/slab.h> 46 #include <linux/perf_event.h> 47 #include <linux/uaccess.h> 48 #include <linux/hash.h> 49 #include <linux/pci.h> 50 #include <linux/timekeeper_internal.h> 51 #include <linux/pvclock_gtod.h> 52 #include <trace/events/kvm.h> 53 54 #define CREATE_TRACE_POINTS 55 #include "trace.h" 56 57 #include <asm/debugreg.h> 58 #include <asm/msr.h> 59 #include <asm/desc.h> 60 #include <asm/mtrr.h> 61 #include <asm/mce.h> 62 #include <asm/i387.h> 63 #include <asm/fpu-internal.h> /* Ugh! */ 64 #include <asm/xcr.h> 65 #include <asm/pvclock.h> 66 #include <asm/div64.h> 67 68 #define MAX_IO_MSRS 256 69 #define KVM_MAX_MCE_BANKS 32 70 #define KVM_MCE_CAP_SUPPORTED (MCG_CTL_P | MCG_SER_P) 71 72 #define emul_to_vcpu(ctxt) \ 73 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt) 74 75 /* EFER defaults: 76 * - enable syscall per default because its emulated by KVM 77 * - enable LME and LMA per default on 64 bit KVM 78 */ 79 #ifdef CONFIG_X86_64 80 static 81 u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA)); 82 #else 83 static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE); 84 #endif 85 86 #define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM 87 #define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU 88 89 static void update_cr8_intercept(struct kvm_vcpu *vcpu); 90 static void process_nmi(struct kvm_vcpu *vcpu); 91 static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags); 92 93 struct kvm_x86_ops *kvm_x86_ops; 94 EXPORT_SYMBOL_GPL(kvm_x86_ops); 95 96 static bool ignore_msrs = 0; 97 module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR); 98 99 unsigned int min_timer_period_us = 500; 100 module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR); 101 102 bool kvm_has_tsc_control; 103 EXPORT_SYMBOL_GPL(kvm_has_tsc_control); 104 u32 kvm_max_guest_tsc_khz; 105 EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz); 106 107 /* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */ 108 static u32 tsc_tolerance_ppm = 250; 109 module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR); 110 111 /* lapic timer advance (tscdeadline mode only) in nanoseconds */ 112 unsigned int lapic_timer_advance_ns = 0; 113 module_param(lapic_timer_advance_ns, uint, S_IRUGO | S_IWUSR); 114 115 static bool backwards_tsc_observed = false; 116 117 #define KVM_NR_SHARED_MSRS 16 118 119 struct kvm_shared_msrs_global { 120 int nr; 121 u32 msrs[KVM_NR_SHARED_MSRS]; 122 }; 123 124 struct kvm_shared_msrs { 125 struct user_return_notifier urn; 126 bool registered; 127 struct kvm_shared_msr_values { 128 u64 host; 129 u64 curr; 130 } values[KVM_NR_SHARED_MSRS]; 131 }; 132 133 static struct kvm_shared_msrs_global __read_mostly shared_msrs_global; 134 static struct kvm_shared_msrs __percpu *shared_msrs; 135 136 struct kvm_stats_debugfs_item debugfs_entries[] = { 137 { "pf_fixed", VCPU_STAT(pf_fixed) }, 138 { "pf_guest", VCPU_STAT(pf_guest) }, 139 { "tlb_flush", VCPU_STAT(tlb_flush) }, 140 { "invlpg", VCPU_STAT(invlpg) }, 141 { "exits", VCPU_STAT(exits) }, 142 { "io_exits", VCPU_STAT(io_exits) }, 143 { "mmio_exits", VCPU_STAT(mmio_exits) }, 144 { "signal_exits", VCPU_STAT(signal_exits) }, 145 { "irq_window", VCPU_STAT(irq_window_exits) }, 146 { "nmi_window", VCPU_STAT(nmi_window_exits) }, 147 { "halt_exits", VCPU_STAT(halt_exits) }, 148 { "halt_successful_poll", VCPU_STAT(halt_successful_poll) }, 149 { "halt_wakeup", VCPU_STAT(halt_wakeup) }, 150 { "hypercalls", VCPU_STAT(hypercalls) }, 151 { "request_irq", VCPU_STAT(request_irq_exits) }, 152 { "irq_exits", VCPU_STAT(irq_exits) }, 153 { "host_state_reload", VCPU_STAT(host_state_reload) }, 154 { "efer_reload", VCPU_STAT(efer_reload) }, 155 { "fpu_reload", VCPU_STAT(fpu_reload) }, 156 { "insn_emulation", VCPU_STAT(insn_emulation) }, 157 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) }, 158 { "irq_injections", VCPU_STAT(irq_injections) }, 159 { "nmi_injections", VCPU_STAT(nmi_injections) }, 160 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) }, 161 { "mmu_pte_write", VM_STAT(mmu_pte_write) }, 162 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) }, 163 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) }, 164 { "mmu_flooded", VM_STAT(mmu_flooded) }, 165 { "mmu_recycled", VM_STAT(mmu_recycled) }, 166 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) }, 167 { "mmu_unsync", VM_STAT(mmu_unsync) }, 168 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) }, 169 { "largepages", VM_STAT(lpages) }, 170 { NULL } 171 }; 172 173 u64 __read_mostly host_xcr0; 174 175 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt); 176 177 static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu) 178 { 179 int i; 180 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++) 181 vcpu->arch.apf.gfns[i] = ~0; 182 } 183 184 static void kvm_on_user_return(struct user_return_notifier *urn) 185 { 186 unsigned slot; 187 struct kvm_shared_msrs *locals 188 = container_of(urn, struct kvm_shared_msrs, urn); 189 struct kvm_shared_msr_values *values; 190 191 for (slot = 0; slot < shared_msrs_global.nr; ++slot) { 192 values = &locals->values[slot]; 193 if (values->host != values->curr) { 194 wrmsrl(shared_msrs_global.msrs[slot], values->host); 195 values->curr = values->host; 196 } 197 } 198 locals->registered = false; 199 user_return_notifier_unregister(urn); 200 } 201 202 static void shared_msr_update(unsigned slot, u32 msr) 203 { 204 u64 value; 205 unsigned int cpu = smp_processor_id(); 206 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu); 207 208 /* only read, and nobody should modify it at this time, 209 * so don't need lock */ 210 if (slot >= shared_msrs_global.nr) { 211 printk(KERN_ERR "kvm: invalid MSR slot!"); 212 return; 213 } 214 rdmsrl_safe(msr, &value); 215 smsr->values[slot].host = value; 216 smsr->values[slot].curr = value; 217 } 218 219 void kvm_define_shared_msr(unsigned slot, u32 msr) 220 { 221 BUG_ON(slot >= KVM_NR_SHARED_MSRS); 222 if (slot >= shared_msrs_global.nr) 223 shared_msrs_global.nr = slot + 1; 224 shared_msrs_global.msrs[slot] = msr; 225 /* we need ensured the shared_msr_global have been updated */ 226 smp_wmb(); 227 } 228 EXPORT_SYMBOL_GPL(kvm_define_shared_msr); 229 230 static void kvm_shared_msr_cpu_online(void) 231 { 232 unsigned i; 233 234 for (i = 0; i < shared_msrs_global.nr; ++i) 235 shared_msr_update(i, shared_msrs_global.msrs[i]); 236 } 237 238 int kvm_set_shared_msr(unsigned slot, u64 value, u64 mask) 239 { 240 unsigned int cpu = smp_processor_id(); 241 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu); 242 int err; 243 244 if (((value ^ smsr->values[slot].curr) & mask) == 0) 245 return 0; 246 smsr->values[slot].curr = value; 247 err = wrmsrl_safe(shared_msrs_global.msrs[slot], value); 248 if (err) 249 return 1; 250 251 if (!smsr->registered) { 252 smsr->urn.on_user_return = kvm_on_user_return; 253 user_return_notifier_register(&smsr->urn); 254 smsr->registered = true; 255 } 256 return 0; 257 } 258 EXPORT_SYMBOL_GPL(kvm_set_shared_msr); 259 260 static void drop_user_return_notifiers(void) 261 { 262 unsigned int cpu = smp_processor_id(); 263 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu); 264 265 if (smsr->registered) 266 kvm_on_user_return(&smsr->urn); 267 } 268 269 u64 kvm_get_apic_base(struct kvm_vcpu *vcpu) 270 { 271 return vcpu->arch.apic_base; 272 } 273 EXPORT_SYMBOL_GPL(kvm_get_apic_base); 274 275 int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info) 276 { 277 u64 old_state = vcpu->arch.apic_base & 278 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE); 279 u64 new_state = msr_info->data & 280 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE); 281 u64 reserved_bits = ((~0ULL) << cpuid_maxphyaddr(vcpu)) | 282 0x2ff | (guest_cpuid_has_x2apic(vcpu) ? 0 : X2APIC_ENABLE); 283 284 if (!msr_info->host_initiated && 285 ((msr_info->data & reserved_bits) != 0 || 286 new_state == X2APIC_ENABLE || 287 (new_state == MSR_IA32_APICBASE_ENABLE && 288 old_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE)) || 289 (new_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE) && 290 old_state == 0))) 291 return 1; 292 293 kvm_lapic_set_base(vcpu, msr_info->data); 294 return 0; 295 } 296 EXPORT_SYMBOL_GPL(kvm_set_apic_base); 297 298 asmlinkage __visible void kvm_spurious_fault(void) 299 { 300 /* Fault while not rebooting. We want the trace. */ 301 BUG(); 302 } 303 EXPORT_SYMBOL_GPL(kvm_spurious_fault); 304 305 #define EXCPT_BENIGN 0 306 #define EXCPT_CONTRIBUTORY 1 307 #define EXCPT_PF 2 308 309 static int exception_class(int vector) 310 { 311 switch (vector) { 312 case PF_VECTOR: 313 return EXCPT_PF; 314 case DE_VECTOR: 315 case TS_VECTOR: 316 case NP_VECTOR: 317 case SS_VECTOR: 318 case GP_VECTOR: 319 return EXCPT_CONTRIBUTORY; 320 default: 321 break; 322 } 323 return EXCPT_BENIGN; 324 } 325 326 #define EXCPT_FAULT 0 327 #define EXCPT_TRAP 1 328 #define EXCPT_ABORT 2 329 #define EXCPT_INTERRUPT 3 330 331 static int exception_type(int vector) 332 { 333 unsigned int mask; 334 335 if (WARN_ON(vector > 31 || vector == NMI_VECTOR)) 336 return EXCPT_INTERRUPT; 337 338 mask = 1 << vector; 339 340 /* #DB is trap, as instruction watchpoints are handled elsewhere */ 341 if (mask & ((1 << DB_VECTOR) | (1 << BP_VECTOR) | (1 << OF_VECTOR))) 342 return EXCPT_TRAP; 343 344 if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR))) 345 return EXCPT_ABORT; 346 347 /* Reserved exceptions will result in fault */ 348 return EXCPT_FAULT; 349 } 350 351 static void kvm_multiple_exception(struct kvm_vcpu *vcpu, 352 unsigned nr, bool has_error, u32 error_code, 353 bool reinject) 354 { 355 u32 prev_nr; 356 int class1, class2; 357 358 kvm_make_request(KVM_REQ_EVENT, vcpu); 359 360 if (!vcpu->arch.exception.pending) { 361 queue: 362 if (has_error && !is_protmode(vcpu)) 363 has_error = false; 364 vcpu->arch.exception.pending = true; 365 vcpu->arch.exception.has_error_code = has_error; 366 vcpu->arch.exception.nr = nr; 367 vcpu->arch.exception.error_code = error_code; 368 vcpu->arch.exception.reinject = reinject; 369 return; 370 } 371 372 /* to check exception */ 373 prev_nr = vcpu->arch.exception.nr; 374 if (prev_nr == DF_VECTOR) { 375 /* triple fault -> shutdown */ 376 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); 377 return; 378 } 379 class1 = exception_class(prev_nr); 380 class2 = exception_class(nr); 381 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY) 382 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) { 383 /* generate double fault per SDM Table 5-5 */ 384 vcpu->arch.exception.pending = true; 385 vcpu->arch.exception.has_error_code = true; 386 vcpu->arch.exception.nr = DF_VECTOR; 387 vcpu->arch.exception.error_code = 0; 388 } else 389 /* replace previous exception with a new one in a hope 390 that instruction re-execution will regenerate lost 391 exception */ 392 goto queue; 393 } 394 395 void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr) 396 { 397 kvm_multiple_exception(vcpu, nr, false, 0, false); 398 } 399 EXPORT_SYMBOL_GPL(kvm_queue_exception); 400 401 void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr) 402 { 403 kvm_multiple_exception(vcpu, nr, false, 0, true); 404 } 405 EXPORT_SYMBOL_GPL(kvm_requeue_exception); 406 407 void kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err) 408 { 409 if (err) 410 kvm_inject_gp(vcpu, 0); 411 else 412 kvm_x86_ops->skip_emulated_instruction(vcpu); 413 } 414 EXPORT_SYMBOL_GPL(kvm_complete_insn_gp); 415 416 void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault) 417 { 418 ++vcpu->stat.pf_guest; 419 vcpu->arch.cr2 = fault->address; 420 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code); 421 } 422 EXPORT_SYMBOL_GPL(kvm_inject_page_fault); 423 424 static bool kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault) 425 { 426 if (mmu_is_nested(vcpu) && !fault->nested_page_fault) 427 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault); 428 else 429 vcpu->arch.mmu.inject_page_fault(vcpu, fault); 430 431 return fault->nested_page_fault; 432 } 433 434 void kvm_inject_nmi(struct kvm_vcpu *vcpu) 435 { 436 atomic_inc(&vcpu->arch.nmi_queued); 437 kvm_make_request(KVM_REQ_NMI, vcpu); 438 } 439 EXPORT_SYMBOL_GPL(kvm_inject_nmi); 440 441 void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code) 442 { 443 kvm_multiple_exception(vcpu, nr, true, error_code, false); 444 } 445 EXPORT_SYMBOL_GPL(kvm_queue_exception_e); 446 447 void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code) 448 { 449 kvm_multiple_exception(vcpu, nr, true, error_code, true); 450 } 451 EXPORT_SYMBOL_GPL(kvm_requeue_exception_e); 452 453 /* 454 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue 455 * a #GP and return false. 456 */ 457 bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl) 458 { 459 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl) 460 return true; 461 kvm_queue_exception_e(vcpu, GP_VECTOR, 0); 462 return false; 463 } 464 EXPORT_SYMBOL_GPL(kvm_require_cpl); 465 466 bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr) 467 { 468 if ((dr != 4 && dr != 5) || !kvm_read_cr4_bits(vcpu, X86_CR4_DE)) 469 return true; 470 471 kvm_queue_exception(vcpu, UD_VECTOR); 472 return false; 473 } 474 EXPORT_SYMBOL_GPL(kvm_require_dr); 475 476 /* 477 * This function will be used to read from the physical memory of the currently 478 * running guest. The difference to kvm_read_guest_page is that this function 479 * can read from guest physical or from the guest's guest physical memory. 480 */ 481 int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, 482 gfn_t ngfn, void *data, int offset, int len, 483 u32 access) 484 { 485 struct x86_exception exception; 486 gfn_t real_gfn; 487 gpa_t ngpa; 488 489 ngpa = gfn_to_gpa(ngfn); 490 real_gfn = mmu->translate_gpa(vcpu, ngpa, access, &exception); 491 if (real_gfn == UNMAPPED_GVA) 492 return -EFAULT; 493 494 real_gfn = gpa_to_gfn(real_gfn); 495 496 return kvm_read_guest_page(vcpu->kvm, real_gfn, data, offset, len); 497 } 498 EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu); 499 500 static int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn, 501 void *data, int offset, int len, u32 access) 502 { 503 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn, 504 data, offset, len, access); 505 } 506 507 /* 508 * Load the pae pdptrs. Return true is they are all valid. 509 */ 510 int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3) 511 { 512 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT; 513 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2; 514 int i; 515 int ret; 516 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)]; 517 518 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte, 519 offset * sizeof(u64), sizeof(pdpte), 520 PFERR_USER_MASK|PFERR_WRITE_MASK); 521 if (ret < 0) { 522 ret = 0; 523 goto out; 524 } 525 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) { 526 if (is_present_gpte(pdpte[i]) && 527 (pdpte[i] & vcpu->arch.mmu.rsvd_bits_mask[0][2])) { 528 ret = 0; 529 goto out; 530 } 531 } 532 ret = 1; 533 534 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs)); 535 __set_bit(VCPU_EXREG_PDPTR, 536 (unsigned long *)&vcpu->arch.regs_avail); 537 __set_bit(VCPU_EXREG_PDPTR, 538 (unsigned long *)&vcpu->arch.regs_dirty); 539 out: 540 541 return ret; 542 } 543 EXPORT_SYMBOL_GPL(load_pdptrs); 544 545 static bool pdptrs_changed(struct kvm_vcpu *vcpu) 546 { 547 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)]; 548 bool changed = true; 549 int offset; 550 gfn_t gfn; 551 int r; 552 553 if (is_long_mode(vcpu) || !is_pae(vcpu)) 554 return false; 555 556 if (!test_bit(VCPU_EXREG_PDPTR, 557 (unsigned long *)&vcpu->arch.regs_avail)) 558 return true; 559 560 gfn = (kvm_read_cr3(vcpu) & ~31u) >> PAGE_SHIFT; 561 offset = (kvm_read_cr3(vcpu) & ~31u) & (PAGE_SIZE - 1); 562 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte), 563 PFERR_USER_MASK | PFERR_WRITE_MASK); 564 if (r < 0) 565 goto out; 566 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0; 567 out: 568 569 return changed; 570 } 571 572 int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0) 573 { 574 unsigned long old_cr0 = kvm_read_cr0(vcpu); 575 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP | 576 X86_CR0_CD | X86_CR0_NW; 577 578 cr0 |= X86_CR0_ET; 579 580 #ifdef CONFIG_X86_64 581 if (cr0 & 0xffffffff00000000UL) 582 return 1; 583 #endif 584 585 cr0 &= ~CR0_RESERVED_BITS; 586 587 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD)) 588 return 1; 589 590 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE)) 591 return 1; 592 593 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) { 594 #ifdef CONFIG_X86_64 595 if ((vcpu->arch.efer & EFER_LME)) { 596 int cs_db, cs_l; 597 598 if (!is_pae(vcpu)) 599 return 1; 600 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l); 601 if (cs_l) 602 return 1; 603 } else 604 #endif 605 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu, 606 kvm_read_cr3(vcpu))) 607 return 1; 608 } 609 610 if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE)) 611 return 1; 612 613 kvm_x86_ops->set_cr0(vcpu, cr0); 614 615 if ((cr0 ^ old_cr0) & X86_CR0_PG) { 616 kvm_clear_async_pf_completion_queue(vcpu); 617 kvm_async_pf_hash_reset(vcpu); 618 } 619 620 if ((cr0 ^ old_cr0) & update_bits) 621 kvm_mmu_reset_context(vcpu); 622 return 0; 623 } 624 EXPORT_SYMBOL_GPL(kvm_set_cr0); 625 626 void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw) 627 { 628 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f)); 629 } 630 EXPORT_SYMBOL_GPL(kvm_lmsw); 631 632 static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu) 633 { 634 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) && 635 !vcpu->guest_xcr0_loaded) { 636 /* kvm_set_xcr() also depends on this */ 637 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0); 638 vcpu->guest_xcr0_loaded = 1; 639 } 640 } 641 642 static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu) 643 { 644 if (vcpu->guest_xcr0_loaded) { 645 if (vcpu->arch.xcr0 != host_xcr0) 646 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0); 647 vcpu->guest_xcr0_loaded = 0; 648 } 649 } 650 651 static int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr) 652 { 653 u64 xcr0 = xcr; 654 u64 old_xcr0 = vcpu->arch.xcr0; 655 u64 valid_bits; 656 657 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */ 658 if (index != XCR_XFEATURE_ENABLED_MASK) 659 return 1; 660 if (!(xcr0 & XSTATE_FP)) 661 return 1; 662 if ((xcr0 & XSTATE_YMM) && !(xcr0 & XSTATE_SSE)) 663 return 1; 664 665 /* 666 * Do not allow the guest to set bits that we do not support 667 * saving. However, xcr0 bit 0 is always set, even if the 668 * emulated CPU does not support XSAVE (see fx_init). 669 */ 670 valid_bits = vcpu->arch.guest_supported_xcr0 | XSTATE_FP; 671 if (xcr0 & ~valid_bits) 672 return 1; 673 674 if ((!(xcr0 & XSTATE_BNDREGS)) != (!(xcr0 & XSTATE_BNDCSR))) 675 return 1; 676 677 if (xcr0 & XSTATE_AVX512) { 678 if (!(xcr0 & XSTATE_YMM)) 679 return 1; 680 if ((xcr0 & XSTATE_AVX512) != XSTATE_AVX512) 681 return 1; 682 } 683 kvm_put_guest_xcr0(vcpu); 684 vcpu->arch.xcr0 = xcr0; 685 686 if ((xcr0 ^ old_xcr0) & XSTATE_EXTEND_MASK) 687 kvm_update_cpuid(vcpu); 688 return 0; 689 } 690 691 int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr) 692 { 693 if (kvm_x86_ops->get_cpl(vcpu) != 0 || 694 __kvm_set_xcr(vcpu, index, xcr)) { 695 kvm_inject_gp(vcpu, 0); 696 return 1; 697 } 698 return 0; 699 } 700 EXPORT_SYMBOL_GPL(kvm_set_xcr); 701 702 int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4) 703 { 704 unsigned long old_cr4 = kvm_read_cr4(vcpu); 705 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | 706 X86_CR4_PAE | X86_CR4_SMEP; 707 if (cr4 & CR4_RESERVED_BITS) 708 return 1; 709 710 if (!guest_cpuid_has_xsave(vcpu) && (cr4 & X86_CR4_OSXSAVE)) 711 return 1; 712 713 if (!guest_cpuid_has_smep(vcpu) && (cr4 & X86_CR4_SMEP)) 714 return 1; 715 716 if (!guest_cpuid_has_smap(vcpu) && (cr4 & X86_CR4_SMAP)) 717 return 1; 718 719 if (!guest_cpuid_has_fsgsbase(vcpu) && (cr4 & X86_CR4_FSGSBASE)) 720 return 1; 721 722 if (is_long_mode(vcpu)) { 723 if (!(cr4 & X86_CR4_PAE)) 724 return 1; 725 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE) 726 && ((cr4 ^ old_cr4) & pdptr_bits) 727 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu, 728 kvm_read_cr3(vcpu))) 729 return 1; 730 731 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) { 732 if (!guest_cpuid_has_pcid(vcpu)) 733 return 1; 734 735 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */ 736 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu)) 737 return 1; 738 } 739 740 if (kvm_x86_ops->set_cr4(vcpu, cr4)) 741 return 1; 742 743 if (((cr4 ^ old_cr4) & pdptr_bits) || 744 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE))) 745 kvm_mmu_reset_context(vcpu); 746 747 if ((cr4 ^ old_cr4) & X86_CR4_SMAP) 748 update_permission_bitmask(vcpu, vcpu->arch.walk_mmu, false); 749 750 if ((cr4 ^ old_cr4) & X86_CR4_OSXSAVE) 751 kvm_update_cpuid(vcpu); 752 753 return 0; 754 } 755 EXPORT_SYMBOL_GPL(kvm_set_cr4); 756 757 int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3) 758 { 759 #ifdef CONFIG_X86_64 760 cr3 &= ~CR3_PCID_INVD; 761 #endif 762 763 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) { 764 kvm_mmu_sync_roots(vcpu); 765 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu); 766 return 0; 767 } 768 769 if (is_long_mode(vcpu)) { 770 if (cr3 & CR3_L_MODE_RESERVED_BITS) 771 return 1; 772 } else if (is_pae(vcpu) && is_paging(vcpu) && 773 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3)) 774 return 1; 775 776 vcpu->arch.cr3 = cr3; 777 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail); 778 kvm_mmu_new_cr3(vcpu); 779 return 0; 780 } 781 EXPORT_SYMBOL_GPL(kvm_set_cr3); 782 783 int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8) 784 { 785 if (cr8 & CR8_RESERVED_BITS) 786 return 1; 787 if (irqchip_in_kernel(vcpu->kvm)) 788 kvm_lapic_set_tpr(vcpu, cr8); 789 else 790 vcpu->arch.cr8 = cr8; 791 return 0; 792 } 793 EXPORT_SYMBOL_GPL(kvm_set_cr8); 794 795 unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu) 796 { 797 if (irqchip_in_kernel(vcpu->kvm)) 798 return kvm_lapic_get_cr8(vcpu); 799 else 800 return vcpu->arch.cr8; 801 } 802 EXPORT_SYMBOL_GPL(kvm_get_cr8); 803 804 static void kvm_update_dr6(struct kvm_vcpu *vcpu) 805 { 806 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) 807 kvm_x86_ops->set_dr6(vcpu, vcpu->arch.dr6); 808 } 809 810 static void kvm_update_dr7(struct kvm_vcpu *vcpu) 811 { 812 unsigned long dr7; 813 814 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) 815 dr7 = vcpu->arch.guest_debug_dr7; 816 else 817 dr7 = vcpu->arch.dr7; 818 kvm_x86_ops->set_dr7(vcpu, dr7); 819 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED; 820 if (dr7 & DR7_BP_EN_MASK) 821 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED; 822 } 823 824 static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu) 825 { 826 u64 fixed = DR6_FIXED_1; 827 828 if (!guest_cpuid_has_rtm(vcpu)) 829 fixed |= DR6_RTM; 830 return fixed; 831 } 832 833 static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val) 834 { 835 switch (dr) { 836 case 0 ... 3: 837 vcpu->arch.db[dr] = val; 838 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) 839 vcpu->arch.eff_db[dr] = val; 840 break; 841 case 4: 842 /* fall through */ 843 case 6: 844 if (val & 0xffffffff00000000ULL) 845 return -1; /* #GP */ 846 vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu); 847 kvm_update_dr6(vcpu); 848 break; 849 case 5: 850 /* fall through */ 851 default: /* 7 */ 852 if (val & 0xffffffff00000000ULL) 853 return -1; /* #GP */ 854 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1; 855 kvm_update_dr7(vcpu); 856 break; 857 } 858 859 return 0; 860 } 861 862 int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val) 863 { 864 if (__kvm_set_dr(vcpu, dr, val)) { 865 kvm_inject_gp(vcpu, 0); 866 return 1; 867 } 868 return 0; 869 } 870 EXPORT_SYMBOL_GPL(kvm_set_dr); 871 872 int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val) 873 { 874 switch (dr) { 875 case 0 ... 3: 876 *val = vcpu->arch.db[dr]; 877 break; 878 case 4: 879 /* fall through */ 880 case 6: 881 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) 882 *val = vcpu->arch.dr6; 883 else 884 *val = kvm_x86_ops->get_dr6(vcpu); 885 break; 886 case 5: 887 /* fall through */ 888 default: /* 7 */ 889 *val = vcpu->arch.dr7; 890 break; 891 } 892 return 0; 893 } 894 EXPORT_SYMBOL_GPL(kvm_get_dr); 895 896 bool kvm_rdpmc(struct kvm_vcpu *vcpu) 897 { 898 u32 ecx = kvm_register_read(vcpu, VCPU_REGS_RCX); 899 u64 data; 900 int err; 901 902 err = kvm_pmu_read_pmc(vcpu, ecx, &data); 903 if (err) 904 return err; 905 kvm_register_write(vcpu, VCPU_REGS_RAX, (u32)data); 906 kvm_register_write(vcpu, VCPU_REGS_RDX, data >> 32); 907 return err; 908 } 909 EXPORT_SYMBOL_GPL(kvm_rdpmc); 910 911 /* 912 * List of msr numbers which we expose to userspace through KVM_GET_MSRS 913 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST. 914 * 915 * This list is modified at module load time to reflect the 916 * capabilities of the host cpu. This capabilities test skips MSRs that are 917 * kvm-specific. Those are put in the beginning of the list. 918 */ 919 920 #define KVM_SAVE_MSRS_BEGIN 12 921 static u32 msrs_to_save[] = { 922 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK, 923 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW, 924 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL, 925 HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC, 926 HV_X64_MSR_APIC_ASSIST_PAGE, MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME, 927 MSR_KVM_PV_EOI_EN, 928 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP, 929 MSR_STAR, 930 #ifdef CONFIG_X86_64 931 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR, 932 #endif 933 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA, 934 MSR_IA32_FEATURE_CONTROL, MSR_IA32_BNDCFGS 935 }; 936 937 static unsigned num_msrs_to_save; 938 939 static const u32 emulated_msrs[] = { 940 MSR_IA32_TSC_ADJUST, 941 MSR_IA32_TSCDEADLINE, 942 MSR_IA32_MISC_ENABLE, 943 MSR_IA32_MCG_STATUS, 944 MSR_IA32_MCG_CTL, 945 }; 946 947 bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer) 948 { 949 if (efer & efer_reserved_bits) 950 return false; 951 952 if (efer & EFER_FFXSR) { 953 struct kvm_cpuid_entry2 *feat; 954 955 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0); 956 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT))) 957 return false; 958 } 959 960 if (efer & EFER_SVME) { 961 struct kvm_cpuid_entry2 *feat; 962 963 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0); 964 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM))) 965 return false; 966 } 967 968 return true; 969 } 970 EXPORT_SYMBOL_GPL(kvm_valid_efer); 971 972 static int set_efer(struct kvm_vcpu *vcpu, u64 efer) 973 { 974 u64 old_efer = vcpu->arch.efer; 975 976 if (!kvm_valid_efer(vcpu, efer)) 977 return 1; 978 979 if (is_paging(vcpu) 980 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME)) 981 return 1; 982 983 efer &= ~EFER_LMA; 984 efer |= vcpu->arch.efer & EFER_LMA; 985 986 kvm_x86_ops->set_efer(vcpu, efer); 987 988 /* Update reserved bits */ 989 if ((efer ^ old_efer) & EFER_NX) 990 kvm_mmu_reset_context(vcpu); 991 992 return 0; 993 } 994 995 void kvm_enable_efer_bits(u64 mask) 996 { 997 efer_reserved_bits &= ~mask; 998 } 999 EXPORT_SYMBOL_GPL(kvm_enable_efer_bits); 1000 1001 /* 1002 * Writes msr value into into the appropriate "register". 1003 * Returns 0 on success, non-0 otherwise. 1004 * Assumes vcpu_load() was already called. 1005 */ 1006 int kvm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr) 1007 { 1008 switch (msr->index) { 1009 case MSR_FS_BASE: 1010 case MSR_GS_BASE: 1011 case MSR_KERNEL_GS_BASE: 1012 case MSR_CSTAR: 1013 case MSR_LSTAR: 1014 if (is_noncanonical_address(msr->data)) 1015 return 1; 1016 break; 1017 case MSR_IA32_SYSENTER_EIP: 1018 case MSR_IA32_SYSENTER_ESP: 1019 /* 1020 * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if 1021 * non-canonical address is written on Intel but not on 1022 * AMD (which ignores the top 32-bits, because it does 1023 * not implement 64-bit SYSENTER). 1024 * 1025 * 64-bit code should hence be able to write a non-canonical 1026 * value on AMD. Making the address canonical ensures that 1027 * vmentry does not fail on Intel after writing a non-canonical 1028 * value, and that something deterministic happens if the guest 1029 * invokes 64-bit SYSENTER. 1030 */ 1031 msr->data = get_canonical(msr->data); 1032 } 1033 return kvm_x86_ops->set_msr(vcpu, msr); 1034 } 1035 EXPORT_SYMBOL_GPL(kvm_set_msr); 1036 1037 /* 1038 * Adapt set_msr() to msr_io()'s calling convention 1039 */ 1040 static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data) 1041 { 1042 struct msr_data msr; 1043 1044 msr.data = *data; 1045 msr.index = index; 1046 msr.host_initiated = true; 1047 return kvm_set_msr(vcpu, &msr); 1048 } 1049 1050 #ifdef CONFIG_X86_64 1051 struct pvclock_gtod_data { 1052 seqcount_t seq; 1053 1054 struct { /* extract of a clocksource struct */ 1055 int vclock_mode; 1056 cycle_t cycle_last; 1057 cycle_t mask; 1058 u32 mult; 1059 u32 shift; 1060 } clock; 1061 1062 u64 boot_ns; 1063 u64 nsec_base; 1064 }; 1065 1066 static struct pvclock_gtod_data pvclock_gtod_data; 1067 1068 static void update_pvclock_gtod(struct timekeeper *tk) 1069 { 1070 struct pvclock_gtod_data *vdata = &pvclock_gtod_data; 1071 u64 boot_ns; 1072 1073 boot_ns = ktime_to_ns(ktime_add(tk->tkr.base_mono, tk->offs_boot)); 1074 1075 write_seqcount_begin(&vdata->seq); 1076 1077 /* copy pvclock gtod data */ 1078 vdata->clock.vclock_mode = tk->tkr.clock->archdata.vclock_mode; 1079 vdata->clock.cycle_last = tk->tkr.cycle_last; 1080 vdata->clock.mask = tk->tkr.mask; 1081 vdata->clock.mult = tk->tkr.mult; 1082 vdata->clock.shift = tk->tkr.shift; 1083 1084 vdata->boot_ns = boot_ns; 1085 vdata->nsec_base = tk->tkr.xtime_nsec; 1086 1087 write_seqcount_end(&vdata->seq); 1088 } 1089 #endif 1090 1091 void kvm_set_pending_timer(struct kvm_vcpu *vcpu) 1092 { 1093 /* 1094 * Note: KVM_REQ_PENDING_TIMER is implicitly checked in 1095 * vcpu_enter_guest. This function is only called from 1096 * the physical CPU that is running vcpu. 1097 */ 1098 kvm_make_request(KVM_REQ_PENDING_TIMER, vcpu); 1099 } 1100 1101 static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock) 1102 { 1103 int version; 1104 int r; 1105 struct pvclock_wall_clock wc; 1106 struct timespec boot; 1107 1108 if (!wall_clock) 1109 return; 1110 1111 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version)); 1112 if (r) 1113 return; 1114 1115 if (version & 1) 1116 ++version; /* first time write, random junk */ 1117 1118 ++version; 1119 1120 kvm_write_guest(kvm, wall_clock, &version, sizeof(version)); 1121 1122 /* 1123 * The guest calculates current wall clock time by adding 1124 * system time (updated by kvm_guest_time_update below) to the 1125 * wall clock specified here. guest system time equals host 1126 * system time for us, thus we must fill in host boot time here. 1127 */ 1128 getboottime(&boot); 1129 1130 if (kvm->arch.kvmclock_offset) { 1131 struct timespec ts = ns_to_timespec(kvm->arch.kvmclock_offset); 1132 boot = timespec_sub(boot, ts); 1133 } 1134 wc.sec = boot.tv_sec; 1135 wc.nsec = boot.tv_nsec; 1136 wc.version = version; 1137 1138 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc)); 1139 1140 version++; 1141 kvm_write_guest(kvm, wall_clock, &version, sizeof(version)); 1142 } 1143 1144 static uint32_t div_frac(uint32_t dividend, uint32_t divisor) 1145 { 1146 uint32_t quotient, remainder; 1147 1148 /* Don't try to replace with do_div(), this one calculates 1149 * "(dividend << 32) / divisor" */ 1150 __asm__ ( "divl %4" 1151 : "=a" (quotient), "=d" (remainder) 1152 : "0" (0), "1" (dividend), "r" (divisor) ); 1153 return quotient; 1154 } 1155 1156 static void kvm_get_time_scale(uint32_t scaled_khz, uint32_t base_khz, 1157 s8 *pshift, u32 *pmultiplier) 1158 { 1159 uint64_t scaled64; 1160 int32_t shift = 0; 1161 uint64_t tps64; 1162 uint32_t tps32; 1163 1164 tps64 = base_khz * 1000LL; 1165 scaled64 = scaled_khz * 1000LL; 1166 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) { 1167 tps64 >>= 1; 1168 shift--; 1169 } 1170 1171 tps32 = (uint32_t)tps64; 1172 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) { 1173 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000) 1174 scaled64 >>= 1; 1175 else 1176 tps32 <<= 1; 1177 shift++; 1178 } 1179 1180 *pshift = shift; 1181 *pmultiplier = div_frac(scaled64, tps32); 1182 1183 pr_debug("%s: base_khz %u => %u, shift %d, mul %u\n", 1184 __func__, base_khz, scaled_khz, shift, *pmultiplier); 1185 } 1186 1187 static inline u64 get_kernel_ns(void) 1188 { 1189 return ktime_get_boot_ns(); 1190 } 1191 1192 #ifdef CONFIG_X86_64 1193 static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0); 1194 #endif 1195 1196 static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz); 1197 static unsigned long max_tsc_khz; 1198 1199 static inline u64 nsec_to_cycles(struct kvm_vcpu *vcpu, u64 nsec) 1200 { 1201 return pvclock_scale_delta(nsec, vcpu->arch.virtual_tsc_mult, 1202 vcpu->arch.virtual_tsc_shift); 1203 } 1204 1205 static u32 adjust_tsc_khz(u32 khz, s32 ppm) 1206 { 1207 u64 v = (u64)khz * (1000000 + ppm); 1208 do_div(v, 1000000); 1209 return v; 1210 } 1211 1212 static void kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 this_tsc_khz) 1213 { 1214 u32 thresh_lo, thresh_hi; 1215 int use_scaling = 0; 1216 1217 /* tsc_khz can be zero if TSC calibration fails */ 1218 if (this_tsc_khz == 0) 1219 return; 1220 1221 /* Compute a scale to convert nanoseconds in TSC cycles */ 1222 kvm_get_time_scale(this_tsc_khz, NSEC_PER_SEC / 1000, 1223 &vcpu->arch.virtual_tsc_shift, 1224 &vcpu->arch.virtual_tsc_mult); 1225 vcpu->arch.virtual_tsc_khz = this_tsc_khz; 1226 1227 /* 1228 * Compute the variation in TSC rate which is acceptable 1229 * within the range of tolerance and decide if the 1230 * rate being applied is within that bounds of the hardware 1231 * rate. If so, no scaling or compensation need be done. 1232 */ 1233 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm); 1234 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm); 1235 if (this_tsc_khz < thresh_lo || this_tsc_khz > thresh_hi) { 1236 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", this_tsc_khz, thresh_lo, thresh_hi); 1237 use_scaling = 1; 1238 } 1239 kvm_x86_ops->set_tsc_khz(vcpu, this_tsc_khz, use_scaling); 1240 } 1241 1242 static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns) 1243 { 1244 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec, 1245 vcpu->arch.virtual_tsc_mult, 1246 vcpu->arch.virtual_tsc_shift); 1247 tsc += vcpu->arch.this_tsc_write; 1248 return tsc; 1249 } 1250 1251 static void kvm_track_tsc_matching(struct kvm_vcpu *vcpu) 1252 { 1253 #ifdef CONFIG_X86_64 1254 bool vcpus_matched; 1255 struct kvm_arch *ka = &vcpu->kvm->arch; 1256 struct pvclock_gtod_data *gtod = &pvclock_gtod_data; 1257 1258 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 == 1259 atomic_read(&vcpu->kvm->online_vcpus)); 1260 1261 /* 1262 * Once the masterclock is enabled, always perform request in 1263 * order to update it. 1264 * 1265 * In order to enable masterclock, the host clocksource must be TSC 1266 * and the vcpus need to have matched TSCs. When that happens, 1267 * perform request to enable masterclock. 1268 */ 1269 if (ka->use_master_clock || 1270 (gtod->clock.vclock_mode == VCLOCK_TSC && vcpus_matched)) 1271 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu); 1272 1273 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc, 1274 atomic_read(&vcpu->kvm->online_vcpus), 1275 ka->use_master_clock, gtod->clock.vclock_mode); 1276 #endif 1277 } 1278 1279 static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset) 1280 { 1281 u64 curr_offset = kvm_x86_ops->read_tsc_offset(vcpu); 1282 vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset; 1283 } 1284 1285 void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr) 1286 { 1287 struct kvm *kvm = vcpu->kvm; 1288 u64 offset, ns, elapsed; 1289 unsigned long flags; 1290 s64 usdiff; 1291 bool matched; 1292 bool already_matched; 1293 u64 data = msr->data; 1294 1295 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags); 1296 offset = kvm_x86_ops->compute_tsc_offset(vcpu, data); 1297 ns = get_kernel_ns(); 1298 elapsed = ns - kvm->arch.last_tsc_nsec; 1299 1300 if (vcpu->arch.virtual_tsc_khz) { 1301 int faulted = 0; 1302 1303 /* n.b - signed multiplication and division required */ 1304 usdiff = data - kvm->arch.last_tsc_write; 1305 #ifdef CONFIG_X86_64 1306 usdiff = (usdiff * 1000) / vcpu->arch.virtual_tsc_khz; 1307 #else 1308 /* do_div() only does unsigned */ 1309 asm("1: idivl %[divisor]\n" 1310 "2: xor %%edx, %%edx\n" 1311 " movl $0, %[faulted]\n" 1312 "3:\n" 1313 ".section .fixup,\"ax\"\n" 1314 "4: movl $1, %[faulted]\n" 1315 " jmp 3b\n" 1316 ".previous\n" 1317 1318 _ASM_EXTABLE(1b, 4b) 1319 1320 : "=A"(usdiff), [faulted] "=r" (faulted) 1321 : "A"(usdiff * 1000), [divisor] "rm"(vcpu->arch.virtual_tsc_khz)); 1322 1323 #endif 1324 do_div(elapsed, 1000); 1325 usdiff -= elapsed; 1326 if (usdiff < 0) 1327 usdiff = -usdiff; 1328 1329 /* idivl overflow => difference is larger than USEC_PER_SEC */ 1330 if (faulted) 1331 usdiff = USEC_PER_SEC; 1332 } else 1333 usdiff = USEC_PER_SEC; /* disable TSC match window below */ 1334 1335 /* 1336 * Special case: TSC write with a small delta (1 second) of virtual 1337 * cycle time against real time is interpreted as an attempt to 1338 * synchronize the CPU. 1339 * 1340 * For a reliable TSC, we can match TSC offsets, and for an unstable 1341 * TSC, we add elapsed time in this computation. We could let the 1342 * compensation code attempt to catch up if we fall behind, but 1343 * it's better to try to match offsets from the beginning. 1344 */ 1345 if (usdiff < USEC_PER_SEC && 1346 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) { 1347 if (!check_tsc_unstable()) { 1348 offset = kvm->arch.cur_tsc_offset; 1349 pr_debug("kvm: matched tsc offset for %llu\n", data); 1350 } else { 1351 u64 delta = nsec_to_cycles(vcpu, elapsed); 1352 data += delta; 1353 offset = kvm_x86_ops->compute_tsc_offset(vcpu, data); 1354 pr_debug("kvm: adjusted tsc offset by %llu\n", delta); 1355 } 1356 matched = true; 1357 already_matched = (vcpu->arch.this_tsc_generation == kvm->arch.cur_tsc_generation); 1358 } else { 1359 /* 1360 * We split periods of matched TSC writes into generations. 1361 * For each generation, we track the original measured 1362 * nanosecond time, offset, and write, so if TSCs are in 1363 * sync, we can match exact offset, and if not, we can match 1364 * exact software computation in compute_guest_tsc() 1365 * 1366 * These values are tracked in kvm->arch.cur_xxx variables. 1367 */ 1368 kvm->arch.cur_tsc_generation++; 1369 kvm->arch.cur_tsc_nsec = ns; 1370 kvm->arch.cur_tsc_write = data; 1371 kvm->arch.cur_tsc_offset = offset; 1372 matched = false; 1373 pr_debug("kvm: new tsc generation %llu, clock %llu\n", 1374 kvm->arch.cur_tsc_generation, data); 1375 } 1376 1377 /* 1378 * We also track th most recent recorded KHZ, write and time to 1379 * allow the matching interval to be extended at each write. 1380 */ 1381 kvm->arch.last_tsc_nsec = ns; 1382 kvm->arch.last_tsc_write = data; 1383 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz; 1384 1385 vcpu->arch.last_guest_tsc = data; 1386 1387 /* Keep track of which generation this VCPU has synchronized to */ 1388 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation; 1389 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec; 1390 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write; 1391 1392 if (guest_cpuid_has_tsc_adjust(vcpu) && !msr->host_initiated) 1393 update_ia32_tsc_adjust_msr(vcpu, offset); 1394 kvm_x86_ops->write_tsc_offset(vcpu, offset); 1395 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags); 1396 1397 spin_lock(&kvm->arch.pvclock_gtod_sync_lock); 1398 if (!matched) { 1399 kvm->arch.nr_vcpus_matched_tsc = 0; 1400 } else if (!already_matched) { 1401 kvm->arch.nr_vcpus_matched_tsc++; 1402 } 1403 1404 kvm_track_tsc_matching(vcpu); 1405 spin_unlock(&kvm->arch.pvclock_gtod_sync_lock); 1406 } 1407 1408 EXPORT_SYMBOL_GPL(kvm_write_tsc); 1409 1410 #ifdef CONFIG_X86_64 1411 1412 static cycle_t read_tsc(void) 1413 { 1414 cycle_t ret; 1415 u64 last; 1416 1417 /* 1418 * Empirically, a fence (of type that depends on the CPU) 1419 * before rdtsc is enough to ensure that rdtsc is ordered 1420 * with respect to loads. The various CPU manuals are unclear 1421 * as to whether rdtsc can be reordered with later loads, 1422 * but no one has ever seen it happen. 1423 */ 1424 rdtsc_barrier(); 1425 ret = (cycle_t)vget_cycles(); 1426 1427 last = pvclock_gtod_data.clock.cycle_last; 1428 1429 if (likely(ret >= last)) 1430 return ret; 1431 1432 /* 1433 * GCC likes to generate cmov here, but this branch is extremely 1434 * predictable (it's just a funciton of time and the likely is 1435 * very likely) and there's a data dependence, so force GCC 1436 * to generate a branch instead. I don't barrier() because 1437 * we don't actually need a barrier, and if this function 1438 * ever gets inlined it will generate worse code. 1439 */ 1440 asm volatile (""); 1441 return last; 1442 } 1443 1444 static inline u64 vgettsc(cycle_t *cycle_now) 1445 { 1446 long v; 1447 struct pvclock_gtod_data *gtod = &pvclock_gtod_data; 1448 1449 *cycle_now = read_tsc(); 1450 1451 v = (*cycle_now - gtod->clock.cycle_last) & gtod->clock.mask; 1452 return v * gtod->clock.mult; 1453 } 1454 1455 static int do_monotonic_boot(s64 *t, cycle_t *cycle_now) 1456 { 1457 struct pvclock_gtod_data *gtod = &pvclock_gtod_data; 1458 unsigned long seq; 1459 int mode; 1460 u64 ns; 1461 1462 do { 1463 seq = read_seqcount_begin(>od->seq); 1464 mode = gtod->clock.vclock_mode; 1465 ns = gtod->nsec_base; 1466 ns += vgettsc(cycle_now); 1467 ns >>= gtod->clock.shift; 1468 ns += gtod->boot_ns; 1469 } while (unlikely(read_seqcount_retry(>od->seq, seq))); 1470 *t = ns; 1471 1472 return mode; 1473 } 1474 1475 /* returns true if host is using tsc clocksource */ 1476 static bool kvm_get_time_and_clockread(s64 *kernel_ns, cycle_t *cycle_now) 1477 { 1478 /* checked again under seqlock below */ 1479 if (pvclock_gtod_data.clock.vclock_mode != VCLOCK_TSC) 1480 return false; 1481 1482 return do_monotonic_boot(kernel_ns, cycle_now) == VCLOCK_TSC; 1483 } 1484 #endif 1485 1486 /* 1487 * 1488 * Assuming a stable TSC across physical CPUS, and a stable TSC 1489 * across virtual CPUs, the following condition is possible. 1490 * Each numbered line represents an event visible to both 1491 * CPUs at the next numbered event. 1492 * 1493 * "timespecX" represents host monotonic time. "tscX" represents 1494 * RDTSC value. 1495 * 1496 * VCPU0 on CPU0 | VCPU1 on CPU1 1497 * 1498 * 1. read timespec0,tsc0 1499 * 2. | timespec1 = timespec0 + N 1500 * | tsc1 = tsc0 + M 1501 * 3. transition to guest | transition to guest 1502 * 4. ret0 = timespec0 + (rdtsc - tsc0) | 1503 * 5. | ret1 = timespec1 + (rdtsc - tsc1) 1504 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M)) 1505 * 1506 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity: 1507 * 1508 * - ret0 < ret1 1509 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M)) 1510 * ... 1511 * - 0 < N - M => M < N 1512 * 1513 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not 1514 * always the case (the difference between two distinct xtime instances 1515 * might be smaller then the difference between corresponding TSC reads, 1516 * when updating guest vcpus pvclock areas). 1517 * 1518 * To avoid that problem, do not allow visibility of distinct 1519 * system_timestamp/tsc_timestamp values simultaneously: use a master 1520 * copy of host monotonic time values. Update that master copy 1521 * in lockstep. 1522 * 1523 * Rely on synchronization of host TSCs and guest TSCs for monotonicity. 1524 * 1525 */ 1526 1527 static void pvclock_update_vm_gtod_copy(struct kvm *kvm) 1528 { 1529 #ifdef CONFIG_X86_64 1530 struct kvm_arch *ka = &kvm->arch; 1531 int vclock_mode; 1532 bool host_tsc_clocksource, vcpus_matched; 1533 1534 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 == 1535 atomic_read(&kvm->online_vcpus)); 1536 1537 /* 1538 * If the host uses TSC clock, then passthrough TSC as stable 1539 * to the guest. 1540 */ 1541 host_tsc_clocksource = kvm_get_time_and_clockread( 1542 &ka->master_kernel_ns, 1543 &ka->master_cycle_now); 1544 1545 ka->use_master_clock = host_tsc_clocksource && vcpus_matched 1546 && !backwards_tsc_observed 1547 && !ka->boot_vcpu_runs_old_kvmclock; 1548 1549 if (ka->use_master_clock) 1550 atomic_set(&kvm_guest_has_master_clock, 1); 1551 1552 vclock_mode = pvclock_gtod_data.clock.vclock_mode; 1553 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode, 1554 vcpus_matched); 1555 #endif 1556 } 1557 1558 static void kvm_gen_update_masterclock(struct kvm *kvm) 1559 { 1560 #ifdef CONFIG_X86_64 1561 int i; 1562 struct kvm_vcpu *vcpu; 1563 struct kvm_arch *ka = &kvm->arch; 1564 1565 spin_lock(&ka->pvclock_gtod_sync_lock); 1566 kvm_make_mclock_inprogress_request(kvm); 1567 /* no guest entries from this point */ 1568 pvclock_update_vm_gtod_copy(kvm); 1569 1570 kvm_for_each_vcpu(i, vcpu, kvm) 1571 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 1572 1573 /* guest entries allowed */ 1574 kvm_for_each_vcpu(i, vcpu, kvm) 1575 clear_bit(KVM_REQ_MCLOCK_INPROGRESS, &vcpu->requests); 1576 1577 spin_unlock(&ka->pvclock_gtod_sync_lock); 1578 #endif 1579 } 1580 1581 static int kvm_guest_time_update(struct kvm_vcpu *v) 1582 { 1583 unsigned long flags, this_tsc_khz; 1584 struct kvm_vcpu_arch *vcpu = &v->arch; 1585 struct kvm_arch *ka = &v->kvm->arch; 1586 s64 kernel_ns; 1587 u64 tsc_timestamp, host_tsc; 1588 struct pvclock_vcpu_time_info guest_hv_clock; 1589 u8 pvclock_flags; 1590 bool use_master_clock; 1591 1592 kernel_ns = 0; 1593 host_tsc = 0; 1594 1595 /* 1596 * If the host uses TSC clock, then passthrough TSC as stable 1597 * to the guest. 1598 */ 1599 spin_lock(&ka->pvclock_gtod_sync_lock); 1600 use_master_clock = ka->use_master_clock; 1601 if (use_master_clock) { 1602 host_tsc = ka->master_cycle_now; 1603 kernel_ns = ka->master_kernel_ns; 1604 } 1605 spin_unlock(&ka->pvclock_gtod_sync_lock); 1606 1607 /* Keep irq disabled to prevent changes to the clock */ 1608 local_irq_save(flags); 1609 this_tsc_khz = __this_cpu_read(cpu_tsc_khz); 1610 if (unlikely(this_tsc_khz == 0)) { 1611 local_irq_restore(flags); 1612 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v); 1613 return 1; 1614 } 1615 if (!use_master_clock) { 1616 host_tsc = native_read_tsc(); 1617 kernel_ns = get_kernel_ns(); 1618 } 1619 1620 tsc_timestamp = kvm_x86_ops->read_l1_tsc(v, host_tsc); 1621 1622 /* 1623 * We may have to catch up the TSC to match elapsed wall clock 1624 * time for two reasons, even if kvmclock is used. 1625 * 1) CPU could have been running below the maximum TSC rate 1626 * 2) Broken TSC compensation resets the base at each VCPU 1627 * entry to avoid unknown leaps of TSC even when running 1628 * again on the same CPU. This may cause apparent elapsed 1629 * time to disappear, and the guest to stand still or run 1630 * very slowly. 1631 */ 1632 if (vcpu->tsc_catchup) { 1633 u64 tsc = compute_guest_tsc(v, kernel_ns); 1634 if (tsc > tsc_timestamp) { 1635 adjust_tsc_offset_guest(v, tsc - tsc_timestamp); 1636 tsc_timestamp = tsc; 1637 } 1638 } 1639 1640 local_irq_restore(flags); 1641 1642 if (!vcpu->pv_time_enabled) 1643 return 0; 1644 1645 if (unlikely(vcpu->hw_tsc_khz != this_tsc_khz)) { 1646 kvm_get_time_scale(NSEC_PER_SEC / 1000, this_tsc_khz, 1647 &vcpu->hv_clock.tsc_shift, 1648 &vcpu->hv_clock.tsc_to_system_mul); 1649 vcpu->hw_tsc_khz = this_tsc_khz; 1650 } 1651 1652 /* With all the info we got, fill in the values */ 1653 vcpu->hv_clock.tsc_timestamp = tsc_timestamp; 1654 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset; 1655 vcpu->last_guest_tsc = tsc_timestamp; 1656 1657 if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time, 1658 &guest_hv_clock, sizeof(guest_hv_clock)))) 1659 return 0; 1660 1661 /* 1662 * The interface expects us to write an even number signaling that the 1663 * update is finished. Since the guest won't see the intermediate 1664 * state, we just increase by 2 at the end. 1665 */ 1666 vcpu->hv_clock.version = guest_hv_clock.version + 2; 1667 1668 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */ 1669 pvclock_flags = (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED); 1670 1671 if (vcpu->pvclock_set_guest_stopped_request) { 1672 pvclock_flags |= PVCLOCK_GUEST_STOPPED; 1673 vcpu->pvclock_set_guest_stopped_request = false; 1674 } 1675 1676 /* If the host uses TSC clocksource, then it is stable */ 1677 if (use_master_clock) 1678 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT; 1679 1680 vcpu->hv_clock.flags = pvclock_flags; 1681 1682 trace_kvm_pvclock_update(v->vcpu_id, &vcpu->hv_clock); 1683 1684 kvm_write_guest_cached(v->kvm, &vcpu->pv_time, 1685 &vcpu->hv_clock, 1686 sizeof(vcpu->hv_clock)); 1687 return 0; 1688 } 1689 1690 /* 1691 * kvmclock updates which are isolated to a given vcpu, such as 1692 * vcpu->cpu migration, should not allow system_timestamp from 1693 * the rest of the vcpus to remain static. Otherwise ntp frequency 1694 * correction applies to one vcpu's system_timestamp but not 1695 * the others. 1696 * 1697 * So in those cases, request a kvmclock update for all vcpus. 1698 * We need to rate-limit these requests though, as they can 1699 * considerably slow guests that have a large number of vcpus. 1700 * The time for a remote vcpu to update its kvmclock is bound 1701 * by the delay we use to rate-limit the updates. 1702 */ 1703 1704 #define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100) 1705 1706 static void kvmclock_update_fn(struct work_struct *work) 1707 { 1708 int i; 1709 struct delayed_work *dwork = to_delayed_work(work); 1710 struct kvm_arch *ka = container_of(dwork, struct kvm_arch, 1711 kvmclock_update_work); 1712 struct kvm *kvm = container_of(ka, struct kvm, arch); 1713 struct kvm_vcpu *vcpu; 1714 1715 kvm_for_each_vcpu(i, vcpu, kvm) { 1716 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 1717 kvm_vcpu_kick(vcpu); 1718 } 1719 } 1720 1721 static void kvm_gen_kvmclock_update(struct kvm_vcpu *v) 1722 { 1723 struct kvm *kvm = v->kvm; 1724 1725 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v); 1726 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 1727 KVMCLOCK_UPDATE_DELAY); 1728 } 1729 1730 #define KVMCLOCK_SYNC_PERIOD (300 * HZ) 1731 1732 static void kvmclock_sync_fn(struct work_struct *work) 1733 { 1734 struct delayed_work *dwork = to_delayed_work(work); 1735 struct kvm_arch *ka = container_of(dwork, struct kvm_arch, 1736 kvmclock_sync_work); 1737 struct kvm *kvm = container_of(ka, struct kvm, arch); 1738 1739 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0); 1740 schedule_delayed_work(&kvm->arch.kvmclock_sync_work, 1741 KVMCLOCK_SYNC_PERIOD); 1742 } 1743 1744 static bool msr_mtrr_valid(unsigned msr) 1745 { 1746 switch (msr) { 1747 case 0x200 ... 0x200 + 2 * KVM_NR_VAR_MTRR - 1: 1748 case MSR_MTRRfix64K_00000: 1749 case MSR_MTRRfix16K_80000: 1750 case MSR_MTRRfix16K_A0000: 1751 case MSR_MTRRfix4K_C0000: 1752 case MSR_MTRRfix4K_C8000: 1753 case MSR_MTRRfix4K_D0000: 1754 case MSR_MTRRfix4K_D8000: 1755 case MSR_MTRRfix4K_E0000: 1756 case MSR_MTRRfix4K_E8000: 1757 case MSR_MTRRfix4K_F0000: 1758 case MSR_MTRRfix4K_F8000: 1759 case MSR_MTRRdefType: 1760 case MSR_IA32_CR_PAT: 1761 return true; 1762 case 0x2f8: 1763 return true; 1764 } 1765 return false; 1766 } 1767 1768 static bool valid_pat_type(unsigned t) 1769 { 1770 return t < 8 && (1 << t) & 0xf3; /* 0, 1, 4, 5, 6, 7 */ 1771 } 1772 1773 static bool valid_mtrr_type(unsigned t) 1774 { 1775 return t < 8 && (1 << t) & 0x73; /* 0, 1, 4, 5, 6 */ 1776 } 1777 1778 bool kvm_mtrr_valid(struct kvm_vcpu *vcpu, u32 msr, u64 data) 1779 { 1780 int i; 1781 u64 mask; 1782 1783 if (!msr_mtrr_valid(msr)) 1784 return false; 1785 1786 if (msr == MSR_IA32_CR_PAT) { 1787 for (i = 0; i < 8; i++) 1788 if (!valid_pat_type((data >> (i * 8)) & 0xff)) 1789 return false; 1790 return true; 1791 } else if (msr == MSR_MTRRdefType) { 1792 if (data & ~0xcff) 1793 return false; 1794 return valid_mtrr_type(data & 0xff); 1795 } else if (msr >= MSR_MTRRfix64K_00000 && msr <= MSR_MTRRfix4K_F8000) { 1796 for (i = 0; i < 8 ; i++) 1797 if (!valid_mtrr_type((data >> (i * 8)) & 0xff)) 1798 return false; 1799 return true; 1800 } 1801 1802 /* variable MTRRs */ 1803 WARN_ON(!(msr >= 0x200 && msr < 0x200 + 2 * KVM_NR_VAR_MTRR)); 1804 1805 mask = (~0ULL) << cpuid_maxphyaddr(vcpu); 1806 if ((msr & 1) == 0) { 1807 /* MTRR base */ 1808 if (!valid_mtrr_type(data & 0xff)) 1809 return false; 1810 mask |= 0xf00; 1811 } else 1812 /* MTRR mask */ 1813 mask |= 0x7ff; 1814 if (data & mask) { 1815 kvm_inject_gp(vcpu, 0); 1816 return false; 1817 } 1818 1819 return true; 1820 } 1821 EXPORT_SYMBOL_GPL(kvm_mtrr_valid); 1822 1823 static int set_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 data) 1824 { 1825 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges; 1826 1827 if (!kvm_mtrr_valid(vcpu, msr, data)) 1828 return 1; 1829 1830 if (msr == MSR_MTRRdefType) { 1831 vcpu->arch.mtrr_state.def_type = data; 1832 vcpu->arch.mtrr_state.enabled = (data & 0xc00) >> 10; 1833 } else if (msr == MSR_MTRRfix64K_00000) 1834 p[0] = data; 1835 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000) 1836 p[1 + msr - MSR_MTRRfix16K_80000] = data; 1837 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000) 1838 p[3 + msr - MSR_MTRRfix4K_C0000] = data; 1839 else if (msr == MSR_IA32_CR_PAT) 1840 vcpu->arch.pat = data; 1841 else { /* Variable MTRRs */ 1842 int idx, is_mtrr_mask; 1843 u64 *pt; 1844 1845 idx = (msr - 0x200) / 2; 1846 is_mtrr_mask = msr - 0x200 - 2 * idx; 1847 if (!is_mtrr_mask) 1848 pt = 1849 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo; 1850 else 1851 pt = 1852 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo; 1853 *pt = data; 1854 } 1855 1856 kvm_mmu_reset_context(vcpu); 1857 return 0; 1858 } 1859 1860 static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data) 1861 { 1862 u64 mcg_cap = vcpu->arch.mcg_cap; 1863 unsigned bank_num = mcg_cap & 0xff; 1864 1865 switch (msr) { 1866 case MSR_IA32_MCG_STATUS: 1867 vcpu->arch.mcg_status = data; 1868 break; 1869 case MSR_IA32_MCG_CTL: 1870 if (!(mcg_cap & MCG_CTL_P)) 1871 return 1; 1872 if (data != 0 && data != ~(u64)0) 1873 return -1; 1874 vcpu->arch.mcg_ctl = data; 1875 break; 1876 default: 1877 if (msr >= MSR_IA32_MC0_CTL && 1878 msr < MSR_IA32_MCx_CTL(bank_num)) { 1879 u32 offset = msr - MSR_IA32_MC0_CTL; 1880 /* only 0 or all 1s can be written to IA32_MCi_CTL 1881 * some Linux kernels though clear bit 10 in bank 4 to 1882 * workaround a BIOS/GART TBL issue on AMD K8s, ignore 1883 * this to avoid an uncatched #GP in the guest 1884 */ 1885 if ((offset & 0x3) == 0 && 1886 data != 0 && (data | (1 << 10)) != ~(u64)0) 1887 return -1; 1888 vcpu->arch.mce_banks[offset] = data; 1889 break; 1890 } 1891 return 1; 1892 } 1893 return 0; 1894 } 1895 1896 static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data) 1897 { 1898 struct kvm *kvm = vcpu->kvm; 1899 int lm = is_long_mode(vcpu); 1900 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64 1901 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32; 1902 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64 1903 : kvm->arch.xen_hvm_config.blob_size_32; 1904 u32 page_num = data & ~PAGE_MASK; 1905 u64 page_addr = data & PAGE_MASK; 1906 u8 *page; 1907 int r; 1908 1909 r = -E2BIG; 1910 if (page_num >= blob_size) 1911 goto out; 1912 r = -ENOMEM; 1913 page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE); 1914 if (IS_ERR(page)) { 1915 r = PTR_ERR(page); 1916 goto out; 1917 } 1918 if (kvm_write_guest(kvm, page_addr, page, PAGE_SIZE)) 1919 goto out_free; 1920 r = 0; 1921 out_free: 1922 kfree(page); 1923 out: 1924 return r; 1925 } 1926 1927 static bool kvm_hv_hypercall_enabled(struct kvm *kvm) 1928 { 1929 return kvm->arch.hv_hypercall & HV_X64_MSR_HYPERCALL_ENABLE; 1930 } 1931 1932 static bool kvm_hv_msr_partition_wide(u32 msr) 1933 { 1934 bool r = false; 1935 switch (msr) { 1936 case HV_X64_MSR_GUEST_OS_ID: 1937 case HV_X64_MSR_HYPERCALL: 1938 case HV_X64_MSR_REFERENCE_TSC: 1939 case HV_X64_MSR_TIME_REF_COUNT: 1940 r = true; 1941 break; 1942 } 1943 1944 return r; 1945 } 1946 1947 static int set_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 data) 1948 { 1949 struct kvm *kvm = vcpu->kvm; 1950 1951 switch (msr) { 1952 case HV_X64_MSR_GUEST_OS_ID: 1953 kvm->arch.hv_guest_os_id = data; 1954 /* setting guest os id to zero disables hypercall page */ 1955 if (!kvm->arch.hv_guest_os_id) 1956 kvm->arch.hv_hypercall &= ~HV_X64_MSR_HYPERCALL_ENABLE; 1957 break; 1958 case HV_X64_MSR_HYPERCALL: { 1959 u64 gfn; 1960 unsigned long addr; 1961 u8 instructions[4]; 1962 1963 /* if guest os id is not set hypercall should remain disabled */ 1964 if (!kvm->arch.hv_guest_os_id) 1965 break; 1966 if (!(data & HV_X64_MSR_HYPERCALL_ENABLE)) { 1967 kvm->arch.hv_hypercall = data; 1968 break; 1969 } 1970 gfn = data >> HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT; 1971 addr = gfn_to_hva(kvm, gfn); 1972 if (kvm_is_error_hva(addr)) 1973 return 1; 1974 kvm_x86_ops->patch_hypercall(vcpu, instructions); 1975 ((unsigned char *)instructions)[3] = 0xc3; /* ret */ 1976 if (__copy_to_user((void __user *)addr, instructions, 4)) 1977 return 1; 1978 kvm->arch.hv_hypercall = data; 1979 mark_page_dirty(kvm, gfn); 1980 break; 1981 } 1982 case HV_X64_MSR_REFERENCE_TSC: { 1983 u64 gfn; 1984 HV_REFERENCE_TSC_PAGE tsc_ref; 1985 memset(&tsc_ref, 0, sizeof(tsc_ref)); 1986 kvm->arch.hv_tsc_page = data; 1987 if (!(data & HV_X64_MSR_TSC_REFERENCE_ENABLE)) 1988 break; 1989 gfn = data >> HV_X64_MSR_TSC_REFERENCE_ADDRESS_SHIFT; 1990 if (kvm_write_guest(kvm, gfn << HV_X64_MSR_TSC_REFERENCE_ADDRESS_SHIFT, 1991 &tsc_ref, sizeof(tsc_ref))) 1992 return 1; 1993 mark_page_dirty(kvm, gfn); 1994 break; 1995 } 1996 default: 1997 vcpu_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x " 1998 "data 0x%llx\n", msr, data); 1999 return 1; 2000 } 2001 return 0; 2002 } 2003 2004 static int set_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 data) 2005 { 2006 switch (msr) { 2007 case HV_X64_MSR_APIC_ASSIST_PAGE: { 2008 u64 gfn; 2009 unsigned long addr; 2010 2011 if (!(data & HV_X64_MSR_APIC_ASSIST_PAGE_ENABLE)) { 2012 vcpu->arch.hv_vapic = data; 2013 if (kvm_lapic_enable_pv_eoi(vcpu, 0)) 2014 return 1; 2015 break; 2016 } 2017 gfn = data >> HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_SHIFT; 2018 addr = gfn_to_hva(vcpu->kvm, gfn); 2019 if (kvm_is_error_hva(addr)) 2020 return 1; 2021 if (__clear_user((void __user *)addr, PAGE_SIZE)) 2022 return 1; 2023 vcpu->arch.hv_vapic = data; 2024 mark_page_dirty(vcpu->kvm, gfn); 2025 if (kvm_lapic_enable_pv_eoi(vcpu, gfn_to_gpa(gfn) | KVM_MSR_ENABLED)) 2026 return 1; 2027 break; 2028 } 2029 case HV_X64_MSR_EOI: 2030 return kvm_hv_vapic_msr_write(vcpu, APIC_EOI, data); 2031 case HV_X64_MSR_ICR: 2032 return kvm_hv_vapic_msr_write(vcpu, APIC_ICR, data); 2033 case HV_X64_MSR_TPR: 2034 return kvm_hv_vapic_msr_write(vcpu, APIC_TASKPRI, data); 2035 default: 2036 vcpu_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x " 2037 "data 0x%llx\n", msr, data); 2038 return 1; 2039 } 2040 2041 return 0; 2042 } 2043 2044 static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data) 2045 { 2046 gpa_t gpa = data & ~0x3f; 2047 2048 /* Bits 2:5 are reserved, Should be zero */ 2049 if (data & 0x3c) 2050 return 1; 2051 2052 vcpu->arch.apf.msr_val = data; 2053 2054 if (!(data & KVM_ASYNC_PF_ENABLED)) { 2055 kvm_clear_async_pf_completion_queue(vcpu); 2056 kvm_async_pf_hash_reset(vcpu); 2057 return 0; 2058 } 2059 2060 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa, 2061 sizeof(u32))) 2062 return 1; 2063 2064 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS); 2065 kvm_async_pf_wakeup_all(vcpu); 2066 return 0; 2067 } 2068 2069 static void kvmclock_reset(struct kvm_vcpu *vcpu) 2070 { 2071 vcpu->arch.pv_time_enabled = false; 2072 } 2073 2074 static void accumulate_steal_time(struct kvm_vcpu *vcpu) 2075 { 2076 u64 delta; 2077 2078 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED)) 2079 return; 2080 2081 delta = current->sched_info.run_delay - vcpu->arch.st.last_steal; 2082 vcpu->arch.st.last_steal = current->sched_info.run_delay; 2083 vcpu->arch.st.accum_steal = delta; 2084 } 2085 2086 static void record_steal_time(struct kvm_vcpu *vcpu) 2087 { 2088 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED)) 2089 return; 2090 2091 if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime, 2092 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time)))) 2093 return; 2094 2095 vcpu->arch.st.steal.steal += vcpu->arch.st.accum_steal; 2096 vcpu->arch.st.steal.version += 2; 2097 vcpu->arch.st.accum_steal = 0; 2098 2099 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime, 2100 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time)); 2101 } 2102 2103 int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info) 2104 { 2105 bool pr = false; 2106 u32 msr = msr_info->index; 2107 u64 data = msr_info->data; 2108 2109 switch (msr) { 2110 case MSR_AMD64_NB_CFG: 2111 case MSR_IA32_UCODE_REV: 2112 case MSR_IA32_UCODE_WRITE: 2113 case MSR_VM_HSAVE_PA: 2114 case MSR_AMD64_PATCH_LOADER: 2115 case MSR_AMD64_BU_CFG2: 2116 break; 2117 2118 case MSR_EFER: 2119 return set_efer(vcpu, data); 2120 case MSR_K7_HWCR: 2121 data &= ~(u64)0x40; /* ignore flush filter disable */ 2122 data &= ~(u64)0x100; /* ignore ignne emulation enable */ 2123 data &= ~(u64)0x8; /* ignore TLB cache disable */ 2124 data &= ~(u64)0x40000; /* ignore Mc status write enable */ 2125 if (data != 0) { 2126 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n", 2127 data); 2128 return 1; 2129 } 2130 break; 2131 case MSR_FAM10H_MMIO_CONF_BASE: 2132 if (data != 0) { 2133 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: " 2134 "0x%llx\n", data); 2135 return 1; 2136 } 2137 break; 2138 case MSR_IA32_DEBUGCTLMSR: 2139 if (!data) { 2140 /* We support the non-activated case already */ 2141 break; 2142 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) { 2143 /* Values other than LBR and BTF are vendor-specific, 2144 thus reserved and should throw a #GP */ 2145 return 1; 2146 } 2147 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n", 2148 __func__, data); 2149 break; 2150 case 0x200 ... 0x2ff: 2151 return set_msr_mtrr(vcpu, msr, data); 2152 case MSR_IA32_APICBASE: 2153 return kvm_set_apic_base(vcpu, msr_info); 2154 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff: 2155 return kvm_x2apic_msr_write(vcpu, msr, data); 2156 case MSR_IA32_TSCDEADLINE: 2157 kvm_set_lapic_tscdeadline_msr(vcpu, data); 2158 break; 2159 case MSR_IA32_TSC_ADJUST: 2160 if (guest_cpuid_has_tsc_adjust(vcpu)) { 2161 if (!msr_info->host_initiated) { 2162 s64 adj = data - vcpu->arch.ia32_tsc_adjust_msr; 2163 kvm_x86_ops->adjust_tsc_offset(vcpu, adj, true); 2164 } 2165 vcpu->arch.ia32_tsc_adjust_msr = data; 2166 } 2167 break; 2168 case MSR_IA32_MISC_ENABLE: 2169 vcpu->arch.ia32_misc_enable_msr = data; 2170 break; 2171 case MSR_KVM_WALL_CLOCK_NEW: 2172 case MSR_KVM_WALL_CLOCK: 2173 vcpu->kvm->arch.wall_clock = data; 2174 kvm_write_wall_clock(vcpu->kvm, data); 2175 break; 2176 case MSR_KVM_SYSTEM_TIME_NEW: 2177 case MSR_KVM_SYSTEM_TIME: { 2178 u64 gpa_offset; 2179 struct kvm_arch *ka = &vcpu->kvm->arch; 2180 2181 kvmclock_reset(vcpu); 2182 2183 if (vcpu->vcpu_id == 0 && !msr_info->host_initiated) { 2184 bool tmp = (msr == MSR_KVM_SYSTEM_TIME); 2185 2186 if (ka->boot_vcpu_runs_old_kvmclock != tmp) 2187 set_bit(KVM_REQ_MASTERCLOCK_UPDATE, 2188 &vcpu->requests); 2189 2190 ka->boot_vcpu_runs_old_kvmclock = tmp; 2191 } 2192 2193 vcpu->arch.time = data; 2194 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu); 2195 2196 /* we verify if the enable bit is set... */ 2197 if (!(data & 1)) 2198 break; 2199 2200 gpa_offset = data & ~(PAGE_MASK | 1); 2201 2202 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, 2203 &vcpu->arch.pv_time, data & ~1ULL, 2204 sizeof(struct pvclock_vcpu_time_info))) 2205 vcpu->arch.pv_time_enabled = false; 2206 else 2207 vcpu->arch.pv_time_enabled = true; 2208 2209 break; 2210 } 2211 case MSR_KVM_ASYNC_PF_EN: 2212 if (kvm_pv_enable_async_pf(vcpu, data)) 2213 return 1; 2214 break; 2215 case MSR_KVM_STEAL_TIME: 2216 2217 if (unlikely(!sched_info_on())) 2218 return 1; 2219 2220 if (data & KVM_STEAL_RESERVED_MASK) 2221 return 1; 2222 2223 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime, 2224 data & KVM_STEAL_VALID_BITS, 2225 sizeof(struct kvm_steal_time))) 2226 return 1; 2227 2228 vcpu->arch.st.msr_val = data; 2229 2230 if (!(data & KVM_MSR_ENABLED)) 2231 break; 2232 2233 vcpu->arch.st.last_steal = current->sched_info.run_delay; 2234 2235 preempt_disable(); 2236 accumulate_steal_time(vcpu); 2237 preempt_enable(); 2238 2239 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu); 2240 2241 break; 2242 case MSR_KVM_PV_EOI_EN: 2243 if (kvm_lapic_enable_pv_eoi(vcpu, data)) 2244 return 1; 2245 break; 2246 2247 case MSR_IA32_MCG_CTL: 2248 case MSR_IA32_MCG_STATUS: 2249 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1: 2250 return set_msr_mce(vcpu, msr, data); 2251 2252 /* Performance counters are not protected by a CPUID bit, 2253 * so we should check all of them in the generic path for the sake of 2254 * cross vendor migration. 2255 * Writing a zero into the event select MSRs disables them, 2256 * which we perfectly emulate ;-). Any other value should be at least 2257 * reported, some guests depend on them. 2258 */ 2259 case MSR_K7_EVNTSEL0: 2260 case MSR_K7_EVNTSEL1: 2261 case MSR_K7_EVNTSEL2: 2262 case MSR_K7_EVNTSEL3: 2263 if (data != 0) 2264 vcpu_unimpl(vcpu, "unimplemented perfctr wrmsr: " 2265 "0x%x data 0x%llx\n", msr, data); 2266 break; 2267 /* at least RHEL 4 unconditionally writes to the perfctr registers, 2268 * so we ignore writes to make it happy. 2269 */ 2270 case MSR_K7_PERFCTR0: 2271 case MSR_K7_PERFCTR1: 2272 case MSR_K7_PERFCTR2: 2273 case MSR_K7_PERFCTR3: 2274 vcpu_unimpl(vcpu, "unimplemented perfctr wrmsr: " 2275 "0x%x data 0x%llx\n", msr, data); 2276 break; 2277 case MSR_P6_PERFCTR0: 2278 case MSR_P6_PERFCTR1: 2279 pr = true; 2280 case MSR_P6_EVNTSEL0: 2281 case MSR_P6_EVNTSEL1: 2282 if (kvm_pmu_msr(vcpu, msr)) 2283 return kvm_pmu_set_msr(vcpu, msr_info); 2284 2285 if (pr || data != 0) 2286 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: " 2287 "0x%x data 0x%llx\n", msr, data); 2288 break; 2289 case MSR_K7_CLK_CTL: 2290 /* 2291 * Ignore all writes to this no longer documented MSR. 2292 * Writes are only relevant for old K7 processors, 2293 * all pre-dating SVM, but a recommended workaround from 2294 * AMD for these chips. It is possible to specify the 2295 * affected processor models on the command line, hence 2296 * the need to ignore the workaround. 2297 */ 2298 break; 2299 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15: 2300 if (kvm_hv_msr_partition_wide(msr)) { 2301 int r; 2302 mutex_lock(&vcpu->kvm->lock); 2303 r = set_msr_hyperv_pw(vcpu, msr, data); 2304 mutex_unlock(&vcpu->kvm->lock); 2305 return r; 2306 } else 2307 return set_msr_hyperv(vcpu, msr, data); 2308 break; 2309 case MSR_IA32_BBL_CR_CTL3: 2310 /* Drop writes to this legacy MSR -- see rdmsr 2311 * counterpart for further detail. 2312 */ 2313 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n", msr, data); 2314 break; 2315 case MSR_AMD64_OSVW_ID_LENGTH: 2316 if (!guest_cpuid_has_osvw(vcpu)) 2317 return 1; 2318 vcpu->arch.osvw.length = data; 2319 break; 2320 case MSR_AMD64_OSVW_STATUS: 2321 if (!guest_cpuid_has_osvw(vcpu)) 2322 return 1; 2323 vcpu->arch.osvw.status = data; 2324 break; 2325 default: 2326 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr)) 2327 return xen_hvm_config(vcpu, data); 2328 if (kvm_pmu_msr(vcpu, msr)) 2329 return kvm_pmu_set_msr(vcpu, msr_info); 2330 if (!ignore_msrs) { 2331 vcpu_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n", 2332 msr, data); 2333 return 1; 2334 } else { 2335 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n", 2336 msr, data); 2337 break; 2338 } 2339 } 2340 return 0; 2341 } 2342 EXPORT_SYMBOL_GPL(kvm_set_msr_common); 2343 2344 2345 /* 2346 * Reads an msr value (of 'msr_index') into 'pdata'. 2347 * Returns 0 on success, non-0 otherwise. 2348 * Assumes vcpu_load() was already called. 2349 */ 2350 int kvm_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata) 2351 { 2352 return kvm_x86_ops->get_msr(vcpu, msr_index, pdata); 2353 } 2354 EXPORT_SYMBOL_GPL(kvm_get_msr); 2355 2356 static int get_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata) 2357 { 2358 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges; 2359 2360 if (!msr_mtrr_valid(msr)) 2361 return 1; 2362 2363 if (msr == MSR_MTRRdefType) 2364 *pdata = vcpu->arch.mtrr_state.def_type + 2365 (vcpu->arch.mtrr_state.enabled << 10); 2366 else if (msr == MSR_MTRRfix64K_00000) 2367 *pdata = p[0]; 2368 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000) 2369 *pdata = p[1 + msr - MSR_MTRRfix16K_80000]; 2370 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000) 2371 *pdata = p[3 + msr - MSR_MTRRfix4K_C0000]; 2372 else if (msr == MSR_IA32_CR_PAT) 2373 *pdata = vcpu->arch.pat; 2374 else { /* Variable MTRRs */ 2375 int idx, is_mtrr_mask; 2376 u64 *pt; 2377 2378 idx = (msr - 0x200) / 2; 2379 is_mtrr_mask = msr - 0x200 - 2 * idx; 2380 if (!is_mtrr_mask) 2381 pt = 2382 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo; 2383 else 2384 pt = 2385 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo; 2386 *pdata = *pt; 2387 } 2388 2389 return 0; 2390 } 2391 2392 static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata) 2393 { 2394 u64 data; 2395 u64 mcg_cap = vcpu->arch.mcg_cap; 2396 unsigned bank_num = mcg_cap & 0xff; 2397 2398 switch (msr) { 2399 case MSR_IA32_P5_MC_ADDR: 2400 case MSR_IA32_P5_MC_TYPE: 2401 data = 0; 2402 break; 2403 case MSR_IA32_MCG_CAP: 2404 data = vcpu->arch.mcg_cap; 2405 break; 2406 case MSR_IA32_MCG_CTL: 2407 if (!(mcg_cap & MCG_CTL_P)) 2408 return 1; 2409 data = vcpu->arch.mcg_ctl; 2410 break; 2411 case MSR_IA32_MCG_STATUS: 2412 data = vcpu->arch.mcg_status; 2413 break; 2414 default: 2415 if (msr >= MSR_IA32_MC0_CTL && 2416 msr < MSR_IA32_MCx_CTL(bank_num)) { 2417 u32 offset = msr - MSR_IA32_MC0_CTL; 2418 data = vcpu->arch.mce_banks[offset]; 2419 break; 2420 } 2421 return 1; 2422 } 2423 *pdata = data; 2424 return 0; 2425 } 2426 2427 static int get_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata) 2428 { 2429 u64 data = 0; 2430 struct kvm *kvm = vcpu->kvm; 2431 2432 switch (msr) { 2433 case HV_X64_MSR_GUEST_OS_ID: 2434 data = kvm->arch.hv_guest_os_id; 2435 break; 2436 case HV_X64_MSR_HYPERCALL: 2437 data = kvm->arch.hv_hypercall; 2438 break; 2439 case HV_X64_MSR_TIME_REF_COUNT: { 2440 data = 2441 div_u64(get_kernel_ns() + kvm->arch.kvmclock_offset, 100); 2442 break; 2443 } 2444 case HV_X64_MSR_REFERENCE_TSC: 2445 data = kvm->arch.hv_tsc_page; 2446 break; 2447 default: 2448 vcpu_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr); 2449 return 1; 2450 } 2451 2452 *pdata = data; 2453 return 0; 2454 } 2455 2456 static int get_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata) 2457 { 2458 u64 data = 0; 2459 2460 switch (msr) { 2461 case HV_X64_MSR_VP_INDEX: { 2462 int r; 2463 struct kvm_vcpu *v; 2464 kvm_for_each_vcpu(r, v, vcpu->kvm) { 2465 if (v == vcpu) { 2466 data = r; 2467 break; 2468 } 2469 } 2470 break; 2471 } 2472 case HV_X64_MSR_EOI: 2473 return kvm_hv_vapic_msr_read(vcpu, APIC_EOI, pdata); 2474 case HV_X64_MSR_ICR: 2475 return kvm_hv_vapic_msr_read(vcpu, APIC_ICR, pdata); 2476 case HV_X64_MSR_TPR: 2477 return kvm_hv_vapic_msr_read(vcpu, APIC_TASKPRI, pdata); 2478 case HV_X64_MSR_APIC_ASSIST_PAGE: 2479 data = vcpu->arch.hv_vapic; 2480 break; 2481 default: 2482 vcpu_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr); 2483 return 1; 2484 } 2485 *pdata = data; 2486 return 0; 2487 } 2488 2489 int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata) 2490 { 2491 u64 data; 2492 2493 switch (msr) { 2494 case MSR_IA32_PLATFORM_ID: 2495 case MSR_IA32_EBL_CR_POWERON: 2496 case MSR_IA32_DEBUGCTLMSR: 2497 case MSR_IA32_LASTBRANCHFROMIP: 2498 case MSR_IA32_LASTBRANCHTOIP: 2499 case MSR_IA32_LASTINTFROMIP: 2500 case MSR_IA32_LASTINTTOIP: 2501 case MSR_K8_SYSCFG: 2502 case MSR_K7_HWCR: 2503 case MSR_VM_HSAVE_PA: 2504 case MSR_K7_EVNTSEL0: 2505 case MSR_K7_EVNTSEL1: 2506 case MSR_K7_EVNTSEL2: 2507 case MSR_K7_EVNTSEL3: 2508 case MSR_K7_PERFCTR0: 2509 case MSR_K7_PERFCTR1: 2510 case MSR_K7_PERFCTR2: 2511 case MSR_K7_PERFCTR3: 2512 case MSR_K8_INT_PENDING_MSG: 2513 case MSR_AMD64_NB_CFG: 2514 case MSR_FAM10H_MMIO_CONF_BASE: 2515 case MSR_AMD64_BU_CFG2: 2516 data = 0; 2517 break; 2518 case MSR_P6_PERFCTR0: 2519 case MSR_P6_PERFCTR1: 2520 case MSR_P6_EVNTSEL0: 2521 case MSR_P6_EVNTSEL1: 2522 if (kvm_pmu_msr(vcpu, msr)) 2523 return kvm_pmu_get_msr(vcpu, msr, pdata); 2524 data = 0; 2525 break; 2526 case MSR_IA32_UCODE_REV: 2527 data = 0x100000000ULL; 2528 break; 2529 case MSR_MTRRcap: 2530 data = 0x500 | KVM_NR_VAR_MTRR; 2531 break; 2532 case 0x200 ... 0x2ff: 2533 return get_msr_mtrr(vcpu, msr, pdata); 2534 case 0xcd: /* fsb frequency */ 2535 data = 3; 2536 break; 2537 /* 2538 * MSR_EBC_FREQUENCY_ID 2539 * Conservative value valid for even the basic CPU models. 2540 * Models 0,1: 000 in bits 23:21 indicating a bus speed of 2541 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz, 2542 * and 266MHz for model 3, or 4. Set Core Clock 2543 * Frequency to System Bus Frequency Ratio to 1 (bits 2544 * 31:24) even though these are only valid for CPU 2545 * models > 2, however guests may end up dividing or 2546 * multiplying by zero otherwise. 2547 */ 2548 case MSR_EBC_FREQUENCY_ID: 2549 data = 1 << 24; 2550 break; 2551 case MSR_IA32_APICBASE: 2552 data = kvm_get_apic_base(vcpu); 2553 break; 2554 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff: 2555 return kvm_x2apic_msr_read(vcpu, msr, pdata); 2556 break; 2557 case MSR_IA32_TSCDEADLINE: 2558 data = kvm_get_lapic_tscdeadline_msr(vcpu); 2559 break; 2560 case MSR_IA32_TSC_ADJUST: 2561 data = (u64)vcpu->arch.ia32_tsc_adjust_msr; 2562 break; 2563 case MSR_IA32_MISC_ENABLE: 2564 data = vcpu->arch.ia32_misc_enable_msr; 2565 break; 2566 case MSR_IA32_PERF_STATUS: 2567 /* TSC increment by tick */ 2568 data = 1000ULL; 2569 /* CPU multiplier */ 2570 data |= (((uint64_t)4ULL) << 40); 2571 break; 2572 case MSR_EFER: 2573 data = vcpu->arch.efer; 2574 break; 2575 case MSR_KVM_WALL_CLOCK: 2576 case MSR_KVM_WALL_CLOCK_NEW: 2577 data = vcpu->kvm->arch.wall_clock; 2578 break; 2579 case MSR_KVM_SYSTEM_TIME: 2580 case MSR_KVM_SYSTEM_TIME_NEW: 2581 data = vcpu->arch.time; 2582 break; 2583 case MSR_KVM_ASYNC_PF_EN: 2584 data = vcpu->arch.apf.msr_val; 2585 break; 2586 case MSR_KVM_STEAL_TIME: 2587 data = vcpu->arch.st.msr_val; 2588 break; 2589 case MSR_KVM_PV_EOI_EN: 2590 data = vcpu->arch.pv_eoi.msr_val; 2591 break; 2592 case MSR_IA32_P5_MC_ADDR: 2593 case MSR_IA32_P5_MC_TYPE: 2594 case MSR_IA32_MCG_CAP: 2595 case MSR_IA32_MCG_CTL: 2596 case MSR_IA32_MCG_STATUS: 2597 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1: 2598 return get_msr_mce(vcpu, msr, pdata); 2599 case MSR_K7_CLK_CTL: 2600 /* 2601 * Provide expected ramp-up count for K7. All other 2602 * are set to zero, indicating minimum divisors for 2603 * every field. 2604 * 2605 * This prevents guest kernels on AMD host with CPU 2606 * type 6, model 8 and higher from exploding due to 2607 * the rdmsr failing. 2608 */ 2609 data = 0x20000000; 2610 break; 2611 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15: 2612 if (kvm_hv_msr_partition_wide(msr)) { 2613 int r; 2614 mutex_lock(&vcpu->kvm->lock); 2615 r = get_msr_hyperv_pw(vcpu, msr, pdata); 2616 mutex_unlock(&vcpu->kvm->lock); 2617 return r; 2618 } else 2619 return get_msr_hyperv(vcpu, msr, pdata); 2620 break; 2621 case MSR_IA32_BBL_CR_CTL3: 2622 /* This legacy MSR exists but isn't fully documented in current 2623 * silicon. It is however accessed by winxp in very narrow 2624 * scenarios where it sets bit #19, itself documented as 2625 * a "reserved" bit. Best effort attempt to source coherent 2626 * read data here should the balance of the register be 2627 * interpreted by the guest: 2628 * 2629 * L2 cache control register 3: 64GB range, 256KB size, 2630 * enabled, latency 0x1, configured 2631 */ 2632 data = 0xbe702111; 2633 break; 2634 case MSR_AMD64_OSVW_ID_LENGTH: 2635 if (!guest_cpuid_has_osvw(vcpu)) 2636 return 1; 2637 data = vcpu->arch.osvw.length; 2638 break; 2639 case MSR_AMD64_OSVW_STATUS: 2640 if (!guest_cpuid_has_osvw(vcpu)) 2641 return 1; 2642 data = vcpu->arch.osvw.status; 2643 break; 2644 default: 2645 if (kvm_pmu_msr(vcpu, msr)) 2646 return kvm_pmu_get_msr(vcpu, msr, pdata); 2647 if (!ignore_msrs) { 2648 vcpu_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr); 2649 return 1; 2650 } else { 2651 vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr); 2652 data = 0; 2653 } 2654 break; 2655 } 2656 *pdata = data; 2657 return 0; 2658 } 2659 EXPORT_SYMBOL_GPL(kvm_get_msr_common); 2660 2661 /* 2662 * Read or write a bunch of msrs. All parameters are kernel addresses. 2663 * 2664 * @return number of msrs set successfully. 2665 */ 2666 static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs, 2667 struct kvm_msr_entry *entries, 2668 int (*do_msr)(struct kvm_vcpu *vcpu, 2669 unsigned index, u64 *data)) 2670 { 2671 int i, idx; 2672 2673 idx = srcu_read_lock(&vcpu->kvm->srcu); 2674 for (i = 0; i < msrs->nmsrs; ++i) 2675 if (do_msr(vcpu, entries[i].index, &entries[i].data)) 2676 break; 2677 srcu_read_unlock(&vcpu->kvm->srcu, idx); 2678 2679 return i; 2680 } 2681 2682 /* 2683 * Read or write a bunch of msrs. Parameters are user addresses. 2684 * 2685 * @return number of msrs set successfully. 2686 */ 2687 static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs, 2688 int (*do_msr)(struct kvm_vcpu *vcpu, 2689 unsigned index, u64 *data), 2690 int writeback) 2691 { 2692 struct kvm_msrs msrs; 2693 struct kvm_msr_entry *entries; 2694 int r, n; 2695 unsigned size; 2696 2697 r = -EFAULT; 2698 if (copy_from_user(&msrs, user_msrs, sizeof msrs)) 2699 goto out; 2700 2701 r = -E2BIG; 2702 if (msrs.nmsrs >= MAX_IO_MSRS) 2703 goto out; 2704 2705 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs; 2706 entries = memdup_user(user_msrs->entries, size); 2707 if (IS_ERR(entries)) { 2708 r = PTR_ERR(entries); 2709 goto out; 2710 } 2711 2712 r = n = __msr_io(vcpu, &msrs, entries, do_msr); 2713 if (r < 0) 2714 goto out_free; 2715 2716 r = -EFAULT; 2717 if (writeback && copy_to_user(user_msrs->entries, entries, size)) 2718 goto out_free; 2719 2720 r = n; 2721 2722 out_free: 2723 kfree(entries); 2724 out: 2725 return r; 2726 } 2727 2728 int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext) 2729 { 2730 int r; 2731 2732 switch (ext) { 2733 case KVM_CAP_IRQCHIP: 2734 case KVM_CAP_HLT: 2735 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL: 2736 case KVM_CAP_SET_TSS_ADDR: 2737 case KVM_CAP_EXT_CPUID: 2738 case KVM_CAP_EXT_EMUL_CPUID: 2739 case KVM_CAP_CLOCKSOURCE: 2740 case KVM_CAP_PIT: 2741 case KVM_CAP_NOP_IO_DELAY: 2742 case KVM_CAP_MP_STATE: 2743 case KVM_CAP_SYNC_MMU: 2744 case KVM_CAP_USER_NMI: 2745 case KVM_CAP_REINJECT_CONTROL: 2746 case KVM_CAP_IRQ_INJECT_STATUS: 2747 case KVM_CAP_IOEVENTFD: 2748 case KVM_CAP_IOEVENTFD_NO_LENGTH: 2749 case KVM_CAP_PIT2: 2750 case KVM_CAP_PIT_STATE2: 2751 case KVM_CAP_SET_IDENTITY_MAP_ADDR: 2752 case KVM_CAP_XEN_HVM: 2753 case KVM_CAP_ADJUST_CLOCK: 2754 case KVM_CAP_VCPU_EVENTS: 2755 case KVM_CAP_HYPERV: 2756 case KVM_CAP_HYPERV_VAPIC: 2757 case KVM_CAP_HYPERV_SPIN: 2758 case KVM_CAP_PCI_SEGMENT: 2759 case KVM_CAP_DEBUGREGS: 2760 case KVM_CAP_X86_ROBUST_SINGLESTEP: 2761 case KVM_CAP_XSAVE: 2762 case KVM_CAP_ASYNC_PF: 2763 case KVM_CAP_GET_TSC_KHZ: 2764 case KVM_CAP_KVMCLOCK_CTRL: 2765 case KVM_CAP_READONLY_MEM: 2766 case KVM_CAP_HYPERV_TIME: 2767 case KVM_CAP_IOAPIC_POLARITY_IGNORED: 2768 case KVM_CAP_TSC_DEADLINE_TIMER: 2769 #ifdef CONFIG_KVM_DEVICE_ASSIGNMENT 2770 case KVM_CAP_ASSIGN_DEV_IRQ: 2771 case KVM_CAP_PCI_2_3: 2772 #endif 2773 r = 1; 2774 break; 2775 case KVM_CAP_COALESCED_MMIO: 2776 r = KVM_COALESCED_MMIO_PAGE_OFFSET; 2777 break; 2778 case KVM_CAP_VAPIC: 2779 r = !kvm_x86_ops->cpu_has_accelerated_tpr(); 2780 break; 2781 case KVM_CAP_NR_VCPUS: 2782 r = KVM_SOFT_MAX_VCPUS; 2783 break; 2784 case KVM_CAP_MAX_VCPUS: 2785 r = KVM_MAX_VCPUS; 2786 break; 2787 case KVM_CAP_NR_MEMSLOTS: 2788 r = KVM_USER_MEM_SLOTS; 2789 break; 2790 case KVM_CAP_PV_MMU: /* obsolete */ 2791 r = 0; 2792 break; 2793 #ifdef CONFIG_KVM_DEVICE_ASSIGNMENT 2794 case KVM_CAP_IOMMU: 2795 r = iommu_present(&pci_bus_type); 2796 break; 2797 #endif 2798 case KVM_CAP_MCE: 2799 r = KVM_MAX_MCE_BANKS; 2800 break; 2801 case KVM_CAP_XCRS: 2802 r = cpu_has_xsave; 2803 break; 2804 case KVM_CAP_TSC_CONTROL: 2805 r = kvm_has_tsc_control; 2806 break; 2807 default: 2808 r = 0; 2809 break; 2810 } 2811 return r; 2812 2813 } 2814 2815 long kvm_arch_dev_ioctl(struct file *filp, 2816 unsigned int ioctl, unsigned long arg) 2817 { 2818 void __user *argp = (void __user *)arg; 2819 long r; 2820 2821 switch (ioctl) { 2822 case KVM_GET_MSR_INDEX_LIST: { 2823 struct kvm_msr_list __user *user_msr_list = argp; 2824 struct kvm_msr_list msr_list; 2825 unsigned n; 2826 2827 r = -EFAULT; 2828 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list)) 2829 goto out; 2830 n = msr_list.nmsrs; 2831 msr_list.nmsrs = num_msrs_to_save + ARRAY_SIZE(emulated_msrs); 2832 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list)) 2833 goto out; 2834 r = -E2BIG; 2835 if (n < msr_list.nmsrs) 2836 goto out; 2837 r = -EFAULT; 2838 if (copy_to_user(user_msr_list->indices, &msrs_to_save, 2839 num_msrs_to_save * sizeof(u32))) 2840 goto out; 2841 if (copy_to_user(user_msr_list->indices + num_msrs_to_save, 2842 &emulated_msrs, 2843 ARRAY_SIZE(emulated_msrs) * sizeof(u32))) 2844 goto out; 2845 r = 0; 2846 break; 2847 } 2848 case KVM_GET_SUPPORTED_CPUID: 2849 case KVM_GET_EMULATED_CPUID: { 2850 struct kvm_cpuid2 __user *cpuid_arg = argp; 2851 struct kvm_cpuid2 cpuid; 2852 2853 r = -EFAULT; 2854 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid)) 2855 goto out; 2856 2857 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries, 2858 ioctl); 2859 if (r) 2860 goto out; 2861 2862 r = -EFAULT; 2863 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid)) 2864 goto out; 2865 r = 0; 2866 break; 2867 } 2868 case KVM_X86_GET_MCE_CAP_SUPPORTED: { 2869 u64 mce_cap; 2870 2871 mce_cap = KVM_MCE_CAP_SUPPORTED; 2872 r = -EFAULT; 2873 if (copy_to_user(argp, &mce_cap, sizeof mce_cap)) 2874 goto out; 2875 r = 0; 2876 break; 2877 } 2878 default: 2879 r = -EINVAL; 2880 } 2881 out: 2882 return r; 2883 } 2884 2885 static void wbinvd_ipi(void *garbage) 2886 { 2887 wbinvd(); 2888 } 2889 2890 static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu) 2891 { 2892 return kvm_arch_has_noncoherent_dma(vcpu->kvm); 2893 } 2894 2895 void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu) 2896 { 2897 /* Address WBINVD may be executed by guest */ 2898 if (need_emulate_wbinvd(vcpu)) { 2899 if (kvm_x86_ops->has_wbinvd_exit()) 2900 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask); 2901 else if (vcpu->cpu != -1 && vcpu->cpu != cpu) 2902 smp_call_function_single(vcpu->cpu, 2903 wbinvd_ipi, NULL, 1); 2904 } 2905 2906 kvm_x86_ops->vcpu_load(vcpu, cpu); 2907 2908 /* Apply any externally detected TSC adjustments (due to suspend) */ 2909 if (unlikely(vcpu->arch.tsc_offset_adjustment)) { 2910 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment); 2911 vcpu->arch.tsc_offset_adjustment = 0; 2912 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 2913 } 2914 2915 if (unlikely(vcpu->cpu != cpu) || check_tsc_unstable()) { 2916 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 : 2917 native_read_tsc() - vcpu->arch.last_host_tsc; 2918 if (tsc_delta < 0) 2919 mark_tsc_unstable("KVM discovered backwards TSC"); 2920 if (check_tsc_unstable()) { 2921 u64 offset = kvm_x86_ops->compute_tsc_offset(vcpu, 2922 vcpu->arch.last_guest_tsc); 2923 kvm_x86_ops->write_tsc_offset(vcpu, offset); 2924 vcpu->arch.tsc_catchup = 1; 2925 } 2926 /* 2927 * On a host with synchronized TSC, there is no need to update 2928 * kvmclock on vcpu->cpu migration 2929 */ 2930 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1) 2931 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu); 2932 if (vcpu->cpu != cpu) 2933 kvm_migrate_timers(vcpu); 2934 vcpu->cpu = cpu; 2935 } 2936 2937 accumulate_steal_time(vcpu); 2938 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu); 2939 } 2940 2941 void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu) 2942 { 2943 kvm_x86_ops->vcpu_put(vcpu); 2944 kvm_put_guest_fpu(vcpu); 2945 vcpu->arch.last_host_tsc = native_read_tsc(); 2946 } 2947 2948 static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu, 2949 struct kvm_lapic_state *s) 2950 { 2951 kvm_x86_ops->sync_pir_to_irr(vcpu); 2952 memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s); 2953 2954 return 0; 2955 } 2956 2957 static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu, 2958 struct kvm_lapic_state *s) 2959 { 2960 kvm_apic_post_state_restore(vcpu, s); 2961 update_cr8_intercept(vcpu); 2962 2963 return 0; 2964 } 2965 2966 static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu, 2967 struct kvm_interrupt *irq) 2968 { 2969 if (irq->irq >= KVM_NR_INTERRUPTS) 2970 return -EINVAL; 2971 if (irqchip_in_kernel(vcpu->kvm)) 2972 return -ENXIO; 2973 2974 kvm_queue_interrupt(vcpu, irq->irq, false); 2975 kvm_make_request(KVM_REQ_EVENT, vcpu); 2976 2977 return 0; 2978 } 2979 2980 static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu) 2981 { 2982 kvm_inject_nmi(vcpu); 2983 2984 return 0; 2985 } 2986 2987 static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu, 2988 struct kvm_tpr_access_ctl *tac) 2989 { 2990 if (tac->flags) 2991 return -EINVAL; 2992 vcpu->arch.tpr_access_reporting = !!tac->enabled; 2993 return 0; 2994 } 2995 2996 static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu, 2997 u64 mcg_cap) 2998 { 2999 int r; 3000 unsigned bank_num = mcg_cap & 0xff, bank; 3001 3002 r = -EINVAL; 3003 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS) 3004 goto out; 3005 if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000)) 3006 goto out; 3007 r = 0; 3008 vcpu->arch.mcg_cap = mcg_cap; 3009 /* Init IA32_MCG_CTL to all 1s */ 3010 if (mcg_cap & MCG_CTL_P) 3011 vcpu->arch.mcg_ctl = ~(u64)0; 3012 /* Init IA32_MCi_CTL to all 1s */ 3013 for (bank = 0; bank < bank_num; bank++) 3014 vcpu->arch.mce_banks[bank*4] = ~(u64)0; 3015 out: 3016 return r; 3017 } 3018 3019 static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu, 3020 struct kvm_x86_mce *mce) 3021 { 3022 u64 mcg_cap = vcpu->arch.mcg_cap; 3023 unsigned bank_num = mcg_cap & 0xff; 3024 u64 *banks = vcpu->arch.mce_banks; 3025 3026 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL)) 3027 return -EINVAL; 3028 /* 3029 * if IA32_MCG_CTL is not all 1s, the uncorrected error 3030 * reporting is disabled 3031 */ 3032 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) && 3033 vcpu->arch.mcg_ctl != ~(u64)0) 3034 return 0; 3035 banks += 4 * mce->bank; 3036 /* 3037 * if IA32_MCi_CTL is not all 1s, the uncorrected error 3038 * reporting is disabled for the bank 3039 */ 3040 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0) 3041 return 0; 3042 if (mce->status & MCI_STATUS_UC) { 3043 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) || 3044 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) { 3045 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); 3046 return 0; 3047 } 3048 if (banks[1] & MCI_STATUS_VAL) 3049 mce->status |= MCI_STATUS_OVER; 3050 banks[2] = mce->addr; 3051 banks[3] = mce->misc; 3052 vcpu->arch.mcg_status = mce->mcg_status; 3053 banks[1] = mce->status; 3054 kvm_queue_exception(vcpu, MC_VECTOR); 3055 } else if (!(banks[1] & MCI_STATUS_VAL) 3056 || !(banks[1] & MCI_STATUS_UC)) { 3057 if (banks[1] & MCI_STATUS_VAL) 3058 mce->status |= MCI_STATUS_OVER; 3059 banks[2] = mce->addr; 3060 banks[3] = mce->misc; 3061 banks[1] = mce->status; 3062 } else 3063 banks[1] |= MCI_STATUS_OVER; 3064 return 0; 3065 } 3066 3067 static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu, 3068 struct kvm_vcpu_events *events) 3069 { 3070 process_nmi(vcpu); 3071 events->exception.injected = 3072 vcpu->arch.exception.pending && 3073 !kvm_exception_is_soft(vcpu->arch.exception.nr); 3074 events->exception.nr = vcpu->arch.exception.nr; 3075 events->exception.has_error_code = vcpu->arch.exception.has_error_code; 3076 events->exception.pad = 0; 3077 events->exception.error_code = vcpu->arch.exception.error_code; 3078 3079 events->interrupt.injected = 3080 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft; 3081 events->interrupt.nr = vcpu->arch.interrupt.nr; 3082 events->interrupt.soft = 0; 3083 events->interrupt.shadow = kvm_x86_ops->get_interrupt_shadow(vcpu); 3084 3085 events->nmi.injected = vcpu->arch.nmi_injected; 3086 events->nmi.pending = vcpu->arch.nmi_pending != 0; 3087 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu); 3088 events->nmi.pad = 0; 3089 3090 events->sipi_vector = 0; /* never valid when reporting to user space */ 3091 3092 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING 3093 | KVM_VCPUEVENT_VALID_SHADOW); 3094 memset(&events->reserved, 0, sizeof(events->reserved)); 3095 } 3096 3097 static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu, 3098 struct kvm_vcpu_events *events) 3099 { 3100 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING 3101 | KVM_VCPUEVENT_VALID_SIPI_VECTOR 3102 | KVM_VCPUEVENT_VALID_SHADOW)) 3103 return -EINVAL; 3104 3105 process_nmi(vcpu); 3106 vcpu->arch.exception.pending = events->exception.injected; 3107 vcpu->arch.exception.nr = events->exception.nr; 3108 vcpu->arch.exception.has_error_code = events->exception.has_error_code; 3109 vcpu->arch.exception.error_code = events->exception.error_code; 3110 3111 vcpu->arch.interrupt.pending = events->interrupt.injected; 3112 vcpu->arch.interrupt.nr = events->interrupt.nr; 3113 vcpu->arch.interrupt.soft = events->interrupt.soft; 3114 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW) 3115 kvm_x86_ops->set_interrupt_shadow(vcpu, 3116 events->interrupt.shadow); 3117 3118 vcpu->arch.nmi_injected = events->nmi.injected; 3119 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING) 3120 vcpu->arch.nmi_pending = events->nmi.pending; 3121 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked); 3122 3123 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR && 3124 kvm_vcpu_has_lapic(vcpu)) 3125 vcpu->arch.apic->sipi_vector = events->sipi_vector; 3126 3127 kvm_make_request(KVM_REQ_EVENT, vcpu); 3128 3129 return 0; 3130 } 3131 3132 static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu, 3133 struct kvm_debugregs *dbgregs) 3134 { 3135 unsigned long val; 3136 3137 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db)); 3138 kvm_get_dr(vcpu, 6, &val); 3139 dbgregs->dr6 = val; 3140 dbgregs->dr7 = vcpu->arch.dr7; 3141 dbgregs->flags = 0; 3142 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved)); 3143 } 3144 3145 static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu, 3146 struct kvm_debugregs *dbgregs) 3147 { 3148 if (dbgregs->flags) 3149 return -EINVAL; 3150 3151 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db)); 3152 vcpu->arch.dr6 = dbgregs->dr6; 3153 kvm_update_dr6(vcpu); 3154 vcpu->arch.dr7 = dbgregs->dr7; 3155 kvm_update_dr7(vcpu); 3156 3157 return 0; 3158 } 3159 3160 #define XSTATE_COMPACTION_ENABLED (1ULL << 63) 3161 3162 static void fill_xsave(u8 *dest, struct kvm_vcpu *vcpu) 3163 { 3164 struct xsave_struct *xsave = &vcpu->arch.guest_fpu.state->xsave; 3165 u64 xstate_bv = xsave->xsave_hdr.xstate_bv; 3166 u64 valid; 3167 3168 /* 3169 * Copy legacy XSAVE area, to avoid complications with CPUID 3170 * leaves 0 and 1 in the loop below. 3171 */ 3172 memcpy(dest, xsave, XSAVE_HDR_OFFSET); 3173 3174 /* Set XSTATE_BV */ 3175 *(u64 *)(dest + XSAVE_HDR_OFFSET) = xstate_bv; 3176 3177 /* 3178 * Copy each region from the possibly compacted offset to the 3179 * non-compacted offset. 3180 */ 3181 valid = xstate_bv & ~XSTATE_FPSSE; 3182 while (valid) { 3183 u64 feature = valid & -valid; 3184 int index = fls64(feature) - 1; 3185 void *src = get_xsave_addr(xsave, feature); 3186 3187 if (src) { 3188 u32 size, offset, ecx, edx; 3189 cpuid_count(XSTATE_CPUID, index, 3190 &size, &offset, &ecx, &edx); 3191 memcpy(dest + offset, src, size); 3192 } 3193 3194 valid -= feature; 3195 } 3196 } 3197 3198 static void load_xsave(struct kvm_vcpu *vcpu, u8 *src) 3199 { 3200 struct xsave_struct *xsave = &vcpu->arch.guest_fpu.state->xsave; 3201 u64 xstate_bv = *(u64 *)(src + XSAVE_HDR_OFFSET); 3202 u64 valid; 3203 3204 /* 3205 * Copy legacy XSAVE area, to avoid complications with CPUID 3206 * leaves 0 and 1 in the loop below. 3207 */ 3208 memcpy(xsave, src, XSAVE_HDR_OFFSET); 3209 3210 /* Set XSTATE_BV and possibly XCOMP_BV. */ 3211 xsave->xsave_hdr.xstate_bv = xstate_bv; 3212 if (cpu_has_xsaves) 3213 xsave->xsave_hdr.xcomp_bv = host_xcr0 | XSTATE_COMPACTION_ENABLED; 3214 3215 /* 3216 * Copy each region from the non-compacted offset to the 3217 * possibly compacted offset. 3218 */ 3219 valid = xstate_bv & ~XSTATE_FPSSE; 3220 while (valid) { 3221 u64 feature = valid & -valid; 3222 int index = fls64(feature) - 1; 3223 void *dest = get_xsave_addr(xsave, feature); 3224 3225 if (dest) { 3226 u32 size, offset, ecx, edx; 3227 cpuid_count(XSTATE_CPUID, index, 3228 &size, &offset, &ecx, &edx); 3229 memcpy(dest, src + offset, size); 3230 } else 3231 WARN_ON_ONCE(1); 3232 3233 valid -= feature; 3234 } 3235 } 3236 3237 static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu, 3238 struct kvm_xsave *guest_xsave) 3239 { 3240 if (cpu_has_xsave) { 3241 memset(guest_xsave, 0, sizeof(struct kvm_xsave)); 3242 fill_xsave((u8 *) guest_xsave->region, vcpu); 3243 } else { 3244 memcpy(guest_xsave->region, 3245 &vcpu->arch.guest_fpu.state->fxsave, 3246 sizeof(struct i387_fxsave_struct)); 3247 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] = 3248 XSTATE_FPSSE; 3249 } 3250 } 3251 3252 static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu, 3253 struct kvm_xsave *guest_xsave) 3254 { 3255 u64 xstate_bv = 3256 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)]; 3257 3258 if (cpu_has_xsave) { 3259 /* 3260 * Here we allow setting states that are not present in 3261 * CPUID leaf 0xD, index 0, EDX:EAX. This is for compatibility 3262 * with old userspace. 3263 */ 3264 if (xstate_bv & ~kvm_supported_xcr0()) 3265 return -EINVAL; 3266 load_xsave(vcpu, (u8 *)guest_xsave->region); 3267 } else { 3268 if (xstate_bv & ~XSTATE_FPSSE) 3269 return -EINVAL; 3270 memcpy(&vcpu->arch.guest_fpu.state->fxsave, 3271 guest_xsave->region, sizeof(struct i387_fxsave_struct)); 3272 } 3273 return 0; 3274 } 3275 3276 static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu, 3277 struct kvm_xcrs *guest_xcrs) 3278 { 3279 if (!cpu_has_xsave) { 3280 guest_xcrs->nr_xcrs = 0; 3281 return; 3282 } 3283 3284 guest_xcrs->nr_xcrs = 1; 3285 guest_xcrs->flags = 0; 3286 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK; 3287 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0; 3288 } 3289 3290 static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu, 3291 struct kvm_xcrs *guest_xcrs) 3292 { 3293 int i, r = 0; 3294 3295 if (!cpu_has_xsave) 3296 return -EINVAL; 3297 3298 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags) 3299 return -EINVAL; 3300 3301 for (i = 0; i < guest_xcrs->nr_xcrs; i++) 3302 /* Only support XCR0 currently */ 3303 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) { 3304 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK, 3305 guest_xcrs->xcrs[i].value); 3306 break; 3307 } 3308 if (r) 3309 r = -EINVAL; 3310 return r; 3311 } 3312 3313 /* 3314 * kvm_set_guest_paused() indicates to the guest kernel that it has been 3315 * stopped by the hypervisor. This function will be called from the host only. 3316 * EINVAL is returned when the host attempts to set the flag for a guest that 3317 * does not support pv clocks. 3318 */ 3319 static int kvm_set_guest_paused(struct kvm_vcpu *vcpu) 3320 { 3321 if (!vcpu->arch.pv_time_enabled) 3322 return -EINVAL; 3323 vcpu->arch.pvclock_set_guest_stopped_request = true; 3324 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 3325 return 0; 3326 } 3327 3328 long kvm_arch_vcpu_ioctl(struct file *filp, 3329 unsigned int ioctl, unsigned long arg) 3330 { 3331 struct kvm_vcpu *vcpu = filp->private_data; 3332 void __user *argp = (void __user *)arg; 3333 int r; 3334 union { 3335 struct kvm_lapic_state *lapic; 3336 struct kvm_xsave *xsave; 3337 struct kvm_xcrs *xcrs; 3338 void *buffer; 3339 } u; 3340 3341 u.buffer = NULL; 3342 switch (ioctl) { 3343 case KVM_GET_LAPIC: { 3344 r = -EINVAL; 3345 if (!vcpu->arch.apic) 3346 goto out; 3347 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL); 3348 3349 r = -ENOMEM; 3350 if (!u.lapic) 3351 goto out; 3352 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic); 3353 if (r) 3354 goto out; 3355 r = -EFAULT; 3356 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state))) 3357 goto out; 3358 r = 0; 3359 break; 3360 } 3361 case KVM_SET_LAPIC: { 3362 r = -EINVAL; 3363 if (!vcpu->arch.apic) 3364 goto out; 3365 u.lapic = memdup_user(argp, sizeof(*u.lapic)); 3366 if (IS_ERR(u.lapic)) 3367 return PTR_ERR(u.lapic); 3368 3369 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic); 3370 break; 3371 } 3372 case KVM_INTERRUPT: { 3373 struct kvm_interrupt irq; 3374 3375 r = -EFAULT; 3376 if (copy_from_user(&irq, argp, sizeof irq)) 3377 goto out; 3378 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq); 3379 break; 3380 } 3381 case KVM_NMI: { 3382 r = kvm_vcpu_ioctl_nmi(vcpu); 3383 break; 3384 } 3385 case KVM_SET_CPUID: { 3386 struct kvm_cpuid __user *cpuid_arg = argp; 3387 struct kvm_cpuid cpuid; 3388 3389 r = -EFAULT; 3390 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid)) 3391 goto out; 3392 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries); 3393 break; 3394 } 3395 case KVM_SET_CPUID2: { 3396 struct kvm_cpuid2 __user *cpuid_arg = argp; 3397 struct kvm_cpuid2 cpuid; 3398 3399 r = -EFAULT; 3400 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid)) 3401 goto out; 3402 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid, 3403 cpuid_arg->entries); 3404 break; 3405 } 3406 case KVM_GET_CPUID2: { 3407 struct kvm_cpuid2 __user *cpuid_arg = argp; 3408 struct kvm_cpuid2 cpuid; 3409 3410 r = -EFAULT; 3411 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid)) 3412 goto out; 3413 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid, 3414 cpuid_arg->entries); 3415 if (r) 3416 goto out; 3417 r = -EFAULT; 3418 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid)) 3419 goto out; 3420 r = 0; 3421 break; 3422 } 3423 case KVM_GET_MSRS: 3424 r = msr_io(vcpu, argp, kvm_get_msr, 1); 3425 break; 3426 case KVM_SET_MSRS: 3427 r = msr_io(vcpu, argp, do_set_msr, 0); 3428 break; 3429 case KVM_TPR_ACCESS_REPORTING: { 3430 struct kvm_tpr_access_ctl tac; 3431 3432 r = -EFAULT; 3433 if (copy_from_user(&tac, argp, sizeof tac)) 3434 goto out; 3435 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac); 3436 if (r) 3437 goto out; 3438 r = -EFAULT; 3439 if (copy_to_user(argp, &tac, sizeof tac)) 3440 goto out; 3441 r = 0; 3442 break; 3443 }; 3444 case KVM_SET_VAPIC_ADDR: { 3445 struct kvm_vapic_addr va; 3446 3447 r = -EINVAL; 3448 if (!irqchip_in_kernel(vcpu->kvm)) 3449 goto out; 3450 r = -EFAULT; 3451 if (copy_from_user(&va, argp, sizeof va)) 3452 goto out; 3453 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr); 3454 break; 3455 } 3456 case KVM_X86_SETUP_MCE: { 3457 u64 mcg_cap; 3458 3459 r = -EFAULT; 3460 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap)) 3461 goto out; 3462 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap); 3463 break; 3464 } 3465 case KVM_X86_SET_MCE: { 3466 struct kvm_x86_mce mce; 3467 3468 r = -EFAULT; 3469 if (copy_from_user(&mce, argp, sizeof mce)) 3470 goto out; 3471 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce); 3472 break; 3473 } 3474 case KVM_GET_VCPU_EVENTS: { 3475 struct kvm_vcpu_events events; 3476 3477 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events); 3478 3479 r = -EFAULT; 3480 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events))) 3481 break; 3482 r = 0; 3483 break; 3484 } 3485 case KVM_SET_VCPU_EVENTS: { 3486 struct kvm_vcpu_events events; 3487 3488 r = -EFAULT; 3489 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events))) 3490 break; 3491 3492 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events); 3493 break; 3494 } 3495 case KVM_GET_DEBUGREGS: { 3496 struct kvm_debugregs dbgregs; 3497 3498 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs); 3499 3500 r = -EFAULT; 3501 if (copy_to_user(argp, &dbgregs, 3502 sizeof(struct kvm_debugregs))) 3503 break; 3504 r = 0; 3505 break; 3506 } 3507 case KVM_SET_DEBUGREGS: { 3508 struct kvm_debugregs dbgregs; 3509 3510 r = -EFAULT; 3511 if (copy_from_user(&dbgregs, argp, 3512 sizeof(struct kvm_debugregs))) 3513 break; 3514 3515 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs); 3516 break; 3517 } 3518 case KVM_GET_XSAVE: { 3519 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL); 3520 r = -ENOMEM; 3521 if (!u.xsave) 3522 break; 3523 3524 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave); 3525 3526 r = -EFAULT; 3527 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave))) 3528 break; 3529 r = 0; 3530 break; 3531 } 3532 case KVM_SET_XSAVE: { 3533 u.xsave = memdup_user(argp, sizeof(*u.xsave)); 3534 if (IS_ERR(u.xsave)) 3535 return PTR_ERR(u.xsave); 3536 3537 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave); 3538 break; 3539 } 3540 case KVM_GET_XCRS: { 3541 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL); 3542 r = -ENOMEM; 3543 if (!u.xcrs) 3544 break; 3545 3546 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs); 3547 3548 r = -EFAULT; 3549 if (copy_to_user(argp, u.xcrs, 3550 sizeof(struct kvm_xcrs))) 3551 break; 3552 r = 0; 3553 break; 3554 } 3555 case KVM_SET_XCRS: { 3556 u.xcrs = memdup_user(argp, sizeof(*u.xcrs)); 3557 if (IS_ERR(u.xcrs)) 3558 return PTR_ERR(u.xcrs); 3559 3560 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs); 3561 break; 3562 } 3563 case KVM_SET_TSC_KHZ: { 3564 u32 user_tsc_khz; 3565 3566 r = -EINVAL; 3567 user_tsc_khz = (u32)arg; 3568 3569 if (user_tsc_khz >= kvm_max_guest_tsc_khz) 3570 goto out; 3571 3572 if (user_tsc_khz == 0) 3573 user_tsc_khz = tsc_khz; 3574 3575 kvm_set_tsc_khz(vcpu, user_tsc_khz); 3576 3577 r = 0; 3578 goto out; 3579 } 3580 case KVM_GET_TSC_KHZ: { 3581 r = vcpu->arch.virtual_tsc_khz; 3582 goto out; 3583 } 3584 case KVM_KVMCLOCK_CTRL: { 3585 r = kvm_set_guest_paused(vcpu); 3586 goto out; 3587 } 3588 default: 3589 r = -EINVAL; 3590 } 3591 out: 3592 kfree(u.buffer); 3593 return r; 3594 } 3595 3596 int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf) 3597 { 3598 return VM_FAULT_SIGBUS; 3599 } 3600 3601 static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr) 3602 { 3603 int ret; 3604 3605 if (addr > (unsigned int)(-3 * PAGE_SIZE)) 3606 return -EINVAL; 3607 ret = kvm_x86_ops->set_tss_addr(kvm, addr); 3608 return ret; 3609 } 3610 3611 static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm, 3612 u64 ident_addr) 3613 { 3614 kvm->arch.ept_identity_map_addr = ident_addr; 3615 return 0; 3616 } 3617 3618 static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm, 3619 u32 kvm_nr_mmu_pages) 3620 { 3621 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES) 3622 return -EINVAL; 3623 3624 mutex_lock(&kvm->slots_lock); 3625 3626 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages); 3627 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages; 3628 3629 mutex_unlock(&kvm->slots_lock); 3630 return 0; 3631 } 3632 3633 static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm) 3634 { 3635 return kvm->arch.n_max_mmu_pages; 3636 } 3637 3638 static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip) 3639 { 3640 int r; 3641 3642 r = 0; 3643 switch (chip->chip_id) { 3644 case KVM_IRQCHIP_PIC_MASTER: 3645 memcpy(&chip->chip.pic, 3646 &pic_irqchip(kvm)->pics[0], 3647 sizeof(struct kvm_pic_state)); 3648 break; 3649 case KVM_IRQCHIP_PIC_SLAVE: 3650 memcpy(&chip->chip.pic, 3651 &pic_irqchip(kvm)->pics[1], 3652 sizeof(struct kvm_pic_state)); 3653 break; 3654 case KVM_IRQCHIP_IOAPIC: 3655 r = kvm_get_ioapic(kvm, &chip->chip.ioapic); 3656 break; 3657 default: 3658 r = -EINVAL; 3659 break; 3660 } 3661 return r; 3662 } 3663 3664 static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip) 3665 { 3666 int r; 3667 3668 r = 0; 3669 switch (chip->chip_id) { 3670 case KVM_IRQCHIP_PIC_MASTER: 3671 spin_lock(&pic_irqchip(kvm)->lock); 3672 memcpy(&pic_irqchip(kvm)->pics[0], 3673 &chip->chip.pic, 3674 sizeof(struct kvm_pic_state)); 3675 spin_unlock(&pic_irqchip(kvm)->lock); 3676 break; 3677 case KVM_IRQCHIP_PIC_SLAVE: 3678 spin_lock(&pic_irqchip(kvm)->lock); 3679 memcpy(&pic_irqchip(kvm)->pics[1], 3680 &chip->chip.pic, 3681 sizeof(struct kvm_pic_state)); 3682 spin_unlock(&pic_irqchip(kvm)->lock); 3683 break; 3684 case KVM_IRQCHIP_IOAPIC: 3685 r = kvm_set_ioapic(kvm, &chip->chip.ioapic); 3686 break; 3687 default: 3688 r = -EINVAL; 3689 break; 3690 } 3691 kvm_pic_update_irq(pic_irqchip(kvm)); 3692 return r; 3693 } 3694 3695 static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps) 3696 { 3697 int r = 0; 3698 3699 mutex_lock(&kvm->arch.vpit->pit_state.lock); 3700 memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state)); 3701 mutex_unlock(&kvm->arch.vpit->pit_state.lock); 3702 return r; 3703 } 3704 3705 static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps) 3706 { 3707 int r = 0; 3708 3709 mutex_lock(&kvm->arch.vpit->pit_state.lock); 3710 memcpy(&kvm->arch.vpit->pit_state, ps, sizeof(struct kvm_pit_state)); 3711 kvm_pit_load_count(kvm, 0, ps->channels[0].count, 0); 3712 mutex_unlock(&kvm->arch.vpit->pit_state.lock); 3713 return r; 3714 } 3715 3716 static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps) 3717 { 3718 int r = 0; 3719 3720 mutex_lock(&kvm->arch.vpit->pit_state.lock); 3721 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels, 3722 sizeof(ps->channels)); 3723 ps->flags = kvm->arch.vpit->pit_state.flags; 3724 mutex_unlock(&kvm->arch.vpit->pit_state.lock); 3725 memset(&ps->reserved, 0, sizeof(ps->reserved)); 3726 return r; 3727 } 3728 3729 static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps) 3730 { 3731 int r = 0, start = 0; 3732 u32 prev_legacy, cur_legacy; 3733 mutex_lock(&kvm->arch.vpit->pit_state.lock); 3734 prev_legacy = kvm->arch.vpit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY; 3735 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY; 3736 if (!prev_legacy && cur_legacy) 3737 start = 1; 3738 memcpy(&kvm->arch.vpit->pit_state.channels, &ps->channels, 3739 sizeof(kvm->arch.vpit->pit_state.channels)); 3740 kvm->arch.vpit->pit_state.flags = ps->flags; 3741 kvm_pit_load_count(kvm, 0, kvm->arch.vpit->pit_state.channels[0].count, start); 3742 mutex_unlock(&kvm->arch.vpit->pit_state.lock); 3743 return r; 3744 } 3745 3746 static int kvm_vm_ioctl_reinject(struct kvm *kvm, 3747 struct kvm_reinject_control *control) 3748 { 3749 if (!kvm->arch.vpit) 3750 return -ENXIO; 3751 mutex_lock(&kvm->arch.vpit->pit_state.lock); 3752 kvm->arch.vpit->pit_state.reinject = control->pit_reinject; 3753 mutex_unlock(&kvm->arch.vpit->pit_state.lock); 3754 return 0; 3755 } 3756 3757 /** 3758 * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot 3759 * @kvm: kvm instance 3760 * @log: slot id and address to which we copy the log 3761 * 3762 * Steps 1-4 below provide general overview of dirty page logging. See 3763 * kvm_get_dirty_log_protect() function description for additional details. 3764 * 3765 * We call kvm_get_dirty_log_protect() to handle steps 1-3, upon return we 3766 * always flush the TLB (step 4) even if previous step failed and the dirty 3767 * bitmap may be corrupt. Regardless of previous outcome the KVM logging API 3768 * does not preclude user space subsequent dirty log read. Flushing TLB ensures 3769 * writes will be marked dirty for next log read. 3770 * 3771 * 1. Take a snapshot of the bit and clear it if needed. 3772 * 2. Write protect the corresponding page. 3773 * 3. Copy the snapshot to the userspace. 3774 * 4. Flush TLB's if needed. 3775 */ 3776 int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log) 3777 { 3778 bool is_dirty = false; 3779 int r; 3780 3781 mutex_lock(&kvm->slots_lock); 3782 3783 /* 3784 * Flush potentially hardware-cached dirty pages to dirty_bitmap. 3785 */ 3786 if (kvm_x86_ops->flush_log_dirty) 3787 kvm_x86_ops->flush_log_dirty(kvm); 3788 3789 r = kvm_get_dirty_log_protect(kvm, log, &is_dirty); 3790 3791 /* 3792 * All the TLBs can be flushed out of mmu lock, see the comments in 3793 * kvm_mmu_slot_remove_write_access(). 3794 */ 3795 lockdep_assert_held(&kvm->slots_lock); 3796 if (is_dirty) 3797 kvm_flush_remote_tlbs(kvm); 3798 3799 mutex_unlock(&kvm->slots_lock); 3800 return r; 3801 } 3802 3803 int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event, 3804 bool line_status) 3805 { 3806 if (!irqchip_in_kernel(kvm)) 3807 return -ENXIO; 3808 3809 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID, 3810 irq_event->irq, irq_event->level, 3811 line_status); 3812 return 0; 3813 } 3814 3815 long kvm_arch_vm_ioctl(struct file *filp, 3816 unsigned int ioctl, unsigned long arg) 3817 { 3818 struct kvm *kvm = filp->private_data; 3819 void __user *argp = (void __user *)arg; 3820 int r = -ENOTTY; 3821 /* 3822 * This union makes it completely explicit to gcc-3.x 3823 * that these two variables' stack usage should be 3824 * combined, not added together. 3825 */ 3826 union { 3827 struct kvm_pit_state ps; 3828 struct kvm_pit_state2 ps2; 3829 struct kvm_pit_config pit_config; 3830 } u; 3831 3832 switch (ioctl) { 3833 case KVM_SET_TSS_ADDR: 3834 r = kvm_vm_ioctl_set_tss_addr(kvm, arg); 3835 break; 3836 case KVM_SET_IDENTITY_MAP_ADDR: { 3837 u64 ident_addr; 3838 3839 r = -EFAULT; 3840 if (copy_from_user(&ident_addr, argp, sizeof ident_addr)) 3841 goto out; 3842 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr); 3843 break; 3844 } 3845 case KVM_SET_NR_MMU_PAGES: 3846 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg); 3847 break; 3848 case KVM_GET_NR_MMU_PAGES: 3849 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm); 3850 break; 3851 case KVM_CREATE_IRQCHIP: { 3852 struct kvm_pic *vpic; 3853 3854 mutex_lock(&kvm->lock); 3855 r = -EEXIST; 3856 if (kvm->arch.vpic) 3857 goto create_irqchip_unlock; 3858 r = -EINVAL; 3859 if (atomic_read(&kvm->online_vcpus)) 3860 goto create_irqchip_unlock; 3861 r = -ENOMEM; 3862 vpic = kvm_create_pic(kvm); 3863 if (vpic) { 3864 r = kvm_ioapic_init(kvm); 3865 if (r) { 3866 mutex_lock(&kvm->slots_lock); 3867 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS, 3868 &vpic->dev_master); 3869 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS, 3870 &vpic->dev_slave); 3871 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS, 3872 &vpic->dev_eclr); 3873 mutex_unlock(&kvm->slots_lock); 3874 kfree(vpic); 3875 goto create_irqchip_unlock; 3876 } 3877 } else 3878 goto create_irqchip_unlock; 3879 smp_wmb(); 3880 kvm->arch.vpic = vpic; 3881 smp_wmb(); 3882 r = kvm_setup_default_irq_routing(kvm); 3883 if (r) { 3884 mutex_lock(&kvm->slots_lock); 3885 mutex_lock(&kvm->irq_lock); 3886 kvm_ioapic_destroy(kvm); 3887 kvm_destroy_pic(kvm); 3888 mutex_unlock(&kvm->irq_lock); 3889 mutex_unlock(&kvm->slots_lock); 3890 } 3891 create_irqchip_unlock: 3892 mutex_unlock(&kvm->lock); 3893 break; 3894 } 3895 case KVM_CREATE_PIT: 3896 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY; 3897 goto create_pit; 3898 case KVM_CREATE_PIT2: 3899 r = -EFAULT; 3900 if (copy_from_user(&u.pit_config, argp, 3901 sizeof(struct kvm_pit_config))) 3902 goto out; 3903 create_pit: 3904 mutex_lock(&kvm->slots_lock); 3905 r = -EEXIST; 3906 if (kvm->arch.vpit) 3907 goto create_pit_unlock; 3908 r = -ENOMEM; 3909 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags); 3910 if (kvm->arch.vpit) 3911 r = 0; 3912 create_pit_unlock: 3913 mutex_unlock(&kvm->slots_lock); 3914 break; 3915 case KVM_GET_IRQCHIP: { 3916 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */ 3917 struct kvm_irqchip *chip; 3918 3919 chip = memdup_user(argp, sizeof(*chip)); 3920 if (IS_ERR(chip)) { 3921 r = PTR_ERR(chip); 3922 goto out; 3923 } 3924 3925 r = -ENXIO; 3926 if (!irqchip_in_kernel(kvm)) 3927 goto get_irqchip_out; 3928 r = kvm_vm_ioctl_get_irqchip(kvm, chip); 3929 if (r) 3930 goto get_irqchip_out; 3931 r = -EFAULT; 3932 if (copy_to_user(argp, chip, sizeof *chip)) 3933 goto get_irqchip_out; 3934 r = 0; 3935 get_irqchip_out: 3936 kfree(chip); 3937 break; 3938 } 3939 case KVM_SET_IRQCHIP: { 3940 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */ 3941 struct kvm_irqchip *chip; 3942 3943 chip = memdup_user(argp, sizeof(*chip)); 3944 if (IS_ERR(chip)) { 3945 r = PTR_ERR(chip); 3946 goto out; 3947 } 3948 3949 r = -ENXIO; 3950 if (!irqchip_in_kernel(kvm)) 3951 goto set_irqchip_out; 3952 r = kvm_vm_ioctl_set_irqchip(kvm, chip); 3953 if (r) 3954 goto set_irqchip_out; 3955 r = 0; 3956 set_irqchip_out: 3957 kfree(chip); 3958 break; 3959 } 3960 case KVM_GET_PIT: { 3961 r = -EFAULT; 3962 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state))) 3963 goto out; 3964 r = -ENXIO; 3965 if (!kvm->arch.vpit) 3966 goto out; 3967 r = kvm_vm_ioctl_get_pit(kvm, &u.ps); 3968 if (r) 3969 goto out; 3970 r = -EFAULT; 3971 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state))) 3972 goto out; 3973 r = 0; 3974 break; 3975 } 3976 case KVM_SET_PIT: { 3977 r = -EFAULT; 3978 if (copy_from_user(&u.ps, argp, sizeof u.ps)) 3979 goto out; 3980 r = -ENXIO; 3981 if (!kvm->arch.vpit) 3982 goto out; 3983 r = kvm_vm_ioctl_set_pit(kvm, &u.ps); 3984 break; 3985 } 3986 case KVM_GET_PIT2: { 3987 r = -ENXIO; 3988 if (!kvm->arch.vpit) 3989 goto out; 3990 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2); 3991 if (r) 3992 goto out; 3993 r = -EFAULT; 3994 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2))) 3995 goto out; 3996 r = 0; 3997 break; 3998 } 3999 case KVM_SET_PIT2: { 4000 r = -EFAULT; 4001 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2))) 4002 goto out; 4003 r = -ENXIO; 4004 if (!kvm->arch.vpit) 4005 goto out; 4006 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2); 4007 break; 4008 } 4009 case KVM_REINJECT_CONTROL: { 4010 struct kvm_reinject_control control; 4011 r = -EFAULT; 4012 if (copy_from_user(&control, argp, sizeof(control))) 4013 goto out; 4014 r = kvm_vm_ioctl_reinject(kvm, &control); 4015 break; 4016 } 4017 case KVM_XEN_HVM_CONFIG: { 4018 r = -EFAULT; 4019 if (copy_from_user(&kvm->arch.xen_hvm_config, argp, 4020 sizeof(struct kvm_xen_hvm_config))) 4021 goto out; 4022 r = -EINVAL; 4023 if (kvm->arch.xen_hvm_config.flags) 4024 goto out; 4025 r = 0; 4026 break; 4027 } 4028 case KVM_SET_CLOCK: { 4029 struct kvm_clock_data user_ns; 4030 u64 now_ns; 4031 s64 delta; 4032 4033 r = -EFAULT; 4034 if (copy_from_user(&user_ns, argp, sizeof(user_ns))) 4035 goto out; 4036 4037 r = -EINVAL; 4038 if (user_ns.flags) 4039 goto out; 4040 4041 r = 0; 4042 local_irq_disable(); 4043 now_ns = get_kernel_ns(); 4044 delta = user_ns.clock - now_ns; 4045 local_irq_enable(); 4046 kvm->arch.kvmclock_offset = delta; 4047 kvm_gen_update_masterclock(kvm); 4048 break; 4049 } 4050 case KVM_GET_CLOCK: { 4051 struct kvm_clock_data user_ns; 4052 u64 now_ns; 4053 4054 local_irq_disable(); 4055 now_ns = get_kernel_ns(); 4056 user_ns.clock = kvm->arch.kvmclock_offset + now_ns; 4057 local_irq_enable(); 4058 user_ns.flags = 0; 4059 memset(&user_ns.pad, 0, sizeof(user_ns.pad)); 4060 4061 r = -EFAULT; 4062 if (copy_to_user(argp, &user_ns, sizeof(user_ns))) 4063 goto out; 4064 r = 0; 4065 break; 4066 } 4067 4068 default: 4069 r = kvm_vm_ioctl_assigned_device(kvm, ioctl, arg); 4070 } 4071 out: 4072 return r; 4073 } 4074 4075 static void kvm_init_msr_list(void) 4076 { 4077 u32 dummy[2]; 4078 unsigned i, j; 4079 4080 /* skip the first msrs in the list. KVM-specific */ 4081 for (i = j = KVM_SAVE_MSRS_BEGIN; i < ARRAY_SIZE(msrs_to_save); i++) { 4082 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0) 4083 continue; 4084 4085 /* 4086 * Even MSRs that are valid in the host may not be exposed 4087 * to the guests in some cases. We could work around this 4088 * in VMX with the generic MSR save/load machinery, but it 4089 * is not really worthwhile since it will really only 4090 * happen with nested virtualization. 4091 */ 4092 switch (msrs_to_save[i]) { 4093 case MSR_IA32_BNDCFGS: 4094 if (!kvm_x86_ops->mpx_supported()) 4095 continue; 4096 break; 4097 default: 4098 break; 4099 } 4100 4101 if (j < i) 4102 msrs_to_save[j] = msrs_to_save[i]; 4103 j++; 4104 } 4105 num_msrs_to_save = j; 4106 } 4107 4108 static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len, 4109 const void *v) 4110 { 4111 int handled = 0; 4112 int n; 4113 4114 do { 4115 n = min(len, 8); 4116 if (!(vcpu->arch.apic && 4117 !kvm_iodevice_write(&vcpu->arch.apic->dev, addr, n, v)) 4118 && kvm_io_bus_write(vcpu->kvm, KVM_MMIO_BUS, addr, n, v)) 4119 break; 4120 handled += n; 4121 addr += n; 4122 len -= n; 4123 v += n; 4124 } while (len); 4125 4126 return handled; 4127 } 4128 4129 static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v) 4130 { 4131 int handled = 0; 4132 int n; 4133 4134 do { 4135 n = min(len, 8); 4136 if (!(vcpu->arch.apic && 4137 !kvm_iodevice_read(&vcpu->arch.apic->dev, addr, n, v)) 4138 && kvm_io_bus_read(vcpu->kvm, KVM_MMIO_BUS, addr, n, v)) 4139 break; 4140 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, *(u64 *)v); 4141 handled += n; 4142 addr += n; 4143 len -= n; 4144 v += n; 4145 } while (len); 4146 4147 return handled; 4148 } 4149 4150 static void kvm_set_segment(struct kvm_vcpu *vcpu, 4151 struct kvm_segment *var, int seg) 4152 { 4153 kvm_x86_ops->set_segment(vcpu, var, seg); 4154 } 4155 4156 void kvm_get_segment(struct kvm_vcpu *vcpu, 4157 struct kvm_segment *var, int seg) 4158 { 4159 kvm_x86_ops->get_segment(vcpu, var, seg); 4160 } 4161 4162 gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access, 4163 struct x86_exception *exception) 4164 { 4165 gpa_t t_gpa; 4166 4167 BUG_ON(!mmu_is_nested(vcpu)); 4168 4169 /* NPT walks are always user-walks */ 4170 access |= PFERR_USER_MASK; 4171 t_gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, exception); 4172 4173 return t_gpa; 4174 } 4175 4176 gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva, 4177 struct x86_exception *exception) 4178 { 4179 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0; 4180 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception); 4181 } 4182 4183 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva, 4184 struct x86_exception *exception) 4185 { 4186 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0; 4187 access |= PFERR_FETCH_MASK; 4188 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception); 4189 } 4190 4191 gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva, 4192 struct x86_exception *exception) 4193 { 4194 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0; 4195 access |= PFERR_WRITE_MASK; 4196 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception); 4197 } 4198 4199 /* uses this to access any guest's mapped memory without checking CPL */ 4200 gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva, 4201 struct x86_exception *exception) 4202 { 4203 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception); 4204 } 4205 4206 static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes, 4207 struct kvm_vcpu *vcpu, u32 access, 4208 struct x86_exception *exception) 4209 { 4210 void *data = val; 4211 int r = X86EMUL_CONTINUE; 4212 4213 while (bytes) { 4214 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access, 4215 exception); 4216 unsigned offset = addr & (PAGE_SIZE-1); 4217 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset); 4218 int ret; 4219 4220 if (gpa == UNMAPPED_GVA) 4221 return X86EMUL_PROPAGATE_FAULT; 4222 ret = kvm_read_guest_page(vcpu->kvm, gpa >> PAGE_SHIFT, data, 4223 offset, toread); 4224 if (ret < 0) { 4225 r = X86EMUL_IO_NEEDED; 4226 goto out; 4227 } 4228 4229 bytes -= toread; 4230 data += toread; 4231 addr += toread; 4232 } 4233 out: 4234 return r; 4235 } 4236 4237 /* used for instruction fetching */ 4238 static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt, 4239 gva_t addr, void *val, unsigned int bytes, 4240 struct x86_exception *exception) 4241 { 4242 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 4243 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0; 4244 unsigned offset; 4245 int ret; 4246 4247 /* Inline kvm_read_guest_virt_helper for speed. */ 4248 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access|PFERR_FETCH_MASK, 4249 exception); 4250 if (unlikely(gpa == UNMAPPED_GVA)) 4251 return X86EMUL_PROPAGATE_FAULT; 4252 4253 offset = addr & (PAGE_SIZE-1); 4254 if (WARN_ON(offset + bytes > PAGE_SIZE)) 4255 bytes = (unsigned)PAGE_SIZE - offset; 4256 ret = kvm_read_guest_page(vcpu->kvm, gpa >> PAGE_SHIFT, val, 4257 offset, bytes); 4258 if (unlikely(ret < 0)) 4259 return X86EMUL_IO_NEEDED; 4260 4261 return X86EMUL_CONTINUE; 4262 } 4263 4264 int kvm_read_guest_virt(struct x86_emulate_ctxt *ctxt, 4265 gva_t addr, void *val, unsigned int bytes, 4266 struct x86_exception *exception) 4267 { 4268 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 4269 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0; 4270 4271 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access, 4272 exception); 4273 } 4274 EXPORT_SYMBOL_GPL(kvm_read_guest_virt); 4275 4276 static int kvm_read_guest_virt_system(struct x86_emulate_ctxt *ctxt, 4277 gva_t addr, void *val, unsigned int bytes, 4278 struct x86_exception *exception) 4279 { 4280 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 4281 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, exception); 4282 } 4283 4284 int kvm_write_guest_virt_system(struct x86_emulate_ctxt *ctxt, 4285 gva_t addr, void *val, 4286 unsigned int bytes, 4287 struct x86_exception *exception) 4288 { 4289 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 4290 void *data = val; 4291 int r = X86EMUL_CONTINUE; 4292 4293 while (bytes) { 4294 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, 4295 PFERR_WRITE_MASK, 4296 exception); 4297 unsigned offset = addr & (PAGE_SIZE-1); 4298 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset); 4299 int ret; 4300 4301 if (gpa == UNMAPPED_GVA) 4302 return X86EMUL_PROPAGATE_FAULT; 4303 ret = kvm_write_guest(vcpu->kvm, gpa, data, towrite); 4304 if (ret < 0) { 4305 r = X86EMUL_IO_NEEDED; 4306 goto out; 4307 } 4308 4309 bytes -= towrite; 4310 data += towrite; 4311 addr += towrite; 4312 } 4313 out: 4314 return r; 4315 } 4316 EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system); 4317 4318 static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva, 4319 gpa_t *gpa, struct x86_exception *exception, 4320 bool write) 4321 { 4322 u32 access = ((kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0) 4323 | (write ? PFERR_WRITE_MASK : 0); 4324 4325 if (vcpu_match_mmio_gva(vcpu, gva) 4326 && !permission_fault(vcpu, vcpu->arch.walk_mmu, 4327 vcpu->arch.access, access)) { 4328 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT | 4329 (gva & (PAGE_SIZE - 1)); 4330 trace_vcpu_match_mmio(gva, *gpa, write, false); 4331 return 1; 4332 } 4333 4334 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception); 4335 4336 if (*gpa == UNMAPPED_GVA) 4337 return -1; 4338 4339 /* For APIC access vmexit */ 4340 if ((*gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE) 4341 return 1; 4342 4343 if (vcpu_match_mmio_gpa(vcpu, *gpa)) { 4344 trace_vcpu_match_mmio(gva, *gpa, write, true); 4345 return 1; 4346 } 4347 4348 return 0; 4349 } 4350 4351 int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa, 4352 const void *val, int bytes) 4353 { 4354 int ret; 4355 4356 ret = kvm_write_guest(vcpu->kvm, gpa, val, bytes); 4357 if (ret < 0) 4358 return 0; 4359 kvm_mmu_pte_write(vcpu, gpa, val, bytes); 4360 return 1; 4361 } 4362 4363 struct read_write_emulator_ops { 4364 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val, 4365 int bytes); 4366 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa, 4367 void *val, int bytes); 4368 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa, 4369 int bytes, void *val); 4370 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa, 4371 void *val, int bytes); 4372 bool write; 4373 }; 4374 4375 static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes) 4376 { 4377 if (vcpu->mmio_read_completed) { 4378 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes, 4379 vcpu->mmio_fragments[0].gpa, *(u64 *)val); 4380 vcpu->mmio_read_completed = 0; 4381 return 1; 4382 } 4383 4384 return 0; 4385 } 4386 4387 static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa, 4388 void *val, int bytes) 4389 { 4390 return !kvm_read_guest(vcpu->kvm, gpa, val, bytes); 4391 } 4392 4393 static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa, 4394 void *val, int bytes) 4395 { 4396 return emulator_write_phys(vcpu, gpa, val, bytes); 4397 } 4398 4399 static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val) 4400 { 4401 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val); 4402 return vcpu_mmio_write(vcpu, gpa, bytes, val); 4403 } 4404 4405 static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, 4406 void *val, int bytes) 4407 { 4408 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0); 4409 return X86EMUL_IO_NEEDED; 4410 } 4411 4412 static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, 4413 void *val, int bytes) 4414 { 4415 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0]; 4416 4417 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len)); 4418 return X86EMUL_CONTINUE; 4419 } 4420 4421 static const struct read_write_emulator_ops read_emultor = { 4422 .read_write_prepare = read_prepare, 4423 .read_write_emulate = read_emulate, 4424 .read_write_mmio = vcpu_mmio_read, 4425 .read_write_exit_mmio = read_exit_mmio, 4426 }; 4427 4428 static const struct read_write_emulator_ops write_emultor = { 4429 .read_write_emulate = write_emulate, 4430 .read_write_mmio = write_mmio, 4431 .read_write_exit_mmio = write_exit_mmio, 4432 .write = true, 4433 }; 4434 4435 static int emulator_read_write_onepage(unsigned long addr, void *val, 4436 unsigned int bytes, 4437 struct x86_exception *exception, 4438 struct kvm_vcpu *vcpu, 4439 const struct read_write_emulator_ops *ops) 4440 { 4441 gpa_t gpa; 4442 int handled, ret; 4443 bool write = ops->write; 4444 struct kvm_mmio_fragment *frag; 4445 4446 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write); 4447 4448 if (ret < 0) 4449 return X86EMUL_PROPAGATE_FAULT; 4450 4451 /* For APIC access vmexit */ 4452 if (ret) 4453 goto mmio; 4454 4455 if (ops->read_write_emulate(vcpu, gpa, val, bytes)) 4456 return X86EMUL_CONTINUE; 4457 4458 mmio: 4459 /* 4460 * Is this MMIO handled locally? 4461 */ 4462 handled = ops->read_write_mmio(vcpu, gpa, bytes, val); 4463 if (handled == bytes) 4464 return X86EMUL_CONTINUE; 4465 4466 gpa += handled; 4467 bytes -= handled; 4468 val += handled; 4469 4470 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS); 4471 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++]; 4472 frag->gpa = gpa; 4473 frag->data = val; 4474 frag->len = bytes; 4475 return X86EMUL_CONTINUE; 4476 } 4477 4478 int emulator_read_write(struct x86_emulate_ctxt *ctxt, unsigned long addr, 4479 void *val, unsigned int bytes, 4480 struct x86_exception *exception, 4481 const struct read_write_emulator_ops *ops) 4482 { 4483 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 4484 gpa_t gpa; 4485 int rc; 4486 4487 if (ops->read_write_prepare && 4488 ops->read_write_prepare(vcpu, val, bytes)) 4489 return X86EMUL_CONTINUE; 4490 4491 vcpu->mmio_nr_fragments = 0; 4492 4493 /* Crossing a page boundary? */ 4494 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) { 4495 int now; 4496 4497 now = -addr & ~PAGE_MASK; 4498 rc = emulator_read_write_onepage(addr, val, now, exception, 4499 vcpu, ops); 4500 4501 if (rc != X86EMUL_CONTINUE) 4502 return rc; 4503 addr += now; 4504 if (ctxt->mode != X86EMUL_MODE_PROT64) 4505 addr = (u32)addr; 4506 val += now; 4507 bytes -= now; 4508 } 4509 4510 rc = emulator_read_write_onepage(addr, val, bytes, exception, 4511 vcpu, ops); 4512 if (rc != X86EMUL_CONTINUE) 4513 return rc; 4514 4515 if (!vcpu->mmio_nr_fragments) 4516 return rc; 4517 4518 gpa = vcpu->mmio_fragments[0].gpa; 4519 4520 vcpu->mmio_needed = 1; 4521 vcpu->mmio_cur_fragment = 0; 4522 4523 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len); 4524 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write; 4525 vcpu->run->exit_reason = KVM_EXIT_MMIO; 4526 vcpu->run->mmio.phys_addr = gpa; 4527 4528 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes); 4529 } 4530 4531 static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt, 4532 unsigned long addr, 4533 void *val, 4534 unsigned int bytes, 4535 struct x86_exception *exception) 4536 { 4537 return emulator_read_write(ctxt, addr, val, bytes, 4538 exception, &read_emultor); 4539 } 4540 4541 int emulator_write_emulated(struct x86_emulate_ctxt *ctxt, 4542 unsigned long addr, 4543 const void *val, 4544 unsigned int bytes, 4545 struct x86_exception *exception) 4546 { 4547 return emulator_read_write(ctxt, addr, (void *)val, bytes, 4548 exception, &write_emultor); 4549 } 4550 4551 #define CMPXCHG_TYPE(t, ptr, old, new) \ 4552 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old)) 4553 4554 #ifdef CONFIG_X86_64 4555 # define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new) 4556 #else 4557 # define CMPXCHG64(ptr, old, new) \ 4558 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old)) 4559 #endif 4560 4561 static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt, 4562 unsigned long addr, 4563 const void *old, 4564 const void *new, 4565 unsigned int bytes, 4566 struct x86_exception *exception) 4567 { 4568 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 4569 gpa_t gpa; 4570 struct page *page; 4571 char *kaddr; 4572 bool exchanged; 4573 4574 /* guests cmpxchg8b have to be emulated atomically */ 4575 if (bytes > 8 || (bytes & (bytes - 1))) 4576 goto emul_write; 4577 4578 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL); 4579 4580 if (gpa == UNMAPPED_GVA || 4581 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE) 4582 goto emul_write; 4583 4584 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK)) 4585 goto emul_write; 4586 4587 page = gfn_to_page(vcpu->kvm, gpa >> PAGE_SHIFT); 4588 if (is_error_page(page)) 4589 goto emul_write; 4590 4591 kaddr = kmap_atomic(page); 4592 kaddr += offset_in_page(gpa); 4593 switch (bytes) { 4594 case 1: 4595 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new); 4596 break; 4597 case 2: 4598 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new); 4599 break; 4600 case 4: 4601 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new); 4602 break; 4603 case 8: 4604 exchanged = CMPXCHG64(kaddr, old, new); 4605 break; 4606 default: 4607 BUG(); 4608 } 4609 kunmap_atomic(kaddr); 4610 kvm_release_page_dirty(page); 4611 4612 if (!exchanged) 4613 return X86EMUL_CMPXCHG_FAILED; 4614 4615 mark_page_dirty(vcpu->kvm, gpa >> PAGE_SHIFT); 4616 kvm_mmu_pte_write(vcpu, gpa, new, bytes); 4617 4618 return X86EMUL_CONTINUE; 4619 4620 emul_write: 4621 printk_once(KERN_WARNING "kvm: emulating exchange as write\n"); 4622 4623 return emulator_write_emulated(ctxt, addr, new, bytes, exception); 4624 } 4625 4626 static int kernel_pio(struct kvm_vcpu *vcpu, void *pd) 4627 { 4628 /* TODO: String I/O for in kernel device */ 4629 int r; 4630 4631 if (vcpu->arch.pio.in) 4632 r = kvm_io_bus_read(vcpu->kvm, KVM_PIO_BUS, vcpu->arch.pio.port, 4633 vcpu->arch.pio.size, pd); 4634 else 4635 r = kvm_io_bus_write(vcpu->kvm, KVM_PIO_BUS, 4636 vcpu->arch.pio.port, vcpu->arch.pio.size, 4637 pd); 4638 return r; 4639 } 4640 4641 static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size, 4642 unsigned short port, void *val, 4643 unsigned int count, bool in) 4644 { 4645 vcpu->arch.pio.port = port; 4646 vcpu->arch.pio.in = in; 4647 vcpu->arch.pio.count = count; 4648 vcpu->arch.pio.size = size; 4649 4650 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) { 4651 vcpu->arch.pio.count = 0; 4652 return 1; 4653 } 4654 4655 vcpu->run->exit_reason = KVM_EXIT_IO; 4656 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT; 4657 vcpu->run->io.size = size; 4658 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE; 4659 vcpu->run->io.count = count; 4660 vcpu->run->io.port = port; 4661 4662 return 0; 4663 } 4664 4665 static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt, 4666 int size, unsigned short port, void *val, 4667 unsigned int count) 4668 { 4669 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 4670 int ret; 4671 4672 if (vcpu->arch.pio.count) 4673 goto data_avail; 4674 4675 ret = emulator_pio_in_out(vcpu, size, port, val, count, true); 4676 if (ret) { 4677 data_avail: 4678 memcpy(val, vcpu->arch.pio_data, size * count); 4679 trace_kvm_pio(KVM_PIO_IN, port, size, count, vcpu->arch.pio_data); 4680 vcpu->arch.pio.count = 0; 4681 return 1; 4682 } 4683 4684 return 0; 4685 } 4686 4687 static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt, 4688 int size, unsigned short port, 4689 const void *val, unsigned int count) 4690 { 4691 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 4692 4693 memcpy(vcpu->arch.pio_data, val, size * count); 4694 trace_kvm_pio(KVM_PIO_OUT, port, size, count, vcpu->arch.pio_data); 4695 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false); 4696 } 4697 4698 static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg) 4699 { 4700 return kvm_x86_ops->get_segment_base(vcpu, seg); 4701 } 4702 4703 static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address) 4704 { 4705 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address); 4706 } 4707 4708 int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu) 4709 { 4710 if (!need_emulate_wbinvd(vcpu)) 4711 return X86EMUL_CONTINUE; 4712 4713 if (kvm_x86_ops->has_wbinvd_exit()) { 4714 int cpu = get_cpu(); 4715 4716 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask); 4717 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask, 4718 wbinvd_ipi, NULL, 1); 4719 put_cpu(); 4720 cpumask_clear(vcpu->arch.wbinvd_dirty_mask); 4721 } else 4722 wbinvd(); 4723 return X86EMUL_CONTINUE; 4724 } 4725 EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd); 4726 4727 static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt) 4728 { 4729 kvm_emulate_wbinvd(emul_to_vcpu(ctxt)); 4730 } 4731 4732 int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long *dest) 4733 { 4734 return kvm_get_dr(emul_to_vcpu(ctxt), dr, dest); 4735 } 4736 4737 int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long value) 4738 { 4739 4740 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value); 4741 } 4742 4743 static u64 mk_cr_64(u64 curr_cr, u32 new_val) 4744 { 4745 return (curr_cr & ~((1ULL << 32) - 1)) | new_val; 4746 } 4747 4748 static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr) 4749 { 4750 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 4751 unsigned long value; 4752 4753 switch (cr) { 4754 case 0: 4755 value = kvm_read_cr0(vcpu); 4756 break; 4757 case 2: 4758 value = vcpu->arch.cr2; 4759 break; 4760 case 3: 4761 value = kvm_read_cr3(vcpu); 4762 break; 4763 case 4: 4764 value = kvm_read_cr4(vcpu); 4765 break; 4766 case 8: 4767 value = kvm_get_cr8(vcpu); 4768 break; 4769 default: 4770 kvm_err("%s: unexpected cr %u\n", __func__, cr); 4771 return 0; 4772 } 4773 4774 return value; 4775 } 4776 4777 static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val) 4778 { 4779 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 4780 int res = 0; 4781 4782 switch (cr) { 4783 case 0: 4784 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val)); 4785 break; 4786 case 2: 4787 vcpu->arch.cr2 = val; 4788 break; 4789 case 3: 4790 res = kvm_set_cr3(vcpu, val); 4791 break; 4792 case 4: 4793 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val)); 4794 break; 4795 case 8: 4796 res = kvm_set_cr8(vcpu, val); 4797 break; 4798 default: 4799 kvm_err("%s: unexpected cr %u\n", __func__, cr); 4800 res = -1; 4801 } 4802 4803 return res; 4804 } 4805 4806 static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt) 4807 { 4808 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt)); 4809 } 4810 4811 static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt) 4812 { 4813 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt); 4814 } 4815 4816 static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt) 4817 { 4818 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt); 4819 } 4820 4821 static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt) 4822 { 4823 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt); 4824 } 4825 4826 static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt) 4827 { 4828 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt); 4829 } 4830 4831 static unsigned long emulator_get_cached_segment_base( 4832 struct x86_emulate_ctxt *ctxt, int seg) 4833 { 4834 return get_segment_base(emul_to_vcpu(ctxt), seg); 4835 } 4836 4837 static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector, 4838 struct desc_struct *desc, u32 *base3, 4839 int seg) 4840 { 4841 struct kvm_segment var; 4842 4843 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg); 4844 *selector = var.selector; 4845 4846 if (var.unusable) { 4847 memset(desc, 0, sizeof(*desc)); 4848 return false; 4849 } 4850 4851 if (var.g) 4852 var.limit >>= 12; 4853 set_desc_limit(desc, var.limit); 4854 set_desc_base(desc, (unsigned long)var.base); 4855 #ifdef CONFIG_X86_64 4856 if (base3) 4857 *base3 = var.base >> 32; 4858 #endif 4859 desc->type = var.type; 4860 desc->s = var.s; 4861 desc->dpl = var.dpl; 4862 desc->p = var.present; 4863 desc->avl = var.avl; 4864 desc->l = var.l; 4865 desc->d = var.db; 4866 desc->g = var.g; 4867 4868 return true; 4869 } 4870 4871 static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector, 4872 struct desc_struct *desc, u32 base3, 4873 int seg) 4874 { 4875 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 4876 struct kvm_segment var; 4877 4878 var.selector = selector; 4879 var.base = get_desc_base(desc); 4880 #ifdef CONFIG_X86_64 4881 var.base |= ((u64)base3) << 32; 4882 #endif 4883 var.limit = get_desc_limit(desc); 4884 if (desc->g) 4885 var.limit = (var.limit << 12) | 0xfff; 4886 var.type = desc->type; 4887 var.dpl = desc->dpl; 4888 var.db = desc->d; 4889 var.s = desc->s; 4890 var.l = desc->l; 4891 var.g = desc->g; 4892 var.avl = desc->avl; 4893 var.present = desc->p; 4894 var.unusable = !var.present; 4895 var.padding = 0; 4896 4897 kvm_set_segment(vcpu, &var, seg); 4898 return; 4899 } 4900 4901 static int emulator_get_msr(struct x86_emulate_ctxt *ctxt, 4902 u32 msr_index, u64 *pdata) 4903 { 4904 return kvm_get_msr(emul_to_vcpu(ctxt), msr_index, pdata); 4905 } 4906 4907 static int emulator_set_msr(struct x86_emulate_ctxt *ctxt, 4908 u32 msr_index, u64 data) 4909 { 4910 struct msr_data msr; 4911 4912 msr.data = data; 4913 msr.index = msr_index; 4914 msr.host_initiated = false; 4915 return kvm_set_msr(emul_to_vcpu(ctxt), &msr); 4916 } 4917 4918 static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt, 4919 u32 pmc) 4920 { 4921 return kvm_pmu_check_pmc(emul_to_vcpu(ctxt), pmc); 4922 } 4923 4924 static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt, 4925 u32 pmc, u64 *pdata) 4926 { 4927 return kvm_pmu_read_pmc(emul_to_vcpu(ctxt), pmc, pdata); 4928 } 4929 4930 static void emulator_halt(struct x86_emulate_ctxt *ctxt) 4931 { 4932 emul_to_vcpu(ctxt)->arch.halt_request = 1; 4933 } 4934 4935 static void emulator_get_fpu(struct x86_emulate_ctxt *ctxt) 4936 { 4937 preempt_disable(); 4938 kvm_load_guest_fpu(emul_to_vcpu(ctxt)); 4939 /* 4940 * CR0.TS may reference the host fpu state, not the guest fpu state, 4941 * so it may be clear at this point. 4942 */ 4943 clts(); 4944 } 4945 4946 static void emulator_put_fpu(struct x86_emulate_ctxt *ctxt) 4947 { 4948 preempt_enable(); 4949 } 4950 4951 static int emulator_intercept(struct x86_emulate_ctxt *ctxt, 4952 struct x86_instruction_info *info, 4953 enum x86_intercept_stage stage) 4954 { 4955 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage); 4956 } 4957 4958 static void emulator_get_cpuid(struct x86_emulate_ctxt *ctxt, 4959 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx) 4960 { 4961 kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx); 4962 } 4963 4964 static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg) 4965 { 4966 return kvm_register_read(emul_to_vcpu(ctxt), reg); 4967 } 4968 4969 static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val) 4970 { 4971 kvm_register_write(emul_to_vcpu(ctxt), reg, val); 4972 } 4973 4974 static void emulator_set_nmi_mask(struct x86_emulate_ctxt *ctxt, bool masked) 4975 { 4976 kvm_x86_ops->set_nmi_mask(emul_to_vcpu(ctxt), masked); 4977 } 4978 4979 static const struct x86_emulate_ops emulate_ops = { 4980 .read_gpr = emulator_read_gpr, 4981 .write_gpr = emulator_write_gpr, 4982 .read_std = kvm_read_guest_virt_system, 4983 .write_std = kvm_write_guest_virt_system, 4984 .fetch = kvm_fetch_guest_virt, 4985 .read_emulated = emulator_read_emulated, 4986 .write_emulated = emulator_write_emulated, 4987 .cmpxchg_emulated = emulator_cmpxchg_emulated, 4988 .invlpg = emulator_invlpg, 4989 .pio_in_emulated = emulator_pio_in_emulated, 4990 .pio_out_emulated = emulator_pio_out_emulated, 4991 .get_segment = emulator_get_segment, 4992 .set_segment = emulator_set_segment, 4993 .get_cached_segment_base = emulator_get_cached_segment_base, 4994 .get_gdt = emulator_get_gdt, 4995 .get_idt = emulator_get_idt, 4996 .set_gdt = emulator_set_gdt, 4997 .set_idt = emulator_set_idt, 4998 .get_cr = emulator_get_cr, 4999 .set_cr = emulator_set_cr, 5000 .cpl = emulator_get_cpl, 5001 .get_dr = emulator_get_dr, 5002 .set_dr = emulator_set_dr, 5003 .set_msr = emulator_set_msr, 5004 .get_msr = emulator_get_msr, 5005 .check_pmc = emulator_check_pmc, 5006 .read_pmc = emulator_read_pmc, 5007 .halt = emulator_halt, 5008 .wbinvd = emulator_wbinvd, 5009 .fix_hypercall = emulator_fix_hypercall, 5010 .get_fpu = emulator_get_fpu, 5011 .put_fpu = emulator_put_fpu, 5012 .intercept = emulator_intercept, 5013 .get_cpuid = emulator_get_cpuid, 5014 .set_nmi_mask = emulator_set_nmi_mask, 5015 }; 5016 5017 static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask) 5018 { 5019 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu); 5020 /* 5021 * an sti; sti; sequence only disable interrupts for the first 5022 * instruction. So, if the last instruction, be it emulated or 5023 * not, left the system with the INT_STI flag enabled, it 5024 * means that the last instruction is an sti. We should not 5025 * leave the flag on in this case. The same goes for mov ss 5026 */ 5027 if (int_shadow & mask) 5028 mask = 0; 5029 if (unlikely(int_shadow || mask)) { 5030 kvm_x86_ops->set_interrupt_shadow(vcpu, mask); 5031 if (!mask) 5032 kvm_make_request(KVM_REQ_EVENT, vcpu); 5033 } 5034 } 5035 5036 static bool inject_emulated_exception(struct kvm_vcpu *vcpu) 5037 { 5038 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt; 5039 if (ctxt->exception.vector == PF_VECTOR) 5040 return kvm_propagate_fault(vcpu, &ctxt->exception); 5041 5042 if (ctxt->exception.error_code_valid) 5043 kvm_queue_exception_e(vcpu, ctxt->exception.vector, 5044 ctxt->exception.error_code); 5045 else 5046 kvm_queue_exception(vcpu, ctxt->exception.vector); 5047 return false; 5048 } 5049 5050 static void init_emulate_ctxt(struct kvm_vcpu *vcpu) 5051 { 5052 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt; 5053 int cs_db, cs_l; 5054 5055 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l); 5056 5057 ctxt->eflags = kvm_get_rflags(vcpu); 5058 ctxt->eip = kvm_rip_read(vcpu); 5059 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL : 5060 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 : 5061 (cs_l && is_long_mode(vcpu)) ? X86EMUL_MODE_PROT64 : 5062 cs_db ? X86EMUL_MODE_PROT32 : 5063 X86EMUL_MODE_PROT16; 5064 ctxt->guest_mode = is_guest_mode(vcpu); 5065 5066 init_decode_cache(ctxt); 5067 vcpu->arch.emulate_regs_need_sync_from_vcpu = false; 5068 } 5069 5070 int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip) 5071 { 5072 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt; 5073 int ret; 5074 5075 init_emulate_ctxt(vcpu); 5076 5077 ctxt->op_bytes = 2; 5078 ctxt->ad_bytes = 2; 5079 ctxt->_eip = ctxt->eip + inc_eip; 5080 ret = emulate_int_real(ctxt, irq); 5081 5082 if (ret != X86EMUL_CONTINUE) 5083 return EMULATE_FAIL; 5084 5085 ctxt->eip = ctxt->_eip; 5086 kvm_rip_write(vcpu, ctxt->eip); 5087 kvm_set_rflags(vcpu, ctxt->eflags); 5088 5089 if (irq == NMI_VECTOR) 5090 vcpu->arch.nmi_pending = 0; 5091 else 5092 vcpu->arch.interrupt.pending = false; 5093 5094 return EMULATE_DONE; 5095 } 5096 EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt); 5097 5098 static int handle_emulation_failure(struct kvm_vcpu *vcpu) 5099 { 5100 int r = EMULATE_DONE; 5101 5102 ++vcpu->stat.insn_emulation_fail; 5103 trace_kvm_emulate_insn_failed(vcpu); 5104 if (!is_guest_mode(vcpu) && kvm_x86_ops->get_cpl(vcpu) == 0) { 5105 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR; 5106 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION; 5107 vcpu->run->internal.ndata = 0; 5108 r = EMULATE_FAIL; 5109 } 5110 kvm_queue_exception(vcpu, UD_VECTOR); 5111 5112 return r; 5113 } 5114 5115 static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t cr2, 5116 bool write_fault_to_shadow_pgtable, 5117 int emulation_type) 5118 { 5119 gpa_t gpa = cr2; 5120 pfn_t pfn; 5121 5122 if (emulation_type & EMULTYPE_NO_REEXECUTE) 5123 return false; 5124 5125 if (!vcpu->arch.mmu.direct_map) { 5126 /* 5127 * Write permission should be allowed since only 5128 * write access need to be emulated. 5129 */ 5130 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL); 5131 5132 /* 5133 * If the mapping is invalid in guest, let cpu retry 5134 * it to generate fault. 5135 */ 5136 if (gpa == UNMAPPED_GVA) 5137 return true; 5138 } 5139 5140 /* 5141 * Do not retry the unhandleable instruction if it faults on the 5142 * readonly host memory, otherwise it will goto a infinite loop: 5143 * retry instruction -> write #PF -> emulation fail -> retry 5144 * instruction -> ... 5145 */ 5146 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa)); 5147 5148 /* 5149 * If the instruction failed on the error pfn, it can not be fixed, 5150 * report the error to userspace. 5151 */ 5152 if (is_error_noslot_pfn(pfn)) 5153 return false; 5154 5155 kvm_release_pfn_clean(pfn); 5156 5157 /* The instructions are well-emulated on direct mmu. */ 5158 if (vcpu->arch.mmu.direct_map) { 5159 unsigned int indirect_shadow_pages; 5160 5161 spin_lock(&vcpu->kvm->mmu_lock); 5162 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages; 5163 spin_unlock(&vcpu->kvm->mmu_lock); 5164 5165 if (indirect_shadow_pages) 5166 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa)); 5167 5168 return true; 5169 } 5170 5171 /* 5172 * if emulation was due to access to shadowed page table 5173 * and it failed try to unshadow page and re-enter the 5174 * guest to let CPU execute the instruction. 5175 */ 5176 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa)); 5177 5178 /* 5179 * If the access faults on its page table, it can not 5180 * be fixed by unprotecting shadow page and it should 5181 * be reported to userspace. 5182 */ 5183 return !write_fault_to_shadow_pgtable; 5184 } 5185 5186 static bool retry_instruction(struct x86_emulate_ctxt *ctxt, 5187 unsigned long cr2, int emulation_type) 5188 { 5189 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 5190 unsigned long last_retry_eip, last_retry_addr, gpa = cr2; 5191 5192 last_retry_eip = vcpu->arch.last_retry_eip; 5193 last_retry_addr = vcpu->arch.last_retry_addr; 5194 5195 /* 5196 * If the emulation is caused by #PF and it is non-page_table 5197 * writing instruction, it means the VM-EXIT is caused by shadow 5198 * page protected, we can zap the shadow page and retry this 5199 * instruction directly. 5200 * 5201 * Note: if the guest uses a non-page-table modifying instruction 5202 * on the PDE that points to the instruction, then we will unmap 5203 * the instruction and go to an infinite loop. So, we cache the 5204 * last retried eip and the last fault address, if we meet the eip 5205 * and the address again, we can break out of the potential infinite 5206 * loop. 5207 */ 5208 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0; 5209 5210 if (!(emulation_type & EMULTYPE_RETRY)) 5211 return false; 5212 5213 if (x86_page_table_writing_insn(ctxt)) 5214 return false; 5215 5216 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2) 5217 return false; 5218 5219 vcpu->arch.last_retry_eip = ctxt->eip; 5220 vcpu->arch.last_retry_addr = cr2; 5221 5222 if (!vcpu->arch.mmu.direct_map) 5223 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL); 5224 5225 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa)); 5226 5227 return true; 5228 } 5229 5230 static int complete_emulated_mmio(struct kvm_vcpu *vcpu); 5231 static int complete_emulated_pio(struct kvm_vcpu *vcpu); 5232 5233 static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7, 5234 unsigned long *db) 5235 { 5236 u32 dr6 = 0; 5237 int i; 5238 u32 enable, rwlen; 5239 5240 enable = dr7; 5241 rwlen = dr7 >> 16; 5242 for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4) 5243 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr) 5244 dr6 |= (1 << i); 5245 return dr6; 5246 } 5247 5248 static void kvm_vcpu_check_singlestep(struct kvm_vcpu *vcpu, unsigned long rflags, int *r) 5249 { 5250 struct kvm_run *kvm_run = vcpu->run; 5251 5252 /* 5253 * rflags is the old, "raw" value of the flags. The new value has 5254 * not been saved yet. 5255 * 5256 * This is correct even for TF set by the guest, because "the 5257 * processor will not generate this exception after the instruction 5258 * that sets the TF flag". 5259 */ 5260 if (unlikely(rflags & X86_EFLAGS_TF)) { 5261 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) { 5262 kvm_run->debug.arch.dr6 = DR6_BS | DR6_FIXED_1 | 5263 DR6_RTM; 5264 kvm_run->debug.arch.pc = vcpu->arch.singlestep_rip; 5265 kvm_run->debug.arch.exception = DB_VECTOR; 5266 kvm_run->exit_reason = KVM_EXIT_DEBUG; 5267 *r = EMULATE_USER_EXIT; 5268 } else { 5269 vcpu->arch.emulate_ctxt.eflags &= ~X86_EFLAGS_TF; 5270 /* 5271 * "Certain debug exceptions may clear bit 0-3. The 5272 * remaining contents of the DR6 register are never 5273 * cleared by the processor". 5274 */ 5275 vcpu->arch.dr6 &= ~15; 5276 vcpu->arch.dr6 |= DR6_BS | DR6_RTM; 5277 kvm_queue_exception(vcpu, DB_VECTOR); 5278 } 5279 } 5280 } 5281 5282 static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r) 5283 { 5284 if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) && 5285 (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) { 5286 struct kvm_run *kvm_run = vcpu->run; 5287 unsigned long eip = kvm_get_linear_rip(vcpu); 5288 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0, 5289 vcpu->arch.guest_debug_dr7, 5290 vcpu->arch.eff_db); 5291 5292 if (dr6 != 0) { 5293 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1 | DR6_RTM; 5294 kvm_run->debug.arch.pc = eip; 5295 kvm_run->debug.arch.exception = DB_VECTOR; 5296 kvm_run->exit_reason = KVM_EXIT_DEBUG; 5297 *r = EMULATE_USER_EXIT; 5298 return true; 5299 } 5300 } 5301 5302 if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) && 5303 !(kvm_get_rflags(vcpu) & X86_EFLAGS_RF)) { 5304 unsigned long eip = kvm_get_linear_rip(vcpu); 5305 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0, 5306 vcpu->arch.dr7, 5307 vcpu->arch.db); 5308 5309 if (dr6 != 0) { 5310 vcpu->arch.dr6 &= ~15; 5311 vcpu->arch.dr6 |= dr6 | DR6_RTM; 5312 kvm_queue_exception(vcpu, DB_VECTOR); 5313 *r = EMULATE_DONE; 5314 return true; 5315 } 5316 } 5317 5318 return false; 5319 } 5320 5321 int x86_emulate_instruction(struct kvm_vcpu *vcpu, 5322 unsigned long cr2, 5323 int emulation_type, 5324 void *insn, 5325 int insn_len) 5326 { 5327 int r; 5328 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt; 5329 bool writeback = true; 5330 bool write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable; 5331 5332 /* 5333 * Clear write_fault_to_shadow_pgtable here to ensure it is 5334 * never reused. 5335 */ 5336 vcpu->arch.write_fault_to_shadow_pgtable = false; 5337 kvm_clear_exception_queue(vcpu); 5338 5339 if (!(emulation_type & EMULTYPE_NO_DECODE)) { 5340 init_emulate_ctxt(vcpu); 5341 5342 /* 5343 * We will reenter on the same instruction since 5344 * we do not set complete_userspace_io. This does not 5345 * handle watchpoints yet, those would be handled in 5346 * the emulate_ops. 5347 */ 5348 if (kvm_vcpu_check_breakpoint(vcpu, &r)) 5349 return r; 5350 5351 ctxt->interruptibility = 0; 5352 ctxt->have_exception = false; 5353 ctxt->exception.vector = -1; 5354 ctxt->perm_ok = false; 5355 5356 ctxt->ud = emulation_type & EMULTYPE_TRAP_UD; 5357 5358 r = x86_decode_insn(ctxt, insn, insn_len); 5359 5360 trace_kvm_emulate_insn_start(vcpu); 5361 ++vcpu->stat.insn_emulation; 5362 if (r != EMULATION_OK) { 5363 if (emulation_type & EMULTYPE_TRAP_UD) 5364 return EMULATE_FAIL; 5365 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt, 5366 emulation_type)) 5367 return EMULATE_DONE; 5368 if (emulation_type & EMULTYPE_SKIP) 5369 return EMULATE_FAIL; 5370 return handle_emulation_failure(vcpu); 5371 } 5372 } 5373 5374 if (emulation_type & EMULTYPE_SKIP) { 5375 kvm_rip_write(vcpu, ctxt->_eip); 5376 if (ctxt->eflags & X86_EFLAGS_RF) 5377 kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF); 5378 return EMULATE_DONE; 5379 } 5380 5381 if (retry_instruction(ctxt, cr2, emulation_type)) 5382 return EMULATE_DONE; 5383 5384 /* this is needed for vmware backdoor interface to work since it 5385 changes registers values during IO operation */ 5386 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) { 5387 vcpu->arch.emulate_regs_need_sync_from_vcpu = false; 5388 emulator_invalidate_register_cache(ctxt); 5389 } 5390 5391 restart: 5392 r = x86_emulate_insn(ctxt); 5393 5394 if (r == EMULATION_INTERCEPTED) 5395 return EMULATE_DONE; 5396 5397 if (r == EMULATION_FAILED) { 5398 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt, 5399 emulation_type)) 5400 return EMULATE_DONE; 5401 5402 return handle_emulation_failure(vcpu); 5403 } 5404 5405 if (ctxt->have_exception) { 5406 r = EMULATE_DONE; 5407 if (inject_emulated_exception(vcpu)) 5408 return r; 5409 } else if (vcpu->arch.pio.count) { 5410 if (!vcpu->arch.pio.in) { 5411 /* FIXME: return into emulator if single-stepping. */ 5412 vcpu->arch.pio.count = 0; 5413 } else { 5414 writeback = false; 5415 vcpu->arch.complete_userspace_io = complete_emulated_pio; 5416 } 5417 r = EMULATE_USER_EXIT; 5418 } else if (vcpu->mmio_needed) { 5419 if (!vcpu->mmio_is_write) 5420 writeback = false; 5421 r = EMULATE_USER_EXIT; 5422 vcpu->arch.complete_userspace_io = complete_emulated_mmio; 5423 } else if (r == EMULATION_RESTART) 5424 goto restart; 5425 else 5426 r = EMULATE_DONE; 5427 5428 if (writeback) { 5429 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu); 5430 toggle_interruptibility(vcpu, ctxt->interruptibility); 5431 vcpu->arch.emulate_regs_need_sync_to_vcpu = false; 5432 kvm_rip_write(vcpu, ctxt->eip); 5433 if (r == EMULATE_DONE) 5434 kvm_vcpu_check_singlestep(vcpu, rflags, &r); 5435 if (!ctxt->have_exception || 5436 exception_type(ctxt->exception.vector) == EXCPT_TRAP) 5437 __kvm_set_rflags(vcpu, ctxt->eflags); 5438 5439 /* 5440 * For STI, interrupts are shadowed; so KVM_REQ_EVENT will 5441 * do nothing, and it will be requested again as soon as 5442 * the shadow expires. But we still need to check here, 5443 * because POPF has no interrupt shadow. 5444 */ 5445 if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF)) 5446 kvm_make_request(KVM_REQ_EVENT, vcpu); 5447 } else 5448 vcpu->arch.emulate_regs_need_sync_to_vcpu = true; 5449 5450 return r; 5451 } 5452 EXPORT_SYMBOL_GPL(x86_emulate_instruction); 5453 5454 int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port) 5455 { 5456 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX); 5457 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt, 5458 size, port, &val, 1); 5459 /* do not return to emulator after return from userspace */ 5460 vcpu->arch.pio.count = 0; 5461 return ret; 5462 } 5463 EXPORT_SYMBOL_GPL(kvm_fast_pio_out); 5464 5465 static void tsc_bad(void *info) 5466 { 5467 __this_cpu_write(cpu_tsc_khz, 0); 5468 } 5469 5470 static void tsc_khz_changed(void *data) 5471 { 5472 struct cpufreq_freqs *freq = data; 5473 unsigned long khz = 0; 5474 5475 if (data) 5476 khz = freq->new; 5477 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) 5478 khz = cpufreq_quick_get(raw_smp_processor_id()); 5479 if (!khz) 5480 khz = tsc_khz; 5481 __this_cpu_write(cpu_tsc_khz, khz); 5482 } 5483 5484 static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val, 5485 void *data) 5486 { 5487 struct cpufreq_freqs *freq = data; 5488 struct kvm *kvm; 5489 struct kvm_vcpu *vcpu; 5490 int i, send_ipi = 0; 5491 5492 /* 5493 * We allow guests to temporarily run on slowing clocks, 5494 * provided we notify them after, or to run on accelerating 5495 * clocks, provided we notify them before. Thus time never 5496 * goes backwards. 5497 * 5498 * However, we have a problem. We can't atomically update 5499 * the frequency of a given CPU from this function; it is 5500 * merely a notifier, which can be called from any CPU. 5501 * Changing the TSC frequency at arbitrary points in time 5502 * requires a recomputation of local variables related to 5503 * the TSC for each VCPU. We must flag these local variables 5504 * to be updated and be sure the update takes place with the 5505 * new frequency before any guests proceed. 5506 * 5507 * Unfortunately, the combination of hotplug CPU and frequency 5508 * change creates an intractable locking scenario; the order 5509 * of when these callouts happen is undefined with respect to 5510 * CPU hotplug, and they can race with each other. As such, 5511 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is 5512 * undefined; you can actually have a CPU frequency change take 5513 * place in between the computation of X and the setting of the 5514 * variable. To protect against this problem, all updates of 5515 * the per_cpu tsc_khz variable are done in an interrupt 5516 * protected IPI, and all callers wishing to update the value 5517 * must wait for a synchronous IPI to complete (which is trivial 5518 * if the caller is on the CPU already). This establishes the 5519 * necessary total order on variable updates. 5520 * 5521 * Note that because a guest time update may take place 5522 * anytime after the setting of the VCPU's request bit, the 5523 * correct TSC value must be set before the request. However, 5524 * to ensure the update actually makes it to any guest which 5525 * starts running in hardware virtualization between the set 5526 * and the acquisition of the spinlock, we must also ping the 5527 * CPU after setting the request bit. 5528 * 5529 */ 5530 5531 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new) 5532 return 0; 5533 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new) 5534 return 0; 5535 5536 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1); 5537 5538 spin_lock(&kvm_lock); 5539 list_for_each_entry(kvm, &vm_list, vm_list) { 5540 kvm_for_each_vcpu(i, vcpu, kvm) { 5541 if (vcpu->cpu != freq->cpu) 5542 continue; 5543 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 5544 if (vcpu->cpu != smp_processor_id()) 5545 send_ipi = 1; 5546 } 5547 } 5548 spin_unlock(&kvm_lock); 5549 5550 if (freq->old < freq->new && send_ipi) { 5551 /* 5552 * We upscale the frequency. Must make the guest 5553 * doesn't see old kvmclock values while running with 5554 * the new frequency, otherwise we risk the guest sees 5555 * time go backwards. 5556 * 5557 * In case we update the frequency for another cpu 5558 * (which might be in guest context) send an interrupt 5559 * to kick the cpu out of guest context. Next time 5560 * guest context is entered kvmclock will be updated, 5561 * so the guest will not see stale values. 5562 */ 5563 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1); 5564 } 5565 return 0; 5566 } 5567 5568 static struct notifier_block kvmclock_cpufreq_notifier_block = { 5569 .notifier_call = kvmclock_cpufreq_notifier 5570 }; 5571 5572 static int kvmclock_cpu_notifier(struct notifier_block *nfb, 5573 unsigned long action, void *hcpu) 5574 { 5575 unsigned int cpu = (unsigned long)hcpu; 5576 5577 switch (action) { 5578 case CPU_ONLINE: 5579 case CPU_DOWN_FAILED: 5580 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1); 5581 break; 5582 case CPU_DOWN_PREPARE: 5583 smp_call_function_single(cpu, tsc_bad, NULL, 1); 5584 break; 5585 } 5586 return NOTIFY_OK; 5587 } 5588 5589 static struct notifier_block kvmclock_cpu_notifier_block = { 5590 .notifier_call = kvmclock_cpu_notifier, 5591 .priority = -INT_MAX 5592 }; 5593 5594 static void kvm_timer_init(void) 5595 { 5596 int cpu; 5597 5598 max_tsc_khz = tsc_khz; 5599 5600 cpu_notifier_register_begin(); 5601 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) { 5602 #ifdef CONFIG_CPU_FREQ 5603 struct cpufreq_policy policy; 5604 memset(&policy, 0, sizeof(policy)); 5605 cpu = get_cpu(); 5606 cpufreq_get_policy(&policy, cpu); 5607 if (policy.cpuinfo.max_freq) 5608 max_tsc_khz = policy.cpuinfo.max_freq; 5609 put_cpu(); 5610 #endif 5611 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block, 5612 CPUFREQ_TRANSITION_NOTIFIER); 5613 } 5614 pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz); 5615 for_each_online_cpu(cpu) 5616 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1); 5617 5618 __register_hotcpu_notifier(&kvmclock_cpu_notifier_block); 5619 cpu_notifier_register_done(); 5620 5621 } 5622 5623 static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu); 5624 5625 int kvm_is_in_guest(void) 5626 { 5627 return __this_cpu_read(current_vcpu) != NULL; 5628 } 5629 5630 static int kvm_is_user_mode(void) 5631 { 5632 int user_mode = 3; 5633 5634 if (__this_cpu_read(current_vcpu)) 5635 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu)); 5636 5637 return user_mode != 0; 5638 } 5639 5640 static unsigned long kvm_get_guest_ip(void) 5641 { 5642 unsigned long ip = 0; 5643 5644 if (__this_cpu_read(current_vcpu)) 5645 ip = kvm_rip_read(__this_cpu_read(current_vcpu)); 5646 5647 return ip; 5648 } 5649 5650 static struct perf_guest_info_callbacks kvm_guest_cbs = { 5651 .is_in_guest = kvm_is_in_guest, 5652 .is_user_mode = kvm_is_user_mode, 5653 .get_guest_ip = kvm_get_guest_ip, 5654 }; 5655 5656 void kvm_before_handle_nmi(struct kvm_vcpu *vcpu) 5657 { 5658 __this_cpu_write(current_vcpu, vcpu); 5659 } 5660 EXPORT_SYMBOL_GPL(kvm_before_handle_nmi); 5661 5662 void kvm_after_handle_nmi(struct kvm_vcpu *vcpu) 5663 { 5664 __this_cpu_write(current_vcpu, NULL); 5665 } 5666 EXPORT_SYMBOL_GPL(kvm_after_handle_nmi); 5667 5668 static void kvm_set_mmio_spte_mask(void) 5669 { 5670 u64 mask; 5671 int maxphyaddr = boot_cpu_data.x86_phys_bits; 5672 5673 /* 5674 * Set the reserved bits and the present bit of an paging-structure 5675 * entry to generate page fault with PFER.RSV = 1. 5676 */ 5677 /* Mask the reserved physical address bits. */ 5678 mask = rsvd_bits(maxphyaddr, 51); 5679 5680 /* Bit 62 is always reserved for 32bit host. */ 5681 mask |= 0x3ull << 62; 5682 5683 /* Set the present bit. */ 5684 mask |= 1ull; 5685 5686 #ifdef CONFIG_X86_64 5687 /* 5688 * If reserved bit is not supported, clear the present bit to disable 5689 * mmio page fault. 5690 */ 5691 if (maxphyaddr == 52) 5692 mask &= ~1ull; 5693 #endif 5694 5695 kvm_mmu_set_mmio_spte_mask(mask); 5696 } 5697 5698 #ifdef CONFIG_X86_64 5699 static void pvclock_gtod_update_fn(struct work_struct *work) 5700 { 5701 struct kvm *kvm; 5702 5703 struct kvm_vcpu *vcpu; 5704 int i; 5705 5706 spin_lock(&kvm_lock); 5707 list_for_each_entry(kvm, &vm_list, vm_list) 5708 kvm_for_each_vcpu(i, vcpu, kvm) 5709 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu); 5710 atomic_set(&kvm_guest_has_master_clock, 0); 5711 spin_unlock(&kvm_lock); 5712 } 5713 5714 static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn); 5715 5716 /* 5717 * Notification about pvclock gtod data update. 5718 */ 5719 static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused, 5720 void *priv) 5721 { 5722 struct pvclock_gtod_data *gtod = &pvclock_gtod_data; 5723 struct timekeeper *tk = priv; 5724 5725 update_pvclock_gtod(tk); 5726 5727 /* disable master clock if host does not trust, or does not 5728 * use, TSC clocksource 5729 */ 5730 if (gtod->clock.vclock_mode != VCLOCK_TSC && 5731 atomic_read(&kvm_guest_has_master_clock) != 0) 5732 queue_work(system_long_wq, &pvclock_gtod_work); 5733 5734 return 0; 5735 } 5736 5737 static struct notifier_block pvclock_gtod_notifier = { 5738 .notifier_call = pvclock_gtod_notify, 5739 }; 5740 #endif 5741 5742 int kvm_arch_init(void *opaque) 5743 { 5744 int r; 5745 struct kvm_x86_ops *ops = opaque; 5746 5747 if (kvm_x86_ops) { 5748 printk(KERN_ERR "kvm: already loaded the other module\n"); 5749 r = -EEXIST; 5750 goto out; 5751 } 5752 5753 if (!ops->cpu_has_kvm_support()) { 5754 printk(KERN_ERR "kvm: no hardware support\n"); 5755 r = -EOPNOTSUPP; 5756 goto out; 5757 } 5758 if (ops->disabled_by_bios()) { 5759 printk(KERN_ERR "kvm: disabled by bios\n"); 5760 r = -EOPNOTSUPP; 5761 goto out; 5762 } 5763 5764 r = -ENOMEM; 5765 shared_msrs = alloc_percpu(struct kvm_shared_msrs); 5766 if (!shared_msrs) { 5767 printk(KERN_ERR "kvm: failed to allocate percpu kvm_shared_msrs\n"); 5768 goto out; 5769 } 5770 5771 r = kvm_mmu_module_init(); 5772 if (r) 5773 goto out_free_percpu; 5774 5775 kvm_set_mmio_spte_mask(); 5776 5777 kvm_x86_ops = ops; 5778 kvm_init_msr_list(); 5779 5780 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK, 5781 PT_DIRTY_MASK, PT64_NX_MASK, 0); 5782 5783 kvm_timer_init(); 5784 5785 perf_register_guest_info_callbacks(&kvm_guest_cbs); 5786 5787 if (cpu_has_xsave) 5788 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK); 5789 5790 kvm_lapic_init(); 5791 #ifdef CONFIG_X86_64 5792 pvclock_gtod_register_notifier(&pvclock_gtod_notifier); 5793 #endif 5794 5795 return 0; 5796 5797 out_free_percpu: 5798 free_percpu(shared_msrs); 5799 out: 5800 return r; 5801 } 5802 5803 void kvm_arch_exit(void) 5804 { 5805 perf_unregister_guest_info_callbacks(&kvm_guest_cbs); 5806 5807 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) 5808 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block, 5809 CPUFREQ_TRANSITION_NOTIFIER); 5810 unregister_hotcpu_notifier(&kvmclock_cpu_notifier_block); 5811 #ifdef CONFIG_X86_64 5812 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier); 5813 #endif 5814 kvm_x86_ops = NULL; 5815 kvm_mmu_module_exit(); 5816 free_percpu(shared_msrs); 5817 } 5818 5819 int kvm_emulate_halt(struct kvm_vcpu *vcpu) 5820 { 5821 ++vcpu->stat.halt_exits; 5822 if (irqchip_in_kernel(vcpu->kvm)) { 5823 vcpu->arch.mp_state = KVM_MP_STATE_HALTED; 5824 return 1; 5825 } else { 5826 vcpu->run->exit_reason = KVM_EXIT_HLT; 5827 return 0; 5828 } 5829 } 5830 EXPORT_SYMBOL_GPL(kvm_emulate_halt); 5831 5832 int kvm_hv_hypercall(struct kvm_vcpu *vcpu) 5833 { 5834 u64 param, ingpa, outgpa, ret; 5835 uint16_t code, rep_idx, rep_cnt, res = HV_STATUS_SUCCESS, rep_done = 0; 5836 bool fast, longmode; 5837 5838 /* 5839 * hypercall generates UD from non zero cpl and real mode 5840 * per HYPER-V spec 5841 */ 5842 if (kvm_x86_ops->get_cpl(vcpu) != 0 || !is_protmode(vcpu)) { 5843 kvm_queue_exception(vcpu, UD_VECTOR); 5844 return 0; 5845 } 5846 5847 longmode = is_64_bit_mode(vcpu); 5848 5849 if (!longmode) { 5850 param = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDX) << 32) | 5851 (kvm_register_read(vcpu, VCPU_REGS_RAX) & 0xffffffff); 5852 ingpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RBX) << 32) | 5853 (kvm_register_read(vcpu, VCPU_REGS_RCX) & 0xffffffff); 5854 outgpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDI) << 32) | 5855 (kvm_register_read(vcpu, VCPU_REGS_RSI) & 0xffffffff); 5856 } 5857 #ifdef CONFIG_X86_64 5858 else { 5859 param = kvm_register_read(vcpu, VCPU_REGS_RCX); 5860 ingpa = kvm_register_read(vcpu, VCPU_REGS_RDX); 5861 outgpa = kvm_register_read(vcpu, VCPU_REGS_R8); 5862 } 5863 #endif 5864 5865 code = param & 0xffff; 5866 fast = (param >> 16) & 0x1; 5867 rep_cnt = (param >> 32) & 0xfff; 5868 rep_idx = (param >> 48) & 0xfff; 5869 5870 trace_kvm_hv_hypercall(code, fast, rep_cnt, rep_idx, ingpa, outgpa); 5871 5872 switch (code) { 5873 case HV_X64_HV_NOTIFY_LONG_SPIN_WAIT: 5874 kvm_vcpu_on_spin(vcpu); 5875 break; 5876 default: 5877 res = HV_STATUS_INVALID_HYPERCALL_CODE; 5878 break; 5879 } 5880 5881 ret = res | (((u64)rep_done & 0xfff) << 32); 5882 if (longmode) { 5883 kvm_register_write(vcpu, VCPU_REGS_RAX, ret); 5884 } else { 5885 kvm_register_write(vcpu, VCPU_REGS_RDX, ret >> 32); 5886 kvm_register_write(vcpu, VCPU_REGS_RAX, ret & 0xffffffff); 5887 } 5888 5889 return 1; 5890 } 5891 5892 /* 5893 * kvm_pv_kick_cpu_op: Kick a vcpu. 5894 * 5895 * @apicid - apicid of vcpu to be kicked. 5896 */ 5897 static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid) 5898 { 5899 struct kvm_lapic_irq lapic_irq; 5900 5901 lapic_irq.shorthand = 0; 5902 lapic_irq.dest_mode = 0; 5903 lapic_irq.dest_id = apicid; 5904 5905 lapic_irq.delivery_mode = APIC_DM_REMRD; 5906 kvm_irq_delivery_to_apic(kvm, 0, &lapic_irq, NULL); 5907 } 5908 5909 int kvm_emulate_hypercall(struct kvm_vcpu *vcpu) 5910 { 5911 unsigned long nr, a0, a1, a2, a3, ret; 5912 int op_64_bit, r = 1; 5913 5914 if (kvm_hv_hypercall_enabled(vcpu->kvm)) 5915 return kvm_hv_hypercall(vcpu); 5916 5917 nr = kvm_register_read(vcpu, VCPU_REGS_RAX); 5918 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX); 5919 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX); 5920 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX); 5921 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI); 5922 5923 trace_kvm_hypercall(nr, a0, a1, a2, a3); 5924 5925 op_64_bit = is_64_bit_mode(vcpu); 5926 if (!op_64_bit) { 5927 nr &= 0xFFFFFFFF; 5928 a0 &= 0xFFFFFFFF; 5929 a1 &= 0xFFFFFFFF; 5930 a2 &= 0xFFFFFFFF; 5931 a3 &= 0xFFFFFFFF; 5932 } 5933 5934 if (kvm_x86_ops->get_cpl(vcpu) != 0) { 5935 ret = -KVM_EPERM; 5936 goto out; 5937 } 5938 5939 switch (nr) { 5940 case KVM_HC_VAPIC_POLL_IRQ: 5941 ret = 0; 5942 break; 5943 case KVM_HC_KICK_CPU: 5944 kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1); 5945 ret = 0; 5946 break; 5947 default: 5948 ret = -KVM_ENOSYS; 5949 break; 5950 } 5951 out: 5952 if (!op_64_bit) 5953 ret = (u32)ret; 5954 kvm_register_write(vcpu, VCPU_REGS_RAX, ret); 5955 ++vcpu->stat.hypercalls; 5956 return r; 5957 } 5958 EXPORT_SYMBOL_GPL(kvm_emulate_hypercall); 5959 5960 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt) 5961 { 5962 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 5963 char instruction[3]; 5964 unsigned long rip = kvm_rip_read(vcpu); 5965 5966 kvm_x86_ops->patch_hypercall(vcpu, instruction); 5967 5968 return emulator_write_emulated(ctxt, rip, instruction, 3, NULL); 5969 } 5970 5971 /* 5972 * Check if userspace requested an interrupt window, and that the 5973 * interrupt window is open. 5974 * 5975 * No need to exit to userspace if we already have an interrupt queued. 5976 */ 5977 static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu) 5978 { 5979 return (!irqchip_in_kernel(vcpu->kvm) && !kvm_cpu_has_interrupt(vcpu) && 5980 vcpu->run->request_interrupt_window && 5981 kvm_arch_interrupt_allowed(vcpu)); 5982 } 5983 5984 static void post_kvm_run_save(struct kvm_vcpu *vcpu) 5985 { 5986 struct kvm_run *kvm_run = vcpu->run; 5987 5988 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0; 5989 kvm_run->cr8 = kvm_get_cr8(vcpu); 5990 kvm_run->apic_base = kvm_get_apic_base(vcpu); 5991 if (irqchip_in_kernel(vcpu->kvm)) 5992 kvm_run->ready_for_interrupt_injection = 1; 5993 else 5994 kvm_run->ready_for_interrupt_injection = 5995 kvm_arch_interrupt_allowed(vcpu) && 5996 !kvm_cpu_has_interrupt(vcpu) && 5997 !kvm_event_needs_reinjection(vcpu); 5998 } 5999 6000 static void update_cr8_intercept(struct kvm_vcpu *vcpu) 6001 { 6002 int max_irr, tpr; 6003 6004 if (!kvm_x86_ops->update_cr8_intercept) 6005 return; 6006 6007 if (!vcpu->arch.apic) 6008 return; 6009 6010 if (!vcpu->arch.apic->vapic_addr) 6011 max_irr = kvm_lapic_find_highest_irr(vcpu); 6012 else 6013 max_irr = -1; 6014 6015 if (max_irr != -1) 6016 max_irr >>= 4; 6017 6018 tpr = kvm_lapic_get_cr8(vcpu); 6019 6020 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr); 6021 } 6022 6023 static int inject_pending_event(struct kvm_vcpu *vcpu, bool req_int_win) 6024 { 6025 int r; 6026 6027 /* try to reinject previous events if any */ 6028 if (vcpu->arch.exception.pending) { 6029 trace_kvm_inj_exception(vcpu->arch.exception.nr, 6030 vcpu->arch.exception.has_error_code, 6031 vcpu->arch.exception.error_code); 6032 6033 if (exception_type(vcpu->arch.exception.nr) == EXCPT_FAULT) 6034 __kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) | 6035 X86_EFLAGS_RF); 6036 6037 if (vcpu->arch.exception.nr == DB_VECTOR && 6038 (vcpu->arch.dr7 & DR7_GD)) { 6039 vcpu->arch.dr7 &= ~DR7_GD; 6040 kvm_update_dr7(vcpu); 6041 } 6042 6043 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr, 6044 vcpu->arch.exception.has_error_code, 6045 vcpu->arch.exception.error_code, 6046 vcpu->arch.exception.reinject); 6047 return 0; 6048 } 6049 6050 if (vcpu->arch.nmi_injected) { 6051 kvm_x86_ops->set_nmi(vcpu); 6052 return 0; 6053 } 6054 6055 if (vcpu->arch.interrupt.pending) { 6056 kvm_x86_ops->set_irq(vcpu); 6057 return 0; 6058 } 6059 6060 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) { 6061 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win); 6062 if (r != 0) 6063 return r; 6064 } 6065 6066 /* try to inject new event if pending */ 6067 if (vcpu->arch.nmi_pending) { 6068 if (kvm_x86_ops->nmi_allowed(vcpu)) { 6069 --vcpu->arch.nmi_pending; 6070 vcpu->arch.nmi_injected = true; 6071 kvm_x86_ops->set_nmi(vcpu); 6072 } 6073 } else if (kvm_cpu_has_injectable_intr(vcpu)) { 6074 /* 6075 * Because interrupts can be injected asynchronously, we are 6076 * calling check_nested_events again here to avoid a race condition. 6077 * See https://lkml.org/lkml/2014/7/2/60 for discussion about this 6078 * proposal and current concerns. Perhaps we should be setting 6079 * KVM_REQ_EVENT only on certain events and not unconditionally? 6080 */ 6081 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) { 6082 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win); 6083 if (r != 0) 6084 return r; 6085 } 6086 if (kvm_x86_ops->interrupt_allowed(vcpu)) { 6087 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu), 6088 false); 6089 kvm_x86_ops->set_irq(vcpu); 6090 } 6091 } 6092 return 0; 6093 } 6094 6095 static void process_nmi(struct kvm_vcpu *vcpu) 6096 { 6097 unsigned limit = 2; 6098 6099 /* 6100 * x86 is limited to one NMI running, and one NMI pending after it. 6101 * If an NMI is already in progress, limit further NMIs to just one. 6102 * Otherwise, allow two (and we'll inject the first one immediately). 6103 */ 6104 if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected) 6105 limit = 1; 6106 6107 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0); 6108 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit); 6109 kvm_make_request(KVM_REQ_EVENT, vcpu); 6110 } 6111 6112 static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu) 6113 { 6114 u64 eoi_exit_bitmap[4]; 6115 u32 tmr[8]; 6116 6117 if (!kvm_apic_hw_enabled(vcpu->arch.apic)) 6118 return; 6119 6120 memset(eoi_exit_bitmap, 0, 32); 6121 memset(tmr, 0, 32); 6122 6123 kvm_ioapic_scan_entry(vcpu, eoi_exit_bitmap, tmr); 6124 kvm_x86_ops->load_eoi_exitmap(vcpu, eoi_exit_bitmap); 6125 kvm_apic_update_tmr(vcpu, tmr); 6126 } 6127 6128 static void kvm_vcpu_flush_tlb(struct kvm_vcpu *vcpu) 6129 { 6130 ++vcpu->stat.tlb_flush; 6131 kvm_x86_ops->tlb_flush(vcpu); 6132 } 6133 6134 void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu) 6135 { 6136 struct page *page = NULL; 6137 6138 if (!irqchip_in_kernel(vcpu->kvm)) 6139 return; 6140 6141 if (!kvm_x86_ops->set_apic_access_page_addr) 6142 return; 6143 6144 page = gfn_to_page(vcpu->kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT); 6145 kvm_x86_ops->set_apic_access_page_addr(vcpu, page_to_phys(page)); 6146 6147 /* 6148 * Do not pin apic access page in memory, the MMU notifier 6149 * will call us again if it is migrated or swapped out. 6150 */ 6151 put_page(page); 6152 } 6153 EXPORT_SYMBOL_GPL(kvm_vcpu_reload_apic_access_page); 6154 6155 void kvm_arch_mmu_notifier_invalidate_page(struct kvm *kvm, 6156 unsigned long address) 6157 { 6158 /* 6159 * The physical address of apic access page is stored in the VMCS. 6160 * Update it when it becomes invalid. 6161 */ 6162 if (address == gfn_to_hva(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT)) 6163 kvm_make_all_cpus_request(kvm, KVM_REQ_APIC_PAGE_RELOAD); 6164 } 6165 6166 /* 6167 * Returns 1 to let __vcpu_run() continue the guest execution loop without 6168 * exiting to the userspace. Otherwise, the value will be returned to the 6169 * userspace. 6170 */ 6171 static int vcpu_enter_guest(struct kvm_vcpu *vcpu) 6172 { 6173 int r; 6174 bool req_int_win = !irqchip_in_kernel(vcpu->kvm) && 6175 vcpu->run->request_interrupt_window; 6176 bool req_immediate_exit = false; 6177 6178 if (vcpu->requests) { 6179 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu)) 6180 kvm_mmu_unload(vcpu); 6181 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu)) 6182 __kvm_migrate_timers(vcpu); 6183 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu)) 6184 kvm_gen_update_masterclock(vcpu->kvm); 6185 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu)) 6186 kvm_gen_kvmclock_update(vcpu); 6187 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) { 6188 r = kvm_guest_time_update(vcpu); 6189 if (unlikely(r)) 6190 goto out; 6191 } 6192 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu)) 6193 kvm_mmu_sync_roots(vcpu); 6194 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu)) 6195 kvm_vcpu_flush_tlb(vcpu); 6196 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) { 6197 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS; 6198 r = 0; 6199 goto out; 6200 } 6201 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) { 6202 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN; 6203 r = 0; 6204 goto out; 6205 } 6206 if (kvm_check_request(KVM_REQ_DEACTIVATE_FPU, vcpu)) { 6207 vcpu->fpu_active = 0; 6208 kvm_x86_ops->fpu_deactivate(vcpu); 6209 } 6210 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) { 6211 /* Page is swapped out. Do synthetic halt */ 6212 vcpu->arch.apf.halted = true; 6213 r = 1; 6214 goto out; 6215 } 6216 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu)) 6217 record_steal_time(vcpu); 6218 if (kvm_check_request(KVM_REQ_NMI, vcpu)) 6219 process_nmi(vcpu); 6220 if (kvm_check_request(KVM_REQ_PMU, vcpu)) 6221 kvm_handle_pmu_event(vcpu); 6222 if (kvm_check_request(KVM_REQ_PMI, vcpu)) 6223 kvm_deliver_pmi(vcpu); 6224 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu)) 6225 vcpu_scan_ioapic(vcpu); 6226 if (kvm_check_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu)) 6227 kvm_vcpu_reload_apic_access_page(vcpu); 6228 } 6229 6230 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) { 6231 kvm_apic_accept_events(vcpu); 6232 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) { 6233 r = 1; 6234 goto out; 6235 } 6236 6237 if (inject_pending_event(vcpu, req_int_win) != 0) 6238 req_immediate_exit = true; 6239 /* enable NMI/IRQ window open exits if needed */ 6240 else if (vcpu->arch.nmi_pending) 6241 kvm_x86_ops->enable_nmi_window(vcpu); 6242 else if (kvm_cpu_has_injectable_intr(vcpu) || req_int_win) 6243 kvm_x86_ops->enable_irq_window(vcpu); 6244 6245 if (kvm_lapic_enabled(vcpu)) { 6246 /* 6247 * Update architecture specific hints for APIC 6248 * virtual interrupt delivery. 6249 */ 6250 if (kvm_x86_ops->hwapic_irr_update) 6251 kvm_x86_ops->hwapic_irr_update(vcpu, 6252 kvm_lapic_find_highest_irr(vcpu)); 6253 update_cr8_intercept(vcpu); 6254 kvm_lapic_sync_to_vapic(vcpu); 6255 } 6256 } 6257 6258 r = kvm_mmu_reload(vcpu); 6259 if (unlikely(r)) { 6260 goto cancel_injection; 6261 } 6262 6263 preempt_disable(); 6264 6265 kvm_x86_ops->prepare_guest_switch(vcpu); 6266 if (vcpu->fpu_active) 6267 kvm_load_guest_fpu(vcpu); 6268 kvm_load_guest_xcr0(vcpu); 6269 6270 vcpu->mode = IN_GUEST_MODE; 6271 6272 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx); 6273 6274 /* We should set ->mode before check ->requests, 6275 * see the comment in make_all_cpus_request. 6276 */ 6277 smp_mb__after_srcu_read_unlock(); 6278 6279 local_irq_disable(); 6280 6281 if (vcpu->mode == EXITING_GUEST_MODE || vcpu->requests 6282 || need_resched() || signal_pending(current)) { 6283 vcpu->mode = OUTSIDE_GUEST_MODE; 6284 smp_wmb(); 6285 local_irq_enable(); 6286 preempt_enable(); 6287 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu); 6288 r = 1; 6289 goto cancel_injection; 6290 } 6291 6292 if (req_immediate_exit) 6293 smp_send_reschedule(vcpu->cpu); 6294 6295 kvm_guest_enter(); 6296 6297 if (unlikely(vcpu->arch.switch_db_regs)) { 6298 set_debugreg(0, 7); 6299 set_debugreg(vcpu->arch.eff_db[0], 0); 6300 set_debugreg(vcpu->arch.eff_db[1], 1); 6301 set_debugreg(vcpu->arch.eff_db[2], 2); 6302 set_debugreg(vcpu->arch.eff_db[3], 3); 6303 set_debugreg(vcpu->arch.dr6, 6); 6304 } 6305 6306 trace_kvm_entry(vcpu->vcpu_id); 6307 wait_lapic_expire(vcpu); 6308 kvm_x86_ops->run(vcpu); 6309 6310 /* 6311 * Do this here before restoring debug registers on the host. And 6312 * since we do this before handling the vmexit, a DR access vmexit 6313 * can (a) read the correct value of the debug registers, (b) set 6314 * KVM_DEBUGREG_WONT_EXIT again. 6315 */ 6316 if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) { 6317 int i; 6318 6319 WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP); 6320 kvm_x86_ops->sync_dirty_debug_regs(vcpu); 6321 for (i = 0; i < KVM_NR_DB_REGS; i++) 6322 vcpu->arch.eff_db[i] = vcpu->arch.db[i]; 6323 } 6324 6325 /* 6326 * If the guest has used debug registers, at least dr7 6327 * will be disabled while returning to the host. 6328 * If we don't have active breakpoints in the host, we don't 6329 * care about the messed up debug address registers. But if 6330 * we have some of them active, restore the old state. 6331 */ 6332 if (hw_breakpoint_active()) 6333 hw_breakpoint_restore(); 6334 6335 vcpu->arch.last_guest_tsc = kvm_x86_ops->read_l1_tsc(vcpu, 6336 native_read_tsc()); 6337 6338 vcpu->mode = OUTSIDE_GUEST_MODE; 6339 smp_wmb(); 6340 6341 /* Interrupt is enabled by handle_external_intr() */ 6342 kvm_x86_ops->handle_external_intr(vcpu); 6343 6344 ++vcpu->stat.exits; 6345 6346 /* 6347 * We must have an instruction between local_irq_enable() and 6348 * kvm_guest_exit(), so the timer interrupt isn't delayed by 6349 * the interrupt shadow. The stat.exits increment will do nicely. 6350 * But we need to prevent reordering, hence this barrier(): 6351 */ 6352 barrier(); 6353 6354 kvm_guest_exit(); 6355 6356 preempt_enable(); 6357 6358 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu); 6359 6360 /* 6361 * Profile KVM exit RIPs: 6362 */ 6363 if (unlikely(prof_on == KVM_PROFILING)) { 6364 unsigned long rip = kvm_rip_read(vcpu); 6365 profile_hit(KVM_PROFILING, (void *)rip); 6366 } 6367 6368 if (unlikely(vcpu->arch.tsc_always_catchup)) 6369 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 6370 6371 if (vcpu->arch.apic_attention) 6372 kvm_lapic_sync_from_vapic(vcpu); 6373 6374 r = kvm_x86_ops->handle_exit(vcpu); 6375 return r; 6376 6377 cancel_injection: 6378 kvm_x86_ops->cancel_injection(vcpu); 6379 if (unlikely(vcpu->arch.apic_attention)) 6380 kvm_lapic_sync_from_vapic(vcpu); 6381 out: 6382 return r; 6383 } 6384 6385 6386 static int __vcpu_run(struct kvm_vcpu *vcpu) 6387 { 6388 int r; 6389 struct kvm *kvm = vcpu->kvm; 6390 6391 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu); 6392 6393 r = 1; 6394 while (r > 0) { 6395 if (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE && 6396 !vcpu->arch.apf.halted) 6397 r = vcpu_enter_guest(vcpu); 6398 else { 6399 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx); 6400 kvm_vcpu_block(vcpu); 6401 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu); 6402 if (kvm_check_request(KVM_REQ_UNHALT, vcpu)) { 6403 kvm_apic_accept_events(vcpu); 6404 switch(vcpu->arch.mp_state) { 6405 case KVM_MP_STATE_HALTED: 6406 vcpu->arch.pv.pv_unhalted = false; 6407 vcpu->arch.mp_state = 6408 KVM_MP_STATE_RUNNABLE; 6409 case KVM_MP_STATE_RUNNABLE: 6410 vcpu->arch.apf.halted = false; 6411 break; 6412 case KVM_MP_STATE_INIT_RECEIVED: 6413 break; 6414 default: 6415 r = -EINTR; 6416 break; 6417 } 6418 } 6419 } 6420 6421 if (r <= 0) 6422 break; 6423 6424 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests); 6425 if (kvm_cpu_has_pending_timer(vcpu)) 6426 kvm_inject_pending_timer_irqs(vcpu); 6427 6428 if (dm_request_for_irq_injection(vcpu)) { 6429 r = -EINTR; 6430 vcpu->run->exit_reason = KVM_EXIT_INTR; 6431 ++vcpu->stat.request_irq_exits; 6432 } 6433 6434 kvm_check_async_pf_completion(vcpu); 6435 6436 if (signal_pending(current)) { 6437 r = -EINTR; 6438 vcpu->run->exit_reason = KVM_EXIT_INTR; 6439 ++vcpu->stat.signal_exits; 6440 } 6441 if (need_resched()) { 6442 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx); 6443 cond_resched(); 6444 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu); 6445 } 6446 } 6447 6448 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx); 6449 6450 return r; 6451 } 6452 6453 static inline int complete_emulated_io(struct kvm_vcpu *vcpu) 6454 { 6455 int r; 6456 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu); 6457 r = emulate_instruction(vcpu, EMULTYPE_NO_DECODE); 6458 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx); 6459 if (r != EMULATE_DONE) 6460 return 0; 6461 return 1; 6462 } 6463 6464 static int complete_emulated_pio(struct kvm_vcpu *vcpu) 6465 { 6466 BUG_ON(!vcpu->arch.pio.count); 6467 6468 return complete_emulated_io(vcpu); 6469 } 6470 6471 /* 6472 * Implements the following, as a state machine: 6473 * 6474 * read: 6475 * for each fragment 6476 * for each mmio piece in the fragment 6477 * write gpa, len 6478 * exit 6479 * copy data 6480 * execute insn 6481 * 6482 * write: 6483 * for each fragment 6484 * for each mmio piece in the fragment 6485 * write gpa, len 6486 * copy data 6487 * exit 6488 */ 6489 static int complete_emulated_mmio(struct kvm_vcpu *vcpu) 6490 { 6491 struct kvm_run *run = vcpu->run; 6492 struct kvm_mmio_fragment *frag; 6493 unsigned len; 6494 6495 BUG_ON(!vcpu->mmio_needed); 6496 6497 /* Complete previous fragment */ 6498 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment]; 6499 len = min(8u, frag->len); 6500 if (!vcpu->mmio_is_write) 6501 memcpy(frag->data, run->mmio.data, len); 6502 6503 if (frag->len <= 8) { 6504 /* Switch to the next fragment. */ 6505 frag++; 6506 vcpu->mmio_cur_fragment++; 6507 } else { 6508 /* Go forward to the next mmio piece. */ 6509 frag->data += len; 6510 frag->gpa += len; 6511 frag->len -= len; 6512 } 6513 6514 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) { 6515 vcpu->mmio_needed = 0; 6516 6517 /* FIXME: return into emulator if single-stepping. */ 6518 if (vcpu->mmio_is_write) 6519 return 1; 6520 vcpu->mmio_read_completed = 1; 6521 return complete_emulated_io(vcpu); 6522 } 6523 6524 run->exit_reason = KVM_EXIT_MMIO; 6525 run->mmio.phys_addr = frag->gpa; 6526 if (vcpu->mmio_is_write) 6527 memcpy(run->mmio.data, frag->data, min(8u, frag->len)); 6528 run->mmio.len = min(8u, frag->len); 6529 run->mmio.is_write = vcpu->mmio_is_write; 6530 vcpu->arch.complete_userspace_io = complete_emulated_mmio; 6531 return 0; 6532 } 6533 6534 6535 int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) 6536 { 6537 int r; 6538 sigset_t sigsaved; 6539 6540 if (!tsk_used_math(current) && init_fpu(current)) 6541 return -ENOMEM; 6542 6543 if (vcpu->sigset_active) 6544 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved); 6545 6546 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) { 6547 kvm_vcpu_block(vcpu); 6548 kvm_apic_accept_events(vcpu); 6549 clear_bit(KVM_REQ_UNHALT, &vcpu->requests); 6550 r = -EAGAIN; 6551 goto out; 6552 } 6553 6554 /* re-sync apic's tpr */ 6555 if (!irqchip_in_kernel(vcpu->kvm)) { 6556 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) { 6557 r = -EINVAL; 6558 goto out; 6559 } 6560 } 6561 6562 if (unlikely(vcpu->arch.complete_userspace_io)) { 6563 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io; 6564 vcpu->arch.complete_userspace_io = NULL; 6565 r = cui(vcpu); 6566 if (r <= 0) 6567 goto out; 6568 } else 6569 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed); 6570 6571 r = __vcpu_run(vcpu); 6572 6573 out: 6574 post_kvm_run_save(vcpu); 6575 if (vcpu->sigset_active) 6576 sigprocmask(SIG_SETMASK, &sigsaved, NULL); 6577 6578 return r; 6579 } 6580 6581 int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) 6582 { 6583 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) { 6584 /* 6585 * We are here if userspace calls get_regs() in the middle of 6586 * instruction emulation. Registers state needs to be copied 6587 * back from emulation context to vcpu. Userspace shouldn't do 6588 * that usually, but some bad designed PV devices (vmware 6589 * backdoor interface) need this to work 6590 */ 6591 emulator_writeback_register_cache(&vcpu->arch.emulate_ctxt); 6592 vcpu->arch.emulate_regs_need_sync_to_vcpu = false; 6593 } 6594 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX); 6595 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX); 6596 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX); 6597 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX); 6598 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI); 6599 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI); 6600 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP); 6601 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP); 6602 #ifdef CONFIG_X86_64 6603 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8); 6604 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9); 6605 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10); 6606 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11); 6607 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12); 6608 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13); 6609 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14); 6610 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15); 6611 #endif 6612 6613 regs->rip = kvm_rip_read(vcpu); 6614 regs->rflags = kvm_get_rflags(vcpu); 6615 6616 return 0; 6617 } 6618 6619 int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) 6620 { 6621 vcpu->arch.emulate_regs_need_sync_from_vcpu = true; 6622 vcpu->arch.emulate_regs_need_sync_to_vcpu = false; 6623 6624 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax); 6625 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx); 6626 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx); 6627 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx); 6628 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi); 6629 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi); 6630 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp); 6631 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp); 6632 #ifdef CONFIG_X86_64 6633 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8); 6634 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9); 6635 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10); 6636 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11); 6637 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12); 6638 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13); 6639 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14); 6640 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15); 6641 #endif 6642 6643 kvm_rip_write(vcpu, regs->rip); 6644 kvm_set_rflags(vcpu, regs->rflags); 6645 6646 vcpu->arch.exception.pending = false; 6647 6648 kvm_make_request(KVM_REQ_EVENT, vcpu); 6649 6650 return 0; 6651 } 6652 6653 void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l) 6654 { 6655 struct kvm_segment cs; 6656 6657 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS); 6658 *db = cs.db; 6659 *l = cs.l; 6660 } 6661 EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits); 6662 6663 int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu, 6664 struct kvm_sregs *sregs) 6665 { 6666 struct desc_ptr dt; 6667 6668 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS); 6669 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS); 6670 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES); 6671 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS); 6672 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS); 6673 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS); 6674 6675 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR); 6676 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR); 6677 6678 kvm_x86_ops->get_idt(vcpu, &dt); 6679 sregs->idt.limit = dt.size; 6680 sregs->idt.base = dt.address; 6681 kvm_x86_ops->get_gdt(vcpu, &dt); 6682 sregs->gdt.limit = dt.size; 6683 sregs->gdt.base = dt.address; 6684 6685 sregs->cr0 = kvm_read_cr0(vcpu); 6686 sregs->cr2 = vcpu->arch.cr2; 6687 sregs->cr3 = kvm_read_cr3(vcpu); 6688 sregs->cr4 = kvm_read_cr4(vcpu); 6689 sregs->cr8 = kvm_get_cr8(vcpu); 6690 sregs->efer = vcpu->arch.efer; 6691 sregs->apic_base = kvm_get_apic_base(vcpu); 6692 6693 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap); 6694 6695 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft) 6696 set_bit(vcpu->arch.interrupt.nr, 6697 (unsigned long *)sregs->interrupt_bitmap); 6698 6699 return 0; 6700 } 6701 6702 int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu, 6703 struct kvm_mp_state *mp_state) 6704 { 6705 kvm_apic_accept_events(vcpu); 6706 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED && 6707 vcpu->arch.pv.pv_unhalted) 6708 mp_state->mp_state = KVM_MP_STATE_RUNNABLE; 6709 else 6710 mp_state->mp_state = vcpu->arch.mp_state; 6711 6712 return 0; 6713 } 6714 6715 int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu, 6716 struct kvm_mp_state *mp_state) 6717 { 6718 if (!kvm_vcpu_has_lapic(vcpu) && 6719 mp_state->mp_state != KVM_MP_STATE_RUNNABLE) 6720 return -EINVAL; 6721 6722 if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) { 6723 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED; 6724 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events); 6725 } else 6726 vcpu->arch.mp_state = mp_state->mp_state; 6727 kvm_make_request(KVM_REQ_EVENT, vcpu); 6728 return 0; 6729 } 6730 6731 int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index, 6732 int reason, bool has_error_code, u32 error_code) 6733 { 6734 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt; 6735 int ret; 6736 6737 init_emulate_ctxt(vcpu); 6738 6739 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason, 6740 has_error_code, error_code); 6741 6742 if (ret) 6743 return EMULATE_FAIL; 6744 6745 kvm_rip_write(vcpu, ctxt->eip); 6746 kvm_set_rflags(vcpu, ctxt->eflags); 6747 kvm_make_request(KVM_REQ_EVENT, vcpu); 6748 return EMULATE_DONE; 6749 } 6750 EXPORT_SYMBOL_GPL(kvm_task_switch); 6751 6752 int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu, 6753 struct kvm_sregs *sregs) 6754 { 6755 struct msr_data apic_base_msr; 6756 int mmu_reset_needed = 0; 6757 int pending_vec, max_bits, idx; 6758 struct desc_ptr dt; 6759 6760 if (!guest_cpuid_has_xsave(vcpu) && (sregs->cr4 & X86_CR4_OSXSAVE)) 6761 return -EINVAL; 6762 6763 dt.size = sregs->idt.limit; 6764 dt.address = sregs->idt.base; 6765 kvm_x86_ops->set_idt(vcpu, &dt); 6766 dt.size = sregs->gdt.limit; 6767 dt.address = sregs->gdt.base; 6768 kvm_x86_ops->set_gdt(vcpu, &dt); 6769 6770 vcpu->arch.cr2 = sregs->cr2; 6771 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3; 6772 vcpu->arch.cr3 = sregs->cr3; 6773 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail); 6774 6775 kvm_set_cr8(vcpu, sregs->cr8); 6776 6777 mmu_reset_needed |= vcpu->arch.efer != sregs->efer; 6778 kvm_x86_ops->set_efer(vcpu, sregs->efer); 6779 apic_base_msr.data = sregs->apic_base; 6780 apic_base_msr.host_initiated = true; 6781 kvm_set_apic_base(vcpu, &apic_base_msr); 6782 6783 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0; 6784 kvm_x86_ops->set_cr0(vcpu, sregs->cr0); 6785 vcpu->arch.cr0 = sregs->cr0; 6786 6787 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4; 6788 kvm_x86_ops->set_cr4(vcpu, sregs->cr4); 6789 if (sregs->cr4 & X86_CR4_OSXSAVE) 6790 kvm_update_cpuid(vcpu); 6791 6792 idx = srcu_read_lock(&vcpu->kvm->srcu); 6793 if (!is_long_mode(vcpu) && is_pae(vcpu)) { 6794 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu)); 6795 mmu_reset_needed = 1; 6796 } 6797 srcu_read_unlock(&vcpu->kvm->srcu, idx); 6798 6799 if (mmu_reset_needed) 6800 kvm_mmu_reset_context(vcpu); 6801 6802 max_bits = KVM_NR_INTERRUPTS; 6803 pending_vec = find_first_bit( 6804 (const unsigned long *)sregs->interrupt_bitmap, max_bits); 6805 if (pending_vec < max_bits) { 6806 kvm_queue_interrupt(vcpu, pending_vec, false); 6807 pr_debug("Set back pending irq %d\n", pending_vec); 6808 } 6809 6810 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS); 6811 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS); 6812 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES); 6813 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS); 6814 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS); 6815 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS); 6816 6817 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR); 6818 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR); 6819 6820 update_cr8_intercept(vcpu); 6821 6822 /* Older userspace won't unhalt the vcpu on reset. */ 6823 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 && 6824 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 && 6825 !is_protmode(vcpu)) 6826 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; 6827 6828 kvm_make_request(KVM_REQ_EVENT, vcpu); 6829 6830 return 0; 6831 } 6832 6833 int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu, 6834 struct kvm_guest_debug *dbg) 6835 { 6836 unsigned long rflags; 6837 int i, r; 6838 6839 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) { 6840 r = -EBUSY; 6841 if (vcpu->arch.exception.pending) 6842 goto out; 6843 if (dbg->control & KVM_GUESTDBG_INJECT_DB) 6844 kvm_queue_exception(vcpu, DB_VECTOR); 6845 else 6846 kvm_queue_exception(vcpu, BP_VECTOR); 6847 } 6848 6849 /* 6850 * Read rflags as long as potentially injected trace flags are still 6851 * filtered out. 6852 */ 6853 rflags = kvm_get_rflags(vcpu); 6854 6855 vcpu->guest_debug = dbg->control; 6856 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE)) 6857 vcpu->guest_debug = 0; 6858 6859 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) { 6860 for (i = 0; i < KVM_NR_DB_REGS; ++i) 6861 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i]; 6862 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7]; 6863 } else { 6864 for (i = 0; i < KVM_NR_DB_REGS; i++) 6865 vcpu->arch.eff_db[i] = vcpu->arch.db[i]; 6866 } 6867 kvm_update_dr7(vcpu); 6868 6869 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) 6870 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) + 6871 get_segment_base(vcpu, VCPU_SREG_CS); 6872 6873 /* 6874 * Trigger an rflags update that will inject or remove the trace 6875 * flags. 6876 */ 6877 kvm_set_rflags(vcpu, rflags); 6878 6879 kvm_x86_ops->update_db_bp_intercept(vcpu); 6880 6881 r = 0; 6882 6883 out: 6884 6885 return r; 6886 } 6887 6888 /* 6889 * Translate a guest virtual address to a guest physical address. 6890 */ 6891 int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu, 6892 struct kvm_translation *tr) 6893 { 6894 unsigned long vaddr = tr->linear_address; 6895 gpa_t gpa; 6896 int idx; 6897 6898 idx = srcu_read_lock(&vcpu->kvm->srcu); 6899 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL); 6900 srcu_read_unlock(&vcpu->kvm->srcu, idx); 6901 tr->physical_address = gpa; 6902 tr->valid = gpa != UNMAPPED_GVA; 6903 tr->writeable = 1; 6904 tr->usermode = 0; 6905 6906 return 0; 6907 } 6908 6909 int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu) 6910 { 6911 struct i387_fxsave_struct *fxsave = 6912 &vcpu->arch.guest_fpu.state->fxsave; 6913 6914 memcpy(fpu->fpr, fxsave->st_space, 128); 6915 fpu->fcw = fxsave->cwd; 6916 fpu->fsw = fxsave->swd; 6917 fpu->ftwx = fxsave->twd; 6918 fpu->last_opcode = fxsave->fop; 6919 fpu->last_ip = fxsave->rip; 6920 fpu->last_dp = fxsave->rdp; 6921 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space); 6922 6923 return 0; 6924 } 6925 6926 int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu) 6927 { 6928 struct i387_fxsave_struct *fxsave = 6929 &vcpu->arch.guest_fpu.state->fxsave; 6930 6931 memcpy(fxsave->st_space, fpu->fpr, 128); 6932 fxsave->cwd = fpu->fcw; 6933 fxsave->swd = fpu->fsw; 6934 fxsave->twd = fpu->ftwx; 6935 fxsave->fop = fpu->last_opcode; 6936 fxsave->rip = fpu->last_ip; 6937 fxsave->rdp = fpu->last_dp; 6938 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space); 6939 6940 return 0; 6941 } 6942 6943 int fx_init(struct kvm_vcpu *vcpu) 6944 { 6945 int err; 6946 6947 err = fpu_alloc(&vcpu->arch.guest_fpu); 6948 if (err) 6949 return err; 6950 6951 fpu_finit(&vcpu->arch.guest_fpu); 6952 if (cpu_has_xsaves) 6953 vcpu->arch.guest_fpu.state->xsave.xsave_hdr.xcomp_bv = 6954 host_xcr0 | XSTATE_COMPACTION_ENABLED; 6955 6956 /* 6957 * Ensure guest xcr0 is valid for loading 6958 */ 6959 vcpu->arch.xcr0 = XSTATE_FP; 6960 6961 vcpu->arch.cr0 |= X86_CR0_ET; 6962 6963 return 0; 6964 } 6965 EXPORT_SYMBOL_GPL(fx_init); 6966 6967 static void fx_free(struct kvm_vcpu *vcpu) 6968 { 6969 fpu_free(&vcpu->arch.guest_fpu); 6970 } 6971 6972 void kvm_load_guest_fpu(struct kvm_vcpu *vcpu) 6973 { 6974 if (vcpu->guest_fpu_loaded) 6975 return; 6976 6977 /* 6978 * Restore all possible states in the guest, 6979 * and assume host would use all available bits. 6980 * Guest xcr0 would be loaded later. 6981 */ 6982 kvm_put_guest_xcr0(vcpu); 6983 vcpu->guest_fpu_loaded = 1; 6984 __kernel_fpu_begin(); 6985 fpu_restore_checking(&vcpu->arch.guest_fpu); 6986 trace_kvm_fpu(1); 6987 } 6988 6989 void kvm_put_guest_fpu(struct kvm_vcpu *vcpu) 6990 { 6991 kvm_put_guest_xcr0(vcpu); 6992 6993 if (!vcpu->guest_fpu_loaded) 6994 return; 6995 6996 vcpu->guest_fpu_loaded = 0; 6997 fpu_save_init(&vcpu->arch.guest_fpu); 6998 __kernel_fpu_end(); 6999 ++vcpu->stat.fpu_reload; 7000 kvm_make_request(KVM_REQ_DEACTIVATE_FPU, vcpu); 7001 trace_kvm_fpu(0); 7002 } 7003 7004 void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu) 7005 { 7006 kvmclock_reset(vcpu); 7007 7008 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask); 7009 fx_free(vcpu); 7010 kvm_x86_ops->vcpu_free(vcpu); 7011 } 7012 7013 struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm, 7014 unsigned int id) 7015 { 7016 if (check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0) 7017 printk_once(KERN_WARNING 7018 "kvm: SMP vm created on host with unstable TSC; " 7019 "guest TSC will not be reliable\n"); 7020 return kvm_x86_ops->vcpu_create(kvm, id); 7021 } 7022 7023 int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu) 7024 { 7025 int r; 7026 7027 vcpu->arch.mtrr_state.have_fixed = 1; 7028 r = vcpu_load(vcpu); 7029 if (r) 7030 return r; 7031 kvm_vcpu_reset(vcpu); 7032 kvm_mmu_setup(vcpu); 7033 vcpu_put(vcpu); 7034 7035 return r; 7036 } 7037 7038 void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu) 7039 { 7040 struct msr_data msr; 7041 struct kvm *kvm = vcpu->kvm; 7042 7043 if (vcpu_load(vcpu)) 7044 return; 7045 msr.data = 0x0; 7046 msr.index = MSR_IA32_TSC; 7047 msr.host_initiated = true; 7048 kvm_write_tsc(vcpu, &msr); 7049 vcpu_put(vcpu); 7050 7051 schedule_delayed_work(&kvm->arch.kvmclock_sync_work, 7052 KVMCLOCK_SYNC_PERIOD); 7053 } 7054 7055 void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu) 7056 { 7057 int r; 7058 vcpu->arch.apf.msr_val = 0; 7059 7060 r = vcpu_load(vcpu); 7061 BUG_ON(r); 7062 kvm_mmu_unload(vcpu); 7063 vcpu_put(vcpu); 7064 7065 fx_free(vcpu); 7066 kvm_x86_ops->vcpu_free(vcpu); 7067 } 7068 7069 void kvm_vcpu_reset(struct kvm_vcpu *vcpu) 7070 { 7071 atomic_set(&vcpu->arch.nmi_queued, 0); 7072 vcpu->arch.nmi_pending = 0; 7073 vcpu->arch.nmi_injected = false; 7074 kvm_clear_interrupt_queue(vcpu); 7075 kvm_clear_exception_queue(vcpu); 7076 7077 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db)); 7078 vcpu->arch.dr6 = DR6_INIT; 7079 kvm_update_dr6(vcpu); 7080 vcpu->arch.dr7 = DR7_FIXED_1; 7081 kvm_update_dr7(vcpu); 7082 7083 kvm_make_request(KVM_REQ_EVENT, vcpu); 7084 vcpu->arch.apf.msr_val = 0; 7085 vcpu->arch.st.msr_val = 0; 7086 7087 kvmclock_reset(vcpu); 7088 7089 kvm_clear_async_pf_completion_queue(vcpu); 7090 kvm_async_pf_hash_reset(vcpu); 7091 vcpu->arch.apf.halted = false; 7092 7093 kvm_pmu_reset(vcpu); 7094 7095 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs)); 7096 vcpu->arch.regs_avail = ~0; 7097 vcpu->arch.regs_dirty = ~0; 7098 7099 kvm_x86_ops->vcpu_reset(vcpu); 7100 } 7101 7102 void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector) 7103 { 7104 struct kvm_segment cs; 7105 7106 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS); 7107 cs.selector = vector << 8; 7108 cs.base = vector << 12; 7109 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS); 7110 kvm_rip_write(vcpu, 0); 7111 } 7112 7113 int kvm_arch_hardware_enable(void) 7114 { 7115 struct kvm *kvm; 7116 struct kvm_vcpu *vcpu; 7117 int i; 7118 int ret; 7119 u64 local_tsc; 7120 u64 max_tsc = 0; 7121 bool stable, backwards_tsc = false; 7122 7123 kvm_shared_msr_cpu_online(); 7124 ret = kvm_x86_ops->hardware_enable(); 7125 if (ret != 0) 7126 return ret; 7127 7128 local_tsc = native_read_tsc(); 7129 stable = !check_tsc_unstable(); 7130 list_for_each_entry(kvm, &vm_list, vm_list) { 7131 kvm_for_each_vcpu(i, vcpu, kvm) { 7132 if (!stable && vcpu->cpu == smp_processor_id()) 7133 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 7134 if (stable && vcpu->arch.last_host_tsc > local_tsc) { 7135 backwards_tsc = true; 7136 if (vcpu->arch.last_host_tsc > max_tsc) 7137 max_tsc = vcpu->arch.last_host_tsc; 7138 } 7139 } 7140 } 7141 7142 /* 7143 * Sometimes, even reliable TSCs go backwards. This happens on 7144 * platforms that reset TSC during suspend or hibernate actions, but 7145 * maintain synchronization. We must compensate. Fortunately, we can 7146 * detect that condition here, which happens early in CPU bringup, 7147 * before any KVM threads can be running. Unfortunately, we can't 7148 * bring the TSCs fully up to date with real time, as we aren't yet far 7149 * enough into CPU bringup that we know how much real time has actually 7150 * elapsed; our helper function, get_kernel_ns() will be using boot 7151 * variables that haven't been updated yet. 7152 * 7153 * So we simply find the maximum observed TSC above, then record the 7154 * adjustment to TSC in each VCPU. When the VCPU later gets loaded, 7155 * the adjustment will be applied. Note that we accumulate 7156 * adjustments, in case multiple suspend cycles happen before some VCPU 7157 * gets a chance to run again. In the event that no KVM threads get a 7158 * chance to run, we will miss the entire elapsed period, as we'll have 7159 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may 7160 * loose cycle time. This isn't too big a deal, since the loss will be 7161 * uniform across all VCPUs (not to mention the scenario is extremely 7162 * unlikely). It is possible that a second hibernate recovery happens 7163 * much faster than a first, causing the observed TSC here to be 7164 * smaller; this would require additional padding adjustment, which is 7165 * why we set last_host_tsc to the local tsc observed here. 7166 * 7167 * N.B. - this code below runs only on platforms with reliable TSC, 7168 * as that is the only way backwards_tsc is set above. Also note 7169 * that this runs for ALL vcpus, which is not a bug; all VCPUs should 7170 * have the same delta_cyc adjustment applied if backwards_tsc 7171 * is detected. Note further, this adjustment is only done once, 7172 * as we reset last_host_tsc on all VCPUs to stop this from being 7173 * called multiple times (one for each physical CPU bringup). 7174 * 7175 * Platforms with unreliable TSCs don't have to deal with this, they 7176 * will be compensated by the logic in vcpu_load, which sets the TSC to 7177 * catchup mode. This will catchup all VCPUs to real time, but cannot 7178 * guarantee that they stay in perfect synchronization. 7179 */ 7180 if (backwards_tsc) { 7181 u64 delta_cyc = max_tsc - local_tsc; 7182 backwards_tsc_observed = true; 7183 list_for_each_entry(kvm, &vm_list, vm_list) { 7184 kvm_for_each_vcpu(i, vcpu, kvm) { 7185 vcpu->arch.tsc_offset_adjustment += delta_cyc; 7186 vcpu->arch.last_host_tsc = local_tsc; 7187 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu); 7188 } 7189 7190 /* 7191 * We have to disable TSC offset matching.. if you were 7192 * booting a VM while issuing an S4 host suspend.... 7193 * you may have some problem. Solving this issue is 7194 * left as an exercise to the reader. 7195 */ 7196 kvm->arch.last_tsc_nsec = 0; 7197 kvm->arch.last_tsc_write = 0; 7198 } 7199 7200 } 7201 return 0; 7202 } 7203 7204 void kvm_arch_hardware_disable(void) 7205 { 7206 kvm_x86_ops->hardware_disable(); 7207 drop_user_return_notifiers(); 7208 } 7209 7210 int kvm_arch_hardware_setup(void) 7211 { 7212 return kvm_x86_ops->hardware_setup(); 7213 } 7214 7215 void kvm_arch_hardware_unsetup(void) 7216 { 7217 kvm_x86_ops->hardware_unsetup(); 7218 } 7219 7220 void kvm_arch_check_processor_compat(void *rtn) 7221 { 7222 kvm_x86_ops->check_processor_compatibility(rtn); 7223 } 7224 7225 bool kvm_vcpu_compatible(struct kvm_vcpu *vcpu) 7226 { 7227 return irqchip_in_kernel(vcpu->kvm) == (vcpu->arch.apic != NULL); 7228 } 7229 7230 struct static_key kvm_no_apic_vcpu __read_mostly; 7231 7232 int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu) 7233 { 7234 struct page *page; 7235 struct kvm *kvm; 7236 int r; 7237 7238 BUG_ON(vcpu->kvm == NULL); 7239 kvm = vcpu->kvm; 7240 7241 vcpu->arch.pv.pv_unhalted = false; 7242 vcpu->arch.emulate_ctxt.ops = &emulate_ops; 7243 if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_bsp(vcpu)) 7244 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; 7245 else 7246 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED; 7247 7248 page = alloc_page(GFP_KERNEL | __GFP_ZERO); 7249 if (!page) { 7250 r = -ENOMEM; 7251 goto fail; 7252 } 7253 vcpu->arch.pio_data = page_address(page); 7254 7255 kvm_set_tsc_khz(vcpu, max_tsc_khz); 7256 7257 r = kvm_mmu_create(vcpu); 7258 if (r < 0) 7259 goto fail_free_pio_data; 7260 7261 if (irqchip_in_kernel(kvm)) { 7262 r = kvm_create_lapic(vcpu); 7263 if (r < 0) 7264 goto fail_mmu_destroy; 7265 } else 7266 static_key_slow_inc(&kvm_no_apic_vcpu); 7267 7268 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4, 7269 GFP_KERNEL); 7270 if (!vcpu->arch.mce_banks) { 7271 r = -ENOMEM; 7272 goto fail_free_lapic; 7273 } 7274 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS; 7275 7276 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL)) { 7277 r = -ENOMEM; 7278 goto fail_free_mce_banks; 7279 } 7280 7281 r = fx_init(vcpu); 7282 if (r) 7283 goto fail_free_wbinvd_dirty_mask; 7284 7285 vcpu->arch.ia32_tsc_adjust_msr = 0x0; 7286 vcpu->arch.pv_time_enabled = false; 7287 7288 vcpu->arch.guest_supported_xcr0 = 0; 7289 vcpu->arch.guest_xstate_size = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET; 7290 7291 kvm_async_pf_hash_reset(vcpu); 7292 kvm_pmu_init(vcpu); 7293 7294 return 0; 7295 fail_free_wbinvd_dirty_mask: 7296 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask); 7297 fail_free_mce_banks: 7298 kfree(vcpu->arch.mce_banks); 7299 fail_free_lapic: 7300 kvm_free_lapic(vcpu); 7301 fail_mmu_destroy: 7302 kvm_mmu_destroy(vcpu); 7303 fail_free_pio_data: 7304 free_page((unsigned long)vcpu->arch.pio_data); 7305 fail: 7306 return r; 7307 } 7308 7309 void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu) 7310 { 7311 int idx; 7312 7313 kvm_pmu_destroy(vcpu); 7314 kfree(vcpu->arch.mce_banks); 7315 kvm_free_lapic(vcpu); 7316 idx = srcu_read_lock(&vcpu->kvm->srcu); 7317 kvm_mmu_destroy(vcpu); 7318 srcu_read_unlock(&vcpu->kvm->srcu, idx); 7319 free_page((unsigned long)vcpu->arch.pio_data); 7320 if (!irqchip_in_kernel(vcpu->kvm)) 7321 static_key_slow_dec(&kvm_no_apic_vcpu); 7322 } 7323 7324 void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu) 7325 { 7326 kvm_x86_ops->sched_in(vcpu, cpu); 7327 } 7328 7329 int kvm_arch_init_vm(struct kvm *kvm, unsigned long type) 7330 { 7331 if (type) 7332 return -EINVAL; 7333 7334 INIT_HLIST_HEAD(&kvm->arch.mask_notifier_list); 7335 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages); 7336 INIT_LIST_HEAD(&kvm->arch.zapped_obsolete_pages); 7337 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head); 7338 atomic_set(&kvm->arch.noncoherent_dma_count, 0); 7339 7340 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */ 7341 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap); 7342 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */ 7343 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID, 7344 &kvm->arch.irq_sources_bitmap); 7345 7346 raw_spin_lock_init(&kvm->arch.tsc_write_lock); 7347 mutex_init(&kvm->arch.apic_map_lock); 7348 spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock); 7349 7350 pvclock_update_vm_gtod_copy(kvm); 7351 7352 INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn); 7353 INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn); 7354 7355 return 0; 7356 } 7357 7358 static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu) 7359 { 7360 int r; 7361 r = vcpu_load(vcpu); 7362 BUG_ON(r); 7363 kvm_mmu_unload(vcpu); 7364 vcpu_put(vcpu); 7365 } 7366 7367 static void kvm_free_vcpus(struct kvm *kvm) 7368 { 7369 unsigned int i; 7370 struct kvm_vcpu *vcpu; 7371 7372 /* 7373 * Unpin any mmu pages first. 7374 */ 7375 kvm_for_each_vcpu(i, vcpu, kvm) { 7376 kvm_clear_async_pf_completion_queue(vcpu); 7377 kvm_unload_vcpu_mmu(vcpu); 7378 } 7379 kvm_for_each_vcpu(i, vcpu, kvm) 7380 kvm_arch_vcpu_free(vcpu); 7381 7382 mutex_lock(&kvm->lock); 7383 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++) 7384 kvm->vcpus[i] = NULL; 7385 7386 atomic_set(&kvm->online_vcpus, 0); 7387 mutex_unlock(&kvm->lock); 7388 } 7389 7390 void kvm_arch_sync_events(struct kvm *kvm) 7391 { 7392 cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work); 7393 cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work); 7394 kvm_free_all_assigned_devices(kvm); 7395 kvm_free_pit(kvm); 7396 } 7397 7398 void kvm_arch_destroy_vm(struct kvm *kvm) 7399 { 7400 if (current->mm == kvm->mm) { 7401 /* 7402 * Free memory regions allocated on behalf of userspace, 7403 * unless the the memory map has changed due to process exit 7404 * or fd copying. 7405 */ 7406 struct kvm_userspace_memory_region mem; 7407 memset(&mem, 0, sizeof(mem)); 7408 mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT; 7409 kvm_set_memory_region(kvm, &mem); 7410 7411 mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT; 7412 kvm_set_memory_region(kvm, &mem); 7413 7414 mem.slot = TSS_PRIVATE_MEMSLOT; 7415 kvm_set_memory_region(kvm, &mem); 7416 } 7417 kvm_iommu_unmap_guest(kvm); 7418 kfree(kvm->arch.vpic); 7419 kfree(kvm->arch.vioapic); 7420 kvm_free_vcpus(kvm); 7421 kfree(rcu_dereference_check(kvm->arch.apic_map, 1)); 7422 } 7423 7424 void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *free, 7425 struct kvm_memory_slot *dont) 7426 { 7427 int i; 7428 7429 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) { 7430 if (!dont || free->arch.rmap[i] != dont->arch.rmap[i]) { 7431 kvm_kvfree(free->arch.rmap[i]); 7432 free->arch.rmap[i] = NULL; 7433 } 7434 if (i == 0) 7435 continue; 7436 7437 if (!dont || free->arch.lpage_info[i - 1] != 7438 dont->arch.lpage_info[i - 1]) { 7439 kvm_kvfree(free->arch.lpage_info[i - 1]); 7440 free->arch.lpage_info[i - 1] = NULL; 7441 } 7442 } 7443 } 7444 7445 int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot, 7446 unsigned long npages) 7447 { 7448 int i; 7449 7450 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) { 7451 unsigned long ugfn; 7452 int lpages; 7453 int level = i + 1; 7454 7455 lpages = gfn_to_index(slot->base_gfn + npages - 1, 7456 slot->base_gfn, level) + 1; 7457 7458 slot->arch.rmap[i] = 7459 kvm_kvzalloc(lpages * sizeof(*slot->arch.rmap[i])); 7460 if (!slot->arch.rmap[i]) 7461 goto out_free; 7462 if (i == 0) 7463 continue; 7464 7465 slot->arch.lpage_info[i - 1] = kvm_kvzalloc(lpages * 7466 sizeof(*slot->arch.lpage_info[i - 1])); 7467 if (!slot->arch.lpage_info[i - 1]) 7468 goto out_free; 7469 7470 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1)) 7471 slot->arch.lpage_info[i - 1][0].write_count = 1; 7472 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1)) 7473 slot->arch.lpage_info[i - 1][lpages - 1].write_count = 1; 7474 ugfn = slot->userspace_addr >> PAGE_SHIFT; 7475 /* 7476 * If the gfn and userspace address are not aligned wrt each 7477 * other, or if explicitly asked to, disable large page 7478 * support for this slot 7479 */ 7480 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) || 7481 !kvm_largepages_enabled()) { 7482 unsigned long j; 7483 7484 for (j = 0; j < lpages; ++j) 7485 slot->arch.lpage_info[i - 1][j].write_count = 1; 7486 } 7487 } 7488 7489 return 0; 7490 7491 out_free: 7492 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) { 7493 kvm_kvfree(slot->arch.rmap[i]); 7494 slot->arch.rmap[i] = NULL; 7495 if (i == 0) 7496 continue; 7497 7498 kvm_kvfree(slot->arch.lpage_info[i - 1]); 7499 slot->arch.lpage_info[i - 1] = NULL; 7500 } 7501 return -ENOMEM; 7502 } 7503 7504 void kvm_arch_memslots_updated(struct kvm *kvm) 7505 { 7506 /* 7507 * memslots->generation has been incremented. 7508 * mmio generation may have reached its maximum value. 7509 */ 7510 kvm_mmu_invalidate_mmio_sptes(kvm); 7511 } 7512 7513 int kvm_arch_prepare_memory_region(struct kvm *kvm, 7514 struct kvm_memory_slot *memslot, 7515 struct kvm_userspace_memory_region *mem, 7516 enum kvm_mr_change change) 7517 { 7518 /* 7519 * Only private memory slots need to be mapped here since 7520 * KVM_SET_MEMORY_REGION ioctl is no longer supported. 7521 */ 7522 if ((memslot->id >= KVM_USER_MEM_SLOTS) && (change == KVM_MR_CREATE)) { 7523 unsigned long userspace_addr; 7524 7525 /* 7526 * MAP_SHARED to prevent internal slot pages from being moved 7527 * by fork()/COW. 7528 */ 7529 userspace_addr = vm_mmap(NULL, 0, memslot->npages * PAGE_SIZE, 7530 PROT_READ | PROT_WRITE, 7531 MAP_SHARED | MAP_ANONYMOUS, 0); 7532 7533 if (IS_ERR((void *)userspace_addr)) 7534 return PTR_ERR((void *)userspace_addr); 7535 7536 memslot->userspace_addr = userspace_addr; 7537 } 7538 7539 return 0; 7540 } 7541 7542 static void kvm_mmu_slot_apply_flags(struct kvm *kvm, 7543 struct kvm_memory_slot *new) 7544 { 7545 /* Still write protect RO slot */ 7546 if (new->flags & KVM_MEM_READONLY) { 7547 kvm_mmu_slot_remove_write_access(kvm, new); 7548 return; 7549 } 7550 7551 /* 7552 * Call kvm_x86_ops dirty logging hooks when they are valid. 7553 * 7554 * kvm_x86_ops->slot_disable_log_dirty is called when: 7555 * 7556 * - KVM_MR_CREATE with dirty logging is disabled 7557 * - KVM_MR_FLAGS_ONLY with dirty logging is disabled in new flag 7558 * 7559 * The reason is, in case of PML, we need to set D-bit for any slots 7560 * with dirty logging disabled in order to eliminate unnecessary GPA 7561 * logging in PML buffer (and potential PML buffer full VMEXT). This 7562 * guarantees leaving PML enabled during guest's lifetime won't have 7563 * any additonal overhead from PML when guest is running with dirty 7564 * logging disabled for memory slots. 7565 * 7566 * kvm_x86_ops->slot_enable_log_dirty is called when switching new slot 7567 * to dirty logging mode. 7568 * 7569 * If kvm_x86_ops dirty logging hooks are invalid, use write protect. 7570 * 7571 * In case of write protect: 7572 * 7573 * Write protect all pages for dirty logging. 7574 * 7575 * All the sptes including the large sptes which point to this 7576 * slot are set to readonly. We can not create any new large 7577 * spte on this slot until the end of the logging. 7578 * 7579 * See the comments in fast_page_fault(). 7580 */ 7581 if (new->flags & KVM_MEM_LOG_DIRTY_PAGES) { 7582 if (kvm_x86_ops->slot_enable_log_dirty) 7583 kvm_x86_ops->slot_enable_log_dirty(kvm, new); 7584 else 7585 kvm_mmu_slot_remove_write_access(kvm, new); 7586 } else { 7587 if (kvm_x86_ops->slot_disable_log_dirty) 7588 kvm_x86_ops->slot_disable_log_dirty(kvm, new); 7589 } 7590 } 7591 7592 void kvm_arch_commit_memory_region(struct kvm *kvm, 7593 struct kvm_userspace_memory_region *mem, 7594 const struct kvm_memory_slot *old, 7595 enum kvm_mr_change change) 7596 { 7597 struct kvm_memory_slot *new; 7598 int nr_mmu_pages = 0; 7599 7600 if ((mem->slot >= KVM_USER_MEM_SLOTS) && (change == KVM_MR_DELETE)) { 7601 int ret; 7602 7603 ret = vm_munmap(old->userspace_addr, 7604 old->npages * PAGE_SIZE); 7605 if (ret < 0) 7606 printk(KERN_WARNING 7607 "kvm_vm_ioctl_set_memory_region: " 7608 "failed to munmap memory\n"); 7609 } 7610 7611 if (!kvm->arch.n_requested_mmu_pages) 7612 nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm); 7613 7614 if (nr_mmu_pages) 7615 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages); 7616 7617 /* It's OK to get 'new' slot here as it has already been installed */ 7618 new = id_to_memslot(kvm->memslots, mem->slot); 7619 7620 /* 7621 * Set up write protection and/or dirty logging for the new slot. 7622 * 7623 * For KVM_MR_DELETE and KVM_MR_MOVE, the shadow pages of old slot have 7624 * been zapped so no dirty logging staff is needed for old slot. For 7625 * KVM_MR_FLAGS_ONLY, the old slot is essentially the same one as the 7626 * new and it's also covered when dealing with the new slot. 7627 */ 7628 if (change != KVM_MR_DELETE) 7629 kvm_mmu_slot_apply_flags(kvm, new); 7630 } 7631 7632 void kvm_arch_flush_shadow_all(struct kvm *kvm) 7633 { 7634 kvm_mmu_invalidate_zap_all_pages(kvm); 7635 } 7636 7637 void kvm_arch_flush_shadow_memslot(struct kvm *kvm, 7638 struct kvm_memory_slot *slot) 7639 { 7640 kvm_mmu_invalidate_zap_all_pages(kvm); 7641 } 7642 7643 int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu) 7644 { 7645 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) 7646 kvm_x86_ops->check_nested_events(vcpu, false); 7647 7648 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE && 7649 !vcpu->arch.apf.halted) 7650 || !list_empty_careful(&vcpu->async_pf.done) 7651 || kvm_apic_has_events(vcpu) 7652 || vcpu->arch.pv.pv_unhalted 7653 || atomic_read(&vcpu->arch.nmi_queued) || 7654 (kvm_arch_interrupt_allowed(vcpu) && 7655 kvm_cpu_has_interrupt(vcpu)); 7656 } 7657 7658 int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu) 7659 { 7660 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE; 7661 } 7662 7663 int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu) 7664 { 7665 return kvm_x86_ops->interrupt_allowed(vcpu); 7666 } 7667 7668 unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu) 7669 { 7670 if (is_64_bit_mode(vcpu)) 7671 return kvm_rip_read(vcpu); 7672 return (u32)(get_segment_base(vcpu, VCPU_SREG_CS) + 7673 kvm_rip_read(vcpu)); 7674 } 7675 EXPORT_SYMBOL_GPL(kvm_get_linear_rip); 7676 7677 bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip) 7678 { 7679 return kvm_get_linear_rip(vcpu) == linear_rip; 7680 } 7681 EXPORT_SYMBOL_GPL(kvm_is_linear_rip); 7682 7683 unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu) 7684 { 7685 unsigned long rflags; 7686 7687 rflags = kvm_x86_ops->get_rflags(vcpu); 7688 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) 7689 rflags &= ~X86_EFLAGS_TF; 7690 return rflags; 7691 } 7692 EXPORT_SYMBOL_GPL(kvm_get_rflags); 7693 7694 static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags) 7695 { 7696 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP && 7697 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip)) 7698 rflags |= X86_EFLAGS_TF; 7699 kvm_x86_ops->set_rflags(vcpu, rflags); 7700 } 7701 7702 void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags) 7703 { 7704 __kvm_set_rflags(vcpu, rflags); 7705 kvm_make_request(KVM_REQ_EVENT, vcpu); 7706 } 7707 EXPORT_SYMBOL_GPL(kvm_set_rflags); 7708 7709 void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work) 7710 { 7711 int r; 7712 7713 if ((vcpu->arch.mmu.direct_map != work->arch.direct_map) || 7714 work->wakeup_all) 7715 return; 7716 7717 r = kvm_mmu_reload(vcpu); 7718 if (unlikely(r)) 7719 return; 7720 7721 if (!vcpu->arch.mmu.direct_map && 7722 work->arch.cr3 != vcpu->arch.mmu.get_cr3(vcpu)) 7723 return; 7724 7725 vcpu->arch.mmu.page_fault(vcpu, work->gva, 0, true); 7726 } 7727 7728 static inline u32 kvm_async_pf_hash_fn(gfn_t gfn) 7729 { 7730 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU)); 7731 } 7732 7733 static inline u32 kvm_async_pf_next_probe(u32 key) 7734 { 7735 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1); 7736 } 7737 7738 static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn) 7739 { 7740 u32 key = kvm_async_pf_hash_fn(gfn); 7741 7742 while (vcpu->arch.apf.gfns[key] != ~0) 7743 key = kvm_async_pf_next_probe(key); 7744 7745 vcpu->arch.apf.gfns[key] = gfn; 7746 } 7747 7748 static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn) 7749 { 7750 int i; 7751 u32 key = kvm_async_pf_hash_fn(gfn); 7752 7753 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) && 7754 (vcpu->arch.apf.gfns[key] != gfn && 7755 vcpu->arch.apf.gfns[key] != ~0); i++) 7756 key = kvm_async_pf_next_probe(key); 7757 7758 return key; 7759 } 7760 7761 bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn) 7762 { 7763 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn; 7764 } 7765 7766 static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn) 7767 { 7768 u32 i, j, k; 7769 7770 i = j = kvm_async_pf_gfn_slot(vcpu, gfn); 7771 while (true) { 7772 vcpu->arch.apf.gfns[i] = ~0; 7773 do { 7774 j = kvm_async_pf_next_probe(j); 7775 if (vcpu->arch.apf.gfns[j] == ~0) 7776 return; 7777 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]); 7778 /* 7779 * k lies cyclically in ]i,j] 7780 * | i.k.j | 7781 * |....j i.k.| or |.k..j i...| 7782 */ 7783 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j)); 7784 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j]; 7785 i = j; 7786 } 7787 } 7788 7789 static int apf_put_user(struct kvm_vcpu *vcpu, u32 val) 7790 { 7791 7792 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val, 7793 sizeof(val)); 7794 } 7795 7796 void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu, 7797 struct kvm_async_pf *work) 7798 { 7799 struct x86_exception fault; 7800 7801 trace_kvm_async_pf_not_present(work->arch.token, work->gva); 7802 kvm_add_async_pf_gfn(vcpu, work->arch.gfn); 7803 7804 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) || 7805 (vcpu->arch.apf.send_user_only && 7806 kvm_x86_ops->get_cpl(vcpu) == 0)) 7807 kvm_make_request(KVM_REQ_APF_HALT, vcpu); 7808 else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) { 7809 fault.vector = PF_VECTOR; 7810 fault.error_code_valid = true; 7811 fault.error_code = 0; 7812 fault.nested_page_fault = false; 7813 fault.address = work->arch.token; 7814 kvm_inject_page_fault(vcpu, &fault); 7815 } 7816 } 7817 7818 void kvm_arch_async_page_present(struct kvm_vcpu *vcpu, 7819 struct kvm_async_pf *work) 7820 { 7821 struct x86_exception fault; 7822 7823 trace_kvm_async_pf_ready(work->arch.token, work->gva); 7824 if (work->wakeup_all) 7825 work->arch.token = ~0; /* broadcast wakeup */ 7826 else 7827 kvm_del_async_pf_gfn(vcpu, work->arch.gfn); 7828 7829 if ((vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) && 7830 !apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) { 7831 fault.vector = PF_VECTOR; 7832 fault.error_code_valid = true; 7833 fault.error_code = 0; 7834 fault.nested_page_fault = false; 7835 fault.address = work->arch.token; 7836 kvm_inject_page_fault(vcpu, &fault); 7837 } 7838 vcpu->arch.apf.halted = false; 7839 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; 7840 } 7841 7842 bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu) 7843 { 7844 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED)) 7845 return true; 7846 else 7847 return !kvm_event_needs_reinjection(vcpu) && 7848 kvm_x86_ops->interrupt_allowed(vcpu); 7849 } 7850 7851 void kvm_arch_register_noncoherent_dma(struct kvm *kvm) 7852 { 7853 atomic_inc(&kvm->arch.noncoherent_dma_count); 7854 } 7855 EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma); 7856 7857 void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm) 7858 { 7859 atomic_dec(&kvm->arch.noncoherent_dma_count); 7860 } 7861 EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma); 7862 7863 bool kvm_arch_has_noncoherent_dma(struct kvm *kvm) 7864 { 7865 return atomic_read(&kvm->arch.noncoherent_dma_count); 7866 } 7867 EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma); 7868 7869 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit); 7870 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq); 7871 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault); 7872 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr); 7873 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr); 7874 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun); 7875 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit); 7876 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject); 7877 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit); 7878 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga); 7879 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit); 7880 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts); 7881 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset); 7882 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_ple_window); 7883 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pml_full); 7884