1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef __KVM_X86_VMX_H 3 #define __KVM_X86_VMX_H 4 5 #include <linux/kvm_host.h> 6 7 #include <asm/kvm.h> 8 #include <asm/intel_pt.h> 9 10 #include "capabilities.h" 11 #include "kvm_cache_regs.h" 12 #include "posted_intr.h" 13 #include "vmcs.h" 14 #include "vmx_ops.h" 15 #include "cpuid.h" 16 17 extern const u32 vmx_msr_index[]; 18 19 #define MSR_TYPE_R 1 20 #define MSR_TYPE_W 2 21 #define MSR_TYPE_RW 3 22 23 #define X2APIC_MSR(r) (APIC_BASE_MSR + ((r) >> 4)) 24 25 #ifdef CONFIG_X86_64 26 #define MAX_NR_USER_RETURN_MSRS 7 27 #else 28 #define MAX_NR_USER_RETURN_MSRS 4 29 #endif 30 31 #define MAX_NR_LOADSTORE_MSRS 8 32 33 struct vmx_msrs { 34 unsigned int nr; 35 struct vmx_msr_entry val[MAX_NR_LOADSTORE_MSRS]; 36 }; 37 38 struct vmx_uret_msr { 39 unsigned int slot; /* The MSR's slot in kvm_user_return_msrs. */ 40 u64 data; 41 u64 mask; 42 }; 43 44 enum segment_cache_field { 45 SEG_FIELD_SEL = 0, 46 SEG_FIELD_BASE = 1, 47 SEG_FIELD_LIMIT = 2, 48 SEG_FIELD_AR = 3, 49 50 SEG_FIELD_NR = 4 51 }; 52 53 #define RTIT_ADDR_RANGE 4 54 55 struct pt_ctx { 56 u64 ctl; 57 u64 status; 58 u64 output_base; 59 u64 output_mask; 60 u64 cr3_match; 61 u64 addr_a[RTIT_ADDR_RANGE]; 62 u64 addr_b[RTIT_ADDR_RANGE]; 63 }; 64 65 struct pt_desc { 66 u64 ctl_bitmask; 67 u32 addr_range; 68 u32 caps[PT_CPUID_REGS_NUM * PT_CPUID_LEAVES]; 69 struct pt_ctx host; 70 struct pt_ctx guest; 71 }; 72 73 union vmx_exit_reason { 74 struct { 75 u32 basic : 16; 76 u32 reserved16 : 1; 77 u32 reserved17 : 1; 78 u32 reserved18 : 1; 79 u32 reserved19 : 1; 80 u32 reserved20 : 1; 81 u32 reserved21 : 1; 82 u32 reserved22 : 1; 83 u32 reserved23 : 1; 84 u32 reserved24 : 1; 85 u32 reserved25 : 1; 86 u32 bus_lock_detected : 1; 87 u32 enclave_mode : 1; 88 u32 smi_pending_mtf : 1; 89 u32 smi_from_vmx_root : 1; 90 u32 reserved30 : 1; 91 u32 failed_vmentry : 1; 92 }; 93 u32 full; 94 }; 95 96 #define vcpu_to_lbr_desc(vcpu) (&to_vmx(vcpu)->lbr_desc) 97 #define vcpu_to_lbr_records(vcpu) (&to_vmx(vcpu)->lbr_desc.records) 98 99 bool intel_pmu_lbr_is_compatible(struct kvm_vcpu *vcpu); 100 bool intel_pmu_lbr_is_enabled(struct kvm_vcpu *vcpu); 101 102 int intel_pmu_create_guest_lbr_event(struct kvm_vcpu *vcpu); 103 void vmx_passthrough_lbr_msrs(struct kvm_vcpu *vcpu); 104 105 struct lbr_desc { 106 /* Basic info about guest LBR records. */ 107 struct x86_pmu_lbr records; 108 109 /* 110 * Emulate LBR feature via passthrough LBR registers when the 111 * per-vcpu guest LBR event is scheduled on the current pcpu. 112 * 113 * The records may be inaccurate if the host reclaims the LBR. 114 */ 115 struct perf_event *event; 116 117 /* True if LBRs are marked as not intercepted in the MSR bitmap */ 118 bool msr_passthrough; 119 }; 120 121 /* 122 * The nested_vmx structure is part of vcpu_vmx, and holds information we need 123 * for correct emulation of VMX (i.e., nested VMX) on this vcpu. 124 */ 125 struct nested_vmx { 126 /* Has the level1 guest done vmxon? */ 127 bool vmxon; 128 gpa_t vmxon_ptr; 129 bool pml_full; 130 131 /* The guest-physical address of the current VMCS L1 keeps for L2 */ 132 gpa_t current_vmptr; 133 /* 134 * Cache of the guest's VMCS, existing outside of guest memory. 135 * Loaded from guest memory during VMPTRLD. Flushed to guest 136 * memory during VMCLEAR and VMPTRLD. 137 */ 138 struct vmcs12 *cached_vmcs12; 139 /* 140 * Cache of the guest's shadow VMCS, existing outside of guest 141 * memory. Loaded from guest memory during VM entry. Flushed 142 * to guest memory during VM exit. 143 */ 144 struct vmcs12 *cached_shadow_vmcs12; 145 146 /* 147 * Indicates if the shadow vmcs or enlightened vmcs must be updated 148 * with the data held by struct vmcs12. 149 */ 150 bool need_vmcs12_to_shadow_sync; 151 bool dirty_vmcs12; 152 153 /* 154 * Indicates lazily loaded guest state has not yet been decached from 155 * vmcs02. 156 */ 157 bool need_sync_vmcs02_to_vmcs12_rare; 158 159 /* 160 * vmcs02 has been initialized, i.e. state that is constant for 161 * vmcs02 has been written to the backing VMCS. Initialization 162 * is delayed until L1 actually attempts to run a nested VM. 163 */ 164 bool vmcs02_initialized; 165 166 bool change_vmcs01_virtual_apic_mode; 167 bool reload_vmcs01_apic_access_page; 168 169 /* 170 * Enlightened VMCS has been enabled. It does not mean that L1 has to 171 * use it. However, VMX features available to L1 will be limited based 172 * on what the enlightened VMCS supports. 173 */ 174 bool enlightened_vmcs_enabled; 175 176 /* L2 must run next, and mustn't decide to exit to L1. */ 177 bool nested_run_pending; 178 179 /* Pending MTF VM-exit into L1. */ 180 bool mtf_pending; 181 182 struct loaded_vmcs vmcs02; 183 184 /* 185 * Guest pages referred to in the vmcs02 with host-physical 186 * pointers, so we must keep them pinned while L2 runs. 187 */ 188 struct page *apic_access_page; 189 struct kvm_host_map virtual_apic_map; 190 struct kvm_host_map pi_desc_map; 191 192 struct kvm_host_map msr_bitmap_map; 193 194 struct pi_desc *pi_desc; 195 bool pi_pending; 196 u16 posted_intr_nv; 197 198 struct hrtimer preemption_timer; 199 u64 preemption_timer_deadline; 200 bool has_preemption_timer_deadline; 201 bool preemption_timer_expired; 202 203 /* to migrate it to L2 if VM_ENTRY_LOAD_DEBUG_CONTROLS is off */ 204 u64 vmcs01_debugctl; 205 u64 vmcs01_guest_bndcfgs; 206 207 /* to migrate it to L1 if L2 writes to L1's CR8 directly */ 208 int l1_tpr_threshold; 209 210 u16 vpid02; 211 u16 last_vpid; 212 213 struct nested_vmx_msrs msrs; 214 215 /* SMM related state */ 216 struct { 217 /* in VMX operation on SMM entry? */ 218 bool vmxon; 219 /* in guest mode on SMM entry? */ 220 bool guest_mode; 221 } smm; 222 223 gpa_t hv_evmcs_vmptr; 224 struct kvm_host_map hv_evmcs_map; 225 struct hv_enlightened_vmcs *hv_evmcs; 226 }; 227 228 struct vcpu_vmx { 229 struct kvm_vcpu vcpu; 230 u8 fail; 231 u8 msr_bitmap_mode; 232 233 /* 234 * If true, host state has been stored in vmx->loaded_vmcs for 235 * the CPU registers that only need to be switched when transitioning 236 * to/from the kernel, and the registers have been loaded with guest 237 * values. If false, host state is loaded in the CPU registers 238 * and vmx->loaded_vmcs->host_state is invalid. 239 */ 240 bool guest_state_loaded; 241 242 unsigned long exit_qualification; 243 u32 exit_intr_info; 244 u32 idt_vectoring_info; 245 ulong rflags; 246 247 struct vmx_uret_msr guest_uret_msrs[MAX_NR_USER_RETURN_MSRS]; 248 int nr_uret_msrs; 249 int nr_active_uret_msrs; 250 bool guest_uret_msrs_loaded; 251 #ifdef CONFIG_X86_64 252 u64 msr_host_kernel_gs_base; 253 u64 msr_guest_kernel_gs_base; 254 #endif 255 256 u64 spec_ctrl; 257 u32 msr_ia32_umwait_control; 258 259 u32 secondary_exec_control; 260 261 /* 262 * loaded_vmcs points to the VMCS currently used in this vcpu. For a 263 * non-nested (L1) guest, it always points to vmcs01. For a nested 264 * guest (L2), it points to a different VMCS. 265 */ 266 struct loaded_vmcs vmcs01; 267 struct loaded_vmcs *loaded_vmcs; 268 269 struct msr_autoload { 270 struct vmx_msrs guest; 271 struct vmx_msrs host; 272 } msr_autoload; 273 274 struct msr_autostore { 275 struct vmx_msrs guest; 276 } msr_autostore; 277 278 struct { 279 int vm86_active; 280 ulong save_rflags; 281 struct kvm_segment segs[8]; 282 } rmode; 283 struct { 284 u32 bitmask; /* 4 bits per segment (1 bit per field) */ 285 struct kvm_save_segment { 286 u16 selector; 287 unsigned long base; 288 u32 limit; 289 u32 ar; 290 } seg[8]; 291 } segment_cache; 292 int vpid; 293 bool emulation_required; 294 295 union vmx_exit_reason exit_reason; 296 297 /* Posted interrupt descriptor */ 298 struct pi_desc pi_desc; 299 300 /* Support for a guest hypervisor (nested VMX) */ 301 struct nested_vmx nested; 302 303 /* Dynamic PLE window. */ 304 unsigned int ple_window; 305 bool ple_window_dirty; 306 307 bool req_immediate_exit; 308 309 /* Support for PML */ 310 #define PML_ENTITY_NUM 512 311 struct page *pml_pg; 312 313 /* apic deadline value in host tsc */ 314 u64 hv_deadline_tsc; 315 316 u64 current_tsc_ratio; 317 318 unsigned long host_debugctlmsr; 319 320 /* 321 * Only bits masked by msr_ia32_feature_control_valid_bits can be set in 322 * msr_ia32_feature_control. FEAT_CTL_LOCKED is always included 323 * in msr_ia32_feature_control_valid_bits. 324 */ 325 u64 msr_ia32_feature_control; 326 u64 msr_ia32_feature_control_valid_bits; 327 u64 ept_pointer; 328 329 struct pt_desc pt_desc; 330 struct lbr_desc lbr_desc; 331 332 /* Save desired MSR intercept (read: pass-through) state */ 333 #define MAX_POSSIBLE_PASSTHROUGH_MSRS 13 334 struct { 335 DECLARE_BITMAP(read, MAX_POSSIBLE_PASSTHROUGH_MSRS); 336 DECLARE_BITMAP(write, MAX_POSSIBLE_PASSTHROUGH_MSRS); 337 } shadow_msr_intercept; 338 }; 339 340 enum ept_pointers_status { 341 EPT_POINTERS_CHECK = 0, 342 EPT_POINTERS_MATCH = 1, 343 EPT_POINTERS_MISMATCH = 2 344 }; 345 346 struct kvm_vmx { 347 struct kvm kvm; 348 349 unsigned int tss_addr; 350 bool ept_identity_pagetable_done; 351 gpa_t ept_identity_map_addr; 352 353 enum ept_pointers_status ept_pointers_match; 354 spinlock_t ept_pointer_lock; 355 }; 356 357 bool nested_vmx_allowed(struct kvm_vcpu *vcpu); 358 void vmx_vcpu_load_vmcs(struct kvm_vcpu *vcpu, int cpu, 359 struct loaded_vmcs *buddy); 360 int allocate_vpid(void); 361 void free_vpid(int vpid); 362 void vmx_set_constant_host_state(struct vcpu_vmx *vmx); 363 void vmx_prepare_switch_to_guest(struct kvm_vcpu *vcpu); 364 void vmx_set_host_fs_gs(struct vmcs_host_state *host, u16 fs_sel, u16 gs_sel, 365 unsigned long fs_base, unsigned long gs_base); 366 int vmx_get_cpl(struct kvm_vcpu *vcpu); 367 unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu); 368 void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags); 369 u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu); 370 void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask); 371 int vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer); 372 void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0); 373 void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4); 374 void set_cr4_guest_host_mask(struct vcpu_vmx *vmx); 375 void ept_save_pdptrs(struct kvm_vcpu *vcpu); 376 void vmx_get_segment(struct kvm_vcpu *vcpu, struct kvm_segment *var, int seg); 377 void vmx_set_segment(struct kvm_vcpu *vcpu, struct kvm_segment *var, int seg); 378 u64 construct_eptp(struct kvm_vcpu *vcpu, unsigned long root_hpa, 379 int root_level); 380 381 void vmx_update_exception_bitmap(struct kvm_vcpu *vcpu); 382 void vmx_update_msr_bitmap(struct kvm_vcpu *vcpu); 383 bool vmx_nmi_blocked(struct kvm_vcpu *vcpu); 384 bool vmx_interrupt_blocked(struct kvm_vcpu *vcpu); 385 bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu); 386 void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked); 387 void vmx_set_virtual_apic_mode(struct kvm_vcpu *vcpu); 388 struct vmx_uret_msr *vmx_find_uret_msr(struct vcpu_vmx *vmx, u32 msr); 389 void pt_update_intercept_for_msr(struct kvm_vcpu *vcpu); 390 void vmx_update_host_rsp(struct vcpu_vmx *vmx, unsigned long host_rsp); 391 bool __vmx_vcpu_run(struct vcpu_vmx *vmx, unsigned long *regs, bool launched); 392 int vmx_find_loadstore_msr_slot(struct vmx_msrs *m, u32 msr); 393 void vmx_ept_load_pdptrs(struct kvm_vcpu *vcpu); 394 void vmx_set_intercept_for_msr(struct kvm_vcpu *vcpu, 395 u32 msr, int type, bool value); 396 397 static inline u8 vmx_get_rvi(void) 398 { 399 return vmcs_read16(GUEST_INTR_STATUS) & 0xff; 400 } 401 402 #define BUILD_CONTROLS_SHADOW(lname, uname) \ 403 static inline void lname##_controls_set(struct vcpu_vmx *vmx, u32 val) \ 404 { \ 405 if (vmx->loaded_vmcs->controls_shadow.lname != val) { \ 406 vmcs_write32(uname, val); \ 407 vmx->loaded_vmcs->controls_shadow.lname = val; \ 408 } \ 409 } \ 410 static inline u32 lname##_controls_get(struct vcpu_vmx *vmx) \ 411 { \ 412 return vmx->loaded_vmcs->controls_shadow.lname; \ 413 } \ 414 static inline void lname##_controls_setbit(struct vcpu_vmx *vmx, u32 val) \ 415 { \ 416 lname##_controls_set(vmx, lname##_controls_get(vmx) | val); \ 417 } \ 418 static inline void lname##_controls_clearbit(struct vcpu_vmx *vmx, u32 val) \ 419 { \ 420 lname##_controls_set(vmx, lname##_controls_get(vmx) & ~val); \ 421 } 422 BUILD_CONTROLS_SHADOW(vm_entry, VM_ENTRY_CONTROLS) 423 BUILD_CONTROLS_SHADOW(vm_exit, VM_EXIT_CONTROLS) 424 BUILD_CONTROLS_SHADOW(pin, PIN_BASED_VM_EXEC_CONTROL) 425 BUILD_CONTROLS_SHADOW(exec, CPU_BASED_VM_EXEC_CONTROL) 426 BUILD_CONTROLS_SHADOW(secondary_exec, SECONDARY_VM_EXEC_CONTROL) 427 428 static inline void vmx_register_cache_reset(struct kvm_vcpu *vcpu) 429 { 430 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP) 431 | (1 << VCPU_EXREG_RFLAGS) 432 | (1 << VCPU_EXREG_PDPTR) 433 | (1 << VCPU_EXREG_SEGMENTS) 434 | (1 << VCPU_EXREG_CR0) 435 | (1 << VCPU_EXREG_CR3) 436 | (1 << VCPU_EXREG_CR4) 437 | (1 << VCPU_EXREG_EXIT_INFO_1) 438 | (1 << VCPU_EXREG_EXIT_INFO_2)); 439 vcpu->arch.regs_dirty = 0; 440 } 441 442 static inline u32 vmx_vmentry_ctrl(void) 443 { 444 u32 vmentry_ctrl = vmcs_config.vmentry_ctrl; 445 if (vmx_pt_mode_is_system()) 446 vmentry_ctrl &= ~(VM_ENTRY_PT_CONCEAL_PIP | 447 VM_ENTRY_LOAD_IA32_RTIT_CTL); 448 /* Loading of EFER and PERF_GLOBAL_CTRL are toggled dynamically */ 449 return vmentry_ctrl & 450 ~(VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VM_ENTRY_LOAD_IA32_EFER); 451 } 452 453 static inline u32 vmx_vmexit_ctrl(void) 454 { 455 u32 vmexit_ctrl = vmcs_config.vmexit_ctrl; 456 if (vmx_pt_mode_is_system()) 457 vmexit_ctrl &= ~(VM_EXIT_PT_CONCEAL_PIP | 458 VM_EXIT_CLEAR_IA32_RTIT_CTL); 459 /* Loading of EFER and PERF_GLOBAL_CTRL are toggled dynamically */ 460 return vmexit_ctrl & 461 ~(VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | VM_EXIT_LOAD_IA32_EFER); 462 } 463 464 u32 vmx_exec_control(struct vcpu_vmx *vmx); 465 u32 vmx_pin_based_exec_ctrl(struct vcpu_vmx *vmx); 466 467 static inline struct kvm_vmx *to_kvm_vmx(struct kvm *kvm) 468 { 469 return container_of(kvm, struct kvm_vmx, kvm); 470 } 471 472 static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu) 473 { 474 return container_of(vcpu, struct vcpu_vmx, vcpu); 475 } 476 477 static inline unsigned long vmx_get_exit_qual(struct kvm_vcpu *vcpu) 478 { 479 struct vcpu_vmx *vmx = to_vmx(vcpu); 480 481 if (!kvm_register_is_available(vcpu, VCPU_EXREG_EXIT_INFO_1)) { 482 kvm_register_mark_available(vcpu, VCPU_EXREG_EXIT_INFO_1); 483 vmx->exit_qualification = vmcs_readl(EXIT_QUALIFICATION); 484 } 485 return vmx->exit_qualification; 486 } 487 488 static inline u32 vmx_get_intr_info(struct kvm_vcpu *vcpu) 489 { 490 struct vcpu_vmx *vmx = to_vmx(vcpu); 491 492 if (!kvm_register_is_available(vcpu, VCPU_EXREG_EXIT_INFO_2)) { 493 kvm_register_mark_available(vcpu, VCPU_EXREG_EXIT_INFO_2); 494 vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO); 495 } 496 return vmx->exit_intr_info; 497 } 498 499 struct vmcs *alloc_vmcs_cpu(bool shadow, int cpu, gfp_t flags); 500 void free_vmcs(struct vmcs *vmcs); 501 int alloc_loaded_vmcs(struct loaded_vmcs *loaded_vmcs); 502 void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs); 503 void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs); 504 505 static inline struct vmcs *alloc_vmcs(bool shadow) 506 { 507 return alloc_vmcs_cpu(shadow, raw_smp_processor_id(), 508 GFP_KERNEL_ACCOUNT); 509 } 510 511 static inline void decache_tsc_multiplier(struct vcpu_vmx *vmx) 512 { 513 vmx->current_tsc_ratio = vmx->vcpu.arch.tsc_scaling_ratio; 514 vmcs_write64(TSC_MULTIPLIER, vmx->current_tsc_ratio); 515 } 516 517 static inline bool vmx_has_waitpkg(struct vcpu_vmx *vmx) 518 { 519 return vmx->secondary_exec_control & 520 SECONDARY_EXEC_ENABLE_USR_WAIT_PAUSE; 521 } 522 523 static inline bool vmx_need_pf_intercept(struct kvm_vcpu *vcpu) 524 { 525 if (!enable_ept) 526 return true; 527 528 return allow_smaller_maxphyaddr && cpuid_maxphyaddr(vcpu) < boot_cpu_data.x86_phys_bits; 529 } 530 531 static inline bool is_unrestricted_guest(struct kvm_vcpu *vcpu) 532 { 533 return enable_unrestricted_guest && (!is_guest_mode(vcpu) || 534 (secondary_exec_controls_get(to_vmx(vcpu)) & 535 SECONDARY_EXEC_UNRESTRICTED_GUEST)); 536 } 537 538 bool __vmx_guest_state_valid(struct kvm_vcpu *vcpu); 539 static inline bool vmx_guest_state_valid(struct kvm_vcpu *vcpu) 540 { 541 return is_unrestricted_guest(vcpu) || __vmx_guest_state_valid(vcpu); 542 } 543 544 void dump_vmcs(void); 545 546 #endif /* __KVM_X86_VMX_H */ 547