1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef __KVM_X86_VMX_H 3 #define __KVM_X86_VMX_H 4 5 #include <linux/kvm_host.h> 6 7 #include <asm/kvm.h> 8 #include <asm/intel_pt.h> 9 #include <asm/perf_event.h> 10 #include <asm/posted_intr.h> 11 12 #include "capabilities.h" 13 #include "../regs.h" 14 #include "pmu_intel.h" 15 #include "vmcs.h" 16 #include "vmx_ops.h" 17 #include "../cpuid.h" 18 #include "../mmu.h" 19 #include "common.h" 20 21 #ifdef CONFIG_X86_64 22 #define MAX_NR_USER_RETURN_MSRS 7 23 #else 24 #define MAX_NR_USER_RETURN_MSRS 4 25 #endif 26 27 #define MAX_NR_LOADSTORE_MSRS 8 28 29 struct vmx_msrs { 30 unsigned int nr; 31 struct vmx_msr_entry val[MAX_NR_LOADSTORE_MSRS]; 32 }; 33 34 struct vmx_uret_msr { 35 bool load_into_hardware; 36 u64 data; 37 u64 mask; 38 }; 39 40 enum segment_cache_field { 41 SEG_FIELD_SEL = 0, 42 SEG_FIELD_BASE = 1, 43 SEG_FIELD_LIMIT = 2, 44 SEG_FIELD_AR = 3, 45 46 SEG_FIELD_NR = 4 47 }; 48 49 #define RTIT_ADDR_RANGE 4 50 51 struct pt_ctx { 52 u64 ctl; 53 u64 status; 54 u64 output_base; 55 u64 output_mask; 56 u64 cr3_match; 57 u64 addr_a[RTIT_ADDR_RANGE]; 58 u64 addr_b[RTIT_ADDR_RANGE]; 59 }; 60 61 struct pt_desc { 62 u64 ctl_bitmask; 63 u32 num_address_ranges; 64 u32 caps[PT_CPUID_REGS_NUM * PT_CPUID_LEAVES]; 65 struct pt_ctx host; 66 struct pt_ctx guest; 67 }; 68 69 /* 70 * The nested_vmx structure is part of vcpu_vmx, and holds information we need 71 * for correct emulation of VMX (i.e., nested VMX) on this vcpu. 72 */ 73 struct nested_vmx { 74 /* Has the level1 guest done vmxon? */ 75 bool vmxon; 76 gpa_t vmxon_ptr; 77 bool pml_full; 78 79 /* The guest-physical address of the current VMCS L1 keeps for L2 */ 80 gpa_t current_vmptr; 81 /* 82 * Cache of the guest's VMCS, existing outside of guest memory. 83 * Loaded from guest memory during VMPTRLD. Flushed to guest 84 * memory during VMCLEAR and VMPTRLD. 85 */ 86 struct vmcs12 *cached_vmcs12; 87 /* 88 * Cache of the guest's shadow VMCS, existing outside of guest 89 * memory. Loaded from guest memory during VM entry. Flushed 90 * to guest memory during VM exit. 91 */ 92 struct vmcs12 *cached_shadow_vmcs12; 93 94 /* 95 * GPA to HVA cache for accessing vmcs12->vmcs_link_pointer 96 */ 97 struct gfn_to_hva_cache shadow_vmcs12_cache; 98 99 /* 100 * GPA to HVA cache for VMCS12 101 */ 102 struct gfn_to_hva_cache vmcs12_cache; 103 104 /* 105 * Indicates if the shadow vmcs or enlightened vmcs must be updated 106 * with the data held by struct vmcs12. 107 */ 108 bool need_vmcs12_to_shadow_sync; 109 bool dirty_vmcs12; 110 111 /* 112 * Indicates whether MSR bitmap for L2 needs to be rebuilt due to 113 * changes in MSR bitmap for L1 or switching to a different L2. Note, 114 * this flag can only be used reliably in conjunction with a paravirt L1 115 * which informs L0 whether any changes to MSR bitmap for L2 were done 116 * on its side. 117 */ 118 bool force_msr_bitmap_recalc; 119 120 /* 121 * Indicates lazily loaded guest state has not yet been decached from 122 * vmcs02. 123 */ 124 bool need_sync_vmcs02_to_vmcs12_rare; 125 126 /* 127 * vmcs02 has been initialized, i.e. state that is constant for 128 * vmcs02 has been written to the backing VMCS. Initialization 129 * is delayed until L1 actually attempts to run a nested VM. 130 */ 131 bool vmcs02_initialized; 132 133 /* 134 * Enlightened VMCS has been enabled. It does not mean that L1 has to 135 * use it. However, VMX features available to L1 will be limited based 136 * on what the enlightened VMCS supports. 137 */ 138 bool enlightened_vmcs_enabled; 139 140 /* Pending MTF VM-exit into L1. */ 141 bool mtf_pending; 142 143 struct loaded_vmcs vmcs02; 144 145 /* 146 * Guest pages referred to in the vmcs02 with host-physical 147 * pointers, so we must keep them pinned while L2 runs. 148 */ 149 struct kvm_host_map apic_access_page_map; 150 struct kvm_host_map virtual_apic_map; 151 struct kvm_host_map pi_desc_map; 152 153 struct pi_desc *pi_desc; 154 bool pi_pending; 155 u16 posted_intr_nv; 156 157 struct hrtimer preemption_timer; 158 u64 preemption_timer_deadline; 159 bool has_preemption_timer_deadline; 160 bool preemption_timer_expired; 161 162 /* 163 * Used to snapshot MSRs that are conditionally loaded on VM-Enter in 164 * order to propagate the guest's pre-VM-Enter value into vmcs02. For 165 * emulation of VMLAUNCH/VMRESUME, the snapshot will be of L1's value. 166 * For KVM_SET_NESTED_STATE, the snapshot is of L2's value, _if_ 167 * userspace restores MSRs before nested state. If userspace restores 168 * MSRs after nested state, the snapshot holds garbage, but KVM can't 169 * detect that, and the garbage value in vmcs02 will be overwritten by 170 * MSR restoration in any case. 171 */ 172 u64 pre_vmenter_debugctl; 173 u64 pre_vmenter_bndcfgs; 174 u64 pre_vmenter_s_cet; 175 u64 pre_vmenter_ssp; 176 u64 pre_vmenter_ssp_tbl; 177 178 u16 vpid02; 179 u16 last_vpid; 180 181 int tsc_autostore_slot; 182 struct nested_vmx_msrs msrs; 183 184 /* SMM related state */ 185 struct { 186 /* in VMX operation on SMM entry? */ 187 bool vmxon; 188 /* in guest mode on SMM entry? */ 189 bool guest_mode; 190 } smm; 191 192 #ifdef CONFIG_KVM_HYPERV 193 gpa_t hv_evmcs_vmptr; 194 struct kvm_host_map hv_evmcs_map; 195 struct hv_enlightened_vmcs *hv_evmcs; 196 #endif 197 }; 198 199 struct vcpu_vmx { 200 struct kvm_vcpu vcpu; 201 struct vcpu_vt vt; 202 u8 fail; 203 u8 x2apic_msr_bitmap_mode; 204 205 u32 idt_vectoring_info; 206 ulong rflags; 207 208 /* 209 * User return MSRs are always emulated when enabled in the guest, but 210 * only loaded into hardware when necessary, e.g. SYSCALL #UDs outside 211 * of 64-bit mode or if EFER.SCE=1, thus the SYSCALL MSRs don't need to 212 * be loaded into hardware if those conditions aren't met. 213 */ 214 struct vmx_uret_msr guest_uret_msrs[MAX_NR_USER_RETURN_MSRS]; 215 bool guest_uret_msrs_loaded; 216 #ifdef CONFIG_X86_64 217 u64 msr_guest_kernel_gs_base; 218 #endif 219 220 u64 spec_ctrl; 221 u32 msr_ia32_umwait_control; 222 223 /* 224 * loaded_vmcs points to the VMCS currently used in this vcpu. For a 225 * non-nested (L1) guest, it always points to vmcs01. For a nested 226 * guest (L2), it points to a different VMCS. 227 */ 228 struct loaded_vmcs vmcs01; 229 struct loaded_vmcs *loaded_vmcs; 230 231 struct msr_autoload { 232 struct vmx_msrs guest; 233 struct vmx_msrs host; 234 } msr_autoload; 235 236 struct vmx_msrs msr_autostore; 237 238 struct { 239 int vm86_active; 240 ulong save_rflags; 241 struct kvm_segment segs[8]; 242 } rmode; 243 struct { 244 u32 bitmask; /* 4 bits per segment (1 bit per field) */ 245 struct kvm_save_segment { 246 u16 selector; 247 unsigned long base; 248 u32 limit; 249 u32 ar; 250 } seg[8]; 251 } segment_cache; 252 int vpid; 253 254 /* Support for a guest hypervisor (nested VMX) */ 255 struct nested_vmx nested; 256 257 /* Dynamic PLE window. */ 258 unsigned int ple_window; 259 bool ple_window_dirty; 260 261 /* Support for PML */ 262 #define PML_LOG_NR_ENTRIES 512 263 /* PML is written backwards: this is the first entry written by the CPU */ 264 #define PML_HEAD_INDEX (PML_LOG_NR_ENTRIES-1) 265 266 struct page *pml_pg; 267 268 /* apic deadline value in host tsc */ 269 u64 hv_deadline_tsc; 270 271 /* 272 * Only bits masked by msr_ia32_feature_control_valid_bits can be set in 273 * msr_ia32_feature_control. FEAT_CTL_LOCKED is always included 274 * in msr_ia32_feature_control_valid_bits. 275 */ 276 u64 msr_ia32_feature_control; 277 u64 msr_ia32_feature_control_valid_bits; 278 /* SGX Launch Control public key hash */ 279 u64 msr_ia32_sgxlepubkeyhash[4]; 280 u64 msr_ia32_mcu_opt_ctrl; 281 bool disable_fb_clear; 282 283 struct pt_desc pt_desc; 284 struct lbr_desc lbr_desc; 285 286 /* ve_info must be page aligned. */ 287 struct vmx_ve_information *ve_info; 288 }; 289 290 struct kvm_vmx { 291 struct kvm kvm; 292 293 unsigned int tss_addr; 294 bool ept_identity_pagetable_done; 295 gpa_t ept_identity_map_addr; 296 /* Posted Interrupt Descriptor (PID) table for IPI virtualization */ 297 u64 *pid_table; 298 }; 299 300 static __always_inline struct vcpu_vt *to_vt(struct kvm_vcpu *vcpu) 301 { 302 return &(container_of(vcpu, struct vcpu_vmx, vcpu)->vt); 303 } 304 305 static __always_inline struct kvm_vcpu *vt_to_vcpu(struct vcpu_vt *vt) 306 { 307 return &(container_of(vt, struct vcpu_vmx, vt)->vcpu); 308 } 309 310 static __always_inline union vmx_exit_reason vmx_get_exit_reason(struct kvm_vcpu *vcpu) 311 { 312 return to_vt(vcpu)->exit_reason; 313 } 314 315 static __always_inline unsigned long vmx_get_exit_qual(struct kvm_vcpu *vcpu) 316 { 317 struct vcpu_vt *vt = to_vt(vcpu); 318 319 if (!kvm_register_test_and_mark_available(vcpu, VCPU_REG_EXIT_INFO_1) && 320 !WARN_ON_ONCE(is_td_vcpu(vcpu))) 321 vt->exit_qualification = vmcs_readl(EXIT_QUALIFICATION); 322 323 return vt->exit_qualification; 324 } 325 326 static __always_inline u32 vmx_get_intr_info(struct kvm_vcpu *vcpu) 327 { 328 struct vcpu_vt *vt = to_vt(vcpu); 329 330 if (!kvm_register_test_and_mark_available(vcpu, VCPU_REG_EXIT_INFO_2) && 331 !WARN_ON_ONCE(is_td_vcpu(vcpu))) 332 vt->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO); 333 334 return vt->exit_intr_info; 335 } 336 337 void vmx_vcpu_load_vmcs(struct kvm_vcpu *vcpu, int cpu); 338 int allocate_vpid(void); 339 void free_vpid(int vpid); 340 void vmx_set_constant_host_state(struct vcpu_vmx *vmx); 341 void vmx_prepare_switch_to_guest(struct kvm_vcpu *vcpu); 342 void vmx_set_host_fs_gs(struct vmcs_host_state *host, u16 fs_sel, u16 gs_sel, 343 unsigned long fs_base, unsigned long gs_base); 344 int vmx_get_cpl(struct kvm_vcpu *vcpu); 345 int vmx_get_cpl_no_cache(struct kvm_vcpu *vcpu); 346 bool vmx_emulation_required(struct kvm_vcpu *vcpu); 347 unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu); 348 void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags); 349 u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu); 350 void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask); 351 int vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer); 352 void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0); 353 void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4); 354 void set_cr4_guest_host_mask(struct vcpu_vmx *vmx); 355 void ept_save_pdptrs(struct kvm_vcpu *vcpu); 356 void vmx_get_segment(struct kvm_vcpu *vcpu, struct kvm_segment *var, int seg); 357 void __vmx_set_segment(struct kvm_vcpu *vcpu, struct kvm_segment *var, int seg); 358 359 bool vmx_guest_inject_ac(struct kvm_vcpu *vcpu); 360 void vmx_update_exception_bitmap(struct kvm_vcpu *vcpu); 361 bool vmx_nmi_blocked(struct kvm_vcpu *vcpu); 362 bool __vmx_interrupt_blocked(struct kvm_vcpu *vcpu); 363 bool vmx_interrupt_blocked(struct kvm_vcpu *vcpu); 364 bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu); 365 void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked); 366 void vmx_set_virtual_apic_mode(struct kvm_vcpu *vcpu); 367 struct vmx_uret_msr *vmx_find_uret_msr(struct vcpu_vmx *vmx, u32 msr); 368 void pt_update_intercept_for_msr(struct kvm_vcpu *vcpu); 369 void vmx_update_host_rsp(struct vcpu_vmx *vmx, unsigned long host_rsp); 370 unsigned int __vmx_vcpu_enter_flags(struct vcpu_vmx *vmx); 371 bool __vmx_vcpu_run(struct vcpu_vmx *vmx, unsigned int flags); 372 void vmx_ept_load_pdptrs(struct kvm_vcpu *vcpu); 373 374 void vmx_set_intercept_for_msr(struct kvm_vcpu *vcpu, u32 msr, int type, bool set); 375 376 static inline void vmx_disable_intercept_for_msr(struct kvm_vcpu *vcpu, 377 u32 msr, int type) 378 { 379 vmx_set_intercept_for_msr(vcpu, msr, type, false); 380 } 381 382 static inline void vmx_enable_intercept_for_msr(struct kvm_vcpu *vcpu, 383 u32 msr, int type) 384 { 385 vmx_set_intercept_for_msr(vcpu, msr, type, true); 386 } 387 388 u64 vmx_get_l2_tsc_offset(struct kvm_vcpu *vcpu); 389 u64 vmx_get_l2_tsc_multiplier(struct kvm_vcpu *vcpu); 390 391 gva_t vmx_get_untagged_addr(struct kvm_vcpu *vcpu, gva_t gva, unsigned int flags); 392 393 void vmx_update_cpu_dirty_logging(struct kvm_vcpu *vcpu); 394 395 u64 vmx_get_supported_debugctl(struct kvm_vcpu *vcpu, bool host_initiated); 396 bool vmx_is_valid_debugctl(struct kvm_vcpu *vcpu, u64 data, bool host_initiated); 397 398 #define VMX_HOST_OWNED_DEBUGCTL_BITS (DEBUGCTLMSR_FREEZE_IN_SMM) 399 400 static inline void vmx_guest_debugctl_write(struct kvm_vcpu *vcpu, u64 val) 401 { 402 WARN_ON_ONCE(val & VMX_HOST_OWNED_DEBUGCTL_BITS); 403 404 val |= vcpu->arch.host_debugctl & VMX_HOST_OWNED_DEBUGCTL_BITS; 405 vmcs_write64(GUEST_IA32_DEBUGCTL, val); 406 } 407 408 static inline u64 vmx_guest_debugctl_read(void) 409 { 410 return vmcs_read64(GUEST_IA32_DEBUGCTL) & ~VMX_HOST_OWNED_DEBUGCTL_BITS; 411 } 412 413 static inline void vmx_reload_guest_debugctl(struct kvm_vcpu *vcpu) 414 { 415 u64 val = vmcs_read64(GUEST_IA32_DEBUGCTL); 416 417 if (!((val ^ vcpu->arch.host_debugctl) & VMX_HOST_OWNED_DEBUGCTL_BITS)) 418 return; 419 420 vmx_guest_debugctl_write(vcpu, val & ~VMX_HOST_OWNED_DEBUGCTL_BITS); 421 } 422 423 /* 424 * Note, early Intel manuals have the write-low and read-high bitmap offsets 425 * the wrong way round. The bitmaps control MSRs 0x00000000-0x00001fff and 426 * 0xc0000000-0xc0001fff. The former (low) uses bytes 0-0x3ff for reads and 427 * 0x800-0xbff for writes. The latter (high) uses 0x400-0x7ff for reads and 428 * 0xc00-0xfff for writes. MSRs not covered by either of the ranges always 429 * VM-Exit. 430 */ 431 #define __BUILD_VMX_MSR_BITMAP_HELPER(rtype, action, bitop, access, base) \ 432 static inline rtype vmx_##action##_msr_bitmap_##access(unsigned long *bitmap, \ 433 u32 msr) \ 434 { \ 435 int f = sizeof(unsigned long); \ 436 \ 437 if (msr <= 0x1fff) \ 438 return bitop##_bit(msr, bitmap + base / f); \ 439 else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) \ 440 return bitop##_bit(msr & 0x1fff, bitmap + (base + 0x400) / f); \ 441 return (rtype)true; \ 442 } 443 #define BUILD_VMX_MSR_BITMAP_HELPERS(ret_type, action, bitop) \ 444 __BUILD_VMX_MSR_BITMAP_HELPER(ret_type, action, bitop, read, 0x0) \ 445 __BUILD_VMX_MSR_BITMAP_HELPER(ret_type, action, bitop, write, 0x800) 446 447 BUILD_VMX_MSR_BITMAP_HELPERS(bool, test, test) 448 BUILD_VMX_MSR_BITMAP_HELPERS(void, clear, __clear) 449 BUILD_VMX_MSR_BITMAP_HELPERS(void, set, __set) 450 451 static inline u8 vmx_get_rvi(void) 452 { 453 return vmcs_read16(GUEST_INTR_STATUS) & 0xff; 454 } 455 456 #define __KVM_REQUIRED_VMX_VM_ENTRY_CONTROLS \ 457 (VM_ENTRY_LOAD_DEBUG_CONTROLS) 458 #ifdef CONFIG_X86_64 459 #define KVM_REQUIRED_VMX_VM_ENTRY_CONTROLS \ 460 (__KVM_REQUIRED_VMX_VM_ENTRY_CONTROLS | \ 461 VM_ENTRY_IA32E_MODE) 462 #else 463 #define KVM_REQUIRED_VMX_VM_ENTRY_CONTROLS \ 464 __KVM_REQUIRED_VMX_VM_ENTRY_CONTROLS 465 #endif 466 #define KVM_OPTIONAL_VMX_VM_ENTRY_CONTROLS \ 467 (VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | \ 468 VM_ENTRY_LOAD_IA32_PAT | \ 469 VM_ENTRY_LOAD_IA32_EFER | \ 470 VM_ENTRY_LOAD_BNDCFGS | \ 471 VM_ENTRY_PT_CONCEAL_PIP | \ 472 VM_ENTRY_LOAD_IA32_RTIT_CTL | \ 473 VM_ENTRY_LOAD_CET_STATE) 474 475 #define __KVM_REQUIRED_VMX_VM_EXIT_CONTROLS \ 476 (VM_EXIT_SAVE_DEBUG_CONTROLS | \ 477 VM_EXIT_ACK_INTR_ON_EXIT) 478 #ifdef CONFIG_X86_64 479 #define KVM_REQUIRED_VMX_VM_EXIT_CONTROLS \ 480 (__KVM_REQUIRED_VMX_VM_EXIT_CONTROLS | \ 481 VM_EXIT_HOST_ADDR_SPACE_SIZE) 482 #else 483 #define KVM_REQUIRED_VMX_VM_EXIT_CONTROLS \ 484 __KVM_REQUIRED_VMX_VM_EXIT_CONTROLS 485 #endif 486 #define KVM_OPTIONAL_VMX_VM_EXIT_CONTROLS \ 487 (VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | \ 488 VM_EXIT_SAVE_IA32_PAT | \ 489 VM_EXIT_LOAD_IA32_PAT | \ 490 VM_EXIT_SAVE_IA32_EFER | \ 491 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER | \ 492 VM_EXIT_LOAD_IA32_EFER | \ 493 VM_EXIT_CLEAR_BNDCFGS | \ 494 VM_EXIT_PT_CONCEAL_PIP | \ 495 VM_EXIT_CLEAR_IA32_RTIT_CTL | \ 496 VM_EXIT_LOAD_CET_STATE | \ 497 VM_EXIT_SAVE_IA32_PERF_GLOBAL_CTRL) 498 499 #define KVM_REQUIRED_VMX_PIN_BASED_VM_EXEC_CONTROL \ 500 (PIN_BASED_EXT_INTR_MASK | \ 501 PIN_BASED_NMI_EXITING) 502 #define KVM_OPTIONAL_VMX_PIN_BASED_VM_EXEC_CONTROL \ 503 (PIN_BASED_VIRTUAL_NMIS | \ 504 PIN_BASED_POSTED_INTR | \ 505 PIN_BASED_VMX_PREEMPTION_TIMER) 506 507 #define __KVM_REQUIRED_VMX_CPU_BASED_VM_EXEC_CONTROL \ 508 (CPU_BASED_HLT_EXITING | \ 509 CPU_BASED_CR3_LOAD_EXITING | \ 510 CPU_BASED_CR3_STORE_EXITING | \ 511 CPU_BASED_UNCOND_IO_EXITING | \ 512 CPU_BASED_MOV_DR_EXITING | \ 513 CPU_BASED_USE_TSC_OFFSETTING | \ 514 CPU_BASED_MWAIT_EXITING | \ 515 CPU_BASED_MONITOR_EXITING | \ 516 CPU_BASED_INVLPG_EXITING | \ 517 CPU_BASED_RDPMC_EXITING | \ 518 CPU_BASED_INTR_WINDOW_EXITING) 519 520 #ifdef CONFIG_X86_64 521 #define KVM_REQUIRED_VMX_CPU_BASED_VM_EXEC_CONTROL \ 522 (__KVM_REQUIRED_VMX_CPU_BASED_VM_EXEC_CONTROL | \ 523 CPU_BASED_CR8_LOAD_EXITING | \ 524 CPU_BASED_CR8_STORE_EXITING) 525 #else 526 #define KVM_REQUIRED_VMX_CPU_BASED_VM_EXEC_CONTROL \ 527 __KVM_REQUIRED_VMX_CPU_BASED_VM_EXEC_CONTROL 528 #endif 529 530 #define KVM_OPTIONAL_VMX_CPU_BASED_VM_EXEC_CONTROL \ 531 (CPU_BASED_RDTSC_EXITING | \ 532 CPU_BASED_TPR_SHADOW | \ 533 CPU_BASED_USE_IO_BITMAPS | \ 534 CPU_BASED_MONITOR_TRAP_FLAG | \ 535 CPU_BASED_USE_MSR_BITMAPS | \ 536 CPU_BASED_NMI_WINDOW_EXITING | \ 537 CPU_BASED_PAUSE_EXITING | \ 538 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS | \ 539 CPU_BASED_ACTIVATE_TERTIARY_CONTROLS) 540 541 #define KVM_REQUIRED_VMX_SECONDARY_VM_EXEC_CONTROL 0 542 #define KVM_OPTIONAL_VMX_SECONDARY_VM_EXEC_CONTROL \ 543 (SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | \ 544 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | \ 545 SECONDARY_EXEC_WBINVD_EXITING | \ 546 SECONDARY_EXEC_ENABLE_VPID | \ 547 SECONDARY_EXEC_ENABLE_EPT | \ 548 SECONDARY_EXEC_UNRESTRICTED_GUEST | \ 549 SECONDARY_EXEC_PAUSE_LOOP_EXITING | \ 550 SECONDARY_EXEC_DESC | \ 551 SECONDARY_EXEC_ENABLE_RDTSCP | \ 552 SECONDARY_EXEC_ENABLE_INVPCID | \ 553 SECONDARY_EXEC_APIC_REGISTER_VIRT | \ 554 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | \ 555 SECONDARY_EXEC_SHADOW_VMCS | \ 556 SECONDARY_EXEC_ENABLE_XSAVES | \ 557 SECONDARY_EXEC_RDSEED_EXITING | \ 558 SECONDARY_EXEC_RDRAND_EXITING | \ 559 SECONDARY_EXEC_ENABLE_PML | \ 560 SECONDARY_EXEC_TSC_SCALING | \ 561 SECONDARY_EXEC_ENABLE_USR_WAIT_PAUSE | \ 562 SECONDARY_EXEC_PT_USE_GPA | \ 563 SECONDARY_EXEC_PT_CONCEAL_VMX | \ 564 SECONDARY_EXEC_ENABLE_VMFUNC | \ 565 SECONDARY_EXEC_BUS_LOCK_DETECTION | \ 566 SECONDARY_EXEC_NOTIFY_VM_EXITING | \ 567 SECONDARY_EXEC_MODE_BASED_EPT_EXEC | \ 568 SECONDARY_EXEC_ENCLS_EXITING | \ 569 SECONDARY_EXEC_EPT_VIOLATION_VE) 570 571 #define KVM_REQUIRED_VMX_TERTIARY_VM_EXEC_CONTROL 0 572 #define KVM_OPTIONAL_VMX_TERTIARY_VM_EXEC_CONTROL \ 573 (TERTIARY_EXEC_IPI_VIRT) 574 575 #define BUILD_CONTROLS_SHADOW(lname, uname, bits) \ 576 static inline void lname##_controls_set(struct vcpu_vmx *vmx, u##bits val) \ 577 { \ 578 if (vmx->loaded_vmcs->controls_shadow.lname != val) { \ 579 vmcs_write##bits(uname, val); \ 580 vmx->loaded_vmcs->controls_shadow.lname = val; \ 581 } \ 582 } \ 583 static inline u##bits __##lname##_controls_get(struct loaded_vmcs *vmcs) \ 584 { \ 585 return vmcs->controls_shadow.lname; \ 586 } \ 587 static inline u##bits lname##_controls_get(struct vcpu_vmx *vmx) \ 588 { \ 589 return __##lname##_controls_get(vmx->loaded_vmcs); \ 590 } \ 591 static __always_inline void lname##_controls_setbit(struct vcpu_vmx *vmx, u##bits val) \ 592 { \ 593 BUILD_BUG_ON(!(val & (KVM_REQUIRED_VMX_##uname | KVM_OPTIONAL_VMX_##uname))); \ 594 lname##_controls_set(vmx, lname##_controls_get(vmx) | val); \ 595 } \ 596 static __always_inline void lname##_controls_clearbit(struct vcpu_vmx *vmx, u##bits val) \ 597 { \ 598 BUILD_BUG_ON(!(val & (KVM_REQUIRED_VMX_##uname | KVM_OPTIONAL_VMX_##uname))); \ 599 lname##_controls_set(vmx, lname##_controls_get(vmx) & ~val); \ 600 } \ 601 static __always_inline void lname##_controls_changebit(struct vcpu_vmx *vmx, u##bits val, \ 602 bool set) \ 603 { \ 604 if (set) \ 605 lname##_controls_setbit(vmx, val); \ 606 else \ 607 lname##_controls_clearbit(vmx, val); \ 608 } 609 BUILD_CONTROLS_SHADOW(vm_entry, VM_ENTRY_CONTROLS, 32) 610 BUILD_CONTROLS_SHADOW(vm_exit, VM_EXIT_CONTROLS, 32) 611 BUILD_CONTROLS_SHADOW(pin, PIN_BASED_VM_EXEC_CONTROL, 32) 612 BUILD_CONTROLS_SHADOW(exec, CPU_BASED_VM_EXEC_CONTROL, 32) 613 BUILD_CONTROLS_SHADOW(secondary_exec, SECONDARY_VM_EXEC_CONTROL, 32) 614 BUILD_CONTROLS_SHADOW(tertiary_exec, TERTIARY_VM_EXEC_CONTROL, 64) 615 616 /* 617 * VMX_REGS_LAZY_LOAD_SET - The set of registers that will be updated in the 618 * cache on demand. Other registers not listed here are synced to 619 * the cache immediately after VM-Exit. 620 */ 621 #define VMX_REGS_LAZY_LOAD_SET (BIT(VCPU_REGS_RSP) | \ 622 BIT(VCPU_REG_RIP) | \ 623 BIT(VCPU_REG_RFLAGS) | \ 624 BIT(VCPU_REG_PDPTR) | \ 625 BIT(VCPU_REG_SEGMENTS) | \ 626 BIT(VCPU_REG_CR0) | \ 627 BIT(VCPU_REG_CR3) | \ 628 BIT(VCPU_REG_CR4) | \ 629 BIT(VCPU_REG_EXIT_INFO_1) | \ 630 BIT(VCPU_REG_EXIT_INFO_2)) 631 632 static inline unsigned long vmx_l1_guest_owned_cr0_bits(void) 633 { 634 unsigned long bits = KVM_POSSIBLE_CR0_GUEST_BITS; 635 636 /* 637 * CR0.WP needs to be intercepted when KVM is shadowing legacy paging 638 * in order to construct shadow PTEs with the correct protections. 639 * Note! CR0.WP technically can be passed through to the guest if 640 * paging is disabled, but checking CR0.PG would generate a cyclical 641 * dependency of sorts due to forcing the caller to ensure CR0 holds 642 * the correct value prior to determining which CR0 bits can be owned 643 * by L1. Keep it simple and limit the optimization to EPT. 644 */ 645 if (!enable_ept) 646 bits &= ~X86_CR0_WP; 647 return bits; 648 } 649 650 static __always_inline struct kvm_vmx *to_kvm_vmx(struct kvm *kvm) 651 { 652 return container_of(kvm, struct kvm_vmx, kvm); 653 } 654 655 static __always_inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu) 656 { 657 return container_of(vcpu, struct vcpu_vmx, vcpu); 658 } 659 660 void intel_pmu_cross_mapped_check(struct kvm_pmu *pmu); 661 int intel_pmu_create_guest_lbr_event(struct kvm_vcpu *vcpu); 662 void vmx_passthrough_lbr_msrs(struct kvm_vcpu *vcpu); 663 664 struct vmcs *alloc_vmcs_cpu(bool shadow, int cpu, gfp_t flags); 665 void free_vmcs(struct vmcs *vmcs); 666 int alloc_loaded_vmcs(struct loaded_vmcs *loaded_vmcs); 667 void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs); 668 669 static inline struct vmcs *alloc_vmcs(bool shadow) 670 { 671 return alloc_vmcs_cpu(shadow, raw_smp_processor_id(), 672 GFP_KERNEL_ACCOUNT); 673 } 674 675 static inline bool vmx_has_waitpkg(struct vcpu_vmx *vmx) 676 { 677 return secondary_exec_controls_get(vmx) & 678 SECONDARY_EXEC_ENABLE_USR_WAIT_PAUSE; 679 } 680 681 static inline bool vmx_need_pf_intercept(struct kvm_vcpu *vcpu) 682 { 683 if (!enable_ept) 684 return true; 685 686 return allow_smaller_maxphyaddr && 687 cpuid_maxphyaddr(vcpu) < kvm_host.maxphyaddr; 688 } 689 690 static inline bool is_unrestricted_guest(struct kvm_vcpu *vcpu) 691 { 692 return enable_unrestricted_guest && (!is_guest_mode(vcpu) || 693 (secondary_exec_controls_get(to_vmx(vcpu)) & 694 SECONDARY_EXEC_UNRESTRICTED_GUEST)); 695 } 696 697 bool __vmx_guest_state_valid(struct kvm_vcpu *vcpu); 698 static inline bool vmx_guest_state_valid(struct kvm_vcpu *vcpu) 699 { 700 return is_unrestricted_guest(vcpu) || __vmx_guest_state_valid(vcpu); 701 } 702 703 void dump_vmcs(struct kvm_vcpu *vcpu); 704 705 static inline int vmx_get_instr_info_reg(u32 vmx_instr_info) 706 { 707 return (vmx_instr_info >> 3) & 0xf; 708 } 709 710 static inline int vmx_get_instr_info_reg2(u32 vmx_instr_info) 711 { 712 return (vmx_instr_info >> 28) & 0xf; 713 } 714 715 static inline bool vmx_can_use_ipiv(struct kvm_vcpu *vcpu) 716 { 717 return lapic_in_kernel(vcpu) && enable_ipiv; 718 } 719 720 static inline void vmx_segment_cache_clear(struct vcpu_vmx *vmx) 721 { 722 vmx->segment_cache.bitmask = 0; 723 } 724 725 int vmx_init(void); 726 void vmx_exit(void); 727 728 #endif /* __KVM_X86_VMX_H */ 729