1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef __KVM_X86_VMX_H 3 #define __KVM_X86_VMX_H 4 5 #include <linux/kvm_host.h> 6 7 #include <asm/kvm.h> 8 #include <asm/intel_pt.h> 9 10 #include "capabilities.h" 11 #include "ops.h" 12 #include "vmcs.h" 13 14 extern const u32 vmx_msr_index[]; 15 extern u64 host_efer; 16 17 extern u32 get_umwait_control_msr(void); 18 19 #define MSR_TYPE_R 1 20 #define MSR_TYPE_W 2 21 #define MSR_TYPE_RW 3 22 23 #define X2APIC_MSR(r) (APIC_BASE_MSR + ((r) >> 4)) 24 25 #ifdef CONFIG_X86_64 26 #define NR_SHARED_MSRS 7 27 #else 28 #define NR_SHARED_MSRS 4 29 #endif 30 31 #define NR_LOADSTORE_MSRS 8 32 33 struct vmx_msrs { 34 unsigned int nr; 35 struct vmx_msr_entry val[NR_LOADSTORE_MSRS]; 36 }; 37 38 struct shared_msr_entry { 39 unsigned index; 40 u64 data; 41 u64 mask; 42 }; 43 44 enum segment_cache_field { 45 SEG_FIELD_SEL = 0, 46 SEG_FIELD_BASE = 1, 47 SEG_FIELD_LIMIT = 2, 48 SEG_FIELD_AR = 3, 49 50 SEG_FIELD_NR = 4 51 }; 52 53 /* Posted-Interrupt Descriptor */ 54 struct pi_desc { 55 u32 pir[8]; /* Posted interrupt requested */ 56 union { 57 struct { 58 /* bit 256 - Outstanding Notification */ 59 u16 on : 1, 60 /* bit 257 - Suppress Notification */ 61 sn : 1, 62 /* bit 271:258 - Reserved */ 63 rsvd_1 : 14; 64 /* bit 279:272 - Notification Vector */ 65 u8 nv; 66 /* bit 287:280 - Reserved */ 67 u8 rsvd_2; 68 /* bit 319:288 - Notification Destination */ 69 u32 ndst; 70 }; 71 u64 control; 72 }; 73 u32 rsvd[6]; 74 } __aligned(64); 75 76 #define RTIT_ADDR_RANGE 4 77 78 struct pt_ctx { 79 u64 ctl; 80 u64 status; 81 u64 output_base; 82 u64 output_mask; 83 u64 cr3_match; 84 u64 addr_a[RTIT_ADDR_RANGE]; 85 u64 addr_b[RTIT_ADDR_RANGE]; 86 }; 87 88 struct pt_desc { 89 u64 ctl_bitmask; 90 u32 addr_range; 91 u32 caps[PT_CPUID_REGS_NUM * PT_CPUID_LEAVES]; 92 struct pt_ctx host; 93 struct pt_ctx guest; 94 }; 95 96 /* 97 * The nested_vmx structure is part of vcpu_vmx, and holds information we need 98 * for correct emulation of VMX (i.e., nested VMX) on this vcpu. 99 */ 100 struct nested_vmx { 101 /* Has the level1 guest done vmxon? */ 102 bool vmxon; 103 gpa_t vmxon_ptr; 104 bool pml_full; 105 106 /* The guest-physical address of the current VMCS L1 keeps for L2 */ 107 gpa_t current_vmptr; 108 /* 109 * Cache of the guest's VMCS, existing outside of guest memory. 110 * Loaded from guest memory during VMPTRLD. Flushed to guest 111 * memory during VMCLEAR and VMPTRLD. 112 */ 113 struct vmcs12 *cached_vmcs12; 114 /* 115 * Cache of the guest's shadow VMCS, existing outside of guest 116 * memory. Loaded from guest memory during VM entry. Flushed 117 * to guest memory during VM exit. 118 */ 119 struct vmcs12 *cached_shadow_vmcs12; 120 121 /* 122 * Indicates if the shadow vmcs or enlightened vmcs must be updated 123 * with the data held by struct vmcs12. 124 */ 125 bool need_vmcs12_to_shadow_sync; 126 bool dirty_vmcs12; 127 128 /* 129 * Indicates lazily loaded guest state has not yet been decached from 130 * vmcs02. 131 */ 132 bool need_sync_vmcs02_to_vmcs12_rare; 133 134 /* 135 * vmcs02 has been initialized, i.e. state that is constant for 136 * vmcs02 has been written to the backing VMCS. Initialization 137 * is delayed until L1 actually attempts to run a nested VM. 138 */ 139 bool vmcs02_initialized; 140 141 bool change_vmcs01_virtual_apic_mode; 142 143 /* 144 * Enlightened VMCS has been enabled. It does not mean that L1 has to 145 * use it. However, VMX features available to L1 will be limited based 146 * on what the enlightened VMCS supports. 147 */ 148 bool enlightened_vmcs_enabled; 149 150 /* L2 must run next, and mustn't decide to exit to L1. */ 151 bool nested_run_pending; 152 153 struct loaded_vmcs vmcs02; 154 155 /* 156 * Guest pages referred to in the vmcs02 with host-physical 157 * pointers, so we must keep them pinned while L2 runs. 158 */ 159 struct page *apic_access_page; 160 struct kvm_host_map virtual_apic_map; 161 struct kvm_host_map pi_desc_map; 162 163 struct kvm_host_map msr_bitmap_map; 164 165 struct pi_desc *pi_desc; 166 bool pi_pending; 167 u16 posted_intr_nv; 168 169 struct hrtimer preemption_timer; 170 bool preemption_timer_expired; 171 172 /* to migrate it to L2 if VM_ENTRY_LOAD_DEBUG_CONTROLS is off */ 173 u64 vmcs01_debugctl; 174 u64 vmcs01_guest_bndcfgs; 175 176 /* to migrate it to L1 if L2 writes to L1's CR8 directly */ 177 int l1_tpr_threshold; 178 179 u16 vpid02; 180 u16 last_vpid; 181 182 struct nested_vmx_msrs msrs; 183 184 /* SMM related state */ 185 struct { 186 /* in VMX operation on SMM entry? */ 187 bool vmxon; 188 /* in guest mode on SMM entry? */ 189 bool guest_mode; 190 } smm; 191 192 gpa_t hv_evmcs_vmptr; 193 struct kvm_host_map hv_evmcs_map; 194 struct hv_enlightened_vmcs *hv_evmcs; 195 }; 196 197 struct vcpu_vmx { 198 struct kvm_vcpu vcpu; 199 u8 fail; 200 u8 msr_bitmap_mode; 201 202 /* 203 * If true, host state has been stored in vmx->loaded_vmcs for 204 * the CPU registers that only need to be switched when transitioning 205 * to/from the kernel, and the registers have been loaded with guest 206 * values. If false, host state is loaded in the CPU registers 207 * and vmx->loaded_vmcs->host_state is invalid. 208 */ 209 bool guest_state_loaded; 210 211 u32 exit_intr_info; 212 u32 idt_vectoring_info; 213 ulong rflags; 214 215 struct shared_msr_entry guest_msrs[NR_SHARED_MSRS]; 216 int nmsrs; 217 int save_nmsrs; 218 bool guest_msrs_ready; 219 #ifdef CONFIG_X86_64 220 u64 msr_host_kernel_gs_base; 221 u64 msr_guest_kernel_gs_base; 222 #endif 223 224 u64 spec_ctrl; 225 u32 msr_ia32_umwait_control; 226 227 u32 secondary_exec_control; 228 229 /* 230 * loaded_vmcs points to the VMCS currently used in this vcpu. For a 231 * non-nested (L1) guest, it always points to vmcs01. For a nested 232 * guest (L2), it points to a different VMCS. 233 */ 234 struct loaded_vmcs vmcs01; 235 struct loaded_vmcs *loaded_vmcs; 236 237 struct msr_autoload { 238 struct vmx_msrs guest; 239 struct vmx_msrs host; 240 } msr_autoload; 241 242 struct msr_autostore { 243 struct vmx_msrs guest; 244 } msr_autostore; 245 246 struct { 247 int vm86_active; 248 ulong save_rflags; 249 struct kvm_segment segs[8]; 250 } rmode; 251 struct { 252 u32 bitmask; /* 4 bits per segment (1 bit per field) */ 253 struct kvm_save_segment { 254 u16 selector; 255 unsigned long base; 256 u32 limit; 257 u32 ar; 258 } seg[8]; 259 } segment_cache; 260 int vpid; 261 bool emulation_required; 262 263 u32 exit_reason; 264 265 /* Posted interrupt descriptor */ 266 struct pi_desc pi_desc; 267 268 /* Support for a guest hypervisor (nested VMX) */ 269 struct nested_vmx nested; 270 271 /* Dynamic PLE window. */ 272 unsigned int ple_window; 273 bool ple_window_dirty; 274 275 bool req_immediate_exit; 276 277 /* Support for PML */ 278 #define PML_ENTITY_NUM 512 279 struct page *pml_pg; 280 281 /* apic deadline value in host tsc */ 282 u64 hv_deadline_tsc; 283 284 u64 current_tsc_ratio; 285 286 u32 host_pkru; 287 288 unsigned long host_debugctlmsr; 289 290 /* 291 * Only bits masked by msr_ia32_feature_control_valid_bits can be set in 292 * msr_ia32_feature_control. FEAT_CTL_LOCKED is always included 293 * in msr_ia32_feature_control_valid_bits. 294 */ 295 u64 msr_ia32_feature_control; 296 u64 msr_ia32_feature_control_valid_bits; 297 u64 ept_pointer; 298 299 struct pt_desc pt_desc; 300 }; 301 302 enum ept_pointers_status { 303 EPT_POINTERS_CHECK = 0, 304 EPT_POINTERS_MATCH = 1, 305 EPT_POINTERS_MISMATCH = 2 306 }; 307 308 struct kvm_vmx { 309 struct kvm kvm; 310 311 unsigned int tss_addr; 312 bool ept_identity_pagetable_done; 313 gpa_t ept_identity_map_addr; 314 315 enum ept_pointers_status ept_pointers_match; 316 spinlock_t ept_pointer_lock; 317 }; 318 319 bool nested_vmx_allowed(struct kvm_vcpu *vcpu); 320 void vmx_vcpu_load_vmcs(struct kvm_vcpu *vcpu, int cpu); 321 void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu); 322 int allocate_vpid(void); 323 void free_vpid(int vpid); 324 void vmx_set_constant_host_state(struct vcpu_vmx *vmx); 325 void vmx_prepare_switch_to_guest(struct kvm_vcpu *vcpu); 326 void vmx_set_host_fs_gs(struct vmcs_host_state *host, u16 fs_sel, u16 gs_sel, 327 unsigned long fs_base, unsigned long gs_base); 328 int vmx_get_cpl(struct kvm_vcpu *vcpu); 329 unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu); 330 void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags); 331 u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu); 332 void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask); 333 void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer); 334 void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0); 335 void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3); 336 int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4); 337 void set_cr4_guest_host_mask(struct vcpu_vmx *vmx); 338 void ept_save_pdptrs(struct kvm_vcpu *vcpu); 339 void vmx_get_segment(struct kvm_vcpu *vcpu, struct kvm_segment *var, int seg); 340 void vmx_set_segment(struct kvm_vcpu *vcpu, struct kvm_segment *var, int seg); 341 u64 construct_eptp(struct kvm_vcpu *vcpu, unsigned long root_hpa); 342 void update_exception_bitmap(struct kvm_vcpu *vcpu); 343 void vmx_update_msr_bitmap(struct kvm_vcpu *vcpu); 344 bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu); 345 void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked); 346 void vmx_set_virtual_apic_mode(struct kvm_vcpu *vcpu); 347 struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr); 348 void pt_update_intercept_for_msr(struct vcpu_vmx *vmx); 349 void vmx_update_host_rsp(struct vcpu_vmx *vmx, unsigned long host_rsp); 350 int vmx_find_msr_index(struct vmx_msrs *m, u32 msr); 351 352 #define POSTED_INTR_ON 0 353 #define POSTED_INTR_SN 1 354 355 static inline bool pi_test_and_set_on(struct pi_desc *pi_desc) 356 { 357 return test_and_set_bit(POSTED_INTR_ON, 358 (unsigned long *)&pi_desc->control); 359 } 360 361 static inline bool pi_test_and_clear_on(struct pi_desc *pi_desc) 362 { 363 return test_and_clear_bit(POSTED_INTR_ON, 364 (unsigned long *)&pi_desc->control); 365 } 366 367 static inline int pi_test_and_set_pir(int vector, struct pi_desc *pi_desc) 368 { 369 return test_and_set_bit(vector, (unsigned long *)pi_desc->pir); 370 } 371 372 static inline bool pi_is_pir_empty(struct pi_desc *pi_desc) 373 { 374 return bitmap_empty((unsigned long *)pi_desc->pir, NR_VECTORS); 375 } 376 377 static inline void pi_set_sn(struct pi_desc *pi_desc) 378 { 379 set_bit(POSTED_INTR_SN, 380 (unsigned long *)&pi_desc->control); 381 } 382 383 static inline void pi_set_on(struct pi_desc *pi_desc) 384 { 385 set_bit(POSTED_INTR_ON, 386 (unsigned long *)&pi_desc->control); 387 } 388 389 static inline void pi_clear_on(struct pi_desc *pi_desc) 390 { 391 clear_bit(POSTED_INTR_ON, 392 (unsigned long *)&pi_desc->control); 393 } 394 395 static inline void pi_clear_sn(struct pi_desc *pi_desc) 396 { 397 clear_bit(POSTED_INTR_SN, 398 (unsigned long *)&pi_desc->control); 399 } 400 401 static inline int pi_test_on(struct pi_desc *pi_desc) 402 { 403 return test_bit(POSTED_INTR_ON, 404 (unsigned long *)&pi_desc->control); 405 } 406 407 static inline int pi_test_sn(struct pi_desc *pi_desc) 408 { 409 return test_bit(POSTED_INTR_SN, 410 (unsigned long *)&pi_desc->control); 411 } 412 413 static inline u8 vmx_get_rvi(void) 414 { 415 return vmcs_read16(GUEST_INTR_STATUS) & 0xff; 416 } 417 418 #define BUILD_CONTROLS_SHADOW(lname, uname) \ 419 static inline void lname##_controls_set(struct vcpu_vmx *vmx, u32 val) \ 420 { \ 421 if (vmx->loaded_vmcs->controls_shadow.lname != val) { \ 422 vmcs_write32(uname, val); \ 423 vmx->loaded_vmcs->controls_shadow.lname = val; \ 424 } \ 425 } \ 426 static inline u32 lname##_controls_get(struct vcpu_vmx *vmx) \ 427 { \ 428 return vmx->loaded_vmcs->controls_shadow.lname; \ 429 } \ 430 static inline void lname##_controls_setbit(struct vcpu_vmx *vmx, u32 val) \ 431 { \ 432 lname##_controls_set(vmx, lname##_controls_get(vmx) | val); \ 433 } \ 434 static inline void lname##_controls_clearbit(struct vcpu_vmx *vmx, u32 val) \ 435 { \ 436 lname##_controls_set(vmx, lname##_controls_get(vmx) & ~val); \ 437 } 438 BUILD_CONTROLS_SHADOW(vm_entry, VM_ENTRY_CONTROLS) 439 BUILD_CONTROLS_SHADOW(vm_exit, VM_EXIT_CONTROLS) 440 BUILD_CONTROLS_SHADOW(pin, PIN_BASED_VM_EXEC_CONTROL) 441 BUILD_CONTROLS_SHADOW(exec, CPU_BASED_VM_EXEC_CONTROL) 442 BUILD_CONTROLS_SHADOW(secondary_exec, SECONDARY_VM_EXEC_CONTROL) 443 444 static inline void vmx_segment_cache_clear(struct vcpu_vmx *vmx) 445 { 446 vmx->segment_cache.bitmask = 0; 447 } 448 449 static inline u32 vmx_vmentry_ctrl(void) 450 { 451 u32 vmentry_ctrl = vmcs_config.vmentry_ctrl; 452 if (pt_mode == PT_MODE_SYSTEM) 453 vmentry_ctrl &= ~(VM_ENTRY_PT_CONCEAL_PIP | 454 VM_ENTRY_LOAD_IA32_RTIT_CTL); 455 /* Loading of EFER and PERF_GLOBAL_CTRL are toggled dynamically */ 456 return vmentry_ctrl & 457 ~(VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VM_ENTRY_LOAD_IA32_EFER); 458 } 459 460 static inline u32 vmx_vmexit_ctrl(void) 461 { 462 u32 vmexit_ctrl = vmcs_config.vmexit_ctrl; 463 if (pt_mode == PT_MODE_SYSTEM) 464 vmexit_ctrl &= ~(VM_EXIT_PT_CONCEAL_PIP | 465 VM_EXIT_CLEAR_IA32_RTIT_CTL); 466 /* Loading of EFER and PERF_GLOBAL_CTRL are toggled dynamically */ 467 return vmexit_ctrl & 468 ~(VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | VM_EXIT_LOAD_IA32_EFER); 469 } 470 471 u32 vmx_exec_control(struct vcpu_vmx *vmx); 472 u32 vmx_pin_based_exec_ctrl(struct vcpu_vmx *vmx); 473 474 static inline struct kvm_vmx *to_kvm_vmx(struct kvm *kvm) 475 { 476 return container_of(kvm, struct kvm_vmx, kvm); 477 } 478 479 static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu) 480 { 481 return container_of(vcpu, struct vcpu_vmx, vcpu); 482 } 483 484 static inline struct pi_desc *vcpu_to_pi_desc(struct kvm_vcpu *vcpu) 485 { 486 return &(to_vmx(vcpu)->pi_desc); 487 } 488 489 struct vmcs *alloc_vmcs_cpu(bool shadow, int cpu, gfp_t flags); 490 void free_vmcs(struct vmcs *vmcs); 491 int alloc_loaded_vmcs(struct loaded_vmcs *loaded_vmcs); 492 void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs); 493 void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs); 494 void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs); 495 496 static inline struct vmcs *alloc_vmcs(bool shadow) 497 { 498 return alloc_vmcs_cpu(shadow, raw_smp_processor_id(), 499 GFP_KERNEL_ACCOUNT); 500 } 501 502 u64 construct_eptp(struct kvm_vcpu *vcpu, unsigned long root_hpa); 503 504 static inline void __vmx_flush_tlb(struct kvm_vcpu *vcpu, int vpid, 505 bool invalidate_gpa) 506 { 507 if (enable_ept && (invalidate_gpa || !enable_vpid)) { 508 if (!VALID_PAGE(vcpu->arch.mmu->root_hpa)) 509 return; 510 ept_sync_context(construct_eptp(vcpu, 511 vcpu->arch.mmu->root_hpa)); 512 } else { 513 vpid_sync_context(vpid); 514 } 515 } 516 517 static inline void vmx_flush_tlb(struct kvm_vcpu *vcpu, bool invalidate_gpa) 518 { 519 __vmx_flush_tlb(vcpu, to_vmx(vcpu)->vpid, invalidate_gpa); 520 } 521 522 static inline void decache_tsc_multiplier(struct vcpu_vmx *vmx) 523 { 524 vmx->current_tsc_ratio = vmx->vcpu.arch.tsc_scaling_ratio; 525 vmcs_write64(TSC_MULTIPLIER, vmx->current_tsc_ratio); 526 } 527 528 static inline bool vmx_has_waitpkg(struct vcpu_vmx *vmx) 529 { 530 return vmx->secondary_exec_control & 531 SECONDARY_EXEC_ENABLE_USR_WAIT_PAUSE; 532 } 533 534 void dump_vmcs(void); 535 536 #endif /* __KVM_X86_VMX_H */ 537