1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef __KVM_X86_VMX_H 3 #define __KVM_X86_VMX_H 4 5 #include <linux/kvm_host.h> 6 7 #include <asm/kvm.h> 8 #include <asm/intel_pt.h> 9 10 #include "capabilities.h" 11 #include "ops.h" 12 #include "vmcs.h" 13 14 extern const u32 vmx_msr_index[]; 15 extern u64 host_efer; 16 17 #define MSR_TYPE_R 1 18 #define MSR_TYPE_W 2 19 #define MSR_TYPE_RW 3 20 21 #define X2APIC_MSR(r) (APIC_BASE_MSR + ((r) >> 4)) 22 23 #ifdef CONFIG_X86_64 24 #define NR_SHARED_MSRS 7 25 #else 26 #define NR_SHARED_MSRS 4 27 #endif 28 29 #define NR_LOADSTORE_MSRS 8 30 31 struct vmx_msrs { 32 unsigned int nr; 33 struct vmx_msr_entry val[NR_LOADSTORE_MSRS]; 34 }; 35 36 struct shared_msr_entry { 37 unsigned index; 38 u64 data; 39 u64 mask; 40 }; 41 42 enum segment_cache_field { 43 SEG_FIELD_SEL = 0, 44 SEG_FIELD_BASE = 1, 45 SEG_FIELD_LIMIT = 2, 46 SEG_FIELD_AR = 3, 47 48 SEG_FIELD_NR = 4 49 }; 50 51 /* Posted-Interrupt Descriptor */ 52 struct pi_desc { 53 u32 pir[8]; /* Posted interrupt requested */ 54 union { 55 struct { 56 /* bit 256 - Outstanding Notification */ 57 u16 on : 1, 58 /* bit 257 - Suppress Notification */ 59 sn : 1, 60 /* bit 271:258 - Reserved */ 61 rsvd_1 : 14; 62 /* bit 279:272 - Notification Vector */ 63 u8 nv; 64 /* bit 287:280 - Reserved */ 65 u8 rsvd_2; 66 /* bit 319:288 - Notification Destination */ 67 u32 ndst; 68 }; 69 u64 control; 70 }; 71 u32 rsvd[6]; 72 } __aligned(64); 73 74 #define RTIT_ADDR_RANGE 4 75 76 struct pt_ctx { 77 u64 ctl; 78 u64 status; 79 u64 output_base; 80 u64 output_mask; 81 u64 cr3_match; 82 u64 addr_a[RTIT_ADDR_RANGE]; 83 u64 addr_b[RTIT_ADDR_RANGE]; 84 }; 85 86 struct pt_desc { 87 u64 ctl_bitmask; 88 u32 addr_range; 89 u32 caps[PT_CPUID_REGS_NUM * PT_CPUID_LEAVES]; 90 struct pt_ctx host; 91 struct pt_ctx guest; 92 }; 93 94 /* 95 * The nested_vmx structure is part of vcpu_vmx, and holds information we need 96 * for correct emulation of VMX (i.e., nested VMX) on this vcpu. 97 */ 98 struct nested_vmx { 99 /* Has the level1 guest done vmxon? */ 100 bool vmxon; 101 gpa_t vmxon_ptr; 102 bool pml_full; 103 104 /* The guest-physical address of the current VMCS L1 keeps for L2 */ 105 gpa_t current_vmptr; 106 /* 107 * Cache of the guest's VMCS, existing outside of guest memory. 108 * Loaded from guest memory during VMPTRLD. Flushed to guest 109 * memory during VMCLEAR and VMPTRLD. 110 */ 111 struct vmcs12 *cached_vmcs12; 112 /* 113 * Cache of the guest's shadow VMCS, existing outside of guest 114 * memory. Loaded from guest memory during VM entry. Flushed 115 * to guest memory during VM exit. 116 */ 117 struct vmcs12 *cached_shadow_vmcs12; 118 119 /* 120 * Indicates if the shadow vmcs or enlightened vmcs must be updated 121 * with the data held by struct vmcs12. 122 */ 123 bool need_vmcs12_to_shadow_sync; 124 bool dirty_vmcs12; 125 126 /* 127 * Indicates lazily loaded guest state has not yet been decached from 128 * vmcs02. 129 */ 130 bool need_sync_vmcs02_to_vmcs12_rare; 131 132 /* 133 * vmcs02 has been initialized, i.e. state that is constant for 134 * vmcs02 has been written to the backing VMCS. Initialization 135 * is delayed until L1 actually attempts to run a nested VM. 136 */ 137 bool vmcs02_initialized; 138 139 bool change_vmcs01_virtual_apic_mode; 140 141 /* 142 * Enlightened VMCS has been enabled. It does not mean that L1 has to 143 * use it. However, VMX features available to L1 will be limited based 144 * on what the enlightened VMCS supports. 145 */ 146 bool enlightened_vmcs_enabled; 147 148 /* L2 must run next, and mustn't decide to exit to L1. */ 149 bool nested_run_pending; 150 151 /* Pending MTF VM-exit into L1. */ 152 bool mtf_pending; 153 154 struct loaded_vmcs vmcs02; 155 156 /* 157 * Guest pages referred to in the vmcs02 with host-physical 158 * pointers, so we must keep them pinned while L2 runs. 159 */ 160 struct page *apic_access_page; 161 struct kvm_host_map virtual_apic_map; 162 struct kvm_host_map pi_desc_map; 163 164 struct kvm_host_map msr_bitmap_map; 165 166 struct pi_desc *pi_desc; 167 bool pi_pending; 168 u16 posted_intr_nv; 169 170 struct hrtimer preemption_timer; 171 bool preemption_timer_expired; 172 173 /* to migrate it to L2 if VM_ENTRY_LOAD_DEBUG_CONTROLS is off */ 174 u64 vmcs01_debugctl; 175 u64 vmcs01_guest_bndcfgs; 176 177 /* to migrate it to L1 if L2 writes to L1's CR8 directly */ 178 int l1_tpr_threshold; 179 180 u16 vpid02; 181 u16 last_vpid; 182 183 struct nested_vmx_msrs msrs; 184 185 /* SMM related state */ 186 struct { 187 /* in VMX operation on SMM entry? */ 188 bool vmxon; 189 /* in guest mode on SMM entry? */ 190 bool guest_mode; 191 } smm; 192 193 gpa_t hv_evmcs_vmptr; 194 struct kvm_host_map hv_evmcs_map; 195 struct hv_enlightened_vmcs *hv_evmcs; 196 }; 197 198 struct vcpu_vmx { 199 struct kvm_vcpu vcpu; 200 u8 fail; 201 u8 msr_bitmap_mode; 202 203 /* 204 * If true, host state has been stored in vmx->loaded_vmcs for 205 * the CPU registers that only need to be switched when transitioning 206 * to/from the kernel, and the registers have been loaded with guest 207 * values. If false, host state is loaded in the CPU registers 208 * and vmx->loaded_vmcs->host_state is invalid. 209 */ 210 bool guest_state_loaded; 211 212 u32 exit_intr_info; 213 u32 idt_vectoring_info; 214 ulong rflags; 215 216 struct shared_msr_entry guest_msrs[NR_SHARED_MSRS]; 217 int nmsrs; 218 int save_nmsrs; 219 bool guest_msrs_ready; 220 #ifdef CONFIG_X86_64 221 u64 msr_host_kernel_gs_base; 222 u64 msr_guest_kernel_gs_base; 223 #endif 224 225 u64 spec_ctrl; 226 u32 msr_ia32_umwait_control; 227 228 u32 secondary_exec_control; 229 230 /* 231 * loaded_vmcs points to the VMCS currently used in this vcpu. For a 232 * non-nested (L1) guest, it always points to vmcs01. For a nested 233 * guest (L2), it points to a different VMCS. 234 */ 235 struct loaded_vmcs vmcs01; 236 struct loaded_vmcs *loaded_vmcs; 237 238 struct msr_autoload { 239 struct vmx_msrs guest; 240 struct vmx_msrs host; 241 } msr_autoload; 242 243 struct msr_autostore { 244 struct vmx_msrs guest; 245 } msr_autostore; 246 247 struct { 248 int vm86_active; 249 ulong save_rflags; 250 struct kvm_segment segs[8]; 251 } rmode; 252 struct { 253 u32 bitmask; /* 4 bits per segment (1 bit per field) */ 254 struct kvm_save_segment { 255 u16 selector; 256 unsigned long base; 257 u32 limit; 258 u32 ar; 259 } seg[8]; 260 } segment_cache; 261 int vpid; 262 bool emulation_required; 263 264 u32 exit_reason; 265 266 /* Posted interrupt descriptor */ 267 struct pi_desc pi_desc; 268 269 /* Support for a guest hypervisor (nested VMX) */ 270 struct nested_vmx nested; 271 272 /* Dynamic PLE window. */ 273 unsigned int ple_window; 274 bool ple_window_dirty; 275 276 bool req_immediate_exit; 277 278 /* Support for PML */ 279 #define PML_ENTITY_NUM 512 280 struct page *pml_pg; 281 282 /* apic deadline value in host tsc */ 283 u64 hv_deadline_tsc; 284 285 u64 current_tsc_ratio; 286 287 u32 host_pkru; 288 289 unsigned long host_debugctlmsr; 290 291 /* 292 * Only bits masked by msr_ia32_feature_control_valid_bits can be set in 293 * msr_ia32_feature_control. FEAT_CTL_LOCKED is always included 294 * in msr_ia32_feature_control_valid_bits. 295 */ 296 u64 msr_ia32_feature_control; 297 u64 msr_ia32_feature_control_valid_bits; 298 u64 ept_pointer; 299 300 struct pt_desc pt_desc; 301 }; 302 303 enum ept_pointers_status { 304 EPT_POINTERS_CHECK = 0, 305 EPT_POINTERS_MATCH = 1, 306 EPT_POINTERS_MISMATCH = 2 307 }; 308 309 struct kvm_vmx { 310 struct kvm kvm; 311 312 unsigned int tss_addr; 313 bool ept_identity_pagetable_done; 314 gpa_t ept_identity_map_addr; 315 316 enum ept_pointers_status ept_pointers_match; 317 spinlock_t ept_pointer_lock; 318 }; 319 320 bool nested_vmx_allowed(struct kvm_vcpu *vcpu); 321 void vmx_vcpu_load_vmcs(struct kvm_vcpu *vcpu, int cpu); 322 void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu); 323 int allocate_vpid(void); 324 void free_vpid(int vpid); 325 void vmx_set_constant_host_state(struct vcpu_vmx *vmx); 326 void vmx_prepare_switch_to_guest(struct kvm_vcpu *vcpu); 327 void vmx_set_host_fs_gs(struct vmcs_host_state *host, u16 fs_sel, u16 gs_sel, 328 unsigned long fs_base, unsigned long gs_base); 329 int vmx_get_cpl(struct kvm_vcpu *vcpu); 330 unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu); 331 void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags); 332 u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu); 333 void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask); 334 void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer); 335 void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0); 336 void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3); 337 int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4); 338 void set_cr4_guest_host_mask(struct vcpu_vmx *vmx); 339 void ept_save_pdptrs(struct kvm_vcpu *vcpu); 340 void vmx_get_segment(struct kvm_vcpu *vcpu, struct kvm_segment *var, int seg); 341 void vmx_set_segment(struct kvm_vcpu *vcpu, struct kvm_segment *var, int seg); 342 u64 construct_eptp(struct kvm_vcpu *vcpu, unsigned long root_hpa); 343 void update_exception_bitmap(struct kvm_vcpu *vcpu); 344 void vmx_update_msr_bitmap(struct kvm_vcpu *vcpu); 345 bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu); 346 void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked); 347 void vmx_set_virtual_apic_mode(struct kvm_vcpu *vcpu); 348 struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr); 349 void pt_update_intercept_for_msr(struct vcpu_vmx *vmx); 350 void vmx_update_host_rsp(struct vcpu_vmx *vmx, unsigned long host_rsp); 351 int vmx_find_msr_index(struct vmx_msrs *m, u32 msr); 352 353 #define POSTED_INTR_ON 0 354 #define POSTED_INTR_SN 1 355 356 static inline bool pi_test_and_set_on(struct pi_desc *pi_desc) 357 { 358 return test_and_set_bit(POSTED_INTR_ON, 359 (unsigned long *)&pi_desc->control); 360 } 361 362 static inline bool pi_test_and_clear_on(struct pi_desc *pi_desc) 363 { 364 return test_and_clear_bit(POSTED_INTR_ON, 365 (unsigned long *)&pi_desc->control); 366 } 367 368 static inline int pi_test_and_set_pir(int vector, struct pi_desc *pi_desc) 369 { 370 return test_and_set_bit(vector, (unsigned long *)pi_desc->pir); 371 } 372 373 static inline bool pi_is_pir_empty(struct pi_desc *pi_desc) 374 { 375 return bitmap_empty((unsigned long *)pi_desc->pir, NR_VECTORS); 376 } 377 378 static inline void pi_set_sn(struct pi_desc *pi_desc) 379 { 380 set_bit(POSTED_INTR_SN, 381 (unsigned long *)&pi_desc->control); 382 } 383 384 static inline void pi_set_on(struct pi_desc *pi_desc) 385 { 386 set_bit(POSTED_INTR_ON, 387 (unsigned long *)&pi_desc->control); 388 } 389 390 static inline void pi_clear_on(struct pi_desc *pi_desc) 391 { 392 clear_bit(POSTED_INTR_ON, 393 (unsigned long *)&pi_desc->control); 394 } 395 396 static inline void pi_clear_sn(struct pi_desc *pi_desc) 397 { 398 clear_bit(POSTED_INTR_SN, 399 (unsigned long *)&pi_desc->control); 400 } 401 402 static inline int pi_test_on(struct pi_desc *pi_desc) 403 { 404 return test_bit(POSTED_INTR_ON, 405 (unsigned long *)&pi_desc->control); 406 } 407 408 static inline int pi_test_sn(struct pi_desc *pi_desc) 409 { 410 return test_bit(POSTED_INTR_SN, 411 (unsigned long *)&pi_desc->control); 412 } 413 414 static inline u8 vmx_get_rvi(void) 415 { 416 return vmcs_read16(GUEST_INTR_STATUS) & 0xff; 417 } 418 419 #define BUILD_CONTROLS_SHADOW(lname, uname) \ 420 static inline void lname##_controls_set(struct vcpu_vmx *vmx, u32 val) \ 421 { \ 422 if (vmx->loaded_vmcs->controls_shadow.lname != val) { \ 423 vmcs_write32(uname, val); \ 424 vmx->loaded_vmcs->controls_shadow.lname = val; \ 425 } \ 426 } \ 427 static inline u32 lname##_controls_get(struct vcpu_vmx *vmx) \ 428 { \ 429 return vmx->loaded_vmcs->controls_shadow.lname; \ 430 } \ 431 static inline void lname##_controls_setbit(struct vcpu_vmx *vmx, u32 val) \ 432 { \ 433 lname##_controls_set(vmx, lname##_controls_get(vmx) | val); \ 434 } \ 435 static inline void lname##_controls_clearbit(struct vcpu_vmx *vmx, u32 val) \ 436 { \ 437 lname##_controls_set(vmx, lname##_controls_get(vmx) & ~val); \ 438 } 439 BUILD_CONTROLS_SHADOW(vm_entry, VM_ENTRY_CONTROLS) 440 BUILD_CONTROLS_SHADOW(vm_exit, VM_EXIT_CONTROLS) 441 BUILD_CONTROLS_SHADOW(pin, PIN_BASED_VM_EXEC_CONTROL) 442 BUILD_CONTROLS_SHADOW(exec, CPU_BASED_VM_EXEC_CONTROL) 443 BUILD_CONTROLS_SHADOW(secondary_exec, SECONDARY_VM_EXEC_CONTROL) 444 445 static inline void vmx_segment_cache_clear(struct vcpu_vmx *vmx) 446 { 447 vmx->segment_cache.bitmask = 0; 448 } 449 450 static inline u32 vmx_vmentry_ctrl(void) 451 { 452 u32 vmentry_ctrl = vmcs_config.vmentry_ctrl; 453 if (pt_mode == PT_MODE_SYSTEM) 454 vmentry_ctrl &= ~(VM_ENTRY_PT_CONCEAL_PIP | 455 VM_ENTRY_LOAD_IA32_RTIT_CTL); 456 /* Loading of EFER and PERF_GLOBAL_CTRL are toggled dynamically */ 457 return vmentry_ctrl & 458 ~(VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VM_ENTRY_LOAD_IA32_EFER); 459 } 460 461 static inline u32 vmx_vmexit_ctrl(void) 462 { 463 u32 vmexit_ctrl = vmcs_config.vmexit_ctrl; 464 if (pt_mode == PT_MODE_SYSTEM) 465 vmexit_ctrl &= ~(VM_EXIT_PT_CONCEAL_PIP | 466 VM_EXIT_CLEAR_IA32_RTIT_CTL); 467 /* Loading of EFER and PERF_GLOBAL_CTRL are toggled dynamically */ 468 return vmexit_ctrl & 469 ~(VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | VM_EXIT_LOAD_IA32_EFER); 470 } 471 472 u32 vmx_exec_control(struct vcpu_vmx *vmx); 473 u32 vmx_pin_based_exec_ctrl(struct vcpu_vmx *vmx); 474 475 static inline struct kvm_vmx *to_kvm_vmx(struct kvm *kvm) 476 { 477 return container_of(kvm, struct kvm_vmx, kvm); 478 } 479 480 static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu) 481 { 482 return container_of(vcpu, struct vcpu_vmx, vcpu); 483 } 484 485 static inline struct pi_desc *vcpu_to_pi_desc(struct kvm_vcpu *vcpu) 486 { 487 return &(to_vmx(vcpu)->pi_desc); 488 } 489 490 struct vmcs *alloc_vmcs_cpu(bool shadow, int cpu, gfp_t flags); 491 void free_vmcs(struct vmcs *vmcs); 492 int alloc_loaded_vmcs(struct loaded_vmcs *loaded_vmcs); 493 void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs); 494 void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs); 495 void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs); 496 497 static inline struct vmcs *alloc_vmcs(bool shadow) 498 { 499 return alloc_vmcs_cpu(shadow, raw_smp_processor_id(), 500 GFP_KERNEL_ACCOUNT); 501 } 502 503 u64 construct_eptp(struct kvm_vcpu *vcpu, unsigned long root_hpa); 504 505 static inline void __vmx_flush_tlb(struct kvm_vcpu *vcpu, int vpid, 506 bool invalidate_gpa) 507 { 508 if (enable_ept && (invalidate_gpa || !enable_vpid)) { 509 if (!VALID_PAGE(vcpu->arch.mmu->root_hpa)) 510 return; 511 ept_sync_context(construct_eptp(vcpu, 512 vcpu->arch.mmu->root_hpa)); 513 } else { 514 vpid_sync_context(vpid); 515 } 516 } 517 518 static inline void vmx_flush_tlb(struct kvm_vcpu *vcpu, bool invalidate_gpa) 519 { 520 __vmx_flush_tlb(vcpu, to_vmx(vcpu)->vpid, invalidate_gpa); 521 } 522 523 static inline void decache_tsc_multiplier(struct vcpu_vmx *vmx) 524 { 525 vmx->current_tsc_ratio = vmx->vcpu.arch.tsc_scaling_ratio; 526 vmcs_write64(TSC_MULTIPLIER, vmx->current_tsc_ratio); 527 } 528 529 static inline bool vmx_has_waitpkg(struct vcpu_vmx *vmx) 530 { 531 return vmx->secondary_exec_control & 532 SECONDARY_EXEC_ENABLE_USR_WAIT_PAUSE; 533 } 534 535 void dump_vmcs(void); 536 537 #endif /* __KVM_X86_VMX_H */ 538