1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef __KVM_X86_VMX_H 3 #define __KVM_X86_VMX_H 4 5 #include <linux/kvm_host.h> 6 7 #include <asm/kvm.h> 8 #include <asm/intel_pt.h> 9 #include <asm/perf_event.h> 10 #include <asm/posted_intr.h> 11 12 #include "capabilities.h" 13 #include "../kvm_cache_regs.h" 14 #include "pmu_intel.h" 15 #include "vmcs.h" 16 #include "vmx_ops.h" 17 #include "../cpuid.h" 18 #include "run_flags.h" 19 #include "../mmu.h" 20 #include "common.h" 21 22 #define X2APIC_MSR(r) (APIC_BASE_MSR + ((r) >> 4)) 23 24 #ifdef CONFIG_X86_64 25 #define MAX_NR_USER_RETURN_MSRS 7 26 #else 27 #define MAX_NR_USER_RETURN_MSRS 4 28 #endif 29 30 #define MAX_NR_LOADSTORE_MSRS 8 31 32 struct vmx_msrs { 33 unsigned int nr; 34 struct vmx_msr_entry val[MAX_NR_LOADSTORE_MSRS]; 35 }; 36 37 struct vmx_uret_msr { 38 bool load_into_hardware; 39 u64 data; 40 u64 mask; 41 }; 42 43 enum segment_cache_field { 44 SEG_FIELD_SEL = 0, 45 SEG_FIELD_BASE = 1, 46 SEG_FIELD_LIMIT = 2, 47 SEG_FIELD_AR = 3, 48 49 SEG_FIELD_NR = 4 50 }; 51 52 #define RTIT_ADDR_RANGE 4 53 54 struct pt_ctx { 55 u64 ctl; 56 u64 status; 57 u64 output_base; 58 u64 output_mask; 59 u64 cr3_match; 60 u64 addr_a[RTIT_ADDR_RANGE]; 61 u64 addr_b[RTIT_ADDR_RANGE]; 62 }; 63 64 struct pt_desc { 65 u64 ctl_bitmask; 66 u32 num_address_ranges; 67 u32 caps[PT_CPUID_REGS_NUM * PT_CPUID_LEAVES]; 68 struct pt_ctx host; 69 struct pt_ctx guest; 70 }; 71 72 /* 73 * The nested_vmx structure is part of vcpu_vmx, and holds information we need 74 * for correct emulation of VMX (i.e., nested VMX) on this vcpu. 75 */ 76 struct nested_vmx { 77 /* Has the level1 guest done vmxon? */ 78 bool vmxon; 79 gpa_t vmxon_ptr; 80 bool pml_full; 81 82 /* The guest-physical address of the current VMCS L1 keeps for L2 */ 83 gpa_t current_vmptr; 84 /* 85 * Cache of the guest's VMCS, existing outside of guest memory. 86 * Loaded from guest memory during VMPTRLD. Flushed to guest 87 * memory during VMCLEAR and VMPTRLD. 88 */ 89 struct vmcs12 *cached_vmcs12; 90 /* 91 * Cache of the guest's shadow VMCS, existing outside of guest 92 * memory. Loaded from guest memory during VM entry. Flushed 93 * to guest memory during VM exit. 94 */ 95 struct vmcs12 *cached_shadow_vmcs12; 96 97 /* 98 * GPA to HVA cache for accessing vmcs12->vmcs_link_pointer 99 */ 100 struct gfn_to_hva_cache shadow_vmcs12_cache; 101 102 /* 103 * GPA to HVA cache for VMCS12 104 */ 105 struct gfn_to_hva_cache vmcs12_cache; 106 107 /* 108 * Indicates if the shadow vmcs or enlightened vmcs must be updated 109 * with the data held by struct vmcs12. 110 */ 111 bool need_vmcs12_to_shadow_sync; 112 bool dirty_vmcs12; 113 114 /* 115 * Indicates whether MSR bitmap for L2 needs to be rebuilt due to 116 * changes in MSR bitmap for L1 or switching to a different L2. Note, 117 * this flag can only be used reliably in conjunction with a paravirt L1 118 * which informs L0 whether any changes to MSR bitmap for L2 were done 119 * on its side. 120 */ 121 bool force_msr_bitmap_recalc; 122 123 /* 124 * Indicates lazily loaded guest state has not yet been decached from 125 * vmcs02. 126 */ 127 bool need_sync_vmcs02_to_vmcs12_rare; 128 129 /* 130 * vmcs02 has been initialized, i.e. state that is constant for 131 * vmcs02 has been written to the backing VMCS. Initialization 132 * is delayed until L1 actually attempts to run a nested VM. 133 */ 134 bool vmcs02_initialized; 135 136 bool change_vmcs01_virtual_apic_mode; 137 bool reload_vmcs01_apic_access_page; 138 bool update_vmcs01_cpu_dirty_logging; 139 bool update_vmcs01_apicv_status; 140 bool update_vmcs01_hwapic_isr; 141 142 /* 143 * Enlightened VMCS has been enabled. It does not mean that L1 has to 144 * use it. However, VMX features available to L1 will be limited based 145 * on what the enlightened VMCS supports. 146 */ 147 bool enlightened_vmcs_enabled; 148 149 /* L2 must run next, and mustn't decide to exit to L1. */ 150 bool nested_run_pending; 151 152 /* Pending MTF VM-exit into L1. */ 153 bool mtf_pending; 154 155 struct loaded_vmcs vmcs02; 156 157 /* 158 * Guest pages referred to in the vmcs02 with host-physical 159 * pointers, so we must keep them pinned while L2 runs. 160 */ 161 struct kvm_host_map apic_access_page_map; 162 struct kvm_host_map virtual_apic_map; 163 struct kvm_host_map pi_desc_map; 164 165 struct pi_desc *pi_desc; 166 bool pi_pending; 167 u16 posted_intr_nv; 168 169 struct hrtimer preemption_timer; 170 u64 preemption_timer_deadline; 171 bool has_preemption_timer_deadline; 172 bool preemption_timer_expired; 173 174 /* 175 * Used to snapshot MSRs that are conditionally loaded on VM-Enter in 176 * order to propagate the guest's pre-VM-Enter value into vmcs02. For 177 * emulation of VMLAUNCH/VMRESUME, the snapshot will be of L1's value. 178 * For KVM_SET_NESTED_STATE, the snapshot is of L2's value, _if_ 179 * userspace restores MSRs before nested state. If userspace restores 180 * MSRs after nested state, the snapshot holds garbage, but KVM can't 181 * detect that, and the garbage value in vmcs02 will be overwritten by 182 * MSR restoration in any case. 183 */ 184 u64 pre_vmenter_debugctl; 185 u64 pre_vmenter_bndcfgs; 186 187 /* to migrate it to L1 if L2 writes to L1's CR8 directly */ 188 int l1_tpr_threshold; 189 190 u16 vpid02; 191 u16 last_vpid; 192 193 struct nested_vmx_msrs msrs; 194 195 /* SMM related state */ 196 struct { 197 /* in VMX operation on SMM entry? */ 198 bool vmxon; 199 /* in guest mode on SMM entry? */ 200 bool guest_mode; 201 } smm; 202 203 #ifdef CONFIG_KVM_HYPERV 204 gpa_t hv_evmcs_vmptr; 205 struct kvm_host_map hv_evmcs_map; 206 struct hv_enlightened_vmcs *hv_evmcs; 207 #endif 208 }; 209 210 struct vcpu_vmx { 211 struct kvm_vcpu vcpu; 212 struct vcpu_vt vt; 213 u8 fail; 214 u8 x2apic_msr_bitmap_mode; 215 216 u32 idt_vectoring_info; 217 ulong rflags; 218 219 /* 220 * User return MSRs are always emulated when enabled in the guest, but 221 * only loaded into hardware when necessary, e.g. SYSCALL #UDs outside 222 * of 64-bit mode or if EFER.SCE=1, thus the SYSCALL MSRs don't need to 223 * be loaded into hardware if those conditions aren't met. 224 */ 225 struct vmx_uret_msr guest_uret_msrs[MAX_NR_USER_RETURN_MSRS]; 226 bool guest_uret_msrs_loaded; 227 #ifdef CONFIG_X86_64 228 u64 msr_guest_kernel_gs_base; 229 #endif 230 231 u64 spec_ctrl; 232 u32 msr_ia32_umwait_control; 233 234 /* 235 * loaded_vmcs points to the VMCS currently used in this vcpu. For a 236 * non-nested (L1) guest, it always points to vmcs01. For a nested 237 * guest (L2), it points to a different VMCS. 238 */ 239 struct loaded_vmcs vmcs01; 240 struct loaded_vmcs *loaded_vmcs; 241 242 struct msr_autoload { 243 struct vmx_msrs guest; 244 struct vmx_msrs host; 245 } msr_autoload; 246 247 struct msr_autostore { 248 struct vmx_msrs guest; 249 } msr_autostore; 250 251 struct { 252 int vm86_active; 253 ulong save_rflags; 254 struct kvm_segment segs[8]; 255 } rmode; 256 struct { 257 u32 bitmask; /* 4 bits per segment (1 bit per field) */ 258 struct kvm_save_segment { 259 u16 selector; 260 unsigned long base; 261 u32 limit; 262 u32 ar; 263 } seg[8]; 264 } segment_cache; 265 int vpid; 266 267 /* Support for a guest hypervisor (nested VMX) */ 268 struct nested_vmx nested; 269 270 /* Dynamic PLE window. */ 271 unsigned int ple_window; 272 bool ple_window_dirty; 273 274 /* Support for PML */ 275 #define PML_LOG_NR_ENTRIES 512 276 /* PML is written backwards: this is the first entry written by the CPU */ 277 #define PML_HEAD_INDEX (PML_LOG_NR_ENTRIES-1) 278 279 struct page *pml_pg; 280 281 /* apic deadline value in host tsc */ 282 u64 hv_deadline_tsc; 283 284 /* 285 * Only bits masked by msr_ia32_feature_control_valid_bits can be set in 286 * msr_ia32_feature_control. FEAT_CTL_LOCKED is always included 287 * in msr_ia32_feature_control_valid_bits. 288 */ 289 u64 msr_ia32_feature_control; 290 u64 msr_ia32_feature_control_valid_bits; 291 /* SGX Launch Control public key hash */ 292 u64 msr_ia32_sgxlepubkeyhash[4]; 293 u64 msr_ia32_mcu_opt_ctrl; 294 bool disable_fb_clear; 295 296 struct pt_desc pt_desc; 297 struct lbr_desc lbr_desc; 298 299 /* Save desired MSR intercept (read: pass-through) state */ 300 #define MAX_POSSIBLE_PASSTHROUGH_MSRS 16 301 struct { 302 DECLARE_BITMAP(read, MAX_POSSIBLE_PASSTHROUGH_MSRS); 303 DECLARE_BITMAP(write, MAX_POSSIBLE_PASSTHROUGH_MSRS); 304 } shadow_msr_intercept; 305 306 /* ve_info must be page aligned. */ 307 struct vmx_ve_information *ve_info; 308 }; 309 310 struct kvm_vmx { 311 struct kvm kvm; 312 313 unsigned int tss_addr; 314 bool ept_identity_pagetable_done; 315 gpa_t ept_identity_map_addr; 316 /* Posted Interrupt Descriptor (PID) table for IPI virtualization */ 317 u64 *pid_table; 318 }; 319 320 static __always_inline struct vcpu_vt *to_vt(struct kvm_vcpu *vcpu) 321 { 322 return &(container_of(vcpu, struct vcpu_vmx, vcpu)->vt); 323 } 324 325 static __always_inline struct kvm_vcpu *vt_to_vcpu(struct vcpu_vt *vt) 326 { 327 return &(container_of(vt, struct vcpu_vmx, vt)->vcpu); 328 } 329 330 static __always_inline union vmx_exit_reason vmx_get_exit_reason(struct kvm_vcpu *vcpu) 331 { 332 return to_vt(vcpu)->exit_reason; 333 } 334 335 static __always_inline unsigned long vmx_get_exit_qual(struct kvm_vcpu *vcpu) 336 { 337 struct vcpu_vt *vt = to_vt(vcpu); 338 339 if (!kvm_register_test_and_mark_available(vcpu, VCPU_EXREG_EXIT_INFO_1) && 340 !WARN_ON_ONCE(is_td_vcpu(vcpu))) 341 vt->exit_qualification = vmcs_readl(EXIT_QUALIFICATION); 342 343 return vt->exit_qualification; 344 } 345 346 static __always_inline u32 vmx_get_intr_info(struct kvm_vcpu *vcpu) 347 { 348 struct vcpu_vt *vt = to_vt(vcpu); 349 350 if (!kvm_register_test_and_mark_available(vcpu, VCPU_EXREG_EXIT_INFO_2) && 351 !WARN_ON_ONCE(is_td_vcpu(vcpu))) 352 vt->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO); 353 354 return vt->exit_intr_info; 355 } 356 357 void vmx_vcpu_load_vmcs(struct kvm_vcpu *vcpu, int cpu); 358 int allocate_vpid(void); 359 void free_vpid(int vpid); 360 void vmx_set_constant_host_state(struct vcpu_vmx *vmx); 361 void vmx_prepare_switch_to_guest(struct kvm_vcpu *vcpu); 362 void vmx_set_host_fs_gs(struct vmcs_host_state *host, u16 fs_sel, u16 gs_sel, 363 unsigned long fs_base, unsigned long gs_base); 364 int vmx_get_cpl(struct kvm_vcpu *vcpu); 365 int vmx_get_cpl_no_cache(struct kvm_vcpu *vcpu); 366 bool vmx_emulation_required(struct kvm_vcpu *vcpu); 367 unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu); 368 void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags); 369 u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu); 370 void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask); 371 int vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer); 372 void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0); 373 void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4); 374 void set_cr4_guest_host_mask(struct vcpu_vmx *vmx); 375 void ept_save_pdptrs(struct kvm_vcpu *vcpu); 376 void vmx_get_segment(struct kvm_vcpu *vcpu, struct kvm_segment *var, int seg); 377 void __vmx_set_segment(struct kvm_vcpu *vcpu, struct kvm_segment *var, int seg); 378 u64 construct_eptp(struct kvm_vcpu *vcpu, hpa_t root_hpa, int root_level); 379 380 bool vmx_guest_inject_ac(struct kvm_vcpu *vcpu); 381 void vmx_update_exception_bitmap(struct kvm_vcpu *vcpu); 382 bool vmx_nmi_blocked(struct kvm_vcpu *vcpu); 383 bool __vmx_interrupt_blocked(struct kvm_vcpu *vcpu); 384 bool vmx_interrupt_blocked(struct kvm_vcpu *vcpu); 385 bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu); 386 void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked); 387 void vmx_set_virtual_apic_mode(struct kvm_vcpu *vcpu); 388 struct vmx_uret_msr *vmx_find_uret_msr(struct vcpu_vmx *vmx, u32 msr); 389 void pt_update_intercept_for_msr(struct kvm_vcpu *vcpu); 390 void vmx_update_host_rsp(struct vcpu_vmx *vmx, unsigned long host_rsp); 391 void vmx_spec_ctrl_restore_host(struct vcpu_vmx *vmx, unsigned int flags); 392 unsigned int __vmx_vcpu_run_flags(struct vcpu_vmx *vmx); 393 bool __vmx_vcpu_run(struct vcpu_vmx *vmx, unsigned long *regs, 394 unsigned int flags); 395 int vmx_find_loadstore_msr_slot(struct vmx_msrs *m, u32 msr); 396 void vmx_ept_load_pdptrs(struct kvm_vcpu *vcpu); 397 398 void vmx_disable_intercept_for_msr(struct kvm_vcpu *vcpu, u32 msr, int type); 399 void vmx_enable_intercept_for_msr(struct kvm_vcpu *vcpu, u32 msr, int type); 400 401 u64 vmx_get_l2_tsc_offset(struct kvm_vcpu *vcpu); 402 u64 vmx_get_l2_tsc_multiplier(struct kvm_vcpu *vcpu); 403 404 gva_t vmx_get_untagged_addr(struct kvm_vcpu *vcpu, gva_t gva, unsigned int flags); 405 406 static inline void vmx_set_intercept_for_msr(struct kvm_vcpu *vcpu, u32 msr, 407 int type, bool value) 408 { 409 if (value) 410 vmx_enable_intercept_for_msr(vcpu, msr, type); 411 else 412 vmx_disable_intercept_for_msr(vcpu, msr, type); 413 } 414 415 void vmx_update_cpu_dirty_logging(struct kvm_vcpu *vcpu); 416 417 /* 418 * Note, early Intel manuals have the write-low and read-high bitmap offsets 419 * the wrong way round. The bitmaps control MSRs 0x00000000-0x00001fff and 420 * 0xc0000000-0xc0001fff. The former (low) uses bytes 0-0x3ff for reads and 421 * 0x800-0xbff for writes. The latter (high) uses 0x400-0x7ff for reads and 422 * 0xc00-0xfff for writes. MSRs not covered by either of the ranges always 423 * VM-Exit. 424 */ 425 #define __BUILD_VMX_MSR_BITMAP_HELPER(rtype, action, bitop, access, base) \ 426 static inline rtype vmx_##action##_msr_bitmap_##access(unsigned long *bitmap, \ 427 u32 msr) \ 428 { \ 429 int f = sizeof(unsigned long); \ 430 \ 431 if (msr <= 0x1fff) \ 432 return bitop##_bit(msr, bitmap + base / f); \ 433 else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) \ 434 return bitop##_bit(msr & 0x1fff, bitmap + (base + 0x400) / f); \ 435 return (rtype)true; \ 436 } 437 #define BUILD_VMX_MSR_BITMAP_HELPERS(ret_type, action, bitop) \ 438 __BUILD_VMX_MSR_BITMAP_HELPER(ret_type, action, bitop, read, 0x0) \ 439 __BUILD_VMX_MSR_BITMAP_HELPER(ret_type, action, bitop, write, 0x800) 440 441 BUILD_VMX_MSR_BITMAP_HELPERS(bool, test, test) 442 BUILD_VMX_MSR_BITMAP_HELPERS(void, clear, __clear) 443 BUILD_VMX_MSR_BITMAP_HELPERS(void, set, __set) 444 445 static inline u8 vmx_get_rvi(void) 446 { 447 return vmcs_read16(GUEST_INTR_STATUS) & 0xff; 448 } 449 450 #define __KVM_REQUIRED_VMX_VM_ENTRY_CONTROLS \ 451 (VM_ENTRY_LOAD_DEBUG_CONTROLS) 452 #ifdef CONFIG_X86_64 453 #define KVM_REQUIRED_VMX_VM_ENTRY_CONTROLS \ 454 (__KVM_REQUIRED_VMX_VM_ENTRY_CONTROLS | \ 455 VM_ENTRY_IA32E_MODE) 456 #else 457 #define KVM_REQUIRED_VMX_VM_ENTRY_CONTROLS \ 458 __KVM_REQUIRED_VMX_VM_ENTRY_CONTROLS 459 #endif 460 #define KVM_OPTIONAL_VMX_VM_ENTRY_CONTROLS \ 461 (VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | \ 462 VM_ENTRY_LOAD_IA32_PAT | \ 463 VM_ENTRY_LOAD_IA32_EFER | \ 464 VM_ENTRY_LOAD_BNDCFGS | \ 465 VM_ENTRY_PT_CONCEAL_PIP | \ 466 VM_ENTRY_LOAD_IA32_RTIT_CTL) 467 468 #define __KVM_REQUIRED_VMX_VM_EXIT_CONTROLS \ 469 (VM_EXIT_SAVE_DEBUG_CONTROLS | \ 470 VM_EXIT_ACK_INTR_ON_EXIT) 471 #ifdef CONFIG_X86_64 472 #define KVM_REQUIRED_VMX_VM_EXIT_CONTROLS \ 473 (__KVM_REQUIRED_VMX_VM_EXIT_CONTROLS | \ 474 VM_EXIT_HOST_ADDR_SPACE_SIZE) 475 #else 476 #define KVM_REQUIRED_VMX_VM_EXIT_CONTROLS \ 477 __KVM_REQUIRED_VMX_VM_EXIT_CONTROLS 478 #endif 479 #define KVM_OPTIONAL_VMX_VM_EXIT_CONTROLS \ 480 (VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | \ 481 VM_EXIT_SAVE_IA32_PAT | \ 482 VM_EXIT_LOAD_IA32_PAT | \ 483 VM_EXIT_SAVE_IA32_EFER | \ 484 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER | \ 485 VM_EXIT_LOAD_IA32_EFER | \ 486 VM_EXIT_CLEAR_BNDCFGS | \ 487 VM_EXIT_PT_CONCEAL_PIP | \ 488 VM_EXIT_CLEAR_IA32_RTIT_CTL) 489 490 #define KVM_REQUIRED_VMX_PIN_BASED_VM_EXEC_CONTROL \ 491 (PIN_BASED_EXT_INTR_MASK | \ 492 PIN_BASED_NMI_EXITING) 493 #define KVM_OPTIONAL_VMX_PIN_BASED_VM_EXEC_CONTROL \ 494 (PIN_BASED_VIRTUAL_NMIS | \ 495 PIN_BASED_POSTED_INTR | \ 496 PIN_BASED_VMX_PREEMPTION_TIMER) 497 498 #define __KVM_REQUIRED_VMX_CPU_BASED_VM_EXEC_CONTROL \ 499 (CPU_BASED_HLT_EXITING | \ 500 CPU_BASED_CR3_LOAD_EXITING | \ 501 CPU_BASED_CR3_STORE_EXITING | \ 502 CPU_BASED_UNCOND_IO_EXITING | \ 503 CPU_BASED_MOV_DR_EXITING | \ 504 CPU_BASED_USE_TSC_OFFSETTING | \ 505 CPU_BASED_MWAIT_EXITING | \ 506 CPU_BASED_MONITOR_EXITING | \ 507 CPU_BASED_INVLPG_EXITING | \ 508 CPU_BASED_RDPMC_EXITING | \ 509 CPU_BASED_INTR_WINDOW_EXITING) 510 511 #ifdef CONFIG_X86_64 512 #define KVM_REQUIRED_VMX_CPU_BASED_VM_EXEC_CONTROL \ 513 (__KVM_REQUIRED_VMX_CPU_BASED_VM_EXEC_CONTROL | \ 514 CPU_BASED_CR8_LOAD_EXITING | \ 515 CPU_BASED_CR8_STORE_EXITING) 516 #else 517 #define KVM_REQUIRED_VMX_CPU_BASED_VM_EXEC_CONTROL \ 518 __KVM_REQUIRED_VMX_CPU_BASED_VM_EXEC_CONTROL 519 #endif 520 521 #define KVM_OPTIONAL_VMX_CPU_BASED_VM_EXEC_CONTROL \ 522 (CPU_BASED_RDTSC_EXITING | \ 523 CPU_BASED_TPR_SHADOW | \ 524 CPU_BASED_USE_IO_BITMAPS | \ 525 CPU_BASED_MONITOR_TRAP_FLAG | \ 526 CPU_BASED_USE_MSR_BITMAPS | \ 527 CPU_BASED_NMI_WINDOW_EXITING | \ 528 CPU_BASED_PAUSE_EXITING | \ 529 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS | \ 530 CPU_BASED_ACTIVATE_TERTIARY_CONTROLS) 531 532 #define KVM_REQUIRED_VMX_SECONDARY_VM_EXEC_CONTROL 0 533 #define KVM_OPTIONAL_VMX_SECONDARY_VM_EXEC_CONTROL \ 534 (SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | \ 535 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | \ 536 SECONDARY_EXEC_WBINVD_EXITING | \ 537 SECONDARY_EXEC_ENABLE_VPID | \ 538 SECONDARY_EXEC_ENABLE_EPT | \ 539 SECONDARY_EXEC_UNRESTRICTED_GUEST | \ 540 SECONDARY_EXEC_PAUSE_LOOP_EXITING | \ 541 SECONDARY_EXEC_DESC | \ 542 SECONDARY_EXEC_ENABLE_RDTSCP | \ 543 SECONDARY_EXEC_ENABLE_INVPCID | \ 544 SECONDARY_EXEC_APIC_REGISTER_VIRT | \ 545 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | \ 546 SECONDARY_EXEC_SHADOW_VMCS | \ 547 SECONDARY_EXEC_ENABLE_XSAVES | \ 548 SECONDARY_EXEC_RDSEED_EXITING | \ 549 SECONDARY_EXEC_RDRAND_EXITING | \ 550 SECONDARY_EXEC_ENABLE_PML | \ 551 SECONDARY_EXEC_TSC_SCALING | \ 552 SECONDARY_EXEC_ENABLE_USR_WAIT_PAUSE | \ 553 SECONDARY_EXEC_PT_USE_GPA | \ 554 SECONDARY_EXEC_PT_CONCEAL_VMX | \ 555 SECONDARY_EXEC_ENABLE_VMFUNC | \ 556 SECONDARY_EXEC_BUS_LOCK_DETECTION | \ 557 SECONDARY_EXEC_NOTIFY_VM_EXITING | \ 558 SECONDARY_EXEC_ENCLS_EXITING | \ 559 SECONDARY_EXEC_EPT_VIOLATION_VE) 560 561 #define KVM_REQUIRED_VMX_TERTIARY_VM_EXEC_CONTROL 0 562 #define KVM_OPTIONAL_VMX_TERTIARY_VM_EXEC_CONTROL \ 563 (TERTIARY_EXEC_IPI_VIRT) 564 565 #define BUILD_CONTROLS_SHADOW(lname, uname, bits) \ 566 static inline void lname##_controls_set(struct vcpu_vmx *vmx, u##bits val) \ 567 { \ 568 if (vmx->loaded_vmcs->controls_shadow.lname != val) { \ 569 vmcs_write##bits(uname, val); \ 570 vmx->loaded_vmcs->controls_shadow.lname = val; \ 571 } \ 572 } \ 573 static inline u##bits __##lname##_controls_get(struct loaded_vmcs *vmcs) \ 574 { \ 575 return vmcs->controls_shadow.lname; \ 576 } \ 577 static inline u##bits lname##_controls_get(struct vcpu_vmx *vmx) \ 578 { \ 579 return __##lname##_controls_get(vmx->loaded_vmcs); \ 580 } \ 581 static __always_inline void lname##_controls_setbit(struct vcpu_vmx *vmx, u##bits val) \ 582 { \ 583 BUILD_BUG_ON(!(val & (KVM_REQUIRED_VMX_##uname | KVM_OPTIONAL_VMX_##uname))); \ 584 lname##_controls_set(vmx, lname##_controls_get(vmx) | val); \ 585 } \ 586 static __always_inline void lname##_controls_clearbit(struct vcpu_vmx *vmx, u##bits val) \ 587 { \ 588 BUILD_BUG_ON(!(val & (KVM_REQUIRED_VMX_##uname | KVM_OPTIONAL_VMX_##uname))); \ 589 lname##_controls_set(vmx, lname##_controls_get(vmx) & ~val); \ 590 } 591 BUILD_CONTROLS_SHADOW(vm_entry, VM_ENTRY_CONTROLS, 32) 592 BUILD_CONTROLS_SHADOW(vm_exit, VM_EXIT_CONTROLS, 32) 593 BUILD_CONTROLS_SHADOW(pin, PIN_BASED_VM_EXEC_CONTROL, 32) 594 BUILD_CONTROLS_SHADOW(exec, CPU_BASED_VM_EXEC_CONTROL, 32) 595 BUILD_CONTROLS_SHADOW(secondary_exec, SECONDARY_VM_EXEC_CONTROL, 32) 596 BUILD_CONTROLS_SHADOW(tertiary_exec, TERTIARY_VM_EXEC_CONTROL, 64) 597 598 /* 599 * VMX_REGS_LAZY_LOAD_SET - The set of registers that will be updated in the 600 * cache on demand. Other registers not listed here are synced to 601 * the cache immediately after VM-Exit. 602 */ 603 #define VMX_REGS_LAZY_LOAD_SET ((1 << VCPU_REGS_RIP) | \ 604 (1 << VCPU_REGS_RSP) | \ 605 (1 << VCPU_EXREG_RFLAGS) | \ 606 (1 << VCPU_EXREG_PDPTR) | \ 607 (1 << VCPU_EXREG_SEGMENTS) | \ 608 (1 << VCPU_EXREG_CR0) | \ 609 (1 << VCPU_EXREG_CR3) | \ 610 (1 << VCPU_EXREG_CR4) | \ 611 (1 << VCPU_EXREG_EXIT_INFO_1) | \ 612 (1 << VCPU_EXREG_EXIT_INFO_2)) 613 614 static inline unsigned long vmx_l1_guest_owned_cr0_bits(void) 615 { 616 unsigned long bits = KVM_POSSIBLE_CR0_GUEST_BITS; 617 618 /* 619 * CR0.WP needs to be intercepted when KVM is shadowing legacy paging 620 * in order to construct shadow PTEs with the correct protections. 621 * Note! CR0.WP technically can be passed through to the guest if 622 * paging is disabled, but checking CR0.PG would generate a cyclical 623 * dependency of sorts due to forcing the caller to ensure CR0 holds 624 * the correct value prior to determining which CR0 bits can be owned 625 * by L1. Keep it simple and limit the optimization to EPT. 626 */ 627 if (!enable_ept) 628 bits &= ~X86_CR0_WP; 629 return bits; 630 } 631 632 static __always_inline struct kvm_vmx *to_kvm_vmx(struct kvm *kvm) 633 { 634 return container_of(kvm, struct kvm_vmx, kvm); 635 } 636 637 static __always_inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu) 638 { 639 return container_of(vcpu, struct vcpu_vmx, vcpu); 640 } 641 642 void intel_pmu_cross_mapped_check(struct kvm_pmu *pmu); 643 int intel_pmu_create_guest_lbr_event(struct kvm_vcpu *vcpu); 644 void vmx_passthrough_lbr_msrs(struct kvm_vcpu *vcpu); 645 646 struct vmcs *alloc_vmcs_cpu(bool shadow, int cpu, gfp_t flags); 647 void free_vmcs(struct vmcs *vmcs); 648 int alloc_loaded_vmcs(struct loaded_vmcs *loaded_vmcs); 649 void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs); 650 void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs); 651 652 static inline struct vmcs *alloc_vmcs(bool shadow) 653 { 654 return alloc_vmcs_cpu(shadow, raw_smp_processor_id(), 655 GFP_KERNEL_ACCOUNT); 656 } 657 658 static inline bool vmx_has_waitpkg(struct vcpu_vmx *vmx) 659 { 660 return secondary_exec_controls_get(vmx) & 661 SECONDARY_EXEC_ENABLE_USR_WAIT_PAUSE; 662 } 663 664 static inline bool vmx_need_pf_intercept(struct kvm_vcpu *vcpu) 665 { 666 if (!enable_ept) 667 return true; 668 669 return allow_smaller_maxphyaddr && 670 cpuid_maxphyaddr(vcpu) < kvm_host.maxphyaddr; 671 } 672 673 static inline bool is_unrestricted_guest(struct kvm_vcpu *vcpu) 674 { 675 return enable_unrestricted_guest && (!is_guest_mode(vcpu) || 676 (secondary_exec_controls_get(to_vmx(vcpu)) & 677 SECONDARY_EXEC_UNRESTRICTED_GUEST)); 678 } 679 680 bool __vmx_guest_state_valid(struct kvm_vcpu *vcpu); 681 static inline bool vmx_guest_state_valid(struct kvm_vcpu *vcpu) 682 { 683 return is_unrestricted_guest(vcpu) || __vmx_guest_state_valid(vcpu); 684 } 685 686 void dump_vmcs(struct kvm_vcpu *vcpu); 687 688 static inline int vmx_get_instr_info_reg2(u32 vmx_instr_info) 689 { 690 return (vmx_instr_info >> 28) & 0xf; 691 } 692 693 static inline bool vmx_can_use_ipiv(struct kvm_vcpu *vcpu) 694 { 695 return lapic_in_kernel(vcpu) && enable_ipiv; 696 } 697 698 static inline void vmx_segment_cache_clear(struct vcpu_vmx *vmx) 699 { 700 vmx->segment_cache.bitmask = 0; 701 } 702 703 int vmx_init(void); 704 void vmx_exit(void); 705 706 #endif /* __KVM_X86_VMX_H */ 707