1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef __KVM_X86_VMX_H 3 #define __KVM_X86_VMX_H 4 5 #include <linux/kvm_host.h> 6 7 #include <asm/kvm.h> 8 #include <asm/intel_pt.h> 9 #include <asm/perf_event.h> 10 #include <asm/posted_intr.h> 11 12 #include "capabilities.h" 13 #include "../kvm_cache_regs.h" 14 #include "vmcs.h" 15 #include "vmx_ops.h" 16 #include "../cpuid.h" 17 #include "run_flags.h" 18 #include "../mmu.h" 19 20 #define X2APIC_MSR(r) (APIC_BASE_MSR + ((r) >> 4)) 21 22 #ifdef CONFIG_X86_64 23 #define MAX_NR_USER_RETURN_MSRS 7 24 #else 25 #define MAX_NR_USER_RETURN_MSRS 4 26 #endif 27 28 #define MAX_NR_LOADSTORE_MSRS 8 29 30 struct vmx_msrs { 31 unsigned int nr; 32 struct vmx_msr_entry val[MAX_NR_LOADSTORE_MSRS]; 33 }; 34 35 struct vmx_uret_msr { 36 bool load_into_hardware; 37 u64 data; 38 u64 mask; 39 }; 40 41 enum segment_cache_field { 42 SEG_FIELD_SEL = 0, 43 SEG_FIELD_BASE = 1, 44 SEG_FIELD_LIMIT = 2, 45 SEG_FIELD_AR = 3, 46 47 SEG_FIELD_NR = 4 48 }; 49 50 #define RTIT_ADDR_RANGE 4 51 52 struct pt_ctx { 53 u64 ctl; 54 u64 status; 55 u64 output_base; 56 u64 output_mask; 57 u64 cr3_match; 58 u64 addr_a[RTIT_ADDR_RANGE]; 59 u64 addr_b[RTIT_ADDR_RANGE]; 60 }; 61 62 struct pt_desc { 63 u64 ctl_bitmask; 64 u32 num_address_ranges; 65 u32 caps[PT_CPUID_REGS_NUM * PT_CPUID_LEAVES]; 66 struct pt_ctx host; 67 struct pt_ctx guest; 68 }; 69 70 union vmx_exit_reason { 71 struct { 72 u32 basic : 16; 73 u32 reserved16 : 1; 74 u32 reserved17 : 1; 75 u32 reserved18 : 1; 76 u32 reserved19 : 1; 77 u32 reserved20 : 1; 78 u32 reserved21 : 1; 79 u32 reserved22 : 1; 80 u32 reserved23 : 1; 81 u32 reserved24 : 1; 82 u32 reserved25 : 1; 83 u32 bus_lock_detected : 1; 84 u32 enclave_mode : 1; 85 u32 smi_pending_mtf : 1; 86 u32 smi_from_vmx_root : 1; 87 u32 reserved30 : 1; 88 u32 failed_vmentry : 1; 89 }; 90 u32 full; 91 }; 92 93 struct lbr_desc { 94 /* Basic info about guest LBR records. */ 95 struct x86_pmu_lbr records; 96 97 /* 98 * Emulate LBR feature via passthrough LBR registers when the 99 * per-vcpu guest LBR event is scheduled on the current pcpu. 100 * 101 * The records may be inaccurate if the host reclaims the LBR. 102 */ 103 struct perf_event *event; 104 105 /* True if LBRs are marked as not intercepted in the MSR bitmap */ 106 bool msr_passthrough; 107 }; 108 109 extern struct x86_pmu_lbr vmx_lbr_caps; 110 111 /* 112 * The nested_vmx structure is part of vcpu_vmx, and holds information we need 113 * for correct emulation of VMX (i.e., nested VMX) on this vcpu. 114 */ 115 struct nested_vmx { 116 /* Has the level1 guest done vmxon? */ 117 bool vmxon; 118 gpa_t vmxon_ptr; 119 bool pml_full; 120 121 /* The guest-physical address of the current VMCS L1 keeps for L2 */ 122 gpa_t current_vmptr; 123 /* 124 * Cache of the guest's VMCS, existing outside of guest memory. 125 * Loaded from guest memory during VMPTRLD. Flushed to guest 126 * memory during VMCLEAR and VMPTRLD. 127 */ 128 struct vmcs12 *cached_vmcs12; 129 /* 130 * Cache of the guest's shadow VMCS, existing outside of guest 131 * memory. Loaded from guest memory during VM entry. Flushed 132 * to guest memory during VM exit. 133 */ 134 struct vmcs12 *cached_shadow_vmcs12; 135 136 /* 137 * GPA to HVA cache for accessing vmcs12->vmcs_link_pointer 138 */ 139 struct gfn_to_hva_cache shadow_vmcs12_cache; 140 141 /* 142 * GPA to HVA cache for VMCS12 143 */ 144 struct gfn_to_hva_cache vmcs12_cache; 145 146 /* 147 * Indicates if the shadow vmcs or enlightened vmcs must be updated 148 * with the data held by struct vmcs12. 149 */ 150 bool need_vmcs12_to_shadow_sync; 151 bool dirty_vmcs12; 152 153 /* 154 * Indicates whether MSR bitmap for L2 needs to be rebuilt due to 155 * changes in MSR bitmap for L1 or switching to a different L2. Note, 156 * this flag can only be used reliably in conjunction with a paravirt L1 157 * which informs L0 whether any changes to MSR bitmap for L2 were done 158 * on its side. 159 */ 160 bool force_msr_bitmap_recalc; 161 162 /* 163 * Indicates lazily loaded guest state has not yet been decached from 164 * vmcs02. 165 */ 166 bool need_sync_vmcs02_to_vmcs12_rare; 167 168 /* 169 * vmcs02 has been initialized, i.e. state that is constant for 170 * vmcs02 has been written to the backing VMCS. Initialization 171 * is delayed until L1 actually attempts to run a nested VM. 172 */ 173 bool vmcs02_initialized; 174 175 bool change_vmcs01_virtual_apic_mode; 176 bool reload_vmcs01_apic_access_page; 177 bool update_vmcs01_cpu_dirty_logging; 178 bool update_vmcs01_apicv_status; 179 180 /* 181 * Enlightened VMCS has been enabled. It does not mean that L1 has to 182 * use it. However, VMX features available to L1 will be limited based 183 * on what the enlightened VMCS supports. 184 */ 185 bool enlightened_vmcs_enabled; 186 187 /* L2 must run next, and mustn't decide to exit to L1. */ 188 bool nested_run_pending; 189 190 /* Pending MTF VM-exit into L1. */ 191 bool mtf_pending; 192 193 struct loaded_vmcs vmcs02; 194 195 /* 196 * Guest pages referred to in the vmcs02 with host-physical 197 * pointers, so we must keep them pinned while L2 runs. 198 */ 199 struct kvm_host_map apic_access_page_map; 200 struct kvm_host_map virtual_apic_map; 201 struct kvm_host_map pi_desc_map; 202 203 struct pi_desc *pi_desc; 204 bool pi_pending; 205 u16 posted_intr_nv; 206 207 struct hrtimer preemption_timer; 208 u64 preemption_timer_deadline; 209 bool has_preemption_timer_deadline; 210 bool preemption_timer_expired; 211 212 /* 213 * Used to snapshot MSRs that are conditionally loaded on VM-Enter in 214 * order to propagate the guest's pre-VM-Enter value into vmcs02. For 215 * emulation of VMLAUNCH/VMRESUME, the snapshot will be of L1's value. 216 * For KVM_SET_NESTED_STATE, the snapshot is of L2's value, _if_ 217 * userspace restores MSRs before nested state. If userspace restores 218 * MSRs after nested state, the snapshot holds garbage, but KVM can't 219 * detect that, and the garbage value in vmcs02 will be overwritten by 220 * MSR restoration in any case. 221 */ 222 u64 pre_vmenter_debugctl; 223 u64 pre_vmenter_bndcfgs; 224 225 /* to migrate it to L1 if L2 writes to L1's CR8 directly */ 226 int l1_tpr_threshold; 227 228 u16 vpid02; 229 u16 last_vpid; 230 231 struct nested_vmx_msrs msrs; 232 233 /* SMM related state */ 234 struct { 235 /* in VMX operation on SMM entry? */ 236 bool vmxon; 237 /* in guest mode on SMM entry? */ 238 bool guest_mode; 239 } smm; 240 241 #ifdef CONFIG_KVM_HYPERV 242 gpa_t hv_evmcs_vmptr; 243 struct kvm_host_map hv_evmcs_map; 244 struct hv_enlightened_vmcs *hv_evmcs; 245 #endif 246 }; 247 248 struct vcpu_vmx { 249 struct kvm_vcpu vcpu; 250 u8 fail; 251 u8 x2apic_msr_bitmap_mode; 252 253 /* 254 * If true, host state has been stored in vmx->loaded_vmcs for 255 * the CPU registers that only need to be switched when transitioning 256 * to/from the kernel, and the registers have been loaded with guest 257 * values. If false, host state is loaded in the CPU registers 258 * and vmx->loaded_vmcs->host_state is invalid. 259 */ 260 bool guest_state_loaded; 261 262 unsigned long exit_qualification; 263 u32 exit_intr_info; 264 u32 idt_vectoring_info; 265 ulong rflags; 266 267 /* 268 * User return MSRs are always emulated when enabled in the guest, but 269 * only loaded into hardware when necessary, e.g. SYSCALL #UDs outside 270 * of 64-bit mode or if EFER.SCE=1, thus the SYSCALL MSRs don't need to 271 * be loaded into hardware if those conditions aren't met. 272 */ 273 struct vmx_uret_msr guest_uret_msrs[MAX_NR_USER_RETURN_MSRS]; 274 bool guest_uret_msrs_loaded; 275 #ifdef CONFIG_X86_64 276 u64 msr_host_kernel_gs_base; 277 u64 msr_guest_kernel_gs_base; 278 #endif 279 280 u64 spec_ctrl; 281 u32 msr_ia32_umwait_control; 282 283 /* 284 * loaded_vmcs points to the VMCS currently used in this vcpu. For a 285 * non-nested (L1) guest, it always points to vmcs01. For a nested 286 * guest (L2), it points to a different VMCS. 287 */ 288 struct loaded_vmcs vmcs01; 289 struct loaded_vmcs *loaded_vmcs; 290 291 struct msr_autoload { 292 struct vmx_msrs guest; 293 struct vmx_msrs host; 294 } msr_autoload; 295 296 struct msr_autostore { 297 struct vmx_msrs guest; 298 } msr_autostore; 299 300 struct { 301 int vm86_active; 302 ulong save_rflags; 303 struct kvm_segment segs[8]; 304 } rmode; 305 struct { 306 u32 bitmask; /* 4 bits per segment (1 bit per field) */ 307 struct kvm_save_segment { 308 u16 selector; 309 unsigned long base; 310 u32 limit; 311 u32 ar; 312 } seg[8]; 313 } segment_cache; 314 int vpid; 315 bool emulation_required; 316 317 union vmx_exit_reason exit_reason; 318 319 /* Posted interrupt descriptor */ 320 struct pi_desc pi_desc; 321 322 /* Used if this vCPU is waiting for PI notification wakeup. */ 323 struct list_head pi_wakeup_list; 324 325 /* Support for a guest hypervisor (nested VMX) */ 326 struct nested_vmx nested; 327 328 /* Dynamic PLE window. */ 329 unsigned int ple_window; 330 bool ple_window_dirty; 331 332 /* Support for PML */ 333 #define PML_ENTITY_NUM 512 334 struct page *pml_pg; 335 336 /* apic deadline value in host tsc */ 337 u64 hv_deadline_tsc; 338 339 unsigned long host_debugctlmsr; 340 341 /* 342 * Only bits masked by msr_ia32_feature_control_valid_bits can be set in 343 * msr_ia32_feature_control. FEAT_CTL_LOCKED is always included 344 * in msr_ia32_feature_control_valid_bits. 345 */ 346 u64 msr_ia32_feature_control; 347 u64 msr_ia32_feature_control_valid_bits; 348 /* SGX Launch Control public key hash */ 349 u64 msr_ia32_sgxlepubkeyhash[4]; 350 u64 msr_ia32_mcu_opt_ctrl; 351 bool disable_fb_clear; 352 353 struct pt_desc pt_desc; 354 struct lbr_desc lbr_desc; 355 356 /* Save desired MSR intercept (read: pass-through) state */ 357 #define MAX_POSSIBLE_PASSTHROUGH_MSRS 16 358 struct { 359 DECLARE_BITMAP(read, MAX_POSSIBLE_PASSTHROUGH_MSRS); 360 DECLARE_BITMAP(write, MAX_POSSIBLE_PASSTHROUGH_MSRS); 361 } shadow_msr_intercept; 362 363 /* ve_info must be page aligned. */ 364 struct vmx_ve_information *ve_info; 365 }; 366 367 struct kvm_vmx { 368 struct kvm kvm; 369 370 unsigned int tss_addr; 371 bool ept_identity_pagetable_done; 372 gpa_t ept_identity_map_addr; 373 /* Posted Interrupt Descriptor (PID) table for IPI virtualization */ 374 u64 *pid_table; 375 }; 376 377 void vmx_vcpu_load_vmcs(struct kvm_vcpu *vcpu, int cpu, 378 struct loaded_vmcs *buddy); 379 int allocate_vpid(void); 380 void free_vpid(int vpid); 381 void vmx_set_constant_host_state(struct vcpu_vmx *vmx); 382 void vmx_prepare_switch_to_guest(struct kvm_vcpu *vcpu); 383 void vmx_set_host_fs_gs(struct vmcs_host_state *host, u16 fs_sel, u16 gs_sel, 384 unsigned long fs_base, unsigned long gs_base); 385 int vmx_get_cpl(struct kvm_vcpu *vcpu); 386 int vmx_get_cpl_no_cache(struct kvm_vcpu *vcpu); 387 bool vmx_emulation_required(struct kvm_vcpu *vcpu); 388 unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu); 389 void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags); 390 u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu); 391 void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask); 392 int vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer); 393 void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0); 394 void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4); 395 void set_cr4_guest_host_mask(struct vcpu_vmx *vmx); 396 void ept_save_pdptrs(struct kvm_vcpu *vcpu); 397 void vmx_get_segment(struct kvm_vcpu *vcpu, struct kvm_segment *var, int seg); 398 void __vmx_set_segment(struct kvm_vcpu *vcpu, struct kvm_segment *var, int seg); 399 u64 construct_eptp(struct kvm_vcpu *vcpu, hpa_t root_hpa, int root_level); 400 401 bool vmx_guest_inject_ac(struct kvm_vcpu *vcpu); 402 void vmx_update_exception_bitmap(struct kvm_vcpu *vcpu); 403 bool vmx_nmi_blocked(struct kvm_vcpu *vcpu); 404 bool __vmx_interrupt_blocked(struct kvm_vcpu *vcpu); 405 bool vmx_interrupt_blocked(struct kvm_vcpu *vcpu); 406 bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu); 407 void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked); 408 void vmx_set_virtual_apic_mode(struct kvm_vcpu *vcpu); 409 struct vmx_uret_msr *vmx_find_uret_msr(struct vcpu_vmx *vmx, u32 msr); 410 void pt_update_intercept_for_msr(struct kvm_vcpu *vcpu); 411 void vmx_update_host_rsp(struct vcpu_vmx *vmx, unsigned long host_rsp); 412 void vmx_spec_ctrl_restore_host(struct vcpu_vmx *vmx, unsigned int flags); 413 unsigned int __vmx_vcpu_run_flags(struct vcpu_vmx *vmx); 414 bool __vmx_vcpu_run(struct vcpu_vmx *vmx, unsigned long *regs, 415 unsigned int flags); 416 int vmx_find_loadstore_msr_slot(struct vmx_msrs *m, u32 msr); 417 void vmx_ept_load_pdptrs(struct kvm_vcpu *vcpu); 418 419 void vmx_disable_intercept_for_msr(struct kvm_vcpu *vcpu, u32 msr, int type); 420 void vmx_enable_intercept_for_msr(struct kvm_vcpu *vcpu, u32 msr, int type); 421 422 u64 vmx_get_l2_tsc_offset(struct kvm_vcpu *vcpu); 423 u64 vmx_get_l2_tsc_multiplier(struct kvm_vcpu *vcpu); 424 425 gva_t vmx_get_untagged_addr(struct kvm_vcpu *vcpu, gva_t gva, unsigned int flags); 426 427 static inline void vmx_set_intercept_for_msr(struct kvm_vcpu *vcpu, u32 msr, 428 int type, bool value) 429 { 430 if (value) 431 vmx_enable_intercept_for_msr(vcpu, msr, type); 432 else 433 vmx_disable_intercept_for_msr(vcpu, msr, type); 434 } 435 436 void vmx_update_cpu_dirty_logging(struct kvm_vcpu *vcpu); 437 438 /* 439 * Note, early Intel manuals have the write-low and read-high bitmap offsets 440 * the wrong way round. The bitmaps control MSRs 0x00000000-0x00001fff and 441 * 0xc0000000-0xc0001fff. The former (low) uses bytes 0-0x3ff for reads and 442 * 0x800-0xbff for writes. The latter (high) uses 0x400-0x7ff for reads and 443 * 0xc00-0xfff for writes. MSRs not covered by either of the ranges always 444 * VM-Exit. 445 */ 446 #define __BUILD_VMX_MSR_BITMAP_HELPER(rtype, action, bitop, access, base) \ 447 static inline rtype vmx_##action##_msr_bitmap_##access(unsigned long *bitmap, \ 448 u32 msr) \ 449 { \ 450 int f = sizeof(unsigned long); \ 451 \ 452 if (msr <= 0x1fff) \ 453 return bitop##_bit(msr, bitmap + base / f); \ 454 else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) \ 455 return bitop##_bit(msr & 0x1fff, bitmap + (base + 0x400) / f); \ 456 return (rtype)true; \ 457 } 458 #define BUILD_VMX_MSR_BITMAP_HELPERS(ret_type, action, bitop) \ 459 __BUILD_VMX_MSR_BITMAP_HELPER(ret_type, action, bitop, read, 0x0) \ 460 __BUILD_VMX_MSR_BITMAP_HELPER(ret_type, action, bitop, write, 0x800) 461 462 BUILD_VMX_MSR_BITMAP_HELPERS(bool, test, test) 463 BUILD_VMX_MSR_BITMAP_HELPERS(void, clear, __clear) 464 BUILD_VMX_MSR_BITMAP_HELPERS(void, set, __set) 465 466 static inline u8 vmx_get_rvi(void) 467 { 468 return vmcs_read16(GUEST_INTR_STATUS) & 0xff; 469 } 470 471 #define __KVM_REQUIRED_VMX_VM_ENTRY_CONTROLS \ 472 (VM_ENTRY_LOAD_DEBUG_CONTROLS) 473 #ifdef CONFIG_X86_64 474 #define KVM_REQUIRED_VMX_VM_ENTRY_CONTROLS \ 475 (__KVM_REQUIRED_VMX_VM_ENTRY_CONTROLS | \ 476 VM_ENTRY_IA32E_MODE) 477 #else 478 #define KVM_REQUIRED_VMX_VM_ENTRY_CONTROLS \ 479 __KVM_REQUIRED_VMX_VM_ENTRY_CONTROLS 480 #endif 481 #define KVM_OPTIONAL_VMX_VM_ENTRY_CONTROLS \ 482 (VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | \ 483 VM_ENTRY_LOAD_IA32_PAT | \ 484 VM_ENTRY_LOAD_IA32_EFER | \ 485 VM_ENTRY_LOAD_BNDCFGS | \ 486 VM_ENTRY_PT_CONCEAL_PIP | \ 487 VM_ENTRY_LOAD_IA32_RTIT_CTL) 488 489 #define __KVM_REQUIRED_VMX_VM_EXIT_CONTROLS \ 490 (VM_EXIT_SAVE_DEBUG_CONTROLS | \ 491 VM_EXIT_ACK_INTR_ON_EXIT) 492 #ifdef CONFIG_X86_64 493 #define KVM_REQUIRED_VMX_VM_EXIT_CONTROLS \ 494 (__KVM_REQUIRED_VMX_VM_EXIT_CONTROLS | \ 495 VM_EXIT_HOST_ADDR_SPACE_SIZE) 496 #else 497 #define KVM_REQUIRED_VMX_VM_EXIT_CONTROLS \ 498 __KVM_REQUIRED_VMX_VM_EXIT_CONTROLS 499 #endif 500 #define KVM_OPTIONAL_VMX_VM_EXIT_CONTROLS \ 501 (VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | \ 502 VM_EXIT_SAVE_IA32_PAT | \ 503 VM_EXIT_LOAD_IA32_PAT | \ 504 VM_EXIT_SAVE_IA32_EFER | \ 505 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER | \ 506 VM_EXIT_LOAD_IA32_EFER | \ 507 VM_EXIT_CLEAR_BNDCFGS | \ 508 VM_EXIT_PT_CONCEAL_PIP | \ 509 VM_EXIT_CLEAR_IA32_RTIT_CTL) 510 511 #define KVM_REQUIRED_VMX_PIN_BASED_VM_EXEC_CONTROL \ 512 (PIN_BASED_EXT_INTR_MASK | \ 513 PIN_BASED_NMI_EXITING) 514 #define KVM_OPTIONAL_VMX_PIN_BASED_VM_EXEC_CONTROL \ 515 (PIN_BASED_VIRTUAL_NMIS | \ 516 PIN_BASED_POSTED_INTR | \ 517 PIN_BASED_VMX_PREEMPTION_TIMER) 518 519 #define __KVM_REQUIRED_VMX_CPU_BASED_VM_EXEC_CONTROL \ 520 (CPU_BASED_HLT_EXITING | \ 521 CPU_BASED_CR3_LOAD_EXITING | \ 522 CPU_BASED_CR3_STORE_EXITING | \ 523 CPU_BASED_UNCOND_IO_EXITING | \ 524 CPU_BASED_MOV_DR_EXITING | \ 525 CPU_BASED_USE_TSC_OFFSETTING | \ 526 CPU_BASED_MWAIT_EXITING | \ 527 CPU_BASED_MONITOR_EXITING | \ 528 CPU_BASED_INVLPG_EXITING | \ 529 CPU_BASED_RDPMC_EXITING | \ 530 CPU_BASED_INTR_WINDOW_EXITING) 531 532 #ifdef CONFIG_X86_64 533 #define KVM_REQUIRED_VMX_CPU_BASED_VM_EXEC_CONTROL \ 534 (__KVM_REQUIRED_VMX_CPU_BASED_VM_EXEC_CONTROL | \ 535 CPU_BASED_CR8_LOAD_EXITING | \ 536 CPU_BASED_CR8_STORE_EXITING) 537 #else 538 #define KVM_REQUIRED_VMX_CPU_BASED_VM_EXEC_CONTROL \ 539 __KVM_REQUIRED_VMX_CPU_BASED_VM_EXEC_CONTROL 540 #endif 541 542 #define KVM_OPTIONAL_VMX_CPU_BASED_VM_EXEC_CONTROL \ 543 (CPU_BASED_RDTSC_EXITING | \ 544 CPU_BASED_TPR_SHADOW | \ 545 CPU_BASED_USE_IO_BITMAPS | \ 546 CPU_BASED_MONITOR_TRAP_FLAG | \ 547 CPU_BASED_USE_MSR_BITMAPS | \ 548 CPU_BASED_NMI_WINDOW_EXITING | \ 549 CPU_BASED_PAUSE_EXITING | \ 550 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS | \ 551 CPU_BASED_ACTIVATE_TERTIARY_CONTROLS) 552 553 #define KVM_REQUIRED_VMX_SECONDARY_VM_EXEC_CONTROL 0 554 #define KVM_OPTIONAL_VMX_SECONDARY_VM_EXEC_CONTROL \ 555 (SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | \ 556 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | \ 557 SECONDARY_EXEC_WBINVD_EXITING | \ 558 SECONDARY_EXEC_ENABLE_VPID | \ 559 SECONDARY_EXEC_ENABLE_EPT | \ 560 SECONDARY_EXEC_UNRESTRICTED_GUEST | \ 561 SECONDARY_EXEC_PAUSE_LOOP_EXITING | \ 562 SECONDARY_EXEC_DESC | \ 563 SECONDARY_EXEC_ENABLE_RDTSCP | \ 564 SECONDARY_EXEC_ENABLE_INVPCID | \ 565 SECONDARY_EXEC_APIC_REGISTER_VIRT | \ 566 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | \ 567 SECONDARY_EXEC_SHADOW_VMCS | \ 568 SECONDARY_EXEC_ENABLE_XSAVES | \ 569 SECONDARY_EXEC_RDSEED_EXITING | \ 570 SECONDARY_EXEC_RDRAND_EXITING | \ 571 SECONDARY_EXEC_ENABLE_PML | \ 572 SECONDARY_EXEC_TSC_SCALING | \ 573 SECONDARY_EXEC_ENABLE_USR_WAIT_PAUSE | \ 574 SECONDARY_EXEC_PT_USE_GPA | \ 575 SECONDARY_EXEC_PT_CONCEAL_VMX | \ 576 SECONDARY_EXEC_ENABLE_VMFUNC | \ 577 SECONDARY_EXEC_BUS_LOCK_DETECTION | \ 578 SECONDARY_EXEC_NOTIFY_VM_EXITING | \ 579 SECONDARY_EXEC_ENCLS_EXITING | \ 580 SECONDARY_EXEC_EPT_VIOLATION_VE) 581 582 #define KVM_REQUIRED_VMX_TERTIARY_VM_EXEC_CONTROL 0 583 #define KVM_OPTIONAL_VMX_TERTIARY_VM_EXEC_CONTROL \ 584 (TERTIARY_EXEC_IPI_VIRT) 585 586 #define BUILD_CONTROLS_SHADOW(lname, uname, bits) \ 587 static inline void lname##_controls_set(struct vcpu_vmx *vmx, u##bits val) \ 588 { \ 589 if (vmx->loaded_vmcs->controls_shadow.lname != val) { \ 590 vmcs_write##bits(uname, val); \ 591 vmx->loaded_vmcs->controls_shadow.lname = val; \ 592 } \ 593 } \ 594 static inline u##bits __##lname##_controls_get(struct loaded_vmcs *vmcs) \ 595 { \ 596 return vmcs->controls_shadow.lname; \ 597 } \ 598 static inline u##bits lname##_controls_get(struct vcpu_vmx *vmx) \ 599 { \ 600 return __##lname##_controls_get(vmx->loaded_vmcs); \ 601 } \ 602 static __always_inline void lname##_controls_setbit(struct vcpu_vmx *vmx, u##bits val) \ 603 { \ 604 BUILD_BUG_ON(!(val & (KVM_REQUIRED_VMX_##uname | KVM_OPTIONAL_VMX_##uname))); \ 605 lname##_controls_set(vmx, lname##_controls_get(vmx) | val); \ 606 } \ 607 static __always_inline void lname##_controls_clearbit(struct vcpu_vmx *vmx, u##bits val) \ 608 { \ 609 BUILD_BUG_ON(!(val & (KVM_REQUIRED_VMX_##uname | KVM_OPTIONAL_VMX_##uname))); \ 610 lname##_controls_set(vmx, lname##_controls_get(vmx) & ~val); \ 611 } 612 BUILD_CONTROLS_SHADOW(vm_entry, VM_ENTRY_CONTROLS, 32) 613 BUILD_CONTROLS_SHADOW(vm_exit, VM_EXIT_CONTROLS, 32) 614 BUILD_CONTROLS_SHADOW(pin, PIN_BASED_VM_EXEC_CONTROL, 32) 615 BUILD_CONTROLS_SHADOW(exec, CPU_BASED_VM_EXEC_CONTROL, 32) 616 BUILD_CONTROLS_SHADOW(secondary_exec, SECONDARY_VM_EXEC_CONTROL, 32) 617 BUILD_CONTROLS_SHADOW(tertiary_exec, TERTIARY_VM_EXEC_CONTROL, 64) 618 619 /* 620 * VMX_REGS_LAZY_LOAD_SET - The set of registers that will be updated in the 621 * cache on demand. Other registers not listed here are synced to 622 * the cache immediately after VM-Exit. 623 */ 624 #define VMX_REGS_LAZY_LOAD_SET ((1 << VCPU_REGS_RIP) | \ 625 (1 << VCPU_REGS_RSP) | \ 626 (1 << VCPU_EXREG_RFLAGS) | \ 627 (1 << VCPU_EXREG_PDPTR) | \ 628 (1 << VCPU_EXREG_SEGMENTS) | \ 629 (1 << VCPU_EXREG_CR0) | \ 630 (1 << VCPU_EXREG_CR3) | \ 631 (1 << VCPU_EXREG_CR4) | \ 632 (1 << VCPU_EXREG_EXIT_INFO_1) | \ 633 (1 << VCPU_EXREG_EXIT_INFO_2)) 634 635 static inline unsigned long vmx_l1_guest_owned_cr0_bits(void) 636 { 637 unsigned long bits = KVM_POSSIBLE_CR0_GUEST_BITS; 638 639 /* 640 * CR0.WP needs to be intercepted when KVM is shadowing legacy paging 641 * in order to construct shadow PTEs with the correct protections. 642 * Note! CR0.WP technically can be passed through to the guest if 643 * paging is disabled, but checking CR0.PG would generate a cyclical 644 * dependency of sorts due to forcing the caller to ensure CR0 holds 645 * the correct value prior to determining which CR0 bits can be owned 646 * by L1. Keep it simple and limit the optimization to EPT. 647 */ 648 if (!enable_ept) 649 bits &= ~X86_CR0_WP; 650 return bits; 651 } 652 653 static __always_inline struct kvm_vmx *to_kvm_vmx(struct kvm *kvm) 654 { 655 return container_of(kvm, struct kvm_vmx, kvm); 656 } 657 658 static __always_inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu) 659 { 660 return container_of(vcpu, struct vcpu_vmx, vcpu); 661 } 662 663 static inline struct lbr_desc *vcpu_to_lbr_desc(struct kvm_vcpu *vcpu) 664 { 665 return &to_vmx(vcpu)->lbr_desc; 666 } 667 668 static inline struct x86_pmu_lbr *vcpu_to_lbr_records(struct kvm_vcpu *vcpu) 669 { 670 return &vcpu_to_lbr_desc(vcpu)->records; 671 } 672 673 static inline bool intel_pmu_lbr_is_enabled(struct kvm_vcpu *vcpu) 674 { 675 return !!vcpu_to_lbr_records(vcpu)->nr; 676 } 677 678 void intel_pmu_cross_mapped_check(struct kvm_pmu *pmu); 679 int intel_pmu_create_guest_lbr_event(struct kvm_vcpu *vcpu); 680 void vmx_passthrough_lbr_msrs(struct kvm_vcpu *vcpu); 681 682 static __always_inline unsigned long vmx_get_exit_qual(struct kvm_vcpu *vcpu) 683 { 684 struct vcpu_vmx *vmx = to_vmx(vcpu); 685 686 if (!kvm_register_test_and_mark_available(vcpu, VCPU_EXREG_EXIT_INFO_1)) 687 vmx->exit_qualification = vmcs_readl(EXIT_QUALIFICATION); 688 689 return vmx->exit_qualification; 690 } 691 692 static __always_inline u32 vmx_get_intr_info(struct kvm_vcpu *vcpu) 693 { 694 struct vcpu_vmx *vmx = to_vmx(vcpu); 695 696 if (!kvm_register_test_and_mark_available(vcpu, VCPU_EXREG_EXIT_INFO_2)) 697 vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO); 698 699 return vmx->exit_intr_info; 700 } 701 702 struct vmcs *alloc_vmcs_cpu(bool shadow, int cpu, gfp_t flags); 703 void free_vmcs(struct vmcs *vmcs); 704 int alloc_loaded_vmcs(struct loaded_vmcs *loaded_vmcs); 705 void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs); 706 void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs); 707 708 static inline struct vmcs *alloc_vmcs(bool shadow) 709 { 710 return alloc_vmcs_cpu(shadow, raw_smp_processor_id(), 711 GFP_KERNEL_ACCOUNT); 712 } 713 714 static inline bool vmx_has_waitpkg(struct vcpu_vmx *vmx) 715 { 716 return secondary_exec_controls_get(vmx) & 717 SECONDARY_EXEC_ENABLE_USR_WAIT_PAUSE; 718 } 719 720 static inline bool vmx_need_pf_intercept(struct kvm_vcpu *vcpu) 721 { 722 if (!enable_ept) 723 return true; 724 725 return allow_smaller_maxphyaddr && 726 cpuid_maxphyaddr(vcpu) < kvm_host.maxphyaddr; 727 } 728 729 static inline bool is_unrestricted_guest(struct kvm_vcpu *vcpu) 730 { 731 return enable_unrestricted_guest && (!is_guest_mode(vcpu) || 732 (secondary_exec_controls_get(to_vmx(vcpu)) & 733 SECONDARY_EXEC_UNRESTRICTED_GUEST)); 734 } 735 736 bool __vmx_guest_state_valid(struct kvm_vcpu *vcpu); 737 static inline bool vmx_guest_state_valid(struct kvm_vcpu *vcpu) 738 { 739 return is_unrestricted_guest(vcpu) || __vmx_guest_state_valid(vcpu); 740 } 741 742 void dump_vmcs(struct kvm_vcpu *vcpu); 743 744 static inline int vmx_get_instr_info_reg2(u32 vmx_instr_info) 745 { 746 return (vmx_instr_info >> 28) & 0xf; 747 } 748 749 static inline bool vmx_can_use_ipiv(struct kvm_vcpu *vcpu) 750 { 751 return lapic_in_kernel(vcpu) && enable_ipiv; 752 } 753 754 static inline void vmx_segment_cache_clear(struct vcpu_vmx *vmx) 755 { 756 vmx->segment_cache.bitmask = 0; 757 } 758 759 #endif /* __KVM_X86_VMX_H */ 760