1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef __KVM_X86_VMX_H 3 #define __KVM_X86_VMX_H 4 5 #include <linux/kvm_host.h> 6 7 #include <asm/kvm.h> 8 #include <asm/intel_pt.h> 9 #include <asm/perf_event.h> 10 #include <asm/posted_intr.h> 11 12 #include "capabilities.h" 13 #include "../kvm_cache_regs.h" 14 #include "pmu_intel.h" 15 #include "vmcs.h" 16 #include "vmx_ops.h" 17 #include "../cpuid.h" 18 #include "run_flags.h" 19 #include "../mmu.h" 20 #include "common.h" 21 22 #ifdef CONFIG_X86_64 23 #define MAX_NR_USER_RETURN_MSRS 7 24 #else 25 #define MAX_NR_USER_RETURN_MSRS 4 26 #endif 27 28 #define MAX_NR_LOADSTORE_MSRS 8 29 30 struct vmx_msrs { 31 unsigned int nr; 32 struct vmx_msr_entry val[MAX_NR_LOADSTORE_MSRS]; 33 }; 34 35 struct vmx_uret_msr { 36 bool load_into_hardware; 37 u64 data; 38 u64 mask; 39 }; 40 41 enum segment_cache_field { 42 SEG_FIELD_SEL = 0, 43 SEG_FIELD_BASE = 1, 44 SEG_FIELD_LIMIT = 2, 45 SEG_FIELD_AR = 3, 46 47 SEG_FIELD_NR = 4 48 }; 49 50 #define RTIT_ADDR_RANGE 4 51 52 struct pt_ctx { 53 u64 ctl; 54 u64 status; 55 u64 output_base; 56 u64 output_mask; 57 u64 cr3_match; 58 u64 addr_a[RTIT_ADDR_RANGE]; 59 u64 addr_b[RTIT_ADDR_RANGE]; 60 }; 61 62 struct pt_desc { 63 u64 ctl_bitmask; 64 u32 num_address_ranges; 65 u32 caps[PT_CPUID_REGS_NUM * PT_CPUID_LEAVES]; 66 struct pt_ctx host; 67 struct pt_ctx guest; 68 }; 69 70 /* 71 * The nested_vmx structure is part of vcpu_vmx, and holds information we need 72 * for correct emulation of VMX (i.e., nested VMX) on this vcpu. 73 */ 74 struct nested_vmx { 75 /* Has the level1 guest done vmxon? */ 76 bool vmxon; 77 gpa_t vmxon_ptr; 78 bool pml_full; 79 80 /* The guest-physical address of the current VMCS L1 keeps for L2 */ 81 gpa_t current_vmptr; 82 /* 83 * Cache of the guest's VMCS, existing outside of guest memory. 84 * Loaded from guest memory during VMPTRLD. Flushed to guest 85 * memory during VMCLEAR and VMPTRLD. 86 */ 87 struct vmcs12 *cached_vmcs12; 88 /* 89 * Cache of the guest's shadow VMCS, existing outside of guest 90 * memory. Loaded from guest memory during VM entry. Flushed 91 * to guest memory during VM exit. 92 */ 93 struct vmcs12 *cached_shadow_vmcs12; 94 95 /* 96 * GPA to HVA cache for accessing vmcs12->vmcs_link_pointer 97 */ 98 struct gfn_to_hva_cache shadow_vmcs12_cache; 99 100 /* 101 * GPA to HVA cache for VMCS12 102 */ 103 struct gfn_to_hva_cache vmcs12_cache; 104 105 /* 106 * Indicates if the shadow vmcs or enlightened vmcs must be updated 107 * with the data held by struct vmcs12. 108 */ 109 bool need_vmcs12_to_shadow_sync; 110 bool dirty_vmcs12; 111 112 /* 113 * Indicates whether MSR bitmap for L2 needs to be rebuilt due to 114 * changes in MSR bitmap for L1 or switching to a different L2. Note, 115 * this flag can only be used reliably in conjunction with a paravirt L1 116 * which informs L0 whether any changes to MSR bitmap for L2 were done 117 * on its side. 118 */ 119 bool force_msr_bitmap_recalc; 120 121 /* 122 * Indicates lazily loaded guest state has not yet been decached from 123 * vmcs02. 124 */ 125 bool need_sync_vmcs02_to_vmcs12_rare; 126 127 /* 128 * vmcs02 has been initialized, i.e. state that is constant for 129 * vmcs02 has been written to the backing VMCS. Initialization 130 * is delayed until L1 actually attempts to run a nested VM. 131 */ 132 bool vmcs02_initialized; 133 134 /* 135 * Enlightened VMCS has been enabled. It does not mean that L1 has to 136 * use it. However, VMX features available to L1 will be limited based 137 * on what the enlightened VMCS supports. 138 */ 139 bool enlightened_vmcs_enabled; 140 141 /* Pending MTF VM-exit into L1. */ 142 bool mtf_pending; 143 144 struct loaded_vmcs vmcs02; 145 146 /* 147 * Guest pages referred to in the vmcs02 with host-physical 148 * pointers, so we must keep them pinned while L2 runs. 149 */ 150 struct kvm_host_map apic_access_page_map; 151 struct kvm_host_map virtual_apic_map; 152 struct kvm_host_map pi_desc_map; 153 154 struct pi_desc *pi_desc; 155 bool pi_pending; 156 u16 posted_intr_nv; 157 158 struct hrtimer preemption_timer; 159 u64 preemption_timer_deadline; 160 bool has_preemption_timer_deadline; 161 bool preemption_timer_expired; 162 163 /* 164 * Used to snapshot MSRs that are conditionally loaded on VM-Enter in 165 * order to propagate the guest's pre-VM-Enter value into vmcs02. For 166 * emulation of VMLAUNCH/VMRESUME, the snapshot will be of L1's value. 167 * For KVM_SET_NESTED_STATE, the snapshot is of L2's value, _if_ 168 * userspace restores MSRs before nested state. If userspace restores 169 * MSRs after nested state, the snapshot holds garbage, but KVM can't 170 * detect that, and the garbage value in vmcs02 will be overwritten by 171 * MSR restoration in any case. 172 */ 173 u64 pre_vmenter_debugctl; 174 u64 pre_vmenter_bndcfgs; 175 u64 pre_vmenter_s_cet; 176 u64 pre_vmenter_ssp; 177 u64 pre_vmenter_ssp_tbl; 178 179 u16 vpid02; 180 u16 last_vpid; 181 182 int tsc_autostore_slot; 183 struct nested_vmx_msrs msrs; 184 185 /* SMM related state */ 186 struct { 187 /* in VMX operation on SMM entry? */ 188 bool vmxon; 189 /* in guest mode on SMM entry? */ 190 bool guest_mode; 191 } smm; 192 193 #ifdef CONFIG_KVM_HYPERV 194 gpa_t hv_evmcs_vmptr; 195 struct kvm_host_map hv_evmcs_map; 196 struct hv_enlightened_vmcs *hv_evmcs; 197 #endif 198 }; 199 200 struct vcpu_vmx { 201 struct kvm_vcpu vcpu; 202 struct vcpu_vt vt; 203 u8 fail; 204 u8 x2apic_msr_bitmap_mode; 205 206 u32 idt_vectoring_info; 207 ulong rflags; 208 209 /* 210 * User return MSRs are always emulated when enabled in the guest, but 211 * only loaded into hardware when necessary, e.g. SYSCALL #UDs outside 212 * of 64-bit mode or if EFER.SCE=1, thus the SYSCALL MSRs don't need to 213 * be loaded into hardware if those conditions aren't met. 214 */ 215 struct vmx_uret_msr guest_uret_msrs[MAX_NR_USER_RETURN_MSRS]; 216 bool guest_uret_msrs_loaded; 217 #ifdef CONFIG_X86_64 218 u64 msr_guest_kernel_gs_base; 219 #endif 220 221 u64 spec_ctrl; 222 u32 msr_ia32_umwait_control; 223 224 /* 225 * loaded_vmcs points to the VMCS currently used in this vcpu. For a 226 * non-nested (L1) guest, it always points to vmcs01. For a nested 227 * guest (L2), it points to a different VMCS. 228 */ 229 struct loaded_vmcs vmcs01; 230 struct loaded_vmcs *loaded_vmcs; 231 232 struct msr_autoload { 233 struct vmx_msrs guest; 234 struct vmx_msrs host; 235 } msr_autoload; 236 237 struct vmx_msrs msr_autostore; 238 239 struct { 240 int vm86_active; 241 ulong save_rflags; 242 struct kvm_segment segs[8]; 243 } rmode; 244 struct { 245 u32 bitmask; /* 4 bits per segment (1 bit per field) */ 246 struct kvm_save_segment { 247 u16 selector; 248 unsigned long base; 249 u32 limit; 250 u32 ar; 251 } seg[8]; 252 } segment_cache; 253 int vpid; 254 255 /* Support for a guest hypervisor (nested VMX) */ 256 struct nested_vmx nested; 257 258 /* Dynamic PLE window. */ 259 unsigned int ple_window; 260 bool ple_window_dirty; 261 262 /* Support for PML */ 263 #define PML_LOG_NR_ENTRIES 512 264 /* PML is written backwards: this is the first entry written by the CPU */ 265 #define PML_HEAD_INDEX (PML_LOG_NR_ENTRIES-1) 266 267 struct page *pml_pg; 268 269 /* apic deadline value in host tsc */ 270 u64 hv_deadline_tsc; 271 272 /* 273 * Only bits masked by msr_ia32_feature_control_valid_bits can be set in 274 * msr_ia32_feature_control. FEAT_CTL_LOCKED is always included 275 * in msr_ia32_feature_control_valid_bits. 276 */ 277 u64 msr_ia32_feature_control; 278 u64 msr_ia32_feature_control_valid_bits; 279 /* SGX Launch Control public key hash */ 280 u64 msr_ia32_sgxlepubkeyhash[4]; 281 u64 msr_ia32_mcu_opt_ctrl; 282 bool disable_fb_clear; 283 284 struct pt_desc pt_desc; 285 struct lbr_desc lbr_desc; 286 287 /* ve_info must be page aligned. */ 288 struct vmx_ve_information *ve_info; 289 }; 290 291 struct kvm_vmx { 292 struct kvm kvm; 293 294 unsigned int tss_addr; 295 bool ept_identity_pagetable_done; 296 gpa_t ept_identity_map_addr; 297 /* Posted Interrupt Descriptor (PID) table for IPI virtualization */ 298 u64 *pid_table; 299 }; 300 301 static __always_inline struct vcpu_vt *to_vt(struct kvm_vcpu *vcpu) 302 { 303 return &(container_of(vcpu, struct vcpu_vmx, vcpu)->vt); 304 } 305 306 static __always_inline struct kvm_vcpu *vt_to_vcpu(struct vcpu_vt *vt) 307 { 308 return &(container_of(vt, struct vcpu_vmx, vt)->vcpu); 309 } 310 311 static __always_inline union vmx_exit_reason vmx_get_exit_reason(struct kvm_vcpu *vcpu) 312 { 313 return to_vt(vcpu)->exit_reason; 314 } 315 316 static __always_inline unsigned long vmx_get_exit_qual(struct kvm_vcpu *vcpu) 317 { 318 struct vcpu_vt *vt = to_vt(vcpu); 319 320 if (!kvm_register_test_and_mark_available(vcpu, VCPU_EXREG_EXIT_INFO_1) && 321 !WARN_ON_ONCE(is_td_vcpu(vcpu))) 322 vt->exit_qualification = vmcs_readl(EXIT_QUALIFICATION); 323 324 return vt->exit_qualification; 325 } 326 327 static __always_inline u32 vmx_get_intr_info(struct kvm_vcpu *vcpu) 328 { 329 struct vcpu_vt *vt = to_vt(vcpu); 330 331 if (!kvm_register_test_and_mark_available(vcpu, VCPU_EXREG_EXIT_INFO_2) && 332 !WARN_ON_ONCE(is_td_vcpu(vcpu))) 333 vt->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO); 334 335 return vt->exit_intr_info; 336 } 337 338 void vmx_vcpu_load_vmcs(struct kvm_vcpu *vcpu, int cpu); 339 int allocate_vpid(void); 340 void free_vpid(int vpid); 341 void vmx_set_constant_host_state(struct vcpu_vmx *vmx); 342 void vmx_prepare_switch_to_guest(struct kvm_vcpu *vcpu); 343 void vmx_set_host_fs_gs(struct vmcs_host_state *host, u16 fs_sel, u16 gs_sel, 344 unsigned long fs_base, unsigned long gs_base); 345 int vmx_get_cpl(struct kvm_vcpu *vcpu); 346 int vmx_get_cpl_no_cache(struct kvm_vcpu *vcpu); 347 bool vmx_emulation_required(struct kvm_vcpu *vcpu); 348 unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu); 349 void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags); 350 u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu); 351 void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask); 352 int vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer); 353 void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0); 354 void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4); 355 void set_cr4_guest_host_mask(struct vcpu_vmx *vmx); 356 void ept_save_pdptrs(struct kvm_vcpu *vcpu); 357 void vmx_get_segment(struct kvm_vcpu *vcpu, struct kvm_segment *var, int seg); 358 void __vmx_set_segment(struct kvm_vcpu *vcpu, struct kvm_segment *var, int seg); 359 360 bool vmx_guest_inject_ac(struct kvm_vcpu *vcpu); 361 void vmx_update_exception_bitmap(struct kvm_vcpu *vcpu); 362 bool vmx_nmi_blocked(struct kvm_vcpu *vcpu); 363 bool __vmx_interrupt_blocked(struct kvm_vcpu *vcpu); 364 bool vmx_interrupt_blocked(struct kvm_vcpu *vcpu); 365 bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu); 366 void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked); 367 void vmx_set_virtual_apic_mode(struct kvm_vcpu *vcpu); 368 struct vmx_uret_msr *vmx_find_uret_msr(struct vcpu_vmx *vmx, u32 msr); 369 void pt_update_intercept_for_msr(struct kvm_vcpu *vcpu); 370 void vmx_update_host_rsp(struct vcpu_vmx *vmx, unsigned long host_rsp); 371 void vmx_spec_ctrl_restore_host(struct vcpu_vmx *vmx, unsigned int flags); 372 unsigned int __vmx_vcpu_run_flags(struct vcpu_vmx *vmx); 373 bool __vmx_vcpu_run(struct vcpu_vmx *vmx, unsigned long *regs, 374 unsigned int flags); 375 void vmx_ept_load_pdptrs(struct kvm_vcpu *vcpu); 376 377 void vmx_set_intercept_for_msr(struct kvm_vcpu *vcpu, u32 msr, int type, bool set); 378 379 static inline void vmx_disable_intercept_for_msr(struct kvm_vcpu *vcpu, 380 u32 msr, int type) 381 { 382 vmx_set_intercept_for_msr(vcpu, msr, type, false); 383 } 384 385 static inline void vmx_enable_intercept_for_msr(struct kvm_vcpu *vcpu, 386 u32 msr, int type) 387 { 388 vmx_set_intercept_for_msr(vcpu, msr, type, true); 389 } 390 391 u64 vmx_get_l2_tsc_offset(struct kvm_vcpu *vcpu); 392 u64 vmx_get_l2_tsc_multiplier(struct kvm_vcpu *vcpu); 393 394 gva_t vmx_get_untagged_addr(struct kvm_vcpu *vcpu, gva_t gva, unsigned int flags); 395 396 void vmx_update_cpu_dirty_logging(struct kvm_vcpu *vcpu); 397 398 u64 vmx_get_supported_debugctl(struct kvm_vcpu *vcpu, bool host_initiated); 399 bool vmx_is_valid_debugctl(struct kvm_vcpu *vcpu, u64 data, bool host_initiated); 400 401 #define VMX_HOST_OWNED_DEBUGCTL_BITS (DEBUGCTLMSR_FREEZE_IN_SMM) 402 403 static inline void vmx_guest_debugctl_write(struct kvm_vcpu *vcpu, u64 val) 404 { 405 WARN_ON_ONCE(val & VMX_HOST_OWNED_DEBUGCTL_BITS); 406 407 val |= vcpu->arch.host_debugctl & VMX_HOST_OWNED_DEBUGCTL_BITS; 408 vmcs_write64(GUEST_IA32_DEBUGCTL, val); 409 } 410 411 static inline u64 vmx_guest_debugctl_read(void) 412 { 413 return vmcs_read64(GUEST_IA32_DEBUGCTL) & ~VMX_HOST_OWNED_DEBUGCTL_BITS; 414 } 415 416 static inline void vmx_reload_guest_debugctl(struct kvm_vcpu *vcpu) 417 { 418 u64 val = vmcs_read64(GUEST_IA32_DEBUGCTL); 419 420 if (!((val ^ vcpu->arch.host_debugctl) & VMX_HOST_OWNED_DEBUGCTL_BITS)) 421 return; 422 423 vmx_guest_debugctl_write(vcpu, val & ~VMX_HOST_OWNED_DEBUGCTL_BITS); 424 } 425 426 /* 427 * Note, early Intel manuals have the write-low and read-high bitmap offsets 428 * the wrong way round. The bitmaps control MSRs 0x00000000-0x00001fff and 429 * 0xc0000000-0xc0001fff. The former (low) uses bytes 0-0x3ff for reads and 430 * 0x800-0xbff for writes. The latter (high) uses 0x400-0x7ff for reads and 431 * 0xc00-0xfff for writes. MSRs not covered by either of the ranges always 432 * VM-Exit. 433 */ 434 #define __BUILD_VMX_MSR_BITMAP_HELPER(rtype, action, bitop, access, base) \ 435 static inline rtype vmx_##action##_msr_bitmap_##access(unsigned long *bitmap, \ 436 u32 msr) \ 437 { \ 438 int f = sizeof(unsigned long); \ 439 \ 440 if (msr <= 0x1fff) \ 441 return bitop##_bit(msr, bitmap + base / f); \ 442 else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) \ 443 return bitop##_bit(msr & 0x1fff, bitmap + (base + 0x400) / f); \ 444 return (rtype)true; \ 445 } 446 #define BUILD_VMX_MSR_BITMAP_HELPERS(ret_type, action, bitop) \ 447 __BUILD_VMX_MSR_BITMAP_HELPER(ret_type, action, bitop, read, 0x0) \ 448 __BUILD_VMX_MSR_BITMAP_HELPER(ret_type, action, bitop, write, 0x800) 449 450 BUILD_VMX_MSR_BITMAP_HELPERS(bool, test, test) 451 BUILD_VMX_MSR_BITMAP_HELPERS(void, clear, __clear) 452 BUILD_VMX_MSR_BITMAP_HELPERS(void, set, __set) 453 454 static inline u8 vmx_get_rvi(void) 455 { 456 return vmcs_read16(GUEST_INTR_STATUS) & 0xff; 457 } 458 459 #define __KVM_REQUIRED_VMX_VM_ENTRY_CONTROLS \ 460 (VM_ENTRY_LOAD_DEBUG_CONTROLS) 461 #ifdef CONFIG_X86_64 462 #define KVM_REQUIRED_VMX_VM_ENTRY_CONTROLS \ 463 (__KVM_REQUIRED_VMX_VM_ENTRY_CONTROLS | \ 464 VM_ENTRY_IA32E_MODE) 465 #else 466 #define KVM_REQUIRED_VMX_VM_ENTRY_CONTROLS \ 467 __KVM_REQUIRED_VMX_VM_ENTRY_CONTROLS 468 #endif 469 #define KVM_OPTIONAL_VMX_VM_ENTRY_CONTROLS \ 470 (VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | \ 471 VM_ENTRY_LOAD_IA32_PAT | \ 472 VM_ENTRY_LOAD_IA32_EFER | \ 473 VM_ENTRY_LOAD_BNDCFGS | \ 474 VM_ENTRY_PT_CONCEAL_PIP | \ 475 VM_ENTRY_LOAD_IA32_RTIT_CTL | \ 476 VM_ENTRY_LOAD_CET_STATE) 477 478 #define __KVM_REQUIRED_VMX_VM_EXIT_CONTROLS \ 479 (VM_EXIT_SAVE_DEBUG_CONTROLS | \ 480 VM_EXIT_ACK_INTR_ON_EXIT) 481 #ifdef CONFIG_X86_64 482 #define KVM_REQUIRED_VMX_VM_EXIT_CONTROLS \ 483 (__KVM_REQUIRED_VMX_VM_EXIT_CONTROLS | \ 484 VM_EXIT_HOST_ADDR_SPACE_SIZE) 485 #else 486 #define KVM_REQUIRED_VMX_VM_EXIT_CONTROLS \ 487 __KVM_REQUIRED_VMX_VM_EXIT_CONTROLS 488 #endif 489 #define KVM_OPTIONAL_VMX_VM_EXIT_CONTROLS \ 490 (VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | \ 491 VM_EXIT_SAVE_IA32_PAT | \ 492 VM_EXIT_LOAD_IA32_PAT | \ 493 VM_EXIT_SAVE_IA32_EFER | \ 494 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER | \ 495 VM_EXIT_LOAD_IA32_EFER | \ 496 VM_EXIT_CLEAR_BNDCFGS | \ 497 VM_EXIT_PT_CONCEAL_PIP | \ 498 VM_EXIT_CLEAR_IA32_RTIT_CTL | \ 499 VM_EXIT_LOAD_CET_STATE | \ 500 VM_EXIT_SAVE_IA32_PERF_GLOBAL_CTRL) 501 502 #define KVM_REQUIRED_VMX_PIN_BASED_VM_EXEC_CONTROL \ 503 (PIN_BASED_EXT_INTR_MASK | \ 504 PIN_BASED_NMI_EXITING) 505 #define KVM_OPTIONAL_VMX_PIN_BASED_VM_EXEC_CONTROL \ 506 (PIN_BASED_VIRTUAL_NMIS | \ 507 PIN_BASED_POSTED_INTR | \ 508 PIN_BASED_VMX_PREEMPTION_TIMER) 509 510 #define __KVM_REQUIRED_VMX_CPU_BASED_VM_EXEC_CONTROL \ 511 (CPU_BASED_HLT_EXITING | \ 512 CPU_BASED_CR3_LOAD_EXITING | \ 513 CPU_BASED_CR3_STORE_EXITING | \ 514 CPU_BASED_UNCOND_IO_EXITING | \ 515 CPU_BASED_MOV_DR_EXITING | \ 516 CPU_BASED_USE_TSC_OFFSETTING | \ 517 CPU_BASED_MWAIT_EXITING | \ 518 CPU_BASED_MONITOR_EXITING | \ 519 CPU_BASED_INVLPG_EXITING | \ 520 CPU_BASED_RDPMC_EXITING | \ 521 CPU_BASED_INTR_WINDOW_EXITING) 522 523 #ifdef CONFIG_X86_64 524 #define KVM_REQUIRED_VMX_CPU_BASED_VM_EXEC_CONTROL \ 525 (__KVM_REQUIRED_VMX_CPU_BASED_VM_EXEC_CONTROL | \ 526 CPU_BASED_CR8_LOAD_EXITING | \ 527 CPU_BASED_CR8_STORE_EXITING) 528 #else 529 #define KVM_REQUIRED_VMX_CPU_BASED_VM_EXEC_CONTROL \ 530 __KVM_REQUIRED_VMX_CPU_BASED_VM_EXEC_CONTROL 531 #endif 532 533 #define KVM_OPTIONAL_VMX_CPU_BASED_VM_EXEC_CONTROL \ 534 (CPU_BASED_RDTSC_EXITING | \ 535 CPU_BASED_TPR_SHADOW | \ 536 CPU_BASED_USE_IO_BITMAPS | \ 537 CPU_BASED_MONITOR_TRAP_FLAG | \ 538 CPU_BASED_USE_MSR_BITMAPS | \ 539 CPU_BASED_NMI_WINDOW_EXITING | \ 540 CPU_BASED_PAUSE_EXITING | \ 541 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS | \ 542 CPU_BASED_ACTIVATE_TERTIARY_CONTROLS) 543 544 #define KVM_REQUIRED_VMX_SECONDARY_VM_EXEC_CONTROL 0 545 #define KVM_OPTIONAL_VMX_SECONDARY_VM_EXEC_CONTROL \ 546 (SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | \ 547 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | \ 548 SECONDARY_EXEC_WBINVD_EXITING | \ 549 SECONDARY_EXEC_ENABLE_VPID | \ 550 SECONDARY_EXEC_ENABLE_EPT | \ 551 SECONDARY_EXEC_UNRESTRICTED_GUEST | \ 552 SECONDARY_EXEC_PAUSE_LOOP_EXITING | \ 553 SECONDARY_EXEC_DESC | \ 554 SECONDARY_EXEC_ENABLE_RDTSCP | \ 555 SECONDARY_EXEC_ENABLE_INVPCID | \ 556 SECONDARY_EXEC_APIC_REGISTER_VIRT | \ 557 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | \ 558 SECONDARY_EXEC_SHADOW_VMCS | \ 559 SECONDARY_EXEC_ENABLE_XSAVES | \ 560 SECONDARY_EXEC_RDSEED_EXITING | \ 561 SECONDARY_EXEC_RDRAND_EXITING | \ 562 SECONDARY_EXEC_ENABLE_PML | \ 563 SECONDARY_EXEC_TSC_SCALING | \ 564 SECONDARY_EXEC_ENABLE_USR_WAIT_PAUSE | \ 565 SECONDARY_EXEC_PT_USE_GPA | \ 566 SECONDARY_EXEC_PT_CONCEAL_VMX | \ 567 SECONDARY_EXEC_ENABLE_VMFUNC | \ 568 SECONDARY_EXEC_BUS_LOCK_DETECTION | \ 569 SECONDARY_EXEC_NOTIFY_VM_EXITING | \ 570 SECONDARY_EXEC_ENCLS_EXITING | \ 571 SECONDARY_EXEC_EPT_VIOLATION_VE) 572 573 #define KVM_REQUIRED_VMX_TERTIARY_VM_EXEC_CONTROL 0 574 #define KVM_OPTIONAL_VMX_TERTIARY_VM_EXEC_CONTROL \ 575 (TERTIARY_EXEC_IPI_VIRT) 576 577 #define BUILD_CONTROLS_SHADOW(lname, uname, bits) \ 578 static inline void lname##_controls_set(struct vcpu_vmx *vmx, u##bits val) \ 579 { \ 580 if (vmx->loaded_vmcs->controls_shadow.lname != val) { \ 581 vmcs_write##bits(uname, val); \ 582 vmx->loaded_vmcs->controls_shadow.lname = val; \ 583 } \ 584 } \ 585 static inline u##bits __##lname##_controls_get(struct loaded_vmcs *vmcs) \ 586 { \ 587 return vmcs->controls_shadow.lname; \ 588 } \ 589 static inline u##bits lname##_controls_get(struct vcpu_vmx *vmx) \ 590 { \ 591 return __##lname##_controls_get(vmx->loaded_vmcs); \ 592 } \ 593 static __always_inline void lname##_controls_setbit(struct vcpu_vmx *vmx, u##bits val) \ 594 { \ 595 BUILD_BUG_ON(!(val & (KVM_REQUIRED_VMX_##uname | KVM_OPTIONAL_VMX_##uname))); \ 596 lname##_controls_set(vmx, lname##_controls_get(vmx) | val); \ 597 } \ 598 static __always_inline void lname##_controls_clearbit(struct vcpu_vmx *vmx, u##bits val) \ 599 { \ 600 BUILD_BUG_ON(!(val & (KVM_REQUIRED_VMX_##uname | KVM_OPTIONAL_VMX_##uname))); \ 601 lname##_controls_set(vmx, lname##_controls_get(vmx) & ~val); \ 602 } \ 603 static __always_inline void lname##_controls_changebit(struct vcpu_vmx *vmx, u##bits val, \ 604 bool set) \ 605 { \ 606 if (set) \ 607 lname##_controls_setbit(vmx, val); \ 608 else \ 609 lname##_controls_clearbit(vmx, val); \ 610 } 611 BUILD_CONTROLS_SHADOW(vm_entry, VM_ENTRY_CONTROLS, 32) 612 BUILD_CONTROLS_SHADOW(vm_exit, VM_EXIT_CONTROLS, 32) 613 BUILD_CONTROLS_SHADOW(pin, PIN_BASED_VM_EXEC_CONTROL, 32) 614 BUILD_CONTROLS_SHADOW(exec, CPU_BASED_VM_EXEC_CONTROL, 32) 615 BUILD_CONTROLS_SHADOW(secondary_exec, SECONDARY_VM_EXEC_CONTROL, 32) 616 BUILD_CONTROLS_SHADOW(tertiary_exec, TERTIARY_VM_EXEC_CONTROL, 64) 617 618 /* 619 * VMX_REGS_LAZY_LOAD_SET - The set of registers that will be updated in the 620 * cache on demand. Other registers not listed here are synced to 621 * the cache immediately after VM-Exit. 622 */ 623 #define VMX_REGS_LAZY_LOAD_SET ((1 << VCPU_REGS_RIP) | \ 624 (1 << VCPU_REGS_RSP) | \ 625 (1 << VCPU_EXREG_RFLAGS) | \ 626 (1 << VCPU_EXREG_PDPTR) | \ 627 (1 << VCPU_EXREG_SEGMENTS) | \ 628 (1 << VCPU_EXREG_CR0) | \ 629 (1 << VCPU_EXREG_CR3) | \ 630 (1 << VCPU_EXREG_CR4) | \ 631 (1 << VCPU_EXREG_EXIT_INFO_1) | \ 632 (1 << VCPU_EXREG_EXIT_INFO_2)) 633 634 static inline unsigned long vmx_l1_guest_owned_cr0_bits(void) 635 { 636 unsigned long bits = KVM_POSSIBLE_CR0_GUEST_BITS; 637 638 /* 639 * CR0.WP needs to be intercepted when KVM is shadowing legacy paging 640 * in order to construct shadow PTEs with the correct protections. 641 * Note! CR0.WP technically can be passed through to the guest if 642 * paging is disabled, but checking CR0.PG would generate a cyclical 643 * dependency of sorts due to forcing the caller to ensure CR0 holds 644 * the correct value prior to determining which CR0 bits can be owned 645 * by L1. Keep it simple and limit the optimization to EPT. 646 */ 647 if (!enable_ept) 648 bits &= ~X86_CR0_WP; 649 return bits; 650 } 651 652 static __always_inline struct kvm_vmx *to_kvm_vmx(struct kvm *kvm) 653 { 654 return container_of(kvm, struct kvm_vmx, kvm); 655 } 656 657 static __always_inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu) 658 { 659 return container_of(vcpu, struct vcpu_vmx, vcpu); 660 } 661 662 void intel_pmu_cross_mapped_check(struct kvm_pmu *pmu); 663 int intel_pmu_create_guest_lbr_event(struct kvm_vcpu *vcpu); 664 void vmx_passthrough_lbr_msrs(struct kvm_vcpu *vcpu); 665 666 struct vmcs *alloc_vmcs_cpu(bool shadow, int cpu, gfp_t flags); 667 void free_vmcs(struct vmcs *vmcs); 668 int alloc_loaded_vmcs(struct loaded_vmcs *loaded_vmcs); 669 void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs); 670 671 static inline struct vmcs *alloc_vmcs(bool shadow) 672 { 673 return alloc_vmcs_cpu(shadow, raw_smp_processor_id(), 674 GFP_KERNEL_ACCOUNT); 675 } 676 677 static inline bool vmx_has_waitpkg(struct vcpu_vmx *vmx) 678 { 679 return secondary_exec_controls_get(vmx) & 680 SECONDARY_EXEC_ENABLE_USR_WAIT_PAUSE; 681 } 682 683 static inline bool vmx_need_pf_intercept(struct kvm_vcpu *vcpu) 684 { 685 if (!enable_ept) 686 return true; 687 688 return allow_smaller_maxphyaddr && 689 cpuid_maxphyaddr(vcpu) < kvm_host.maxphyaddr; 690 } 691 692 static inline bool is_unrestricted_guest(struct kvm_vcpu *vcpu) 693 { 694 return enable_unrestricted_guest && (!is_guest_mode(vcpu) || 695 (secondary_exec_controls_get(to_vmx(vcpu)) & 696 SECONDARY_EXEC_UNRESTRICTED_GUEST)); 697 } 698 699 bool __vmx_guest_state_valid(struct kvm_vcpu *vcpu); 700 static inline bool vmx_guest_state_valid(struct kvm_vcpu *vcpu) 701 { 702 return is_unrestricted_guest(vcpu) || __vmx_guest_state_valid(vcpu); 703 } 704 705 void dump_vmcs(struct kvm_vcpu *vcpu); 706 707 static inline int vmx_get_instr_info_reg(u32 vmx_instr_info) 708 { 709 return (vmx_instr_info >> 3) & 0xf; 710 } 711 712 static inline int vmx_get_instr_info_reg2(u32 vmx_instr_info) 713 { 714 return (vmx_instr_info >> 28) & 0xf; 715 } 716 717 static inline bool vmx_can_use_ipiv(struct kvm_vcpu *vcpu) 718 { 719 return lapic_in_kernel(vcpu) && enable_ipiv; 720 } 721 722 static inline void vmx_segment_cache_clear(struct vcpu_vmx *vmx) 723 { 724 vmx->segment_cache.bitmask = 0; 725 } 726 727 int vmx_init(void); 728 void vmx_exit(void); 729 730 #endif /* __KVM_X86_VMX_H */ 731