1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Kernel-based Virtual Machine driver for Linux 4 * 5 * This module enables machines with Intel VT-x extensions to run virtual 6 * machines without emulation or binary translation. 7 * 8 * Copyright (C) 2006 Qumranet, Inc. 9 * Copyright 2010 Red Hat, Inc. and/or its affiliates. 10 * 11 * Authors: 12 * Avi Kivity <avi@qumranet.com> 13 * Yaniv Kamay <yaniv@qumranet.com> 14 */ 15 16 #include <linux/frame.h> 17 #include <linux/highmem.h> 18 #include <linux/hrtimer.h> 19 #include <linux/kernel.h> 20 #include <linux/kvm_host.h> 21 #include <linux/module.h> 22 #include <linux/moduleparam.h> 23 #include <linux/mod_devicetable.h> 24 #include <linux/mm.h> 25 #include <linux/sched.h> 26 #include <linux/sched/smt.h> 27 #include <linux/slab.h> 28 #include <linux/tboot.h> 29 #include <linux/trace_events.h> 30 31 #include <asm/apic.h> 32 #include <asm/asm.h> 33 #include <asm/cpu.h> 34 #include <asm/debugreg.h> 35 #include <asm/desc.h> 36 #include <asm/fpu/internal.h> 37 #include <asm/io.h> 38 #include <asm/irq_remapping.h> 39 #include <asm/kexec.h> 40 #include <asm/perf_event.h> 41 #include <asm/mce.h> 42 #include <asm/mmu_context.h> 43 #include <asm/mshyperv.h> 44 #include <asm/spec-ctrl.h> 45 #include <asm/virtext.h> 46 #include <asm/vmx.h> 47 48 #include "capabilities.h" 49 #include "cpuid.h" 50 #include "evmcs.h" 51 #include "irq.h" 52 #include "kvm_cache_regs.h" 53 #include "lapic.h" 54 #include "mmu.h" 55 #include "nested.h" 56 #include "ops.h" 57 #include "pmu.h" 58 #include "trace.h" 59 #include "vmcs.h" 60 #include "vmcs12.h" 61 #include "vmx.h" 62 #include "x86.h" 63 64 MODULE_AUTHOR("Qumranet"); 65 MODULE_LICENSE("GPL"); 66 67 static const struct x86_cpu_id vmx_cpu_id[] = { 68 X86_FEATURE_MATCH(X86_FEATURE_VMX), 69 {} 70 }; 71 MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id); 72 73 bool __read_mostly enable_vpid = 1; 74 module_param_named(vpid, enable_vpid, bool, 0444); 75 76 static bool __read_mostly enable_vnmi = 1; 77 module_param_named(vnmi, enable_vnmi, bool, S_IRUGO); 78 79 bool __read_mostly flexpriority_enabled = 1; 80 module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO); 81 82 bool __read_mostly enable_ept = 1; 83 module_param_named(ept, enable_ept, bool, S_IRUGO); 84 85 bool __read_mostly enable_unrestricted_guest = 1; 86 module_param_named(unrestricted_guest, 87 enable_unrestricted_guest, bool, S_IRUGO); 88 89 bool __read_mostly enable_ept_ad_bits = 1; 90 module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO); 91 92 static bool __read_mostly emulate_invalid_guest_state = true; 93 module_param(emulate_invalid_guest_state, bool, S_IRUGO); 94 95 static bool __read_mostly fasteoi = 1; 96 module_param(fasteoi, bool, S_IRUGO); 97 98 static bool __read_mostly enable_apicv = 1; 99 module_param(enable_apicv, bool, S_IRUGO); 100 101 /* 102 * If nested=1, nested virtualization is supported, i.e., guests may use 103 * VMX and be a hypervisor for its own guests. If nested=0, guests may not 104 * use VMX instructions. 105 */ 106 static bool __read_mostly nested = 1; 107 module_param(nested, bool, S_IRUGO); 108 109 bool __read_mostly enable_pml = 1; 110 module_param_named(pml, enable_pml, bool, S_IRUGO); 111 112 static bool __read_mostly dump_invalid_vmcs = 0; 113 module_param(dump_invalid_vmcs, bool, 0644); 114 115 #define MSR_BITMAP_MODE_X2APIC 1 116 #define MSR_BITMAP_MODE_X2APIC_APICV 2 117 118 #define KVM_VMX_TSC_MULTIPLIER_MAX 0xffffffffffffffffULL 119 120 /* Guest_tsc -> host_tsc conversion requires 64-bit division. */ 121 static int __read_mostly cpu_preemption_timer_multi; 122 static bool __read_mostly enable_preemption_timer = 1; 123 #ifdef CONFIG_X86_64 124 module_param_named(preemption_timer, enable_preemption_timer, bool, S_IRUGO); 125 #endif 126 127 #define KVM_VM_CR0_ALWAYS_OFF (X86_CR0_NW | X86_CR0_CD) 128 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST X86_CR0_NE 129 #define KVM_VM_CR0_ALWAYS_ON \ 130 (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | \ 131 X86_CR0_WP | X86_CR0_PG | X86_CR0_PE) 132 #define KVM_CR4_GUEST_OWNED_BITS \ 133 (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \ 134 | X86_CR4_OSXMMEXCPT | X86_CR4_LA57 | X86_CR4_TSD) 135 136 #define KVM_VM_CR4_ALWAYS_ON_UNRESTRICTED_GUEST X86_CR4_VMXE 137 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE) 138 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE) 139 140 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM)) 141 142 #define MSR_IA32_RTIT_STATUS_MASK (~(RTIT_STATUS_FILTEREN | \ 143 RTIT_STATUS_CONTEXTEN | RTIT_STATUS_TRIGGEREN | \ 144 RTIT_STATUS_ERROR | RTIT_STATUS_STOPPED | \ 145 RTIT_STATUS_BYTECNT)) 146 147 #define MSR_IA32_RTIT_OUTPUT_BASE_MASK \ 148 (~((1UL << cpuid_query_maxphyaddr(vcpu)) - 1) | 0x7f) 149 150 /* 151 * These 2 parameters are used to config the controls for Pause-Loop Exiting: 152 * ple_gap: upper bound on the amount of time between two successive 153 * executions of PAUSE in a loop. Also indicate if ple enabled. 154 * According to test, this time is usually smaller than 128 cycles. 155 * ple_window: upper bound on the amount of time a guest is allowed to execute 156 * in a PAUSE loop. Tests indicate that most spinlocks are held for 157 * less than 2^12 cycles 158 * Time is measured based on a counter that runs at the same rate as the TSC, 159 * refer SDM volume 3b section 21.6.13 & 22.1.3. 160 */ 161 static unsigned int ple_gap = KVM_DEFAULT_PLE_GAP; 162 module_param(ple_gap, uint, 0444); 163 164 static unsigned int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW; 165 module_param(ple_window, uint, 0444); 166 167 /* Default doubles per-vcpu window every exit. */ 168 static unsigned int ple_window_grow = KVM_DEFAULT_PLE_WINDOW_GROW; 169 module_param(ple_window_grow, uint, 0444); 170 171 /* Default resets per-vcpu window every exit to ple_window. */ 172 static unsigned int ple_window_shrink = KVM_DEFAULT_PLE_WINDOW_SHRINK; 173 module_param(ple_window_shrink, uint, 0444); 174 175 /* Default is to compute the maximum so we can never overflow. */ 176 static unsigned int ple_window_max = KVM_VMX_DEFAULT_PLE_WINDOW_MAX; 177 module_param(ple_window_max, uint, 0444); 178 179 /* Default is SYSTEM mode, 1 for host-guest mode */ 180 int __read_mostly pt_mode = PT_MODE_SYSTEM; 181 module_param(pt_mode, int, S_IRUGO); 182 183 static DEFINE_STATIC_KEY_FALSE(vmx_l1d_should_flush); 184 static DEFINE_STATIC_KEY_FALSE(vmx_l1d_flush_cond); 185 static DEFINE_MUTEX(vmx_l1d_flush_mutex); 186 187 /* Storage for pre module init parameter parsing */ 188 static enum vmx_l1d_flush_state __read_mostly vmentry_l1d_flush_param = VMENTER_L1D_FLUSH_AUTO; 189 190 static const struct { 191 const char *option; 192 bool for_parse; 193 } vmentry_l1d_param[] = { 194 [VMENTER_L1D_FLUSH_AUTO] = {"auto", true}, 195 [VMENTER_L1D_FLUSH_NEVER] = {"never", true}, 196 [VMENTER_L1D_FLUSH_COND] = {"cond", true}, 197 [VMENTER_L1D_FLUSH_ALWAYS] = {"always", true}, 198 [VMENTER_L1D_FLUSH_EPT_DISABLED] = {"EPT disabled", false}, 199 [VMENTER_L1D_FLUSH_NOT_REQUIRED] = {"not required", false}, 200 }; 201 202 #define L1D_CACHE_ORDER 4 203 static void *vmx_l1d_flush_pages; 204 205 static int vmx_setup_l1d_flush(enum vmx_l1d_flush_state l1tf) 206 { 207 struct page *page; 208 unsigned int i; 209 210 if (!boot_cpu_has_bug(X86_BUG_L1TF)) { 211 l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_NOT_REQUIRED; 212 return 0; 213 } 214 215 if (!enable_ept) { 216 l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_EPT_DISABLED; 217 return 0; 218 } 219 220 if (boot_cpu_has(X86_FEATURE_ARCH_CAPABILITIES)) { 221 u64 msr; 222 223 rdmsrl(MSR_IA32_ARCH_CAPABILITIES, msr); 224 if (msr & ARCH_CAP_SKIP_VMENTRY_L1DFLUSH) { 225 l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_NOT_REQUIRED; 226 return 0; 227 } 228 } 229 230 /* If set to auto use the default l1tf mitigation method */ 231 if (l1tf == VMENTER_L1D_FLUSH_AUTO) { 232 switch (l1tf_mitigation) { 233 case L1TF_MITIGATION_OFF: 234 l1tf = VMENTER_L1D_FLUSH_NEVER; 235 break; 236 case L1TF_MITIGATION_FLUSH_NOWARN: 237 case L1TF_MITIGATION_FLUSH: 238 case L1TF_MITIGATION_FLUSH_NOSMT: 239 l1tf = VMENTER_L1D_FLUSH_COND; 240 break; 241 case L1TF_MITIGATION_FULL: 242 case L1TF_MITIGATION_FULL_FORCE: 243 l1tf = VMENTER_L1D_FLUSH_ALWAYS; 244 break; 245 } 246 } else if (l1tf_mitigation == L1TF_MITIGATION_FULL_FORCE) { 247 l1tf = VMENTER_L1D_FLUSH_ALWAYS; 248 } 249 250 if (l1tf != VMENTER_L1D_FLUSH_NEVER && !vmx_l1d_flush_pages && 251 !boot_cpu_has(X86_FEATURE_FLUSH_L1D)) { 252 /* 253 * This allocation for vmx_l1d_flush_pages is not tied to a VM 254 * lifetime and so should not be charged to a memcg. 255 */ 256 page = alloc_pages(GFP_KERNEL, L1D_CACHE_ORDER); 257 if (!page) 258 return -ENOMEM; 259 vmx_l1d_flush_pages = page_address(page); 260 261 /* 262 * Initialize each page with a different pattern in 263 * order to protect against KSM in the nested 264 * virtualization case. 265 */ 266 for (i = 0; i < 1u << L1D_CACHE_ORDER; ++i) { 267 memset(vmx_l1d_flush_pages + i * PAGE_SIZE, i + 1, 268 PAGE_SIZE); 269 } 270 } 271 272 l1tf_vmx_mitigation = l1tf; 273 274 if (l1tf != VMENTER_L1D_FLUSH_NEVER) 275 static_branch_enable(&vmx_l1d_should_flush); 276 else 277 static_branch_disable(&vmx_l1d_should_flush); 278 279 if (l1tf == VMENTER_L1D_FLUSH_COND) 280 static_branch_enable(&vmx_l1d_flush_cond); 281 else 282 static_branch_disable(&vmx_l1d_flush_cond); 283 return 0; 284 } 285 286 static int vmentry_l1d_flush_parse(const char *s) 287 { 288 unsigned int i; 289 290 if (s) { 291 for (i = 0; i < ARRAY_SIZE(vmentry_l1d_param); i++) { 292 if (vmentry_l1d_param[i].for_parse && 293 sysfs_streq(s, vmentry_l1d_param[i].option)) 294 return i; 295 } 296 } 297 return -EINVAL; 298 } 299 300 static int vmentry_l1d_flush_set(const char *s, const struct kernel_param *kp) 301 { 302 int l1tf, ret; 303 304 l1tf = vmentry_l1d_flush_parse(s); 305 if (l1tf < 0) 306 return l1tf; 307 308 if (!boot_cpu_has(X86_BUG_L1TF)) 309 return 0; 310 311 /* 312 * Has vmx_init() run already? If not then this is the pre init 313 * parameter parsing. In that case just store the value and let 314 * vmx_init() do the proper setup after enable_ept has been 315 * established. 316 */ 317 if (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_AUTO) { 318 vmentry_l1d_flush_param = l1tf; 319 return 0; 320 } 321 322 mutex_lock(&vmx_l1d_flush_mutex); 323 ret = vmx_setup_l1d_flush(l1tf); 324 mutex_unlock(&vmx_l1d_flush_mutex); 325 return ret; 326 } 327 328 static int vmentry_l1d_flush_get(char *s, const struct kernel_param *kp) 329 { 330 if (WARN_ON_ONCE(l1tf_vmx_mitigation >= ARRAY_SIZE(vmentry_l1d_param))) 331 return sprintf(s, "???\n"); 332 333 return sprintf(s, "%s\n", vmentry_l1d_param[l1tf_vmx_mitigation].option); 334 } 335 336 static const struct kernel_param_ops vmentry_l1d_flush_ops = { 337 .set = vmentry_l1d_flush_set, 338 .get = vmentry_l1d_flush_get, 339 }; 340 module_param_cb(vmentry_l1d_flush, &vmentry_l1d_flush_ops, NULL, 0644); 341 342 static bool guest_state_valid(struct kvm_vcpu *vcpu); 343 static u32 vmx_segment_access_rights(struct kvm_segment *var); 344 static __always_inline void vmx_disable_intercept_for_msr(unsigned long *msr_bitmap, 345 u32 msr, int type); 346 347 void vmx_vmexit(void); 348 349 #define vmx_insn_failed(fmt...) \ 350 do { \ 351 WARN_ONCE(1, fmt); \ 352 pr_warn_ratelimited(fmt); \ 353 } while (0) 354 355 asmlinkage void vmread_error(unsigned long field, bool fault) 356 { 357 if (fault) 358 kvm_spurious_fault(); 359 else 360 vmx_insn_failed("kvm: vmread failed: field=%lx\n", field); 361 } 362 363 noinline void vmwrite_error(unsigned long field, unsigned long value) 364 { 365 vmx_insn_failed("kvm: vmwrite failed: field=%lx val=%lx err=%d\n", 366 field, value, vmcs_read32(VM_INSTRUCTION_ERROR)); 367 } 368 369 noinline void vmclear_error(struct vmcs *vmcs, u64 phys_addr) 370 { 371 vmx_insn_failed("kvm: vmclear failed: %p/%llx\n", vmcs, phys_addr); 372 } 373 374 noinline void vmptrld_error(struct vmcs *vmcs, u64 phys_addr) 375 { 376 vmx_insn_failed("kvm: vmptrld failed: %p/%llx\n", vmcs, phys_addr); 377 } 378 379 noinline void invvpid_error(unsigned long ext, u16 vpid, gva_t gva) 380 { 381 vmx_insn_failed("kvm: invvpid failed: ext=0x%lx vpid=%u gva=0x%lx\n", 382 ext, vpid, gva); 383 } 384 385 noinline void invept_error(unsigned long ext, u64 eptp, gpa_t gpa) 386 { 387 vmx_insn_failed("kvm: invept failed: ext=0x%lx eptp=%llx gpa=0x%llx\n", 388 ext, eptp, gpa); 389 } 390 391 static DEFINE_PER_CPU(struct vmcs *, vmxarea); 392 DEFINE_PER_CPU(struct vmcs *, current_vmcs); 393 /* 394 * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed 395 * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it. 396 */ 397 static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu); 398 399 /* 400 * We maintian a per-CPU linked-list of vCPU, so in wakeup_handler() we 401 * can find which vCPU should be waken up. 402 */ 403 static DEFINE_PER_CPU(struct list_head, blocked_vcpu_on_cpu); 404 static DEFINE_PER_CPU(spinlock_t, blocked_vcpu_on_cpu_lock); 405 406 static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS); 407 static DEFINE_SPINLOCK(vmx_vpid_lock); 408 409 struct vmcs_config vmcs_config; 410 struct vmx_capability vmx_capability; 411 412 #define VMX_SEGMENT_FIELD(seg) \ 413 [VCPU_SREG_##seg] = { \ 414 .selector = GUEST_##seg##_SELECTOR, \ 415 .base = GUEST_##seg##_BASE, \ 416 .limit = GUEST_##seg##_LIMIT, \ 417 .ar_bytes = GUEST_##seg##_AR_BYTES, \ 418 } 419 420 static const struct kvm_vmx_segment_field { 421 unsigned selector; 422 unsigned base; 423 unsigned limit; 424 unsigned ar_bytes; 425 } kvm_vmx_segment_fields[] = { 426 VMX_SEGMENT_FIELD(CS), 427 VMX_SEGMENT_FIELD(DS), 428 VMX_SEGMENT_FIELD(ES), 429 VMX_SEGMENT_FIELD(FS), 430 VMX_SEGMENT_FIELD(GS), 431 VMX_SEGMENT_FIELD(SS), 432 VMX_SEGMENT_FIELD(TR), 433 VMX_SEGMENT_FIELD(LDTR), 434 }; 435 436 u64 host_efer; 437 static unsigned long host_idt_base; 438 439 /* 440 * Though SYSCALL is only supported in 64-bit mode on Intel CPUs, kvm 441 * will emulate SYSCALL in legacy mode if the vendor string in guest 442 * CPUID.0:{EBX,ECX,EDX} is "AuthenticAMD" or "AMDisbetter!" To 443 * support this emulation, IA32_STAR must always be included in 444 * vmx_msr_index[], even in i386 builds. 445 */ 446 const u32 vmx_msr_index[] = { 447 #ifdef CONFIG_X86_64 448 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR, 449 #endif 450 MSR_EFER, MSR_TSC_AUX, MSR_STAR, 451 MSR_IA32_TSX_CTRL, 452 }; 453 454 #if IS_ENABLED(CONFIG_HYPERV) 455 static bool __read_mostly enlightened_vmcs = true; 456 module_param(enlightened_vmcs, bool, 0444); 457 458 /* check_ept_pointer() should be under protection of ept_pointer_lock. */ 459 static void check_ept_pointer_match(struct kvm *kvm) 460 { 461 struct kvm_vcpu *vcpu; 462 u64 tmp_eptp = INVALID_PAGE; 463 int i; 464 465 kvm_for_each_vcpu(i, vcpu, kvm) { 466 if (!VALID_PAGE(tmp_eptp)) { 467 tmp_eptp = to_vmx(vcpu)->ept_pointer; 468 } else if (tmp_eptp != to_vmx(vcpu)->ept_pointer) { 469 to_kvm_vmx(kvm)->ept_pointers_match 470 = EPT_POINTERS_MISMATCH; 471 return; 472 } 473 } 474 475 to_kvm_vmx(kvm)->ept_pointers_match = EPT_POINTERS_MATCH; 476 } 477 478 static int kvm_fill_hv_flush_list_func(struct hv_guest_mapping_flush_list *flush, 479 void *data) 480 { 481 struct kvm_tlb_range *range = data; 482 483 return hyperv_fill_flush_guest_mapping_list(flush, range->start_gfn, 484 range->pages); 485 } 486 487 static inline int __hv_remote_flush_tlb_with_range(struct kvm *kvm, 488 struct kvm_vcpu *vcpu, struct kvm_tlb_range *range) 489 { 490 u64 ept_pointer = to_vmx(vcpu)->ept_pointer; 491 492 /* 493 * FLUSH_GUEST_PHYSICAL_ADDRESS_SPACE hypercall needs address 494 * of the base of EPT PML4 table, strip off EPT configuration 495 * information. 496 */ 497 if (range) 498 return hyperv_flush_guest_mapping_range(ept_pointer & PAGE_MASK, 499 kvm_fill_hv_flush_list_func, (void *)range); 500 else 501 return hyperv_flush_guest_mapping(ept_pointer & PAGE_MASK); 502 } 503 504 static int hv_remote_flush_tlb_with_range(struct kvm *kvm, 505 struct kvm_tlb_range *range) 506 { 507 struct kvm_vcpu *vcpu; 508 int ret = 0, i; 509 510 spin_lock(&to_kvm_vmx(kvm)->ept_pointer_lock); 511 512 if (to_kvm_vmx(kvm)->ept_pointers_match == EPT_POINTERS_CHECK) 513 check_ept_pointer_match(kvm); 514 515 if (to_kvm_vmx(kvm)->ept_pointers_match != EPT_POINTERS_MATCH) { 516 kvm_for_each_vcpu(i, vcpu, kvm) { 517 /* If ept_pointer is invalid pointer, bypass flush request. */ 518 if (VALID_PAGE(to_vmx(vcpu)->ept_pointer)) 519 ret |= __hv_remote_flush_tlb_with_range( 520 kvm, vcpu, range); 521 } 522 } else { 523 ret = __hv_remote_flush_tlb_with_range(kvm, 524 kvm_get_vcpu(kvm, 0), range); 525 } 526 527 spin_unlock(&to_kvm_vmx(kvm)->ept_pointer_lock); 528 return ret; 529 } 530 static int hv_remote_flush_tlb(struct kvm *kvm) 531 { 532 return hv_remote_flush_tlb_with_range(kvm, NULL); 533 } 534 535 static int hv_enable_direct_tlbflush(struct kvm_vcpu *vcpu) 536 { 537 struct hv_enlightened_vmcs *evmcs; 538 struct hv_partition_assist_pg **p_hv_pa_pg = 539 &vcpu->kvm->arch.hyperv.hv_pa_pg; 540 /* 541 * Synthetic VM-Exit is not enabled in current code and so All 542 * evmcs in singe VM shares same assist page. 543 */ 544 if (!*p_hv_pa_pg) 545 *p_hv_pa_pg = kzalloc(PAGE_SIZE, GFP_KERNEL); 546 547 if (!*p_hv_pa_pg) 548 return -ENOMEM; 549 550 evmcs = (struct hv_enlightened_vmcs *)to_vmx(vcpu)->loaded_vmcs->vmcs; 551 552 evmcs->partition_assist_page = 553 __pa(*p_hv_pa_pg); 554 evmcs->hv_vm_id = (unsigned long)vcpu->kvm; 555 evmcs->hv_enlightenments_control.nested_flush_hypercall = 1; 556 557 return 0; 558 } 559 560 #endif /* IS_ENABLED(CONFIG_HYPERV) */ 561 562 /* 563 * Comment's format: document - errata name - stepping - processor name. 564 * Refer from 565 * https://www.virtualbox.org/svn/vbox/trunk/src/VBox/VMM/VMMR0/HMR0.cpp 566 */ 567 static u32 vmx_preemption_cpu_tfms[] = { 568 /* 323344.pdf - BA86 - D0 - Xeon 7500 Series */ 569 0x000206E6, 570 /* 323056.pdf - AAX65 - C2 - Xeon L3406 */ 571 /* 322814.pdf - AAT59 - C2 - i7-600, i5-500, i5-400 and i3-300 Mobile */ 572 /* 322911.pdf - AAU65 - C2 - i5-600, i3-500 Desktop and Pentium G6950 */ 573 0x00020652, 574 /* 322911.pdf - AAU65 - K0 - i5-600, i3-500 Desktop and Pentium G6950 */ 575 0x00020655, 576 /* 322373.pdf - AAO95 - B1 - Xeon 3400 Series */ 577 /* 322166.pdf - AAN92 - B1 - i7-800 and i5-700 Desktop */ 578 /* 579 * 320767.pdf - AAP86 - B1 - 580 * i7-900 Mobile Extreme, i7-800 and i7-700 Mobile 581 */ 582 0x000106E5, 583 /* 321333.pdf - AAM126 - C0 - Xeon 3500 */ 584 0x000106A0, 585 /* 321333.pdf - AAM126 - C1 - Xeon 3500 */ 586 0x000106A1, 587 /* 320836.pdf - AAJ124 - C0 - i7-900 Desktop Extreme and i7-900 Desktop */ 588 0x000106A4, 589 /* 321333.pdf - AAM126 - D0 - Xeon 3500 */ 590 /* 321324.pdf - AAK139 - D0 - Xeon 5500 */ 591 /* 320836.pdf - AAJ124 - D0 - i7-900 Extreme and i7-900 Desktop */ 592 0x000106A5, 593 /* Xeon E3-1220 V2 */ 594 0x000306A8, 595 }; 596 597 static inline bool cpu_has_broken_vmx_preemption_timer(void) 598 { 599 u32 eax = cpuid_eax(0x00000001), i; 600 601 /* Clear the reserved bits */ 602 eax &= ~(0x3U << 14 | 0xfU << 28); 603 for (i = 0; i < ARRAY_SIZE(vmx_preemption_cpu_tfms); i++) 604 if (eax == vmx_preemption_cpu_tfms[i]) 605 return true; 606 607 return false; 608 } 609 610 static inline bool cpu_need_virtualize_apic_accesses(struct kvm_vcpu *vcpu) 611 { 612 return flexpriority_enabled && lapic_in_kernel(vcpu); 613 } 614 615 static inline bool report_flexpriority(void) 616 { 617 return flexpriority_enabled; 618 } 619 620 static inline int __find_msr_index(struct vcpu_vmx *vmx, u32 msr) 621 { 622 int i; 623 624 for (i = 0; i < vmx->nmsrs; ++i) 625 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr) 626 return i; 627 return -1; 628 } 629 630 struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr) 631 { 632 int i; 633 634 i = __find_msr_index(vmx, msr); 635 if (i >= 0) 636 return &vmx->guest_msrs[i]; 637 return NULL; 638 } 639 640 static int vmx_set_guest_msr(struct vcpu_vmx *vmx, struct shared_msr_entry *msr, u64 data) 641 { 642 int ret = 0; 643 644 u64 old_msr_data = msr->data; 645 msr->data = data; 646 if (msr - vmx->guest_msrs < vmx->save_nmsrs) { 647 preempt_disable(); 648 ret = kvm_set_shared_msr(msr->index, msr->data, 649 msr->mask); 650 preempt_enable(); 651 if (ret) 652 msr->data = old_msr_data; 653 } 654 return ret; 655 } 656 657 void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs) 658 { 659 vmcs_clear(loaded_vmcs->vmcs); 660 if (loaded_vmcs->shadow_vmcs && loaded_vmcs->launched) 661 vmcs_clear(loaded_vmcs->shadow_vmcs); 662 loaded_vmcs->cpu = -1; 663 loaded_vmcs->launched = 0; 664 } 665 666 #ifdef CONFIG_KEXEC_CORE 667 /* 668 * This bitmap is used to indicate whether the vmclear 669 * operation is enabled on all cpus. All disabled by 670 * default. 671 */ 672 static cpumask_t crash_vmclear_enabled_bitmap = CPU_MASK_NONE; 673 674 static inline void crash_enable_local_vmclear(int cpu) 675 { 676 cpumask_set_cpu(cpu, &crash_vmclear_enabled_bitmap); 677 } 678 679 static inline void crash_disable_local_vmclear(int cpu) 680 { 681 cpumask_clear_cpu(cpu, &crash_vmclear_enabled_bitmap); 682 } 683 684 static inline int crash_local_vmclear_enabled(int cpu) 685 { 686 return cpumask_test_cpu(cpu, &crash_vmclear_enabled_bitmap); 687 } 688 689 static void crash_vmclear_local_loaded_vmcss(void) 690 { 691 int cpu = raw_smp_processor_id(); 692 struct loaded_vmcs *v; 693 694 if (!crash_local_vmclear_enabled(cpu)) 695 return; 696 697 list_for_each_entry(v, &per_cpu(loaded_vmcss_on_cpu, cpu), 698 loaded_vmcss_on_cpu_link) 699 vmcs_clear(v->vmcs); 700 } 701 #else 702 static inline void crash_enable_local_vmclear(int cpu) { } 703 static inline void crash_disable_local_vmclear(int cpu) { } 704 #endif /* CONFIG_KEXEC_CORE */ 705 706 static void __loaded_vmcs_clear(void *arg) 707 { 708 struct loaded_vmcs *loaded_vmcs = arg; 709 int cpu = raw_smp_processor_id(); 710 711 if (loaded_vmcs->cpu != cpu) 712 return; /* vcpu migration can race with cpu offline */ 713 if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs) 714 per_cpu(current_vmcs, cpu) = NULL; 715 crash_disable_local_vmclear(cpu); 716 list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link); 717 718 /* 719 * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link 720 * is before setting loaded_vmcs->vcpu to -1 which is done in 721 * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist 722 * then adds the vmcs into percpu list before it is deleted. 723 */ 724 smp_wmb(); 725 726 loaded_vmcs_init(loaded_vmcs); 727 crash_enable_local_vmclear(cpu); 728 } 729 730 void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs) 731 { 732 int cpu = loaded_vmcs->cpu; 733 734 if (cpu != -1) 735 smp_call_function_single(cpu, 736 __loaded_vmcs_clear, loaded_vmcs, 1); 737 } 738 739 static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg, 740 unsigned field) 741 { 742 bool ret; 743 u32 mask = 1 << (seg * SEG_FIELD_NR + field); 744 745 if (!kvm_register_is_available(&vmx->vcpu, VCPU_EXREG_SEGMENTS)) { 746 kvm_register_mark_available(&vmx->vcpu, VCPU_EXREG_SEGMENTS); 747 vmx->segment_cache.bitmask = 0; 748 } 749 ret = vmx->segment_cache.bitmask & mask; 750 vmx->segment_cache.bitmask |= mask; 751 return ret; 752 } 753 754 static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg) 755 { 756 u16 *p = &vmx->segment_cache.seg[seg].selector; 757 758 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL)) 759 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector); 760 return *p; 761 } 762 763 static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg) 764 { 765 ulong *p = &vmx->segment_cache.seg[seg].base; 766 767 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE)) 768 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base); 769 return *p; 770 } 771 772 static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg) 773 { 774 u32 *p = &vmx->segment_cache.seg[seg].limit; 775 776 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT)) 777 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit); 778 return *p; 779 } 780 781 static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg) 782 { 783 u32 *p = &vmx->segment_cache.seg[seg].ar; 784 785 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR)) 786 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes); 787 return *p; 788 } 789 790 void update_exception_bitmap(struct kvm_vcpu *vcpu) 791 { 792 u32 eb; 793 794 eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) | 795 (1u << DB_VECTOR) | (1u << AC_VECTOR); 796 /* 797 * Guest access to VMware backdoor ports could legitimately 798 * trigger #GP because of TSS I/O permission bitmap. 799 * We intercept those #GP and allow access to them anyway 800 * as VMware does. 801 */ 802 if (enable_vmware_backdoor) 803 eb |= (1u << GP_VECTOR); 804 if ((vcpu->guest_debug & 805 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) == 806 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) 807 eb |= 1u << BP_VECTOR; 808 if (to_vmx(vcpu)->rmode.vm86_active) 809 eb = ~0; 810 if (enable_ept) 811 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */ 812 813 /* When we are running a nested L2 guest and L1 specified for it a 814 * certain exception bitmap, we must trap the same exceptions and pass 815 * them to L1. When running L2, we will only handle the exceptions 816 * specified above if L1 did not want them. 817 */ 818 if (is_guest_mode(vcpu)) 819 eb |= get_vmcs12(vcpu)->exception_bitmap; 820 821 vmcs_write32(EXCEPTION_BITMAP, eb); 822 } 823 824 /* 825 * Check if MSR is intercepted for currently loaded MSR bitmap. 826 */ 827 static bool msr_write_intercepted(struct kvm_vcpu *vcpu, u32 msr) 828 { 829 unsigned long *msr_bitmap; 830 int f = sizeof(unsigned long); 831 832 if (!cpu_has_vmx_msr_bitmap()) 833 return true; 834 835 msr_bitmap = to_vmx(vcpu)->loaded_vmcs->msr_bitmap; 836 837 if (msr <= 0x1fff) { 838 return !!test_bit(msr, msr_bitmap + 0x800 / f); 839 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) { 840 msr &= 0x1fff; 841 return !!test_bit(msr, msr_bitmap + 0xc00 / f); 842 } 843 844 return true; 845 } 846 847 static void clear_atomic_switch_msr_special(struct vcpu_vmx *vmx, 848 unsigned long entry, unsigned long exit) 849 { 850 vm_entry_controls_clearbit(vmx, entry); 851 vm_exit_controls_clearbit(vmx, exit); 852 } 853 854 int vmx_find_msr_index(struct vmx_msrs *m, u32 msr) 855 { 856 unsigned int i; 857 858 for (i = 0; i < m->nr; ++i) { 859 if (m->val[i].index == msr) 860 return i; 861 } 862 return -ENOENT; 863 } 864 865 static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr) 866 { 867 int i; 868 struct msr_autoload *m = &vmx->msr_autoload; 869 870 switch (msr) { 871 case MSR_EFER: 872 if (cpu_has_load_ia32_efer()) { 873 clear_atomic_switch_msr_special(vmx, 874 VM_ENTRY_LOAD_IA32_EFER, 875 VM_EXIT_LOAD_IA32_EFER); 876 return; 877 } 878 break; 879 case MSR_CORE_PERF_GLOBAL_CTRL: 880 if (cpu_has_load_perf_global_ctrl()) { 881 clear_atomic_switch_msr_special(vmx, 882 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL, 883 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL); 884 return; 885 } 886 break; 887 } 888 i = vmx_find_msr_index(&m->guest, msr); 889 if (i < 0) 890 goto skip_guest; 891 --m->guest.nr; 892 m->guest.val[i] = m->guest.val[m->guest.nr]; 893 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->guest.nr); 894 895 skip_guest: 896 i = vmx_find_msr_index(&m->host, msr); 897 if (i < 0) 898 return; 899 900 --m->host.nr; 901 m->host.val[i] = m->host.val[m->host.nr]; 902 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->host.nr); 903 } 904 905 static void add_atomic_switch_msr_special(struct vcpu_vmx *vmx, 906 unsigned long entry, unsigned long exit, 907 unsigned long guest_val_vmcs, unsigned long host_val_vmcs, 908 u64 guest_val, u64 host_val) 909 { 910 vmcs_write64(guest_val_vmcs, guest_val); 911 if (host_val_vmcs != HOST_IA32_EFER) 912 vmcs_write64(host_val_vmcs, host_val); 913 vm_entry_controls_setbit(vmx, entry); 914 vm_exit_controls_setbit(vmx, exit); 915 } 916 917 static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr, 918 u64 guest_val, u64 host_val, bool entry_only) 919 { 920 int i, j = 0; 921 struct msr_autoload *m = &vmx->msr_autoload; 922 923 switch (msr) { 924 case MSR_EFER: 925 if (cpu_has_load_ia32_efer()) { 926 add_atomic_switch_msr_special(vmx, 927 VM_ENTRY_LOAD_IA32_EFER, 928 VM_EXIT_LOAD_IA32_EFER, 929 GUEST_IA32_EFER, 930 HOST_IA32_EFER, 931 guest_val, host_val); 932 return; 933 } 934 break; 935 case MSR_CORE_PERF_GLOBAL_CTRL: 936 if (cpu_has_load_perf_global_ctrl()) { 937 add_atomic_switch_msr_special(vmx, 938 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL, 939 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL, 940 GUEST_IA32_PERF_GLOBAL_CTRL, 941 HOST_IA32_PERF_GLOBAL_CTRL, 942 guest_val, host_val); 943 return; 944 } 945 break; 946 case MSR_IA32_PEBS_ENABLE: 947 /* PEBS needs a quiescent period after being disabled (to write 948 * a record). Disabling PEBS through VMX MSR swapping doesn't 949 * provide that period, so a CPU could write host's record into 950 * guest's memory. 951 */ 952 wrmsrl(MSR_IA32_PEBS_ENABLE, 0); 953 } 954 955 i = vmx_find_msr_index(&m->guest, msr); 956 if (!entry_only) 957 j = vmx_find_msr_index(&m->host, msr); 958 959 if ((i < 0 && m->guest.nr == NR_LOADSTORE_MSRS) || 960 (j < 0 && m->host.nr == NR_LOADSTORE_MSRS)) { 961 printk_once(KERN_WARNING "Not enough msr switch entries. " 962 "Can't add msr %x\n", msr); 963 return; 964 } 965 if (i < 0) { 966 i = m->guest.nr++; 967 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->guest.nr); 968 } 969 m->guest.val[i].index = msr; 970 m->guest.val[i].value = guest_val; 971 972 if (entry_only) 973 return; 974 975 if (j < 0) { 976 j = m->host.nr++; 977 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->host.nr); 978 } 979 m->host.val[j].index = msr; 980 m->host.val[j].value = host_val; 981 } 982 983 static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset) 984 { 985 u64 guest_efer = vmx->vcpu.arch.efer; 986 u64 ignore_bits = 0; 987 988 /* Shadow paging assumes NX to be available. */ 989 if (!enable_ept) 990 guest_efer |= EFER_NX; 991 992 /* 993 * LMA and LME handled by hardware; SCE meaningless outside long mode. 994 */ 995 ignore_bits |= EFER_SCE; 996 #ifdef CONFIG_X86_64 997 ignore_bits |= EFER_LMA | EFER_LME; 998 /* SCE is meaningful only in long mode on Intel */ 999 if (guest_efer & EFER_LMA) 1000 ignore_bits &= ~(u64)EFER_SCE; 1001 #endif 1002 1003 /* 1004 * On EPT, we can't emulate NX, so we must switch EFER atomically. 1005 * On CPUs that support "load IA32_EFER", always switch EFER 1006 * atomically, since it's faster than switching it manually. 1007 */ 1008 if (cpu_has_load_ia32_efer() || 1009 (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX))) { 1010 if (!(guest_efer & EFER_LMA)) 1011 guest_efer &= ~EFER_LME; 1012 if (guest_efer != host_efer) 1013 add_atomic_switch_msr(vmx, MSR_EFER, 1014 guest_efer, host_efer, false); 1015 else 1016 clear_atomic_switch_msr(vmx, MSR_EFER); 1017 return false; 1018 } else { 1019 clear_atomic_switch_msr(vmx, MSR_EFER); 1020 1021 guest_efer &= ~ignore_bits; 1022 guest_efer |= host_efer & ignore_bits; 1023 1024 vmx->guest_msrs[efer_offset].data = guest_efer; 1025 vmx->guest_msrs[efer_offset].mask = ~ignore_bits; 1026 1027 return true; 1028 } 1029 } 1030 1031 #ifdef CONFIG_X86_32 1032 /* 1033 * On 32-bit kernels, VM exits still load the FS and GS bases from the 1034 * VMCS rather than the segment table. KVM uses this helper to figure 1035 * out the current bases to poke them into the VMCS before entry. 1036 */ 1037 static unsigned long segment_base(u16 selector) 1038 { 1039 struct desc_struct *table; 1040 unsigned long v; 1041 1042 if (!(selector & ~SEGMENT_RPL_MASK)) 1043 return 0; 1044 1045 table = get_current_gdt_ro(); 1046 1047 if ((selector & SEGMENT_TI_MASK) == SEGMENT_LDT) { 1048 u16 ldt_selector = kvm_read_ldt(); 1049 1050 if (!(ldt_selector & ~SEGMENT_RPL_MASK)) 1051 return 0; 1052 1053 table = (struct desc_struct *)segment_base(ldt_selector); 1054 } 1055 v = get_desc_base(&table[selector >> 3]); 1056 return v; 1057 } 1058 #endif 1059 1060 static inline bool pt_can_write_msr(struct vcpu_vmx *vmx) 1061 { 1062 return (pt_mode == PT_MODE_HOST_GUEST) && 1063 !(vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN); 1064 } 1065 1066 static inline void pt_load_msr(struct pt_ctx *ctx, u32 addr_range) 1067 { 1068 u32 i; 1069 1070 wrmsrl(MSR_IA32_RTIT_STATUS, ctx->status); 1071 wrmsrl(MSR_IA32_RTIT_OUTPUT_BASE, ctx->output_base); 1072 wrmsrl(MSR_IA32_RTIT_OUTPUT_MASK, ctx->output_mask); 1073 wrmsrl(MSR_IA32_RTIT_CR3_MATCH, ctx->cr3_match); 1074 for (i = 0; i < addr_range; i++) { 1075 wrmsrl(MSR_IA32_RTIT_ADDR0_A + i * 2, ctx->addr_a[i]); 1076 wrmsrl(MSR_IA32_RTIT_ADDR0_B + i * 2, ctx->addr_b[i]); 1077 } 1078 } 1079 1080 static inline void pt_save_msr(struct pt_ctx *ctx, u32 addr_range) 1081 { 1082 u32 i; 1083 1084 rdmsrl(MSR_IA32_RTIT_STATUS, ctx->status); 1085 rdmsrl(MSR_IA32_RTIT_OUTPUT_BASE, ctx->output_base); 1086 rdmsrl(MSR_IA32_RTIT_OUTPUT_MASK, ctx->output_mask); 1087 rdmsrl(MSR_IA32_RTIT_CR3_MATCH, ctx->cr3_match); 1088 for (i = 0; i < addr_range; i++) { 1089 rdmsrl(MSR_IA32_RTIT_ADDR0_A + i * 2, ctx->addr_a[i]); 1090 rdmsrl(MSR_IA32_RTIT_ADDR0_B + i * 2, ctx->addr_b[i]); 1091 } 1092 } 1093 1094 static void pt_guest_enter(struct vcpu_vmx *vmx) 1095 { 1096 if (pt_mode == PT_MODE_SYSTEM) 1097 return; 1098 1099 /* 1100 * GUEST_IA32_RTIT_CTL is already set in the VMCS. 1101 * Save host state before VM entry. 1102 */ 1103 rdmsrl(MSR_IA32_RTIT_CTL, vmx->pt_desc.host.ctl); 1104 if (vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) { 1105 wrmsrl(MSR_IA32_RTIT_CTL, 0); 1106 pt_save_msr(&vmx->pt_desc.host, vmx->pt_desc.addr_range); 1107 pt_load_msr(&vmx->pt_desc.guest, vmx->pt_desc.addr_range); 1108 } 1109 } 1110 1111 static void pt_guest_exit(struct vcpu_vmx *vmx) 1112 { 1113 if (pt_mode == PT_MODE_SYSTEM) 1114 return; 1115 1116 if (vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) { 1117 pt_save_msr(&vmx->pt_desc.guest, vmx->pt_desc.addr_range); 1118 pt_load_msr(&vmx->pt_desc.host, vmx->pt_desc.addr_range); 1119 } 1120 1121 /* Reload host state (IA32_RTIT_CTL will be cleared on VM exit). */ 1122 wrmsrl(MSR_IA32_RTIT_CTL, vmx->pt_desc.host.ctl); 1123 } 1124 1125 void vmx_set_host_fs_gs(struct vmcs_host_state *host, u16 fs_sel, u16 gs_sel, 1126 unsigned long fs_base, unsigned long gs_base) 1127 { 1128 if (unlikely(fs_sel != host->fs_sel)) { 1129 if (!(fs_sel & 7)) 1130 vmcs_write16(HOST_FS_SELECTOR, fs_sel); 1131 else 1132 vmcs_write16(HOST_FS_SELECTOR, 0); 1133 host->fs_sel = fs_sel; 1134 } 1135 if (unlikely(gs_sel != host->gs_sel)) { 1136 if (!(gs_sel & 7)) 1137 vmcs_write16(HOST_GS_SELECTOR, gs_sel); 1138 else 1139 vmcs_write16(HOST_GS_SELECTOR, 0); 1140 host->gs_sel = gs_sel; 1141 } 1142 if (unlikely(fs_base != host->fs_base)) { 1143 vmcs_writel(HOST_FS_BASE, fs_base); 1144 host->fs_base = fs_base; 1145 } 1146 if (unlikely(gs_base != host->gs_base)) { 1147 vmcs_writel(HOST_GS_BASE, gs_base); 1148 host->gs_base = gs_base; 1149 } 1150 } 1151 1152 void vmx_prepare_switch_to_guest(struct kvm_vcpu *vcpu) 1153 { 1154 struct vcpu_vmx *vmx = to_vmx(vcpu); 1155 struct vmcs_host_state *host_state; 1156 #ifdef CONFIG_X86_64 1157 int cpu = raw_smp_processor_id(); 1158 #endif 1159 unsigned long fs_base, gs_base; 1160 u16 fs_sel, gs_sel; 1161 int i; 1162 1163 vmx->req_immediate_exit = false; 1164 1165 /* 1166 * Note that guest MSRs to be saved/restored can also be changed 1167 * when guest state is loaded. This happens when guest transitions 1168 * to/from long-mode by setting MSR_EFER.LMA. 1169 */ 1170 if (!vmx->guest_msrs_ready) { 1171 vmx->guest_msrs_ready = true; 1172 for (i = 0; i < vmx->save_nmsrs; ++i) 1173 kvm_set_shared_msr(vmx->guest_msrs[i].index, 1174 vmx->guest_msrs[i].data, 1175 vmx->guest_msrs[i].mask); 1176 1177 } 1178 if (vmx->guest_state_loaded) 1179 return; 1180 1181 host_state = &vmx->loaded_vmcs->host_state; 1182 1183 /* 1184 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not 1185 * allow segment selectors with cpl > 0 or ti == 1. 1186 */ 1187 host_state->ldt_sel = kvm_read_ldt(); 1188 1189 #ifdef CONFIG_X86_64 1190 savesegment(ds, host_state->ds_sel); 1191 savesegment(es, host_state->es_sel); 1192 1193 gs_base = cpu_kernelmode_gs_base(cpu); 1194 if (likely(is_64bit_mm(current->mm))) { 1195 save_fsgs_for_kvm(); 1196 fs_sel = current->thread.fsindex; 1197 gs_sel = current->thread.gsindex; 1198 fs_base = current->thread.fsbase; 1199 vmx->msr_host_kernel_gs_base = current->thread.gsbase; 1200 } else { 1201 savesegment(fs, fs_sel); 1202 savesegment(gs, gs_sel); 1203 fs_base = read_msr(MSR_FS_BASE); 1204 vmx->msr_host_kernel_gs_base = read_msr(MSR_KERNEL_GS_BASE); 1205 } 1206 1207 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base); 1208 #else 1209 savesegment(fs, fs_sel); 1210 savesegment(gs, gs_sel); 1211 fs_base = segment_base(fs_sel); 1212 gs_base = segment_base(gs_sel); 1213 #endif 1214 1215 vmx_set_host_fs_gs(host_state, fs_sel, gs_sel, fs_base, gs_base); 1216 vmx->guest_state_loaded = true; 1217 } 1218 1219 static void vmx_prepare_switch_to_host(struct vcpu_vmx *vmx) 1220 { 1221 struct vmcs_host_state *host_state; 1222 1223 if (!vmx->guest_state_loaded) 1224 return; 1225 1226 host_state = &vmx->loaded_vmcs->host_state; 1227 1228 ++vmx->vcpu.stat.host_state_reload; 1229 1230 #ifdef CONFIG_X86_64 1231 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base); 1232 #endif 1233 if (host_state->ldt_sel || (host_state->gs_sel & 7)) { 1234 kvm_load_ldt(host_state->ldt_sel); 1235 #ifdef CONFIG_X86_64 1236 load_gs_index(host_state->gs_sel); 1237 #else 1238 loadsegment(gs, host_state->gs_sel); 1239 #endif 1240 } 1241 if (host_state->fs_sel & 7) 1242 loadsegment(fs, host_state->fs_sel); 1243 #ifdef CONFIG_X86_64 1244 if (unlikely(host_state->ds_sel | host_state->es_sel)) { 1245 loadsegment(ds, host_state->ds_sel); 1246 loadsegment(es, host_state->es_sel); 1247 } 1248 #endif 1249 invalidate_tss_limit(); 1250 #ifdef CONFIG_X86_64 1251 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base); 1252 #endif 1253 load_fixmap_gdt(raw_smp_processor_id()); 1254 vmx->guest_state_loaded = false; 1255 vmx->guest_msrs_ready = false; 1256 } 1257 1258 #ifdef CONFIG_X86_64 1259 static u64 vmx_read_guest_kernel_gs_base(struct vcpu_vmx *vmx) 1260 { 1261 preempt_disable(); 1262 if (vmx->guest_state_loaded) 1263 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base); 1264 preempt_enable(); 1265 return vmx->msr_guest_kernel_gs_base; 1266 } 1267 1268 static void vmx_write_guest_kernel_gs_base(struct vcpu_vmx *vmx, u64 data) 1269 { 1270 preempt_disable(); 1271 if (vmx->guest_state_loaded) 1272 wrmsrl(MSR_KERNEL_GS_BASE, data); 1273 preempt_enable(); 1274 vmx->msr_guest_kernel_gs_base = data; 1275 } 1276 #endif 1277 1278 static void vmx_vcpu_pi_load(struct kvm_vcpu *vcpu, int cpu) 1279 { 1280 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu); 1281 struct pi_desc old, new; 1282 unsigned int dest; 1283 1284 /* 1285 * In case of hot-plug or hot-unplug, we may have to undo 1286 * vmx_vcpu_pi_put even if there is no assigned device. And we 1287 * always keep PI.NDST up to date for simplicity: it makes the 1288 * code easier, and CPU migration is not a fast path. 1289 */ 1290 if (!pi_test_sn(pi_desc) && vcpu->cpu == cpu) 1291 return; 1292 1293 /* 1294 * If the 'nv' field is POSTED_INTR_WAKEUP_VECTOR, do not change 1295 * PI.NDST: pi_post_block is the one expected to change PID.NDST and the 1296 * wakeup handler expects the vCPU to be on the blocked_vcpu_list that 1297 * matches PI.NDST. Otherwise, a vcpu may not be able to be woken up 1298 * correctly. 1299 */ 1300 if (pi_desc->nv == POSTED_INTR_WAKEUP_VECTOR || vcpu->cpu == cpu) { 1301 pi_clear_sn(pi_desc); 1302 goto after_clear_sn; 1303 } 1304 1305 /* The full case. */ 1306 do { 1307 old.control = new.control = pi_desc->control; 1308 1309 dest = cpu_physical_id(cpu); 1310 1311 if (x2apic_enabled()) 1312 new.ndst = dest; 1313 else 1314 new.ndst = (dest << 8) & 0xFF00; 1315 1316 new.sn = 0; 1317 } while (cmpxchg64(&pi_desc->control, old.control, 1318 new.control) != old.control); 1319 1320 after_clear_sn: 1321 1322 /* 1323 * Clear SN before reading the bitmap. The VT-d firmware 1324 * writes the bitmap and reads SN atomically (5.2.3 in the 1325 * spec), so it doesn't really have a memory barrier that 1326 * pairs with this, but we cannot do that and we need one. 1327 */ 1328 smp_mb__after_atomic(); 1329 1330 if (!pi_is_pir_empty(pi_desc)) 1331 pi_set_on(pi_desc); 1332 } 1333 1334 void vmx_vcpu_load_vmcs(struct kvm_vcpu *vcpu, int cpu) 1335 { 1336 struct vcpu_vmx *vmx = to_vmx(vcpu); 1337 bool already_loaded = vmx->loaded_vmcs->cpu == cpu; 1338 1339 if (!already_loaded) { 1340 loaded_vmcs_clear(vmx->loaded_vmcs); 1341 local_irq_disable(); 1342 crash_disable_local_vmclear(cpu); 1343 1344 /* 1345 * Read loaded_vmcs->cpu should be before fetching 1346 * loaded_vmcs->loaded_vmcss_on_cpu_link. 1347 * See the comments in __loaded_vmcs_clear(). 1348 */ 1349 smp_rmb(); 1350 1351 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link, 1352 &per_cpu(loaded_vmcss_on_cpu, cpu)); 1353 crash_enable_local_vmclear(cpu); 1354 local_irq_enable(); 1355 } 1356 1357 if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) { 1358 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs; 1359 vmcs_load(vmx->loaded_vmcs->vmcs); 1360 indirect_branch_prediction_barrier(); 1361 } 1362 1363 if (!already_loaded) { 1364 void *gdt = get_current_gdt_ro(); 1365 unsigned long sysenter_esp; 1366 1367 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu); 1368 1369 /* 1370 * Linux uses per-cpu TSS and GDT, so set these when switching 1371 * processors. See 22.2.4. 1372 */ 1373 vmcs_writel(HOST_TR_BASE, 1374 (unsigned long)&get_cpu_entry_area(cpu)->tss.x86_tss); 1375 vmcs_writel(HOST_GDTR_BASE, (unsigned long)gdt); /* 22.2.4 */ 1376 1377 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp); 1378 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */ 1379 1380 vmx->loaded_vmcs->cpu = cpu; 1381 } 1382 1383 /* Setup TSC multiplier */ 1384 if (kvm_has_tsc_control && 1385 vmx->current_tsc_ratio != vcpu->arch.tsc_scaling_ratio) 1386 decache_tsc_multiplier(vmx); 1387 } 1388 1389 /* 1390 * Switches to specified vcpu, until a matching vcpu_put(), but assumes 1391 * vcpu mutex is already taken. 1392 */ 1393 void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu) 1394 { 1395 struct vcpu_vmx *vmx = to_vmx(vcpu); 1396 1397 vmx_vcpu_load_vmcs(vcpu, cpu); 1398 1399 vmx_vcpu_pi_load(vcpu, cpu); 1400 1401 vmx->host_pkru = read_pkru(); 1402 vmx->host_debugctlmsr = get_debugctlmsr(); 1403 } 1404 1405 static void vmx_vcpu_pi_put(struct kvm_vcpu *vcpu) 1406 { 1407 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu); 1408 1409 if (!kvm_arch_has_assigned_device(vcpu->kvm) || 1410 !irq_remapping_cap(IRQ_POSTING_CAP) || 1411 !kvm_vcpu_apicv_active(vcpu)) 1412 return; 1413 1414 /* Set SN when the vCPU is preempted */ 1415 if (vcpu->preempted) 1416 pi_set_sn(pi_desc); 1417 } 1418 1419 static void vmx_vcpu_put(struct kvm_vcpu *vcpu) 1420 { 1421 vmx_vcpu_pi_put(vcpu); 1422 1423 vmx_prepare_switch_to_host(to_vmx(vcpu)); 1424 } 1425 1426 static bool emulation_required(struct kvm_vcpu *vcpu) 1427 { 1428 return emulate_invalid_guest_state && !guest_state_valid(vcpu); 1429 } 1430 1431 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu); 1432 1433 unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu) 1434 { 1435 struct vcpu_vmx *vmx = to_vmx(vcpu); 1436 unsigned long rflags, save_rflags; 1437 1438 if (!kvm_register_is_available(vcpu, VCPU_EXREG_RFLAGS)) { 1439 kvm_register_mark_available(vcpu, VCPU_EXREG_RFLAGS); 1440 rflags = vmcs_readl(GUEST_RFLAGS); 1441 if (vmx->rmode.vm86_active) { 1442 rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS; 1443 save_rflags = vmx->rmode.save_rflags; 1444 rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS; 1445 } 1446 vmx->rflags = rflags; 1447 } 1448 return vmx->rflags; 1449 } 1450 1451 void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags) 1452 { 1453 struct vcpu_vmx *vmx = to_vmx(vcpu); 1454 unsigned long old_rflags; 1455 1456 if (enable_unrestricted_guest) { 1457 kvm_register_mark_available(vcpu, VCPU_EXREG_RFLAGS); 1458 vmx->rflags = rflags; 1459 vmcs_writel(GUEST_RFLAGS, rflags); 1460 return; 1461 } 1462 1463 old_rflags = vmx_get_rflags(vcpu); 1464 vmx->rflags = rflags; 1465 if (vmx->rmode.vm86_active) { 1466 vmx->rmode.save_rflags = rflags; 1467 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM; 1468 } 1469 vmcs_writel(GUEST_RFLAGS, rflags); 1470 1471 if ((old_rflags ^ vmx->rflags) & X86_EFLAGS_VM) 1472 vmx->emulation_required = emulation_required(vcpu); 1473 } 1474 1475 u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu) 1476 { 1477 u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO); 1478 int ret = 0; 1479 1480 if (interruptibility & GUEST_INTR_STATE_STI) 1481 ret |= KVM_X86_SHADOW_INT_STI; 1482 if (interruptibility & GUEST_INTR_STATE_MOV_SS) 1483 ret |= KVM_X86_SHADOW_INT_MOV_SS; 1484 1485 return ret; 1486 } 1487 1488 void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask) 1489 { 1490 u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO); 1491 u32 interruptibility = interruptibility_old; 1492 1493 interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS); 1494 1495 if (mask & KVM_X86_SHADOW_INT_MOV_SS) 1496 interruptibility |= GUEST_INTR_STATE_MOV_SS; 1497 else if (mask & KVM_X86_SHADOW_INT_STI) 1498 interruptibility |= GUEST_INTR_STATE_STI; 1499 1500 if ((interruptibility != interruptibility_old)) 1501 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility); 1502 } 1503 1504 static int vmx_rtit_ctl_check(struct kvm_vcpu *vcpu, u64 data) 1505 { 1506 struct vcpu_vmx *vmx = to_vmx(vcpu); 1507 unsigned long value; 1508 1509 /* 1510 * Any MSR write that attempts to change bits marked reserved will 1511 * case a #GP fault. 1512 */ 1513 if (data & vmx->pt_desc.ctl_bitmask) 1514 return 1; 1515 1516 /* 1517 * Any attempt to modify IA32_RTIT_CTL while TraceEn is set will 1518 * result in a #GP unless the same write also clears TraceEn. 1519 */ 1520 if ((vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) && 1521 ((vmx->pt_desc.guest.ctl ^ data) & ~RTIT_CTL_TRACEEN)) 1522 return 1; 1523 1524 /* 1525 * WRMSR to IA32_RTIT_CTL that sets TraceEn but clears this bit 1526 * and FabricEn would cause #GP, if 1527 * CPUID.(EAX=14H, ECX=0):ECX.SNGLRGNOUT[bit 2] = 0 1528 */ 1529 if ((data & RTIT_CTL_TRACEEN) && !(data & RTIT_CTL_TOPA) && 1530 !(data & RTIT_CTL_FABRIC_EN) && 1531 !intel_pt_validate_cap(vmx->pt_desc.caps, 1532 PT_CAP_single_range_output)) 1533 return 1; 1534 1535 /* 1536 * MTCFreq, CycThresh and PSBFreq encodings check, any MSR write that 1537 * utilize encodings marked reserved will casue a #GP fault. 1538 */ 1539 value = intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_mtc_periods); 1540 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_mtc) && 1541 !test_bit((data & RTIT_CTL_MTC_RANGE) >> 1542 RTIT_CTL_MTC_RANGE_OFFSET, &value)) 1543 return 1; 1544 value = intel_pt_validate_cap(vmx->pt_desc.caps, 1545 PT_CAP_cycle_thresholds); 1546 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_psb_cyc) && 1547 !test_bit((data & RTIT_CTL_CYC_THRESH) >> 1548 RTIT_CTL_CYC_THRESH_OFFSET, &value)) 1549 return 1; 1550 value = intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_psb_periods); 1551 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_psb_cyc) && 1552 !test_bit((data & RTIT_CTL_PSB_FREQ) >> 1553 RTIT_CTL_PSB_FREQ_OFFSET, &value)) 1554 return 1; 1555 1556 /* 1557 * If ADDRx_CFG is reserved or the encodings is >2 will 1558 * cause a #GP fault. 1559 */ 1560 value = (data & RTIT_CTL_ADDR0) >> RTIT_CTL_ADDR0_OFFSET; 1561 if ((value && (vmx->pt_desc.addr_range < 1)) || (value > 2)) 1562 return 1; 1563 value = (data & RTIT_CTL_ADDR1) >> RTIT_CTL_ADDR1_OFFSET; 1564 if ((value && (vmx->pt_desc.addr_range < 2)) || (value > 2)) 1565 return 1; 1566 value = (data & RTIT_CTL_ADDR2) >> RTIT_CTL_ADDR2_OFFSET; 1567 if ((value && (vmx->pt_desc.addr_range < 3)) || (value > 2)) 1568 return 1; 1569 value = (data & RTIT_CTL_ADDR3) >> RTIT_CTL_ADDR3_OFFSET; 1570 if ((value && (vmx->pt_desc.addr_range < 4)) || (value > 2)) 1571 return 1; 1572 1573 return 0; 1574 } 1575 1576 static int skip_emulated_instruction(struct kvm_vcpu *vcpu) 1577 { 1578 unsigned long rip; 1579 1580 /* 1581 * Using VMCS.VM_EXIT_INSTRUCTION_LEN on EPT misconfig depends on 1582 * undefined behavior: Intel's SDM doesn't mandate the VMCS field be 1583 * set when EPT misconfig occurs. In practice, real hardware updates 1584 * VM_EXIT_INSTRUCTION_LEN on EPT misconfig, but other hypervisors 1585 * (namely Hyper-V) don't set it due to it being undefined behavior, 1586 * i.e. we end up advancing IP with some random value. 1587 */ 1588 if (!static_cpu_has(X86_FEATURE_HYPERVISOR) || 1589 to_vmx(vcpu)->exit_reason != EXIT_REASON_EPT_MISCONFIG) { 1590 rip = kvm_rip_read(vcpu); 1591 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN); 1592 kvm_rip_write(vcpu, rip); 1593 } else { 1594 if (!kvm_emulate_instruction(vcpu, EMULTYPE_SKIP)) 1595 return 0; 1596 } 1597 1598 /* skipping an emulated instruction also counts */ 1599 vmx_set_interrupt_shadow(vcpu, 0); 1600 1601 return 1; 1602 } 1603 1604 static void vmx_clear_hlt(struct kvm_vcpu *vcpu) 1605 { 1606 /* 1607 * Ensure that we clear the HLT state in the VMCS. We don't need to 1608 * explicitly skip the instruction because if the HLT state is set, 1609 * then the instruction is already executing and RIP has already been 1610 * advanced. 1611 */ 1612 if (kvm_hlt_in_guest(vcpu->kvm) && 1613 vmcs_read32(GUEST_ACTIVITY_STATE) == GUEST_ACTIVITY_HLT) 1614 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE); 1615 } 1616 1617 static void vmx_queue_exception(struct kvm_vcpu *vcpu) 1618 { 1619 struct vcpu_vmx *vmx = to_vmx(vcpu); 1620 unsigned nr = vcpu->arch.exception.nr; 1621 bool has_error_code = vcpu->arch.exception.has_error_code; 1622 u32 error_code = vcpu->arch.exception.error_code; 1623 u32 intr_info = nr | INTR_INFO_VALID_MASK; 1624 1625 kvm_deliver_exception_payload(vcpu); 1626 1627 if (has_error_code) { 1628 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code); 1629 intr_info |= INTR_INFO_DELIVER_CODE_MASK; 1630 } 1631 1632 if (vmx->rmode.vm86_active) { 1633 int inc_eip = 0; 1634 if (kvm_exception_is_soft(nr)) 1635 inc_eip = vcpu->arch.event_exit_inst_len; 1636 kvm_inject_realmode_interrupt(vcpu, nr, inc_eip); 1637 return; 1638 } 1639 1640 WARN_ON_ONCE(vmx->emulation_required); 1641 1642 if (kvm_exception_is_soft(nr)) { 1643 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1644 vmx->vcpu.arch.event_exit_inst_len); 1645 intr_info |= INTR_TYPE_SOFT_EXCEPTION; 1646 } else 1647 intr_info |= INTR_TYPE_HARD_EXCEPTION; 1648 1649 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info); 1650 1651 vmx_clear_hlt(vcpu); 1652 } 1653 1654 static bool vmx_rdtscp_supported(void) 1655 { 1656 return cpu_has_vmx_rdtscp(); 1657 } 1658 1659 static bool vmx_invpcid_supported(void) 1660 { 1661 return cpu_has_vmx_invpcid(); 1662 } 1663 1664 /* 1665 * Swap MSR entry in host/guest MSR entry array. 1666 */ 1667 static void move_msr_up(struct vcpu_vmx *vmx, int from, int to) 1668 { 1669 struct shared_msr_entry tmp; 1670 1671 tmp = vmx->guest_msrs[to]; 1672 vmx->guest_msrs[to] = vmx->guest_msrs[from]; 1673 vmx->guest_msrs[from] = tmp; 1674 } 1675 1676 /* 1677 * Set up the vmcs to automatically save and restore system 1678 * msrs. Don't touch the 64-bit msrs if the guest is in legacy 1679 * mode, as fiddling with msrs is very expensive. 1680 */ 1681 static void setup_msrs(struct vcpu_vmx *vmx) 1682 { 1683 int save_nmsrs, index; 1684 1685 save_nmsrs = 0; 1686 #ifdef CONFIG_X86_64 1687 /* 1688 * The SYSCALL MSRs are only needed on long mode guests, and only 1689 * when EFER.SCE is set. 1690 */ 1691 if (is_long_mode(&vmx->vcpu) && (vmx->vcpu.arch.efer & EFER_SCE)) { 1692 index = __find_msr_index(vmx, MSR_STAR); 1693 if (index >= 0) 1694 move_msr_up(vmx, index, save_nmsrs++); 1695 index = __find_msr_index(vmx, MSR_LSTAR); 1696 if (index >= 0) 1697 move_msr_up(vmx, index, save_nmsrs++); 1698 index = __find_msr_index(vmx, MSR_SYSCALL_MASK); 1699 if (index >= 0) 1700 move_msr_up(vmx, index, save_nmsrs++); 1701 } 1702 #endif 1703 index = __find_msr_index(vmx, MSR_EFER); 1704 if (index >= 0 && update_transition_efer(vmx, index)) 1705 move_msr_up(vmx, index, save_nmsrs++); 1706 index = __find_msr_index(vmx, MSR_TSC_AUX); 1707 if (index >= 0 && guest_cpuid_has(&vmx->vcpu, X86_FEATURE_RDTSCP)) 1708 move_msr_up(vmx, index, save_nmsrs++); 1709 index = __find_msr_index(vmx, MSR_IA32_TSX_CTRL); 1710 if (index >= 0) 1711 move_msr_up(vmx, index, save_nmsrs++); 1712 1713 vmx->save_nmsrs = save_nmsrs; 1714 vmx->guest_msrs_ready = false; 1715 1716 if (cpu_has_vmx_msr_bitmap()) 1717 vmx_update_msr_bitmap(&vmx->vcpu); 1718 } 1719 1720 static u64 vmx_read_l1_tsc_offset(struct kvm_vcpu *vcpu) 1721 { 1722 struct vmcs12 *vmcs12 = get_vmcs12(vcpu); 1723 1724 if (is_guest_mode(vcpu) && 1725 (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETTING)) 1726 return vcpu->arch.tsc_offset - vmcs12->tsc_offset; 1727 1728 return vcpu->arch.tsc_offset; 1729 } 1730 1731 static u64 vmx_write_l1_tsc_offset(struct kvm_vcpu *vcpu, u64 offset) 1732 { 1733 struct vmcs12 *vmcs12 = get_vmcs12(vcpu); 1734 u64 g_tsc_offset = 0; 1735 1736 /* 1737 * We're here if L1 chose not to trap WRMSR to TSC. According 1738 * to the spec, this should set L1's TSC; The offset that L1 1739 * set for L2 remains unchanged, and still needs to be added 1740 * to the newly set TSC to get L2's TSC. 1741 */ 1742 if (is_guest_mode(vcpu) && 1743 (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETTING)) 1744 g_tsc_offset = vmcs12->tsc_offset; 1745 1746 trace_kvm_write_tsc_offset(vcpu->vcpu_id, 1747 vcpu->arch.tsc_offset - g_tsc_offset, 1748 offset); 1749 vmcs_write64(TSC_OFFSET, offset + g_tsc_offset); 1750 return offset + g_tsc_offset; 1751 } 1752 1753 /* 1754 * nested_vmx_allowed() checks whether a guest should be allowed to use VMX 1755 * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for 1756 * all guests if the "nested" module option is off, and can also be disabled 1757 * for a single guest by disabling its VMX cpuid bit. 1758 */ 1759 bool nested_vmx_allowed(struct kvm_vcpu *vcpu) 1760 { 1761 return nested && guest_cpuid_has(vcpu, X86_FEATURE_VMX); 1762 } 1763 1764 static inline bool vmx_feature_control_msr_valid(struct kvm_vcpu *vcpu, 1765 uint64_t val) 1766 { 1767 uint64_t valid_bits = to_vmx(vcpu)->msr_ia32_feature_control_valid_bits; 1768 1769 return !(val & ~valid_bits); 1770 } 1771 1772 static int vmx_get_msr_feature(struct kvm_msr_entry *msr) 1773 { 1774 switch (msr->index) { 1775 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC: 1776 if (!nested) 1777 return 1; 1778 return vmx_get_vmx_msr(&vmcs_config.nested, msr->index, &msr->data); 1779 default: 1780 return 1; 1781 } 1782 } 1783 1784 /* 1785 * Reads an msr value (of 'msr_index') into 'pdata'. 1786 * Returns 0 on success, non-0 otherwise. 1787 * Assumes vcpu_load() was already called. 1788 */ 1789 static int vmx_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info) 1790 { 1791 struct vcpu_vmx *vmx = to_vmx(vcpu); 1792 struct shared_msr_entry *msr; 1793 u32 index; 1794 1795 switch (msr_info->index) { 1796 #ifdef CONFIG_X86_64 1797 case MSR_FS_BASE: 1798 msr_info->data = vmcs_readl(GUEST_FS_BASE); 1799 break; 1800 case MSR_GS_BASE: 1801 msr_info->data = vmcs_readl(GUEST_GS_BASE); 1802 break; 1803 case MSR_KERNEL_GS_BASE: 1804 msr_info->data = vmx_read_guest_kernel_gs_base(vmx); 1805 break; 1806 #endif 1807 case MSR_EFER: 1808 return kvm_get_msr_common(vcpu, msr_info); 1809 case MSR_IA32_TSX_CTRL: 1810 if (!msr_info->host_initiated && 1811 !(vcpu->arch.arch_capabilities & ARCH_CAP_TSX_CTRL_MSR)) 1812 return 1; 1813 goto find_shared_msr; 1814 case MSR_IA32_UMWAIT_CONTROL: 1815 if (!msr_info->host_initiated && !vmx_has_waitpkg(vmx)) 1816 return 1; 1817 1818 msr_info->data = vmx->msr_ia32_umwait_control; 1819 break; 1820 case MSR_IA32_SPEC_CTRL: 1821 if (!msr_info->host_initiated && 1822 !guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL)) 1823 return 1; 1824 1825 msr_info->data = to_vmx(vcpu)->spec_ctrl; 1826 break; 1827 case MSR_IA32_SYSENTER_CS: 1828 msr_info->data = vmcs_read32(GUEST_SYSENTER_CS); 1829 break; 1830 case MSR_IA32_SYSENTER_EIP: 1831 msr_info->data = vmcs_readl(GUEST_SYSENTER_EIP); 1832 break; 1833 case MSR_IA32_SYSENTER_ESP: 1834 msr_info->data = vmcs_readl(GUEST_SYSENTER_ESP); 1835 break; 1836 case MSR_IA32_BNDCFGS: 1837 if (!kvm_mpx_supported() || 1838 (!msr_info->host_initiated && 1839 !guest_cpuid_has(vcpu, X86_FEATURE_MPX))) 1840 return 1; 1841 msr_info->data = vmcs_read64(GUEST_BNDCFGS); 1842 break; 1843 case MSR_IA32_MCG_EXT_CTL: 1844 if (!msr_info->host_initiated && 1845 !(vmx->msr_ia32_feature_control & 1846 FEAT_CTL_LMCE_ENABLED)) 1847 return 1; 1848 msr_info->data = vcpu->arch.mcg_ext_ctl; 1849 break; 1850 case MSR_IA32_FEAT_CTL: 1851 msr_info->data = vmx->msr_ia32_feature_control; 1852 break; 1853 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC: 1854 if (!nested_vmx_allowed(vcpu)) 1855 return 1; 1856 return vmx_get_vmx_msr(&vmx->nested.msrs, msr_info->index, 1857 &msr_info->data); 1858 case MSR_IA32_RTIT_CTL: 1859 if (pt_mode != PT_MODE_HOST_GUEST) 1860 return 1; 1861 msr_info->data = vmx->pt_desc.guest.ctl; 1862 break; 1863 case MSR_IA32_RTIT_STATUS: 1864 if (pt_mode != PT_MODE_HOST_GUEST) 1865 return 1; 1866 msr_info->data = vmx->pt_desc.guest.status; 1867 break; 1868 case MSR_IA32_RTIT_CR3_MATCH: 1869 if ((pt_mode != PT_MODE_HOST_GUEST) || 1870 !intel_pt_validate_cap(vmx->pt_desc.caps, 1871 PT_CAP_cr3_filtering)) 1872 return 1; 1873 msr_info->data = vmx->pt_desc.guest.cr3_match; 1874 break; 1875 case MSR_IA32_RTIT_OUTPUT_BASE: 1876 if ((pt_mode != PT_MODE_HOST_GUEST) || 1877 (!intel_pt_validate_cap(vmx->pt_desc.caps, 1878 PT_CAP_topa_output) && 1879 !intel_pt_validate_cap(vmx->pt_desc.caps, 1880 PT_CAP_single_range_output))) 1881 return 1; 1882 msr_info->data = vmx->pt_desc.guest.output_base; 1883 break; 1884 case MSR_IA32_RTIT_OUTPUT_MASK: 1885 if ((pt_mode != PT_MODE_HOST_GUEST) || 1886 (!intel_pt_validate_cap(vmx->pt_desc.caps, 1887 PT_CAP_topa_output) && 1888 !intel_pt_validate_cap(vmx->pt_desc.caps, 1889 PT_CAP_single_range_output))) 1890 return 1; 1891 msr_info->data = vmx->pt_desc.guest.output_mask; 1892 break; 1893 case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B: 1894 index = msr_info->index - MSR_IA32_RTIT_ADDR0_A; 1895 if ((pt_mode != PT_MODE_HOST_GUEST) || 1896 (index >= 2 * intel_pt_validate_cap(vmx->pt_desc.caps, 1897 PT_CAP_num_address_ranges))) 1898 return 1; 1899 if (index % 2) 1900 msr_info->data = vmx->pt_desc.guest.addr_b[index / 2]; 1901 else 1902 msr_info->data = vmx->pt_desc.guest.addr_a[index / 2]; 1903 break; 1904 case MSR_TSC_AUX: 1905 if (!msr_info->host_initiated && 1906 !guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP)) 1907 return 1; 1908 goto find_shared_msr; 1909 default: 1910 find_shared_msr: 1911 msr = find_msr_entry(vmx, msr_info->index); 1912 if (msr) { 1913 msr_info->data = msr->data; 1914 break; 1915 } 1916 return kvm_get_msr_common(vcpu, msr_info); 1917 } 1918 1919 return 0; 1920 } 1921 1922 /* 1923 * Writes msr value into the appropriate "register". 1924 * Returns 0 on success, non-0 otherwise. 1925 * Assumes vcpu_load() was already called. 1926 */ 1927 static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info) 1928 { 1929 struct vcpu_vmx *vmx = to_vmx(vcpu); 1930 struct shared_msr_entry *msr; 1931 int ret = 0; 1932 u32 msr_index = msr_info->index; 1933 u64 data = msr_info->data; 1934 u32 index; 1935 1936 switch (msr_index) { 1937 case MSR_EFER: 1938 ret = kvm_set_msr_common(vcpu, msr_info); 1939 break; 1940 #ifdef CONFIG_X86_64 1941 case MSR_FS_BASE: 1942 vmx_segment_cache_clear(vmx); 1943 vmcs_writel(GUEST_FS_BASE, data); 1944 break; 1945 case MSR_GS_BASE: 1946 vmx_segment_cache_clear(vmx); 1947 vmcs_writel(GUEST_GS_BASE, data); 1948 break; 1949 case MSR_KERNEL_GS_BASE: 1950 vmx_write_guest_kernel_gs_base(vmx, data); 1951 break; 1952 #endif 1953 case MSR_IA32_SYSENTER_CS: 1954 if (is_guest_mode(vcpu)) 1955 get_vmcs12(vcpu)->guest_sysenter_cs = data; 1956 vmcs_write32(GUEST_SYSENTER_CS, data); 1957 break; 1958 case MSR_IA32_SYSENTER_EIP: 1959 if (is_guest_mode(vcpu)) 1960 get_vmcs12(vcpu)->guest_sysenter_eip = data; 1961 vmcs_writel(GUEST_SYSENTER_EIP, data); 1962 break; 1963 case MSR_IA32_SYSENTER_ESP: 1964 if (is_guest_mode(vcpu)) 1965 get_vmcs12(vcpu)->guest_sysenter_esp = data; 1966 vmcs_writel(GUEST_SYSENTER_ESP, data); 1967 break; 1968 case MSR_IA32_DEBUGCTLMSR: 1969 if (is_guest_mode(vcpu) && get_vmcs12(vcpu)->vm_exit_controls & 1970 VM_EXIT_SAVE_DEBUG_CONTROLS) 1971 get_vmcs12(vcpu)->guest_ia32_debugctl = data; 1972 1973 ret = kvm_set_msr_common(vcpu, msr_info); 1974 break; 1975 1976 case MSR_IA32_BNDCFGS: 1977 if (!kvm_mpx_supported() || 1978 (!msr_info->host_initiated && 1979 !guest_cpuid_has(vcpu, X86_FEATURE_MPX))) 1980 return 1; 1981 if (is_noncanonical_address(data & PAGE_MASK, vcpu) || 1982 (data & MSR_IA32_BNDCFGS_RSVD)) 1983 return 1; 1984 vmcs_write64(GUEST_BNDCFGS, data); 1985 break; 1986 case MSR_IA32_UMWAIT_CONTROL: 1987 if (!msr_info->host_initiated && !vmx_has_waitpkg(vmx)) 1988 return 1; 1989 1990 /* The reserved bit 1 and non-32 bit [63:32] should be zero */ 1991 if (data & (BIT_ULL(1) | GENMASK_ULL(63, 32))) 1992 return 1; 1993 1994 vmx->msr_ia32_umwait_control = data; 1995 break; 1996 case MSR_IA32_SPEC_CTRL: 1997 if (!msr_info->host_initiated && 1998 !guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL)) 1999 return 1; 2000 2001 if (data & ~kvm_spec_ctrl_valid_bits(vcpu)) 2002 return 1; 2003 2004 vmx->spec_ctrl = data; 2005 if (!data) 2006 break; 2007 2008 /* 2009 * For non-nested: 2010 * When it's written (to non-zero) for the first time, pass 2011 * it through. 2012 * 2013 * For nested: 2014 * The handling of the MSR bitmap for L2 guests is done in 2015 * nested_vmx_prepare_msr_bitmap. We should not touch the 2016 * vmcs02.msr_bitmap here since it gets completely overwritten 2017 * in the merging. We update the vmcs01 here for L1 as well 2018 * since it will end up touching the MSR anyway now. 2019 */ 2020 vmx_disable_intercept_for_msr(vmx->vmcs01.msr_bitmap, 2021 MSR_IA32_SPEC_CTRL, 2022 MSR_TYPE_RW); 2023 break; 2024 case MSR_IA32_TSX_CTRL: 2025 if (!msr_info->host_initiated && 2026 !(vcpu->arch.arch_capabilities & ARCH_CAP_TSX_CTRL_MSR)) 2027 return 1; 2028 if (data & ~(TSX_CTRL_RTM_DISABLE | TSX_CTRL_CPUID_CLEAR)) 2029 return 1; 2030 goto find_shared_msr; 2031 case MSR_IA32_PRED_CMD: 2032 if (!msr_info->host_initiated && 2033 !guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL)) 2034 return 1; 2035 2036 if (data & ~PRED_CMD_IBPB) 2037 return 1; 2038 if (!boot_cpu_has(X86_FEATURE_SPEC_CTRL)) 2039 return 1; 2040 if (!data) 2041 break; 2042 2043 wrmsrl(MSR_IA32_PRED_CMD, PRED_CMD_IBPB); 2044 2045 /* 2046 * For non-nested: 2047 * When it's written (to non-zero) for the first time, pass 2048 * it through. 2049 * 2050 * For nested: 2051 * The handling of the MSR bitmap for L2 guests is done in 2052 * nested_vmx_prepare_msr_bitmap. We should not touch the 2053 * vmcs02.msr_bitmap here since it gets completely overwritten 2054 * in the merging. 2055 */ 2056 vmx_disable_intercept_for_msr(vmx->vmcs01.msr_bitmap, MSR_IA32_PRED_CMD, 2057 MSR_TYPE_W); 2058 break; 2059 case MSR_IA32_CR_PAT: 2060 if (!kvm_pat_valid(data)) 2061 return 1; 2062 2063 if (is_guest_mode(vcpu) && 2064 get_vmcs12(vcpu)->vm_exit_controls & VM_EXIT_SAVE_IA32_PAT) 2065 get_vmcs12(vcpu)->guest_ia32_pat = data; 2066 2067 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) { 2068 vmcs_write64(GUEST_IA32_PAT, data); 2069 vcpu->arch.pat = data; 2070 break; 2071 } 2072 ret = kvm_set_msr_common(vcpu, msr_info); 2073 break; 2074 case MSR_IA32_TSC_ADJUST: 2075 ret = kvm_set_msr_common(vcpu, msr_info); 2076 break; 2077 case MSR_IA32_MCG_EXT_CTL: 2078 if ((!msr_info->host_initiated && 2079 !(to_vmx(vcpu)->msr_ia32_feature_control & 2080 FEAT_CTL_LMCE_ENABLED)) || 2081 (data & ~MCG_EXT_CTL_LMCE_EN)) 2082 return 1; 2083 vcpu->arch.mcg_ext_ctl = data; 2084 break; 2085 case MSR_IA32_FEAT_CTL: 2086 if (!vmx_feature_control_msr_valid(vcpu, data) || 2087 (to_vmx(vcpu)->msr_ia32_feature_control & 2088 FEAT_CTL_LOCKED && !msr_info->host_initiated)) 2089 return 1; 2090 vmx->msr_ia32_feature_control = data; 2091 if (msr_info->host_initiated && data == 0) 2092 vmx_leave_nested(vcpu); 2093 break; 2094 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC: 2095 if (!msr_info->host_initiated) 2096 return 1; /* they are read-only */ 2097 if (!nested_vmx_allowed(vcpu)) 2098 return 1; 2099 return vmx_set_vmx_msr(vcpu, msr_index, data); 2100 case MSR_IA32_RTIT_CTL: 2101 if ((pt_mode != PT_MODE_HOST_GUEST) || 2102 vmx_rtit_ctl_check(vcpu, data) || 2103 vmx->nested.vmxon) 2104 return 1; 2105 vmcs_write64(GUEST_IA32_RTIT_CTL, data); 2106 vmx->pt_desc.guest.ctl = data; 2107 pt_update_intercept_for_msr(vmx); 2108 break; 2109 case MSR_IA32_RTIT_STATUS: 2110 if (!pt_can_write_msr(vmx)) 2111 return 1; 2112 if (data & MSR_IA32_RTIT_STATUS_MASK) 2113 return 1; 2114 vmx->pt_desc.guest.status = data; 2115 break; 2116 case MSR_IA32_RTIT_CR3_MATCH: 2117 if (!pt_can_write_msr(vmx)) 2118 return 1; 2119 if (!intel_pt_validate_cap(vmx->pt_desc.caps, 2120 PT_CAP_cr3_filtering)) 2121 return 1; 2122 vmx->pt_desc.guest.cr3_match = data; 2123 break; 2124 case MSR_IA32_RTIT_OUTPUT_BASE: 2125 if (!pt_can_write_msr(vmx)) 2126 return 1; 2127 if (!intel_pt_validate_cap(vmx->pt_desc.caps, 2128 PT_CAP_topa_output) && 2129 !intel_pt_validate_cap(vmx->pt_desc.caps, 2130 PT_CAP_single_range_output)) 2131 return 1; 2132 if (data & MSR_IA32_RTIT_OUTPUT_BASE_MASK) 2133 return 1; 2134 vmx->pt_desc.guest.output_base = data; 2135 break; 2136 case MSR_IA32_RTIT_OUTPUT_MASK: 2137 if (!pt_can_write_msr(vmx)) 2138 return 1; 2139 if (!intel_pt_validate_cap(vmx->pt_desc.caps, 2140 PT_CAP_topa_output) && 2141 !intel_pt_validate_cap(vmx->pt_desc.caps, 2142 PT_CAP_single_range_output)) 2143 return 1; 2144 vmx->pt_desc.guest.output_mask = data; 2145 break; 2146 case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B: 2147 if (!pt_can_write_msr(vmx)) 2148 return 1; 2149 index = msr_info->index - MSR_IA32_RTIT_ADDR0_A; 2150 if (index >= 2 * intel_pt_validate_cap(vmx->pt_desc.caps, 2151 PT_CAP_num_address_ranges)) 2152 return 1; 2153 if (is_noncanonical_address(data, vcpu)) 2154 return 1; 2155 if (index % 2) 2156 vmx->pt_desc.guest.addr_b[index / 2] = data; 2157 else 2158 vmx->pt_desc.guest.addr_a[index / 2] = data; 2159 break; 2160 case MSR_TSC_AUX: 2161 if (!msr_info->host_initiated && 2162 !guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP)) 2163 return 1; 2164 /* Check reserved bit, higher 32 bits should be zero */ 2165 if ((data >> 32) != 0) 2166 return 1; 2167 goto find_shared_msr; 2168 2169 default: 2170 find_shared_msr: 2171 msr = find_msr_entry(vmx, msr_index); 2172 if (msr) 2173 ret = vmx_set_guest_msr(vmx, msr, data); 2174 else 2175 ret = kvm_set_msr_common(vcpu, msr_info); 2176 } 2177 2178 return ret; 2179 } 2180 2181 static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg) 2182 { 2183 kvm_register_mark_available(vcpu, reg); 2184 2185 switch (reg) { 2186 case VCPU_REGS_RSP: 2187 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP); 2188 break; 2189 case VCPU_REGS_RIP: 2190 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP); 2191 break; 2192 case VCPU_EXREG_PDPTR: 2193 if (enable_ept) 2194 ept_save_pdptrs(vcpu); 2195 break; 2196 case VCPU_EXREG_CR3: 2197 if (enable_unrestricted_guest || (enable_ept && is_paging(vcpu))) 2198 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3); 2199 break; 2200 default: 2201 WARN_ON_ONCE(1); 2202 break; 2203 } 2204 } 2205 2206 static __init int cpu_has_kvm_support(void) 2207 { 2208 return cpu_has_vmx(); 2209 } 2210 2211 static __init int vmx_disabled_by_bios(void) 2212 { 2213 return !boot_cpu_has(X86_FEATURE_MSR_IA32_FEAT_CTL) || 2214 !boot_cpu_has(X86_FEATURE_VMX); 2215 } 2216 2217 static void kvm_cpu_vmxon(u64 addr) 2218 { 2219 cr4_set_bits(X86_CR4_VMXE); 2220 intel_pt_handle_vmx(1); 2221 2222 asm volatile ("vmxon %0" : : "m"(addr)); 2223 } 2224 2225 static int hardware_enable(void) 2226 { 2227 int cpu = raw_smp_processor_id(); 2228 u64 phys_addr = __pa(per_cpu(vmxarea, cpu)); 2229 2230 if (cr4_read_shadow() & X86_CR4_VMXE) 2231 return -EBUSY; 2232 2233 /* 2234 * This can happen if we hot-added a CPU but failed to allocate 2235 * VP assist page for it. 2236 */ 2237 if (static_branch_unlikely(&enable_evmcs) && 2238 !hv_get_vp_assist_page(cpu)) 2239 return -EFAULT; 2240 2241 INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu)); 2242 INIT_LIST_HEAD(&per_cpu(blocked_vcpu_on_cpu, cpu)); 2243 spin_lock_init(&per_cpu(blocked_vcpu_on_cpu_lock, cpu)); 2244 2245 /* 2246 * Now we can enable the vmclear operation in kdump 2247 * since the loaded_vmcss_on_cpu list on this cpu 2248 * has been initialized. 2249 * 2250 * Though the cpu is not in VMX operation now, there 2251 * is no problem to enable the vmclear operation 2252 * for the loaded_vmcss_on_cpu list is empty! 2253 */ 2254 crash_enable_local_vmclear(cpu); 2255 2256 kvm_cpu_vmxon(phys_addr); 2257 if (enable_ept) 2258 ept_sync_global(); 2259 2260 return 0; 2261 } 2262 2263 static void vmclear_local_loaded_vmcss(void) 2264 { 2265 int cpu = raw_smp_processor_id(); 2266 struct loaded_vmcs *v, *n; 2267 2268 list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu), 2269 loaded_vmcss_on_cpu_link) 2270 __loaded_vmcs_clear(v); 2271 } 2272 2273 2274 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot() 2275 * tricks. 2276 */ 2277 static void kvm_cpu_vmxoff(void) 2278 { 2279 asm volatile (__ex("vmxoff")); 2280 2281 intel_pt_handle_vmx(0); 2282 cr4_clear_bits(X86_CR4_VMXE); 2283 } 2284 2285 static void hardware_disable(void) 2286 { 2287 vmclear_local_loaded_vmcss(); 2288 kvm_cpu_vmxoff(); 2289 } 2290 2291 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt, 2292 u32 msr, u32 *result) 2293 { 2294 u32 vmx_msr_low, vmx_msr_high; 2295 u32 ctl = ctl_min | ctl_opt; 2296 2297 rdmsr(msr, vmx_msr_low, vmx_msr_high); 2298 2299 ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */ 2300 ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */ 2301 2302 /* Ensure minimum (required) set of control bits are supported. */ 2303 if (ctl_min & ~ctl) 2304 return -EIO; 2305 2306 *result = ctl; 2307 return 0; 2308 } 2309 2310 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf, 2311 struct vmx_capability *vmx_cap) 2312 { 2313 u32 vmx_msr_low, vmx_msr_high; 2314 u32 min, opt, min2, opt2; 2315 u32 _pin_based_exec_control = 0; 2316 u32 _cpu_based_exec_control = 0; 2317 u32 _cpu_based_2nd_exec_control = 0; 2318 u32 _vmexit_control = 0; 2319 u32 _vmentry_control = 0; 2320 2321 memset(vmcs_conf, 0, sizeof(*vmcs_conf)); 2322 min = CPU_BASED_HLT_EXITING | 2323 #ifdef CONFIG_X86_64 2324 CPU_BASED_CR8_LOAD_EXITING | 2325 CPU_BASED_CR8_STORE_EXITING | 2326 #endif 2327 CPU_BASED_CR3_LOAD_EXITING | 2328 CPU_BASED_CR3_STORE_EXITING | 2329 CPU_BASED_UNCOND_IO_EXITING | 2330 CPU_BASED_MOV_DR_EXITING | 2331 CPU_BASED_USE_TSC_OFFSETTING | 2332 CPU_BASED_MWAIT_EXITING | 2333 CPU_BASED_MONITOR_EXITING | 2334 CPU_BASED_INVLPG_EXITING | 2335 CPU_BASED_RDPMC_EXITING; 2336 2337 opt = CPU_BASED_TPR_SHADOW | 2338 CPU_BASED_USE_MSR_BITMAPS | 2339 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS; 2340 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS, 2341 &_cpu_based_exec_control) < 0) 2342 return -EIO; 2343 #ifdef CONFIG_X86_64 2344 if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW)) 2345 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING & 2346 ~CPU_BASED_CR8_STORE_EXITING; 2347 #endif 2348 if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) { 2349 min2 = 0; 2350 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 2351 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 2352 SECONDARY_EXEC_WBINVD_EXITING | 2353 SECONDARY_EXEC_ENABLE_VPID | 2354 SECONDARY_EXEC_ENABLE_EPT | 2355 SECONDARY_EXEC_UNRESTRICTED_GUEST | 2356 SECONDARY_EXEC_PAUSE_LOOP_EXITING | 2357 SECONDARY_EXEC_DESC | 2358 SECONDARY_EXEC_RDTSCP | 2359 SECONDARY_EXEC_ENABLE_INVPCID | 2360 SECONDARY_EXEC_APIC_REGISTER_VIRT | 2361 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 2362 SECONDARY_EXEC_SHADOW_VMCS | 2363 SECONDARY_EXEC_XSAVES | 2364 SECONDARY_EXEC_RDSEED_EXITING | 2365 SECONDARY_EXEC_RDRAND_EXITING | 2366 SECONDARY_EXEC_ENABLE_PML | 2367 SECONDARY_EXEC_TSC_SCALING | 2368 SECONDARY_EXEC_ENABLE_USR_WAIT_PAUSE | 2369 SECONDARY_EXEC_PT_USE_GPA | 2370 SECONDARY_EXEC_PT_CONCEAL_VMX | 2371 SECONDARY_EXEC_ENABLE_VMFUNC | 2372 SECONDARY_EXEC_ENCLS_EXITING; 2373 if (adjust_vmx_controls(min2, opt2, 2374 MSR_IA32_VMX_PROCBASED_CTLS2, 2375 &_cpu_based_2nd_exec_control) < 0) 2376 return -EIO; 2377 } 2378 #ifndef CONFIG_X86_64 2379 if (!(_cpu_based_2nd_exec_control & 2380 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) 2381 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW; 2382 #endif 2383 2384 if (!(_cpu_based_exec_control & CPU_BASED_TPR_SHADOW)) 2385 _cpu_based_2nd_exec_control &= ~( 2386 SECONDARY_EXEC_APIC_REGISTER_VIRT | 2387 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 2388 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY); 2389 2390 rdmsr_safe(MSR_IA32_VMX_EPT_VPID_CAP, 2391 &vmx_cap->ept, &vmx_cap->vpid); 2392 2393 if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) { 2394 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT 2395 enabled */ 2396 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING | 2397 CPU_BASED_CR3_STORE_EXITING | 2398 CPU_BASED_INVLPG_EXITING); 2399 } else if (vmx_cap->ept) { 2400 vmx_cap->ept = 0; 2401 pr_warn_once("EPT CAP should not exist if not support " 2402 "1-setting enable EPT VM-execution control\n"); 2403 } 2404 if (!(_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_VPID) && 2405 vmx_cap->vpid) { 2406 vmx_cap->vpid = 0; 2407 pr_warn_once("VPID CAP should not exist if not support " 2408 "1-setting enable VPID VM-execution control\n"); 2409 } 2410 2411 min = VM_EXIT_SAVE_DEBUG_CONTROLS | VM_EXIT_ACK_INTR_ON_EXIT; 2412 #ifdef CONFIG_X86_64 2413 min |= VM_EXIT_HOST_ADDR_SPACE_SIZE; 2414 #endif 2415 opt = VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 2416 VM_EXIT_LOAD_IA32_PAT | 2417 VM_EXIT_LOAD_IA32_EFER | 2418 VM_EXIT_CLEAR_BNDCFGS | 2419 VM_EXIT_PT_CONCEAL_PIP | 2420 VM_EXIT_CLEAR_IA32_RTIT_CTL; 2421 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS, 2422 &_vmexit_control) < 0) 2423 return -EIO; 2424 2425 min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING; 2426 opt = PIN_BASED_VIRTUAL_NMIS | PIN_BASED_POSTED_INTR | 2427 PIN_BASED_VMX_PREEMPTION_TIMER; 2428 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS, 2429 &_pin_based_exec_control) < 0) 2430 return -EIO; 2431 2432 if (cpu_has_broken_vmx_preemption_timer()) 2433 _pin_based_exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER; 2434 if (!(_cpu_based_2nd_exec_control & 2435 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY)) 2436 _pin_based_exec_control &= ~PIN_BASED_POSTED_INTR; 2437 2438 min = VM_ENTRY_LOAD_DEBUG_CONTROLS; 2439 opt = VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | 2440 VM_ENTRY_LOAD_IA32_PAT | 2441 VM_ENTRY_LOAD_IA32_EFER | 2442 VM_ENTRY_LOAD_BNDCFGS | 2443 VM_ENTRY_PT_CONCEAL_PIP | 2444 VM_ENTRY_LOAD_IA32_RTIT_CTL; 2445 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS, 2446 &_vmentry_control) < 0) 2447 return -EIO; 2448 2449 /* 2450 * Some cpus support VM_{ENTRY,EXIT}_IA32_PERF_GLOBAL_CTRL but they 2451 * can't be used due to an errata where VM Exit may incorrectly clear 2452 * IA32_PERF_GLOBAL_CTRL[34:32]. Workaround the errata by using the 2453 * MSR load mechanism to switch IA32_PERF_GLOBAL_CTRL. 2454 */ 2455 if (boot_cpu_data.x86 == 0x6) { 2456 switch (boot_cpu_data.x86_model) { 2457 case 26: /* AAK155 */ 2458 case 30: /* AAP115 */ 2459 case 37: /* AAT100 */ 2460 case 44: /* BC86,AAY89,BD102 */ 2461 case 46: /* BA97 */ 2462 _vmentry_control &= ~VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL; 2463 _vmexit_control &= ~VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL; 2464 pr_warn_once("kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL " 2465 "does not work properly. Using workaround\n"); 2466 break; 2467 default: 2468 break; 2469 } 2470 } 2471 2472 2473 rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high); 2474 2475 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */ 2476 if ((vmx_msr_high & 0x1fff) > PAGE_SIZE) 2477 return -EIO; 2478 2479 #ifdef CONFIG_X86_64 2480 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */ 2481 if (vmx_msr_high & (1u<<16)) 2482 return -EIO; 2483 #endif 2484 2485 /* Require Write-Back (WB) memory type for VMCS accesses. */ 2486 if (((vmx_msr_high >> 18) & 15) != 6) 2487 return -EIO; 2488 2489 vmcs_conf->size = vmx_msr_high & 0x1fff; 2490 vmcs_conf->order = get_order(vmcs_conf->size); 2491 vmcs_conf->basic_cap = vmx_msr_high & ~0x1fff; 2492 2493 vmcs_conf->revision_id = vmx_msr_low; 2494 2495 vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control; 2496 vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control; 2497 vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control; 2498 vmcs_conf->vmexit_ctrl = _vmexit_control; 2499 vmcs_conf->vmentry_ctrl = _vmentry_control; 2500 2501 if (static_branch_unlikely(&enable_evmcs)) 2502 evmcs_sanitize_exec_ctrls(vmcs_conf); 2503 2504 return 0; 2505 } 2506 2507 struct vmcs *alloc_vmcs_cpu(bool shadow, int cpu, gfp_t flags) 2508 { 2509 int node = cpu_to_node(cpu); 2510 struct page *pages; 2511 struct vmcs *vmcs; 2512 2513 pages = __alloc_pages_node(node, flags, vmcs_config.order); 2514 if (!pages) 2515 return NULL; 2516 vmcs = page_address(pages); 2517 memset(vmcs, 0, vmcs_config.size); 2518 2519 /* KVM supports Enlightened VMCS v1 only */ 2520 if (static_branch_unlikely(&enable_evmcs)) 2521 vmcs->hdr.revision_id = KVM_EVMCS_VERSION; 2522 else 2523 vmcs->hdr.revision_id = vmcs_config.revision_id; 2524 2525 if (shadow) 2526 vmcs->hdr.shadow_vmcs = 1; 2527 return vmcs; 2528 } 2529 2530 void free_vmcs(struct vmcs *vmcs) 2531 { 2532 free_pages((unsigned long)vmcs, vmcs_config.order); 2533 } 2534 2535 /* 2536 * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded 2537 */ 2538 void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs) 2539 { 2540 if (!loaded_vmcs->vmcs) 2541 return; 2542 loaded_vmcs_clear(loaded_vmcs); 2543 free_vmcs(loaded_vmcs->vmcs); 2544 loaded_vmcs->vmcs = NULL; 2545 if (loaded_vmcs->msr_bitmap) 2546 free_page((unsigned long)loaded_vmcs->msr_bitmap); 2547 WARN_ON(loaded_vmcs->shadow_vmcs != NULL); 2548 } 2549 2550 int alloc_loaded_vmcs(struct loaded_vmcs *loaded_vmcs) 2551 { 2552 loaded_vmcs->vmcs = alloc_vmcs(false); 2553 if (!loaded_vmcs->vmcs) 2554 return -ENOMEM; 2555 2556 loaded_vmcs->shadow_vmcs = NULL; 2557 loaded_vmcs->hv_timer_soft_disabled = false; 2558 loaded_vmcs_init(loaded_vmcs); 2559 2560 if (cpu_has_vmx_msr_bitmap()) { 2561 loaded_vmcs->msr_bitmap = (unsigned long *) 2562 __get_free_page(GFP_KERNEL_ACCOUNT); 2563 if (!loaded_vmcs->msr_bitmap) 2564 goto out_vmcs; 2565 memset(loaded_vmcs->msr_bitmap, 0xff, PAGE_SIZE); 2566 2567 if (IS_ENABLED(CONFIG_HYPERV) && 2568 static_branch_unlikely(&enable_evmcs) && 2569 (ms_hyperv.nested_features & HV_X64_NESTED_MSR_BITMAP)) { 2570 struct hv_enlightened_vmcs *evmcs = 2571 (struct hv_enlightened_vmcs *)loaded_vmcs->vmcs; 2572 2573 evmcs->hv_enlightenments_control.msr_bitmap = 1; 2574 } 2575 } 2576 2577 memset(&loaded_vmcs->host_state, 0, sizeof(struct vmcs_host_state)); 2578 memset(&loaded_vmcs->controls_shadow, 0, 2579 sizeof(struct vmcs_controls_shadow)); 2580 2581 return 0; 2582 2583 out_vmcs: 2584 free_loaded_vmcs(loaded_vmcs); 2585 return -ENOMEM; 2586 } 2587 2588 static void free_kvm_area(void) 2589 { 2590 int cpu; 2591 2592 for_each_possible_cpu(cpu) { 2593 free_vmcs(per_cpu(vmxarea, cpu)); 2594 per_cpu(vmxarea, cpu) = NULL; 2595 } 2596 } 2597 2598 static __init int alloc_kvm_area(void) 2599 { 2600 int cpu; 2601 2602 for_each_possible_cpu(cpu) { 2603 struct vmcs *vmcs; 2604 2605 vmcs = alloc_vmcs_cpu(false, cpu, GFP_KERNEL); 2606 if (!vmcs) { 2607 free_kvm_area(); 2608 return -ENOMEM; 2609 } 2610 2611 /* 2612 * When eVMCS is enabled, alloc_vmcs_cpu() sets 2613 * vmcs->revision_id to KVM_EVMCS_VERSION instead of 2614 * revision_id reported by MSR_IA32_VMX_BASIC. 2615 * 2616 * However, even though not explicitly documented by 2617 * TLFS, VMXArea passed as VMXON argument should 2618 * still be marked with revision_id reported by 2619 * physical CPU. 2620 */ 2621 if (static_branch_unlikely(&enable_evmcs)) 2622 vmcs->hdr.revision_id = vmcs_config.revision_id; 2623 2624 per_cpu(vmxarea, cpu) = vmcs; 2625 } 2626 return 0; 2627 } 2628 2629 static void fix_pmode_seg(struct kvm_vcpu *vcpu, int seg, 2630 struct kvm_segment *save) 2631 { 2632 if (!emulate_invalid_guest_state) { 2633 /* 2634 * CS and SS RPL should be equal during guest entry according 2635 * to VMX spec, but in reality it is not always so. Since vcpu 2636 * is in the middle of the transition from real mode to 2637 * protected mode it is safe to assume that RPL 0 is a good 2638 * default value. 2639 */ 2640 if (seg == VCPU_SREG_CS || seg == VCPU_SREG_SS) 2641 save->selector &= ~SEGMENT_RPL_MASK; 2642 save->dpl = save->selector & SEGMENT_RPL_MASK; 2643 save->s = 1; 2644 } 2645 vmx_set_segment(vcpu, save, seg); 2646 } 2647 2648 static void enter_pmode(struct kvm_vcpu *vcpu) 2649 { 2650 unsigned long flags; 2651 struct vcpu_vmx *vmx = to_vmx(vcpu); 2652 2653 /* 2654 * Update real mode segment cache. It may be not up-to-date if sement 2655 * register was written while vcpu was in a guest mode. 2656 */ 2657 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES); 2658 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS); 2659 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS); 2660 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS); 2661 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS); 2662 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS); 2663 2664 vmx->rmode.vm86_active = 0; 2665 2666 vmx_set_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR); 2667 2668 flags = vmcs_readl(GUEST_RFLAGS); 2669 flags &= RMODE_GUEST_OWNED_EFLAGS_BITS; 2670 flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS; 2671 vmcs_writel(GUEST_RFLAGS, flags); 2672 2673 vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) | 2674 (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME)); 2675 2676 update_exception_bitmap(vcpu); 2677 2678 fix_pmode_seg(vcpu, VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]); 2679 fix_pmode_seg(vcpu, VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]); 2680 fix_pmode_seg(vcpu, VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]); 2681 fix_pmode_seg(vcpu, VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]); 2682 fix_pmode_seg(vcpu, VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]); 2683 fix_pmode_seg(vcpu, VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]); 2684 } 2685 2686 static void fix_rmode_seg(int seg, struct kvm_segment *save) 2687 { 2688 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg]; 2689 struct kvm_segment var = *save; 2690 2691 var.dpl = 0x3; 2692 if (seg == VCPU_SREG_CS) 2693 var.type = 0x3; 2694 2695 if (!emulate_invalid_guest_state) { 2696 var.selector = var.base >> 4; 2697 var.base = var.base & 0xffff0; 2698 var.limit = 0xffff; 2699 var.g = 0; 2700 var.db = 0; 2701 var.present = 1; 2702 var.s = 1; 2703 var.l = 0; 2704 var.unusable = 0; 2705 var.type = 0x3; 2706 var.avl = 0; 2707 if (save->base & 0xf) 2708 printk_once(KERN_WARNING "kvm: segment base is not " 2709 "paragraph aligned when entering " 2710 "protected mode (seg=%d)", seg); 2711 } 2712 2713 vmcs_write16(sf->selector, var.selector); 2714 vmcs_writel(sf->base, var.base); 2715 vmcs_write32(sf->limit, var.limit); 2716 vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(&var)); 2717 } 2718 2719 static void enter_rmode(struct kvm_vcpu *vcpu) 2720 { 2721 unsigned long flags; 2722 struct vcpu_vmx *vmx = to_vmx(vcpu); 2723 struct kvm_vmx *kvm_vmx = to_kvm_vmx(vcpu->kvm); 2724 2725 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR); 2726 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES); 2727 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS); 2728 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS); 2729 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS); 2730 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS); 2731 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS); 2732 2733 vmx->rmode.vm86_active = 1; 2734 2735 /* 2736 * Very old userspace does not call KVM_SET_TSS_ADDR before entering 2737 * vcpu. Warn the user that an update is overdue. 2738 */ 2739 if (!kvm_vmx->tss_addr) 2740 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be " 2741 "called before entering vcpu\n"); 2742 2743 vmx_segment_cache_clear(vmx); 2744 2745 vmcs_writel(GUEST_TR_BASE, kvm_vmx->tss_addr); 2746 vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1); 2747 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b); 2748 2749 flags = vmcs_readl(GUEST_RFLAGS); 2750 vmx->rmode.save_rflags = flags; 2751 2752 flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM; 2753 2754 vmcs_writel(GUEST_RFLAGS, flags); 2755 vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME); 2756 update_exception_bitmap(vcpu); 2757 2758 fix_rmode_seg(VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]); 2759 fix_rmode_seg(VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]); 2760 fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]); 2761 fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]); 2762 fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]); 2763 fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]); 2764 2765 kvm_mmu_reset_context(vcpu); 2766 } 2767 2768 void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer) 2769 { 2770 struct vcpu_vmx *vmx = to_vmx(vcpu); 2771 struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER); 2772 2773 if (!msr) 2774 return; 2775 2776 vcpu->arch.efer = efer; 2777 if (efer & EFER_LMA) { 2778 vm_entry_controls_setbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE); 2779 msr->data = efer; 2780 } else { 2781 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE); 2782 2783 msr->data = efer & ~EFER_LME; 2784 } 2785 setup_msrs(vmx); 2786 } 2787 2788 #ifdef CONFIG_X86_64 2789 2790 static void enter_lmode(struct kvm_vcpu *vcpu) 2791 { 2792 u32 guest_tr_ar; 2793 2794 vmx_segment_cache_clear(to_vmx(vcpu)); 2795 2796 guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES); 2797 if ((guest_tr_ar & VMX_AR_TYPE_MASK) != VMX_AR_TYPE_BUSY_64_TSS) { 2798 pr_debug_ratelimited("%s: tss fixup for long mode. \n", 2799 __func__); 2800 vmcs_write32(GUEST_TR_AR_BYTES, 2801 (guest_tr_ar & ~VMX_AR_TYPE_MASK) 2802 | VMX_AR_TYPE_BUSY_64_TSS); 2803 } 2804 vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA); 2805 } 2806 2807 static void exit_lmode(struct kvm_vcpu *vcpu) 2808 { 2809 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE); 2810 vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA); 2811 } 2812 2813 #endif 2814 2815 static void vmx_flush_tlb_gva(struct kvm_vcpu *vcpu, gva_t addr) 2816 { 2817 int vpid = to_vmx(vcpu)->vpid; 2818 2819 if (!vpid_sync_vcpu_addr(vpid, addr)) 2820 vpid_sync_context(vpid); 2821 2822 /* 2823 * If VPIDs are not supported or enabled, then the above is a no-op. 2824 * But we don't really need a TLB flush in that case anyway, because 2825 * each VM entry/exit includes an implicit flush when VPID is 0. 2826 */ 2827 } 2828 2829 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu) 2830 { 2831 ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits; 2832 2833 vcpu->arch.cr0 &= ~cr0_guest_owned_bits; 2834 vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits; 2835 } 2836 2837 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu) 2838 { 2839 ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits; 2840 2841 vcpu->arch.cr4 &= ~cr4_guest_owned_bits; 2842 vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits; 2843 } 2844 2845 static void ept_load_pdptrs(struct kvm_vcpu *vcpu) 2846 { 2847 struct kvm_mmu *mmu = vcpu->arch.walk_mmu; 2848 2849 if (!kvm_register_is_dirty(vcpu, VCPU_EXREG_PDPTR)) 2850 return; 2851 2852 if (is_pae_paging(vcpu)) { 2853 vmcs_write64(GUEST_PDPTR0, mmu->pdptrs[0]); 2854 vmcs_write64(GUEST_PDPTR1, mmu->pdptrs[1]); 2855 vmcs_write64(GUEST_PDPTR2, mmu->pdptrs[2]); 2856 vmcs_write64(GUEST_PDPTR3, mmu->pdptrs[3]); 2857 } 2858 } 2859 2860 void ept_save_pdptrs(struct kvm_vcpu *vcpu) 2861 { 2862 struct kvm_mmu *mmu = vcpu->arch.walk_mmu; 2863 2864 if (is_pae_paging(vcpu)) { 2865 mmu->pdptrs[0] = vmcs_read64(GUEST_PDPTR0); 2866 mmu->pdptrs[1] = vmcs_read64(GUEST_PDPTR1); 2867 mmu->pdptrs[2] = vmcs_read64(GUEST_PDPTR2); 2868 mmu->pdptrs[3] = vmcs_read64(GUEST_PDPTR3); 2869 } 2870 2871 kvm_register_mark_dirty(vcpu, VCPU_EXREG_PDPTR); 2872 } 2873 2874 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0, 2875 unsigned long cr0, 2876 struct kvm_vcpu *vcpu) 2877 { 2878 struct vcpu_vmx *vmx = to_vmx(vcpu); 2879 2880 if (!kvm_register_is_available(vcpu, VCPU_EXREG_CR3)) 2881 vmx_cache_reg(vcpu, VCPU_EXREG_CR3); 2882 if (!(cr0 & X86_CR0_PG)) { 2883 /* From paging/starting to nonpaging */ 2884 exec_controls_setbit(vmx, CPU_BASED_CR3_LOAD_EXITING | 2885 CPU_BASED_CR3_STORE_EXITING); 2886 vcpu->arch.cr0 = cr0; 2887 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu)); 2888 } else if (!is_paging(vcpu)) { 2889 /* From nonpaging to paging */ 2890 exec_controls_clearbit(vmx, CPU_BASED_CR3_LOAD_EXITING | 2891 CPU_BASED_CR3_STORE_EXITING); 2892 vcpu->arch.cr0 = cr0; 2893 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu)); 2894 } 2895 2896 if (!(cr0 & X86_CR0_WP)) 2897 *hw_cr0 &= ~X86_CR0_WP; 2898 } 2899 2900 void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0) 2901 { 2902 struct vcpu_vmx *vmx = to_vmx(vcpu); 2903 unsigned long hw_cr0; 2904 2905 hw_cr0 = (cr0 & ~KVM_VM_CR0_ALWAYS_OFF); 2906 if (enable_unrestricted_guest) 2907 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST; 2908 else { 2909 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON; 2910 2911 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE)) 2912 enter_pmode(vcpu); 2913 2914 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE)) 2915 enter_rmode(vcpu); 2916 } 2917 2918 #ifdef CONFIG_X86_64 2919 if (vcpu->arch.efer & EFER_LME) { 2920 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) 2921 enter_lmode(vcpu); 2922 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) 2923 exit_lmode(vcpu); 2924 } 2925 #endif 2926 2927 if (enable_ept && !enable_unrestricted_guest) 2928 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu); 2929 2930 vmcs_writel(CR0_READ_SHADOW, cr0); 2931 vmcs_writel(GUEST_CR0, hw_cr0); 2932 vcpu->arch.cr0 = cr0; 2933 2934 /* depends on vcpu->arch.cr0 to be set to a new value */ 2935 vmx->emulation_required = emulation_required(vcpu); 2936 } 2937 2938 static int get_ept_level(struct kvm_vcpu *vcpu) 2939 { 2940 if (cpu_has_vmx_ept_5levels() && (cpuid_maxphyaddr(vcpu) > 48)) 2941 return 5; 2942 return 4; 2943 } 2944 2945 u64 construct_eptp(struct kvm_vcpu *vcpu, unsigned long root_hpa) 2946 { 2947 u64 eptp = VMX_EPTP_MT_WB; 2948 2949 eptp |= (get_ept_level(vcpu) == 5) ? VMX_EPTP_PWL_5 : VMX_EPTP_PWL_4; 2950 2951 if (enable_ept_ad_bits && 2952 (!is_guest_mode(vcpu) || nested_ept_ad_enabled(vcpu))) 2953 eptp |= VMX_EPTP_AD_ENABLE_BIT; 2954 eptp |= (root_hpa & PAGE_MASK); 2955 2956 return eptp; 2957 } 2958 2959 void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3) 2960 { 2961 struct kvm *kvm = vcpu->kvm; 2962 bool update_guest_cr3 = true; 2963 unsigned long guest_cr3; 2964 u64 eptp; 2965 2966 guest_cr3 = cr3; 2967 if (enable_ept) { 2968 eptp = construct_eptp(vcpu, cr3); 2969 vmcs_write64(EPT_POINTER, eptp); 2970 2971 if (kvm_x86_ops->tlb_remote_flush) { 2972 spin_lock(&to_kvm_vmx(kvm)->ept_pointer_lock); 2973 to_vmx(vcpu)->ept_pointer = eptp; 2974 to_kvm_vmx(kvm)->ept_pointers_match 2975 = EPT_POINTERS_CHECK; 2976 spin_unlock(&to_kvm_vmx(kvm)->ept_pointer_lock); 2977 } 2978 2979 /* Loading vmcs02.GUEST_CR3 is handled by nested VM-Enter. */ 2980 if (is_guest_mode(vcpu)) 2981 update_guest_cr3 = false; 2982 else if (!enable_unrestricted_guest && !is_paging(vcpu)) 2983 guest_cr3 = to_kvm_vmx(kvm)->ept_identity_map_addr; 2984 else if (test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail)) 2985 guest_cr3 = vcpu->arch.cr3; 2986 else /* vmcs01.GUEST_CR3 is already up-to-date. */ 2987 update_guest_cr3 = false; 2988 ept_load_pdptrs(vcpu); 2989 } 2990 2991 if (update_guest_cr3) 2992 vmcs_writel(GUEST_CR3, guest_cr3); 2993 } 2994 2995 int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4) 2996 { 2997 struct vcpu_vmx *vmx = to_vmx(vcpu); 2998 /* 2999 * Pass through host's Machine Check Enable value to hw_cr4, which 3000 * is in force while we are in guest mode. Do not let guests control 3001 * this bit, even if host CR4.MCE == 0. 3002 */ 3003 unsigned long hw_cr4; 3004 3005 hw_cr4 = (cr4_read_shadow() & X86_CR4_MCE) | (cr4 & ~X86_CR4_MCE); 3006 if (enable_unrestricted_guest) 3007 hw_cr4 |= KVM_VM_CR4_ALWAYS_ON_UNRESTRICTED_GUEST; 3008 else if (vmx->rmode.vm86_active) 3009 hw_cr4 |= KVM_RMODE_VM_CR4_ALWAYS_ON; 3010 else 3011 hw_cr4 |= KVM_PMODE_VM_CR4_ALWAYS_ON; 3012 3013 if (!boot_cpu_has(X86_FEATURE_UMIP) && vmx_umip_emulated()) { 3014 if (cr4 & X86_CR4_UMIP) { 3015 secondary_exec_controls_setbit(vmx, SECONDARY_EXEC_DESC); 3016 hw_cr4 &= ~X86_CR4_UMIP; 3017 } else if (!is_guest_mode(vcpu) || 3018 !nested_cpu_has2(get_vmcs12(vcpu), SECONDARY_EXEC_DESC)) { 3019 secondary_exec_controls_clearbit(vmx, SECONDARY_EXEC_DESC); 3020 } 3021 } 3022 3023 if (cr4 & X86_CR4_VMXE) { 3024 /* 3025 * To use VMXON (and later other VMX instructions), a guest 3026 * must first be able to turn on cr4.VMXE (see handle_vmon()). 3027 * So basically the check on whether to allow nested VMX 3028 * is here. We operate under the default treatment of SMM, 3029 * so VMX cannot be enabled under SMM. 3030 */ 3031 if (!nested_vmx_allowed(vcpu) || is_smm(vcpu)) 3032 return 1; 3033 } 3034 3035 if (vmx->nested.vmxon && !nested_cr4_valid(vcpu, cr4)) 3036 return 1; 3037 3038 vcpu->arch.cr4 = cr4; 3039 3040 if (!enable_unrestricted_guest) { 3041 if (enable_ept) { 3042 if (!is_paging(vcpu)) { 3043 hw_cr4 &= ~X86_CR4_PAE; 3044 hw_cr4 |= X86_CR4_PSE; 3045 } else if (!(cr4 & X86_CR4_PAE)) { 3046 hw_cr4 &= ~X86_CR4_PAE; 3047 } 3048 } 3049 3050 /* 3051 * SMEP/SMAP/PKU is disabled if CPU is in non-paging mode in 3052 * hardware. To emulate this behavior, SMEP/SMAP/PKU needs 3053 * to be manually disabled when guest switches to non-paging 3054 * mode. 3055 * 3056 * If !enable_unrestricted_guest, the CPU is always running 3057 * with CR0.PG=1 and CR4 needs to be modified. 3058 * If enable_unrestricted_guest, the CPU automatically 3059 * disables SMEP/SMAP/PKU when the guest sets CR0.PG=0. 3060 */ 3061 if (!is_paging(vcpu)) 3062 hw_cr4 &= ~(X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE); 3063 } 3064 3065 vmcs_writel(CR4_READ_SHADOW, cr4); 3066 vmcs_writel(GUEST_CR4, hw_cr4); 3067 return 0; 3068 } 3069 3070 void vmx_get_segment(struct kvm_vcpu *vcpu, struct kvm_segment *var, int seg) 3071 { 3072 struct vcpu_vmx *vmx = to_vmx(vcpu); 3073 u32 ar; 3074 3075 if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) { 3076 *var = vmx->rmode.segs[seg]; 3077 if (seg == VCPU_SREG_TR 3078 || var->selector == vmx_read_guest_seg_selector(vmx, seg)) 3079 return; 3080 var->base = vmx_read_guest_seg_base(vmx, seg); 3081 var->selector = vmx_read_guest_seg_selector(vmx, seg); 3082 return; 3083 } 3084 var->base = vmx_read_guest_seg_base(vmx, seg); 3085 var->limit = vmx_read_guest_seg_limit(vmx, seg); 3086 var->selector = vmx_read_guest_seg_selector(vmx, seg); 3087 ar = vmx_read_guest_seg_ar(vmx, seg); 3088 var->unusable = (ar >> 16) & 1; 3089 var->type = ar & 15; 3090 var->s = (ar >> 4) & 1; 3091 var->dpl = (ar >> 5) & 3; 3092 /* 3093 * Some userspaces do not preserve unusable property. Since usable 3094 * segment has to be present according to VMX spec we can use present 3095 * property to amend userspace bug by making unusable segment always 3096 * nonpresent. vmx_segment_access_rights() already marks nonpresent 3097 * segment as unusable. 3098 */ 3099 var->present = !var->unusable; 3100 var->avl = (ar >> 12) & 1; 3101 var->l = (ar >> 13) & 1; 3102 var->db = (ar >> 14) & 1; 3103 var->g = (ar >> 15) & 1; 3104 } 3105 3106 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg) 3107 { 3108 struct kvm_segment s; 3109 3110 if (to_vmx(vcpu)->rmode.vm86_active) { 3111 vmx_get_segment(vcpu, &s, seg); 3112 return s.base; 3113 } 3114 return vmx_read_guest_seg_base(to_vmx(vcpu), seg); 3115 } 3116 3117 int vmx_get_cpl(struct kvm_vcpu *vcpu) 3118 { 3119 struct vcpu_vmx *vmx = to_vmx(vcpu); 3120 3121 if (unlikely(vmx->rmode.vm86_active)) 3122 return 0; 3123 else { 3124 int ar = vmx_read_guest_seg_ar(vmx, VCPU_SREG_SS); 3125 return VMX_AR_DPL(ar); 3126 } 3127 } 3128 3129 static u32 vmx_segment_access_rights(struct kvm_segment *var) 3130 { 3131 u32 ar; 3132 3133 if (var->unusable || !var->present) 3134 ar = 1 << 16; 3135 else { 3136 ar = var->type & 15; 3137 ar |= (var->s & 1) << 4; 3138 ar |= (var->dpl & 3) << 5; 3139 ar |= (var->present & 1) << 7; 3140 ar |= (var->avl & 1) << 12; 3141 ar |= (var->l & 1) << 13; 3142 ar |= (var->db & 1) << 14; 3143 ar |= (var->g & 1) << 15; 3144 } 3145 3146 return ar; 3147 } 3148 3149 void vmx_set_segment(struct kvm_vcpu *vcpu, struct kvm_segment *var, int seg) 3150 { 3151 struct vcpu_vmx *vmx = to_vmx(vcpu); 3152 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg]; 3153 3154 vmx_segment_cache_clear(vmx); 3155 3156 if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) { 3157 vmx->rmode.segs[seg] = *var; 3158 if (seg == VCPU_SREG_TR) 3159 vmcs_write16(sf->selector, var->selector); 3160 else if (var->s) 3161 fix_rmode_seg(seg, &vmx->rmode.segs[seg]); 3162 goto out; 3163 } 3164 3165 vmcs_writel(sf->base, var->base); 3166 vmcs_write32(sf->limit, var->limit); 3167 vmcs_write16(sf->selector, var->selector); 3168 3169 /* 3170 * Fix the "Accessed" bit in AR field of segment registers for older 3171 * qemu binaries. 3172 * IA32 arch specifies that at the time of processor reset the 3173 * "Accessed" bit in the AR field of segment registers is 1. And qemu 3174 * is setting it to 0 in the userland code. This causes invalid guest 3175 * state vmexit when "unrestricted guest" mode is turned on. 3176 * Fix for this setup issue in cpu_reset is being pushed in the qemu 3177 * tree. Newer qemu binaries with that qemu fix would not need this 3178 * kvm hack. 3179 */ 3180 if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR)) 3181 var->type |= 0x1; /* Accessed */ 3182 3183 vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(var)); 3184 3185 out: 3186 vmx->emulation_required = emulation_required(vcpu); 3187 } 3188 3189 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l) 3190 { 3191 u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS); 3192 3193 *db = (ar >> 14) & 1; 3194 *l = (ar >> 13) & 1; 3195 } 3196 3197 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt) 3198 { 3199 dt->size = vmcs_read32(GUEST_IDTR_LIMIT); 3200 dt->address = vmcs_readl(GUEST_IDTR_BASE); 3201 } 3202 3203 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt) 3204 { 3205 vmcs_write32(GUEST_IDTR_LIMIT, dt->size); 3206 vmcs_writel(GUEST_IDTR_BASE, dt->address); 3207 } 3208 3209 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt) 3210 { 3211 dt->size = vmcs_read32(GUEST_GDTR_LIMIT); 3212 dt->address = vmcs_readl(GUEST_GDTR_BASE); 3213 } 3214 3215 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt) 3216 { 3217 vmcs_write32(GUEST_GDTR_LIMIT, dt->size); 3218 vmcs_writel(GUEST_GDTR_BASE, dt->address); 3219 } 3220 3221 static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg) 3222 { 3223 struct kvm_segment var; 3224 u32 ar; 3225 3226 vmx_get_segment(vcpu, &var, seg); 3227 var.dpl = 0x3; 3228 if (seg == VCPU_SREG_CS) 3229 var.type = 0x3; 3230 ar = vmx_segment_access_rights(&var); 3231 3232 if (var.base != (var.selector << 4)) 3233 return false; 3234 if (var.limit != 0xffff) 3235 return false; 3236 if (ar != 0xf3) 3237 return false; 3238 3239 return true; 3240 } 3241 3242 static bool code_segment_valid(struct kvm_vcpu *vcpu) 3243 { 3244 struct kvm_segment cs; 3245 unsigned int cs_rpl; 3246 3247 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS); 3248 cs_rpl = cs.selector & SEGMENT_RPL_MASK; 3249 3250 if (cs.unusable) 3251 return false; 3252 if (~cs.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_ACCESSES_MASK)) 3253 return false; 3254 if (!cs.s) 3255 return false; 3256 if (cs.type & VMX_AR_TYPE_WRITEABLE_MASK) { 3257 if (cs.dpl > cs_rpl) 3258 return false; 3259 } else { 3260 if (cs.dpl != cs_rpl) 3261 return false; 3262 } 3263 if (!cs.present) 3264 return false; 3265 3266 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */ 3267 return true; 3268 } 3269 3270 static bool stack_segment_valid(struct kvm_vcpu *vcpu) 3271 { 3272 struct kvm_segment ss; 3273 unsigned int ss_rpl; 3274 3275 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS); 3276 ss_rpl = ss.selector & SEGMENT_RPL_MASK; 3277 3278 if (ss.unusable) 3279 return true; 3280 if (ss.type != 3 && ss.type != 7) 3281 return false; 3282 if (!ss.s) 3283 return false; 3284 if (ss.dpl != ss_rpl) /* DPL != RPL */ 3285 return false; 3286 if (!ss.present) 3287 return false; 3288 3289 return true; 3290 } 3291 3292 static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg) 3293 { 3294 struct kvm_segment var; 3295 unsigned int rpl; 3296 3297 vmx_get_segment(vcpu, &var, seg); 3298 rpl = var.selector & SEGMENT_RPL_MASK; 3299 3300 if (var.unusable) 3301 return true; 3302 if (!var.s) 3303 return false; 3304 if (!var.present) 3305 return false; 3306 if (~var.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_WRITEABLE_MASK)) { 3307 if (var.dpl < rpl) /* DPL < RPL */ 3308 return false; 3309 } 3310 3311 /* TODO: Add other members to kvm_segment_field to allow checking for other access 3312 * rights flags 3313 */ 3314 return true; 3315 } 3316 3317 static bool tr_valid(struct kvm_vcpu *vcpu) 3318 { 3319 struct kvm_segment tr; 3320 3321 vmx_get_segment(vcpu, &tr, VCPU_SREG_TR); 3322 3323 if (tr.unusable) 3324 return false; 3325 if (tr.selector & SEGMENT_TI_MASK) /* TI = 1 */ 3326 return false; 3327 if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */ 3328 return false; 3329 if (!tr.present) 3330 return false; 3331 3332 return true; 3333 } 3334 3335 static bool ldtr_valid(struct kvm_vcpu *vcpu) 3336 { 3337 struct kvm_segment ldtr; 3338 3339 vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR); 3340 3341 if (ldtr.unusable) 3342 return true; 3343 if (ldtr.selector & SEGMENT_TI_MASK) /* TI = 1 */ 3344 return false; 3345 if (ldtr.type != 2) 3346 return false; 3347 if (!ldtr.present) 3348 return false; 3349 3350 return true; 3351 } 3352 3353 static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu) 3354 { 3355 struct kvm_segment cs, ss; 3356 3357 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS); 3358 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS); 3359 3360 return ((cs.selector & SEGMENT_RPL_MASK) == 3361 (ss.selector & SEGMENT_RPL_MASK)); 3362 } 3363 3364 /* 3365 * Check if guest state is valid. Returns true if valid, false if 3366 * not. 3367 * We assume that registers are always usable 3368 */ 3369 static bool guest_state_valid(struct kvm_vcpu *vcpu) 3370 { 3371 if (enable_unrestricted_guest) 3372 return true; 3373 3374 /* real mode guest state checks */ 3375 if (!is_protmode(vcpu) || (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) { 3376 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS)) 3377 return false; 3378 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS)) 3379 return false; 3380 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS)) 3381 return false; 3382 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES)) 3383 return false; 3384 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS)) 3385 return false; 3386 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS)) 3387 return false; 3388 } else { 3389 /* protected mode guest state checks */ 3390 if (!cs_ss_rpl_check(vcpu)) 3391 return false; 3392 if (!code_segment_valid(vcpu)) 3393 return false; 3394 if (!stack_segment_valid(vcpu)) 3395 return false; 3396 if (!data_segment_valid(vcpu, VCPU_SREG_DS)) 3397 return false; 3398 if (!data_segment_valid(vcpu, VCPU_SREG_ES)) 3399 return false; 3400 if (!data_segment_valid(vcpu, VCPU_SREG_FS)) 3401 return false; 3402 if (!data_segment_valid(vcpu, VCPU_SREG_GS)) 3403 return false; 3404 if (!tr_valid(vcpu)) 3405 return false; 3406 if (!ldtr_valid(vcpu)) 3407 return false; 3408 } 3409 /* TODO: 3410 * - Add checks on RIP 3411 * - Add checks on RFLAGS 3412 */ 3413 3414 return true; 3415 } 3416 3417 static int init_rmode_tss(struct kvm *kvm) 3418 { 3419 gfn_t fn; 3420 u16 data = 0; 3421 int idx, r; 3422 3423 idx = srcu_read_lock(&kvm->srcu); 3424 fn = to_kvm_vmx(kvm)->tss_addr >> PAGE_SHIFT; 3425 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE); 3426 if (r < 0) 3427 goto out; 3428 data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE; 3429 r = kvm_write_guest_page(kvm, fn++, &data, 3430 TSS_IOPB_BASE_OFFSET, sizeof(u16)); 3431 if (r < 0) 3432 goto out; 3433 r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE); 3434 if (r < 0) 3435 goto out; 3436 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE); 3437 if (r < 0) 3438 goto out; 3439 data = ~0; 3440 r = kvm_write_guest_page(kvm, fn, &data, 3441 RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1, 3442 sizeof(u8)); 3443 out: 3444 srcu_read_unlock(&kvm->srcu, idx); 3445 return r; 3446 } 3447 3448 static int init_rmode_identity_map(struct kvm *kvm) 3449 { 3450 struct kvm_vmx *kvm_vmx = to_kvm_vmx(kvm); 3451 int i, r = 0; 3452 kvm_pfn_t identity_map_pfn; 3453 u32 tmp; 3454 3455 /* Protect kvm_vmx->ept_identity_pagetable_done. */ 3456 mutex_lock(&kvm->slots_lock); 3457 3458 if (likely(kvm_vmx->ept_identity_pagetable_done)) 3459 goto out; 3460 3461 if (!kvm_vmx->ept_identity_map_addr) 3462 kvm_vmx->ept_identity_map_addr = VMX_EPT_IDENTITY_PAGETABLE_ADDR; 3463 identity_map_pfn = kvm_vmx->ept_identity_map_addr >> PAGE_SHIFT; 3464 3465 r = __x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT, 3466 kvm_vmx->ept_identity_map_addr, PAGE_SIZE); 3467 if (r < 0) 3468 goto out; 3469 3470 r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE); 3471 if (r < 0) 3472 goto out; 3473 /* Set up identity-mapping pagetable for EPT in real mode */ 3474 for (i = 0; i < PT32_ENT_PER_PAGE; i++) { 3475 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER | 3476 _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE); 3477 r = kvm_write_guest_page(kvm, identity_map_pfn, 3478 &tmp, i * sizeof(tmp), sizeof(tmp)); 3479 if (r < 0) 3480 goto out; 3481 } 3482 kvm_vmx->ept_identity_pagetable_done = true; 3483 3484 out: 3485 mutex_unlock(&kvm->slots_lock); 3486 return r; 3487 } 3488 3489 static void seg_setup(int seg) 3490 { 3491 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg]; 3492 unsigned int ar; 3493 3494 vmcs_write16(sf->selector, 0); 3495 vmcs_writel(sf->base, 0); 3496 vmcs_write32(sf->limit, 0xffff); 3497 ar = 0x93; 3498 if (seg == VCPU_SREG_CS) 3499 ar |= 0x08; /* code segment */ 3500 3501 vmcs_write32(sf->ar_bytes, ar); 3502 } 3503 3504 static int alloc_apic_access_page(struct kvm *kvm) 3505 { 3506 struct page *page; 3507 int r = 0; 3508 3509 mutex_lock(&kvm->slots_lock); 3510 if (kvm->arch.apic_access_page_done) 3511 goto out; 3512 r = __x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT, 3513 APIC_DEFAULT_PHYS_BASE, PAGE_SIZE); 3514 if (r) 3515 goto out; 3516 3517 page = gfn_to_page(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT); 3518 if (is_error_page(page)) { 3519 r = -EFAULT; 3520 goto out; 3521 } 3522 3523 /* 3524 * Do not pin the page in memory, so that memory hot-unplug 3525 * is able to migrate it. 3526 */ 3527 put_page(page); 3528 kvm->arch.apic_access_page_done = true; 3529 out: 3530 mutex_unlock(&kvm->slots_lock); 3531 return r; 3532 } 3533 3534 int allocate_vpid(void) 3535 { 3536 int vpid; 3537 3538 if (!enable_vpid) 3539 return 0; 3540 spin_lock(&vmx_vpid_lock); 3541 vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS); 3542 if (vpid < VMX_NR_VPIDS) 3543 __set_bit(vpid, vmx_vpid_bitmap); 3544 else 3545 vpid = 0; 3546 spin_unlock(&vmx_vpid_lock); 3547 return vpid; 3548 } 3549 3550 void free_vpid(int vpid) 3551 { 3552 if (!enable_vpid || vpid == 0) 3553 return; 3554 spin_lock(&vmx_vpid_lock); 3555 __clear_bit(vpid, vmx_vpid_bitmap); 3556 spin_unlock(&vmx_vpid_lock); 3557 } 3558 3559 static __always_inline void vmx_disable_intercept_for_msr(unsigned long *msr_bitmap, 3560 u32 msr, int type) 3561 { 3562 int f = sizeof(unsigned long); 3563 3564 if (!cpu_has_vmx_msr_bitmap()) 3565 return; 3566 3567 if (static_branch_unlikely(&enable_evmcs)) 3568 evmcs_touch_msr_bitmap(); 3569 3570 /* 3571 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals 3572 * have the write-low and read-high bitmap offsets the wrong way round. 3573 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff. 3574 */ 3575 if (msr <= 0x1fff) { 3576 if (type & MSR_TYPE_R) 3577 /* read-low */ 3578 __clear_bit(msr, msr_bitmap + 0x000 / f); 3579 3580 if (type & MSR_TYPE_W) 3581 /* write-low */ 3582 __clear_bit(msr, msr_bitmap + 0x800 / f); 3583 3584 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) { 3585 msr &= 0x1fff; 3586 if (type & MSR_TYPE_R) 3587 /* read-high */ 3588 __clear_bit(msr, msr_bitmap + 0x400 / f); 3589 3590 if (type & MSR_TYPE_W) 3591 /* write-high */ 3592 __clear_bit(msr, msr_bitmap + 0xc00 / f); 3593 3594 } 3595 } 3596 3597 static __always_inline void vmx_enable_intercept_for_msr(unsigned long *msr_bitmap, 3598 u32 msr, int type) 3599 { 3600 int f = sizeof(unsigned long); 3601 3602 if (!cpu_has_vmx_msr_bitmap()) 3603 return; 3604 3605 if (static_branch_unlikely(&enable_evmcs)) 3606 evmcs_touch_msr_bitmap(); 3607 3608 /* 3609 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals 3610 * have the write-low and read-high bitmap offsets the wrong way round. 3611 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff. 3612 */ 3613 if (msr <= 0x1fff) { 3614 if (type & MSR_TYPE_R) 3615 /* read-low */ 3616 __set_bit(msr, msr_bitmap + 0x000 / f); 3617 3618 if (type & MSR_TYPE_W) 3619 /* write-low */ 3620 __set_bit(msr, msr_bitmap + 0x800 / f); 3621 3622 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) { 3623 msr &= 0x1fff; 3624 if (type & MSR_TYPE_R) 3625 /* read-high */ 3626 __set_bit(msr, msr_bitmap + 0x400 / f); 3627 3628 if (type & MSR_TYPE_W) 3629 /* write-high */ 3630 __set_bit(msr, msr_bitmap + 0xc00 / f); 3631 3632 } 3633 } 3634 3635 static __always_inline void vmx_set_intercept_for_msr(unsigned long *msr_bitmap, 3636 u32 msr, int type, bool value) 3637 { 3638 if (value) 3639 vmx_enable_intercept_for_msr(msr_bitmap, msr, type); 3640 else 3641 vmx_disable_intercept_for_msr(msr_bitmap, msr, type); 3642 } 3643 3644 static u8 vmx_msr_bitmap_mode(struct kvm_vcpu *vcpu) 3645 { 3646 u8 mode = 0; 3647 3648 if (cpu_has_secondary_exec_ctrls() && 3649 (secondary_exec_controls_get(to_vmx(vcpu)) & 3650 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE)) { 3651 mode |= MSR_BITMAP_MODE_X2APIC; 3652 if (enable_apicv && kvm_vcpu_apicv_active(vcpu)) 3653 mode |= MSR_BITMAP_MODE_X2APIC_APICV; 3654 } 3655 3656 return mode; 3657 } 3658 3659 static void vmx_update_msr_bitmap_x2apic(unsigned long *msr_bitmap, 3660 u8 mode) 3661 { 3662 int msr; 3663 3664 for (msr = 0x800; msr <= 0x8ff; msr += BITS_PER_LONG) { 3665 unsigned word = msr / BITS_PER_LONG; 3666 msr_bitmap[word] = (mode & MSR_BITMAP_MODE_X2APIC_APICV) ? 0 : ~0; 3667 msr_bitmap[word + (0x800 / sizeof(long))] = ~0; 3668 } 3669 3670 if (mode & MSR_BITMAP_MODE_X2APIC) { 3671 /* 3672 * TPR reads and writes can be virtualized even if virtual interrupt 3673 * delivery is not in use. 3674 */ 3675 vmx_disable_intercept_for_msr(msr_bitmap, X2APIC_MSR(APIC_TASKPRI), MSR_TYPE_RW); 3676 if (mode & MSR_BITMAP_MODE_X2APIC_APICV) { 3677 vmx_enable_intercept_for_msr(msr_bitmap, X2APIC_MSR(APIC_TMCCT), MSR_TYPE_R); 3678 vmx_disable_intercept_for_msr(msr_bitmap, X2APIC_MSR(APIC_EOI), MSR_TYPE_W); 3679 vmx_disable_intercept_for_msr(msr_bitmap, X2APIC_MSR(APIC_SELF_IPI), MSR_TYPE_W); 3680 } 3681 } 3682 } 3683 3684 void vmx_update_msr_bitmap(struct kvm_vcpu *vcpu) 3685 { 3686 struct vcpu_vmx *vmx = to_vmx(vcpu); 3687 unsigned long *msr_bitmap = vmx->vmcs01.msr_bitmap; 3688 u8 mode = vmx_msr_bitmap_mode(vcpu); 3689 u8 changed = mode ^ vmx->msr_bitmap_mode; 3690 3691 if (!changed) 3692 return; 3693 3694 if (changed & (MSR_BITMAP_MODE_X2APIC | MSR_BITMAP_MODE_X2APIC_APICV)) 3695 vmx_update_msr_bitmap_x2apic(msr_bitmap, mode); 3696 3697 vmx->msr_bitmap_mode = mode; 3698 } 3699 3700 void pt_update_intercept_for_msr(struct vcpu_vmx *vmx) 3701 { 3702 unsigned long *msr_bitmap = vmx->vmcs01.msr_bitmap; 3703 bool flag = !(vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN); 3704 u32 i; 3705 3706 vmx_set_intercept_for_msr(msr_bitmap, MSR_IA32_RTIT_STATUS, 3707 MSR_TYPE_RW, flag); 3708 vmx_set_intercept_for_msr(msr_bitmap, MSR_IA32_RTIT_OUTPUT_BASE, 3709 MSR_TYPE_RW, flag); 3710 vmx_set_intercept_for_msr(msr_bitmap, MSR_IA32_RTIT_OUTPUT_MASK, 3711 MSR_TYPE_RW, flag); 3712 vmx_set_intercept_for_msr(msr_bitmap, MSR_IA32_RTIT_CR3_MATCH, 3713 MSR_TYPE_RW, flag); 3714 for (i = 0; i < vmx->pt_desc.addr_range; i++) { 3715 vmx_set_intercept_for_msr(msr_bitmap, 3716 MSR_IA32_RTIT_ADDR0_A + i * 2, MSR_TYPE_RW, flag); 3717 vmx_set_intercept_for_msr(msr_bitmap, 3718 MSR_IA32_RTIT_ADDR0_B + i * 2, MSR_TYPE_RW, flag); 3719 } 3720 } 3721 3722 static bool vmx_get_enable_apicv(struct kvm *kvm) 3723 { 3724 return enable_apicv; 3725 } 3726 3727 static bool vmx_guest_apic_has_interrupt(struct kvm_vcpu *vcpu) 3728 { 3729 struct vcpu_vmx *vmx = to_vmx(vcpu); 3730 void *vapic_page; 3731 u32 vppr; 3732 int rvi; 3733 3734 if (WARN_ON_ONCE(!is_guest_mode(vcpu)) || 3735 !nested_cpu_has_vid(get_vmcs12(vcpu)) || 3736 WARN_ON_ONCE(!vmx->nested.virtual_apic_map.gfn)) 3737 return false; 3738 3739 rvi = vmx_get_rvi(); 3740 3741 vapic_page = vmx->nested.virtual_apic_map.hva; 3742 vppr = *((u32 *)(vapic_page + APIC_PROCPRI)); 3743 3744 return ((rvi & 0xf0) > (vppr & 0xf0)); 3745 } 3746 3747 static inline bool kvm_vcpu_trigger_posted_interrupt(struct kvm_vcpu *vcpu, 3748 bool nested) 3749 { 3750 #ifdef CONFIG_SMP 3751 int pi_vec = nested ? POSTED_INTR_NESTED_VECTOR : POSTED_INTR_VECTOR; 3752 3753 if (vcpu->mode == IN_GUEST_MODE) { 3754 /* 3755 * The vector of interrupt to be delivered to vcpu had 3756 * been set in PIR before this function. 3757 * 3758 * Following cases will be reached in this block, and 3759 * we always send a notification event in all cases as 3760 * explained below. 3761 * 3762 * Case 1: vcpu keeps in non-root mode. Sending a 3763 * notification event posts the interrupt to vcpu. 3764 * 3765 * Case 2: vcpu exits to root mode and is still 3766 * runnable. PIR will be synced to vIRR before the 3767 * next vcpu entry. Sending a notification event in 3768 * this case has no effect, as vcpu is not in root 3769 * mode. 3770 * 3771 * Case 3: vcpu exits to root mode and is blocked. 3772 * vcpu_block() has already synced PIR to vIRR and 3773 * never blocks vcpu if vIRR is not cleared. Therefore, 3774 * a blocked vcpu here does not wait for any requested 3775 * interrupts in PIR, and sending a notification event 3776 * which has no effect is safe here. 3777 */ 3778 3779 apic->send_IPI_mask(get_cpu_mask(vcpu->cpu), pi_vec); 3780 return true; 3781 } 3782 #endif 3783 return false; 3784 } 3785 3786 static int vmx_deliver_nested_posted_interrupt(struct kvm_vcpu *vcpu, 3787 int vector) 3788 { 3789 struct vcpu_vmx *vmx = to_vmx(vcpu); 3790 3791 if (is_guest_mode(vcpu) && 3792 vector == vmx->nested.posted_intr_nv) { 3793 /* 3794 * If a posted intr is not recognized by hardware, 3795 * we will accomplish it in the next vmentry. 3796 */ 3797 vmx->nested.pi_pending = true; 3798 kvm_make_request(KVM_REQ_EVENT, vcpu); 3799 /* the PIR and ON have been set by L1. */ 3800 if (!kvm_vcpu_trigger_posted_interrupt(vcpu, true)) 3801 kvm_vcpu_kick(vcpu); 3802 return 0; 3803 } 3804 return -1; 3805 } 3806 /* 3807 * Send interrupt to vcpu via posted interrupt way. 3808 * 1. If target vcpu is running(non-root mode), send posted interrupt 3809 * notification to vcpu and hardware will sync PIR to vIRR atomically. 3810 * 2. If target vcpu isn't running(root mode), kick it to pick up the 3811 * interrupt from PIR in next vmentry. 3812 */ 3813 static void vmx_deliver_posted_interrupt(struct kvm_vcpu *vcpu, int vector) 3814 { 3815 struct vcpu_vmx *vmx = to_vmx(vcpu); 3816 int r; 3817 3818 r = vmx_deliver_nested_posted_interrupt(vcpu, vector); 3819 if (!r) 3820 return; 3821 3822 if (pi_test_and_set_pir(vector, &vmx->pi_desc)) 3823 return; 3824 3825 /* If a previous notification has sent the IPI, nothing to do. */ 3826 if (pi_test_and_set_on(&vmx->pi_desc)) 3827 return; 3828 3829 if (!kvm_vcpu_trigger_posted_interrupt(vcpu, false)) 3830 kvm_vcpu_kick(vcpu); 3831 } 3832 3833 /* 3834 * Set up the vmcs's constant host-state fields, i.e., host-state fields that 3835 * will not change in the lifetime of the guest. 3836 * Note that host-state that does change is set elsewhere. E.g., host-state 3837 * that is set differently for each CPU is set in vmx_vcpu_load(), not here. 3838 */ 3839 void vmx_set_constant_host_state(struct vcpu_vmx *vmx) 3840 { 3841 u32 low32, high32; 3842 unsigned long tmpl; 3843 unsigned long cr0, cr3, cr4; 3844 3845 cr0 = read_cr0(); 3846 WARN_ON(cr0 & X86_CR0_TS); 3847 vmcs_writel(HOST_CR0, cr0); /* 22.2.3 */ 3848 3849 /* 3850 * Save the most likely value for this task's CR3 in the VMCS. 3851 * We can't use __get_current_cr3_fast() because we're not atomic. 3852 */ 3853 cr3 = __read_cr3(); 3854 vmcs_writel(HOST_CR3, cr3); /* 22.2.3 FIXME: shadow tables */ 3855 vmx->loaded_vmcs->host_state.cr3 = cr3; 3856 3857 /* Save the most likely value for this task's CR4 in the VMCS. */ 3858 cr4 = cr4_read_shadow(); 3859 vmcs_writel(HOST_CR4, cr4); /* 22.2.3, 22.2.5 */ 3860 vmx->loaded_vmcs->host_state.cr4 = cr4; 3861 3862 vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */ 3863 #ifdef CONFIG_X86_64 3864 /* 3865 * Load null selectors, so we can avoid reloading them in 3866 * vmx_prepare_switch_to_host(), in case userspace uses 3867 * the null selectors too (the expected case). 3868 */ 3869 vmcs_write16(HOST_DS_SELECTOR, 0); 3870 vmcs_write16(HOST_ES_SELECTOR, 0); 3871 #else 3872 vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */ 3873 vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */ 3874 #endif 3875 vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */ 3876 vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */ 3877 3878 vmcs_writel(HOST_IDTR_BASE, host_idt_base); /* 22.2.4 */ 3879 3880 vmcs_writel(HOST_RIP, (unsigned long)vmx_vmexit); /* 22.2.5 */ 3881 3882 rdmsr(MSR_IA32_SYSENTER_CS, low32, high32); 3883 vmcs_write32(HOST_IA32_SYSENTER_CS, low32); 3884 rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl); 3885 vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl); /* 22.2.3 */ 3886 3887 if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) { 3888 rdmsr(MSR_IA32_CR_PAT, low32, high32); 3889 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32)); 3890 } 3891 3892 if (cpu_has_load_ia32_efer()) 3893 vmcs_write64(HOST_IA32_EFER, host_efer); 3894 } 3895 3896 void set_cr4_guest_host_mask(struct vcpu_vmx *vmx) 3897 { 3898 vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS; 3899 if (enable_ept) 3900 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE; 3901 if (is_guest_mode(&vmx->vcpu)) 3902 vmx->vcpu.arch.cr4_guest_owned_bits &= 3903 ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask; 3904 vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits); 3905 } 3906 3907 u32 vmx_pin_based_exec_ctrl(struct vcpu_vmx *vmx) 3908 { 3909 u32 pin_based_exec_ctrl = vmcs_config.pin_based_exec_ctrl; 3910 3911 if (!kvm_vcpu_apicv_active(&vmx->vcpu)) 3912 pin_based_exec_ctrl &= ~PIN_BASED_POSTED_INTR; 3913 3914 if (!enable_vnmi) 3915 pin_based_exec_ctrl &= ~PIN_BASED_VIRTUAL_NMIS; 3916 3917 if (!enable_preemption_timer) 3918 pin_based_exec_ctrl &= ~PIN_BASED_VMX_PREEMPTION_TIMER; 3919 3920 return pin_based_exec_ctrl; 3921 } 3922 3923 static void vmx_refresh_apicv_exec_ctrl(struct kvm_vcpu *vcpu) 3924 { 3925 struct vcpu_vmx *vmx = to_vmx(vcpu); 3926 3927 pin_controls_set(vmx, vmx_pin_based_exec_ctrl(vmx)); 3928 if (cpu_has_secondary_exec_ctrls()) { 3929 if (kvm_vcpu_apicv_active(vcpu)) 3930 secondary_exec_controls_setbit(vmx, 3931 SECONDARY_EXEC_APIC_REGISTER_VIRT | 3932 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY); 3933 else 3934 secondary_exec_controls_clearbit(vmx, 3935 SECONDARY_EXEC_APIC_REGISTER_VIRT | 3936 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY); 3937 } 3938 3939 if (cpu_has_vmx_msr_bitmap()) 3940 vmx_update_msr_bitmap(vcpu); 3941 } 3942 3943 u32 vmx_exec_control(struct vcpu_vmx *vmx) 3944 { 3945 u32 exec_control = vmcs_config.cpu_based_exec_ctrl; 3946 3947 if (vmx->vcpu.arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT) 3948 exec_control &= ~CPU_BASED_MOV_DR_EXITING; 3949 3950 if (!cpu_need_tpr_shadow(&vmx->vcpu)) { 3951 exec_control &= ~CPU_BASED_TPR_SHADOW; 3952 #ifdef CONFIG_X86_64 3953 exec_control |= CPU_BASED_CR8_STORE_EXITING | 3954 CPU_BASED_CR8_LOAD_EXITING; 3955 #endif 3956 } 3957 if (!enable_ept) 3958 exec_control |= CPU_BASED_CR3_STORE_EXITING | 3959 CPU_BASED_CR3_LOAD_EXITING | 3960 CPU_BASED_INVLPG_EXITING; 3961 if (kvm_mwait_in_guest(vmx->vcpu.kvm)) 3962 exec_control &= ~(CPU_BASED_MWAIT_EXITING | 3963 CPU_BASED_MONITOR_EXITING); 3964 if (kvm_hlt_in_guest(vmx->vcpu.kvm)) 3965 exec_control &= ~CPU_BASED_HLT_EXITING; 3966 return exec_control; 3967 } 3968 3969 3970 static void vmx_compute_secondary_exec_control(struct vcpu_vmx *vmx) 3971 { 3972 struct kvm_vcpu *vcpu = &vmx->vcpu; 3973 3974 u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl; 3975 3976 if (pt_mode == PT_MODE_SYSTEM) 3977 exec_control &= ~(SECONDARY_EXEC_PT_USE_GPA | SECONDARY_EXEC_PT_CONCEAL_VMX); 3978 if (!cpu_need_virtualize_apic_accesses(vcpu)) 3979 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES; 3980 if (vmx->vpid == 0) 3981 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID; 3982 if (!enable_ept) { 3983 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT; 3984 enable_unrestricted_guest = 0; 3985 } 3986 if (!enable_unrestricted_guest) 3987 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST; 3988 if (kvm_pause_in_guest(vmx->vcpu.kvm)) 3989 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING; 3990 if (!kvm_vcpu_apicv_active(vcpu)) 3991 exec_control &= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT | 3992 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY); 3993 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE; 3994 3995 /* SECONDARY_EXEC_DESC is enabled/disabled on writes to CR4.UMIP, 3996 * in vmx_set_cr4. */ 3997 exec_control &= ~SECONDARY_EXEC_DESC; 3998 3999 /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD 4000 (handle_vmptrld). 4001 We can NOT enable shadow_vmcs here because we don't have yet 4002 a current VMCS12 4003 */ 4004 exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS; 4005 4006 if (!enable_pml) 4007 exec_control &= ~SECONDARY_EXEC_ENABLE_PML; 4008 4009 if (vmx_xsaves_supported()) { 4010 /* Exposing XSAVES only when XSAVE is exposed */ 4011 bool xsaves_enabled = 4012 boot_cpu_has(X86_FEATURE_XSAVE) && 4013 guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) && 4014 guest_cpuid_has(vcpu, X86_FEATURE_XSAVES); 4015 4016 vcpu->arch.xsaves_enabled = xsaves_enabled; 4017 4018 if (!xsaves_enabled) 4019 exec_control &= ~SECONDARY_EXEC_XSAVES; 4020 4021 if (nested) { 4022 if (xsaves_enabled) 4023 vmx->nested.msrs.secondary_ctls_high |= 4024 SECONDARY_EXEC_XSAVES; 4025 else 4026 vmx->nested.msrs.secondary_ctls_high &= 4027 ~SECONDARY_EXEC_XSAVES; 4028 } 4029 } 4030 4031 if (vmx_rdtscp_supported()) { 4032 bool rdtscp_enabled = guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP); 4033 if (!rdtscp_enabled) 4034 exec_control &= ~SECONDARY_EXEC_RDTSCP; 4035 4036 if (nested) { 4037 if (rdtscp_enabled) 4038 vmx->nested.msrs.secondary_ctls_high |= 4039 SECONDARY_EXEC_RDTSCP; 4040 else 4041 vmx->nested.msrs.secondary_ctls_high &= 4042 ~SECONDARY_EXEC_RDTSCP; 4043 } 4044 } 4045 4046 if (vmx_invpcid_supported()) { 4047 /* Exposing INVPCID only when PCID is exposed */ 4048 bool invpcid_enabled = 4049 guest_cpuid_has(vcpu, X86_FEATURE_INVPCID) && 4050 guest_cpuid_has(vcpu, X86_FEATURE_PCID); 4051 4052 if (!invpcid_enabled) { 4053 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID; 4054 guest_cpuid_clear(vcpu, X86_FEATURE_INVPCID); 4055 } 4056 4057 if (nested) { 4058 if (invpcid_enabled) 4059 vmx->nested.msrs.secondary_ctls_high |= 4060 SECONDARY_EXEC_ENABLE_INVPCID; 4061 else 4062 vmx->nested.msrs.secondary_ctls_high &= 4063 ~SECONDARY_EXEC_ENABLE_INVPCID; 4064 } 4065 } 4066 4067 if (vmx_rdrand_supported()) { 4068 bool rdrand_enabled = guest_cpuid_has(vcpu, X86_FEATURE_RDRAND); 4069 if (rdrand_enabled) 4070 exec_control &= ~SECONDARY_EXEC_RDRAND_EXITING; 4071 4072 if (nested) { 4073 if (rdrand_enabled) 4074 vmx->nested.msrs.secondary_ctls_high |= 4075 SECONDARY_EXEC_RDRAND_EXITING; 4076 else 4077 vmx->nested.msrs.secondary_ctls_high &= 4078 ~SECONDARY_EXEC_RDRAND_EXITING; 4079 } 4080 } 4081 4082 if (vmx_rdseed_supported()) { 4083 bool rdseed_enabled = guest_cpuid_has(vcpu, X86_FEATURE_RDSEED); 4084 if (rdseed_enabled) 4085 exec_control &= ~SECONDARY_EXEC_RDSEED_EXITING; 4086 4087 if (nested) { 4088 if (rdseed_enabled) 4089 vmx->nested.msrs.secondary_ctls_high |= 4090 SECONDARY_EXEC_RDSEED_EXITING; 4091 else 4092 vmx->nested.msrs.secondary_ctls_high &= 4093 ~SECONDARY_EXEC_RDSEED_EXITING; 4094 } 4095 } 4096 4097 if (vmx_waitpkg_supported()) { 4098 bool waitpkg_enabled = 4099 guest_cpuid_has(vcpu, X86_FEATURE_WAITPKG); 4100 4101 if (!waitpkg_enabled) 4102 exec_control &= ~SECONDARY_EXEC_ENABLE_USR_WAIT_PAUSE; 4103 4104 if (nested) { 4105 if (waitpkg_enabled) 4106 vmx->nested.msrs.secondary_ctls_high |= 4107 SECONDARY_EXEC_ENABLE_USR_WAIT_PAUSE; 4108 else 4109 vmx->nested.msrs.secondary_ctls_high &= 4110 ~SECONDARY_EXEC_ENABLE_USR_WAIT_PAUSE; 4111 } 4112 } 4113 4114 vmx->secondary_exec_control = exec_control; 4115 } 4116 4117 static void ept_set_mmio_spte_mask(void) 4118 { 4119 /* 4120 * EPT Misconfigurations can be generated if the value of bits 2:0 4121 * of an EPT paging-structure entry is 110b (write/execute). 4122 */ 4123 kvm_mmu_set_mmio_spte_mask(VMX_EPT_RWX_MASK, 4124 VMX_EPT_MISCONFIG_WX_VALUE, 0); 4125 } 4126 4127 #define VMX_XSS_EXIT_BITMAP 0 4128 4129 /* 4130 * Noting that the initialization of Guest-state Area of VMCS is in 4131 * vmx_vcpu_reset(). 4132 */ 4133 static void init_vmcs(struct vcpu_vmx *vmx) 4134 { 4135 if (nested) 4136 nested_vmx_set_vmcs_shadowing_bitmap(); 4137 4138 if (cpu_has_vmx_msr_bitmap()) 4139 vmcs_write64(MSR_BITMAP, __pa(vmx->vmcs01.msr_bitmap)); 4140 4141 vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */ 4142 4143 /* Control */ 4144 pin_controls_set(vmx, vmx_pin_based_exec_ctrl(vmx)); 4145 4146 exec_controls_set(vmx, vmx_exec_control(vmx)); 4147 4148 if (cpu_has_secondary_exec_ctrls()) { 4149 vmx_compute_secondary_exec_control(vmx); 4150 secondary_exec_controls_set(vmx, vmx->secondary_exec_control); 4151 } 4152 4153 if (kvm_vcpu_apicv_active(&vmx->vcpu)) { 4154 vmcs_write64(EOI_EXIT_BITMAP0, 0); 4155 vmcs_write64(EOI_EXIT_BITMAP1, 0); 4156 vmcs_write64(EOI_EXIT_BITMAP2, 0); 4157 vmcs_write64(EOI_EXIT_BITMAP3, 0); 4158 4159 vmcs_write16(GUEST_INTR_STATUS, 0); 4160 4161 vmcs_write16(POSTED_INTR_NV, POSTED_INTR_VECTOR); 4162 vmcs_write64(POSTED_INTR_DESC_ADDR, __pa((&vmx->pi_desc))); 4163 } 4164 4165 if (!kvm_pause_in_guest(vmx->vcpu.kvm)) { 4166 vmcs_write32(PLE_GAP, ple_gap); 4167 vmx->ple_window = ple_window; 4168 vmx->ple_window_dirty = true; 4169 } 4170 4171 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0); 4172 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0); 4173 vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */ 4174 4175 vmcs_write16(HOST_FS_SELECTOR, 0); /* 22.2.4 */ 4176 vmcs_write16(HOST_GS_SELECTOR, 0); /* 22.2.4 */ 4177 vmx_set_constant_host_state(vmx); 4178 vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */ 4179 vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */ 4180 4181 if (cpu_has_vmx_vmfunc()) 4182 vmcs_write64(VM_FUNCTION_CONTROL, 0); 4183 4184 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0); 4185 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0); 4186 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host.val)); 4187 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0); 4188 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest.val)); 4189 4190 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) 4191 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat); 4192 4193 vm_exit_controls_set(vmx, vmx_vmexit_ctrl()); 4194 4195 /* 22.2.1, 20.8.1 */ 4196 vm_entry_controls_set(vmx, vmx_vmentry_ctrl()); 4197 4198 vmx->vcpu.arch.cr0_guest_owned_bits = X86_CR0_TS; 4199 vmcs_writel(CR0_GUEST_HOST_MASK, ~X86_CR0_TS); 4200 4201 set_cr4_guest_host_mask(vmx); 4202 4203 if (vmx->vpid != 0) 4204 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid); 4205 4206 if (vmx_xsaves_supported()) 4207 vmcs_write64(XSS_EXIT_BITMAP, VMX_XSS_EXIT_BITMAP); 4208 4209 if (enable_pml) { 4210 vmcs_write64(PML_ADDRESS, page_to_phys(vmx->pml_pg)); 4211 vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1); 4212 } 4213 4214 if (cpu_has_vmx_encls_vmexit()) 4215 vmcs_write64(ENCLS_EXITING_BITMAP, -1ull); 4216 4217 if (pt_mode == PT_MODE_HOST_GUEST) { 4218 memset(&vmx->pt_desc, 0, sizeof(vmx->pt_desc)); 4219 /* Bit[6~0] are forced to 1, writes are ignored. */ 4220 vmx->pt_desc.guest.output_mask = 0x7F; 4221 vmcs_write64(GUEST_IA32_RTIT_CTL, 0); 4222 } 4223 } 4224 4225 static void vmx_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event) 4226 { 4227 struct vcpu_vmx *vmx = to_vmx(vcpu); 4228 struct msr_data apic_base_msr; 4229 u64 cr0; 4230 4231 vmx->rmode.vm86_active = 0; 4232 vmx->spec_ctrl = 0; 4233 4234 vmx->msr_ia32_umwait_control = 0; 4235 4236 vcpu->arch.microcode_version = 0x100000000ULL; 4237 vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val(); 4238 vmx->hv_deadline_tsc = -1; 4239 kvm_set_cr8(vcpu, 0); 4240 4241 if (!init_event) { 4242 apic_base_msr.data = APIC_DEFAULT_PHYS_BASE | 4243 MSR_IA32_APICBASE_ENABLE; 4244 if (kvm_vcpu_is_reset_bsp(vcpu)) 4245 apic_base_msr.data |= MSR_IA32_APICBASE_BSP; 4246 apic_base_msr.host_initiated = true; 4247 kvm_set_apic_base(vcpu, &apic_base_msr); 4248 } 4249 4250 vmx_segment_cache_clear(vmx); 4251 4252 seg_setup(VCPU_SREG_CS); 4253 vmcs_write16(GUEST_CS_SELECTOR, 0xf000); 4254 vmcs_writel(GUEST_CS_BASE, 0xffff0000ul); 4255 4256 seg_setup(VCPU_SREG_DS); 4257 seg_setup(VCPU_SREG_ES); 4258 seg_setup(VCPU_SREG_FS); 4259 seg_setup(VCPU_SREG_GS); 4260 seg_setup(VCPU_SREG_SS); 4261 4262 vmcs_write16(GUEST_TR_SELECTOR, 0); 4263 vmcs_writel(GUEST_TR_BASE, 0); 4264 vmcs_write32(GUEST_TR_LIMIT, 0xffff); 4265 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b); 4266 4267 vmcs_write16(GUEST_LDTR_SELECTOR, 0); 4268 vmcs_writel(GUEST_LDTR_BASE, 0); 4269 vmcs_write32(GUEST_LDTR_LIMIT, 0xffff); 4270 vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082); 4271 4272 if (!init_event) { 4273 vmcs_write32(GUEST_SYSENTER_CS, 0); 4274 vmcs_writel(GUEST_SYSENTER_ESP, 0); 4275 vmcs_writel(GUEST_SYSENTER_EIP, 0); 4276 vmcs_write64(GUEST_IA32_DEBUGCTL, 0); 4277 } 4278 4279 kvm_set_rflags(vcpu, X86_EFLAGS_FIXED); 4280 kvm_rip_write(vcpu, 0xfff0); 4281 4282 vmcs_writel(GUEST_GDTR_BASE, 0); 4283 vmcs_write32(GUEST_GDTR_LIMIT, 0xffff); 4284 4285 vmcs_writel(GUEST_IDTR_BASE, 0); 4286 vmcs_write32(GUEST_IDTR_LIMIT, 0xffff); 4287 4288 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE); 4289 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0); 4290 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS, 0); 4291 if (kvm_mpx_supported()) 4292 vmcs_write64(GUEST_BNDCFGS, 0); 4293 4294 setup_msrs(vmx); 4295 4296 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */ 4297 4298 if (cpu_has_vmx_tpr_shadow() && !init_event) { 4299 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0); 4300 if (cpu_need_tpr_shadow(vcpu)) 4301 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 4302 __pa(vcpu->arch.apic->regs)); 4303 vmcs_write32(TPR_THRESHOLD, 0); 4304 } 4305 4306 kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu); 4307 4308 cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET; 4309 vmx->vcpu.arch.cr0 = cr0; 4310 vmx_set_cr0(vcpu, cr0); /* enter rmode */ 4311 vmx_set_cr4(vcpu, 0); 4312 vmx_set_efer(vcpu, 0); 4313 4314 update_exception_bitmap(vcpu); 4315 4316 vpid_sync_context(vmx->vpid); 4317 if (init_event) 4318 vmx_clear_hlt(vcpu); 4319 } 4320 4321 static void enable_irq_window(struct kvm_vcpu *vcpu) 4322 { 4323 exec_controls_setbit(to_vmx(vcpu), CPU_BASED_INTR_WINDOW_EXITING); 4324 } 4325 4326 static void enable_nmi_window(struct kvm_vcpu *vcpu) 4327 { 4328 if (!enable_vnmi || 4329 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) { 4330 enable_irq_window(vcpu); 4331 return; 4332 } 4333 4334 exec_controls_setbit(to_vmx(vcpu), CPU_BASED_NMI_WINDOW_EXITING); 4335 } 4336 4337 static void vmx_inject_irq(struct kvm_vcpu *vcpu) 4338 { 4339 struct vcpu_vmx *vmx = to_vmx(vcpu); 4340 uint32_t intr; 4341 int irq = vcpu->arch.interrupt.nr; 4342 4343 trace_kvm_inj_virq(irq); 4344 4345 ++vcpu->stat.irq_injections; 4346 if (vmx->rmode.vm86_active) { 4347 int inc_eip = 0; 4348 if (vcpu->arch.interrupt.soft) 4349 inc_eip = vcpu->arch.event_exit_inst_len; 4350 kvm_inject_realmode_interrupt(vcpu, irq, inc_eip); 4351 return; 4352 } 4353 intr = irq | INTR_INFO_VALID_MASK; 4354 if (vcpu->arch.interrupt.soft) { 4355 intr |= INTR_TYPE_SOFT_INTR; 4356 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 4357 vmx->vcpu.arch.event_exit_inst_len); 4358 } else 4359 intr |= INTR_TYPE_EXT_INTR; 4360 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr); 4361 4362 vmx_clear_hlt(vcpu); 4363 } 4364 4365 static void vmx_inject_nmi(struct kvm_vcpu *vcpu) 4366 { 4367 struct vcpu_vmx *vmx = to_vmx(vcpu); 4368 4369 if (!enable_vnmi) { 4370 /* 4371 * Tracking the NMI-blocked state in software is built upon 4372 * finding the next open IRQ window. This, in turn, depends on 4373 * well-behaving guests: They have to keep IRQs disabled at 4374 * least as long as the NMI handler runs. Otherwise we may 4375 * cause NMI nesting, maybe breaking the guest. But as this is 4376 * highly unlikely, we can live with the residual risk. 4377 */ 4378 vmx->loaded_vmcs->soft_vnmi_blocked = 1; 4379 vmx->loaded_vmcs->vnmi_blocked_time = 0; 4380 } 4381 4382 ++vcpu->stat.nmi_injections; 4383 vmx->loaded_vmcs->nmi_known_unmasked = false; 4384 4385 if (vmx->rmode.vm86_active) { 4386 kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0); 4387 return; 4388 } 4389 4390 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 4391 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR); 4392 4393 vmx_clear_hlt(vcpu); 4394 } 4395 4396 bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu) 4397 { 4398 struct vcpu_vmx *vmx = to_vmx(vcpu); 4399 bool masked; 4400 4401 if (!enable_vnmi) 4402 return vmx->loaded_vmcs->soft_vnmi_blocked; 4403 if (vmx->loaded_vmcs->nmi_known_unmasked) 4404 return false; 4405 masked = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI; 4406 vmx->loaded_vmcs->nmi_known_unmasked = !masked; 4407 return masked; 4408 } 4409 4410 void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked) 4411 { 4412 struct vcpu_vmx *vmx = to_vmx(vcpu); 4413 4414 if (!enable_vnmi) { 4415 if (vmx->loaded_vmcs->soft_vnmi_blocked != masked) { 4416 vmx->loaded_vmcs->soft_vnmi_blocked = masked; 4417 vmx->loaded_vmcs->vnmi_blocked_time = 0; 4418 } 4419 } else { 4420 vmx->loaded_vmcs->nmi_known_unmasked = !masked; 4421 if (masked) 4422 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, 4423 GUEST_INTR_STATE_NMI); 4424 else 4425 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO, 4426 GUEST_INTR_STATE_NMI); 4427 } 4428 } 4429 4430 static int vmx_nmi_allowed(struct kvm_vcpu *vcpu) 4431 { 4432 if (to_vmx(vcpu)->nested.nested_run_pending) 4433 return 0; 4434 4435 if (!enable_vnmi && 4436 to_vmx(vcpu)->loaded_vmcs->soft_vnmi_blocked) 4437 return 0; 4438 4439 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & 4440 (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI 4441 | GUEST_INTR_STATE_NMI)); 4442 } 4443 4444 static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu) 4445 { 4446 return (!to_vmx(vcpu)->nested.nested_run_pending && 4447 vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) && 4448 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & 4449 (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS)); 4450 } 4451 4452 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr) 4453 { 4454 int ret; 4455 4456 if (enable_unrestricted_guest) 4457 return 0; 4458 4459 mutex_lock(&kvm->slots_lock); 4460 ret = __x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, addr, 4461 PAGE_SIZE * 3); 4462 mutex_unlock(&kvm->slots_lock); 4463 4464 if (ret) 4465 return ret; 4466 to_kvm_vmx(kvm)->tss_addr = addr; 4467 return init_rmode_tss(kvm); 4468 } 4469 4470 static int vmx_set_identity_map_addr(struct kvm *kvm, u64 ident_addr) 4471 { 4472 to_kvm_vmx(kvm)->ept_identity_map_addr = ident_addr; 4473 return 0; 4474 } 4475 4476 static bool rmode_exception(struct kvm_vcpu *vcpu, int vec) 4477 { 4478 switch (vec) { 4479 case BP_VECTOR: 4480 /* 4481 * Update instruction length as we may reinject the exception 4482 * from user space while in guest debugging mode. 4483 */ 4484 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len = 4485 vmcs_read32(VM_EXIT_INSTRUCTION_LEN); 4486 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP) 4487 return false; 4488 /* fall through */ 4489 case DB_VECTOR: 4490 if (vcpu->guest_debug & 4491 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) 4492 return false; 4493 /* fall through */ 4494 case DE_VECTOR: 4495 case OF_VECTOR: 4496 case BR_VECTOR: 4497 case UD_VECTOR: 4498 case DF_VECTOR: 4499 case SS_VECTOR: 4500 case GP_VECTOR: 4501 case MF_VECTOR: 4502 return true; 4503 break; 4504 } 4505 return false; 4506 } 4507 4508 static int handle_rmode_exception(struct kvm_vcpu *vcpu, 4509 int vec, u32 err_code) 4510 { 4511 /* 4512 * Instruction with address size override prefix opcode 0x67 4513 * Cause the #SS fault with 0 error code in VM86 mode. 4514 */ 4515 if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0) { 4516 if (kvm_emulate_instruction(vcpu, 0)) { 4517 if (vcpu->arch.halt_request) { 4518 vcpu->arch.halt_request = 0; 4519 return kvm_vcpu_halt(vcpu); 4520 } 4521 return 1; 4522 } 4523 return 0; 4524 } 4525 4526 /* 4527 * Forward all other exceptions that are valid in real mode. 4528 * FIXME: Breaks guest debugging in real mode, needs to be fixed with 4529 * the required debugging infrastructure rework. 4530 */ 4531 kvm_queue_exception(vcpu, vec); 4532 return 1; 4533 } 4534 4535 /* 4536 * Trigger machine check on the host. We assume all the MSRs are already set up 4537 * by the CPU and that we still run on the same CPU as the MCE occurred on. 4538 * We pass a fake environment to the machine check handler because we want 4539 * the guest to be always treated like user space, no matter what context 4540 * it used internally. 4541 */ 4542 static void kvm_machine_check(void) 4543 { 4544 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64) 4545 struct pt_regs regs = { 4546 .cs = 3, /* Fake ring 3 no matter what the guest ran on */ 4547 .flags = X86_EFLAGS_IF, 4548 }; 4549 4550 do_machine_check(®s, 0); 4551 #endif 4552 } 4553 4554 static int handle_machine_check(struct kvm_vcpu *vcpu) 4555 { 4556 /* handled by vmx_vcpu_run() */ 4557 return 1; 4558 } 4559 4560 static int handle_exception_nmi(struct kvm_vcpu *vcpu) 4561 { 4562 struct vcpu_vmx *vmx = to_vmx(vcpu); 4563 struct kvm_run *kvm_run = vcpu->run; 4564 u32 intr_info, ex_no, error_code; 4565 unsigned long cr2, rip, dr6; 4566 u32 vect_info; 4567 4568 vect_info = vmx->idt_vectoring_info; 4569 intr_info = vmx->exit_intr_info; 4570 4571 if (is_machine_check(intr_info) || is_nmi(intr_info)) 4572 return 1; /* handled by handle_exception_nmi_irqoff() */ 4573 4574 if (is_invalid_opcode(intr_info)) 4575 return handle_ud(vcpu); 4576 4577 error_code = 0; 4578 if (intr_info & INTR_INFO_DELIVER_CODE_MASK) 4579 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE); 4580 4581 if (!vmx->rmode.vm86_active && is_gp_fault(intr_info)) { 4582 WARN_ON_ONCE(!enable_vmware_backdoor); 4583 4584 /* 4585 * VMware backdoor emulation on #GP interception only handles 4586 * IN{S}, OUT{S}, and RDPMC, none of which generate a non-zero 4587 * error code on #GP. 4588 */ 4589 if (error_code) { 4590 kvm_queue_exception_e(vcpu, GP_VECTOR, error_code); 4591 return 1; 4592 } 4593 return kvm_emulate_instruction(vcpu, EMULTYPE_VMWARE_GP); 4594 } 4595 4596 /* 4597 * The #PF with PFEC.RSVD = 1 indicates the guest is accessing 4598 * MMIO, it is better to report an internal error. 4599 * See the comments in vmx_handle_exit. 4600 */ 4601 if ((vect_info & VECTORING_INFO_VALID_MASK) && 4602 !(is_page_fault(intr_info) && !(error_code & PFERR_RSVD_MASK))) { 4603 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR; 4604 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX; 4605 vcpu->run->internal.ndata = 3; 4606 vcpu->run->internal.data[0] = vect_info; 4607 vcpu->run->internal.data[1] = intr_info; 4608 vcpu->run->internal.data[2] = error_code; 4609 return 0; 4610 } 4611 4612 if (is_page_fault(intr_info)) { 4613 cr2 = vmcs_readl(EXIT_QUALIFICATION); 4614 /* EPT won't cause page fault directly */ 4615 WARN_ON_ONCE(!vcpu->arch.apf.host_apf_reason && enable_ept); 4616 return kvm_handle_page_fault(vcpu, error_code, cr2, NULL, 0); 4617 } 4618 4619 ex_no = intr_info & INTR_INFO_VECTOR_MASK; 4620 4621 if (vmx->rmode.vm86_active && rmode_exception(vcpu, ex_no)) 4622 return handle_rmode_exception(vcpu, ex_no, error_code); 4623 4624 switch (ex_no) { 4625 case AC_VECTOR: 4626 kvm_queue_exception_e(vcpu, AC_VECTOR, error_code); 4627 return 1; 4628 case DB_VECTOR: 4629 dr6 = vmcs_readl(EXIT_QUALIFICATION); 4630 if (!(vcpu->guest_debug & 4631 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) { 4632 vcpu->arch.dr6 &= ~DR_TRAP_BITS; 4633 vcpu->arch.dr6 |= dr6 | DR6_RTM; 4634 if (is_icebp(intr_info)) 4635 WARN_ON(!skip_emulated_instruction(vcpu)); 4636 4637 kvm_queue_exception(vcpu, DB_VECTOR); 4638 return 1; 4639 } 4640 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1; 4641 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7); 4642 /* fall through */ 4643 case BP_VECTOR: 4644 /* 4645 * Update instruction length as we may reinject #BP from 4646 * user space while in guest debugging mode. Reading it for 4647 * #DB as well causes no harm, it is not used in that case. 4648 */ 4649 vmx->vcpu.arch.event_exit_inst_len = 4650 vmcs_read32(VM_EXIT_INSTRUCTION_LEN); 4651 kvm_run->exit_reason = KVM_EXIT_DEBUG; 4652 rip = kvm_rip_read(vcpu); 4653 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip; 4654 kvm_run->debug.arch.exception = ex_no; 4655 break; 4656 default: 4657 kvm_run->exit_reason = KVM_EXIT_EXCEPTION; 4658 kvm_run->ex.exception = ex_no; 4659 kvm_run->ex.error_code = error_code; 4660 break; 4661 } 4662 return 0; 4663 } 4664 4665 static __always_inline int handle_external_interrupt(struct kvm_vcpu *vcpu) 4666 { 4667 ++vcpu->stat.irq_exits; 4668 return 1; 4669 } 4670 4671 static int handle_triple_fault(struct kvm_vcpu *vcpu) 4672 { 4673 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN; 4674 vcpu->mmio_needed = 0; 4675 return 0; 4676 } 4677 4678 static int handle_io(struct kvm_vcpu *vcpu) 4679 { 4680 unsigned long exit_qualification; 4681 int size, in, string; 4682 unsigned port; 4683 4684 exit_qualification = vmcs_readl(EXIT_QUALIFICATION); 4685 string = (exit_qualification & 16) != 0; 4686 4687 ++vcpu->stat.io_exits; 4688 4689 if (string) 4690 return kvm_emulate_instruction(vcpu, 0); 4691 4692 port = exit_qualification >> 16; 4693 size = (exit_qualification & 7) + 1; 4694 in = (exit_qualification & 8) != 0; 4695 4696 return kvm_fast_pio(vcpu, size, port, in); 4697 } 4698 4699 static void 4700 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall) 4701 { 4702 /* 4703 * Patch in the VMCALL instruction: 4704 */ 4705 hypercall[0] = 0x0f; 4706 hypercall[1] = 0x01; 4707 hypercall[2] = 0xc1; 4708 } 4709 4710 /* called to set cr0 as appropriate for a mov-to-cr0 exit. */ 4711 static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val) 4712 { 4713 if (is_guest_mode(vcpu)) { 4714 struct vmcs12 *vmcs12 = get_vmcs12(vcpu); 4715 unsigned long orig_val = val; 4716 4717 /* 4718 * We get here when L2 changed cr0 in a way that did not change 4719 * any of L1's shadowed bits (see nested_vmx_exit_handled_cr), 4720 * but did change L0 shadowed bits. So we first calculate the 4721 * effective cr0 value that L1 would like to write into the 4722 * hardware. It consists of the L2-owned bits from the new 4723 * value combined with the L1-owned bits from L1's guest_cr0. 4724 */ 4725 val = (val & ~vmcs12->cr0_guest_host_mask) | 4726 (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask); 4727 4728 if (!nested_guest_cr0_valid(vcpu, val)) 4729 return 1; 4730 4731 if (kvm_set_cr0(vcpu, val)) 4732 return 1; 4733 vmcs_writel(CR0_READ_SHADOW, orig_val); 4734 return 0; 4735 } else { 4736 if (to_vmx(vcpu)->nested.vmxon && 4737 !nested_host_cr0_valid(vcpu, val)) 4738 return 1; 4739 4740 return kvm_set_cr0(vcpu, val); 4741 } 4742 } 4743 4744 static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val) 4745 { 4746 if (is_guest_mode(vcpu)) { 4747 struct vmcs12 *vmcs12 = get_vmcs12(vcpu); 4748 unsigned long orig_val = val; 4749 4750 /* analogously to handle_set_cr0 */ 4751 val = (val & ~vmcs12->cr4_guest_host_mask) | 4752 (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask); 4753 if (kvm_set_cr4(vcpu, val)) 4754 return 1; 4755 vmcs_writel(CR4_READ_SHADOW, orig_val); 4756 return 0; 4757 } else 4758 return kvm_set_cr4(vcpu, val); 4759 } 4760 4761 static int handle_desc(struct kvm_vcpu *vcpu) 4762 { 4763 WARN_ON(!(vcpu->arch.cr4 & X86_CR4_UMIP)); 4764 return kvm_emulate_instruction(vcpu, 0); 4765 } 4766 4767 static int handle_cr(struct kvm_vcpu *vcpu) 4768 { 4769 unsigned long exit_qualification, val; 4770 int cr; 4771 int reg; 4772 int err; 4773 int ret; 4774 4775 exit_qualification = vmcs_readl(EXIT_QUALIFICATION); 4776 cr = exit_qualification & 15; 4777 reg = (exit_qualification >> 8) & 15; 4778 switch ((exit_qualification >> 4) & 3) { 4779 case 0: /* mov to cr */ 4780 val = kvm_register_readl(vcpu, reg); 4781 trace_kvm_cr_write(cr, val); 4782 switch (cr) { 4783 case 0: 4784 err = handle_set_cr0(vcpu, val); 4785 return kvm_complete_insn_gp(vcpu, err); 4786 case 3: 4787 WARN_ON_ONCE(enable_unrestricted_guest); 4788 err = kvm_set_cr3(vcpu, val); 4789 return kvm_complete_insn_gp(vcpu, err); 4790 case 4: 4791 err = handle_set_cr4(vcpu, val); 4792 return kvm_complete_insn_gp(vcpu, err); 4793 case 8: { 4794 u8 cr8_prev = kvm_get_cr8(vcpu); 4795 u8 cr8 = (u8)val; 4796 err = kvm_set_cr8(vcpu, cr8); 4797 ret = kvm_complete_insn_gp(vcpu, err); 4798 if (lapic_in_kernel(vcpu)) 4799 return ret; 4800 if (cr8_prev <= cr8) 4801 return ret; 4802 /* 4803 * TODO: we might be squashing a 4804 * KVM_GUESTDBG_SINGLESTEP-triggered 4805 * KVM_EXIT_DEBUG here. 4806 */ 4807 vcpu->run->exit_reason = KVM_EXIT_SET_TPR; 4808 return 0; 4809 } 4810 } 4811 break; 4812 case 2: /* clts */ 4813 WARN_ONCE(1, "Guest should always own CR0.TS"); 4814 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS)); 4815 trace_kvm_cr_write(0, kvm_read_cr0(vcpu)); 4816 return kvm_skip_emulated_instruction(vcpu); 4817 case 1: /*mov from cr*/ 4818 switch (cr) { 4819 case 3: 4820 WARN_ON_ONCE(enable_unrestricted_guest); 4821 val = kvm_read_cr3(vcpu); 4822 kvm_register_write(vcpu, reg, val); 4823 trace_kvm_cr_read(cr, val); 4824 return kvm_skip_emulated_instruction(vcpu); 4825 case 8: 4826 val = kvm_get_cr8(vcpu); 4827 kvm_register_write(vcpu, reg, val); 4828 trace_kvm_cr_read(cr, val); 4829 return kvm_skip_emulated_instruction(vcpu); 4830 } 4831 break; 4832 case 3: /* lmsw */ 4833 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f; 4834 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val); 4835 kvm_lmsw(vcpu, val); 4836 4837 return kvm_skip_emulated_instruction(vcpu); 4838 default: 4839 break; 4840 } 4841 vcpu->run->exit_reason = 0; 4842 vcpu_unimpl(vcpu, "unhandled control register: op %d cr %d\n", 4843 (int)(exit_qualification >> 4) & 3, cr); 4844 return 0; 4845 } 4846 4847 static int handle_dr(struct kvm_vcpu *vcpu) 4848 { 4849 unsigned long exit_qualification; 4850 int dr, dr7, reg; 4851 4852 exit_qualification = vmcs_readl(EXIT_QUALIFICATION); 4853 dr = exit_qualification & DEBUG_REG_ACCESS_NUM; 4854 4855 /* First, if DR does not exist, trigger UD */ 4856 if (!kvm_require_dr(vcpu, dr)) 4857 return 1; 4858 4859 /* Do not handle if the CPL > 0, will trigger GP on re-entry */ 4860 if (!kvm_require_cpl(vcpu, 0)) 4861 return 1; 4862 dr7 = vmcs_readl(GUEST_DR7); 4863 if (dr7 & DR7_GD) { 4864 /* 4865 * As the vm-exit takes precedence over the debug trap, we 4866 * need to emulate the latter, either for the host or the 4867 * guest debugging itself. 4868 */ 4869 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) { 4870 vcpu->run->debug.arch.dr6 = vcpu->arch.dr6; 4871 vcpu->run->debug.arch.dr7 = dr7; 4872 vcpu->run->debug.arch.pc = kvm_get_linear_rip(vcpu); 4873 vcpu->run->debug.arch.exception = DB_VECTOR; 4874 vcpu->run->exit_reason = KVM_EXIT_DEBUG; 4875 return 0; 4876 } else { 4877 vcpu->arch.dr6 &= ~DR_TRAP_BITS; 4878 vcpu->arch.dr6 |= DR6_BD | DR6_RTM; 4879 kvm_queue_exception(vcpu, DB_VECTOR); 4880 return 1; 4881 } 4882 } 4883 4884 if (vcpu->guest_debug == 0) { 4885 exec_controls_clearbit(to_vmx(vcpu), CPU_BASED_MOV_DR_EXITING); 4886 4887 /* 4888 * No more DR vmexits; force a reload of the debug registers 4889 * and reenter on this instruction. The next vmexit will 4890 * retrieve the full state of the debug registers. 4891 */ 4892 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT; 4893 return 1; 4894 } 4895 4896 reg = DEBUG_REG_ACCESS_REG(exit_qualification); 4897 if (exit_qualification & TYPE_MOV_FROM_DR) { 4898 unsigned long val; 4899 4900 if (kvm_get_dr(vcpu, dr, &val)) 4901 return 1; 4902 kvm_register_write(vcpu, reg, val); 4903 } else 4904 if (kvm_set_dr(vcpu, dr, kvm_register_readl(vcpu, reg))) 4905 return 1; 4906 4907 return kvm_skip_emulated_instruction(vcpu); 4908 } 4909 4910 static u64 vmx_get_dr6(struct kvm_vcpu *vcpu) 4911 { 4912 return vcpu->arch.dr6; 4913 } 4914 4915 static void vmx_set_dr6(struct kvm_vcpu *vcpu, unsigned long val) 4916 { 4917 } 4918 4919 static void vmx_sync_dirty_debug_regs(struct kvm_vcpu *vcpu) 4920 { 4921 get_debugreg(vcpu->arch.db[0], 0); 4922 get_debugreg(vcpu->arch.db[1], 1); 4923 get_debugreg(vcpu->arch.db[2], 2); 4924 get_debugreg(vcpu->arch.db[3], 3); 4925 get_debugreg(vcpu->arch.dr6, 6); 4926 vcpu->arch.dr7 = vmcs_readl(GUEST_DR7); 4927 4928 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT; 4929 exec_controls_setbit(to_vmx(vcpu), CPU_BASED_MOV_DR_EXITING); 4930 } 4931 4932 static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val) 4933 { 4934 vmcs_writel(GUEST_DR7, val); 4935 } 4936 4937 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu) 4938 { 4939 kvm_apic_update_ppr(vcpu); 4940 return 1; 4941 } 4942 4943 static int handle_interrupt_window(struct kvm_vcpu *vcpu) 4944 { 4945 exec_controls_clearbit(to_vmx(vcpu), CPU_BASED_INTR_WINDOW_EXITING); 4946 4947 kvm_make_request(KVM_REQ_EVENT, vcpu); 4948 4949 ++vcpu->stat.irq_window_exits; 4950 return 1; 4951 } 4952 4953 static int handle_vmcall(struct kvm_vcpu *vcpu) 4954 { 4955 return kvm_emulate_hypercall(vcpu); 4956 } 4957 4958 static int handle_invd(struct kvm_vcpu *vcpu) 4959 { 4960 return kvm_emulate_instruction(vcpu, 0); 4961 } 4962 4963 static int handle_invlpg(struct kvm_vcpu *vcpu) 4964 { 4965 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION); 4966 4967 kvm_mmu_invlpg(vcpu, exit_qualification); 4968 return kvm_skip_emulated_instruction(vcpu); 4969 } 4970 4971 static int handle_rdpmc(struct kvm_vcpu *vcpu) 4972 { 4973 int err; 4974 4975 err = kvm_rdpmc(vcpu); 4976 return kvm_complete_insn_gp(vcpu, err); 4977 } 4978 4979 static int handle_wbinvd(struct kvm_vcpu *vcpu) 4980 { 4981 return kvm_emulate_wbinvd(vcpu); 4982 } 4983 4984 static int handle_xsetbv(struct kvm_vcpu *vcpu) 4985 { 4986 u64 new_bv = kvm_read_edx_eax(vcpu); 4987 u32 index = kvm_rcx_read(vcpu); 4988 4989 if (kvm_set_xcr(vcpu, index, new_bv) == 0) 4990 return kvm_skip_emulated_instruction(vcpu); 4991 return 1; 4992 } 4993 4994 static int handle_apic_access(struct kvm_vcpu *vcpu) 4995 { 4996 if (likely(fasteoi)) { 4997 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION); 4998 int access_type, offset; 4999 5000 access_type = exit_qualification & APIC_ACCESS_TYPE; 5001 offset = exit_qualification & APIC_ACCESS_OFFSET; 5002 /* 5003 * Sane guest uses MOV to write EOI, with written value 5004 * not cared. So make a short-circuit here by avoiding 5005 * heavy instruction emulation. 5006 */ 5007 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) && 5008 (offset == APIC_EOI)) { 5009 kvm_lapic_set_eoi(vcpu); 5010 return kvm_skip_emulated_instruction(vcpu); 5011 } 5012 } 5013 return kvm_emulate_instruction(vcpu, 0); 5014 } 5015 5016 static int handle_apic_eoi_induced(struct kvm_vcpu *vcpu) 5017 { 5018 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION); 5019 int vector = exit_qualification & 0xff; 5020 5021 /* EOI-induced VM exit is trap-like and thus no need to adjust IP */ 5022 kvm_apic_set_eoi_accelerated(vcpu, vector); 5023 return 1; 5024 } 5025 5026 static int handle_apic_write(struct kvm_vcpu *vcpu) 5027 { 5028 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION); 5029 u32 offset = exit_qualification & 0xfff; 5030 5031 /* APIC-write VM exit is trap-like and thus no need to adjust IP */ 5032 kvm_apic_write_nodecode(vcpu, offset); 5033 return 1; 5034 } 5035 5036 static int handle_task_switch(struct kvm_vcpu *vcpu) 5037 { 5038 struct vcpu_vmx *vmx = to_vmx(vcpu); 5039 unsigned long exit_qualification; 5040 bool has_error_code = false; 5041 u32 error_code = 0; 5042 u16 tss_selector; 5043 int reason, type, idt_v, idt_index; 5044 5045 idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK); 5046 idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK); 5047 type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK); 5048 5049 exit_qualification = vmcs_readl(EXIT_QUALIFICATION); 5050 5051 reason = (u32)exit_qualification >> 30; 5052 if (reason == TASK_SWITCH_GATE && idt_v) { 5053 switch (type) { 5054 case INTR_TYPE_NMI_INTR: 5055 vcpu->arch.nmi_injected = false; 5056 vmx_set_nmi_mask(vcpu, true); 5057 break; 5058 case INTR_TYPE_EXT_INTR: 5059 case INTR_TYPE_SOFT_INTR: 5060 kvm_clear_interrupt_queue(vcpu); 5061 break; 5062 case INTR_TYPE_HARD_EXCEPTION: 5063 if (vmx->idt_vectoring_info & 5064 VECTORING_INFO_DELIVER_CODE_MASK) { 5065 has_error_code = true; 5066 error_code = 5067 vmcs_read32(IDT_VECTORING_ERROR_CODE); 5068 } 5069 /* fall through */ 5070 case INTR_TYPE_SOFT_EXCEPTION: 5071 kvm_clear_exception_queue(vcpu); 5072 break; 5073 default: 5074 break; 5075 } 5076 } 5077 tss_selector = exit_qualification; 5078 5079 if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION && 5080 type != INTR_TYPE_EXT_INTR && 5081 type != INTR_TYPE_NMI_INTR)) 5082 WARN_ON(!skip_emulated_instruction(vcpu)); 5083 5084 /* 5085 * TODO: What about debug traps on tss switch? 5086 * Are we supposed to inject them and update dr6? 5087 */ 5088 return kvm_task_switch(vcpu, tss_selector, 5089 type == INTR_TYPE_SOFT_INTR ? idt_index : -1, 5090 reason, has_error_code, error_code); 5091 } 5092 5093 static int handle_ept_violation(struct kvm_vcpu *vcpu) 5094 { 5095 unsigned long exit_qualification; 5096 gpa_t gpa; 5097 u64 error_code; 5098 5099 exit_qualification = vmcs_readl(EXIT_QUALIFICATION); 5100 5101 /* 5102 * EPT violation happened while executing iret from NMI, 5103 * "blocked by NMI" bit has to be set before next VM entry. 5104 * There are errata that may cause this bit to not be set: 5105 * AAK134, BY25. 5106 */ 5107 if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) && 5108 enable_vnmi && 5109 (exit_qualification & INTR_INFO_UNBLOCK_NMI)) 5110 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, GUEST_INTR_STATE_NMI); 5111 5112 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS); 5113 trace_kvm_page_fault(gpa, exit_qualification); 5114 5115 /* Is it a read fault? */ 5116 error_code = (exit_qualification & EPT_VIOLATION_ACC_READ) 5117 ? PFERR_USER_MASK : 0; 5118 /* Is it a write fault? */ 5119 error_code |= (exit_qualification & EPT_VIOLATION_ACC_WRITE) 5120 ? PFERR_WRITE_MASK : 0; 5121 /* Is it a fetch fault? */ 5122 error_code |= (exit_qualification & EPT_VIOLATION_ACC_INSTR) 5123 ? PFERR_FETCH_MASK : 0; 5124 /* ept page table entry is present? */ 5125 error_code |= (exit_qualification & 5126 (EPT_VIOLATION_READABLE | EPT_VIOLATION_WRITABLE | 5127 EPT_VIOLATION_EXECUTABLE)) 5128 ? PFERR_PRESENT_MASK : 0; 5129 5130 error_code |= (exit_qualification & 0x100) != 0 ? 5131 PFERR_GUEST_FINAL_MASK : PFERR_GUEST_PAGE_MASK; 5132 5133 vcpu->arch.exit_qualification = exit_qualification; 5134 return kvm_mmu_page_fault(vcpu, gpa, error_code, NULL, 0); 5135 } 5136 5137 static int handle_ept_misconfig(struct kvm_vcpu *vcpu) 5138 { 5139 gpa_t gpa; 5140 5141 /* 5142 * A nested guest cannot optimize MMIO vmexits, because we have an 5143 * nGPA here instead of the required GPA. 5144 */ 5145 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS); 5146 if (!is_guest_mode(vcpu) && 5147 !kvm_io_bus_write(vcpu, KVM_FAST_MMIO_BUS, gpa, 0, NULL)) { 5148 trace_kvm_fast_mmio(gpa); 5149 return kvm_skip_emulated_instruction(vcpu); 5150 } 5151 5152 return kvm_mmu_page_fault(vcpu, gpa, PFERR_RSVD_MASK, NULL, 0); 5153 } 5154 5155 static int handle_nmi_window(struct kvm_vcpu *vcpu) 5156 { 5157 WARN_ON_ONCE(!enable_vnmi); 5158 exec_controls_clearbit(to_vmx(vcpu), CPU_BASED_NMI_WINDOW_EXITING); 5159 ++vcpu->stat.nmi_window_exits; 5160 kvm_make_request(KVM_REQ_EVENT, vcpu); 5161 5162 return 1; 5163 } 5164 5165 static int handle_invalid_guest_state(struct kvm_vcpu *vcpu) 5166 { 5167 struct vcpu_vmx *vmx = to_vmx(vcpu); 5168 bool intr_window_requested; 5169 unsigned count = 130; 5170 5171 /* 5172 * We should never reach the point where we are emulating L2 5173 * due to invalid guest state as that means we incorrectly 5174 * allowed a nested VMEntry with an invalid vmcs12. 5175 */ 5176 WARN_ON_ONCE(vmx->emulation_required && vmx->nested.nested_run_pending); 5177 5178 intr_window_requested = exec_controls_get(vmx) & 5179 CPU_BASED_INTR_WINDOW_EXITING; 5180 5181 while (vmx->emulation_required && count-- != 0) { 5182 if (intr_window_requested && vmx_interrupt_allowed(vcpu)) 5183 return handle_interrupt_window(&vmx->vcpu); 5184 5185 if (kvm_test_request(KVM_REQ_EVENT, vcpu)) 5186 return 1; 5187 5188 if (!kvm_emulate_instruction(vcpu, 0)) 5189 return 0; 5190 5191 if (vmx->emulation_required && !vmx->rmode.vm86_active && 5192 vcpu->arch.exception.pending) { 5193 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR; 5194 vcpu->run->internal.suberror = 5195 KVM_INTERNAL_ERROR_EMULATION; 5196 vcpu->run->internal.ndata = 0; 5197 return 0; 5198 } 5199 5200 if (vcpu->arch.halt_request) { 5201 vcpu->arch.halt_request = 0; 5202 return kvm_vcpu_halt(vcpu); 5203 } 5204 5205 /* 5206 * Note, return 1 and not 0, vcpu_run() is responsible for 5207 * morphing the pending signal into the proper return code. 5208 */ 5209 if (signal_pending(current)) 5210 return 1; 5211 5212 if (need_resched()) 5213 schedule(); 5214 } 5215 5216 return 1; 5217 } 5218 5219 static void grow_ple_window(struct kvm_vcpu *vcpu) 5220 { 5221 struct vcpu_vmx *vmx = to_vmx(vcpu); 5222 unsigned int old = vmx->ple_window; 5223 5224 vmx->ple_window = __grow_ple_window(old, ple_window, 5225 ple_window_grow, 5226 ple_window_max); 5227 5228 if (vmx->ple_window != old) { 5229 vmx->ple_window_dirty = true; 5230 trace_kvm_ple_window_update(vcpu->vcpu_id, 5231 vmx->ple_window, old); 5232 } 5233 } 5234 5235 static void shrink_ple_window(struct kvm_vcpu *vcpu) 5236 { 5237 struct vcpu_vmx *vmx = to_vmx(vcpu); 5238 unsigned int old = vmx->ple_window; 5239 5240 vmx->ple_window = __shrink_ple_window(old, ple_window, 5241 ple_window_shrink, 5242 ple_window); 5243 5244 if (vmx->ple_window != old) { 5245 vmx->ple_window_dirty = true; 5246 trace_kvm_ple_window_update(vcpu->vcpu_id, 5247 vmx->ple_window, old); 5248 } 5249 } 5250 5251 /* 5252 * Handler for POSTED_INTERRUPT_WAKEUP_VECTOR. 5253 */ 5254 static void wakeup_handler(void) 5255 { 5256 struct kvm_vcpu *vcpu; 5257 int cpu = smp_processor_id(); 5258 5259 spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu)); 5260 list_for_each_entry(vcpu, &per_cpu(blocked_vcpu_on_cpu, cpu), 5261 blocked_vcpu_list) { 5262 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu); 5263 5264 if (pi_test_on(pi_desc) == 1) 5265 kvm_vcpu_kick(vcpu); 5266 } 5267 spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu)); 5268 } 5269 5270 static void vmx_enable_tdp(void) 5271 { 5272 kvm_mmu_set_mask_ptes(VMX_EPT_READABLE_MASK, 5273 enable_ept_ad_bits ? VMX_EPT_ACCESS_BIT : 0ull, 5274 enable_ept_ad_bits ? VMX_EPT_DIRTY_BIT : 0ull, 5275 0ull, VMX_EPT_EXECUTABLE_MASK, 5276 cpu_has_vmx_ept_execute_only() ? 0ull : VMX_EPT_READABLE_MASK, 5277 VMX_EPT_RWX_MASK, 0ull); 5278 5279 ept_set_mmio_spte_mask(); 5280 kvm_enable_tdp(); 5281 } 5282 5283 /* 5284 * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE 5285 * exiting, so only get here on cpu with PAUSE-Loop-Exiting. 5286 */ 5287 static int handle_pause(struct kvm_vcpu *vcpu) 5288 { 5289 if (!kvm_pause_in_guest(vcpu->kvm)) 5290 grow_ple_window(vcpu); 5291 5292 /* 5293 * Intel sdm vol3 ch-25.1.3 says: The "PAUSE-loop exiting" 5294 * VM-execution control is ignored if CPL > 0. OTOH, KVM 5295 * never set PAUSE_EXITING and just set PLE if supported, 5296 * so the vcpu must be CPL=0 if it gets a PAUSE exit. 5297 */ 5298 kvm_vcpu_on_spin(vcpu, true); 5299 return kvm_skip_emulated_instruction(vcpu); 5300 } 5301 5302 static int handle_nop(struct kvm_vcpu *vcpu) 5303 { 5304 return kvm_skip_emulated_instruction(vcpu); 5305 } 5306 5307 static int handle_mwait(struct kvm_vcpu *vcpu) 5308 { 5309 printk_once(KERN_WARNING "kvm: MWAIT instruction emulated as NOP!\n"); 5310 return handle_nop(vcpu); 5311 } 5312 5313 static int handle_invalid_op(struct kvm_vcpu *vcpu) 5314 { 5315 kvm_queue_exception(vcpu, UD_VECTOR); 5316 return 1; 5317 } 5318 5319 static int handle_monitor_trap(struct kvm_vcpu *vcpu) 5320 { 5321 return 1; 5322 } 5323 5324 static int handle_monitor(struct kvm_vcpu *vcpu) 5325 { 5326 printk_once(KERN_WARNING "kvm: MONITOR instruction emulated as NOP!\n"); 5327 return handle_nop(vcpu); 5328 } 5329 5330 static int handle_invpcid(struct kvm_vcpu *vcpu) 5331 { 5332 u32 vmx_instruction_info; 5333 unsigned long type; 5334 bool pcid_enabled; 5335 gva_t gva; 5336 struct x86_exception e; 5337 unsigned i; 5338 unsigned long roots_to_free = 0; 5339 struct { 5340 u64 pcid; 5341 u64 gla; 5342 } operand; 5343 5344 if (!guest_cpuid_has(vcpu, X86_FEATURE_INVPCID)) { 5345 kvm_queue_exception(vcpu, UD_VECTOR); 5346 return 1; 5347 } 5348 5349 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO); 5350 type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf); 5351 5352 if (type > 3) { 5353 kvm_inject_gp(vcpu, 0); 5354 return 1; 5355 } 5356 5357 /* According to the Intel instruction reference, the memory operand 5358 * is read even if it isn't needed (e.g., for type==all) 5359 */ 5360 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION), 5361 vmx_instruction_info, false, 5362 sizeof(operand), &gva)) 5363 return 1; 5364 5365 if (kvm_read_guest_virt(vcpu, gva, &operand, sizeof(operand), &e)) { 5366 kvm_inject_page_fault(vcpu, &e); 5367 return 1; 5368 } 5369 5370 if (operand.pcid >> 12 != 0) { 5371 kvm_inject_gp(vcpu, 0); 5372 return 1; 5373 } 5374 5375 pcid_enabled = kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE); 5376 5377 switch (type) { 5378 case INVPCID_TYPE_INDIV_ADDR: 5379 if ((!pcid_enabled && (operand.pcid != 0)) || 5380 is_noncanonical_address(operand.gla, vcpu)) { 5381 kvm_inject_gp(vcpu, 0); 5382 return 1; 5383 } 5384 kvm_mmu_invpcid_gva(vcpu, operand.gla, operand.pcid); 5385 return kvm_skip_emulated_instruction(vcpu); 5386 5387 case INVPCID_TYPE_SINGLE_CTXT: 5388 if (!pcid_enabled && (operand.pcid != 0)) { 5389 kvm_inject_gp(vcpu, 0); 5390 return 1; 5391 } 5392 5393 if (kvm_get_active_pcid(vcpu) == operand.pcid) { 5394 kvm_mmu_sync_roots(vcpu); 5395 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu); 5396 } 5397 5398 for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++) 5399 if (kvm_get_pcid(vcpu, vcpu->arch.mmu->prev_roots[i].cr3) 5400 == operand.pcid) 5401 roots_to_free |= KVM_MMU_ROOT_PREVIOUS(i); 5402 5403 kvm_mmu_free_roots(vcpu, vcpu->arch.mmu, roots_to_free); 5404 /* 5405 * If neither the current cr3 nor any of the prev_roots use the 5406 * given PCID, then nothing needs to be done here because a 5407 * resync will happen anyway before switching to any other CR3. 5408 */ 5409 5410 return kvm_skip_emulated_instruction(vcpu); 5411 5412 case INVPCID_TYPE_ALL_NON_GLOBAL: 5413 /* 5414 * Currently, KVM doesn't mark global entries in the shadow 5415 * page tables, so a non-global flush just degenerates to a 5416 * global flush. If needed, we could optimize this later by 5417 * keeping track of global entries in shadow page tables. 5418 */ 5419 5420 /* fall-through */ 5421 case INVPCID_TYPE_ALL_INCL_GLOBAL: 5422 kvm_mmu_unload(vcpu); 5423 return kvm_skip_emulated_instruction(vcpu); 5424 5425 default: 5426 BUG(); /* We have already checked above that type <= 3 */ 5427 } 5428 } 5429 5430 static int handle_pml_full(struct kvm_vcpu *vcpu) 5431 { 5432 unsigned long exit_qualification; 5433 5434 trace_kvm_pml_full(vcpu->vcpu_id); 5435 5436 exit_qualification = vmcs_readl(EXIT_QUALIFICATION); 5437 5438 /* 5439 * PML buffer FULL happened while executing iret from NMI, 5440 * "blocked by NMI" bit has to be set before next VM entry. 5441 */ 5442 if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) && 5443 enable_vnmi && 5444 (exit_qualification & INTR_INFO_UNBLOCK_NMI)) 5445 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, 5446 GUEST_INTR_STATE_NMI); 5447 5448 /* 5449 * PML buffer already flushed at beginning of VMEXIT. Nothing to do 5450 * here.., and there's no userspace involvement needed for PML. 5451 */ 5452 return 1; 5453 } 5454 5455 static int handle_preemption_timer(struct kvm_vcpu *vcpu) 5456 { 5457 struct vcpu_vmx *vmx = to_vmx(vcpu); 5458 5459 if (!vmx->req_immediate_exit && 5460 !unlikely(vmx->loaded_vmcs->hv_timer_soft_disabled)) 5461 kvm_lapic_expired_hv_timer(vcpu); 5462 5463 return 1; 5464 } 5465 5466 /* 5467 * When nested=0, all VMX instruction VM Exits filter here. The handlers 5468 * are overwritten by nested_vmx_setup() when nested=1. 5469 */ 5470 static int handle_vmx_instruction(struct kvm_vcpu *vcpu) 5471 { 5472 kvm_queue_exception(vcpu, UD_VECTOR); 5473 return 1; 5474 } 5475 5476 static int handle_encls(struct kvm_vcpu *vcpu) 5477 { 5478 /* 5479 * SGX virtualization is not yet supported. There is no software 5480 * enable bit for SGX, so we have to trap ENCLS and inject a #UD 5481 * to prevent the guest from executing ENCLS. 5482 */ 5483 kvm_queue_exception(vcpu, UD_VECTOR); 5484 return 1; 5485 } 5486 5487 /* 5488 * The exit handlers return 1 if the exit was handled fully and guest execution 5489 * may resume. Otherwise they set the kvm_run parameter to indicate what needs 5490 * to be done to userspace and return 0. 5491 */ 5492 static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = { 5493 [EXIT_REASON_EXCEPTION_NMI] = handle_exception_nmi, 5494 [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt, 5495 [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault, 5496 [EXIT_REASON_NMI_WINDOW] = handle_nmi_window, 5497 [EXIT_REASON_IO_INSTRUCTION] = handle_io, 5498 [EXIT_REASON_CR_ACCESS] = handle_cr, 5499 [EXIT_REASON_DR_ACCESS] = handle_dr, 5500 [EXIT_REASON_CPUID] = kvm_emulate_cpuid, 5501 [EXIT_REASON_MSR_READ] = kvm_emulate_rdmsr, 5502 [EXIT_REASON_MSR_WRITE] = kvm_emulate_wrmsr, 5503 [EXIT_REASON_INTERRUPT_WINDOW] = handle_interrupt_window, 5504 [EXIT_REASON_HLT] = kvm_emulate_halt, 5505 [EXIT_REASON_INVD] = handle_invd, 5506 [EXIT_REASON_INVLPG] = handle_invlpg, 5507 [EXIT_REASON_RDPMC] = handle_rdpmc, 5508 [EXIT_REASON_VMCALL] = handle_vmcall, 5509 [EXIT_REASON_VMCLEAR] = handle_vmx_instruction, 5510 [EXIT_REASON_VMLAUNCH] = handle_vmx_instruction, 5511 [EXIT_REASON_VMPTRLD] = handle_vmx_instruction, 5512 [EXIT_REASON_VMPTRST] = handle_vmx_instruction, 5513 [EXIT_REASON_VMREAD] = handle_vmx_instruction, 5514 [EXIT_REASON_VMRESUME] = handle_vmx_instruction, 5515 [EXIT_REASON_VMWRITE] = handle_vmx_instruction, 5516 [EXIT_REASON_VMOFF] = handle_vmx_instruction, 5517 [EXIT_REASON_VMON] = handle_vmx_instruction, 5518 [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold, 5519 [EXIT_REASON_APIC_ACCESS] = handle_apic_access, 5520 [EXIT_REASON_APIC_WRITE] = handle_apic_write, 5521 [EXIT_REASON_EOI_INDUCED] = handle_apic_eoi_induced, 5522 [EXIT_REASON_WBINVD] = handle_wbinvd, 5523 [EXIT_REASON_XSETBV] = handle_xsetbv, 5524 [EXIT_REASON_TASK_SWITCH] = handle_task_switch, 5525 [EXIT_REASON_MCE_DURING_VMENTRY] = handle_machine_check, 5526 [EXIT_REASON_GDTR_IDTR] = handle_desc, 5527 [EXIT_REASON_LDTR_TR] = handle_desc, 5528 [EXIT_REASON_EPT_VIOLATION] = handle_ept_violation, 5529 [EXIT_REASON_EPT_MISCONFIG] = handle_ept_misconfig, 5530 [EXIT_REASON_PAUSE_INSTRUCTION] = handle_pause, 5531 [EXIT_REASON_MWAIT_INSTRUCTION] = handle_mwait, 5532 [EXIT_REASON_MONITOR_TRAP_FLAG] = handle_monitor_trap, 5533 [EXIT_REASON_MONITOR_INSTRUCTION] = handle_monitor, 5534 [EXIT_REASON_INVEPT] = handle_vmx_instruction, 5535 [EXIT_REASON_INVVPID] = handle_vmx_instruction, 5536 [EXIT_REASON_RDRAND] = handle_invalid_op, 5537 [EXIT_REASON_RDSEED] = handle_invalid_op, 5538 [EXIT_REASON_PML_FULL] = handle_pml_full, 5539 [EXIT_REASON_INVPCID] = handle_invpcid, 5540 [EXIT_REASON_VMFUNC] = handle_vmx_instruction, 5541 [EXIT_REASON_PREEMPTION_TIMER] = handle_preemption_timer, 5542 [EXIT_REASON_ENCLS] = handle_encls, 5543 }; 5544 5545 static const int kvm_vmx_max_exit_handlers = 5546 ARRAY_SIZE(kvm_vmx_exit_handlers); 5547 5548 static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2) 5549 { 5550 *info1 = vmcs_readl(EXIT_QUALIFICATION); 5551 *info2 = vmcs_read32(VM_EXIT_INTR_INFO); 5552 } 5553 5554 static void vmx_destroy_pml_buffer(struct vcpu_vmx *vmx) 5555 { 5556 if (vmx->pml_pg) { 5557 __free_page(vmx->pml_pg); 5558 vmx->pml_pg = NULL; 5559 } 5560 } 5561 5562 static void vmx_flush_pml_buffer(struct kvm_vcpu *vcpu) 5563 { 5564 struct vcpu_vmx *vmx = to_vmx(vcpu); 5565 u64 *pml_buf; 5566 u16 pml_idx; 5567 5568 pml_idx = vmcs_read16(GUEST_PML_INDEX); 5569 5570 /* Do nothing if PML buffer is empty */ 5571 if (pml_idx == (PML_ENTITY_NUM - 1)) 5572 return; 5573 5574 /* PML index always points to next available PML buffer entity */ 5575 if (pml_idx >= PML_ENTITY_NUM) 5576 pml_idx = 0; 5577 else 5578 pml_idx++; 5579 5580 pml_buf = page_address(vmx->pml_pg); 5581 for (; pml_idx < PML_ENTITY_NUM; pml_idx++) { 5582 u64 gpa; 5583 5584 gpa = pml_buf[pml_idx]; 5585 WARN_ON(gpa & (PAGE_SIZE - 1)); 5586 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT); 5587 } 5588 5589 /* reset PML index */ 5590 vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1); 5591 } 5592 5593 /* 5594 * Flush all vcpus' PML buffer and update logged GPAs to dirty_bitmap. 5595 * Called before reporting dirty_bitmap to userspace. 5596 */ 5597 static void kvm_flush_pml_buffers(struct kvm *kvm) 5598 { 5599 int i; 5600 struct kvm_vcpu *vcpu; 5601 /* 5602 * We only need to kick vcpu out of guest mode here, as PML buffer 5603 * is flushed at beginning of all VMEXITs, and it's obvious that only 5604 * vcpus running in guest are possible to have unflushed GPAs in PML 5605 * buffer. 5606 */ 5607 kvm_for_each_vcpu(i, vcpu, kvm) 5608 kvm_vcpu_kick(vcpu); 5609 } 5610 5611 static void vmx_dump_sel(char *name, uint32_t sel) 5612 { 5613 pr_err("%s sel=0x%04x, attr=0x%05x, limit=0x%08x, base=0x%016lx\n", 5614 name, vmcs_read16(sel), 5615 vmcs_read32(sel + GUEST_ES_AR_BYTES - GUEST_ES_SELECTOR), 5616 vmcs_read32(sel + GUEST_ES_LIMIT - GUEST_ES_SELECTOR), 5617 vmcs_readl(sel + GUEST_ES_BASE - GUEST_ES_SELECTOR)); 5618 } 5619 5620 static void vmx_dump_dtsel(char *name, uint32_t limit) 5621 { 5622 pr_err("%s limit=0x%08x, base=0x%016lx\n", 5623 name, vmcs_read32(limit), 5624 vmcs_readl(limit + GUEST_GDTR_BASE - GUEST_GDTR_LIMIT)); 5625 } 5626 5627 void dump_vmcs(void) 5628 { 5629 u32 vmentry_ctl, vmexit_ctl; 5630 u32 cpu_based_exec_ctrl, pin_based_exec_ctrl, secondary_exec_control; 5631 unsigned long cr4; 5632 u64 efer; 5633 int i, n; 5634 5635 if (!dump_invalid_vmcs) { 5636 pr_warn_ratelimited("set kvm_intel.dump_invalid_vmcs=1 to dump internal KVM state.\n"); 5637 return; 5638 } 5639 5640 vmentry_ctl = vmcs_read32(VM_ENTRY_CONTROLS); 5641 vmexit_ctl = vmcs_read32(VM_EXIT_CONTROLS); 5642 cpu_based_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL); 5643 pin_based_exec_ctrl = vmcs_read32(PIN_BASED_VM_EXEC_CONTROL); 5644 cr4 = vmcs_readl(GUEST_CR4); 5645 efer = vmcs_read64(GUEST_IA32_EFER); 5646 secondary_exec_control = 0; 5647 if (cpu_has_secondary_exec_ctrls()) 5648 secondary_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL); 5649 5650 pr_err("*** Guest State ***\n"); 5651 pr_err("CR0: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n", 5652 vmcs_readl(GUEST_CR0), vmcs_readl(CR0_READ_SHADOW), 5653 vmcs_readl(CR0_GUEST_HOST_MASK)); 5654 pr_err("CR4: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n", 5655 cr4, vmcs_readl(CR4_READ_SHADOW), vmcs_readl(CR4_GUEST_HOST_MASK)); 5656 pr_err("CR3 = 0x%016lx\n", vmcs_readl(GUEST_CR3)); 5657 if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT) && 5658 (cr4 & X86_CR4_PAE) && !(efer & EFER_LMA)) 5659 { 5660 pr_err("PDPTR0 = 0x%016llx PDPTR1 = 0x%016llx\n", 5661 vmcs_read64(GUEST_PDPTR0), vmcs_read64(GUEST_PDPTR1)); 5662 pr_err("PDPTR2 = 0x%016llx PDPTR3 = 0x%016llx\n", 5663 vmcs_read64(GUEST_PDPTR2), vmcs_read64(GUEST_PDPTR3)); 5664 } 5665 pr_err("RSP = 0x%016lx RIP = 0x%016lx\n", 5666 vmcs_readl(GUEST_RSP), vmcs_readl(GUEST_RIP)); 5667 pr_err("RFLAGS=0x%08lx DR7 = 0x%016lx\n", 5668 vmcs_readl(GUEST_RFLAGS), vmcs_readl(GUEST_DR7)); 5669 pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n", 5670 vmcs_readl(GUEST_SYSENTER_ESP), 5671 vmcs_read32(GUEST_SYSENTER_CS), vmcs_readl(GUEST_SYSENTER_EIP)); 5672 vmx_dump_sel("CS: ", GUEST_CS_SELECTOR); 5673 vmx_dump_sel("DS: ", GUEST_DS_SELECTOR); 5674 vmx_dump_sel("SS: ", GUEST_SS_SELECTOR); 5675 vmx_dump_sel("ES: ", GUEST_ES_SELECTOR); 5676 vmx_dump_sel("FS: ", GUEST_FS_SELECTOR); 5677 vmx_dump_sel("GS: ", GUEST_GS_SELECTOR); 5678 vmx_dump_dtsel("GDTR:", GUEST_GDTR_LIMIT); 5679 vmx_dump_sel("LDTR:", GUEST_LDTR_SELECTOR); 5680 vmx_dump_dtsel("IDTR:", GUEST_IDTR_LIMIT); 5681 vmx_dump_sel("TR: ", GUEST_TR_SELECTOR); 5682 if ((vmexit_ctl & (VM_EXIT_SAVE_IA32_PAT | VM_EXIT_SAVE_IA32_EFER)) || 5683 (vmentry_ctl & (VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_IA32_EFER))) 5684 pr_err("EFER = 0x%016llx PAT = 0x%016llx\n", 5685 efer, vmcs_read64(GUEST_IA32_PAT)); 5686 pr_err("DebugCtl = 0x%016llx DebugExceptions = 0x%016lx\n", 5687 vmcs_read64(GUEST_IA32_DEBUGCTL), 5688 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS)); 5689 if (cpu_has_load_perf_global_ctrl() && 5690 vmentry_ctl & VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL) 5691 pr_err("PerfGlobCtl = 0x%016llx\n", 5692 vmcs_read64(GUEST_IA32_PERF_GLOBAL_CTRL)); 5693 if (vmentry_ctl & VM_ENTRY_LOAD_BNDCFGS) 5694 pr_err("BndCfgS = 0x%016llx\n", vmcs_read64(GUEST_BNDCFGS)); 5695 pr_err("Interruptibility = %08x ActivityState = %08x\n", 5696 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO), 5697 vmcs_read32(GUEST_ACTIVITY_STATE)); 5698 if (secondary_exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) 5699 pr_err("InterruptStatus = %04x\n", 5700 vmcs_read16(GUEST_INTR_STATUS)); 5701 5702 pr_err("*** Host State ***\n"); 5703 pr_err("RIP = 0x%016lx RSP = 0x%016lx\n", 5704 vmcs_readl(HOST_RIP), vmcs_readl(HOST_RSP)); 5705 pr_err("CS=%04x SS=%04x DS=%04x ES=%04x FS=%04x GS=%04x TR=%04x\n", 5706 vmcs_read16(HOST_CS_SELECTOR), vmcs_read16(HOST_SS_SELECTOR), 5707 vmcs_read16(HOST_DS_SELECTOR), vmcs_read16(HOST_ES_SELECTOR), 5708 vmcs_read16(HOST_FS_SELECTOR), vmcs_read16(HOST_GS_SELECTOR), 5709 vmcs_read16(HOST_TR_SELECTOR)); 5710 pr_err("FSBase=%016lx GSBase=%016lx TRBase=%016lx\n", 5711 vmcs_readl(HOST_FS_BASE), vmcs_readl(HOST_GS_BASE), 5712 vmcs_readl(HOST_TR_BASE)); 5713 pr_err("GDTBase=%016lx IDTBase=%016lx\n", 5714 vmcs_readl(HOST_GDTR_BASE), vmcs_readl(HOST_IDTR_BASE)); 5715 pr_err("CR0=%016lx CR3=%016lx CR4=%016lx\n", 5716 vmcs_readl(HOST_CR0), vmcs_readl(HOST_CR3), 5717 vmcs_readl(HOST_CR4)); 5718 pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n", 5719 vmcs_readl(HOST_IA32_SYSENTER_ESP), 5720 vmcs_read32(HOST_IA32_SYSENTER_CS), 5721 vmcs_readl(HOST_IA32_SYSENTER_EIP)); 5722 if (vmexit_ctl & (VM_EXIT_LOAD_IA32_PAT | VM_EXIT_LOAD_IA32_EFER)) 5723 pr_err("EFER = 0x%016llx PAT = 0x%016llx\n", 5724 vmcs_read64(HOST_IA32_EFER), 5725 vmcs_read64(HOST_IA32_PAT)); 5726 if (cpu_has_load_perf_global_ctrl() && 5727 vmexit_ctl & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL) 5728 pr_err("PerfGlobCtl = 0x%016llx\n", 5729 vmcs_read64(HOST_IA32_PERF_GLOBAL_CTRL)); 5730 5731 pr_err("*** Control State ***\n"); 5732 pr_err("PinBased=%08x CPUBased=%08x SecondaryExec=%08x\n", 5733 pin_based_exec_ctrl, cpu_based_exec_ctrl, secondary_exec_control); 5734 pr_err("EntryControls=%08x ExitControls=%08x\n", vmentry_ctl, vmexit_ctl); 5735 pr_err("ExceptionBitmap=%08x PFECmask=%08x PFECmatch=%08x\n", 5736 vmcs_read32(EXCEPTION_BITMAP), 5737 vmcs_read32(PAGE_FAULT_ERROR_CODE_MASK), 5738 vmcs_read32(PAGE_FAULT_ERROR_CODE_MATCH)); 5739 pr_err("VMEntry: intr_info=%08x errcode=%08x ilen=%08x\n", 5740 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD), 5741 vmcs_read32(VM_ENTRY_EXCEPTION_ERROR_CODE), 5742 vmcs_read32(VM_ENTRY_INSTRUCTION_LEN)); 5743 pr_err("VMExit: intr_info=%08x errcode=%08x ilen=%08x\n", 5744 vmcs_read32(VM_EXIT_INTR_INFO), 5745 vmcs_read32(VM_EXIT_INTR_ERROR_CODE), 5746 vmcs_read32(VM_EXIT_INSTRUCTION_LEN)); 5747 pr_err(" reason=%08x qualification=%016lx\n", 5748 vmcs_read32(VM_EXIT_REASON), vmcs_readl(EXIT_QUALIFICATION)); 5749 pr_err("IDTVectoring: info=%08x errcode=%08x\n", 5750 vmcs_read32(IDT_VECTORING_INFO_FIELD), 5751 vmcs_read32(IDT_VECTORING_ERROR_CODE)); 5752 pr_err("TSC Offset = 0x%016llx\n", vmcs_read64(TSC_OFFSET)); 5753 if (secondary_exec_control & SECONDARY_EXEC_TSC_SCALING) 5754 pr_err("TSC Multiplier = 0x%016llx\n", 5755 vmcs_read64(TSC_MULTIPLIER)); 5756 if (cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW) { 5757 if (secondary_exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) { 5758 u16 status = vmcs_read16(GUEST_INTR_STATUS); 5759 pr_err("SVI|RVI = %02x|%02x ", status >> 8, status & 0xff); 5760 } 5761 pr_cont("TPR Threshold = 0x%02x\n", vmcs_read32(TPR_THRESHOLD)); 5762 if (secondary_exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) 5763 pr_err("APIC-access addr = 0x%016llx ", vmcs_read64(APIC_ACCESS_ADDR)); 5764 pr_cont("virt-APIC addr = 0x%016llx\n", vmcs_read64(VIRTUAL_APIC_PAGE_ADDR)); 5765 } 5766 if (pin_based_exec_ctrl & PIN_BASED_POSTED_INTR) 5767 pr_err("PostedIntrVec = 0x%02x\n", vmcs_read16(POSTED_INTR_NV)); 5768 if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT)) 5769 pr_err("EPT pointer = 0x%016llx\n", vmcs_read64(EPT_POINTER)); 5770 n = vmcs_read32(CR3_TARGET_COUNT); 5771 for (i = 0; i + 1 < n; i += 4) 5772 pr_err("CR3 target%u=%016lx target%u=%016lx\n", 5773 i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2), 5774 i + 1, vmcs_readl(CR3_TARGET_VALUE0 + i * 2 + 2)); 5775 if (i < n) 5776 pr_err("CR3 target%u=%016lx\n", 5777 i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2)); 5778 if (secondary_exec_control & SECONDARY_EXEC_PAUSE_LOOP_EXITING) 5779 pr_err("PLE Gap=%08x Window=%08x\n", 5780 vmcs_read32(PLE_GAP), vmcs_read32(PLE_WINDOW)); 5781 if (secondary_exec_control & SECONDARY_EXEC_ENABLE_VPID) 5782 pr_err("Virtual processor ID = 0x%04x\n", 5783 vmcs_read16(VIRTUAL_PROCESSOR_ID)); 5784 } 5785 5786 /* 5787 * The guest has exited. See if we can fix it or if we need userspace 5788 * assistance. 5789 */ 5790 static int vmx_handle_exit(struct kvm_vcpu *vcpu, 5791 enum exit_fastpath_completion exit_fastpath) 5792 { 5793 struct vcpu_vmx *vmx = to_vmx(vcpu); 5794 u32 exit_reason = vmx->exit_reason; 5795 u32 vectoring_info = vmx->idt_vectoring_info; 5796 5797 trace_kvm_exit(exit_reason, vcpu, KVM_ISA_VMX); 5798 5799 /* 5800 * Flush logged GPAs PML buffer, this will make dirty_bitmap more 5801 * updated. Another good is, in kvm_vm_ioctl_get_dirty_log, before 5802 * querying dirty_bitmap, we only need to kick all vcpus out of guest 5803 * mode as if vcpus is in root mode, the PML buffer must has been 5804 * flushed already. 5805 */ 5806 if (enable_pml) 5807 vmx_flush_pml_buffer(vcpu); 5808 5809 /* If guest state is invalid, start emulating */ 5810 if (vmx->emulation_required) 5811 return handle_invalid_guest_state(vcpu); 5812 5813 if (is_guest_mode(vcpu) && nested_vmx_exit_reflected(vcpu, exit_reason)) 5814 return nested_vmx_reflect_vmexit(vcpu, exit_reason); 5815 5816 if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) { 5817 dump_vmcs(); 5818 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY; 5819 vcpu->run->fail_entry.hardware_entry_failure_reason 5820 = exit_reason; 5821 return 0; 5822 } 5823 5824 if (unlikely(vmx->fail)) { 5825 dump_vmcs(); 5826 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY; 5827 vcpu->run->fail_entry.hardware_entry_failure_reason 5828 = vmcs_read32(VM_INSTRUCTION_ERROR); 5829 return 0; 5830 } 5831 5832 /* 5833 * Note: 5834 * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by 5835 * delivery event since it indicates guest is accessing MMIO. 5836 * The vm-exit can be triggered again after return to guest that 5837 * will cause infinite loop. 5838 */ 5839 if ((vectoring_info & VECTORING_INFO_VALID_MASK) && 5840 (exit_reason != EXIT_REASON_EXCEPTION_NMI && 5841 exit_reason != EXIT_REASON_EPT_VIOLATION && 5842 exit_reason != EXIT_REASON_PML_FULL && 5843 exit_reason != EXIT_REASON_TASK_SWITCH)) { 5844 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR; 5845 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_DELIVERY_EV; 5846 vcpu->run->internal.ndata = 3; 5847 vcpu->run->internal.data[0] = vectoring_info; 5848 vcpu->run->internal.data[1] = exit_reason; 5849 vcpu->run->internal.data[2] = vcpu->arch.exit_qualification; 5850 if (exit_reason == EXIT_REASON_EPT_MISCONFIG) { 5851 vcpu->run->internal.ndata++; 5852 vcpu->run->internal.data[3] = 5853 vmcs_read64(GUEST_PHYSICAL_ADDRESS); 5854 } 5855 return 0; 5856 } 5857 5858 if (unlikely(!enable_vnmi && 5859 vmx->loaded_vmcs->soft_vnmi_blocked)) { 5860 if (vmx_interrupt_allowed(vcpu)) { 5861 vmx->loaded_vmcs->soft_vnmi_blocked = 0; 5862 } else if (vmx->loaded_vmcs->vnmi_blocked_time > 1000000000LL && 5863 vcpu->arch.nmi_pending) { 5864 /* 5865 * This CPU don't support us in finding the end of an 5866 * NMI-blocked window if the guest runs with IRQs 5867 * disabled. So we pull the trigger after 1 s of 5868 * futile waiting, but inform the user about this. 5869 */ 5870 printk(KERN_WARNING "%s: Breaking out of NMI-blocked " 5871 "state on VCPU %d after 1 s timeout\n", 5872 __func__, vcpu->vcpu_id); 5873 vmx->loaded_vmcs->soft_vnmi_blocked = 0; 5874 } 5875 } 5876 5877 if (exit_fastpath == EXIT_FASTPATH_SKIP_EMUL_INS) { 5878 kvm_skip_emulated_instruction(vcpu); 5879 return 1; 5880 } 5881 5882 if (exit_reason >= kvm_vmx_max_exit_handlers) 5883 goto unexpected_vmexit; 5884 #ifdef CONFIG_RETPOLINE 5885 if (exit_reason == EXIT_REASON_MSR_WRITE) 5886 return kvm_emulate_wrmsr(vcpu); 5887 else if (exit_reason == EXIT_REASON_PREEMPTION_TIMER) 5888 return handle_preemption_timer(vcpu); 5889 else if (exit_reason == EXIT_REASON_INTERRUPT_WINDOW) 5890 return handle_interrupt_window(vcpu); 5891 else if (exit_reason == EXIT_REASON_EXTERNAL_INTERRUPT) 5892 return handle_external_interrupt(vcpu); 5893 else if (exit_reason == EXIT_REASON_HLT) 5894 return kvm_emulate_halt(vcpu); 5895 else if (exit_reason == EXIT_REASON_EPT_MISCONFIG) 5896 return handle_ept_misconfig(vcpu); 5897 #endif 5898 5899 exit_reason = array_index_nospec(exit_reason, 5900 kvm_vmx_max_exit_handlers); 5901 if (!kvm_vmx_exit_handlers[exit_reason]) 5902 goto unexpected_vmexit; 5903 5904 return kvm_vmx_exit_handlers[exit_reason](vcpu); 5905 5906 unexpected_vmexit: 5907 vcpu_unimpl(vcpu, "vmx: unexpected exit reason 0x%x\n", exit_reason); 5908 dump_vmcs(); 5909 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR; 5910 vcpu->run->internal.suberror = 5911 KVM_INTERNAL_ERROR_UNEXPECTED_EXIT_REASON; 5912 vcpu->run->internal.ndata = 1; 5913 vcpu->run->internal.data[0] = exit_reason; 5914 return 0; 5915 } 5916 5917 /* 5918 * Software based L1D cache flush which is used when microcode providing 5919 * the cache control MSR is not loaded. 5920 * 5921 * The L1D cache is 32 KiB on Nehalem and later microarchitectures, but to 5922 * flush it is required to read in 64 KiB because the replacement algorithm 5923 * is not exactly LRU. This could be sized at runtime via topology 5924 * information but as all relevant affected CPUs have 32KiB L1D cache size 5925 * there is no point in doing so. 5926 */ 5927 static void vmx_l1d_flush(struct kvm_vcpu *vcpu) 5928 { 5929 int size = PAGE_SIZE << L1D_CACHE_ORDER; 5930 5931 /* 5932 * This code is only executed when the the flush mode is 'cond' or 5933 * 'always' 5934 */ 5935 if (static_branch_likely(&vmx_l1d_flush_cond)) { 5936 bool flush_l1d; 5937 5938 /* 5939 * Clear the per-vcpu flush bit, it gets set again 5940 * either from vcpu_run() or from one of the unsafe 5941 * VMEXIT handlers. 5942 */ 5943 flush_l1d = vcpu->arch.l1tf_flush_l1d; 5944 vcpu->arch.l1tf_flush_l1d = false; 5945 5946 /* 5947 * Clear the per-cpu flush bit, it gets set again from 5948 * the interrupt handlers. 5949 */ 5950 flush_l1d |= kvm_get_cpu_l1tf_flush_l1d(); 5951 kvm_clear_cpu_l1tf_flush_l1d(); 5952 5953 if (!flush_l1d) 5954 return; 5955 } 5956 5957 vcpu->stat.l1d_flush++; 5958 5959 if (static_cpu_has(X86_FEATURE_FLUSH_L1D)) { 5960 wrmsrl(MSR_IA32_FLUSH_CMD, L1D_FLUSH); 5961 return; 5962 } 5963 5964 asm volatile( 5965 /* First ensure the pages are in the TLB */ 5966 "xorl %%eax, %%eax\n" 5967 ".Lpopulate_tlb:\n\t" 5968 "movzbl (%[flush_pages], %%" _ASM_AX "), %%ecx\n\t" 5969 "addl $4096, %%eax\n\t" 5970 "cmpl %%eax, %[size]\n\t" 5971 "jne .Lpopulate_tlb\n\t" 5972 "xorl %%eax, %%eax\n\t" 5973 "cpuid\n\t" 5974 /* Now fill the cache */ 5975 "xorl %%eax, %%eax\n" 5976 ".Lfill_cache:\n" 5977 "movzbl (%[flush_pages], %%" _ASM_AX "), %%ecx\n\t" 5978 "addl $64, %%eax\n\t" 5979 "cmpl %%eax, %[size]\n\t" 5980 "jne .Lfill_cache\n\t" 5981 "lfence\n" 5982 :: [flush_pages] "r" (vmx_l1d_flush_pages), 5983 [size] "r" (size) 5984 : "eax", "ebx", "ecx", "edx"); 5985 } 5986 5987 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr) 5988 { 5989 struct vmcs12 *vmcs12 = get_vmcs12(vcpu); 5990 int tpr_threshold; 5991 5992 if (is_guest_mode(vcpu) && 5993 nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW)) 5994 return; 5995 5996 tpr_threshold = (irr == -1 || tpr < irr) ? 0 : irr; 5997 if (is_guest_mode(vcpu)) 5998 to_vmx(vcpu)->nested.l1_tpr_threshold = tpr_threshold; 5999 else 6000 vmcs_write32(TPR_THRESHOLD, tpr_threshold); 6001 } 6002 6003 void vmx_set_virtual_apic_mode(struct kvm_vcpu *vcpu) 6004 { 6005 struct vcpu_vmx *vmx = to_vmx(vcpu); 6006 u32 sec_exec_control; 6007 6008 if (!lapic_in_kernel(vcpu)) 6009 return; 6010 6011 if (!flexpriority_enabled && 6012 !cpu_has_vmx_virtualize_x2apic_mode()) 6013 return; 6014 6015 /* Postpone execution until vmcs01 is the current VMCS. */ 6016 if (is_guest_mode(vcpu)) { 6017 vmx->nested.change_vmcs01_virtual_apic_mode = true; 6018 return; 6019 } 6020 6021 sec_exec_control = secondary_exec_controls_get(vmx); 6022 sec_exec_control &= ~(SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 6023 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE); 6024 6025 switch (kvm_get_apic_mode(vcpu)) { 6026 case LAPIC_MODE_INVALID: 6027 WARN_ONCE(true, "Invalid local APIC state"); 6028 case LAPIC_MODE_DISABLED: 6029 break; 6030 case LAPIC_MODE_XAPIC: 6031 if (flexpriority_enabled) { 6032 sec_exec_control |= 6033 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES; 6034 vmx_flush_tlb(vcpu, true); 6035 } 6036 break; 6037 case LAPIC_MODE_X2APIC: 6038 if (cpu_has_vmx_virtualize_x2apic_mode()) 6039 sec_exec_control |= 6040 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE; 6041 break; 6042 } 6043 secondary_exec_controls_set(vmx, sec_exec_control); 6044 6045 vmx_update_msr_bitmap(vcpu); 6046 } 6047 6048 static void vmx_set_apic_access_page_addr(struct kvm_vcpu *vcpu, hpa_t hpa) 6049 { 6050 if (!is_guest_mode(vcpu)) { 6051 vmcs_write64(APIC_ACCESS_ADDR, hpa); 6052 vmx_flush_tlb(vcpu, true); 6053 } 6054 } 6055 6056 static void vmx_hwapic_isr_update(struct kvm_vcpu *vcpu, int max_isr) 6057 { 6058 u16 status; 6059 u8 old; 6060 6061 if (max_isr == -1) 6062 max_isr = 0; 6063 6064 status = vmcs_read16(GUEST_INTR_STATUS); 6065 old = status >> 8; 6066 if (max_isr != old) { 6067 status &= 0xff; 6068 status |= max_isr << 8; 6069 vmcs_write16(GUEST_INTR_STATUS, status); 6070 } 6071 } 6072 6073 static void vmx_set_rvi(int vector) 6074 { 6075 u16 status; 6076 u8 old; 6077 6078 if (vector == -1) 6079 vector = 0; 6080 6081 status = vmcs_read16(GUEST_INTR_STATUS); 6082 old = (u8)status & 0xff; 6083 if ((u8)vector != old) { 6084 status &= ~0xff; 6085 status |= (u8)vector; 6086 vmcs_write16(GUEST_INTR_STATUS, status); 6087 } 6088 } 6089 6090 static void vmx_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr) 6091 { 6092 /* 6093 * When running L2, updating RVI is only relevant when 6094 * vmcs12 virtual-interrupt-delivery enabled. 6095 * However, it can be enabled only when L1 also 6096 * intercepts external-interrupts and in that case 6097 * we should not update vmcs02 RVI but instead intercept 6098 * interrupt. Therefore, do nothing when running L2. 6099 */ 6100 if (!is_guest_mode(vcpu)) 6101 vmx_set_rvi(max_irr); 6102 } 6103 6104 static int vmx_sync_pir_to_irr(struct kvm_vcpu *vcpu) 6105 { 6106 struct vcpu_vmx *vmx = to_vmx(vcpu); 6107 int max_irr; 6108 bool max_irr_updated; 6109 6110 WARN_ON(!vcpu->arch.apicv_active); 6111 if (pi_test_on(&vmx->pi_desc)) { 6112 pi_clear_on(&vmx->pi_desc); 6113 /* 6114 * IOMMU can write to PID.ON, so the barrier matters even on UP. 6115 * But on x86 this is just a compiler barrier anyway. 6116 */ 6117 smp_mb__after_atomic(); 6118 max_irr_updated = 6119 kvm_apic_update_irr(vcpu, vmx->pi_desc.pir, &max_irr); 6120 6121 /* 6122 * If we are running L2 and L1 has a new pending interrupt 6123 * which can be injected, we should re-evaluate 6124 * what should be done with this new L1 interrupt. 6125 * If L1 intercepts external-interrupts, we should 6126 * exit from L2 to L1. Otherwise, interrupt should be 6127 * delivered directly to L2. 6128 */ 6129 if (is_guest_mode(vcpu) && max_irr_updated) { 6130 if (nested_exit_on_intr(vcpu)) 6131 kvm_vcpu_exiting_guest_mode(vcpu); 6132 else 6133 kvm_make_request(KVM_REQ_EVENT, vcpu); 6134 } 6135 } else { 6136 max_irr = kvm_lapic_find_highest_irr(vcpu); 6137 } 6138 vmx_hwapic_irr_update(vcpu, max_irr); 6139 return max_irr; 6140 } 6141 6142 static bool vmx_dy_apicv_has_pending_interrupt(struct kvm_vcpu *vcpu) 6143 { 6144 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu); 6145 6146 return pi_test_on(pi_desc) || 6147 (pi_test_sn(pi_desc) && !pi_is_pir_empty(pi_desc)); 6148 } 6149 6150 static void vmx_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap) 6151 { 6152 if (!kvm_vcpu_apicv_active(vcpu)) 6153 return; 6154 6155 vmcs_write64(EOI_EXIT_BITMAP0, eoi_exit_bitmap[0]); 6156 vmcs_write64(EOI_EXIT_BITMAP1, eoi_exit_bitmap[1]); 6157 vmcs_write64(EOI_EXIT_BITMAP2, eoi_exit_bitmap[2]); 6158 vmcs_write64(EOI_EXIT_BITMAP3, eoi_exit_bitmap[3]); 6159 } 6160 6161 static void vmx_apicv_post_state_restore(struct kvm_vcpu *vcpu) 6162 { 6163 struct vcpu_vmx *vmx = to_vmx(vcpu); 6164 6165 pi_clear_on(&vmx->pi_desc); 6166 memset(vmx->pi_desc.pir, 0, sizeof(vmx->pi_desc.pir)); 6167 } 6168 6169 static void handle_exception_nmi_irqoff(struct vcpu_vmx *vmx) 6170 { 6171 vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO); 6172 6173 /* if exit due to PF check for async PF */ 6174 if (is_page_fault(vmx->exit_intr_info)) 6175 vmx->vcpu.arch.apf.host_apf_reason = kvm_read_and_reset_pf_reason(); 6176 6177 /* Handle machine checks before interrupts are enabled */ 6178 if (is_machine_check(vmx->exit_intr_info)) 6179 kvm_machine_check(); 6180 6181 /* We need to handle NMIs before interrupts are enabled */ 6182 if (is_nmi(vmx->exit_intr_info)) { 6183 kvm_before_interrupt(&vmx->vcpu); 6184 asm("int $2"); 6185 kvm_after_interrupt(&vmx->vcpu); 6186 } 6187 } 6188 6189 static void handle_external_interrupt_irqoff(struct kvm_vcpu *vcpu) 6190 { 6191 unsigned int vector; 6192 unsigned long entry; 6193 #ifdef CONFIG_X86_64 6194 unsigned long tmp; 6195 #endif 6196 gate_desc *desc; 6197 u32 intr_info; 6198 6199 intr_info = vmcs_read32(VM_EXIT_INTR_INFO); 6200 if (WARN_ONCE(!is_external_intr(intr_info), 6201 "KVM: unexpected VM-Exit interrupt info: 0x%x", intr_info)) 6202 return; 6203 6204 vector = intr_info & INTR_INFO_VECTOR_MASK; 6205 desc = (gate_desc *)host_idt_base + vector; 6206 entry = gate_offset(desc); 6207 6208 kvm_before_interrupt(vcpu); 6209 6210 asm volatile( 6211 #ifdef CONFIG_X86_64 6212 "mov %%" _ASM_SP ", %[sp]\n\t" 6213 "and $0xfffffffffffffff0, %%" _ASM_SP "\n\t" 6214 "push $%c[ss]\n\t" 6215 "push %[sp]\n\t" 6216 #endif 6217 "pushf\n\t" 6218 __ASM_SIZE(push) " $%c[cs]\n\t" 6219 CALL_NOSPEC 6220 : 6221 #ifdef CONFIG_X86_64 6222 [sp]"=&r"(tmp), 6223 #endif 6224 ASM_CALL_CONSTRAINT 6225 : 6226 THUNK_TARGET(entry), 6227 [ss]"i"(__KERNEL_DS), 6228 [cs]"i"(__KERNEL_CS) 6229 ); 6230 6231 kvm_after_interrupt(vcpu); 6232 } 6233 STACK_FRAME_NON_STANDARD(handle_external_interrupt_irqoff); 6234 6235 static void vmx_handle_exit_irqoff(struct kvm_vcpu *vcpu, 6236 enum exit_fastpath_completion *exit_fastpath) 6237 { 6238 struct vcpu_vmx *vmx = to_vmx(vcpu); 6239 6240 if (vmx->exit_reason == EXIT_REASON_EXTERNAL_INTERRUPT) 6241 handle_external_interrupt_irqoff(vcpu); 6242 else if (vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI) 6243 handle_exception_nmi_irqoff(vmx); 6244 else if (!is_guest_mode(vcpu) && 6245 vmx->exit_reason == EXIT_REASON_MSR_WRITE) 6246 *exit_fastpath = handle_fastpath_set_msr_irqoff(vcpu); 6247 } 6248 6249 static bool vmx_has_emulated_msr(int index) 6250 { 6251 switch (index) { 6252 case MSR_IA32_SMBASE: 6253 /* 6254 * We cannot do SMM unless we can run the guest in big 6255 * real mode. 6256 */ 6257 return enable_unrestricted_guest || emulate_invalid_guest_state; 6258 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC: 6259 return nested; 6260 case MSR_AMD64_VIRT_SPEC_CTRL: 6261 /* This is AMD only. */ 6262 return false; 6263 default: 6264 return true; 6265 } 6266 } 6267 6268 static bool vmx_pt_supported(void) 6269 { 6270 return pt_mode == PT_MODE_HOST_GUEST; 6271 } 6272 6273 static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx) 6274 { 6275 u32 exit_intr_info; 6276 bool unblock_nmi; 6277 u8 vector; 6278 bool idtv_info_valid; 6279 6280 idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK; 6281 6282 if (enable_vnmi) { 6283 if (vmx->loaded_vmcs->nmi_known_unmasked) 6284 return; 6285 /* 6286 * Can't use vmx->exit_intr_info since we're not sure what 6287 * the exit reason is. 6288 */ 6289 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO); 6290 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0; 6291 vector = exit_intr_info & INTR_INFO_VECTOR_MASK; 6292 /* 6293 * SDM 3: 27.7.1.2 (September 2008) 6294 * Re-set bit "block by NMI" before VM entry if vmexit caused by 6295 * a guest IRET fault. 6296 * SDM 3: 23.2.2 (September 2008) 6297 * Bit 12 is undefined in any of the following cases: 6298 * If the VM exit sets the valid bit in the IDT-vectoring 6299 * information field. 6300 * If the VM exit is due to a double fault. 6301 */ 6302 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi && 6303 vector != DF_VECTOR && !idtv_info_valid) 6304 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, 6305 GUEST_INTR_STATE_NMI); 6306 else 6307 vmx->loaded_vmcs->nmi_known_unmasked = 6308 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) 6309 & GUEST_INTR_STATE_NMI); 6310 } else if (unlikely(vmx->loaded_vmcs->soft_vnmi_blocked)) 6311 vmx->loaded_vmcs->vnmi_blocked_time += 6312 ktime_to_ns(ktime_sub(ktime_get(), 6313 vmx->loaded_vmcs->entry_time)); 6314 } 6315 6316 static void __vmx_complete_interrupts(struct kvm_vcpu *vcpu, 6317 u32 idt_vectoring_info, 6318 int instr_len_field, 6319 int error_code_field) 6320 { 6321 u8 vector; 6322 int type; 6323 bool idtv_info_valid; 6324 6325 idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK; 6326 6327 vcpu->arch.nmi_injected = false; 6328 kvm_clear_exception_queue(vcpu); 6329 kvm_clear_interrupt_queue(vcpu); 6330 6331 if (!idtv_info_valid) 6332 return; 6333 6334 kvm_make_request(KVM_REQ_EVENT, vcpu); 6335 6336 vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK; 6337 type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK; 6338 6339 switch (type) { 6340 case INTR_TYPE_NMI_INTR: 6341 vcpu->arch.nmi_injected = true; 6342 /* 6343 * SDM 3: 27.7.1.2 (September 2008) 6344 * Clear bit "block by NMI" before VM entry if a NMI 6345 * delivery faulted. 6346 */ 6347 vmx_set_nmi_mask(vcpu, false); 6348 break; 6349 case INTR_TYPE_SOFT_EXCEPTION: 6350 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field); 6351 /* fall through */ 6352 case INTR_TYPE_HARD_EXCEPTION: 6353 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) { 6354 u32 err = vmcs_read32(error_code_field); 6355 kvm_requeue_exception_e(vcpu, vector, err); 6356 } else 6357 kvm_requeue_exception(vcpu, vector); 6358 break; 6359 case INTR_TYPE_SOFT_INTR: 6360 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field); 6361 /* fall through */ 6362 case INTR_TYPE_EXT_INTR: 6363 kvm_queue_interrupt(vcpu, vector, type == INTR_TYPE_SOFT_INTR); 6364 break; 6365 default: 6366 break; 6367 } 6368 } 6369 6370 static void vmx_complete_interrupts(struct vcpu_vmx *vmx) 6371 { 6372 __vmx_complete_interrupts(&vmx->vcpu, vmx->idt_vectoring_info, 6373 VM_EXIT_INSTRUCTION_LEN, 6374 IDT_VECTORING_ERROR_CODE); 6375 } 6376 6377 static void vmx_cancel_injection(struct kvm_vcpu *vcpu) 6378 { 6379 __vmx_complete_interrupts(vcpu, 6380 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD), 6381 VM_ENTRY_INSTRUCTION_LEN, 6382 VM_ENTRY_EXCEPTION_ERROR_CODE); 6383 6384 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); 6385 } 6386 6387 static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx) 6388 { 6389 int i, nr_msrs; 6390 struct perf_guest_switch_msr *msrs; 6391 6392 msrs = perf_guest_get_msrs(&nr_msrs); 6393 6394 if (!msrs) 6395 return; 6396 6397 for (i = 0; i < nr_msrs; i++) 6398 if (msrs[i].host == msrs[i].guest) 6399 clear_atomic_switch_msr(vmx, msrs[i].msr); 6400 else 6401 add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest, 6402 msrs[i].host, false); 6403 } 6404 6405 static void atomic_switch_umwait_control_msr(struct vcpu_vmx *vmx) 6406 { 6407 u32 host_umwait_control; 6408 6409 if (!vmx_has_waitpkg(vmx)) 6410 return; 6411 6412 host_umwait_control = get_umwait_control_msr(); 6413 6414 if (vmx->msr_ia32_umwait_control != host_umwait_control) 6415 add_atomic_switch_msr(vmx, MSR_IA32_UMWAIT_CONTROL, 6416 vmx->msr_ia32_umwait_control, 6417 host_umwait_control, false); 6418 else 6419 clear_atomic_switch_msr(vmx, MSR_IA32_UMWAIT_CONTROL); 6420 } 6421 6422 static void vmx_update_hv_timer(struct kvm_vcpu *vcpu) 6423 { 6424 struct vcpu_vmx *vmx = to_vmx(vcpu); 6425 u64 tscl; 6426 u32 delta_tsc; 6427 6428 if (vmx->req_immediate_exit) { 6429 vmcs_write32(VMX_PREEMPTION_TIMER_VALUE, 0); 6430 vmx->loaded_vmcs->hv_timer_soft_disabled = false; 6431 } else if (vmx->hv_deadline_tsc != -1) { 6432 tscl = rdtsc(); 6433 if (vmx->hv_deadline_tsc > tscl) 6434 /* set_hv_timer ensures the delta fits in 32-bits */ 6435 delta_tsc = (u32)((vmx->hv_deadline_tsc - tscl) >> 6436 cpu_preemption_timer_multi); 6437 else 6438 delta_tsc = 0; 6439 6440 vmcs_write32(VMX_PREEMPTION_TIMER_VALUE, delta_tsc); 6441 vmx->loaded_vmcs->hv_timer_soft_disabled = false; 6442 } else if (!vmx->loaded_vmcs->hv_timer_soft_disabled) { 6443 vmcs_write32(VMX_PREEMPTION_TIMER_VALUE, -1); 6444 vmx->loaded_vmcs->hv_timer_soft_disabled = true; 6445 } 6446 } 6447 6448 void vmx_update_host_rsp(struct vcpu_vmx *vmx, unsigned long host_rsp) 6449 { 6450 if (unlikely(host_rsp != vmx->loaded_vmcs->host_state.rsp)) { 6451 vmx->loaded_vmcs->host_state.rsp = host_rsp; 6452 vmcs_writel(HOST_RSP, host_rsp); 6453 } 6454 } 6455 6456 bool __vmx_vcpu_run(struct vcpu_vmx *vmx, unsigned long *regs, bool launched); 6457 6458 static void vmx_vcpu_run(struct kvm_vcpu *vcpu) 6459 { 6460 struct vcpu_vmx *vmx = to_vmx(vcpu); 6461 unsigned long cr3, cr4; 6462 6463 /* Record the guest's net vcpu time for enforced NMI injections. */ 6464 if (unlikely(!enable_vnmi && 6465 vmx->loaded_vmcs->soft_vnmi_blocked)) 6466 vmx->loaded_vmcs->entry_time = ktime_get(); 6467 6468 /* Don't enter VMX if guest state is invalid, let the exit handler 6469 start emulation until we arrive back to a valid state */ 6470 if (vmx->emulation_required) 6471 return; 6472 6473 if (vmx->ple_window_dirty) { 6474 vmx->ple_window_dirty = false; 6475 vmcs_write32(PLE_WINDOW, vmx->ple_window); 6476 } 6477 6478 if (vmx->nested.need_vmcs12_to_shadow_sync) 6479 nested_sync_vmcs12_to_shadow(vcpu); 6480 6481 if (kvm_register_is_dirty(vcpu, VCPU_REGS_RSP)) 6482 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]); 6483 if (kvm_register_is_dirty(vcpu, VCPU_REGS_RIP)) 6484 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]); 6485 6486 cr3 = __get_current_cr3_fast(); 6487 if (unlikely(cr3 != vmx->loaded_vmcs->host_state.cr3)) { 6488 vmcs_writel(HOST_CR3, cr3); 6489 vmx->loaded_vmcs->host_state.cr3 = cr3; 6490 } 6491 6492 cr4 = cr4_read_shadow(); 6493 if (unlikely(cr4 != vmx->loaded_vmcs->host_state.cr4)) { 6494 vmcs_writel(HOST_CR4, cr4); 6495 vmx->loaded_vmcs->host_state.cr4 = cr4; 6496 } 6497 6498 /* When single-stepping over STI and MOV SS, we must clear the 6499 * corresponding interruptibility bits in the guest state. Otherwise 6500 * vmentry fails as it then expects bit 14 (BS) in pending debug 6501 * exceptions being set, but that's not correct for the guest debugging 6502 * case. */ 6503 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) 6504 vmx_set_interrupt_shadow(vcpu, 0); 6505 6506 kvm_load_guest_xsave_state(vcpu); 6507 6508 if (static_cpu_has(X86_FEATURE_PKU) && 6509 kvm_read_cr4_bits(vcpu, X86_CR4_PKE) && 6510 vcpu->arch.pkru != vmx->host_pkru) 6511 __write_pkru(vcpu->arch.pkru); 6512 6513 pt_guest_enter(vmx); 6514 6515 atomic_switch_perf_msrs(vmx); 6516 atomic_switch_umwait_control_msr(vmx); 6517 6518 if (enable_preemption_timer) 6519 vmx_update_hv_timer(vcpu); 6520 6521 if (lapic_in_kernel(vcpu) && 6522 vcpu->arch.apic->lapic_timer.timer_advance_ns) 6523 kvm_wait_lapic_expire(vcpu); 6524 6525 /* 6526 * If this vCPU has touched SPEC_CTRL, restore the guest's value if 6527 * it's non-zero. Since vmentry is serialising on affected CPUs, there 6528 * is no need to worry about the conditional branch over the wrmsr 6529 * being speculatively taken. 6530 */ 6531 x86_spec_ctrl_set_guest(vmx->spec_ctrl, 0); 6532 6533 /* L1D Flush includes CPU buffer clear to mitigate MDS */ 6534 if (static_branch_unlikely(&vmx_l1d_should_flush)) 6535 vmx_l1d_flush(vcpu); 6536 else if (static_branch_unlikely(&mds_user_clear)) 6537 mds_clear_cpu_buffers(); 6538 6539 if (vcpu->arch.cr2 != read_cr2()) 6540 write_cr2(vcpu->arch.cr2); 6541 6542 vmx->fail = __vmx_vcpu_run(vmx, (unsigned long *)&vcpu->arch.regs, 6543 vmx->loaded_vmcs->launched); 6544 6545 vcpu->arch.cr2 = read_cr2(); 6546 6547 /* 6548 * We do not use IBRS in the kernel. If this vCPU has used the 6549 * SPEC_CTRL MSR it may have left it on; save the value and 6550 * turn it off. This is much more efficient than blindly adding 6551 * it to the atomic save/restore list. Especially as the former 6552 * (Saving guest MSRs on vmexit) doesn't even exist in KVM. 6553 * 6554 * For non-nested case: 6555 * If the L01 MSR bitmap does not intercept the MSR, then we need to 6556 * save it. 6557 * 6558 * For nested case: 6559 * If the L02 MSR bitmap does not intercept the MSR, then we need to 6560 * save it. 6561 */ 6562 if (unlikely(!msr_write_intercepted(vcpu, MSR_IA32_SPEC_CTRL))) 6563 vmx->spec_ctrl = native_read_msr(MSR_IA32_SPEC_CTRL); 6564 6565 x86_spec_ctrl_restore_host(vmx->spec_ctrl, 0); 6566 6567 /* All fields are clean at this point */ 6568 if (static_branch_unlikely(&enable_evmcs)) 6569 current_evmcs->hv_clean_fields |= 6570 HV_VMX_ENLIGHTENED_CLEAN_FIELD_ALL; 6571 6572 if (static_branch_unlikely(&enable_evmcs)) 6573 current_evmcs->hv_vp_id = vcpu->arch.hyperv.vp_index; 6574 6575 /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */ 6576 if (vmx->host_debugctlmsr) 6577 update_debugctlmsr(vmx->host_debugctlmsr); 6578 6579 #ifndef CONFIG_X86_64 6580 /* 6581 * The sysexit path does not restore ds/es, so we must set them to 6582 * a reasonable value ourselves. 6583 * 6584 * We can't defer this to vmx_prepare_switch_to_host() since that 6585 * function may be executed in interrupt context, which saves and 6586 * restore segments around it, nullifying its effect. 6587 */ 6588 loadsegment(ds, __USER_DS); 6589 loadsegment(es, __USER_DS); 6590 #endif 6591 6592 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP) 6593 | (1 << VCPU_EXREG_RFLAGS) 6594 | (1 << VCPU_EXREG_PDPTR) 6595 | (1 << VCPU_EXREG_SEGMENTS) 6596 | (1 << VCPU_EXREG_CR3)); 6597 vcpu->arch.regs_dirty = 0; 6598 6599 pt_guest_exit(vmx); 6600 6601 /* 6602 * eager fpu is enabled if PKEY is supported and CR4 is switched 6603 * back on host, so it is safe to read guest PKRU from current 6604 * XSAVE. 6605 */ 6606 if (static_cpu_has(X86_FEATURE_PKU) && 6607 kvm_read_cr4_bits(vcpu, X86_CR4_PKE)) { 6608 vcpu->arch.pkru = rdpkru(); 6609 if (vcpu->arch.pkru != vmx->host_pkru) 6610 __write_pkru(vmx->host_pkru); 6611 } 6612 6613 kvm_load_host_xsave_state(vcpu); 6614 6615 vmx->nested.nested_run_pending = 0; 6616 vmx->idt_vectoring_info = 0; 6617 6618 vmx->exit_reason = vmx->fail ? 0xdead : vmcs_read32(VM_EXIT_REASON); 6619 if ((u16)vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY) 6620 kvm_machine_check(); 6621 6622 if (vmx->fail || (vmx->exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY)) 6623 return; 6624 6625 vmx->loaded_vmcs->launched = 1; 6626 vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD); 6627 6628 vmx_recover_nmi_blocking(vmx); 6629 vmx_complete_interrupts(vmx); 6630 } 6631 6632 static struct kvm *vmx_vm_alloc(void) 6633 { 6634 struct kvm_vmx *kvm_vmx = __vmalloc(sizeof(struct kvm_vmx), 6635 GFP_KERNEL_ACCOUNT | __GFP_ZERO, 6636 PAGE_KERNEL); 6637 return &kvm_vmx->kvm; 6638 } 6639 6640 static void vmx_vm_free(struct kvm *kvm) 6641 { 6642 kfree(kvm->arch.hyperv.hv_pa_pg); 6643 vfree(to_kvm_vmx(kvm)); 6644 } 6645 6646 static void vmx_free_vcpu(struct kvm_vcpu *vcpu) 6647 { 6648 struct vcpu_vmx *vmx = to_vmx(vcpu); 6649 6650 if (enable_pml) 6651 vmx_destroy_pml_buffer(vmx); 6652 free_vpid(vmx->vpid); 6653 nested_vmx_free_vcpu(vcpu); 6654 free_loaded_vmcs(vmx->loaded_vmcs); 6655 } 6656 6657 static int vmx_create_vcpu(struct kvm_vcpu *vcpu) 6658 { 6659 struct vcpu_vmx *vmx; 6660 unsigned long *msr_bitmap; 6661 int i, cpu, err; 6662 6663 BUILD_BUG_ON(offsetof(struct vcpu_vmx, vcpu) != 0); 6664 vmx = to_vmx(vcpu); 6665 6666 err = -ENOMEM; 6667 6668 vmx->vpid = allocate_vpid(); 6669 6670 /* 6671 * If PML is turned on, failure on enabling PML just results in failure 6672 * of creating the vcpu, therefore we can simplify PML logic (by 6673 * avoiding dealing with cases, such as enabling PML partially on vcpus 6674 * for the guest), etc. 6675 */ 6676 if (enable_pml) { 6677 vmx->pml_pg = alloc_page(GFP_KERNEL_ACCOUNT | __GFP_ZERO); 6678 if (!vmx->pml_pg) 6679 goto free_vpid; 6680 } 6681 6682 BUILD_BUG_ON(ARRAY_SIZE(vmx_msr_index) != NR_SHARED_MSRS); 6683 6684 for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i) { 6685 u32 index = vmx_msr_index[i]; 6686 u32 data_low, data_high; 6687 int j = vmx->nmsrs; 6688 6689 if (rdmsr_safe(index, &data_low, &data_high) < 0) 6690 continue; 6691 if (wrmsr_safe(index, data_low, data_high) < 0) 6692 continue; 6693 6694 vmx->guest_msrs[j].index = i; 6695 vmx->guest_msrs[j].data = 0; 6696 switch (index) { 6697 case MSR_IA32_TSX_CTRL: 6698 /* 6699 * No need to pass TSX_CTRL_CPUID_CLEAR through, so 6700 * let's avoid changing CPUID bits under the host 6701 * kernel's feet. 6702 */ 6703 vmx->guest_msrs[j].mask = ~(u64)TSX_CTRL_CPUID_CLEAR; 6704 break; 6705 default: 6706 vmx->guest_msrs[j].mask = -1ull; 6707 break; 6708 } 6709 ++vmx->nmsrs; 6710 } 6711 6712 err = alloc_loaded_vmcs(&vmx->vmcs01); 6713 if (err < 0) 6714 goto free_pml; 6715 6716 msr_bitmap = vmx->vmcs01.msr_bitmap; 6717 vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_TSC, MSR_TYPE_R); 6718 vmx_disable_intercept_for_msr(msr_bitmap, MSR_FS_BASE, MSR_TYPE_RW); 6719 vmx_disable_intercept_for_msr(msr_bitmap, MSR_GS_BASE, MSR_TYPE_RW); 6720 vmx_disable_intercept_for_msr(msr_bitmap, MSR_KERNEL_GS_BASE, MSR_TYPE_RW); 6721 vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_SYSENTER_CS, MSR_TYPE_RW); 6722 vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_SYSENTER_ESP, MSR_TYPE_RW); 6723 vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_SYSENTER_EIP, MSR_TYPE_RW); 6724 if (kvm_cstate_in_guest(vcpu->kvm)) { 6725 vmx_disable_intercept_for_msr(msr_bitmap, MSR_CORE_C1_RES, MSR_TYPE_R); 6726 vmx_disable_intercept_for_msr(msr_bitmap, MSR_CORE_C3_RESIDENCY, MSR_TYPE_R); 6727 vmx_disable_intercept_for_msr(msr_bitmap, MSR_CORE_C6_RESIDENCY, MSR_TYPE_R); 6728 vmx_disable_intercept_for_msr(msr_bitmap, MSR_CORE_C7_RESIDENCY, MSR_TYPE_R); 6729 } 6730 vmx->msr_bitmap_mode = 0; 6731 6732 vmx->loaded_vmcs = &vmx->vmcs01; 6733 cpu = get_cpu(); 6734 vmx_vcpu_load(vcpu, cpu); 6735 vcpu->cpu = cpu; 6736 init_vmcs(vmx); 6737 vmx_vcpu_put(vcpu); 6738 put_cpu(); 6739 if (cpu_need_virtualize_apic_accesses(vcpu)) { 6740 err = alloc_apic_access_page(vcpu->kvm); 6741 if (err) 6742 goto free_vmcs; 6743 } 6744 6745 if (enable_ept && !enable_unrestricted_guest) { 6746 err = init_rmode_identity_map(vcpu->kvm); 6747 if (err) 6748 goto free_vmcs; 6749 } 6750 6751 if (nested) 6752 nested_vmx_setup_ctls_msrs(&vmx->nested.msrs, 6753 vmx_capability.ept, 6754 kvm_vcpu_apicv_active(vcpu)); 6755 else 6756 memset(&vmx->nested.msrs, 0, sizeof(vmx->nested.msrs)); 6757 6758 vmx->nested.posted_intr_nv = -1; 6759 vmx->nested.current_vmptr = -1ull; 6760 6761 vmx->msr_ia32_feature_control_valid_bits = FEAT_CTL_LOCKED; 6762 6763 /* 6764 * Enforce invariant: pi_desc.nv is always either POSTED_INTR_VECTOR 6765 * or POSTED_INTR_WAKEUP_VECTOR. 6766 */ 6767 vmx->pi_desc.nv = POSTED_INTR_VECTOR; 6768 vmx->pi_desc.sn = 1; 6769 6770 vmx->ept_pointer = INVALID_PAGE; 6771 6772 return 0; 6773 6774 free_vmcs: 6775 free_loaded_vmcs(vmx->loaded_vmcs); 6776 free_pml: 6777 vmx_destroy_pml_buffer(vmx); 6778 free_vpid: 6779 free_vpid(vmx->vpid); 6780 return err; 6781 } 6782 6783 #define L1TF_MSG_SMT "L1TF CPU bug present and SMT on, data leak possible. See CVE-2018-3646 and https://www.kernel.org/doc/html/latest/admin-guide/hw-vuln/l1tf.html for details.\n" 6784 #define L1TF_MSG_L1D "L1TF CPU bug present and virtualization mitigation disabled, data leak possible. See CVE-2018-3646 and https://www.kernel.org/doc/html/latest/admin-guide/hw-vuln/l1tf.html for details.\n" 6785 6786 static int vmx_vm_init(struct kvm *kvm) 6787 { 6788 spin_lock_init(&to_kvm_vmx(kvm)->ept_pointer_lock); 6789 6790 if (!ple_gap) 6791 kvm->arch.pause_in_guest = true; 6792 6793 if (boot_cpu_has(X86_BUG_L1TF) && enable_ept) { 6794 switch (l1tf_mitigation) { 6795 case L1TF_MITIGATION_OFF: 6796 case L1TF_MITIGATION_FLUSH_NOWARN: 6797 /* 'I explicitly don't care' is set */ 6798 break; 6799 case L1TF_MITIGATION_FLUSH: 6800 case L1TF_MITIGATION_FLUSH_NOSMT: 6801 case L1TF_MITIGATION_FULL: 6802 /* 6803 * Warn upon starting the first VM in a potentially 6804 * insecure environment. 6805 */ 6806 if (sched_smt_active()) 6807 pr_warn_once(L1TF_MSG_SMT); 6808 if (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_NEVER) 6809 pr_warn_once(L1TF_MSG_L1D); 6810 break; 6811 case L1TF_MITIGATION_FULL_FORCE: 6812 /* Flush is enforced */ 6813 break; 6814 } 6815 } 6816 return 0; 6817 } 6818 6819 static int __init vmx_check_processor_compat(void) 6820 { 6821 struct vmcs_config vmcs_conf; 6822 struct vmx_capability vmx_cap; 6823 6824 if (!this_cpu_has(X86_FEATURE_MSR_IA32_FEAT_CTL) || 6825 !this_cpu_has(X86_FEATURE_VMX)) { 6826 pr_err("kvm: VMX is disabled on CPU %d\n", smp_processor_id()); 6827 return -EIO; 6828 } 6829 6830 if (setup_vmcs_config(&vmcs_conf, &vmx_cap) < 0) 6831 return -EIO; 6832 if (nested) 6833 nested_vmx_setup_ctls_msrs(&vmcs_conf.nested, vmx_cap.ept, 6834 enable_apicv); 6835 if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) { 6836 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n", 6837 smp_processor_id()); 6838 return -EIO; 6839 } 6840 return 0; 6841 } 6842 6843 static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio) 6844 { 6845 u8 cache; 6846 u64 ipat = 0; 6847 6848 /* For VT-d and EPT combination 6849 * 1. MMIO: always map as UC 6850 * 2. EPT with VT-d: 6851 * a. VT-d without snooping control feature: can't guarantee the 6852 * result, try to trust guest. 6853 * b. VT-d with snooping control feature: snooping control feature of 6854 * VT-d engine can guarantee the cache correctness. Just set it 6855 * to WB to keep consistent with host. So the same as item 3. 6856 * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep 6857 * consistent with host MTRR 6858 */ 6859 if (is_mmio) { 6860 cache = MTRR_TYPE_UNCACHABLE; 6861 goto exit; 6862 } 6863 6864 if (!kvm_arch_has_noncoherent_dma(vcpu->kvm)) { 6865 ipat = VMX_EPT_IPAT_BIT; 6866 cache = MTRR_TYPE_WRBACK; 6867 goto exit; 6868 } 6869 6870 if (kvm_read_cr0(vcpu) & X86_CR0_CD) { 6871 ipat = VMX_EPT_IPAT_BIT; 6872 if (kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED)) 6873 cache = MTRR_TYPE_WRBACK; 6874 else 6875 cache = MTRR_TYPE_UNCACHABLE; 6876 goto exit; 6877 } 6878 6879 cache = kvm_mtrr_get_guest_memory_type(vcpu, gfn); 6880 6881 exit: 6882 return (cache << VMX_EPT_MT_EPTE_SHIFT) | ipat; 6883 } 6884 6885 static int vmx_get_lpage_level(void) 6886 { 6887 if (enable_ept && !cpu_has_vmx_ept_1g_page()) 6888 return PT_DIRECTORY_LEVEL; 6889 else 6890 /* For shadow and EPT supported 1GB page */ 6891 return PT_PDPE_LEVEL; 6892 } 6893 6894 static void vmcs_set_secondary_exec_control(struct vcpu_vmx *vmx) 6895 { 6896 /* 6897 * These bits in the secondary execution controls field 6898 * are dynamic, the others are mostly based on the hypervisor 6899 * architecture and the guest's CPUID. Do not touch the 6900 * dynamic bits. 6901 */ 6902 u32 mask = 6903 SECONDARY_EXEC_SHADOW_VMCS | 6904 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 6905 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 6906 SECONDARY_EXEC_DESC; 6907 6908 u32 new_ctl = vmx->secondary_exec_control; 6909 u32 cur_ctl = secondary_exec_controls_get(vmx); 6910 6911 secondary_exec_controls_set(vmx, (new_ctl & ~mask) | (cur_ctl & mask)); 6912 } 6913 6914 /* 6915 * Generate MSR_IA32_VMX_CR{0,4}_FIXED1 according to CPUID. Only set bits 6916 * (indicating "allowed-1") if they are supported in the guest's CPUID. 6917 */ 6918 static void nested_vmx_cr_fixed1_bits_update(struct kvm_vcpu *vcpu) 6919 { 6920 struct vcpu_vmx *vmx = to_vmx(vcpu); 6921 struct kvm_cpuid_entry2 *entry; 6922 6923 vmx->nested.msrs.cr0_fixed1 = 0xffffffff; 6924 vmx->nested.msrs.cr4_fixed1 = X86_CR4_PCE; 6925 6926 #define cr4_fixed1_update(_cr4_mask, _reg, _cpuid_mask) do { \ 6927 if (entry && (entry->_reg & (_cpuid_mask))) \ 6928 vmx->nested.msrs.cr4_fixed1 |= (_cr4_mask); \ 6929 } while (0) 6930 6931 entry = kvm_find_cpuid_entry(vcpu, 0x1, 0); 6932 cr4_fixed1_update(X86_CR4_VME, edx, feature_bit(VME)); 6933 cr4_fixed1_update(X86_CR4_PVI, edx, feature_bit(VME)); 6934 cr4_fixed1_update(X86_CR4_TSD, edx, feature_bit(TSC)); 6935 cr4_fixed1_update(X86_CR4_DE, edx, feature_bit(DE)); 6936 cr4_fixed1_update(X86_CR4_PSE, edx, feature_bit(PSE)); 6937 cr4_fixed1_update(X86_CR4_PAE, edx, feature_bit(PAE)); 6938 cr4_fixed1_update(X86_CR4_MCE, edx, feature_bit(MCE)); 6939 cr4_fixed1_update(X86_CR4_PGE, edx, feature_bit(PGE)); 6940 cr4_fixed1_update(X86_CR4_OSFXSR, edx, feature_bit(FXSR)); 6941 cr4_fixed1_update(X86_CR4_OSXMMEXCPT, edx, feature_bit(XMM)); 6942 cr4_fixed1_update(X86_CR4_VMXE, ecx, feature_bit(VMX)); 6943 cr4_fixed1_update(X86_CR4_SMXE, ecx, feature_bit(SMX)); 6944 cr4_fixed1_update(X86_CR4_PCIDE, ecx, feature_bit(PCID)); 6945 cr4_fixed1_update(X86_CR4_OSXSAVE, ecx, feature_bit(XSAVE)); 6946 6947 entry = kvm_find_cpuid_entry(vcpu, 0x7, 0); 6948 cr4_fixed1_update(X86_CR4_FSGSBASE, ebx, feature_bit(FSGSBASE)); 6949 cr4_fixed1_update(X86_CR4_SMEP, ebx, feature_bit(SMEP)); 6950 cr4_fixed1_update(X86_CR4_SMAP, ebx, feature_bit(SMAP)); 6951 cr4_fixed1_update(X86_CR4_PKE, ecx, feature_bit(PKU)); 6952 cr4_fixed1_update(X86_CR4_UMIP, ecx, feature_bit(UMIP)); 6953 cr4_fixed1_update(X86_CR4_LA57, ecx, feature_bit(LA57)); 6954 6955 #undef cr4_fixed1_update 6956 } 6957 6958 static void nested_vmx_entry_exit_ctls_update(struct kvm_vcpu *vcpu) 6959 { 6960 struct vcpu_vmx *vmx = to_vmx(vcpu); 6961 6962 if (kvm_mpx_supported()) { 6963 bool mpx_enabled = guest_cpuid_has(vcpu, X86_FEATURE_MPX); 6964 6965 if (mpx_enabled) { 6966 vmx->nested.msrs.entry_ctls_high |= VM_ENTRY_LOAD_BNDCFGS; 6967 vmx->nested.msrs.exit_ctls_high |= VM_EXIT_CLEAR_BNDCFGS; 6968 } else { 6969 vmx->nested.msrs.entry_ctls_high &= ~VM_ENTRY_LOAD_BNDCFGS; 6970 vmx->nested.msrs.exit_ctls_high &= ~VM_EXIT_CLEAR_BNDCFGS; 6971 } 6972 } 6973 } 6974 6975 static void update_intel_pt_cfg(struct kvm_vcpu *vcpu) 6976 { 6977 struct vcpu_vmx *vmx = to_vmx(vcpu); 6978 struct kvm_cpuid_entry2 *best = NULL; 6979 int i; 6980 6981 for (i = 0; i < PT_CPUID_LEAVES; i++) { 6982 best = kvm_find_cpuid_entry(vcpu, 0x14, i); 6983 if (!best) 6984 return; 6985 vmx->pt_desc.caps[CPUID_EAX + i*PT_CPUID_REGS_NUM] = best->eax; 6986 vmx->pt_desc.caps[CPUID_EBX + i*PT_CPUID_REGS_NUM] = best->ebx; 6987 vmx->pt_desc.caps[CPUID_ECX + i*PT_CPUID_REGS_NUM] = best->ecx; 6988 vmx->pt_desc.caps[CPUID_EDX + i*PT_CPUID_REGS_NUM] = best->edx; 6989 } 6990 6991 /* Get the number of configurable Address Ranges for filtering */ 6992 vmx->pt_desc.addr_range = intel_pt_validate_cap(vmx->pt_desc.caps, 6993 PT_CAP_num_address_ranges); 6994 6995 /* Initialize and clear the no dependency bits */ 6996 vmx->pt_desc.ctl_bitmask = ~(RTIT_CTL_TRACEEN | RTIT_CTL_OS | 6997 RTIT_CTL_USR | RTIT_CTL_TSC_EN | RTIT_CTL_DISRETC); 6998 6999 /* 7000 * If CPUID.(EAX=14H,ECX=0):EBX[0]=1 CR3Filter can be set otherwise 7001 * will inject an #GP 7002 */ 7003 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_cr3_filtering)) 7004 vmx->pt_desc.ctl_bitmask &= ~RTIT_CTL_CR3EN; 7005 7006 /* 7007 * If CPUID.(EAX=14H,ECX=0):EBX[1]=1 CYCEn, CycThresh and 7008 * PSBFreq can be set 7009 */ 7010 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_psb_cyc)) 7011 vmx->pt_desc.ctl_bitmask &= ~(RTIT_CTL_CYCLEACC | 7012 RTIT_CTL_CYC_THRESH | RTIT_CTL_PSB_FREQ); 7013 7014 /* 7015 * If CPUID.(EAX=14H,ECX=0):EBX[3]=1 MTCEn BranchEn and 7016 * MTCFreq can be set 7017 */ 7018 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_mtc)) 7019 vmx->pt_desc.ctl_bitmask &= ~(RTIT_CTL_MTC_EN | 7020 RTIT_CTL_BRANCH_EN | RTIT_CTL_MTC_RANGE); 7021 7022 /* If CPUID.(EAX=14H,ECX=0):EBX[4]=1 FUPonPTW and PTWEn can be set */ 7023 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_ptwrite)) 7024 vmx->pt_desc.ctl_bitmask &= ~(RTIT_CTL_FUP_ON_PTW | 7025 RTIT_CTL_PTW_EN); 7026 7027 /* If CPUID.(EAX=14H,ECX=0):EBX[5]=1 PwrEvEn can be set */ 7028 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_power_event_trace)) 7029 vmx->pt_desc.ctl_bitmask &= ~RTIT_CTL_PWR_EVT_EN; 7030 7031 /* If CPUID.(EAX=14H,ECX=0):ECX[0]=1 ToPA can be set */ 7032 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_topa_output)) 7033 vmx->pt_desc.ctl_bitmask &= ~RTIT_CTL_TOPA; 7034 7035 /* If CPUID.(EAX=14H,ECX=0):ECX[3]=1 FabircEn can be set */ 7036 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_output_subsys)) 7037 vmx->pt_desc.ctl_bitmask &= ~RTIT_CTL_FABRIC_EN; 7038 7039 /* unmask address range configure area */ 7040 for (i = 0; i < vmx->pt_desc.addr_range; i++) 7041 vmx->pt_desc.ctl_bitmask &= ~(0xfULL << (32 + i * 4)); 7042 } 7043 7044 static void vmx_cpuid_update(struct kvm_vcpu *vcpu) 7045 { 7046 struct vcpu_vmx *vmx = to_vmx(vcpu); 7047 7048 /* xsaves_enabled is recomputed in vmx_compute_secondary_exec_control(). */ 7049 vcpu->arch.xsaves_enabled = false; 7050 7051 if (cpu_has_secondary_exec_ctrls()) { 7052 vmx_compute_secondary_exec_control(vmx); 7053 vmcs_set_secondary_exec_control(vmx); 7054 } 7055 7056 if (nested_vmx_allowed(vcpu)) 7057 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits |= 7058 FEAT_CTL_VMX_ENABLED_INSIDE_SMX | 7059 FEAT_CTL_VMX_ENABLED_OUTSIDE_SMX; 7060 else 7061 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits &= 7062 ~(FEAT_CTL_VMX_ENABLED_INSIDE_SMX | 7063 FEAT_CTL_VMX_ENABLED_OUTSIDE_SMX); 7064 7065 if (nested_vmx_allowed(vcpu)) { 7066 nested_vmx_cr_fixed1_bits_update(vcpu); 7067 nested_vmx_entry_exit_ctls_update(vcpu); 7068 } 7069 7070 if (boot_cpu_has(X86_FEATURE_INTEL_PT) && 7071 guest_cpuid_has(vcpu, X86_FEATURE_INTEL_PT)) 7072 update_intel_pt_cfg(vcpu); 7073 7074 if (boot_cpu_has(X86_FEATURE_RTM)) { 7075 struct shared_msr_entry *msr; 7076 msr = find_msr_entry(vmx, MSR_IA32_TSX_CTRL); 7077 if (msr) { 7078 bool enabled = guest_cpuid_has(vcpu, X86_FEATURE_RTM); 7079 vmx_set_guest_msr(vmx, msr, enabled ? 0 : TSX_CTRL_RTM_DISABLE); 7080 } 7081 } 7082 } 7083 7084 static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry) 7085 { 7086 if (func == 1 && nested) 7087 entry->ecx |= feature_bit(VMX); 7088 } 7089 7090 static void vmx_request_immediate_exit(struct kvm_vcpu *vcpu) 7091 { 7092 to_vmx(vcpu)->req_immediate_exit = true; 7093 } 7094 7095 static int vmx_check_intercept(struct kvm_vcpu *vcpu, 7096 struct x86_instruction_info *info, 7097 enum x86_intercept_stage stage) 7098 { 7099 struct vmcs12 *vmcs12 = get_vmcs12(vcpu); 7100 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt; 7101 7102 /* 7103 * RDPID causes #UD if disabled through secondary execution controls. 7104 * Because it is marked as EmulateOnUD, we need to intercept it here. 7105 */ 7106 if (info->intercept == x86_intercept_rdtscp && 7107 !nested_cpu_has2(vmcs12, SECONDARY_EXEC_RDTSCP)) { 7108 ctxt->exception.vector = UD_VECTOR; 7109 ctxt->exception.error_code_valid = false; 7110 return X86EMUL_PROPAGATE_FAULT; 7111 } 7112 7113 /* TODO: check more intercepts... */ 7114 return X86EMUL_CONTINUE; 7115 } 7116 7117 #ifdef CONFIG_X86_64 7118 /* (a << shift) / divisor, return 1 if overflow otherwise 0 */ 7119 static inline int u64_shl_div_u64(u64 a, unsigned int shift, 7120 u64 divisor, u64 *result) 7121 { 7122 u64 low = a << shift, high = a >> (64 - shift); 7123 7124 /* To avoid the overflow on divq */ 7125 if (high >= divisor) 7126 return 1; 7127 7128 /* Low hold the result, high hold rem which is discarded */ 7129 asm("divq %2\n\t" : "=a" (low), "=d" (high) : 7130 "rm" (divisor), "0" (low), "1" (high)); 7131 *result = low; 7132 7133 return 0; 7134 } 7135 7136 static int vmx_set_hv_timer(struct kvm_vcpu *vcpu, u64 guest_deadline_tsc, 7137 bool *expired) 7138 { 7139 struct vcpu_vmx *vmx; 7140 u64 tscl, guest_tscl, delta_tsc, lapic_timer_advance_cycles; 7141 struct kvm_timer *ktimer = &vcpu->arch.apic->lapic_timer; 7142 7143 if (kvm_mwait_in_guest(vcpu->kvm) || 7144 kvm_can_post_timer_interrupt(vcpu)) 7145 return -EOPNOTSUPP; 7146 7147 vmx = to_vmx(vcpu); 7148 tscl = rdtsc(); 7149 guest_tscl = kvm_read_l1_tsc(vcpu, tscl); 7150 delta_tsc = max(guest_deadline_tsc, guest_tscl) - guest_tscl; 7151 lapic_timer_advance_cycles = nsec_to_cycles(vcpu, 7152 ktimer->timer_advance_ns); 7153 7154 if (delta_tsc > lapic_timer_advance_cycles) 7155 delta_tsc -= lapic_timer_advance_cycles; 7156 else 7157 delta_tsc = 0; 7158 7159 /* Convert to host delta tsc if tsc scaling is enabled */ 7160 if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio && 7161 delta_tsc && u64_shl_div_u64(delta_tsc, 7162 kvm_tsc_scaling_ratio_frac_bits, 7163 vcpu->arch.tsc_scaling_ratio, &delta_tsc)) 7164 return -ERANGE; 7165 7166 /* 7167 * If the delta tsc can't fit in the 32 bit after the multi shift, 7168 * we can't use the preemption timer. 7169 * It's possible that it fits on later vmentries, but checking 7170 * on every vmentry is costly so we just use an hrtimer. 7171 */ 7172 if (delta_tsc >> (cpu_preemption_timer_multi + 32)) 7173 return -ERANGE; 7174 7175 vmx->hv_deadline_tsc = tscl + delta_tsc; 7176 *expired = !delta_tsc; 7177 return 0; 7178 } 7179 7180 static void vmx_cancel_hv_timer(struct kvm_vcpu *vcpu) 7181 { 7182 to_vmx(vcpu)->hv_deadline_tsc = -1; 7183 } 7184 #endif 7185 7186 static void vmx_sched_in(struct kvm_vcpu *vcpu, int cpu) 7187 { 7188 if (!kvm_pause_in_guest(vcpu->kvm)) 7189 shrink_ple_window(vcpu); 7190 } 7191 7192 static void vmx_slot_enable_log_dirty(struct kvm *kvm, 7193 struct kvm_memory_slot *slot) 7194 { 7195 kvm_mmu_slot_leaf_clear_dirty(kvm, slot); 7196 kvm_mmu_slot_largepage_remove_write_access(kvm, slot); 7197 } 7198 7199 static void vmx_slot_disable_log_dirty(struct kvm *kvm, 7200 struct kvm_memory_slot *slot) 7201 { 7202 kvm_mmu_slot_set_dirty(kvm, slot); 7203 } 7204 7205 static void vmx_flush_log_dirty(struct kvm *kvm) 7206 { 7207 kvm_flush_pml_buffers(kvm); 7208 } 7209 7210 static int vmx_write_pml_buffer(struct kvm_vcpu *vcpu) 7211 { 7212 struct vmcs12 *vmcs12; 7213 struct vcpu_vmx *vmx = to_vmx(vcpu); 7214 gpa_t gpa, dst; 7215 7216 if (is_guest_mode(vcpu)) { 7217 WARN_ON_ONCE(vmx->nested.pml_full); 7218 7219 /* 7220 * Check if PML is enabled for the nested guest. 7221 * Whether eptp bit 6 is set is already checked 7222 * as part of A/D emulation. 7223 */ 7224 vmcs12 = get_vmcs12(vcpu); 7225 if (!nested_cpu_has_pml(vmcs12)) 7226 return 0; 7227 7228 if (vmcs12->guest_pml_index >= PML_ENTITY_NUM) { 7229 vmx->nested.pml_full = true; 7230 return 1; 7231 } 7232 7233 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS) & ~0xFFFull; 7234 dst = vmcs12->pml_address + sizeof(u64) * vmcs12->guest_pml_index; 7235 7236 if (kvm_write_guest_page(vcpu->kvm, gpa_to_gfn(dst), &gpa, 7237 offset_in_page(dst), sizeof(gpa))) 7238 return 0; 7239 7240 vmcs12->guest_pml_index--; 7241 } 7242 7243 return 0; 7244 } 7245 7246 static void vmx_enable_log_dirty_pt_masked(struct kvm *kvm, 7247 struct kvm_memory_slot *memslot, 7248 gfn_t offset, unsigned long mask) 7249 { 7250 kvm_mmu_clear_dirty_pt_masked(kvm, memslot, offset, mask); 7251 } 7252 7253 static void __pi_post_block(struct kvm_vcpu *vcpu) 7254 { 7255 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu); 7256 struct pi_desc old, new; 7257 unsigned int dest; 7258 7259 do { 7260 old.control = new.control = pi_desc->control; 7261 WARN(old.nv != POSTED_INTR_WAKEUP_VECTOR, 7262 "Wakeup handler not enabled while the VCPU is blocked\n"); 7263 7264 dest = cpu_physical_id(vcpu->cpu); 7265 7266 if (x2apic_enabled()) 7267 new.ndst = dest; 7268 else 7269 new.ndst = (dest << 8) & 0xFF00; 7270 7271 /* set 'NV' to 'notification vector' */ 7272 new.nv = POSTED_INTR_VECTOR; 7273 } while (cmpxchg64(&pi_desc->control, old.control, 7274 new.control) != old.control); 7275 7276 if (!WARN_ON_ONCE(vcpu->pre_pcpu == -1)) { 7277 spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu)); 7278 list_del(&vcpu->blocked_vcpu_list); 7279 spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu)); 7280 vcpu->pre_pcpu = -1; 7281 } 7282 } 7283 7284 /* 7285 * This routine does the following things for vCPU which is going 7286 * to be blocked if VT-d PI is enabled. 7287 * - Store the vCPU to the wakeup list, so when interrupts happen 7288 * we can find the right vCPU to wake up. 7289 * - Change the Posted-interrupt descriptor as below: 7290 * 'NDST' <-- vcpu->pre_pcpu 7291 * 'NV' <-- POSTED_INTR_WAKEUP_VECTOR 7292 * - If 'ON' is set during this process, which means at least one 7293 * interrupt is posted for this vCPU, we cannot block it, in 7294 * this case, return 1, otherwise, return 0. 7295 * 7296 */ 7297 static int pi_pre_block(struct kvm_vcpu *vcpu) 7298 { 7299 unsigned int dest; 7300 struct pi_desc old, new; 7301 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu); 7302 7303 if (!kvm_arch_has_assigned_device(vcpu->kvm) || 7304 !irq_remapping_cap(IRQ_POSTING_CAP) || 7305 !kvm_vcpu_apicv_active(vcpu)) 7306 return 0; 7307 7308 WARN_ON(irqs_disabled()); 7309 local_irq_disable(); 7310 if (!WARN_ON_ONCE(vcpu->pre_pcpu != -1)) { 7311 vcpu->pre_pcpu = vcpu->cpu; 7312 spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu)); 7313 list_add_tail(&vcpu->blocked_vcpu_list, 7314 &per_cpu(blocked_vcpu_on_cpu, 7315 vcpu->pre_pcpu)); 7316 spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu)); 7317 } 7318 7319 do { 7320 old.control = new.control = pi_desc->control; 7321 7322 WARN((pi_desc->sn == 1), 7323 "Warning: SN field of posted-interrupts " 7324 "is set before blocking\n"); 7325 7326 /* 7327 * Since vCPU can be preempted during this process, 7328 * vcpu->cpu could be different with pre_pcpu, we 7329 * need to set pre_pcpu as the destination of wakeup 7330 * notification event, then we can find the right vCPU 7331 * to wakeup in wakeup handler if interrupts happen 7332 * when the vCPU is in blocked state. 7333 */ 7334 dest = cpu_physical_id(vcpu->pre_pcpu); 7335 7336 if (x2apic_enabled()) 7337 new.ndst = dest; 7338 else 7339 new.ndst = (dest << 8) & 0xFF00; 7340 7341 /* set 'NV' to 'wakeup vector' */ 7342 new.nv = POSTED_INTR_WAKEUP_VECTOR; 7343 } while (cmpxchg64(&pi_desc->control, old.control, 7344 new.control) != old.control); 7345 7346 /* We should not block the vCPU if an interrupt is posted for it. */ 7347 if (pi_test_on(pi_desc) == 1) 7348 __pi_post_block(vcpu); 7349 7350 local_irq_enable(); 7351 return (vcpu->pre_pcpu == -1); 7352 } 7353 7354 static int vmx_pre_block(struct kvm_vcpu *vcpu) 7355 { 7356 if (pi_pre_block(vcpu)) 7357 return 1; 7358 7359 if (kvm_lapic_hv_timer_in_use(vcpu)) 7360 kvm_lapic_switch_to_sw_timer(vcpu); 7361 7362 return 0; 7363 } 7364 7365 static void pi_post_block(struct kvm_vcpu *vcpu) 7366 { 7367 if (vcpu->pre_pcpu == -1) 7368 return; 7369 7370 WARN_ON(irqs_disabled()); 7371 local_irq_disable(); 7372 __pi_post_block(vcpu); 7373 local_irq_enable(); 7374 } 7375 7376 static void vmx_post_block(struct kvm_vcpu *vcpu) 7377 { 7378 if (kvm_x86_ops->set_hv_timer) 7379 kvm_lapic_switch_to_hv_timer(vcpu); 7380 7381 pi_post_block(vcpu); 7382 } 7383 7384 /* 7385 * vmx_update_pi_irte - set IRTE for Posted-Interrupts 7386 * 7387 * @kvm: kvm 7388 * @host_irq: host irq of the interrupt 7389 * @guest_irq: gsi of the interrupt 7390 * @set: set or unset PI 7391 * returns 0 on success, < 0 on failure 7392 */ 7393 static int vmx_update_pi_irte(struct kvm *kvm, unsigned int host_irq, 7394 uint32_t guest_irq, bool set) 7395 { 7396 struct kvm_kernel_irq_routing_entry *e; 7397 struct kvm_irq_routing_table *irq_rt; 7398 struct kvm_lapic_irq irq; 7399 struct kvm_vcpu *vcpu; 7400 struct vcpu_data vcpu_info; 7401 int idx, ret = 0; 7402 7403 if (!kvm_arch_has_assigned_device(kvm) || 7404 !irq_remapping_cap(IRQ_POSTING_CAP) || 7405 !kvm_vcpu_apicv_active(kvm->vcpus[0])) 7406 return 0; 7407 7408 idx = srcu_read_lock(&kvm->irq_srcu); 7409 irq_rt = srcu_dereference(kvm->irq_routing, &kvm->irq_srcu); 7410 if (guest_irq >= irq_rt->nr_rt_entries || 7411 hlist_empty(&irq_rt->map[guest_irq])) { 7412 pr_warn_once("no route for guest_irq %u/%u (broken user space?)\n", 7413 guest_irq, irq_rt->nr_rt_entries); 7414 goto out; 7415 } 7416 7417 hlist_for_each_entry(e, &irq_rt->map[guest_irq], link) { 7418 if (e->type != KVM_IRQ_ROUTING_MSI) 7419 continue; 7420 /* 7421 * VT-d PI cannot support posting multicast/broadcast 7422 * interrupts to a vCPU, we still use interrupt remapping 7423 * for these kind of interrupts. 7424 * 7425 * For lowest-priority interrupts, we only support 7426 * those with single CPU as the destination, e.g. user 7427 * configures the interrupts via /proc/irq or uses 7428 * irqbalance to make the interrupts single-CPU. 7429 * 7430 * We will support full lowest-priority interrupt later. 7431 * 7432 * In addition, we can only inject generic interrupts using 7433 * the PI mechanism, refuse to route others through it. 7434 */ 7435 7436 kvm_set_msi_irq(kvm, e, &irq); 7437 if (!kvm_intr_is_single_vcpu(kvm, &irq, &vcpu) || 7438 !kvm_irq_is_postable(&irq)) { 7439 /* 7440 * Make sure the IRTE is in remapped mode if 7441 * we don't handle it in posted mode. 7442 */ 7443 ret = irq_set_vcpu_affinity(host_irq, NULL); 7444 if (ret < 0) { 7445 printk(KERN_INFO 7446 "failed to back to remapped mode, irq: %u\n", 7447 host_irq); 7448 goto out; 7449 } 7450 7451 continue; 7452 } 7453 7454 vcpu_info.pi_desc_addr = __pa(vcpu_to_pi_desc(vcpu)); 7455 vcpu_info.vector = irq.vector; 7456 7457 trace_kvm_pi_irte_update(host_irq, vcpu->vcpu_id, e->gsi, 7458 vcpu_info.vector, vcpu_info.pi_desc_addr, set); 7459 7460 if (set) 7461 ret = irq_set_vcpu_affinity(host_irq, &vcpu_info); 7462 else 7463 ret = irq_set_vcpu_affinity(host_irq, NULL); 7464 7465 if (ret < 0) { 7466 printk(KERN_INFO "%s: failed to update PI IRTE\n", 7467 __func__); 7468 goto out; 7469 } 7470 } 7471 7472 ret = 0; 7473 out: 7474 srcu_read_unlock(&kvm->irq_srcu, idx); 7475 return ret; 7476 } 7477 7478 static void vmx_setup_mce(struct kvm_vcpu *vcpu) 7479 { 7480 if (vcpu->arch.mcg_cap & MCG_LMCE_P) 7481 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits |= 7482 FEAT_CTL_LMCE_ENABLED; 7483 else 7484 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits &= 7485 ~FEAT_CTL_LMCE_ENABLED; 7486 } 7487 7488 static int vmx_smi_allowed(struct kvm_vcpu *vcpu) 7489 { 7490 /* we need a nested vmexit to enter SMM, postpone if run is pending */ 7491 if (to_vmx(vcpu)->nested.nested_run_pending) 7492 return 0; 7493 return 1; 7494 } 7495 7496 static int vmx_pre_enter_smm(struct kvm_vcpu *vcpu, char *smstate) 7497 { 7498 struct vcpu_vmx *vmx = to_vmx(vcpu); 7499 7500 vmx->nested.smm.guest_mode = is_guest_mode(vcpu); 7501 if (vmx->nested.smm.guest_mode) 7502 nested_vmx_vmexit(vcpu, -1, 0, 0); 7503 7504 vmx->nested.smm.vmxon = vmx->nested.vmxon; 7505 vmx->nested.vmxon = false; 7506 vmx_clear_hlt(vcpu); 7507 return 0; 7508 } 7509 7510 static int vmx_pre_leave_smm(struct kvm_vcpu *vcpu, const char *smstate) 7511 { 7512 struct vcpu_vmx *vmx = to_vmx(vcpu); 7513 int ret; 7514 7515 if (vmx->nested.smm.vmxon) { 7516 vmx->nested.vmxon = true; 7517 vmx->nested.smm.vmxon = false; 7518 } 7519 7520 if (vmx->nested.smm.guest_mode) { 7521 ret = nested_vmx_enter_non_root_mode(vcpu, false); 7522 if (ret) 7523 return ret; 7524 7525 vmx->nested.smm.guest_mode = false; 7526 } 7527 return 0; 7528 } 7529 7530 static int enable_smi_window(struct kvm_vcpu *vcpu) 7531 { 7532 return 0; 7533 } 7534 7535 static bool vmx_need_emulation_on_page_fault(struct kvm_vcpu *vcpu) 7536 { 7537 return false; 7538 } 7539 7540 static bool vmx_apic_init_signal_blocked(struct kvm_vcpu *vcpu) 7541 { 7542 return to_vmx(vcpu)->nested.vmxon; 7543 } 7544 7545 static __init int hardware_setup(void) 7546 { 7547 unsigned long host_bndcfgs; 7548 struct desc_ptr dt; 7549 int r, i; 7550 7551 rdmsrl_safe(MSR_EFER, &host_efer); 7552 7553 store_idt(&dt); 7554 host_idt_base = dt.address; 7555 7556 for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i) 7557 kvm_define_shared_msr(i, vmx_msr_index[i]); 7558 7559 if (setup_vmcs_config(&vmcs_config, &vmx_capability) < 0) 7560 return -EIO; 7561 7562 if (boot_cpu_has(X86_FEATURE_NX)) 7563 kvm_enable_efer_bits(EFER_NX); 7564 7565 if (boot_cpu_has(X86_FEATURE_MPX)) { 7566 rdmsrl(MSR_IA32_BNDCFGS, host_bndcfgs); 7567 WARN_ONCE(host_bndcfgs, "KVM: BNDCFGS in host will be lost"); 7568 } 7569 7570 if (!cpu_has_vmx_vpid() || !cpu_has_vmx_invvpid() || 7571 !(cpu_has_vmx_invvpid_single() || cpu_has_vmx_invvpid_global())) 7572 enable_vpid = 0; 7573 7574 if (!cpu_has_vmx_ept() || 7575 !cpu_has_vmx_ept_4levels() || 7576 !cpu_has_vmx_ept_mt_wb() || 7577 !cpu_has_vmx_invept_global()) 7578 enable_ept = 0; 7579 7580 if (!cpu_has_vmx_ept_ad_bits() || !enable_ept) 7581 enable_ept_ad_bits = 0; 7582 7583 if (!cpu_has_vmx_unrestricted_guest() || !enable_ept) 7584 enable_unrestricted_guest = 0; 7585 7586 if (!cpu_has_vmx_flexpriority()) 7587 flexpriority_enabled = 0; 7588 7589 if (!cpu_has_virtual_nmis()) 7590 enable_vnmi = 0; 7591 7592 /* 7593 * set_apic_access_page_addr() is used to reload apic access 7594 * page upon invalidation. No need to do anything if not 7595 * using the APIC_ACCESS_ADDR VMCS field. 7596 */ 7597 if (!flexpriority_enabled) 7598 kvm_x86_ops->set_apic_access_page_addr = NULL; 7599 7600 if (!cpu_has_vmx_tpr_shadow()) 7601 kvm_x86_ops->update_cr8_intercept = NULL; 7602 7603 if (enable_ept && !cpu_has_vmx_ept_2m_page()) 7604 kvm_disable_largepages(); 7605 7606 #if IS_ENABLED(CONFIG_HYPERV) 7607 if (ms_hyperv.nested_features & HV_X64_NESTED_GUEST_MAPPING_FLUSH 7608 && enable_ept) { 7609 kvm_x86_ops->tlb_remote_flush = hv_remote_flush_tlb; 7610 kvm_x86_ops->tlb_remote_flush_with_range = 7611 hv_remote_flush_tlb_with_range; 7612 } 7613 #endif 7614 7615 if (!cpu_has_vmx_ple()) { 7616 ple_gap = 0; 7617 ple_window = 0; 7618 ple_window_grow = 0; 7619 ple_window_max = 0; 7620 ple_window_shrink = 0; 7621 } 7622 7623 if (!cpu_has_vmx_apicv()) { 7624 enable_apicv = 0; 7625 kvm_x86_ops->sync_pir_to_irr = NULL; 7626 } 7627 7628 if (cpu_has_vmx_tsc_scaling()) { 7629 kvm_has_tsc_control = true; 7630 kvm_max_tsc_scaling_ratio = KVM_VMX_TSC_MULTIPLIER_MAX; 7631 kvm_tsc_scaling_ratio_frac_bits = 48; 7632 } 7633 7634 set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */ 7635 7636 if (enable_ept) 7637 vmx_enable_tdp(); 7638 else 7639 kvm_disable_tdp(); 7640 7641 /* 7642 * Only enable PML when hardware supports PML feature, and both EPT 7643 * and EPT A/D bit features are enabled -- PML depends on them to work. 7644 */ 7645 if (!enable_ept || !enable_ept_ad_bits || !cpu_has_vmx_pml()) 7646 enable_pml = 0; 7647 7648 if (!enable_pml) { 7649 kvm_x86_ops->slot_enable_log_dirty = NULL; 7650 kvm_x86_ops->slot_disable_log_dirty = NULL; 7651 kvm_x86_ops->flush_log_dirty = NULL; 7652 kvm_x86_ops->enable_log_dirty_pt_masked = NULL; 7653 } 7654 7655 if (!cpu_has_vmx_preemption_timer()) 7656 enable_preemption_timer = false; 7657 7658 if (enable_preemption_timer) { 7659 u64 use_timer_freq = 5000ULL * 1000 * 1000; 7660 u64 vmx_msr; 7661 7662 rdmsrl(MSR_IA32_VMX_MISC, vmx_msr); 7663 cpu_preemption_timer_multi = 7664 vmx_msr & VMX_MISC_PREEMPTION_TIMER_RATE_MASK; 7665 7666 if (tsc_khz) 7667 use_timer_freq = (u64)tsc_khz * 1000; 7668 use_timer_freq >>= cpu_preemption_timer_multi; 7669 7670 /* 7671 * KVM "disables" the preemption timer by setting it to its max 7672 * value. Don't use the timer if it might cause spurious exits 7673 * at a rate faster than 0.1 Hz (of uninterrupted guest time). 7674 */ 7675 if (use_timer_freq > 0xffffffffu / 10) 7676 enable_preemption_timer = false; 7677 } 7678 7679 if (!enable_preemption_timer) { 7680 kvm_x86_ops->set_hv_timer = NULL; 7681 kvm_x86_ops->cancel_hv_timer = NULL; 7682 kvm_x86_ops->request_immediate_exit = __kvm_request_immediate_exit; 7683 } 7684 7685 kvm_set_posted_intr_wakeup_handler(wakeup_handler); 7686 7687 kvm_mce_cap_supported |= MCG_LMCE_P; 7688 7689 if (pt_mode != PT_MODE_SYSTEM && pt_mode != PT_MODE_HOST_GUEST) 7690 return -EINVAL; 7691 if (!enable_ept || !cpu_has_vmx_intel_pt()) 7692 pt_mode = PT_MODE_SYSTEM; 7693 7694 if (nested) { 7695 nested_vmx_setup_ctls_msrs(&vmcs_config.nested, 7696 vmx_capability.ept, enable_apicv); 7697 7698 r = nested_vmx_hardware_setup(kvm_vmx_exit_handlers); 7699 if (r) 7700 return r; 7701 } 7702 7703 r = alloc_kvm_area(); 7704 if (r) 7705 nested_vmx_hardware_unsetup(); 7706 return r; 7707 } 7708 7709 static __exit void hardware_unsetup(void) 7710 { 7711 if (nested) 7712 nested_vmx_hardware_unsetup(); 7713 7714 free_kvm_area(); 7715 } 7716 7717 static struct kvm_x86_ops vmx_x86_ops __ro_after_init = { 7718 .cpu_has_kvm_support = cpu_has_kvm_support, 7719 .disabled_by_bios = vmx_disabled_by_bios, 7720 .hardware_setup = hardware_setup, 7721 .hardware_unsetup = hardware_unsetup, 7722 .check_processor_compatibility = vmx_check_processor_compat, 7723 .hardware_enable = hardware_enable, 7724 .hardware_disable = hardware_disable, 7725 .cpu_has_accelerated_tpr = report_flexpriority, 7726 .has_emulated_msr = vmx_has_emulated_msr, 7727 7728 .vm_init = vmx_vm_init, 7729 .vm_alloc = vmx_vm_alloc, 7730 .vm_free = vmx_vm_free, 7731 7732 .vcpu_create = vmx_create_vcpu, 7733 .vcpu_free = vmx_free_vcpu, 7734 .vcpu_reset = vmx_vcpu_reset, 7735 7736 .prepare_guest_switch = vmx_prepare_switch_to_guest, 7737 .vcpu_load = vmx_vcpu_load, 7738 .vcpu_put = vmx_vcpu_put, 7739 7740 .update_bp_intercept = update_exception_bitmap, 7741 .get_msr_feature = vmx_get_msr_feature, 7742 .get_msr = vmx_get_msr, 7743 .set_msr = vmx_set_msr, 7744 .get_segment_base = vmx_get_segment_base, 7745 .get_segment = vmx_get_segment, 7746 .set_segment = vmx_set_segment, 7747 .get_cpl = vmx_get_cpl, 7748 .get_cs_db_l_bits = vmx_get_cs_db_l_bits, 7749 .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits, 7750 .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits, 7751 .set_cr0 = vmx_set_cr0, 7752 .set_cr3 = vmx_set_cr3, 7753 .set_cr4 = vmx_set_cr4, 7754 .set_efer = vmx_set_efer, 7755 .get_idt = vmx_get_idt, 7756 .set_idt = vmx_set_idt, 7757 .get_gdt = vmx_get_gdt, 7758 .set_gdt = vmx_set_gdt, 7759 .get_dr6 = vmx_get_dr6, 7760 .set_dr6 = vmx_set_dr6, 7761 .set_dr7 = vmx_set_dr7, 7762 .sync_dirty_debug_regs = vmx_sync_dirty_debug_regs, 7763 .cache_reg = vmx_cache_reg, 7764 .get_rflags = vmx_get_rflags, 7765 .set_rflags = vmx_set_rflags, 7766 7767 .tlb_flush = vmx_flush_tlb, 7768 .tlb_flush_gva = vmx_flush_tlb_gva, 7769 7770 .run = vmx_vcpu_run, 7771 .handle_exit = vmx_handle_exit, 7772 .skip_emulated_instruction = skip_emulated_instruction, 7773 .set_interrupt_shadow = vmx_set_interrupt_shadow, 7774 .get_interrupt_shadow = vmx_get_interrupt_shadow, 7775 .patch_hypercall = vmx_patch_hypercall, 7776 .set_irq = vmx_inject_irq, 7777 .set_nmi = vmx_inject_nmi, 7778 .queue_exception = vmx_queue_exception, 7779 .cancel_injection = vmx_cancel_injection, 7780 .interrupt_allowed = vmx_interrupt_allowed, 7781 .nmi_allowed = vmx_nmi_allowed, 7782 .get_nmi_mask = vmx_get_nmi_mask, 7783 .set_nmi_mask = vmx_set_nmi_mask, 7784 .enable_nmi_window = enable_nmi_window, 7785 .enable_irq_window = enable_irq_window, 7786 .update_cr8_intercept = update_cr8_intercept, 7787 .set_virtual_apic_mode = vmx_set_virtual_apic_mode, 7788 .set_apic_access_page_addr = vmx_set_apic_access_page_addr, 7789 .get_enable_apicv = vmx_get_enable_apicv, 7790 .refresh_apicv_exec_ctrl = vmx_refresh_apicv_exec_ctrl, 7791 .load_eoi_exitmap = vmx_load_eoi_exitmap, 7792 .apicv_post_state_restore = vmx_apicv_post_state_restore, 7793 .hwapic_irr_update = vmx_hwapic_irr_update, 7794 .hwapic_isr_update = vmx_hwapic_isr_update, 7795 .guest_apic_has_interrupt = vmx_guest_apic_has_interrupt, 7796 .sync_pir_to_irr = vmx_sync_pir_to_irr, 7797 .deliver_posted_interrupt = vmx_deliver_posted_interrupt, 7798 .dy_apicv_has_pending_interrupt = vmx_dy_apicv_has_pending_interrupt, 7799 7800 .set_tss_addr = vmx_set_tss_addr, 7801 .set_identity_map_addr = vmx_set_identity_map_addr, 7802 .get_tdp_level = get_ept_level, 7803 .get_mt_mask = vmx_get_mt_mask, 7804 7805 .get_exit_info = vmx_get_exit_info, 7806 7807 .get_lpage_level = vmx_get_lpage_level, 7808 7809 .cpuid_update = vmx_cpuid_update, 7810 7811 .rdtscp_supported = vmx_rdtscp_supported, 7812 .invpcid_supported = vmx_invpcid_supported, 7813 7814 .set_supported_cpuid = vmx_set_supported_cpuid, 7815 7816 .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit, 7817 7818 .read_l1_tsc_offset = vmx_read_l1_tsc_offset, 7819 .write_l1_tsc_offset = vmx_write_l1_tsc_offset, 7820 7821 .set_tdp_cr3 = vmx_set_cr3, 7822 7823 .check_intercept = vmx_check_intercept, 7824 .handle_exit_irqoff = vmx_handle_exit_irqoff, 7825 .mpx_supported = vmx_mpx_supported, 7826 .xsaves_supported = vmx_xsaves_supported, 7827 .umip_emulated = vmx_umip_emulated, 7828 .pt_supported = vmx_pt_supported, 7829 .pku_supported = vmx_pku_supported, 7830 7831 .request_immediate_exit = vmx_request_immediate_exit, 7832 7833 .sched_in = vmx_sched_in, 7834 7835 .slot_enable_log_dirty = vmx_slot_enable_log_dirty, 7836 .slot_disable_log_dirty = vmx_slot_disable_log_dirty, 7837 .flush_log_dirty = vmx_flush_log_dirty, 7838 .enable_log_dirty_pt_masked = vmx_enable_log_dirty_pt_masked, 7839 .write_log_dirty = vmx_write_pml_buffer, 7840 7841 .pre_block = vmx_pre_block, 7842 .post_block = vmx_post_block, 7843 7844 .pmu_ops = &intel_pmu_ops, 7845 7846 .update_pi_irte = vmx_update_pi_irte, 7847 7848 #ifdef CONFIG_X86_64 7849 .set_hv_timer = vmx_set_hv_timer, 7850 .cancel_hv_timer = vmx_cancel_hv_timer, 7851 #endif 7852 7853 .setup_mce = vmx_setup_mce, 7854 7855 .smi_allowed = vmx_smi_allowed, 7856 .pre_enter_smm = vmx_pre_enter_smm, 7857 .pre_leave_smm = vmx_pre_leave_smm, 7858 .enable_smi_window = enable_smi_window, 7859 7860 .check_nested_events = NULL, 7861 .get_nested_state = NULL, 7862 .set_nested_state = NULL, 7863 .get_vmcs12_pages = NULL, 7864 .nested_enable_evmcs = NULL, 7865 .nested_get_evmcs_version = NULL, 7866 .need_emulation_on_page_fault = vmx_need_emulation_on_page_fault, 7867 .apic_init_signal_blocked = vmx_apic_init_signal_blocked, 7868 }; 7869 7870 static void vmx_cleanup_l1d_flush(void) 7871 { 7872 if (vmx_l1d_flush_pages) { 7873 free_pages((unsigned long)vmx_l1d_flush_pages, L1D_CACHE_ORDER); 7874 vmx_l1d_flush_pages = NULL; 7875 } 7876 /* Restore state so sysfs ignores VMX */ 7877 l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_AUTO; 7878 } 7879 7880 static void vmx_exit(void) 7881 { 7882 #ifdef CONFIG_KEXEC_CORE 7883 RCU_INIT_POINTER(crash_vmclear_loaded_vmcss, NULL); 7884 synchronize_rcu(); 7885 #endif 7886 7887 kvm_exit(); 7888 7889 #if IS_ENABLED(CONFIG_HYPERV) 7890 if (static_branch_unlikely(&enable_evmcs)) { 7891 int cpu; 7892 struct hv_vp_assist_page *vp_ap; 7893 /* 7894 * Reset everything to support using non-enlightened VMCS 7895 * access later (e.g. when we reload the module with 7896 * enlightened_vmcs=0) 7897 */ 7898 for_each_online_cpu(cpu) { 7899 vp_ap = hv_get_vp_assist_page(cpu); 7900 7901 if (!vp_ap) 7902 continue; 7903 7904 vp_ap->nested_control.features.directhypercall = 0; 7905 vp_ap->current_nested_vmcs = 0; 7906 vp_ap->enlighten_vmentry = 0; 7907 } 7908 7909 static_branch_disable(&enable_evmcs); 7910 } 7911 #endif 7912 vmx_cleanup_l1d_flush(); 7913 } 7914 module_exit(vmx_exit); 7915 7916 static int __init vmx_init(void) 7917 { 7918 int r; 7919 7920 #if IS_ENABLED(CONFIG_HYPERV) 7921 /* 7922 * Enlightened VMCS usage should be recommended and the host needs 7923 * to support eVMCS v1 or above. We can also disable eVMCS support 7924 * with module parameter. 7925 */ 7926 if (enlightened_vmcs && 7927 ms_hyperv.hints & HV_X64_ENLIGHTENED_VMCS_RECOMMENDED && 7928 (ms_hyperv.nested_features & HV_X64_ENLIGHTENED_VMCS_VERSION) >= 7929 KVM_EVMCS_VERSION) { 7930 int cpu; 7931 7932 /* Check that we have assist pages on all online CPUs */ 7933 for_each_online_cpu(cpu) { 7934 if (!hv_get_vp_assist_page(cpu)) { 7935 enlightened_vmcs = false; 7936 break; 7937 } 7938 } 7939 7940 if (enlightened_vmcs) { 7941 pr_info("KVM: vmx: using Hyper-V Enlightened VMCS\n"); 7942 static_branch_enable(&enable_evmcs); 7943 } 7944 7945 if (ms_hyperv.nested_features & HV_X64_NESTED_DIRECT_FLUSH) 7946 vmx_x86_ops.enable_direct_tlbflush 7947 = hv_enable_direct_tlbflush; 7948 7949 } else { 7950 enlightened_vmcs = false; 7951 } 7952 #endif 7953 7954 r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx), 7955 __alignof__(struct vcpu_vmx), THIS_MODULE); 7956 if (r) 7957 return r; 7958 7959 /* 7960 * Must be called after kvm_init() so enable_ept is properly set 7961 * up. Hand the parameter mitigation value in which was stored in 7962 * the pre module init parser. If no parameter was given, it will 7963 * contain 'auto' which will be turned into the default 'cond' 7964 * mitigation mode. 7965 */ 7966 r = vmx_setup_l1d_flush(vmentry_l1d_flush_param); 7967 if (r) { 7968 vmx_exit(); 7969 return r; 7970 } 7971 7972 #ifdef CONFIG_KEXEC_CORE 7973 rcu_assign_pointer(crash_vmclear_loaded_vmcss, 7974 crash_vmclear_local_loaded_vmcss); 7975 #endif 7976 vmx_check_vmcs12_offsets(); 7977 7978 return 0; 7979 } 7980 module_init(vmx_init); 7981