1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Kernel-based Virtual Machine driver for Linux 4 * 5 * This module enables machines with Intel VT-x extensions to run virtual 6 * machines without emulation or binary translation. 7 * 8 * Copyright (C) 2006 Qumranet, Inc. 9 * Copyright 2010 Red Hat, Inc. and/or its affiliates. 10 * 11 * Authors: 12 * Avi Kivity <avi@qumranet.com> 13 * Yaniv Kamay <yaniv@qumranet.com> 14 */ 15 16 #include <linux/frame.h> 17 #include <linux/highmem.h> 18 #include <linux/hrtimer.h> 19 #include <linux/kernel.h> 20 #include <linux/kvm_host.h> 21 #include <linux/module.h> 22 #include <linux/moduleparam.h> 23 #include <linux/mod_devicetable.h> 24 #include <linux/mm.h> 25 #include <linux/sched.h> 26 #include <linux/sched/smt.h> 27 #include <linux/slab.h> 28 #include <linux/tboot.h> 29 #include <linux/trace_events.h> 30 31 #include <asm/apic.h> 32 #include <asm/asm.h> 33 #include <asm/cpu.h> 34 #include <asm/cpu_device_id.h> 35 #include <asm/debugreg.h> 36 #include <asm/desc.h> 37 #include <asm/fpu/internal.h> 38 #include <asm/io.h> 39 #include <asm/irq_remapping.h> 40 #include <asm/kexec.h> 41 #include <asm/perf_event.h> 42 #include <asm/mce.h> 43 #include <asm/mmu_context.h> 44 #include <asm/mshyperv.h> 45 #include <asm/mwait.h> 46 #include <asm/spec-ctrl.h> 47 #include <asm/virtext.h> 48 #include <asm/vmx.h> 49 50 #include "capabilities.h" 51 #include "cpuid.h" 52 #include "evmcs.h" 53 #include "irq.h" 54 #include "kvm_cache_regs.h" 55 #include "lapic.h" 56 #include "mmu.h" 57 #include "nested.h" 58 #include "ops.h" 59 #include "pmu.h" 60 #include "trace.h" 61 #include "vmcs.h" 62 #include "vmcs12.h" 63 #include "vmx.h" 64 #include "x86.h" 65 66 MODULE_AUTHOR("Qumranet"); 67 MODULE_LICENSE("GPL"); 68 69 #ifdef MODULE 70 static const struct x86_cpu_id vmx_cpu_id[] = { 71 X86_MATCH_FEATURE(X86_FEATURE_VMX, NULL), 72 {} 73 }; 74 MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id); 75 #endif 76 77 bool __read_mostly enable_vpid = 1; 78 module_param_named(vpid, enable_vpid, bool, 0444); 79 80 static bool __read_mostly enable_vnmi = 1; 81 module_param_named(vnmi, enable_vnmi, bool, S_IRUGO); 82 83 bool __read_mostly flexpriority_enabled = 1; 84 module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO); 85 86 bool __read_mostly enable_ept = 1; 87 module_param_named(ept, enable_ept, bool, S_IRUGO); 88 89 bool __read_mostly enable_unrestricted_guest = 1; 90 module_param_named(unrestricted_guest, 91 enable_unrestricted_guest, bool, S_IRUGO); 92 93 bool __read_mostly enable_ept_ad_bits = 1; 94 module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO); 95 96 static bool __read_mostly emulate_invalid_guest_state = true; 97 module_param(emulate_invalid_guest_state, bool, S_IRUGO); 98 99 static bool __read_mostly fasteoi = 1; 100 module_param(fasteoi, bool, S_IRUGO); 101 102 bool __read_mostly enable_apicv = 1; 103 module_param(enable_apicv, bool, S_IRUGO); 104 105 /* 106 * If nested=1, nested virtualization is supported, i.e., guests may use 107 * VMX and be a hypervisor for its own guests. If nested=0, guests may not 108 * use VMX instructions. 109 */ 110 static bool __read_mostly nested = 1; 111 module_param(nested, bool, S_IRUGO); 112 113 bool __read_mostly enable_pml = 1; 114 module_param_named(pml, enable_pml, bool, S_IRUGO); 115 116 static bool __read_mostly dump_invalid_vmcs = 0; 117 module_param(dump_invalid_vmcs, bool, 0644); 118 119 #define MSR_BITMAP_MODE_X2APIC 1 120 #define MSR_BITMAP_MODE_X2APIC_APICV 2 121 122 #define KVM_VMX_TSC_MULTIPLIER_MAX 0xffffffffffffffffULL 123 124 /* Guest_tsc -> host_tsc conversion requires 64-bit division. */ 125 static int __read_mostly cpu_preemption_timer_multi; 126 static bool __read_mostly enable_preemption_timer = 1; 127 #ifdef CONFIG_X86_64 128 module_param_named(preemption_timer, enable_preemption_timer, bool, S_IRUGO); 129 #endif 130 131 #define KVM_VM_CR0_ALWAYS_OFF (X86_CR0_NW | X86_CR0_CD) 132 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST X86_CR0_NE 133 #define KVM_VM_CR0_ALWAYS_ON \ 134 (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | \ 135 X86_CR0_WP | X86_CR0_PG | X86_CR0_PE) 136 #define KVM_CR4_GUEST_OWNED_BITS \ 137 (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \ 138 | X86_CR4_OSXMMEXCPT | X86_CR4_LA57 | X86_CR4_TSD) 139 140 #define KVM_VM_CR4_ALWAYS_ON_UNRESTRICTED_GUEST X86_CR4_VMXE 141 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE) 142 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE) 143 144 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM)) 145 146 #define MSR_IA32_RTIT_STATUS_MASK (~(RTIT_STATUS_FILTEREN | \ 147 RTIT_STATUS_CONTEXTEN | RTIT_STATUS_TRIGGEREN | \ 148 RTIT_STATUS_ERROR | RTIT_STATUS_STOPPED | \ 149 RTIT_STATUS_BYTECNT)) 150 151 #define MSR_IA32_RTIT_OUTPUT_BASE_MASK \ 152 (~((1UL << cpuid_query_maxphyaddr(vcpu)) - 1) | 0x7f) 153 154 /* 155 * These 2 parameters are used to config the controls for Pause-Loop Exiting: 156 * ple_gap: upper bound on the amount of time between two successive 157 * executions of PAUSE in a loop. Also indicate if ple enabled. 158 * According to test, this time is usually smaller than 128 cycles. 159 * ple_window: upper bound on the amount of time a guest is allowed to execute 160 * in a PAUSE loop. Tests indicate that most spinlocks are held for 161 * less than 2^12 cycles 162 * Time is measured based on a counter that runs at the same rate as the TSC, 163 * refer SDM volume 3b section 21.6.13 & 22.1.3. 164 */ 165 static unsigned int ple_gap = KVM_DEFAULT_PLE_GAP; 166 module_param(ple_gap, uint, 0444); 167 168 static unsigned int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW; 169 module_param(ple_window, uint, 0444); 170 171 /* Default doubles per-vcpu window every exit. */ 172 static unsigned int ple_window_grow = KVM_DEFAULT_PLE_WINDOW_GROW; 173 module_param(ple_window_grow, uint, 0444); 174 175 /* Default resets per-vcpu window every exit to ple_window. */ 176 static unsigned int ple_window_shrink = KVM_DEFAULT_PLE_WINDOW_SHRINK; 177 module_param(ple_window_shrink, uint, 0444); 178 179 /* Default is to compute the maximum so we can never overflow. */ 180 static unsigned int ple_window_max = KVM_VMX_DEFAULT_PLE_WINDOW_MAX; 181 module_param(ple_window_max, uint, 0444); 182 183 /* Default is SYSTEM mode, 1 for host-guest mode */ 184 int __read_mostly pt_mode = PT_MODE_SYSTEM; 185 module_param(pt_mode, int, S_IRUGO); 186 187 static DEFINE_STATIC_KEY_FALSE(vmx_l1d_should_flush); 188 static DEFINE_STATIC_KEY_FALSE(vmx_l1d_flush_cond); 189 static DEFINE_MUTEX(vmx_l1d_flush_mutex); 190 191 /* Storage for pre module init parameter parsing */ 192 static enum vmx_l1d_flush_state __read_mostly vmentry_l1d_flush_param = VMENTER_L1D_FLUSH_AUTO; 193 194 static const struct { 195 const char *option; 196 bool for_parse; 197 } vmentry_l1d_param[] = { 198 [VMENTER_L1D_FLUSH_AUTO] = {"auto", true}, 199 [VMENTER_L1D_FLUSH_NEVER] = {"never", true}, 200 [VMENTER_L1D_FLUSH_COND] = {"cond", true}, 201 [VMENTER_L1D_FLUSH_ALWAYS] = {"always", true}, 202 [VMENTER_L1D_FLUSH_EPT_DISABLED] = {"EPT disabled", false}, 203 [VMENTER_L1D_FLUSH_NOT_REQUIRED] = {"not required", false}, 204 }; 205 206 #define L1D_CACHE_ORDER 4 207 static void *vmx_l1d_flush_pages; 208 209 static int vmx_setup_l1d_flush(enum vmx_l1d_flush_state l1tf) 210 { 211 struct page *page; 212 unsigned int i; 213 214 if (!boot_cpu_has_bug(X86_BUG_L1TF)) { 215 l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_NOT_REQUIRED; 216 return 0; 217 } 218 219 if (!enable_ept) { 220 l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_EPT_DISABLED; 221 return 0; 222 } 223 224 if (boot_cpu_has(X86_FEATURE_ARCH_CAPABILITIES)) { 225 u64 msr; 226 227 rdmsrl(MSR_IA32_ARCH_CAPABILITIES, msr); 228 if (msr & ARCH_CAP_SKIP_VMENTRY_L1DFLUSH) { 229 l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_NOT_REQUIRED; 230 return 0; 231 } 232 } 233 234 /* If set to auto use the default l1tf mitigation method */ 235 if (l1tf == VMENTER_L1D_FLUSH_AUTO) { 236 switch (l1tf_mitigation) { 237 case L1TF_MITIGATION_OFF: 238 l1tf = VMENTER_L1D_FLUSH_NEVER; 239 break; 240 case L1TF_MITIGATION_FLUSH_NOWARN: 241 case L1TF_MITIGATION_FLUSH: 242 case L1TF_MITIGATION_FLUSH_NOSMT: 243 l1tf = VMENTER_L1D_FLUSH_COND; 244 break; 245 case L1TF_MITIGATION_FULL: 246 case L1TF_MITIGATION_FULL_FORCE: 247 l1tf = VMENTER_L1D_FLUSH_ALWAYS; 248 break; 249 } 250 } else if (l1tf_mitigation == L1TF_MITIGATION_FULL_FORCE) { 251 l1tf = VMENTER_L1D_FLUSH_ALWAYS; 252 } 253 254 if (l1tf != VMENTER_L1D_FLUSH_NEVER && !vmx_l1d_flush_pages && 255 !boot_cpu_has(X86_FEATURE_FLUSH_L1D)) { 256 /* 257 * This allocation for vmx_l1d_flush_pages is not tied to a VM 258 * lifetime and so should not be charged to a memcg. 259 */ 260 page = alloc_pages(GFP_KERNEL, L1D_CACHE_ORDER); 261 if (!page) 262 return -ENOMEM; 263 vmx_l1d_flush_pages = page_address(page); 264 265 /* 266 * Initialize each page with a different pattern in 267 * order to protect against KSM in the nested 268 * virtualization case. 269 */ 270 for (i = 0; i < 1u << L1D_CACHE_ORDER; ++i) { 271 memset(vmx_l1d_flush_pages + i * PAGE_SIZE, i + 1, 272 PAGE_SIZE); 273 } 274 } 275 276 l1tf_vmx_mitigation = l1tf; 277 278 if (l1tf != VMENTER_L1D_FLUSH_NEVER) 279 static_branch_enable(&vmx_l1d_should_flush); 280 else 281 static_branch_disable(&vmx_l1d_should_flush); 282 283 if (l1tf == VMENTER_L1D_FLUSH_COND) 284 static_branch_enable(&vmx_l1d_flush_cond); 285 else 286 static_branch_disable(&vmx_l1d_flush_cond); 287 return 0; 288 } 289 290 static int vmentry_l1d_flush_parse(const char *s) 291 { 292 unsigned int i; 293 294 if (s) { 295 for (i = 0; i < ARRAY_SIZE(vmentry_l1d_param); i++) { 296 if (vmentry_l1d_param[i].for_parse && 297 sysfs_streq(s, vmentry_l1d_param[i].option)) 298 return i; 299 } 300 } 301 return -EINVAL; 302 } 303 304 static int vmentry_l1d_flush_set(const char *s, const struct kernel_param *kp) 305 { 306 int l1tf, ret; 307 308 l1tf = vmentry_l1d_flush_parse(s); 309 if (l1tf < 0) 310 return l1tf; 311 312 if (!boot_cpu_has(X86_BUG_L1TF)) 313 return 0; 314 315 /* 316 * Has vmx_init() run already? If not then this is the pre init 317 * parameter parsing. In that case just store the value and let 318 * vmx_init() do the proper setup after enable_ept has been 319 * established. 320 */ 321 if (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_AUTO) { 322 vmentry_l1d_flush_param = l1tf; 323 return 0; 324 } 325 326 mutex_lock(&vmx_l1d_flush_mutex); 327 ret = vmx_setup_l1d_flush(l1tf); 328 mutex_unlock(&vmx_l1d_flush_mutex); 329 return ret; 330 } 331 332 static int vmentry_l1d_flush_get(char *s, const struct kernel_param *kp) 333 { 334 if (WARN_ON_ONCE(l1tf_vmx_mitigation >= ARRAY_SIZE(vmentry_l1d_param))) 335 return sprintf(s, "???\n"); 336 337 return sprintf(s, "%s\n", vmentry_l1d_param[l1tf_vmx_mitigation].option); 338 } 339 340 static const struct kernel_param_ops vmentry_l1d_flush_ops = { 341 .set = vmentry_l1d_flush_set, 342 .get = vmentry_l1d_flush_get, 343 }; 344 module_param_cb(vmentry_l1d_flush, &vmentry_l1d_flush_ops, NULL, 0644); 345 346 static bool guest_state_valid(struct kvm_vcpu *vcpu); 347 static u32 vmx_segment_access_rights(struct kvm_segment *var); 348 static __always_inline void vmx_disable_intercept_for_msr(unsigned long *msr_bitmap, 349 u32 msr, int type); 350 351 void vmx_vmexit(void); 352 353 #define vmx_insn_failed(fmt...) \ 354 do { \ 355 WARN_ONCE(1, fmt); \ 356 pr_warn_ratelimited(fmt); \ 357 } while (0) 358 359 asmlinkage void vmread_error(unsigned long field, bool fault) 360 { 361 if (fault) 362 kvm_spurious_fault(); 363 else 364 vmx_insn_failed("kvm: vmread failed: field=%lx\n", field); 365 } 366 367 noinline void vmwrite_error(unsigned long field, unsigned long value) 368 { 369 vmx_insn_failed("kvm: vmwrite failed: field=%lx val=%lx err=%d\n", 370 field, value, vmcs_read32(VM_INSTRUCTION_ERROR)); 371 } 372 373 noinline void vmclear_error(struct vmcs *vmcs, u64 phys_addr) 374 { 375 vmx_insn_failed("kvm: vmclear failed: %p/%llx\n", vmcs, phys_addr); 376 } 377 378 noinline void vmptrld_error(struct vmcs *vmcs, u64 phys_addr) 379 { 380 vmx_insn_failed("kvm: vmptrld failed: %p/%llx\n", vmcs, phys_addr); 381 } 382 383 noinline void invvpid_error(unsigned long ext, u16 vpid, gva_t gva) 384 { 385 vmx_insn_failed("kvm: invvpid failed: ext=0x%lx vpid=%u gva=0x%lx\n", 386 ext, vpid, gva); 387 } 388 389 noinline void invept_error(unsigned long ext, u64 eptp, gpa_t gpa) 390 { 391 vmx_insn_failed("kvm: invept failed: ext=0x%lx eptp=%llx gpa=0x%llx\n", 392 ext, eptp, gpa); 393 } 394 395 static DEFINE_PER_CPU(struct vmcs *, vmxarea); 396 DEFINE_PER_CPU(struct vmcs *, current_vmcs); 397 /* 398 * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed 399 * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it. 400 */ 401 static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu); 402 403 /* 404 * We maintian a per-CPU linked-list of vCPU, so in wakeup_handler() we 405 * can find which vCPU should be waken up. 406 */ 407 static DEFINE_PER_CPU(struct list_head, blocked_vcpu_on_cpu); 408 static DEFINE_PER_CPU(spinlock_t, blocked_vcpu_on_cpu_lock); 409 410 static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS); 411 static DEFINE_SPINLOCK(vmx_vpid_lock); 412 413 struct vmcs_config vmcs_config; 414 struct vmx_capability vmx_capability; 415 416 #define VMX_SEGMENT_FIELD(seg) \ 417 [VCPU_SREG_##seg] = { \ 418 .selector = GUEST_##seg##_SELECTOR, \ 419 .base = GUEST_##seg##_BASE, \ 420 .limit = GUEST_##seg##_LIMIT, \ 421 .ar_bytes = GUEST_##seg##_AR_BYTES, \ 422 } 423 424 static const struct kvm_vmx_segment_field { 425 unsigned selector; 426 unsigned base; 427 unsigned limit; 428 unsigned ar_bytes; 429 } kvm_vmx_segment_fields[] = { 430 VMX_SEGMENT_FIELD(CS), 431 VMX_SEGMENT_FIELD(DS), 432 VMX_SEGMENT_FIELD(ES), 433 VMX_SEGMENT_FIELD(FS), 434 VMX_SEGMENT_FIELD(GS), 435 VMX_SEGMENT_FIELD(SS), 436 VMX_SEGMENT_FIELD(TR), 437 VMX_SEGMENT_FIELD(LDTR), 438 }; 439 440 u64 host_efer; 441 static unsigned long host_idt_base; 442 443 /* 444 * Though SYSCALL is only supported in 64-bit mode on Intel CPUs, kvm 445 * will emulate SYSCALL in legacy mode if the vendor string in guest 446 * CPUID.0:{EBX,ECX,EDX} is "AuthenticAMD" or "AMDisbetter!" To 447 * support this emulation, IA32_STAR must always be included in 448 * vmx_msr_index[], even in i386 builds. 449 */ 450 const u32 vmx_msr_index[] = { 451 #ifdef CONFIG_X86_64 452 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR, 453 #endif 454 MSR_EFER, MSR_TSC_AUX, MSR_STAR, 455 MSR_IA32_TSX_CTRL, 456 }; 457 458 #if IS_ENABLED(CONFIG_HYPERV) 459 static bool __read_mostly enlightened_vmcs = true; 460 module_param(enlightened_vmcs, bool, 0444); 461 462 /* check_ept_pointer() should be under protection of ept_pointer_lock. */ 463 static void check_ept_pointer_match(struct kvm *kvm) 464 { 465 struct kvm_vcpu *vcpu; 466 u64 tmp_eptp = INVALID_PAGE; 467 int i; 468 469 kvm_for_each_vcpu(i, vcpu, kvm) { 470 if (!VALID_PAGE(tmp_eptp)) { 471 tmp_eptp = to_vmx(vcpu)->ept_pointer; 472 } else if (tmp_eptp != to_vmx(vcpu)->ept_pointer) { 473 to_kvm_vmx(kvm)->ept_pointers_match 474 = EPT_POINTERS_MISMATCH; 475 return; 476 } 477 } 478 479 to_kvm_vmx(kvm)->ept_pointers_match = EPT_POINTERS_MATCH; 480 } 481 482 static int kvm_fill_hv_flush_list_func(struct hv_guest_mapping_flush_list *flush, 483 void *data) 484 { 485 struct kvm_tlb_range *range = data; 486 487 return hyperv_fill_flush_guest_mapping_list(flush, range->start_gfn, 488 range->pages); 489 } 490 491 static inline int __hv_remote_flush_tlb_with_range(struct kvm *kvm, 492 struct kvm_vcpu *vcpu, struct kvm_tlb_range *range) 493 { 494 u64 ept_pointer = to_vmx(vcpu)->ept_pointer; 495 496 /* 497 * FLUSH_GUEST_PHYSICAL_ADDRESS_SPACE hypercall needs address 498 * of the base of EPT PML4 table, strip off EPT configuration 499 * information. 500 */ 501 if (range) 502 return hyperv_flush_guest_mapping_range(ept_pointer & PAGE_MASK, 503 kvm_fill_hv_flush_list_func, (void *)range); 504 else 505 return hyperv_flush_guest_mapping(ept_pointer & PAGE_MASK); 506 } 507 508 static int hv_remote_flush_tlb_with_range(struct kvm *kvm, 509 struct kvm_tlb_range *range) 510 { 511 struct kvm_vcpu *vcpu; 512 int ret = 0, i; 513 514 spin_lock(&to_kvm_vmx(kvm)->ept_pointer_lock); 515 516 if (to_kvm_vmx(kvm)->ept_pointers_match == EPT_POINTERS_CHECK) 517 check_ept_pointer_match(kvm); 518 519 if (to_kvm_vmx(kvm)->ept_pointers_match != EPT_POINTERS_MATCH) { 520 kvm_for_each_vcpu(i, vcpu, kvm) { 521 /* If ept_pointer is invalid pointer, bypass flush request. */ 522 if (VALID_PAGE(to_vmx(vcpu)->ept_pointer)) 523 ret |= __hv_remote_flush_tlb_with_range( 524 kvm, vcpu, range); 525 } 526 } else { 527 ret = __hv_remote_flush_tlb_with_range(kvm, 528 kvm_get_vcpu(kvm, 0), range); 529 } 530 531 spin_unlock(&to_kvm_vmx(kvm)->ept_pointer_lock); 532 return ret; 533 } 534 static int hv_remote_flush_tlb(struct kvm *kvm) 535 { 536 return hv_remote_flush_tlb_with_range(kvm, NULL); 537 } 538 539 static int hv_enable_direct_tlbflush(struct kvm_vcpu *vcpu) 540 { 541 struct hv_enlightened_vmcs *evmcs; 542 struct hv_partition_assist_pg **p_hv_pa_pg = 543 &vcpu->kvm->arch.hyperv.hv_pa_pg; 544 /* 545 * Synthetic VM-Exit is not enabled in current code and so All 546 * evmcs in singe VM shares same assist page. 547 */ 548 if (!*p_hv_pa_pg) 549 *p_hv_pa_pg = kzalloc(PAGE_SIZE, GFP_KERNEL); 550 551 if (!*p_hv_pa_pg) 552 return -ENOMEM; 553 554 evmcs = (struct hv_enlightened_vmcs *)to_vmx(vcpu)->loaded_vmcs->vmcs; 555 556 evmcs->partition_assist_page = 557 __pa(*p_hv_pa_pg); 558 evmcs->hv_vm_id = (unsigned long)vcpu->kvm; 559 evmcs->hv_enlightenments_control.nested_flush_hypercall = 1; 560 561 return 0; 562 } 563 564 #endif /* IS_ENABLED(CONFIG_HYPERV) */ 565 566 /* 567 * Comment's format: document - errata name - stepping - processor name. 568 * Refer from 569 * https://www.virtualbox.org/svn/vbox/trunk/src/VBox/VMM/VMMR0/HMR0.cpp 570 */ 571 static u32 vmx_preemption_cpu_tfms[] = { 572 /* 323344.pdf - BA86 - D0 - Xeon 7500 Series */ 573 0x000206E6, 574 /* 323056.pdf - AAX65 - C2 - Xeon L3406 */ 575 /* 322814.pdf - AAT59 - C2 - i7-600, i5-500, i5-400 and i3-300 Mobile */ 576 /* 322911.pdf - AAU65 - C2 - i5-600, i3-500 Desktop and Pentium G6950 */ 577 0x00020652, 578 /* 322911.pdf - AAU65 - K0 - i5-600, i3-500 Desktop and Pentium G6950 */ 579 0x00020655, 580 /* 322373.pdf - AAO95 - B1 - Xeon 3400 Series */ 581 /* 322166.pdf - AAN92 - B1 - i7-800 and i5-700 Desktop */ 582 /* 583 * 320767.pdf - AAP86 - B1 - 584 * i7-900 Mobile Extreme, i7-800 and i7-700 Mobile 585 */ 586 0x000106E5, 587 /* 321333.pdf - AAM126 - C0 - Xeon 3500 */ 588 0x000106A0, 589 /* 321333.pdf - AAM126 - C1 - Xeon 3500 */ 590 0x000106A1, 591 /* 320836.pdf - AAJ124 - C0 - i7-900 Desktop Extreme and i7-900 Desktop */ 592 0x000106A4, 593 /* 321333.pdf - AAM126 - D0 - Xeon 3500 */ 594 /* 321324.pdf - AAK139 - D0 - Xeon 5500 */ 595 /* 320836.pdf - AAJ124 - D0 - i7-900 Extreme and i7-900 Desktop */ 596 0x000106A5, 597 /* Xeon E3-1220 V2 */ 598 0x000306A8, 599 }; 600 601 static inline bool cpu_has_broken_vmx_preemption_timer(void) 602 { 603 u32 eax = cpuid_eax(0x00000001), i; 604 605 /* Clear the reserved bits */ 606 eax &= ~(0x3U << 14 | 0xfU << 28); 607 for (i = 0; i < ARRAY_SIZE(vmx_preemption_cpu_tfms); i++) 608 if (eax == vmx_preemption_cpu_tfms[i]) 609 return true; 610 611 return false; 612 } 613 614 static inline bool cpu_need_virtualize_apic_accesses(struct kvm_vcpu *vcpu) 615 { 616 return flexpriority_enabled && lapic_in_kernel(vcpu); 617 } 618 619 static inline bool report_flexpriority(void) 620 { 621 return flexpriority_enabled; 622 } 623 624 static inline int __find_msr_index(struct vcpu_vmx *vmx, u32 msr) 625 { 626 int i; 627 628 for (i = 0; i < vmx->nmsrs; ++i) 629 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr) 630 return i; 631 return -1; 632 } 633 634 struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr) 635 { 636 int i; 637 638 i = __find_msr_index(vmx, msr); 639 if (i >= 0) 640 return &vmx->guest_msrs[i]; 641 return NULL; 642 } 643 644 static int vmx_set_guest_msr(struct vcpu_vmx *vmx, struct shared_msr_entry *msr, u64 data) 645 { 646 int ret = 0; 647 648 u64 old_msr_data = msr->data; 649 msr->data = data; 650 if (msr - vmx->guest_msrs < vmx->save_nmsrs) { 651 preempt_disable(); 652 ret = kvm_set_shared_msr(msr->index, msr->data, 653 msr->mask); 654 preempt_enable(); 655 if (ret) 656 msr->data = old_msr_data; 657 } 658 return ret; 659 } 660 661 void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs) 662 { 663 vmcs_clear(loaded_vmcs->vmcs); 664 if (loaded_vmcs->shadow_vmcs && loaded_vmcs->launched) 665 vmcs_clear(loaded_vmcs->shadow_vmcs); 666 loaded_vmcs->cpu = -1; 667 loaded_vmcs->launched = 0; 668 } 669 670 #ifdef CONFIG_KEXEC_CORE 671 /* 672 * This bitmap is used to indicate whether the vmclear 673 * operation is enabled on all cpus. All disabled by 674 * default. 675 */ 676 static cpumask_t crash_vmclear_enabled_bitmap = CPU_MASK_NONE; 677 678 static inline void crash_enable_local_vmclear(int cpu) 679 { 680 cpumask_set_cpu(cpu, &crash_vmclear_enabled_bitmap); 681 } 682 683 static inline void crash_disable_local_vmclear(int cpu) 684 { 685 cpumask_clear_cpu(cpu, &crash_vmclear_enabled_bitmap); 686 } 687 688 static inline int crash_local_vmclear_enabled(int cpu) 689 { 690 return cpumask_test_cpu(cpu, &crash_vmclear_enabled_bitmap); 691 } 692 693 static void crash_vmclear_local_loaded_vmcss(void) 694 { 695 int cpu = raw_smp_processor_id(); 696 struct loaded_vmcs *v; 697 698 if (!crash_local_vmclear_enabled(cpu)) 699 return; 700 701 list_for_each_entry(v, &per_cpu(loaded_vmcss_on_cpu, cpu), 702 loaded_vmcss_on_cpu_link) 703 vmcs_clear(v->vmcs); 704 } 705 #else 706 static inline void crash_enable_local_vmclear(int cpu) { } 707 static inline void crash_disable_local_vmclear(int cpu) { } 708 #endif /* CONFIG_KEXEC_CORE */ 709 710 static void __loaded_vmcs_clear(void *arg) 711 { 712 struct loaded_vmcs *loaded_vmcs = arg; 713 int cpu = raw_smp_processor_id(); 714 715 if (loaded_vmcs->cpu != cpu) 716 return; /* vcpu migration can race with cpu offline */ 717 if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs) 718 per_cpu(current_vmcs, cpu) = NULL; 719 crash_disable_local_vmclear(cpu); 720 list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link); 721 722 /* 723 * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link 724 * is before setting loaded_vmcs->vcpu to -1 which is done in 725 * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist 726 * then adds the vmcs into percpu list before it is deleted. 727 */ 728 smp_wmb(); 729 730 loaded_vmcs_init(loaded_vmcs); 731 crash_enable_local_vmclear(cpu); 732 } 733 734 void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs) 735 { 736 int cpu = loaded_vmcs->cpu; 737 738 if (cpu != -1) 739 smp_call_function_single(cpu, 740 __loaded_vmcs_clear, loaded_vmcs, 1); 741 } 742 743 static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg, 744 unsigned field) 745 { 746 bool ret; 747 u32 mask = 1 << (seg * SEG_FIELD_NR + field); 748 749 if (!kvm_register_is_available(&vmx->vcpu, VCPU_EXREG_SEGMENTS)) { 750 kvm_register_mark_available(&vmx->vcpu, VCPU_EXREG_SEGMENTS); 751 vmx->segment_cache.bitmask = 0; 752 } 753 ret = vmx->segment_cache.bitmask & mask; 754 vmx->segment_cache.bitmask |= mask; 755 return ret; 756 } 757 758 static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg) 759 { 760 u16 *p = &vmx->segment_cache.seg[seg].selector; 761 762 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL)) 763 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector); 764 return *p; 765 } 766 767 static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg) 768 { 769 ulong *p = &vmx->segment_cache.seg[seg].base; 770 771 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE)) 772 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base); 773 return *p; 774 } 775 776 static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg) 777 { 778 u32 *p = &vmx->segment_cache.seg[seg].limit; 779 780 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT)) 781 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit); 782 return *p; 783 } 784 785 static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg) 786 { 787 u32 *p = &vmx->segment_cache.seg[seg].ar; 788 789 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR)) 790 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes); 791 return *p; 792 } 793 794 void update_exception_bitmap(struct kvm_vcpu *vcpu) 795 { 796 u32 eb; 797 798 eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) | 799 (1u << DB_VECTOR) | (1u << AC_VECTOR); 800 /* 801 * Guest access to VMware backdoor ports could legitimately 802 * trigger #GP because of TSS I/O permission bitmap. 803 * We intercept those #GP and allow access to them anyway 804 * as VMware does. 805 */ 806 if (enable_vmware_backdoor) 807 eb |= (1u << GP_VECTOR); 808 if ((vcpu->guest_debug & 809 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) == 810 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) 811 eb |= 1u << BP_VECTOR; 812 if (to_vmx(vcpu)->rmode.vm86_active) 813 eb = ~0; 814 if (enable_ept) 815 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */ 816 817 /* When we are running a nested L2 guest and L1 specified for it a 818 * certain exception bitmap, we must trap the same exceptions and pass 819 * them to L1. When running L2, we will only handle the exceptions 820 * specified above if L1 did not want them. 821 */ 822 if (is_guest_mode(vcpu)) 823 eb |= get_vmcs12(vcpu)->exception_bitmap; 824 825 vmcs_write32(EXCEPTION_BITMAP, eb); 826 } 827 828 /* 829 * Check if MSR is intercepted for currently loaded MSR bitmap. 830 */ 831 static bool msr_write_intercepted(struct kvm_vcpu *vcpu, u32 msr) 832 { 833 unsigned long *msr_bitmap; 834 int f = sizeof(unsigned long); 835 836 if (!cpu_has_vmx_msr_bitmap()) 837 return true; 838 839 msr_bitmap = to_vmx(vcpu)->loaded_vmcs->msr_bitmap; 840 841 if (msr <= 0x1fff) { 842 return !!test_bit(msr, msr_bitmap + 0x800 / f); 843 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) { 844 msr &= 0x1fff; 845 return !!test_bit(msr, msr_bitmap + 0xc00 / f); 846 } 847 848 return true; 849 } 850 851 static void clear_atomic_switch_msr_special(struct vcpu_vmx *vmx, 852 unsigned long entry, unsigned long exit) 853 { 854 vm_entry_controls_clearbit(vmx, entry); 855 vm_exit_controls_clearbit(vmx, exit); 856 } 857 858 int vmx_find_msr_index(struct vmx_msrs *m, u32 msr) 859 { 860 unsigned int i; 861 862 for (i = 0; i < m->nr; ++i) { 863 if (m->val[i].index == msr) 864 return i; 865 } 866 return -ENOENT; 867 } 868 869 static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr) 870 { 871 int i; 872 struct msr_autoload *m = &vmx->msr_autoload; 873 874 switch (msr) { 875 case MSR_EFER: 876 if (cpu_has_load_ia32_efer()) { 877 clear_atomic_switch_msr_special(vmx, 878 VM_ENTRY_LOAD_IA32_EFER, 879 VM_EXIT_LOAD_IA32_EFER); 880 return; 881 } 882 break; 883 case MSR_CORE_PERF_GLOBAL_CTRL: 884 if (cpu_has_load_perf_global_ctrl()) { 885 clear_atomic_switch_msr_special(vmx, 886 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL, 887 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL); 888 return; 889 } 890 break; 891 } 892 i = vmx_find_msr_index(&m->guest, msr); 893 if (i < 0) 894 goto skip_guest; 895 --m->guest.nr; 896 m->guest.val[i] = m->guest.val[m->guest.nr]; 897 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->guest.nr); 898 899 skip_guest: 900 i = vmx_find_msr_index(&m->host, msr); 901 if (i < 0) 902 return; 903 904 --m->host.nr; 905 m->host.val[i] = m->host.val[m->host.nr]; 906 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->host.nr); 907 } 908 909 static void add_atomic_switch_msr_special(struct vcpu_vmx *vmx, 910 unsigned long entry, unsigned long exit, 911 unsigned long guest_val_vmcs, unsigned long host_val_vmcs, 912 u64 guest_val, u64 host_val) 913 { 914 vmcs_write64(guest_val_vmcs, guest_val); 915 if (host_val_vmcs != HOST_IA32_EFER) 916 vmcs_write64(host_val_vmcs, host_val); 917 vm_entry_controls_setbit(vmx, entry); 918 vm_exit_controls_setbit(vmx, exit); 919 } 920 921 static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr, 922 u64 guest_val, u64 host_val, bool entry_only) 923 { 924 int i, j = 0; 925 struct msr_autoload *m = &vmx->msr_autoload; 926 927 switch (msr) { 928 case MSR_EFER: 929 if (cpu_has_load_ia32_efer()) { 930 add_atomic_switch_msr_special(vmx, 931 VM_ENTRY_LOAD_IA32_EFER, 932 VM_EXIT_LOAD_IA32_EFER, 933 GUEST_IA32_EFER, 934 HOST_IA32_EFER, 935 guest_val, host_val); 936 return; 937 } 938 break; 939 case MSR_CORE_PERF_GLOBAL_CTRL: 940 if (cpu_has_load_perf_global_ctrl()) { 941 add_atomic_switch_msr_special(vmx, 942 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL, 943 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL, 944 GUEST_IA32_PERF_GLOBAL_CTRL, 945 HOST_IA32_PERF_GLOBAL_CTRL, 946 guest_val, host_val); 947 return; 948 } 949 break; 950 case MSR_IA32_PEBS_ENABLE: 951 /* PEBS needs a quiescent period after being disabled (to write 952 * a record). Disabling PEBS through VMX MSR swapping doesn't 953 * provide that period, so a CPU could write host's record into 954 * guest's memory. 955 */ 956 wrmsrl(MSR_IA32_PEBS_ENABLE, 0); 957 } 958 959 i = vmx_find_msr_index(&m->guest, msr); 960 if (!entry_only) 961 j = vmx_find_msr_index(&m->host, msr); 962 963 if ((i < 0 && m->guest.nr == NR_LOADSTORE_MSRS) || 964 (j < 0 && m->host.nr == NR_LOADSTORE_MSRS)) { 965 printk_once(KERN_WARNING "Not enough msr switch entries. " 966 "Can't add msr %x\n", msr); 967 return; 968 } 969 if (i < 0) { 970 i = m->guest.nr++; 971 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->guest.nr); 972 } 973 m->guest.val[i].index = msr; 974 m->guest.val[i].value = guest_val; 975 976 if (entry_only) 977 return; 978 979 if (j < 0) { 980 j = m->host.nr++; 981 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->host.nr); 982 } 983 m->host.val[j].index = msr; 984 m->host.val[j].value = host_val; 985 } 986 987 static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset) 988 { 989 u64 guest_efer = vmx->vcpu.arch.efer; 990 u64 ignore_bits = 0; 991 992 /* Shadow paging assumes NX to be available. */ 993 if (!enable_ept) 994 guest_efer |= EFER_NX; 995 996 /* 997 * LMA and LME handled by hardware; SCE meaningless outside long mode. 998 */ 999 ignore_bits |= EFER_SCE; 1000 #ifdef CONFIG_X86_64 1001 ignore_bits |= EFER_LMA | EFER_LME; 1002 /* SCE is meaningful only in long mode on Intel */ 1003 if (guest_efer & EFER_LMA) 1004 ignore_bits &= ~(u64)EFER_SCE; 1005 #endif 1006 1007 /* 1008 * On EPT, we can't emulate NX, so we must switch EFER atomically. 1009 * On CPUs that support "load IA32_EFER", always switch EFER 1010 * atomically, since it's faster than switching it manually. 1011 */ 1012 if (cpu_has_load_ia32_efer() || 1013 (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX))) { 1014 if (!(guest_efer & EFER_LMA)) 1015 guest_efer &= ~EFER_LME; 1016 if (guest_efer != host_efer) 1017 add_atomic_switch_msr(vmx, MSR_EFER, 1018 guest_efer, host_efer, false); 1019 else 1020 clear_atomic_switch_msr(vmx, MSR_EFER); 1021 return false; 1022 } else { 1023 clear_atomic_switch_msr(vmx, MSR_EFER); 1024 1025 guest_efer &= ~ignore_bits; 1026 guest_efer |= host_efer & ignore_bits; 1027 1028 vmx->guest_msrs[efer_offset].data = guest_efer; 1029 vmx->guest_msrs[efer_offset].mask = ~ignore_bits; 1030 1031 return true; 1032 } 1033 } 1034 1035 #ifdef CONFIG_X86_32 1036 /* 1037 * On 32-bit kernels, VM exits still load the FS and GS bases from the 1038 * VMCS rather than the segment table. KVM uses this helper to figure 1039 * out the current bases to poke them into the VMCS before entry. 1040 */ 1041 static unsigned long segment_base(u16 selector) 1042 { 1043 struct desc_struct *table; 1044 unsigned long v; 1045 1046 if (!(selector & ~SEGMENT_RPL_MASK)) 1047 return 0; 1048 1049 table = get_current_gdt_ro(); 1050 1051 if ((selector & SEGMENT_TI_MASK) == SEGMENT_LDT) { 1052 u16 ldt_selector = kvm_read_ldt(); 1053 1054 if (!(ldt_selector & ~SEGMENT_RPL_MASK)) 1055 return 0; 1056 1057 table = (struct desc_struct *)segment_base(ldt_selector); 1058 } 1059 v = get_desc_base(&table[selector >> 3]); 1060 return v; 1061 } 1062 #endif 1063 1064 static inline bool pt_can_write_msr(struct vcpu_vmx *vmx) 1065 { 1066 return (pt_mode == PT_MODE_HOST_GUEST) && 1067 !(vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN); 1068 } 1069 1070 static inline void pt_load_msr(struct pt_ctx *ctx, u32 addr_range) 1071 { 1072 u32 i; 1073 1074 wrmsrl(MSR_IA32_RTIT_STATUS, ctx->status); 1075 wrmsrl(MSR_IA32_RTIT_OUTPUT_BASE, ctx->output_base); 1076 wrmsrl(MSR_IA32_RTIT_OUTPUT_MASK, ctx->output_mask); 1077 wrmsrl(MSR_IA32_RTIT_CR3_MATCH, ctx->cr3_match); 1078 for (i = 0; i < addr_range; i++) { 1079 wrmsrl(MSR_IA32_RTIT_ADDR0_A + i * 2, ctx->addr_a[i]); 1080 wrmsrl(MSR_IA32_RTIT_ADDR0_B + i * 2, ctx->addr_b[i]); 1081 } 1082 } 1083 1084 static inline void pt_save_msr(struct pt_ctx *ctx, u32 addr_range) 1085 { 1086 u32 i; 1087 1088 rdmsrl(MSR_IA32_RTIT_STATUS, ctx->status); 1089 rdmsrl(MSR_IA32_RTIT_OUTPUT_BASE, ctx->output_base); 1090 rdmsrl(MSR_IA32_RTIT_OUTPUT_MASK, ctx->output_mask); 1091 rdmsrl(MSR_IA32_RTIT_CR3_MATCH, ctx->cr3_match); 1092 for (i = 0; i < addr_range; i++) { 1093 rdmsrl(MSR_IA32_RTIT_ADDR0_A + i * 2, ctx->addr_a[i]); 1094 rdmsrl(MSR_IA32_RTIT_ADDR0_B + i * 2, ctx->addr_b[i]); 1095 } 1096 } 1097 1098 static void pt_guest_enter(struct vcpu_vmx *vmx) 1099 { 1100 if (pt_mode == PT_MODE_SYSTEM) 1101 return; 1102 1103 /* 1104 * GUEST_IA32_RTIT_CTL is already set in the VMCS. 1105 * Save host state before VM entry. 1106 */ 1107 rdmsrl(MSR_IA32_RTIT_CTL, vmx->pt_desc.host.ctl); 1108 if (vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) { 1109 wrmsrl(MSR_IA32_RTIT_CTL, 0); 1110 pt_save_msr(&vmx->pt_desc.host, vmx->pt_desc.addr_range); 1111 pt_load_msr(&vmx->pt_desc.guest, vmx->pt_desc.addr_range); 1112 } 1113 } 1114 1115 static void pt_guest_exit(struct vcpu_vmx *vmx) 1116 { 1117 if (pt_mode == PT_MODE_SYSTEM) 1118 return; 1119 1120 if (vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) { 1121 pt_save_msr(&vmx->pt_desc.guest, vmx->pt_desc.addr_range); 1122 pt_load_msr(&vmx->pt_desc.host, vmx->pt_desc.addr_range); 1123 } 1124 1125 /* Reload host state (IA32_RTIT_CTL will be cleared on VM exit). */ 1126 wrmsrl(MSR_IA32_RTIT_CTL, vmx->pt_desc.host.ctl); 1127 } 1128 1129 void vmx_set_host_fs_gs(struct vmcs_host_state *host, u16 fs_sel, u16 gs_sel, 1130 unsigned long fs_base, unsigned long gs_base) 1131 { 1132 if (unlikely(fs_sel != host->fs_sel)) { 1133 if (!(fs_sel & 7)) 1134 vmcs_write16(HOST_FS_SELECTOR, fs_sel); 1135 else 1136 vmcs_write16(HOST_FS_SELECTOR, 0); 1137 host->fs_sel = fs_sel; 1138 } 1139 if (unlikely(gs_sel != host->gs_sel)) { 1140 if (!(gs_sel & 7)) 1141 vmcs_write16(HOST_GS_SELECTOR, gs_sel); 1142 else 1143 vmcs_write16(HOST_GS_SELECTOR, 0); 1144 host->gs_sel = gs_sel; 1145 } 1146 if (unlikely(fs_base != host->fs_base)) { 1147 vmcs_writel(HOST_FS_BASE, fs_base); 1148 host->fs_base = fs_base; 1149 } 1150 if (unlikely(gs_base != host->gs_base)) { 1151 vmcs_writel(HOST_GS_BASE, gs_base); 1152 host->gs_base = gs_base; 1153 } 1154 } 1155 1156 void vmx_prepare_switch_to_guest(struct kvm_vcpu *vcpu) 1157 { 1158 struct vcpu_vmx *vmx = to_vmx(vcpu); 1159 struct vmcs_host_state *host_state; 1160 #ifdef CONFIG_X86_64 1161 int cpu = raw_smp_processor_id(); 1162 #endif 1163 unsigned long fs_base, gs_base; 1164 u16 fs_sel, gs_sel; 1165 int i; 1166 1167 vmx->req_immediate_exit = false; 1168 1169 /* 1170 * Note that guest MSRs to be saved/restored can also be changed 1171 * when guest state is loaded. This happens when guest transitions 1172 * to/from long-mode by setting MSR_EFER.LMA. 1173 */ 1174 if (!vmx->guest_msrs_ready) { 1175 vmx->guest_msrs_ready = true; 1176 for (i = 0; i < vmx->save_nmsrs; ++i) 1177 kvm_set_shared_msr(vmx->guest_msrs[i].index, 1178 vmx->guest_msrs[i].data, 1179 vmx->guest_msrs[i].mask); 1180 1181 } 1182 1183 if (vmx->nested.need_vmcs12_to_shadow_sync) 1184 nested_sync_vmcs12_to_shadow(vcpu); 1185 1186 if (vmx->guest_state_loaded) 1187 return; 1188 1189 host_state = &vmx->loaded_vmcs->host_state; 1190 1191 /* 1192 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not 1193 * allow segment selectors with cpl > 0 or ti == 1. 1194 */ 1195 host_state->ldt_sel = kvm_read_ldt(); 1196 1197 #ifdef CONFIG_X86_64 1198 savesegment(ds, host_state->ds_sel); 1199 savesegment(es, host_state->es_sel); 1200 1201 gs_base = cpu_kernelmode_gs_base(cpu); 1202 if (likely(is_64bit_mm(current->mm))) { 1203 save_fsgs_for_kvm(); 1204 fs_sel = current->thread.fsindex; 1205 gs_sel = current->thread.gsindex; 1206 fs_base = current->thread.fsbase; 1207 vmx->msr_host_kernel_gs_base = current->thread.gsbase; 1208 } else { 1209 savesegment(fs, fs_sel); 1210 savesegment(gs, gs_sel); 1211 fs_base = read_msr(MSR_FS_BASE); 1212 vmx->msr_host_kernel_gs_base = read_msr(MSR_KERNEL_GS_BASE); 1213 } 1214 1215 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base); 1216 #else 1217 savesegment(fs, fs_sel); 1218 savesegment(gs, gs_sel); 1219 fs_base = segment_base(fs_sel); 1220 gs_base = segment_base(gs_sel); 1221 #endif 1222 1223 vmx_set_host_fs_gs(host_state, fs_sel, gs_sel, fs_base, gs_base); 1224 vmx->guest_state_loaded = true; 1225 } 1226 1227 static void vmx_prepare_switch_to_host(struct vcpu_vmx *vmx) 1228 { 1229 struct vmcs_host_state *host_state; 1230 1231 if (!vmx->guest_state_loaded) 1232 return; 1233 1234 host_state = &vmx->loaded_vmcs->host_state; 1235 1236 ++vmx->vcpu.stat.host_state_reload; 1237 1238 #ifdef CONFIG_X86_64 1239 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base); 1240 #endif 1241 if (host_state->ldt_sel || (host_state->gs_sel & 7)) { 1242 kvm_load_ldt(host_state->ldt_sel); 1243 #ifdef CONFIG_X86_64 1244 load_gs_index(host_state->gs_sel); 1245 #else 1246 loadsegment(gs, host_state->gs_sel); 1247 #endif 1248 } 1249 if (host_state->fs_sel & 7) 1250 loadsegment(fs, host_state->fs_sel); 1251 #ifdef CONFIG_X86_64 1252 if (unlikely(host_state->ds_sel | host_state->es_sel)) { 1253 loadsegment(ds, host_state->ds_sel); 1254 loadsegment(es, host_state->es_sel); 1255 } 1256 #endif 1257 invalidate_tss_limit(); 1258 #ifdef CONFIG_X86_64 1259 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base); 1260 #endif 1261 load_fixmap_gdt(raw_smp_processor_id()); 1262 vmx->guest_state_loaded = false; 1263 vmx->guest_msrs_ready = false; 1264 } 1265 1266 #ifdef CONFIG_X86_64 1267 static u64 vmx_read_guest_kernel_gs_base(struct vcpu_vmx *vmx) 1268 { 1269 preempt_disable(); 1270 if (vmx->guest_state_loaded) 1271 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base); 1272 preempt_enable(); 1273 return vmx->msr_guest_kernel_gs_base; 1274 } 1275 1276 static void vmx_write_guest_kernel_gs_base(struct vcpu_vmx *vmx, u64 data) 1277 { 1278 preempt_disable(); 1279 if (vmx->guest_state_loaded) 1280 wrmsrl(MSR_KERNEL_GS_BASE, data); 1281 preempt_enable(); 1282 vmx->msr_guest_kernel_gs_base = data; 1283 } 1284 #endif 1285 1286 static void vmx_vcpu_pi_load(struct kvm_vcpu *vcpu, int cpu) 1287 { 1288 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu); 1289 struct pi_desc old, new; 1290 unsigned int dest; 1291 1292 /* 1293 * In case of hot-plug or hot-unplug, we may have to undo 1294 * vmx_vcpu_pi_put even if there is no assigned device. And we 1295 * always keep PI.NDST up to date for simplicity: it makes the 1296 * code easier, and CPU migration is not a fast path. 1297 */ 1298 if (!pi_test_sn(pi_desc) && vcpu->cpu == cpu) 1299 return; 1300 1301 /* 1302 * If the 'nv' field is POSTED_INTR_WAKEUP_VECTOR, do not change 1303 * PI.NDST: pi_post_block is the one expected to change PID.NDST and the 1304 * wakeup handler expects the vCPU to be on the blocked_vcpu_list that 1305 * matches PI.NDST. Otherwise, a vcpu may not be able to be woken up 1306 * correctly. 1307 */ 1308 if (pi_desc->nv == POSTED_INTR_WAKEUP_VECTOR || vcpu->cpu == cpu) { 1309 pi_clear_sn(pi_desc); 1310 goto after_clear_sn; 1311 } 1312 1313 /* The full case. */ 1314 do { 1315 old.control = new.control = pi_desc->control; 1316 1317 dest = cpu_physical_id(cpu); 1318 1319 if (x2apic_enabled()) 1320 new.ndst = dest; 1321 else 1322 new.ndst = (dest << 8) & 0xFF00; 1323 1324 new.sn = 0; 1325 } while (cmpxchg64(&pi_desc->control, old.control, 1326 new.control) != old.control); 1327 1328 after_clear_sn: 1329 1330 /* 1331 * Clear SN before reading the bitmap. The VT-d firmware 1332 * writes the bitmap and reads SN atomically (5.2.3 in the 1333 * spec), so it doesn't really have a memory barrier that 1334 * pairs with this, but we cannot do that and we need one. 1335 */ 1336 smp_mb__after_atomic(); 1337 1338 if (!pi_is_pir_empty(pi_desc)) 1339 pi_set_on(pi_desc); 1340 } 1341 1342 void vmx_vcpu_load_vmcs(struct kvm_vcpu *vcpu, int cpu) 1343 { 1344 struct vcpu_vmx *vmx = to_vmx(vcpu); 1345 bool already_loaded = vmx->loaded_vmcs->cpu == cpu; 1346 1347 if (!already_loaded) { 1348 loaded_vmcs_clear(vmx->loaded_vmcs); 1349 local_irq_disable(); 1350 crash_disable_local_vmclear(cpu); 1351 1352 /* 1353 * Read loaded_vmcs->cpu should be before fetching 1354 * loaded_vmcs->loaded_vmcss_on_cpu_link. 1355 * See the comments in __loaded_vmcs_clear(). 1356 */ 1357 smp_rmb(); 1358 1359 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link, 1360 &per_cpu(loaded_vmcss_on_cpu, cpu)); 1361 crash_enable_local_vmclear(cpu); 1362 local_irq_enable(); 1363 } 1364 1365 if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) { 1366 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs; 1367 vmcs_load(vmx->loaded_vmcs->vmcs); 1368 indirect_branch_prediction_barrier(); 1369 } 1370 1371 if (!already_loaded) { 1372 void *gdt = get_current_gdt_ro(); 1373 unsigned long sysenter_esp; 1374 1375 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu); 1376 1377 /* 1378 * Linux uses per-cpu TSS and GDT, so set these when switching 1379 * processors. See 22.2.4. 1380 */ 1381 vmcs_writel(HOST_TR_BASE, 1382 (unsigned long)&get_cpu_entry_area(cpu)->tss.x86_tss); 1383 vmcs_writel(HOST_GDTR_BASE, (unsigned long)gdt); /* 22.2.4 */ 1384 1385 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp); 1386 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */ 1387 1388 vmx->loaded_vmcs->cpu = cpu; 1389 } 1390 1391 /* Setup TSC multiplier */ 1392 if (kvm_has_tsc_control && 1393 vmx->current_tsc_ratio != vcpu->arch.tsc_scaling_ratio) 1394 decache_tsc_multiplier(vmx); 1395 } 1396 1397 /* 1398 * Switches to specified vcpu, until a matching vcpu_put(), but assumes 1399 * vcpu mutex is already taken. 1400 */ 1401 void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu) 1402 { 1403 struct vcpu_vmx *vmx = to_vmx(vcpu); 1404 1405 vmx_vcpu_load_vmcs(vcpu, cpu); 1406 1407 vmx_vcpu_pi_load(vcpu, cpu); 1408 1409 vmx->host_pkru = read_pkru(); 1410 vmx->host_debugctlmsr = get_debugctlmsr(); 1411 } 1412 1413 static void vmx_vcpu_pi_put(struct kvm_vcpu *vcpu) 1414 { 1415 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu); 1416 1417 if (!kvm_arch_has_assigned_device(vcpu->kvm) || 1418 !irq_remapping_cap(IRQ_POSTING_CAP) || 1419 !kvm_vcpu_apicv_active(vcpu)) 1420 return; 1421 1422 /* Set SN when the vCPU is preempted */ 1423 if (vcpu->preempted) 1424 pi_set_sn(pi_desc); 1425 } 1426 1427 static void vmx_vcpu_put(struct kvm_vcpu *vcpu) 1428 { 1429 vmx_vcpu_pi_put(vcpu); 1430 1431 vmx_prepare_switch_to_host(to_vmx(vcpu)); 1432 } 1433 1434 static bool emulation_required(struct kvm_vcpu *vcpu) 1435 { 1436 return emulate_invalid_guest_state && !guest_state_valid(vcpu); 1437 } 1438 1439 unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu) 1440 { 1441 struct vcpu_vmx *vmx = to_vmx(vcpu); 1442 unsigned long rflags, save_rflags; 1443 1444 if (!kvm_register_is_available(vcpu, VCPU_EXREG_RFLAGS)) { 1445 kvm_register_mark_available(vcpu, VCPU_EXREG_RFLAGS); 1446 rflags = vmcs_readl(GUEST_RFLAGS); 1447 if (vmx->rmode.vm86_active) { 1448 rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS; 1449 save_rflags = vmx->rmode.save_rflags; 1450 rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS; 1451 } 1452 vmx->rflags = rflags; 1453 } 1454 return vmx->rflags; 1455 } 1456 1457 void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags) 1458 { 1459 struct vcpu_vmx *vmx = to_vmx(vcpu); 1460 unsigned long old_rflags; 1461 1462 if (enable_unrestricted_guest) { 1463 kvm_register_mark_available(vcpu, VCPU_EXREG_RFLAGS); 1464 vmx->rflags = rflags; 1465 vmcs_writel(GUEST_RFLAGS, rflags); 1466 return; 1467 } 1468 1469 old_rflags = vmx_get_rflags(vcpu); 1470 vmx->rflags = rflags; 1471 if (vmx->rmode.vm86_active) { 1472 vmx->rmode.save_rflags = rflags; 1473 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM; 1474 } 1475 vmcs_writel(GUEST_RFLAGS, rflags); 1476 1477 if ((old_rflags ^ vmx->rflags) & X86_EFLAGS_VM) 1478 vmx->emulation_required = emulation_required(vcpu); 1479 } 1480 1481 u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu) 1482 { 1483 u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO); 1484 int ret = 0; 1485 1486 if (interruptibility & GUEST_INTR_STATE_STI) 1487 ret |= KVM_X86_SHADOW_INT_STI; 1488 if (interruptibility & GUEST_INTR_STATE_MOV_SS) 1489 ret |= KVM_X86_SHADOW_INT_MOV_SS; 1490 1491 return ret; 1492 } 1493 1494 void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask) 1495 { 1496 u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO); 1497 u32 interruptibility = interruptibility_old; 1498 1499 interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS); 1500 1501 if (mask & KVM_X86_SHADOW_INT_MOV_SS) 1502 interruptibility |= GUEST_INTR_STATE_MOV_SS; 1503 else if (mask & KVM_X86_SHADOW_INT_STI) 1504 interruptibility |= GUEST_INTR_STATE_STI; 1505 1506 if ((interruptibility != interruptibility_old)) 1507 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility); 1508 } 1509 1510 static int vmx_rtit_ctl_check(struct kvm_vcpu *vcpu, u64 data) 1511 { 1512 struct vcpu_vmx *vmx = to_vmx(vcpu); 1513 unsigned long value; 1514 1515 /* 1516 * Any MSR write that attempts to change bits marked reserved will 1517 * case a #GP fault. 1518 */ 1519 if (data & vmx->pt_desc.ctl_bitmask) 1520 return 1; 1521 1522 /* 1523 * Any attempt to modify IA32_RTIT_CTL while TraceEn is set will 1524 * result in a #GP unless the same write also clears TraceEn. 1525 */ 1526 if ((vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) && 1527 ((vmx->pt_desc.guest.ctl ^ data) & ~RTIT_CTL_TRACEEN)) 1528 return 1; 1529 1530 /* 1531 * WRMSR to IA32_RTIT_CTL that sets TraceEn but clears this bit 1532 * and FabricEn would cause #GP, if 1533 * CPUID.(EAX=14H, ECX=0):ECX.SNGLRGNOUT[bit 2] = 0 1534 */ 1535 if ((data & RTIT_CTL_TRACEEN) && !(data & RTIT_CTL_TOPA) && 1536 !(data & RTIT_CTL_FABRIC_EN) && 1537 !intel_pt_validate_cap(vmx->pt_desc.caps, 1538 PT_CAP_single_range_output)) 1539 return 1; 1540 1541 /* 1542 * MTCFreq, CycThresh and PSBFreq encodings check, any MSR write that 1543 * utilize encodings marked reserved will casue a #GP fault. 1544 */ 1545 value = intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_mtc_periods); 1546 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_mtc) && 1547 !test_bit((data & RTIT_CTL_MTC_RANGE) >> 1548 RTIT_CTL_MTC_RANGE_OFFSET, &value)) 1549 return 1; 1550 value = intel_pt_validate_cap(vmx->pt_desc.caps, 1551 PT_CAP_cycle_thresholds); 1552 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_psb_cyc) && 1553 !test_bit((data & RTIT_CTL_CYC_THRESH) >> 1554 RTIT_CTL_CYC_THRESH_OFFSET, &value)) 1555 return 1; 1556 value = intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_psb_periods); 1557 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_psb_cyc) && 1558 !test_bit((data & RTIT_CTL_PSB_FREQ) >> 1559 RTIT_CTL_PSB_FREQ_OFFSET, &value)) 1560 return 1; 1561 1562 /* 1563 * If ADDRx_CFG is reserved or the encodings is >2 will 1564 * cause a #GP fault. 1565 */ 1566 value = (data & RTIT_CTL_ADDR0) >> RTIT_CTL_ADDR0_OFFSET; 1567 if ((value && (vmx->pt_desc.addr_range < 1)) || (value > 2)) 1568 return 1; 1569 value = (data & RTIT_CTL_ADDR1) >> RTIT_CTL_ADDR1_OFFSET; 1570 if ((value && (vmx->pt_desc.addr_range < 2)) || (value > 2)) 1571 return 1; 1572 value = (data & RTIT_CTL_ADDR2) >> RTIT_CTL_ADDR2_OFFSET; 1573 if ((value && (vmx->pt_desc.addr_range < 3)) || (value > 2)) 1574 return 1; 1575 value = (data & RTIT_CTL_ADDR3) >> RTIT_CTL_ADDR3_OFFSET; 1576 if ((value && (vmx->pt_desc.addr_range < 4)) || (value > 2)) 1577 return 1; 1578 1579 return 0; 1580 } 1581 1582 static int skip_emulated_instruction(struct kvm_vcpu *vcpu) 1583 { 1584 unsigned long rip; 1585 1586 /* 1587 * Using VMCS.VM_EXIT_INSTRUCTION_LEN on EPT misconfig depends on 1588 * undefined behavior: Intel's SDM doesn't mandate the VMCS field be 1589 * set when EPT misconfig occurs. In practice, real hardware updates 1590 * VM_EXIT_INSTRUCTION_LEN on EPT misconfig, but other hypervisors 1591 * (namely Hyper-V) don't set it due to it being undefined behavior, 1592 * i.e. we end up advancing IP with some random value. 1593 */ 1594 if (!static_cpu_has(X86_FEATURE_HYPERVISOR) || 1595 to_vmx(vcpu)->exit_reason != EXIT_REASON_EPT_MISCONFIG) { 1596 rip = kvm_rip_read(vcpu); 1597 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN); 1598 kvm_rip_write(vcpu, rip); 1599 } else { 1600 if (!kvm_emulate_instruction(vcpu, EMULTYPE_SKIP)) 1601 return 0; 1602 } 1603 1604 /* skipping an emulated instruction also counts */ 1605 vmx_set_interrupt_shadow(vcpu, 0); 1606 1607 return 1; 1608 } 1609 1610 1611 /* 1612 * Recognizes a pending MTF VM-exit and records the nested state for later 1613 * delivery. 1614 */ 1615 static void vmx_update_emulated_instruction(struct kvm_vcpu *vcpu) 1616 { 1617 struct vmcs12 *vmcs12 = get_vmcs12(vcpu); 1618 struct vcpu_vmx *vmx = to_vmx(vcpu); 1619 1620 if (!is_guest_mode(vcpu)) 1621 return; 1622 1623 /* 1624 * Per the SDM, MTF takes priority over debug-trap exceptions besides 1625 * T-bit traps. As instruction emulation is completed (i.e. at the 1626 * instruction boundary), any #DB exception pending delivery must be a 1627 * debug-trap. Record the pending MTF state to be delivered in 1628 * vmx_check_nested_events(). 1629 */ 1630 if (nested_cpu_has_mtf(vmcs12) && 1631 (!vcpu->arch.exception.pending || 1632 vcpu->arch.exception.nr == DB_VECTOR)) 1633 vmx->nested.mtf_pending = true; 1634 else 1635 vmx->nested.mtf_pending = false; 1636 } 1637 1638 static int vmx_skip_emulated_instruction(struct kvm_vcpu *vcpu) 1639 { 1640 vmx_update_emulated_instruction(vcpu); 1641 return skip_emulated_instruction(vcpu); 1642 } 1643 1644 static void vmx_clear_hlt(struct kvm_vcpu *vcpu) 1645 { 1646 /* 1647 * Ensure that we clear the HLT state in the VMCS. We don't need to 1648 * explicitly skip the instruction because if the HLT state is set, 1649 * then the instruction is already executing and RIP has already been 1650 * advanced. 1651 */ 1652 if (kvm_hlt_in_guest(vcpu->kvm) && 1653 vmcs_read32(GUEST_ACTIVITY_STATE) == GUEST_ACTIVITY_HLT) 1654 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE); 1655 } 1656 1657 static void vmx_queue_exception(struct kvm_vcpu *vcpu) 1658 { 1659 struct vcpu_vmx *vmx = to_vmx(vcpu); 1660 unsigned nr = vcpu->arch.exception.nr; 1661 bool has_error_code = vcpu->arch.exception.has_error_code; 1662 u32 error_code = vcpu->arch.exception.error_code; 1663 u32 intr_info = nr | INTR_INFO_VALID_MASK; 1664 1665 kvm_deliver_exception_payload(vcpu); 1666 1667 if (has_error_code) { 1668 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code); 1669 intr_info |= INTR_INFO_DELIVER_CODE_MASK; 1670 } 1671 1672 if (vmx->rmode.vm86_active) { 1673 int inc_eip = 0; 1674 if (kvm_exception_is_soft(nr)) 1675 inc_eip = vcpu->arch.event_exit_inst_len; 1676 kvm_inject_realmode_interrupt(vcpu, nr, inc_eip); 1677 return; 1678 } 1679 1680 WARN_ON_ONCE(vmx->emulation_required); 1681 1682 if (kvm_exception_is_soft(nr)) { 1683 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1684 vmx->vcpu.arch.event_exit_inst_len); 1685 intr_info |= INTR_TYPE_SOFT_EXCEPTION; 1686 } else 1687 intr_info |= INTR_TYPE_HARD_EXCEPTION; 1688 1689 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info); 1690 1691 vmx_clear_hlt(vcpu); 1692 } 1693 1694 static bool vmx_rdtscp_supported(void) 1695 { 1696 return cpu_has_vmx_rdtscp(); 1697 } 1698 1699 static bool vmx_invpcid_supported(void) 1700 { 1701 return cpu_has_vmx_invpcid(); 1702 } 1703 1704 /* 1705 * Swap MSR entry in host/guest MSR entry array. 1706 */ 1707 static void move_msr_up(struct vcpu_vmx *vmx, int from, int to) 1708 { 1709 struct shared_msr_entry tmp; 1710 1711 tmp = vmx->guest_msrs[to]; 1712 vmx->guest_msrs[to] = vmx->guest_msrs[from]; 1713 vmx->guest_msrs[from] = tmp; 1714 } 1715 1716 /* 1717 * Set up the vmcs to automatically save and restore system 1718 * msrs. Don't touch the 64-bit msrs if the guest is in legacy 1719 * mode, as fiddling with msrs is very expensive. 1720 */ 1721 static void setup_msrs(struct vcpu_vmx *vmx) 1722 { 1723 int save_nmsrs, index; 1724 1725 save_nmsrs = 0; 1726 #ifdef CONFIG_X86_64 1727 /* 1728 * The SYSCALL MSRs are only needed on long mode guests, and only 1729 * when EFER.SCE is set. 1730 */ 1731 if (is_long_mode(&vmx->vcpu) && (vmx->vcpu.arch.efer & EFER_SCE)) { 1732 index = __find_msr_index(vmx, MSR_STAR); 1733 if (index >= 0) 1734 move_msr_up(vmx, index, save_nmsrs++); 1735 index = __find_msr_index(vmx, MSR_LSTAR); 1736 if (index >= 0) 1737 move_msr_up(vmx, index, save_nmsrs++); 1738 index = __find_msr_index(vmx, MSR_SYSCALL_MASK); 1739 if (index >= 0) 1740 move_msr_up(vmx, index, save_nmsrs++); 1741 } 1742 #endif 1743 index = __find_msr_index(vmx, MSR_EFER); 1744 if (index >= 0 && update_transition_efer(vmx, index)) 1745 move_msr_up(vmx, index, save_nmsrs++); 1746 index = __find_msr_index(vmx, MSR_TSC_AUX); 1747 if (index >= 0 && guest_cpuid_has(&vmx->vcpu, X86_FEATURE_RDTSCP)) 1748 move_msr_up(vmx, index, save_nmsrs++); 1749 index = __find_msr_index(vmx, MSR_IA32_TSX_CTRL); 1750 if (index >= 0) 1751 move_msr_up(vmx, index, save_nmsrs++); 1752 1753 vmx->save_nmsrs = save_nmsrs; 1754 vmx->guest_msrs_ready = false; 1755 1756 if (cpu_has_vmx_msr_bitmap()) 1757 vmx_update_msr_bitmap(&vmx->vcpu); 1758 } 1759 1760 static u64 vmx_read_l1_tsc_offset(struct kvm_vcpu *vcpu) 1761 { 1762 struct vmcs12 *vmcs12 = get_vmcs12(vcpu); 1763 1764 if (is_guest_mode(vcpu) && 1765 (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETTING)) 1766 return vcpu->arch.tsc_offset - vmcs12->tsc_offset; 1767 1768 return vcpu->arch.tsc_offset; 1769 } 1770 1771 static u64 vmx_write_l1_tsc_offset(struct kvm_vcpu *vcpu, u64 offset) 1772 { 1773 struct vmcs12 *vmcs12 = get_vmcs12(vcpu); 1774 u64 g_tsc_offset = 0; 1775 1776 /* 1777 * We're here if L1 chose not to trap WRMSR to TSC. According 1778 * to the spec, this should set L1's TSC; The offset that L1 1779 * set for L2 remains unchanged, and still needs to be added 1780 * to the newly set TSC to get L2's TSC. 1781 */ 1782 if (is_guest_mode(vcpu) && 1783 (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETTING)) 1784 g_tsc_offset = vmcs12->tsc_offset; 1785 1786 trace_kvm_write_tsc_offset(vcpu->vcpu_id, 1787 vcpu->arch.tsc_offset - g_tsc_offset, 1788 offset); 1789 vmcs_write64(TSC_OFFSET, offset + g_tsc_offset); 1790 return offset + g_tsc_offset; 1791 } 1792 1793 /* 1794 * nested_vmx_allowed() checks whether a guest should be allowed to use VMX 1795 * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for 1796 * all guests if the "nested" module option is off, and can also be disabled 1797 * for a single guest by disabling its VMX cpuid bit. 1798 */ 1799 bool nested_vmx_allowed(struct kvm_vcpu *vcpu) 1800 { 1801 return nested && guest_cpuid_has(vcpu, X86_FEATURE_VMX); 1802 } 1803 1804 static inline bool vmx_feature_control_msr_valid(struct kvm_vcpu *vcpu, 1805 uint64_t val) 1806 { 1807 uint64_t valid_bits = to_vmx(vcpu)->msr_ia32_feature_control_valid_bits; 1808 1809 return !(val & ~valid_bits); 1810 } 1811 1812 static int vmx_get_msr_feature(struct kvm_msr_entry *msr) 1813 { 1814 switch (msr->index) { 1815 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC: 1816 if (!nested) 1817 return 1; 1818 return vmx_get_vmx_msr(&vmcs_config.nested, msr->index, &msr->data); 1819 default: 1820 return 1; 1821 } 1822 } 1823 1824 /* 1825 * Reads an msr value (of 'msr_index') into 'pdata'. 1826 * Returns 0 on success, non-0 otherwise. 1827 * Assumes vcpu_load() was already called. 1828 */ 1829 static int vmx_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info) 1830 { 1831 struct vcpu_vmx *vmx = to_vmx(vcpu); 1832 struct shared_msr_entry *msr; 1833 u32 index; 1834 1835 switch (msr_info->index) { 1836 #ifdef CONFIG_X86_64 1837 case MSR_FS_BASE: 1838 msr_info->data = vmcs_readl(GUEST_FS_BASE); 1839 break; 1840 case MSR_GS_BASE: 1841 msr_info->data = vmcs_readl(GUEST_GS_BASE); 1842 break; 1843 case MSR_KERNEL_GS_BASE: 1844 msr_info->data = vmx_read_guest_kernel_gs_base(vmx); 1845 break; 1846 #endif 1847 case MSR_EFER: 1848 return kvm_get_msr_common(vcpu, msr_info); 1849 case MSR_IA32_TSX_CTRL: 1850 if (!msr_info->host_initiated && 1851 !(vcpu->arch.arch_capabilities & ARCH_CAP_TSX_CTRL_MSR)) 1852 return 1; 1853 goto find_shared_msr; 1854 case MSR_IA32_UMWAIT_CONTROL: 1855 if (!msr_info->host_initiated && !vmx_has_waitpkg(vmx)) 1856 return 1; 1857 1858 msr_info->data = vmx->msr_ia32_umwait_control; 1859 break; 1860 case MSR_IA32_SPEC_CTRL: 1861 if (!msr_info->host_initiated && 1862 !guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL)) 1863 return 1; 1864 1865 msr_info->data = to_vmx(vcpu)->spec_ctrl; 1866 break; 1867 case MSR_IA32_SYSENTER_CS: 1868 msr_info->data = vmcs_read32(GUEST_SYSENTER_CS); 1869 break; 1870 case MSR_IA32_SYSENTER_EIP: 1871 msr_info->data = vmcs_readl(GUEST_SYSENTER_EIP); 1872 break; 1873 case MSR_IA32_SYSENTER_ESP: 1874 msr_info->data = vmcs_readl(GUEST_SYSENTER_ESP); 1875 break; 1876 case MSR_IA32_BNDCFGS: 1877 if (!kvm_mpx_supported() || 1878 (!msr_info->host_initiated && 1879 !guest_cpuid_has(vcpu, X86_FEATURE_MPX))) 1880 return 1; 1881 msr_info->data = vmcs_read64(GUEST_BNDCFGS); 1882 break; 1883 case MSR_IA32_MCG_EXT_CTL: 1884 if (!msr_info->host_initiated && 1885 !(vmx->msr_ia32_feature_control & 1886 FEAT_CTL_LMCE_ENABLED)) 1887 return 1; 1888 msr_info->data = vcpu->arch.mcg_ext_ctl; 1889 break; 1890 case MSR_IA32_FEAT_CTL: 1891 msr_info->data = vmx->msr_ia32_feature_control; 1892 break; 1893 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC: 1894 if (!nested_vmx_allowed(vcpu)) 1895 return 1; 1896 if (vmx_get_vmx_msr(&vmx->nested.msrs, msr_info->index, 1897 &msr_info->data)) 1898 return 1; 1899 /* 1900 * Enlightened VMCS v1 doesn't have certain fields, but buggy 1901 * Hyper-V versions are still trying to use corresponding 1902 * features when they are exposed. Filter out the essential 1903 * minimum. 1904 */ 1905 if (!msr_info->host_initiated && 1906 vmx->nested.enlightened_vmcs_enabled) 1907 nested_evmcs_filter_control_msr(msr_info->index, 1908 &msr_info->data); 1909 break; 1910 case MSR_IA32_RTIT_CTL: 1911 if (pt_mode != PT_MODE_HOST_GUEST) 1912 return 1; 1913 msr_info->data = vmx->pt_desc.guest.ctl; 1914 break; 1915 case MSR_IA32_RTIT_STATUS: 1916 if (pt_mode != PT_MODE_HOST_GUEST) 1917 return 1; 1918 msr_info->data = vmx->pt_desc.guest.status; 1919 break; 1920 case MSR_IA32_RTIT_CR3_MATCH: 1921 if ((pt_mode != PT_MODE_HOST_GUEST) || 1922 !intel_pt_validate_cap(vmx->pt_desc.caps, 1923 PT_CAP_cr3_filtering)) 1924 return 1; 1925 msr_info->data = vmx->pt_desc.guest.cr3_match; 1926 break; 1927 case MSR_IA32_RTIT_OUTPUT_BASE: 1928 if ((pt_mode != PT_MODE_HOST_GUEST) || 1929 (!intel_pt_validate_cap(vmx->pt_desc.caps, 1930 PT_CAP_topa_output) && 1931 !intel_pt_validate_cap(vmx->pt_desc.caps, 1932 PT_CAP_single_range_output))) 1933 return 1; 1934 msr_info->data = vmx->pt_desc.guest.output_base; 1935 break; 1936 case MSR_IA32_RTIT_OUTPUT_MASK: 1937 if ((pt_mode != PT_MODE_HOST_GUEST) || 1938 (!intel_pt_validate_cap(vmx->pt_desc.caps, 1939 PT_CAP_topa_output) && 1940 !intel_pt_validate_cap(vmx->pt_desc.caps, 1941 PT_CAP_single_range_output))) 1942 return 1; 1943 msr_info->data = vmx->pt_desc.guest.output_mask; 1944 break; 1945 case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B: 1946 index = msr_info->index - MSR_IA32_RTIT_ADDR0_A; 1947 if ((pt_mode != PT_MODE_HOST_GUEST) || 1948 (index >= 2 * intel_pt_validate_cap(vmx->pt_desc.caps, 1949 PT_CAP_num_address_ranges))) 1950 return 1; 1951 if (index % 2) 1952 msr_info->data = vmx->pt_desc.guest.addr_b[index / 2]; 1953 else 1954 msr_info->data = vmx->pt_desc.guest.addr_a[index / 2]; 1955 break; 1956 case MSR_TSC_AUX: 1957 if (!msr_info->host_initiated && 1958 !guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP)) 1959 return 1; 1960 goto find_shared_msr; 1961 default: 1962 find_shared_msr: 1963 msr = find_msr_entry(vmx, msr_info->index); 1964 if (msr) { 1965 msr_info->data = msr->data; 1966 break; 1967 } 1968 return kvm_get_msr_common(vcpu, msr_info); 1969 } 1970 1971 return 0; 1972 } 1973 1974 /* 1975 * Writes msr value into the appropriate "register". 1976 * Returns 0 on success, non-0 otherwise. 1977 * Assumes vcpu_load() was already called. 1978 */ 1979 static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info) 1980 { 1981 struct vcpu_vmx *vmx = to_vmx(vcpu); 1982 struct shared_msr_entry *msr; 1983 int ret = 0; 1984 u32 msr_index = msr_info->index; 1985 u64 data = msr_info->data; 1986 u32 index; 1987 1988 switch (msr_index) { 1989 case MSR_EFER: 1990 ret = kvm_set_msr_common(vcpu, msr_info); 1991 break; 1992 #ifdef CONFIG_X86_64 1993 case MSR_FS_BASE: 1994 vmx_segment_cache_clear(vmx); 1995 vmcs_writel(GUEST_FS_BASE, data); 1996 break; 1997 case MSR_GS_BASE: 1998 vmx_segment_cache_clear(vmx); 1999 vmcs_writel(GUEST_GS_BASE, data); 2000 break; 2001 case MSR_KERNEL_GS_BASE: 2002 vmx_write_guest_kernel_gs_base(vmx, data); 2003 break; 2004 #endif 2005 case MSR_IA32_SYSENTER_CS: 2006 if (is_guest_mode(vcpu)) 2007 get_vmcs12(vcpu)->guest_sysenter_cs = data; 2008 vmcs_write32(GUEST_SYSENTER_CS, data); 2009 break; 2010 case MSR_IA32_SYSENTER_EIP: 2011 if (is_guest_mode(vcpu)) 2012 get_vmcs12(vcpu)->guest_sysenter_eip = data; 2013 vmcs_writel(GUEST_SYSENTER_EIP, data); 2014 break; 2015 case MSR_IA32_SYSENTER_ESP: 2016 if (is_guest_mode(vcpu)) 2017 get_vmcs12(vcpu)->guest_sysenter_esp = data; 2018 vmcs_writel(GUEST_SYSENTER_ESP, data); 2019 break; 2020 case MSR_IA32_DEBUGCTLMSR: 2021 if (is_guest_mode(vcpu) && get_vmcs12(vcpu)->vm_exit_controls & 2022 VM_EXIT_SAVE_DEBUG_CONTROLS) 2023 get_vmcs12(vcpu)->guest_ia32_debugctl = data; 2024 2025 ret = kvm_set_msr_common(vcpu, msr_info); 2026 break; 2027 2028 case MSR_IA32_BNDCFGS: 2029 if (!kvm_mpx_supported() || 2030 (!msr_info->host_initiated && 2031 !guest_cpuid_has(vcpu, X86_FEATURE_MPX))) 2032 return 1; 2033 if (is_noncanonical_address(data & PAGE_MASK, vcpu) || 2034 (data & MSR_IA32_BNDCFGS_RSVD)) 2035 return 1; 2036 vmcs_write64(GUEST_BNDCFGS, data); 2037 break; 2038 case MSR_IA32_UMWAIT_CONTROL: 2039 if (!msr_info->host_initiated && !vmx_has_waitpkg(vmx)) 2040 return 1; 2041 2042 /* The reserved bit 1 and non-32 bit [63:32] should be zero */ 2043 if (data & (BIT_ULL(1) | GENMASK_ULL(63, 32))) 2044 return 1; 2045 2046 vmx->msr_ia32_umwait_control = data; 2047 break; 2048 case MSR_IA32_SPEC_CTRL: 2049 if (!msr_info->host_initiated && 2050 !guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL)) 2051 return 1; 2052 2053 if (data & ~kvm_spec_ctrl_valid_bits(vcpu)) 2054 return 1; 2055 2056 vmx->spec_ctrl = data; 2057 if (!data) 2058 break; 2059 2060 /* 2061 * For non-nested: 2062 * When it's written (to non-zero) for the first time, pass 2063 * it through. 2064 * 2065 * For nested: 2066 * The handling of the MSR bitmap for L2 guests is done in 2067 * nested_vmx_prepare_msr_bitmap. We should not touch the 2068 * vmcs02.msr_bitmap here since it gets completely overwritten 2069 * in the merging. We update the vmcs01 here for L1 as well 2070 * since it will end up touching the MSR anyway now. 2071 */ 2072 vmx_disable_intercept_for_msr(vmx->vmcs01.msr_bitmap, 2073 MSR_IA32_SPEC_CTRL, 2074 MSR_TYPE_RW); 2075 break; 2076 case MSR_IA32_TSX_CTRL: 2077 if (!msr_info->host_initiated && 2078 !(vcpu->arch.arch_capabilities & ARCH_CAP_TSX_CTRL_MSR)) 2079 return 1; 2080 if (data & ~(TSX_CTRL_RTM_DISABLE | TSX_CTRL_CPUID_CLEAR)) 2081 return 1; 2082 goto find_shared_msr; 2083 case MSR_IA32_PRED_CMD: 2084 if (!msr_info->host_initiated && 2085 !guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL)) 2086 return 1; 2087 2088 if (data & ~PRED_CMD_IBPB) 2089 return 1; 2090 if (!boot_cpu_has(X86_FEATURE_SPEC_CTRL)) 2091 return 1; 2092 if (!data) 2093 break; 2094 2095 wrmsrl(MSR_IA32_PRED_CMD, PRED_CMD_IBPB); 2096 2097 /* 2098 * For non-nested: 2099 * When it's written (to non-zero) for the first time, pass 2100 * it through. 2101 * 2102 * For nested: 2103 * The handling of the MSR bitmap for L2 guests is done in 2104 * nested_vmx_prepare_msr_bitmap. We should not touch the 2105 * vmcs02.msr_bitmap here since it gets completely overwritten 2106 * in the merging. 2107 */ 2108 vmx_disable_intercept_for_msr(vmx->vmcs01.msr_bitmap, MSR_IA32_PRED_CMD, 2109 MSR_TYPE_W); 2110 break; 2111 case MSR_IA32_CR_PAT: 2112 if (!kvm_pat_valid(data)) 2113 return 1; 2114 2115 if (is_guest_mode(vcpu) && 2116 get_vmcs12(vcpu)->vm_exit_controls & VM_EXIT_SAVE_IA32_PAT) 2117 get_vmcs12(vcpu)->guest_ia32_pat = data; 2118 2119 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) { 2120 vmcs_write64(GUEST_IA32_PAT, data); 2121 vcpu->arch.pat = data; 2122 break; 2123 } 2124 ret = kvm_set_msr_common(vcpu, msr_info); 2125 break; 2126 case MSR_IA32_TSC_ADJUST: 2127 ret = kvm_set_msr_common(vcpu, msr_info); 2128 break; 2129 case MSR_IA32_MCG_EXT_CTL: 2130 if ((!msr_info->host_initiated && 2131 !(to_vmx(vcpu)->msr_ia32_feature_control & 2132 FEAT_CTL_LMCE_ENABLED)) || 2133 (data & ~MCG_EXT_CTL_LMCE_EN)) 2134 return 1; 2135 vcpu->arch.mcg_ext_ctl = data; 2136 break; 2137 case MSR_IA32_FEAT_CTL: 2138 if (!vmx_feature_control_msr_valid(vcpu, data) || 2139 (to_vmx(vcpu)->msr_ia32_feature_control & 2140 FEAT_CTL_LOCKED && !msr_info->host_initiated)) 2141 return 1; 2142 vmx->msr_ia32_feature_control = data; 2143 if (msr_info->host_initiated && data == 0) 2144 vmx_leave_nested(vcpu); 2145 break; 2146 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC: 2147 if (!msr_info->host_initiated) 2148 return 1; /* they are read-only */ 2149 if (!nested_vmx_allowed(vcpu)) 2150 return 1; 2151 return vmx_set_vmx_msr(vcpu, msr_index, data); 2152 case MSR_IA32_RTIT_CTL: 2153 if ((pt_mode != PT_MODE_HOST_GUEST) || 2154 vmx_rtit_ctl_check(vcpu, data) || 2155 vmx->nested.vmxon) 2156 return 1; 2157 vmcs_write64(GUEST_IA32_RTIT_CTL, data); 2158 vmx->pt_desc.guest.ctl = data; 2159 pt_update_intercept_for_msr(vmx); 2160 break; 2161 case MSR_IA32_RTIT_STATUS: 2162 if (!pt_can_write_msr(vmx)) 2163 return 1; 2164 if (data & MSR_IA32_RTIT_STATUS_MASK) 2165 return 1; 2166 vmx->pt_desc.guest.status = data; 2167 break; 2168 case MSR_IA32_RTIT_CR3_MATCH: 2169 if (!pt_can_write_msr(vmx)) 2170 return 1; 2171 if (!intel_pt_validate_cap(vmx->pt_desc.caps, 2172 PT_CAP_cr3_filtering)) 2173 return 1; 2174 vmx->pt_desc.guest.cr3_match = data; 2175 break; 2176 case MSR_IA32_RTIT_OUTPUT_BASE: 2177 if (!pt_can_write_msr(vmx)) 2178 return 1; 2179 if (!intel_pt_validate_cap(vmx->pt_desc.caps, 2180 PT_CAP_topa_output) && 2181 !intel_pt_validate_cap(vmx->pt_desc.caps, 2182 PT_CAP_single_range_output)) 2183 return 1; 2184 if (data & MSR_IA32_RTIT_OUTPUT_BASE_MASK) 2185 return 1; 2186 vmx->pt_desc.guest.output_base = data; 2187 break; 2188 case MSR_IA32_RTIT_OUTPUT_MASK: 2189 if (!pt_can_write_msr(vmx)) 2190 return 1; 2191 if (!intel_pt_validate_cap(vmx->pt_desc.caps, 2192 PT_CAP_topa_output) && 2193 !intel_pt_validate_cap(vmx->pt_desc.caps, 2194 PT_CAP_single_range_output)) 2195 return 1; 2196 vmx->pt_desc.guest.output_mask = data; 2197 break; 2198 case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B: 2199 if (!pt_can_write_msr(vmx)) 2200 return 1; 2201 index = msr_info->index - MSR_IA32_RTIT_ADDR0_A; 2202 if (index >= 2 * intel_pt_validate_cap(vmx->pt_desc.caps, 2203 PT_CAP_num_address_ranges)) 2204 return 1; 2205 if (is_noncanonical_address(data, vcpu)) 2206 return 1; 2207 if (index % 2) 2208 vmx->pt_desc.guest.addr_b[index / 2] = data; 2209 else 2210 vmx->pt_desc.guest.addr_a[index / 2] = data; 2211 break; 2212 case MSR_TSC_AUX: 2213 if (!msr_info->host_initiated && 2214 !guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP)) 2215 return 1; 2216 /* Check reserved bit, higher 32 bits should be zero */ 2217 if ((data >> 32) != 0) 2218 return 1; 2219 goto find_shared_msr; 2220 2221 default: 2222 find_shared_msr: 2223 msr = find_msr_entry(vmx, msr_index); 2224 if (msr) 2225 ret = vmx_set_guest_msr(vmx, msr, data); 2226 else 2227 ret = kvm_set_msr_common(vcpu, msr_info); 2228 } 2229 2230 return ret; 2231 } 2232 2233 static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg) 2234 { 2235 kvm_register_mark_available(vcpu, reg); 2236 2237 switch (reg) { 2238 case VCPU_REGS_RSP: 2239 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP); 2240 break; 2241 case VCPU_REGS_RIP: 2242 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP); 2243 break; 2244 case VCPU_EXREG_PDPTR: 2245 if (enable_ept) 2246 ept_save_pdptrs(vcpu); 2247 break; 2248 case VCPU_EXREG_CR3: 2249 if (enable_unrestricted_guest || (enable_ept && is_paging(vcpu))) 2250 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3); 2251 break; 2252 default: 2253 WARN_ON_ONCE(1); 2254 break; 2255 } 2256 } 2257 2258 static __init int cpu_has_kvm_support(void) 2259 { 2260 return cpu_has_vmx(); 2261 } 2262 2263 static __init int vmx_disabled_by_bios(void) 2264 { 2265 return !boot_cpu_has(X86_FEATURE_MSR_IA32_FEAT_CTL) || 2266 !boot_cpu_has(X86_FEATURE_VMX); 2267 } 2268 2269 static void kvm_cpu_vmxon(u64 addr) 2270 { 2271 cr4_set_bits(X86_CR4_VMXE); 2272 intel_pt_handle_vmx(1); 2273 2274 asm volatile ("vmxon %0" : : "m"(addr)); 2275 } 2276 2277 static int hardware_enable(void) 2278 { 2279 int cpu = raw_smp_processor_id(); 2280 u64 phys_addr = __pa(per_cpu(vmxarea, cpu)); 2281 2282 if (cr4_read_shadow() & X86_CR4_VMXE) 2283 return -EBUSY; 2284 2285 /* 2286 * This can happen if we hot-added a CPU but failed to allocate 2287 * VP assist page for it. 2288 */ 2289 if (static_branch_unlikely(&enable_evmcs) && 2290 !hv_get_vp_assist_page(cpu)) 2291 return -EFAULT; 2292 2293 INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu)); 2294 INIT_LIST_HEAD(&per_cpu(blocked_vcpu_on_cpu, cpu)); 2295 spin_lock_init(&per_cpu(blocked_vcpu_on_cpu_lock, cpu)); 2296 2297 /* 2298 * Now we can enable the vmclear operation in kdump 2299 * since the loaded_vmcss_on_cpu list on this cpu 2300 * has been initialized. 2301 * 2302 * Though the cpu is not in VMX operation now, there 2303 * is no problem to enable the vmclear operation 2304 * for the loaded_vmcss_on_cpu list is empty! 2305 */ 2306 crash_enable_local_vmclear(cpu); 2307 2308 kvm_cpu_vmxon(phys_addr); 2309 if (enable_ept) 2310 ept_sync_global(); 2311 2312 return 0; 2313 } 2314 2315 static void vmclear_local_loaded_vmcss(void) 2316 { 2317 int cpu = raw_smp_processor_id(); 2318 struct loaded_vmcs *v, *n; 2319 2320 list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu), 2321 loaded_vmcss_on_cpu_link) 2322 __loaded_vmcs_clear(v); 2323 } 2324 2325 2326 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot() 2327 * tricks. 2328 */ 2329 static void kvm_cpu_vmxoff(void) 2330 { 2331 asm volatile (__ex("vmxoff")); 2332 2333 intel_pt_handle_vmx(0); 2334 cr4_clear_bits(X86_CR4_VMXE); 2335 } 2336 2337 static void hardware_disable(void) 2338 { 2339 vmclear_local_loaded_vmcss(); 2340 kvm_cpu_vmxoff(); 2341 } 2342 2343 /* 2344 * There is no X86_FEATURE for SGX yet, but anyway we need to query CPUID 2345 * directly instead of going through cpu_has(), to ensure KVM is trapping 2346 * ENCLS whenever it's supported in hardware. It does not matter whether 2347 * the host OS supports or has enabled SGX. 2348 */ 2349 static bool cpu_has_sgx(void) 2350 { 2351 return cpuid_eax(0) >= 0x12 && (cpuid_eax(0x12) & BIT(0)); 2352 } 2353 2354 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt, 2355 u32 msr, u32 *result) 2356 { 2357 u32 vmx_msr_low, vmx_msr_high; 2358 u32 ctl = ctl_min | ctl_opt; 2359 2360 rdmsr(msr, vmx_msr_low, vmx_msr_high); 2361 2362 ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */ 2363 ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */ 2364 2365 /* Ensure minimum (required) set of control bits are supported. */ 2366 if (ctl_min & ~ctl) 2367 return -EIO; 2368 2369 *result = ctl; 2370 return 0; 2371 } 2372 2373 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf, 2374 struct vmx_capability *vmx_cap) 2375 { 2376 u32 vmx_msr_low, vmx_msr_high; 2377 u32 min, opt, min2, opt2; 2378 u32 _pin_based_exec_control = 0; 2379 u32 _cpu_based_exec_control = 0; 2380 u32 _cpu_based_2nd_exec_control = 0; 2381 u32 _vmexit_control = 0; 2382 u32 _vmentry_control = 0; 2383 2384 memset(vmcs_conf, 0, sizeof(*vmcs_conf)); 2385 min = CPU_BASED_HLT_EXITING | 2386 #ifdef CONFIG_X86_64 2387 CPU_BASED_CR8_LOAD_EXITING | 2388 CPU_BASED_CR8_STORE_EXITING | 2389 #endif 2390 CPU_BASED_CR3_LOAD_EXITING | 2391 CPU_BASED_CR3_STORE_EXITING | 2392 CPU_BASED_UNCOND_IO_EXITING | 2393 CPU_BASED_MOV_DR_EXITING | 2394 CPU_BASED_USE_TSC_OFFSETTING | 2395 CPU_BASED_MWAIT_EXITING | 2396 CPU_BASED_MONITOR_EXITING | 2397 CPU_BASED_INVLPG_EXITING | 2398 CPU_BASED_RDPMC_EXITING; 2399 2400 opt = CPU_BASED_TPR_SHADOW | 2401 CPU_BASED_USE_MSR_BITMAPS | 2402 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS; 2403 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS, 2404 &_cpu_based_exec_control) < 0) 2405 return -EIO; 2406 #ifdef CONFIG_X86_64 2407 if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW)) 2408 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING & 2409 ~CPU_BASED_CR8_STORE_EXITING; 2410 #endif 2411 if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) { 2412 min2 = 0; 2413 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 2414 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 2415 SECONDARY_EXEC_WBINVD_EXITING | 2416 SECONDARY_EXEC_ENABLE_VPID | 2417 SECONDARY_EXEC_ENABLE_EPT | 2418 SECONDARY_EXEC_UNRESTRICTED_GUEST | 2419 SECONDARY_EXEC_PAUSE_LOOP_EXITING | 2420 SECONDARY_EXEC_DESC | 2421 SECONDARY_EXEC_RDTSCP | 2422 SECONDARY_EXEC_ENABLE_INVPCID | 2423 SECONDARY_EXEC_APIC_REGISTER_VIRT | 2424 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 2425 SECONDARY_EXEC_SHADOW_VMCS | 2426 SECONDARY_EXEC_XSAVES | 2427 SECONDARY_EXEC_RDSEED_EXITING | 2428 SECONDARY_EXEC_RDRAND_EXITING | 2429 SECONDARY_EXEC_ENABLE_PML | 2430 SECONDARY_EXEC_TSC_SCALING | 2431 SECONDARY_EXEC_ENABLE_USR_WAIT_PAUSE | 2432 SECONDARY_EXEC_PT_USE_GPA | 2433 SECONDARY_EXEC_PT_CONCEAL_VMX | 2434 SECONDARY_EXEC_ENABLE_VMFUNC; 2435 if (cpu_has_sgx()) 2436 opt2 |= SECONDARY_EXEC_ENCLS_EXITING; 2437 if (adjust_vmx_controls(min2, opt2, 2438 MSR_IA32_VMX_PROCBASED_CTLS2, 2439 &_cpu_based_2nd_exec_control) < 0) 2440 return -EIO; 2441 } 2442 #ifndef CONFIG_X86_64 2443 if (!(_cpu_based_2nd_exec_control & 2444 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) 2445 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW; 2446 #endif 2447 2448 if (!(_cpu_based_exec_control & CPU_BASED_TPR_SHADOW)) 2449 _cpu_based_2nd_exec_control &= ~( 2450 SECONDARY_EXEC_APIC_REGISTER_VIRT | 2451 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 2452 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY); 2453 2454 rdmsr_safe(MSR_IA32_VMX_EPT_VPID_CAP, 2455 &vmx_cap->ept, &vmx_cap->vpid); 2456 2457 if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) { 2458 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT 2459 enabled */ 2460 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING | 2461 CPU_BASED_CR3_STORE_EXITING | 2462 CPU_BASED_INVLPG_EXITING); 2463 } else if (vmx_cap->ept) { 2464 vmx_cap->ept = 0; 2465 pr_warn_once("EPT CAP should not exist if not support " 2466 "1-setting enable EPT VM-execution control\n"); 2467 } 2468 if (!(_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_VPID) && 2469 vmx_cap->vpid) { 2470 vmx_cap->vpid = 0; 2471 pr_warn_once("VPID CAP should not exist if not support " 2472 "1-setting enable VPID VM-execution control\n"); 2473 } 2474 2475 min = VM_EXIT_SAVE_DEBUG_CONTROLS | VM_EXIT_ACK_INTR_ON_EXIT; 2476 #ifdef CONFIG_X86_64 2477 min |= VM_EXIT_HOST_ADDR_SPACE_SIZE; 2478 #endif 2479 opt = VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 2480 VM_EXIT_LOAD_IA32_PAT | 2481 VM_EXIT_LOAD_IA32_EFER | 2482 VM_EXIT_CLEAR_BNDCFGS | 2483 VM_EXIT_PT_CONCEAL_PIP | 2484 VM_EXIT_CLEAR_IA32_RTIT_CTL; 2485 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS, 2486 &_vmexit_control) < 0) 2487 return -EIO; 2488 2489 min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING; 2490 opt = PIN_BASED_VIRTUAL_NMIS | PIN_BASED_POSTED_INTR | 2491 PIN_BASED_VMX_PREEMPTION_TIMER; 2492 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS, 2493 &_pin_based_exec_control) < 0) 2494 return -EIO; 2495 2496 if (cpu_has_broken_vmx_preemption_timer()) 2497 _pin_based_exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER; 2498 if (!(_cpu_based_2nd_exec_control & 2499 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY)) 2500 _pin_based_exec_control &= ~PIN_BASED_POSTED_INTR; 2501 2502 min = VM_ENTRY_LOAD_DEBUG_CONTROLS; 2503 opt = VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | 2504 VM_ENTRY_LOAD_IA32_PAT | 2505 VM_ENTRY_LOAD_IA32_EFER | 2506 VM_ENTRY_LOAD_BNDCFGS | 2507 VM_ENTRY_PT_CONCEAL_PIP | 2508 VM_ENTRY_LOAD_IA32_RTIT_CTL; 2509 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS, 2510 &_vmentry_control) < 0) 2511 return -EIO; 2512 2513 /* 2514 * Some cpus support VM_{ENTRY,EXIT}_IA32_PERF_GLOBAL_CTRL but they 2515 * can't be used due to an errata where VM Exit may incorrectly clear 2516 * IA32_PERF_GLOBAL_CTRL[34:32]. Workaround the errata by using the 2517 * MSR load mechanism to switch IA32_PERF_GLOBAL_CTRL. 2518 */ 2519 if (boot_cpu_data.x86 == 0x6) { 2520 switch (boot_cpu_data.x86_model) { 2521 case 26: /* AAK155 */ 2522 case 30: /* AAP115 */ 2523 case 37: /* AAT100 */ 2524 case 44: /* BC86,AAY89,BD102 */ 2525 case 46: /* BA97 */ 2526 _vmentry_control &= ~VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL; 2527 _vmexit_control &= ~VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL; 2528 pr_warn_once("kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL " 2529 "does not work properly. Using workaround\n"); 2530 break; 2531 default: 2532 break; 2533 } 2534 } 2535 2536 2537 rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high); 2538 2539 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */ 2540 if ((vmx_msr_high & 0x1fff) > PAGE_SIZE) 2541 return -EIO; 2542 2543 #ifdef CONFIG_X86_64 2544 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */ 2545 if (vmx_msr_high & (1u<<16)) 2546 return -EIO; 2547 #endif 2548 2549 /* Require Write-Back (WB) memory type for VMCS accesses. */ 2550 if (((vmx_msr_high >> 18) & 15) != 6) 2551 return -EIO; 2552 2553 vmcs_conf->size = vmx_msr_high & 0x1fff; 2554 vmcs_conf->order = get_order(vmcs_conf->size); 2555 vmcs_conf->basic_cap = vmx_msr_high & ~0x1fff; 2556 2557 vmcs_conf->revision_id = vmx_msr_low; 2558 2559 vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control; 2560 vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control; 2561 vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control; 2562 vmcs_conf->vmexit_ctrl = _vmexit_control; 2563 vmcs_conf->vmentry_ctrl = _vmentry_control; 2564 2565 if (static_branch_unlikely(&enable_evmcs)) 2566 evmcs_sanitize_exec_ctrls(vmcs_conf); 2567 2568 return 0; 2569 } 2570 2571 struct vmcs *alloc_vmcs_cpu(bool shadow, int cpu, gfp_t flags) 2572 { 2573 int node = cpu_to_node(cpu); 2574 struct page *pages; 2575 struct vmcs *vmcs; 2576 2577 pages = __alloc_pages_node(node, flags, vmcs_config.order); 2578 if (!pages) 2579 return NULL; 2580 vmcs = page_address(pages); 2581 memset(vmcs, 0, vmcs_config.size); 2582 2583 /* KVM supports Enlightened VMCS v1 only */ 2584 if (static_branch_unlikely(&enable_evmcs)) 2585 vmcs->hdr.revision_id = KVM_EVMCS_VERSION; 2586 else 2587 vmcs->hdr.revision_id = vmcs_config.revision_id; 2588 2589 if (shadow) 2590 vmcs->hdr.shadow_vmcs = 1; 2591 return vmcs; 2592 } 2593 2594 void free_vmcs(struct vmcs *vmcs) 2595 { 2596 free_pages((unsigned long)vmcs, vmcs_config.order); 2597 } 2598 2599 /* 2600 * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded 2601 */ 2602 void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs) 2603 { 2604 if (!loaded_vmcs->vmcs) 2605 return; 2606 loaded_vmcs_clear(loaded_vmcs); 2607 free_vmcs(loaded_vmcs->vmcs); 2608 loaded_vmcs->vmcs = NULL; 2609 if (loaded_vmcs->msr_bitmap) 2610 free_page((unsigned long)loaded_vmcs->msr_bitmap); 2611 WARN_ON(loaded_vmcs->shadow_vmcs != NULL); 2612 } 2613 2614 int alloc_loaded_vmcs(struct loaded_vmcs *loaded_vmcs) 2615 { 2616 loaded_vmcs->vmcs = alloc_vmcs(false); 2617 if (!loaded_vmcs->vmcs) 2618 return -ENOMEM; 2619 2620 loaded_vmcs->shadow_vmcs = NULL; 2621 loaded_vmcs->hv_timer_soft_disabled = false; 2622 loaded_vmcs_init(loaded_vmcs); 2623 2624 if (cpu_has_vmx_msr_bitmap()) { 2625 loaded_vmcs->msr_bitmap = (unsigned long *) 2626 __get_free_page(GFP_KERNEL_ACCOUNT); 2627 if (!loaded_vmcs->msr_bitmap) 2628 goto out_vmcs; 2629 memset(loaded_vmcs->msr_bitmap, 0xff, PAGE_SIZE); 2630 2631 if (IS_ENABLED(CONFIG_HYPERV) && 2632 static_branch_unlikely(&enable_evmcs) && 2633 (ms_hyperv.nested_features & HV_X64_NESTED_MSR_BITMAP)) { 2634 struct hv_enlightened_vmcs *evmcs = 2635 (struct hv_enlightened_vmcs *)loaded_vmcs->vmcs; 2636 2637 evmcs->hv_enlightenments_control.msr_bitmap = 1; 2638 } 2639 } 2640 2641 memset(&loaded_vmcs->host_state, 0, sizeof(struct vmcs_host_state)); 2642 memset(&loaded_vmcs->controls_shadow, 0, 2643 sizeof(struct vmcs_controls_shadow)); 2644 2645 return 0; 2646 2647 out_vmcs: 2648 free_loaded_vmcs(loaded_vmcs); 2649 return -ENOMEM; 2650 } 2651 2652 static void free_kvm_area(void) 2653 { 2654 int cpu; 2655 2656 for_each_possible_cpu(cpu) { 2657 free_vmcs(per_cpu(vmxarea, cpu)); 2658 per_cpu(vmxarea, cpu) = NULL; 2659 } 2660 } 2661 2662 static __init int alloc_kvm_area(void) 2663 { 2664 int cpu; 2665 2666 for_each_possible_cpu(cpu) { 2667 struct vmcs *vmcs; 2668 2669 vmcs = alloc_vmcs_cpu(false, cpu, GFP_KERNEL); 2670 if (!vmcs) { 2671 free_kvm_area(); 2672 return -ENOMEM; 2673 } 2674 2675 /* 2676 * When eVMCS is enabled, alloc_vmcs_cpu() sets 2677 * vmcs->revision_id to KVM_EVMCS_VERSION instead of 2678 * revision_id reported by MSR_IA32_VMX_BASIC. 2679 * 2680 * However, even though not explicitly documented by 2681 * TLFS, VMXArea passed as VMXON argument should 2682 * still be marked with revision_id reported by 2683 * physical CPU. 2684 */ 2685 if (static_branch_unlikely(&enable_evmcs)) 2686 vmcs->hdr.revision_id = vmcs_config.revision_id; 2687 2688 per_cpu(vmxarea, cpu) = vmcs; 2689 } 2690 return 0; 2691 } 2692 2693 static void fix_pmode_seg(struct kvm_vcpu *vcpu, int seg, 2694 struct kvm_segment *save) 2695 { 2696 if (!emulate_invalid_guest_state) { 2697 /* 2698 * CS and SS RPL should be equal during guest entry according 2699 * to VMX spec, but in reality it is not always so. Since vcpu 2700 * is in the middle of the transition from real mode to 2701 * protected mode it is safe to assume that RPL 0 is a good 2702 * default value. 2703 */ 2704 if (seg == VCPU_SREG_CS || seg == VCPU_SREG_SS) 2705 save->selector &= ~SEGMENT_RPL_MASK; 2706 save->dpl = save->selector & SEGMENT_RPL_MASK; 2707 save->s = 1; 2708 } 2709 vmx_set_segment(vcpu, save, seg); 2710 } 2711 2712 static void enter_pmode(struct kvm_vcpu *vcpu) 2713 { 2714 unsigned long flags; 2715 struct vcpu_vmx *vmx = to_vmx(vcpu); 2716 2717 /* 2718 * Update real mode segment cache. It may be not up-to-date if sement 2719 * register was written while vcpu was in a guest mode. 2720 */ 2721 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES); 2722 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS); 2723 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS); 2724 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS); 2725 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS); 2726 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS); 2727 2728 vmx->rmode.vm86_active = 0; 2729 2730 vmx_set_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR); 2731 2732 flags = vmcs_readl(GUEST_RFLAGS); 2733 flags &= RMODE_GUEST_OWNED_EFLAGS_BITS; 2734 flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS; 2735 vmcs_writel(GUEST_RFLAGS, flags); 2736 2737 vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) | 2738 (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME)); 2739 2740 update_exception_bitmap(vcpu); 2741 2742 fix_pmode_seg(vcpu, VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]); 2743 fix_pmode_seg(vcpu, VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]); 2744 fix_pmode_seg(vcpu, VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]); 2745 fix_pmode_seg(vcpu, VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]); 2746 fix_pmode_seg(vcpu, VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]); 2747 fix_pmode_seg(vcpu, VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]); 2748 } 2749 2750 static void fix_rmode_seg(int seg, struct kvm_segment *save) 2751 { 2752 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg]; 2753 struct kvm_segment var = *save; 2754 2755 var.dpl = 0x3; 2756 if (seg == VCPU_SREG_CS) 2757 var.type = 0x3; 2758 2759 if (!emulate_invalid_guest_state) { 2760 var.selector = var.base >> 4; 2761 var.base = var.base & 0xffff0; 2762 var.limit = 0xffff; 2763 var.g = 0; 2764 var.db = 0; 2765 var.present = 1; 2766 var.s = 1; 2767 var.l = 0; 2768 var.unusable = 0; 2769 var.type = 0x3; 2770 var.avl = 0; 2771 if (save->base & 0xf) 2772 printk_once(KERN_WARNING "kvm: segment base is not " 2773 "paragraph aligned when entering " 2774 "protected mode (seg=%d)", seg); 2775 } 2776 2777 vmcs_write16(sf->selector, var.selector); 2778 vmcs_writel(sf->base, var.base); 2779 vmcs_write32(sf->limit, var.limit); 2780 vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(&var)); 2781 } 2782 2783 static void enter_rmode(struct kvm_vcpu *vcpu) 2784 { 2785 unsigned long flags; 2786 struct vcpu_vmx *vmx = to_vmx(vcpu); 2787 struct kvm_vmx *kvm_vmx = to_kvm_vmx(vcpu->kvm); 2788 2789 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR); 2790 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES); 2791 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS); 2792 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS); 2793 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS); 2794 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS); 2795 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS); 2796 2797 vmx->rmode.vm86_active = 1; 2798 2799 /* 2800 * Very old userspace does not call KVM_SET_TSS_ADDR before entering 2801 * vcpu. Warn the user that an update is overdue. 2802 */ 2803 if (!kvm_vmx->tss_addr) 2804 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be " 2805 "called before entering vcpu\n"); 2806 2807 vmx_segment_cache_clear(vmx); 2808 2809 vmcs_writel(GUEST_TR_BASE, kvm_vmx->tss_addr); 2810 vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1); 2811 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b); 2812 2813 flags = vmcs_readl(GUEST_RFLAGS); 2814 vmx->rmode.save_rflags = flags; 2815 2816 flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM; 2817 2818 vmcs_writel(GUEST_RFLAGS, flags); 2819 vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME); 2820 update_exception_bitmap(vcpu); 2821 2822 fix_rmode_seg(VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]); 2823 fix_rmode_seg(VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]); 2824 fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]); 2825 fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]); 2826 fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]); 2827 fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]); 2828 2829 kvm_mmu_reset_context(vcpu); 2830 } 2831 2832 void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer) 2833 { 2834 struct vcpu_vmx *vmx = to_vmx(vcpu); 2835 struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER); 2836 2837 if (!msr) 2838 return; 2839 2840 vcpu->arch.efer = efer; 2841 if (efer & EFER_LMA) { 2842 vm_entry_controls_setbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE); 2843 msr->data = efer; 2844 } else { 2845 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE); 2846 2847 msr->data = efer & ~EFER_LME; 2848 } 2849 setup_msrs(vmx); 2850 } 2851 2852 #ifdef CONFIG_X86_64 2853 2854 static void enter_lmode(struct kvm_vcpu *vcpu) 2855 { 2856 u32 guest_tr_ar; 2857 2858 vmx_segment_cache_clear(to_vmx(vcpu)); 2859 2860 guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES); 2861 if ((guest_tr_ar & VMX_AR_TYPE_MASK) != VMX_AR_TYPE_BUSY_64_TSS) { 2862 pr_debug_ratelimited("%s: tss fixup for long mode. \n", 2863 __func__); 2864 vmcs_write32(GUEST_TR_AR_BYTES, 2865 (guest_tr_ar & ~VMX_AR_TYPE_MASK) 2866 | VMX_AR_TYPE_BUSY_64_TSS); 2867 } 2868 vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA); 2869 } 2870 2871 static void exit_lmode(struct kvm_vcpu *vcpu) 2872 { 2873 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE); 2874 vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA); 2875 } 2876 2877 #endif 2878 2879 static void vmx_flush_tlb_gva(struct kvm_vcpu *vcpu, gva_t addr) 2880 { 2881 int vpid = to_vmx(vcpu)->vpid; 2882 2883 if (!vpid_sync_vcpu_addr(vpid, addr)) 2884 vpid_sync_context(vpid); 2885 2886 /* 2887 * If VPIDs are not supported or enabled, then the above is a no-op. 2888 * But we don't really need a TLB flush in that case anyway, because 2889 * each VM entry/exit includes an implicit flush when VPID is 0. 2890 */ 2891 } 2892 2893 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu) 2894 { 2895 ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits; 2896 2897 vcpu->arch.cr0 &= ~cr0_guest_owned_bits; 2898 vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits; 2899 } 2900 2901 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu) 2902 { 2903 ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits; 2904 2905 vcpu->arch.cr4 &= ~cr4_guest_owned_bits; 2906 vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits; 2907 } 2908 2909 static void ept_load_pdptrs(struct kvm_vcpu *vcpu) 2910 { 2911 struct kvm_mmu *mmu = vcpu->arch.walk_mmu; 2912 2913 if (!kvm_register_is_dirty(vcpu, VCPU_EXREG_PDPTR)) 2914 return; 2915 2916 if (is_pae_paging(vcpu)) { 2917 vmcs_write64(GUEST_PDPTR0, mmu->pdptrs[0]); 2918 vmcs_write64(GUEST_PDPTR1, mmu->pdptrs[1]); 2919 vmcs_write64(GUEST_PDPTR2, mmu->pdptrs[2]); 2920 vmcs_write64(GUEST_PDPTR3, mmu->pdptrs[3]); 2921 } 2922 } 2923 2924 void ept_save_pdptrs(struct kvm_vcpu *vcpu) 2925 { 2926 struct kvm_mmu *mmu = vcpu->arch.walk_mmu; 2927 2928 if (is_pae_paging(vcpu)) { 2929 mmu->pdptrs[0] = vmcs_read64(GUEST_PDPTR0); 2930 mmu->pdptrs[1] = vmcs_read64(GUEST_PDPTR1); 2931 mmu->pdptrs[2] = vmcs_read64(GUEST_PDPTR2); 2932 mmu->pdptrs[3] = vmcs_read64(GUEST_PDPTR3); 2933 } 2934 2935 kvm_register_mark_dirty(vcpu, VCPU_EXREG_PDPTR); 2936 } 2937 2938 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0, 2939 unsigned long cr0, 2940 struct kvm_vcpu *vcpu) 2941 { 2942 struct vcpu_vmx *vmx = to_vmx(vcpu); 2943 2944 if (!kvm_register_is_available(vcpu, VCPU_EXREG_CR3)) 2945 vmx_cache_reg(vcpu, VCPU_EXREG_CR3); 2946 if (!(cr0 & X86_CR0_PG)) { 2947 /* From paging/starting to nonpaging */ 2948 exec_controls_setbit(vmx, CPU_BASED_CR3_LOAD_EXITING | 2949 CPU_BASED_CR3_STORE_EXITING); 2950 vcpu->arch.cr0 = cr0; 2951 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu)); 2952 } else if (!is_paging(vcpu)) { 2953 /* From nonpaging to paging */ 2954 exec_controls_clearbit(vmx, CPU_BASED_CR3_LOAD_EXITING | 2955 CPU_BASED_CR3_STORE_EXITING); 2956 vcpu->arch.cr0 = cr0; 2957 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu)); 2958 } 2959 2960 if (!(cr0 & X86_CR0_WP)) 2961 *hw_cr0 &= ~X86_CR0_WP; 2962 } 2963 2964 void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0) 2965 { 2966 struct vcpu_vmx *vmx = to_vmx(vcpu); 2967 unsigned long hw_cr0; 2968 2969 hw_cr0 = (cr0 & ~KVM_VM_CR0_ALWAYS_OFF); 2970 if (enable_unrestricted_guest) 2971 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST; 2972 else { 2973 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON; 2974 2975 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE)) 2976 enter_pmode(vcpu); 2977 2978 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE)) 2979 enter_rmode(vcpu); 2980 } 2981 2982 #ifdef CONFIG_X86_64 2983 if (vcpu->arch.efer & EFER_LME) { 2984 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) 2985 enter_lmode(vcpu); 2986 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) 2987 exit_lmode(vcpu); 2988 } 2989 #endif 2990 2991 if (enable_ept && !enable_unrestricted_guest) 2992 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu); 2993 2994 vmcs_writel(CR0_READ_SHADOW, cr0); 2995 vmcs_writel(GUEST_CR0, hw_cr0); 2996 vcpu->arch.cr0 = cr0; 2997 2998 /* depends on vcpu->arch.cr0 to be set to a new value */ 2999 vmx->emulation_required = emulation_required(vcpu); 3000 } 3001 3002 static int get_ept_level(struct kvm_vcpu *vcpu) 3003 { 3004 /* Nested EPT currently only supports 4-level walks. */ 3005 if (is_guest_mode(vcpu) && nested_cpu_has_ept(get_vmcs12(vcpu))) 3006 return 4; 3007 if (cpu_has_vmx_ept_5levels() && (cpuid_maxphyaddr(vcpu) > 48)) 3008 return 5; 3009 return 4; 3010 } 3011 3012 u64 construct_eptp(struct kvm_vcpu *vcpu, unsigned long root_hpa) 3013 { 3014 u64 eptp = VMX_EPTP_MT_WB; 3015 3016 eptp |= (get_ept_level(vcpu) == 5) ? VMX_EPTP_PWL_5 : VMX_EPTP_PWL_4; 3017 3018 if (enable_ept_ad_bits && 3019 (!is_guest_mode(vcpu) || nested_ept_ad_enabled(vcpu))) 3020 eptp |= VMX_EPTP_AD_ENABLE_BIT; 3021 eptp |= (root_hpa & PAGE_MASK); 3022 3023 return eptp; 3024 } 3025 3026 void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3) 3027 { 3028 struct kvm *kvm = vcpu->kvm; 3029 bool update_guest_cr3 = true; 3030 unsigned long guest_cr3; 3031 u64 eptp; 3032 3033 guest_cr3 = cr3; 3034 if (enable_ept) { 3035 eptp = construct_eptp(vcpu, cr3); 3036 vmcs_write64(EPT_POINTER, eptp); 3037 3038 if (kvm_x86_ops->tlb_remote_flush) { 3039 spin_lock(&to_kvm_vmx(kvm)->ept_pointer_lock); 3040 to_vmx(vcpu)->ept_pointer = eptp; 3041 to_kvm_vmx(kvm)->ept_pointers_match 3042 = EPT_POINTERS_CHECK; 3043 spin_unlock(&to_kvm_vmx(kvm)->ept_pointer_lock); 3044 } 3045 3046 /* Loading vmcs02.GUEST_CR3 is handled by nested VM-Enter. */ 3047 if (is_guest_mode(vcpu)) 3048 update_guest_cr3 = false; 3049 else if (!enable_unrestricted_guest && !is_paging(vcpu)) 3050 guest_cr3 = to_kvm_vmx(kvm)->ept_identity_map_addr; 3051 else if (test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail)) 3052 guest_cr3 = vcpu->arch.cr3; 3053 else /* vmcs01.GUEST_CR3 is already up-to-date. */ 3054 update_guest_cr3 = false; 3055 ept_load_pdptrs(vcpu); 3056 } 3057 3058 if (update_guest_cr3) 3059 vmcs_writel(GUEST_CR3, guest_cr3); 3060 } 3061 3062 int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4) 3063 { 3064 struct vcpu_vmx *vmx = to_vmx(vcpu); 3065 /* 3066 * Pass through host's Machine Check Enable value to hw_cr4, which 3067 * is in force while we are in guest mode. Do not let guests control 3068 * this bit, even if host CR4.MCE == 0. 3069 */ 3070 unsigned long hw_cr4; 3071 3072 hw_cr4 = (cr4_read_shadow() & X86_CR4_MCE) | (cr4 & ~X86_CR4_MCE); 3073 if (enable_unrestricted_guest) 3074 hw_cr4 |= KVM_VM_CR4_ALWAYS_ON_UNRESTRICTED_GUEST; 3075 else if (vmx->rmode.vm86_active) 3076 hw_cr4 |= KVM_RMODE_VM_CR4_ALWAYS_ON; 3077 else 3078 hw_cr4 |= KVM_PMODE_VM_CR4_ALWAYS_ON; 3079 3080 if (!boot_cpu_has(X86_FEATURE_UMIP) && vmx_umip_emulated()) { 3081 if (cr4 & X86_CR4_UMIP) { 3082 secondary_exec_controls_setbit(vmx, SECONDARY_EXEC_DESC); 3083 hw_cr4 &= ~X86_CR4_UMIP; 3084 } else if (!is_guest_mode(vcpu) || 3085 !nested_cpu_has2(get_vmcs12(vcpu), SECONDARY_EXEC_DESC)) { 3086 secondary_exec_controls_clearbit(vmx, SECONDARY_EXEC_DESC); 3087 } 3088 } 3089 3090 if (cr4 & X86_CR4_VMXE) { 3091 /* 3092 * To use VMXON (and later other VMX instructions), a guest 3093 * must first be able to turn on cr4.VMXE (see handle_vmon()). 3094 * So basically the check on whether to allow nested VMX 3095 * is here. We operate under the default treatment of SMM, 3096 * so VMX cannot be enabled under SMM. 3097 */ 3098 if (!nested_vmx_allowed(vcpu) || is_smm(vcpu)) 3099 return 1; 3100 } 3101 3102 if (vmx->nested.vmxon && !nested_cr4_valid(vcpu, cr4)) 3103 return 1; 3104 3105 vcpu->arch.cr4 = cr4; 3106 3107 if (!enable_unrestricted_guest) { 3108 if (enable_ept) { 3109 if (!is_paging(vcpu)) { 3110 hw_cr4 &= ~X86_CR4_PAE; 3111 hw_cr4 |= X86_CR4_PSE; 3112 } else if (!(cr4 & X86_CR4_PAE)) { 3113 hw_cr4 &= ~X86_CR4_PAE; 3114 } 3115 } 3116 3117 /* 3118 * SMEP/SMAP/PKU is disabled if CPU is in non-paging mode in 3119 * hardware. To emulate this behavior, SMEP/SMAP/PKU needs 3120 * to be manually disabled when guest switches to non-paging 3121 * mode. 3122 * 3123 * If !enable_unrestricted_guest, the CPU is always running 3124 * with CR0.PG=1 and CR4 needs to be modified. 3125 * If enable_unrestricted_guest, the CPU automatically 3126 * disables SMEP/SMAP/PKU when the guest sets CR0.PG=0. 3127 */ 3128 if (!is_paging(vcpu)) 3129 hw_cr4 &= ~(X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE); 3130 } 3131 3132 vmcs_writel(CR4_READ_SHADOW, cr4); 3133 vmcs_writel(GUEST_CR4, hw_cr4); 3134 return 0; 3135 } 3136 3137 void vmx_get_segment(struct kvm_vcpu *vcpu, struct kvm_segment *var, int seg) 3138 { 3139 struct vcpu_vmx *vmx = to_vmx(vcpu); 3140 u32 ar; 3141 3142 if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) { 3143 *var = vmx->rmode.segs[seg]; 3144 if (seg == VCPU_SREG_TR 3145 || var->selector == vmx_read_guest_seg_selector(vmx, seg)) 3146 return; 3147 var->base = vmx_read_guest_seg_base(vmx, seg); 3148 var->selector = vmx_read_guest_seg_selector(vmx, seg); 3149 return; 3150 } 3151 var->base = vmx_read_guest_seg_base(vmx, seg); 3152 var->limit = vmx_read_guest_seg_limit(vmx, seg); 3153 var->selector = vmx_read_guest_seg_selector(vmx, seg); 3154 ar = vmx_read_guest_seg_ar(vmx, seg); 3155 var->unusable = (ar >> 16) & 1; 3156 var->type = ar & 15; 3157 var->s = (ar >> 4) & 1; 3158 var->dpl = (ar >> 5) & 3; 3159 /* 3160 * Some userspaces do not preserve unusable property. Since usable 3161 * segment has to be present according to VMX spec we can use present 3162 * property to amend userspace bug by making unusable segment always 3163 * nonpresent. vmx_segment_access_rights() already marks nonpresent 3164 * segment as unusable. 3165 */ 3166 var->present = !var->unusable; 3167 var->avl = (ar >> 12) & 1; 3168 var->l = (ar >> 13) & 1; 3169 var->db = (ar >> 14) & 1; 3170 var->g = (ar >> 15) & 1; 3171 } 3172 3173 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg) 3174 { 3175 struct kvm_segment s; 3176 3177 if (to_vmx(vcpu)->rmode.vm86_active) { 3178 vmx_get_segment(vcpu, &s, seg); 3179 return s.base; 3180 } 3181 return vmx_read_guest_seg_base(to_vmx(vcpu), seg); 3182 } 3183 3184 int vmx_get_cpl(struct kvm_vcpu *vcpu) 3185 { 3186 struct vcpu_vmx *vmx = to_vmx(vcpu); 3187 3188 if (unlikely(vmx->rmode.vm86_active)) 3189 return 0; 3190 else { 3191 int ar = vmx_read_guest_seg_ar(vmx, VCPU_SREG_SS); 3192 return VMX_AR_DPL(ar); 3193 } 3194 } 3195 3196 static u32 vmx_segment_access_rights(struct kvm_segment *var) 3197 { 3198 u32 ar; 3199 3200 if (var->unusable || !var->present) 3201 ar = 1 << 16; 3202 else { 3203 ar = var->type & 15; 3204 ar |= (var->s & 1) << 4; 3205 ar |= (var->dpl & 3) << 5; 3206 ar |= (var->present & 1) << 7; 3207 ar |= (var->avl & 1) << 12; 3208 ar |= (var->l & 1) << 13; 3209 ar |= (var->db & 1) << 14; 3210 ar |= (var->g & 1) << 15; 3211 } 3212 3213 return ar; 3214 } 3215 3216 void vmx_set_segment(struct kvm_vcpu *vcpu, struct kvm_segment *var, int seg) 3217 { 3218 struct vcpu_vmx *vmx = to_vmx(vcpu); 3219 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg]; 3220 3221 vmx_segment_cache_clear(vmx); 3222 3223 if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) { 3224 vmx->rmode.segs[seg] = *var; 3225 if (seg == VCPU_SREG_TR) 3226 vmcs_write16(sf->selector, var->selector); 3227 else if (var->s) 3228 fix_rmode_seg(seg, &vmx->rmode.segs[seg]); 3229 goto out; 3230 } 3231 3232 vmcs_writel(sf->base, var->base); 3233 vmcs_write32(sf->limit, var->limit); 3234 vmcs_write16(sf->selector, var->selector); 3235 3236 /* 3237 * Fix the "Accessed" bit in AR field of segment registers for older 3238 * qemu binaries. 3239 * IA32 arch specifies that at the time of processor reset the 3240 * "Accessed" bit in the AR field of segment registers is 1. And qemu 3241 * is setting it to 0 in the userland code. This causes invalid guest 3242 * state vmexit when "unrestricted guest" mode is turned on. 3243 * Fix for this setup issue in cpu_reset is being pushed in the qemu 3244 * tree. Newer qemu binaries with that qemu fix would not need this 3245 * kvm hack. 3246 */ 3247 if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR)) 3248 var->type |= 0x1; /* Accessed */ 3249 3250 vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(var)); 3251 3252 out: 3253 vmx->emulation_required = emulation_required(vcpu); 3254 } 3255 3256 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l) 3257 { 3258 u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS); 3259 3260 *db = (ar >> 14) & 1; 3261 *l = (ar >> 13) & 1; 3262 } 3263 3264 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt) 3265 { 3266 dt->size = vmcs_read32(GUEST_IDTR_LIMIT); 3267 dt->address = vmcs_readl(GUEST_IDTR_BASE); 3268 } 3269 3270 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt) 3271 { 3272 vmcs_write32(GUEST_IDTR_LIMIT, dt->size); 3273 vmcs_writel(GUEST_IDTR_BASE, dt->address); 3274 } 3275 3276 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt) 3277 { 3278 dt->size = vmcs_read32(GUEST_GDTR_LIMIT); 3279 dt->address = vmcs_readl(GUEST_GDTR_BASE); 3280 } 3281 3282 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt) 3283 { 3284 vmcs_write32(GUEST_GDTR_LIMIT, dt->size); 3285 vmcs_writel(GUEST_GDTR_BASE, dt->address); 3286 } 3287 3288 static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg) 3289 { 3290 struct kvm_segment var; 3291 u32 ar; 3292 3293 vmx_get_segment(vcpu, &var, seg); 3294 var.dpl = 0x3; 3295 if (seg == VCPU_SREG_CS) 3296 var.type = 0x3; 3297 ar = vmx_segment_access_rights(&var); 3298 3299 if (var.base != (var.selector << 4)) 3300 return false; 3301 if (var.limit != 0xffff) 3302 return false; 3303 if (ar != 0xf3) 3304 return false; 3305 3306 return true; 3307 } 3308 3309 static bool code_segment_valid(struct kvm_vcpu *vcpu) 3310 { 3311 struct kvm_segment cs; 3312 unsigned int cs_rpl; 3313 3314 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS); 3315 cs_rpl = cs.selector & SEGMENT_RPL_MASK; 3316 3317 if (cs.unusable) 3318 return false; 3319 if (~cs.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_ACCESSES_MASK)) 3320 return false; 3321 if (!cs.s) 3322 return false; 3323 if (cs.type & VMX_AR_TYPE_WRITEABLE_MASK) { 3324 if (cs.dpl > cs_rpl) 3325 return false; 3326 } else { 3327 if (cs.dpl != cs_rpl) 3328 return false; 3329 } 3330 if (!cs.present) 3331 return false; 3332 3333 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */ 3334 return true; 3335 } 3336 3337 static bool stack_segment_valid(struct kvm_vcpu *vcpu) 3338 { 3339 struct kvm_segment ss; 3340 unsigned int ss_rpl; 3341 3342 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS); 3343 ss_rpl = ss.selector & SEGMENT_RPL_MASK; 3344 3345 if (ss.unusable) 3346 return true; 3347 if (ss.type != 3 && ss.type != 7) 3348 return false; 3349 if (!ss.s) 3350 return false; 3351 if (ss.dpl != ss_rpl) /* DPL != RPL */ 3352 return false; 3353 if (!ss.present) 3354 return false; 3355 3356 return true; 3357 } 3358 3359 static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg) 3360 { 3361 struct kvm_segment var; 3362 unsigned int rpl; 3363 3364 vmx_get_segment(vcpu, &var, seg); 3365 rpl = var.selector & SEGMENT_RPL_MASK; 3366 3367 if (var.unusable) 3368 return true; 3369 if (!var.s) 3370 return false; 3371 if (!var.present) 3372 return false; 3373 if (~var.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_WRITEABLE_MASK)) { 3374 if (var.dpl < rpl) /* DPL < RPL */ 3375 return false; 3376 } 3377 3378 /* TODO: Add other members to kvm_segment_field to allow checking for other access 3379 * rights flags 3380 */ 3381 return true; 3382 } 3383 3384 static bool tr_valid(struct kvm_vcpu *vcpu) 3385 { 3386 struct kvm_segment tr; 3387 3388 vmx_get_segment(vcpu, &tr, VCPU_SREG_TR); 3389 3390 if (tr.unusable) 3391 return false; 3392 if (tr.selector & SEGMENT_TI_MASK) /* TI = 1 */ 3393 return false; 3394 if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */ 3395 return false; 3396 if (!tr.present) 3397 return false; 3398 3399 return true; 3400 } 3401 3402 static bool ldtr_valid(struct kvm_vcpu *vcpu) 3403 { 3404 struct kvm_segment ldtr; 3405 3406 vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR); 3407 3408 if (ldtr.unusable) 3409 return true; 3410 if (ldtr.selector & SEGMENT_TI_MASK) /* TI = 1 */ 3411 return false; 3412 if (ldtr.type != 2) 3413 return false; 3414 if (!ldtr.present) 3415 return false; 3416 3417 return true; 3418 } 3419 3420 static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu) 3421 { 3422 struct kvm_segment cs, ss; 3423 3424 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS); 3425 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS); 3426 3427 return ((cs.selector & SEGMENT_RPL_MASK) == 3428 (ss.selector & SEGMENT_RPL_MASK)); 3429 } 3430 3431 /* 3432 * Check if guest state is valid. Returns true if valid, false if 3433 * not. 3434 * We assume that registers are always usable 3435 */ 3436 static bool guest_state_valid(struct kvm_vcpu *vcpu) 3437 { 3438 if (enable_unrestricted_guest) 3439 return true; 3440 3441 /* real mode guest state checks */ 3442 if (!is_protmode(vcpu) || (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) { 3443 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS)) 3444 return false; 3445 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS)) 3446 return false; 3447 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS)) 3448 return false; 3449 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES)) 3450 return false; 3451 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS)) 3452 return false; 3453 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS)) 3454 return false; 3455 } else { 3456 /* protected mode guest state checks */ 3457 if (!cs_ss_rpl_check(vcpu)) 3458 return false; 3459 if (!code_segment_valid(vcpu)) 3460 return false; 3461 if (!stack_segment_valid(vcpu)) 3462 return false; 3463 if (!data_segment_valid(vcpu, VCPU_SREG_DS)) 3464 return false; 3465 if (!data_segment_valid(vcpu, VCPU_SREG_ES)) 3466 return false; 3467 if (!data_segment_valid(vcpu, VCPU_SREG_FS)) 3468 return false; 3469 if (!data_segment_valid(vcpu, VCPU_SREG_GS)) 3470 return false; 3471 if (!tr_valid(vcpu)) 3472 return false; 3473 if (!ldtr_valid(vcpu)) 3474 return false; 3475 } 3476 /* TODO: 3477 * - Add checks on RIP 3478 * - Add checks on RFLAGS 3479 */ 3480 3481 return true; 3482 } 3483 3484 static int init_rmode_tss(struct kvm *kvm) 3485 { 3486 gfn_t fn; 3487 u16 data = 0; 3488 int idx, r; 3489 3490 idx = srcu_read_lock(&kvm->srcu); 3491 fn = to_kvm_vmx(kvm)->tss_addr >> PAGE_SHIFT; 3492 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE); 3493 if (r < 0) 3494 goto out; 3495 data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE; 3496 r = kvm_write_guest_page(kvm, fn++, &data, 3497 TSS_IOPB_BASE_OFFSET, sizeof(u16)); 3498 if (r < 0) 3499 goto out; 3500 r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE); 3501 if (r < 0) 3502 goto out; 3503 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE); 3504 if (r < 0) 3505 goto out; 3506 data = ~0; 3507 r = kvm_write_guest_page(kvm, fn, &data, 3508 RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1, 3509 sizeof(u8)); 3510 out: 3511 srcu_read_unlock(&kvm->srcu, idx); 3512 return r; 3513 } 3514 3515 static int init_rmode_identity_map(struct kvm *kvm) 3516 { 3517 struct kvm_vmx *kvm_vmx = to_kvm_vmx(kvm); 3518 int i, r = 0; 3519 kvm_pfn_t identity_map_pfn; 3520 u32 tmp; 3521 3522 /* Protect kvm_vmx->ept_identity_pagetable_done. */ 3523 mutex_lock(&kvm->slots_lock); 3524 3525 if (likely(kvm_vmx->ept_identity_pagetable_done)) 3526 goto out; 3527 3528 if (!kvm_vmx->ept_identity_map_addr) 3529 kvm_vmx->ept_identity_map_addr = VMX_EPT_IDENTITY_PAGETABLE_ADDR; 3530 identity_map_pfn = kvm_vmx->ept_identity_map_addr >> PAGE_SHIFT; 3531 3532 r = __x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT, 3533 kvm_vmx->ept_identity_map_addr, PAGE_SIZE); 3534 if (r < 0) 3535 goto out; 3536 3537 r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE); 3538 if (r < 0) 3539 goto out; 3540 /* Set up identity-mapping pagetable for EPT in real mode */ 3541 for (i = 0; i < PT32_ENT_PER_PAGE; i++) { 3542 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER | 3543 _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE); 3544 r = kvm_write_guest_page(kvm, identity_map_pfn, 3545 &tmp, i * sizeof(tmp), sizeof(tmp)); 3546 if (r < 0) 3547 goto out; 3548 } 3549 kvm_vmx->ept_identity_pagetable_done = true; 3550 3551 out: 3552 mutex_unlock(&kvm->slots_lock); 3553 return r; 3554 } 3555 3556 static void seg_setup(int seg) 3557 { 3558 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg]; 3559 unsigned int ar; 3560 3561 vmcs_write16(sf->selector, 0); 3562 vmcs_writel(sf->base, 0); 3563 vmcs_write32(sf->limit, 0xffff); 3564 ar = 0x93; 3565 if (seg == VCPU_SREG_CS) 3566 ar |= 0x08; /* code segment */ 3567 3568 vmcs_write32(sf->ar_bytes, ar); 3569 } 3570 3571 static int alloc_apic_access_page(struct kvm *kvm) 3572 { 3573 struct page *page; 3574 int r = 0; 3575 3576 mutex_lock(&kvm->slots_lock); 3577 if (kvm->arch.apic_access_page_done) 3578 goto out; 3579 r = __x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT, 3580 APIC_DEFAULT_PHYS_BASE, PAGE_SIZE); 3581 if (r) 3582 goto out; 3583 3584 page = gfn_to_page(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT); 3585 if (is_error_page(page)) { 3586 r = -EFAULT; 3587 goto out; 3588 } 3589 3590 /* 3591 * Do not pin the page in memory, so that memory hot-unplug 3592 * is able to migrate it. 3593 */ 3594 put_page(page); 3595 kvm->arch.apic_access_page_done = true; 3596 out: 3597 mutex_unlock(&kvm->slots_lock); 3598 return r; 3599 } 3600 3601 int allocate_vpid(void) 3602 { 3603 int vpid; 3604 3605 if (!enable_vpid) 3606 return 0; 3607 spin_lock(&vmx_vpid_lock); 3608 vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS); 3609 if (vpid < VMX_NR_VPIDS) 3610 __set_bit(vpid, vmx_vpid_bitmap); 3611 else 3612 vpid = 0; 3613 spin_unlock(&vmx_vpid_lock); 3614 return vpid; 3615 } 3616 3617 void free_vpid(int vpid) 3618 { 3619 if (!enable_vpid || vpid == 0) 3620 return; 3621 spin_lock(&vmx_vpid_lock); 3622 __clear_bit(vpid, vmx_vpid_bitmap); 3623 spin_unlock(&vmx_vpid_lock); 3624 } 3625 3626 static __always_inline void vmx_disable_intercept_for_msr(unsigned long *msr_bitmap, 3627 u32 msr, int type) 3628 { 3629 int f = sizeof(unsigned long); 3630 3631 if (!cpu_has_vmx_msr_bitmap()) 3632 return; 3633 3634 if (static_branch_unlikely(&enable_evmcs)) 3635 evmcs_touch_msr_bitmap(); 3636 3637 /* 3638 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals 3639 * have the write-low and read-high bitmap offsets the wrong way round. 3640 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff. 3641 */ 3642 if (msr <= 0x1fff) { 3643 if (type & MSR_TYPE_R) 3644 /* read-low */ 3645 __clear_bit(msr, msr_bitmap + 0x000 / f); 3646 3647 if (type & MSR_TYPE_W) 3648 /* write-low */ 3649 __clear_bit(msr, msr_bitmap + 0x800 / f); 3650 3651 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) { 3652 msr &= 0x1fff; 3653 if (type & MSR_TYPE_R) 3654 /* read-high */ 3655 __clear_bit(msr, msr_bitmap + 0x400 / f); 3656 3657 if (type & MSR_TYPE_W) 3658 /* write-high */ 3659 __clear_bit(msr, msr_bitmap + 0xc00 / f); 3660 3661 } 3662 } 3663 3664 static __always_inline void vmx_enable_intercept_for_msr(unsigned long *msr_bitmap, 3665 u32 msr, int type) 3666 { 3667 int f = sizeof(unsigned long); 3668 3669 if (!cpu_has_vmx_msr_bitmap()) 3670 return; 3671 3672 if (static_branch_unlikely(&enable_evmcs)) 3673 evmcs_touch_msr_bitmap(); 3674 3675 /* 3676 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals 3677 * have the write-low and read-high bitmap offsets the wrong way round. 3678 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff. 3679 */ 3680 if (msr <= 0x1fff) { 3681 if (type & MSR_TYPE_R) 3682 /* read-low */ 3683 __set_bit(msr, msr_bitmap + 0x000 / f); 3684 3685 if (type & MSR_TYPE_W) 3686 /* write-low */ 3687 __set_bit(msr, msr_bitmap + 0x800 / f); 3688 3689 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) { 3690 msr &= 0x1fff; 3691 if (type & MSR_TYPE_R) 3692 /* read-high */ 3693 __set_bit(msr, msr_bitmap + 0x400 / f); 3694 3695 if (type & MSR_TYPE_W) 3696 /* write-high */ 3697 __set_bit(msr, msr_bitmap + 0xc00 / f); 3698 3699 } 3700 } 3701 3702 static __always_inline void vmx_set_intercept_for_msr(unsigned long *msr_bitmap, 3703 u32 msr, int type, bool value) 3704 { 3705 if (value) 3706 vmx_enable_intercept_for_msr(msr_bitmap, msr, type); 3707 else 3708 vmx_disable_intercept_for_msr(msr_bitmap, msr, type); 3709 } 3710 3711 static u8 vmx_msr_bitmap_mode(struct kvm_vcpu *vcpu) 3712 { 3713 u8 mode = 0; 3714 3715 if (cpu_has_secondary_exec_ctrls() && 3716 (secondary_exec_controls_get(to_vmx(vcpu)) & 3717 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE)) { 3718 mode |= MSR_BITMAP_MODE_X2APIC; 3719 if (enable_apicv && kvm_vcpu_apicv_active(vcpu)) 3720 mode |= MSR_BITMAP_MODE_X2APIC_APICV; 3721 } 3722 3723 return mode; 3724 } 3725 3726 static void vmx_update_msr_bitmap_x2apic(unsigned long *msr_bitmap, 3727 u8 mode) 3728 { 3729 int msr; 3730 3731 for (msr = 0x800; msr <= 0x8ff; msr += BITS_PER_LONG) { 3732 unsigned word = msr / BITS_PER_LONG; 3733 msr_bitmap[word] = (mode & MSR_BITMAP_MODE_X2APIC_APICV) ? 0 : ~0; 3734 msr_bitmap[word + (0x800 / sizeof(long))] = ~0; 3735 } 3736 3737 if (mode & MSR_BITMAP_MODE_X2APIC) { 3738 /* 3739 * TPR reads and writes can be virtualized even if virtual interrupt 3740 * delivery is not in use. 3741 */ 3742 vmx_disable_intercept_for_msr(msr_bitmap, X2APIC_MSR(APIC_TASKPRI), MSR_TYPE_RW); 3743 if (mode & MSR_BITMAP_MODE_X2APIC_APICV) { 3744 vmx_enable_intercept_for_msr(msr_bitmap, X2APIC_MSR(APIC_TMCCT), MSR_TYPE_R); 3745 vmx_disable_intercept_for_msr(msr_bitmap, X2APIC_MSR(APIC_EOI), MSR_TYPE_W); 3746 vmx_disable_intercept_for_msr(msr_bitmap, X2APIC_MSR(APIC_SELF_IPI), MSR_TYPE_W); 3747 } 3748 } 3749 } 3750 3751 void vmx_update_msr_bitmap(struct kvm_vcpu *vcpu) 3752 { 3753 struct vcpu_vmx *vmx = to_vmx(vcpu); 3754 unsigned long *msr_bitmap = vmx->vmcs01.msr_bitmap; 3755 u8 mode = vmx_msr_bitmap_mode(vcpu); 3756 u8 changed = mode ^ vmx->msr_bitmap_mode; 3757 3758 if (!changed) 3759 return; 3760 3761 if (changed & (MSR_BITMAP_MODE_X2APIC | MSR_BITMAP_MODE_X2APIC_APICV)) 3762 vmx_update_msr_bitmap_x2apic(msr_bitmap, mode); 3763 3764 vmx->msr_bitmap_mode = mode; 3765 } 3766 3767 void pt_update_intercept_for_msr(struct vcpu_vmx *vmx) 3768 { 3769 unsigned long *msr_bitmap = vmx->vmcs01.msr_bitmap; 3770 bool flag = !(vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN); 3771 u32 i; 3772 3773 vmx_set_intercept_for_msr(msr_bitmap, MSR_IA32_RTIT_STATUS, 3774 MSR_TYPE_RW, flag); 3775 vmx_set_intercept_for_msr(msr_bitmap, MSR_IA32_RTIT_OUTPUT_BASE, 3776 MSR_TYPE_RW, flag); 3777 vmx_set_intercept_for_msr(msr_bitmap, MSR_IA32_RTIT_OUTPUT_MASK, 3778 MSR_TYPE_RW, flag); 3779 vmx_set_intercept_for_msr(msr_bitmap, MSR_IA32_RTIT_CR3_MATCH, 3780 MSR_TYPE_RW, flag); 3781 for (i = 0; i < vmx->pt_desc.addr_range; i++) { 3782 vmx_set_intercept_for_msr(msr_bitmap, 3783 MSR_IA32_RTIT_ADDR0_A + i * 2, MSR_TYPE_RW, flag); 3784 vmx_set_intercept_for_msr(msr_bitmap, 3785 MSR_IA32_RTIT_ADDR0_B + i * 2, MSR_TYPE_RW, flag); 3786 } 3787 } 3788 3789 static bool vmx_guest_apic_has_interrupt(struct kvm_vcpu *vcpu) 3790 { 3791 struct vcpu_vmx *vmx = to_vmx(vcpu); 3792 void *vapic_page; 3793 u32 vppr; 3794 int rvi; 3795 3796 if (WARN_ON_ONCE(!is_guest_mode(vcpu)) || 3797 !nested_cpu_has_vid(get_vmcs12(vcpu)) || 3798 WARN_ON_ONCE(!vmx->nested.virtual_apic_map.gfn)) 3799 return false; 3800 3801 rvi = vmx_get_rvi(); 3802 3803 vapic_page = vmx->nested.virtual_apic_map.hva; 3804 vppr = *((u32 *)(vapic_page + APIC_PROCPRI)); 3805 3806 return ((rvi & 0xf0) > (vppr & 0xf0)); 3807 } 3808 3809 static inline bool kvm_vcpu_trigger_posted_interrupt(struct kvm_vcpu *vcpu, 3810 bool nested) 3811 { 3812 #ifdef CONFIG_SMP 3813 int pi_vec = nested ? POSTED_INTR_NESTED_VECTOR : POSTED_INTR_VECTOR; 3814 3815 if (vcpu->mode == IN_GUEST_MODE) { 3816 /* 3817 * The vector of interrupt to be delivered to vcpu had 3818 * been set in PIR before this function. 3819 * 3820 * Following cases will be reached in this block, and 3821 * we always send a notification event in all cases as 3822 * explained below. 3823 * 3824 * Case 1: vcpu keeps in non-root mode. Sending a 3825 * notification event posts the interrupt to vcpu. 3826 * 3827 * Case 2: vcpu exits to root mode and is still 3828 * runnable. PIR will be synced to vIRR before the 3829 * next vcpu entry. Sending a notification event in 3830 * this case has no effect, as vcpu is not in root 3831 * mode. 3832 * 3833 * Case 3: vcpu exits to root mode and is blocked. 3834 * vcpu_block() has already synced PIR to vIRR and 3835 * never blocks vcpu if vIRR is not cleared. Therefore, 3836 * a blocked vcpu here does not wait for any requested 3837 * interrupts in PIR, and sending a notification event 3838 * which has no effect is safe here. 3839 */ 3840 3841 apic->send_IPI_mask(get_cpu_mask(vcpu->cpu), pi_vec); 3842 return true; 3843 } 3844 #endif 3845 return false; 3846 } 3847 3848 static int vmx_deliver_nested_posted_interrupt(struct kvm_vcpu *vcpu, 3849 int vector) 3850 { 3851 struct vcpu_vmx *vmx = to_vmx(vcpu); 3852 3853 if (is_guest_mode(vcpu) && 3854 vector == vmx->nested.posted_intr_nv) { 3855 /* 3856 * If a posted intr is not recognized by hardware, 3857 * we will accomplish it in the next vmentry. 3858 */ 3859 vmx->nested.pi_pending = true; 3860 kvm_make_request(KVM_REQ_EVENT, vcpu); 3861 /* the PIR and ON have been set by L1. */ 3862 if (!kvm_vcpu_trigger_posted_interrupt(vcpu, true)) 3863 kvm_vcpu_kick(vcpu); 3864 return 0; 3865 } 3866 return -1; 3867 } 3868 /* 3869 * Send interrupt to vcpu via posted interrupt way. 3870 * 1. If target vcpu is running(non-root mode), send posted interrupt 3871 * notification to vcpu and hardware will sync PIR to vIRR atomically. 3872 * 2. If target vcpu isn't running(root mode), kick it to pick up the 3873 * interrupt from PIR in next vmentry. 3874 */ 3875 static int vmx_deliver_posted_interrupt(struct kvm_vcpu *vcpu, int vector) 3876 { 3877 struct vcpu_vmx *vmx = to_vmx(vcpu); 3878 int r; 3879 3880 r = vmx_deliver_nested_posted_interrupt(vcpu, vector); 3881 if (!r) 3882 return 0; 3883 3884 if (!vcpu->arch.apicv_active) 3885 return -1; 3886 3887 if (pi_test_and_set_pir(vector, &vmx->pi_desc)) 3888 return 0; 3889 3890 /* If a previous notification has sent the IPI, nothing to do. */ 3891 if (pi_test_and_set_on(&vmx->pi_desc)) 3892 return 0; 3893 3894 if (!kvm_vcpu_trigger_posted_interrupt(vcpu, false)) 3895 kvm_vcpu_kick(vcpu); 3896 3897 return 0; 3898 } 3899 3900 /* 3901 * Set up the vmcs's constant host-state fields, i.e., host-state fields that 3902 * will not change in the lifetime of the guest. 3903 * Note that host-state that does change is set elsewhere. E.g., host-state 3904 * that is set differently for each CPU is set in vmx_vcpu_load(), not here. 3905 */ 3906 void vmx_set_constant_host_state(struct vcpu_vmx *vmx) 3907 { 3908 u32 low32, high32; 3909 unsigned long tmpl; 3910 unsigned long cr0, cr3, cr4; 3911 3912 cr0 = read_cr0(); 3913 WARN_ON(cr0 & X86_CR0_TS); 3914 vmcs_writel(HOST_CR0, cr0); /* 22.2.3 */ 3915 3916 /* 3917 * Save the most likely value for this task's CR3 in the VMCS. 3918 * We can't use __get_current_cr3_fast() because we're not atomic. 3919 */ 3920 cr3 = __read_cr3(); 3921 vmcs_writel(HOST_CR3, cr3); /* 22.2.3 FIXME: shadow tables */ 3922 vmx->loaded_vmcs->host_state.cr3 = cr3; 3923 3924 /* Save the most likely value for this task's CR4 in the VMCS. */ 3925 cr4 = cr4_read_shadow(); 3926 vmcs_writel(HOST_CR4, cr4); /* 22.2.3, 22.2.5 */ 3927 vmx->loaded_vmcs->host_state.cr4 = cr4; 3928 3929 vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */ 3930 #ifdef CONFIG_X86_64 3931 /* 3932 * Load null selectors, so we can avoid reloading them in 3933 * vmx_prepare_switch_to_host(), in case userspace uses 3934 * the null selectors too (the expected case). 3935 */ 3936 vmcs_write16(HOST_DS_SELECTOR, 0); 3937 vmcs_write16(HOST_ES_SELECTOR, 0); 3938 #else 3939 vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */ 3940 vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */ 3941 #endif 3942 vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */ 3943 vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */ 3944 3945 vmcs_writel(HOST_IDTR_BASE, host_idt_base); /* 22.2.4 */ 3946 3947 vmcs_writel(HOST_RIP, (unsigned long)vmx_vmexit); /* 22.2.5 */ 3948 3949 rdmsr(MSR_IA32_SYSENTER_CS, low32, high32); 3950 vmcs_write32(HOST_IA32_SYSENTER_CS, low32); 3951 rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl); 3952 vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl); /* 22.2.3 */ 3953 3954 if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) { 3955 rdmsr(MSR_IA32_CR_PAT, low32, high32); 3956 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32)); 3957 } 3958 3959 if (cpu_has_load_ia32_efer()) 3960 vmcs_write64(HOST_IA32_EFER, host_efer); 3961 } 3962 3963 void set_cr4_guest_host_mask(struct vcpu_vmx *vmx) 3964 { 3965 vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS; 3966 if (enable_ept) 3967 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE; 3968 if (is_guest_mode(&vmx->vcpu)) 3969 vmx->vcpu.arch.cr4_guest_owned_bits &= 3970 ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask; 3971 vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits); 3972 } 3973 3974 u32 vmx_pin_based_exec_ctrl(struct vcpu_vmx *vmx) 3975 { 3976 u32 pin_based_exec_ctrl = vmcs_config.pin_based_exec_ctrl; 3977 3978 if (!kvm_vcpu_apicv_active(&vmx->vcpu)) 3979 pin_based_exec_ctrl &= ~PIN_BASED_POSTED_INTR; 3980 3981 if (!enable_vnmi) 3982 pin_based_exec_ctrl &= ~PIN_BASED_VIRTUAL_NMIS; 3983 3984 if (!enable_preemption_timer) 3985 pin_based_exec_ctrl &= ~PIN_BASED_VMX_PREEMPTION_TIMER; 3986 3987 return pin_based_exec_ctrl; 3988 } 3989 3990 static void vmx_refresh_apicv_exec_ctrl(struct kvm_vcpu *vcpu) 3991 { 3992 struct vcpu_vmx *vmx = to_vmx(vcpu); 3993 3994 pin_controls_set(vmx, vmx_pin_based_exec_ctrl(vmx)); 3995 if (cpu_has_secondary_exec_ctrls()) { 3996 if (kvm_vcpu_apicv_active(vcpu)) 3997 secondary_exec_controls_setbit(vmx, 3998 SECONDARY_EXEC_APIC_REGISTER_VIRT | 3999 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY); 4000 else 4001 secondary_exec_controls_clearbit(vmx, 4002 SECONDARY_EXEC_APIC_REGISTER_VIRT | 4003 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY); 4004 } 4005 4006 if (cpu_has_vmx_msr_bitmap()) 4007 vmx_update_msr_bitmap(vcpu); 4008 } 4009 4010 u32 vmx_exec_control(struct vcpu_vmx *vmx) 4011 { 4012 u32 exec_control = vmcs_config.cpu_based_exec_ctrl; 4013 4014 if (vmx->vcpu.arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT) 4015 exec_control &= ~CPU_BASED_MOV_DR_EXITING; 4016 4017 if (!cpu_need_tpr_shadow(&vmx->vcpu)) { 4018 exec_control &= ~CPU_BASED_TPR_SHADOW; 4019 #ifdef CONFIG_X86_64 4020 exec_control |= CPU_BASED_CR8_STORE_EXITING | 4021 CPU_BASED_CR8_LOAD_EXITING; 4022 #endif 4023 } 4024 if (!enable_ept) 4025 exec_control |= CPU_BASED_CR3_STORE_EXITING | 4026 CPU_BASED_CR3_LOAD_EXITING | 4027 CPU_BASED_INVLPG_EXITING; 4028 if (kvm_mwait_in_guest(vmx->vcpu.kvm)) 4029 exec_control &= ~(CPU_BASED_MWAIT_EXITING | 4030 CPU_BASED_MONITOR_EXITING); 4031 if (kvm_hlt_in_guest(vmx->vcpu.kvm)) 4032 exec_control &= ~CPU_BASED_HLT_EXITING; 4033 return exec_control; 4034 } 4035 4036 4037 static void vmx_compute_secondary_exec_control(struct vcpu_vmx *vmx) 4038 { 4039 struct kvm_vcpu *vcpu = &vmx->vcpu; 4040 4041 u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl; 4042 4043 if (pt_mode == PT_MODE_SYSTEM) 4044 exec_control &= ~(SECONDARY_EXEC_PT_USE_GPA | SECONDARY_EXEC_PT_CONCEAL_VMX); 4045 if (!cpu_need_virtualize_apic_accesses(vcpu)) 4046 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES; 4047 if (vmx->vpid == 0) 4048 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID; 4049 if (!enable_ept) { 4050 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT; 4051 enable_unrestricted_guest = 0; 4052 } 4053 if (!enable_unrestricted_guest) 4054 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST; 4055 if (kvm_pause_in_guest(vmx->vcpu.kvm)) 4056 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING; 4057 if (!kvm_vcpu_apicv_active(vcpu)) 4058 exec_control &= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT | 4059 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY); 4060 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE; 4061 4062 /* SECONDARY_EXEC_DESC is enabled/disabled on writes to CR4.UMIP, 4063 * in vmx_set_cr4. */ 4064 exec_control &= ~SECONDARY_EXEC_DESC; 4065 4066 /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD 4067 (handle_vmptrld). 4068 We can NOT enable shadow_vmcs here because we don't have yet 4069 a current VMCS12 4070 */ 4071 exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS; 4072 4073 if (!enable_pml) 4074 exec_control &= ~SECONDARY_EXEC_ENABLE_PML; 4075 4076 if (vmx_xsaves_supported()) { 4077 /* Exposing XSAVES only when XSAVE is exposed */ 4078 bool xsaves_enabled = 4079 boot_cpu_has(X86_FEATURE_XSAVE) && 4080 guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) && 4081 guest_cpuid_has(vcpu, X86_FEATURE_XSAVES); 4082 4083 vcpu->arch.xsaves_enabled = xsaves_enabled; 4084 4085 if (!xsaves_enabled) 4086 exec_control &= ~SECONDARY_EXEC_XSAVES; 4087 4088 if (nested) { 4089 if (xsaves_enabled) 4090 vmx->nested.msrs.secondary_ctls_high |= 4091 SECONDARY_EXEC_XSAVES; 4092 else 4093 vmx->nested.msrs.secondary_ctls_high &= 4094 ~SECONDARY_EXEC_XSAVES; 4095 } 4096 } 4097 4098 if (vmx_rdtscp_supported()) { 4099 bool rdtscp_enabled = guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP); 4100 if (!rdtscp_enabled) 4101 exec_control &= ~SECONDARY_EXEC_RDTSCP; 4102 4103 if (nested) { 4104 if (rdtscp_enabled) 4105 vmx->nested.msrs.secondary_ctls_high |= 4106 SECONDARY_EXEC_RDTSCP; 4107 else 4108 vmx->nested.msrs.secondary_ctls_high &= 4109 ~SECONDARY_EXEC_RDTSCP; 4110 } 4111 } 4112 4113 if (vmx_invpcid_supported()) { 4114 /* Exposing INVPCID only when PCID is exposed */ 4115 bool invpcid_enabled = 4116 guest_cpuid_has(vcpu, X86_FEATURE_INVPCID) && 4117 guest_cpuid_has(vcpu, X86_FEATURE_PCID); 4118 4119 if (!invpcid_enabled) { 4120 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID; 4121 guest_cpuid_clear(vcpu, X86_FEATURE_INVPCID); 4122 } 4123 4124 if (nested) { 4125 if (invpcid_enabled) 4126 vmx->nested.msrs.secondary_ctls_high |= 4127 SECONDARY_EXEC_ENABLE_INVPCID; 4128 else 4129 vmx->nested.msrs.secondary_ctls_high &= 4130 ~SECONDARY_EXEC_ENABLE_INVPCID; 4131 } 4132 } 4133 4134 if (vmx_rdrand_supported()) { 4135 bool rdrand_enabled = guest_cpuid_has(vcpu, X86_FEATURE_RDRAND); 4136 if (rdrand_enabled) 4137 exec_control &= ~SECONDARY_EXEC_RDRAND_EXITING; 4138 4139 if (nested) { 4140 if (rdrand_enabled) 4141 vmx->nested.msrs.secondary_ctls_high |= 4142 SECONDARY_EXEC_RDRAND_EXITING; 4143 else 4144 vmx->nested.msrs.secondary_ctls_high &= 4145 ~SECONDARY_EXEC_RDRAND_EXITING; 4146 } 4147 } 4148 4149 if (vmx_rdseed_supported()) { 4150 bool rdseed_enabled = guest_cpuid_has(vcpu, X86_FEATURE_RDSEED); 4151 if (rdseed_enabled) 4152 exec_control &= ~SECONDARY_EXEC_RDSEED_EXITING; 4153 4154 if (nested) { 4155 if (rdseed_enabled) 4156 vmx->nested.msrs.secondary_ctls_high |= 4157 SECONDARY_EXEC_RDSEED_EXITING; 4158 else 4159 vmx->nested.msrs.secondary_ctls_high &= 4160 ~SECONDARY_EXEC_RDSEED_EXITING; 4161 } 4162 } 4163 4164 if (vmx_waitpkg_supported()) { 4165 bool waitpkg_enabled = 4166 guest_cpuid_has(vcpu, X86_FEATURE_WAITPKG); 4167 4168 if (!waitpkg_enabled) 4169 exec_control &= ~SECONDARY_EXEC_ENABLE_USR_WAIT_PAUSE; 4170 4171 if (nested) { 4172 if (waitpkg_enabled) 4173 vmx->nested.msrs.secondary_ctls_high |= 4174 SECONDARY_EXEC_ENABLE_USR_WAIT_PAUSE; 4175 else 4176 vmx->nested.msrs.secondary_ctls_high &= 4177 ~SECONDARY_EXEC_ENABLE_USR_WAIT_PAUSE; 4178 } 4179 } 4180 4181 vmx->secondary_exec_control = exec_control; 4182 } 4183 4184 static void ept_set_mmio_spte_mask(void) 4185 { 4186 /* 4187 * EPT Misconfigurations can be generated if the value of bits 2:0 4188 * of an EPT paging-structure entry is 110b (write/execute). 4189 */ 4190 kvm_mmu_set_mmio_spte_mask(VMX_EPT_RWX_MASK, 4191 VMX_EPT_MISCONFIG_WX_VALUE, 0); 4192 } 4193 4194 #define VMX_XSS_EXIT_BITMAP 0 4195 4196 /* 4197 * Noting that the initialization of Guest-state Area of VMCS is in 4198 * vmx_vcpu_reset(). 4199 */ 4200 static void init_vmcs(struct vcpu_vmx *vmx) 4201 { 4202 if (nested) 4203 nested_vmx_set_vmcs_shadowing_bitmap(); 4204 4205 if (cpu_has_vmx_msr_bitmap()) 4206 vmcs_write64(MSR_BITMAP, __pa(vmx->vmcs01.msr_bitmap)); 4207 4208 vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */ 4209 4210 /* Control */ 4211 pin_controls_set(vmx, vmx_pin_based_exec_ctrl(vmx)); 4212 4213 exec_controls_set(vmx, vmx_exec_control(vmx)); 4214 4215 if (cpu_has_secondary_exec_ctrls()) { 4216 vmx_compute_secondary_exec_control(vmx); 4217 secondary_exec_controls_set(vmx, vmx->secondary_exec_control); 4218 } 4219 4220 if (kvm_vcpu_apicv_active(&vmx->vcpu)) { 4221 vmcs_write64(EOI_EXIT_BITMAP0, 0); 4222 vmcs_write64(EOI_EXIT_BITMAP1, 0); 4223 vmcs_write64(EOI_EXIT_BITMAP2, 0); 4224 vmcs_write64(EOI_EXIT_BITMAP3, 0); 4225 4226 vmcs_write16(GUEST_INTR_STATUS, 0); 4227 4228 vmcs_write16(POSTED_INTR_NV, POSTED_INTR_VECTOR); 4229 vmcs_write64(POSTED_INTR_DESC_ADDR, __pa((&vmx->pi_desc))); 4230 } 4231 4232 if (!kvm_pause_in_guest(vmx->vcpu.kvm)) { 4233 vmcs_write32(PLE_GAP, ple_gap); 4234 vmx->ple_window = ple_window; 4235 vmx->ple_window_dirty = true; 4236 } 4237 4238 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0); 4239 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0); 4240 vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */ 4241 4242 vmcs_write16(HOST_FS_SELECTOR, 0); /* 22.2.4 */ 4243 vmcs_write16(HOST_GS_SELECTOR, 0); /* 22.2.4 */ 4244 vmx_set_constant_host_state(vmx); 4245 vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */ 4246 vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */ 4247 4248 if (cpu_has_vmx_vmfunc()) 4249 vmcs_write64(VM_FUNCTION_CONTROL, 0); 4250 4251 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0); 4252 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0); 4253 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host.val)); 4254 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0); 4255 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest.val)); 4256 4257 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) 4258 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat); 4259 4260 vm_exit_controls_set(vmx, vmx_vmexit_ctrl()); 4261 4262 /* 22.2.1, 20.8.1 */ 4263 vm_entry_controls_set(vmx, vmx_vmentry_ctrl()); 4264 4265 vmx->vcpu.arch.cr0_guest_owned_bits = X86_CR0_TS; 4266 vmcs_writel(CR0_GUEST_HOST_MASK, ~X86_CR0_TS); 4267 4268 set_cr4_guest_host_mask(vmx); 4269 4270 if (vmx->vpid != 0) 4271 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid); 4272 4273 if (vmx_xsaves_supported()) 4274 vmcs_write64(XSS_EXIT_BITMAP, VMX_XSS_EXIT_BITMAP); 4275 4276 if (enable_pml) { 4277 vmcs_write64(PML_ADDRESS, page_to_phys(vmx->pml_pg)); 4278 vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1); 4279 } 4280 4281 if (cpu_has_vmx_encls_vmexit()) 4282 vmcs_write64(ENCLS_EXITING_BITMAP, -1ull); 4283 4284 if (pt_mode == PT_MODE_HOST_GUEST) { 4285 memset(&vmx->pt_desc, 0, sizeof(vmx->pt_desc)); 4286 /* Bit[6~0] are forced to 1, writes are ignored. */ 4287 vmx->pt_desc.guest.output_mask = 0x7F; 4288 vmcs_write64(GUEST_IA32_RTIT_CTL, 0); 4289 } 4290 } 4291 4292 static void vmx_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event) 4293 { 4294 struct vcpu_vmx *vmx = to_vmx(vcpu); 4295 struct msr_data apic_base_msr; 4296 u64 cr0; 4297 4298 vmx->rmode.vm86_active = 0; 4299 vmx->spec_ctrl = 0; 4300 4301 vmx->msr_ia32_umwait_control = 0; 4302 4303 vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val(); 4304 vmx->hv_deadline_tsc = -1; 4305 kvm_set_cr8(vcpu, 0); 4306 4307 if (!init_event) { 4308 apic_base_msr.data = APIC_DEFAULT_PHYS_BASE | 4309 MSR_IA32_APICBASE_ENABLE; 4310 if (kvm_vcpu_is_reset_bsp(vcpu)) 4311 apic_base_msr.data |= MSR_IA32_APICBASE_BSP; 4312 apic_base_msr.host_initiated = true; 4313 kvm_set_apic_base(vcpu, &apic_base_msr); 4314 } 4315 4316 vmx_segment_cache_clear(vmx); 4317 4318 seg_setup(VCPU_SREG_CS); 4319 vmcs_write16(GUEST_CS_SELECTOR, 0xf000); 4320 vmcs_writel(GUEST_CS_BASE, 0xffff0000ul); 4321 4322 seg_setup(VCPU_SREG_DS); 4323 seg_setup(VCPU_SREG_ES); 4324 seg_setup(VCPU_SREG_FS); 4325 seg_setup(VCPU_SREG_GS); 4326 seg_setup(VCPU_SREG_SS); 4327 4328 vmcs_write16(GUEST_TR_SELECTOR, 0); 4329 vmcs_writel(GUEST_TR_BASE, 0); 4330 vmcs_write32(GUEST_TR_LIMIT, 0xffff); 4331 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b); 4332 4333 vmcs_write16(GUEST_LDTR_SELECTOR, 0); 4334 vmcs_writel(GUEST_LDTR_BASE, 0); 4335 vmcs_write32(GUEST_LDTR_LIMIT, 0xffff); 4336 vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082); 4337 4338 if (!init_event) { 4339 vmcs_write32(GUEST_SYSENTER_CS, 0); 4340 vmcs_writel(GUEST_SYSENTER_ESP, 0); 4341 vmcs_writel(GUEST_SYSENTER_EIP, 0); 4342 vmcs_write64(GUEST_IA32_DEBUGCTL, 0); 4343 } 4344 4345 kvm_set_rflags(vcpu, X86_EFLAGS_FIXED); 4346 kvm_rip_write(vcpu, 0xfff0); 4347 4348 vmcs_writel(GUEST_GDTR_BASE, 0); 4349 vmcs_write32(GUEST_GDTR_LIMIT, 0xffff); 4350 4351 vmcs_writel(GUEST_IDTR_BASE, 0); 4352 vmcs_write32(GUEST_IDTR_LIMIT, 0xffff); 4353 4354 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE); 4355 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0); 4356 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS, 0); 4357 if (kvm_mpx_supported()) 4358 vmcs_write64(GUEST_BNDCFGS, 0); 4359 4360 setup_msrs(vmx); 4361 4362 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */ 4363 4364 if (cpu_has_vmx_tpr_shadow() && !init_event) { 4365 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0); 4366 if (cpu_need_tpr_shadow(vcpu)) 4367 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 4368 __pa(vcpu->arch.apic->regs)); 4369 vmcs_write32(TPR_THRESHOLD, 0); 4370 } 4371 4372 kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu); 4373 4374 cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET; 4375 vmx->vcpu.arch.cr0 = cr0; 4376 vmx_set_cr0(vcpu, cr0); /* enter rmode */ 4377 vmx_set_cr4(vcpu, 0); 4378 vmx_set_efer(vcpu, 0); 4379 4380 update_exception_bitmap(vcpu); 4381 4382 vpid_sync_context(vmx->vpid); 4383 if (init_event) 4384 vmx_clear_hlt(vcpu); 4385 } 4386 4387 static void enable_irq_window(struct kvm_vcpu *vcpu) 4388 { 4389 exec_controls_setbit(to_vmx(vcpu), CPU_BASED_INTR_WINDOW_EXITING); 4390 } 4391 4392 static void enable_nmi_window(struct kvm_vcpu *vcpu) 4393 { 4394 if (!enable_vnmi || 4395 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) { 4396 enable_irq_window(vcpu); 4397 return; 4398 } 4399 4400 exec_controls_setbit(to_vmx(vcpu), CPU_BASED_NMI_WINDOW_EXITING); 4401 } 4402 4403 static void vmx_inject_irq(struct kvm_vcpu *vcpu) 4404 { 4405 struct vcpu_vmx *vmx = to_vmx(vcpu); 4406 uint32_t intr; 4407 int irq = vcpu->arch.interrupt.nr; 4408 4409 trace_kvm_inj_virq(irq); 4410 4411 ++vcpu->stat.irq_injections; 4412 if (vmx->rmode.vm86_active) { 4413 int inc_eip = 0; 4414 if (vcpu->arch.interrupt.soft) 4415 inc_eip = vcpu->arch.event_exit_inst_len; 4416 kvm_inject_realmode_interrupt(vcpu, irq, inc_eip); 4417 return; 4418 } 4419 intr = irq | INTR_INFO_VALID_MASK; 4420 if (vcpu->arch.interrupt.soft) { 4421 intr |= INTR_TYPE_SOFT_INTR; 4422 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 4423 vmx->vcpu.arch.event_exit_inst_len); 4424 } else 4425 intr |= INTR_TYPE_EXT_INTR; 4426 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr); 4427 4428 vmx_clear_hlt(vcpu); 4429 } 4430 4431 static void vmx_inject_nmi(struct kvm_vcpu *vcpu) 4432 { 4433 struct vcpu_vmx *vmx = to_vmx(vcpu); 4434 4435 if (!enable_vnmi) { 4436 /* 4437 * Tracking the NMI-blocked state in software is built upon 4438 * finding the next open IRQ window. This, in turn, depends on 4439 * well-behaving guests: They have to keep IRQs disabled at 4440 * least as long as the NMI handler runs. Otherwise we may 4441 * cause NMI nesting, maybe breaking the guest. But as this is 4442 * highly unlikely, we can live with the residual risk. 4443 */ 4444 vmx->loaded_vmcs->soft_vnmi_blocked = 1; 4445 vmx->loaded_vmcs->vnmi_blocked_time = 0; 4446 } 4447 4448 ++vcpu->stat.nmi_injections; 4449 vmx->loaded_vmcs->nmi_known_unmasked = false; 4450 4451 if (vmx->rmode.vm86_active) { 4452 kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0); 4453 return; 4454 } 4455 4456 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 4457 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR); 4458 4459 vmx_clear_hlt(vcpu); 4460 } 4461 4462 bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu) 4463 { 4464 struct vcpu_vmx *vmx = to_vmx(vcpu); 4465 bool masked; 4466 4467 if (!enable_vnmi) 4468 return vmx->loaded_vmcs->soft_vnmi_blocked; 4469 if (vmx->loaded_vmcs->nmi_known_unmasked) 4470 return false; 4471 masked = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI; 4472 vmx->loaded_vmcs->nmi_known_unmasked = !masked; 4473 return masked; 4474 } 4475 4476 void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked) 4477 { 4478 struct vcpu_vmx *vmx = to_vmx(vcpu); 4479 4480 if (!enable_vnmi) { 4481 if (vmx->loaded_vmcs->soft_vnmi_blocked != masked) { 4482 vmx->loaded_vmcs->soft_vnmi_blocked = masked; 4483 vmx->loaded_vmcs->vnmi_blocked_time = 0; 4484 } 4485 } else { 4486 vmx->loaded_vmcs->nmi_known_unmasked = !masked; 4487 if (masked) 4488 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, 4489 GUEST_INTR_STATE_NMI); 4490 else 4491 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO, 4492 GUEST_INTR_STATE_NMI); 4493 } 4494 } 4495 4496 static int vmx_nmi_allowed(struct kvm_vcpu *vcpu) 4497 { 4498 if (to_vmx(vcpu)->nested.nested_run_pending) 4499 return 0; 4500 4501 if (!enable_vnmi && 4502 to_vmx(vcpu)->loaded_vmcs->soft_vnmi_blocked) 4503 return 0; 4504 4505 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & 4506 (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI 4507 | GUEST_INTR_STATE_NMI)); 4508 } 4509 4510 static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu) 4511 { 4512 return (!to_vmx(vcpu)->nested.nested_run_pending && 4513 vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) && 4514 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & 4515 (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS)); 4516 } 4517 4518 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr) 4519 { 4520 int ret; 4521 4522 if (enable_unrestricted_guest) 4523 return 0; 4524 4525 mutex_lock(&kvm->slots_lock); 4526 ret = __x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, addr, 4527 PAGE_SIZE * 3); 4528 mutex_unlock(&kvm->slots_lock); 4529 4530 if (ret) 4531 return ret; 4532 to_kvm_vmx(kvm)->tss_addr = addr; 4533 return init_rmode_tss(kvm); 4534 } 4535 4536 static int vmx_set_identity_map_addr(struct kvm *kvm, u64 ident_addr) 4537 { 4538 to_kvm_vmx(kvm)->ept_identity_map_addr = ident_addr; 4539 return 0; 4540 } 4541 4542 static bool rmode_exception(struct kvm_vcpu *vcpu, int vec) 4543 { 4544 switch (vec) { 4545 case BP_VECTOR: 4546 /* 4547 * Update instruction length as we may reinject the exception 4548 * from user space while in guest debugging mode. 4549 */ 4550 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len = 4551 vmcs_read32(VM_EXIT_INSTRUCTION_LEN); 4552 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP) 4553 return false; 4554 /* fall through */ 4555 case DB_VECTOR: 4556 if (vcpu->guest_debug & 4557 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) 4558 return false; 4559 /* fall through */ 4560 case DE_VECTOR: 4561 case OF_VECTOR: 4562 case BR_VECTOR: 4563 case UD_VECTOR: 4564 case DF_VECTOR: 4565 case SS_VECTOR: 4566 case GP_VECTOR: 4567 case MF_VECTOR: 4568 return true; 4569 break; 4570 } 4571 return false; 4572 } 4573 4574 static int handle_rmode_exception(struct kvm_vcpu *vcpu, 4575 int vec, u32 err_code) 4576 { 4577 /* 4578 * Instruction with address size override prefix opcode 0x67 4579 * Cause the #SS fault with 0 error code in VM86 mode. 4580 */ 4581 if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0) { 4582 if (kvm_emulate_instruction(vcpu, 0)) { 4583 if (vcpu->arch.halt_request) { 4584 vcpu->arch.halt_request = 0; 4585 return kvm_vcpu_halt(vcpu); 4586 } 4587 return 1; 4588 } 4589 return 0; 4590 } 4591 4592 /* 4593 * Forward all other exceptions that are valid in real mode. 4594 * FIXME: Breaks guest debugging in real mode, needs to be fixed with 4595 * the required debugging infrastructure rework. 4596 */ 4597 kvm_queue_exception(vcpu, vec); 4598 return 1; 4599 } 4600 4601 /* 4602 * Trigger machine check on the host. We assume all the MSRs are already set up 4603 * by the CPU and that we still run on the same CPU as the MCE occurred on. 4604 * We pass a fake environment to the machine check handler because we want 4605 * the guest to be always treated like user space, no matter what context 4606 * it used internally. 4607 */ 4608 static void kvm_machine_check(void) 4609 { 4610 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64) 4611 struct pt_regs regs = { 4612 .cs = 3, /* Fake ring 3 no matter what the guest ran on */ 4613 .flags = X86_EFLAGS_IF, 4614 }; 4615 4616 do_machine_check(®s, 0); 4617 #endif 4618 } 4619 4620 static int handle_machine_check(struct kvm_vcpu *vcpu) 4621 { 4622 /* handled by vmx_vcpu_run() */ 4623 return 1; 4624 } 4625 4626 static int handle_exception_nmi(struct kvm_vcpu *vcpu) 4627 { 4628 struct vcpu_vmx *vmx = to_vmx(vcpu); 4629 struct kvm_run *kvm_run = vcpu->run; 4630 u32 intr_info, ex_no, error_code; 4631 unsigned long cr2, rip, dr6; 4632 u32 vect_info; 4633 4634 vect_info = vmx->idt_vectoring_info; 4635 intr_info = vmx->exit_intr_info; 4636 4637 if (is_machine_check(intr_info) || is_nmi(intr_info)) 4638 return 1; /* handled by handle_exception_nmi_irqoff() */ 4639 4640 if (is_invalid_opcode(intr_info)) 4641 return handle_ud(vcpu); 4642 4643 error_code = 0; 4644 if (intr_info & INTR_INFO_DELIVER_CODE_MASK) 4645 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE); 4646 4647 if (!vmx->rmode.vm86_active && is_gp_fault(intr_info)) { 4648 WARN_ON_ONCE(!enable_vmware_backdoor); 4649 4650 /* 4651 * VMware backdoor emulation on #GP interception only handles 4652 * IN{S}, OUT{S}, and RDPMC, none of which generate a non-zero 4653 * error code on #GP. 4654 */ 4655 if (error_code) { 4656 kvm_queue_exception_e(vcpu, GP_VECTOR, error_code); 4657 return 1; 4658 } 4659 return kvm_emulate_instruction(vcpu, EMULTYPE_VMWARE_GP); 4660 } 4661 4662 /* 4663 * The #PF with PFEC.RSVD = 1 indicates the guest is accessing 4664 * MMIO, it is better to report an internal error. 4665 * See the comments in vmx_handle_exit. 4666 */ 4667 if ((vect_info & VECTORING_INFO_VALID_MASK) && 4668 !(is_page_fault(intr_info) && !(error_code & PFERR_RSVD_MASK))) { 4669 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR; 4670 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX; 4671 vcpu->run->internal.ndata = 3; 4672 vcpu->run->internal.data[0] = vect_info; 4673 vcpu->run->internal.data[1] = intr_info; 4674 vcpu->run->internal.data[2] = error_code; 4675 return 0; 4676 } 4677 4678 if (is_page_fault(intr_info)) { 4679 cr2 = vmcs_readl(EXIT_QUALIFICATION); 4680 /* EPT won't cause page fault directly */ 4681 WARN_ON_ONCE(!vcpu->arch.apf.host_apf_reason && enable_ept); 4682 return kvm_handle_page_fault(vcpu, error_code, cr2, NULL, 0); 4683 } 4684 4685 ex_no = intr_info & INTR_INFO_VECTOR_MASK; 4686 4687 if (vmx->rmode.vm86_active && rmode_exception(vcpu, ex_no)) 4688 return handle_rmode_exception(vcpu, ex_no, error_code); 4689 4690 switch (ex_no) { 4691 case AC_VECTOR: 4692 kvm_queue_exception_e(vcpu, AC_VECTOR, error_code); 4693 return 1; 4694 case DB_VECTOR: 4695 dr6 = vmcs_readl(EXIT_QUALIFICATION); 4696 if (!(vcpu->guest_debug & 4697 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) { 4698 vcpu->arch.dr6 &= ~DR_TRAP_BITS; 4699 vcpu->arch.dr6 |= dr6 | DR6_RTM; 4700 if (is_icebp(intr_info)) 4701 WARN_ON(!skip_emulated_instruction(vcpu)); 4702 4703 kvm_queue_exception(vcpu, DB_VECTOR); 4704 return 1; 4705 } 4706 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1; 4707 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7); 4708 /* fall through */ 4709 case BP_VECTOR: 4710 /* 4711 * Update instruction length as we may reinject #BP from 4712 * user space while in guest debugging mode. Reading it for 4713 * #DB as well causes no harm, it is not used in that case. 4714 */ 4715 vmx->vcpu.arch.event_exit_inst_len = 4716 vmcs_read32(VM_EXIT_INSTRUCTION_LEN); 4717 kvm_run->exit_reason = KVM_EXIT_DEBUG; 4718 rip = kvm_rip_read(vcpu); 4719 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip; 4720 kvm_run->debug.arch.exception = ex_no; 4721 break; 4722 default: 4723 kvm_run->exit_reason = KVM_EXIT_EXCEPTION; 4724 kvm_run->ex.exception = ex_no; 4725 kvm_run->ex.error_code = error_code; 4726 break; 4727 } 4728 return 0; 4729 } 4730 4731 static __always_inline int handle_external_interrupt(struct kvm_vcpu *vcpu) 4732 { 4733 ++vcpu->stat.irq_exits; 4734 return 1; 4735 } 4736 4737 static int handle_triple_fault(struct kvm_vcpu *vcpu) 4738 { 4739 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN; 4740 vcpu->mmio_needed = 0; 4741 return 0; 4742 } 4743 4744 static int handle_io(struct kvm_vcpu *vcpu) 4745 { 4746 unsigned long exit_qualification; 4747 int size, in, string; 4748 unsigned port; 4749 4750 exit_qualification = vmcs_readl(EXIT_QUALIFICATION); 4751 string = (exit_qualification & 16) != 0; 4752 4753 ++vcpu->stat.io_exits; 4754 4755 if (string) 4756 return kvm_emulate_instruction(vcpu, 0); 4757 4758 port = exit_qualification >> 16; 4759 size = (exit_qualification & 7) + 1; 4760 in = (exit_qualification & 8) != 0; 4761 4762 return kvm_fast_pio(vcpu, size, port, in); 4763 } 4764 4765 static void 4766 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall) 4767 { 4768 /* 4769 * Patch in the VMCALL instruction: 4770 */ 4771 hypercall[0] = 0x0f; 4772 hypercall[1] = 0x01; 4773 hypercall[2] = 0xc1; 4774 } 4775 4776 /* called to set cr0 as appropriate for a mov-to-cr0 exit. */ 4777 static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val) 4778 { 4779 if (is_guest_mode(vcpu)) { 4780 struct vmcs12 *vmcs12 = get_vmcs12(vcpu); 4781 unsigned long orig_val = val; 4782 4783 /* 4784 * We get here when L2 changed cr0 in a way that did not change 4785 * any of L1's shadowed bits (see nested_vmx_exit_handled_cr), 4786 * but did change L0 shadowed bits. So we first calculate the 4787 * effective cr0 value that L1 would like to write into the 4788 * hardware. It consists of the L2-owned bits from the new 4789 * value combined with the L1-owned bits from L1's guest_cr0. 4790 */ 4791 val = (val & ~vmcs12->cr0_guest_host_mask) | 4792 (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask); 4793 4794 if (!nested_guest_cr0_valid(vcpu, val)) 4795 return 1; 4796 4797 if (kvm_set_cr0(vcpu, val)) 4798 return 1; 4799 vmcs_writel(CR0_READ_SHADOW, orig_val); 4800 return 0; 4801 } else { 4802 if (to_vmx(vcpu)->nested.vmxon && 4803 !nested_host_cr0_valid(vcpu, val)) 4804 return 1; 4805 4806 return kvm_set_cr0(vcpu, val); 4807 } 4808 } 4809 4810 static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val) 4811 { 4812 if (is_guest_mode(vcpu)) { 4813 struct vmcs12 *vmcs12 = get_vmcs12(vcpu); 4814 unsigned long orig_val = val; 4815 4816 /* analogously to handle_set_cr0 */ 4817 val = (val & ~vmcs12->cr4_guest_host_mask) | 4818 (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask); 4819 if (kvm_set_cr4(vcpu, val)) 4820 return 1; 4821 vmcs_writel(CR4_READ_SHADOW, orig_val); 4822 return 0; 4823 } else 4824 return kvm_set_cr4(vcpu, val); 4825 } 4826 4827 static int handle_desc(struct kvm_vcpu *vcpu) 4828 { 4829 WARN_ON(!(vcpu->arch.cr4 & X86_CR4_UMIP)); 4830 return kvm_emulate_instruction(vcpu, 0); 4831 } 4832 4833 static int handle_cr(struct kvm_vcpu *vcpu) 4834 { 4835 unsigned long exit_qualification, val; 4836 int cr; 4837 int reg; 4838 int err; 4839 int ret; 4840 4841 exit_qualification = vmcs_readl(EXIT_QUALIFICATION); 4842 cr = exit_qualification & 15; 4843 reg = (exit_qualification >> 8) & 15; 4844 switch ((exit_qualification >> 4) & 3) { 4845 case 0: /* mov to cr */ 4846 val = kvm_register_readl(vcpu, reg); 4847 trace_kvm_cr_write(cr, val); 4848 switch (cr) { 4849 case 0: 4850 err = handle_set_cr0(vcpu, val); 4851 return kvm_complete_insn_gp(vcpu, err); 4852 case 3: 4853 WARN_ON_ONCE(enable_unrestricted_guest); 4854 err = kvm_set_cr3(vcpu, val); 4855 return kvm_complete_insn_gp(vcpu, err); 4856 case 4: 4857 err = handle_set_cr4(vcpu, val); 4858 return kvm_complete_insn_gp(vcpu, err); 4859 case 8: { 4860 u8 cr8_prev = kvm_get_cr8(vcpu); 4861 u8 cr8 = (u8)val; 4862 err = kvm_set_cr8(vcpu, cr8); 4863 ret = kvm_complete_insn_gp(vcpu, err); 4864 if (lapic_in_kernel(vcpu)) 4865 return ret; 4866 if (cr8_prev <= cr8) 4867 return ret; 4868 /* 4869 * TODO: we might be squashing a 4870 * KVM_GUESTDBG_SINGLESTEP-triggered 4871 * KVM_EXIT_DEBUG here. 4872 */ 4873 vcpu->run->exit_reason = KVM_EXIT_SET_TPR; 4874 return 0; 4875 } 4876 } 4877 break; 4878 case 2: /* clts */ 4879 WARN_ONCE(1, "Guest should always own CR0.TS"); 4880 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS)); 4881 trace_kvm_cr_write(0, kvm_read_cr0(vcpu)); 4882 return kvm_skip_emulated_instruction(vcpu); 4883 case 1: /*mov from cr*/ 4884 switch (cr) { 4885 case 3: 4886 WARN_ON_ONCE(enable_unrestricted_guest); 4887 val = kvm_read_cr3(vcpu); 4888 kvm_register_write(vcpu, reg, val); 4889 trace_kvm_cr_read(cr, val); 4890 return kvm_skip_emulated_instruction(vcpu); 4891 case 8: 4892 val = kvm_get_cr8(vcpu); 4893 kvm_register_write(vcpu, reg, val); 4894 trace_kvm_cr_read(cr, val); 4895 return kvm_skip_emulated_instruction(vcpu); 4896 } 4897 break; 4898 case 3: /* lmsw */ 4899 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f; 4900 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val); 4901 kvm_lmsw(vcpu, val); 4902 4903 return kvm_skip_emulated_instruction(vcpu); 4904 default: 4905 break; 4906 } 4907 vcpu->run->exit_reason = 0; 4908 vcpu_unimpl(vcpu, "unhandled control register: op %d cr %d\n", 4909 (int)(exit_qualification >> 4) & 3, cr); 4910 return 0; 4911 } 4912 4913 static int handle_dr(struct kvm_vcpu *vcpu) 4914 { 4915 unsigned long exit_qualification; 4916 int dr, dr7, reg; 4917 4918 exit_qualification = vmcs_readl(EXIT_QUALIFICATION); 4919 dr = exit_qualification & DEBUG_REG_ACCESS_NUM; 4920 4921 /* First, if DR does not exist, trigger UD */ 4922 if (!kvm_require_dr(vcpu, dr)) 4923 return 1; 4924 4925 /* Do not handle if the CPL > 0, will trigger GP on re-entry */ 4926 if (!kvm_require_cpl(vcpu, 0)) 4927 return 1; 4928 dr7 = vmcs_readl(GUEST_DR7); 4929 if (dr7 & DR7_GD) { 4930 /* 4931 * As the vm-exit takes precedence over the debug trap, we 4932 * need to emulate the latter, either for the host or the 4933 * guest debugging itself. 4934 */ 4935 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) { 4936 vcpu->run->debug.arch.dr6 = vcpu->arch.dr6; 4937 vcpu->run->debug.arch.dr7 = dr7; 4938 vcpu->run->debug.arch.pc = kvm_get_linear_rip(vcpu); 4939 vcpu->run->debug.arch.exception = DB_VECTOR; 4940 vcpu->run->exit_reason = KVM_EXIT_DEBUG; 4941 return 0; 4942 } else { 4943 vcpu->arch.dr6 &= ~DR_TRAP_BITS; 4944 vcpu->arch.dr6 |= DR6_BD | DR6_RTM; 4945 kvm_queue_exception(vcpu, DB_VECTOR); 4946 return 1; 4947 } 4948 } 4949 4950 if (vcpu->guest_debug == 0) { 4951 exec_controls_clearbit(to_vmx(vcpu), CPU_BASED_MOV_DR_EXITING); 4952 4953 /* 4954 * No more DR vmexits; force a reload of the debug registers 4955 * and reenter on this instruction. The next vmexit will 4956 * retrieve the full state of the debug registers. 4957 */ 4958 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT; 4959 return 1; 4960 } 4961 4962 reg = DEBUG_REG_ACCESS_REG(exit_qualification); 4963 if (exit_qualification & TYPE_MOV_FROM_DR) { 4964 unsigned long val; 4965 4966 if (kvm_get_dr(vcpu, dr, &val)) 4967 return 1; 4968 kvm_register_write(vcpu, reg, val); 4969 } else 4970 if (kvm_set_dr(vcpu, dr, kvm_register_readl(vcpu, reg))) 4971 return 1; 4972 4973 return kvm_skip_emulated_instruction(vcpu); 4974 } 4975 4976 static u64 vmx_get_dr6(struct kvm_vcpu *vcpu) 4977 { 4978 return vcpu->arch.dr6; 4979 } 4980 4981 static void vmx_set_dr6(struct kvm_vcpu *vcpu, unsigned long val) 4982 { 4983 } 4984 4985 static void vmx_sync_dirty_debug_regs(struct kvm_vcpu *vcpu) 4986 { 4987 get_debugreg(vcpu->arch.db[0], 0); 4988 get_debugreg(vcpu->arch.db[1], 1); 4989 get_debugreg(vcpu->arch.db[2], 2); 4990 get_debugreg(vcpu->arch.db[3], 3); 4991 get_debugreg(vcpu->arch.dr6, 6); 4992 vcpu->arch.dr7 = vmcs_readl(GUEST_DR7); 4993 4994 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT; 4995 exec_controls_setbit(to_vmx(vcpu), CPU_BASED_MOV_DR_EXITING); 4996 } 4997 4998 static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val) 4999 { 5000 vmcs_writel(GUEST_DR7, val); 5001 } 5002 5003 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu) 5004 { 5005 kvm_apic_update_ppr(vcpu); 5006 return 1; 5007 } 5008 5009 static int handle_interrupt_window(struct kvm_vcpu *vcpu) 5010 { 5011 exec_controls_clearbit(to_vmx(vcpu), CPU_BASED_INTR_WINDOW_EXITING); 5012 5013 kvm_make_request(KVM_REQ_EVENT, vcpu); 5014 5015 ++vcpu->stat.irq_window_exits; 5016 return 1; 5017 } 5018 5019 static int handle_vmcall(struct kvm_vcpu *vcpu) 5020 { 5021 return kvm_emulate_hypercall(vcpu); 5022 } 5023 5024 static int handle_invd(struct kvm_vcpu *vcpu) 5025 { 5026 return kvm_emulate_instruction(vcpu, 0); 5027 } 5028 5029 static int handle_invlpg(struct kvm_vcpu *vcpu) 5030 { 5031 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION); 5032 5033 kvm_mmu_invlpg(vcpu, exit_qualification); 5034 return kvm_skip_emulated_instruction(vcpu); 5035 } 5036 5037 static int handle_rdpmc(struct kvm_vcpu *vcpu) 5038 { 5039 int err; 5040 5041 err = kvm_rdpmc(vcpu); 5042 return kvm_complete_insn_gp(vcpu, err); 5043 } 5044 5045 static int handle_wbinvd(struct kvm_vcpu *vcpu) 5046 { 5047 return kvm_emulate_wbinvd(vcpu); 5048 } 5049 5050 static int handle_xsetbv(struct kvm_vcpu *vcpu) 5051 { 5052 u64 new_bv = kvm_read_edx_eax(vcpu); 5053 u32 index = kvm_rcx_read(vcpu); 5054 5055 if (kvm_set_xcr(vcpu, index, new_bv) == 0) 5056 return kvm_skip_emulated_instruction(vcpu); 5057 return 1; 5058 } 5059 5060 static int handle_apic_access(struct kvm_vcpu *vcpu) 5061 { 5062 if (likely(fasteoi)) { 5063 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION); 5064 int access_type, offset; 5065 5066 access_type = exit_qualification & APIC_ACCESS_TYPE; 5067 offset = exit_qualification & APIC_ACCESS_OFFSET; 5068 /* 5069 * Sane guest uses MOV to write EOI, with written value 5070 * not cared. So make a short-circuit here by avoiding 5071 * heavy instruction emulation. 5072 */ 5073 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) && 5074 (offset == APIC_EOI)) { 5075 kvm_lapic_set_eoi(vcpu); 5076 return kvm_skip_emulated_instruction(vcpu); 5077 } 5078 } 5079 return kvm_emulate_instruction(vcpu, 0); 5080 } 5081 5082 static int handle_apic_eoi_induced(struct kvm_vcpu *vcpu) 5083 { 5084 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION); 5085 int vector = exit_qualification & 0xff; 5086 5087 /* EOI-induced VM exit is trap-like and thus no need to adjust IP */ 5088 kvm_apic_set_eoi_accelerated(vcpu, vector); 5089 return 1; 5090 } 5091 5092 static int handle_apic_write(struct kvm_vcpu *vcpu) 5093 { 5094 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION); 5095 u32 offset = exit_qualification & 0xfff; 5096 5097 /* APIC-write VM exit is trap-like and thus no need to adjust IP */ 5098 kvm_apic_write_nodecode(vcpu, offset); 5099 return 1; 5100 } 5101 5102 static int handle_task_switch(struct kvm_vcpu *vcpu) 5103 { 5104 struct vcpu_vmx *vmx = to_vmx(vcpu); 5105 unsigned long exit_qualification; 5106 bool has_error_code = false; 5107 u32 error_code = 0; 5108 u16 tss_selector; 5109 int reason, type, idt_v, idt_index; 5110 5111 idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK); 5112 idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK); 5113 type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK); 5114 5115 exit_qualification = vmcs_readl(EXIT_QUALIFICATION); 5116 5117 reason = (u32)exit_qualification >> 30; 5118 if (reason == TASK_SWITCH_GATE && idt_v) { 5119 switch (type) { 5120 case INTR_TYPE_NMI_INTR: 5121 vcpu->arch.nmi_injected = false; 5122 vmx_set_nmi_mask(vcpu, true); 5123 break; 5124 case INTR_TYPE_EXT_INTR: 5125 case INTR_TYPE_SOFT_INTR: 5126 kvm_clear_interrupt_queue(vcpu); 5127 break; 5128 case INTR_TYPE_HARD_EXCEPTION: 5129 if (vmx->idt_vectoring_info & 5130 VECTORING_INFO_DELIVER_CODE_MASK) { 5131 has_error_code = true; 5132 error_code = 5133 vmcs_read32(IDT_VECTORING_ERROR_CODE); 5134 } 5135 /* fall through */ 5136 case INTR_TYPE_SOFT_EXCEPTION: 5137 kvm_clear_exception_queue(vcpu); 5138 break; 5139 default: 5140 break; 5141 } 5142 } 5143 tss_selector = exit_qualification; 5144 5145 if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION && 5146 type != INTR_TYPE_EXT_INTR && 5147 type != INTR_TYPE_NMI_INTR)) 5148 WARN_ON(!skip_emulated_instruction(vcpu)); 5149 5150 /* 5151 * TODO: What about debug traps on tss switch? 5152 * Are we supposed to inject them and update dr6? 5153 */ 5154 return kvm_task_switch(vcpu, tss_selector, 5155 type == INTR_TYPE_SOFT_INTR ? idt_index : -1, 5156 reason, has_error_code, error_code); 5157 } 5158 5159 static int handle_ept_violation(struct kvm_vcpu *vcpu) 5160 { 5161 unsigned long exit_qualification; 5162 gpa_t gpa; 5163 u64 error_code; 5164 5165 exit_qualification = vmcs_readl(EXIT_QUALIFICATION); 5166 5167 /* 5168 * EPT violation happened while executing iret from NMI, 5169 * "blocked by NMI" bit has to be set before next VM entry. 5170 * There are errata that may cause this bit to not be set: 5171 * AAK134, BY25. 5172 */ 5173 if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) && 5174 enable_vnmi && 5175 (exit_qualification & INTR_INFO_UNBLOCK_NMI)) 5176 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, GUEST_INTR_STATE_NMI); 5177 5178 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS); 5179 trace_kvm_page_fault(gpa, exit_qualification); 5180 5181 /* Is it a read fault? */ 5182 error_code = (exit_qualification & EPT_VIOLATION_ACC_READ) 5183 ? PFERR_USER_MASK : 0; 5184 /* Is it a write fault? */ 5185 error_code |= (exit_qualification & EPT_VIOLATION_ACC_WRITE) 5186 ? PFERR_WRITE_MASK : 0; 5187 /* Is it a fetch fault? */ 5188 error_code |= (exit_qualification & EPT_VIOLATION_ACC_INSTR) 5189 ? PFERR_FETCH_MASK : 0; 5190 /* ept page table entry is present? */ 5191 error_code |= (exit_qualification & 5192 (EPT_VIOLATION_READABLE | EPT_VIOLATION_WRITABLE | 5193 EPT_VIOLATION_EXECUTABLE)) 5194 ? PFERR_PRESENT_MASK : 0; 5195 5196 error_code |= (exit_qualification & 0x100) != 0 ? 5197 PFERR_GUEST_FINAL_MASK : PFERR_GUEST_PAGE_MASK; 5198 5199 vcpu->arch.exit_qualification = exit_qualification; 5200 return kvm_mmu_page_fault(vcpu, gpa, error_code, NULL, 0); 5201 } 5202 5203 static int handle_ept_misconfig(struct kvm_vcpu *vcpu) 5204 { 5205 gpa_t gpa; 5206 5207 /* 5208 * A nested guest cannot optimize MMIO vmexits, because we have an 5209 * nGPA here instead of the required GPA. 5210 */ 5211 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS); 5212 if (!is_guest_mode(vcpu) && 5213 !kvm_io_bus_write(vcpu, KVM_FAST_MMIO_BUS, gpa, 0, NULL)) { 5214 trace_kvm_fast_mmio(gpa); 5215 return kvm_skip_emulated_instruction(vcpu); 5216 } 5217 5218 return kvm_mmu_page_fault(vcpu, gpa, PFERR_RSVD_MASK, NULL, 0); 5219 } 5220 5221 static int handle_nmi_window(struct kvm_vcpu *vcpu) 5222 { 5223 WARN_ON_ONCE(!enable_vnmi); 5224 exec_controls_clearbit(to_vmx(vcpu), CPU_BASED_NMI_WINDOW_EXITING); 5225 ++vcpu->stat.nmi_window_exits; 5226 kvm_make_request(KVM_REQ_EVENT, vcpu); 5227 5228 return 1; 5229 } 5230 5231 static int handle_invalid_guest_state(struct kvm_vcpu *vcpu) 5232 { 5233 struct vcpu_vmx *vmx = to_vmx(vcpu); 5234 bool intr_window_requested; 5235 unsigned count = 130; 5236 5237 /* 5238 * We should never reach the point where we are emulating L2 5239 * due to invalid guest state as that means we incorrectly 5240 * allowed a nested VMEntry with an invalid vmcs12. 5241 */ 5242 WARN_ON_ONCE(vmx->emulation_required && vmx->nested.nested_run_pending); 5243 5244 intr_window_requested = exec_controls_get(vmx) & 5245 CPU_BASED_INTR_WINDOW_EXITING; 5246 5247 while (vmx->emulation_required && count-- != 0) { 5248 if (intr_window_requested && vmx_interrupt_allowed(vcpu)) 5249 return handle_interrupt_window(&vmx->vcpu); 5250 5251 if (kvm_test_request(KVM_REQ_EVENT, vcpu)) 5252 return 1; 5253 5254 if (!kvm_emulate_instruction(vcpu, 0)) 5255 return 0; 5256 5257 if (vmx->emulation_required && !vmx->rmode.vm86_active && 5258 vcpu->arch.exception.pending) { 5259 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR; 5260 vcpu->run->internal.suberror = 5261 KVM_INTERNAL_ERROR_EMULATION; 5262 vcpu->run->internal.ndata = 0; 5263 return 0; 5264 } 5265 5266 if (vcpu->arch.halt_request) { 5267 vcpu->arch.halt_request = 0; 5268 return kvm_vcpu_halt(vcpu); 5269 } 5270 5271 /* 5272 * Note, return 1 and not 0, vcpu_run() is responsible for 5273 * morphing the pending signal into the proper return code. 5274 */ 5275 if (signal_pending(current)) 5276 return 1; 5277 5278 if (need_resched()) 5279 schedule(); 5280 } 5281 5282 return 1; 5283 } 5284 5285 static void grow_ple_window(struct kvm_vcpu *vcpu) 5286 { 5287 struct vcpu_vmx *vmx = to_vmx(vcpu); 5288 unsigned int old = vmx->ple_window; 5289 5290 vmx->ple_window = __grow_ple_window(old, ple_window, 5291 ple_window_grow, 5292 ple_window_max); 5293 5294 if (vmx->ple_window != old) { 5295 vmx->ple_window_dirty = true; 5296 trace_kvm_ple_window_update(vcpu->vcpu_id, 5297 vmx->ple_window, old); 5298 } 5299 } 5300 5301 static void shrink_ple_window(struct kvm_vcpu *vcpu) 5302 { 5303 struct vcpu_vmx *vmx = to_vmx(vcpu); 5304 unsigned int old = vmx->ple_window; 5305 5306 vmx->ple_window = __shrink_ple_window(old, ple_window, 5307 ple_window_shrink, 5308 ple_window); 5309 5310 if (vmx->ple_window != old) { 5311 vmx->ple_window_dirty = true; 5312 trace_kvm_ple_window_update(vcpu->vcpu_id, 5313 vmx->ple_window, old); 5314 } 5315 } 5316 5317 /* 5318 * Handler for POSTED_INTERRUPT_WAKEUP_VECTOR. 5319 */ 5320 static void wakeup_handler(void) 5321 { 5322 struct kvm_vcpu *vcpu; 5323 int cpu = smp_processor_id(); 5324 5325 spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu)); 5326 list_for_each_entry(vcpu, &per_cpu(blocked_vcpu_on_cpu, cpu), 5327 blocked_vcpu_list) { 5328 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu); 5329 5330 if (pi_test_on(pi_desc) == 1) 5331 kvm_vcpu_kick(vcpu); 5332 } 5333 spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu)); 5334 } 5335 5336 static void vmx_enable_tdp(void) 5337 { 5338 kvm_mmu_set_mask_ptes(VMX_EPT_READABLE_MASK, 5339 enable_ept_ad_bits ? VMX_EPT_ACCESS_BIT : 0ull, 5340 enable_ept_ad_bits ? VMX_EPT_DIRTY_BIT : 0ull, 5341 0ull, VMX_EPT_EXECUTABLE_MASK, 5342 cpu_has_vmx_ept_execute_only() ? 0ull : VMX_EPT_READABLE_MASK, 5343 VMX_EPT_RWX_MASK, 0ull); 5344 5345 ept_set_mmio_spte_mask(); 5346 kvm_enable_tdp(); 5347 } 5348 5349 /* 5350 * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE 5351 * exiting, so only get here on cpu with PAUSE-Loop-Exiting. 5352 */ 5353 static int handle_pause(struct kvm_vcpu *vcpu) 5354 { 5355 if (!kvm_pause_in_guest(vcpu->kvm)) 5356 grow_ple_window(vcpu); 5357 5358 /* 5359 * Intel sdm vol3 ch-25.1.3 says: The "PAUSE-loop exiting" 5360 * VM-execution control is ignored if CPL > 0. OTOH, KVM 5361 * never set PAUSE_EXITING and just set PLE if supported, 5362 * so the vcpu must be CPL=0 if it gets a PAUSE exit. 5363 */ 5364 kvm_vcpu_on_spin(vcpu, true); 5365 return kvm_skip_emulated_instruction(vcpu); 5366 } 5367 5368 static int handle_nop(struct kvm_vcpu *vcpu) 5369 { 5370 return kvm_skip_emulated_instruction(vcpu); 5371 } 5372 5373 static int handle_mwait(struct kvm_vcpu *vcpu) 5374 { 5375 printk_once(KERN_WARNING "kvm: MWAIT instruction emulated as NOP!\n"); 5376 return handle_nop(vcpu); 5377 } 5378 5379 static int handle_invalid_op(struct kvm_vcpu *vcpu) 5380 { 5381 kvm_queue_exception(vcpu, UD_VECTOR); 5382 return 1; 5383 } 5384 5385 static int handle_monitor_trap(struct kvm_vcpu *vcpu) 5386 { 5387 return 1; 5388 } 5389 5390 static int handle_monitor(struct kvm_vcpu *vcpu) 5391 { 5392 printk_once(KERN_WARNING "kvm: MONITOR instruction emulated as NOP!\n"); 5393 return handle_nop(vcpu); 5394 } 5395 5396 static int handle_invpcid(struct kvm_vcpu *vcpu) 5397 { 5398 u32 vmx_instruction_info; 5399 unsigned long type; 5400 bool pcid_enabled; 5401 gva_t gva; 5402 struct x86_exception e; 5403 unsigned i; 5404 unsigned long roots_to_free = 0; 5405 struct { 5406 u64 pcid; 5407 u64 gla; 5408 } operand; 5409 5410 if (!guest_cpuid_has(vcpu, X86_FEATURE_INVPCID)) { 5411 kvm_queue_exception(vcpu, UD_VECTOR); 5412 return 1; 5413 } 5414 5415 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO); 5416 type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf); 5417 5418 if (type > 3) { 5419 kvm_inject_gp(vcpu, 0); 5420 return 1; 5421 } 5422 5423 /* According to the Intel instruction reference, the memory operand 5424 * is read even if it isn't needed (e.g., for type==all) 5425 */ 5426 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION), 5427 vmx_instruction_info, false, 5428 sizeof(operand), &gva)) 5429 return 1; 5430 5431 if (kvm_read_guest_virt(vcpu, gva, &operand, sizeof(operand), &e)) { 5432 kvm_inject_page_fault(vcpu, &e); 5433 return 1; 5434 } 5435 5436 if (operand.pcid >> 12 != 0) { 5437 kvm_inject_gp(vcpu, 0); 5438 return 1; 5439 } 5440 5441 pcid_enabled = kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE); 5442 5443 switch (type) { 5444 case INVPCID_TYPE_INDIV_ADDR: 5445 if ((!pcid_enabled && (operand.pcid != 0)) || 5446 is_noncanonical_address(operand.gla, vcpu)) { 5447 kvm_inject_gp(vcpu, 0); 5448 return 1; 5449 } 5450 kvm_mmu_invpcid_gva(vcpu, operand.gla, operand.pcid); 5451 return kvm_skip_emulated_instruction(vcpu); 5452 5453 case INVPCID_TYPE_SINGLE_CTXT: 5454 if (!pcid_enabled && (operand.pcid != 0)) { 5455 kvm_inject_gp(vcpu, 0); 5456 return 1; 5457 } 5458 5459 if (kvm_get_active_pcid(vcpu) == operand.pcid) { 5460 kvm_mmu_sync_roots(vcpu); 5461 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu); 5462 } 5463 5464 for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++) 5465 if (kvm_get_pcid(vcpu, vcpu->arch.mmu->prev_roots[i].cr3) 5466 == operand.pcid) 5467 roots_to_free |= KVM_MMU_ROOT_PREVIOUS(i); 5468 5469 kvm_mmu_free_roots(vcpu, vcpu->arch.mmu, roots_to_free); 5470 /* 5471 * If neither the current cr3 nor any of the prev_roots use the 5472 * given PCID, then nothing needs to be done here because a 5473 * resync will happen anyway before switching to any other CR3. 5474 */ 5475 5476 return kvm_skip_emulated_instruction(vcpu); 5477 5478 case INVPCID_TYPE_ALL_NON_GLOBAL: 5479 /* 5480 * Currently, KVM doesn't mark global entries in the shadow 5481 * page tables, so a non-global flush just degenerates to a 5482 * global flush. If needed, we could optimize this later by 5483 * keeping track of global entries in shadow page tables. 5484 */ 5485 5486 /* fall-through */ 5487 case INVPCID_TYPE_ALL_INCL_GLOBAL: 5488 kvm_mmu_unload(vcpu); 5489 return kvm_skip_emulated_instruction(vcpu); 5490 5491 default: 5492 BUG(); /* We have already checked above that type <= 3 */ 5493 } 5494 } 5495 5496 static int handle_pml_full(struct kvm_vcpu *vcpu) 5497 { 5498 unsigned long exit_qualification; 5499 5500 trace_kvm_pml_full(vcpu->vcpu_id); 5501 5502 exit_qualification = vmcs_readl(EXIT_QUALIFICATION); 5503 5504 /* 5505 * PML buffer FULL happened while executing iret from NMI, 5506 * "blocked by NMI" bit has to be set before next VM entry. 5507 */ 5508 if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) && 5509 enable_vnmi && 5510 (exit_qualification & INTR_INFO_UNBLOCK_NMI)) 5511 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, 5512 GUEST_INTR_STATE_NMI); 5513 5514 /* 5515 * PML buffer already flushed at beginning of VMEXIT. Nothing to do 5516 * here.., and there's no userspace involvement needed for PML. 5517 */ 5518 return 1; 5519 } 5520 5521 static int handle_preemption_timer(struct kvm_vcpu *vcpu) 5522 { 5523 struct vcpu_vmx *vmx = to_vmx(vcpu); 5524 5525 if (!vmx->req_immediate_exit && 5526 !unlikely(vmx->loaded_vmcs->hv_timer_soft_disabled)) 5527 kvm_lapic_expired_hv_timer(vcpu); 5528 5529 return 1; 5530 } 5531 5532 /* 5533 * When nested=0, all VMX instruction VM Exits filter here. The handlers 5534 * are overwritten by nested_vmx_setup() when nested=1. 5535 */ 5536 static int handle_vmx_instruction(struct kvm_vcpu *vcpu) 5537 { 5538 kvm_queue_exception(vcpu, UD_VECTOR); 5539 return 1; 5540 } 5541 5542 static int handle_encls(struct kvm_vcpu *vcpu) 5543 { 5544 /* 5545 * SGX virtualization is not yet supported. There is no software 5546 * enable bit for SGX, so we have to trap ENCLS and inject a #UD 5547 * to prevent the guest from executing ENCLS. 5548 */ 5549 kvm_queue_exception(vcpu, UD_VECTOR); 5550 return 1; 5551 } 5552 5553 /* 5554 * The exit handlers return 1 if the exit was handled fully and guest execution 5555 * may resume. Otherwise they set the kvm_run parameter to indicate what needs 5556 * to be done to userspace and return 0. 5557 */ 5558 static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = { 5559 [EXIT_REASON_EXCEPTION_NMI] = handle_exception_nmi, 5560 [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt, 5561 [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault, 5562 [EXIT_REASON_NMI_WINDOW] = handle_nmi_window, 5563 [EXIT_REASON_IO_INSTRUCTION] = handle_io, 5564 [EXIT_REASON_CR_ACCESS] = handle_cr, 5565 [EXIT_REASON_DR_ACCESS] = handle_dr, 5566 [EXIT_REASON_CPUID] = kvm_emulate_cpuid, 5567 [EXIT_REASON_MSR_READ] = kvm_emulate_rdmsr, 5568 [EXIT_REASON_MSR_WRITE] = kvm_emulate_wrmsr, 5569 [EXIT_REASON_INTERRUPT_WINDOW] = handle_interrupt_window, 5570 [EXIT_REASON_HLT] = kvm_emulate_halt, 5571 [EXIT_REASON_INVD] = handle_invd, 5572 [EXIT_REASON_INVLPG] = handle_invlpg, 5573 [EXIT_REASON_RDPMC] = handle_rdpmc, 5574 [EXIT_REASON_VMCALL] = handle_vmcall, 5575 [EXIT_REASON_VMCLEAR] = handle_vmx_instruction, 5576 [EXIT_REASON_VMLAUNCH] = handle_vmx_instruction, 5577 [EXIT_REASON_VMPTRLD] = handle_vmx_instruction, 5578 [EXIT_REASON_VMPTRST] = handle_vmx_instruction, 5579 [EXIT_REASON_VMREAD] = handle_vmx_instruction, 5580 [EXIT_REASON_VMRESUME] = handle_vmx_instruction, 5581 [EXIT_REASON_VMWRITE] = handle_vmx_instruction, 5582 [EXIT_REASON_VMOFF] = handle_vmx_instruction, 5583 [EXIT_REASON_VMON] = handle_vmx_instruction, 5584 [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold, 5585 [EXIT_REASON_APIC_ACCESS] = handle_apic_access, 5586 [EXIT_REASON_APIC_WRITE] = handle_apic_write, 5587 [EXIT_REASON_EOI_INDUCED] = handle_apic_eoi_induced, 5588 [EXIT_REASON_WBINVD] = handle_wbinvd, 5589 [EXIT_REASON_XSETBV] = handle_xsetbv, 5590 [EXIT_REASON_TASK_SWITCH] = handle_task_switch, 5591 [EXIT_REASON_MCE_DURING_VMENTRY] = handle_machine_check, 5592 [EXIT_REASON_GDTR_IDTR] = handle_desc, 5593 [EXIT_REASON_LDTR_TR] = handle_desc, 5594 [EXIT_REASON_EPT_VIOLATION] = handle_ept_violation, 5595 [EXIT_REASON_EPT_MISCONFIG] = handle_ept_misconfig, 5596 [EXIT_REASON_PAUSE_INSTRUCTION] = handle_pause, 5597 [EXIT_REASON_MWAIT_INSTRUCTION] = handle_mwait, 5598 [EXIT_REASON_MONITOR_TRAP_FLAG] = handle_monitor_trap, 5599 [EXIT_REASON_MONITOR_INSTRUCTION] = handle_monitor, 5600 [EXIT_REASON_INVEPT] = handle_vmx_instruction, 5601 [EXIT_REASON_INVVPID] = handle_vmx_instruction, 5602 [EXIT_REASON_RDRAND] = handle_invalid_op, 5603 [EXIT_REASON_RDSEED] = handle_invalid_op, 5604 [EXIT_REASON_PML_FULL] = handle_pml_full, 5605 [EXIT_REASON_INVPCID] = handle_invpcid, 5606 [EXIT_REASON_VMFUNC] = handle_vmx_instruction, 5607 [EXIT_REASON_PREEMPTION_TIMER] = handle_preemption_timer, 5608 [EXIT_REASON_ENCLS] = handle_encls, 5609 }; 5610 5611 static const int kvm_vmx_max_exit_handlers = 5612 ARRAY_SIZE(kvm_vmx_exit_handlers); 5613 5614 static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2) 5615 { 5616 *info1 = vmcs_readl(EXIT_QUALIFICATION); 5617 *info2 = vmcs_read32(VM_EXIT_INTR_INFO); 5618 } 5619 5620 static void vmx_destroy_pml_buffer(struct vcpu_vmx *vmx) 5621 { 5622 if (vmx->pml_pg) { 5623 __free_page(vmx->pml_pg); 5624 vmx->pml_pg = NULL; 5625 } 5626 } 5627 5628 static void vmx_flush_pml_buffer(struct kvm_vcpu *vcpu) 5629 { 5630 struct vcpu_vmx *vmx = to_vmx(vcpu); 5631 u64 *pml_buf; 5632 u16 pml_idx; 5633 5634 pml_idx = vmcs_read16(GUEST_PML_INDEX); 5635 5636 /* Do nothing if PML buffer is empty */ 5637 if (pml_idx == (PML_ENTITY_NUM - 1)) 5638 return; 5639 5640 /* PML index always points to next available PML buffer entity */ 5641 if (pml_idx >= PML_ENTITY_NUM) 5642 pml_idx = 0; 5643 else 5644 pml_idx++; 5645 5646 pml_buf = page_address(vmx->pml_pg); 5647 for (; pml_idx < PML_ENTITY_NUM; pml_idx++) { 5648 u64 gpa; 5649 5650 gpa = pml_buf[pml_idx]; 5651 WARN_ON(gpa & (PAGE_SIZE - 1)); 5652 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT); 5653 } 5654 5655 /* reset PML index */ 5656 vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1); 5657 } 5658 5659 /* 5660 * Flush all vcpus' PML buffer and update logged GPAs to dirty_bitmap. 5661 * Called before reporting dirty_bitmap to userspace. 5662 */ 5663 static void kvm_flush_pml_buffers(struct kvm *kvm) 5664 { 5665 int i; 5666 struct kvm_vcpu *vcpu; 5667 /* 5668 * We only need to kick vcpu out of guest mode here, as PML buffer 5669 * is flushed at beginning of all VMEXITs, and it's obvious that only 5670 * vcpus running in guest are possible to have unflushed GPAs in PML 5671 * buffer. 5672 */ 5673 kvm_for_each_vcpu(i, vcpu, kvm) 5674 kvm_vcpu_kick(vcpu); 5675 } 5676 5677 static void vmx_dump_sel(char *name, uint32_t sel) 5678 { 5679 pr_err("%s sel=0x%04x, attr=0x%05x, limit=0x%08x, base=0x%016lx\n", 5680 name, vmcs_read16(sel), 5681 vmcs_read32(sel + GUEST_ES_AR_BYTES - GUEST_ES_SELECTOR), 5682 vmcs_read32(sel + GUEST_ES_LIMIT - GUEST_ES_SELECTOR), 5683 vmcs_readl(sel + GUEST_ES_BASE - GUEST_ES_SELECTOR)); 5684 } 5685 5686 static void vmx_dump_dtsel(char *name, uint32_t limit) 5687 { 5688 pr_err("%s limit=0x%08x, base=0x%016lx\n", 5689 name, vmcs_read32(limit), 5690 vmcs_readl(limit + GUEST_GDTR_BASE - GUEST_GDTR_LIMIT)); 5691 } 5692 5693 void dump_vmcs(void) 5694 { 5695 u32 vmentry_ctl, vmexit_ctl; 5696 u32 cpu_based_exec_ctrl, pin_based_exec_ctrl, secondary_exec_control; 5697 unsigned long cr4; 5698 u64 efer; 5699 int i, n; 5700 5701 if (!dump_invalid_vmcs) { 5702 pr_warn_ratelimited("set kvm_intel.dump_invalid_vmcs=1 to dump internal KVM state.\n"); 5703 return; 5704 } 5705 5706 vmentry_ctl = vmcs_read32(VM_ENTRY_CONTROLS); 5707 vmexit_ctl = vmcs_read32(VM_EXIT_CONTROLS); 5708 cpu_based_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL); 5709 pin_based_exec_ctrl = vmcs_read32(PIN_BASED_VM_EXEC_CONTROL); 5710 cr4 = vmcs_readl(GUEST_CR4); 5711 efer = vmcs_read64(GUEST_IA32_EFER); 5712 secondary_exec_control = 0; 5713 if (cpu_has_secondary_exec_ctrls()) 5714 secondary_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL); 5715 5716 pr_err("*** Guest State ***\n"); 5717 pr_err("CR0: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n", 5718 vmcs_readl(GUEST_CR0), vmcs_readl(CR0_READ_SHADOW), 5719 vmcs_readl(CR0_GUEST_HOST_MASK)); 5720 pr_err("CR4: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n", 5721 cr4, vmcs_readl(CR4_READ_SHADOW), vmcs_readl(CR4_GUEST_HOST_MASK)); 5722 pr_err("CR3 = 0x%016lx\n", vmcs_readl(GUEST_CR3)); 5723 if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT) && 5724 (cr4 & X86_CR4_PAE) && !(efer & EFER_LMA)) 5725 { 5726 pr_err("PDPTR0 = 0x%016llx PDPTR1 = 0x%016llx\n", 5727 vmcs_read64(GUEST_PDPTR0), vmcs_read64(GUEST_PDPTR1)); 5728 pr_err("PDPTR2 = 0x%016llx PDPTR3 = 0x%016llx\n", 5729 vmcs_read64(GUEST_PDPTR2), vmcs_read64(GUEST_PDPTR3)); 5730 } 5731 pr_err("RSP = 0x%016lx RIP = 0x%016lx\n", 5732 vmcs_readl(GUEST_RSP), vmcs_readl(GUEST_RIP)); 5733 pr_err("RFLAGS=0x%08lx DR7 = 0x%016lx\n", 5734 vmcs_readl(GUEST_RFLAGS), vmcs_readl(GUEST_DR7)); 5735 pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n", 5736 vmcs_readl(GUEST_SYSENTER_ESP), 5737 vmcs_read32(GUEST_SYSENTER_CS), vmcs_readl(GUEST_SYSENTER_EIP)); 5738 vmx_dump_sel("CS: ", GUEST_CS_SELECTOR); 5739 vmx_dump_sel("DS: ", GUEST_DS_SELECTOR); 5740 vmx_dump_sel("SS: ", GUEST_SS_SELECTOR); 5741 vmx_dump_sel("ES: ", GUEST_ES_SELECTOR); 5742 vmx_dump_sel("FS: ", GUEST_FS_SELECTOR); 5743 vmx_dump_sel("GS: ", GUEST_GS_SELECTOR); 5744 vmx_dump_dtsel("GDTR:", GUEST_GDTR_LIMIT); 5745 vmx_dump_sel("LDTR:", GUEST_LDTR_SELECTOR); 5746 vmx_dump_dtsel("IDTR:", GUEST_IDTR_LIMIT); 5747 vmx_dump_sel("TR: ", GUEST_TR_SELECTOR); 5748 if ((vmexit_ctl & (VM_EXIT_SAVE_IA32_PAT | VM_EXIT_SAVE_IA32_EFER)) || 5749 (vmentry_ctl & (VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_IA32_EFER))) 5750 pr_err("EFER = 0x%016llx PAT = 0x%016llx\n", 5751 efer, vmcs_read64(GUEST_IA32_PAT)); 5752 pr_err("DebugCtl = 0x%016llx DebugExceptions = 0x%016lx\n", 5753 vmcs_read64(GUEST_IA32_DEBUGCTL), 5754 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS)); 5755 if (cpu_has_load_perf_global_ctrl() && 5756 vmentry_ctl & VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL) 5757 pr_err("PerfGlobCtl = 0x%016llx\n", 5758 vmcs_read64(GUEST_IA32_PERF_GLOBAL_CTRL)); 5759 if (vmentry_ctl & VM_ENTRY_LOAD_BNDCFGS) 5760 pr_err("BndCfgS = 0x%016llx\n", vmcs_read64(GUEST_BNDCFGS)); 5761 pr_err("Interruptibility = %08x ActivityState = %08x\n", 5762 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO), 5763 vmcs_read32(GUEST_ACTIVITY_STATE)); 5764 if (secondary_exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) 5765 pr_err("InterruptStatus = %04x\n", 5766 vmcs_read16(GUEST_INTR_STATUS)); 5767 5768 pr_err("*** Host State ***\n"); 5769 pr_err("RIP = 0x%016lx RSP = 0x%016lx\n", 5770 vmcs_readl(HOST_RIP), vmcs_readl(HOST_RSP)); 5771 pr_err("CS=%04x SS=%04x DS=%04x ES=%04x FS=%04x GS=%04x TR=%04x\n", 5772 vmcs_read16(HOST_CS_SELECTOR), vmcs_read16(HOST_SS_SELECTOR), 5773 vmcs_read16(HOST_DS_SELECTOR), vmcs_read16(HOST_ES_SELECTOR), 5774 vmcs_read16(HOST_FS_SELECTOR), vmcs_read16(HOST_GS_SELECTOR), 5775 vmcs_read16(HOST_TR_SELECTOR)); 5776 pr_err("FSBase=%016lx GSBase=%016lx TRBase=%016lx\n", 5777 vmcs_readl(HOST_FS_BASE), vmcs_readl(HOST_GS_BASE), 5778 vmcs_readl(HOST_TR_BASE)); 5779 pr_err("GDTBase=%016lx IDTBase=%016lx\n", 5780 vmcs_readl(HOST_GDTR_BASE), vmcs_readl(HOST_IDTR_BASE)); 5781 pr_err("CR0=%016lx CR3=%016lx CR4=%016lx\n", 5782 vmcs_readl(HOST_CR0), vmcs_readl(HOST_CR3), 5783 vmcs_readl(HOST_CR4)); 5784 pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n", 5785 vmcs_readl(HOST_IA32_SYSENTER_ESP), 5786 vmcs_read32(HOST_IA32_SYSENTER_CS), 5787 vmcs_readl(HOST_IA32_SYSENTER_EIP)); 5788 if (vmexit_ctl & (VM_EXIT_LOAD_IA32_PAT | VM_EXIT_LOAD_IA32_EFER)) 5789 pr_err("EFER = 0x%016llx PAT = 0x%016llx\n", 5790 vmcs_read64(HOST_IA32_EFER), 5791 vmcs_read64(HOST_IA32_PAT)); 5792 if (cpu_has_load_perf_global_ctrl() && 5793 vmexit_ctl & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL) 5794 pr_err("PerfGlobCtl = 0x%016llx\n", 5795 vmcs_read64(HOST_IA32_PERF_GLOBAL_CTRL)); 5796 5797 pr_err("*** Control State ***\n"); 5798 pr_err("PinBased=%08x CPUBased=%08x SecondaryExec=%08x\n", 5799 pin_based_exec_ctrl, cpu_based_exec_ctrl, secondary_exec_control); 5800 pr_err("EntryControls=%08x ExitControls=%08x\n", vmentry_ctl, vmexit_ctl); 5801 pr_err("ExceptionBitmap=%08x PFECmask=%08x PFECmatch=%08x\n", 5802 vmcs_read32(EXCEPTION_BITMAP), 5803 vmcs_read32(PAGE_FAULT_ERROR_CODE_MASK), 5804 vmcs_read32(PAGE_FAULT_ERROR_CODE_MATCH)); 5805 pr_err("VMEntry: intr_info=%08x errcode=%08x ilen=%08x\n", 5806 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD), 5807 vmcs_read32(VM_ENTRY_EXCEPTION_ERROR_CODE), 5808 vmcs_read32(VM_ENTRY_INSTRUCTION_LEN)); 5809 pr_err("VMExit: intr_info=%08x errcode=%08x ilen=%08x\n", 5810 vmcs_read32(VM_EXIT_INTR_INFO), 5811 vmcs_read32(VM_EXIT_INTR_ERROR_CODE), 5812 vmcs_read32(VM_EXIT_INSTRUCTION_LEN)); 5813 pr_err(" reason=%08x qualification=%016lx\n", 5814 vmcs_read32(VM_EXIT_REASON), vmcs_readl(EXIT_QUALIFICATION)); 5815 pr_err("IDTVectoring: info=%08x errcode=%08x\n", 5816 vmcs_read32(IDT_VECTORING_INFO_FIELD), 5817 vmcs_read32(IDT_VECTORING_ERROR_CODE)); 5818 pr_err("TSC Offset = 0x%016llx\n", vmcs_read64(TSC_OFFSET)); 5819 if (secondary_exec_control & SECONDARY_EXEC_TSC_SCALING) 5820 pr_err("TSC Multiplier = 0x%016llx\n", 5821 vmcs_read64(TSC_MULTIPLIER)); 5822 if (cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW) { 5823 if (secondary_exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) { 5824 u16 status = vmcs_read16(GUEST_INTR_STATUS); 5825 pr_err("SVI|RVI = %02x|%02x ", status >> 8, status & 0xff); 5826 } 5827 pr_cont("TPR Threshold = 0x%02x\n", vmcs_read32(TPR_THRESHOLD)); 5828 if (secondary_exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) 5829 pr_err("APIC-access addr = 0x%016llx ", vmcs_read64(APIC_ACCESS_ADDR)); 5830 pr_cont("virt-APIC addr = 0x%016llx\n", vmcs_read64(VIRTUAL_APIC_PAGE_ADDR)); 5831 } 5832 if (pin_based_exec_ctrl & PIN_BASED_POSTED_INTR) 5833 pr_err("PostedIntrVec = 0x%02x\n", vmcs_read16(POSTED_INTR_NV)); 5834 if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT)) 5835 pr_err("EPT pointer = 0x%016llx\n", vmcs_read64(EPT_POINTER)); 5836 n = vmcs_read32(CR3_TARGET_COUNT); 5837 for (i = 0; i + 1 < n; i += 4) 5838 pr_err("CR3 target%u=%016lx target%u=%016lx\n", 5839 i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2), 5840 i + 1, vmcs_readl(CR3_TARGET_VALUE0 + i * 2 + 2)); 5841 if (i < n) 5842 pr_err("CR3 target%u=%016lx\n", 5843 i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2)); 5844 if (secondary_exec_control & SECONDARY_EXEC_PAUSE_LOOP_EXITING) 5845 pr_err("PLE Gap=%08x Window=%08x\n", 5846 vmcs_read32(PLE_GAP), vmcs_read32(PLE_WINDOW)); 5847 if (secondary_exec_control & SECONDARY_EXEC_ENABLE_VPID) 5848 pr_err("Virtual processor ID = 0x%04x\n", 5849 vmcs_read16(VIRTUAL_PROCESSOR_ID)); 5850 } 5851 5852 /* 5853 * The guest has exited. See if we can fix it or if we need userspace 5854 * assistance. 5855 */ 5856 static int vmx_handle_exit(struct kvm_vcpu *vcpu, 5857 enum exit_fastpath_completion exit_fastpath) 5858 { 5859 struct vcpu_vmx *vmx = to_vmx(vcpu); 5860 u32 exit_reason = vmx->exit_reason; 5861 u32 vectoring_info = vmx->idt_vectoring_info; 5862 5863 trace_kvm_exit(exit_reason, vcpu, KVM_ISA_VMX); 5864 5865 /* 5866 * Flush logged GPAs PML buffer, this will make dirty_bitmap more 5867 * updated. Another good is, in kvm_vm_ioctl_get_dirty_log, before 5868 * querying dirty_bitmap, we only need to kick all vcpus out of guest 5869 * mode as if vcpus is in root mode, the PML buffer must has been 5870 * flushed already. 5871 */ 5872 if (enable_pml) 5873 vmx_flush_pml_buffer(vcpu); 5874 5875 /* If guest state is invalid, start emulating */ 5876 if (vmx->emulation_required) 5877 return handle_invalid_guest_state(vcpu); 5878 5879 if (is_guest_mode(vcpu) && nested_vmx_exit_reflected(vcpu, exit_reason)) 5880 return nested_vmx_reflect_vmexit(vcpu, exit_reason); 5881 5882 if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) { 5883 dump_vmcs(); 5884 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY; 5885 vcpu->run->fail_entry.hardware_entry_failure_reason 5886 = exit_reason; 5887 return 0; 5888 } 5889 5890 if (unlikely(vmx->fail)) { 5891 dump_vmcs(); 5892 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY; 5893 vcpu->run->fail_entry.hardware_entry_failure_reason 5894 = vmcs_read32(VM_INSTRUCTION_ERROR); 5895 return 0; 5896 } 5897 5898 /* 5899 * Note: 5900 * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by 5901 * delivery event since it indicates guest is accessing MMIO. 5902 * The vm-exit can be triggered again after return to guest that 5903 * will cause infinite loop. 5904 */ 5905 if ((vectoring_info & VECTORING_INFO_VALID_MASK) && 5906 (exit_reason != EXIT_REASON_EXCEPTION_NMI && 5907 exit_reason != EXIT_REASON_EPT_VIOLATION && 5908 exit_reason != EXIT_REASON_PML_FULL && 5909 exit_reason != EXIT_REASON_TASK_SWITCH)) { 5910 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR; 5911 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_DELIVERY_EV; 5912 vcpu->run->internal.ndata = 3; 5913 vcpu->run->internal.data[0] = vectoring_info; 5914 vcpu->run->internal.data[1] = exit_reason; 5915 vcpu->run->internal.data[2] = vcpu->arch.exit_qualification; 5916 if (exit_reason == EXIT_REASON_EPT_MISCONFIG) { 5917 vcpu->run->internal.ndata++; 5918 vcpu->run->internal.data[3] = 5919 vmcs_read64(GUEST_PHYSICAL_ADDRESS); 5920 } 5921 return 0; 5922 } 5923 5924 if (unlikely(!enable_vnmi && 5925 vmx->loaded_vmcs->soft_vnmi_blocked)) { 5926 if (vmx_interrupt_allowed(vcpu)) { 5927 vmx->loaded_vmcs->soft_vnmi_blocked = 0; 5928 } else if (vmx->loaded_vmcs->vnmi_blocked_time > 1000000000LL && 5929 vcpu->arch.nmi_pending) { 5930 /* 5931 * This CPU don't support us in finding the end of an 5932 * NMI-blocked window if the guest runs with IRQs 5933 * disabled. So we pull the trigger after 1 s of 5934 * futile waiting, but inform the user about this. 5935 */ 5936 printk(KERN_WARNING "%s: Breaking out of NMI-blocked " 5937 "state on VCPU %d after 1 s timeout\n", 5938 __func__, vcpu->vcpu_id); 5939 vmx->loaded_vmcs->soft_vnmi_blocked = 0; 5940 } 5941 } 5942 5943 if (exit_fastpath == EXIT_FASTPATH_SKIP_EMUL_INS) { 5944 kvm_skip_emulated_instruction(vcpu); 5945 return 1; 5946 } 5947 5948 if (exit_reason >= kvm_vmx_max_exit_handlers) 5949 goto unexpected_vmexit; 5950 #ifdef CONFIG_RETPOLINE 5951 if (exit_reason == EXIT_REASON_MSR_WRITE) 5952 return kvm_emulate_wrmsr(vcpu); 5953 else if (exit_reason == EXIT_REASON_PREEMPTION_TIMER) 5954 return handle_preemption_timer(vcpu); 5955 else if (exit_reason == EXIT_REASON_INTERRUPT_WINDOW) 5956 return handle_interrupt_window(vcpu); 5957 else if (exit_reason == EXIT_REASON_EXTERNAL_INTERRUPT) 5958 return handle_external_interrupt(vcpu); 5959 else if (exit_reason == EXIT_REASON_HLT) 5960 return kvm_emulate_halt(vcpu); 5961 else if (exit_reason == EXIT_REASON_EPT_MISCONFIG) 5962 return handle_ept_misconfig(vcpu); 5963 #endif 5964 5965 exit_reason = array_index_nospec(exit_reason, 5966 kvm_vmx_max_exit_handlers); 5967 if (!kvm_vmx_exit_handlers[exit_reason]) 5968 goto unexpected_vmexit; 5969 5970 return kvm_vmx_exit_handlers[exit_reason](vcpu); 5971 5972 unexpected_vmexit: 5973 vcpu_unimpl(vcpu, "vmx: unexpected exit reason 0x%x\n", exit_reason); 5974 dump_vmcs(); 5975 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR; 5976 vcpu->run->internal.suberror = 5977 KVM_INTERNAL_ERROR_UNEXPECTED_EXIT_REASON; 5978 vcpu->run->internal.ndata = 1; 5979 vcpu->run->internal.data[0] = exit_reason; 5980 return 0; 5981 } 5982 5983 /* 5984 * Software based L1D cache flush which is used when microcode providing 5985 * the cache control MSR is not loaded. 5986 * 5987 * The L1D cache is 32 KiB on Nehalem and later microarchitectures, but to 5988 * flush it is required to read in 64 KiB because the replacement algorithm 5989 * is not exactly LRU. This could be sized at runtime via topology 5990 * information but as all relevant affected CPUs have 32KiB L1D cache size 5991 * there is no point in doing so. 5992 */ 5993 static void vmx_l1d_flush(struct kvm_vcpu *vcpu) 5994 { 5995 int size = PAGE_SIZE << L1D_CACHE_ORDER; 5996 5997 /* 5998 * This code is only executed when the the flush mode is 'cond' or 5999 * 'always' 6000 */ 6001 if (static_branch_likely(&vmx_l1d_flush_cond)) { 6002 bool flush_l1d; 6003 6004 /* 6005 * Clear the per-vcpu flush bit, it gets set again 6006 * either from vcpu_run() or from one of the unsafe 6007 * VMEXIT handlers. 6008 */ 6009 flush_l1d = vcpu->arch.l1tf_flush_l1d; 6010 vcpu->arch.l1tf_flush_l1d = false; 6011 6012 /* 6013 * Clear the per-cpu flush bit, it gets set again from 6014 * the interrupt handlers. 6015 */ 6016 flush_l1d |= kvm_get_cpu_l1tf_flush_l1d(); 6017 kvm_clear_cpu_l1tf_flush_l1d(); 6018 6019 if (!flush_l1d) 6020 return; 6021 } 6022 6023 vcpu->stat.l1d_flush++; 6024 6025 if (static_cpu_has(X86_FEATURE_FLUSH_L1D)) { 6026 wrmsrl(MSR_IA32_FLUSH_CMD, L1D_FLUSH); 6027 return; 6028 } 6029 6030 asm volatile( 6031 /* First ensure the pages are in the TLB */ 6032 "xorl %%eax, %%eax\n" 6033 ".Lpopulate_tlb:\n\t" 6034 "movzbl (%[flush_pages], %%" _ASM_AX "), %%ecx\n\t" 6035 "addl $4096, %%eax\n\t" 6036 "cmpl %%eax, %[size]\n\t" 6037 "jne .Lpopulate_tlb\n\t" 6038 "xorl %%eax, %%eax\n\t" 6039 "cpuid\n\t" 6040 /* Now fill the cache */ 6041 "xorl %%eax, %%eax\n" 6042 ".Lfill_cache:\n" 6043 "movzbl (%[flush_pages], %%" _ASM_AX "), %%ecx\n\t" 6044 "addl $64, %%eax\n\t" 6045 "cmpl %%eax, %[size]\n\t" 6046 "jne .Lfill_cache\n\t" 6047 "lfence\n" 6048 :: [flush_pages] "r" (vmx_l1d_flush_pages), 6049 [size] "r" (size) 6050 : "eax", "ebx", "ecx", "edx"); 6051 } 6052 6053 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr) 6054 { 6055 struct vmcs12 *vmcs12 = get_vmcs12(vcpu); 6056 int tpr_threshold; 6057 6058 if (is_guest_mode(vcpu) && 6059 nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW)) 6060 return; 6061 6062 tpr_threshold = (irr == -1 || tpr < irr) ? 0 : irr; 6063 if (is_guest_mode(vcpu)) 6064 to_vmx(vcpu)->nested.l1_tpr_threshold = tpr_threshold; 6065 else 6066 vmcs_write32(TPR_THRESHOLD, tpr_threshold); 6067 } 6068 6069 void vmx_set_virtual_apic_mode(struct kvm_vcpu *vcpu) 6070 { 6071 struct vcpu_vmx *vmx = to_vmx(vcpu); 6072 u32 sec_exec_control; 6073 6074 if (!lapic_in_kernel(vcpu)) 6075 return; 6076 6077 if (!flexpriority_enabled && 6078 !cpu_has_vmx_virtualize_x2apic_mode()) 6079 return; 6080 6081 /* Postpone execution until vmcs01 is the current VMCS. */ 6082 if (is_guest_mode(vcpu)) { 6083 vmx->nested.change_vmcs01_virtual_apic_mode = true; 6084 return; 6085 } 6086 6087 sec_exec_control = secondary_exec_controls_get(vmx); 6088 sec_exec_control &= ~(SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 6089 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE); 6090 6091 switch (kvm_get_apic_mode(vcpu)) { 6092 case LAPIC_MODE_INVALID: 6093 WARN_ONCE(true, "Invalid local APIC state"); 6094 case LAPIC_MODE_DISABLED: 6095 break; 6096 case LAPIC_MODE_XAPIC: 6097 if (flexpriority_enabled) { 6098 sec_exec_control |= 6099 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES; 6100 vmx_flush_tlb(vcpu, true); 6101 } 6102 break; 6103 case LAPIC_MODE_X2APIC: 6104 if (cpu_has_vmx_virtualize_x2apic_mode()) 6105 sec_exec_control |= 6106 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE; 6107 break; 6108 } 6109 secondary_exec_controls_set(vmx, sec_exec_control); 6110 6111 vmx_update_msr_bitmap(vcpu); 6112 } 6113 6114 static void vmx_set_apic_access_page_addr(struct kvm_vcpu *vcpu, hpa_t hpa) 6115 { 6116 if (!is_guest_mode(vcpu)) { 6117 vmcs_write64(APIC_ACCESS_ADDR, hpa); 6118 vmx_flush_tlb(vcpu, true); 6119 } 6120 } 6121 6122 static void vmx_hwapic_isr_update(struct kvm_vcpu *vcpu, int max_isr) 6123 { 6124 u16 status; 6125 u8 old; 6126 6127 if (max_isr == -1) 6128 max_isr = 0; 6129 6130 status = vmcs_read16(GUEST_INTR_STATUS); 6131 old = status >> 8; 6132 if (max_isr != old) { 6133 status &= 0xff; 6134 status |= max_isr << 8; 6135 vmcs_write16(GUEST_INTR_STATUS, status); 6136 } 6137 } 6138 6139 static void vmx_set_rvi(int vector) 6140 { 6141 u16 status; 6142 u8 old; 6143 6144 if (vector == -1) 6145 vector = 0; 6146 6147 status = vmcs_read16(GUEST_INTR_STATUS); 6148 old = (u8)status & 0xff; 6149 if ((u8)vector != old) { 6150 status &= ~0xff; 6151 status |= (u8)vector; 6152 vmcs_write16(GUEST_INTR_STATUS, status); 6153 } 6154 } 6155 6156 static void vmx_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr) 6157 { 6158 /* 6159 * When running L2, updating RVI is only relevant when 6160 * vmcs12 virtual-interrupt-delivery enabled. 6161 * However, it can be enabled only when L1 also 6162 * intercepts external-interrupts and in that case 6163 * we should not update vmcs02 RVI but instead intercept 6164 * interrupt. Therefore, do nothing when running L2. 6165 */ 6166 if (!is_guest_mode(vcpu)) 6167 vmx_set_rvi(max_irr); 6168 } 6169 6170 static int vmx_sync_pir_to_irr(struct kvm_vcpu *vcpu) 6171 { 6172 struct vcpu_vmx *vmx = to_vmx(vcpu); 6173 int max_irr; 6174 bool max_irr_updated; 6175 6176 WARN_ON(!vcpu->arch.apicv_active); 6177 if (pi_test_on(&vmx->pi_desc)) { 6178 pi_clear_on(&vmx->pi_desc); 6179 /* 6180 * IOMMU can write to PID.ON, so the barrier matters even on UP. 6181 * But on x86 this is just a compiler barrier anyway. 6182 */ 6183 smp_mb__after_atomic(); 6184 max_irr_updated = 6185 kvm_apic_update_irr(vcpu, vmx->pi_desc.pir, &max_irr); 6186 6187 /* 6188 * If we are running L2 and L1 has a new pending interrupt 6189 * which can be injected, we should re-evaluate 6190 * what should be done with this new L1 interrupt. 6191 * If L1 intercepts external-interrupts, we should 6192 * exit from L2 to L1. Otherwise, interrupt should be 6193 * delivered directly to L2. 6194 */ 6195 if (is_guest_mode(vcpu) && max_irr_updated) { 6196 if (nested_exit_on_intr(vcpu)) 6197 kvm_vcpu_exiting_guest_mode(vcpu); 6198 else 6199 kvm_make_request(KVM_REQ_EVENT, vcpu); 6200 } 6201 } else { 6202 max_irr = kvm_lapic_find_highest_irr(vcpu); 6203 } 6204 vmx_hwapic_irr_update(vcpu, max_irr); 6205 return max_irr; 6206 } 6207 6208 static bool vmx_dy_apicv_has_pending_interrupt(struct kvm_vcpu *vcpu) 6209 { 6210 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu); 6211 6212 return pi_test_on(pi_desc) || 6213 (pi_test_sn(pi_desc) && !pi_is_pir_empty(pi_desc)); 6214 } 6215 6216 static void vmx_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap) 6217 { 6218 if (!kvm_vcpu_apicv_active(vcpu)) 6219 return; 6220 6221 vmcs_write64(EOI_EXIT_BITMAP0, eoi_exit_bitmap[0]); 6222 vmcs_write64(EOI_EXIT_BITMAP1, eoi_exit_bitmap[1]); 6223 vmcs_write64(EOI_EXIT_BITMAP2, eoi_exit_bitmap[2]); 6224 vmcs_write64(EOI_EXIT_BITMAP3, eoi_exit_bitmap[3]); 6225 } 6226 6227 static void vmx_apicv_post_state_restore(struct kvm_vcpu *vcpu) 6228 { 6229 struct vcpu_vmx *vmx = to_vmx(vcpu); 6230 6231 pi_clear_on(&vmx->pi_desc); 6232 memset(vmx->pi_desc.pir, 0, sizeof(vmx->pi_desc.pir)); 6233 } 6234 6235 static void handle_exception_nmi_irqoff(struct vcpu_vmx *vmx) 6236 { 6237 vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO); 6238 6239 /* if exit due to PF check for async PF */ 6240 if (is_page_fault(vmx->exit_intr_info)) 6241 vmx->vcpu.arch.apf.host_apf_reason = kvm_read_and_reset_pf_reason(); 6242 6243 /* Handle machine checks before interrupts are enabled */ 6244 if (is_machine_check(vmx->exit_intr_info)) 6245 kvm_machine_check(); 6246 6247 /* We need to handle NMIs before interrupts are enabled */ 6248 if (is_nmi(vmx->exit_intr_info)) { 6249 kvm_before_interrupt(&vmx->vcpu); 6250 asm("int $2"); 6251 kvm_after_interrupt(&vmx->vcpu); 6252 } 6253 } 6254 6255 static void handle_external_interrupt_irqoff(struct kvm_vcpu *vcpu) 6256 { 6257 unsigned int vector; 6258 unsigned long entry; 6259 #ifdef CONFIG_X86_64 6260 unsigned long tmp; 6261 #endif 6262 gate_desc *desc; 6263 u32 intr_info; 6264 6265 intr_info = vmcs_read32(VM_EXIT_INTR_INFO); 6266 if (WARN_ONCE(!is_external_intr(intr_info), 6267 "KVM: unexpected VM-Exit interrupt info: 0x%x", intr_info)) 6268 return; 6269 6270 vector = intr_info & INTR_INFO_VECTOR_MASK; 6271 desc = (gate_desc *)host_idt_base + vector; 6272 entry = gate_offset(desc); 6273 6274 kvm_before_interrupt(vcpu); 6275 6276 asm volatile( 6277 #ifdef CONFIG_X86_64 6278 "mov %%" _ASM_SP ", %[sp]\n\t" 6279 "and $0xfffffffffffffff0, %%" _ASM_SP "\n\t" 6280 "push $%c[ss]\n\t" 6281 "push %[sp]\n\t" 6282 #endif 6283 "pushf\n\t" 6284 __ASM_SIZE(push) " $%c[cs]\n\t" 6285 CALL_NOSPEC 6286 : 6287 #ifdef CONFIG_X86_64 6288 [sp]"=&r"(tmp), 6289 #endif 6290 ASM_CALL_CONSTRAINT 6291 : 6292 [thunk_target]"r"(entry), 6293 [ss]"i"(__KERNEL_DS), 6294 [cs]"i"(__KERNEL_CS) 6295 ); 6296 6297 kvm_after_interrupt(vcpu); 6298 } 6299 STACK_FRAME_NON_STANDARD(handle_external_interrupt_irqoff); 6300 6301 static void vmx_handle_exit_irqoff(struct kvm_vcpu *vcpu, 6302 enum exit_fastpath_completion *exit_fastpath) 6303 { 6304 struct vcpu_vmx *vmx = to_vmx(vcpu); 6305 6306 if (vmx->exit_reason == EXIT_REASON_EXTERNAL_INTERRUPT) 6307 handle_external_interrupt_irqoff(vcpu); 6308 else if (vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI) 6309 handle_exception_nmi_irqoff(vmx); 6310 else if (!is_guest_mode(vcpu) && 6311 vmx->exit_reason == EXIT_REASON_MSR_WRITE) 6312 *exit_fastpath = handle_fastpath_set_msr_irqoff(vcpu); 6313 } 6314 6315 static bool vmx_has_emulated_msr(int index) 6316 { 6317 switch (index) { 6318 case MSR_IA32_SMBASE: 6319 /* 6320 * We cannot do SMM unless we can run the guest in big 6321 * real mode. 6322 */ 6323 return enable_unrestricted_guest || emulate_invalid_guest_state; 6324 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC: 6325 return nested; 6326 case MSR_AMD64_VIRT_SPEC_CTRL: 6327 /* This is AMD only. */ 6328 return false; 6329 default: 6330 return true; 6331 } 6332 } 6333 6334 static bool vmx_pt_supported(void) 6335 { 6336 return pt_mode == PT_MODE_HOST_GUEST; 6337 } 6338 6339 static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx) 6340 { 6341 u32 exit_intr_info; 6342 bool unblock_nmi; 6343 u8 vector; 6344 bool idtv_info_valid; 6345 6346 idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK; 6347 6348 if (enable_vnmi) { 6349 if (vmx->loaded_vmcs->nmi_known_unmasked) 6350 return; 6351 /* 6352 * Can't use vmx->exit_intr_info since we're not sure what 6353 * the exit reason is. 6354 */ 6355 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO); 6356 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0; 6357 vector = exit_intr_info & INTR_INFO_VECTOR_MASK; 6358 /* 6359 * SDM 3: 27.7.1.2 (September 2008) 6360 * Re-set bit "block by NMI" before VM entry if vmexit caused by 6361 * a guest IRET fault. 6362 * SDM 3: 23.2.2 (September 2008) 6363 * Bit 12 is undefined in any of the following cases: 6364 * If the VM exit sets the valid bit in the IDT-vectoring 6365 * information field. 6366 * If the VM exit is due to a double fault. 6367 */ 6368 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi && 6369 vector != DF_VECTOR && !idtv_info_valid) 6370 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, 6371 GUEST_INTR_STATE_NMI); 6372 else 6373 vmx->loaded_vmcs->nmi_known_unmasked = 6374 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) 6375 & GUEST_INTR_STATE_NMI); 6376 } else if (unlikely(vmx->loaded_vmcs->soft_vnmi_blocked)) 6377 vmx->loaded_vmcs->vnmi_blocked_time += 6378 ktime_to_ns(ktime_sub(ktime_get(), 6379 vmx->loaded_vmcs->entry_time)); 6380 } 6381 6382 static void __vmx_complete_interrupts(struct kvm_vcpu *vcpu, 6383 u32 idt_vectoring_info, 6384 int instr_len_field, 6385 int error_code_field) 6386 { 6387 u8 vector; 6388 int type; 6389 bool idtv_info_valid; 6390 6391 idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK; 6392 6393 vcpu->arch.nmi_injected = false; 6394 kvm_clear_exception_queue(vcpu); 6395 kvm_clear_interrupt_queue(vcpu); 6396 6397 if (!idtv_info_valid) 6398 return; 6399 6400 kvm_make_request(KVM_REQ_EVENT, vcpu); 6401 6402 vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK; 6403 type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK; 6404 6405 switch (type) { 6406 case INTR_TYPE_NMI_INTR: 6407 vcpu->arch.nmi_injected = true; 6408 /* 6409 * SDM 3: 27.7.1.2 (September 2008) 6410 * Clear bit "block by NMI" before VM entry if a NMI 6411 * delivery faulted. 6412 */ 6413 vmx_set_nmi_mask(vcpu, false); 6414 break; 6415 case INTR_TYPE_SOFT_EXCEPTION: 6416 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field); 6417 /* fall through */ 6418 case INTR_TYPE_HARD_EXCEPTION: 6419 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) { 6420 u32 err = vmcs_read32(error_code_field); 6421 kvm_requeue_exception_e(vcpu, vector, err); 6422 } else 6423 kvm_requeue_exception(vcpu, vector); 6424 break; 6425 case INTR_TYPE_SOFT_INTR: 6426 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field); 6427 /* fall through */ 6428 case INTR_TYPE_EXT_INTR: 6429 kvm_queue_interrupt(vcpu, vector, type == INTR_TYPE_SOFT_INTR); 6430 break; 6431 default: 6432 break; 6433 } 6434 } 6435 6436 static void vmx_complete_interrupts(struct vcpu_vmx *vmx) 6437 { 6438 __vmx_complete_interrupts(&vmx->vcpu, vmx->idt_vectoring_info, 6439 VM_EXIT_INSTRUCTION_LEN, 6440 IDT_VECTORING_ERROR_CODE); 6441 } 6442 6443 static void vmx_cancel_injection(struct kvm_vcpu *vcpu) 6444 { 6445 __vmx_complete_interrupts(vcpu, 6446 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD), 6447 VM_ENTRY_INSTRUCTION_LEN, 6448 VM_ENTRY_EXCEPTION_ERROR_CODE); 6449 6450 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); 6451 } 6452 6453 static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx) 6454 { 6455 int i, nr_msrs; 6456 struct perf_guest_switch_msr *msrs; 6457 6458 msrs = perf_guest_get_msrs(&nr_msrs); 6459 6460 if (!msrs) 6461 return; 6462 6463 for (i = 0; i < nr_msrs; i++) 6464 if (msrs[i].host == msrs[i].guest) 6465 clear_atomic_switch_msr(vmx, msrs[i].msr); 6466 else 6467 add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest, 6468 msrs[i].host, false); 6469 } 6470 6471 static void atomic_switch_umwait_control_msr(struct vcpu_vmx *vmx) 6472 { 6473 u32 host_umwait_control; 6474 6475 if (!vmx_has_waitpkg(vmx)) 6476 return; 6477 6478 host_umwait_control = get_umwait_control_msr(); 6479 6480 if (vmx->msr_ia32_umwait_control != host_umwait_control) 6481 add_atomic_switch_msr(vmx, MSR_IA32_UMWAIT_CONTROL, 6482 vmx->msr_ia32_umwait_control, 6483 host_umwait_control, false); 6484 else 6485 clear_atomic_switch_msr(vmx, MSR_IA32_UMWAIT_CONTROL); 6486 } 6487 6488 static void vmx_update_hv_timer(struct kvm_vcpu *vcpu) 6489 { 6490 struct vcpu_vmx *vmx = to_vmx(vcpu); 6491 u64 tscl; 6492 u32 delta_tsc; 6493 6494 if (vmx->req_immediate_exit) { 6495 vmcs_write32(VMX_PREEMPTION_TIMER_VALUE, 0); 6496 vmx->loaded_vmcs->hv_timer_soft_disabled = false; 6497 } else if (vmx->hv_deadline_tsc != -1) { 6498 tscl = rdtsc(); 6499 if (vmx->hv_deadline_tsc > tscl) 6500 /* set_hv_timer ensures the delta fits in 32-bits */ 6501 delta_tsc = (u32)((vmx->hv_deadline_tsc - tscl) >> 6502 cpu_preemption_timer_multi); 6503 else 6504 delta_tsc = 0; 6505 6506 vmcs_write32(VMX_PREEMPTION_TIMER_VALUE, delta_tsc); 6507 vmx->loaded_vmcs->hv_timer_soft_disabled = false; 6508 } else if (!vmx->loaded_vmcs->hv_timer_soft_disabled) { 6509 vmcs_write32(VMX_PREEMPTION_TIMER_VALUE, -1); 6510 vmx->loaded_vmcs->hv_timer_soft_disabled = true; 6511 } 6512 } 6513 6514 void vmx_update_host_rsp(struct vcpu_vmx *vmx, unsigned long host_rsp) 6515 { 6516 if (unlikely(host_rsp != vmx->loaded_vmcs->host_state.rsp)) { 6517 vmx->loaded_vmcs->host_state.rsp = host_rsp; 6518 vmcs_writel(HOST_RSP, host_rsp); 6519 } 6520 } 6521 6522 bool __vmx_vcpu_run(struct vcpu_vmx *vmx, unsigned long *regs, bool launched); 6523 6524 static void vmx_vcpu_run(struct kvm_vcpu *vcpu) 6525 { 6526 struct vcpu_vmx *vmx = to_vmx(vcpu); 6527 unsigned long cr3, cr4; 6528 6529 /* Record the guest's net vcpu time for enforced NMI injections. */ 6530 if (unlikely(!enable_vnmi && 6531 vmx->loaded_vmcs->soft_vnmi_blocked)) 6532 vmx->loaded_vmcs->entry_time = ktime_get(); 6533 6534 /* Don't enter VMX if guest state is invalid, let the exit handler 6535 start emulation until we arrive back to a valid state */ 6536 if (vmx->emulation_required) 6537 return; 6538 6539 if (vmx->ple_window_dirty) { 6540 vmx->ple_window_dirty = false; 6541 vmcs_write32(PLE_WINDOW, vmx->ple_window); 6542 } 6543 6544 /* 6545 * We did this in prepare_switch_to_guest, because it needs to 6546 * be within srcu_read_lock. 6547 */ 6548 WARN_ON_ONCE(vmx->nested.need_vmcs12_to_shadow_sync); 6549 6550 if (kvm_register_is_dirty(vcpu, VCPU_REGS_RSP)) 6551 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]); 6552 if (kvm_register_is_dirty(vcpu, VCPU_REGS_RIP)) 6553 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]); 6554 6555 cr3 = __get_current_cr3_fast(); 6556 if (unlikely(cr3 != vmx->loaded_vmcs->host_state.cr3)) { 6557 vmcs_writel(HOST_CR3, cr3); 6558 vmx->loaded_vmcs->host_state.cr3 = cr3; 6559 } 6560 6561 cr4 = cr4_read_shadow(); 6562 if (unlikely(cr4 != vmx->loaded_vmcs->host_state.cr4)) { 6563 vmcs_writel(HOST_CR4, cr4); 6564 vmx->loaded_vmcs->host_state.cr4 = cr4; 6565 } 6566 6567 /* When single-stepping over STI and MOV SS, we must clear the 6568 * corresponding interruptibility bits in the guest state. Otherwise 6569 * vmentry fails as it then expects bit 14 (BS) in pending debug 6570 * exceptions being set, but that's not correct for the guest debugging 6571 * case. */ 6572 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) 6573 vmx_set_interrupt_shadow(vcpu, 0); 6574 6575 kvm_load_guest_xsave_state(vcpu); 6576 6577 if (static_cpu_has(X86_FEATURE_PKU) && 6578 kvm_read_cr4_bits(vcpu, X86_CR4_PKE) && 6579 vcpu->arch.pkru != vmx->host_pkru) 6580 __write_pkru(vcpu->arch.pkru); 6581 6582 pt_guest_enter(vmx); 6583 6584 atomic_switch_perf_msrs(vmx); 6585 atomic_switch_umwait_control_msr(vmx); 6586 6587 if (enable_preemption_timer) 6588 vmx_update_hv_timer(vcpu); 6589 6590 if (lapic_in_kernel(vcpu) && 6591 vcpu->arch.apic->lapic_timer.timer_advance_ns) 6592 kvm_wait_lapic_expire(vcpu); 6593 6594 /* 6595 * If this vCPU has touched SPEC_CTRL, restore the guest's value if 6596 * it's non-zero. Since vmentry is serialising on affected CPUs, there 6597 * is no need to worry about the conditional branch over the wrmsr 6598 * being speculatively taken. 6599 */ 6600 x86_spec_ctrl_set_guest(vmx->spec_ctrl, 0); 6601 6602 /* L1D Flush includes CPU buffer clear to mitigate MDS */ 6603 if (static_branch_unlikely(&vmx_l1d_should_flush)) 6604 vmx_l1d_flush(vcpu); 6605 else if (static_branch_unlikely(&mds_user_clear)) 6606 mds_clear_cpu_buffers(); 6607 6608 if (vcpu->arch.cr2 != read_cr2()) 6609 write_cr2(vcpu->arch.cr2); 6610 6611 vmx->fail = __vmx_vcpu_run(vmx, (unsigned long *)&vcpu->arch.regs, 6612 vmx->loaded_vmcs->launched); 6613 6614 vcpu->arch.cr2 = read_cr2(); 6615 6616 /* 6617 * We do not use IBRS in the kernel. If this vCPU has used the 6618 * SPEC_CTRL MSR it may have left it on; save the value and 6619 * turn it off. This is much more efficient than blindly adding 6620 * it to the atomic save/restore list. Especially as the former 6621 * (Saving guest MSRs on vmexit) doesn't even exist in KVM. 6622 * 6623 * For non-nested case: 6624 * If the L01 MSR bitmap does not intercept the MSR, then we need to 6625 * save it. 6626 * 6627 * For nested case: 6628 * If the L02 MSR bitmap does not intercept the MSR, then we need to 6629 * save it. 6630 */ 6631 if (unlikely(!msr_write_intercepted(vcpu, MSR_IA32_SPEC_CTRL))) 6632 vmx->spec_ctrl = native_read_msr(MSR_IA32_SPEC_CTRL); 6633 6634 x86_spec_ctrl_restore_host(vmx->spec_ctrl, 0); 6635 6636 /* All fields are clean at this point */ 6637 if (static_branch_unlikely(&enable_evmcs)) 6638 current_evmcs->hv_clean_fields |= 6639 HV_VMX_ENLIGHTENED_CLEAN_FIELD_ALL; 6640 6641 if (static_branch_unlikely(&enable_evmcs)) 6642 current_evmcs->hv_vp_id = vcpu->arch.hyperv.vp_index; 6643 6644 /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */ 6645 if (vmx->host_debugctlmsr) 6646 update_debugctlmsr(vmx->host_debugctlmsr); 6647 6648 #ifndef CONFIG_X86_64 6649 /* 6650 * The sysexit path does not restore ds/es, so we must set them to 6651 * a reasonable value ourselves. 6652 * 6653 * We can't defer this to vmx_prepare_switch_to_host() since that 6654 * function may be executed in interrupt context, which saves and 6655 * restore segments around it, nullifying its effect. 6656 */ 6657 loadsegment(ds, __USER_DS); 6658 loadsegment(es, __USER_DS); 6659 #endif 6660 6661 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP) 6662 | (1 << VCPU_EXREG_RFLAGS) 6663 | (1 << VCPU_EXREG_PDPTR) 6664 | (1 << VCPU_EXREG_SEGMENTS) 6665 | (1 << VCPU_EXREG_CR3)); 6666 vcpu->arch.regs_dirty = 0; 6667 6668 pt_guest_exit(vmx); 6669 6670 /* 6671 * eager fpu is enabled if PKEY is supported and CR4 is switched 6672 * back on host, so it is safe to read guest PKRU from current 6673 * XSAVE. 6674 */ 6675 if (static_cpu_has(X86_FEATURE_PKU) && 6676 kvm_read_cr4_bits(vcpu, X86_CR4_PKE)) { 6677 vcpu->arch.pkru = rdpkru(); 6678 if (vcpu->arch.pkru != vmx->host_pkru) 6679 __write_pkru(vmx->host_pkru); 6680 } 6681 6682 kvm_load_host_xsave_state(vcpu); 6683 6684 vmx->nested.nested_run_pending = 0; 6685 vmx->idt_vectoring_info = 0; 6686 6687 vmx->exit_reason = vmx->fail ? 0xdead : vmcs_read32(VM_EXIT_REASON); 6688 if ((u16)vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY) 6689 kvm_machine_check(); 6690 6691 if (vmx->fail || (vmx->exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY)) 6692 return; 6693 6694 vmx->loaded_vmcs->launched = 1; 6695 vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD); 6696 6697 vmx_recover_nmi_blocking(vmx); 6698 vmx_complete_interrupts(vmx); 6699 } 6700 6701 static struct kvm *vmx_vm_alloc(void) 6702 { 6703 struct kvm_vmx *kvm_vmx = __vmalloc(sizeof(struct kvm_vmx), 6704 GFP_KERNEL_ACCOUNT | __GFP_ZERO, 6705 PAGE_KERNEL); 6706 return &kvm_vmx->kvm; 6707 } 6708 6709 static void vmx_vm_free(struct kvm *kvm) 6710 { 6711 kfree(kvm->arch.hyperv.hv_pa_pg); 6712 vfree(to_kvm_vmx(kvm)); 6713 } 6714 6715 static void vmx_free_vcpu(struct kvm_vcpu *vcpu) 6716 { 6717 struct vcpu_vmx *vmx = to_vmx(vcpu); 6718 6719 if (enable_pml) 6720 vmx_destroy_pml_buffer(vmx); 6721 free_vpid(vmx->vpid); 6722 nested_vmx_free_vcpu(vcpu); 6723 free_loaded_vmcs(vmx->loaded_vmcs); 6724 } 6725 6726 static int vmx_create_vcpu(struct kvm_vcpu *vcpu) 6727 { 6728 struct vcpu_vmx *vmx; 6729 unsigned long *msr_bitmap; 6730 int i, cpu, err; 6731 6732 BUILD_BUG_ON(offsetof(struct vcpu_vmx, vcpu) != 0); 6733 vmx = to_vmx(vcpu); 6734 6735 err = -ENOMEM; 6736 6737 vmx->vpid = allocate_vpid(); 6738 6739 /* 6740 * If PML is turned on, failure on enabling PML just results in failure 6741 * of creating the vcpu, therefore we can simplify PML logic (by 6742 * avoiding dealing with cases, such as enabling PML partially on vcpus 6743 * for the guest), etc. 6744 */ 6745 if (enable_pml) { 6746 vmx->pml_pg = alloc_page(GFP_KERNEL_ACCOUNT | __GFP_ZERO); 6747 if (!vmx->pml_pg) 6748 goto free_vpid; 6749 } 6750 6751 BUILD_BUG_ON(ARRAY_SIZE(vmx_msr_index) != NR_SHARED_MSRS); 6752 6753 for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i) { 6754 u32 index = vmx_msr_index[i]; 6755 u32 data_low, data_high; 6756 int j = vmx->nmsrs; 6757 6758 if (rdmsr_safe(index, &data_low, &data_high) < 0) 6759 continue; 6760 if (wrmsr_safe(index, data_low, data_high) < 0) 6761 continue; 6762 6763 vmx->guest_msrs[j].index = i; 6764 vmx->guest_msrs[j].data = 0; 6765 switch (index) { 6766 case MSR_IA32_TSX_CTRL: 6767 /* 6768 * No need to pass TSX_CTRL_CPUID_CLEAR through, so 6769 * let's avoid changing CPUID bits under the host 6770 * kernel's feet. 6771 */ 6772 vmx->guest_msrs[j].mask = ~(u64)TSX_CTRL_CPUID_CLEAR; 6773 break; 6774 default: 6775 vmx->guest_msrs[j].mask = -1ull; 6776 break; 6777 } 6778 ++vmx->nmsrs; 6779 } 6780 6781 err = alloc_loaded_vmcs(&vmx->vmcs01); 6782 if (err < 0) 6783 goto free_pml; 6784 6785 msr_bitmap = vmx->vmcs01.msr_bitmap; 6786 vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_TSC, MSR_TYPE_R); 6787 vmx_disable_intercept_for_msr(msr_bitmap, MSR_FS_BASE, MSR_TYPE_RW); 6788 vmx_disable_intercept_for_msr(msr_bitmap, MSR_GS_BASE, MSR_TYPE_RW); 6789 vmx_disable_intercept_for_msr(msr_bitmap, MSR_KERNEL_GS_BASE, MSR_TYPE_RW); 6790 vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_SYSENTER_CS, MSR_TYPE_RW); 6791 vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_SYSENTER_ESP, MSR_TYPE_RW); 6792 vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_SYSENTER_EIP, MSR_TYPE_RW); 6793 if (kvm_cstate_in_guest(vcpu->kvm)) { 6794 vmx_disable_intercept_for_msr(msr_bitmap, MSR_CORE_C1_RES, MSR_TYPE_R); 6795 vmx_disable_intercept_for_msr(msr_bitmap, MSR_CORE_C3_RESIDENCY, MSR_TYPE_R); 6796 vmx_disable_intercept_for_msr(msr_bitmap, MSR_CORE_C6_RESIDENCY, MSR_TYPE_R); 6797 vmx_disable_intercept_for_msr(msr_bitmap, MSR_CORE_C7_RESIDENCY, MSR_TYPE_R); 6798 } 6799 vmx->msr_bitmap_mode = 0; 6800 6801 vmx->loaded_vmcs = &vmx->vmcs01; 6802 cpu = get_cpu(); 6803 vmx_vcpu_load(vcpu, cpu); 6804 vcpu->cpu = cpu; 6805 init_vmcs(vmx); 6806 vmx_vcpu_put(vcpu); 6807 put_cpu(); 6808 if (cpu_need_virtualize_apic_accesses(vcpu)) { 6809 err = alloc_apic_access_page(vcpu->kvm); 6810 if (err) 6811 goto free_vmcs; 6812 } 6813 6814 if (enable_ept && !enable_unrestricted_guest) { 6815 err = init_rmode_identity_map(vcpu->kvm); 6816 if (err) 6817 goto free_vmcs; 6818 } 6819 6820 if (nested) 6821 nested_vmx_setup_ctls_msrs(&vmx->nested.msrs, 6822 vmx_capability.ept); 6823 else 6824 memset(&vmx->nested.msrs, 0, sizeof(vmx->nested.msrs)); 6825 6826 vmx->nested.posted_intr_nv = -1; 6827 vmx->nested.current_vmptr = -1ull; 6828 6829 vcpu->arch.microcode_version = 0x100000000ULL; 6830 vmx->msr_ia32_feature_control_valid_bits = FEAT_CTL_LOCKED; 6831 6832 /* 6833 * Enforce invariant: pi_desc.nv is always either POSTED_INTR_VECTOR 6834 * or POSTED_INTR_WAKEUP_VECTOR. 6835 */ 6836 vmx->pi_desc.nv = POSTED_INTR_VECTOR; 6837 vmx->pi_desc.sn = 1; 6838 6839 vmx->ept_pointer = INVALID_PAGE; 6840 6841 return 0; 6842 6843 free_vmcs: 6844 free_loaded_vmcs(vmx->loaded_vmcs); 6845 free_pml: 6846 vmx_destroy_pml_buffer(vmx); 6847 free_vpid: 6848 free_vpid(vmx->vpid); 6849 return err; 6850 } 6851 6852 #define L1TF_MSG_SMT "L1TF CPU bug present and SMT on, data leak possible. See CVE-2018-3646 and https://www.kernel.org/doc/html/latest/admin-guide/hw-vuln/l1tf.html for details.\n" 6853 #define L1TF_MSG_L1D "L1TF CPU bug present and virtualization mitigation disabled, data leak possible. See CVE-2018-3646 and https://www.kernel.org/doc/html/latest/admin-guide/hw-vuln/l1tf.html for details.\n" 6854 6855 static int vmx_vm_init(struct kvm *kvm) 6856 { 6857 spin_lock_init(&to_kvm_vmx(kvm)->ept_pointer_lock); 6858 6859 if (!ple_gap) 6860 kvm->arch.pause_in_guest = true; 6861 6862 if (boot_cpu_has(X86_BUG_L1TF) && enable_ept) { 6863 switch (l1tf_mitigation) { 6864 case L1TF_MITIGATION_OFF: 6865 case L1TF_MITIGATION_FLUSH_NOWARN: 6866 /* 'I explicitly don't care' is set */ 6867 break; 6868 case L1TF_MITIGATION_FLUSH: 6869 case L1TF_MITIGATION_FLUSH_NOSMT: 6870 case L1TF_MITIGATION_FULL: 6871 /* 6872 * Warn upon starting the first VM in a potentially 6873 * insecure environment. 6874 */ 6875 if (sched_smt_active()) 6876 pr_warn_once(L1TF_MSG_SMT); 6877 if (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_NEVER) 6878 pr_warn_once(L1TF_MSG_L1D); 6879 break; 6880 case L1TF_MITIGATION_FULL_FORCE: 6881 /* Flush is enforced */ 6882 break; 6883 } 6884 } 6885 kvm_apicv_init(kvm, enable_apicv); 6886 return 0; 6887 } 6888 6889 static int __init vmx_check_processor_compat(void) 6890 { 6891 struct vmcs_config vmcs_conf; 6892 struct vmx_capability vmx_cap; 6893 6894 if (!this_cpu_has(X86_FEATURE_MSR_IA32_FEAT_CTL) || 6895 !this_cpu_has(X86_FEATURE_VMX)) { 6896 pr_err("kvm: VMX is disabled on CPU %d\n", smp_processor_id()); 6897 return -EIO; 6898 } 6899 6900 if (setup_vmcs_config(&vmcs_conf, &vmx_cap) < 0) 6901 return -EIO; 6902 if (nested) 6903 nested_vmx_setup_ctls_msrs(&vmcs_conf.nested, vmx_cap.ept); 6904 if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) { 6905 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n", 6906 smp_processor_id()); 6907 return -EIO; 6908 } 6909 return 0; 6910 } 6911 6912 static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio) 6913 { 6914 u8 cache; 6915 u64 ipat = 0; 6916 6917 /* For VT-d and EPT combination 6918 * 1. MMIO: always map as UC 6919 * 2. EPT with VT-d: 6920 * a. VT-d without snooping control feature: can't guarantee the 6921 * result, try to trust guest. 6922 * b. VT-d with snooping control feature: snooping control feature of 6923 * VT-d engine can guarantee the cache correctness. Just set it 6924 * to WB to keep consistent with host. So the same as item 3. 6925 * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep 6926 * consistent with host MTRR 6927 */ 6928 if (is_mmio) { 6929 cache = MTRR_TYPE_UNCACHABLE; 6930 goto exit; 6931 } 6932 6933 if (!kvm_arch_has_noncoherent_dma(vcpu->kvm)) { 6934 ipat = VMX_EPT_IPAT_BIT; 6935 cache = MTRR_TYPE_WRBACK; 6936 goto exit; 6937 } 6938 6939 if (kvm_read_cr0(vcpu) & X86_CR0_CD) { 6940 ipat = VMX_EPT_IPAT_BIT; 6941 if (kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED)) 6942 cache = MTRR_TYPE_WRBACK; 6943 else 6944 cache = MTRR_TYPE_UNCACHABLE; 6945 goto exit; 6946 } 6947 6948 cache = kvm_mtrr_get_guest_memory_type(vcpu, gfn); 6949 6950 exit: 6951 return (cache << VMX_EPT_MT_EPTE_SHIFT) | ipat; 6952 } 6953 6954 static int vmx_get_lpage_level(void) 6955 { 6956 if (enable_ept && !cpu_has_vmx_ept_1g_page()) 6957 return PT_DIRECTORY_LEVEL; 6958 else 6959 /* For shadow and EPT supported 1GB page */ 6960 return PT_PDPE_LEVEL; 6961 } 6962 6963 static void vmcs_set_secondary_exec_control(struct vcpu_vmx *vmx) 6964 { 6965 /* 6966 * These bits in the secondary execution controls field 6967 * are dynamic, the others are mostly based on the hypervisor 6968 * architecture and the guest's CPUID. Do not touch the 6969 * dynamic bits. 6970 */ 6971 u32 mask = 6972 SECONDARY_EXEC_SHADOW_VMCS | 6973 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 6974 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 6975 SECONDARY_EXEC_DESC; 6976 6977 u32 new_ctl = vmx->secondary_exec_control; 6978 u32 cur_ctl = secondary_exec_controls_get(vmx); 6979 6980 secondary_exec_controls_set(vmx, (new_ctl & ~mask) | (cur_ctl & mask)); 6981 } 6982 6983 /* 6984 * Generate MSR_IA32_VMX_CR{0,4}_FIXED1 according to CPUID. Only set bits 6985 * (indicating "allowed-1") if they are supported in the guest's CPUID. 6986 */ 6987 static void nested_vmx_cr_fixed1_bits_update(struct kvm_vcpu *vcpu) 6988 { 6989 struct vcpu_vmx *vmx = to_vmx(vcpu); 6990 struct kvm_cpuid_entry2 *entry; 6991 6992 vmx->nested.msrs.cr0_fixed1 = 0xffffffff; 6993 vmx->nested.msrs.cr4_fixed1 = X86_CR4_PCE; 6994 6995 #define cr4_fixed1_update(_cr4_mask, _reg, _cpuid_mask) do { \ 6996 if (entry && (entry->_reg & (_cpuid_mask))) \ 6997 vmx->nested.msrs.cr4_fixed1 |= (_cr4_mask); \ 6998 } while (0) 6999 7000 entry = kvm_find_cpuid_entry(vcpu, 0x1, 0); 7001 cr4_fixed1_update(X86_CR4_VME, edx, feature_bit(VME)); 7002 cr4_fixed1_update(X86_CR4_PVI, edx, feature_bit(VME)); 7003 cr4_fixed1_update(X86_CR4_TSD, edx, feature_bit(TSC)); 7004 cr4_fixed1_update(X86_CR4_DE, edx, feature_bit(DE)); 7005 cr4_fixed1_update(X86_CR4_PSE, edx, feature_bit(PSE)); 7006 cr4_fixed1_update(X86_CR4_PAE, edx, feature_bit(PAE)); 7007 cr4_fixed1_update(X86_CR4_MCE, edx, feature_bit(MCE)); 7008 cr4_fixed1_update(X86_CR4_PGE, edx, feature_bit(PGE)); 7009 cr4_fixed1_update(X86_CR4_OSFXSR, edx, feature_bit(FXSR)); 7010 cr4_fixed1_update(X86_CR4_OSXMMEXCPT, edx, feature_bit(XMM)); 7011 cr4_fixed1_update(X86_CR4_VMXE, ecx, feature_bit(VMX)); 7012 cr4_fixed1_update(X86_CR4_SMXE, ecx, feature_bit(SMX)); 7013 cr4_fixed1_update(X86_CR4_PCIDE, ecx, feature_bit(PCID)); 7014 cr4_fixed1_update(X86_CR4_OSXSAVE, ecx, feature_bit(XSAVE)); 7015 7016 entry = kvm_find_cpuid_entry(vcpu, 0x7, 0); 7017 cr4_fixed1_update(X86_CR4_FSGSBASE, ebx, feature_bit(FSGSBASE)); 7018 cr4_fixed1_update(X86_CR4_SMEP, ebx, feature_bit(SMEP)); 7019 cr4_fixed1_update(X86_CR4_SMAP, ebx, feature_bit(SMAP)); 7020 cr4_fixed1_update(X86_CR4_PKE, ecx, feature_bit(PKU)); 7021 cr4_fixed1_update(X86_CR4_UMIP, ecx, feature_bit(UMIP)); 7022 cr4_fixed1_update(X86_CR4_LA57, ecx, feature_bit(LA57)); 7023 7024 #undef cr4_fixed1_update 7025 } 7026 7027 static void nested_vmx_entry_exit_ctls_update(struct kvm_vcpu *vcpu) 7028 { 7029 struct vcpu_vmx *vmx = to_vmx(vcpu); 7030 7031 if (kvm_mpx_supported()) { 7032 bool mpx_enabled = guest_cpuid_has(vcpu, X86_FEATURE_MPX); 7033 7034 if (mpx_enabled) { 7035 vmx->nested.msrs.entry_ctls_high |= VM_ENTRY_LOAD_BNDCFGS; 7036 vmx->nested.msrs.exit_ctls_high |= VM_EXIT_CLEAR_BNDCFGS; 7037 } else { 7038 vmx->nested.msrs.entry_ctls_high &= ~VM_ENTRY_LOAD_BNDCFGS; 7039 vmx->nested.msrs.exit_ctls_high &= ~VM_EXIT_CLEAR_BNDCFGS; 7040 } 7041 } 7042 } 7043 7044 static void update_intel_pt_cfg(struct kvm_vcpu *vcpu) 7045 { 7046 struct vcpu_vmx *vmx = to_vmx(vcpu); 7047 struct kvm_cpuid_entry2 *best = NULL; 7048 int i; 7049 7050 for (i = 0; i < PT_CPUID_LEAVES; i++) { 7051 best = kvm_find_cpuid_entry(vcpu, 0x14, i); 7052 if (!best) 7053 return; 7054 vmx->pt_desc.caps[CPUID_EAX + i*PT_CPUID_REGS_NUM] = best->eax; 7055 vmx->pt_desc.caps[CPUID_EBX + i*PT_CPUID_REGS_NUM] = best->ebx; 7056 vmx->pt_desc.caps[CPUID_ECX + i*PT_CPUID_REGS_NUM] = best->ecx; 7057 vmx->pt_desc.caps[CPUID_EDX + i*PT_CPUID_REGS_NUM] = best->edx; 7058 } 7059 7060 /* Get the number of configurable Address Ranges for filtering */ 7061 vmx->pt_desc.addr_range = intel_pt_validate_cap(vmx->pt_desc.caps, 7062 PT_CAP_num_address_ranges); 7063 7064 /* Initialize and clear the no dependency bits */ 7065 vmx->pt_desc.ctl_bitmask = ~(RTIT_CTL_TRACEEN | RTIT_CTL_OS | 7066 RTIT_CTL_USR | RTIT_CTL_TSC_EN | RTIT_CTL_DISRETC); 7067 7068 /* 7069 * If CPUID.(EAX=14H,ECX=0):EBX[0]=1 CR3Filter can be set otherwise 7070 * will inject an #GP 7071 */ 7072 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_cr3_filtering)) 7073 vmx->pt_desc.ctl_bitmask &= ~RTIT_CTL_CR3EN; 7074 7075 /* 7076 * If CPUID.(EAX=14H,ECX=0):EBX[1]=1 CYCEn, CycThresh and 7077 * PSBFreq can be set 7078 */ 7079 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_psb_cyc)) 7080 vmx->pt_desc.ctl_bitmask &= ~(RTIT_CTL_CYCLEACC | 7081 RTIT_CTL_CYC_THRESH | RTIT_CTL_PSB_FREQ); 7082 7083 /* 7084 * If CPUID.(EAX=14H,ECX=0):EBX[3]=1 MTCEn BranchEn and 7085 * MTCFreq can be set 7086 */ 7087 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_mtc)) 7088 vmx->pt_desc.ctl_bitmask &= ~(RTIT_CTL_MTC_EN | 7089 RTIT_CTL_BRANCH_EN | RTIT_CTL_MTC_RANGE); 7090 7091 /* If CPUID.(EAX=14H,ECX=0):EBX[4]=1 FUPonPTW and PTWEn can be set */ 7092 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_ptwrite)) 7093 vmx->pt_desc.ctl_bitmask &= ~(RTIT_CTL_FUP_ON_PTW | 7094 RTIT_CTL_PTW_EN); 7095 7096 /* If CPUID.(EAX=14H,ECX=0):EBX[5]=1 PwrEvEn can be set */ 7097 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_power_event_trace)) 7098 vmx->pt_desc.ctl_bitmask &= ~RTIT_CTL_PWR_EVT_EN; 7099 7100 /* If CPUID.(EAX=14H,ECX=0):ECX[0]=1 ToPA can be set */ 7101 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_topa_output)) 7102 vmx->pt_desc.ctl_bitmask &= ~RTIT_CTL_TOPA; 7103 7104 /* If CPUID.(EAX=14H,ECX=0):ECX[3]=1 FabircEn can be set */ 7105 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_output_subsys)) 7106 vmx->pt_desc.ctl_bitmask &= ~RTIT_CTL_FABRIC_EN; 7107 7108 /* unmask address range configure area */ 7109 for (i = 0; i < vmx->pt_desc.addr_range; i++) 7110 vmx->pt_desc.ctl_bitmask &= ~(0xfULL << (32 + i * 4)); 7111 } 7112 7113 static void vmx_cpuid_update(struct kvm_vcpu *vcpu) 7114 { 7115 struct vcpu_vmx *vmx = to_vmx(vcpu); 7116 7117 /* xsaves_enabled is recomputed in vmx_compute_secondary_exec_control(). */ 7118 vcpu->arch.xsaves_enabled = false; 7119 7120 if (cpu_has_secondary_exec_ctrls()) { 7121 vmx_compute_secondary_exec_control(vmx); 7122 vmcs_set_secondary_exec_control(vmx); 7123 } 7124 7125 if (nested_vmx_allowed(vcpu)) 7126 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits |= 7127 FEAT_CTL_VMX_ENABLED_INSIDE_SMX | 7128 FEAT_CTL_VMX_ENABLED_OUTSIDE_SMX; 7129 else 7130 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits &= 7131 ~(FEAT_CTL_VMX_ENABLED_INSIDE_SMX | 7132 FEAT_CTL_VMX_ENABLED_OUTSIDE_SMX); 7133 7134 if (nested_vmx_allowed(vcpu)) { 7135 nested_vmx_cr_fixed1_bits_update(vcpu); 7136 nested_vmx_entry_exit_ctls_update(vcpu); 7137 } 7138 7139 if (boot_cpu_has(X86_FEATURE_INTEL_PT) && 7140 guest_cpuid_has(vcpu, X86_FEATURE_INTEL_PT)) 7141 update_intel_pt_cfg(vcpu); 7142 7143 if (boot_cpu_has(X86_FEATURE_RTM)) { 7144 struct shared_msr_entry *msr; 7145 msr = find_msr_entry(vmx, MSR_IA32_TSX_CTRL); 7146 if (msr) { 7147 bool enabled = guest_cpuid_has(vcpu, X86_FEATURE_RTM); 7148 vmx_set_guest_msr(vmx, msr, enabled ? 0 : TSX_CTRL_RTM_DISABLE); 7149 } 7150 } 7151 } 7152 7153 static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry) 7154 { 7155 if (func == 1 && nested) 7156 entry->ecx |= feature_bit(VMX); 7157 } 7158 7159 static void vmx_request_immediate_exit(struct kvm_vcpu *vcpu) 7160 { 7161 to_vmx(vcpu)->req_immediate_exit = true; 7162 } 7163 7164 static int vmx_check_intercept_io(struct kvm_vcpu *vcpu, 7165 struct x86_instruction_info *info) 7166 { 7167 struct vmcs12 *vmcs12 = get_vmcs12(vcpu); 7168 unsigned short port; 7169 bool intercept; 7170 int size; 7171 7172 if (info->intercept == x86_intercept_in || 7173 info->intercept == x86_intercept_ins) { 7174 port = info->src_val; 7175 size = info->dst_bytes; 7176 } else { 7177 port = info->dst_val; 7178 size = info->src_bytes; 7179 } 7180 7181 /* 7182 * If the 'use IO bitmaps' VM-execution control is 0, IO instruction 7183 * VM-exits depend on the 'unconditional IO exiting' VM-execution 7184 * control. 7185 * 7186 * Otherwise, IO instruction VM-exits are controlled by the IO bitmaps. 7187 */ 7188 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS)) 7189 intercept = nested_cpu_has(vmcs12, 7190 CPU_BASED_UNCOND_IO_EXITING); 7191 else 7192 intercept = nested_vmx_check_io_bitmaps(vcpu, port, size); 7193 7194 /* FIXME: produce nested vmexit and return X86EMUL_INTERCEPTED. */ 7195 return intercept ? X86EMUL_UNHANDLEABLE : X86EMUL_CONTINUE; 7196 } 7197 7198 static int vmx_check_intercept(struct kvm_vcpu *vcpu, 7199 struct x86_instruction_info *info, 7200 enum x86_intercept_stage stage) 7201 { 7202 struct vmcs12 *vmcs12 = get_vmcs12(vcpu); 7203 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt; 7204 7205 switch (info->intercept) { 7206 /* 7207 * RDPID causes #UD if disabled through secondary execution controls. 7208 * Because it is marked as EmulateOnUD, we need to intercept it here. 7209 */ 7210 case x86_intercept_rdtscp: 7211 if (!nested_cpu_has2(vmcs12, SECONDARY_EXEC_RDTSCP)) { 7212 ctxt->exception.vector = UD_VECTOR; 7213 ctxt->exception.error_code_valid = false; 7214 return X86EMUL_PROPAGATE_FAULT; 7215 } 7216 break; 7217 7218 case x86_intercept_in: 7219 case x86_intercept_ins: 7220 case x86_intercept_out: 7221 case x86_intercept_outs: 7222 return vmx_check_intercept_io(vcpu, info); 7223 7224 case x86_intercept_lgdt: 7225 case x86_intercept_lidt: 7226 case x86_intercept_lldt: 7227 case x86_intercept_ltr: 7228 case x86_intercept_sgdt: 7229 case x86_intercept_sidt: 7230 case x86_intercept_sldt: 7231 case x86_intercept_str: 7232 if (!nested_cpu_has2(vmcs12, SECONDARY_EXEC_DESC)) 7233 return X86EMUL_CONTINUE; 7234 7235 /* FIXME: produce nested vmexit and return X86EMUL_INTERCEPTED. */ 7236 break; 7237 7238 /* TODO: check more intercepts... */ 7239 default: 7240 break; 7241 } 7242 7243 return X86EMUL_UNHANDLEABLE; 7244 } 7245 7246 #ifdef CONFIG_X86_64 7247 /* (a << shift) / divisor, return 1 if overflow otherwise 0 */ 7248 static inline int u64_shl_div_u64(u64 a, unsigned int shift, 7249 u64 divisor, u64 *result) 7250 { 7251 u64 low = a << shift, high = a >> (64 - shift); 7252 7253 /* To avoid the overflow on divq */ 7254 if (high >= divisor) 7255 return 1; 7256 7257 /* Low hold the result, high hold rem which is discarded */ 7258 asm("divq %2\n\t" : "=a" (low), "=d" (high) : 7259 "rm" (divisor), "0" (low), "1" (high)); 7260 *result = low; 7261 7262 return 0; 7263 } 7264 7265 static int vmx_set_hv_timer(struct kvm_vcpu *vcpu, u64 guest_deadline_tsc, 7266 bool *expired) 7267 { 7268 struct vcpu_vmx *vmx; 7269 u64 tscl, guest_tscl, delta_tsc, lapic_timer_advance_cycles; 7270 struct kvm_timer *ktimer = &vcpu->arch.apic->lapic_timer; 7271 7272 if (kvm_mwait_in_guest(vcpu->kvm) || 7273 kvm_can_post_timer_interrupt(vcpu)) 7274 return -EOPNOTSUPP; 7275 7276 vmx = to_vmx(vcpu); 7277 tscl = rdtsc(); 7278 guest_tscl = kvm_read_l1_tsc(vcpu, tscl); 7279 delta_tsc = max(guest_deadline_tsc, guest_tscl) - guest_tscl; 7280 lapic_timer_advance_cycles = nsec_to_cycles(vcpu, 7281 ktimer->timer_advance_ns); 7282 7283 if (delta_tsc > lapic_timer_advance_cycles) 7284 delta_tsc -= lapic_timer_advance_cycles; 7285 else 7286 delta_tsc = 0; 7287 7288 /* Convert to host delta tsc if tsc scaling is enabled */ 7289 if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio && 7290 delta_tsc && u64_shl_div_u64(delta_tsc, 7291 kvm_tsc_scaling_ratio_frac_bits, 7292 vcpu->arch.tsc_scaling_ratio, &delta_tsc)) 7293 return -ERANGE; 7294 7295 /* 7296 * If the delta tsc can't fit in the 32 bit after the multi shift, 7297 * we can't use the preemption timer. 7298 * It's possible that it fits on later vmentries, but checking 7299 * on every vmentry is costly so we just use an hrtimer. 7300 */ 7301 if (delta_tsc >> (cpu_preemption_timer_multi + 32)) 7302 return -ERANGE; 7303 7304 vmx->hv_deadline_tsc = tscl + delta_tsc; 7305 *expired = !delta_tsc; 7306 return 0; 7307 } 7308 7309 static void vmx_cancel_hv_timer(struct kvm_vcpu *vcpu) 7310 { 7311 to_vmx(vcpu)->hv_deadline_tsc = -1; 7312 } 7313 #endif 7314 7315 static void vmx_sched_in(struct kvm_vcpu *vcpu, int cpu) 7316 { 7317 if (!kvm_pause_in_guest(vcpu->kvm)) 7318 shrink_ple_window(vcpu); 7319 } 7320 7321 static void vmx_slot_enable_log_dirty(struct kvm *kvm, 7322 struct kvm_memory_slot *slot) 7323 { 7324 kvm_mmu_slot_leaf_clear_dirty(kvm, slot); 7325 kvm_mmu_slot_largepage_remove_write_access(kvm, slot); 7326 } 7327 7328 static void vmx_slot_disable_log_dirty(struct kvm *kvm, 7329 struct kvm_memory_slot *slot) 7330 { 7331 kvm_mmu_slot_set_dirty(kvm, slot); 7332 } 7333 7334 static void vmx_flush_log_dirty(struct kvm *kvm) 7335 { 7336 kvm_flush_pml_buffers(kvm); 7337 } 7338 7339 static int vmx_write_pml_buffer(struct kvm_vcpu *vcpu) 7340 { 7341 struct vmcs12 *vmcs12; 7342 struct vcpu_vmx *vmx = to_vmx(vcpu); 7343 gpa_t gpa, dst; 7344 7345 if (is_guest_mode(vcpu)) { 7346 WARN_ON_ONCE(vmx->nested.pml_full); 7347 7348 /* 7349 * Check if PML is enabled for the nested guest. 7350 * Whether eptp bit 6 is set is already checked 7351 * as part of A/D emulation. 7352 */ 7353 vmcs12 = get_vmcs12(vcpu); 7354 if (!nested_cpu_has_pml(vmcs12)) 7355 return 0; 7356 7357 if (vmcs12->guest_pml_index >= PML_ENTITY_NUM) { 7358 vmx->nested.pml_full = true; 7359 return 1; 7360 } 7361 7362 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS) & ~0xFFFull; 7363 dst = vmcs12->pml_address + sizeof(u64) * vmcs12->guest_pml_index; 7364 7365 if (kvm_write_guest_page(vcpu->kvm, gpa_to_gfn(dst), &gpa, 7366 offset_in_page(dst), sizeof(gpa))) 7367 return 0; 7368 7369 vmcs12->guest_pml_index--; 7370 } 7371 7372 return 0; 7373 } 7374 7375 static void vmx_enable_log_dirty_pt_masked(struct kvm *kvm, 7376 struct kvm_memory_slot *memslot, 7377 gfn_t offset, unsigned long mask) 7378 { 7379 kvm_mmu_clear_dirty_pt_masked(kvm, memslot, offset, mask); 7380 } 7381 7382 static void __pi_post_block(struct kvm_vcpu *vcpu) 7383 { 7384 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu); 7385 struct pi_desc old, new; 7386 unsigned int dest; 7387 7388 do { 7389 old.control = new.control = pi_desc->control; 7390 WARN(old.nv != POSTED_INTR_WAKEUP_VECTOR, 7391 "Wakeup handler not enabled while the VCPU is blocked\n"); 7392 7393 dest = cpu_physical_id(vcpu->cpu); 7394 7395 if (x2apic_enabled()) 7396 new.ndst = dest; 7397 else 7398 new.ndst = (dest << 8) & 0xFF00; 7399 7400 /* set 'NV' to 'notification vector' */ 7401 new.nv = POSTED_INTR_VECTOR; 7402 } while (cmpxchg64(&pi_desc->control, old.control, 7403 new.control) != old.control); 7404 7405 if (!WARN_ON_ONCE(vcpu->pre_pcpu == -1)) { 7406 spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu)); 7407 list_del(&vcpu->blocked_vcpu_list); 7408 spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu)); 7409 vcpu->pre_pcpu = -1; 7410 } 7411 } 7412 7413 /* 7414 * This routine does the following things for vCPU which is going 7415 * to be blocked if VT-d PI is enabled. 7416 * - Store the vCPU to the wakeup list, so when interrupts happen 7417 * we can find the right vCPU to wake up. 7418 * - Change the Posted-interrupt descriptor as below: 7419 * 'NDST' <-- vcpu->pre_pcpu 7420 * 'NV' <-- POSTED_INTR_WAKEUP_VECTOR 7421 * - If 'ON' is set during this process, which means at least one 7422 * interrupt is posted for this vCPU, we cannot block it, in 7423 * this case, return 1, otherwise, return 0. 7424 * 7425 */ 7426 static int pi_pre_block(struct kvm_vcpu *vcpu) 7427 { 7428 unsigned int dest; 7429 struct pi_desc old, new; 7430 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu); 7431 7432 if (!kvm_arch_has_assigned_device(vcpu->kvm) || 7433 !irq_remapping_cap(IRQ_POSTING_CAP) || 7434 !kvm_vcpu_apicv_active(vcpu)) 7435 return 0; 7436 7437 WARN_ON(irqs_disabled()); 7438 local_irq_disable(); 7439 if (!WARN_ON_ONCE(vcpu->pre_pcpu != -1)) { 7440 vcpu->pre_pcpu = vcpu->cpu; 7441 spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu)); 7442 list_add_tail(&vcpu->blocked_vcpu_list, 7443 &per_cpu(blocked_vcpu_on_cpu, 7444 vcpu->pre_pcpu)); 7445 spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu)); 7446 } 7447 7448 do { 7449 old.control = new.control = pi_desc->control; 7450 7451 WARN((pi_desc->sn == 1), 7452 "Warning: SN field of posted-interrupts " 7453 "is set before blocking\n"); 7454 7455 /* 7456 * Since vCPU can be preempted during this process, 7457 * vcpu->cpu could be different with pre_pcpu, we 7458 * need to set pre_pcpu as the destination of wakeup 7459 * notification event, then we can find the right vCPU 7460 * to wakeup in wakeup handler if interrupts happen 7461 * when the vCPU is in blocked state. 7462 */ 7463 dest = cpu_physical_id(vcpu->pre_pcpu); 7464 7465 if (x2apic_enabled()) 7466 new.ndst = dest; 7467 else 7468 new.ndst = (dest << 8) & 0xFF00; 7469 7470 /* set 'NV' to 'wakeup vector' */ 7471 new.nv = POSTED_INTR_WAKEUP_VECTOR; 7472 } while (cmpxchg64(&pi_desc->control, old.control, 7473 new.control) != old.control); 7474 7475 /* We should not block the vCPU if an interrupt is posted for it. */ 7476 if (pi_test_on(pi_desc) == 1) 7477 __pi_post_block(vcpu); 7478 7479 local_irq_enable(); 7480 return (vcpu->pre_pcpu == -1); 7481 } 7482 7483 static int vmx_pre_block(struct kvm_vcpu *vcpu) 7484 { 7485 if (pi_pre_block(vcpu)) 7486 return 1; 7487 7488 if (kvm_lapic_hv_timer_in_use(vcpu)) 7489 kvm_lapic_switch_to_sw_timer(vcpu); 7490 7491 return 0; 7492 } 7493 7494 static void pi_post_block(struct kvm_vcpu *vcpu) 7495 { 7496 if (vcpu->pre_pcpu == -1) 7497 return; 7498 7499 WARN_ON(irqs_disabled()); 7500 local_irq_disable(); 7501 __pi_post_block(vcpu); 7502 local_irq_enable(); 7503 } 7504 7505 static void vmx_post_block(struct kvm_vcpu *vcpu) 7506 { 7507 if (kvm_x86_ops->set_hv_timer) 7508 kvm_lapic_switch_to_hv_timer(vcpu); 7509 7510 pi_post_block(vcpu); 7511 } 7512 7513 /* 7514 * vmx_update_pi_irte - set IRTE for Posted-Interrupts 7515 * 7516 * @kvm: kvm 7517 * @host_irq: host irq of the interrupt 7518 * @guest_irq: gsi of the interrupt 7519 * @set: set or unset PI 7520 * returns 0 on success, < 0 on failure 7521 */ 7522 static int vmx_update_pi_irte(struct kvm *kvm, unsigned int host_irq, 7523 uint32_t guest_irq, bool set) 7524 { 7525 struct kvm_kernel_irq_routing_entry *e; 7526 struct kvm_irq_routing_table *irq_rt; 7527 struct kvm_lapic_irq irq; 7528 struct kvm_vcpu *vcpu; 7529 struct vcpu_data vcpu_info; 7530 int idx, ret = 0; 7531 7532 if (!kvm_arch_has_assigned_device(kvm) || 7533 !irq_remapping_cap(IRQ_POSTING_CAP) || 7534 !kvm_vcpu_apicv_active(kvm->vcpus[0])) 7535 return 0; 7536 7537 idx = srcu_read_lock(&kvm->irq_srcu); 7538 irq_rt = srcu_dereference(kvm->irq_routing, &kvm->irq_srcu); 7539 if (guest_irq >= irq_rt->nr_rt_entries || 7540 hlist_empty(&irq_rt->map[guest_irq])) { 7541 pr_warn_once("no route for guest_irq %u/%u (broken user space?)\n", 7542 guest_irq, irq_rt->nr_rt_entries); 7543 goto out; 7544 } 7545 7546 hlist_for_each_entry(e, &irq_rt->map[guest_irq], link) { 7547 if (e->type != KVM_IRQ_ROUTING_MSI) 7548 continue; 7549 /* 7550 * VT-d PI cannot support posting multicast/broadcast 7551 * interrupts to a vCPU, we still use interrupt remapping 7552 * for these kind of interrupts. 7553 * 7554 * For lowest-priority interrupts, we only support 7555 * those with single CPU as the destination, e.g. user 7556 * configures the interrupts via /proc/irq or uses 7557 * irqbalance to make the interrupts single-CPU. 7558 * 7559 * We will support full lowest-priority interrupt later. 7560 * 7561 * In addition, we can only inject generic interrupts using 7562 * the PI mechanism, refuse to route others through it. 7563 */ 7564 7565 kvm_set_msi_irq(kvm, e, &irq); 7566 if (!kvm_intr_is_single_vcpu(kvm, &irq, &vcpu) || 7567 !kvm_irq_is_postable(&irq)) { 7568 /* 7569 * Make sure the IRTE is in remapped mode if 7570 * we don't handle it in posted mode. 7571 */ 7572 ret = irq_set_vcpu_affinity(host_irq, NULL); 7573 if (ret < 0) { 7574 printk(KERN_INFO 7575 "failed to back to remapped mode, irq: %u\n", 7576 host_irq); 7577 goto out; 7578 } 7579 7580 continue; 7581 } 7582 7583 vcpu_info.pi_desc_addr = __pa(vcpu_to_pi_desc(vcpu)); 7584 vcpu_info.vector = irq.vector; 7585 7586 trace_kvm_pi_irte_update(host_irq, vcpu->vcpu_id, e->gsi, 7587 vcpu_info.vector, vcpu_info.pi_desc_addr, set); 7588 7589 if (set) 7590 ret = irq_set_vcpu_affinity(host_irq, &vcpu_info); 7591 else 7592 ret = irq_set_vcpu_affinity(host_irq, NULL); 7593 7594 if (ret < 0) { 7595 printk(KERN_INFO "%s: failed to update PI IRTE\n", 7596 __func__); 7597 goto out; 7598 } 7599 } 7600 7601 ret = 0; 7602 out: 7603 srcu_read_unlock(&kvm->irq_srcu, idx); 7604 return ret; 7605 } 7606 7607 static void vmx_setup_mce(struct kvm_vcpu *vcpu) 7608 { 7609 if (vcpu->arch.mcg_cap & MCG_LMCE_P) 7610 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits |= 7611 FEAT_CTL_LMCE_ENABLED; 7612 else 7613 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits &= 7614 ~FEAT_CTL_LMCE_ENABLED; 7615 } 7616 7617 static int vmx_smi_allowed(struct kvm_vcpu *vcpu) 7618 { 7619 /* we need a nested vmexit to enter SMM, postpone if run is pending */ 7620 if (to_vmx(vcpu)->nested.nested_run_pending) 7621 return 0; 7622 return 1; 7623 } 7624 7625 static int vmx_pre_enter_smm(struct kvm_vcpu *vcpu, char *smstate) 7626 { 7627 struct vcpu_vmx *vmx = to_vmx(vcpu); 7628 7629 vmx->nested.smm.guest_mode = is_guest_mode(vcpu); 7630 if (vmx->nested.smm.guest_mode) 7631 nested_vmx_vmexit(vcpu, -1, 0, 0); 7632 7633 vmx->nested.smm.vmxon = vmx->nested.vmxon; 7634 vmx->nested.vmxon = false; 7635 vmx_clear_hlt(vcpu); 7636 return 0; 7637 } 7638 7639 static int vmx_pre_leave_smm(struct kvm_vcpu *vcpu, const char *smstate) 7640 { 7641 struct vcpu_vmx *vmx = to_vmx(vcpu); 7642 int ret; 7643 7644 if (vmx->nested.smm.vmxon) { 7645 vmx->nested.vmxon = true; 7646 vmx->nested.smm.vmxon = false; 7647 } 7648 7649 if (vmx->nested.smm.guest_mode) { 7650 ret = nested_vmx_enter_non_root_mode(vcpu, false); 7651 if (ret) 7652 return ret; 7653 7654 vmx->nested.smm.guest_mode = false; 7655 } 7656 return 0; 7657 } 7658 7659 static int enable_smi_window(struct kvm_vcpu *vcpu) 7660 { 7661 return 0; 7662 } 7663 7664 static bool vmx_need_emulation_on_page_fault(struct kvm_vcpu *vcpu) 7665 { 7666 return false; 7667 } 7668 7669 static bool vmx_apic_init_signal_blocked(struct kvm_vcpu *vcpu) 7670 { 7671 return to_vmx(vcpu)->nested.vmxon; 7672 } 7673 7674 static __init int hardware_setup(void) 7675 { 7676 unsigned long host_bndcfgs; 7677 struct desc_ptr dt; 7678 int r, i; 7679 7680 rdmsrl_safe(MSR_EFER, &host_efer); 7681 7682 store_idt(&dt); 7683 host_idt_base = dt.address; 7684 7685 for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i) 7686 kvm_define_shared_msr(i, vmx_msr_index[i]); 7687 7688 if (setup_vmcs_config(&vmcs_config, &vmx_capability) < 0) 7689 return -EIO; 7690 7691 if (boot_cpu_has(X86_FEATURE_NX)) 7692 kvm_enable_efer_bits(EFER_NX); 7693 7694 if (boot_cpu_has(X86_FEATURE_MPX)) { 7695 rdmsrl(MSR_IA32_BNDCFGS, host_bndcfgs); 7696 WARN_ONCE(host_bndcfgs, "KVM: BNDCFGS in host will be lost"); 7697 } 7698 7699 if (!cpu_has_vmx_vpid() || !cpu_has_vmx_invvpid() || 7700 !(cpu_has_vmx_invvpid_single() || cpu_has_vmx_invvpid_global())) 7701 enable_vpid = 0; 7702 7703 if (!cpu_has_vmx_ept() || 7704 !cpu_has_vmx_ept_4levels() || 7705 !cpu_has_vmx_ept_mt_wb() || 7706 !cpu_has_vmx_invept_global()) 7707 enable_ept = 0; 7708 7709 if (!cpu_has_vmx_ept_ad_bits() || !enable_ept) 7710 enable_ept_ad_bits = 0; 7711 7712 if (!cpu_has_vmx_unrestricted_guest() || !enable_ept) 7713 enable_unrestricted_guest = 0; 7714 7715 if (!cpu_has_vmx_flexpriority()) 7716 flexpriority_enabled = 0; 7717 7718 if (!cpu_has_virtual_nmis()) 7719 enable_vnmi = 0; 7720 7721 /* 7722 * set_apic_access_page_addr() is used to reload apic access 7723 * page upon invalidation. No need to do anything if not 7724 * using the APIC_ACCESS_ADDR VMCS field. 7725 */ 7726 if (!flexpriority_enabled) 7727 kvm_x86_ops->set_apic_access_page_addr = NULL; 7728 7729 if (!cpu_has_vmx_tpr_shadow()) 7730 kvm_x86_ops->update_cr8_intercept = NULL; 7731 7732 if (enable_ept && !cpu_has_vmx_ept_2m_page()) 7733 kvm_disable_largepages(); 7734 7735 #if IS_ENABLED(CONFIG_HYPERV) 7736 if (ms_hyperv.nested_features & HV_X64_NESTED_GUEST_MAPPING_FLUSH 7737 && enable_ept) { 7738 kvm_x86_ops->tlb_remote_flush = hv_remote_flush_tlb; 7739 kvm_x86_ops->tlb_remote_flush_with_range = 7740 hv_remote_flush_tlb_with_range; 7741 } 7742 #endif 7743 7744 if (!cpu_has_vmx_ple()) { 7745 ple_gap = 0; 7746 ple_window = 0; 7747 ple_window_grow = 0; 7748 ple_window_max = 0; 7749 ple_window_shrink = 0; 7750 } 7751 7752 if (!cpu_has_vmx_apicv()) { 7753 enable_apicv = 0; 7754 kvm_x86_ops->sync_pir_to_irr = NULL; 7755 } 7756 7757 if (cpu_has_vmx_tsc_scaling()) { 7758 kvm_has_tsc_control = true; 7759 kvm_max_tsc_scaling_ratio = KVM_VMX_TSC_MULTIPLIER_MAX; 7760 kvm_tsc_scaling_ratio_frac_bits = 48; 7761 } 7762 7763 set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */ 7764 7765 if (enable_ept) 7766 vmx_enable_tdp(); 7767 else 7768 kvm_disable_tdp(); 7769 7770 /* 7771 * Only enable PML when hardware supports PML feature, and both EPT 7772 * and EPT A/D bit features are enabled -- PML depends on them to work. 7773 */ 7774 if (!enable_ept || !enable_ept_ad_bits || !cpu_has_vmx_pml()) 7775 enable_pml = 0; 7776 7777 if (!enable_pml) { 7778 kvm_x86_ops->slot_enable_log_dirty = NULL; 7779 kvm_x86_ops->slot_disable_log_dirty = NULL; 7780 kvm_x86_ops->flush_log_dirty = NULL; 7781 kvm_x86_ops->enable_log_dirty_pt_masked = NULL; 7782 } 7783 7784 if (!cpu_has_vmx_preemption_timer()) 7785 enable_preemption_timer = false; 7786 7787 if (enable_preemption_timer) { 7788 u64 use_timer_freq = 5000ULL * 1000 * 1000; 7789 u64 vmx_msr; 7790 7791 rdmsrl(MSR_IA32_VMX_MISC, vmx_msr); 7792 cpu_preemption_timer_multi = 7793 vmx_msr & VMX_MISC_PREEMPTION_TIMER_RATE_MASK; 7794 7795 if (tsc_khz) 7796 use_timer_freq = (u64)tsc_khz * 1000; 7797 use_timer_freq >>= cpu_preemption_timer_multi; 7798 7799 /* 7800 * KVM "disables" the preemption timer by setting it to its max 7801 * value. Don't use the timer if it might cause spurious exits 7802 * at a rate faster than 0.1 Hz (of uninterrupted guest time). 7803 */ 7804 if (use_timer_freq > 0xffffffffu / 10) 7805 enable_preemption_timer = false; 7806 } 7807 7808 if (!enable_preemption_timer) { 7809 kvm_x86_ops->set_hv_timer = NULL; 7810 kvm_x86_ops->cancel_hv_timer = NULL; 7811 kvm_x86_ops->request_immediate_exit = __kvm_request_immediate_exit; 7812 } 7813 7814 kvm_set_posted_intr_wakeup_handler(wakeup_handler); 7815 7816 kvm_mce_cap_supported |= MCG_LMCE_P; 7817 7818 if (pt_mode != PT_MODE_SYSTEM && pt_mode != PT_MODE_HOST_GUEST) 7819 return -EINVAL; 7820 if (!enable_ept || !cpu_has_vmx_intel_pt()) 7821 pt_mode = PT_MODE_SYSTEM; 7822 7823 if (nested) { 7824 nested_vmx_setup_ctls_msrs(&vmcs_config.nested, 7825 vmx_capability.ept); 7826 7827 r = nested_vmx_hardware_setup(kvm_vmx_exit_handlers); 7828 if (r) 7829 return r; 7830 } 7831 7832 r = alloc_kvm_area(); 7833 if (r) 7834 nested_vmx_hardware_unsetup(); 7835 return r; 7836 } 7837 7838 static __exit void hardware_unsetup(void) 7839 { 7840 if (nested) 7841 nested_vmx_hardware_unsetup(); 7842 7843 free_kvm_area(); 7844 } 7845 7846 static bool vmx_check_apicv_inhibit_reasons(ulong bit) 7847 { 7848 ulong supported = BIT(APICV_INHIBIT_REASON_DISABLE) | 7849 BIT(APICV_INHIBIT_REASON_HYPERV); 7850 7851 return supported & BIT(bit); 7852 } 7853 7854 static struct kvm_x86_ops vmx_x86_ops __ro_after_init = { 7855 .cpu_has_kvm_support = cpu_has_kvm_support, 7856 .disabled_by_bios = vmx_disabled_by_bios, 7857 .hardware_setup = hardware_setup, 7858 .hardware_unsetup = hardware_unsetup, 7859 .check_processor_compatibility = vmx_check_processor_compat, 7860 .hardware_enable = hardware_enable, 7861 .hardware_disable = hardware_disable, 7862 .cpu_has_accelerated_tpr = report_flexpriority, 7863 .has_emulated_msr = vmx_has_emulated_msr, 7864 7865 .vm_init = vmx_vm_init, 7866 .vm_alloc = vmx_vm_alloc, 7867 .vm_free = vmx_vm_free, 7868 7869 .vcpu_create = vmx_create_vcpu, 7870 .vcpu_free = vmx_free_vcpu, 7871 .vcpu_reset = vmx_vcpu_reset, 7872 7873 .prepare_guest_switch = vmx_prepare_switch_to_guest, 7874 .vcpu_load = vmx_vcpu_load, 7875 .vcpu_put = vmx_vcpu_put, 7876 7877 .update_bp_intercept = update_exception_bitmap, 7878 .get_msr_feature = vmx_get_msr_feature, 7879 .get_msr = vmx_get_msr, 7880 .set_msr = vmx_set_msr, 7881 .get_segment_base = vmx_get_segment_base, 7882 .get_segment = vmx_get_segment, 7883 .set_segment = vmx_set_segment, 7884 .get_cpl = vmx_get_cpl, 7885 .get_cs_db_l_bits = vmx_get_cs_db_l_bits, 7886 .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits, 7887 .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits, 7888 .set_cr0 = vmx_set_cr0, 7889 .set_cr3 = vmx_set_cr3, 7890 .set_cr4 = vmx_set_cr4, 7891 .set_efer = vmx_set_efer, 7892 .get_idt = vmx_get_idt, 7893 .set_idt = vmx_set_idt, 7894 .get_gdt = vmx_get_gdt, 7895 .set_gdt = vmx_set_gdt, 7896 .get_dr6 = vmx_get_dr6, 7897 .set_dr6 = vmx_set_dr6, 7898 .set_dr7 = vmx_set_dr7, 7899 .sync_dirty_debug_regs = vmx_sync_dirty_debug_regs, 7900 .cache_reg = vmx_cache_reg, 7901 .get_rflags = vmx_get_rflags, 7902 .set_rflags = vmx_set_rflags, 7903 7904 .tlb_flush = vmx_flush_tlb, 7905 .tlb_flush_gva = vmx_flush_tlb_gva, 7906 7907 .run = vmx_vcpu_run, 7908 .handle_exit = vmx_handle_exit, 7909 .skip_emulated_instruction = vmx_skip_emulated_instruction, 7910 .update_emulated_instruction = vmx_update_emulated_instruction, 7911 .set_interrupt_shadow = vmx_set_interrupt_shadow, 7912 .get_interrupt_shadow = vmx_get_interrupt_shadow, 7913 .patch_hypercall = vmx_patch_hypercall, 7914 .set_irq = vmx_inject_irq, 7915 .set_nmi = vmx_inject_nmi, 7916 .queue_exception = vmx_queue_exception, 7917 .cancel_injection = vmx_cancel_injection, 7918 .interrupt_allowed = vmx_interrupt_allowed, 7919 .nmi_allowed = vmx_nmi_allowed, 7920 .get_nmi_mask = vmx_get_nmi_mask, 7921 .set_nmi_mask = vmx_set_nmi_mask, 7922 .enable_nmi_window = enable_nmi_window, 7923 .enable_irq_window = enable_irq_window, 7924 .update_cr8_intercept = update_cr8_intercept, 7925 .set_virtual_apic_mode = vmx_set_virtual_apic_mode, 7926 .set_apic_access_page_addr = vmx_set_apic_access_page_addr, 7927 .refresh_apicv_exec_ctrl = vmx_refresh_apicv_exec_ctrl, 7928 .load_eoi_exitmap = vmx_load_eoi_exitmap, 7929 .apicv_post_state_restore = vmx_apicv_post_state_restore, 7930 .check_apicv_inhibit_reasons = vmx_check_apicv_inhibit_reasons, 7931 .hwapic_irr_update = vmx_hwapic_irr_update, 7932 .hwapic_isr_update = vmx_hwapic_isr_update, 7933 .guest_apic_has_interrupt = vmx_guest_apic_has_interrupt, 7934 .sync_pir_to_irr = vmx_sync_pir_to_irr, 7935 .deliver_posted_interrupt = vmx_deliver_posted_interrupt, 7936 .dy_apicv_has_pending_interrupt = vmx_dy_apicv_has_pending_interrupt, 7937 7938 .set_tss_addr = vmx_set_tss_addr, 7939 .set_identity_map_addr = vmx_set_identity_map_addr, 7940 .get_tdp_level = get_ept_level, 7941 .get_mt_mask = vmx_get_mt_mask, 7942 7943 .get_exit_info = vmx_get_exit_info, 7944 7945 .get_lpage_level = vmx_get_lpage_level, 7946 7947 .cpuid_update = vmx_cpuid_update, 7948 7949 .rdtscp_supported = vmx_rdtscp_supported, 7950 .invpcid_supported = vmx_invpcid_supported, 7951 7952 .set_supported_cpuid = vmx_set_supported_cpuid, 7953 7954 .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit, 7955 7956 .read_l1_tsc_offset = vmx_read_l1_tsc_offset, 7957 .write_l1_tsc_offset = vmx_write_l1_tsc_offset, 7958 7959 .set_tdp_cr3 = vmx_set_cr3, 7960 7961 .check_intercept = vmx_check_intercept, 7962 .handle_exit_irqoff = vmx_handle_exit_irqoff, 7963 .mpx_supported = vmx_mpx_supported, 7964 .xsaves_supported = vmx_xsaves_supported, 7965 .umip_emulated = vmx_umip_emulated, 7966 .pt_supported = vmx_pt_supported, 7967 .pku_supported = vmx_pku_supported, 7968 7969 .request_immediate_exit = vmx_request_immediate_exit, 7970 7971 .sched_in = vmx_sched_in, 7972 7973 .slot_enable_log_dirty = vmx_slot_enable_log_dirty, 7974 .slot_disable_log_dirty = vmx_slot_disable_log_dirty, 7975 .flush_log_dirty = vmx_flush_log_dirty, 7976 .enable_log_dirty_pt_masked = vmx_enable_log_dirty_pt_masked, 7977 .write_log_dirty = vmx_write_pml_buffer, 7978 7979 .pre_block = vmx_pre_block, 7980 .post_block = vmx_post_block, 7981 7982 .pmu_ops = &intel_pmu_ops, 7983 7984 .update_pi_irte = vmx_update_pi_irte, 7985 7986 #ifdef CONFIG_X86_64 7987 .set_hv_timer = vmx_set_hv_timer, 7988 .cancel_hv_timer = vmx_cancel_hv_timer, 7989 #endif 7990 7991 .setup_mce = vmx_setup_mce, 7992 7993 .smi_allowed = vmx_smi_allowed, 7994 .pre_enter_smm = vmx_pre_enter_smm, 7995 .pre_leave_smm = vmx_pre_leave_smm, 7996 .enable_smi_window = enable_smi_window, 7997 7998 .check_nested_events = NULL, 7999 .get_nested_state = NULL, 8000 .set_nested_state = NULL, 8001 .get_vmcs12_pages = NULL, 8002 .nested_enable_evmcs = NULL, 8003 .nested_get_evmcs_version = NULL, 8004 .need_emulation_on_page_fault = vmx_need_emulation_on_page_fault, 8005 .apic_init_signal_blocked = vmx_apic_init_signal_blocked, 8006 }; 8007 8008 static void vmx_cleanup_l1d_flush(void) 8009 { 8010 if (vmx_l1d_flush_pages) { 8011 free_pages((unsigned long)vmx_l1d_flush_pages, L1D_CACHE_ORDER); 8012 vmx_l1d_flush_pages = NULL; 8013 } 8014 /* Restore state so sysfs ignores VMX */ 8015 l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_AUTO; 8016 } 8017 8018 static void vmx_exit(void) 8019 { 8020 #ifdef CONFIG_KEXEC_CORE 8021 RCU_INIT_POINTER(crash_vmclear_loaded_vmcss, NULL); 8022 synchronize_rcu(); 8023 #endif 8024 8025 kvm_exit(); 8026 8027 #if IS_ENABLED(CONFIG_HYPERV) 8028 if (static_branch_unlikely(&enable_evmcs)) { 8029 int cpu; 8030 struct hv_vp_assist_page *vp_ap; 8031 /* 8032 * Reset everything to support using non-enlightened VMCS 8033 * access later (e.g. when we reload the module with 8034 * enlightened_vmcs=0) 8035 */ 8036 for_each_online_cpu(cpu) { 8037 vp_ap = hv_get_vp_assist_page(cpu); 8038 8039 if (!vp_ap) 8040 continue; 8041 8042 vp_ap->nested_control.features.directhypercall = 0; 8043 vp_ap->current_nested_vmcs = 0; 8044 vp_ap->enlighten_vmentry = 0; 8045 } 8046 8047 static_branch_disable(&enable_evmcs); 8048 } 8049 #endif 8050 vmx_cleanup_l1d_flush(); 8051 } 8052 module_exit(vmx_exit); 8053 8054 static int __init vmx_init(void) 8055 { 8056 int r; 8057 8058 #if IS_ENABLED(CONFIG_HYPERV) 8059 /* 8060 * Enlightened VMCS usage should be recommended and the host needs 8061 * to support eVMCS v1 or above. We can also disable eVMCS support 8062 * with module parameter. 8063 */ 8064 if (enlightened_vmcs && 8065 ms_hyperv.hints & HV_X64_ENLIGHTENED_VMCS_RECOMMENDED && 8066 (ms_hyperv.nested_features & HV_X64_ENLIGHTENED_VMCS_VERSION) >= 8067 KVM_EVMCS_VERSION) { 8068 int cpu; 8069 8070 /* Check that we have assist pages on all online CPUs */ 8071 for_each_online_cpu(cpu) { 8072 if (!hv_get_vp_assist_page(cpu)) { 8073 enlightened_vmcs = false; 8074 break; 8075 } 8076 } 8077 8078 if (enlightened_vmcs) { 8079 pr_info("KVM: vmx: using Hyper-V Enlightened VMCS\n"); 8080 static_branch_enable(&enable_evmcs); 8081 } 8082 8083 if (ms_hyperv.nested_features & HV_X64_NESTED_DIRECT_FLUSH) 8084 vmx_x86_ops.enable_direct_tlbflush 8085 = hv_enable_direct_tlbflush; 8086 8087 } else { 8088 enlightened_vmcs = false; 8089 } 8090 #endif 8091 8092 r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx), 8093 __alignof__(struct vcpu_vmx), THIS_MODULE); 8094 if (r) 8095 return r; 8096 8097 /* 8098 * Must be called after kvm_init() so enable_ept is properly set 8099 * up. Hand the parameter mitigation value in which was stored in 8100 * the pre module init parser. If no parameter was given, it will 8101 * contain 'auto' which will be turned into the default 'cond' 8102 * mitigation mode. 8103 */ 8104 r = vmx_setup_l1d_flush(vmentry_l1d_flush_param); 8105 if (r) { 8106 vmx_exit(); 8107 return r; 8108 } 8109 8110 #ifdef CONFIG_KEXEC_CORE 8111 rcu_assign_pointer(crash_vmclear_loaded_vmcss, 8112 crash_vmclear_local_loaded_vmcss); 8113 #endif 8114 vmx_check_vmcs12_offsets(); 8115 8116 return 0; 8117 } 8118 module_init(vmx_init); 8119