1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Kernel-based Virtual Machine driver for Linux 4 * 5 * This module enables machines with Intel VT-x extensions to run virtual 6 * machines without emulation or binary translation. 7 * 8 * Copyright (C) 2006 Qumranet, Inc. 9 * Copyright 2010 Red Hat, Inc. and/or its affiliates. 10 * 11 * Authors: 12 * Avi Kivity <avi@qumranet.com> 13 * Yaniv Kamay <yaniv@qumranet.com> 14 */ 15 16 #include <linux/frame.h> 17 #include <linux/highmem.h> 18 #include <linux/hrtimer.h> 19 #include <linux/kernel.h> 20 #include <linux/kvm_host.h> 21 #include <linux/module.h> 22 #include <linux/moduleparam.h> 23 #include <linux/mod_devicetable.h> 24 #include <linux/mm.h> 25 #include <linux/sched.h> 26 #include <linux/sched/smt.h> 27 #include <linux/slab.h> 28 #include <linux/tboot.h> 29 #include <linux/trace_events.h> 30 31 #include <asm/apic.h> 32 #include <asm/asm.h> 33 #include <asm/cpu.h> 34 #include <asm/cpu_device_id.h> 35 #include <asm/debugreg.h> 36 #include <asm/desc.h> 37 #include <asm/fpu/internal.h> 38 #include <asm/io.h> 39 #include <asm/irq_remapping.h> 40 #include <asm/kexec.h> 41 #include <asm/perf_event.h> 42 #include <asm/mce.h> 43 #include <asm/mmu_context.h> 44 #include <asm/mshyperv.h> 45 #include <asm/mwait.h> 46 #include <asm/spec-ctrl.h> 47 #include <asm/virtext.h> 48 #include <asm/vmx.h> 49 50 #include "capabilities.h" 51 #include "cpuid.h" 52 #include "evmcs.h" 53 #include "irq.h" 54 #include "kvm_cache_regs.h" 55 #include "lapic.h" 56 #include "mmu.h" 57 #include "nested.h" 58 #include "ops.h" 59 #include "pmu.h" 60 #include "trace.h" 61 #include "vmcs.h" 62 #include "vmcs12.h" 63 #include "vmx.h" 64 #include "x86.h" 65 66 MODULE_AUTHOR("Qumranet"); 67 MODULE_LICENSE("GPL"); 68 69 #ifdef MODULE 70 static const struct x86_cpu_id vmx_cpu_id[] = { 71 X86_MATCH_FEATURE(X86_FEATURE_VMX, NULL), 72 {} 73 }; 74 MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id); 75 #endif 76 77 bool __read_mostly enable_vpid = 1; 78 module_param_named(vpid, enable_vpid, bool, 0444); 79 80 static bool __read_mostly enable_vnmi = 1; 81 module_param_named(vnmi, enable_vnmi, bool, S_IRUGO); 82 83 bool __read_mostly flexpriority_enabled = 1; 84 module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO); 85 86 bool __read_mostly enable_ept = 1; 87 module_param_named(ept, enable_ept, bool, S_IRUGO); 88 89 bool __read_mostly enable_unrestricted_guest = 1; 90 module_param_named(unrestricted_guest, 91 enable_unrestricted_guest, bool, S_IRUGO); 92 93 bool __read_mostly enable_ept_ad_bits = 1; 94 module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO); 95 96 static bool __read_mostly emulate_invalid_guest_state = true; 97 module_param(emulate_invalid_guest_state, bool, S_IRUGO); 98 99 static bool __read_mostly fasteoi = 1; 100 module_param(fasteoi, bool, S_IRUGO); 101 102 bool __read_mostly enable_apicv = 1; 103 module_param(enable_apicv, bool, S_IRUGO); 104 105 /* 106 * If nested=1, nested virtualization is supported, i.e., guests may use 107 * VMX and be a hypervisor for its own guests. If nested=0, guests may not 108 * use VMX instructions. 109 */ 110 static bool __read_mostly nested = 1; 111 module_param(nested, bool, S_IRUGO); 112 113 bool __read_mostly enable_pml = 1; 114 module_param_named(pml, enable_pml, bool, S_IRUGO); 115 116 static bool __read_mostly dump_invalid_vmcs = 0; 117 module_param(dump_invalid_vmcs, bool, 0644); 118 119 #define MSR_BITMAP_MODE_X2APIC 1 120 #define MSR_BITMAP_MODE_X2APIC_APICV 2 121 122 #define KVM_VMX_TSC_MULTIPLIER_MAX 0xffffffffffffffffULL 123 124 /* Guest_tsc -> host_tsc conversion requires 64-bit division. */ 125 static int __read_mostly cpu_preemption_timer_multi; 126 static bool __read_mostly enable_preemption_timer = 1; 127 #ifdef CONFIG_X86_64 128 module_param_named(preemption_timer, enable_preemption_timer, bool, S_IRUGO); 129 #endif 130 131 #define KVM_VM_CR0_ALWAYS_OFF (X86_CR0_NW | X86_CR0_CD) 132 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST X86_CR0_NE 133 #define KVM_VM_CR0_ALWAYS_ON \ 134 (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | \ 135 X86_CR0_WP | X86_CR0_PG | X86_CR0_PE) 136 #define KVM_CR4_GUEST_OWNED_BITS \ 137 (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \ 138 | X86_CR4_OSXMMEXCPT | X86_CR4_LA57 | X86_CR4_TSD) 139 140 #define KVM_VM_CR4_ALWAYS_ON_UNRESTRICTED_GUEST X86_CR4_VMXE 141 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE) 142 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE) 143 144 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM)) 145 146 #define MSR_IA32_RTIT_STATUS_MASK (~(RTIT_STATUS_FILTEREN | \ 147 RTIT_STATUS_CONTEXTEN | RTIT_STATUS_TRIGGEREN | \ 148 RTIT_STATUS_ERROR | RTIT_STATUS_STOPPED | \ 149 RTIT_STATUS_BYTECNT)) 150 151 #define MSR_IA32_RTIT_OUTPUT_BASE_MASK \ 152 (~((1UL << cpuid_query_maxphyaddr(vcpu)) - 1) | 0x7f) 153 154 /* 155 * These 2 parameters are used to config the controls for Pause-Loop Exiting: 156 * ple_gap: upper bound on the amount of time between two successive 157 * executions of PAUSE in a loop. Also indicate if ple enabled. 158 * According to test, this time is usually smaller than 128 cycles. 159 * ple_window: upper bound on the amount of time a guest is allowed to execute 160 * in a PAUSE loop. Tests indicate that most spinlocks are held for 161 * less than 2^12 cycles 162 * Time is measured based on a counter that runs at the same rate as the TSC, 163 * refer SDM volume 3b section 21.6.13 & 22.1.3. 164 */ 165 static unsigned int ple_gap = KVM_DEFAULT_PLE_GAP; 166 module_param(ple_gap, uint, 0444); 167 168 static unsigned int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW; 169 module_param(ple_window, uint, 0444); 170 171 /* Default doubles per-vcpu window every exit. */ 172 static unsigned int ple_window_grow = KVM_DEFAULT_PLE_WINDOW_GROW; 173 module_param(ple_window_grow, uint, 0444); 174 175 /* Default resets per-vcpu window every exit to ple_window. */ 176 static unsigned int ple_window_shrink = KVM_DEFAULT_PLE_WINDOW_SHRINK; 177 module_param(ple_window_shrink, uint, 0444); 178 179 /* Default is to compute the maximum so we can never overflow. */ 180 static unsigned int ple_window_max = KVM_VMX_DEFAULT_PLE_WINDOW_MAX; 181 module_param(ple_window_max, uint, 0444); 182 183 /* Default is SYSTEM mode, 1 for host-guest mode */ 184 int __read_mostly pt_mode = PT_MODE_SYSTEM; 185 module_param(pt_mode, int, S_IRUGO); 186 187 static DEFINE_STATIC_KEY_FALSE(vmx_l1d_should_flush); 188 static DEFINE_STATIC_KEY_FALSE(vmx_l1d_flush_cond); 189 static DEFINE_MUTEX(vmx_l1d_flush_mutex); 190 191 /* Storage for pre module init parameter parsing */ 192 static enum vmx_l1d_flush_state __read_mostly vmentry_l1d_flush_param = VMENTER_L1D_FLUSH_AUTO; 193 194 static const struct { 195 const char *option; 196 bool for_parse; 197 } vmentry_l1d_param[] = { 198 [VMENTER_L1D_FLUSH_AUTO] = {"auto", true}, 199 [VMENTER_L1D_FLUSH_NEVER] = {"never", true}, 200 [VMENTER_L1D_FLUSH_COND] = {"cond", true}, 201 [VMENTER_L1D_FLUSH_ALWAYS] = {"always", true}, 202 [VMENTER_L1D_FLUSH_EPT_DISABLED] = {"EPT disabled", false}, 203 [VMENTER_L1D_FLUSH_NOT_REQUIRED] = {"not required", false}, 204 }; 205 206 #define L1D_CACHE_ORDER 4 207 static void *vmx_l1d_flush_pages; 208 209 static int vmx_setup_l1d_flush(enum vmx_l1d_flush_state l1tf) 210 { 211 struct page *page; 212 unsigned int i; 213 214 if (!boot_cpu_has_bug(X86_BUG_L1TF)) { 215 l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_NOT_REQUIRED; 216 return 0; 217 } 218 219 if (!enable_ept) { 220 l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_EPT_DISABLED; 221 return 0; 222 } 223 224 if (boot_cpu_has(X86_FEATURE_ARCH_CAPABILITIES)) { 225 u64 msr; 226 227 rdmsrl(MSR_IA32_ARCH_CAPABILITIES, msr); 228 if (msr & ARCH_CAP_SKIP_VMENTRY_L1DFLUSH) { 229 l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_NOT_REQUIRED; 230 return 0; 231 } 232 } 233 234 /* If set to auto use the default l1tf mitigation method */ 235 if (l1tf == VMENTER_L1D_FLUSH_AUTO) { 236 switch (l1tf_mitigation) { 237 case L1TF_MITIGATION_OFF: 238 l1tf = VMENTER_L1D_FLUSH_NEVER; 239 break; 240 case L1TF_MITIGATION_FLUSH_NOWARN: 241 case L1TF_MITIGATION_FLUSH: 242 case L1TF_MITIGATION_FLUSH_NOSMT: 243 l1tf = VMENTER_L1D_FLUSH_COND; 244 break; 245 case L1TF_MITIGATION_FULL: 246 case L1TF_MITIGATION_FULL_FORCE: 247 l1tf = VMENTER_L1D_FLUSH_ALWAYS; 248 break; 249 } 250 } else if (l1tf_mitigation == L1TF_MITIGATION_FULL_FORCE) { 251 l1tf = VMENTER_L1D_FLUSH_ALWAYS; 252 } 253 254 if (l1tf != VMENTER_L1D_FLUSH_NEVER && !vmx_l1d_flush_pages && 255 !boot_cpu_has(X86_FEATURE_FLUSH_L1D)) { 256 /* 257 * This allocation for vmx_l1d_flush_pages is not tied to a VM 258 * lifetime and so should not be charged to a memcg. 259 */ 260 page = alloc_pages(GFP_KERNEL, L1D_CACHE_ORDER); 261 if (!page) 262 return -ENOMEM; 263 vmx_l1d_flush_pages = page_address(page); 264 265 /* 266 * Initialize each page with a different pattern in 267 * order to protect against KSM in the nested 268 * virtualization case. 269 */ 270 for (i = 0; i < 1u << L1D_CACHE_ORDER; ++i) { 271 memset(vmx_l1d_flush_pages + i * PAGE_SIZE, i + 1, 272 PAGE_SIZE); 273 } 274 } 275 276 l1tf_vmx_mitigation = l1tf; 277 278 if (l1tf != VMENTER_L1D_FLUSH_NEVER) 279 static_branch_enable(&vmx_l1d_should_flush); 280 else 281 static_branch_disable(&vmx_l1d_should_flush); 282 283 if (l1tf == VMENTER_L1D_FLUSH_COND) 284 static_branch_enable(&vmx_l1d_flush_cond); 285 else 286 static_branch_disable(&vmx_l1d_flush_cond); 287 return 0; 288 } 289 290 static int vmentry_l1d_flush_parse(const char *s) 291 { 292 unsigned int i; 293 294 if (s) { 295 for (i = 0; i < ARRAY_SIZE(vmentry_l1d_param); i++) { 296 if (vmentry_l1d_param[i].for_parse && 297 sysfs_streq(s, vmentry_l1d_param[i].option)) 298 return i; 299 } 300 } 301 return -EINVAL; 302 } 303 304 static int vmentry_l1d_flush_set(const char *s, const struct kernel_param *kp) 305 { 306 int l1tf, ret; 307 308 l1tf = vmentry_l1d_flush_parse(s); 309 if (l1tf < 0) 310 return l1tf; 311 312 if (!boot_cpu_has(X86_BUG_L1TF)) 313 return 0; 314 315 /* 316 * Has vmx_init() run already? If not then this is the pre init 317 * parameter parsing. In that case just store the value and let 318 * vmx_init() do the proper setup after enable_ept has been 319 * established. 320 */ 321 if (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_AUTO) { 322 vmentry_l1d_flush_param = l1tf; 323 return 0; 324 } 325 326 mutex_lock(&vmx_l1d_flush_mutex); 327 ret = vmx_setup_l1d_flush(l1tf); 328 mutex_unlock(&vmx_l1d_flush_mutex); 329 return ret; 330 } 331 332 static int vmentry_l1d_flush_get(char *s, const struct kernel_param *kp) 333 { 334 if (WARN_ON_ONCE(l1tf_vmx_mitigation >= ARRAY_SIZE(vmentry_l1d_param))) 335 return sprintf(s, "???\n"); 336 337 return sprintf(s, "%s\n", vmentry_l1d_param[l1tf_vmx_mitigation].option); 338 } 339 340 static const struct kernel_param_ops vmentry_l1d_flush_ops = { 341 .set = vmentry_l1d_flush_set, 342 .get = vmentry_l1d_flush_get, 343 }; 344 module_param_cb(vmentry_l1d_flush, &vmentry_l1d_flush_ops, NULL, 0644); 345 346 static bool guest_state_valid(struct kvm_vcpu *vcpu); 347 static u32 vmx_segment_access_rights(struct kvm_segment *var); 348 static __always_inline void vmx_disable_intercept_for_msr(unsigned long *msr_bitmap, 349 u32 msr, int type); 350 351 void vmx_vmexit(void); 352 353 #define vmx_insn_failed(fmt...) \ 354 do { \ 355 WARN_ONCE(1, fmt); \ 356 pr_warn_ratelimited(fmt); \ 357 } while (0) 358 359 asmlinkage void vmread_error(unsigned long field, bool fault) 360 { 361 if (fault) 362 kvm_spurious_fault(); 363 else 364 vmx_insn_failed("kvm: vmread failed: field=%lx\n", field); 365 } 366 367 noinline void vmwrite_error(unsigned long field, unsigned long value) 368 { 369 vmx_insn_failed("kvm: vmwrite failed: field=%lx val=%lx err=%d\n", 370 field, value, vmcs_read32(VM_INSTRUCTION_ERROR)); 371 } 372 373 noinline void vmclear_error(struct vmcs *vmcs, u64 phys_addr) 374 { 375 vmx_insn_failed("kvm: vmclear failed: %p/%llx\n", vmcs, phys_addr); 376 } 377 378 noinline void vmptrld_error(struct vmcs *vmcs, u64 phys_addr) 379 { 380 vmx_insn_failed("kvm: vmptrld failed: %p/%llx\n", vmcs, phys_addr); 381 } 382 383 noinline void invvpid_error(unsigned long ext, u16 vpid, gva_t gva) 384 { 385 vmx_insn_failed("kvm: invvpid failed: ext=0x%lx vpid=%u gva=0x%lx\n", 386 ext, vpid, gva); 387 } 388 389 noinline void invept_error(unsigned long ext, u64 eptp, gpa_t gpa) 390 { 391 vmx_insn_failed("kvm: invept failed: ext=0x%lx eptp=%llx gpa=0x%llx\n", 392 ext, eptp, gpa); 393 } 394 395 static DEFINE_PER_CPU(struct vmcs *, vmxarea); 396 DEFINE_PER_CPU(struct vmcs *, current_vmcs); 397 /* 398 * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed 399 * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it. 400 */ 401 static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu); 402 403 /* 404 * We maintian a per-CPU linked-list of vCPU, so in wakeup_handler() we 405 * can find which vCPU should be waken up. 406 */ 407 static DEFINE_PER_CPU(struct list_head, blocked_vcpu_on_cpu); 408 static DEFINE_PER_CPU(spinlock_t, blocked_vcpu_on_cpu_lock); 409 410 static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS); 411 static DEFINE_SPINLOCK(vmx_vpid_lock); 412 413 struct vmcs_config vmcs_config; 414 struct vmx_capability vmx_capability; 415 416 #define VMX_SEGMENT_FIELD(seg) \ 417 [VCPU_SREG_##seg] = { \ 418 .selector = GUEST_##seg##_SELECTOR, \ 419 .base = GUEST_##seg##_BASE, \ 420 .limit = GUEST_##seg##_LIMIT, \ 421 .ar_bytes = GUEST_##seg##_AR_BYTES, \ 422 } 423 424 static const struct kvm_vmx_segment_field { 425 unsigned selector; 426 unsigned base; 427 unsigned limit; 428 unsigned ar_bytes; 429 } kvm_vmx_segment_fields[] = { 430 VMX_SEGMENT_FIELD(CS), 431 VMX_SEGMENT_FIELD(DS), 432 VMX_SEGMENT_FIELD(ES), 433 VMX_SEGMENT_FIELD(FS), 434 VMX_SEGMENT_FIELD(GS), 435 VMX_SEGMENT_FIELD(SS), 436 VMX_SEGMENT_FIELD(TR), 437 VMX_SEGMENT_FIELD(LDTR), 438 }; 439 440 static unsigned long host_idt_base; 441 442 /* 443 * Though SYSCALL is only supported in 64-bit mode on Intel CPUs, kvm 444 * will emulate SYSCALL in legacy mode if the vendor string in guest 445 * CPUID.0:{EBX,ECX,EDX} is "AuthenticAMD" or "AMDisbetter!" To 446 * support this emulation, IA32_STAR must always be included in 447 * vmx_msr_index[], even in i386 builds. 448 */ 449 const u32 vmx_msr_index[] = { 450 #ifdef CONFIG_X86_64 451 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR, 452 #endif 453 MSR_EFER, MSR_TSC_AUX, MSR_STAR, 454 MSR_IA32_TSX_CTRL, 455 }; 456 457 #if IS_ENABLED(CONFIG_HYPERV) 458 static bool __read_mostly enlightened_vmcs = true; 459 module_param(enlightened_vmcs, bool, 0444); 460 461 /* check_ept_pointer() should be under protection of ept_pointer_lock. */ 462 static void check_ept_pointer_match(struct kvm *kvm) 463 { 464 struct kvm_vcpu *vcpu; 465 u64 tmp_eptp = INVALID_PAGE; 466 int i; 467 468 kvm_for_each_vcpu(i, vcpu, kvm) { 469 if (!VALID_PAGE(tmp_eptp)) { 470 tmp_eptp = to_vmx(vcpu)->ept_pointer; 471 } else if (tmp_eptp != to_vmx(vcpu)->ept_pointer) { 472 to_kvm_vmx(kvm)->ept_pointers_match 473 = EPT_POINTERS_MISMATCH; 474 return; 475 } 476 } 477 478 to_kvm_vmx(kvm)->ept_pointers_match = EPT_POINTERS_MATCH; 479 } 480 481 static int kvm_fill_hv_flush_list_func(struct hv_guest_mapping_flush_list *flush, 482 void *data) 483 { 484 struct kvm_tlb_range *range = data; 485 486 return hyperv_fill_flush_guest_mapping_list(flush, range->start_gfn, 487 range->pages); 488 } 489 490 static inline int __hv_remote_flush_tlb_with_range(struct kvm *kvm, 491 struct kvm_vcpu *vcpu, struct kvm_tlb_range *range) 492 { 493 u64 ept_pointer = to_vmx(vcpu)->ept_pointer; 494 495 /* 496 * FLUSH_GUEST_PHYSICAL_ADDRESS_SPACE hypercall needs address 497 * of the base of EPT PML4 table, strip off EPT configuration 498 * information. 499 */ 500 if (range) 501 return hyperv_flush_guest_mapping_range(ept_pointer & PAGE_MASK, 502 kvm_fill_hv_flush_list_func, (void *)range); 503 else 504 return hyperv_flush_guest_mapping(ept_pointer & PAGE_MASK); 505 } 506 507 static int hv_remote_flush_tlb_with_range(struct kvm *kvm, 508 struct kvm_tlb_range *range) 509 { 510 struct kvm_vcpu *vcpu; 511 int ret = 0, i; 512 513 spin_lock(&to_kvm_vmx(kvm)->ept_pointer_lock); 514 515 if (to_kvm_vmx(kvm)->ept_pointers_match == EPT_POINTERS_CHECK) 516 check_ept_pointer_match(kvm); 517 518 if (to_kvm_vmx(kvm)->ept_pointers_match != EPT_POINTERS_MATCH) { 519 kvm_for_each_vcpu(i, vcpu, kvm) { 520 /* If ept_pointer is invalid pointer, bypass flush request. */ 521 if (VALID_PAGE(to_vmx(vcpu)->ept_pointer)) 522 ret |= __hv_remote_flush_tlb_with_range( 523 kvm, vcpu, range); 524 } 525 } else { 526 ret = __hv_remote_flush_tlb_with_range(kvm, 527 kvm_get_vcpu(kvm, 0), range); 528 } 529 530 spin_unlock(&to_kvm_vmx(kvm)->ept_pointer_lock); 531 return ret; 532 } 533 static int hv_remote_flush_tlb(struct kvm *kvm) 534 { 535 return hv_remote_flush_tlb_with_range(kvm, NULL); 536 } 537 538 static int hv_enable_direct_tlbflush(struct kvm_vcpu *vcpu) 539 { 540 struct hv_enlightened_vmcs *evmcs; 541 struct hv_partition_assist_pg **p_hv_pa_pg = 542 &vcpu->kvm->arch.hyperv.hv_pa_pg; 543 /* 544 * Synthetic VM-Exit is not enabled in current code and so All 545 * evmcs in singe VM shares same assist page. 546 */ 547 if (!*p_hv_pa_pg) 548 *p_hv_pa_pg = kzalloc(PAGE_SIZE, GFP_KERNEL); 549 550 if (!*p_hv_pa_pg) 551 return -ENOMEM; 552 553 evmcs = (struct hv_enlightened_vmcs *)to_vmx(vcpu)->loaded_vmcs->vmcs; 554 555 evmcs->partition_assist_page = 556 __pa(*p_hv_pa_pg); 557 evmcs->hv_vm_id = (unsigned long)vcpu->kvm; 558 evmcs->hv_enlightenments_control.nested_flush_hypercall = 1; 559 560 return 0; 561 } 562 563 #endif /* IS_ENABLED(CONFIG_HYPERV) */ 564 565 /* 566 * Comment's format: document - errata name - stepping - processor name. 567 * Refer from 568 * https://www.virtualbox.org/svn/vbox/trunk/src/VBox/VMM/VMMR0/HMR0.cpp 569 */ 570 static u32 vmx_preemption_cpu_tfms[] = { 571 /* 323344.pdf - BA86 - D0 - Xeon 7500 Series */ 572 0x000206E6, 573 /* 323056.pdf - AAX65 - C2 - Xeon L3406 */ 574 /* 322814.pdf - AAT59 - C2 - i7-600, i5-500, i5-400 and i3-300 Mobile */ 575 /* 322911.pdf - AAU65 - C2 - i5-600, i3-500 Desktop and Pentium G6950 */ 576 0x00020652, 577 /* 322911.pdf - AAU65 - K0 - i5-600, i3-500 Desktop and Pentium G6950 */ 578 0x00020655, 579 /* 322373.pdf - AAO95 - B1 - Xeon 3400 Series */ 580 /* 322166.pdf - AAN92 - B1 - i7-800 and i5-700 Desktop */ 581 /* 582 * 320767.pdf - AAP86 - B1 - 583 * i7-900 Mobile Extreme, i7-800 and i7-700 Mobile 584 */ 585 0x000106E5, 586 /* 321333.pdf - AAM126 - C0 - Xeon 3500 */ 587 0x000106A0, 588 /* 321333.pdf - AAM126 - C1 - Xeon 3500 */ 589 0x000106A1, 590 /* 320836.pdf - AAJ124 - C0 - i7-900 Desktop Extreme and i7-900 Desktop */ 591 0x000106A4, 592 /* 321333.pdf - AAM126 - D0 - Xeon 3500 */ 593 /* 321324.pdf - AAK139 - D0 - Xeon 5500 */ 594 /* 320836.pdf - AAJ124 - D0 - i7-900 Extreme and i7-900 Desktop */ 595 0x000106A5, 596 /* Xeon E3-1220 V2 */ 597 0x000306A8, 598 }; 599 600 static inline bool cpu_has_broken_vmx_preemption_timer(void) 601 { 602 u32 eax = cpuid_eax(0x00000001), i; 603 604 /* Clear the reserved bits */ 605 eax &= ~(0x3U << 14 | 0xfU << 28); 606 for (i = 0; i < ARRAY_SIZE(vmx_preemption_cpu_tfms); i++) 607 if (eax == vmx_preemption_cpu_tfms[i]) 608 return true; 609 610 return false; 611 } 612 613 static inline bool cpu_need_virtualize_apic_accesses(struct kvm_vcpu *vcpu) 614 { 615 return flexpriority_enabled && lapic_in_kernel(vcpu); 616 } 617 618 static inline bool report_flexpriority(void) 619 { 620 return flexpriority_enabled; 621 } 622 623 static inline int __find_msr_index(struct vcpu_vmx *vmx, u32 msr) 624 { 625 int i; 626 627 for (i = 0; i < vmx->nmsrs; ++i) 628 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr) 629 return i; 630 return -1; 631 } 632 633 struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr) 634 { 635 int i; 636 637 i = __find_msr_index(vmx, msr); 638 if (i >= 0) 639 return &vmx->guest_msrs[i]; 640 return NULL; 641 } 642 643 static int vmx_set_guest_msr(struct vcpu_vmx *vmx, struct shared_msr_entry *msr, u64 data) 644 { 645 int ret = 0; 646 647 u64 old_msr_data = msr->data; 648 msr->data = data; 649 if (msr - vmx->guest_msrs < vmx->save_nmsrs) { 650 preempt_disable(); 651 ret = kvm_set_shared_msr(msr->index, msr->data, 652 msr->mask); 653 preempt_enable(); 654 if (ret) 655 msr->data = old_msr_data; 656 } 657 return ret; 658 } 659 660 #ifdef CONFIG_KEXEC_CORE 661 static void crash_vmclear_local_loaded_vmcss(void) 662 { 663 int cpu = raw_smp_processor_id(); 664 struct loaded_vmcs *v; 665 666 list_for_each_entry(v, &per_cpu(loaded_vmcss_on_cpu, cpu), 667 loaded_vmcss_on_cpu_link) 668 vmcs_clear(v->vmcs); 669 } 670 #endif /* CONFIG_KEXEC_CORE */ 671 672 static void __loaded_vmcs_clear(void *arg) 673 { 674 struct loaded_vmcs *loaded_vmcs = arg; 675 int cpu = raw_smp_processor_id(); 676 677 if (loaded_vmcs->cpu != cpu) 678 return; /* vcpu migration can race with cpu offline */ 679 if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs) 680 per_cpu(current_vmcs, cpu) = NULL; 681 682 vmcs_clear(loaded_vmcs->vmcs); 683 if (loaded_vmcs->shadow_vmcs && loaded_vmcs->launched) 684 vmcs_clear(loaded_vmcs->shadow_vmcs); 685 686 list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link); 687 688 /* 689 * Ensure all writes to loaded_vmcs, including deleting it from its 690 * current percpu list, complete before setting loaded_vmcs->vcpu to 691 * -1, otherwise a different cpu can see vcpu == -1 first and add 692 * loaded_vmcs to its percpu list before it's deleted from this cpu's 693 * list. Pairs with the smp_rmb() in vmx_vcpu_load_vmcs(). 694 */ 695 smp_wmb(); 696 697 loaded_vmcs->cpu = -1; 698 loaded_vmcs->launched = 0; 699 } 700 701 void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs) 702 { 703 int cpu = loaded_vmcs->cpu; 704 705 if (cpu != -1) 706 smp_call_function_single(cpu, 707 __loaded_vmcs_clear, loaded_vmcs, 1); 708 } 709 710 static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg, 711 unsigned field) 712 { 713 bool ret; 714 u32 mask = 1 << (seg * SEG_FIELD_NR + field); 715 716 if (!kvm_register_is_available(&vmx->vcpu, VCPU_EXREG_SEGMENTS)) { 717 kvm_register_mark_available(&vmx->vcpu, VCPU_EXREG_SEGMENTS); 718 vmx->segment_cache.bitmask = 0; 719 } 720 ret = vmx->segment_cache.bitmask & mask; 721 vmx->segment_cache.bitmask |= mask; 722 return ret; 723 } 724 725 static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg) 726 { 727 u16 *p = &vmx->segment_cache.seg[seg].selector; 728 729 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL)) 730 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector); 731 return *p; 732 } 733 734 static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg) 735 { 736 ulong *p = &vmx->segment_cache.seg[seg].base; 737 738 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE)) 739 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base); 740 return *p; 741 } 742 743 static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg) 744 { 745 u32 *p = &vmx->segment_cache.seg[seg].limit; 746 747 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT)) 748 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit); 749 return *p; 750 } 751 752 static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg) 753 { 754 u32 *p = &vmx->segment_cache.seg[seg].ar; 755 756 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR)) 757 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes); 758 return *p; 759 } 760 761 void update_exception_bitmap(struct kvm_vcpu *vcpu) 762 { 763 u32 eb; 764 765 eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) | 766 (1u << DB_VECTOR) | (1u << AC_VECTOR); 767 /* 768 * Guest access to VMware backdoor ports could legitimately 769 * trigger #GP because of TSS I/O permission bitmap. 770 * We intercept those #GP and allow access to them anyway 771 * as VMware does. 772 */ 773 if (enable_vmware_backdoor) 774 eb |= (1u << GP_VECTOR); 775 if ((vcpu->guest_debug & 776 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) == 777 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) 778 eb |= 1u << BP_VECTOR; 779 if (to_vmx(vcpu)->rmode.vm86_active) 780 eb = ~0; 781 if (enable_ept) 782 eb &= ~(1u << PF_VECTOR); 783 784 /* When we are running a nested L2 guest and L1 specified for it a 785 * certain exception bitmap, we must trap the same exceptions and pass 786 * them to L1. When running L2, we will only handle the exceptions 787 * specified above if L1 did not want them. 788 */ 789 if (is_guest_mode(vcpu)) 790 eb |= get_vmcs12(vcpu)->exception_bitmap; 791 792 vmcs_write32(EXCEPTION_BITMAP, eb); 793 } 794 795 /* 796 * Check if MSR is intercepted for currently loaded MSR bitmap. 797 */ 798 static bool msr_write_intercepted(struct kvm_vcpu *vcpu, u32 msr) 799 { 800 unsigned long *msr_bitmap; 801 int f = sizeof(unsigned long); 802 803 if (!cpu_has_vmx_msr_bitmap()) 804 return true; 805 806 msr_bitmap = to_vmx(vcpu)->loaded_vmcs->msr_bitmap; 807 808 if (msr <= 0x1fff) { 809 return !!test_bit(msr, msr_bitmap + 0x800 / f); 810 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) { 811 msr &= 0x1fff; 812 return !!test_bit(msr, msr_bitmap + 0xc00 / f); 813 } 814 815 return true; 816 } 817 818 static void clear_atomic_switch_msr_special(struct vcpu_vmx *vmx, 819 unsigned long entry, unsigned long exit) 820 { 821 vm_entry_controls_clearbit(vmx, entry); 822 vm_exit_controls_clearbit(vmx, exit); 823 } 824 825 int vmx_find_msr_index(struct vmx_msrs *m, u32 msr) 826 { 827 unsigned int i; 828 829 for (i = 0; i < m->nr; ++i) { 830 if (m->val[i].index == msr) 831 return i; 832 } 833 return -ENOENT; 834 } 835 836 static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr) 837 { 838 int i; 839 struct msr_autoload *m = &vmx->msr_autoload; 840 841 switch (msr) { 842 case MSR_EFER: 843 if (cpu_has_load_ia32_efer()) { 844 clear_atomic_switch_msr_special(vmx, 845 VM_ENTRY_LOAD_IA32_EFER, 846 VM_EXIT_LOAD_IA32_EFER); 847 return; 848 } 849 break; 850 case MSR_CORE_PERF_GLOBAL_CTRL: 851 if (cpu_has_load_perf_global_ctrl()) { 852 clear_atomic_switch_msr_special(vmx, 853 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL, 854 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL); 855 return; 856 } 857 break; 858 } 859 i = vmx_find_msr_index(&m->guest, msr); 860 if (i < 0) 861 goto skip_guest; 862 --m->guest.nr; 863 m->guest.val[i] = m->guest.val[m->guest.nr]; 864 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->guest.nr); 865 866 skip_guest: 867 i = vmx_find_msr_index(&m->host, msr); 868 if (i < 0) 869 return; 870 871 --m->host.nr; 872 m->host.val[i] = m->host.val[m->host.nr]; 873 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->host.nr); 874 } 875 876 static void add_atomic_switch_msr_special(struct vcpu_vmx *vmx, 877 unsigned long entry, unsigned long exit, 878 unsigned long guest_val_vmcs, unsigned long host_val_vmcs, 879 u64 guest_val, u64 host_val) 880 { 881 vmcs_write64(guest_val_vmcs, guest_val); 882 if (host_val_vmcs != HOST_IA32_EFER) 883 vmcs_write64(host_val_vmcs, host_val); 884 vm_entry_controls_setbit(vmx, entry); 885 vm_exit_controls_setbit(vmx, exit); 886 } 887 888 static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr, 889 u64 guest_val, u64 host_val, bool entry_only) 890 { 891 int i, j = 0; 892 struct msr_autoload *m = &vmx->msr_autoload; 893 894 switch (msr) { 895 case MSR_EFER: 896 if (cpu_has_load_ia32_efer()) { 897 add_atomic_switch_msr_special(vmx, 898 VM_ENTRY_LOAD_IA32_EFER, 899 VM_EXIT_LOAD_IA32_EFER, 900 GUEST_IA32_EFER, 901 HOST_IA32_EFER, 902 guest_val, host_val); 903 return; 904 } 905 break; 906 case MSR_CORE_PERF_GLOBAL_CTRL: 907 if (cpu_has_load_perf_global_ctrl()) { 908 add_atomic_switch_msr_special(vmx, 909 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL, 910 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL, 911 GUEST_IA32_PERF_GLOBAL_CTRL, 912 HOST_IA32_PERF_GLOBAL_CTRL, 913 guest_val, host_val); 914 return; 915 } 916 break; 917 case MSR_IA32_PEBS_ENABLE: 918 /* PEBS needs a quiescent period after being disabled (to write 919 * a record). Disabling PEBS through VMX MSR swapping doesn't 920 * provide that period, so a CPU could write host's record into 921 * guest's memory. 922 */ 923 wrmsrl(MSR_IA32_PEBS_ENABLE, 0); 924 } 925 926 i = vmx_find_msr_index(&m->guest, msr); 927 if (!entry_only) 928 j = vmx_find_msr_index(&m->host, msr); 929 930 if ((i < 0 && m->guest.nr == NR_LOADSTORE_MSRS) || 931 (j < 0 && m->host.nr == NR_LOADSTORE_MSRS)) { 932 printk_once(KERN_WARNING "Not enough msr switch entries. " 933 "Can't add msr %x\n", msr); 934 return; 935 } 936 if (i < 0) { 937 i = m->guest.nr++; 938 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->guest.nr); 939 } 940 m->guest.val[i].index = msr; 941 m->guest.val[i].value = guest_val; 942 943 if (entry_only) 944 return; 945 946 if (j < 0) { 947 j = m->host.nr++; 948 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->host.nr); 949 } 950 m->host.val[j].index = msr; 951 m->host.val[j].value = host_val; 952 } 953 954 static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset) 955 { 956 u64 guest_efer = vmx->vcpu.arch.efer; 957 u64 ignore_bits = 0; 958 959 /* Shadow paging assumes NX to be available. */ 960 if (!enable_ept) 961 guest_efer |= EFER_NX; 962 963 /* 964 * LMA and LME handled by hardware; SCE meaningless outside long mode. 965 */ 966 ignore_bits |= EFER_SCE; 967 #ifdef CONFIG_X86_64 968 ignore_bits |= EFER_LMA | EFER_LME; 969 /* SCE is meaningful only in long mode on Intel */ 970 if (guest_efer & EFER_LMA) 971 ignore_bits &= ~(u64)EFER_SCE; 972 #endif 973 974 /* 975 * On EPT, we can't emulate NX, so we must switch EFER atomically. 976 * On CPUs that support "load IA32_EFER", always switch EFER 977 * atomically, since it's faster than switching it manually. 978 */ 979 if (cpu_has_load_ia32_efer() || 980 (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX))) { 981 if (!(guest_efer & EFER_LMA)) 982 guest_efer &= ~EFER_LME; 983 if (guest_efer != host_efer) 984 add_atomic_switch_msr(vmx, MSR_EFER, 985 guest_efer, host_efer, false); 986 else 987 clear_atomic_switch_msr(vmx, MSR_EFER); 988 return false; 989 } else { 990 clear_atomic_switch_msr(vmx, MSR_EFER); 991 992 guest_efer &= ~ignore_bits; 993 guest_efer |= host_efer & ignore_bits; 994 995 vmx->guest_msrs[efer_offset].data = guest_efer; 996 vmx->guest_msrs[efer_offset].mask = ~ignore_bits; 997 998 return true; 999 } 1000 } 1001 1002 #ifdef CONFIG_X86_32 1003 /* 1004 * On 32-bit kernels, VM exits still load the FS and GS bases from the 1005 * VMCS rather than the segment table. KVM uses this helper to figure 1006 * out the current bases to poke them into the VMCS before entry. 1007 */ 1008 static unsigned long segment_base(u16 selector) 1009 { 1010 struct desc_struct *table; 1011 unsigned long v; 1012 1013 if (!(selector & ~SEGMENT_RPL_MASK)) 1014 return 0; 1015 1016 table = get_current_gdt_ro(); 1017 1018 if ((selector & SEGMENT_TI_MASK) == SEGMENT_LDT) { 1019 u16 ldt_selector = kvm_read_ldt(); 1020 1021 if (!(ldt_selector & ~SEGMENT_RPL_MASK)) 1022 return 0; 1023 1024 table = (struct desc_struct *)segment_base(ldt_selector); 1025 } 1026 v = get_desc_base(&table[selector >> 3]); 1027 return v; 1028 } 1029 #endif 1030 1031 static inline bool pt_can_write_msr(struct vcpu_vmx *vmx) 1032 { 1033 return vmx_pt_mode_is_host_guest() && 1034 !(vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN); 1035 } 1036 1037 static inline void pt_load_msr(struct pt_ctx *ctx, u32 addr_range) 1038 { 1039 u32 i; 1040 1041 wrmsrl(MSR_IA32_RTIT_STATUS, ctx->status); 1042 wrmsrl(MSR_IA32_RTIT_OUTPUT_BASE, ctx->output_base); 1043 wrmsrl(MSR_IA32_RTIT_OUTPUT_MASK, ctx->output_mask); 1044 wrmsrl(MSR_IA32_RTIT_CR3_MATCH, ctx->cr3_match); 1045 for (i = 0; i < addr_range; i++) { 1046 wrmsrl(MSR_IA32_RTIT_ADDR0_A + i * 2, ctx->addr_a[i]); 1047 wrmsrl(MSR_IA32_RTIT_ADDR0_B + i * 2, ctx->addr_b[i]); 1048 } 1049 } 1050 1051 static inline void pt_save_msr(struct pt_ctx *ctx, u32 addr_range) 1052 { 1053 u32 i; 1054 1055 rdmsrl(MSR_IA32_RTIT_STATUS, ctx->status); 1056 rdmsrl(MSR_IA32_RTIT_OUTPUT_BASE, ctx->output_base); 1057 rdmsrl(MSR_IA32_RTIT_OUTPUT_MASK, ctx->output_mask); 1058 rdmsrl(MSR_IA32_RTIT_CR3_MATCH, ctx->cr3_match); 1059 for (i = 0; i < addr_range; i++) { 1060 rdmsrl(MSR_IA32_RTIT_ADDR0_A + i * 2, ctx->addr_a[i]); 1061 rdmsrl(MSR_IA32_RTIT_ADDR0_B + i * 2, ctx->addr_b[i]); 1062 } 1063 } 1064 1065 static void pt_guest_enter(struct vcpu_vmx *vmx) 1066 { 1067 if (vmx_pt_mode_is_system()) 1068 return; 1069 1070 /* 1071 * GUEST_IA32_RTIT_CTL is already set in the VMCS. 1072 * Save host state before VM entry. 1073 */ 1074 rdmsrl(MSR_IA32_RTIT_CTL, vmx->pt_desc.host.ctl); 1075 if (vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) { 1076 wrmsrl(MSR_IA32_RTIT_CTL, 0); 1077 pt_save_msr(&vmx->pt_desc.host, vmx->pt_desc.addr_range); 1078 pt_load_msr(&vmx->pt_desc.guest, vmx->pt_desc.addr_range); 1079 } 1080 } 1081 1082 static void pt_guest_exit(struct vcpu_vmx *vmx) 1083 { 1084 if (vmx_pt_mode_is_system()) 1085 return; 1086 1087 if (vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) { 1088 pt_save_msr(&vmx->pt_desc.guest, vmx->pt_desc.addr_range); 1089 pt_load_msr(&vmx->pt_desc.host, vmx->pt_desc.addr_range); 1090 } 1091 1092 /* Reload host state (IA32_RTIT_CTL will be cleared on VM exit). */ 1093 wrmsrl(MSR_IA32_RTIT_CTL, vmx->pt_desc.host.ctl); 1094 } 1095 1096 void vmx_set_host_fs_gs(struct vmcs_host_state *host, u16 fs_sel, u16 gs_sel, 1097 unsigned long fs_base, unsigned long gs_base) 1098 { 1099 if (unlikely(fs_sel != host->fs_sel)) { 1100 if (!(fs_sel & 7)) 1101 vmcs_write16(HOST_FS_SELECTOR, fs_sel); 1102 else 1103 vmcs_write16(HOST_FS_SELECTOR, 0); 1104 host->fs_sel = fs_sel; 1105 } 1106 if (unlikely(gs_sel != host->gs_sel)) { 1107 if (!(gs_sel & 7)) 1108 vmcs_write16(HOST_GS_SELECTOR, gs_sel); 1109 else 1110 vmcs_write16(HOST_GS_SELECTOR, 0); 1111 host->gs_sel = gs_sel; 1112 } 1113 if (unlikely(fs_base != host->fs_base)) { 1114 vmcs_writel(HOST_FS_BASE, fs_base); 1115 host->fs_base = fs_base; 1116 } 1117 if (unlikely(gs_base != host->gs_base)) { 1118 vmcs_writel(HOST_GS_BASE, gs_base); 1119 host->gs_base = gs_base; 1120 } 1121 } 1122 1123 void vmx_prepare_switch_to_guest(struct kvm_vcpu *vcpu) 1124 { 1125 struct vcpu_vmx *vmx = to_vmx(vcpu); 1126 struct vmcs_host_state *host_state; 1127 #ifdef CONFIG_X86_64 1128 int cpu = raw_smp_processor_id(); 1129 #endif 1130 unsigned long fs_base, gs_base; 1131 u16 fs_sel, gs_sel; 1132 int i; 1133 1134 vmx->req_immediate_exit = false; 1135 1136 /* 1137 * Note that guest MSRs to be saved/restored can also be changed 1138 * when guest state is loaded. This happens when guest transitions 1139 * to/from long-mode by setting MSR_EFER.LMA. 1140 */ 1141 if (!vmx->guest_msrs_ready) { 1142 vmx->guest_msrs_ready = true; 1143 for (i = 0; i < vmx->save_nmsrs; ++i) 1144 kvm_set_shared_msr(vmx->guest_msrs[i].index, 1145 vmx->guest_msrs[i].data, 1146 vmx->guest_msrs[i].mask); 1147 1148 } 1149 1150 if (vmx->nested.need_vmcs12_to_shadow_sync) 1151 nested_sync_vmcs12_to_shadow(vcpu); 1152 1153 if (vmx->guest_state_loaded) 1154 return; 1155 1156 host_state = &vmx->loaded_vmcs->host_state; 1157 1158 /* 1159 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not 1160 * allow segment selectors with cpl > 0 or ti == 1. 1161 */ 1162 host_state->ldt_sel = kvm_read_ldt(); 1163 1164 #ifdef CONFIG_X86_64 1165 savesegment(ds, host_state->ds_sel); 1166 savesegment(es, host_state->es_sel); 1167 1168 gs_base = cpu_kernelmode_gs_base(cpu); 1169 if (likely(is_64bit_mm(current->mm))) { 1170 save_fsgs_for_kvm(); 1171 fs_sel = current->thread.fsindex; 1172 gs_sel = current->thread.gsindex; 1173 fs_base = current->thread.fsbase; 1174 vmx->msr_host_kernel_gs_base = current->thread.gsbase; 1175 } else { 1176 savesegment(fs, fs_sel); 1177 savesegment(gs, gs_sel); 1178 fs_base = read_msr(MSR_FS_BASE); 1179 vmx->msr_host_kernel_gs_base = read_msr(MSR_KERNEL_GS_BASE); 1180 } 1181 1182 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base); 1183 #else 1184 savesegment(fs, fs_sel); 1185 savesegment(gs, gs_sel); 1186 fs_base = segment_base(fs_sel); 1187 gs_base = segment_base(gs_sel); 1188 #endif 1189 1190 vmx_set_host_fs_gs(host_state, fs_sel, gs_sel, fs_base, gs_base); 1191 vmx->guest_state_loaded = true; 1192 } 1193 1194 static void vmx_prepare_switch_to_host(struct vcpu_vmx *vmx) 1195 { 1196 struct vmcs_host_state *host_state; 1197 1198 if (!vmx->guest_state_loaded) 1199 return; 1200 1201 host_state = &vmx->loaded_vmcs->host_state; 1202 1203 ++vmx->vcpu.stat.host_state_reload; 1204 1205 #ifdef CONFIG_X86_64 1206 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base); 1207 #endif 1208 if (host_state->ldt_sel || (host_state->gs_sel & 7)) { 1209 kvm_load_ldt(host_state->ldt_sel); 1210 #ifdef CONFIG_X86_64 1211 load_gs_index(host_state->gs_sel); 1212 #else 1213 loadsegment(gs, host_state->gs_sel); 1214 #endif 1215 } 1216 if (host_state->fs_sel & 7) 1217 loadsegment(fs, host_state->fs_sel); 1218 #ifdef CONFIG_X86_64 1219 if (unlikely(host_state->ds_sel | host_state->es_sel)) { 1220 loadsegment(ds, host_state->ds_sel); 1221 loadsegment(es, host_state->es_sel); 1222 } 1223 #endif 1224 invalidate_tss_limit(); 1225 #ifdef CONFIG_X86_64 1226 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base); 1227 #endif 1228 load_fixmap_gdt(raw_smp_processor_id()); 1229 vmx->guest_state_loaded = false; 1230 vmx->guest_msrs_ready = false; 1231 } 1232 1233 #ifdef CONFIG_X86_64 1234 static u64 vmx_read_guest_kernel_gs_base(struct vcpu_vmx *vmx) 1235 { 1236 preempt_disable(); 1237 if (vmx->guest_state_loaded) 1238 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base); 1239 preempt_enable(); 1240 return vmx->msr_guest_kernel_gs_base; 1241 } 1242 1243 static void vmx_write_guest_kernel_gs_base(struct vcpu_vmx *vmx, u64 data) 1244 { 1245 preempt_disable(); 1246 if (vmx->guest_state_loaded) 1247 wrmsrl(MSR_KERNEL_GS_BASE, data); 1248 preempt_enable(); 1249 vmx->msr_guest_kernel_gs_base = data; 1250 } 1251 #endif 1252 1253 static void vmx_vcpu_pi_load(struct kvm_vcpu *vcpu, int cpu) 1254 { 1255 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu); 1256 struct pi_desc old, new; 1257 unsigned int dest; 1258 1259 /* 1260 * In case of hot-plug or hot-unplug, we may have to undo 1261 * vmx_vcpu_pi_put even if there is no assigned device. And we 1262 * always keep PI.NDST up to date for simplicity: it makes the 1263 * code easier, and CPU migration is not a fast path. 1264 */ 1265 if (!pi_test_sn(pi_desc) && vcpu->cpu == cpu) 1266 return; 1267 1268 /* 1269 * If the 'nv' field is POSTED_INTR_WAKEUP_VECTOR, do not change 1270 * PI.NDST: pi_post_block is the one expected to change PID.NDST and the 1271 * wakeup handler expects the vCPU to be on the blocked_vcpu_list that 1272 * matches PI.NDST. Otherwise, a vcpu may not be able to be woken up 1273 * correctly. 1274 */ 1275 if (pi_desc->nv == POSTED_INTR_WAKEUP_VECTOR || vcpu->cpu == cpu) { 1276 pi_clear_sn(pi_desc); 1277 goto after_clear_sn; 1278 } 1279 1280 /* The full case. */ 1281 do { 1282 old.control = new.control = pi_desc->control; 1283 1284 dest = cpu_physical_id(cpu); 1285 1286 if (x2apic_enabled()) 1287 new.ndst = dest; 1288 else 1289 new.ndst = (dest << 8) & 0xFF00; 1290 1291 new.sn = 0; 1292 } while (cmpxchg64(&pi_desc->control, old.control, 1293 new.control) != old.control); 1294 1295 after_clear_sn: 1296 1297 /* 1298 * Clear SN before reading the bitmap. The VT-d firmware 1299 * writes the bitmap and reads SN atomically (5.2.3 in the 1300 * spec), so it doesn't really have a memory barrier that 1301 * pairs with this, but we cannot do that and we need one. 1302 */ 1303 smp_mb__after_atomic(); 1304 1305 if (!pi_is_pir_empty(pi_desc)) 1306 pi_set_on(pi_desc); 1307 } 1308 1309 void vmx_vcpu_load_vmcs(struct kvm_vcpu *vcpu, int cpu) 1310 { 1311 struct vcpu_vmx *vmx = to_vmx(vcpu); 1312 bool already_loaded = vmx->loaded_vmcs->cpu == cpu; 1313 1314 if (!already_loaded) { 1315 loaded_vmcs_clear(vmx->loaded_vmcs); 1316 local_irq_disable(); 1317 1318 /* 1319 * Ensure loaded_vmcs->cpu is read before adding loaded_vmcs to 1320 * this cpu's percpu list, otherwise it may not yet be deleted 1321 * from its previous cpu's percpu list. Pairs with the 1322 * smb_wmb() in __loaded_vmcs_clear(). 1323 */ 1324 smp_rmb(); 1325 1326 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link, 1327 &per_cpu(loaded_vmcss_on_cpu, cpu)); 1328 local_irq_enable(); 1329 } 1330 1331 if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) { 1332 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs; 1333 vmcs_load(vmx->loaded_vmcs->vmcs); 1334 indirect_branch_prediction_barrier(); 1335 } 1336 1337 if (!already_loaded) { 1338 void *gdt = get_current_gdt_ro(); 1339 unsigned long sysenter_esp; 1340 1341 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu); 1342 1343 /* 1344 * Linux uses per-cpu TSS and GDT, so set these when switching 1345 * processors. See 22.2.4. 1346 */ 1347 vmcs_writel(HOST_TR_BASE, 1348 (unsigned long)&get_cpu_entry_area(cpu)->tss.x86_tss); 1349 vmcs_writel(HOST_GDTR_BASE, (unsigned long)gdt); /* 22.2.4 */ 1350 1351 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp); 1352 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */ 1353 1354 vmx->loaded_vmcs->cpu = cpu; 1355 } 1356 1357 /* Setup TSC multiplier */ 1358 if (kvm_has_tsc_control && 1359 vmx->current_tsc_ratio != vcpu->arch.tsc_scaling_ratio) 1360 decache_tsc_multiplier(vmx); 1361 } 1362 1363 /* 1364 * Switches to specified vcpu, until a matching vcpu_put(), but assumes 1365 * vcpu mutex is already taken. 1366 */ 1367 void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu) 1368 { 1369 struct vcpu_vmx *vmx = to_vmx(vcpu); 1370 1371 vmx_vcpu_load_vmcs(vcpu, cpu); 1372 1373 vmx_vcpu_pi_load(vcpu, cpu); 1374 1375 vmx->host_pkru = read_pkru(); 1376 vmx->host_debugctlmsr = get_debugctlmsr(); 1377 } 1378 1379 static void vmx_vcpu_pi_put(struct kvm_vcpu *vcpu) 1380 { 1381 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu); 1382 1383 if (!kvm_arch_has_assigned_device(vcpu->kvm) || 1384 !irq_remapping_cap(IRQ_POSTING_CAP) || 1385 !kvm_vcpu_apicv_active(vcpu)) 1386 return; 1387 1388 /* Set SN when the vCPU is preempted */ 1389 if (vcpu->preempted) 1390 pi_set_sn(pi_desc); 1391 } 1392 1393 static void vmx_vcpu_put(struct kvm_vcpu *vcpu) 1394 { 1395 vmx_vcpu_pi_put(vcpu); 1396 1397 vmx_prepare_switch_to_host(to_vmx(vcpu)); 1398 } 1399 1400 static bool emulation_required(struct kvm_vcpu *vcpu) 1401 { 1402 return emulate_invalid_guest_state && !guest_state_valid(vcpu); 1403 } 1404 1405 unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu) 1406 { 1407 struct vcpu_vmx *vmx = to_vmx(vcpu); 1408 unsigned long rflags, save_rflags; 1409 1410 if (!kvm_register_is_available(vcpu, VCPU_EXREG_RFLAGS)) { 1411 kvm_register_mark_available(vcpu, VCPU_EXREG_RFLAGS); 1412 rflags = vmcs_readl(GUEST_RFLAGS); 1413 if (vmx->rmode.vm86_active) { 1414 rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS; 1415 save_rflags = vmx->rmode.save_rflags; 1416 rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS; 1417 } 1418 vmx->rflags = rflags; 1419 } 1420 return vmx->rflags; 1421 } 1422 1423 void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags) 1424 { 1425 struct vcpu_vmx *vmx = to_vmx(vcpu); 1426 unsigned long old_rflags; 1427 1428 if (enable_unrestricted_guest) { 1429 kvm_register_mark_available(vcpu, VCPU_EXREG_RFLAGS); 1430 vmx->rflags = rflags; 1431 vmcs_writel(GUEST_RFLAGS, rflags); 1432 return; 1433 } 1434 1435 old_rflags = vmx_get_rflags(vcpu); 1436 vmx->rflags = rflags; 1437 if (vmx->rmode.vm86_active) { 1438 vmx->rmode.save_rflags = rflags; 1439 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM; 1440 } 1441 vmcs_writel(GUEST_RFLAGS, rflags); 1442 1443 if ((old_rflags ^ vmx->rflags) & X86_EFLAGS_VM) 1444 vmx->emulation_required = emulation_required(vcpu); 1445 } 1446 1447 u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu) 1448 { 1449 u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO); 1450 int ret = 0; 1451 1452 if (interruptibility & GUEST_INTR_STATE_STI) 1453 ret |= KVM_X86_SHADOW_INT_STI; 1454 if (interruptibility & GUEST_INTR_STATE_MOV_SS) 1455 ret |= KVM_X86_SHADOW_INT_MOV_SS; 1456 1457 return ret; 1458 } 1459 1460 void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask) 1461 { 1462 u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO); 1463 u32 interruptibility = interruptibility_old; 1464 1465 interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS); 1466 1467 if (mask & KVM_X86_SHADOW_INT_MOV_SS) 1468 interruptibility |= GUEST_INTR_STATE_MOV_SS; 1469 else if (mask & KVM_X86_SHADOW_INT_STI) 1470 interruptibility |= GUEST_INTR_STATE_STI; 1471 1472 if ((interruptibility != interruptibility_old)) 1473 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility); 1474 } 1475 1476 static int vmx_rtit_ctl_check(struct kvm_vcpu *vcpu, u64 data) 1477 { 1478 struct vcpu_vmx *vmx = to_vmx(vcpu); 1479 unsigned long value; 1480 1481 /* 1482 * Any MSR write that attempts to change bits marked reserved will 1483 * case a #GP fault. 1484 */ 1485 if (data & vmx->pt_desc.ctl_bitmask) 1486 return 1; 1487 1488 /* 1489 * Any attempt to modify IA32_RTIT_CTL while TraceEn is set will 1490 * result in a #GP unless the same write also clears TraceEn. 1491 */ 1492 if ((vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) && 1493 ((vmx->pt_desc.guest.ctl ^ data) & ~RTIT_CTL_TRACEEN)) 1494 return 1; 1495 1496 /* 1497 * WRMSR to IA32_RTIT_CTL that sets TraceEn but clears this bit 1498 * and FabricEn would cause #GP, if 1499 * CPUID.(EAX=14H, ECX=0):ECX.SNGLRGNOUT[bit 2] = 0 1500 */ 1501 if ((data & RTIT_CTL_TRACEEN) && !(data & RTIT_CTL_TOPA) && 1502 !(data & RTIT_CTL_FABRIC_EN) && 1503 !intel_pt_validate_cap(vmx->pt_desc.caps, 1504 PT_CAP_single_range_output)) 1505 return 1; 1506 1507 /* 1508 * MTCFreq, CycThresh and PSBFreq encodings check, any MSR write that 1509 * utilize encodings marked reserved will casue a #GP fault. 1510 */ 1511 value = intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_mtc_periods); 1512 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_mtc) && 1513 !test_bit((data & RTIT_CTL_MTC_RANGE) >> 1514 RTIT_CTL_MTC_RANGE_OFFSET, &value)) 1515 return 1; 1516 value = intel_pt_validate_cap(vmx->pt_desc.caps, 1517 PT_CAP_cycle_thresholds); 1518 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_psb_cyc) && 1519 !test_bit((data & RTIT_CTL_CYC_THRESH) >> 1520 RTIT_CTL_CYC_THRESH_OFFSET, &value)) 1521 return 1; 1522 value = intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_psb_periods); 1523 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_psb_cyc) && 1524 !test_bit((data & RTIT_CTL_PSB_FREQ) >> 1525 RTIT_CTL_PSB_FREQ_OFFSET, &value)) 1526 return 1; 1527 1528 /* 1529 * If ADDRx_CFG is reserved or the encodings is >2 will 1530 * cause a #GP fault. 1531 */ 1532 value = (data & RTIT_CTL_ADDR0) >> RTIT_CTL_ADDR0_OFFSET; 1533 if ((value && (vmx->pt_desc.addr_range < 1)) || (value > 2)) 1534 return 1; 1535 value = (data & RTIT_CTL_ADDR1) >> RTIT_CTL_ADDR1_OFFSET; 1536 if ((value && (vmx->pt_desc.addr_range < 2)) || (value > 2)) 1537 return 1; 1538 value = (data & RTIT_CTL_ADDR2) >> RTIT_CTL_ADDR2_OFFSET; 1539 if ((value && (vmx->pt_desc.addr_range < 3)) || (value > 2)) 1540 return 1; 1541 value = (data & RTIT_CTL_ADDR3) >> RTIT_CTL_ADDR3_OFFSET; 1542 if ((value && (vmx->pt_desc.addr_range < 4)) || (value > 2)) 1543 return 1; 1544 1545 return 0; 1546 } 1547 1548 static int skip_emulated_instruction(struct kvm_vcpu *vcpu) 1549 { 1550 unsigned long rip; 1551 1552 /* 1553 * Using VMCS.VM_EXIT_INSTRUCTION_LEN on EPT misconfig depends on 1554 * undefined behavior: Intel's SDM doesn't mandate the VMCS field be 1555 * set when EPT misconfig occurs. In practice, real hardware updates 1556 * VM_EXIT_INSTRUCTION_LEN on EPT misconfig, but other hypervisors 1557 * (namely Hyper-V) don't set it due to it being undefined behavior, 1558 * i.e. we end up advancing IP with some random value. 1559 */ 1560 if (!static_cpu_has(X86_FEATURE_HYPERVISOR) || 1561 to_vmx(vcpu)->exit_reason != EXIT_REASON_EPT_MISCONFIG) { 1562 rip = kvm_rip_read(vcpu); 1563 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN); 1564 kvm_rip_write(vcpu, rip); 1565 } else { 1566 if (!kvm_emulate_instruction(vcpu, EMULTYPE_SKIP)) 1567 return 0; 1568 } 1569 1570 /* skipping an emulated instruction also counts */ 1571 vmx_set_interrupt_shadow(vcpu, 0); 1572 1573 return 1; 1574 } 1575 1576 1577 /* 1578 * Recognizes a pending MTF VM-exit and records the nested state for later 1579 * delivery. 1580 */ 1581 static void vmx_update_emulated_instruction(struct kvm_vcpu *vcpu) 1582 { 1583 struct vmcs12 *vmcs12 = get_vmcs12(vcpu); 1584 struct vcpu_vmx *vmx = to_vmx(vcpu); 1585 1586 if (!is_guest_mode(vcpu)) 1587 return; 1588 1589 /* 1590 * Per the SDM, MTF takes priority over debug-trap exceptions besides 1591 * T-bit traps. As instruction emulation is completed (i.e. at the 1592 * instruction boundary), any #DB exception pending delivery must be a 1593 * debug-trap. Record the pending MTF state to be delivered in 1594 * vmx_check_nested_events(). 1595 */ 1596 if (nested_cpu_has_mtf(vmcs12) && 1597 (!vcpu->arch.exception.pending || 1598 vcpu->arch.exception.nr == DB_VECTOR)) 1599 vmx->nested.mtf_pending = true; 1600 else 1601 vmx->nested.mtf_pending = false; 1602 } 1603 1604 static int vmx_skip_emulated_instruction(struct kvm_vcpu *vcpu) 1605 { 1606 vmx_update_emulated_instruction(vcpu); 1607 return skip_emulated_instruction(vcpu); 1608 } 1609 1610 static void vmx_clear_hlt(struct kvm_vcpu *vcpu) 1611 { 1612 /* 1613 * Ensure that we clear the HLT state in the VMCS. We don't need to 1614 * explicitly skip the instruction because if the HLT state is set, 1615 * then the instruction is already executing and RIP has already been 1616 * advanced. 1617 */ 1618 if (kvm_hlt_in_guest(vcpu->kvm) && 1619 vmcs_read32(GUEST_ACTIVITY_STATE) == GUEST_ACTIVITY_HLT) 1620 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE); 1621 } 1622 1623 static void vmx_queue_exception(struct kvm_vcpu *vcpu) 1624 { 1625 struct vcpu_vmx *vmx = to_vmx(vcpu); 1626 unsigned nr = vcpu->arch.exception.nr; 1627 bool has_error_code = vcpu->arch.exception.has_error_code; 1628 u32 error_code = vcpu->arch.exception.error_code; 1629 u32 intr_info = nr | INTR_INFO_VALID_MASK; 1630 1631 kvm_deliver_exception_payload(vcpu); 1632 1633 if (has_error_code) { 1634 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code); 1635 intr_info |= INTR_INFO_DELIVER_CODE_MASK; 1636 } 1637 1638 if (vmx->rmode.vm86_active) { 1639 int inc_eip = 0; 1640 if (kvm_exception_is_soft(nr)) 1641 inc_eip = vcpu->arch.event_exit_inst_len; 1642 kvm_inject_realmode_interrupt(vcpu, nr, inc_eip); 1643 return; 1644 } 1645 1646 WARN_ON_ONCE(vmx->emulation_required); 1647 1648 if (kvm_exception_is_soft(nr)) { 1649 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1650 vmx->vcpu.arch.event_exit_inst_len); 1651 intr_info |= INTR_TYPE_SOFT_EXCEPTION; 1652 } else 1653 intr_info |= INTR_TYPE_HARD_EXCEPTION; 1654 1655 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info); 1656 1657 vmx_clear_hlt(vcpu); 1658 } 1659 1660 /* 1661 * Swap MSR entry in host/guest MSR entry array. 1662 */ 1663 static void move_msr_up(struct vcpu_vmx *vmx, int from, int to) 1664 { 1665 struct shared_msr_entry tmp; 1666 1667 tmp = vmx->guest_msrs[to]; 1668 vmx->guest_msrs[to] = vmx->guest_msrs[from]; 1669 vmx->guest_msrs[from] = tmp; 1670 } 1671 1672 /* 1673 * Set up the vmcs to automatically save and restore system 1674 * msrs. Don't touch the 64-bit msrs if the guest is in legacy 1675 * mode, as fiddling with msrs is very expensive. 1676 */ 1677 static void setup_msrs(struct vcpu_vmx *vmx) 1678 { 1679 int save_nmsrs, index; 1680 1681 save_nmsrs = 0; 1682 #ifdef CONFIG_X86_64 1683 /* 1684 * The SYSCALL MSRs are only needed on long mode guests, and only 1685 * when EFER.SCE is set. 1686 */ 1687 if (is_long_mode(&vmx->vcpu) && (vmx->vcpu.arch.efer & EFER_SCE)) { 1688 index = __find_msr_index(vmx, MSR_STAR); 1689 if (index >= 0) 1690 move_msr_up(vmx, index, save_nmsrs++); 1691 index = __find_msr_index(vmx, MSR_LSTAR); 1692 if (index >= 0) 1693 move_msr_up(vmx, index, save_nmsrs++); 1694 index = __find_msr_index(vmx, MSR_SYSCALL_MASK); 1695 if (index >= 0) 1696 move_msr_up(vmx, index, save_nmsrs++); 1697 } 1698 #endif 1699 index = __find_msr_index(vmx, MSR_EFER); 1700 if (index >= 0 && update_transition_efer(vmx, index)) 1701 move_msr_up(vmx, index, save_nmsrs++); 1702 index = __find_msr_index(vmx, MSR_TSC_AUX); 1703 if (index >= 0 && guest_cpuid_has(&vmx->vcpu, X86_FEATURE_RDTSCP)) 1704 move_msr_up(vmx, index, save_nmsrs++); 1705 index = __find_msr_index(vmx, MSR_IA32_TSX_CTRL); 1706 if (index >= 0) 1707 move_msr_up(vmx, index, save_nmsrs++); 1708 1709 vmx->save_nmsrs = save_nmsrs; 1710 vmx->guest_msrs_ready = false; 1711 1712 if (cpu_has_vmx_msr_bitmap()) 1713 vmx_update_msr_bitmap(&vmx->vcpu); 1714 } 1715 1716 static u64 vmx_read_l1_tsc_offset(struct kvm_vcpu *vcpu) 1717 { 1718 struct vmcs12 *vmcs12 = get_vmcs12(vcpu); 1719 1720 if (is_guest_mode(vcpu) && 1721 (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETTING)) 1722 return vcpu->arch.tsc_offset - vmcs12->tsc_offset; 1723 1724 return vcpu->arch.tsc_offset; 1725 } 1726 1727 static u64 vmx_write_l1_tsc_offset(struct kvm_vcpu *vcpu, u64 offset) 1728 { 1729 struct vmcs12 *vmcs12 = get_vmcs12(vcpu); 1730 u64 g_tsc_offset = 0; 1731 1732 /* 1733 * We're here if L1 chose not to trap WRMSR to TSC. According 1734 * to the spec, this should set L1's TSC; The offset that L1 1735 * set for L2 remains unchanged, and still needs to be added 1736 * to the newly set TSC to get L2's TSC. 1737 */ 1738 if (is_guest_mode(vcpu) && 1739 (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETTING)) 1740 g_tsc_offset = vmcs12->tsc_offset; 1741 1742 trace_kvm_write_tsc_offset(vcpu->vcpu_id, 1743 vcpu->arch.tsc_offset - g_tsc_offset, 1744 offset); 1745 vmcs_write64(TSC_OFFSET, offset + g_tsc_offset); 1746 return offset + g_tsc_offset; 1747 } 1748 1749 /* 1750 * nested_vmx_allowed() checks whether a guest should be allowed to use VMX 1751 * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for 1752 * all guests if the "nested" module option is off, and can also be disabled 1753 * for a single guest by disabling its VMX cpuid bit. 1754 */ 1755 bool nested_vmx_allowed(struct kvm_vcpu *vcpu) 1756 { 1757 return nested && guest_cpuid_has(vcpu, X86_FEATURE_VMX); 1758 } 1759 1760 static inline bool vmx_feature_control_msr_valid(struct kvm_vcpu *vcpu, 1761 uint64_t val) 1762 { 1763 uint64_t valid_bits = to_vmx(vcpu)->msr_ia32_feature_control_valid_bits; 1764 1765 return !(val & ~valid_bits); 1766 } 1767 1768 static int vmx_get_msr_feature(struct kvm_msr_entry *msr) 1769 { 1770 switch (msr->index) { 1771 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC: 1772 if (!nested) 1773 return 1; 1774 return vmx_get_vmx_msr(&vmcs_config.nested, msr->index, &msr->data); 1775 default: 1776 return 1; 1777 } 1778 } 1779 1780 /* 1781 * Reads an msr value (of 'msr_index') into 'pdata'. 1782 * Returns 0 on success, non-0 otherwise. 1783 * Assumes vcpu_load() was already called. 1784 */ 1785 static int vmx_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info) 1786 { 1787 struct vcpu_vmx *vmx = to_vmx(vcpu); 1788 struct shared_msr_entry *msr; 1789 u32 index; 1790 1791 switch (msr_info->index) { 1792 #ifdef CONFIG_X86_64 1793 case MSR_FS_BASE: 1794 msr_info->data = vmcs_readl(GUEST_FS_BASE); 1795 break; 1796 case MSR_GS_BASE: 1797 msr_info->data = vmcs_readl(GUEST_GS_BASE); 1798 break; 1799 case MSR_KERNEL_GS_BASE: 1800 msr_info->data = vmx_read_guest_kernel_gs_base(vmx); 1801 break; 1802 #endif 1803 case MSR_EFER: 1804 return kvm_get_msr_common(vcpu, msr_info); 1805 case MSR_IA32_TSX_CTRL: 1806 if (!msr_info->host_initiated && 1807 !(vcpu->arch.arch_capabilities & ARCH_CAP_TSX_CTRL_MSR)) 1808 return 1; 1809 goto find_shared_msr; 1810 case MSR_IA32_UMWAIT_CONTROL: 1811 if (!msr_info->host_initiated && !vmx_has_waitpkg(vmx)) 1812 return 1; 1813 1814 msr_info->data = vmx->msr_ia32_umwait_control; 1815 break; 1816 case MSR_IA32_SPEC_CTRL: 1817 if (!msr_info->host_initiated && 1818 !guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL)) 1819 return 1; 1820 1821 msr_info->data = to_vmx(vcpu)->spec_ctrl; 1822 break; 1823 case MSR_IA32_SYSENTER_CS: 1824 msr_info->data = vmcs_read32(GUEST_SYSENTER_CS); 1825 break; 1826 case MSR_IA32_SYSENTER_EIP: 1827 msr_info->data = vmcs_readl(GUEST_SYSENTER_EIP); 1828 break; 1829 case MSR_IA32_SYSENTER_ESP: 1830 msr_info->data = vmcs_readl(GUEST_SYSENTER_ESP); 1831 break; 1832 case MSR_IA32_BNDCFGS: 1833 if (!kvm_mpx_supported() || 1834 (!msr_info->host_initiated && 1835 !guest_cpuid_has(vcpu, X86_FEATURE_MPX))) 1836 return 1; 1837 msr_info->data = vmcs_read64(GUEST_BNDCFGS); 1838 break; 1839 case MSR_IA32_MCG_EXT_CTL: 1840 if (!msr_info->host_initiated && 1841 !(vmx->msr_ia32_feature_control & 1842 FEAT_CTL_LMCE_ENABLED)) 1843 return 1; 1844 msr_info->data = vcpu->arch.mcg_ext_ctl; 1845 break; 1846 case MSR_IA32_FEAT_CTL: 1847 msr_info->data = vmx->msr_ia32_feature_control; 1848 break; 1849 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC: 1850 if (!nested_vmx_allowed(vcpu)) 1851 return 1; 1852 if (vmx_get_vmx_msr(&vmx->nested.msrs, msr_info->index, 1853 &msr_info->data)) 1854 return 1; 1855 /* 1856 * Enlightened VMCS v1 doesn't have certain fields, but buggy 1857 * Hyper-V versions are still trying to use corresponding 1858 * features when they are exposed. Filter out the essential 1859 * minimum. 1860 */ 1861 if (!msr_info->host_initiated && 1862 vmx->nested.enlightened_vmcs_enabled) 1863 nested_evmcs_filter_control_msr(msr_info->index, 1864 &msr_info->data); 1865 break; 1866 case MSR_IA32_RTIT_CTL: 1867 if (!vmx_pt_mode_is_host_guest()) 1868 return 1; 1869 msr_info->data = vmx->pt_desc.guest.ctl; 1870 break; 1871 case MSR_IA32_RTIT_STATUS: 1872 if (!vmx_pt_mode_is_host_guest()) 1873 return 1; 1874 msr_info->data = vmx->pt_desc.guest.status; 1875 break; 1876 case MSR_IA32_RTIT_CR3_MATCH: 1877 if (!vmx_pt_mode_is_host_guest() || 1878 !intel_pt_validate_cap(vmx->pt_desc.caps, 1879 PT_CAP_cr3_filtering)) 1880 return 1; 1881 msr_info->data = vmx->pt_desc.guest.cr3_match; 1882 break; 1883 case MSR_IA32_RTIT_OUTPUT_BASE: 1884 if (!vmx_pt_mode_is_host_guest() || 1885 (!intel_pt_validate_cap(vmx->pt_desc.caps, 1886 PT_CAP_topa_output) && 1887 !intel_pt_validate_cap(vmx->pt_desc.caps, 1888 PT_CAP_single_range_output))) 1889 return 1; 1890 msr_info->data = vmx->pt_desc.guest.output_base; 1891 break; 1892 case MSR_IA32_RTIT_OUTPUT_MASK: 1893 if (!vmx_pt_mode_is_host_guest() || 1894 (!intel_pt_validate_cap(vmx->pt_desc.caps, 1895 PT_CAP_topa_output) && 1896 !intel_pt_validate_cap(vmx->pt_desc.caps, 1897 PT_CAP_single_range_output))) 1898 return 1; 1899 msr_info->data = vmx->pt_desc.guest.output_mask; 1900 break; 1901 case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B: 1902 index = msr_info->index - MSR_IA32_RTIT_ADDR0_A; 1903 if (!vmx_pt_mode_is_host_guest() || 1904 (index >= 2 * intel_pt_validate_cap(vmx->pt_desc.caps, 1905 PT_CAP_num_address_ranges))) 1906 return 1; 1907 if (index % 2) 1908 msr_info->data = vmx->pt_desc.guest.addr_b[index / 2]; 1909 else 1910 msr_info->data = vmx->pt_desc.guest.addr_a[index / 2]; 1911 break; 1912 case MSR_TSC_AUX: 1913 if (!msr_info->host_initiated && 1914 !guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP)) 1915 return 1; 1916 goto find_shared_msr; 1917 default: 1918 find_shared_msr: 1919 msr = find_msr_entry(vmx, msr_info->index); 1920 if (msr) { 1921 msr_info->data = msr->data; 1922 break; 1923 } 1924 return kvm_get_msr_common(vcpu, msr_info); 1925 } 1926 1927 return 0; 1928 } 1929 1930 /* 1931 * Writes msr value into the appropriate "register". 1932 * Returns 0 on success, non-0 otherwise. 1933 * Assumes vcpu_load() was already called. 1934 */ 1935 static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info) 1936 { 1937 struct vcpu_vmx *vmx = to_vmx(vcpu); 1938 struct shared_msr_entry *msr; 1939 int ret = 0; 1940 u32 msr_index = msr_info->index; 1941 u64 data = msr_info->data; 1942 u32 index; 1943 1944 switch (msr_index) { 1945 case MSR_EFER: 1946 ret = kvm_set_msr_common(vcpu, msr_info); 1947 break; 1948 #ifdef CONFIG_X86_64 1949 case MSR_FS_BASE: 1950 vmx_segment_cache_clear(vmx); 1951 vmcs_writel(GUEST_FS_BASE, data); 1952 break; 1953 case MSR_GS_BASE: 1954 vmx_segment_cache_clear(vmx); 1955 vmcs_writel(GUEST_GS_BASE, data); 1956 break; 1957 case MSR_KERNEL_GS_BASE: 1958 vmx_write_guest_kernel_gs_base(vmx, data); 1959 break; 1960 #endif 1961 case MSR_IA32_SYSENTER_CS: 1962 if (is_guest_mode(vcpu)) 1963 get_vmcs12(vcpu)->guest_sysenter_cs = data; 1964 vmcs_write32(GUEST_SYSENTER_CS, data); 1965 break; 1966 case MSR_IA32_SYSENTER_EIP: 1967 if (is_guest_mode(vcpu)) 1968 get_vmcs12(vcpu)->guest_sysenter_eip = data; 1969 vmcs_writel(GUEST_SYSENTER_EIP, data); 1970 break; 1971 case MSR_IA32_SYSENTER_ESP: 1972 if (is_guest_mode(vcpu)) 1973 get_vmcs12(vcpu)->guest_sysenter_esp = data; 1974 vmcs_writel(GUEST_SYSENTER_ESP, data); 1975 break; 1976 case MSR_IA32_DEBUGCTLMSR: 1977 if (is_guest_mode(vcpu) && get_vmcs12(vcpu)->vm_exit_controls & 1978 VM_EXIT_SAVE_DEBUG_CONTROLS) 1979 get_vmcs12(vcpu)->guest_ia32_debugctl = data; 1980 1981 ret = kvm_set_msr_common(vcpu, msr_info); 1982 break; 1983 1984 case MSR_IA32_BNDCFGS: 1985 if (!kvm_mpx_supported() || 1986 (!msr_info->host_initiated && 1987 !guest_cpuid_has(vcpu, X86_FEATURE_MPX))) 1988 return 1; 1989 if (is_noncanonical_address(data & PAGE_MASK, vcpu) || 1990 (data & MSR_IA32_BNDCFGS_RSVD)) 1991 return 1; 1992 vmcs_write64(GUEST_BNDCFGS, data); 1993 break; 1994 case MSR_IA32_UMWAIT_CONTROL: 1995 if (!msr_info->host_initiated && !vmx_has_waitpkg(vmx)) 1996 return 1; 1997 1998 /* The reserved bit 1 and non-32 bit [63:32] should be zero */ 1999 if (data & (BIT_ULL(1) | GENMASK_ULL(63, 32))) 2000 return 1; 2001 2002 vmx->msr_ia32_umwait_control = data; 2003 break; 2004 case MSR_IA32_SPEC_CTRL: 2005 if (!msr_info->host_initiated && 2006 !guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL)) 2007 return 1; 2008 2009 if (data & ~kvm_spec_ctrl_valid_bits(vcpu)) 2010 return 1; 2011 2012 vmx->spec_ctrl = data; 2013 if (!data) 2014 break; 2015 2016 /* 2017 * For non-nested: 2018 * When it's written (to non-zero) for the first time, pass 2019 * it through. 2020 * 2021 * For nested: 2022 * The handling of the MSR bitmap for L2 guests is done in 2023 * nested_vmx_prepare_msr_bitmap. We should not touch the 2024 * vmcs02.msr_bitmap here since it gets completely overwritten 2025 * in the merging. We update the vmcs01 here for L1 as well 2026 * since it will end up touching the MSR anyway now. 2027 */ 2028 vmx_disable_intercept_for_msr(vmx->vmcs01.msr_bitmap, 2029 MSR_IA32_SPEC_CTRL, 2030 MSR_TYPE_RW); 2031 break; 2032 case MSR_IA32_TSX_CTRL: 2033 if (!msr_info->host_initiated && 2034 !(vcpu->arch.arch_capabilities & ARCH_CAP_TSX_CTRL_MSR)) 2035 return 1; 2036 if (data & ~(TSX_CTRL_RTM_DISABLE | TSX_CTRL_CPUID_CLEAR)) 2037 return 1; 2038 goto find_shared_msr; 2039 case MSR_IA32_PRED_CMD: 2040 if (!msr_info->host_initiated && 2041 !guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL)) 2042 return 1; 2043 2044 if (data & ~PRED_CMD_IBPB) 2045 return 1; 2046 if (!boot_cpu_has(X86_FEATURE_SPEC_CTRL)) 2047 return 1; 2048 if (!data) 2049 break; 2050 2051 wrmsrl(MSR_IA32_PRED_CMD, PRED_CMD_IBPB); 2052 2053 /* 2054 * For non-nested: 2055 * When it's written (to non-zero) for the first time, pass 2056 * it through. 2057 * 2058 * For nested: 2059 * The handling of the MSR bitmap for L2 guests is done in 2060 * nested_vmx_prepare_msr_bitmap. We should not touch the 2061 * vmcs02.msr_bitmap here since it gets completely overwritten 2062 * in the merging. 2063 */ 2064 vmx_disable_intercept_for_msr(vmx->vmcs01.msr_bitmap, MSR_IA32_PRED_CMD, 2065 MSR_TYPE_W); 2066 break; 2067 case MSR_IA32_CR_PAT: 2068 if (!kvm_pat_valid(data)) 2069 return 1; 2070 2071 if (is_guest_mode(vcpu) && 2072 get_vmcs12(vcpu)->vm_exit_controls & VM_EXIT_SAVE_IA32_PAT) 2073 get_vmcs12(vcpu)->guest_ia32_pat = data; 2074 2075 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) { 2076 vmcs_write64(GUEST_IA32_PAT, data); 2077 vcpu->arch.pat = data; 2078 break; 2079 } 2080 ret = kvm_set_msr_common(vcpu, msr_info); 2081 break; 2082 case MSR_IA32_TSC_ADJUST: 2083 ret = kvm_set_msr_common(vcpu, msr_info); 2084 break; 2085 case MSR_IA32_MCG_EXT_CTL: 2086 if ((!msr_info->host_initiated && 2087 !(to_vmx(vcpu)->msr_ia32_feature_control & 2088 FEAT_CTL_LMCE_ENABLED)) || 2089 (data & ~MCG_EXT_CTL_LMCE_EN)) 2090 return 1; 2091 vcpu->arch.mcg_ext_ctl = data; 2092 break; 2093 case MSR_IA32_FEAT_CTL: 2094 if (!vmx_feature_control_msr_valid(vcpu, data) || 2095 (to_vmx(vcpu)->msr_ia32_feature_control & 2096 FEAT_CTL_LOCKED && !msr_info->host_initiated)) 2097 return 1; 2098 vmx->msr_ia32_feature_control = data; 2099 if (msr_info->host_initiated && data == 0) 2100 vmx_leave_nested(vcpu); 2101 break; 2102 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC: 2103 if (!msr_info->host_initiated) 2104 return 1; /* they are read-only */ 2105 if (!nested_vmx_allowed(vcpu)) 2106 return 1; 2107 return vmx_set_vmx_msr(vcpu, msr_index, data); 2108 case MSR_IA32_RTIT_CTL: 2109 if (!vmx_pt_mode_is_host_guest() || 2110 vmx_rtit_ctl_check(vcpu, data) || 2111 vmx->nested.vmxon) 2112 return 1; 2113 vmcs_write64(GUEST_IA32_RTIT_CTL, data); 2114 vmx->pt_desc.guest.ctl = data; 2115 pt_update_intercept_for_msr(vmx); 2116 break; 2117 case MSR_IA32_RTIT_STATUS: 2118 if (!pt_can_write_msr(vmx)) 2119 return 1; 2120 if (data & MSR_IA32_RTIT_STATUS_MASK) 2121 return 1; 2122 vmx->pt_desc.guest.status = data; 2123 break; 2124 case MSR_IA32_RTIT_CR3_MATCH: 2125 if (!pt_can_write_msr(vmx)) 2126 return 1; 2127 if (!intel_pt_validate_cap(vmx->pt_desc.caps, 2128 PT_CAP_cr3_filtering)) 2129 return 1; 2130 vmx->pt_desc.guest.cr3_match = data; 2131 break; 2132 case MSR_IA32_RTIT_OUTPUT_BASE: 2133 if (!pt_can_write_msr(vmx)) 2134 return 1; 2135 if (!intel_pt_validate_cap(vmx->pt_desc.caps, 2136 PT_CAP_topa_output) && 2137 !intel_pt_validate_cap(vmx->pt_desc.caps, 2138 PT_CAP_single_range_output)) 2139 return 1; 2140 if (data & MSR_IA32_RTIT_OUTPUT_BASE_MASK) 2141 return 1; 2142 vmx->pt_desc.guest.output_base = data; 2143 break; 2144 case MSR_IA32_RTIT_OUTPUT_MASK: 2145 if (!pt_can_write_msr(vmx)) 2146 return 1; 2147 if (!intel_pt_validate_cap(vmx->pt_desc.caps, 2148 PT_CAP_topa_output) && 2149 !intel_pt_validate_cap(vmx->pt_desc.caps, 2150 PT_CAP_single_range_output)) 2151 return 1; 2152 vmx->pt_desc.guest.output_mask = data; 2153 break; 2154 case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B: 2155 if (!pt_can_write_msr(vmx)) 2156 return 1; 2157 index = msr_info->index - MSR_IA32_RTIT_ADDR0_A; 2158 if (index >= 2 * intel_pt_validate_cap(vmx->pt_desc.caps, 2159 PT_CAP_num_address_ranges)) 2160 return 1; 2161 if (is_noncanonical_address(data, vcpu)) 2162 return 1; 2163 if (index % 2) 2164 vmx->pt_desc.guest.addr_b[index / 2] = data; 2165 else 2166 vmx->pt_desc.guest.addr_a[index / 2] = data; 2167 break; 2168 case MSR_TSC_AUX: 2169 if (!msr_info->host_initiated && 2170 !guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP)) 2171 return 1; 2172 /* Check reserved bit, higher 32 bits should be zero */ 2173 if ((data >> 32) != 0) 2174 return 1; 2175 goto find_shared_msr; 2176 2177 default: 2178 find_shared_msr: 2179 msr = find_msr_entry(vmx, msr_index); 2180 if (msr) 2181 ret = vmx_set_guest_msr(vmx, msr, data); 2182 else 2183 ret = kvm_set_msr_common(vcpu, msr_info); 2184 } 2185 2186 return ret; 2187 } 2188 2189 static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg) 2190 { 2191 kvm_register_mark_available(vcpu, reg); 2192 2193 switch (reg) { 2194 case VCPU_REGS_RSP: 2195 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP); 2196 break; 2197 case VCPU_REGS_RIP: 2198 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP); 2199 break; 2200 case VCPU_EXREG_PDPTR: 2201 if (enable_ept) 2202 ept_save_pdptrs(vcpu); 2203 break; 2204 case VCPU_EXREG_CR3: 2205 if (enable_unrestricted_guest || (enable_ept && is_paging(vcpu))) 2206 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3); 2207 break; 2208 default: 2209 WARN_ON_ONCE(1); 2210 break; 2211 } 2212 } 2213 2214 static __init int cpu_has_kvm_support(void) 2215 { 2216 return cpu_has_vmx(); 2217 } 2218 2219 static __init int vmx_disabled_by_bios(void) 2220 { 2221 return !boot_cpu_has(X86_FEATURE_MSR_IA32_FEAT_CTL) || 2222 !boot_cpu_has(X86_FEATURE_VMX); 2223 } 2224 2225 static int kvm_cpu_vmxon(u64 vmxon_pointer) 2226 { 2227 u64 msr; 2228 2229 cr4_set_bits(X86_CR4_VMXE); 2230 intel_pt_handle_vmx(1); 2231 2232 asm_volatile_goto("1: vmxon %[vmxon_pointer]\n\t" 2233 _ASM_EXTABLE(1b, %l[fault]) 2234 : : [vmxon_pointer] "m"(vmxon_pointer) 2235 : : fault); 2236 return 0; 2237 2238 fault: 2239 WARN_ONCE(1, "VMXON faulted, MSR_IA32_FEAT_CTL (0x3a) = 0x%llx\n", 2240 rdmsrl_safe(MSR_IA32_FEAT_CTL, &msr) ? 0xdeadbeef : msr); 2241 intel_pt_handle_vmx(0); 2242 cr4_clear_bits(X86_CR4_VMXE); 2243 2244 return -EFAULT; 2245 } 2246 2247 static int hardware_enable(void) 2248 { 2249 int cpu = raw_smp_processor_id(); 2250 u64 phys_addr = __pa(per_cpu(vmxarea, cpu)); 2251 int r; 2252 2253 if (cr4_read_shadow() & X86_CR4_VMXE) 2254 return -EBUSY; 2255 2256 /* 2257 * This can happen if we hot-added a CPU but failed to allocate 2258 * VP assist page for it. 2259 */ 2260 if (static_branch_unlikely(&enable_evmcs) && 2261 !hv_get_vp_assist_page(cpu)) 2262 return -EFAULT; 2263 2264 INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu)); 2265 INIT_LIST_HEAD(&per_cpu(blocked_vcpu_on_cpu, cpu)); 2266 spin_lock_init(&per_cpu(blocked_vcpu_on_cpu_lock, cpu)); 2267 2268 r = kvm_cpu_vmxon(phys_addr); 2269 if (r) 2270 return r; 2271 2272 if (enable_ept) 2273 ept_sync_global(); 2274 2275 return 0; 2276 } 2277 2278 static void vmclear_local_loaded_vmcss(void) 2279 { 2280 int cpu = raw_smp_processor_id(); 2281 struct loaded_vmcs *v, *n; 2282 2283 list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu), 2284 loaded_vmcss_on_cpu_link) 2285 __loaded_vmcs_clear(v); 2286 } 2287 2288 2289 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot() 2290 * tricks. 2291 */ 2292 static void kvm_cpu_vmxoff(void) 2293 { 2294 asm volatile (__ex("vmxoff")); 2295 2296 intel_pt_handle_vmx(0); 2297 cr4_clear_bits(X86_CR4_VMXE); 2298 } 2299 2300 static void hardware_disable(void) 2301 { 2302 vmclear_local_loaded_vmcss(); 2303 kvm_cpu_vmxoff(); 2304 } 2305 2306 /* 2307 * There is no X86_FEATURE for SGX yet, but anyway we need to query CPUID 2308 * directly instead of going through cpu_has(), to ensure KVM is trapping 2309 * ENCLS whenever it's supported in hardware. It does not matter whether 2310 * the host OS supports or has enabled SGX. 2311 */ 2312 static bool cpu_has_sgx(void) 2313 { 2314 return cpuid_eax(0) >= 0x12 && (cpuid_eax(0x12) & BIT(0)); 2315 } 2316 2317 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt, 2318 u32 msr, u32 *result) 2319 { 2320 u32 vmx_msr_low, vmx_msr_high; 2321 u32 ctl = ctl_min | ctl_opt; 2322 2323 rdmsr(msr, vmx_msr_low, vmx_msr_high); 2324 2325 ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */ 2326 ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */ 2327 2328 /* Ensure minimum (required) set of control bits are supported. */ 2329 if (ctl_min & ~ctl) 2330 return -EIO; 2331 2332 *result = ctl; 2333 return 0; 2334 } 2335 2336 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf, 2337 struct vmx_capability *vmx_cap) 2338 { 2339 u32 vmx_msr_low, vmx_msr_high; 2340 u32 min, opt, min2, opt2; 2341 u32 _pin_based_exec_control = 0; 2342 u32 _cpu_based_exec_control = 0; 2343 u32 _cpu_based_2nd_exec_control = 0; 2344 u32 _vmexit_control = 0; 2345 u32 _vmentry_control = 0; 2346 2347 memset(vmcs_conf, 0, sizeof(*vmcs_conf)); 2348 min = CPU_BASED_HLT_EXITING | 2349 #ifdef CONFIG_X86_64 2350 CPU_BASED_CR8_LOAD_EXITING | 2351 CPU_BASED_CR8_STORE_EXITING | 2352 #endif 2353 CPU_BASED_CR3_LOAD_EXITING | 2354 CPU_BASED_CR3_STORE_EXITING | 2355 CPU_BASED_UNCOND_IO_EXITING | 2356 CPU_BASED_MOV_DR_EXITING | 2357 CPU_BASED_USE_TSC_OFFSETTING | 2358 CPU_BASED_MWAIT_EXITING | 2359 CPU_BASED_MONITOR_EXITING | 2360 CPU_BASED_INVLPG_EXITING | 2361 CPU_BASED_RDPMC_EXITING; 2362 2363 opt = CPU_BASED_TPR_SHADOW | 2364 CPU_BASED_USE_MSR_BITMAPS | 2365 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS; 2366 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS, 2367 &_cpu_based_exec_control) < 0) 2368 return -EIO; 2369 #ifdef CONFIG_X86_64 2370 if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW)) 2371 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING & 2372 ~CPU_BASED_CR8_STORE_EXITING; 2373 #endif 2374 if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) { 2375 min2 = 0; 2376 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 2377 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 2378 SECONDARY_EXEC_WBINVD_EXITING | 2379 SECONDARY_EXEC_ENABLE_VPID | 2380 SECONDARY_EXEC_ENABLE_EPT | 2381 SECONDARY_EXEC_UNRESTRICTED_GUEST | 2382 SECONDARY_EXEC_PAUSE_LOOP_EXITING | 2383 SECONDARY_EXEC_DESC | 2384 SECONDARY_EXEC_RDTSCP | 2385 SECONDARY_EXEC_ENABLE_INVPCID | 2386 SECONDARY_EXEC_APIC_REGISTER_VIRT | 2387 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 2388 SECONDARY_EXEC_SHADOW_VMCS | 2389 SECONDARY_EXEC_XSAVES | 2390 SECONDARY_EXEC_RDSEED_EXITING | 2391 SECONDARY_EXEC_RDRAND_EXITING | 2392 SECONDARY_EXEC_ENABLE_PML | 2393 SECONDARY_EXEC_TSC_SCALING | 2394 SECONDARY_EXEC_ENABLE_USR_WAIT_PAUSE | 2395 SECONDARY_EXEC_PT_USE_GPA | 2396 SECONDARY_EXEC_PT_CONCEAL_VMX | 2397 SECONDARY_EXEC_ENABLE_VMFUNC; 2398 if (cpu_has_sgx()) 2399 opt2 |= SECONDARY_EXEC_ENCLS_EXITING; 2400 if (adjust_vmx_controls(min2, opt2, 2401 MSR_IA32_VMX_PROCBASED_CTLS2, 2402 &_cpu_based_2nd_exec_control) < 0) 2403 return -EIO; 2404 } 2405 #ifndef CONFIG_X86_64 2406 if (!(_cpu_based_2nd_exec_control & 2407 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) 2408 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW; 2409 #endif 2410 2411 if (!(_cpu_based_exec_control & CPU_BASED_TPR_SHADOW)) 2412 _cpu_based_2nd_exec_control &= ~( 2413 SECONDARY_EXEC_APIC_REGISTER_VIRT | 2414 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 2415 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY); 2416 2417 rdmsr_safe(MSR_IA32_VMX_EPT_VPID_CAP, 2418 &vmx_cap->ept, &vmx_cap->vpid); 2419 2420 if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) { 2421 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT 2422 enabled */ 2423 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING | 2424 CPU_BASED_CR3_STORE_EXITING | 2425 CPU_BASED_INVLPG_EXITING); 2426 } else if (vmx_cap->ept) { 2427 vmx_cap->ept = 0; 2428 pr_warn_once("EPT CAP should not exist if not support " 2429 "1-setting enable EPT VM-execution control\n"); 2430 } 2431 if (!(_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_VPID) && 2432 vmx_cap->vpid) { 2433 vmx_cap->vpid = 0; 2434 pr_warn_once("VPID CAP should not exist if not support " 2435 "1-setting enable VPID VM-execution control\n"); 2436 } 2437 2438 min = VM_EXIT_SAVE_DEBUG_CONTROLS | VM_EXIT_ACK_INTR_ON_EXIT; 2439 #ifdef CONFIG_X86_64 2440 min |= VM_EXIT_HOST_ADDR_SPACE_SIZE; 2441 #endif 2442 opt = VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 2443 VM_EXIT_LOAD_IA32_PAT | 2444 VM_EXIT_LOAD_IA32_EFER | 2445 VM_EXIT_CLEAR_BNDCFGS | 2446 VM_EXIT_PT_CONCEAL_PIP | 2447 VM_EXIT_CLEAR_IA32_RTIT_CTL; 2448 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS, 2449 &_vmexit_control) < 0) 2450 return -EIO; 2451 2452 min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING; 2453 opt = PIN_BASED_VIRTUAL_NMIS | PIN_BASED_POSTED_INTR | 2454 PIN_BASED_VMX_PREEMPTION_TIMER; 2455 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS, 2456 &_pin_based_exec_control) < 0) 2457 return -EIO; 2458 2459 if (cpu_has_broken_vmx_preemption_timer()) 2460 _pin_based_exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER; 2461 if (!(_cpu_based_2nd_exec_control & 2462 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY)) 2463 _pin_based_exec_control &= ~PIN_BASED_POSTED_INTR; 2464 2465 min = VM_ENTRY_LOAD_DEBUG_CONTROLS; 2466 opt = VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | 2467 VM_ENTRY_LOAD_IA32_PAT | 2468 VM_ENTRY_LOAD_IA32_EFER | 2469 VM_ENTRY_LOAD_BNDCFGS | 2470 VM_ENTRY_PT_CONCEAL_PIP | 2471 VM_ENTRY_LOAD_IA32_RTIT_CTL; 2472 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS, 2473 &_vmentry_control) < 0) 2474 return -EIO; 2475 2476 /* 2477 * Some cpus support VM_{ENTRY,EXIT}_IA32_PERF_GLOBAL_CTRL but they 2478 * can't be used due to an errata where VM Exit may incorrectly clear 2479 * IA32_PERF_GLOBAL_CTRL[34:32]. Workaround the errata by using the 2480 * MSR load mechanism to switch IA32_PERF_GLOBAL_CTRL. 2481 */ 2482 if (boot_cpu_data.x86 == 0x6) { 2483 switch (boot_cpu_data.x86_model) { 2484 case 26: /* AAK155 */ 2485 case 30: /* AAP115 */ 2486 case 37: /* AAT100 */ 2487 case 44: /* BC86,AAY89,BD102 */ 2488 case 46: /* BA97 */ 2489 _vmentry_control &= ~VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL; 2490 _vmexit_control &= ~VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL; 2491 pr_warn_once("kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL " 2492 "does not work properly. Using workaround\n"); 2493 break; 2494 default: 2495 break; 2496 } 2497 } 2498 2499 2500 rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high); 2501 2502 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */ 2503 if ((vmx_msr_high & 0x1fff) > PAGE_SIZE) 2504 return -EIO; 2505 2506 #ifdef CONFIG_X86_64 2507 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */ 2508 if (vmx_msr_high & (1u<<16)) 2509 return -EIO; 2510 #endif 2511 2512 /* Require Write-Back (WB) memory type for VMCS accesses. */ 2513 if (((vmx_msr_high >> 18) & 15) != 6) 2514 return -EIO; 2515 2516 vmcs_conf->size = vmx_msr_high & 0x1fff; 2517 vmcs_conf->order = get_order(vmcs_conf->size); 2518 vmcs_conf->basic_cap = vmx_msr_high & ~0x1fff; 2519 2520 vmcs_conf->revision_id = vmx_msr_low; 2521 2522 vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control; 2523 vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control; 2524 vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control; 2525 vmcs_conf->vmexit_ctrl = _vmexit_control; 2526 vmcs_conf->vmentry_ctrl = _vmentry_control; 2527 2528 if (static_branch_unlikely(&enable_evmcs)) 2529 evmcs_sanitize_exec_ctrls(vmcs_conf); 2530 2531 return 0; 2532 } 2533 2534 struct vmcs *alloc_vmcs_cpu(bool shadow, int cpu, gfp_t flags) 2535 { 2536 int node = cpu_to_node(cpu); 2537 struct page *pages; 2538 struct vmcs *vmcs; 2539 2540 pages = __alloc_pages_node(node, flags, vmcs_config.order); 2541 if (!pages) 2542 return NULL; 2543 vmcs = page_address(pages); 2544 memset(vmcs, 0, vmcs_config.size); 2545 2546 /* KVM supports Enlightened VMCS v1 only */ 2547 if (static_branch_unlikely(&enable_evmcs)) 2548 vmcs->hdr.revision_id = KVM_EVMCS_VERSION; 2549 else 2550 vmcs->hdr.revision_id = vmcs_config.revision_id; 2551 2552 if (shadow) 2553 vmcs->hdr.shadow_vmcs = 1; 2554 return vmcs; 2555 } 2556 2557 void free_vmcs(struct vmcs *vmcs) 2558 { 2559 free_pages((unsigned long)vmcs, vmcs_config.order); 2560 } 2561 2562 /* 2563 * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded 2564 */ 2565 void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs) 2566 { 2567 if (!loaded_vmcs->vmcs) 2568 return; 2569 loaded_vmcs_clear(loaded_vmcs); 2570 free_vmcs(loaded_vmcs->vmcs); 2571 loaded_vmcs->vmcs = NULL; 2572 if (loaded_vmcs->msr_bitmap) 2573 free_page((unsigned long)loaded_vmcs->msr_bitmap); 2574 WARN_ON(loaded_vmcs->shadow_vmcs != NULL); 2575 } 2576 2577 int alloc_loaded_vmcs(struct loaded_vmcs *loaded_vmcs) 2578 { 2579 loaded_vmcs->vmcs = alloc_vmcs(false); 2580 if (!loaded_vmcs->vmcs) 2581 return -ENOMEM; 2582 2583 vmcs_clear(loaded_vmcs->vmcs); 2584 2585 loaded_vmcs->shadow_vmcs = NULL; 2586 loaded_vmcs->hv_timer_soft_disabled = false; 2587 loaded_vmcs->cpu = -1; 2588 loaded_vmcs->launched = 0; 2589 2590 if (cpu_has_vmx_msr_bitmap()) { 2591 loaded_vmcs->msr_bitmap = (unsigned long *) 2592 __get_free_page(GFP_KERNEL_ACCOUNT); 2593 if (!loaded_vmcs->msr_bitmap) 2594 goto out_vmcs; 2595 memset(loaded_vmcs->msr_bitmap, 0xff, PAGE_SIZE); 2596 2597 if (IS_ENABLED(CONFIG_HYPERV) && 2598 static_branch_unlikely(&enable_evmcs) && 2599 (ms_hyperv.nested_features & HV_X64_NESTED_MSR_BITMAP)) { 2600 struct hv_enlightened_vmcs *evmcs = 2601 (struct hv_enlightened_vmcs *)loaded_vmcs->vmcs; 2602 2603 evmcs->hv_enlightenments_control.msr_bitmap = 1; 2604 } 2605 } 2606 2607 memset(&loaded_vmcs->host_state, 0, sizeof(struct vmcs_host_state)); 2608 memset(&loaded_vmcs->controls_shadow, 0, 2609 sizeof(struct vmcs_controls_shadow)); 2610 2611 return 0; 2612 2613 out_vmcs: 2614 free_loaded_vmcs(loaded_vmcs); 2615 return -ENOMEM; 2616 } 2617 2618 static void free_kvm_area(void) 2619 { 2620 int cpu; 2621 2622 for_each_possible_cpu(cpu) { 2623 free_vmcs(per_cpu(vmxarea, cpu)); 2624 per_cpu(vmxarea, cpu) = NULL; 2625 } 2626 } 2627 2628 static __init int alloc_kvm_area(void) 2629 { 2630 int cpu; 2631 2632 for_each_possible_cpu(cpu) { 2633 struct vmcs *vmcs; 2634 2635 vmcs = alloc_vmcs_cpu(false, cpu, GFP_KERNEL); 2636 if (!vmcs) { 2637 free_kvm_area(); 2638 return -ENOMEM; 2639 } 2640 2641 /* 2642 * When eVMCS is enabled, alloc_vmcs_cpu() sets 2643 * vmcs->revision_id to KVM_EVMCS_VERSION instead of 2644 * revision_id reported by MSR_IA32_VMX_BASIC. 2645 * 2646 * However, even though not explicitly documented by 2647 * TLFS, VMXArea passed as VMXON argument should 2648 * still be marked with revision_id reported by 2649 * physical CPU. 2650 */ 2651 if (static_branch_unlikely(&enable_evmcs)) 2652 vmcs->hdr.revision_id = vmcs_config.revision_id; 2653 2654 per_cpu(vmxarea, cpu) = vmcs; 2655 } 2656 return 0; 2657 } 2658 2659 static void fix_pmode_seg(struct kvm_vcpu *vcpu, int seg, 2660 struct kvm_segment *save) 2661 { 2662 if (!emulate_invalid_guest_state) { 2663 /* 2664 * CS and SS RPL should be equal during guest entry according 2665 * to VMX spec, but in reality it is not always so. Since vcpu 2666 * is in the middle of the transition from real mode to 2667 * protected mode it is safe to assume that RPL 0 is a good 2668 * default value. 2669 */ 2670 if (seg == VCPU_SREG_CS || seg == VCPU_SREG_SS) 2671 save->selector &= ~SEGMENT_RPL_MASK; 2672 save->dpl = save->selector & SEGMENT_RPL_MASK; 2673 save->s = 1; 2674 } 2675 vmx_set_segment(vcpu, save, seg); 2676 } 2677 2678 static void enter_pmode(struct kvm_vcpu *vcpu) 2679 { 2680 unsigned long flags; 2681 struct vcpu_vmx *vmx = to_vmx(vcpu); 2682 2683 /* 2684 * Update real mode segment cache. It may be not up-to-date if sement 2685 * register was written while vcpu was in a guest mode. 2686 */ 2687 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES); 2688 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS); 2689 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS); 2690 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS); 2691 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS); 2692 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS); 2693 2694 vmx->rmode.vm86_active = 0; 2695 2696 vmx_set_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR); 2697 2698 flags = vmcs_readl(GUEST_RFLAGS); 2699 flags &= RMODE_GUEST_OWNED_EFLAGS_BITS; 2700 flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS; 2701 vmcs_writel(GUEST_RFLAGS, flags); 2702 2703 vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) | 2704 (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME)); 2705 2706 update_exception_bitmap(vcpu); 2707 2708 fix_pmode_seg(vcpu, VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]); 2709 fix_pmode_seg(vcpu, VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]); 2710 fix_pmode_seg(vcpu, VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]); 2711 fix_pmode_seg(vcpu, VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]); 2712 fix_pmode_seg(vcpu, VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]); 2713 fix_pmode_seg(vcpu, VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]); 2714 } 2715 2716 static void fix_rmode_seg(int seg, struct kvm_segment *save) 2717 { 2718 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg]; 2719 struct kvm_segment var = *save; 2720 2721 var.dpl = 0x3; 2722 if (seg == VCPU_SREG_CS) 2723 var.type = 0x3; 2724 2725 if (!emulate_invalid_guest_state) { 2726 var.selector = var.base >> 4; 2727 var.base = var.base & 0xffff0; 2728 var.limit = 0xffff; 2729 var.g = 0; 2730 var.db = 0; 2731 var.present = 1; 2732 var.s = 1; 2733 var.l = 0; 2734 var.unusable = 0; 2735 var.type = 0x3; 2736 var.avl = 0; 2737 if (save->base & 0xf) 2738 printk_once(KERN_WARNING "kvm: segment base is not " 2739 "paragraph aligned when entering " 2740 "protected mode (seg=%d)", seg); 2741 } 2742 2743 vmcs_write16(sf->selector, var.selector); 2744 vmcs_writel(sf->base, var.base); 2745 vmcs_write32(sf->limit, var.limit); 2746 vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(&var)); 2747 } 2748 2749 static void enter_rmode(struct kvm_vcpu *vcpu) 2750 { 2751 unsigned long flags; 2752 struct vcpu_vmx *vmx = to_vmx(vcpu); 2753 struct kvm_vmx *kvm_vmx = to_kvm_vmx(vcpu->kvm); 2754 2755 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR); 2756 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES); 2757 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS); 2758 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS); 2759 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS); 2760 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS); 2761 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS); 2762 2763 vmx->rmode.vm86_active = 1; 2764 2765 /* 2766 * Very old userspace does not call KVM_SET_TSS_ADDR before entering 2767 * vcpu. Warn the user that an update is overdue. 2768 */ 2769 if (!kvm_vmx->tss_addr) 2770 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be " 2771 "called before entering vcpu\n"); 2772 2773 vmx_segment_cache_clear(vmx); 2774 2775 vmcs_writel(GUEST_TR_BASE, kvm_vmx->tss_addr); 2776 vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1); 2777 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b); 2778 2779 flags = vmcs_readl(GUEST_RFLAGS); 2780 vmx->rmode.save_rflags = flags; 2781 2782 flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM; 2783 2784 vmcs_writel(GUEST_RFLAGS, flags); 2785 vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME); 2786 update_exception_bitmap(vcpu); 2787 2788 fix_rmode_seg(VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]); 2789 fix_rmode_seg(VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]); 2790 fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]); 2791 fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]); 2792 fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]); 2793 fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]); 2794 2795 kvm_mmu_reset_context(vcpu); 2796 } 2797 2798 void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer) 2799 { 2800 struct vcpu_vmx *vmx = to_vmx(vcpu); 2801 struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER); 2802 2803 if (!msr) 2804 return; 2805 2806 vcpu->arch.efer = efer; 2807 if (efer & EFER_LMA) { 2808 vm_entry_controls_setbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE); 2809 msr->data = efer; 2810 } else { 2811 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE); 2812 2813 msr->data = efer & ~EFER_LME; 2814 } 2815 setup_msrs(vmx); 2816 } 2817 2818 #ifdef CONFIG_X86_64 2819 2820 static void enter_lmode(struct kvm_vcpu *vcpu) 2821 { 2822 u32 guest_tr_ar; 2823 2824 vmx_segment_cache_clear(to_vmx(vcpu)); 2825 2826 guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES); 2827 if ((guest_tr_ar & VMX_AR_TYPE_MASK) != VMX_AR_TYPE_BUSY_64_TSS) { 2828 pr_debug_ratelimited("%s: tss fixup for long mode. \n", 2829 __func__); 2830 vmcs_write32(GUEST_TR_AR_BYTES, 2831 (guest_tr_ar & ~VMX_AR_TYPE_MASK) 2832 | VMX_AR_TYPE_BUSY_64_TSS); 2833 } 2834 vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA); 2835 } 2836 2837 static void exit_lmode(struct kvm_vcpu *vcpu) 2838 { 2839 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE); 2840 vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA); 2841 } 2842 2843 #endif 2844 2845 static void vmx_flush_tlb_gva(struct kvm_vcpu *vcpu, gva_t addr) 2846 { 2847 int vpid = to_vmx(vcpu)->vpid; 2848 2849 if (!vpid_sync_vcpu_addr(vpid, addr)) 2850 vpid_sync_context(vpid); 2851 2852 /* 2853 * If VPIDs are not supported or enabled, then the above is a no-op. 2854 * But we don't really need a TLB flush in that case anyway, because 2855 * each VM entry/exit includes an implicit flush when VPID is 0. 2856 */ 2857 } 2858 2859 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu) 2860 { 2861 ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits; 2862 2863 vcpu->arch.cr0 &= ~cr0_guest_owned_bits; 2864 vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits; 2865 } 2866 2867 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu) 2868 { 2869 ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits; 2870 2871 vcpu->arch.cr4 &= ~cr4_guest_owned_bits; 2872 vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits; 2873 } 2874 2875 static void ept_load_pdptrs(struct kvm_vcpu *vcpu) 2876 { 2877 struct kvm_mmu *mmu = vcpu->arch.walk_mmu; 2878 2879 if (!kvm_register_is_dirty(vcpu, VCPU_EXREG_PDPTR)) 2880 return; 2881 2882 if (is_pae_paging(vcpu)) { 2883 vmcs_write64(GUEST_PDPTR0, mmu->pdptrs[0]); 2884 vmcs_write64(GUEST_PDPTR1, mmu->pdptrs[1]); 2885 vmcs_write64(GUEST_PDPTR2, mmu->pdptrs[2]); 2886 vmcs_write64(GUEST_PDPTR3, mmu->pdptrs[3]); 2887 } 2888 } 2889 2890 void ept_save_pdptrs(struct kvm_vcpu *vcpu) 2891 { 2892 struct kvm_mmu *mmu = vcpu->arch.walk_mmu; 2893 2894 if (is_pae_paging(vcpu)) { 2895 mmu->pdptrs[0] = vmcs_read64(GUEST_PDPTR0); 2896 mmu->pdptrs[1] = vmcs_read64(GUEST_PDPTR1); 2897 mmu->pdptrs[2] = vmcs_read64(GUEST_PDPTR2); 2898 mmu->pdptrs[3] = vmcs_read64(GUEST_PDPTR3); 2899 } 2900 2901 kvm_register_mark_dirty(vcpu, VCPU_EXREG_PDPTR); 2902 } 2903 2904 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0, 2905 unsigned long cr0, 2906 struct kvm_vcpu *vcpu) 2907 { 2908 struct vcpu_vmx *vmx = to_vmx(vcpu); 2909 2910 if (!kvm_register_is_available(vcpu, VCPU_EXREG_CR3)) 2911 vmx_cache_reg(vcpu, VCPU_EXREG_CR3); 2912 if (!(cr0 & X86_CR0_PG)) { 2913 /* From paging/starting to nonpaging */ 2914 exec_controls_setbit(vmx, CPU_BASED_CR3_LOAD_EXITING | 2915 CPU_BASED_CR3_STORE_EXITING); 2916 vcpu->arch.cr0 = cr0; 2917 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu)); 2918 } else if (!is_paging(vcpu)) { 2919 /* From nonpaging to paging */ 2920 exec_controls_clearbit(vmx, CPU_BASED_CR3_LOAD_EXITING | 2921 CPU_BASED_CR3_STORE_EXITING); 2922 vcpu->arch.cr0 = cr0; 2923 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu)); 2924 } 2925 2926 if (!(cr0 & X86_CR0_WP)) 2927 *hw_cr0 &= ~X86_CR0_WP; 2928 } 2929 2930 void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0) 2931 { 2932 struct vcpu_vmx *vmx = to_vmx(vcpu); 2933 unsigned long hw_cr0; 2934 2935 hw_cr0 = (cr0 & ~KVM_VM_CR0_ALWAYS_OFF); 2936 if (enable_unrestricted_guest) 2937 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST; 2938 else { 2939 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON; 2940 2941 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE)) 2942 enter_pmode(vcpu); 2943 2944 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE)) 2945 enter_rmode(vcpu); 2946 } 2947 2948 #ifdef CONFIG_X86_64 2949 if (vcpu->arch.efer & EFER_LME) { 2950 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) 2951 enter_lmode(vcpu); 2952 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) 2953 exit_lmode(vcpu); 2954 } 2955 #endif 2956 2957 if (enable_ept && !enable_unrestricted_guest) 2958 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu); 2959 2960 vmcs_writel(CR0_READ_SHADOW, cr0); 2961 vmcs_writel(GUEST_CR0, hw_cr0); 2962 vcpu->arch.cr0 = cr0; 2963 2964 /* depends on vcpu->arch.cr0 to be set to a new value */ 2965 vmx->emulation_required = emulation_required(vcpu); 2966 } 2967 2968 static int get_ept_level(struct kvm_vcpu *vcpu) 2969 { 2970 if (is_guest_mode(vcpu) && nested_cpu_has_ept(get_vmcs12(vcpu))) 2971 return vmx_eptp_page_walk_level(nested_ept_get_eptp(vcpu)); 2972 if (cpu_has_vmx_ept_5levels() && (cpuid_maxphyaddr(vcpu) > 48)) 2973 return 5; 2974 return 4; 2975 } 2976 2977 u64 construct_eptp(struct kvm_vcpu *vcpu, unsigned long root_hpa) 2978 { 2979 u64 eptp = VMX_EPTP_MT_WB; 2980 2981 eptp |= (get_ept_level(vcpu) == 5) ? VMX_EPTP_PWL_5 : VMX_EPTP_PWL_4; 2982 2983 if (enable_ept_ad_bits && 2984 (!is_guest_mode(vcpu) || nested_ept_ad_enabled(vcpu))) 2985 eptp |= VMX_EPTP_AD_ENABLE_BIT; 2986 eptp |= (root_hpa & PAGE_MASK); 2987 2988 return eptp; 2989 } 2990 2991 void vmx_load_mmu_pgd(struct kvm_vcpu *vcpu, unsigned long cr3) 2992 { 2993 struct kvm *kvm = vcpu->kvm; 2994 bool update_guest_cr3 = true; 2995 unsigned long guest_cr3; 2996 u64 eptp; 2997 2998 guest_cr3 = cr3; 2999 if (enable_ept) { 3000 eptp = construct_eptp(vcpu, cr3); 3001 vmcs_write64(EPT_POINTER, eptp); 3002 3003 if (kvm_x86_ops.tlb_remote_flush) { 3004 spin_lock(&to_kvm_vmx(kvm)->ept_pointer_lock); 3005 to_vmx(vcpu)->ept_pointer = eptp; 3006 to_kvm_vmx(kvm)->ept_pointers_match 3007 = EPT_POINTERS_CHECK; 3008 spin_unlock(&to_kvm_vmx(kvm)->ept_pointer_lock); 3009 } 3010 3011 /* Loading vmcs02.GUEST_CR3 is handled by nested VM-Enter. */ 3012 if (is_guest_mode(vcpu)) 3013 update_guest_cr3 = false; 3014 else if (!enable_unrestricted_guest && !is_paging(vcpu)) 3015 guest_cr3 = to_kvm_vmx(kvm)->ept_identity_map_addr; 3016 else if (test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail)) 3017 guest_cr3 = vcpu->arch.cr3; 3018 else /* vmcs01.GUEST_CR3 is already up-to-date. */ 3019 update_guest_cr3 = false; 3020 ept_load_pdptrs(vcpu); 3021 } 3022 3023 if (update_guest_cr3) 3024 vmcs_writel(GUEST_CR3, guest_cr3); 3025 } 3026 3027 int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4) 3028 { 3029 struct vcpu_vmx *vmx = to_vmx(vcpu); 3030 /* 3031 * Pass through host's Machine Check Enable value to hw_cr4, which 3032 * is in force while we are in guest mode. Do not let guests control 3033 * this bit, even if host CR4.MCE == 0. 3034 */ 3035 unsigned long hw_cr4; 3036 3037 hw_cr4 = (cr4_read_shadow() & X86_CR4_MCE) | (cr4 & ~X86_CR4_MCE); 3038 if (enable_unrestricted_guest) 3039 hw_cr4 |= KVM_VM_CR4_ALWAYS_ON_UNRESTRICTED_GUEST; 3040 else if (vmx->rmode.vm86_active) 3041 hw_cr4 |= KVM_RMODE_VM_CR4_ALWAYS_ON; 3042 else 3043 hw_cr4 |= KVM_PMODE_VM_CR4_ALWAYS_ON; 3044 3045 if (!boot_cpu_has(X86_FEATURE_UMIP) && vmx_umip_emulated()) { 3046 if (cr4 & X86_CR4_UMIP) { 3047 secondary_exec_controls_setbit(vmx, SECONDARY_EXEC_DESC); 3048 hw_cr4 &= ~X86_CR4_UMIP; 3049 } else if (!is_guest_mode(vcpu) || 3050 !nested_cpu_has2(get_vmcs12(vcpu), SECONDARY_EXEC_DESC)) { 3051 secondary_exec_controls_clearbit(vmx, SECONDARY_EXEC_DESC); 3052 } 3053 } 3054 3055 if (cr4 & X86_CR4_VMXE) { 3056 /* 3057 * To use VMXON (and later other VMX instructions), a guest 3058 * must first be able to turn on cr4.VMXE (see handle_vmon()). 3059 * So basically the check on whether to allow nested VMX 3060 * is here. We operate under the default treatment of SMM, 3061 * so VMX cannot be enabled under SMM. 3062 */ 3063 if (!nested_vmx_allowed(vcpu) || is_smm(vcpu)) 3064 return 1; 3065 } 3066 3067 if (vmx->nested.vmxon && !nested_cr4_valid(vcpu, cr4)) 3068 return 1; 3069 3070 vcpu->arch.cr4 = cr4; 3071 3072 if (!enable_unrestricted_guest) { 3073 if (enable_ept) { 3074 if (!is_paging(vcpu)) { 3075 hw_cr4 &= ~X86_CR4_PAE; 3076 hw_cr4 |= X86_CR4_PSE; 3077 } else if (!(cr4 & X86_CR4_PAE)) { 3078 hw_cr4 &= ~X86_CR4_PAE; 3079 } 3080 } 3081 3082 /* 3083 * SMEP/SMAP/PKU is disabled if CPU is in non-paging mode in 3084 * hardware. To emulate this behavior, SMEP/SMAP/PKU needs 3085 * to be manually disabled when guest switches to non-paging 3086 * mode. 3087 * 3088 * If !enable_unrestricted_guest, the CPU is always running 3089 * with CR0.PG=1 and CR4 needs to be modified. 3090 * If enable_unrestricted_guest, the CPU automatically 3091 * disables SMEP/SMAP/PKU when the guest sets CR0.PG=0. 3092 */ 3093 if (!is_paging(vcpu)) 3094 hw_cr4 &= ~(X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE); 3095 } 3096 3097 vmcs_writel(CR4_READ_SHADOW, cr4); 3098 vmcs_writel(GUEST_CR4, hw_cr4); 3099 return 0; 3100 } 3101 3102 void vmx_get_segment(struct kvm_vcpu *vcpu, struct kvm_segment *var, int seg) 3103 { 3104 struct vcpu_vmx *vmx = to_vmx(vcpu); 3105 u32 ar; 3106 3107 if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) { 3108 *var = vmx->rmode.segs[seg]; 3109 if (seg == VCPU_SREG_TR 3110 || var->selector == vmx_read_guest_seg_selector(vmx, seg)) 3111 return; 3112 var->base = vmx_read_guest_seg_base(vmx, seg); 3113 var->selector = vmx_read_guest_seg_selector(vmx, seg); 3114 return; 3115 } 3116 var->base = vmx_read_guest_seg_base(vmx, seg); 3117 var->limit = vmx_read_guest_seg_limit(vmx, seg); 3118 var->selector = vmx_read_guest_seg_selector(vmx, seg); 3119 ar = vmx_read_guest_seg_ar(vmx, seg); 3120 var->unusable = (ar >> 16) & 1; 3121 var->type = ar & 15; 3122 var->s = (ar >> 4) & 1; 3123 var->dpl = (ar >> 5) & 3; 3124 /* 3125 * Some userspaces do not preserve unusable property. Since usable 3126 * segment has to be present according to VMX spec we can use present 3127 * property to amend userspace bug by making unusable segment always 3128 * nonpresent. vmx_segment_access_rights() already marks nonpresent 3129 * segment as unusable. 3130 */ 3131 var->present = !var->unusable; 3132 var->avl = (ar >> 12) & 1; 3133 var->l = (ar >> 13) & 1; 3134 var->db = (ar >> 14) & 1; 3135 var->g = (ar >> 15) & 1; 3136 } 3137 3138 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg) 3139 { 3140 struct kvm_segment s; 3141 3142 if (to_vmx(vcpu)->rmode.vm86_active) { 3143 vmx_get_segment(vcpu, &s, seg); 3144 return s.base; 3145 } 3146 return vmx_read_guest_seg_base(to_vmx(vcpu), seg); 3147 } 3148 3149 int vmx_get_cpl(struct kvm_vcpu *vcpu) 3150 { 3151 struct vcpu_vmx *vmx = to_vmx(vcpu); 3152 3153 if (unlikely(vmx->rmode.vm86_active)) 3154 return 0; 3155 else { 3156 int ar = vmx_read_guest_seg_ar(vmx, VCPU_SREG_SS); 3157 return VMX_AR_DPL(ar); 3158 } 3159 } 3160 3161 static u32 vmx_segment_access_rights(struct kvm_segment *var) 3162 { 3163 u32 ar; 3164 3165 if (var->unusable || !var->present) 3166 ar = 1 << 16; 3167 else { 3168 ar = var->type & 15; 3169 ar |= (var->s & 1) << 4; 3170 ar |= (var->dpl & 3) << 5; 3171 ar |= (var->present & 1) << 7; 3172 ar |= (var->avl & 1) << 12; 3173 ar |= (var->l & 1) << 13; 3174 ar |= (var->db & 1) << 14; 3175 ar |= (var->g & 1) << 15; 3176 } 3177 3178 return ar; 3179 } 3180 3181 void vmx_set_segment(struct kvm_vcpu *vcpu, struct kvm_segment *var, int seg) 3182 { 3183 struct vcpu_vmx *vmx = to_vmx(vcpu); 3184 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg]; 3185 3186 vmx_segment_cache_clear(vmx); 3187 3188 if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) { 3189 vmx->rmode.segs[seg] = *var; 3190 if (seg == VCPU_SREG_TR) 3191 vmcs_write16(sf->selector, var->selector); 3192 else if (var->s) 3193 fix_rmode_seg(seg, &vmx->rmode.segs[seg]); 3194 goto out; 3195 } 3196 3197 vmcs_writel(sf->base, var->base); 3198 vmcs_write32(sf->limit, var->limit); 3199 vmcs_write16(sf->selector, var->selector); 3200 3201 /* 3202 * Fix the "Accessed" bit in AR field of segment registers for older 3203 * qemu binaries. 3204 * IA32 arch specifies that at the time of processor reset the 3205 * "Accessed" bit in the AR field of segment registers is 1. And qemu 3206 * is setting it to 0 in the userland code. This causes invalid guest 3207 * state vmexit when "unrestricted guest" mode is turned on. 3208 * Fix for this setup issue in cpu_reset is being pushed in the qemu 3209 * tree. Newer qemu binaries with that qemu fix would not need this 3210 * kvm hack. 3211 */ 3212 if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR)) 3213 var->type |= 0x1; /* Accessed */ 3214 3215 vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(var)); 3216 3217 out: 3218 vmx->emulation_required = emulation_required(vcpu); 3219 } 3220 3221 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l) 3222 { 3223 u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS); 3224 3225 *db = (ar >> 14) & 1; 3226 *l = (ar >> 13) & 1; 3227 } 3228 3229 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt) 3230 { 3231 dt->size = vmcs_read32(GUEST_IDTR_LIMIT); 3232 dt->address = vmcs_readl(GUEST_IDTR_BASE); 3233 } 3234 3235 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt) 3236 { 3237 vmcs_write32(GUEST_IDTR_LIMIT, dt->size); 3238 vmcs_writel(GUEST_IDTR_BASE, dt->address); 3239 } 3240 3241 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt) 3242 { 3243 dt->size = vmcs_read32(GUEST_GDTR_LIMIT); 3244 dt->address = vmcs_readl(GUEST_GDTR_BASE); 3245 } 3246 3247 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt) 3248 { 3249 vmcs_write32(GUEST_GDTR_LIMIT, dt->size); 3250 vmcs_writel(GUEST_GDTR_BASE, dt->address); 3251 } 3252 3253 static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg) 3254 { 3255 struct kvm_segment var; 3256 u32 ar; 3257 3258 vmx_get_segment(vcpu, &var, seg); 3259 var.dpl = 0x3; 3260 if (seg == VCPU_SREG_CS) 3261 var.type = 0x3; 3262 ar = vmx_segment_access_rights(&var); 3263 3264 if (var.base != (var.selector << 4)) 3265 return false; 3266 if (var.limit != 0xffff) 3267 return false; 3268 if (ar != 0xf3) 3269 return false; 3270 3271 return true; 3272 } 3273 3274 static bool code_segment_valid(struct kvm_vcpu *vcpu) 3275 { 3276 struct kvm_segment cs; 3277 unsigned int cs_rpl; 3278 3279 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS); 3280 cs_rpl = cs.selector & SEGMENT_RPL_MASK; 3281 3282 if (cs.unusable) 3283 return false; 3284 if (~cs.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_ACCESSES_MASK)) 3285 return false; 3286 if (!cs.s) 3287 return false; 3288 if (cs.type & VMX_AR_TYPE_WRITEABLE_MASK) { 3289 if (cs.dpl > cs_rpl) 3290 return false; 3291 } else { 3292 if (cs.dpl != cs_rpl) 3293 return false; 3294 } 3295 if (!cs.present) 3296 return false; 3297 3298 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */ 3299 return true; 3300 } 3301 3302 static bool stack_segment_valid(struct kvm_vcpu *vcpu) 3303 { 3304 struct kvm_segment ss; 3305 unsigned int ss_rpl; 3306 3307 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS); 3308 ss_rpl = ss.selector & SEGMENT_RPL_MASK; 3309 3310 if (ss.unusable) 3311 return true; 3312 if (ss.type != 3 && ss.type != 7) 3313 return false; 3314 if (!ss.s) 3315 return false; 3316 if (ss.dpl != ss_rpl) /* DPL != RPL */ 3317 return false; 3318 if (!ss.present) 3319 return false; 3320 3321 return true; 3322 } 3323 3324 static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg) 3325 { 3326 struct kvm_segment var; 3327 unsigned int rpl; 3328 3329 vmx_get_segment(vcpu, &var, seg); 3330 rpl = var.selector & SEGMENT_RPL_MASK; 3331 3332 if (var.unusable) 3333 return true; 3334 if (!var.s) 3335 return false; 3336 if (!var.present) 3337 return false; 3338 if (~var.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_WRITEABLE_MASK)) { 3339 if (var.dpl < rpl) /* DPL < RPL */ 3340 return false; 3341 } 3342 3343 /* TODO: Add other members to kvm_segment_field to allow checking for other access 3344 * rights flags 3345 */ 3346 return true; 3347 } 3348 3349 static bool tr_valid(struct kvm_vcpu *vcpu) 3350 { 3351 struct kvm_segment tr; 3352 3353 vmx_get_segment(vcpu, &tr, VCPU_SREG_TR); 3354 3355 if (tr.unusable) 3356 return false; 3357 if (tr.selector & SEGMENT_TI_MASK) /* TI = 1 */ 3358 return false; 3359 if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */ 3360 return false; 3361 if (!tr.present) 3362 return false; 3363 3364 return true; 3365 } 3366 3367 static bool ldtr_valid(struct kvm_vcpu *vcpu) 3368 { 3369 struct kvm_segment ldtr; 3370 3371 vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR); 3372 3373 if (ldtr.unusable) 3374 return true; 3375 if (ldtr.selector & SEGMENT_TI_MASK) /* TI = 1 */ 3376 return false; 3377 if (ldtr.type != 2) 3378 return false; 3379 if (!ldtr.present) 3380 return false; 3381 3382 return true; 3383 } 3384 3385 static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu) 3386 { 3387 struct kvm_segment cs, ss; 3388 3389 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS); 3390 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS); 3391 3392 return ((cs.selector & SEGMENT_RPL_MASK) == 3393 (ss.selector & SEGMENT_RPL_MASK)); 3394 } 3395 3396 /* 3397 * Check if guest state is valid. Returns true if valid, false if 3398 * not. 3399 * We assume that registers are always usable 3400 */ 3401 static bool guest_state_valid(struct kvm_vcpu *vcpu) 3402 { 3403 if (enable_unrestricted_guest) 3404 return true; 3405 3406 /* real mode guest state checks */ 3407 if (!is_protmode(vcpu) || (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) { 3408 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS)) 3409 return false; 3410 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS)) 3411 return false; 3412 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS)) 3413 return false; 3414 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES)) 3415 return false; 3416 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS)) 3417 return false; 3418 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS)) 3419 return false; 3420 } else { 3421 /* protected mode guest state checks */ 3422 if (!cs_ss_rpl_check(vcpu)) 3423 return false; 3424 if (!code_segment_valid(vcpu)) 3425 return false; 3426 if (!stack_segment_valid(vcpu)) 3427 return false; 3428 if (!data_segment_valid(vcpu, VCPU_SREG_DS)) 3429 return false; 3430 if (!data_segment_valid(vcpu, VCPU_SREG_ES)) 3431 return false; 3432 if (!data_segment_valid(vcpu, VCPU_SREG_FS)) 3433 return false; 3434 if (!data_segment_valid(vcpu, VCPU_SREG_GS)) 3435 return false; 3436 if (!tr_valid(vcpu)) 3437 return false; 3438 if (!ldtr_valid(vcpu)) 3439 return false; 3440 } 3441 /* TODO: 3442 * - Add checks on RIP 3443 * - Add checks on RFLAGS 3444 */ 3445 3446 return true; 3447 } 3448 3449 static int init_rmode_tss(struct kvm *kvm) 3450 { 3451 gfn_t fn; 3452 u16 data = 0; 3453 int idx, r; 3454 3455 idx = srcu_read_lock(&kvm->srcu); 3456 fn = to_kvm_vmx(kvm)->tss_addr >> PAGE_SHIFT; 3457 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE); 3458 if (r < 0) 3459 goto out; 3460 data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE; 3461 r = kvm_write_guest_page(kvm, fn++, &data, 3462 TSS_IOPB_BASE_OFFSET, sizeof(u16)); 3463 if (r < 0) 3464 goto out; 3465 r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE); 3466 if (r < 0) 3467 goto out; 3468 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE); 3469 if (r < 0) 3470 goto out; 3471 data = ~0; 3472 r = kvm_write_guest_page(kvm, fn, &data, 3473 RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1, 3474 sizeof(u8)); 3475 out: 3476 srcu_read_unlock(&kvm->srcu, idx); 3477 return r; 3478 } 3479 3480 static int init_rmode_identity_map(struct kvm *kvm) 3481 { 3482 struct kvm_vmx *kvm_vmx = to_kvm_vmx(kvm); 3483 int i, r = 0; 3484 kvm_pfn_t identity_map_pfn; 3485 u32 tmp; 3486 3487 /* Protect kvm_vmx->ept_identity_pagetable_done. */ 3488 mutex_lock(&kvm->slots_lock); 3489 3490 if (likely(kvm_vmx->ept_identity_pagetable_done)) 3491 goto out; 3492 3493 if (!kvm_vmx->ept_identity_map_addr) 3494 kvm_vmx->ept_identity_map_addr = VMX_EPT_IDENTITY_PAGETABLE_ADDR; 3495 identity_map_pfn = kvm_vmx->ept_identity_map_addr >> PAGE_SHIFT; 3496 3497 r = __x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT, 3498 kvm_vmx->ept_identity_map_addr, PAGE_SIZE); 3499 if (r < 0) 3500 goto out; 3501 3502 r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE); 3503 if (r < 0) 3504 goto out; 3505 /* Set up identity-mapping pagetable for EPT in real mode */ 3506 for (i = 0; i < PT32_ENT_PER_PAGE; i++) { 3507 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER | 3508 _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE); 3509 r = kvm_write_guest_page(kvm, identity_map_pfn, 3510 &tmp, i * sizeof(tmp), sizeof(tmp)); 3511 if (r < 0) 3512 goto out; 3513 } 3514 kvm_vmx->ept_identity_pagetable_done = true; 3515 3516 out: 3517 mutex_unlock(&kvm->slots_lock); 3518 return r; 3519 } 3520 3521 static void seg_setup(int seg) 3522 { 3523 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg]; 3524 unsigned int ar; 3525 3526 vmcs_write16(sf->selector, 0); 3527 vmcs_writel(sf->base, 0); 3528 vmcs_write32(sf->limit, 0xffff); 3529 ar = 0x93; 3530 if (seg == VCPU_SREG_CS) 3531 ar |= 0x08; /* code segment */ 3532 3533 vmcs_write32(sf->ar_bytes, ar); 3534 } 3535 3536 static int alloc_apic_access_page(struct kvm *kvm) 3537 { 3538 struct page *page; 3539 int r = 0; 3540 3541 mutex_lock(&kvm->slots_lock); 3542 if (kvm->arch.apic_access_page_done) 3543 goto out; 3544 r = __x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT, 3545 APIC_DEFAULT_PHYS_BASE, PAGE_SIZE); 3546 if (r) 3547 goto out; 3548 3549 page = gfn_to_page(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT); 3550 if (is_error_page(page)) { 3551 r = -EFAULT; 3552 goto out; 3553 } 3554 3555 /* 3556 * Do not pin the page in memory, so that memory hot-unplug 3557 * is able to migrate it. 3558 */ 3559 put_page(page); 3560 kvm->arch.apic_access_page_done = true; 3561 out: 3562 mutex_unlock(&kvm->slots_lock); 3563 return r; 3564 } 3565 3566 int allocate_vpid(void) 3567 { 3568 int vpid; 3569 3570 if (!enable_vpid) 3571 return 0; 3572 spin_lock(&vmx_vpid_lock); 3573 vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS); 3574 if (vpid < VMX_NR_VPIDS) 3575 __set_bit(vpid, vmx_vpid_bitmap); 3576 else 3577 vpid = 0; 3578 spin_unlock(&vmx_vpid_lock); 3579 return vpid; 3580 } 3581 3582 void free_vpid(int vpid) 3583 { 3584 if (!enable_vpid || vpid == 0) 3585 return; 3586 spin_lock(&vmx_vpid_lock); 3587 __clear_bit(vpid, vmx_vpid_bitmap); 3588 spin_unlock(&vmx_vpid_lock); 3589 } 3590 3591 static __always_inline void vmx_disable_intercept_for_msr(unsigned long *msr_bitmap, 3592 u32 msr, int type) 3593 { 3594 int f = sizeof(unsigned long); 3595 3596 if (!cpu_has_vmx_msr_bitmap()) 3597 return; 3598 3599 if (static_branch_unlikely(&enable_evmcs)) 3600 evmcs_touch_msr_bitmap(); 3601 3602 /* 3603 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals 3604 * have the write-low and read-high bitmap offsets the wrong way round. 3605 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff. 3606 */ 3607 if (msr <= 0x1fff) { 3608 if (type & MSR_TYPE_R) 3609 /* read-low */ 3610 __clear_bit(msr, msr_bitmap + 0x000 / f); 3611 3612 if (type & MSR_TYPE_W) 3613 /* write-low */ 3614 __clear_bit(msr, msr_bitmap + 0x800 / f); 3615 3616 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) { 3617 msr &= 0x1fff; 3618 if (type & MSR_TYPE_R) 3619 /* read-high */ 3620 __clear_bit(msr, msr_bitmap + 0x400 / f); 3621 3622 if (type & MSR_TYPE_W) 3623 /* write-high */ 3624 __clear_bit(msr, msr_bitmap + 0xc00 / f); 3625 3626 } 3627 } 3628 3629 static __always_inline void vmx_enable_intercept_for_msr(unsigned long *msr_bitmap, 3630 u32 msr, int type) 3631 { 3632 int f = sizeof(unsigned long); 3633 3634 if (!cpu_has_vmx_msr_bitmap()) 3635 return; 3636 3637 if (static_branch_unlikely(&enable_evmcs)) 3638 evmcs_touch_msr_bitmap(); 3639 3640 /* 3641 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals 3642 * have the write-low and read-high bitmap offsets the wrong way round. 3643 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff. 3644 */ 3645 if (msr <= 0x1fff) { 3646 if (type & MSR_TYPE_R) 3647 /* read-low */ 3648 __set_bit(msr, msr_bitmap + 0x000 / f); 3649 3650 if (type & MSR_TYPE_W) 3651 /* write-low */ 3652 __set_bit(msr, msr_bitmap + 0x800 / f); 3653 3654 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) { 3655 msr &= 0x1fff; 3656 if (type & MSR_TYPE_R) 3657 /* read-high */ 3658 __set_bit(msr, msr_bitmap + 0x400 / f); 3659 3660 if (type & MSR_TYPE_W) 3661 /* write-high */ 3662 __set_bit(msr, msr_bitmap + 0xc00 / f); 3663 3664 } 3665 } 3666 3667 static __always_inline void vmx_set_intercept_for_msr(unsigned long *msr_bitmap, 3668 u32 msr, int type, bool value) 3669 { 3670 if (value) 3671 vmx_enable_intercept_for_msr(msr_bitmap, msr, type); 3672 else 3673 vmx_disable_intercept_for_msr(msr_bitmap, msr, type); 3674 } 3675 3676 static u8 vmx_msr_bitmap_mode(struct kvm_vcpu *vcpu) 3677 { 3678 u8 mode = 0; 3679 3680 if (cpu_has_secondary_exec_ctrls() && 3681 (secondary_exec_controls_get(to_vmx(vcpu)) & 3682 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE)) { 3683 mode |= MSR_BITMAP_MODE_X2APIC; 3684 if (enable_apicv && kvm_vcpu_apicv_active(vcpu)) 3685 mode |= MSR_BITMAP_MODE_X2APIC_APICV; 3686 } 3687 3688 return mode; 3689 } 3690 3691 static void vmx_update_msr_bitmap_x2apic(unsigned long *msr_bitmap, 3692 u8 mode) 3693 { 3694 int msr; 3695 3696 for (msr = 0x800; msr <= 0x8ff; msr += BITS_PER_LONG) { 3697 unsigned word = msr / BITS_PER_LONG; 3698 msr_bitmap[word] = (mode & MSR_BITMAP_MODE_X2APIC_APICV) ? 0 : ~0; 3699 msr_bitmap[word + (0x800 / sizeof(long))] = ~0; 3700 } 3701 3702 if (mode & MSR_BITMAP_MODE_X2APIC) { 3703 /* 3704 * TPR reads and writes can be virtualized even if virtual interrupt 3705 * delivery is not in use. 3706 */ 3707 vmx_disable_intercept_for_msr(msr_bitmap, X2APIC_MSR(APIC_TASKPRI), MSR_TYPE_RW); 3708 if (mode & MSR_BITMAP_MODE_X2APIC_APICV) { 3709 vmx_enable_intercept_for_msr(msr_bitmap, X2APIC_MSR(APIC_TMCCT), MSR_TYPE_R); 3710 vmx_disable_intercept_for_msr(msr_bitmap, X2APIC_MSR(APIC_EOI), MSR_TYPE_W); 3711 vmx_disable_intercept_for_msr(msr_bitmap, X2APIC_MSR(APIC_SELF_IPI), MSR_TYPE_W); 3712 } 3713 } 3714 } 3715 3716 void vmx_update_msr_bitmap(struct kvm_vcpu *vcpu) 3717 { 3718 struct vcpu_vmx *vmx = to_vmx(vcpu); 3719 unsigned long *msr_bitmap = vmx->vmcs01.msr_bitmap; 3720 u8 mode = vmx_msr_bitmap_mode(vcpu); 3721 u8 changed = mode ^ vmx->msr_bitmap_mode; 3722 3723 if (!changed) 3724 return; 3725 3726 if (changed & (MSR_BITMAP_MODE_X2APIC | MSR_BITMAP_MODE_X2APIC_APICV)) 3727 vmx_update_msr_bitmap_x2apic(msr_bitmap, mode); 3728 3729 vmx->msr_bitmap_mode = mode; 3730 } 3731 3732 void pt_update_intercept_for_msr(struct vcpu_vmx *vmx) 3733 { 3734 unsigned long *msr_bitmap = vmx->vmcs01.msr_bitmap; 3735 bool flag = !(vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN); 3736 u32 i; 3737 3738 vmx_set_intercept_for_msr(msr_bitmap, MSR_IA32_RTIT_STATUS, 3739 MSR_TYPE_RW, flag); 3740 vmx_set_intercept_for_msr(msr_bitmap, MSR_IA32_RTIT_OUTPUT_BASE, 3741 MSR_TYPE_RW, flag); 3742 vmx_set_intercept_for_msr(msr_bitmap, MSR_IA32_RTIT_OUTPUT_MASK, 3743 MSR_TYPE_RW, flag); 3744 vmx_set_intercept_for_msr(msr_bitmap, MSR_IA32_RTIT_CR3_MATCH, 3745 MSR_TYPE_RW, flag); 3746 for (i = 0; i < vmx->pt_desc.addr_range; i++) { 3747 vmx_set_intercept_for_msr(msr_bitmap, 3748 MSR_IA32_RTIT_ADDR0_A + i * 2, MSR_TYPE_RW, flag); 3749 vmx_set_intercept_for_msr(msr_bitmap, 3750 MSR_IA32_RTIT_ADDR0_B + i * 2, MSR_TYPE_RW, flag); 3751 } 3752 } 3753 3754 static bool vmx_guest_apic_has_interrupt(struct kvm_vcpu *vcpu) 3755 { 3756 struct vcpu_vmx *vmx = to_vmx(vcpu); 3757 void *vapic_page; 3758 u32 vppr; 3759 int rvi; 3760 3761 if (WARN_ON_ONCE(!is_guest_mode(vcpu)) || 3762 !nested_cpu_has_vid(get_vmcs12(vcpu)) || 3763 WARN_ON_ONCE(!vmx->nested.virtual_apic_map.gfn)) 3764 return false; 3765 3766 rvi = vmx_get_rvi(); 3767 3768 vapic_page = vmx->nested.virtual_apic_map.hva; 3769 vppr = *((u32 *)(vapic_page + APIC_PROCPRI)); 3770 3771 return ((rvi & 0xf0) > (vppr & 0xf0)); 3772 } 3773 3774 static inline bool kvm_vcpu_trigger_posted_interrupt(struct kvm_vcpu *vcpu, 3775 bool nested) 3776 { 3777 #ifdef CONFIG_SMP 3778 int pi_vec = nested ? POSTED_INTR_NESTED_VECTOR : POSTED_INTR_VECTOR; 3779 3780 if (vcpu->mode == IN_GUEST_MODE) { 3781 /* 3782 * The vector of interrupt to be delivered to vcpu had 3783 * been set in PIR before this function. 3784 * 3785 * Following cases will be reached in this block, and 3786 * we always send a notification event in all cases as 3787 * explained below. 3788 * 3789 * Case 1: vcpu keeps in non-root mode. Sending a 3790 * notification event posts the interrupt to vcpu. 3791 * 3792 * Case 2: vcpu exits to root mode and is still 3793 * runnable. PIR will be synced to vIRR before the 3794 * next vcpu entry. Sending a notification event in 3795 * this case has no effect, as vcpu is not in root 3796 * mode. 3797 * 3798 * Case 3: vcpu exits to root mode and is blocked. 3799 * vcpu_block() has already synced PIR to vIRR and 3800 * never blocks vcpu if vIRR is not cleared. Therefore, 3801 * a blocked vcpu here does not wait for any requested 3802 * interrupts in PIR, and sending a notification event 3803 * which has no effect is safe here. 3804 */ 3805 3806 apic->send_IPI_mask(get_cpu_mask(vcpu->cpu), pi_vec); 3807 return true; 3808 } 3809 #endif 3810 return false; 3811 } 3812 3813 static int vmx_deliver_nested_posted_interrupt(struct kvm_vcpu *vcpu, 3814 int vector) 3815 { 3816 struct vcpu_vmx *vmx = to_vmx(vcpu); 3817 3818 if (is_guest_mode(vcpu) && 3819 vector == vmx->nested.posted_intr_nv) { 3820 /* 3821 * If a posted intr is not recognized by hardware, 3822 * we will accomplish it in the next vmentry. 3823 */ 3824 vmx->nested.pi_pending = true; 3825 kvm_make_request(KVM_REQ_EVENT, vcpu); 3826 /* the PIR and ON have been set by L1. */ 3827 if (!kvm_vcpu_trigger_posted_interrupt(vcpu, true)) 3828 kvm_vcpu_kick(vcpu); 3829 return 0; 3830 } 3831 return -1; 3832 } 3833 /* 3834 * Send interrupt to vcpu via posted interrupt way. 3835 * 1. If target vcpu is running(non-root mode), send posted interrupt 3836 * notification to vcpu and hardware will sync PIR to vIRR atomically. 3837 * 2. If target vcpu isn't running(root mode), kick it to pick up the 3838 * interrupt from PIR in next vmentry. 3839 */ 3840 static int vmx_deliver_posted_interrupt(struct kvm_vcpu *vcpu, int vector) 3841 { 3842 struct vcpu_vmx *vmx = to_vmx(vcpu); 3843 int r; 3844 3845 r = vmx_deliver_nested_posted_interrupt(vcpu, vector); 3846 if (!r) 3847 return 0; 3848 3849 if (!vcpu->arch.apicv_active) 3850 return -1; 3851 3852 if (pi_test_and_set_pir(vector, &vmx->pi_desc)) 3853 return 0; 3854 3855 /* If a previous notification has sent the IPI, nothing to do. */ 3856 if (pi_test_and_set_on(&vmx->pi_desc)) 3857 return 0; 3858 3859 if (!kvm_vcpu_trigger_posted_interrupt(vcpu, false)) 3860 kvm_vcpu_kick(vcpu); 3861 3862 return 0; 3863 } 3864 3865 /* 3866 * Set up the vmcs's constant host-state fields, i.e., host-state fields that 3867 * will not change in the lifetime of the guest. 3868 * Note that host-state that does change is set elsewhere. E.g., host-state 3869 * that is set differently for each CPU is set in vmx_vcpu_load(), not here. 3870 */ 3871 void vmx_set_constant_host_state(struct vcpu_vmx *vmx) 3872 { 3873 u32 low32, high32; 3874 unsigned long tmpl; 3875 unsigned long cr0, cr3, cr4; 3876 3877 cr0 = read_cr0(); 3878 WARN_ON(cr0 & X86_CR0_TS); 3879 vmcs_writel(HOST_CR0, cr0); /* 22.2.3 */ 3880 3881 /* 3882 * Save the most likely value for this task's CR3 in the VMCS. 3883 * We can't use __get_current_cr3_fast() because we're not atomic. 3884 */ 3885 cr3 = __read_cr3(); 3886 vmcs_writel(HOST_CR3, cr3); /* 22.2.3 FIXME: shadow tables */ 3887 vmx->loaded_vmcs->host_state.cr3 = cr3; 3888 3889 /* Save the most likely value for this task's CR4 in the VMCS. */ 3890 cr4 = cr4_read_shadow(); 3891 vmcs_writel(HOST_CR4, cr4); /* 22.2.3, 22.2.5 */ 3892 vmx->loaded_vmcs->host_state.cr4 = cr4; 3893 3894 vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */ 3895 #ifdef CONFIG_X86_64 3896 /* 3897 * Load null selectors, so we can avoid reloading them in 3898 * vmx_prepare_switch_to_host(), in case userspace uses 3899 * the null selectors too (the expected case). 3900 */ 3901 vmcs_write16(HOST_DS_SELECTOR, 0); 3902 vmcs_write16(HOST_ES_SELECTOR, 0); 3903 #else 3904 vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */ 3905 vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */ 3906 #endif 3907 vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */ 3908 vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */ 3909 3910 vmcs_writel(HOST_IDTR_BASE, host_idt_base); /* 22.2.4 */ 3911 3912 vmcs_writel(HOST_RIP, (unsigned long)vmx_vmexit); /* 22.2.5 */ 3913 3914 rdmsr(MSR_IA32_SYSENTER_CS, low32, high32); 3915 vmcs_write32(HOST_IA32_SYSENTER_CS, low32); 3916 rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl); 3917 vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl); /* 22.2.3 */ 3918 3919 if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) { 3920 rdmsr(MSR_IA32_CR_PAT, low32, high32); 3921 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32)); 3922 } 3923 3924 if (cpu_has_load_ia32_efer()) 3925 vmcs_write64(HOST_IA32_EFER, host_efer); 3926 } 3927 3928 void set_cr4_guest_host_mask(struct vcpu_vmx *vmx) 3929 { 3930 vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS; 3931 if (enable_ept) 3932 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE; 3933 if (is_guest_mode(&vmx->vcpu)) 3934 vmx->vcpu.arch.cr4_guest_owned_bits &= 3935 ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask; 3936 vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits); 3937 } 3938 3939 u32 vmx_pin_based_exec_ctrl(struct vcpu_vmx *vmx) 3940 { 3941 u32 pin_based_exec_ctrl = vmcs_config.pin_based_exec_ctrl; 3942 3943 if (!kvm_vcpu_apicv_active(&vmx->vcpu)) 3944 pin_based_exec_ctrl &= ~PIN_BASED_POSTED_INTR; 3945 3946 if (!enable_vnmi) 3947 pin_based_exec_ctrl &= ~PIN_BASED_VIRTUAL_NMIS; 3948 3949 if (!enable_preemption_timer) 3950 pin_based_exec_ctrl &= ~PIN_BASED_VMX_PREEMPTION_TIMER; 3951 3952 return pin_based_exec_ctrl; 3953 } 3954 3955 static void vmx_refresh_apicv_exec_ctrl(struct kvm_vcpu *vcpu) 3956 { 3957 struct vcpu_vmx *vmx = to_vmx(vcpu); 3958 3959 pin_controls_set(vmx, vmx_pin_based_exec_ctrl(vmx)); 3960 if (cpu_has_secondary_exec_ctrls()) { 3961 if (kvm_vcpu_apicv_active(vcpu)) 3962 secondary_exec_controls_setbit(vmx, 3963 SECONDARY_EXEC_APIC_REGISTER_VIRT | 3964 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY); 3965 else 3966 secondary_exec_controls_clearbit(vmx, 3967 SECONDARY_EXEC_APIC_REGISTER_VIRT | 3968 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY); 3969 } 3970 3971 if (cpu_has_vmx_msr_bitmap()) 3972 vmx_update_msr_bitmap(vcpu); 3973 } 3974 3975 u32 vmx_exec_control(struct vcpu_vmx *vmx) 3976 { 3977 u32 exec_control = vmcs_config.cpu_based_exec_ctrl; 3978 3979 if (vmx->vcpu.arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT) 3980 exec_control &= ~CPU_BASED_MOV_DR_EXITING; 3981 3982 if (!cpu_need_tpr_shadow(&vmx->vcpu)) { 3983 exec_control &= ~CPU_BASED_TPR_SHADOW; 3984 #ifdef CONFIG_X86_64 3985 exec_control |= CPU_BASED_CR8_STORE_EXITING | 3986 CPU_BASED_CR8_LOAD_EXITING; 3987 #endif 3988 } 3989 if (!enable_ept) 3990 exec_control |= CPU_BASED_CR3_STORE_EXITING | 3991 CPU_BASED_CR3_LOAD_EXITING | 3992 CPU_BASED_INVLPG_EXITING; 3993 if (kvm_mwait_in_guest(vmx->vcpu.kvm)) 3994 exec_control &= ~(CPU_BASED_MWAIT_EXITING | 3995 CPU_BASED_MONITOR_EXITING); 3996 if (kvm_hlt_in_guest(vmx->vcpu.kvm)) 3997 exec_control &= ~CPU_BASED_HLT_EXITING; 3998 return exec_control; 3999 } 4000 4001 4002 static void vmx_compute_secondary_exec_control(struct vcpu_vmx *vmx) 4003 { 4004 struct kvm_vcpu *vcpu = &vmx->vcpu; 4005 4006 u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl; 4007 4008 if (vmx_pt_mode_is_system()) 4009 exec_control &= ~(SECONDARY_EXEC_PT_USE_GPA | SECONDARY_EXEC_PT_CONCEAL_VMX); 4010 if (!cpu_need_virtualize_apic_accesses(vcpu)) 4011 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES; 4012 if (vmx->vpid == 0) 4013 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID; 4014 if (!enable_ept) { 4015 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT; 4016 enable_unrestricted_guest = 0; 4017 } 4018 if (!enable_unrestricted_guest) 4019 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST; 4020 if (kvm_pause_in_guest(vmx->vcpu.kvm)) 4021 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING; 4022 if (!kvm_vcpu_apicv_active(vcpu)) 4023 exec_control &= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT | 4024 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY); 4025 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE; 4026 4027 /* SECONDARY_EXEC_DESC is enabled/disabled on writes to CR4.UMIP, 4028 * in vmx_set_cr4. */ 4029 exec_control &= ~SECONDARY_EXEC_DESC; 4030 4031 /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD 4032 (handle_vmptrld). 4033 We can NOT enable shadow_vmcs here because we don't have yet 4034 a current VMCS12 4035 */ 4036 exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS; 4037 4038 if (!enable_pml) 4039 exec_control &= ~SECONDARY_EXEC_ENABLE_PML; 4040 4041 if (vmx_xsaves_supported()) { 4042 /* Exposing XSAVES only when XSAVE is exposed */ 4043 bool xsaves_enabled = 4044 boot_cpu_has(X86_FEATURE_XSAVE) && 4045 guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) && 4046 guest_cpuid_has(vcpu, X86_FEATURE_XSAVES); 4047 4048 vcpu->arch.xsaves_enabled = xsaves_enabled; 4049 4050 if (!xsaves_enabled) 4051 exec_control &= ~SECONDARY_EXEC_XSAVES; 4052 4053 if (nested) { 4054 if (xsaves_enabled) 4055 vmx->nested.msrs.secondary_ctls_high |= 4056 SECONDARY_EXEC_XSAVES; 4057 else 4058 vmx->nested.msrs.secondary_ctls_high &= 4059 ~SECONDARY_EXEC_XSAVES; 4060 } 4061 } 4062 4063 if (cpu_has_vmx_rdtscp()) { 4064 bool rdtscp_enabled = guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP); 4065 if (!rdtscp_enabled) 4066 exec_control &= ~SECONDARY_EXEC_RDTSCP; 4067 4068 if (nested) { 4069 if (rdtscp_enabled) 4070 vmx->nested.msrs.secondary_ctls_high |= 4071 SECONDARY_EXEC_RDTSCP; 4072 else 4073 vmx->nested.msrs.secondary_ctls_high &= 4074 ~SECONDARY_EXEC_RDTSCP; 4075 } 4076 } 4077 4078 if (cpu_has_vmx_invpcid()) { 4079 /* Exposing INVPCID only when PCID is exposed */ 4080 bool invpcid_enabled = 4081 guest_cpuid_has(vcpu, X86_FEATURE_INVPCID) && 4082 guest_cpuid_has(vcpu, X86_FEATURE_PCID); 4083 4084 if (!invpcid_enabled) { 4085 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID; 4086 guest_cpuid_clear(vcpu, X86_FEATURE_INVPCID); 4087 } 4088 4089 if (nested) { 4090 if (invpcid_enabled) 4091 vmx->nested.msrs.secondary_ctls_high |= 4092 SECONDARY_EXEC_ENABLE_INVPCID; 4093 else 4094 vmx->nested.msrs.secondary_ctls_high &= 4095 ~SECONDARY_EXEC_ENABLE_INVPCID; 4096 } 4097 } 4098 4099 if (vmx_rdrand_supported()) { 4100 bool rdrand_enabled = guest_cpuid_has(vcpu, X86_FEATURE_RDRAND); 4101 if (rdrand_enabled) 4102 exec_control &= ~SECONDARY_EXEC_RDRAND_EXITING; 4103 4104 if (nested) { 4105 if (rdrand_enabled) 4106 vmx->nested.msrs.secondary_ctls_high |= 4107 SECONDARY_EXEC_RDRAND_EXITING; 4108 else 4109 vmx->nested.msrs.secondary_ctls_high &= 4110 ~SECONDARY_EXEC_RDRAND_EXITING; 4111 } 4112 } 4113 4114 if (vmx_rdseed_supported()) { 4115 bool rdseed_enabled = guest_cpuid_has(vcpu, X86_FEATURE_RDSEED); 4116 if (rdseed_enabled) 4117 exec_control &= ~SECONDARY_EXEC_RDSEED_EXITING; 4118 4119 if (nested) { 4120 if (rdseed_enabled) 4121 vmx->nested.msrs.secondary_ctls_high |= 4122 SECONDARY_EXEC_RDSEED_EXITING; 4123 else 4124 vmx->nested.msrs.secondary_ctls_high &= 4125 ~SECONDARY_EXEC_RDSEED_EXITING; 4126 } 4127 } 4128 4129 if (vmx_waitpkg_supported()) { 4130 bool waitpkg_enabled = 4131 guest_cpuid_has(vcpu, X86_FEATURE_WAITPKG); 4132 4133 if (!waitpkg_enabled) 4134 exec_control &= ~SECONDARY_EXEC_ENABLE_USR_WAIT_PAUSE; 4135 4136 if (nested) { 4137 if (waitpkg_enabled) 4138 vmx->nested.msrs.secondary_ctls_high |= 4139 SECONDARY_EXEC_ENABLE_USR_WAIT_PAUSE; 4140 else 4141 vmx->nested.msrs.secondary_ctls_high &= 4142 ~SECONDARY_EXEC_ENABLE_USR_WAIT_PAUSE; 4143 } 4144 } 4145 4146 vmx->secondary_exec_control = exec_control; 4147 } 4148 4149 static void ept_set_mmio_spte_mask(void) 4150 { 4151 /* 4152 * EPT Misconfigurations can be generated if the value of bits 2:0 4153 * of an EPT paging-structure entry is 110b (write/execute). 4154 */ 4155 kvm_mmu_set_mmio_spte_mask(VMX_EPT_RWX_MASK, 4156 VMX_EPT_MISCONFIG_WX_VALUE, 0); 4157 } 4158 4159 #define VMX_XSS_EXIT_BITMAP 0 4160 4161 /* 4162 * Noting that the initialization of Guest-state Area of VMCS is in 4163 * vmx_vcpu_reset(). 4164 */ 4165 static void init_vmcs(struct vcpu_vmx *vmx) 4166 { 4167 if (nested) 4168 nested_vmx_set_vmcs_shadowing_bitmap(); 4169 4170 if (cpu_has_vmx_msr_bitmap()) 4171 vmcs_write64(MSR_BITMAP, __pa(vmx->vmcs01.msr_bitmap)); 4172 4173 vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */ 4174 4175 /* Control */ 4176 pin_controls_set(vmx, vmx_pin_based_exec_ctrl(vmx)); 4177 4178 exec_controls_set(vmx, vmx_exec_control(vmx)); 4179 4180 if (cpu_has_secondary_exec_ctrls()) { 4181 vmx_compute_secondary_exec_control(vmx); 4182 secondary_exec_controls_set(vmx, vmx->secondary_exec_control); 4183 } 4184 4185 if (kvm_vcpu_apicv_active(&vmx->vcpu)) { 4186 vmcs_write64(EOI_EXIT_BITMAP0, 0); 4187 vmcs_write64(EOI_EXIT_BITMAP1, 0); 4188 vmcs_write64(EOI_EXIT_BITMAP2, 0); 4189 vmcs_write64(EOI_EXIT_BITMAP3, 0); 4190 4191 vmcs_write16(GUEST_INTR_STATUS, 0); 4192 4193 vmcs_write16(POSTED_INTR_NV, POSTED_INTR_VECTOR); 4194 vmcs_write64(POSTED_INTR_DESC_ADDR, __pa((&vmx->pi_desc))); 4195 } 4196 4197 if (!kvm_pause_in_guest(vmx->vcpu.kvm)) { 4198 vmcs_write32(PLE_GAP, ple_gap); 4199 vmx->ple_window = ple_window; 4200 vmx->ple_window_dirty = true; 4201 } 4202 4203 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0); 4204 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0); 4205 vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */ 4206 4207 vmcs_write16(HOST_FS_SELECTOR, 0); /* 22.2.4 */ 4208 vmcs_write16(HOST_GS_SELECTOR, 0); /* 22.2.4 */ 4209 vmx_set_constant_host_state(vmx); 4210 vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */ 4211 vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */ 4212 4213 if (cpu_has_vmx_vmfunc()) 4214 vmcs_write64(VM_FUNCTION_CONTROL, 0); 4215 4216 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0); 4217 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0); 4218 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host.val)); 4219 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0); 4220 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest.val)); 4221 4222 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) 4223 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat); 4224 4225 vm_exit_controls_set(vmx, vmx_vmexit_ctrl()); 4226 4227 /* 22.2.1, 20.8.1 */ 4228 vm_entry_controls_set(vmx, vmx_vmentry_ctrl()); 4229 4230 vmx->vcpu.arch.cr0_guest_owned_bits = X86_CR0_TS; 4231 vmcs_writel(CR0_GUEST_HOST_MASK, ~X86_CR0_TS); 4232 4233 set_cr4_guest_host_mask(vmx); 4234 4235 if (vmx->vpid != 0) 4236 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid); 4237 4238 if (vmx_xsaves_supported()) 4239 vmcs_write64(XSS_EXIT_BITMAP, VMX_XSS_EXIT_BITMAP); 4240 4241 if (enable_pml) { 4242 vmcs_write64(PML_ADDRESS, page_to_phys(vmx->pml_pg)); 4243 vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1); 4244 } 4245 4246 if (cpu_has_vmx_encls_vmexit()) 4247 vmcs_write64(ENCLS_EXITING_BITMAP, -1ull); 4248 4249 if (vmx_pt_mode_is_host_guest()) { 4250 memset(&vmx->pt_desc, 0, sizeof(vmx->pt_desc)); 4251 /* Bit[6~0] are forced to 1, writes are ignored. */ 4252 vmx->pt_desc.guest.output_mask = 0x7F; 4253 vmcs_write64(GUEST_IA32_RTIT_CTL, 0); 4254 } 4255 } 4256 4257 static void vmx_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event) 4258 { 4259 struct vcpu_vmx *vmx = to_vmx(vcpu); 4260 struct msr_data apic_base_msr; 4261 u64 cr0; 4262 4263 vmx->rmode.vm86_active = 0; 4264 vmx->spec_ctrl = 0; 4265 4266 vmx->msr_ia32_umwait_control = 0; 4267 4268 vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val(); 4269 vmx->hv_deadline_tsc = -1; 4270 kvm_set_cr8(vcpu, 0); 4271 4272 if (!init_event) { 4273 apic_base_msr.data = APIC_DEFAULT_PHYS_BASE | 4274 MSR_IA32_APICBASE_ENABLE; 4275 if (kvm_vcpu_is_reset_bsp(vcpu)) 4276 apic_base_msr.data |= MSR_IA32_APICBASE_BSP; 4277 apic_base_msr.host_initiated = true; 4278 kvm_set_apic_base(vcpu, &apic_base_msr); 4279 } 4280 4281 vmx_segment_cache_clear(vmx); 4282 4283 seg_setup(VCPU_SREG_CS); 4284 vmcs_write16(GUEST_CS_SELECTOR, 0xf000); 4285 vmcs_writel(GUEST_CS_BASE, 0xffff0000ul); 4286 4287 seg_setup(VCPU_SREG_DS); 4288 seg_setup(VCPU_SREG_ES); 4289 seg_setup(VCPU_SREG_FS); 4290 seg_setup(VCPU_SREG_GS); 4291 seg_setup(VCPU_SREG_SS); 4292 4293 vmcs_write16(GUEST_TR_SELECTOR, 0); 4294 vmcs_writel(GUEST_TR_BASE, 0); 4295 vmcs_write32(GUEST_TR_LIMIT, 0xffff); 4296 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b); 4297 4298 vmcs_write16(GUEST_LDTR_SELECTOR, 0); 4299 vmcs_writel(GUEST_LDTR_BASE, 0); 4300 vmcs_write32(GUEST_LDTR_LIMIT, 0xffff); 4301 vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082); 4302 4303 if (!init_event) { 4304 vmcs_write32(GUEST_SYSENTER_CS, 0); 4305 vmcs_writel(GUEST_SYSENTER_ESP, 0); 4306 vmcs_writel(GUEST_SYSENTER_EIP, 0); 4307 vmcs_write64(GUEST_IA32_DEBUGCTL, 0); 4308 } 4309 4310 kvm_set_rflags(vcpu, X86_EFLAGS_FIXED); 4311 kvm_rip_write(vcpu, 0xfff0); 4312 4313 vmcs_writel(GUEST_GDTR_BASE, 0); 4314 vmcs_write32(GUEST_GDTR_LIMIT, 0xffff); 4315 4316 vmcs_writel(GUEST_IDTR_BASE, 0); 4317 vmcs_write32(GUEST_IDTR_LIMIT, 0xffff); 4318 4319 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE); 4320 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0); 4321 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS, 0); 4322 if (kvm_mpx_supported()) 4323 vmcs_write64(GUEST_BNDCFGS, 0); 4324 4325 setup_msrs(vmx); 4326 4327 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */ 4328 4329 if (cpu_has_vmx_tpr_shadow() && !init_event) { 4330 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0); 4331 if (cpu_need_tpr_shadow(vcpu)) 4332 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 4333 __pa(vcpu->arch.apic->regs)); 4334 vmcs_write32(TPR_THRESHOLD, 0); 4335 } 4336 4337 kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu); 4338 4339 cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET; 4340 vmx->vcpu.arch.cr0 = cr0; 4341 vmx_set_cr0(vcpu, cr0); /* enter rmode */ 4342 vmx_set_cr4(vcpu, 0); 4343 vmx_set_efer(vcpu, 0); 4344 4345 update_exception_bitmap(vcpu); 4346 4347 vpid_sync_context(vmx->vpid); 4348 if (init_event) 4349 vmx_clear_hlt(vcpu); 4350 } 4351 4352 static void enable_irq_window(struct kvm_vcpu *vcpu) 4353 { 4354 exec_controls_setbit(to_vmx(vcpu), CPU_BASED_INTR_WINDOW_EXITING); 4355 } 4356 4357 static void enable_nmi_window(struct kvm_vcpu *vcpu) 4358 { 4359 if (!enable_vnmi || 4360 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) { 4361 enable_irq_window(vcpu); 4362 return; 4363 } 4364 4365 exec_controls_setbit(to_vmx(vcpu), CPU_BASED_NMI_WINDOW_EXITING); 4366 } 4367 4368 static void vmx_inject_irq(struct kvm_vcpu *vcpu) 4369 { 4370 struct vcpu_vmx *vmx = to_vmx(vcpu); 4371 uint32_t intr; 4372 int irq = vcpu->arch.interrupt.nr; 4373 4374 trace_kvm_inj_virq(irq); 4375 4376 ++vcpu->stat.irq_injections; 4377 if (vmx->rmode.vm86_active) { 4378 int inc_eip = 0; 4379 if (vcpu->arch.interrupt.soft) 4380 inc_eip = vcpu->arch.event_exit_inst_len; 4381 kvm_inject_realmode_interrupt(vcpu, irq, inc_eip); 4382 return; 4383 } 4384 intr = irq | INTR_INFO_VALID_MASK; 4385 if (vcpu->arch.interrupt.soft) { 4386 intr |= INTR_TYPE_SOFT_INTR; 4387 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 4388 vmx->vcpu.arch.event_exit_inst_len); 4389 } else 4390 intr |= INTR_TYPE_EXT_INTR; 4391 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr); 4392 4393 vmx_clear_hlt(vcpu); 4394 } 4395 4396 static void vmx_inject_nmi(struct kvm_vcpu *vcpu) 4397 { 4398 struct vcpu_vmx *vmx = to_vmx(vcpu); 4399 4400 if (!enable_vnmi) { 4401 /* 4402 * Tracking the NMI-blocked state in software is built upon 4403 * finding the next open IRQ window. This, in turn, depends on 4404 * well-behaving guests: They have to keep IRQs disabled at 4405 * least as long as the NMI handler runs. Otherwise we may 4406 * cause NMI nesting, maybe breaking the guest. But as this is 4407 * highly unlikely, we can live with the residual risk. 4408 */ 4409 vmx->loaded_vmcs->soft_vnmi_blocked = 1; 4410 vmx->loaded_vmcs->vnmi_blocked_time = 0; 4411 } 4412 4413 ++vcpu->stat.nmi_injections; 4414 vmx->loaded_vmcs->nmi_known_unmasked = false; 4415 4416 if (vmx->rmode.vm86_active) { 4417 kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0); 4418 return; 4419 } 4420 4421 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 4422 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR); 4423 4424 vmx_clear_hlt(vcpu); 4425 } 4426 4427 bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu) 4428 { 4429 struct vcpu_vmx *vmx = to_vmx(vcpu); 4430 bool masked; 4431 4432 if (!enable_vnmi) 4433 return vmx->loaded_vmcs->soft_vnmi_blocked; 4434 if (vmx->loaded_vmcs->nmi_known_unmasked) 4435 return false; 4436 masked = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI; 4437 vmx->loaded_vmcs->nmi_known_unmasked = !masked; 4438 return masked; 4439 } 4440 4441 void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked) 4442 { 4443 struct vcpu_vmx *vmx = to_vmx(vcpu); 4444 4445 if (!enable_vnmi) { 4446 if (vmx->loaded_vmcs->soft_vnmi_blocked != masked) { 4447 vmx->loaded_vmcs->soft_vnmi_blocked = masked; 4448 vmx->loaded_vmcs->vnmi_blocked_time = 0; 4449 } 4450 } else { 4451 vmx->loaded_vmcs->nmi_known_unmasked = !masked; 4452 if (masked) 4453 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, 4454 GUEST_INTR_STATE_NMI); 4455 else 4456 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO, 4457 GUEST_INTR_STATE_NMI); 4458 } 4459 } 4460 4461 static int vmx_nmi_allowed(struct kvm_vcpu *vcpu) 4462 { 4463 if (to_vmx(vcpu)->nested.nested_run_pending) 4464 return 0; 4465 4466 if (!enable_vnmi && 4467 to_vmx(vcpu)->loaded_vmcs->soft_vnmi_blocked) 4468 return 0; 4469 4470 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & 4471 (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI 4472 | GUEST_INTR_STATE_NMI)); 4473 } 4474 4475 static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu) 4476 { 4477 if (to_vmx(vcpu)->nested.nested_run_pending) 4478 return false; 4479 4480 if (is_guest_mode(vcpu) && nested_exit_on_intr(vcpu)) 4481 return true; 4482 4483 return (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) && 4484 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & 4485 (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS)); 4486 } 4487 4488 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr) 4489 { 4490 int ret; 4491 4492 if (enable_unrestricted_guest) 4493 return 0; 4494 4495 mutex_lock(&kvm->slots_lock); 4496 ret = __x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, addr, 4497 PAGE_SIZE * 3); 4498 mutex_unlock(&kvm->slots_lock); 4499 4500 if (ret) 4501 return ret; 4502 to_kvm_vmx(kvm)->tss_addr = addr; 4503 return init_rmode_tss(kvm); 4504 } 4505 4506 static int vmx_set_identity_map_addr(struct kvm *kvm, u64 ident_addr) 4507 { 4508 to_kvm_vmx(kvm)->ept_identity_map_addr = ident_addr; 4509 return 0; 4510 } 4511 4512 static bool rmode_exception(struct kvm_vcpu *vcpu, int vec) 4513 { 4514 switch (vec) { 4515 case BP_VECTOR: 4516 /* 4517 * Update instruction length as we may reinject the exception 4518 * from user space while in guest debugging mode. 4519 */ 4520 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len = 4521 vmcs_read32(VM_EXIT_INSTRUCTION_LEN); 4522 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP) 4523 return false; 4524 /* fall through */ 4525 case DB_VECTOR: 4526 if (vcpu->guest_debug & 4527 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) 4528 return false; 4529 /* fall through */ 4530 case DE_VECTOR: 4531 case OF_VECTOR: 4532 case BR_VECTOR: 4533 case UD_VECTOR: 4534 case DF_VECTOR: 4535 case SS_VECTOR: 4536 case GP_VECTOR: 4537 case MF_VECTOR: 4538 return true; 4539 } 4540 return false; 4541 } 4542 4543 static int handle_rmode_exception(struct kvm_vcpu *vcpu, 4544 int vec, u32 err_code) 4545 { 4546 /* 4547 * Instruction with address size override prefix opcode 0x67 4548 * Cause the #SS fault with 0 error code in VM86 mode. 4549 */ 4550 if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0) { 4551 if (kvm_emulate_instruction(vcpu, 0)) { 4552 if (vcpu->arch.halt_request) { 4553 vcpu->arch.halt_request = 0; 4554 return kvm_vcpu_halt(vcpu); 4555 } 4556 return 1; 4557 } 4558 return 0; 4559 } 4560 4561 /* 4562 * Forward all other exceptions that are valid in real mode. 4563 * FIXME: Breaks guest debugging in real mode, needs to be fixed with 4564 * the required debugging infrastructure rework. 4565 */ 4566 kvm_queue_exception(vcpu, vec); 4567 return 1; 4568 } 4569 4570 /* 4571 * Trigger machine check on the host. We assume all the MSRs are already set up 4572 * by the CPU and that we still run on the same CPU as the MCE occurred on. 4573 * We pass a fake environment to the machine check handler because we want 4574 * the guest to be always treated like user space, no matter what context 4575 * it used internally. 4576 */ 4577 static void kvm_machine_check(void) 4578 { 4579 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64) 4580 struct pt_regs regs = { 4581 .cs = 3, /* Fake ring 3 no matter what the guest ran on */ 4582 .flags = X86_EFLAGS_IF, 4583 }; 4584 4585 do_machine_check(®s, 0); 4586 #endif 4587 } 4588 4589 static int handle_machine_check(struct kvm_vcpu *vcpu) 4590 { 4591 /* handled by vmx_vcpu_run() */ 4592 return 1; 4593 } 4594 4595 static int handle_exception_nmi(struct kvm_vcpu *vcpu) 4596 { 4597 struct vcpu_vmx *vmx = to_vmx(vcpu); 4598 struct kvm_run *kvm_run = vcpu->run; 4599 u32 intr_info, ex_no, error_code; 4600 unsigned long cr2, rip, dr6; 4601 u32 vect_info; 4602 4603 vect_info = vmx->idt_vectoring_info; 4604 intr_info = vmx->exit_intr_info; 4605 4606 if (is_machine_check(intr_info) || is_nmi(intr_info)) 4607 return 1; /* handled by handle_exception_nmi_irqoff() */ 4608 4609 if (is_invalid_opcode(intr_info)) 4610 return handle_ud(vcpu); 4611 4612 error_code = 0; 4613 if (intr_info & INTR_INFO_DELIVER_CODE_MASK) 4614 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE); 4615 4616 if (!vmx->rmode.vm86_active && is_gp_fault(intr_info)) { 4617 WARN_ON_ONCE(!enable_vmware_backdoor); 4618 4619 /* 4620 * VMware backdoor emulation on #GP interception only handles 4621 * IN{S}, OUT{S}, and RDPMC, none of which generate a non-zero 4622 * error code on #GP. 4623 */ 4624 if (error_code) { 4625 kvm_queue_exception_e(vcpu, GP_VECTOR, error_code); 4626 return 1; 4627 } 4628 return kvm_emulate_instruction(vcpu, EMULTYPE_VMWARE_GP); 4629 } 4630 4631 /* 4632 * The #PF with PFEC.RSVD = 1 indicates the guest is accessing 4633 * MMIO, it is better to report an internal error. 4634 * See the comments in vmx_handle_exit. 4635 */ 4636 if ((vect_info & VECTORING_INFO_VALID_MASK) && 4637 !(is_page_fault(intr_info) && !(error_code & PFERR_RSVD_MASK))) { 4638 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR; 4639 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX; 4640 vcpu->run->internal.ndata = 3; 4641 vcpu->run->internal.data[0] = vect_info; 4642 vcpu->run->internal.data[1] = intr_info; 4643 vcpu->run->internal.data[2] = error_code; 4644 return 0; 4645 } 4646 4647 if (is_page_fault(intr_info)) { 4648 cr2 = vmcs_readl(EXIT_QUALIFICATION); 4649 /* EPT won't cause page fault directly */ 4650 WARN_ON_ONCE(!vcpu->arch.apf.host_apf_reason && enable_ept); 4651 return kvm_handle_page_fault(vcpu, error_code, cr2, NULL, 0); 4652 } 4653 4654 ex_no = intr_info & INTR_INFO_VECTOR_MASK; 4655 4656 if (vmx->rmode.vm86_active && rmode_exception(vcpu, ex_no)) 4657 return handle_rmode_exception(vcpu, ex_no, error_code); 4658 4659 switch (ex_no) { 4660 case AC_VECTOR: 4661 kvm_queue_exception_e(vcpu, AC_VECTOR, error_code); 4662 return 1; 4663 case DB_VECTOR: 4664 dr6 = vmcs_readl(EXIT_QUALIFICATION); 4665 if (!(vcpu->guest_debug & 4666 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) { 4667 vcpu->arch.dr6 &= ~DR_TRAP_BITS; 4668 vcpu->arch.dr6 |= dr6 | DR6_RTM; 4669 if (is_icebp(intr_info)) 4670 WARN_ON(!skip_emulated_instruction(vcpu)); 4671 4672 kvm_queue_exception(vcpu, DB_VECTOR); 4673 return 1; 4674 } 4675 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1; 4676 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7); 4677 /* fall through */ 4678 case BP_VECTOR: 4679 /* 4680 * Update instruction length as we may reinject #BP from 4681 * user space while in guest debugging mode. Reading it for 4682 * #DB as well causes no harm, it is not used in that case. 4683 */ 4684 vmx->vcpu.arch.event_exit_inst_len = 4685 vmcs_read32(VM_EXIT_INSTRUCTION_LEN); 4686 kvm_run->exit_reason = KVM_EXIT_DEBUG; 4687 rip = kvm_rip_read(vcpu); 4688 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip; 4689 kvm_run->debug.arch.exception = ex_no; 4690 break; 4691 default: 4692 kvm_run->exit_reason = KVM_EXIT_EXCEPTION; 4693 kvm_run->ex.exception = ex_no; 4694 kvm_run->ex.error_code = error_code; 4695 break; 4696 } 4697 return 0; 4698 } 4699 4700 static __always_inline int handle_external_interrupt(struct kvm_vcpu *vcpu) 4701 { 4702 ++vcpu->stat.irq_exits; 4703 return 1; 4704 } 4705 4706 static int handle_triple_fault(struct kvm_vcpu *vcpu) 4707 { 4708 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN; 4709 vcpu->mmio_needed = 0; 4710 return 0; 4711 } 4712 4713 static int handle_io(struct kvm_vcpu *vcpu) 4714 { 4715 unsigned long exit_qualification; 4716 int size, in, string; 4717 unsigned port; 4718 4719 exit_qualification = vmcs_readl(EXIT_QUALIFICATION); 4720 string = (exit_qualification & 16) != 0; 4721 4722 ++vcpu->stat.io_exits; 4723 4724 if (string) 4725 return kvm_emulate_instruction(vcpu, 0); 4726 4727 port = exit_qualification >> 16; 4728 size = (exit_qualification & 7) + 1; 4729 in = (exit_qualification & 8) != 0; 4730 4731 return kvm_fast_pio(vcpu, size, port, in); 4732 } 4733 4734 static void 4735 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall) 4736 { 4737 /* 4738 * Patch in the VMCALL instruction: 4739 */ 4740 hypercall[0] = 0x0f; 4741 hypercall[1] = 0x01; 4742 hypercall[2] = 0xc1; 4743 } 4744 4745 /* called to set cr0 as appropriate for a mov-to-cr0 exit. */ 4746 static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val) 4747 { 4748 if (is_guest_mode(vcpu)) { 4749 struct vmcs12 *vmcs12 = get_vmcs12(vcpu); 4750 unsigned long orig_val = val; 4751 4752 /* 4753 * We get here when L2 changed cr0 in a way that did not change 4754 * any of L1's shadowed bits (see nested_vmx_exit_handled_cr), 4755 * but did change L0 shadowed bits. So we first calculate the 4756 * effective cr0 value that L1 would like to write into the 4757 * hardware. It consists of the L2-owned bits from the new 4758 * value combined with the L1-owned bits from L1's guest_cr0. 4759 */ 4760 val = (val & ~vmcs12->cr0_guest_host_mask) | 4761 (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask); 4762 4763 if (!nested_guest_cr0_valid(vcpu, val)) 4764 return 1; 4765 4766 if (kvm_set_cr0(vcpu, val)) 4767 return 1; 4768 vmcs_writel(CR0_READ_SHADOW, orig_val); 4769 return 0; 4770 } else { 4771 if (to_vmx(vcpu)->nested.vmxon && 4772 !nested_host_cr0_valid(vcpu, val)) 4773 return 1; 4774 4775 return kvm_set_cr0(vcpu, val); 4776 } 4777 } 4778 4779 static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val) 4780 { 4781 if (is_guest_mode(vcpu)) { 4782 struct vmcs12 *vmcs12 = get_vmcs12(vcpu); 4783 unsigned long orig_val = val; 4784 4785 /* analogously to handle_set_cr0 */ 4786 val = (val & ~vmcs12->cr4_guest_host_mask) | 4787 (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask); 4788 if (kvm_set_cr4(vcpu, val)) 4789 return 1; 4790 vmcs_writel(CR4_READ_SHADOW, orig_val); 4791 return 0; 4792 } else 4793 return kvm_set_cr4(vcpu, val); 4794 } 4795 4796 static int handle_desc(struct kvm_vcpu *vcpu) 4797 { 4798 WARN_ON(!(vcpu->arch.cr4 & X86_CR4_UMIP)); 4799 return kvm_emulate_instruction(vcpu, 0); 4800 } 4801 4802 static int handle_cr(struct kvm_vcpu *vcpu) 4803 { 4804 unsigned long exit_qualification, val; 4805 int cr; 4806 int reg; 4807 int err; 4808 int ret; 4809 4810 exit_qualification = vmcs_readl(EXIT_QUALIFICATION); 4811 cr = exit_qualification & 15; 4812 reg = (exit_qualification >> 8) & 15; 4813 switch ((exit_qualification >> 4) & 3) { 4814 case 0: /* mov to cr */ 4815 val = kvm_register_readl(vcpu, reg); 4816 trace_kvm_cr_write(cr, val); 4817 switch (cr) { 4818 case 0: 4819 err = handle_set_cr0(vcpu, val); 4820 return kvm_complete_insn_gp(vcpu, err); 4821 case 3: 4822 WARN_ON_ONCE(enable_unrestricted_guest); 4823 err = kvm_set_cr3(vcpu, val); 4824 return kvm_complete_insn_gp(vcpu, err); 4825 case 4: 4826 err = handle_set_cr4(vcpu, val); 4827 return kvm_complete_insn_gp(vcpu, err); 4828 case 8: { 4829 u8 cr8_prev = kvm_get_cr8(vcpu); 4830 u8 cr8 = (u8)val; 4831 err = kvm_set_cr8(vcpu, cr8); 4832 ret = kvm_complete_insn_gp(vcpu, err); 4833 if (lapic_in_kernel(vcpu)) 4834 return ret; 4835 if (cr8_prev <= cr8) 4836 return ret; 4837 /* 4838 * TODO: we might be squashing a 4839 * KVM_GUESTDBG_SINGLESTEP-triggered 4840 * KVM_EXIT_DEBUG here. 4841 */ 4842 vcpu->run->exit_reason = KVM_EXIT_SET_TPR; 4843 return 0; 4844 } 4845 } 4846 break; 4847 case 2: /* clts */ 4848 WARN_ONCE(1, "Guest should always own CR0.TS"); 4849 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS)); 4850 trace_kvm_cr_write(0, kvm_read_cr0(vcpu)); 4851 return kvm_skip_emulated_instruction(vcpu); 4852 case 1: /*mov from cr*/ 4853 switch (cr) { 4854 case 3: 4855 WARN_ON_ONCE(enable_unrestricted_guest); 4856 val = kvm_read_cr3(vcpu); 4857 kvm_register_write(vcpu, reg, val); 4858 trace_kvm_cr_read(cr, val); 4859 return kvm_skip_emulated_instruction(vcpu); 4860 case 8: 4861 val = kvm_get_cr8(vcpu); 4862 kvm_register_write(vcpu, reg, val); 4863 trace_kvm_cr_read(cr, val); 4864 return kvm_skip_emulated_instruction(vcpu); 4865 } 4866 break; 4867 case 3: /* lmsw */ 4868 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f; 4869 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val); 4870 kvm_lmsw(vcpu, val); 4871 4872 return kvm_skip_emulated_instruction(vcpu); 4873 default: 4874 break; 4875 } 4876 vcpu->run->exit_reason = 0; 4877 vcpu_unimpl(vcpu, "unhandled control register: op %d cr %d\n", 4878 (int)(exit_qualification >> 4) & 3, cr); 4879 return 0; 4880 } 4881 4882 static int handle_dr(struct kvm_vcpu *vcpu) 4883 { 4884 unsigned long exit_qualification; 4885 int dr, dr7, reg; 4886 4887 exit_qualification = vmcs_readl(EXIT_QUALIFICATION); 4888 dr = exit_qualification & DEBUG_REG_ACCESS_NUM; 4889 4890 /* First, if DR does not exist, trigger UD */ 4891 if (!kvm_require_dr(vcpu, dr)) 4892 return 1; 4893 4894 /* Do not handle if the CPL > 0, will trigger GP on re-entry */ 4895 if (!kvm_require_cpl(vcpu, 0)) 4896 return 1; 4897 dr7 = vmcs_readl(GUEST_DR7); 4898 if (dr7 & DR7_GD) { 4899 /* 4900 * As the vm-exit takes precedence over the debug trap, we 4901 * need to emulate the latter, either for the host or the 4902 * guest debugging itself. 4903 */ 4904 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) { 4905 vcpu->run->debug.arch.dr6 = vcpu->arch.dr6; 4906 vcpu->run->debug.arch.dr7 = dr7; 4907 vcpu->run->debug.arch.pc = kvm_get_linear_rip(vcpu); 4908 vcpu->run->debug.arch.exception = DB_VECTOR; 4909 vcpu->run->exit_reason = KVM_EXIT_DEBUG; 4910 return 0; 4911 } else { 4912 vcpu->arch.dr6 &= ~DR_TRAP_BITS; 4913 vcpu->arch.dr6 |= DR6_BD | DR6_RTM; 4914 kvm_queue_exception(vcpu, DB_VECTOR); 4915 return 1; 4916 } 4917 } 4918 4919 if (vcpu->guest_debug == 0) { 4920 exec_controls_clearbit(to_vmx(vcpu), CPU_BASED_MOV_DR_EXITING); 4921 4922 /* 4923 * No more DR vmexits; force a reload of the debug registers 4924 * and reenter on this instruction. The next vmexit will 4925 * retrieve the full state of the debug registers. 4926 */ 4927 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT; 4928 return 1; 4929 } 4930 4931 reg = DEBUG_REG_ACCESS_REG(exit_qualification); 4932 if (exit_qualification & TYPE_MOV_FROM_DR) { 4933 unsigned long val; 4934 4935 if (kvm_get_dr(vcpu, dr, &val)) 4936 return 1; 4937 kvm_register_write(vcpu, reg, val); 4938 } else 4939 if (kvm_set_dr(vcpu, dr, kvm_register_readl(vcpu, reg))) 4940 return 1; 4941 4942 return kvm_skip_emulated_instruction(vcpu); 4943 } 4944 4945 static u64 vmx_get_dr6(struct kvm_vcpu *vcpu) 4946 { 4947 return vcpu->arch.dr6; 4948 } 4949 4950 static void vmx_set_dr6(struct kvm_vcpu *vcpu, unsigned long val) 4951 { 4952 } 4953 4954 static void vmx_sync_dirty_debug_regs(struct kvm_vcpu *vcpu) 4955 { 4956 get_debugreg(vcpu->arch.db[0], 0); 4957 get_debugreg(vcpu->arch.db[1], 1); 4958 get_debugreg(vcpu->arch.db[2], 2); 4959 get_debugreg(vcpu->arch.db[3], 3); 4960 get_debugreg(vcpu->arch.dr6, 6); 4961 vcpu->arch.dr7 = vmcs_readl(GUEST_DR7); 4962 4963 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT; 4964 exec_controls_setbit(to_vmx(vcpu), CPU_BASED_MOV_DR_EXITING); 4965 } 4966 4967 static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val) 4968 { 4969 vmcs_writel(GUEST_DR7, val); 4970 } 4971 4972 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu) 4973 { 4974 kvm_apic_update_ppr(vcpu); 4975 return 1; 4976 } 4977 4978 static int handle_interrupt_window(struct kvm_vcpu *vcpu) 4979 { 4980 exec_controls_clearbit(to_vmx(vcpu), CPU_BASED_INTR_WINDOW_EXITING); 4981 4982 kvm_make_request(KVM_REQ_EVENT, vcpu); 4983 4984 ++vcpu->stat.irq_window_exits; 4985 return 1; 4986 } 4987 4988 static int handle_vmcall(struct kvm_vcpu *vcpu) 4989 { 4990 return kvm_emulate_hypercall(vcpu); 4991 } 4992 4993 static int handle_invd(struct kvm_vcpu *vcpu) 4994 { 4995 return kvm_emulate_instruction(vcpu, 0); 4996 } 4997 4998 static int handle_invlpg(struct kvm_vcpu *vcpu) 4999 { 5000 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION); 5001 5002 kvm_mmu_invlpg(vcpu, exit_qualification); 5003 return kvm_skip_emulated_instruction(vcpu); 5004 } 5005 5006 static int handle_rdpmc(struct kvm_vcpu *vcpu) 5007 { 5008 int err; 5009 5010 err = kvm_rdpmc(vcpu); 5011 return kvm_complete_insn_gp(vcpu, err); 5012 } 5013 5014 static int handle_wbinvd(struct kvm_vcpu *vcpu) 5015 { 5016 return kvm_emulate_wbinvd(vcpu); 5017 } 5018 5019 static int handle_xsetbv(struct kvm_vcpu *vcpu) 5020 { 5021 u64 new_bv = kvm_read_edx_eax(vcpu); 5022 u32 index = kvm_rcx_read(vcpu); 5023 5024 if (kvm_set_xcr(vcpu, index, new_bv) == 0) 5025 return kvm_skip_emulated_instruction(vcpu); 5026 return 1; 5027 } 5028 5029 static int handle_apic_access(struct kvm_vcpu *vcpu) 5030 { 5031 if (likely(fasteoi)) { 5032 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION); 5033 int access_type, offset; 5034 5035 access_type = exit_qualification & APIC_ACCESS_TYPE; 5036 offset = exit_qualification & APIC_ACCESS_OFFSET; 5037 /* 5038 * Sane guest uses MOV to write EOI, with written value 5039 * not cared. So make a short-circuit here by avoiding 5040 * heavy instruction emulation. 5041 */ 5042 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) && 5043 (offset == APIC_EOI)) { 5044 kvm_lapic_set_eoi(vcpu); 5045 return kvm_skip_emulated_instruction(vcpu); 5046 } 5047 } 5048 return kvm_emulate_instruction(vcpu, 0); 5049 } 5050 5051 static int handle_apic_eoi_induced(struct kvm_vcpu *vcpu) 5052 { 5053 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION); 5054 int vector = exit_qualification & 0xff; 5055 5056 /* EOI-induced VM exit is trap-like and thus no need to adjust IP */ 5057 kvm_apic_set_eoi_accelerated(vcpu, vector); 5058 return 1; 5059 } 5060 5061 static int handle_apic_write(struct kvm_vcpu *vcpu) 5062 { 5063 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION); 5064 u32 offset = exit_qualification & 0xfff; 5065 5066 /* APIC-write VM exit is trap-like and thus no need to adjust IP */ 5067 kvm_apic_write_nodecode(vcpu, offset); 5068 return 1; 5069 } 5070 5071 static int handle_task_switch(struct kvm_vcpu *vcpu) 5072 { 5073 struct vcpu_vmx *vmx = to_vmx(vcpu); 5074 unsigned long exit_qualification; 5075 bool has_error_code = false; 5076 u32 error_code = 0; 5077 u16 tss_selector; 5078 int reason, type, idt_v, idt_index; 5079 5080 idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK); 5081 idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK); 5082 type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK); 5083 5084 exit_qualification = vmcs_readl(EXIT_QUALIFICATION); 5085 5086 reason = (u32)exit_qualification >> 30; 5087 if (reason == TASK_SWITCH_GATE && idt_v) { 5088 switch (type) { 5089 case INTR_TYPE_NMI_INTR: 5090 vcpu->arch.nmi_injected = false; 5091 vmx_set_nmi_mask(vcpu, true); 5092 break; 5093 case INTR_TYPE_EXT_INTR: 5094 case INTR_TYPE_SOFT_INTR: 5095 kvm_clear_interrupt_queue(vcpu); 5096 break; 5097 case INTR_TYPE_HARD_EXCEPTION: 5098 if (vmx->idt_vectoring_info & 5099 VECTORING_INFO_DELIVER_CODE_MASK) { 5100 has_error_code = true; 5101 error_code = 5102 vmcs_read32(IDT_VECTORING_ERROR_CODE); 5103 } 5104 /* fall through */ 5105 case INTR_TYPE_SOFT_EXCEPTION: 5106 kvm_clear_exception_queue(vcpu); 5107 break; 5108 default: 5109 break; 5110 } 5111 } 5112 tss_selector = exit_qualification; 5113 5114 if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION && 5115 type != INTR_TYPE_EXT_INTR && 5116 type != INTR_TYPE_NMI_INTR)) 5117 WARN_ON(!skip_emulated_instruction(vcpu)); 5118 5119 /* 5120 * TODO: What about debug traps on tss switch? 5121 * Are we supposed to inject them and update dr6? 5122 */ 5123 return kvm_task_switch(vcpu, tss_selector, 5124 type == INTR_TYPE_SOFT_INTR ? idt_index : -1, 5125 reason, has_error_code, error_code); 5126 } 5127 5128 static int handle_ept_violation(struct kvm_vcpu *vcpu) 5129 { 5130 unsigned long exit_qualification; 5131 gpa_t gpa; 5132 u64 error_code; 5133 5134 exit_qualification = vmcs_readl(EXIT_QUALIFICATION); 5135 5136 /* 5137 * EPT violation happened while executing iret from NMI, 5138 * "blocked by NMI" bit has to be set before next VM entry. 5139 * There are errata that may cause this bit to not be set: 5140 * AAK134, BY25. 5141 */ 5142 if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) && 5143 enable_vnmi && 5144 (exit_qualification & INTR_INFO_UNBLOCK_NMI)) 5145 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, GUEST_INTR_STATE_NMI); 5146 5147 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS); 5148 trace_kvm_page_fault(gpa, exit_qualification); 5149 5150 /* Is it a read fault? */ 5151 error_code = (exit_qualification & EPT_VIOLATION_ACC_READ) 5152 ? PFERR_USER_MASK : 0; 5153 /* Is it a write fault? */ 5154 error_code |= (exit_qualification & EPT_VIOLATION_ACC_WRITE) 5155 ? PFERR_WRITE_MASK : 0; 5156 /* Is it a fetch fault? */ 5157 error_code |= (exit_qualification & EPT_VIOLATION_ACC_INSTR) 5158 ? PFERR_FETCH_MASK : 0; 5159 /* ept page table entry is present? */ 5160 error_code |= (exit_qualification & 5161 (EPT_VIOLATION_READABLE | EPT_VIOLATION_WRITABLE | 5162 EPT_VIOLATION_EXECUTABLE)) 5163 ? PFERR_PRESENT_MASK : 0; 5164 5165 error_code |= (exit_qualification & 0x100) != 0 ? 5166 PFERR_GUEST_FINAL_MASK : PFERR_GUEST_PAGE_MASK; 5167 5168 vcpu->arch.exit_qualification = exit_qualification; 5169 return kvm_mmu_page_fault(vcpu, gpa, error_code, NULL, 0); 5170 } 5171 5172 static int handle_ept_misconfig(struct kvm_vcpu *vcpu) 5173 { 5174 gpa_t gpa; 5175 5176 /* 5177 * A nested guest cannot optimize MMIO vmexits, because we have an 5178 * nGPA here instead of the required GPA. 5179 */ 5180 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS); 5181 if (!is_guest_mode(vcpu) && 5182 !kvm_io_bus_write(vcpu, KVM_FAST_MMIO_BUS, gpa, 0, NULL)) { 5183 trace_kvm_fast_mmio(gpa); 5184 return kvm_skip_emulated_instruction(vcpu); 5185 } 5186 5187 return kvm_mmu_page_fault(vcpu, gpa, PFERR_RSVD_MASK, NULL, 0); 5188 } 5189 5190 static int handle_nmi_window(struct kvm_vcpu *vcpu) 5191 { 5192 WARN_ON_ONCE(!enable_vnmi); 5193 exec_controls_clearbit(to_vmx(vcpu), CPU_BASED_NMI_WINDOW_EXITING); 5194 ++vcpu->stat.nmi_window_exits; 5195 kvm_make_request(KVM_REQ_EVENT, vcpu); 5196 5197 return 1; 5198 } 5199 5200 static int handle_invalid_guest_state(struct kvm_vcpu *vcpu) 5201 { 5202 struct vcpu_vmx *vmx = to_vmx(vcpu); 5203 bool intr_window_requested; 5204 unsigned count = 130; 5205 5206 /* 5207 * We should never reach the point where we are emulating L2 5208 * due to invalid guest state as that means we incorrectly 5209 * allowed a nested VMEntry with an invalid vmcs12. 5210 */ 5211 WARN_ON_ONCE(vmx->emulation_required && vmx->nested.nested_run_pending); 5212 5213 intr_window_requested = exec_controls_get(vmx) & 5214 CPU_BASED_INTR_WINDOW_EXITING; 5215 5216 while (vmx->emulation_required && count-- != 0) { 5217 if (intr_window_requested && vmx_interrupt_allowed(vcpu)) 5218 return handle_interrupt_window(&vmx->vcpu); 5219 5220 if (kvm_test_request(KVM_REQ_EVENT, vcpu)) 5221 return 1; 5222 5223 if (!kvm_emulate_instruction(vcpu, 0)) 5224 return 0; 5225 5226 if (vmx->emulation_required && !vmx->rmode.vm86_active && 5227 vcpu->arch.exception.pending) { 5228 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR; 5229 vcpu->run->internal.suberror = 5230 KVM_INTERNAL_ERROR_EMULATION; 5231 vcpu->run->internal.ndata = 0; 5232 return 0; 5233 } 5234 5235 if (vcpu->arch.halt_request) { 5236 vcpu->arch.halt_request = 0; 5237 return kvm_vcpu_halt(vcpu); 5238 } 5239 5240 /* 5241 * Note, return 1 and not 0, vcpu_run() is responsible for 5242 * morphing the pending signal into the proper return code. 5243 */ 5244 if (signal_pending(current)) 5245 return 1; 5246 5247 if (need_resched()) 5248 schedule(); 5249 } 5250 5251 return 1; 5252 } 5253 5254 static void grow_ple_window(struct kvm_vcpu *vcpu) 5255 { 5256 struct vcpu_vmx *vmx = to_vmx(vcpu); 5257 unsigned int old = vmx->ple_window; 5258 5259 vmx->ple_window = __grow_ple_window(old, ple_window, 5260 ple_window_grow, 5261 ple_window_max); 5262 5263 if (vmx->ple_window != old) { 5264 vmx->ple_window_dirty = true; 5265 trace_kvm_ple_window_update(vcpu->vcpu_id, 5266 vmx->ple_window, old); 5267 } 5268 } 5269 5270 static void shrink_ple_window(struct kvm_vcpu *vcpu) 5271 { 5272 struct vcpu_vmx *vmx = to_vmx(vcpu); 5273 unsigned int old = vmx->ple_window; 5274 5275 vmx->ple_window = __shrink_ple_window(old, ple_window, 5276 ple_window_shrink, 5277 ple_window); 5278 5279 if (vmx->ple_window != old) { 5280 vmx->ple_window_dirty = true; 5281 trace_kvm_ple_window_update(vcpu->vcpu_id, 5282 vmx->ple_window, old); 5283 } 5284 } 5285 5286 /* 5287 * Handler for POSTED_INTERRUPT_WAKEUP_VECTOR. 5288 */ 5289 static void wakeup_handler(void) 5290 { 5291 struct kvm_vcpu *vcpu; 5292 int cpu = smp_processor_id(); 5293 5294 spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu)); 5295 list_for_each_entry(vcpu, &per_cpu(blocked_vcpu_on_cpu, cpu), 5296 blocked_vcpu_list) { 5297 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu); 5298 5299 if (pi_test_on(pi_desc) == 1) 5300 kvm_vcpu_kick(vcpu); 5301 } 5302 spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu)); 5303 } 5304 5305 static void vmx_enable_tdp(void) 5306 { 5307 kvm_mmu_set_mask_ptes(VMX_EPT_READABLE_MASK, 5308 enable_ept_ad_bits ? VMX_EPT_ACCESS_BIT : 0ull, 5309 enable_ept_ad_bits ? VMX_EPT_DIRTY_BIT : 0ull, 5310 0ull, VMX_EPT_EXECUTABLE_MASK, 5311 cpu_has_vmx_ept_execute_only() ? 0ull : VMX_EPT_READABLE_MASK, 5312 VMX_EPT_RWX_MASK, 0ull); 5313 5314 ept_set_mmio_spte_mask(); 5315 } 5316 5317 /* 5318 * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE 5319 * exiting, so only get here on cpu with PAUSE-Loop-Exiting. 5320 */ 5321 static int handle_pause(struct kvm_vcpu *vcpu) 5322 { 5323 if (!kvm_pause_in_guest(vcpu->kvm)) 5324 grow_ple_window(vcpu); 5325 5326 /* 5327 * Intel sdm vol3 ch-25.1.3 says: The "PAUSE-loop exiting" 5328 * VM-execution control is ignored if CPL > 0. OTOH, KVM 5329 * never set PAUSE_EXITING and just set PLE if supported, 5330 * so the vcpu must be CPL=0 if it gets a PAUSE exit. 5331 */ 5332 kvm_vcpu_on_spin(vcpu, true); 5333 return kvm_skip_emulated_instruction(vcpu); 5334 } 5335 5336 static int handle_nop(struct kvm_vcpu *vcpu) 5337 { 5338 return kvm_skip_emulated_instruction(vcpu); 5339 } 5340 5341 static int handle_mwait(struct kvm_vcpu *vcpu) 5342 { 5343 printk_once(KERN_WARNING "kvm: MWAIT instruction emulated as NOP!\n"); 5344 return handle_nop(vcpu); 5345 } 5346 5347 static int handle_invalid_op(struct kvm_vcpu *vcpu) 5348 { 5349 kvm_queue_exception(vcpu, UD_VECTOR); 5350 return 1; 5351 } 5352 5353 static int handle_monitor_trap(struct kvm_vcpu *vcpu) 5354 { 5355 return 1; 5356 } 5357 5358 static int handle_monitor(struct kvm_vcpu *vcpu) 5359 { 5360 printk_once(KERN_WARNING "kvm: MONITOR instruction emulated as NOP!\n"); 5361 return handle_nop(vcpu); 5362 } 5363 5364 static int handle_invpcid(struct kvm_vcpu *vcpu) 5365 { 5366 u32 vmx_instruction_info; 5367 unsigned long type; 5368 bool pcid_enabled; 5369 gva_t gva; 5370 struct x86_exception e; 5371 unsigned i; 5372 unsigned long roots_to_free = 0; 5373 struct { 5374 u64 pcid; 5375 u64 gla; 5376 } operand; 5377 5378 if (!guest_cpuid_has(vcpu, X86_FEATURE_INVPCID)) { 5379 kvm_queue_exception(vcpu, UD_VECTOR); 5380 return 1; 5381 } 5382 5383 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO); 5384 type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf); 5385 5386 if (type > 3) { 5387 kvm_inject_gp(vcpu, 0); 5388 return 1; 5389 } 5390 5391 /* According to the Intel instruction reference, the memory operand 5392 * is read even if it isn't needed (e.g., for type==all) 5393 */ 5394 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION), 5395 vmx_instruction_info, false, 5396 sizeof(operand), &gva)) 5397 return 1; 5398 5399 if (kvm_read_guest_virt(vcpu, gva, &operand, sizeof(operand), &e)) { 5400 kvm_inject_page_fault(vcpu, &e); 5401 return 1; 5402 } 5403 5404 if (operand.pcid >> 12 != 0) { 5405 kvm_inject_gp(vcpu, 0); 5406 return 1; 5407 } 5408 5409 pcid_enabled = kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE); 5410 5411 switch (type) { 5412 case INVPCID_TYPE_INDIV_ADDR: 5413 if ((!pcid_enabled && (operand.pcid != 0)) || 5414 is_noncanonical_address(operand.gla, vcpu)) { 5415 kvm_inject_gp(vcpu, 0); 5416 return 1; 5417 } 5418 kvm_mmu_invpcid_gva(vcpu, operand.gla, operand.pcid); 5419 return kvm_skip_emulated_instruction(vcpu); 5420 5421 case INVPCID_TYPE_SINGLE_CTXT: 5422 if (!pcid_enabled && (operand.pcid != 0)) { 5423 kvm_inject_gp(vcpu, 0); 5424 return 1; 5425 } 5426 5427 if (kvm_get_active_pcid(vcpu) == operand.pcid) { 5428 kvm_mmu_sync_roots(vcpu); 5429 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu); 5430 } 5431 5432 for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++) 5433 if (kvm_get_pcid(vcpu, vcpu->arch.mmu->prev_roots[i].cr3) 5434 == operand.pcid) 5435 roots_to_free |= KVM_MMU_ROOT_PREVIOUS(i); 5436 5437 kvm_mmu_free_roots(vcpu, vcpu->arch.mmu, roots_to_free); 5438 /* 5439 * If neither the current cr3 nor any of the prev_roots use the 5440 * given PCID, then nothing needs to be done here because a 5441 * resync will happen anyway before switching to any other CR3. 5442 */ 5443 5444 return kvm_skip_emulated_instruction(vcpu); 5445 5446 case INVPCID_TYPE_ALL_NON_GLOBAL: 5447 /* 5448 * Currently, KVM doesn't mark global entries in the shadow 5449 * page tables, so a non-global flush just degenerates to a 5450 * global flush. If needed, we could optimize this later by 5451 * keeping track of global entries in shadow page tables. 5452 */ 5453 5454 /* fall-through */ 5455 case INVPCID_TYPE_ALL_INCL_GLOBAL: 5456 kvm_mmu_unload(vcpu); 5457 return kvm_skip_emulated_instruction(vcpu); 5458 5459 default: 5460 BUG(); /* We have already checked above that type <= 3 */ 5461 } 5462 } 5463 5464 static int handle_pml_full(struct kvm_vcpu *vcpu) 5465 { 5466 unsigned long exit_qualification; 5467 5468 trace_kvm_pml_full(vcpu->vcpu_id); 5469 5470 exit_qualification = vmcs_readl(EXIT_QUALIFICATION); 5471 5472 /* 5473 * PML buffer FULL happened while executing iret from NMI, 5474 * "blocked by NMI" bit has to be set before next VM entry. 5475 */ 5476 if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) && 5477 enable_vnmi && 5478 (exit_qualification & INTR_INFO_UNBLOCK_NMI)) 5479 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, 5480 GUEST_INTR_STATE_NMI); 5481 5482 /* 5483 * PML buffer already flushed at beginning of VMEXIT. Nothing to do 5484 * here.., and there's no userspace involvement needed for PML. 5485 */ 5486 return 1; 5487 } 5488 5489 static int handle_preemption_timer(struct kvm_vcpu *vcpu) 5490 { 5491 struct vcpu_vmx *vmx = to_vmx(vcpu); 5492 5493 if (!vmx->req_immediate_exit && 5494 !unlikely(vmx->loaded_vmcs->hv_timer_soft_disabled)) 5495 kvm_lapic_expired_hv_timer(vcpu); 5496 5497 return 1; 5498 } 5499 5500 /* 5501 * When nested=0, all VMX instruction VM Exits filter here. The handlers 5502 * are overwritten by nested_vmx_setup() when nested=1. 5503 */ 5504 static int handle_vmx_instruction(struct kvm_vcpu *vcpu) 5505 { 5506 kvm_queue_exception(vcpu, UD_VECTOR); 5507 return 1; 5508 } 5509 5510 static int handle_encls(struct kvm_vcpu *vcpu) 5511 { 5512 /* 5513 * SGX virtualization is not yet supported. There is no software 5514 * enable bit for SGX, so we have to trap ENCLS and inject a #UD 5515 * to prevent the guest from executing ENCLS. 5516 */ 5517 kvm_queue_exception(vcpu, UD_VECTOR); 5518 return 1; 5519 } 5520 5521 /* 5522 * The exit handlers return 1 if the exit was handled fully and guest execution 5523 * may resume. Otherwise they set the kvm_run parameter to indicate what needs 5524 * to be done to userspace and return 0. 5525 */ 5526 static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = { 5527 [EXIT_REASON_EXCEPTION_NMI] = handle_exception_nmi, 5528 [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt, 5529 [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault, 5530 [EXIT_REASON_NMI_WINDOW] = handle_nmi_window, 5531 [EXIT_REASON_IO_INSTRUCTION] = handle_io, 5532 [EXIT_REASON_CR_ACCESS] = handle_cr, 5533 [EXIT_REASON_DR_ACCESS] = handle_dr, 5534 [EXIT_REASON_CPUID] = kvm_emulate_cpuid, 5535 [EXIT_REASON_MSR_READ] = kvm_emulate_rdmsr, 5536 [EXIT_REASON_MSR_WRITE] = kvm_emulate_wrmsr, 5537 [EXIT_REASON_INTERRUPT_WINDOW] = handle_interrupt_window, 5538 [EXIT_REASON_HLT] = kvm_emulate_halt, 5539 [EXIT_REASON_INVD] = handle_invd, 5540 [EXIT_REASON_INVLPG] = handle_invlpg, 5541 [EXIT_REASON_RDPMC] = handle_rdpmc, 5542 [EXIT_REASON_VMCALL] = handle_vmcall, 5543 [EXIT_REASON_VMCLEAR] = handle_vmx_instruction, 5544 [EXIT_REASON_VMLAUNCH] = handle_vmx_instruction, 5545 [EXIT_REASON_VMPTRLD] = handle_vmx_instruction, 5546 [EXIT_REASON_VMPTRST] = handle_vmx_instruction, 5547 [EXIT_REASON_VMREAD] = handle_vmx_instruction, 5548 [EXIT_REASON_VMRESUME] = handle_vmx_instruction, 5549 [EXIT_REASON_VMWRITE] = handle_vmx_instruction, 5550 [EXIT_REASON_VMOFF] = handle_vmx_instruction, 5551 [EXIT_REASON_VMON] = handle_vmx_instruction, 5552 [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold, 5553 [EXIT_REASON_APIC_ACCESS] = handle_apic_access, 5554 [EXIT_REASON_APIC_WRITE] = handle_apic_write, 5555 [EXIT_REASON_EOI_INDUCED] = handle_apic_eoi_induced, 5556 [EXIT_REASON_WBINVD] = handle_wbinvd, 5557 [EXIT_REASON_XSETBV] = handle_xsetbv, 5558 [EXIT_REASON_TASK_SWITCH] = handle_task_switch, 5559 [EXIT_REASON_MCE_DURING_VMENTRY] = handle_machine_check, 5560 [EXIT_REASON_GDTR_IDTR] = handle_desc, 5561 [EXIT_REASON_LDTR_TR] = handle_desc, 5562 [EXIT_REASON_EPT_VIOLATION] = handle_ept_violation, 5563 [EXIT_REASON_EPT_MISCONFIG] = handle_ept_misconfig, 5564 [EXIT_REASON_PAUSE_INSTRUCTION] = handle_pause, 5565 [EXIT_REASON_MWAIT_INSTRUCTION] = handle_mwait, 5566 [EXIT_REASON_MONITOR_TRAP_FLAG] = handle_monitor_trap, 5567 [EXIT_REASON_MONITOR_INSTRUCTION] = handle_monitor, 5568 [EXIT_REASON_INVEPT] = handle_vmx_instruction, 5569 [EXIT_REASON_INVVPID] = handle_vmx_instruction, 5570 [EXIT_REASON_RDRAND] = handle_invalid_op, 5571 [EXIT_REASON_RDSEED] = handle_invalid_op, 5572 [EXIT_REASON_PML_FULL] = handle_pml_full, 5573 [EXIT_REASON_INVPCID] = handle_invpcid, 5574 [EXIT_REASON_VMFUNC] = handle_vmx_instruction, 5575 [EXIT_REASON_PREEMPTION_TIMER] = handle_preemption_timer, 5576 [EXIT_REASON_ENCLS] = handle_encls, 5577 }; 5578 5579 static const int kvm_vmx_max_exit_handlers = 5580 ARRAY_SIZE(kvm_vmx_exit_handlers); 5581 5582 static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2) 5583 { 5584 *info1 = vmcs_readl(EXIT_QUALIFICATION); 5585 *info2 = vmcs_read32(VM_EXIT_INTR_INFO); 5586 } 5587 5588 static void vmx_destroy_pml_buffer(struct vcpu_vmx *vmx) 5589 { 5590 if (vmx->pml_pg) { 5591 __free_page(vmx->pml_pg); 5592 vmx->pml_pg = NULL; 5593 } 5594 } 5595 5596 static void vmx_flush_pml_buffer(struct kvm_vcpu *vcpu) 5597 { 5598 struct vcpu_vmx *vmx = to_vmx(vcpu); 5599 u64 *pml_buf; 5600 u16 pml_idx; 5601 5602 pml_idx = vmcs_read16(GUEST_PML_INDEX); 5603 5604 /* Do nothing if PML buffer is empty */ 5605 if (pml_idx == (PML_ENTITY_NUM - 1)) 5606 return; 5607 5608 /* PML index always points to next available PML buffer entity */ 5609 if (pml_idx >= PML_ENTITY_NUM) 5610 pml_idx = 0; 5611 else 5612 pml_idx++; 5613 5614 pml_buf = page_address(vmx->pml_pg); 5615 for (; pml_idx < PML_ENTITY_NUM; pml_idx++) { 5616 u64 gpa; 5617 5618 gpa = pml_buf[pml_idx]; 5619 WARN_ON(gpa & (PAGE_SIZE - 1)); 5620 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT); 5621 } 5622 5623 /* reset PML index */ 5624 vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1); 5625 } 5626 5627 /* 5628 * Flush all vcpus' PML buffer and update logged GPAs to dirty_bitmap. 5629 * Called before reporting dirty_bitmap to userspace. 5630 */ 5631 static void kvm_flush_pml_buffers(struct kvm *kvm) 5632 { 5633 int i; 5634 struct kvm_vcpu *vcpu; 5635 /* 5636 * We only need to kick vcpu out of guest mode here, as PML buffer 5637 * is flushed at beginning of all VMEXITs, and it's obvious that only 5638 * vcpus running in guest are possible to have unflushed GPAs in PML 5639 * buffer. 5640 */ 5641 kvm_for_each_vcpu(i, vcpu, kvm) 5642 kvm_vcpu_kick(vcpu); 5643 } 5644 5645 static void vmx_dump_sel(char *name, uint32_t sel) 5646 { 5647 pr_err("%s sel=0x%04x, attr=0x%05x, limit=0x%08x, base=0x%016lx\n", 5648 name, vmcs_read16(sel), 5649 vmcs_read32(sel + GUEST_ES_AR_BYTES - GUEST_ES_SELECTOR), 5650 vmcs_read32(sel + GUEST_ES_LIMIT - GUEST_ES_SELECTOR), 5651 vmcs_readl(sel + GUEST_ES_BASE - GUEST_ES_SELECTOR)); 5652 } 5653 5654 static void vmx_dump_dtsel(char *name, uint32_t limit) 5655 { 5656 pr_err("%s limit=0x%08x, base=0x%016lx\n", 5657 name, vmcs_read32(limit), 5658 vmcs_readl(limit + GUEST_GDTR_BASE - GUEST_GDTR_LIMIT)); 5659 } 5660 5661 void dump_vmcs(void) 5662 { 5663 u32 vmentry_ctl, vmexit_ctl; 5664 u32 cpu_based_exec_ctrl, pin_based_exec_ctrl, secondary_exec_control; 5665 unsigned long cr4; 5666 u64 efer; 5667 int i, n; 5668 5669 if (!dump_invalid_vmcs) { 5670 pr_warn_ratelimited("set kvm_intel.dump_invalid_vmcs=1 to dump internal KVM state.\n"); 5671 return; 5672 } 5673 5674 vmentry_ctl = vmcs_read32(VM_ENTRY_CONTROLS); 5675 vmexit_ctl = vmcs_read32(VM_EXIT_CONTROLS); 5676 cpu_based_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL); 5677 pin_based_exec_ctrl = vmcs_read32(PIN_BASED_VM_EXEC_CONTROL); 5678 cr4 = vmcs_readl(GUEST_CR4); 5679 efer = vmcs_read64(GUEST_IA32_EFER); 5680 secondary_exec_control = 0; 5681 if (cpu_has_secondary_exec_ctrls()) 5682 secondary_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL); 5683 5684 pr_err("*** Guest State ***\n"); 5685 pr_err("CR0: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n", 5686 vmcs_readl(GUEST_CR0), vmcs_readl(CR0_READ_SHADOW), 5687 vmcs_readl(CR0_GUEST_HOST_MASK)); 5688 pr_err("CR4: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n", 5689 cr4, vmcs_readl(CR4_READ_SHADOW), vmcs_readl(CR4_GUEST_HOST_MASK)); 5690 pr_err("CR3 = 0x%016lx\n", vmcs_readl(GUEST_CR3)); 5691 if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT) && 5692 (cr4 & X86_CR4_PAE) && !(efer & EFER_LMA)) 5693 { 5694 pr_err("PDPTR0 = 0x%016llx PDPTR1 = 0x%016llx\n", 5695 vmcs_read64(GUEST_PDPTR0), vmcs_read64(GUEST_PDPTR1)); 5696 pr_err("PDPTR2 = 0x%016llx PDPTR3 = 0x%016llx\n", 5697 vmcs_read64(GUEST_PDPTR2), vmcs_read64(GUEST_PDPTR3)); 5698 } 5699 pr_err("RSP = 0x%016lx RIP = 0x%016lx\n", 5700 vmcs_readl(GUEST_RSP), vmcs_readl(GUEST_RIP)); 5701 pr_err("RFLAGS=0x%08lx DR7 = 0x%016lx\n", 5702 vmcs_readl(GUEST_RFLAGS), vmcs_readl(GUEST_DR7)); 5703 pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n", 5704 vmcs_readl(GUEST_SYSENTER_ESP), 5705 vmcs_read32(GUEST_SYSENTER_CS), vmcs_readl(GUEST_SYSENTER_EIP)); 5706 vmx_dump_sel("CS: ", GUEST_CS_SELECTOR); 5707 vmx_dump_sel("DS: ", GUEST_DS_SELECTOR); 5708 vmx_dump_sel("SS: ", GUEST_SS_SELECTOR); 5709 vmx_dump_sel("ES: ", GUEST_ES_SELECTOR); 5710 vmx_dump_sel("FS: ", GUEST_FS_SELECTOR); 5711 vmx_dump_sel("GS: ", GUEST_GS_SELECTOR); 5712 vmx_dump_dtsel("GDTR:", GUEST_GDTR_LIMIT); 5713 vmx_dump_sel("LDTR:", GUEST_LDTR_SELECTOR); 5714 vmx_dump_dtsel("IDTR:", GUEST_IDTR_LIMIT); 5715 vmx_dump_sel("TR: ", GUEST_TR_SELECTOR); 5716 if ((vmexit_ctl & (VM_EXIT_SAVE_IA32_PAT | VM_EXIT_SAVE_IA32_EFER)) || 5717 (vmentry_ctl & (VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_IA32_EFER))) 5718 pr_err("EFER = 0x%016llx PAT = 0x%016llx\n", 5719 efer, vmcs_read64(GUEST_IA32_PAT)); 5720 pr_err("DebugCtl = 0x%016llx DebugExceptions = 0x%016lx\n", 5721 vmcs_read64(GUEST_IA32_DEBUGCTL), 5722 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS)); 5723 if (cpu_has_load_perf_global_ctrl() && 5724 vmentry_ctl & VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL) 5725 pr_err("PerfGlobCtl = 0x%016llx\n", 5726 vmcs_read64(GUEST_IA32_PERF_GLOBAL_CTRL)); 5727 if (vmentry_ctl & VM_ENTRY_LOAD_BNDCFGS) 5728 pr_err("BndCfgS = 0x%016llx\n", vmcs_read64(GUEST_BNDCFGS)); 5729 pr_err("Interruptibility = %08x ActivityState = %08x\n", 5730 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO), 5731 vmcs_read32(GUEST_ACTIVITY_STATE)); 5732 if (secondary_exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) 5733 pr_err("InterruptStatus = %04x\n", 5734 vmcs_read16(GUEST_INTR_STATUS)); 5735 5736 pr_err("*** Host State ***\n"); 5737 pr_err("RIP = 0x%016lx RSP = 0x%016lx\n", 5738 vmcs_readl(HOST_RIP), vmcs_readl(HOST_RSP)); 5739 pr_err("CS=%04x SS=%04x DS=%04x ES=%04x FS=%04x GS=%04x TR=%04x\n", 5740 vmcs_read16(HOST_CS_SELECTOR), vmcs_read16(HOST_SS_SELECTOR), 5741 vmcs_read16(HOST_DS_SELECTOR), vmcs_read16(HOST_ES_SELECTOR), 5742 vmcs_read16(HOST_FS_SELECTOR), vmcs_read16(HOST_GS_SELECTOR), 5743 vmcs_read16(HOST_TR_SELECTOR)); 5744 pr_err("FSBase=%016lx GSBase=%016lx TRBase=%016lx\n", 5745 vmcs_readl(HOST_FS_BASE), vmcs_readl(HOST_GS_BASE), 5746 vmcs_readl(HOST_TR_BASE)); 5747 pr_err("GDTBase=%016lx IDTBase=%016lx\n", 5748 vmcs_readl(HOST_GDTR_BASE), vmcs_readl(HOST_IDTR_BASE)); 5749 pr_err("CR0=%016lx CR3=%016lx CR4=%016lx\n", 5750 vmcs_readl(HOST_CR0), vmcs_readl(HOST_CR3), 5751 vmcs_readl(HOST_CR4)); 5752 pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n", 5753 vmcs_readl(HOST_IA32_SYSENTER_ESP), 5754 vmcs_read32(HOST_IA32_SYSENTER_CS), 5755 vmcs_readl(HOST_IA32_SYSENTER_EIP)); 5756 if (vmexit_ctl & (VM_EXIT_LOAD_IA32_PAT | VM_EXIT_LOAD_IA32_EFER)) 5757 pr_err("EFER = 0x%016llx PAT = 0x%016llx\n", 5758 vmcs_read64(HOST_IA32_EFER), 5759 vmcs_read64(HOST_IA32_PAT)); 5760 if (cpu_has_load_perf_global_ctrl() && 5761 vmexit_ctl & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL) 5762 pr_err("PerfGlobCtl = 0x%016llx\n", 5763 vmcs_read64(HOST_IA32_PERF_GLOBAL_CTRL)); 5764 5765 pr_err("*** Control State ***\n"); 5766 pr_err("PinBased=%08x CPUBased=%08x SecondaryExec=%08x\n", 5767 pin_based_exec_ctrl, cpu_based_exec_ctrl, secondary_exec_control); 5768 pr_err("EntryControls=%08x ExitControls=%08x\n", vmentry_ctl, vmexit_ctl); 5769 pr_err("ExceptionBitmap=%08x PFECmask=%08x PFECmatch=%08x\n", 5770 vmcs_read32(EXCEPTION_BITMAP), 5771 vmcs_read32(PAGE_FAULT_ERROR_CODE_MASK), 5772 vmcs_read32(PAGE_FAULT_ERROR_CODE_MATCH)); 5773 pr_err("VMEntry: intr_info=%08x errcode=%08x ilen=%08x\n", 5774 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD), 5775 vmcs_read32(VM_ENTRY_EXCEPTION_ERROR_CODE), 5776 vmcs_read32(VM_ENTRY_INSTRUCTION_LEN)); 5777 pr_err("VMExit: intr_info=%08x errcode=%08x ilen=%08x\n", 5778 vmcs_read32(VM_EXIT_INTR_INFO), 5779 vmcs_read32(VM_EXIT_INTR_ERROR_CODE), 5780 vmcs_read32(VM_EXIT_INSTRUCTION_LEN)); 5781 pr_err(" reason=%08x qualification=%016lx\n", 5782 vmcs_read32(VM_EXIT_REASON), vmcs_readl(EXIT_QUALIFICATION)); 5783 pr_err("IDTVectoring: info=%08x errcode=%08x\n", 5784 vmcs_read32(IDT_VECTORING_INFO_FIELD), 5785 vmcs_read32(IDT_VECTORING_ERROR_CODE)); 5786 pr_err("TSC Offset = 0x%016llx\n", vmcs_read64(TSC_OFFSET)); 5787 if (secondary_exec_control & SECONDARY_EXEC_TSC_SCALING) 5788 pr_err("TSC Multiplier = 0x%016llx\n", 5789 vmcs_read64(TSC_MULTIPLIER)); 5790 if (cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW) { 5791 if (secondary_exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) { 5792 u16 status = vmcs_read16(GUEST_INTR_STATUS); 5793 pr_err("SVI|RVI = %02x|%02x ", status >> 8, status & 0xff); 5794 } 5795 pr_cont("TPR Threshold = 0x%02x\n", vmcs_read32(TPR_THRESHOLD)); 5796 if (secondary_exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) 5797 pr_err("APIC-access addr = 0x%016llx ", vmcs_read64(APIC_ACCESS_ADDR)); 5798 pr_cont("virt-APIC addr = 0x%016llx\n", vmcs_read64(VIRTUAL_APIC_PAGE_ADDR)); 5799 } 5800 if (pin_based_exec_ctrl & PIN_BASED_POSTED_INTR) 5801 pr_err("PostedIntrVec = 0x%02x\n", vmcs_read16(POSTED_INTR_NV)); 5802 if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT)) 5803 pr_err("EPT pointer = 0x%016llx\n", vmcs_read64(EPT_POINTER)); 5804 n = vmcs_read32(CR3_TARGET_COUNT); 5805 for (i = 0; i + 1 < n; i += 4) 5806 pr_err("CR3 target%u=%016lx target%u=%016lx\n", 5807 i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2), 5808 i + 1, vmcs_readl(CR3_TARGET_VALUE0 + i * 2 + 2)); 5809 if (i < n) 5810 pr_err("CR3 target%u=%016lx\n", 5811 i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2)); 5812 if (secondary_exec_control & SECONDARY_EXEC_PAUSE_LOOP_EXITING) 5813 pr_err("PLE Gap=%08x Window=%08x\n", 5814 vmcs_read32(PLE_GAP), vmcs_read32(PLE_WINDOW)); 5815 if (secondary_exec_control & SECONDARY_EXEC_ENABLE_VPID) 5816 pr_err("Virtual processor ID = 0x%04x\n", 5817 vmcs_read16(VIRTUAL_PROCESSOR_ID)); 5818 } 5819 5820 /* 5821 * The guest has exited. See if we can fix it or if we need userspace 5822 * assistance. 5823 */ 5824 static int vmx_handle_exit(struct kvm_vcpu *vcpu, 5825 enum exit_fastpath_completion exit_fastpath) 5826 { 5827 struct vcpu_vmx *vmx = to_vmx(vcpu); 5828 u32 exit_reason = vmx->exit_reason; 5829 u32 vectoring_info = vmx->idt_vectoring_info; 5830 5831 trace_kvm_exit(exit_reason, vcpu, KVM_ISA_VMX); 5832 5833 /* 5834 * Flush logged GPAs PML buffer, this will make dirty_bitmap more 5835 * updated. Another good is, in kvm_vm_ioctl_get_dirty_log, before 5836 * querying dirty_bitmap, we only need to kick all vcpus out of guest 5837 * mode as if vcpus is in root mode, the PML buffer must has been 5838 * flushed already. 5839 */ 5840 if (enable_pml) 5841 vmx_flush_pml_buffer(vcpu); 5842 5843 /* If guest state is invalid, start emulating */ 5844 if (vmx->emulation_required) 5845 return handle_invalid_guest_state(vcpu); 5846 5847 if (is_guest_mode(vcpu)) { 5848 /* 5849 * The host physical addresses of some pages of guest memory 5850 * are loaded into the vmcs02 (e.g. vmcs12's Virtual APIC 5851 * Page). The CPU may write to these pages via their host 5852 * physical address while L2 is running, bypassing any 5853 * address-translation-based dirty tracking (e.g. EPT write 5854 * protection). 5855 * 5856 * Mark them dirty on every exit from L2 to prevent them from 5857 * getting out of sync with dirty tracking. 5858 */ 5859 nested_mark_vmcs12_pages_dirty(vcpu); 5860 5861 if (nested_vmx_exit_reflected(vcpu, exit_reason)) 5862 return nested_vmx_reflect_vmexit(vcpu, exit_reason); 5863 } 5864 5865 if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) { 5866 dump_vmcs(); 5867 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY; 5868 vcpu->run->fail_entry.hardware_entry_failure_reason 5869 = exit_reason; 5870 return 0; 5871 } 5872 5873 if (unlikely(vmx->fail)) { 5874 dump_vmcs(); 5875 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY; 5876 vcpu->run->fail_entry.hardware_entry_failure_reason 5877 = vmcs_read32(VM_INSTRUCTION_ERROR); 5878 return 0; 5879 } 5880 5881 /* 5882 * Note: 5883 * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by 5884 * delivery event since it indicates guest is accessing MMIO. 5885 * The vm-exit can be triggered again after return to guest that 5886 * will cause infinite loop. 5887 */ 5888 if ((vectoring_info & VECTORING_INFO_VALID_MASK) && 5889 (exit_reason != EXIT_REASON_EXCEPTION_NMI && 5890 exit_reason != EXIT_REASON_EPT_VIOLATION && 5891 exit_reason != EXIT_REASON_PML_FULL && 5892 exit_reason != EXIT_REASON_TASK_SWITCH)) { 5893 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR; 5894 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_DELIVERY_EV; 5895 vcpu->run->internal.ndata = 3; 5896 vcpu->run->internal.data[0] = vectoring_info; 5897 vcpu->run->internal.data[1] = exit_reason; 5898 vcpu->run->internal.data[2] = vcpu->arch.exit_qualification; 5899 if (exit_reason == EXIT_REASON_EPT_MISCONFIG) { 5900 vcpu->run->internal.ndata++; 5901 vcpu->run->internal.data[3] = 5902 vmcs_read64(GUEST_PHYSICAL_ADDRESS); 5903 } 5904 return 0; 5905 } 5906 5907 if (unlikely(!enable_vnmi && 5908 vmx->loaded_vmcs->soft_vnmi_blocked)) { 5909 if (vmx_interrupt_allowed(vcpu)) { 5910 vmx->loaded_vmcs->soft_vnmi_blocked = 0; 5911 } else if (vmx->loaded_vmcs->vnmi_blocked_time > 1000000000LL && 5912 vcpu->arch.nmi_pending) { 5913 /* 5914 * This CPU don't support us in finding the end of an 5915 * NMI-blocked window if the guest runs with IRQs 5916 * disabled. So we pull the trigger after 1 s of 5917 * futile waiting, but inform the user about this. 5918 */ 5919 printk(KERN_WARNING "%s: Breaking out of NMI-blocked " 5920 "state on VCPU %d after 1 s timeout\n", 5921 __func__, vcpu->vcpu_id); 5922 vmx->loaded_vmcs->soft_vnmi_blocked = 0; 5923 } 5924 } 5925 5926 if (exit_fastpath == EXIT_FASTPATH_SKIP_EMUL_INS) { 5927 kvm_skip_emulated_instruction(vcpu); 5928 return 1; 5929 } 5930 5931 if (exit_reason >= kvm_vmx_max_exit_handlers) 5932 goto unexpected_vmexit; 5933 #ifdef CONFIG_RETPOLINE 5934 if (exit_reason == EXIT_REASON_MSR_WRITE) 5935 return kvm_emulate_wrmsr(vcpu); 5936 else if (exit_reason == EXIT_REASON_PREEMPTION_TIMER) 5937 return handle_preemption_timer(vcpu); 5938 else if (exit_reason == EXIT_REASON_INTERRUPT_WINDOW) 5939 return handle_interrupt_window(vcpu); 5940 else if (exit_reason == EXIT_REASON_EXTERNAL_INTERRUPT) 5941 return handle_external_interrupt(vcpu); 5942 else if (exit_reason == EXIT_REASON_HLT) 5943 return kvm_emulate_halt(vcpu); 5944 else if (exit_reason == EXIT_REASON_EPT_MISCONFIG) 5945 return handle_ept_misconfig(vcpu); 5946 #endif 5947 5948 exit_reason = array_index_nospec(exit_reason, 5949 kvm_vmx_max_exit_handlers); 5950 if (!kvm_vmx_exit_handlers[exit_reason]) 5951 goto unexpected_vmexit; 5952 5953 return kvm_vmx_exit_handlers[exit_reason](vcpu); 5954 5955 unexpected_vmexit: 5956 vcpu_unimpl(vcpu, "vmx: unexpected exit reason 0x%x\n", exit_reason); 5957 dump_vmcs(); 5958 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR; 5959 vcpu->run->internal.suberror = 5960 KVM_INTERNAL_ERROR_UNEXPECTED_EXIT_REASON; 5961 vcpu->run->internal.ndata = 1; 5962 vcpu->run->internal.data[0] = exit_reason; 5963 return 0; 5964 } 5965 5966 /* 5967 * Software based L1D cache flush which is used when microcode providing 5968 * the cache control MSR is not loaded. 5969 * 5970 * The L1D cache is 32 KiB on Nehalem and later microarchitectures, but to 5971 * flush it is required to read in 64 KiB because the replacement algorithm 5972 * is not exactly LRU. This could be sized at runtime via topology 5973 * information but as all relevant affected CPUs have 32KiB L1D cache size 5974 * there is no point in doing so. 5975 */ 5976 static void vmx_l1d_flush(struct kvm_vcpu *vcpu) 5977 { 5978 int size = PAGE_SIZE << L1D_CACHE_ORDER; 5979 5980 /* 5981 * This code is only executed when the the flush mode is 'cond' or 5982 * 'always' 5983 */ 5984 if (static_branch_likely(&vmx_l1d_flush_cond)) { 5985 bool flush_l1d; 5986 5987 /* 5988 * Clear the per-vcpu flush bit, it gets set again 5989 * either from vcpu_run() or from one of the unsafe 5990 * VMEXIT handlers. 5991 */ 5992 flush_l1d = vcpu->arch.l1tf_flush_l1d; 5993 vcpu->arch.l1tf_flush_l1d = false; 5994 5995 /* 5996 * Clear the per-cpu flush bit, it gets set again from 5997 * the interrupt handlers. 5998 */ 5999 flush_l1d |= kvm_get_cpu_l1tf_flush_l1d(); 6000 kvm_clear_cpu_l1tf_flush_l1d(); 6001 6002 if (!flush_l1d) 6003 return; 6004 } 6005 6006 vcpu->stat.l1d_flush++; 6007 6008 if (static_cpu_has(X86_FEATURE_FLUSH_L1D)) { 6009 wrmsrl(MSR_IA32_FLUSH_CMD, L1D_FLUSH); 6010 return; 6011 } 6012 6013 asm volatile( 6014 /* First ensure the pages are in the TLB */ 6015 "xorl %%eax, %%eax\n" 6016 ".Lpopulate_tlb:\n\t" 6017 "movzbl (%[flush_pages], %%" _ASM_AX "), %%ecx\n\t" 6018 "addl $4096, %%eax\n\t" 6019 "cmpl %%eax, %[size]\n\t" 6020 "jne .Lpopulate_tlb\n\t" 6021 "xorl %%eax, %%eax\n\t" 6022 "cpuid\n\t" 6023 /* Now fill the cache */ 6024 "xorl %%eax, %%eax\n" 6025 ".Lfill_cache:\n" 6026 "movzbl (%[flush_pages], %%" _ASM_AX "), %%ecx\n\t" 6027 "addl $64, %%eax\n\t" 6028 "cmpl %%eax, %[size]\n\t" 6029 "jne .Lfill_cache\n\t" 6030 "lfence\n" 6031 :: [flush_pages] "r" (vmx_l1d_flush_pages), 6032 [size] "r" (size) 6033 : "eax", "ebx", "ecx", "edx"); 6034 } 6035 6036 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr) 6037 { 6038 struct vmcs12 *vmcs12 = get_vmcs12(vcpu); 6039 int tpr_threshold; 6040 6041 if (is_guest_mode(vcpu) && 6042 nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW)) 6043 return; 6044 6045 tpr_threshold = (irr == -1 || tpr < irr) ? 0 : irr; 6046 if (is_guest_mode(vcpu)) 6047 to_vmx(vcpu)->nested.l1_tpr_threshold = tpr_threshold; 6048 else 6049 vmcs_write32(TPR_THRESHOLD, tpr_threshold); 6050 } 6051 6052 void vmx_set_virtual_apic_mode(struct kvm_vcpu *vcpu) 6053 { 6054 struct vcpu_vmx *vmx = to_vmx(vcpu); 6055 u32 sec_exec_control; 6056 6057 if (!lapic_in_kernel(vcpu)) 6058 return; 6059 6060 if (!flexpriority_enabled && 6061 !cpu_has_vmx_virtualize_x2apic_mode()) 6062 return; 6063 6064 /* Postpone execution until vmcs01 is the current VMCS. */ 6065 if (is_guest_mode(vcpu)) { 6066 vmx->nested.change_vmcs01_virtual_apic_mode = true; 6067 return; 6068 } 6069 6070 sec_exec_control = secondary_exec_controls_get(vmx); 6071 sec_exec_control &= ~(SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 6072 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE); 6073 6074 switch (kvm_get_apic_mode(vcpu)) { 6075 case LAPIC_MODE_INVALID: 6076 WARN_ONCE(true, "Invalid local APIC state"); 6077 case LAPIC_MODE_DISABLED: 6078 break; 6079 case LAPIC_MODE_XAPIC: 6080 if (flexpriority_enabled) { 6081 sec_exec_control |= 6082 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES; 6083 vmx_flush_tlb(vcpu, true); 6084 } 6085 break; 6086 case LAPIC_MODE_X2APIC: 6087 if (cpu_has_vmx_virtualize_x2apic_mode()) 6088 sec_exec_control |= 6089 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE; 6090 break; 6091 } 6092 secondary_exec_controls_set(vmx, sec_exec_control); 6093 6094 vmx_update_msr_bitmap(vcpu); 6095 } 6096 6097 static void vmx_set_apic_access_page_addr(struct kvm_vcpu *vcpu, hpa_t hpa) 6098 { 6099 if (!is_guest_mode(vcpu)) { 6100 vmcs_write64(APIC_ACCESS_ADDR, hpa); 6101 vmx_flush_tlb(vcpu, true); 6102 } 6103 } 6104 6105 static void vmx_hwapic_isr_update(struct kvm_vcpu *vcpu, int max_isr) 6106 { 6107 u16 status; 6108 u8 old; 6109 6110 if (max_isr == -1) 6111 max_isr = 0; 6112 6113 status = vmcs_read16(GUEST_INTR_STATUS); 6114 old = status >> 8; 6115 if (max_isr != old) { 6116 status &= 0xff; 6117 status |= max_isr << 8; 6118 vmcs_write16(GUEST_INTR_STATUS, status); 6119 } 6120 } 6121 6122 static void vmx_set_rvi(int vector) 6123 { 6124 u16 status; 6125 u8 old; 6126 6127 if (vector == -1) 6128 vector = 0; 6129 6130 status = vmcs_read16(GUEST_INTR_STATUS); 6131 old = (u8)status & 0xff; 6132 if ((u8)vector != old) { 6133 status &= ~0xff; 6134 status |= (u8)vector; 6135 vmcs_write16(GUEST_INTR_STATUS, status); 6136 } 6137 } 6138 6139 static void vmx_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr) 6140 { 6141 /* 6142 * When running L2, updating RVI is only relevant when 6143 * vmcs12 virtual-interrupt-delivery enabled. 6144 * However, it can be enabled only when L1 also 6145 * intercepts external-interrupts and in that case 6146 * we should not update vmcs02 RVI but instead intercept 6147 * interrupt. Therefore, do nothing when running L2. 6148 */ 6149 if (!is_guest_mode(vcpu)) 6150 vmx_set_rvi(max_irr); 6151 } 6152 6153 static int vmx_sync_pir_to_irr(struct kvm_vcpu *vcpu) 6154 { 6155 struct vcpu_vmx *vmx = to_vmx(vcpu); 6156 int max_irr; 6157 bool max_irr_updated; 6158 6159 WARN_ON(!vcpu->arch.apicv_active); 6160 if (pi_test_on(&vmx->pi_desc)) { 6161 pi_clear_on(&vmx->pi_desc); 6162 /* 6163 * IOMMU can write to PID.ON, so the barrier matters even on UP. 6164 * But on x86 this is just a compiler barrier anyway. 6165 */ 6166 smp_mb__after_atomic(); 6167 max_irr_updated = 6168 kvm_apic_update_irr(vcpu, vmx->pi_desc.pir, &max_irr); 6169 6170 /* 6171 * If we are running L2 and L1 has a new pending interrupt 6172 * which can be injected, we should re-evaluate 6173 * what should be done with this new L1 interrupt. 6174 * If L1 intercepts external-interrupts, we should 6175 * exit from L2 to L1. Otherwise, interrupt should be 6176 * delivered directly to L2. 6177 */ 6178 if (is_guest_mode(vcpu) && max_irr_updated) { 6179 if (nested_exit_on_intr(vcpu)) 6180 kvm_vcpu_exiting_guest_mode(vcpu); 6181 else 6182 kvm_make_request(KVM_REQ_EVENT, vcpu); 6183 } 6184 } else { 6185 max_irr = kvm_lapic_find_highest_irr(vcpu); 6186 } 6187 vmx_hwapic_irr_update(vcpu, max_irr); 6188 return max_irr; 6189 } 6190 6191 static bool vmx_dy_apicv_has_pending_interrupt(struct kvm_vcpu *vcpu) 6192 { 6193 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu); 6194 6195 return pi_test_on(pi_desc) || 6196 (pi_test_sn(pi_desc) && !pi_is_pir_empty(pi_desc)); 6197 } 6198 6199 static void vmx_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap) 6200 { 6201 if (!kvm_vcpu_apicv_active(vcpu)) 6202 return; 6203 6204 vmcs_write64(EOI_EXIT_BITMAP0, eoi_exit_bitmap[0]); 6205 vmcs_write64(EOI_EXIT_BITMAP1, eoi_exit_bitmap[1]); 6206 vmcs_write64(EOI_EXIT_BITMAP2, eoi_exit_bitmap[2]); 6207 vmcs_write64(EOI_EXIT_BITMAP3, eoi_exit_bitmap[3]); 6208 } 6209 6210 static void vmx_apicv_post_state_restore(struct kvm_vcpu *vcpu) 6211 { 6212 struct vcpu_vmx *vmx = to_vmx(vcpu); 6213 6214 pi_clear_on(&vmx->pi_desc); 6215 memset(vmx->pi_desc.pir, 0, sizeof(vmx->pi_desc.pir)); 6216 } 6217 6218 static void handle_exception_nmi_irqoff(struct vcpu_vmx *vmx) 6219 { 6220 vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO); 6221 6222 /* if exit due to PF check for async PF */ 6223 if (is_page_fault(vmx->exit_intr_info)) { 6224 vmx->vcpu.arch.apf.host_apf_reason = kvm_read_and_reset_pf_reason(); 6225 /* Handle machine checks before interrupts are enabled */ 6226 } else if (is_machine_check(vmx->exit_intr_info)) { 6227 kvm_machine_check(); 6228 /* We need to handle NMIs before interrupts are enabled */ 6229 } else if (is_nmi(vmx->exit_intr_info)) { 6230 kvm_before_interrupt(&vmx->vcpu); 6231 asm("int $2"); 6232 kvm_after_interrupt(&vmx->vcpu); 6233 } 6234 } 6235 6236 static void handle_external_interrupt_irqoff(struct kvm_vcpu *vcpu) 6237 { 6238 unsigned int vector; 6239 unsigned long entry; 6240 #ifdef CONFIG_X86_64 6241 unsigned long tmp; 6242 #endif 6243 gate_desc *desc; 6244 u32 intr_info; 6245 6246 intr_info = vmcs_read32(VM_EXIT_INTR_INFO); 6247 if (WARN_ONCE(!is_external_intr(intr_info), 6248 "KVM: unexpected VM-Exit interrupt info: 0x%x", intr_info)) 6249 return; 6250 6251 vector = intr_info & INTR_INFO_VECTOR_MASK; 6252 desc = (gate_desc *)host_idt_base + vector; 6253 entry = gate_offset(desc); 6254 6255 kvm_before_interrupt(vcpu); 6256 6257 asm volatile( 6258 #ifdef CONFIG_X86_64 6259 "mov %%" _ASM_SP ", %[sp]\n\t" 6260 "and $0xfffffffffffffff0, %%" _ASM_SP "\n\t" 6261 "push $%c[ss]\n\t" 6262 "push %[sp]\n\t" 6263 #endif 6264 "pushf\n\t" 6265 __ASM_SIZE(push) " $%c[cs]\n\t" 6266 CALL_NOSPEC 6267 : 6268 #ifdef CONFIG_X86_64 6269 [sp]"=&r"(tmp), 6270 #endif 6271 ASM_CALL_CONSTRAINT 6272 : 6273 [thunk_target]"r"(entry), 6274 [ss]"i"(__KERNEL_DS), 6275 [cs]"i"(__KERNEL_CS) 6276 ); 6277 6278 kvm_after_interrupt(vcpu); 6279 } 6280 STACK_FRAME_NON_STANDARD(handle_external_interrupt_irqoff); 6281 6282 static void vmx_handle_exit_irqoff(struct kvm_vcpu *vcpu, 6283 enum exit_fastpath_completion *exit_fastpath) 6284 { 6285 struct vcpu_vmx *vmx = to_vmx(vcpu); 6286 6287 if (vmx->exit_reason == EXIT_REASON_EXTERNAL_INTERRUPT) 6288 handle_external_interrupt_irqoff(vcpu); 6289 else if (vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI) 6290 handle_exception_nmi_irqoff(vmx); 6291 else if (!is_guest_mode(vcpu) && 6292 vmx->exit_reason == EXIT_REASON_MSR_WRITE) 6293 *exit_fastpath = handle_fastpath_set_msr_irqoff(vcpu); 6294 } 6295 6296 static bool vmx_has_emulated_msr(int index) 6297 { 6298 switch (index) { 6299 case MSR_IA32_SMBASE: 6300 /* 6301 * We cannot do SMM unless we can run the guest in big 6302 * real mode. 6303 */ 6304 return enable_unrestricted_guest || emulate_invalid_guest_state; 6305 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC: 6306 return nested; 6307 case MSR_AMD64_VIRT_SPEC_CTRL: 6308 /* This is AMD only. */ 6309 return false; 6310 default: 6311 return true; 6312 } 6313 } 6314 6315 static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx) 6316 { 6317 u32 exit_intr_info; 6318 bool unblock_nmi; 6319 u8 vector; 6320 bool idtv_info_valid; 6321 6322 idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK; 6323 6324 if (enable_vnmi) { 6325 if (vmx->loaded_vmcs->nmi_known_unmasked) 6326 return; 6327 /* 6328 * Can't use vmx->exit_intr_info since we're not sure what 6329 * the exit reason is. 6330 */ 6331 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO); 6332 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0; 6333 vector = exit_intr_info & INTR_INFO_VECTOR_MASK; 6334 /* 6335 * SDM 3: 27.7.1.2 (September 2008) 6336 * Re-set bit "block by NMI" before VM entry if vmexit caused by 6337 * a guest IRET fault. 6338 * SDM 3: 23.2.2 (September 2008) 6339 * Bit 12 is undefined in any of the following cases: 6340 * If the VM exit sets the valid bit in the IDT-vectoring 6341 * information field. 6342 * If the VM exit is due to a double fault. 6343 */ 6344 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi && 6345 vector != DF_VECTOR && !idtv_info_valid) 6346 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, 6347 GUEST_INTR_STATE_NMI); 6348 else 6349 vmx->loaded_vmcs->nmi_known_unmasked = 6350 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) 6351 & GUEST_INTR_STATE_NMI); 6352 } else if (unlikely(vmx->loaded_vmcs->soft_vnmi_blocked)) 6353 vmx->loaded_vmcs->vnmi_blocked_time += 6354 ktime_to_ns(ktime_sub(ktime_get(), 6355 vmx->loaded_vmcs->entry_time)); 6356 } 6357 6358 static void __vmx_complete_interrupts(struct kvm_vcpu *vcpu, 6359 u32 idt_vectoring_info, 6360 int instr_len_field, 6361 int error_code_field) 6362 { 6363 u8 vector; 6364 int type; 6365 bool idtv_info_valid; 6366 6367 idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK; 6368 6369 vcpu->arch.nmi_injected = false; 6370 kvm_clear_exception_queue(vcpu); 6371 kvm_clear_interrupt_queue(vcpu); 6372 6373 if (!idtv_info_valid) 6374 return; 6375 6376 kvm_make_request(KVM_REQ_EVENT, vcpu); 6377 6378 vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK; 6379 type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK; 6380 6381 switch (type) { 6382 case INTR_TYPE_NMI_INTR: 6383 vcpu->arch.nmi_injected = true; 6384 /* 6385 * SDM 3: 27.7.1.2 (September 2008) 6386 * Clear bit "block by NMI" before VM entry if a NMI 6387 * delivery faulted. 6388 */ 6389 vmx_set_nmi_mask(vcpu, false); 6390 break; 6391 case INTR_TYPE_SOFT_EXCEPTION: 6392 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field); 6393 /* fall through */ 6394 case INTR_TYPE_HARD_EXCEPTION: 6395 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) { 6396 u32 err = vmcs_read32(error_code_field); 6397 kvm_requeue_exception_e(vcpu, vector, err); 6398 } else 6399 kvm_requeue_exception(vcpu, vector); 6400 break; 6401 case INTR_TYPE_SOFT_INTR: 6402 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field); 6403 /* fall through */ 6404 case INTR_TYPE_EXT_INTR: 6405 kvm_queue_interrupt(vcpu, vector, type == INTR_TYPE_SOFT_INTR); 6406 break; 6407 default: 6408 break; 6409 } 6410 } 6411 6412 static void vmx_complete_interrupts(struct vcpu_vmx *vmx) 6413 { 6414 __vmx_complete_interrupts(&vmx->vcpu, vmx->idt_vectoring_info, 6415 VM_EXIT_INSTRUCTION_LEN, 6416 IDT_VECTORING_ERROR_CODE); 6417 } 6418 6419 static void vmx_cancel_injection(struct kvm_vcpu *vcpu) 6420 { 6421 __vmx_complete_interrupts(vcpu, 6422 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD), 6423 VM_ENTRY_INSTRUCTION_LEN, 6424 VM_ENTRY_EXCEPTION_ERROR_CODE); 6425 6426 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); 6427 } 6428 6429 static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx) 6430 { 6431 int i, nr_msrs; 6432 struct perf_guest_switch_msr *msrs; 6433 6434 msrs = perf_guest_get_msrs(&nr_msrs); 6435 6436 if (!msrs) 6437 return; 6438 6439 for (i = 0; i < nr_msrs; i++) 6440 if (msrs[i].host == msrs[i].guest) 6441 clear_atomic_switch_msr(vmx, msrs[i].msr); 6442 else 6443 add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest, 6444 msrs[i].host, false); 6445 } 6446 6447 static void atomic_switch_umwait_control_msr(struct vcpu_vmx *vmx) 6448 { 6449 u32 host_umwait_control; 6450 6451 if (!vmx_has_waitpkg(vmx)) 6452 return; 6453 6454 host_umwait_control = get_umwait_control_msr(); 6455 6456 if (vmx->msr_ia32_umwait_control != host_umwait_control) 6457 add_atomic_switch_msr(vmx, MSR_IA32_UMWAIT_CONTROL, 6458 vmx->msr_ia32_umwait_control, 6459 host_umwait_control, false); 6460 else 6461 clear_atomic_switch_msr(vmx, MSR_IA32_UMWAIT_CONTROL); 6462 } 6463 6464 static void vmx_update_hv_timer(struct kvm_vcpu *vcpu) 6465 { 6466 struct vcpu_vmx *vmx = to_vmx(vcpu); 6467 u64 tscl; 6468 u32 delta_tsc; 6469 6470 if (vmx->req_immediate_exit) { 6471 vmcs_write32(VMX_PREEMPTION_TIMER_VALUE, 0); 6472 vmx->loaded_vmcs->hv_timer_soft_disabled = false; 6473 } else if (vmx->hv_deadline_tsc != -1) { 6474 tscl = rdtsc(); 6475 if (vmx->hv_deadline_tsc > tscl) 6476 /* set_hv_timer ensures the delta fits in 32-bits */ 6477 delta_tsc = (u32)((vmx->hv_deadline_tsc - tscl) >> 6478 cpu_preemption_timer_multi); 6479 else 6480 delta_tsc = 0; 6481 6482 vmcs_write32(VMX_PREEMPTION_TIMER_VALUE, delta_tsc); 6483 vmx->loaded_vmcs->hv_timer_soft_disabled = false; 6484 } else if (!vmx->loaded_vmcs->hv_timer_soft_disabled) { 6485 vmcs_write32(VMX_PREEMPTION_TIMER_VALUE, -1); 6486 vmx->loaded_vmcs->hv_timer_soft_disabled = true; 6487 } 6488 } 6489 6490 void vmx_update_host_rsp(struct vcpu_vmx *vmx, unsigned long host_rsp) 6491 { 6492 if (unlikely(host_rsp != vmx->loaded_vmcs->host_state.rsp)) { 6493 vmx->loaded_vmcs->host_state.rsp = host_rsp; 6494 vmcs_writel(HOST_RSP, host_rsp); 6495 } 6496 } 6497 6498 bool __vmx_vcpu_run(struct vcpu_vmx *vmx, unsigned long *regs, bool launched); 6499 6500 static void vmx_vcpu_run(struct kvm_vcpu *vcpu) 6501 { 6502 struct vcpu_vmx *vmx = to_vmx(vcpu); 6503 unsigned long cr3, cr4; 6504 6505 /* Record the guest's net vcpu time for enforced NMI injections. */ 6506 if (unlikely(!enable_vnmi && 6507 vmx->loaded_vmcs->soft_vnmi_blocked)) 6508 vmx->loaded_vmcs->entry_time = ktime_get(); 6509 6510 /* Don't enter VMX if guest state is invalid, let the exit handler 6511 start emulation until we arrive back to a valid state */ 6512 if (vmx->emulation_required) 6513 return; 6514 6515 if (vmx->ple_window_dirty) { 6516 vmx->ple_window_dirty = false; 6517 vmcs_write32(PLE_WINDOW, vmx->ple_window); 6518 } 6519 6520 /* 6521 * We did this in prepare_switch_to_guest, because it needs to 6522 * be within srcu_read_lock. 6523 */ 6524 WARN_ON_ONCE(vmx->nested.need_vmcs12_to_shadow_sync); 6525 6526 if (kvm_register_is_dirty(vcpu, VCPU_REGS_RSP)) 6527 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]); 6528 if (kvm_register_is_dirty(vcpu, VCPU_REGS_RIP)) 6529 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]); 6530 6531 cr3 = __get_current_cr3_fast(); 6532 if (unlikely(cr3 != vmx->loaded_vmcs->host_state.cr3)) { 6533 vmcs_writel(HOST_CR3, cr3); 6534 vmx->loaded_vmcs->host_state.cr3 = cr3; 6535 } 6536 6537 cr4 = cr4_read_shadow(); 6538 if (unlikely(cr4 != vmx->loaded_vmcs->host_state.cr4)) { 6539 vmcs_writel(HOST_CR4, cr4); 6540 vmx->loaded_vmcs->host_state.cr4 = cr4; 6541 } 6542 6543 /* When single-stepping over STI and MOV SS, we must clear the 6544 * corresponding interruptibility bits in the guest state. Otherwise 6545 * vmentry fails as it then expects bit 14 (BS) in pending debug 6546 * exceptions being set, but that's not correct for the guest debugging 6547 * case. */ 6548 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) 6549 vmx_set_interrupt_shadow(vcpu, 0); 6550 6551 kvm_load_guest_xsave_state(vcpu); 6552 6553 if (static_cpu_has(X86_FEATURE_PKU) && 6554 kvm_read_cr4_bits(vcpu, X86_CR4_PKE) && 6555 vcpu->arch.pkru != vmx->host_pkru) 6556 __write_pkru(vcpu->arch.pkru); 6557 6558 pt_guest_enter(vmx); 6559 6560 if (vcpu_to_pmu(vcpu)->version) 6561 atomic_switch_perf_msrs(vmx); 6562 atomic_switch_umwait_control_msr(vmx); 6563 6564 if (enable_preemption_timer) 6565 vmx_update_hv_timer(vcpu); 6566 6567 if (lapic_in_kernel(vcpu) && 6568 vcpu->arch.apic->lapic_timer.timer_advance_ns) 6569 kvm_wait_lapic_expire(vcpu); 6570 6571 /* 6572 * If this vCPU has touched SPEC_CTRL, restore the guest's value if 6573 * it's non-zero. Since vmentry is serialising on affected CPUs, there 6574 * is no need to worry about the conditional branch over the wrmsr 6575 * being speculatively taken. 6576 */ 6577 x86_spec_ctrl_set_guest(vmx->spec_ctrl, 0); 6578 6579 /* L1D Flush includes CPU buffer clear to mitigate MDS */ 6580 if (static_branch_unlikely(&vmx_l1d_should_flush)) 6581 vmx_l1d_flush(vcpu); 6582 else if (static_branch_unlikely(&mds_user_clear)) 6583 mds_clear_cpu_buffers(); 6584 6585 if (vcpu->arch.cr2 != read_cr2()) 6586 write_cr2(vcpu->arch.cr2); 6587 6588 vmx->fail = __vmx_vcpu_run(vmx, (unsigned long *)&vcpu->arch.regs, 6589 vmx->loaded_vmcs->launched); 6590 6591 vcpu->arch.cr2 = read_cr2(); 6592 6593 /* 6594 * We do not use IBRS in the kernel. If this vCPU has used the 6595 * SPEC_CTRL MSR it may have left it on; save the value and 6596 * turn it off. This is much more efficient than blindly adding 6597 * it to the atomic save/restore list. Especially as the former 6598 * (Saving guest MSRs on vmexit) doesn't even exist in KVM. 6599 * 6600 * For non-nested case: 6601 * If the L01 MSR bitmap does not intercept the MSR, then we need to 6602 * save it. 6603 * 6604 * For nested case: 6605 * If the L02 MSR bitmap does not intercept the MSR, then we need to 6606 * save it. 6607 */ 6608 if (unlikely(!msr_write_intercepted(vcpu, MSR_IA32_SPEC_CTRL))) 6609 vmx->spec_ctrl = native_read_msr(MSR_IA32_SPEC_CTRL); 6610 6611 x86_spec_ctrl_restore_host(vmx->spec_ctrl, 0); 6612 6613 /* All fields are clean at this point */ 6614 if (static_branch_unlikely(&enable_evmcs)) 6615 current_evmcs->hv_clean_fields |= 6616 HV_VMX_ENLIGHTENED_CLEAN_FIELD_ALL; 6617 6618 if (static_branch_unlikely(&enable_evmcs)) 6619 current_evmcs->hv_vp_id = vcpu->arch.hyperv.vp_index; 6620 6621 /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */ 6622 if (vmx->host_debugctlmsr) 6623 update_debugctlmsr(vmx->host_debugctlmsr); 6624 6625 #ifndef CONFIG_X86_64 6626 /* 6627 * The sysexit path does not restore ds/es, so we must set them to 6628 * a reasonable value ourselves. 6629 * 6630 * We can't defer this to vmx_prepare_switch_to_host() since that 6631 * function may be executed in interrupt context, which saves and 6632 * restore segments around it, nullifying its effect. 6633 */ 6634 loadsegment(ds, __USER_DS); 6635 loadsegment(es, __USER_DS); 6636 #endif 6637 6638 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP) 6639 | (1 << VCPU_EXREG_RFLAGS) 6640 | (1 << VCPU_EXREG_PDPTR) 6641 | (1 << VCPU_EXREG_SEGMENTS) 6642 | (1 << VCPU_EXREG_CR3)); 6643 vcpu->arch.regs_dirty = 0; 6644 6645 pt_guest_exit(vmx); 6646 6647 /* 6648 * eager fpu is enabled if PKEY is supported and CR4 is switched 6649 * back on host, so it is safe to read guest PKRU from current 6650 * XSAVE. 6651 */ 6652 if (static_cpu_has(X86_FEATURE_PKU) && 6653 kvm_read_cr4_bits(vcpu, X86_CR4_PKE)) { 6654 vcpu->arch.pkru = rdpkru(); 6655 if (vcpu->arch.pkru != vmx->host_pkru) 6656 __write_pkru(vmx->host_pkru); 6657 } 6658 6659 kvm_load_host_xsave_state(vcpu); 6660 6661 vmx->nested.nested_run_pending = 0; 6662 vmx->idt_vectoring_info = 0; 6663 6664 vmx->exit_reason = vmx->fail ? 0xdead : vmcs_read32(VM_EXIT_REASON); 6665 if ((u16)vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY) 6666 kvm_machine_check(); 6667 6668 if (vmx->fail || (vmx->exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY)) 6669 return; 6670 6671 vmx->loaded_vmcs->launched = 1; 6672 vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD); 6673 6674 vmx_recover_nmi_blocking(vmx); 6675 vmx_complete_interrupts(vmx); 6676 } 6677 6678 static void vmx_free_vcpu(struct kvm_vcpu *vcpu) 6679 { 6680 struct vcpu_vmx *vmx = to_vmx(vcpu); 6681 6682 if (enable_pml) 6683 vmx_destroy_pml_buffer(vmx); 6684 free_vpid(vmx->vpid); 6685 nested_vmx_free_vcpu(vcpu); 6686 free_loaded_vmcs(vmx->loaded_vmcs); 6687 } 6688 6689 static int vmx_create_vcpu(struct kvm_vcpu *vcpu) 6690 { 6691 struct vcpu_vmx *vmx; 6692 unsigned long *msr_bitmap; 6693 int i, cpu, err; 6694 6695 BUILD_BUG_ON(offsetof(struct vcpu_vmx, vcpu) != 0); 6696 vmx = to_vmx(vcpu); 6697 6698 err = -ENOMEM; 6699 6700 vmx->vpid = allocate_vpid(); 6701 6702 /* 6703 * If PML is turned on, failure on enabling PML just results in failure 6704 * of creating the vcpu, therefore we can simplify PML logic (by 6705 * avoiding dealing with cases, such as enabling PML partially on vcpus 6706 * for the guest), etc. 6707 */ 6708 if (enable_pml) { 6709 vmx->pml_pg = alloc_page(GFP_KERNEL_ACCOUNT | __GFP_ZERO); 6710 if (!vmx->pml_pg) 6711 goto free_vpid; 6712 } 6713 6714 BUILD_BUG_ON(ARRAY_SIZE(vmx_msr_index) != NR_SHARED_MSRS); 6715 6716 for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i) { 6717 u32 index = vmx_msr_index[i]; 6718 u32 data_low, data_high; 6719 int j = vmx->nmsrs; 6720 6721 if (rdmsr_safe(index, &data_low, &data_high) < 0) 6722 continue; 6723 if (wrmsr_safe(index, data_low, data_high) < 0) 6724 continue; 6725 6726 vmx->guest_msrs[j].index = i; 6727 vmx->guest_msrs[j].data = 0; 6728 switch (index) { 6729 case MSR_IA32_TSX_CTRL: 6730 /* 6731 * No need to pass TSX_CTRL_CPUID_CLEAR through, so 6732 * let's avoid changing CPUID bits under the host 6733 * kernel's feet. 6734 */ 6735 vmx->guest_msrs[j].mask = ~(u64)TSX_CTRL_CPUID_CLEAR; 6736 break; 6737 default: 6738 vmx->guest_msrs[j].mask = -1ull; 6739 break; 6740 } 6741 ++vmx->nmsrs; 6742 } 6743 6744 err = alloc_loaded_vmcs(&vmx->vmcs01); 6745 if (err < 0) 6746 goto free_pml; 6747 6748 msr_bitmap = vmx->vmcs01.msr_bitmap; 6749 vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_TSC, MSR_TYPE_R); 6750 vmx_disable_intercept_for_msr(msr_bitmap, MSR_FS_BASE, MSR_TYPE_RW); 6751 vmx_disable_intercept_for_msr(msr_bitmap, MSR_GS_BASE, MSR_TYPE_RW); 6752 vmx_disable_intercept_for_msr(msr_bitmap, MSR_KERNEL_GS_BASE, MSR_TYPE_RW); 6753 vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_SYSENTER_CS, MSR_TYPE_RW); 6754 vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_SYSENTER_ESP, MSR_TYPE_RW); 6755 vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_SYSENTER_EIP, MSR_TYPE_RW); 6756 if (kvm_cstate_in_guest(vcpu->kvm)) { 6757 vmx_disable_intercept_for_msr(msr_bitmap, MSR_CORE_C1_RES, MSR_TYPE_R); 6758 vmx_disable_intercept_for_msr(msr_bitmap, MSR_CORE_C3_RESIDENCY, MSR_TYPE_R); 6759 vmx_disable_intercept_for_msr(msr_bitmap, MSR_CORE_C6_RESIDENCY, MSR_TYPE_R); 6760 vmx_disable_intercept_for_msr(msr_bitmap, MSR_CORE_C7_RESIDENCY, MSR_TYPE_R); 6761 } 6762 vmx->msr_bitmap_mode = 0; 6763 6764 vmx->loaded_vmcs = &vmx->vmcs01; 6765 cpu = get_cpu(); 6766 vmx_vcpu_load(vcpu, cpu); 6767 vcpu->cpu = cpu; 6768 init_vmcs(vmx); 6769 vmx_vcpu_put(vcpu); 6770 put_cpu(); 6771 if (cpu_need_virtualize_apic_accesses(vcpu)) { 6772 err = alloc_apic_access_page(vcpu->kvm); 6773 if (err) 6774 goto free_vmcs; 6775 } 6776 6777 if (enable_ept && !enable_unrestricted_guest) { 6778 err = init_rmode_identity_map(vcpu->kvm); 6779 if (err) 6780 goto free_vmcs; 6781 } 6782 6783 if (nested) 6784 nested_vmx_setup_ctls_msrs(&vmx->nested.msrs, 6785 vmx_capability.ept); 6786 else 6787 memset(&vmx->nested.msrs, 0, sizeof(vmx->nested.msrs)); 6788 6789 vmx->nested.posted_intr_nv = -1; 6790 vmx->nested.current_vmptr = -1ull; 6791 6792 vcpu->arch.microcode_version = 0x100000000ULL; 6793 vmx->msr_ia32_feature_control_valid_bits = FEAT_CTL_LOCKED; 6794 6795 /* 6796 * Enforce invariant: pi_desc.nv is always either POSTED_INTR_VECTOR 6797 * or POSTED_INTR_WAKEUP_VECTOR. 6798 */ 6799 vmx->pi_desc.nv = POSTED_INTR_VECTOR; 6800 vmx->pi_desc.sn = 1; 6801 6802 vmx->ept_pointer = INVALID_PAGE; 6803 6804 return 0; 6805 6806 free_vmcs: 6807 free_loaded_vmcs(vmx->loaded_vmcs); 6808 free_pml: 6809 vmx_destroy_pml_buffer(vmx); 6810 free_vpid: 6811 free_vpid(vmx->vpid); 6812 return err; 6813 } 6814 6815 #define L1TF_MSG_SMT "L1TF CPU bug present and SMT on, data leak possible. See CVE-2018-3646 and https://www.kernel.org/doc/html/latest/admin-guide/hw-vuln/l1tf.html for details.\n" 6816 #define L1TF_MSG_L1D "L1TF CPU bug present and virtualization mitigation disabled, data leak possible. See CVE-2018-3646 and https://www.kernel.org/doc/html/latest/admin-guide/hw-vuln/l1tf.html for details.\n" 6817 6818 static int vmx_vm_init(struct kvm *kvm) 6819 { 6820 spin_lock_init(&to_kvm_vmx(kvm)->ept_pointer_lock); 6821 6822 if (!ple_gap) 6823 kvm->arch.pause_in_guest = true; 6824 6825 if (boot_cpu_has(X86_BUG_L1TF) && enable_ept) { 6826 switch (l1tf_mitigation) { 6827 case L1TF_MITIGATION_OFF: 6828 case L1TF_MITIGATION_FLUSH_NOWARN: 6829 /* 'I explicitly don't care' is set */ 6830 break; 6831 case L1TF_MITIGATION_FLUSH: 6832 case L1TF_MITIGATION_FLUSH_NOSMT: 6833 case L1TF_MITIGATION_FULL: 6834 /* 6835 * Warn upon starting the first VM in a potentially 6836 * insecure environment. 6837 */ 6838 if (sched_smt_active()) 6839 pr_warn_once(L1TF_MSG_SMT); 6840 if (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_NEVER) 6841 pr_warn_once(L1TF_MSG_L1D); 6842 break; 6843 case L1TF_MITIGATION_FULL_FORCE: 6844 /* Flush is enforced */ 6845 break; 6846 } 6847 } 6848 kvm_apicv_init(kvm, enable_apicv); 6849 return 0; 6850 } 6851 6852 static int __init vmx_check_processor_compat(void) 6853 { 6854 struct vmcs_config vmcs_conf; 6855 struct vmx_capability vmx_cap; 6856 6857 if (!this_cpu_has(X86_FEATURE_MSR_IA32_FEAT_CTL) || 6858 !this_cpu_has(X86_FEATURE_VMX)) { 6859 pr_err("kvm: VMX is disabled on CPU %d\n", smp_processor_id()); 6860 return -EIO; 6861 } 6862 6863 if (setup_vmcs_config(&vmcs_conf, &vmx_cap) < 0) 6864 return -EIO; 6865 if (nested) 6866 nested_vmx_setup_ctls_msrs(&vmcs_conf.nested, vmx_cap.ept); 6867 if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) { 6868 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n", 6869 smp_processor_id()); 6870 return -EIO; 6871 } 6872 return 0; 6873 } 6874 6875 static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio) 6876 { 6877 u8 cache; 6878 u64 ipat = 0; 6879 6880 /* We wanted to honor guest CD/MTRR/PAT, but doing so could result in 6881 * memory aliases with conflicting memory types and sometimes MCEs. 6882 * We have to be careful as to what are honored and when. 6883 * 6884 * For MMIO, guest CD/MTRR are ignored. The EPT memory type is set to 6885 * UC. The effective memory type is UC or WC depending on guest PAT. 6886 * This was historically the source of MCEs and we want to be 6887 * conservative. 6888 * 6889 * When there is no need to deal with noncoherent DMA (e.g., no VT-d 6890 * or VT-d has snoop control), guest CD/MTRR/PAT are all ignored. The 6891 * EPT memory type is set to WB. The effective memory type is forced 6892 * WB. 6893 * 6894 * Otherwise, we trust guest. Guest CD/MTRR/PAT are all honored. The 6895 * EPT memory type is used to emulate guest CD/MTRR. 6896 */ 6897 6898 if (is_mmio) { 6899 cache = MTRR_TYPE_UNCACHABLE; 6900 goto exit; 6901 } 6902 6903 if (!kvm_arch_has_noncoherent_dma(vcpu->kvm)) { 6904 ipat = VMX_EPT_IPAT_BIT; 6905 cache = MTRR_TYPE_WRBACK; 6906 goto exit; 6907 } 6908 6909 if (kvm_read_cr0(vcpu) & X86_CR0_CD) { 6910 ipat = VMX_EPT_IPAT_BIT; 6911 if (kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED)) 6912 cache = MTRR_TYPE_WRBACK; 6913 else 6914 cache = MTRR_TYPE_UNCACHABLE; 6915 goto exit; 6916 } 6917 6918 cache = kvm_mtrr_get_guest_memory_type(vcpu, gfn); 6919 6920 exit: 6921 return (cache << VMX_EPT_MT_EPTE_SHIFT) | ipat; 6922 } 6923 6924 static void vmcs_set_secondary_exec_control(struct vcpu_vmx *vmx) 6925 { 6926 /* 6927 * These bits in the secondary execution controls field 6928 * are dynamic, the others are mostly based on the hypervisor 6929 * architecture and the guest's CPUID. Do not touch the 6930 * dynamic bits. 6931 */ 6932 u32 mask = 6933 SECONDARY_EXEC_SHADOW_VMCS | 6934 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 6935 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 6936 SECONDARY_EXEC_DESC; 6937 6938 u32 new_ctl = vmx->secondary_exec_control; 6939 u32 cur_ctl = secondary_exec_controls_get(vmx); 6940 6941 secondary_exec_controls_set(vmx, (new_ctl & ~mask) | (cur_ctl & mask)); 6942 } 6943 6944 /* 6945 * Generate MSR_IA32_VMX_CR{0,4}_FIXED1 according to CPUID. Only set bits 6946 * (indicating "allowed-1") if they are supported in the guest's CPUID. 6947 */ 6948 static void nested_vmx_cr_fixed1_bits_update(struct kvm_vcpu *vcpu) 6949 { 6950 struct vcpu_vmx *vmx = to_vmx(vcpu); 6951 struct kvm_cpuid_entry2 *entry; 6952 6953 vmx->nested.msrs.cr0_fixed1 = 0xffffffff; 6954 vmx->nested.msrs.cr4_fixed1 = X86_CR4_PCE; 6955 6956 #define cr4_fixed1_update(_cr4_mask, _reg, _cpuid_mask) do { \ 6957 if (entry && (entry->_reg & (_cpuid_mask))) \ 6958 vmx->nested.msrs.cr4_fixed1 |= (_cr4_mask); \ 6959 } while (0) 6960 6961 entry = kvm_find_cpuid_entry(vcpu, 0x1, 0); 6962 cr4_fixed1_update(X86_CR4_VME, edx, feature_bit(VME)); 6963 cr4_fixed1_update(X86_CR4_PVI, edx, feature_bit(VME)); 6964 cr4_fixed1_update(X86_CR4_TSD, edx, feature_bit(TSC)); 6965 cr4_fixed1_update(X86_CR4_DE, edx, feature_bit(DE)); 6966 cr4_fixed1_update(X86_CR4_PSE, edx, feature_bit(PSE)); 6967 cr4_fixed1_update(X86_CR4_PAE, edx, feature_bit(PAE)); 6968 cr4_fixed1_update(X86_CR4_MCE, edx, feature_bit(MCE)); 6969 cr4_fixed1_update(X86_CR4_PGE, edx, feature_bit(PGE)); 6970 cr4_fixed1_update(X86_CR4_OSFXSR, edx, feature_bit(FXSR)); 6971 cr4_fixed1_update(X86_CR4_OSXMMEXCPT, edx, feature_bit(XMM)); 6972 cr4_fixed1_update(X86_CR4_VMXE, ecx, feature_bit(VMX)); 6973 cr4_fixed1_update(X86_CR4_SMXE, ecx, feature_bit(SMX)); 6974 cr4_fixed1_update(X86_CR4_PCIDE, ecx, feature_bit(PCID)); 6975 cr4_fixed1_update(X86_CR4_OSXSAVE, ecx, feature_bit(XSAVE)); 6976 6977 entry = kvm_find_cpuid_entry(vcpu, 0x7, 0); 6978 cr4_fixed1_update(X86_CR4_FSGSBASE, ebx, feature_bit(FSGSBASE)); 6979 cr4_fixed1_update(X86_CR4_SMEP, ebx, feature_bit(SMEP)); 6980 cr4_fixed1_update(X86_CR4_SMAP, ebx, feature_bit(SMAP)); 6981 cr4_fixed1_update(X86_CR4_PKE, ecx, feature_bit(PKU)); 6982 cr4_fixed1_update(X86_CR4_UMIP, ecx, feature_bit(UMIP)); 6983 cr4_fixed1_update(X86_CR4_LA57, ecx, feature_bit(LA57)); 6984 6985 #undef cr4_fixed1_update 6986 } 6987 6988 static void nested_vmx_entry_exit_ctls_update(struct kvm_vcpu *vcpu) 6989 { 6990 struct vcpu_vmx *vmx = to_vmx(vcpu); 6991 6992 if (kvm_mpx_supported()) { 6993 bool mpx_enabled = guest_cpuid_has(vcpu, X86_FEATURE_MPX); 6994 6995 if (mpx_enabled) { 6996 vmx->nested.msrs.entry_ctls_high |= VM_ENTRY_LOAD_BNDCFGS; 6997 vmx->nested.msrs.exit_ctls_high |= VM_EXIT_CLEAR_BNDCFGS; 6998 } else { 6999 vmx->nested.msrs.entry_ctls_high &= ~VM_ENTRY_LOAD_BNDCFGS; 7000 vmx->nested.msrs.exit_ctls_high &= ~VM_EXIT_CLEAR_BNDCFGS; 7001 } 7002 } 7003 } 7004 7005 static void update_intel_pt_cfg(struct kvm_vcpu *vcpu) 7006 { 7007 struct vcpu_vmx *vmx = to_vmx(vcpu); 7008 struct kvm_cpuid_entry2 *best = NULL; 7009 int i; 7010 7011 for (i = 0; i < PT_CPUID_LEAVES; i++) { 7012 best = kvm_find_cpuid_entry(vcpu, 0x14, i); 7013 if (!best) 7014 return; 7015 vmx->pt_desc.caps[CPUID_EAX + i*PT_CPUID_REGS_NUM] = best->eax; 7016 vmx->pt_desc.caps[CPUID_EBX + i*PT_CPUID_REGS_NUM] = best->ebx; 7017 vmx->pt_desc.caps[CPUID_ECX + i*PT_CPUID_REGS_NUM] = best->ecx; 7018 vmx->pt_desc.caps[CPUID_EDX + i*PT_CPUID_REGS_NUM] = best->edx; 7019 } 7020 7021 /* Get the number of configurable Address Ranges for filtering */ 7022 vmx->pt_desc.addr_range = intel_pt_validate_cap(vmx->pt_desc.caps, 7023 PT_CAP_num_address_ranges); 7024 7025 /* Initialize and clear the no dependency bits */ 7026 vmx->pt_desc.ctl_bitmask = ~(RTIT_CTL_TRACEEN | RTIT_CTL_OS | 7027 RTIT_CTL_USR | RTIT_CTL_TSC_EN | RTIT_CTL_DISRETC); 7028 7029 /* 7030 * If CPUID.(EAX=14H,ECX=0):EBX[0]=1 CR3Filter can be set otherwise 7031 * will inject an #GP 7032 */ 7033 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_cr3_filtering)) 7034 vmx->pt_desc.ctl_bitmask &= ~RTIT_CTL_CR3EN; 7035 7036 /* 7037 * If CPUID.(EAX=14H,ECX=0):EBX[1]=1 CYCEn, CycThresh and 7038 * PSBFreq can be set 7039 */ 7040 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_psb_cyc)) 7041 vmx->pt_desc.ctl_bitmask &= ~(RTIT_CTL_CYCLEACC | 7042 RTIT_CTL_CYC_THRESH | RTIT_CTL_PSB_FREQ); 7043 7044 /* 7045 * If CPUID.(EAX=14H,ECX=0):EBX[3]=1 MTCEn BranchEn and 7046 * MTCFreq can be set 7047 */ 7048 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_mtc)) 7049 vmx->pt_desc.ctl_bitmask &= ~(RTIT_CTL_MTC_EN | 7050 RTIT_CTL_BRANCH_EN | RTIT_CTL_MTC_RANGE); 7051 7052 /* If CPUID.(EAX=14H,ECX=0):EBX[4]=1 FUPonPTW and PTWEn can be set */ 7053 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_ptwrite)) 7054 vmx->pt_desc.ctl_bitmask &= ~(RTIT_CTL_FUP_ON_PTW | 7055 RTIT_CTL_PTW_EN); 7056 7057 /* If CPUID.(EAX=14H,ECX=0):EBX[5]=1 PwrEvEn can be set */ 7058 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_power_event_trace)) 7059 vmx->pt_desc.ctl_bitmask &= ~RTIT_CTL_PWR_EVT_EN; 7060 7061 /* If CPUID.(EAX=14H,ECX=0):ECX[0]=1 ToPA can be set */ 7062 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_topa_output)) 7063 vmx->pt_desc.ctl_bitmask &= ~RTIT_CTL_TOPA; 7064 7065 /* If CPUID.(EAX=14H,ECX=0):ECX[3]=1 FabircEn can be set */ 7066 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_output_subsys)) 7067 vmx->pt_desc.ctl_bitmask &= ~RTIT_CTL_FABRIC_EN; 7068 7069 /* unmask address range configure area */ 7070 for (i = 0; i < vmx->pt_desc.addr_range; i++) 7071 vmx->pt_desc.ctl_bitmask &= ~(0xfULL << (32 + i * 4)); 7072 } 7073 7074 static void vmx_cpuid_update(struct kvm_vcpu *vcpu) 7075 { 7076 struct vcpu_vmx *vmx = to_vmx(vcpu); 7077 7078 /* xsaves_enabled is recomputed in vmx_compute_secondary_exec_control(). */ 7079 vcpu->arch.xsaves_enabled = false; 7080 7081 if (cpu_has_secondary_exec_ctrls()) { 7082 vmx_compute_secondary_exec_control(vmx); 7083 vmcs_set_secondary_exec_control(vmx); 7084 } 7085 7086 if (nested_vmx_allowed(vcpu)) 7087 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits |= 7088 FEAT_CTL_VMX_ENABLED_INSIDE_SMX | 7089 FEAT_CTL_VMX_ENABLED_OUTSIDE_SMX; 7090 else 7091 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits &= 7092 ~(FEAT_CTL_VMX_ENABLED_INSIDE_SMX | 7093 FEAT_CTL_VMX_ENABLED_OUTSIDE_SMX); 7094 7095 if (nested_vmx_allowed(vcpu)) { 7096 nested_vmx_cr_fixed1_bits_update(vcpu); 7097 nested_vmx_entry_exit_ctls_update(vcpu); 7098 } 7099 7100 if (boot_cpu_has(X86_FEATURE_INTEL_PT) && 7101 guest_cpuid_has(vcpu, X86_FEATURE_INTEL_PT)) 7102 update_intel_pt_cfg(vcpu); 7103 7104 if (boot_cpu_has(X86_FEATURE_RTM)) { 7105 struct shared_msr_entry *msr; 7106 msr = find_msr_entry(vmx, MSR_IA32_TSX_CTRL); 7107 if (msr) { 7108 bool enabled = guest_cpuid_has(vcpu, X86_FEATURE_RTM); 7109 vmx_set_guest_msr(vmx, msr, enabled ? 0 : TSX_CTRL_RTM_DISABLE); 7110 } 7111 } 7112 } 7113 7114 static __init void vmx_set_cpu_caps(void) 7115 { 7116 kvm_set_cpu_caps(); 7117 7118 /* CPUID 0x1 */ 7119 if (nested) 7120 kvm_cpu_cap_set(X86_FEATURE_VMX); 7121 7122 /* CPUID 0x7 */ 7123 if (kvm_mpx_supported()) 7124 kvm_cpu_cap_check_and_set(X86_FEATURE_MPX); 7125 if (cpu_has_vmx_invpcid()) 7126 kvm_cpu_cap_check_and_set(X86_FEATURE_INVPCID); 7127 if (vmx_pt_mode_is_host_guest()) 7128 kvm_cpu_cap_check_and_set(X86_FEATURE_INTEL_PT); 7129 7130 /* PKU is not yet implemented for shadow paging. */ 7131 if (enable_ept && boot_cpu_has(X86_FEATURE_OSPKE)) 7132 kvm_cpu_cap_check_and_set(X86_FEATURE_PKU); 7133 7134 if (vmx_umip_emulated()) 7135 kvm_cpu_cap_set(X86_FEATURE_UMIP); 7136 7137 /* CPUID 0xD.1 */ 7138 supported_xss = 0; 7139 if (!vmx_xsaves_supported()) 7140 kvm_cpu_cap_clear(X86_FEATURE_XSAVES); 7141 7142 /* CPUID 0x80000001 */ 7143 if (!cpu_has_vmx_rdtscp()) 7144 kvm_cpu_cap_clear(X86_FEATURE_RDTSCP); 7145 } 7146 7147 static void vmx_request_immediate_exit(struct kvm_vcpu *vcpu) 7148 { 7149 to_vmx(vcpu)->req_immediate_exit = true; 7150 } 7151 7152 static int vmx_check_intercept_io(struct kvm_vcpu *vcpu, 7153 struct x86_instruction_info *info) 7154 { 7155 struct vmcs12 *vmcs12 = get_vmcs12(vcpu); 7156 unsigned short port; 7157 bool intercept; 7158 int size; 7159 7160 if (info->intercept == x86_intercept_in || 7161 info->intercept == x86_intercept_ins) { 7162 port = info->src_val; 7163 size = info->dst_bytes; 7164 } else { 7165 port = info->dst_val; 7166 size = info->src_bytes; 7167 } 7168 7169 /* 7170 * If the 'use IO bitmaps' VM-execution control is 0, IO instruction 7171 * VM-exits depend on the 'unconditional IO exiting' VM-execution 7172 * control. 7173 * 7174 * Otherwise, IO instruction VM-exits are controlled by the IO bitmaps. 7175 */ 7176 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS)) 7177 intercept = nested_cpu_has(vmcs12, 7178 CPU_BASED_UNCOND_IO_EXITING); 7179 else 7180 intercept = nested_vmx_check_io_bitmaps(vcpu, port, size); 7181 7182 /* FIXME: produce nested vmexit and return X86EMUL_INTERCEPTED. */ 7183 return intercept ? X86EMUL_UNHANDLEABLE : X86EMUL_CONTINUE; 7184 } 7185 7186 static int vmx_check_intercept(struct kvm_vcpu *vcpu, 7187 struct x86_instruction_info *info, 7188 enum x86_intercept_stage stage, 7189 struct x86_exception *exception) 7190 { 7191 struct vmcs12 *vmcs12 = get_vmcs12(vcpu); 7192 7193 switch (info->intercept) { 7194 /* 7195 * RDPID causes #UD if disabled through secondary execution controls. 7196 * Because it is marked as EmulateOnUD, we need to intercept it here. 7197 */ 7198 case x86_intercept_rdtscp: 7199 if (!nested_cpu_has2(vmcs12, SECONDARY_EXEC_RDTSCP)) { 7200 exception->vector = UD_VECTOR; 7201 exception->error_code_valid = false; 7202 return X86EMUL_PROPAGATE_FAULT; 7203 } 7204 break; 7205 7206 case x86_intercept_in: 7207 case x86_intercept_ins: 7208 case x86_intercept_out: 7209 case x86_intercept_outs: 7210 return vmx_check_intercept_io(vcpu, info); 7211 7212 case x86_intercept_lgdt: 7213 case x86_intercept_lidt: 7214 case x86_intercept_lldt: 7215 case x86_intercept_ltr: 7216 case x86_intercept_sgdt: 7217 case x86_intercept_sidt: 7218 case x86_intercept_sldt: 7219 case x86_intercept_str: 7220 if (!nested_cpu_has2(vmcs12, SECONDARY_EXEC_DESC)) 7221 return X86EMUL_CONTINUE; 7222 7223 /* FIXME: produce nested vmexit and return X86EMUL_INTERCEPTED. */ 7224 break; 7225 7226 /* TODO: check more intercepts... */ 7227 default: 7228 break; 7229 } 7230 7231 return X86EMUL_UNHANDLEABLE; 7232 } 7233 7234 #ifdef CONFIG_X86_64 7235 /* (a << shift) / divisor, return 1 if overflow otherwise 0 */ 7236 static inline int u64_shl_div_u64(u64 a, unsigned int shift, 7237 u64 divisor, u64 *result) 7238 { 7239 u64 low = a << shift, high = a >> (64 - shift); 7240 7241 /* To avoid the overflow on divq */ 7242 if (high >= divisor) 7243 return 1; 7244 7245 /* Low hold the result, high hold rem which is discarded */ 7246 asm("divq %2\n\t" : "=a" (low), "=d" (high) : 7247 "rm" (divisor), "0" (low), "1" (high)); 7248 *result = low; 7249 7250 return 0; 7251 } 7252 7253 static int vmx_set_hv_timer(struct kvm_vcpu *vcpu, u64 guest_deadline_tsc, 7254 bool *expired) 7255 { 7256 struct vcpu_vmx *vmx; 7257 u64 tscl, guest_tscl, delta_tsc, lapic_timer_advance_cycles; 7258 struct kvm_timer *ktimer = &vcpu->arch.apic->lapic_timer; 7259 7260 if (kvm_mwait_in_guest(vcpu->kvm) || 7261 kvm_can_post_timer_interrupt(vcpu)) 7262 return -EOPNOTSUPP; 7263 7264 vmx = to_vmx(vcpu); 7265 tscl = rdtsc(); 7266 guest_tscl = kvm_read_l1_tsc(vcpu, tscl); 7267 delta_tsc = max(guest_deadline_tsc, guest_tscl) - guest_tscl; 7268 lapic_timer_advance_cycles = nsec_to_cycles(vcpu, 7269 ktimer->timer_advance_ns); 7270 7271 if (delta_tsc > lapic_timer_advance_cycles) 7272 delta_tsc -= lapic_timer_advance_cycles; 7273 else 7274 delta_tsc = 0; 7275 7276 /* Convert to host delta tsc if tsc scaling is enabled */ 7277 if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio && 7278 delta_tsc && u64_shl_div_u64(delta_tsc, 7279 kvm_tsc_scaling_ratio_frac_bits, 7280 vcpu->arch.tsc_scaling_ratio, &delta_tsc)) 7281 return -ERANGE; 7282 7283 /* 7284 * If the delta tsc can't fit in the 32 bit after the multi shift, 7285 * we can't use the preemption timer. 7286 * It's possible that it fits on later vmentries, but checking 7287 * on every vmentry is costly so we just use an hrtimer. 7288 */ 7289 if (delta_tsc >> (cpu_preemption_timer_multi + 32)) 7290 return -ERANGE; 7291 7292 vmx->hv_deadline_tsc = tscl + delta_tsc; 7293 *expired = !delta_tsc; 7294 return 0; 7295 } 7296 7297 static void vmx_cancel_hv_timer(struct kvm_vcpu *vcpu) 7298 { 7299 to_vmx(vcpu)->hv_deadline_tsc = -1; 7300 } 7301 #endif 7302 7303 static void vmx_sched_in(struct kvm_vcpu *vcpu, int cpu) 7304 { 7305 if (!kvm_pause_in_guest(vcpu->kvm)) 7306 shrink_ple_window(vcpu); 7307 } 7308 7309 static void vmx_slot_enable_log_dirty(struct kvm *kvm, 7310 struct kvm_memory_slot *slot) 7311 { 7312 if (!kvm_dirty_log_manual_protect_and_init_set(kvm)) 7313 kvm_mmu_slot_leaf_clear_dirty(kvm, slot); 7314 kvm_mmu_slot_largepage_remove_write_access(kvm, slot); 7315 } 7316 7317 static void vmx_slot_disable_log_dirty(struct kvm *kvm, 7318 struct kvm_memory_slot *slot) 7319 { 7320 kvm_mmu_slot_set_dirty(kvm, slot); 7321 } 7322 7323 static void vmx_flush_log_dirty(struct kvm *kvm) 7324 { 7325 kvm_flush_pml_buffers(kvm); 7326 } 7327 7328 static int vmx_write_pml_buffer(struct kvm_vcpu *vcpu) 7329 { 7330 struct vmcs12 *vmcs12; 7331 struct vcpu_vmx *vmx = to_vmx(vcpu); 7332 gpa_t gpa, dst; 7333 7334 if (is_guest_mode(vcpu)) { 7335 WARN_ON_ONCE(vmx->nested.pml_full); 7336 7337 /* 7338 * Check if PML is enabled for the nested guest. 7339 * Whether eptp bit 6 is set is already checked 7340 * as part of A/D emulation. 7341 */ 7342 vmcs12 = get_vmcs12(vcpu); 7343 if (!nested_cpu_has_pml(vmcs12)) 7344 return 0; 7345 7346 if (vmcs12->guest_pml_index >= PML_ENTITY_NUM) { 7347 vmx->nested.pml_full = true; 7348 return 1; 7349 } 7350 7351 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS) & ~0xFFFull; 7352 dst = vmcs12->pml_address + sizeof(u64) * vmcs12->guest_pml_index; 7353 7354 if (kvm_write_guest_page(vcpu->kvm, gpa_to_gfn(dst), &gpa, 7355 offset_in_page(dst), sizeof(gpa))) 7356 return 0; 7357 7358 vmcs12->guest_pml_index--; 7359 } 7360 7361 return 0; 7362 } 7363 7364 static void vmx_enable_log_dirty_pt_masked(struct kvm *kvm, 7365 struct kvm_memory_slot *memslot, 7366 gfn_t offset, unsigned long mask) 7367 { 7368 kvm_mmu_clear_dirty_pt_masked(kvm, memslot, offset, mask); 7369 } 7370 7371 static void __pi_post_block(struct kvm_vcpu *vcpu) 7372 { 7373 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu); 7374 struct pi_desc old, new; 7375 unsigned int dest; 7376 7377 do { 7378 old.control = new.control = pi_desc->control; 7379 WARN(old.nv != POSTED_INTR_WAKEUP_VECTOR, 7380 "Wakeup handler not enabled while the VCPU is blocked\n"); 7381 7382 dest = cpu_physical_id(vcpu->cpu); 7383 7384 if (x2apic_enabled()) 7385 new.ndst = dest; 7386 else 7387 new.ndst = (dest << 8) & 0xFF00; 7388 7389 /* set 'NV' to 'notification vector' */ 7390 new.nv = POSTED_INTR_VECTOR; 7391 } while (cmpxchg64(&pi_desc->control, old.control, 7392 new.control) != old.control); 7393 7394 if (!WARN_ON_ONCE(vcpu->pre_pcpu == -1)) { 7395 spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu)); 7396 list_del(&vcpu->blocked_vcpu_list); 7397 spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu)); 7398 vcpu->pre_pcpu = -1; 7399 } 7400 } 7401 7402 /* 7403 * This routine does the following things for vCPU which is going 7404 * to be blocked if VT-d PI is enabled. 7405 * - Store the vCPU to the wakeup list, so when interrupts happen 7406 * we can find the right vCPU to wake up. 7407 * - Change the Posted-interrupt descriptor as below: 7408 * 'NDST' <-- vcpu->pre_pcpu 7409 * 'NV' <-- POSTED_INTR_WAKEUP_VECTOR 7410 * - If 'ON' is set during this process, which means at least one 7411 * interrupt is posted for this vCPU, we cannot block it, in 7412 * this case, return 1, otherwise, return 0. 7413 * 7414 */ 7415 static int pi_pre_block(struct kvm_vcpu *vcpu) 7416 { 7417 unsigned int dest; 7418 struct pi_desc old, new; 7419 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu); 7420 7421 if (!kvm_arch_has_assigned_device(vcpu->kvm) || 7422 !irq_remapping_cap(IRQ_POSTING_CAP) || 7423 !kvm_vcpu_apicv_active(vcpu)) 7424 return 0; 7425 7426 WARN_ON(irqs_disabled()); 7427 local_irq_disable(); 7428 if (!WARN_ON_ONCE(vcpu->pre_pcpu != -1)) { 7429 vcpu->pre_pcpu = vcpu->cpu; 7430 spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu)); 7431 list_add_tail(&vcpu->blocked_vcpu_list, 7432 &per_cpu(blocked_vcpu_on_cpu, 7433 vcpu->pre_pcpu)); 7434 spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu)); 7435 } 7436 7437 do { 7438 old.control = new.control = pi_desc->control; 7439 7440 WARN((pi_desc->sn == 1), 7441 "Warning: SN field of posted-interrupts " 7442 "is set before blocking\n"); 7443 7444 /* 7445 * Since vCPU can be preempted during this process, 7446 * vcpu->cpu could be different with pre_pcpu, we 7447 * need to set pre_pcpu as the destination of wakeup 7448 * notification event, then we can find the right vCPU 7449 * to wakeup in wakeup handler if interrupts happen 7450 * when the vCPU is in blocked state. 7451 */ 7452 dest = cpu_physical_id(vcpu->pre_pcpu); 7453 7454 if (x2apic_enabled()) 7455 new.ndst = dest; 7456 else 7457 new.ndst = (dest << 8) & 0xFF00; 7458 7459 /* set 'NV' to 'wakeup vector' */ 7460 new.nv = POSTED_INTR_WAKEUP_VECTOR; 7461 } while (cmpxchg64(&pi_desc->control, old.control, 7462 new.control) != old.control); 7463 7464 /* We should not block the vCPU if an interrupt is posted for it. */ 7465 if (pi_test_on(pi_desc) == 1) 7466 __pi_post_block(vcpu); 7467 7468 local_irq_enable(); 7469 return (vcpu->pre_pcpu == -1); 7470 } 7471 7472 static int vmx_pre_block(struct kvm_vcpu *vcpu) 7473 { 7474 if (pi_pre_block(vcpu)) 7475 return 1; 7476 7477 if (kvm_lapic_hv_timer_in_use(vcpu)) 7478 kvm_lapic_switch_to_sw_timer(vcpu); 7479 7480 return 0; 7481 } 7482 7483 static void pi_post_block(struct kvm_vcpu *vcpu) 7484 { 7485 if (vcpu->pre_pcpu == -1) 7486 return; 7487 7488 WARN_ON(irqs_disabled()); 7489 local_irq_disable(); 7490 __pi_post_block(vcpu); 7491 local_irq_enable(); 7492 } 7493 7494 static void vmx_post_block(struct kvm_vcpu *vcpu) 7495 { 7496 if (kvm_x86_ops.set_hv_timer) 7497 kvm_lapic_switch_to_hv_timer(vcpu); 7498 7499 pi_post_block(vcpu); 7500 } 7501 7502 /* 7503 * vmx_update_pi_irte - set IRTE for Posted-Interrupts 7504 * 7505 * @kvm: kvm 7506 * @host_irq: host irq of the interrupt 7507 * @guest_irq: gsi of the interrupt 7508 * @set: set or unset PI 7509 * returns 0 on success, < 0 on failure 7510 */ 7511 static int vmx_update_pi_irte(struct kvm *kvm, unsigned int host_irq, 7512 uint32_t guest_irq, bool set) 7513 { 7514 struct kvm_kernel_irq_routing_entry *e; 7515 struct kvm_irq_routing_table *irq_rt; 7516 struct kvm_lapic_irq irq; 7517 struct kvm_vcpu *vcpu; 7518 struct vcpu_data vcpu_info; 7519 int idx, ret = 0; 7520 7521 if (!kvm_arch_has_assigned_device(kvm) || 7522 !irq_remapping_cap(IRQ_POSTING_CAP) || 7523 !kvm_vcpu_apicv_active(kvm->vcpus[0])) 7524 return 0; 7525 7526 idx = srcu_read_lock(&kvm->irq_srcu); 7527 irq_rt = srcu_dereference(kvm->irq_routing, &kvm->irq_srcu); 7528 if (guest_irq >= irq_rt->nr_rt_entries || 7529 hlist_empty(&irq_rt->map[guest_irq])) { 7530 pr_warn_once("no route for guest_irq %u/%u (broken user space?)\n", 7531 guest_irq, irq_rt->nr_rt_entries); 7532 goto out; 7533 } 7534 7535 hlist_for_each_entry(e, &irq_rt->map[guest_irq], link) { 7536 if (e->type != KVM_IRQ_ROUTING_MSI) 7537 continue; 7538 /* 7539 * VT-d PI cannot support posting multicast/broadcast 7540 * interrupts to a vCPU, we still use interrupt remapping 7541 * for these kind of interrupts. 7542 * 7543 * For lowest-priority interrupts, we only support 7544 * those with single CPU as the destination, e.g. user 7545 * configures the interrupts via /proc/irq or uses 7546 * irqbalance to make the interrupts single-CPU. 7547 * 7548 * We will support full lowest-priority interrupt later. 7549 * 7550 * In addition, we can only inject generic interrupts using 7551 * the PI mechanism, refuse to route others through it. 7552 */ 7553 7554 kvm_set_msi_irq(kvm, e, &irq); 7555 if (!kvm_intr_is_single_vcpu(kvm, &irq, &vcpu) || 7556 !kvm_irq_is_postable(&irq)) { 7557 /* 7558 * Make sure the IRTE is in remapped mode if 7559 * we don't handle it in posted mode. 7560 */ 7561 ret = irq_set_vcpu_affinity(host_irq, NULL); 7562 if (ret < 0) { 7563 printk(KERN_INFO 7564 "failed to back to remapped mode, irq: %u\n", 7565 host_irq); 7566 goto out; 7567 } 7568 7569 continue; 7570 } 7571 7572 vcpu_info.pi_desc_addr = __pa(vcpu_to_pi_desc(vcpu)); 7573 vcpu_info.vector = irq.vector; 7574 7575 trace_kvm_pi_irte_update(host_irq, vcpu->vcpu_id, e->gsi, 7576 vcpu_info.vector, vcpu_info.pi_desc_addr, set); 7577 7578 if (set) 7579 ret = irq_set_vcpu_affinity(host_irq, &vcpu_info); 7580 else 7581 ret = irq_set_vcpu_affinity(host_irq, NULL); 7582 7583 if (ret < 0) { 7584 printk(KERN_INFO "%s: failed to update PI IRTE\n", 7585 __func__); 7586 goto out; 7587 } 7588 } 7589 7590 ret = 0; 7591 out: 7592 srcu_read_unlock(&kvm->irq_srcu, idx); 7593 return ret; 7594 } 7595 7596 static void vmx_setup_mce(struct kvm_vcpu *vcpu) 7597 { 7598 if (vcpu->arch.mcg_cap & MCG_LMCE_P) 7599 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits |= 7600 FEAT_CTL_LMCE_ENABLED; 7601 else 7602 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits &= 7603 ~FEAT_CTL_LMCE_ENABLED; 7604 } 7605 7606 static int vmx_smi_allowed(struct kvm_vcpu *vcpu) 7607 { 7608 /* we need a nested vmexit to enter SMM, postpone if run is pending */ 7609 if (to_vmx(vcpu)->nested.nested_run_pending) 7610 return 0; 7611 return 1; 7612 } 7613 7614 static int vmx_pre_enter_smm(struct kvm_vcpu *vcpu, char *smstate) 7615 { 7616 struct vcpu_vmx *vmx = to_vmx(vcpu); 7617 7618 vmx->nested.smm.guest_mode = is_guest_mode(vcpu); 7619 if (vmx->nested.smm.guest_mode) 7620 nested_vmx_vmexit(vcpu, -1, 0, 0); 7621 7622 vmx->nested.smm.vmxon = vmx->nested.vmxon; 7623 vmx->nested.vmxon = false; 7624 vmx_clear_hlt(vcpu); 7625 return 0; 7626 } 7627 7628 static int vmx_pre_leave_smm(struct kvm_vcpu *vcpu, const char *smstate) 7629 { 7630 struct vcpu_vmx *vmx = to_vmx(vcpu); 7631 int ret; 7632 7633 if (vmx->nested.smm.vmxon) { 7634 vmx->nested.vmxon = true; 7635 vmx->nested.smm.vmxon = false; 7636 } 7637 7638 if (vmx->nested.smm.guest_mode) { 7639 ret = nested_vmx_enter_non_root_mode(vcpu, false); 7640 if (ret) 7641 return ret; 7642 7643 vmx->nested.smm.guest_mode = false; 7644 } 7645 return 0; 7646 } 7647 7648 static int enable_smi_window(struct kvm_vcpu *vcpu) 7649 { 7650 return 0; 7651 } 7652 7653 static bool vmx_need_emulation_on_page_fault(struct kvm_vcpu *vcpu) 7654 { 7655 return false; 7656 } 7657 7658 static bool vmx_apic_init_signal_blocked(struct kvm_vcpu *vcpu) 7659 { 7660 return to_vmx(vcpu)->nested.vmxon; 7661 } 7662 7663 static void hardware_unsetup(void) 7664 { 7665 if (nested) 7666 nested_vmx_hardware_unsetup(); 7667 7668 free_kvm_area(); 7669 } 7670 7671 static bool vmx_check_apicv_inhibit_reasons(ulong bit) 7672 { 7673 ulong supported = BIT(APICV_INHIBIT_REASON_DISABLE) | 7674 BIT(APICV_INHIBIT_REASON_HYPERV); 7675 7676 return supported & BIT(bit); 7677 } 7678 7679 static struct kvm_x86_ops vmx_x86_ops __initdata = { 7680 .hardware_unsetup = hardware_unsetup, 7681 7682 .hardware_enable = hardware_enable, 7683 .hardware_disable = hardware_disable, 7684 .cpu_has_accelerated_tpr = report_flexpriority, 7685 .has_emulated_msr = vmx_has_emulated_msr, 7686 7687 .vm_size = sizeof(struct kvm_vmx), 7688 .vm_init = vmx_vm_init, 7689 7690 .vcpu_create = vmx_create_vcpu, 7691 .vcpu_free = vmx_free_vcpu, 7692 .vcpu_reset = vmx_vcpu_reset, 7693 7694 .prepare_guest_switch = vmx_prepare_switch_to_guest, 7695 .vcpu_load = vmx_vcpu_load, 7696 .vcpu_put = vmx_vcpu_put, 7697 7698 .update_bp_intercept = update_exception_bitmap, 7699 .get_msr_feature = vmx_get_msr_feature, 7700 .get_msr = vmx_get_msr, 7701 .set_msr = vmx_set_msr, 7702 .get_segment_base = vmx_get_segment_base, 7703 .get_segment = vmx_get_segment, 7704 .set_segment = vmx_set_segment, 7705 .get_cpl = vmx_get_cpl, 7706 .get_cs_db_l_bits = vmx_get_cs_db_l_bits, 7707 .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits, 7708 .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits, 7709 .set_cr0 = vmx_set_cr0, 7710 .set_cr4 = vmx_set_cr4, 7711 .set_efer = vmx_set_efer, 7712 .get_idt = vmx_get_idt, 7713 .set_idt = vmx_set_idt, 7714 .get_gdt = vmx_get_gdt, 7715 .set_gdt = vmx_set_gdt, 7716 .get_dr6 = vmx_get_dr6, 7717 .set_dr6 = vmx_set_dr6, 7718 .set_dr7 = vmx_set_dr7, 7719 .sync_dirty_debug_regs = vmx_sync_dirty_debug_regs, 7720 .cache_reg = vmx_cache_reg, 7721 .get_rflags = vmx_get_rflags, 7722 .set_rflags = vmx_set_rflags, 7723 7724 .tlb_flush = vmx_flush_tlb, 7725 .tlb_flush_gva = vmx_flush_tlb_gva, 7726 7727 .run = vmx_vcpu_run, 7728 .handle_exit = vmx_handle_exit, 7729 .skip_emulated_instruction = vmx_skip_emulated_instruction, 7730 .update_emulated_instruction = vmx_update_emulated_instruction, 7731 .set_interrupt_shadow = vmx_set_interrupt_shadow, 7732 .get_interrupt_shadow = vmx_get_interrupt_shadow, 7733 .patch_hypercall = vmx_patch_hypercall, 7734 .set_irq = vmx_inject_irq, 7735 .set_nmi = vmx_inject_nmi, 7736 .queue_exception = vmx_queue_exception, 7737 .cancel_injection = vmx_cancel_injection, 7738 .interrupt_allowed = vmx_interrupt_allowed, 7739 .nmi_allowed = vmx_nmi_allowed, 7740 .get_nmi_mask = vmx_get_nmi_mask, 7741 .set_nmi_mask = vmx_set_nmi_mask, 7742 .enable_nmi_window = enable_nmi_window, 7743 .enable_irq_window = enable_irq_window, 7744 .update_cr8_intercept = update_cr8_intercept, 7745 .set_virtual_apic_mode = vmx_set_virtual_apic_mode, 7746 .set_apic_access_page_addr = vmx_set_apic_access_page_addr, 7747 .refresh_apicv_exec_ctrl = vmx_refresh_apicv_exec_ctrl, 7748 .load_eoi_exitmap = vmx_load_eoi_exitmap, 7749 .apicv_post_state_restore = vmx_apicv_post_state_restore, 7750 .check_apicv_inhibit_reasons = vmx_check_apicv_inhibit_reasons, 7751 .hwapic_irr_update = vmx_hwapic_irr_update, 7752 .hwapic_isr_update = vmx_hwapic_isr_update, 7753 .guest_apic_has_interrupt = vmx_guest_apic_has_interrupt, 7754 .sync_pir_to_irr = vmx_sync_pir_to_irr, 7755 .deliver_posted_interrupt = vmx_deliver_posted_interrupt, 7756 .dy_apicv_has_pending_interrupt = vmx_dy_apicv_has_pending_interrupt, 7757 7758 .set_tss_addr = vmx_set_tss_addr, 7759 .set_identity_map_addr = vmx_set_identity_map_addr, 7760 .get_tdp_level = get_ept_level, 7761 .get_mt_mask = vmx_get_mt_mask, 7762 7763 .get_exit_info = vmx_get_exit_info, 7764 7765 .cpuid_update = vmx_cpuid_update, 7766 7767 .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit, 7768 7769 .read_l1_tsc_offset = vmx_read_l1_tsc_offset, 7770 .write_l1_tsc_offset = vmx_write_l1_tsc_offset, 7771 7772 .load_mmu_pgd = vmx_load_mmu_pgd, 7773 7774 .check_intercept = vmx_check_intercept, 7775 .handle_exit_irqoff = vmx_handle_exit_irqoff, 7776 7777 .request_immediate_exit = vmx_request_immediate_exit, 7778 7779 .sched_in = vmx_sched_in, 7780 7781 .slot_enable_log_dirty = vmx_slot_enable_log_dirty, 7782 .slot_disable_log_dirty = vmx_slot_disable_log_dirty, 7783 .flush_log_dirty = vmx_flush_log_dirty, 7784 .enable_log_dirty_pt_masked = vmx_enable_log_dirty_pt_masked, 7785 .write_log_dirty = vmx_write_pml_buffer, 7786 7787 .pre_block = vmx_pre_block, 7788 .post_block = vmx_post_block, 7789 7790 .pmu_ops = &intel_pmu_ops, 7791 7792 .update_pi_irte = vmx_update_pi_irte, 7793 7794 #ifdef CONFIG_X86_64 7795 .set_hv_timer = vmx_set_hv_timer, 7796 .cancel_hv_timer = vmx_cancel_hv_timer, 7797 #endif 7798 7799 .setup_mce = vmx_setup_mce, 7800 7801 .smi_allowed = vmx_smi_allowed, 7802 .pre_enter_smm = vmx_pre_enter_smm, 7803 .pre_leave_smm = vmx_pre_leave_smm, 7804 .enable_smi_window = enable_smi_window, 7805 7806 .check_nested_events = NULL, 7807 .get_nested_state = NULL, 7808 .set_nested_state = NULL, 7809 .get_vmcs12_pages = NULL, 7810 .nested_enable_evmcs = NULL, 7811 .nested_get_evmcs_version = NULL, 7812 .need_emulation_on_page_fault = vmx_need_emulation_on_page_fault, 7813 .apic_init_signal_blocked = vmx_apic_init_signal_blocked, 7814 }; 7815 7816 static __init int hardware_setup(void) 7817 { 7818 unsigned long host_bndcfgs; 7819 struct desc_ptr dt; 7820 int r, i, ept_lpage_level; 7821 7822 store_idt(&dt); 7823 host_idt_base = dt.address; 7824 7825 for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i) 7826 kvm_define_shared_msr(i, vmx_msr_index[i]); 7827 7828 if (setup_vmcs_config(&vmcs_config, &vmx_capability) < 0) 7829 return -EIO; 7830 7831 if (boot_cpu_has(X86_FEATURE_NX)) 7832 kvm_enable_efer_bits(EFER_NX); 7833 7834 if (boot_cpu_has(X86_FEATURE_MPX)) { 7835 rdmsrl(MSR_IA32_BNDCFGS, host_bndcfgs); 7836 WARN_ONCE(host_bndcfgs, "KVM: BNDCFGS in host will be lost"); 7837 } 7838 7839 if (!cpu_has_vmx_mpx()) 7840 supported_xcr0 &= ~(XFEATURE_MASK_BNDREGS | 7841 XFEATURE_MASK_BNDCSR); 7842 7843 if (!cpu_has_vmx_vpid() || !cpu_has_vmx_invvpid() || 7844 !(cpu_has_vmx_invvpid_single() || cpu_has_vmx_invvpid_global())) 7845 enable_vpid = 0; 7846 7847 if (!cpu_has_vmx_ept() || 7848 !cpu_has_vmx_ept_4levels() || 7849 !cpu_has_vmx_ept_mt_wb() || 7850 !cpu_has_vmx_invept_global()) 7851 enable_ept = 0; 7852 7853 if (!cpu_has_vmx_ept_ad_bits() || !enable_ept) 7854 enable_ept_ad_bits = 0; 7855 7856 if (!cpu_has_vmx_unrestricted_guest() || !enable_ept) 7857 enable_unrestricted_guest = 0; 7858 7859 if (!cpu_has_vmx_flexpriority()) 7860 flexpriority_enabled = 0; 7861 7862 if (!cpu_has_virtual_nmis()) 7863 enable_vnmi = 0; 7864 7865 /* 7866 * set_apic_access_page_addr() is used to reload apic access 7867 * page upon invalidation. No need to do anything if not 7868 * using the APIC_ACCESS_ADDR VMCS field. 7869 */ 7870 if (!flexpriority_enabled) 7871 vmx_x86_ops.set_apic_access_page_addr = NULL; 7872 7873 if (!cpu_has_vmx_tpr_shadow()) 7874 vmx_x86_ops.update_cr8_intercept = NULL; 7875 7876 #if IS_ENABLED(CONFIG_HYPERV) 7877 if (ms_hyperv.nested_features & HV_X64_NESTED_GUEST_MAPPING_FLUSH 7878 && enable_ept) { 7879 vmx_x86_ops.tlb_remote_flush = hv_remote_flush_tlb; 7880 vmx_x86_ops.tlb_remote_flush_with_range = 7881 hv_remote_flush_tlb_with_range; 7882 } 7883 #endif 7884 7885 if (!cpu_has_vmx_ple()) { 7886 ple_gap = 0; 7887 ple_window = 0; 7888 ple_window_grow = 0; 7889 ple_window_max = 0; 7890 ple_window_shrink = 0; 7891 } 7892 7893 if (!cpu_has_vmx_apicv()) { 7894 enable_apicv = 0; 7895 vmx_x86_ops.sync_pir_to_irr = NULL; 7896 } 7897 7898 if (cpu_has_vmx_tsc_scaling()) { 7899 kvm_has_tsc_control = true; 7900 kvm_max_tsc_scaling_ratio = KVM_VMX_TSC_MULTIPLIER_MAX; 7901 kvm_tsc_scaling_ratio_frac_bits = 48; 7902 } 7903 7904 set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */ 7905 7906 if (enable_ept) 7907 vmx_enable_tdp(); 7908 7909 if (!enable_ept) 7910 ept_lpage_level = 0; 7911 else if (cpu_has_vmx_ept_1g_page()) 7912 ept_lpage_level = PT_PDPE_LEVEL; 7913 else if (cpu_has_vmx_ept_2m_page()) 7914 ept_lpage_level = PT_DIRECTORY_LEVEL; 7915 else 7916 ept_lpage_level = PT_PAGE_TABLE_LEVEL; 7917 kvm_configure_mmu(enable_ept, ept_lpage_level); 7918 7919 /* 7920 * Only enable PML when hardware supports PML feature, and both EPT 7921 * and EPT A/D bit features are enabled -- PML depends on them to work. 7922 */ 7923 if (!enable_ept || !enable_ept_ad_bits || !cpu_has_vmx_pml()) 7924 enable_pml = 0; 7925 7926 if (!enable_pml) { 7927 vmx_x86_ops.slot_enable_log_dirty = NULL; 7928 vmx_x86_ops.slot_disable_log_dirty = NULL; 7929 vmx_x86_ops.flush_log_dirty = NULL; 7930 vmx_x86_ops.enable_log_dirty_pt_masked = NULL; 7931 } 7932 7933 if (!cpu_has_vmx_preemption_timer()) 7934 enable_preemption_timer = false; 7935 7936 if (enable_preemption_timer) { 7937 u64 use_timer_freq = 5000ULL * 1000 * 1000; 7938 u64 vmx_msr; 7939 7940 rdmsrl(MSR_IA32_VMX_MISC, vmx_msr); 7941 cpu_preemption_timer_multi = 7942 vmx_msr & VMX_MISC_PREEMPTION_TIMER_RATE_MASK; 7943 7944 if (tsc_khz) 7945 use_timer_freq = (u64)tsc_khz * 1000; 7946 use_timer_freq >>= cpu_preemption_timer_multi; 7947 7948 /* 7949 * KVM "disables" the preemption timer by setting it to its max 7950 * value. Don't use the timer if it might cause spurious exits 7951 * at a rate faster than 0.1 Hz (of uninterrupted guest time). 7952 */ 7953 if (use_timer_freq > 0xffffffffu / 10) 7954 enable_preemption_timer = false; 7955 } 7956 7957 if (!enable_preemption_timer) { 7958 vmx_x86_ops.set_hv_timer = NULL; 7959 vmx_x86_ops.cancel_hv_timer = NULL; 7960 vmx_x86_ops.request_immediate_exit = __kvm_request_immediate_exit; 7961 } 7962 7963 kvm_set_posted_intr_wakeup_handler(wakeup_handler); 7964 7965 kvm_mce_cap_supported |= MCG_LMCE_P; 7966 7967 if (pt_mode != PT_MODE_SYSTEM && pt_mode != PT_MODE_HOST_GUEST) 7968 return -EINVAL; 7969 if (!enable_ept || !cpu_has_vmx_intel_pt()) 7970 pt_mode = PT_MODE_SYSTEM; 7971 7972 if (nested) { 7973 nested_vmx_setup_ctls_msrs(&vmcs_config.nested, 7974 vmx_capability.ept); 7975 7976 r = nested_vmx_hardware_setup(&vmx_x86_ops, 7977 kvm_vmx_exit_handlers); 7978 if (r) 7979 return r; 7980 } 7981 7982 vmx_set_cpu_caps(); 7983 7984 r = alloc_kvm_area(); 7985 if (r) 7986 nested_vmx_hardware_unsetup(); 7987 return r; 7988 } 7989 7990 static struct kvm_x86_init_ops vmx_init_ops __initdata = { 7991 .cpu_has_kvm_support = cpu_has_kvm_support, 7992 .disabled_by_bios = vmx_disabled_by_bios, 7993 .check_processor_compatibility = vmx_check_processor_compat, 7994 .hardware_setup = hardware_setup, 7995 7996 .runtime_ops = &vmx_x86_ops, 7997 }; 7998 7999 static void vmx_cleanup_l1d_flush(void) 8000 { 8001 if (vmx_l1d_flush_pages) { 8002 free_pages((unsigned long)vmx_l1d_flush_pages, L1D_CACHE_ORDER); 8003 vmx_l1d_flush_pages = NULL; 8004 } 8005 /* Restore state so sysfs ignores VMX */ 8006 l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_AUTO; 8007 } 8008 8009 static void vmx_exit(void) 8010 { 8011 #ifdef CONFIG_KEXEC_CORE 8012 RCU_INIT_POINTER(crash_vmclear_loaded_vmcss, NULL); 8013 synchronize_rcu(); 8014 #endif 8015 8016 kvm_exit(); 8017 8018 #if IS_ENABLED(CONFIG_HYPERV) 8019 if (static_branch_unlikely(&enable_evmcs)) { 8020 int cpu; 8021 struct hv_vp_assist_page *vp_ap; 8022 /* 8023 * Reset everything to support using non-enlightened VMCS 8024 * access later (e.g. when we reload the module with 8025 * enlightened_vmcs=0) 8026 */ 8027 for_each_online_cpu(cpu) { 8028 vp_ap = hv_get_vp_assist_page(cpu); 8029 8030 if (!vp_ap) 8031 continue; 8032 8033 vp_ap->nested_control.features.directhypercall = 0; 8034 vp_ap->current_nested_vmcs = 0; 8035 vp_ap->enlighten_vmentry = 0; 8036 } 8037 8038 static_branch_disable(&enable_evmcs); 8039 } 8040 #endif 8041 vmx_cleanup_l1d_flush(); 8042 } 8043 module_exit(vmx_exit); 8044 8045 static int __init vmx_init(void) 8046 { 8047 int r; 8048 8049 #if IS_ENABLED(CONFIG_HYPERV) 8050 /* 8051 * Enlightened VMCS usage should be recommended and the host needs 8052 * to support eVMCS v1 or above. We can also disable eVMCS support 8053 * with module parameter. 8054 */ 8055 if (enlightened_vmcs && 8056 ms_hyperv.hints & HV_X64_ENLIGHTENED_VMCS_RECOMMENDED && 8057 (ms_hyperv.nested_features & HV_X64_ENLIGHTENED_VMCS_VERSION) >= 8058 KVM_EVMCS_VERSION) { 8059 int cpu; 8060 8061 /* Check that we have assist pages on all online CPUs */ 8062 for_each_online_cpu(cpu) { 8063 if (!hv_get_vp_assist_page(cpu)) { 8064 enlightened_vmcs = false; 8065 break; 8066 } 8067 } 8068 8069 if (enlightened_vmcs) { 8070 pr_info("KVM: vmx: using Hyper-V Enlightened VMCS\n"); 8071 static_branch_enable(&enable_evmcs); 8072 } 8073 8074 if (ms_hyperv.nested_features & HV_X64_NESTED_DIRECT_FLUSH) 8075 vmx_x86_ops.enable_direct_tlbflush 8076 = hv_enable_direct_tlbflush; 8077 8078 } else { 8079 enlightened_vmcs = false; 8080 } 8081 #endif 8082 8083 r = kvm_init(&vmx_init_ops, sizeof(struct vcpu_vmx), 8084 __alignof__(struct vcpu_vmx), THIS_MODULE); 8085 if (r) 8086 return r; 8087 8088 /* 8089 * Must be called after kvm_init() so enable_ept is properly set 8090 * up. Hand the parameter mitigation value in which was stored in 8091 * the pre module init parser. If no parameter was given, it will 8092 * contain 'auto' which will be turned into the default 'cond' 8093 * mitigation mode. 8094 */ 8095 r = vmx_setup_l1d_flush(vmentry_l1d_flush_param); 8096 if (r) { 8097 vmx_exit(); 8098 return r; 8099 } 8100 8101 #ifdef CONFIG_KEXEC_CORE 8102 rcu_assign_pointer(crash_vmclear_loaded_vmcss, 8103 crash_vmclear_local_loaded_vmcss); 8104 #endif 8105 vmx_check_vmcs12_offsets(); 8106 8107 return 0; 8108 } 8109 module_init(vmx_init); 8110