1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* architectural constants/data definitions for TDX SEAMCALLs */ 3 4 #ifndef __KVM_X86_TDX_ARCH_H 5 #define __KVM_X86_TDX_ARCH_H 6 7 #include <linux/types.h> 8 9 /* TDX control structure (TDR/TDCS/TDVPS) field access codes */ 10 #define TDX_NON_ARCH BIT_ULL(63) 11 #define TDX_CLASS_SHIFT 56 12 #define TDX_FIELD_MASK GENMASK_ULL(31, 0) 13 14 #define __BUILD_TDX_FIELD(non_arch, class, field) \ 15 (((non_arch) ? TDX_NON_ARCH : 0) | \ 16 ((u64)(class) << TDX_CLASS_SHIFT) | \ 17 ((u64)(field) & TDX_FIELD_MASK)) 18 19 #define BUILD_TDX_FIELD(class, field) \ 20 __BUILD_TDX_FIELD(false, (class), (field)) 21 22 #define BUILD_TDX_FIELD_NON_ARCH(class, field) \ 23 __BUILD_TDX_FIELD(true, (class), (field)) 24 25 26 /* Class code for TD */ 27 #define TD_CLASS_EXECUTION_CONTROLS 17ULL 28 29 /* Class code for TDVPS */ 30 #define TDVPS_CLASS_VMCS 0ULL 31 #define TDVPS_CLASS_GUEST_GPR 16ULL 32 #define TDVPS_CLASS_OTHER_GUEST 17ULL 33 #define TDVPS_CLASS_MANAGEMENT 32ULL 34 35 enum tdx_tdcs_execution_control { 36 TD_TDCS_EXEC_TSC_OFFSET = 10, 37 TD_TDCS_EXEC_TSC_MULTIPLIER = 11, 38 }; 39 40 enum tdx_vcpu_guest_other_state { 41 TD_VCPU_STATE_DETAILS_NON_ARCH = 0x100, 42 }; 43 44 #define TDX_VCPU_STATE_DETAILS_INTR_PENDING BIT_ULL(0) 45 46 static inline bool tdx_vcpu_state_details_intr_pending(u64 vcpu_state_details) 47 { 48 return !!(vcpu_state_details & TDX_VCPU_STATE_DETAILS_INTR_PENDING); 49 } 50 51 /* @field is any of enum tdx_tdcs_execution_control */ 52 #define TDCS_EXEC(field) BUILD_TDX_FIELD(TD_CLASS_EXECUTION_CONTROLS, (field)) 53 54 /* @field is the VMCS field encoding */ 55 #define TDVPS_VMCS(field) BUILD_TDX_FIELD(TDVPS_CLASS_VMCS, (field)) 56 57 /* @field is any of enum tdx_guest_other_state */ 58 #define TDVPS_STATE(field) BUILD_TDX_FIELD(TDVPS_CLASS_OTHER_GUEST, (field)) 59 #define TDVPS_STATE_NON_ARCH(field) BUILD_TDX_FIELD_NON_ARCH(TDVPS_CLASS_OTHER_GUEST, (field)) 60 61 /* Management class fields */ 62 enum tdx_vcpu_guest_management { 63 TD_VCPU_PEND_NMI = 11, 64 }; 65 66 /* @field is any of enum tdx_vcpu_guest_management */ 67 #define TDVPS_MANAGEMENT(field) BUILD_TDX_FIELD(TDVPS_CLASS_MANAGEMENT, (field)) 68 69 #define TDX_EXTENDMR_CHUNKSIZE 256 70 71 struct tdx_cpuid_value { 72 u32 eax; 73 u32 ebx; 74 u32 ecx; 75 u32 edx; 76 } __packed; 77 78 #define TDX_TD_ATTR_DEBUG BIT_ULL(0) 79 #define TDX_TD_ATTR_SEPT_VE_DISABLE BIT_ULL(28) 80 #define TDX_TD_ATTR_PKS BIT_ULL(30) 81 #define TDX_TD_ATTR_KL BIT_ULL(31) 82 #define TDX_TD_ATTR_PERFMON BIT_ULL(63) 83 84 #define TDX_EXT_EXIT_QUAL_TYPE_MASK GENMASK(3, 0) 85 #define TDX_EXT_EXIT_QUAL_TYPE_PENDING_EPT_VIOLATION 6 86 /* 87 * TD_PARAMS is provided as an input to TDH_MNG_INIT, the size of which is 1024B. 88 */ 89 struct td_params { 90 u64 attributes; 91 u64 xfam; 92 u16 max_vcpus; 93 u8 reserved0[6]; 94 95 u64 eptp_controls; 96 u64 config_flags; 97 u16 tsc_frequency; 98 u8 reserved1[38]; 99 100 u64 mrconfigid[6]; 101 u64 mrowner[6]; 102 u64 mrownerconfig[6]; 103 u64 reserved2[4]; 104 105 union { 106 DECLARE_FLEX_ARRAY(struct tdx_cpuid_value, cpuid_values); 107 u8 reserved3[768]; 108 }; 109 } __packed __aligned(1024); 110 111 /* 112 * Guest uses MAX_PA for GPAW when set. 113 * 0: GPA.SHARED bit is GPA[47] 114 * 1: GPA.SHARED bit is GPA[51] 115 */ 116 #define TDX_CONFIG_FLAGS_MAX_GPAW BIT_ULL(0) 117 118 /* 119 * TDH.VP.ENTER, TDG.VP.VMCALL preserves RBP 120 * 0: RBP can be used for TDG.VP.VMCALL input. RBP is clobbered. 121 * 1: RBP can't be used for TDG.VP.VMCALL input. RBP is preserved. 122 */ 123 #define TDX_CONFIG_FLAGS_NO_RBP_MOD BIT_ULL(2) 124 125 126 /* 127 * TDX requires the frequency to be defined in units of 25MHz, which is the 128 * frequency of the core crystal clock on TDX-capable platforms, i.e. the TDX 129 * module can only program frequencies that are multiples of 25MHz. The 130 * frequency must be between 100mhz and 10ghz (inclusive). 131 */ 132 #define TDX_TSC_KHZ_TO_25MHZ(tsc_in_khz) ((tsc_in_khz) / (25 * 1000)) 133 #define TDX_TSC_25MHZ_TO_KHZ(tsc_in_25mhz) ((tsc_in_25mhz) * (25 * 1000)) 134 #define TDX_MIN_TSC_FREQUENCY_KHZ (100 * 1000) 135 #define TDX_MAX_TSC_FREQUENCY_KHZ (10 * 1000 * 1000) 136 137 /* Additional Secure EPT entry information */ 138 #define TDX_SEPT_LEVEL_MASK GENMASK_ULL(2, 0) 139 #define TDX_SEPT_STATE_MASK GENMASK_ULL(15, 8) 140 #define TDX_SEPT_STATE_SHIFT 8 141 142 enum tdx_sept_entry_state { 143 TDX_SEPT_FREE = 0, 144 TDX_SEPT_BLOCKED = 1, 145 TDX_SEPT_PENDING = 2, 146 TDX_SEPT_PENDING_BLOCKED = 3, 147 TDX_SEPT_PRESENT = 4, 148 }; 149 150 static inline u8 tdx_get_sept_level(u64 sept_entry_info) 151 { 152 return sept_entry_info & TDX_SEPT_LEVEL_MASK; 153 } 154 155 static inline u8 tdx_get_sept_state(u64 sept_entry_info) 156 { 157 return (sept_entry_info & TDX_SEPT_STATE_MASK) >> TDX_SEPT_STATE_SHIFT; 158 } 159 160 #define MD_FIELD_ID_FEATURES0_TOPOLOGY_ENUM BIT_ULL(20) 161 162 /* 163 * TD scope metadata field ID. 164 */ 165 #define TD_MD_FIELD_ID_CPUID_VALUES 0x9410000300000000ULL 166 167 #endif /* __KVM_X86_TDX_ARCH_H */ 168