1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * KVM PMU support for Intel CPUs 4 * 5 * Copyright 2011 Red Hat, Inc. and/or its affiliates. 6 * 7 * Authors: 8 * Avi Kivity <avi@redhat.com> 9 * Gleb Natapov <gleb@redhat.com> 10 */ 11 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 12 13 #include <linux/types.h> 14 #include <linux/kvm_host.h> 15 #include <linux/perf_event.h> 16 #include <asm/msr.h> 17 #include <asm/perf_event.h> 18 #include "x86.h" 19 #include "cpuid.h" 20 #include "lapic.h" 21 #include "nested.h" 22 #include "pmu.h" 23 #include "tdx.h" 24 25 /* 26 * Perf's "BASE" is wildly misleading, architectural PMUs use bits 31:16 of ECX 27 * to encode the "type" of counter to read, i.e. this is not a "base". And to 28 * further confuse things, non-architectural PMUs use bit 31 as a flag for 29 * "fast" reads, whereas the "type" is an explicit value. 30 */ 31 #define INTEL_RDPMC_GP 0 32 #define INTEL_RDPMC_FIXED INTEL_PMC_FIXED_RDPMC_BASE 33 34 #define INTEL_RDPMC_TYPE_MASK GENMASK(31, 16) 35 #define INTEL_RDPMC_INDEX_MASK GENMASK(15, 0) 36 37 #define MSR_PMC_FULL_WIDTH_BIT (MSR_IA32_PMC0 - MSR_IA32_PERFCTR0) 38 39 static struct lbr_desc *vcpu_to_lbr_desc(struct kvm_vcpu *vcpu) 40 { 41 if (is_td_vcpu(vcpu)) 42 return NULL; 43 44 return &to_vmx(vcpu)->lbr_desc; 45 } 46 47 static struct x86_pmu_lbr *vcpu_to_lbr_records(struct kvm_vcpu *vcpu) 48 { 49 if (is_td_vcpu(vcpu)) 50 return NULL; 51 52 return &to_vmx(vcpu)->lbr_desc.records; 53 } 54 55 #pragma GCC poison to_vmx 56 57 static void reprogram_fixed_counters(struct kvm_pmu *pmu, u64 data) 58 { 59 struct kvm_pmc *pmc; 60 u64 old_fixed_ctr_ctrl = pmu->fixed_ctr_ctrl; 61 int i; 62 63 pmu->fixed_ctr_ctrl = data; 64 for (i = 0; i < pmu->nr_arch_fixed_counters; i++) { 65 u8 new_ctrl = fixed_ctrl_field(data, i); 66 u8 old_ctrl = fixed_ctrl_field(old_fixed_ctr_ctrl, i); 67 68 if (old_ctrl == new_ctrl) 69 continue; 70 71 pmc = get_fixed_pmc(pmu, MSR_CORE_PERF_FIXED_CTR0 + i); 72 73 __set_bit(KVM_FIXED_PMC_BASE_IDX + i, pmu->pmc_in_use); 74 kvm_pmu_request_counter_reprogram(pmc); 75 } 76 } 77 78 static struct kvm_pmc *intel_rdpmc_ecx_to_pmc(struct kvm_vcpu *vcpu, 79 unsigned int idx, u64 *mask) 80 { 81 unsigned int type = idx & INTEL_RDPMC_TYPE_MASK; 82 struct kvm_pmu *pmu = vcpu_to_pmu(vcpu); 83 struct kvm_pmc *counters; 84 unsigned int num_counters; 85 u64 bitmask; 86 87 /* 88 * The encoding of ECX for RDPMC is different for architectural versus 89 * non-architecturals PMUs (PMUs with version '0'). For architectural 90 * PMUs, bits 31:16 specify the PMC type and bits 15:0 specify the PMC 91 * index. For non-architectural PMUs, bit 31 is a "fast" flag, and 92 * bits 30:0 specify the PMC index. 93 * 94 * Yell and reject attempts to read PMCs for a non-architectural PMU, 95 * as KVM doesn't support such PMUs. 96 */ 97 if (WARN_ON_ONCE(!pmu->version)) 98 return NULL; 99 100 /* 101 * General Purpose (GP) PMCs are supported on all PMUs, and fixed PMCs 102 * are supported on all architectural PMUs, i.e. on all virtual PMUs 103 * supported by KVM. Note, KVM only emulates fixed PMCs for PMU v2+, 104 * but the type itself is still valid, i.e. let RDPMC fail due to 105 * accessing a non-existent counter. Reject attempts to read all other 106 * types, which are unknown/unsupported. 107 */ 108 switch (type) { 109 case INTEL_RDPMC_FIXED: 110 counters = pmu->fixed_counters; 111 num_counters = pmu->nr_arch_fixed_counters; 112 bitmask = pmu->counter_bitmask[KVM_PMC_FIXED]; 113 break; 114 case INTEL_RDPMC_GP: 115 counters = pmu->gp_counters; 116 num_counters = pmu->nr_arch_gp_counters; 117 bitmask = pmu->counter_bitmask[KVM_PMC_GP]; 118 break; 119 default: 120 return NULL; 121 } 122 123 idx &= INTEL_RDPMC_INDEX_MASK; 124 if (idx >= num_counters) 125 return NULL; 126 127 *mask &= bitmask; 128 return &counters[array_index_nospec(idx, num_counters)]; 129 } 130 131 static inline u64 vcpu_get_perf_capabilities(struct kvm_vcpu *vcpu) 132 { 133 if (!guest_cpu_cap_has(vcpu, X86_FEATURE_PDCM)) 134 return 0; 135 136 return vcpu->arch.perf_capabilities; 137 } 138 139 static inline bool fw_writes_is_enabled(struct kvm_vcpu *vcpu) 140 { 141 return (vcpu_get_perf_capabilities(vcpu) & PMU_CAP_FW_WRITES) != 0; 142 } 143 144 static inline struct kvm_pmc *get_fw_gp_pmc(struct kvm_pmu *pmu, u32 msr) 145 { 146 if (!fw_writes_is_enabled(pmu_to_vcpu(pmu))) 147 return NULL; 148 149 return get_gp_pmc(pmu, msr, MSR_IA32_PMC0); 150 } 151 152 static bool intel_pmu_lbr_is_compatible(struct kvm_vcpu *vcpu) 153 { 154 if (is_td_vcpu(vcpu)) 155 return false; 156 157 return cpuid_model_is_consistent(vcpu); 158 } 159 160 bool intel_pmu_lbr_is_enabled(struct kvm_vcpu *vcpu) 161 { 162 if (is_td_vcpu(vcpu)) 163 return false; 164 165 return !!vcpu_to_lbr_records(vcpu)->nr; 166 } 167 168 static bool intel_pmu_is_valid_lbr_msr(struct kvm_vcpu *vcpu, u32 index) 169 { 170 struct x86_pmu_lbr *records = vcpu_to_lbr_records(vcpu); 171 bool ret = false; 172 173 if (!intel_pmu_lbr_is_enabled(vcpu)) 174 return ret; 175 176 ret = (index == MSR_LBR_SELECT) || (index == MSR_LBR_TOS) || 177 (index >= records->from && index < records->from + records->nr) || 178 (index >= records->to && index < records->to + records->nr); 179 180 if (!ret && records->info) 181 ret = (index >= records->info && index < records->info + records->nr); 182 183 return ret; 184 } 185 186 static bool intel_is_valid_msr(struct kvm_vcpu *vcpu, u32 msr) 187 { 188 struct kvm_pmu *pmu = vcpu_to_pmu(vcpu); 189 u64 perf_capabilities; 190 int ret; 191 192 switch (msr) { 193 case MSR_CORE_PERF_FIXED_CTR_CTRL: 194 return kvm_pmu_has_perf_global_ctrl(pmu); 195 case MSR_IA32_PEBS_ENABLE: 196 ret = vcpu_get_perf_capabilities(vcpu) & PERF_CAP_PEBS_FORMAT; 197 break; 198 case MSR_IA32_DS_AREA: 199 ret = guest_cpu_cap_has(vcpu, X86_FEATURE_DS); 200 break; 201 case MSR_PEBS_DATA_CFG: 202 perf_capabilities = vcpu_get_perf_capabilities(vcpu); 203 ret = (perf_capabilities & PERF_CAP_PEBS_BASELINE) && 204 ((perf_capabilities & PERF_CAP_PEBS_FORMAT) > 3); 205 break; 206 default: 207 ret = get_gp_pmc(pmu, msr, MSR_IA32_PERFCTR0) || 208 get_gp_pmc(pmu, msr, MSR_P6_EVNTSEL0) || 209 get_fixed_pmc(pmu, msr) || get_fw_gp_pmc(pmu, msr) || 210 intel_pmu_is_valid_lbr_msr(vcpu, msr); 211 break; 212 } 213 214 return ret; 215 } 216 217 static struct kvm_pmc *intel_msr_idx_to_pmc(struct kvm_vcpu *vcpu, u32 msr) 218 { 219 struct kvm_pmu *pmu = vcpu_to_pmu(vcpu); 220 struct kvm_pmc *pmc; 221 222 pmc = get_fixed_pmc(pmu, msr); 223 pmc = pmc ? pmc : get_gp_pmc(pmu, msr, MSR_P6_EVNTSEL0); 224 pmc = pmc ? pmc : get_gp_pmc(pmu, msr, MSR_IA32_PERFCTR0); 225 226 return pmc; 227 } 228 229 static inline void intel_pmu_release_guest_lbr_event(struct kvm_vcpu *vcpu) 230 { 231 struct lbr_desc *lbr_desc = vcpu_to_lbr_desc(vcpu); 232 233 if (!lbr_desc) 234 return; 235 236 if (lbr_desc->event) { 237 perf_event_release_kernel(lbr_desc->event); 238 lbr_desc->event = NULL; 239 vcpu_to_pmu(vcpu)->event_count--; 240 } 241 } 242 243 int intel_pmu_create_guest_lbr_event(struct kvm_vcpu *vcpu) 244 { 245 struct lbr_desc *lbr_desc = vcpu_to_lbr_desc(vcpu); 246 struct kvm_pmu *pmu = vcpu_to_pmu(vcpu); 247 struct perf_event *event; 248 249 /* 250 * The perf_event_attr is constructed in the minimum efficient way: 251 * - set 'pinned = true' to make it task pinned so that if another 252 * cpu pinned event reclaims LBR, the event->oncpu will be set to -1; 253 * - set '.exclude_host = true' to record guest branches behavior; 254 * 255 * - set '.config = INTEL_FIXED_VLBR_EVENT' to indicates host perf 256 * schedule the event without a real HW counter but a fake one; 257 * check is_guest_lbr_event() and __intel_get_event_constraints(); 258 * 259 * - set 'sample_type = PERF_SAMPLE_BRANCH_STACK' and 260 * 'branch_sample_type = PERF_SAMPLE_BRANCH_CALL_STACK | 261 * PERF_SAMPLE_BRANCH_USER' to configure it as a LBR callstack 262 * event, which helps KVM to save/restore guest LBR records 263 * during host context switches and reduces quite a lot overhead, 264 * check branch_user_callstack() and intel_pmu_lbr_sched_task(); 265 */ 266 struct perf_event_attr attr = { 267 .type = PERF_TYPE_RAW, 268 .size = sizeof(attr), 269 .config = INTEL_FIXED_VLBR_EVENT, 270 .sample_type = PERF_SAMPLE_BRANCH_STACK, 271 .pinned = true, 272 .exclude_host = true, 273 .branch_sample_type = PERF_SAMPLE_BRANCH_CALL_STACK | 274 PERF_SAMPLE_BRANCH_USER, 275 }; 276 277 if (WARN_ON_ONCE(!lbr_desc)) 278 return 0; 279 280 if (unlikely(lbr_desc->event)) { 281 __set_bit(INTEL_PMC_IDX_FIXED_VLBR, pmu->pmc_in_use); 282 return 0; 283 } 284 285 event = perf_event_create_kernel_counter(&attr, -1, 286 current, NULL, NULL); 287 if (IS_ERR(event)) { 288 pr_debug_ratelimited("%s: failed %ld\n", 289 __func__, PTR_ERR(event)); 290 return PTR_ERR(event); 291 } 292 lbr_desc->event = event; 293 pmu->event_count++; 294 __set_bit(INTEL_PMC_IDX_FIXED_VLBR, pmu->pmc_in_use); 295 return 0; 296 } 297 298 /* 299 * It's safe to access LBR msrs from guest when they have not 300 * been passthrough since the host would help restore or reset 301 * the LBR msrs records when the guest LBR event is scheduled in. 302 */ 303 static bool intel_pmu_handle_lbr_msrs_access(struct kvm_vcpu *vcpu, 304 struct msr_data *msr_info, bool read) 305 { 306 struct lbr_desc *lbr_desc = vcpu_to_lbr_desc(vcpu); 307 u32 index = msr_info->index; 308 309 if (!intel_pmu_is_valid_lbr_msr(vcpu, index)) 310 return false; 311 312 if (!lbr_desc->event && intel_pmu_create_guest_lbr_event(vcpu) < 0) 313 goto dummy; 314 315 /* 316 * Disable irq to ensure the LBR feature doesn't get reclaimed by the 317 * host at the time the value is read from the msr, and this avoids the 318 * host LBR value to be leaked to the guest. If LBR has been reclaimed, 319 * return 0 on guest reads. 320 */ 321 local_irq_disable(); 322 if (lbr_desc->event->state == PERF_EVENT_STATE_ACTIVE) { 323 if (read) 324 rdmsrq(index, msr_info->data); 325 else 326 wrmsrq(index, msr_info->data); 327 __set_bit(INTEL_PMC_IDX_FIXED_VLBR, vcpu_to_pmu(vcpu)->pmc_in_use); 328 local_irq_enable(); 329 return true; 330 } 331 clear_bit(INTEL_PMC_IDX_FIXED_VLBR, vcpu_to_pmu(vcpu)->pmc_in_use); 332 local_irq_enable(); 333 334 dummy: 335 if (read) 336 msr_info->data = 0; 337 return true; 338 } 339 340 static int intel_pmu_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info) 341 { 342 struct kvm_pmu *pmu = vcpu_to_pmu(vcpu); 343 struct kvm_pmc *pmc; 344 u32 msr = msr_info->index; 345 346 switch (msr) { 347 case MSR_CORE_PERF_FIXED_CTR_CTRL: 348 msr_info->data = pmu->fixed_ctr_ctrl; 349 break; 350 case MSR_IA32_PEBS_ENABLE: 351 msr_info->data = pmu->pebs_enable; 352 break; 353 case MSR_IA32_DS_AREA: 354 msr_info->data = pmu->ds_area; 355 break; 356 case MSR_PEBS_DATA_CFG: 357 msr_info->data = pmu->pebs_data_cfg; 358 break; 359 default: 360 if ((pmc = get_gp_pmc(pmu, msr, MSR_IA32_PERFCTR0)) || 361 (pmc = get_gp_pmc(pmu, msr, MSR_IA32_PMC0))) { 362 u64 val = pmc_read_counter(pmc); 363 msr_info->data = 364 val & pmu->counter_bitmask[KVM_PMC_GP]; 365 break; 366 } else if ((pmc = get_fixed_pmc(pmu, msr))) { 367 u64 val = pmc_read_counter(pmc); 368 msr_info->data = 369 val & pmu->counter_bitmask[KVM_PMC_FIXED]; 370 break; 371 } else if ((pmc = get_gp_pmc(pmu, msr, MSR_P6_EVNTSEL0))) { 372 msr_info->data = pmc->eventsel; 373 break; 374 } else if (intel_pmu_handle_lbr_msrs_access(vcpu, msr_info, true)) { 375 break; 376 } 377 return 1; 378 } 379 380 return 0; 381 } 382 383 static int intel_pmu_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info) 384 { 385 struct kvm_pmu *pmu = vcpu_to_pmu(vcpu); 386 struct kvm_pmc *pmc; 387 u32 msr = msr_info->index; 388 u64 data = msr_info->data; 389 u64 reserved_bits, diff; 390 391 switch (msr) { 392 case MSR_CORE_PERF_FIXED_CTR_CTRL: 393 if (data & pmu->fixed_ctr_ctrl_rsvd) 394 return 1; 395 396 if (pmu->fixed_ctr_ctrl != data) 397 reprogram_fixed_counters(pmu, data); 398 break; 399 case MSR_IA32_PEBS_ENABLE: 400 if (data & pmu->pebs_enable_rsvd) 401 return 1; 402 403 if (pmu->pebs_enable != data) { 404 diff = pmu->pebs_enable ^ data; 405 pmu->pebs_enable = data; 406 reprogram_counters(pmu, diff); 407 } 408 break; 409 case MSR_IA32_DS_AREA: 410 if (is_noncanonical_msr_address(data, vcpu)) 411 return 1; 412 413 pmu->ds_area = data; 414 break; 415 case MSR_PEBS_DATA_CFG: 416 if (data & pmu->pebs_data_cfg_rsvd) 417 return 1; 418 419 pmu->pebs_data_cfg = data; 420 break; 421 default: 422 if ((pmc = get_gp_pmc(pmu, msr, MSR_IA32_PERFCTR0)) || 423 (pmc = get_gp_pmc(pmu, msr, MSR_IA32_PMC0))) { 424 if ((msr & MSR_PMC_FULL_WIDTH_BIT) && 425 (data & ~pmu->counter_bitmask[KVM_PMC_GP])) 426 return 1; 427 428 if (!msr_info->host_initiated && 429 !(msr & MSR_PMC_FULL_WIDTH_BIT)) 430 data = (s64)(s32)data; 431 pmc_write_counter(pmc, data); 432 break; 433 } else if ((pmc = get_fixed_pmc(pmu, msr))) { 434 pmc_write_counter(pmc, data); 435 break; 436 } else if ((pmc = get_gp_pmc(pmu, msr, MSR_P6_EVNTSEL0))) { 437 reserved_bits = pmu->reserved_bits; 438 if ((pmc->idx == 2) && 439 (pmu->raw_event_mask & HSW_IN_TX_CHECKPOINTED)) 440 reserved_bits ^= HSW_IN_TX_CHECKPOINTED; 441 if (data & reserved_bits) 442 return 1; 443 444 if (data != pmc->eventsel) { 445 pmc->eventsel = data; 446 kvm_pmu_request_counter_reprogram(pmc); 447 } 448 break; 449 } else if (intel_pmu_handle_lbr_msrs_access(vcpu, msr_info, false)) { 450 break; 451 } 452 /* Not a known PMU MSR. */ 453 return 1; 454 } 455 456 return 0; 457 } 458 459 /* 460 * Map fixed counter events to architectural general purpose event encodings. 461 * Perf doesn't provide APIs to allow KVM to directly program a fixed counter, 462 * and so KVM instead programs the architectural event to effectively request 463 * the fixed counter. Perf isn't guaranteed to use a fixed counter and may 464 * instead program the encoding into a general purpose counter, e.g. if a 465 * different perf_event is already utilizing the requested counter, but the end 466 * result is the same (ignoring the fact that using a general purpose counter 467 * will likely exacerbate counter contention). 468 * 469 * Forcibly inlined to allow asserting on @index at build time, and there should 470 * never be more than one user. 471 */ 472 static __always_inline u64 intel_get_fixed_pmc_eventsel(unsigned int index) 473 { 474 const enum perf_hw_id fixed_pmc_perf_ids[] = { 475 [0] = PERF_COUNT_HW_INSTRUCTIONS, 476 [1] = PERF_COUNT_HW_CPU_CYCLES, 477 [2] = PERF_COUNT_HW_REF_CPU_CYCLES, 478 }; 479 u64 eventsel; 480 481 BUILD_BUG_ON(ARRAY_SIZE(fixed_pmc_perf_ids) != KVM_MAX_NR_INTEL_FIXED_COUTNERS); 482 BUILD_BUG_ON(index >= KVM_MAX_NR_INTEL_FIXED_COUTNERS); 483 484 /* 485 * Yell if perf reports support for a fixed counter but perf doesn't 486 * have a known encoding for the associated general purpose event. 487 */ 488 eventsel = perf_get_hw_event_config(fixed_pmc_perf_ids[index]); 489 WARN_ON_ONCE(!eventsel && index < kvm_pmu_cap.num_counters_fixed); 490 return eventsel; 491 } 492 493 static void intel_pmu_enable_fixed_counter_bits(struct kvm_pmu *pmu, u64 bits) 494 { 495 int i; 496 497 for (i = 0; i < pmu->nr_arch_fixed_counters; i++) 498 pmu->fixed_ctr_ctrl_rsvd &= ~intel_fixed_bits_by_idx(i, bits); 499 } 500 501 static void intel_pmu_refresh(struct kvm_vcpu *vcpu) 502 { 503 struct kvm_pmu *pmu = vcpu_to_pmu(vcpu); 504 struct lbr_desc *lbr_desc = vcpu_to_lbr_desc(vcpu); 505 struct kvm_cpuid_entry2 *entry; 506 union cpuid10_eax eax; 507 union cpuid10_edx edx; 508 u64 perf_capabilities; 509 u64 counter_rsvd; 510 511 if (!lbr_desc) 512 return; 513 514 memset(&lbr_desc->records, 0, sizeof(lbr_desc->records)); 515 516 /* 517 * Setting passthrough of LBR MSRs is done only in the VM-Entry loop, 518 * and PMU refresh is disallowed after the vCPU has run, i.e. this code 519 * should never be reached while KVM is passing through MSRs. 520 */ 521 if (KVM_BUG_ON(lbr_desc->msr_passthrough, vcpu->kvm)) 522 return; 523 524 entry = kvm_find_cpuid_entry(vcpu, 0xa); 525 if (!entry) 526 return; 527 528 eax.full = entry->eax; 529 edx.full = entry->edx; 530 531 pmu->version = eax.split.version_id; 532 if (!pmu->version) 533 return; 534 535 pmu->nr_arch_gp_counters = min_t(int, eax.split.num_counters, 536 kvm_pmu_cap.num_counters_gp); 537 eax.split.bit_width = min_t(int, eax.split.bit_width, 538 kvm_pmu_cap.bit_width_gp); 539 pmu->counter_bitmask[KVM_PMC_GP] = ((u64)1 << eax.split.bit_width) - 1; 540 eax.split.mask_length = min_t(int, eax.split.mask_length, 541 kvm_pmu_cap.events_mask_len); 542 pmu->available_event_types = ~entry->ebx & 543 ((1ull << eax.split.mask_length) - 1); 544 545 if (pmu->version == 1) { 546 pmu->nr_arch_fixed_counters = 0; 547 } else { 548 pmu->nr_arch_fixed_counters = min_t(int, edx.split.num_counters_fixed, 549 kvm_pmu_cap.num_counters_fixed); 550 edx.split.bit_width_fixed = min_t(int, edx.split.bit_width_fixed, 551 kvm_pmu_cap.bit_width_fixed); 552 pmu->counter_bitmask[KVM_PMC_FIXED] = 553 ((u64)1 << edx.split.bit_width_fixed) - 1; 554 } 555 556 intel_pmu_enable_fixed_counter_bits(pmu, INTEL_FIXED_0_KERNEL | 557 INTEL_FIXED_0_USER | 558 INTEL_FIXED_0_ENABLE_PMI); 559 560 counter_rsvd = ~(((1ull << pmu->nr_arch_gp_counters) - 1) | 561 (((1ull << pmu->nr_arch_fixed_counters) - 1) << KVM_FIXED_PMC_BASE_IDX)); 562 pmu->global_ctrl_rsvd = counter_rsvd; 563 564 /* 565 * GLOBAL_STATUS and GLOBAL_OVF_CONTROL (a.k.a. GLOBAL_STATUS_RESET) 566 * share reserved bit definitions. The kernel just happens to use 567 * OVF_CTRL for the names. 568 */ 569 pmu->global_status_rsvd = pmu->global_ctrl_rsvd 570 & ~(MSR_CORE_PERF_GLOBAL_OVF_CTRL_OVF_BUF | 571 MSR_CORE_PERF_GLOBAL_OVF_CTRL_COND_CHGD); 572 if (vmx_pt_mode_is_host_guest()) 573 pmu->global_status_rsvd &= 574 ~MSR_CORE_PERF_GLOBAL_OVF_CTRL_TRACE_TOPA_PMI; 575 576 entry = kvm_find_cpuid_entry_index(vcpu, 7, 0); 577 if (entry && 578 (boot_cpu_has(X86_FEATURE_HLE) || boot_cpu_has(X86_FEATURE_RTM)) && 579 (entry->ebx & (X86_FEATURE_HLE|X86_FEATURE_RTM))) { 580 pmu->reserved_bits ^= HSW_IN_TX; 581 pmu->raw_event_mask |= (HSW_IN_TX|HSW_IN_TX_CHECKPOINTED); 582 } 583 584 bitmap_set(pmu->all_valid_pmc_idx, 585 0, pmu->nr_arch_gp_counters); 586 bitmap_set(pmu->all_valid_pmc_idx, 587 INTEL_PMC_MAX_GENERIC, pmu->nr_arch_fixed_counters); 588 589 perf_capabilities = vcpu_get_perf_capabilities(vcpu); 590 if (intel_pmu_lbr_is_compatible(vcpu) && 591 (perf_capabilities & PMU_CAP_LBR_FMT)) 592 memcpy(&lbr_desc->records, &vmx_lbr_caps, sizeof(vmx_lbr_caps)); 593 else 594 lbr_desc->records.nr = 0; 595 596 if (lbr_desc->records.nr) 597 bitmap_set(pmu->all_valid_pmc_idx, INTEL_PMC_IDX_FIXED_VLBR, 1); 598 599 if (perf_capabilities & PERF_CAP_PEBS_FORMAT) { 600 if (perf_capabilities & PERF_CAP_PEBS_BASELINE) { 601 pmu->pebs_enable_rsvd = counter_rsvd; 602 pmu->reserved_bits &= ~ICL_EVENTSEL_ADAPTIVE; 603 pmu->pebs_data_cfg_rsvd = ~0xff00000full; 604 intel_pmu_enable_fixed_counter_bits(pmu, ICL_FIXED_0_ADAPTIVE); 605 } else { 606 pmu->pebs_enable_rsvd = 607 ~((1ull << pmu->nr_arch_gp_counters) - 1); 608 } 609 } 610 } 611 612 static void intel_pmu_init(struct kvm_vcpu *vcpu) 613 { 614 int i; 615 struct kvm_pmu *pmu = vcpu_to_pmu(vcpu); 616 struct lbr_desc *lbr_desc = vcpu_to_lbr_desc(vcpu); 617 618 if (!lbr_desc) 619 return; 620 621 for (i = 0; i < KVM_MAX_NR_INTEL_GP_COUNTERS; i++) { 622 pmu->gp_counters[i].type = KVM_PMC_GP; 623 pmu->gp_counters[i].vcpu = vcpu; 624 pmu->gp_counters[i].idx = i; 625 pmu->gp_counters[i].current_config = 0; 626 } 627 628 for (i = 0; i < KVM_MAX_NR_INTEL_FIXED_COUTNERS; i++) { 629 pmu->fixed_counters[i].type = KVM_PMC_FIXED; 630 pmu->fixed_counters[i].vcpu = vcpu; 631 pmu->fixed_counters[i].idx = i + KVM_FIXED_PMC_BASE_IDX; 632 pmu->fixed_counters[i].current_config = 0; 633 pmu->fixed_counters[i].eventsel = intel_get_fixed_pmc_eventsel(i); 634 } 635 636 lbr_desc->records.nr = 0; 637 lbr_desc->event = NULL; 638 lbr_desc->msr_passthrough = false; 639 } 640 641 static void intel_pmu_reset(struct kvm_vcpu *vcpu) 642 { 643 intel_pmu_release_guest_lbr_event(vcpu); 644 } 645 646 /* 647 * Emulate LBR_On_PMI behavior for 1 < pmu.version < 4. 648 * 649 * If Freeze_LBR_On_PMI = 1, the LBR is frozen on PMI and 650 * the KVM emulates to clear the LBR bit (bit 0) in IA32_DEBUGCTL. 651 * 652 * Guest needs to re-enable LBR to resume branches recording. 653 */ 654 static void intel_pmu_legacy_freezing_lbrs_on_pmi(struct kvm_vcpu *vcpu) 655 { 656 u64 data = vmx_guest_debugctl_read(); 657 658 if (data & DEBUGCTLMSR_FREEZE_LBRS_ON_PMI) { 659 data &= ~DEBUGCTLMSR_LBR; 660 vmx_guest_debugctl_write(vcpu, data); 661 } 662 } 663 664 static void intel_pmu_deliver_pmi(struct kvm_vcpu *vcpu) 665 { 666 u8 version = vcpu_to_pmu(vcpu)->version; 667 668 if (!intel_pmu_lbr_is_enabled(vcpu)) 669 return; 670 671 if (version > 1 && version < 4) 672 intel_pmu_legacy_freezing_lbrs_on_pmi(vcpu); 673 } 674 675 static void vmx_update_intercept_for_lbr_msrs(struct kvm_vcpu *vcpu, bool set) 676 { 677 struct x86_pmu_lbr *lbr = vcpu_to_lbr_records(vcpu); 678 int i; 679 680 for (i = 0; i < lbr->nr; i++) { 681 vmx_set_intercept_for_msr(vcpu, lbr->from + i, MSR_TYPE_RW, set); 682 vmx_set_intercept_for_msr(vcpu, lbr->to + i, MSR_TYPE_RW, set); 683 if (lbr->info) 684 vmx_set_intercept_for_msr(vcpu, lbr->info + i, MSR_TYPE_RW, set); 685 } 686 687 vmx_set_intercept_for_msr(vcpu, MSR_LBR_SELECT, MSR_TYPE_RW, set); 688 vmx_set_intercept_for_msr(vcpu, MSR_LBR_TOS, MSR_TYPE_RW, set); 689 } 690 691 static inline void vmx_disable_lbr_msrs_passthrough(struct kvm_vcpu *vcpu) 692 { 693 struct lbr_desc *lbr_desc = vcpu_to_lbr_desc(vcpu); 694 695 if (!lbr_desc->msr_passthrough) 696 return; 697 698 vmx_update_intercept_for_lbr_msrs(vcpu, true); 699 lbr_desc->msr_passthrough = false; 700 } 701 702 static inline void vmx_enable_lbr_msrs_passthrough(struct kvm_vcpu *vcpu) 703 { 704 struct lbr_desc *lbr_desc = vcpu_to_lbr_desc(vcpu); 705 706 if (lbr_desc->msr_passthrough) 707 return; 708 709 vmx_update_intercept_for_lbr_msrs(vcpu, false); 710 lbr_desc->msr_passthrough = true; 711 } 712 713 /* 714 * Higher priority host perf events (e.g. cpu pinned) could reclaim the 715 * pmu resources (e.g. LBR) that were assigned to the guest. This is 716 * usually done via ipi calls (more details in perf_install_in_context). 717 * 718 * Before entering the non-root mode (with irq disabled here), double 719 * confirm that the pmu features enabled to the guest are not reclaimed 720 * by higher priority host events. Otherwise, disallow vcpu's access to 721 * the reclaimed features. 722 */ 723 void vmx_passthrough_lbr_msrs(struct kvm_vcpu *vcpu) 724 { 725 struct kvm_pmu *pmu = vcpu_to_pmu(vcpu); 726 struct lbr_desc *lbr_desc = vcpu_to_lbr_desc(vcpu); 727 728 if (WARN_ON_ONCE(!lbr_desc)) 729 return; 730 731 if (!lbr_desc->event) { 732 vmx_disable_lbr_msrs_passthrough(vcpu); 733 if (vmx_guest_debugctl_read() & DEBUGCTLMSR_LBR) 734 goto warn; 735 if (test_bit(INTEL_PMC_IDX_FIXED_VLBR, pmu->pmc_in_use)) 736 goto warn; 737 return; 738 } 739 740 if (lbr_desc->event->state < PERF_EVENT_STATE_ACTIVE) { 741 vmx_disable_lbr_msrs_passthrough(vcpu); 742 __clear_bit(INTEL_PMC_IDX_FIXED_VLBR, pmu->pmc_in_use); 743 goto warn; 744 } else 745 vmx_enable_lbr_msrs_passthrough(vcpu); 746 747 return; 748 749 warn: 750 pr_warn_ratelimited("vcpu-%d: fail to passthrough LBR.\n", vcpu->vcpu_id); 751 } 752 753 static void intel_pmu_cleanup(struct kvm_vcpu *vcpu) 754 { 755 if (!(vmx_guest_debugctl_read() & DEBUGCTLMSR_LBR)) 756 intel_pmu_release_guest_lbr_event(vcpu); 757 } 758 759 void intel_pmu_cross_mapped_check(struct kvm_pmu *pmu) 760 { 761 struct kvm_pmc *pmc = NULL; 762 int bit, hw_idx; 763 764 kvm_for_each_pmc(pmu, pmc, bit, (unsigned long *)&pmu->global_ctrl) { 765 if (!pmc_speculative_in_use(pmc) || 766 !pmc_is_globally_enabled(pmc) || !pmc->perf_event) 767 continue; 768 769 /* 770 * A negative index indicates the event isn't mapped to a 771 * physical counter in the host, e.g. due to contention. 772 */ 773 hw_idx = pmc->perf_event->hw.idx; 774 if (hw_idx != pmc->idx && hw_idx > -1) 775 pmu->host_cross_mapped_mask |= BIT_ULL(hw_idx); 776 } 777 } 778 779 struct kvm_pmu_ops intel_pmu_ops __initdata = { 780 .rdpmc_ecx_to_pmc = intel_rdpmc_ecx_to_pmc, 781 .msr_idx_to_pmc = intel_msr_idx_to_pmc, 782 .is_valid_msr = intel_is_valid_msr, 783 .get_msr = intel_pmu_get_msr, 784 .set_msr = intel_pmu_set_msr, 785 .refresh = intel_pmu_refresh, 786 .init = intel_pmu_init, 787 .reset = intel_pmu_reset, 788 .deliver_pmi = intel_pmu_deliver_pmi, 789 .cleanup = intel_pmu_cleanup, 790 .EVENTSEL_EVENT = ARCH_PERFMON_EVENTSEL_EVENT, 791 .MAX_NR_GP_COUNTERS = KVM_MAX_NR_INTEL_GP_COUNTERS, 792 .MIN_NR_GP_COUNTERS = 1, 793 }; 794