1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef __KVM_X86_VMX_NESTED_H 3 #define __KVM_X86_VMX_NESTED_H 4 5 #include "kvm_cache_regs.h" 6 #include "hyperv.h" 7 #include "vmcs12.h" 8 #include "vmx.h" 9 10 /* 11 * Status returned by nested_vmx_enter_non_root_mode(): 12 */ 13 enum nvmx_vmentry_status { 14 NVMX_VMENTRY_SUCCESS, /* Entered VMX non-root mode */ 15 NVMX_VMENTRY_VMFAIL, /* Consistency check VMFail */ 16 NVMX_VMENTRY_VMEXIT, /* Consistency check VMExit */ 17 NVMX_VMENTRY_KVM_INTERNAL_ERROR,/* KVM internal error */ 18 }; 19 20 void vmx_leave_nested(struct kvm_vcpu *vcpu); 21 void nested_vmx_setup_ctls_msrs(struct vmcs_config *vmcs_conf, u32 ept_caps); 22 void nested_vmx_hardware_unsetup(void); 23 __init int nested_vmx_hardware_setup(int (*exit_handlers[])(struct kvm_vcpu *)); 24 void nested_vmx_set_vmcs_shadowing_bitmap(void); 25 void nested_vmx_free_vcpu(struct kvm_vcpu *vcpu); 26 enum nvmx_vmentry_status nested_vmx_enter_non_root_mode(struct kvm_vcpu *vcpu, 27 bool from_vmentry); 28 bool nested_vmx_reflect_vmexit(struct kvm_vcpu *vcpu); 29 void __nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 vm_exit_reason, 30 u32 exit_intr_info, unsigned long exit_qualification, 31 u32 exit_insn_len); 32 33 static inline void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 vm_exit_reason, 34 u32 exit_intr_info, 35 unsigned long exit_qualification) 36 { 37 u32 exit_insn_len; 38 39 if (to_vmx(vcpu)->fail || vm_exit_reason == -1 || 40 (vm_exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY)) 41 exit_insn_len = 0; 42 else 43 exit_insn_len = vmcs_read32(VM_EXIT_INSTRUCTION_LEN); 44 45 __nested_vmx_vmexit(vcpu, vm_exit_reason, exit_intr_info, 46 exit_qualification, exit_insn_len); 47 } 48 49 void nested_sync_vmcs12_to_shadow(struct kvm_vcpu *vcpu); 50 int vmx_set_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data); 51 int vmx_get_vmx_msr(struct nested_vmx_msrs *msrs, u32 msr_index, u64 *pdata); 52 int get_vmx_mem_address(struct kvm_vcpu *vcpu, unsigned long exit_qualification, 53 u32 vmx_instruction_info, bool wr, int len, gva_t *ret); 54 bool nested_vmx_check_io_bitmaps(struct kvm_vcpu *vcpu, unsigned int port, 55 int size); 56 57 static inline struct vmcs12 *get_vmcs12(struct kvm_vcpu *vcpu) 58 { 59 lockdep_assert_once(lockdep_is_held(&vcpu->mutex) || 60 !refcount_read(&vcpu->kvm->users_count)); 61 62 return to_vmx(vcpu)->nested.cached_vmcs12; 63 } 64 65 static inline struct vmcs12 *get_shadow_vmcs12(struct kvm_vcpu *vcpu) 66 { 67 lockdep_assert_once(lockdep_is_held(&vcpu->mutex) || 68 !refcount_read(&vcpu->kvm->users_count)); 69 70 return to_vmx(vcpu)->nested.cached_shadow_vmcs12; 71 } 72 73 /* 74 * Note: the same condition is checked against the state provided by userspace 75 * in vmx_set_nested_state; if it is satisfied, the nested state must include 76 * the VMCS12. 77 */ 78 static inline int vmx_has_valid_vmcs12(struct kvm_vcpu *vcpu) 79 { 80 struct vcpu_vmx *vmx = to_vmx(vcpu); 81 82 /* 'hv_evmcs_vmptr' can also be EVMPTR_MAP_PENDING here */ 83 return vmx->nested.current_vmptr != -1ull || 84 nested_vmx_is_evmptr12_set(vmx); 85 } 86 87 static inline u16 nested_get_vpid02(struct kvm_vcpu *vcpu) 88 { 89 struct vcpu_vmx *vmx = to_vmx(vcpu); 90 91 return vmx->nested.vpid02 ? vmx->nested.vpid02 : vmx->vpid; 92 } 93 94 static inline unsigned long nested_ept_get_eptp(struct kvm_vcpu *vcpu) 95 { 96 /* return the page table to be shadowed - in our case, EPT12 */ 97 return get_vmcs12(vcpu)->ept_pointer; 98 } 99 100 static inline bool nested_ept_ad_enabled(struct kvm_vcpu *vcpu) 101 { 102 return nested_ept_get_eptp(vcpu) & VMX_EPTP_AD_ENABLE_BIT; 103 } 104 105 /* 106 * Return the cr0/4 value that a nested guest would read. This is a combination 107 * of L1's "real" cr0 used to run the guest (guest_cr0), and the bits shadowed 108 * by the L1 hypervisor (cr0_read_shadow). KVM must emulate CPU behavior as 109 * the value+mask loaded into vmcs02 may not match the vmcs12 fields. 110 */ 111 static inline unsigned long nested_read_cr0(struct vmcs12 *fields) 112 { 113 return (fields->guest_cr0 & ~fields->cr0_guest_host_mask) | 114 (fields->cr0_read_shadow & fields->cr0_guest_host_mask); 115 } 116 static inline unsigned long nested_read_cr4(struct vmcs12 *fields) 117 { 118 return (fields->guest_cr4 & ~fields->cr4_guest_host_mask) | 119 (fields->cr4_read_shadow & fields->cr4_guest_host_mask); 120 } 121 122 static inline unsigned nested_cpu_vmx_misc_cr3_count(struct kvm_vcpu *vcpu) 123 { 124 return vmx_misc_cr3_count(to_vmx(vcpu)->nested.msrs.misc_low); 125 } 126 127 /* 128 * Do the virtual VMX capability MSRs specify that L1 can use VMWRITE 129 * to modify any valid field of the VMCS, or are the VM-exit 130 * information fields read-only? 131 */ 132 static inline bool nested_cpu_has_vmwrite_any_field(struct kvm_vcpu *vcpu) 133 { 134 return to_vmx(vcpu)->nested.msrs.misc_low & 135 VMX_MISC_VMWRITE_SHADOW_RO_FIELDS; 136 } 137 138 static inline bool nested_cpu_has_zero_length_injection(struct kvm_vcpu *vcpu) 139 { 140 return to_vmx(vcpu)->nested.msrs.misc_low & VMX_MISC_ZERO_LEN_INS; 141 } 142 143 static inline bool nested_cpu_supports_monitor_trap_flag(struct kvm_vcpu *vcpu) 144 { 145 return to_vmx(vcpu)->nested.msrs.procbased_ctls_high & 146 CPU_BASED_MONITOR_TRAP_FLAG; 147 } 148 149 static inline bool nested_cpu_has_vmx_shadow_vmcs(struct kvm_vcpu *vcpu) 150 { 151 return to_vmx(vcpu)->nested.msrs.secondary_ctls_high & 152 SECONDARY_EXEC_SHADOW_VMCS; 153 } 154 155 static inline bool nested_cpu_has(struct vmcs12 *vmcs12, u32 bit) 156 { 157 return vmcs12->cpu_based_vm_exec_control & bit; 158 } 159 160 static inline bool nested_cpu_has2(struct vmcs12 *vmcs12, u32 bit) 161 { 162 return (vmcs12->cpu_based_vm_exec_control & 163 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) && 164 (vmcs12->secondary_vm_exec_control & bit); 165 } 166 167 static inline bool nested_cpu_has_preemption_timer(struct vmcs12 *vmcs12) 168 { 169 return vmcs12->pin_based_vm_exec_control & 170 PIN_BASED_VMX_PREEMPTION_TIMER; 171 } 172 173 static inline bool nested_cpu_has_nmi_exiting(struct vmcs12 *vmcs12) 174 { 175 return vmcs12->pin_based_vm_exec_control & PIN_BASED_NMI_EXITING; 176 } 177 178 static inline bool nested_cpu_has_virtual_nmis(struct vmcs12 *vmcs12) 179 { 180 return vmcs12->pin_based_vm_exec_control & PIN_BASED_VIRTUAL_NMIS; 181 } 182 183 static inline int nested_cpu_has_mtf(struct vmcs12 *vmcs12) 184 { 185 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_TRAP_FLAG); 186 } 187 188 static inline int nested_cpu_has_ept(struct vmcs12 *vmcs12) 189 { 190 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_EPT); 191 } 192 193 static inline bool nested_cpu_has_xsaves(struct vmcs12 *vmcs12) 194 { 195 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_XSAVES); 196 } 197 198 static inline bool nested_cpu_has_pml(struct vmcs12 *vmcs12) 199 { 200 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_PML); 201 } 202 203 static inline bool nested_cpu_has_virt_x2apic_mode(struct vmcs12 *vmcs12) 204 { 205 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE); 206 } 207 208 static inline bool nested_cpu_has_vpid(struct vmcs12 *vmcs12) 209 { 210 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_VPID); 211 } 212 213 static inline bool nested_cpu_has_apic_reg_virt(struct vmcs12 *vmcs12) 214 { 215 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_APIC_REGISTER_VIRT); 216 } 217 218 static inline bool nested_cpu_has_vid(struct vmcs12 *vmcs12) 219 { 220 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY); 221 } 222 223 static inline bool nested_cpu_has_posted_intr(struct vmcs12 *vmcs12) 224 { 225 return vmcs12->pin_based_vm_exec_control & PIN_BASED_POSTED_INTR; 226 } 227 228 static inline bool nested_cpu_has_vmfunc(struct vmcs12 *vmcs12) 229 { 230 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_VMFUNC); 231 } 232 233 static inline bool nested_cpu_has_eptp_switching(struct vmcs12 *vmcs12) 234 { 235 return nested_cpu_has_vmfunc(vmcs12) && 236 (vmcs12->vm_function_control & 237 VMX_VMFUNC_EPTP_SWITCHING); 238 } 239 240 static inline bool nested_cpu_has_shadow_vmcs(struct vmcs12 *vmcs12) 241 { 242 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_SHADOW_VMCS); 243 } 244 245 static inline bool nested_cpu_has_save_preemption_timer(struct vmcs12 *vmcs12) 246 { 247 return vmcs12->vm_exit_controls & 248 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER; 249 } 250 251 static inline bool nested_exit_on_nmi(struct kvm_vcpu *vcpu) 252 { 253 return nested_cpu_has_nmi_exiting(get_vmcs12(vcpu)); 254 } 255 256 /* 257 * In nested virtualization, check if L1 asked to exit on external interrupts. 258 * For most existing hypervisors, this will always return true. 259 */ 260 static inline bool nested_exit_on_intr(struct kvm_vcpu *vcpu) 261 { 262 return get_vmcs12(vcpu)->pin_based_vm_exec_control & 263 PIN_BASED_EXT_INTR_MASK; 264 } 265 266 static inline bool nested_cpu_has_encls_exit(struct vmcs12 *vmcs12) 267 { 268 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENCLS_EXITING); 269 } 270 271 /* 272 * if fixed0[i] == 1: val[i] must be 1 273 * if fixed1[i] == 0: val[i] must be 0 274 */ 275 static inline bool fixed_bits_valid(u64 val, u64 fixed0, u64 fixed1) 276 { 277 return ((val & fixed1) | fixed0) == val; 278 } 279 280 static inline bool nested_guest_cr0_valid(struct kvm_vcpu *vcpu, unsigned long val) 281 { 282 u64 fixed0 = to_vmx(vcpu)->nested.msrs.cr0_fixed0; 283 u64 fixed1 = to_vmx(vcpu)->nested.msrs.cr0_fixed1; 284 struct vmcs12 *vmcs12 = get_vmcs12(vcpu); 285 286 if (to_vmx(vcpu)->nested.msrs.secondary_ctls_high & 287 SECONDARY_EXEC_UNRESTRICTED_GUEST && 288 nested_cpu_has2(vmcs12, SECONDARY_EXEC_UNRESTRICTED_GUEST)) 289 fixed0 &= ~(X86_CR0_PE | X86_CR0_PG); 290 291 return fixed_bits_valid(val, fixed0, fixed1); 292 } 293 294 static inline bool nested_host_cr0_valid(struct kvm_vcpu *vcpu, unsigned long val) 295 { 296 u64 fixed0 = to_vmx(vcpu)->nested.msrs.cr0_fixed0; 297 u64 fixed1 = to_vmx(vcpu)->nested.msrs.cr0_fixed1; 298 299 return fixed_bits_valid(val, fixed0, fixed1); 300 } 301 302 static inline bool nested_cr4_valid(struct kvm_vcpu *vcpu, unsigned long val) 303 { 304 u64 fixed0 = to_vmx(vcpu)->nested.msrs.cr4_fixed0; 305 u64 fixed1 = to_vmx(vcpu)->nested.msrs.cr4_fixed1; 306 307 return fixed_bits_valid(val, fixed0, fixed1) && 308 __kvm_is_valid_cr4(vcpu, val); 309 } 310 311 static inline bool nested_cpu_has_no_hw_errcode_cc(struct kvm_vcpu *vcpu) 312 { 313 return to_vmx(vcpu)->nested.msrs.basic & VMX_BASIC_NO_HW_ERROR_CODE_CC; 314 } 315 316 /* No difference in the restrictions on guest and host CR4 in VMX operation. */ 317 #define nested_guest_cr4_valid nested_cr4_valid 318 #define nested_host_cr4_valid nested_cr4_valid 319 320 extern struct kvm_x86_nested_ops vmx_nested_ops; 321 322 #endif /* __KVM_X86_VMX_NESTED_H */ 323