1 // SPDX-License-Identifier: GPL-2.0 2 3 #include <linux/frame.h> 4 #include <linux/percpu.h> 5 6 #include <asm/debugreg.h> 7 #include <asm/mmu_context.h> 8 9 #include "cpuid.h" 10 #include "hyperv.h" 11 #include "mmu.h" 12 #include "nested.h" 13 #include "pmu.h" 14 #include "trace.h" 15 #include "x86.h" 16 17 static bool __read_mostly enable_shadow_vmcs = 1; 18 module_param_named(enable_shadow_vmcs, enable_shadow_vmcs, bool, S_IRUGO); 19 20 static bool __read_mostly nested_early_check = 0; 21 module_param(nested_early_check, bool, S_IRUGO); 22 23 #define CC(consistency_check) \ 24 ({ \ 25 bool failed = (consistency_check); \ 26 if (failed) \ 27 trace_kvm_nested_vmenter_failed(#consistency_check, 0); \ 28 failed; \ 29 }) 30 31 /* 32 * Hyper-V requires all of these, so mark them as supported even though 33 * they are just treated the same as all-context. 34 */ 35 #define VMX_VPID_EXTENT_SUPPORTED_MASK \ 36 (VMX_VPID_EXTENT_INDIVIDUAL_ADDR_BIT | \ 37 VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT | \ 38 VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT | \ 39 VMX_VPID_EXTENT_SINGLE_NON_GLOBAL_BIT) 40 41 #define VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE 5 42 43 enum { 44 VMX_VMREAD_BITMAP, 45 VMX_VMWRITE_BITMAP, 46 VMX_BITMAP_NR 47 }; 48 static unsigned long *vmx_bitmap[VMX_BITMAP_NR]; 49 50 #define vmx_vmread_bitmap (vmx_bitmap[VMX_VMREAD_BITMAP]) 51 #define vmx_vmwrite_bitmap (vmx_bitmap[VMX_VMWRITE_BITMAP]) 52 53 struct shadow_vmcs_field { 54 u16 encoding; 55 u16 offset; 56 }; 57 static struct shadow_vmcs_field shadow_read_only_fields[] = { 58 #define SHADOW_FIELD_RO(x, y) { x, offsetof(struct vmcs12, y) }, 59 #include "vmcs_shadow_fields.h" 60 }; 61 static int max_shadow_read_only_fields = 62 ARRAY_SIZE(shadow_read_only_fields); 63 64 static struct shadow_vmcs_field shadow_read_write_fields[] = { 65 #define SHADOW_FIELD_RW(x, y) { x, offsetof(struct vmcs12, y) }, 66 #include "vmcs_shadow_fields.h" 67 }; 68 static int max_shadow_read_write_fields = 69 ARRAY_SIZE(shadow_read_write_fields); 70 71 static void init_vmcs_shadow_fields(void) 72 { 73 int i, j; 74 75 memset(vmx_vmread_bitmap, 0xff, PAGE_SIZE); 76 memset(vmx_vmwrite_bitmap, 0xff, PAGE_SIZE); 77 78 for (i = j = 0; i < max_shadow_read_only_fields; i++) { 79 struct shadow_vmcs_field entry = shadow_read_only_fields[i]; 80 u16 field = entry.encoding; 81 82 if (vmcs_field_width(field) == VMCS_FIELD_WIDTH_U64 && 83 (i + 1 == max_shadow_read_only_fields || 84 shadow_read_only_fields[i + 1].encoding != field + 1)) 85 pr_err("Missing field from shadow_read_only_field %x\n", 86 field + 1); 87 88 clear_bit(field, vmx_vmread_bitmap); 89 if (field & 1) 90 #ifdef CONFIG_X86_64 91 continue; 92 #else 93 entry.offset += sizeof(u32); 94 #endif 95 shadow_read_only_fields[j++] = entry; 96 } 97 max_shadow_read_only_fields = j; 98 99 for (i = j = 0; i < max_shadow_read_write_fields; i++) { 100 struct shadow_vmcs_field entry = shadow_read_write_fields[i]; 101 u16 field = entry.encoding; 102 103 if (vmcs_field_width(field) == VMCS_FIELD_WIDTH_U64 && 104 (i + 1 == max_shadow_read_write_fields || 105 shadow_read_write_fields[i + 1].encoding != field + 1)) 106 pr_err("Missing field from shadow_read_write_field %x\n", 107 field + 1); 108 109 WARN_ONCE(field >= GUEST_ES_AR_BYTES && 110 field <= GUEST_TR_AR_BYTES, 111 "Update vmcs12_write_any() to drop reserved bits from AR_BYTES"); 112 113 /* 114 * PML and the preemption timer can be emulated, but the 115 * processor cannot vmwrite to fields that don't exist 116 * on bare metal. 117 */ 118 switch (field) { 119 case GUEST_PML_INDEX: 120 if (!cpu_has_vmx_pml()) 121 continue; 122 break; 123 case VMX_PREEMPTION_TIMER_VALUE: 124 if (!cpu_has_vmx_preemption_timer()) 125 continue; 126 break; 127 case GUEST_INTR_STATUS: 128 if (!cpu_has_vmx_apicv()) 129 continue; 130 break; 131 default: 132 break; 133 } 134 135 clear_bit(field, vmx_vmwrite_bitmap); 136 clear_bit(field, vmx_vmread_bitmap); 137 if (field & 1) 138 #ifdef CONFIG_X86_64 139 continue; 140 #else 141 entry.offset += sizeof(u32); 142 #endif 143 shadow_read_write_fields[j++] = entry; 144 } 145 max_shadow_read_write_fields = j; 146 } 147 148 /* 149 * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(), 150 * set the success or error code of an emulated VMX instruction (as specified 151 * by Vol 2B, VMX Instruction Reference, "Conventions"), and skip the emulated 152 * instruction. 153 */ 154 static int nested_vmx_succeed(struct kvm_vcpu *vcpu) 155 { 156 vmx_set_rflags(vcpu, vmx_get_rflags(vcpu) 157 & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF | 158 X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF)); 159 return kvm_skip_emulated_instruction(vcpu); 160 } 161 162 static int nested_vmx_failInvalid(struct kvm_vcpu *vcpu) 163 { 164 vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu) 165 & ~(X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF | 166 X86_EFLAGS_SF | X86_EFLAGS_OF)) 167 | X86_EFLAGS_CF); 168 return kvm_skip_emulated_instruction(vcpu); 169 } 170 171 static int nested_vmx_failValid(struct kvm_vcpu *vcpu, 172 u32 vm_instruction_error) 173 { 174 struct vcpu_vmx *vmx = to_vmx(vcpu); 175 176 /* 177 * failValid writes the error number to the current VMCS, which 178 * can't be done if there isn't a current VMCS. 179 */ 180 if (vmx->nested.current_vmptr == -1ull && !vmx->nested.hv_evmcs) 181 return nested_vmx_failInvalid(vcpu); 182 183 vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu) 184 & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF | 185 X86_EFLAGS_SF | X86_EFLAGS_OF)) 186 | X86_EFLAGS_ZF); 187 get_vmcs12(vcpu)->vm_instruction_error = vm_instruction_error; 188 /* 189 * We don't need to force a shadow sync because 190 * VM_INSTRUCTION_ERROR is not shadowed 191 */ 192 return kvm_skip_emulated_instruction(vcpu); 193 } 194 195 static void nested_vmx_abort(struct kvm_vcpu *vcpu, u32 indicator) 196 { 197 /* TODO: not to reset guest simply here. */ 198 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); 199 pr_debug_ratelimited("kvm: nested vmx abort, indicator %d\n", indicator); 200 } 201 202 static inline bool vmx_control_verify(u32 control, u32 low, u32 high) 203 { 204 return fixed_bits_valid(control, low, high); 205 } 206 207 static inline u64 vmx_control_msr(u32 low, u32 high) 208 { 209 return low | ((u64)high << 32); 210 } 211 212 static void vmx_disable_shadow_vmcs(struct vcpu_vmx *vmx) 213 { 214 secondary_exec_controls_clearbit(vmx, SECONDARY_EXEC_SHADOW_VMCS); 215 vmcs_write64(VMCS_LINK_POINTER, -1ull); 216 vmx->nested.need_vmcs12_to_shadow_sync = false; 217 } 218 219 static inline void nested_release_evmcs(struct kvm_vcpu *vcpu) 220 { 221 struct vcpu_vmx *vmx = to_vmx(vcpu); 222 223 if (!vmx->nested.hv_evmcs) 224 return; 225 226 kvm_vcpu_unmap(vcpu, &vmx->nested.hv_evmcs_map, true); 227 vmx->nested.hv_evmcs_vmptr = -1ull; 228 vmx->nested.hv_evmcs = NULL; 229 } 230 231 /* 232 * Free whatever needs to be freed from vmx->nested when L1 goes down, or 233 * just stops using VMX. 234 */ 235 static void free_nested(struct kvm_vcpu *vcpu) 236 { 237 struct vcpu_vmx *vmx = to_vmx(vcpu); 238 239 if (!vmx->nested.vmxon && !vmx->nested.smm.vmxon) 240 return; 241 242 kvm_clear_request(KVM_REQ_GET_VMCS12_PAGES, vcpu); 243 244 vmx->nested.vmxon = false; 245 vmx->nested.smm.vmxon = false; 246 free_vpid(vmx->nested.vpid02); 247 vmx->nested.posted_intr_nv = -1; 248 vmx->nested.current_vmptr = -1ull; 249 if (enable_shadow_vmcs) { 250 vmx_disable_shadow_vmcs(vmx); 251 vmcs_clear(vmx->vmcs01.shadow_vmcs); 252 free_vmcs(vmx->vmcs01.shadow_vmcs); 253 vmx->vmcs01.shadow_vmcs = NULL; 254 } 255 kfree(vmx->nested.cached_vmcs12); 256 vmx->nested.cached_vmcs12 = NULL; 257 kfree(vmx->nested.cached_shadow_vmcs12); 258 vmx->nested.cached_shadow_vmcs12 = NULL; 259 /* Unpin physical memory we referred to in the vmcs02 */ 260 if (vmx->nested.apic_access_page) { 261 kvm_release_page_clean(vmx->nested.apic_access_page); 262 vmx->nested.apic_access_page = NULL; 263 } 264 kvm_vcpu_unmap(vcpu, &vmx->nested.virtual_apic_map, true); 265 kvm_vcpu_unmap(vcpu, &vmx->nested.pi_desc_map, true); 266 vmx->nested.pi_desc = NULL; 267 268 kvm_mmu_free_roots(vcpu, &vcpu->arch.guest_mmu, KVM_MMU_ROOTS_ALL); 269 270 nested_release_evmcs(vcpu); 271 272 free_loaded_vmcs(&vmx->nested.vmcs02); 273 } 274 275 static void vmx_sync_vmcs_host_state(struct vcpu_vmx *vmx, 276 struct loaded_vmcs *prev) 277 { 278 struct vmcs_host_state *dest, *src; 279 280 if (unlikely(!vmx->guest_state_loaded)) 281 return; 282 283 src = &prev->host_state; 284 dest = &vmx->loaded_vmcs->host_state; 285 286 vmx_set_host_fs_gs(dest, src->fs_sel, src->gs_sel, src->fs_base, src->gs_base); 287 dest->ldt_sel = src->ldt_sel; 288 #ifdef CONFIG_X86_64 289 dest->ds_sel = src->ds_sel; 290 dest->es_sel = src->es_sel; 291 #endif 292 } 293 294 static void vmx_switch_vmcs(struct kvm_vcpu *vcpu, struct loaded_vmcs *vmcs) 295 { 296 struct vcpu_vmx *vmx = to_vmx(vcpu); 297 struct loaded_vmcs *prev; 298 int cpu; 299 300 if (vmx->loaded_vmcs == vmcs) 301 return; 302 303 cpu = get_cpu(); 304 prev = vmx->loaded_vmcs; 305 vmx->loaded_vmcs = vmcs; 306 vmx_vcpu_load_vmcs(vcpu, cpu); 307 vmx_sync_vmcs_host_state(vmx, prev); 308 put_cpu(); 309 310 vmx_segment_cache_clear(vmx); 311 } 312 313 /* 314 * Ensure that the current vmcs of the logical processor is the 315 * vmcs01 of the vcpu before calling free_nested(). 316 */ 317 void nested_vmx_free_vcpu(struct kvm_vcpu *vcpu) 318 { 319 vcpu_load(vcpu); 320 vmx_leave_nested(vcpu); 321 vmx_switch_vmcs(vcpu, &to_vmx(vcpu)->vmcs01); 322 free_nested(vcpu); 323 vcpu_put(vcpu); 324 } 325 326 static void nested_ept_inject_page_fault(struct kvm_vcpu *vcpu, 327 struct x86_exception *fault) 328 { 329 struct vmcs12 *vmcs12 = get_vmcs12(vcpu); 330 struct vcpu_vmx *vmx = to_vmx(vcpu); 331 u32 exit_reason; 332 unsigned long exit_qualification = vcpu->arch.exit_qualification; 333 334 if (vmx->nested.pml_full) { 335 exit_reason = EXIT_REASON_PML_FULL; 336 vmx->nested.pml_full = false; 337 exit_qualification &= INTR_INFO_UNBLOCK_NMI; 338 } else if (fault->error_code & PFERR_RSVD_MASK) 339 exit_reason = EXIT_REASON_EPT_MISCONFIG; 340 else 341 exit_reason = EXIT_REASON_EPT_VIOLATION; 342 343 nested_vmx_vmexit(vcpu, exit_reason, 0, exit_qualification); 344 vmcs12->guest_physical_address = fault->address; 345 } 346 347 static void nested_ept_init_mmu_context(struct kvm_vcpu *vcpu) 348 { 349 WARN_ON(mmu_is_nested(vcpu)); 350 351 vcpu->arch.mmu = &vcpu->arch.guest_mmu; 352 kvm_init_shadow_ept_mmu(vcpu, 353 to_vmx(vcpu)->nested.msrs.ept_caps & 354 VMX_EPT_EXECUTE_ONLY_BIT, 355 nested_ept_ad_enabled(vcpu), 356 nested_ept_get_cr3(vcpu)); 357 vcpu->arch.mmu->set_cr3 = vmx_set_cr3; 358 vcpu->arch.mmu->get_cr3 = nested_ept_get_cr3; 359 vcpu->arch.mmu->inject_page_fault = nested_ept_inject_page_fault; 360 vcpu->arch.mmu->get_pdptr = kvm_pdptr_read; 361 362 vcpu->arch.walk_mmu = &vcpu->arch.nested_mmu; 363 } 364 365 static void nested_ept_uninit_mmu_context(struct kvm_vcpu *vcpu) 366 { 367 vcpu->arch.mmu = &vcpu->arch.root_mmu; 368 vcpu->arch.walk_mmu = &vcpu->arch.root_mmu; 369 } 370 371 static bool nested_vmx_is_page_fault_vmexit(struct vmcs12 *vmcs12, 372 u16 error_code) 373 { 374 bool inequality, bit; 375 376 bit = (vmcs12->exception_bitmap & (1u << PF_VECTOR)) != 0; 377 inequality = 378 (error_code & vmcs12->page_fault_error_code_mask) != 379 vmcs12->page_fault_error_code_match; 380 return inequality ^ bit; 381 } 382 383 384 /* 385 * KVM wants to inject page-faults which it got to the guest. This function 386 * checks whether in a nested guest, we need to inject them to L1 or L2. 387 */ 388 static int nested_vmx_check_exception(struct kvm_vcpu *vcpu, unsigned long *exit_qual) 389 { 390 struct vmcs12 *vmcs12 = get_vmcs12(vcpu); 391 unsigned int nr = vcpu->arch.exception.nr; 392 bool has_payload = vcpu->arch.exception.has_payload; 393 unsigned long payload = vcpu->arch.exception.payload; 394 395 if (nr == PF_VECTOR) { 396 if (vcpu->arch.exception.nested_apf) { 397 *exit_qual = vcpu->arch.apf.nested_apf_token; 398 return 1; 399 } 400 if (nested_vmx_is_page_fault_vmexit(vmcs12, 401 vcpu->arch.exception.error_code)) { 402 *exit_qual = has_payload ? payload : vcpu->arch.cr2; 403 return 1; 404 } 405 } else if (vmcs12->exception_bitmap & (1u << nr)) { 406 if (nr == DB_VECTOR) { 407 if (!has_payload) { 408 payload = vcpu->arch.dr6; 409 payload &= ~(DR6_FIXED_1 | DR6_BT); 410 payload ^= DR6_RTM; 411 } 412 *exit_qual = payload; 413 } else 414 *exit_qual = 0; 415 return 1; 416 } 417 418 return 0; 419 } 420 421 422 static void vmx_inject_page_fault_nested(struct kvm_vcpu *vcpu, 423 struct x86_exception *fault) 424 { 425 struct vmcs12 *vmcs12 = get_vmcs12(vcpu); 426 427 WARN_ON(!is_guest_mode(vcpu)); 428 429 if (nested_vmx_is_page_fault_vmexit(vmcs12, fault->error_code) && 430 !to_vmx(vcpu)->nested.nested_run_pending) { 431 vmcs12->vm_exit_intr_error_code = fault->error_code; 432 nested_vmx_vmexit(vcpu, EXIT_REASON_EXCEPTION_NMI, 433 PF_VECTOR | INTR_TYPE_HARD_EXCEPTION | 434 INTR_INFO_DELIVER_CODE_MASK | INTR_INFO_VALID_MASK, 435 fault->address); 436 } else { 437 kvm_inject_page_fault(vcpu, fault); 438 } 439 } 440 441 static bool page_address_valid(struct kvm_vcpu *vcpu, gpa_t gpa) 442 { 443 return PAGE_ALIGNED(gpa) && !(gpa >> cpuid_maxphyaddr(vcpu)); 444 } 445 446 static int nested_vmx_check_io_bitmap_controls(struct kvm_vcpu *vcpu, 447 struct vmcs12 *vmcs12) 448 { 449 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS)) 450 return 0; 451 452 if (CC(!page_address_valid(vcpu, vmcs12->io_bitmap_a)) || 453 CC(!page_address_valid(vcpu, vmcs12->io_bitmap_b))) 454 return -EINVAL; 455 456 return 0; 457 } 458 459 static int nested_vmx_check_msr_bitmap_controls(struct kvm_vcpu *vcpu, 460 struct vmcs12 *vmcs12) 461 { 462 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS)) 463 return 0; 464 465 if (CC(!page_address_valid(vcpu, vmcs12->msr_bitmap))) 466 return -EINVAL; 467 468 return 0; 469 } 470 471 static int nested_vmx_check_tpr_shadow_controls(struct kvm_vcpu *vcpu, 472 struct vmcs12 *vmcs12) 473 { 474 if (!nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW)) 475 return 0; 476 477 if (CC(!page_address_valid(vcpu, vmcs12->virtual_apic_page_addr))) 478 return -EINVAL; 479 480 return 0; 481 } 482 483 /* 484 * Check if MSR is intercepted for L01 MSR bitmap. 485 */ 486 static bool msr_write_intercepted_l01(struct kvm_vcpu *vcpu, u32 msr) 487 { 488 unsigned long *msr_bitmap; 489 int f = sizeof(unsigned long); 490 491 if (!cpu_has_vmx_msr_bitmap()) 492 return true; 493 494 msr_bitmap = to_vmx(vcpu)->vmcs01.msr_bitmap; 495 496 if (msr <= 0x1fff) { 497 return !!test_bit(msr, msr_bitmap + 0x800 / f); 498 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) { 499 msr &= 0x1fff; 500 return !!test_bit(msr, msr_bitmap + 0xc00 / f); 501 } 502 503 return true; 504 } 505 506 /* 507 * If a msr is allowed by L0, we should check whether it is allowed by L1. 508 * The corresponding bit will be cleared unless both of L0 and L1 allow it. 509 */ 510 static void nested_vmx_disable_intercept_for_msr(unsigned long *msr_bitmap_l1, 511 unsigned long *msr_bitmap_nested, 512 u32 msr, int type) 513 { 514 int f = sizeof(unsigned long); 515 516 /* 517 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals 518 * have the write-low and read-high bitmap offsets the wrong way round. 519 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff. 520 */ 521 if (msr <= 0x1fff) { 522 if (type & MSR_TYPE_R && 523 !test_bit(msr, msr_bitmap_l1 + 0x000 / f)) 524 /* read-low */ 525 __clear_bit(msr, msr_bitmap_nested + 0x000 / f); 526 527 if (type & MSR_TYPE_W && 528 !test_bit(msr, msr_bitmap_l1 + 0x800 / f)) 529 /* write-low */ 530 __clear_bit(msr, msr_bitmap_nested + 0x800 / f); 531 532 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) { 533 msr &= 0x1fff; 534 if (type & MSR_TYPE_R && 535 !test_bit(msr, msr_bitmap_l1 + 0x400 / f)) 536 /* read-high */ 537 __clear_bit(msr, msr_bitmap_nested + 0x400 / f); 538 539 if (type & MSR_TYPE_W && 540 !test_bit(msr, msr_bitmap_l1 + 0xc00 / f)) 541 /* write-high */ 542 __clear_bit(msr, msr_bitmap_nested + 0xc00 / f); 543 544 } 545 } 546 547 static inline void enable_x2apic_msr_intercepts(unsigned long *msr_bitmap) { 548 int msr; 549 550 for (msr = 0x800; msr <= 0x8ff; msr += BITS_PER_LONG) { 551 unsigned word = msr / BITS_PER_LONG; 552 553 msr_bitmap[word] = ~0; 554 msr_bitmap[word + (0x800 / sizeof(long))] = ~0; 555 } 556 } 557 558 /* 559 * Merge L0's and L1's MSR bitmap, return false to indicate that 560 * we do not use the hardware. 561 */ 562 static inline bool nested_vmx_prepare_msr_bitmap(struct kvm_vcpu *vcpu, 563 struct vmcs12 *vmcs12) 564 { 565 int msr; 566 unsigned long *msr_bitmap_l1; 567 unsigned long *msr_bitmap_l0 = to_vmx(vcpu)->nested.vmcs02.msr_bitmap; 568 struct kvm_host_map *map = &to_vmx(vcpu)->nested.msr_bitmap_map; 569 570 /* Nothing to do if the MSR bitmap is not in use. */ 571 if (!cpu_has_vmx_msr_bitmap() || 572 !nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS)) 573 return false; 574 575 if (kvm_vcpu_map(vcpu, gpa_to_gfn(vmcs12->msr_bitmap), map)) 576 return false; 577 578 msr_bitmap_l1 = (unsigned long *)map->hva; 579 580 /* 581 * To keep the control flow simple, pay eight 8-byte writes (sixteen 582 * 4-byte writes on 32-bit systems) up front to enable intercepts for 583 * the x2APIC MSR range and selectively disable them below. 584 */ 585 enable_x2apic_msr_intercepts(msr_bitmap_l0); 586 587 if (nested_cpu_has_virt_x2apic_mode(vmcs12)) { 588 if (nested_cpu_has_apic_reg_virt(vmcs12)) { 589 /* 590 * L0 need not intercept reads for MSRs between 0x800 591 * and 0x8ff, it just lets the processor take the value 592 * from the virtual-APIC page; take those 256 bits 593 * directly from the L1 bitmap. 594 */ 595 for (msr = 0x800; msr <= 0x8ff; msr += BITS_PER_LONG) { 596 unsigned word = msr / BITS_PER_LONG; 597 598 msr_bitmap_l0[word] = msr_bitmap_l1[word]; 599 } 600 } 601 602 nested_vmx_disable_intercept_for_msr( 603 msr_bitmap_l1, msr_bitmap_l0, 604 X2APIC_MSR(APIC_TASKPRI), 605 MSR_TYPE_R | MSR_TYPE_W); 606 607 if (nested_cpu_has_vid(vmcs12)) { 608 nested_vmx_disable_intercept_for_msr( 609 msr_bitmap_l1, msr_bitmap_l0, 610 X2APIC_MSR(APIC_EOI), 611 MSR_TYPE_W); 612 nested_vmx_disable_intercept_for_msr( 613 msr_bitmap_l1, msr_bitmap_l0, 614 X2APIC_MSR(APIC_SELF_IPI), 615 MSR_TYPE_W); 616 } 617 } 618 619 /* KVM unconditionally exposes the FS/GS base MSRs to L1. */ 620 nested_vmx_disable_intercept_for_msr(msr_bitmap_l1, msr_bitmap_l0, 621 MSR_FS_BASE, MSR_TYPE_RW); 622 623 nested_vmx_disable_intercept_for_msr(msr_bitmap_l1, msr_bitmap_l0, 624 MSR_GS_BASE, MSR_TYPE_RW); 625 626 nested_vmx_disable_intercept_for_msr(msr_bitmap_l1, msr_bitmap_l0, 627 MSR_KERNEL_GS_BASE, MSR_TYPE_RW); 628 629 /* 630 * Checking the L0->L1 bitmap is trying to verify two things: 631 * 632 * 1. L0 gave a permission to L1 to actually passthrough the MSR. This 633 * ensures that we do not accidentally generate an L02 MSR bitmap 634 * from the L12 MSR bitmap that is too permissive. 635 * 2. That L1 or L2s have actually used the MSR. This avoids 636 * unnecessarily merging of the bitmap if the MSR is unused. This 637 * works properly because we only update the L01 MSR bitmap lazily. 638 * So even if L0 should pass L1 these MSRs, the L01 bitmap is only 639 * updated to reflect this when L1 (or its L2s) actually write to 640 * the MSR. 641 */ 642 if (!msr_write_intercepted_l01(vcpu, MSR_IA32_SPEC_CTRL)) 643 nested_vmx_disable_intercept_for_msr( 644 msr_bitmap_l1, msr_bitmap_l0, 645 MSR_IA32_SPEC_CTRL, 646 MSR_TYPE_R | MSR_TYPE_W); 647 648 if (!msr_write_intercepted_l01(vcpu, MSR_IA32_PRED_CMD)) 649 nested_vmx_disable_intercept_for_msr( 650 msr_bitmap_l1, msr_bitmap_l0, 651 MSR_IA32_PRED_CMD, 652 MSR_TYPE_W); 653 654 kvm_vcpu_unmap(vcpu, &to_vmx(vcpu)->nested.msr_bitmap_map, false); 655 656 return true; 657 } 658 659 static void nested_cache_shadow_vmcs12(struct kvm_vcpu *vcpu, 660 struct vmcs12 *vmcs12) 661 { 662 struct kvm_host_map map; 663 struct vmcs12 *shadow; 664 665 if (!nested_cpu_has_shadow_vmcs(vmcs12) || 666 vmcs12->vmcs_link_pointer == -1ull) 667 return; 668 669 shadow = get_shadow_vmcs12(vcpu); 670 671 if (kvm_vcpu_map(vcpu, gpa_to_gfn(vmcs12->vmcs_link_pointer), &map)) 672 return; 673 674 memcpy(shadow, map.hva, VMCS12_SIZE); 675 kvm_vcpu_unmap(vcpu, &map, false); 676 } 677 678 static void nested_flush_cached_shadow_vmcs12(struct kvm_vcpu *vcpu, 679 struct vmcs12 *vmcs12) 680 { 681 struct vcpu_vmx *vmx = to_vmx(vcpu); 682 683 if (!nested_cpu_has_shadow_vmcs(vmcs12) || 684 vmcs12->vmcs_link_pointer == -1ull) 685 return; 686 687 kvm_write_guest(vmx->vcpu.kvm, vmcs12->vmcs_link_pointer, 688 get_shadow_vmcs12(vcpu), VMCS12_SIZE); 689 } 690 691 /* 692 * In nested virtualization, check if L1 has set 693 * VM_EXIT_ACK_INTR_ON_EXIT 694 */ 695 static bool nested_exit_intr_ack_set(struct kvm_vcpu *vcpu) 696 { 697 return get_vmcs12(vcpu)->vm_exit_controls & 698 VM_EXIT_ACK_INTR_ON_EXIT; 699 } 700 701 static bool nested_exit_on_nmi(struct kvm_vcpu *vcpu) 702 { 703 return nested_cpu_has_nmi_exiting(get_vmcs12(vcpu)); 704 } 705 706 static int nested_vmx_check_apic_access_controls(struct kvm_vcpu *vcpu, 707 struct vmcs12 *vmcs12) 708 { 709 if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) && 710 CC(!page_address_valid(vcpu, vmcs12->apic_access_addr))) 711 return -EINVAL; 712 else 713 return 0; 714 } 715 716 static int nested_vmx_check_apicv_controls(struct kvm_vcpu *vcpu, 717 struct vmcs12 *vmcs12) 718 { 719 if (!nested_cpu_has_virt_x2apic_mode(vmcs12) && 720 !nested_cpu_has_apic_reg_virt(vmcs12) && 721 !nested_cpu_has_vid(vmcs12) && 722 !nested_cpu_has_posted_intr(vmcs12)) 723 return 0; 724 725 /* 726 * If virtualize x2apic mode is enabled, 727 * virtualize apic access must be disabled. 728 */ 729 if (CC(nested_cpu_has_virt_x2apic_mode(vmcs12) && 730 nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))) 731 return -EINVAL; 732 733 /* 734 * If virtual interrupt delivery is enabled, 735 * we must exit on external interrupts. 736 */ 737 if (CC(nested_cpu_has_vid(vmcs12) && !nested_exit_on_intr(vcpu))) 738 return -EINVAL; 739 740 /* 741 * bits 15:8 should be zero in posted_intr_nv, 742 * the descriptor address has been already checked 743 * in nested_get_vmcs12_pages. 744 * 745 * bits 5:0 of posted_intr_desc_addr should be zero. 746 */ 747 if (nested_cpu_has_posted_intr(vmcs12) && 748 (CC(!nested_cpu_has_vid(vmcs12)) || 749 CC(!nested_exit_intr_ack_set(vcpu)) || 750 CC((vmcs12->posted_intr_nv & 0xff00)) || 751 CC((vmcs12->posted_intr_desc_addr & 0x3f)) || 752 CC((vmcs12->posted_intr_desc_addr >> cpuid_maxphyaddr(vcpu))))) 753 return -EINVAL; 754 755 /* tpr shadow is needed by all apicv features. */ 756 if (CC(!nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))) 757 return -EINVAL; 758 759 return 0; 760 } 761 762 static int nested_vmx_check_msr_switch(struct kvm_vcpu *vcpu, 763 u32 count, u64 addr) 764 { 765 int maxphyaddr; 766 767 if (count == 0) 768 return 0; 769 maxphyaddr = cpuid_maxphyaddr(vcpu); 770 if (!IS_ALIGNED(addr, 16) || addr >> maxphyaddr || 771 (addr + count * sizeof(struct vmx_msr_entry) - 1) >> maxphyaddr) 772 return -EINVAL; 773 774 return 0; 775 } 776 777 static int nested_vmx_check_exit_msr_switch_controls(struct kvm_vcpu *vcpu, 778 struct vmcs12 *vmcs12) 779 { 780 if (CC(nested_vmx_check_msr_switch(vcpu, 781 vmcs12->vm_exit_msr_load_count, 782 vmcs12->vm_exit_msr_load_addr)) || 783 CC(nested_vmx_check_msr_switch(vcpu, 784 vmcs12->vm_exit_msr_store_count, 785 vmcs12->vm_exit_msr_store_addr))) 786 return -EINVAL; 787 788 return 0; 789 } 790 791 static int nested_vmx_check_entry_msr_switch_controls(struct kvm_vcpu *vcpu, 792 struct vmcs12 *vmcs12) 793 { 794 if (CC(nested_vmx_check_msr_switch(vcpu, 795 vmcs12->vm_entry_msr_load_count, 796 vmcs12->vm_entry_msr_load_addr))) 797 return -EINVAL; 798 799 return 0; 800 } 801 802 static int nested_vmx_check_pml_controls(struct kvm_vcpu *vcpu, 803 struct vmcs12 *vmcs12) 804 { 805 if (!nested_cpu_has_pml(vmcs12)) 806 return 0; 807 808 if (CC(!nested_cpu_has_ept(vmcs12)) || 809 CC(!page_address_valid(vcpu, vmcs12->pml_address))) 810 return -EINVAL; 811 812 return 0; 813 } 814 815 static int nested_vmx_check_unrestricted_guest_controls(struct kvm_vcpu *vcpu, 816 struct vmcs12 *vmcs12) 817 { 818 if (CC(nested_cpu_has2(vmcs12, SECONDARY_EXEC_UNRESTRICTED_GUEST) && 819 !nested_cpu_has_ept(vmcs12))) 820 return -EINVAL; 821 return 0; 822 } 823 824 static int nested_vmx_check_mode_based_ept_exec_controls(struct kvm_vcpu *vcpu, 825 struct vmcs12 *vmcs12) 826 { 827 if (CC(nested_cpu_has2(vmcs12, SECONDARY_EXEC_MODE_BASED_EPT_EXEC) && 828 !nested_cpu_has_ept(vmcs12))) 829 return -EINVAL; 830 return 0; 831 } 832 833 static int nested_vmx_check_shadow_vmcs_controls(struct kvm_vcpu *vcpu, 834 struct vmcs12 *vmcs12) 835 { 836 if (!nested_cpu_has_shadow_vmcs(vmcs12)) 837 return 0; 838 839 if (CC(!page_address_valid(vcpu, vmcs12->vmread_bitmap)) || 840 CC(!page_address_valid(vcpu, vmcs12->vmwrite_bitmap))) 841 return -EINVAL; 842 843 return 0; 844 } 845 846 static int nested_vmx_msr_check_common(struct kvm_vcpu *vcpu, 847 struct vmx_msr_entry *e) 848 { 849 /* x2APIC MSR accesses are not allowed */ 850 if (CC(vcpu->arch.apic_base & X2APIC_ENABLE && e->index >> 8 == 0x8)) 851 return -EINVAL; 852 if (CC(e->index == MSR_IA32_UCODE_WRITE) || /* SDM Table 35-2 */ 853 CC(e->index == MSR_IA32_UCODE_REV)) 854 return -EINVAL; 855 if (CC(e->reserved != 0)) 856 return -EINVAL; 857 return 0; 858 } 859 860 static int nested_vmx_load_msr_check(struct kvm_vcpu *vcpu, 861 struct vmx_msr_entry *e) 862 { 863 if (CC(e->index == MSR_FS_BASE) || 864 CC(e->index == MSR_GS_BASE) || 865 CC(e->index == MSR_IA32_SMM_MONITOR_CTL) || /* SMM is not supported */ 866 nested_vmx_msr_check_common(vcpu, e)) 867 return -EINVAL; 868 return 0; 869 } 870 871 static int nested_vmx_store_msr_check(struct kvm_vcpu *vcpu, 872 struct vmx_msr_entry *e) 873 { 874 if (CC(e->index == MSR_IA32_SMBASE) || /* SMM is not supported */ 875 nested_vmx_msr_check_common(vcpu, e)) 876 return -EINVAL; 877 return 0; 878 } 879 880 static u32 nested_vmx_max_atomic_switch_msrs(struct kvm_vcpu *vcpu) 881 { 882 struct vcpu_vmx *vmx = to_vmx(vcpu); 883 u64 vmx_misc = vmx_control_msr(vmx->nested.msrs.misc_low, 884 vmx->nested.msrs.misc_high); 885 886 return (vmx_misc_max_msr(vmx_misc) + 1) * VMX_MISC_MSR_LIST_MULTIPLIER; 887 } 888 889 /* 890 * Load guest's/host's msr at nested entry/exit. 891 * return 0 for success, entry index for failure. 892 * 893 * One of the failure modes for MSR load/store is when a list exceeds the 894 * virtual hardware's capacity. To maintain compatibility with hardware inasmuch 895 * as possible, process all valid entries before failing rather than precheck 896 * for a capacity violation. 897 */ 898 static u32 nested_vmx_load_msr(struct kvm_vcpu *vcpu, u64 gpa, u32 count) 899 { 900 u32 i; 901 struct vmx_msr_entry e; 902 u32 max_msr_list_size = nested_vmx_max_atomic_switch_msrs(vcpu); 903 904 for (i = 0; i < count; i++) { 905 if (unlikely(i >= max_msr_list_size)) 906 goto fail; 907 908 if (kvm_vcpu_read_guest(vcpu, gpa + i * sizeof(e), 909 &e, sizeof(e))) { 910 pr_debug_ratelimited( 911 "%s cannot read MSR entry (%u, 0x%08llx)\n", 912 __func__, i, gpa + i * sizeof(e)); 913 goto fail; 914 } 915 if (nested_vmx_load_msr_check(vcpu, &e)) { 916 pr_debug_ratelimited( 917 "%s check failed (%u, 0x%x, 0x%x)\n", 918 __func__, i, e.index, e.reserved); 919 goto fail; 920 } 921 if (kvm_set_msr(vcpu, e.index, e.value)) { 922 pr_debug_ratelimited( 923 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n", 924 __func__, i, e.index, e.value); 925 goto fail; 926 } 927 } 928 return 0; 929 fail: 930 return i + 1; 931 } 932 933 static bool nested_vmx_get_vmexit_msr_value(struct kvm_vcpu *vcpu, 934 u32 msr_index, 935 u64 *data) 936 { 937 struct vcpu_vmx *vmx = to_vmx(vcpu); 938 939 /* 940 * If the L0 hypervisor stored a more accurate value for the TSC that 941 * does not include the time taken for emulation of the L2->L1 942 * VM-exit in L0, use the more accurate value. 943 */ 944 if (msr_index == MSR_IA32_TSC) { 945 int index = vmx_find_msr_index(&vmx->msr_autostore.guest, 946 MSR_IA32_TSC); 947 948 if (index >= 0) { 949 u64 val = vmx->msr_autostore.guest.val[index].value; 950 951 *data = kvm_read_l1_tsc(vcpu, val); 952 return true; 953 } 954 } 955 956 if (kvm_get_msr(vcpu, msr_index, data)) { 957 pr_debug_ratelimited("%s cannot read MSR (0x%x)\n", __func__, 958 msr_index); 959 return false; 960 } 961 return true; 962 } 963 964 static bool read_and_check_msr_entry(struct kvm_vcpu *vcpu, u64 gpa, int i, 965 struct vmx_msr_entry *e) 966 { 967 if (kvm_vcpu_read_guest(vcpu, 968 gpa + i * sizeof(*e), 969 e, 2 * sizeof(u32))) { 970 pr_debug_ratelimited( 971 "%s cannot read MSR entry (%u, 0x%08llx)\n", 972 __func__, i, gpa + i * sizeof(*e)); 973 return false; 974 } 975 if (nested_vmx_store_msr_check(vcpu, e)) { 976 pr_debug_ratelimited( 977 "%s check failed (%u, 0x%x, 0x%x)\n", 978 __func__, i, e->index, e->reserved); 979 return false; 980 } 981 return true; 982 } 983 984 static int nested_vmx_store_msr(struct kvm_vcpu *vcpu, u64 gpa, u32 count) 985 { 986 u64 data; 987 u32 i; 988 struct vmx_msr_entry e; 989 u32 max_msr_list_size = nested_vmx_max_atomic_switch_msrs(vcpu); 990 991 for (i = 0; i < count; i++) { 992 if (unlikely(i >= max_msr_list_size)) 993 return -EINVAL; 994 995 if (!read_and_check_msr_entry(vcpu, gpa, i, &e)) 996 return -EINVAL; 997 998 if (!nested_vmx_get_vmexit_msr_value(vcpu, e.index, &data)) 999 return -EINVAL; 1000 1001 if (kvm_vcpu_write_guest(vcpu, 1002 gpa + i * sizeof(e) + 1003 offsetof(struct vmx_msr_entry, value), 1004 &data, sizeof(data))) { 1005 pr_debug_ratelimited( 1006 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n", 1007 __func__, i, e.index, data); 1008 return -EINVAL; 1009 } 1010 } 1011 return 0; 1012 } 1013 1014 static bool nested_msr_store_list_has_msr(struct kvm_vcpu *vcpu, u32 msr_index) 1015 { 1016 struct vmcs12 *vmcs12 = get_vmcs12(vcpu); 1017 u32 count = vmcs12->vm_exit_msr_store_count; 1018 u64 gpa = vmcs12->vm_exit_msr_store_addr; 1019 struct vmx_msr_entry e; 1020 u32 i; 1021 1022 for (i = 0; i < count; i++) { 1023 if (!read_and_check_msr_entry(vcpu, gpa, i, &e)) 1024 return false; 1025 1026 if (e.index == msr_index) 1027 return true; 1028 } 1029 return false; 1030 } 1031 1032 static void prepare_vmx_msr_autostore_list(struct kvm_vcpu *vcpu, 1033 u32 msr_index) 1034 { 1035 struct vcpu_vmx *vmx = to_vmx(vcpu); 1036 struct vmx_msrs *autostore = &vmx->msr_autostore.guest; 1037 bool in_vmcs12_store_list; 1038 int msr_autostore_index; 1039 bool in_autostore_list; 1040 int last; 1041 1042 msr_autostore_index = vmx_find_msr_index(autostore, msr_index); 1043 in_autostore_list = msr_autostore_index >= 0; 1044 in_vmcs12_store_list = nested_msr_store_list_has_msr(vcpu, msr_index); 1045 1046 if (in_vmcs12_store_list && !in_autostore_list) { 1047 if (autostore->nr == NR_LOADSTORE_MSRS) { 1048 /* 1049 * Emulated VMEntry does not fail here. Instead a less 1050 * accurate value will be returned by 1051 * nested_vmx_get_vmexit_msr_value() using kvm_get_msr() 1052 * instead of reading the value from the vmcs02 VMExit 1053 * MSR-store area. 1054 */ 1055 pr_warn_ratelimited( 1056 "Not enough msr entries in msr_autostore. Can't add msr %x\n", 1057 msr_index); 1058 return; 1059 } 1060 last = autostore->nr++; 1061 autostore->val[last].index = msr_index; 1062 } else if (!in_vmcs12_store_list && in_autostore_list) { 1063 last = --autostore->nr; 1064 autostore->val[msr_autostore_index] = autostore->val[last]; 1065 } 1066 } 1067 1068 static bool nested_cr3_valid(struct kvm_vcpu *vcpu, unsigned long val) 1069 { 1070 unsigned long invalid_mask; 1071 1072 invalid_mask = (~0ULL) << cpuid_maxphyaddr(vcpu); 1073 return (val & invalid_mask) == 0; 1074 } 1075 1076 /* 1077 * Load guest's/host's cr3 at nested entry/exit. nested_ept is true if we are 1078 * emulating VM entry into a guest with EPT enabled. 1079 * Returns 0 on success, 1 on failure. Invalid state exit qualification code 1080 * is assigned to entry_failure_code on failure. 1081 */ 1082 static int nested_vmx_load_cr3(struct kvm_vcpu *vcpu, unsigned long cr3, bool nested_ept, 1083 u32 *entry_failure_code) 1084 { 1085 if (cr3 != kvm_read_cr3(vcpu) || (!nested_ept && pdptrs_changed(vcpu))) { 1086 if (CC(!nested_cr3_valid(vcpu, cr3))) { 1087 *entry_failure_code = ENTRY_FAIL_DEFAULT; 1088 return -EINVAL; 1089 } 1090 1091 /* 1092 * If PAE paging and EPT are both on, CR3 is not used by the CPU and 1093 * must not be dereferenced. 1094 */ 1095 if (is_pae_paging(vcpu) && !nested_ept) { 1096 if (CC(!load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))) { 1097 *entry_failure_code = ENTRY_FAIL_PDPTE; 1098 return -EINVAL; 1099 } 1100 } 1101 } 1102 1103 if (!nested_ept) 1104 kvm_mmu_new_cr3(vcpu, cr3, false); 1105 1106 vcpu->arch.cr3 = cr3; 1107 kvm_register_mark_available(vcpu, VCPU_EXREG_CR3); 1108 1109 kvm_init_mmu(vcpu, false); 1110 1111 return 0; 1112 } 1113 1114 /* 1115 * Returns if KVM is able to config CPU to tag TLB entries 1116 * populated by L2 differently than TLB entries populated 1117 * by L1. 1118 * 1119 * If L0 uses EPT, L1 and L2 run with different EPTP because 1120 * guest_mode is part of kvm_mmu_page_role. Thus, TLB entries 1121 * are tagged with different EPTP. 1122 * 1123 * If L1 uses VPID and we allocated a vpid02, TLB entries are tagged 1124 * with different VPID (L1 entries are tagged with vmx->vpid 1125 * while L2 entries are tagged with vmx->nested.vpid02). 1126 */ 1127 static bool nested_has_guest_tlb_tag(struct kvm_vcpu *vcpu) 1128 { 1129 struct vmcs12 *vmcs12 = get_vmcs12(vcpu); 1130 1131 return enable_ept || 1132 (nested_cpu_has_vpid(vmcs12) && to_vmx(vcpu)->nested.vpid02); 1133 } 1134 1135 static u16 nested_get_vpid02(struct kvm_vcpu *vcpu) 1136 { 1137 struct vcpu_vmx *vmx = to_vmx(vcpu); 1138 1139 return vmx->nested.vpid02 ? vmx->nested.vpid02 : vmx->vpid; 1140 } 1141 1142 static bool is_bitwise_subset(u64 superset, u64 subset, u64 mask) 1143 { 1144 superset &= mask; 1145 subset &= mask; 1146 1147 return (superset | subset) == superset; 1148 } 1149 1150 static int vmx_restore_vmx_basic(struct vcpu_vmx *vmx, u64 data) 1151 { 1152 const u64 feature_and_reserved = 1153 /* feature (except bit 48; see below) */ 1154 BIT_ULL(49) | BIT_ULL(54) | BIT_ULL(55) | 1155 /* reserved */ 1156 BIT_ULL(31) | GENMASK_ULL(47, 45) | GENMASK_ULL(63, 56); 1157 u64 vmx_basic = vmx->nested.msrs.basic; 1158 1159 if (!is_bitwise_subset(vmx_basic, data, feature_and_reserved)) 1160 return -EINVAL; 1161 1162 /* 1163 * KVM does not emulate a version of VMX that constrains physical 1164 * addresses of VMX structures (e.g. VMCS) to 32-bits. 1165 */ 1166 if (data & BIT_ULL(48)) 1167 return -EINVAL; 1168 1169 if (vmx_basic_vmcs_revision_id(vmx_basic) != 1170 vmx_basic_vmcs_revision_id(data)) 1171 return -EINVAL; 1172 1173 if (vmx_basic_vmcs_size(vmx_basic) > vmx_basic_vmcs_size(data)) 1174 return -EINVAL; 1175 1176 vmx->nested.msrs.basic = data; 1177 return 0; 1178 } 1179 1180 static int 1181 vmx_restore_control_msr(struct vcpu_vmx *vmx, u32 msr_index, u64 data) 1182 { 1183 u64 supported; 1184 u32 *lowp, *highp; 1185 1186 switch (msr_index) { 1187 case MSR_IA32_VMX_TRUE_PINBASED_CTLS: 1188 lowp = &vmx->nested.msrs.pinbased_ctls_low; 1189 highp = &vmx->nested.msrs.pinbased_ctls_high; 1190 break; 1191 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS: 1192 lowp = &vmx->nested.msrs.procbased_ctls_low; 1193 highp = &vmx->nested.msrs.procbased_ctls_high; 1194 break; 1195 case MSR_IA32_VMX_TRUE_EXIT_CTLS: 1196 lowp = &vmx->nested.msrs.exit_ctls_low; 1197 highp = &vmx->nested.msrs.exit_ctls_high; 1198 break; 1199 case MSR_IA32_VMX_TRUE_ENTRY_CTLS: 1200 lowp = &vmx->nested.msrs.entry_ctls_low; 1201 highp = &vmx->nested.msrs.entry_ctls_high; 1202 break; 1203 case MSR_IA32_VMX_PROCBASED_CTLS2: 1204 lowp = &vmx->nested.msrs.secondary_ctls_low; 1205 highp = &vmx->nested.msrs.secondary_ctls_high; 1206 break; 1207 default: 1208 BUG(); 1209 } 1210 1211 supported = vmx_control_msr(*lowp, *highp); 1212 1213 /* Check must-be-1 bits are still 1. */ 1214 if (!is_bitwise_subset(data, supported, GENMASK_ULL(31, 0))) 1215 return -EINVAL; 1216 1217 /* Check must-be-0 bits are still 0. */ 1218 if (!is_bitwise_subset(supported, data, GENMASK_ULL(63, 32))) 1219 return -EINVAL; 1220 1221 *lowp = data; 1222 *highp = data >> 32; 1223 return 0; 1224 } 1225 1226 static int vmx_restore_vmx_misc(struct vcpu_vmx *vmx, u64 data) 1227 { 1228 const u64 feature_and_reserved_bits = 1229 /* feature */ 1230 BIT_ULL(5) | GENMASK_ULL(8, 6) | BIT_ULL(14) | BIT_ULL(15) | 1231 BIT_ULL(28) | BIT_ULL(29) | BIT_ULL(30) | 1232 /* reserved */ 1233 GENMASK_ULL(13, 9) | BIT_ULL(31); 1234 u64 vmx_misc; 1235 1236 vmx_misc = vmx_control_msr(vmx->nested.msrs.misc_low, 1237 vmx->nested.msrs.misc_high); 1238 1239 if (!is_bitwise_subset(vmx_misc, data, feature_and_reserved_bits)) 1240 return -EINVAL; 1241 1242 if ((vmx->nested.msrs.pinbased_ctls_high & 1243 PIN_BASED_VMX_PREEMPTION_TIMER) && 1244 vmx_misc_preemption_timer_rate(data) != 1245 vmx_misc_preemption_timer_rate(vmx_misc)) 1246 return -EINVAL; 1247 1248 if (vmx_misc_cr3_count(data) > vmx_misc_cr3_count(vmx_misc)) 1249 return -EINVAL; 1250 1251 if (vmx_misc_max_msr(data) > vmx_misc_max_msr(vmx_misc)) 1252 return -EINVAL; 1253 1254 if (vmx_misc_mseg_revid(data) != vmx_misc_mseg_revid(vmx_misc)) 1255 return -EINVAL; 1256 1257 vmx->nested.msrs.misc_low = data; 1258 vmx->nested.msrs.misc_high = data >> 32; 1259 1260 return 0; 1261 } 1262 1263 static int vmx_restore_vmx_ept_vpid_cap(struct vcpu_vmx *vmx, u64 data) 1264 { 1265 u64 vmx_ept_vpid_cap; 1266 1267 vmx_ept_vpid_cap = vmx_control_msr(vmx->nested.msrs.ept_caps, 1268 vmx->nested.msrs.vpid_caps); 1269 1270 /* Every bit is either reserved or a feature bit. */ 1271 if (!is_bitwise_subset(vmx_ept_vpid_cap, data, -1ULL)) 1272 return -EINVAL; 1273 1274 vmx->nested.msrs.ept_caps = data; 1275 vmx->nested.msrs.vpid_caps = data >> 32; 1276 return 0; 1277 } 1278 1279 static int vmx_restore_fixed0_msr(struct vcpu_vmx *vmx, u32 msr_index, u64 data) 1280 { 1281 u64 *msr; 1282 1283 switch (msr_index) { 1284 case MSR_IA32_VMX_CR0_FIXED0: 1285 msr = &vmx->nested.msrs.cr0_fixed0; 1286 break; 1287 case MSR_IA32_VMX_CR4_FIXED0: 1288 msr = &vmx->nested.msrs.cr4_fixed0; 1289 break; 1290 default: 1291 BUG(); 1292 } 1293 1294 /* 1295 * 1 bits (which indicates bits which "must-be-1" during VMX operation) 1296 * must be 1 in the restored value. 1297 */ 1298 if (!is_bitwise_subset(data, *msr, -1ULL)) 1299 return -EINVAL; 1300 1301 *msr = data; 1302 return 0; 1303 } 1304 1305 /* 1306 * Called when userspace is restoring VMX MSRs. 1307 * 1308 * Returns 0 on success, non-0 otherwise. 1309 */ 1310 int vmx_set_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data) 1311 { 1312 struct vcpu_vmx *vmx = to_vmx(vcpu); 1313 1314 /* 1315 * Don't allow changes to the VMX capability MSRs while the vCPU 1316 * is in VMX operation. 1317 */ 1318 if (vmx->nested.vmxon) 1319 return -EBUSY; 1320 1321 switch (msr_index) { 1322 case MSR_IA32_VMX_BASIC: 1323 return vmx_restore_vmx_basic(vmx, data); 1324 case MSR_IA32_VMX_PINBASED_CTLS: 1325 case MSR_IA32_VMX_PROCBASED_CTLS: 1326 case MSR_IA32_VMX_EXIT_CTLS: 1327 case MSR_IA32_VMX_ENTRY_CTLS: 1328 /* 1329 * The "non-true" VMX capability MSRs are generated from the 1330 * "true" MSRs, so we do not support restoring them directly. 1331 * 1332 * If userspace wants to emulate VMX_BASIC[55]=0, userspace 1333 * should restore the "true" MSRs with the must-be-1 bits 1334 * set according to the SDM Vol 3. A.2 "RESERVED CONTROLS AND 1335 * DEFAULT SETTINGS". 1336 */ 1337 return -EINVAL; 1338 case MSR_IA32_VMX_TRUE_PINBASED_CTLS: 1339 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS: 1340 case MSR_IA32_VMX_TRUE_EXIT_CTLS: 1341 case MSR_IA32_VMX_TRUE_ENTRY_CTLS: 1342 case MSR_IA32_VMX_PROCBASED_CTLS2: 1343 return vmx_restore_control_msr(vmx, msr_index, data); 1344 case MSR_IA32_VMX_MISC: 1345 return vmx_restore_vmx_misc(vmx, data); 1346 case MSR_IA32_VMX_CR0_FIXED0: 1347 case MSR_IA32_VMX_CR4_FIXED0: 1348 return vmx_restore_fixed0_msr(vmx, msr_index, data); 1349 case MSR_IA32_VMX_CR0_FIXED1: 1350 case MSR_IA32_VMX_CR4_FIXED1: 1351 /* 1352 * These MSRs are generated based on the vCPU's CPUID, so we 1353 * do not support restoring them directly. 1354 */ 1355 return -EINVAL; 1356 case MSR_IA32_VMX_EPT_VPID_CAP: 1357 return vmx_restore_vmx_ept_vpid_cap(vmx, data); 1358 case MSR_IA32_VMX_VMCS_ENUM: 1359 vmx->nested.msrs.vmcs_enum = data; 1360 return 0; 1361 case MSR_IA32_VMX_VMFUNC: 1362 if (data & ~vmx->nested.msrs.vmfunc_controls) 1363 return -EINVAL; 1364 vmx->nested.msrs.vmfunc_controls = data; 1365 return 0; 1366 default: 1367 /* 1368 * The rest of the VMX capability MSRs do not support restore. 1369 */ 1370 return -EINVAL; 1371 } 1372 } 1373 1374 /* Returns 0 on success, non-0 otherwise. */ 1375 int vmx_get_vmx_msr(struct nested_vmx_msrs *msrs, u32 msr_index, u64 *pdata) 1376 { 1377 switch (msr_index) { 1378 case MSR_IA32_VMX_BASIC: 1379 *pdata = msrs->basic; 1380 break; 1381 case MSR_IA32_VMX_TRUE_PINBASED_CTLS: 1382 case MSR_IA32_VMX_PINBASED_CTLS: 1383 *pdata = vmx_control_msr( 1384 msrs->pinbased_ctls_low, 1385 msrs->pinbased_ctls_high); 1386 if (msr_index == MSR_IA32_VMX_PINBASED_CTLS) 1387 *pdata |= PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR; 1388 break; 1389 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS: 1390 case MSR_IA32_VMX_PROCBASED_CTLS: 1391 *pdata = vmx_control_msr( 1392 msrs->procbased_ctls_low, 1393 msrs->procbased_ctls_high); 1394 if (msr_index == MSR_IA32_VMX_PROCBASED_CTLS) 1395 *pdata |= CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR; 1396 break; 1397 case MSR_IA32_VMX_TRUE_EXIT_CTLS: 1398 case MSR_IA32_VMX_EXIT_CTLS: 1399 *pdata = vmx_control_msr( 1400 msrs->exit_ctls_low, 1401 msrs->exit_ctls_high); 1402 if (msr_index == MSR_IA32_VMX_EXIT_CTLS) 1403 *pdata |= VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR; 1404 break; 1405 case MSR_IA32_VMX_TRUE_ENTRY_CTLS: 1406 case MSR_IA32_VMX_ENTRY_CTLS: 1407 *pdata = vmx_control_msr( 1408 msrs->entry_ctls_low, 1409 msrs->entry_ctls_high); 1410 if (msr_index == MSR_IA32_VMX_ENTRY_CTLS) 1411 *pdata |= VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR; 1412 break; 1413 case MSR_IA32_VMX_MISC: 1414 *pdata = vmx_control_msr( 1415 msrs->misc_low, 1416 msrs->misc_high); 1417 break; 1418 case MSR_IA32_VMX_CR0_FIXED0: 1419 *pdata = msrs->cr0_fixed0; 1420 break; 1421 case MSR_IA32_VMX_CR0_FIXED1: 1422 *pdata = msrs->cr0_fixed1; 1423 break; 1424 case MSR_IA32_VMX_CR4_FIXED0: 1425 *pdata = msrs->cr4_fixed0; 1426 break; 1427 case MSR_IA32_VMX_CR4_FIXED1: 1428 *pdata = msrs->cr4_fixed1; 1429 break; 1430 case MSR_IA32_VMX_VMCS_ENUM: 1431 *pdata = msrs->vmcs_enum; 1432 break; 1433 case MSR_IA32_VMX_PROCBASED_CTLS2: 1434 *pdata = vmx_control_msr( 1435 msrs->secondary_ctls_low, 1436 msrs->secondary_ctls_high); 1437 break; 1438 case MSR_IA32_VMX_EPT_VPID_CAP: 1439 *pdata = msrs->ept_caps | 1440 ((u64)msrs->vpid_caps << 32); 1441 break; 1442 case MSR_IA32_VMX_VMFUNC: 1443 *pdata = msrs->vmfunc_controls; 1444 break; 1445 default: 1446 return 1; 1447 } 1448 1449 return 0; 1450 } 1451 1452 /* 1453 * Copy the writable VMCS shadow fields back to the VMCS12, in case they have 1454 * been modified by the L1 guest. Note, "writable" in this context means 1455 * "writable by the guest", i.e. tagged SHADOW_FIELD_RW; the set of 1456 * fields tagged SHADOW_FIELD_RO may or may not align with the "read-only" 1457 * VM-exit information fields (which are actually writable if the vCPU is 1458 * configured to support "VMWRITE to any supported field in the VMCS"). 1459 */ 1460 static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx) 1461 { 1462 struct vmcs *shadow_vmcs = vmx->vmcs01.shadow_vmcs; 1463 struct vmcs12 *vmcs12 = get_vmcs12(&vmx->vcpu); 1464 struct shadow_vmcs_field field; 1465 unsigned long val; 1466 int i; 1467 1468 if (WARN_ON(!shadow_vmcs)) 1469 return; 1470 1471 preempt_disable(); 1472 1473 vmcs_load(shadow_vmcs); 1474 1475 for (i = 0; i < max_shadow_read_write_fields; i++) { 1476 field = shadow_read_write_fields[i]; 1477 val = __vmcs_readl(field.encoding); 1478 vmcs12_write_any(vmcs12, field.encoding, field.offset, val); 1479 } 1480 1481 vmcs_clear(shadow_vmcs); 1482 vmcs_load(vmx->loaded_vmcs->vmcs); 1483 1484 preempt_enable(); 1485 } 1486 1487 static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx) 1488 { 1489 const struct shadow_vmcs_field *fields[] = { 1490 shadow_read_write_fields, 1491 shadow_read_only_fields 1492 }; 1493 const int max_fields[] = { 1494 max_shadow_read_write_fields, 1495 max_shadow_read_only_fields 1496 }; 1497 struct vmcs *shadow_vmcs = vmx->vmcs01.shadow_vmcs; 1498 struct vmcs12 *vmcs12 = get_vmcs12(&vmx->vcpu); 1499 struct shadow_vmcs_field field; 1500 unsigned long val; 1501 int i, q; 1502 1503 if (WARN_ON(!shadow_vmcs)) 1504 return; 1505 1506 vmcs_load(shadow_vmcs); 1507 1508 for (q = 0; q < ARRAY_SIZE(fields); q++) { 1509 for (i = 0; i < max_fields[q]; i++) { 1510 field = fields[q][i]; 1511 val = vmcs12_read_any(vmcs12, field.encoding, 1512 field.offset); 1513 __vmcs_writel(field.encoding, val); 1514 } 1515 } 1516 1517 vmcs_clear(shadow_vmcs); 1518 vmcs_load(vmx->loaded_vmcs->vmcs); 1519 } 1520 1521 static int copy_enlightened_to_vmcs12(struct vcpu_vmx *vmx) 1522 { 1523 struct vmcs12 *vmcs12 = vmx->nested.cached_vmcs12; 1524 struct hv_enlightened_vmcs *evmcs = vmx->nested.hv_evmcs; 1525 1526 /* HV_VMX_ENLIGHTENED_CLEAN_FIELD_NONE */ 1527 vmcs12->tpr_threshold = evmcs->tpr_threshold; 1528 vmcs12->guest_rip = evmcs->guest_rip; 1529 1530 if (unlikely(!(evmcs->hv_clean_fields & 1531 HV_VMX_ENLIGHTENED_CLEAN_FIELD_GUEST_BASIC))) { 1532 vmcs12->guest_rsp = evmcs->guest_rsp; 1533 vmcs12->guest_rflags = evmcs->guest_rflags; 1534 vmcs12->guest_interruptibility_info = 1535 evmcs->guest_interruptibility_info; 1536 } 1537 1538 if (unlikely(!(evmcs->hv_clean_fields & 1539 HV_VMX_ENLIGHTENED_CLEAN_FIELD_CONTROL_PROC))) { 1540 vmcs12->cpu_based_vm_exec_control = 1541 evmcs->cpu_based_vm_exec_control; 1542 } 1543 1544 if (unlikely(!(evmcs->hv_clean_fields & 1545 HV_VMX_ENLIGHTENED_CLEAN_FIELD_CONTROL_EXCPN))) { 1546 vmcs12->exception_bitmap = evmcs->exception_bitmap; 1547 } 1548 1549 if (unlikely(!(evmcs->hv_clean_fields & 1550 HV_VMX_ENLIGHTENED_CLEAN_FIELD_CONTROL_ENTRY))) { 1551 vmcs12->vm_entry_controls = evmcs->vm_entry_controls; 1552 } 1553 1554 if (unlikely(!(evmcs->hv_clean_fields & 1555 HV_VMX_ENLIGHTENED_CLEAN_FIELD_CONTROL_EVENT))) { 1556 vmcs12->vm_entry_intr_info_field = 1557 evmcs->vm_entry_intr_info_field; 1558 vmcs12->vm_entry_exception_error_code = 1559 evmcs->vm_entry_exception_error_code; 1560 vmcs12->vm_entry_instruction_len = 1561 evmcs->vm_entry_instruction_len; 1562 } 1563 1564 if (unlikely(!(evmcs->hv_clean_fields & 1565 HV_VMX_ENLIGHTENED_CLEAN_FIELD_HOST_GRP1))) { 1566 vmcs12->host_ia32_pat = evmcs->host_ia32_pat; 1567 vmcs12->host_ia32_efer = evmcs->host_ia32_efer; 1568 vmcs12->host_cr0 = evmcs->host_cr0; 1569 vmcs12->host_cr3 = evmcs->host_cr3; 1570 vmcs12->host_cr4 = evmcs->host_cr4; 1571 vmcs12->host_ia32_sysenter_esp = evmcs->host_ia32_sysenter_esp; 1572 vmcs12->host_ia32_sysenter_eip = evmcs->host_ia32_sysenter_eip; 1573 vmcs12->host_rip = evmcs->host_rip; 1574 vmcs12->host_ia32_sysenter_cs = evmcs->host_ia32_sysenter_cs; 1575 vmcs12->host_es_selector = evmcs->host_es_selector; 1576 vmcs12->host_cs_selector = evmcs->host_cs_selector; 1577 vmcs12->host_ss_selector = evmcs->host_ss_selector; 1578 vmcs12->host_ds_selector = evmcs->host_ds_selector; 1579 vmcs12->host_fs_selector = evmcs->host_fs_selector; 1580 vmcs12->host_gs_selector = evmcs->host_gs_selector; 1581 vmcs12->host_tr_selector = evmcs->host_tr_selector; 1582 } 1583 1584 if (unlikely(!(evmcs->hv_clean_fields & 1585 HV_VMX_ENLIGHTENED_CLEAN_FIELD_CONTROL_GRP1))) { 1586 vmcs12->pin_based_vm_exec_control = 1587 evmcs->pin_based_vm_exec_control; 1588 vmcs12->vm_exit_controls = evmcs->vm_exit_controls; 1589 vmcs12->secondary_vm_exec_control = 1590 evmcs->secondary_vm_exec_control; 1591 } 1592 1593 if (unlikely(!(evmcs->hv_clean_fields & 1594 HV_VMX_ENLIGHTENED_CLEAN_FIELD_IO_BITMAP))) { 1595 vmcs12->io_bitmap_a = evmcs->io_bitmap_a; 1596 vmcs12->io_bitmap_b = evmcs->io_bitmap_b; 1597 } 1598 1599 if (unlikely(!(evmcs->hv_clean_fields & 1600 HV_VMX_ENLIGHTENED_CLEAN_FIELD_MSR_BITMAP))) { 1601 vmcs12->msr_bitmap = evmcs->msr_bitmap; 1602 } 1603 1604 if (unlikely(!(evmcs->hv_clean_fields & 1605 HV_VMX_ENLIGHTENED_CLEAN_FIELD_GUEST_GRP2))) { 1606 vmcs12->guest_es_base = evmcs->guest_es_base; 1607 vmcs12->guest_cs_base = evmcs->guest_cs_base; 1608 vmcs12->guest_ss_base = evmcs->guest_ss_base; 1609 vmcs12->guest_ds_base = evmcs->guest_ds_base; 1610 vmcs12->guest_fs_base = evmcs->guest_fs_base; 1611 vmcs12->guest_gs_base = evmcs->guest_gs_base; 1612 vmcs12->guest_ldtr_base = evmcs->guest_ldtr_base; 1613 vmcs12->guest_tr_base = evmcs->guest_tr_base; 1614 vmcs12->guest_gdtr_base = evmcs->guest_gdtr_base; 1615 vmcs12->guest_idtr_base = evmcs->guest_idtr_base; 1616 vmcs12->guest_es_limit = evmcs->guest_es_limit; 1617 vmcs12->guest_cs_limit = evmcs->guest_cs_limit; 1618 vmcs12->guest_ss_limit = evmcs->guest_ss_limit; 1619 vmcs12->guest_ds_limit = evmcs->guest_ds_limit; 1620 vmcs12->guest_fs_limit = evmcs->guest_fs_limit; 1621 vmcs12->guest_gs_limit = evmcs->guest_gs_limit; 1622 vmcs12->guest_ldtr_limit = evmcs->guest_ldtr_limit; 1623 vmcs12->guest_tr_limit = evmcs->guest_tr_limit; 1624 vmcs12->guest_gdtr_limit = evmcs->guest_gdtr_limit; 1625 vmcs12->guest_idtr_limit = evmcs->guest_idtr_limit; 1626 vmcs12->guest_es_ar_bytes = evmcs->guest_es_ar_bytes; 1627 vmcs12->guest_cs_ar_bytes = evmcs->guest_cs_ar_bytes; 1628 vmcs12->guest_ss_ar_bytes = evmcs->guest_ss_ar_bytes; 1629 vmcs12->guest_ds_ar_bytes = evmcs->guest_ds_ar_bytes; 1630 vmcs12->guest_fs_ar_bytes = evmcs->guest_fs_ar_bytes; 1631 vmcs12->guest_gs_ar_bytes = evmcs->guest_gs_ar_bytes; 1632 vmcs12->guest_ldtr_ar_bytes = evmcs->guest_ldtr_ar_bytes; 1633 vmcs12->guest_tr_ar_bytes = evmcs->guest_tr_ar_bytes; 1634 vmcs12->guest_es_selector = evmcs->guest_es_selector; 1635 vmcs12->guest_cs_selector = evmcs->guest_cs_selector; 1636 vmcs12->guest_ss_selector = evmcs->guest_ss_selector; 1637 vmcs12->guest_ds_selector = evmcs->guest_ds_selector; 1638 vmcs12->guest_fs_selector = evmcs->guest_fs_selector; 1639 vmcs12->guest_gs_selector = evmcs->guest_gs_selector; 1640 vmcs12->guest_ldtr_selector = evmcs->guest_ldtr_selector; 1641 vmcs12->guest_tr_selector = evmcs->guest_tr_selector; 1642 } 1643 1644 if (unlikely(!(evmcs->hv_clean_fields & 1645 HV_VMX_ENLIGHTENED_CLEAN_FIELD_CONTROL_GRP2))) { 1646 vmcs12->tsc_offset = evmcs->tsc_offset; 1647 vmcs12->virtual_apic_page_addr = evmcs->virtual_apic_page_addr; 1648 vmcs12->xss_exit_bitmap = evmcs->xss_exit_bitmap; 1649 } 1650 1651 if (unlikely(!(evmcs->hv_clean_fields & 1652 HV_VMX_ENLIGHTENED_CLEAN_FIELD_CRDR))) { 1653 vmcs12->cr0_guest_host_mask = evmcs->cr0_guest_host_mask; 1654 vmcs12->cr4_guest_host_mask = evmcs->cr4_guest_host_mask; 1655 vmcs12->cr0_read_shadow = evmcs->cr0_read_shadow; 1656 vmcs12->cr4_read_shadow = evmcs->cr4_read_shadow; 1657 vmcs12->guest_cr0 = evmcs->guest_cr0; 1658 vmcs12->guest_cr3 = evmcs->guest_cr3; 1659 vmcs12->guest_cr4 = evmcs->guest_cr4; 1660 vmcs12->guest_dr7 = evmcs->guest_dr7; 1661 } 1662 1663 if (unlikely(!(evmcs->hv_clean_fields & 1664 HV_VMX_ENLIGHTENED_CLEAN_FIELD_HOST_POINTER))) { 1665 vmcs12->host_fs_base = evmcs->host_fs_base; 1666 vmcs12->host_gs_base = evmcs->host_gs_base; 1667 vmcs12->host_tr_base = evmcs->host_tr_base; 1668 vmcs12->host_gdtr_base = evmcs->host_gdtr_base; 1669 vmcs12->host_idtr_base = evmcs->host_idtr_base; 1670 vmcs12->host_rsp = evmcs->host_rsp; 1671 } 1672 1673 if (unlikely(!(evmcs->hv_clean_fields & 1674 HV_VMX_ENLIGHTENED_CLEAN_FIELD_CONTROL_XLAT))) { 1675 vmcs12->ept_pointer = evmcs->ept_pointer; 1676 vmcs12->virtual_processor_id = evmcs->virtual_processor_id; 1677 } 1678 1679 if (unlikely(!(evmcs->hv_clean_fields & 1680 HV_VMX_ENLIGHTENED_CLEAN_FIELD_GUEST_GRP1))) { 1681 vmcs12->vmcs_link_pointer = evmcs->vmcs_link_pointer; 1682 vmcs12->guest_ia32_debugctl = evmcs->guest_ia32_debugctl; 1683 vmcs12->guest_ia32_pat = evmcs->guest_ia32_pat; 1684 vmcs12->guest_ia32_efer = evmcs->guest_ia32_efer; 1685 vmcs12->guest_pdptr0 = evmcs->guest_pdptr0; 1686 vmcs12->guest_pdptr1 = evmcs->guest_pdptr1; 1687 vmcs12->guest_pdptr2 = evmcs->guest_pdptr2; 1688 vmcs12->guest_pdptr3 = evmcs->guest_pdptr3; 1689 vmcs12->guest_pending_dbg_exceptions = 1690 evmcs->guest_pending_dbg_exceptions; 1691 vmcs12->guest_sysenter_esp = evmcs->guest_sysenter_esp; 1692 vmcs12->guest_sysenter_eip = evmcs->guest_sysenter_eip; 1693 vmcs12->guest_bndcfgs = evmcs->guest_bndcfgs; 1694 vmcs12->guest_activity_state = evmcs->guest_activity_state; 1695 vmcs12->guest_sysenter_cs = evmcs->guest_sysenter_cs; 1696 } 1697 1698 /* 1699 * Not used? 1700 * vmcs12->vm_exit_msr_store_addr = evmcs->vm_exit_msr_store_addr; 1701 * vmcs12->vm_exit_msr_load_addr = evmcs->vm_exit_msr_load_addr; 1702 * vmcs12->vm_entry_msr_load_addr = evmcs->vm_entry_msr_load_addr; 1703 * vmcs12->cr3_target_value0 = evmcs->cr3_target_value0; 1704 * vmcs12->cr3_target_value1 = evmcs->cr3_target_value1; 1705 * vmcs12->cr3_target_value2 = evmcs->cr3_target_value2; 1706 * vmcs12->cr3_target_value3 = evmcs->cr3_target_value3; 1707 * vmcs12->page_fault_error_code_mask = 1708 * evmcs->page_fault_error_code_mask; 1709 * vmcs12->page_fault_error_code_match = 1710 * evmcs->page_fault_error_code_match; 1711 * vmcs12->cr3_target_count = evmcs->cr3_target_count; 1712 * vmcs12->vm_exit_msr_store_count = evmcs->vm_exit_msr_store_count; 1713 * vmcs12->vm_exit_msr_load_count = evmcs->vm_exit_msr_load_count; 1714 * vmcs12->vm_entry_msr_load_count = evmcs->vm_entry_msr_load_count; 1715 */ 1716 1717 /* 1718 * Read only fields: 1719 * vmcs12->guest_physical_address = evmcs->guest_physical_address; 1720 * vmcs12->vm_instruction_error = evmcs->vm_instruction_error; 1721 * vmcs12->vm_exit_reason = evmcs->vm_exit_reason; 1722 * vmcs12->vm_exit_intr_info = evmcs->vm_exit_intr_info; 1723 * vmcs12->vm_exit_intr_error_code = evmcs->vm_exit_intr_error_code; 1724 * vmcs12->idt_vectoring_info_field = evmcs->idt_vectoring_info_field; 1725 * vmcs12->idt_vectoring_error_code = evmcs->idt_vectoring_error_code; 1726 * vmcs12->vm_exit_instruction_len = evmcs->vm_exit_instruction_len; 1727 * vmcs12->vmx_instruction_info = evmcs->vmx_instruction_info; 1728 * vmcs12->exit_qualification = evmcs->exit_qualification; 1729 * vmcs12->guest_linear_address = evmcs->guest_linear_address; 1730 * 1731 * Not present in struct vmcs12: 1732 * vmcs12->exit_io_instruction_ecx = evmcs->exit_io_instruction_ecx; 1733 * vmcs12->exit_io_instruction_esi = evmcs->exit_io_instruction_esi; 1734 * vmcs12->exit_io_instruction_edi = evmcs->exit_io_instruction_edi; 1735 * vmcs12->exit_io_instruction_eip = evmcs->exit_io_instruction_eip; 1736 */ 1737 1738 return 0; 1739 } 1740 1741 static int copy_vmcs12_to_enlightened(struct vcpu_vmx *vmx) 1742 { 1743 struct vmcs12 *vmcs12 = vmx->nested.cached_vmcs12; 1744 struct hv_enlightened_vmcs *evmcs = vmx->nested.hv_evmcs; 1745 1746 /* 1747 * Should not be changed by KVM: 1748 * 1749 * evmcs->host_es_selector = vmcs12->host_es_selector; 1750 * evmcs->host_cs_selector = vmcs12->host_cs_selector; 1751 * evmcs->host_ss_selector = vmcs12->host_ss_selector; 1752 * evmcs->host_ds_selector = vmcs12->host_ds_selector; 1753 * evmcs->host_fs_selector = vmcs12->host_fs_selector; 1754 * evmcs->host_gs_selector = vmcs12->host_gs_selector; 1755 * evmcs->host_tr_selector = vmcs12->host_tr_selector; 1756 * evmcs->host_ia32_pat = vmcs12->host_ia32_pat; 1757 * evmcs->host_ia32_efer = vmcs12->host_ia32_efer; 1758 * evmcs->host_cr0 = vmcs12->host_cr0; 1759 * evmcs->host_cr3 = vmcs12->host_cr3; 1760 * evmcs->host_cr4 = vmcs12->host_cr4; 1761 * evmcs->host_ia32_sysenter_esp = vmcs12->host_ia32_sysenter_esp; 1762 * evmcs->host_ia32_sysenter_eip = vmcs12->host_ia32_sysenter_eip; 1763 * evmcs->host_rip = vmcs12->host_rip; 1764 * evmcs->host_ia32_sysenter_cs = vmcs12->host_ia32_sysenter_cs; 1765 * evmcs->host_fs_base = vmcs12->host_fs_base; 1766 * evmcs->host_gs_base = vmcs12->host_gs_base; 1767 * evmcs->host_tr_base = vmcs12->host_tr_base; 1768 * evmcs->host_gdtr_base = vmcs12->host_gdtr_base; 1769 * evmcs->host_idtr_base = vmcs12->host_idtr_base; 1770 * evmcs->host_rsp = vmcs12->host_rsp; 1771 * sync_vmcs02_to_vmcs12() doesn't read these: 1772 * evmcs->io_bitmap_a = vmcs12->io_bitmap_a; 1773 * evmcs->io_bitmap_b = vmcs12->io_bitmap_b; 1774 * evmcs->msr_bitmap = vmcs12->msr_bitmap; 1775 * evmcs->ept_pointer = vmcs12->ept_pointer; 1776 * evmcs->xss_exit_bitmap = vmcs12->xss_exit_bitmap; 1777 * evmcs->vm_exit_msr_store_addr = vmcs12->vm_exit_msr_store_addr; 1778 * evmcs->vm_exit_msr_load_addr = vmcs12->vm_exit_msr_load_addr; 1779 * evmcs->vm_entry_msr_load_addr = vmcs12->vm_entry_msr_load_addr; 1780 * evmcs->cr3_target_value0 = vmcs12->cr3_target_value0; 1781 * evmcs->cr3_target_value1 = vmcs12->cr3_target_value1; 1782 * evmcs->cr3_target_value2 = vmcs12->cr3_target_value2; 1783 * evmcs->cr3_target_value3 = vmcs12->cr3_target_value3; 1784 * evmcs->tpr_threshold = vmcs12->tpr_threshold; 1785 * evmcs->virtual_processor_id = vmcs12->virtual_processor_id; 1786 * evmcs->exception_bitmap = vmcs12->exception_bitmap; 1787 * evmcs->vmcs_link_pointer = vmcs12->vmcs_link_pointer; 1788 * evmcs->pin_based_vm_exec_control = vmcs12->pin_based_vm_exec_control; 1789 * evmcs->vm_exit_controls = vmcs12->vm_exit_controls; 1790 * evmcs->secondary_vm_exec_control = vmcs12->secondary_vm_exec_control; 1791 * evmcs->page_fault_error_code_mask = 1792 * vmcs12->page_fault_error_code_mask; 1793 * evmcs->page_fault_error_code_match = 1794 * vmcs12->page_fault_error_code_match; 1795 * evmcs->cr3_target_count = vmcs12->cr3_target_count; 1796 * evmcs->virtual_apic_page_addr = vmcs12->virtual_apic_page_addr; 1797 * evmcs->tsc_offset = vmcs12->tsc_offset; 1798 * evmcs->guest_ia32_debugctl = vmcs12->guest_ia32_debugctl; 1799 * evmcs->cr0_guest_host_mask = vmcs12->cr0_guest_host_mask; 1800 * evmcs->cr4_guest_host_mask = vmcs12->cr4_guest_host_mask; 1801 * evmcs->cr0_read_shadow = vmcs12->cr0_read_shadow; 1802 * evmcs->cr4_read_shadow = vmcs12->cr4_read_shadow; 1803 * evmcs->vm_exit_msr_store_count = vmcs12->vm_exit_msr_store_count; 1804 * evmcs->vm_exit_msr_load_count = vmcs12->vm_exit_msr_load_count; 1805 * evmcs->vm_entry_msr_load_count = vmcs12->vm_entry_msr_load_count; 1806 * 1807 * Not present in struct vmcs12: 1808 * evmcs->exit_io_instruction_ecx = vmcs12->exit_io_instruction_ecx; 1809 * evmcs->exit_io_instruction_esi = vmcs12->exit_io_instruction_esi; 1810 * evmcs->exit_io_instruction_edi = vmcs12->exit_io_instruction_edi; 1811 * evmcs->exit_io_instruction_eip = vmcs12->exit_io_instruction_eip; 1812 */ 1813 1814 evmcs->guest_es_selector = vmcs12->guest_es_selector; 1815 evmcs->guest_cs_selector = vmcs12->guest_cs_selector; 1816 evmcs->guest_ss_selector = vmcs12->guest_ss_selector; 1817 evmcs->guest_ds_selector = vmcs12->guest_ds_selector; 1818 evmcs->guest_fs_selector = vmcs12->guest_fs_selector; 1819 evmcs->guest_gs_selector = vmcs12->guest_gs_selector; 1820 evmcs->guest_ldtr_selector = vmcs12->guest_ldtr_selector; 1821 evmcs->guest_tr_selector = vmcs12->guest_tr_selector; 1822 1823 evmcs->guest_es_limit = vmcs12->guest_es_limit; 1824 evmcs->guest_cs_limit = vmcs12->guest_cs_limit; 1825 evmcs->guest_ss_limit = vmcs12->guest_ss_limit; 1826 evmcs->guest_ds_limit = vmcs12->guest_ds_limit; 1827 evmcs->guest_fs_limit = vmcs12->guest_fs_limit; 1828 evmcs->guest_gs_limit = vmcs12->guest_gs_limit; 1829 evmcs->guest_ldtr_limit = vmcs12->guest_ldtr_limit; 1830 evmcs->guest_tr_limit = vmcs12->guest_tr_limit; 1831 evmcs->guest_gdtr_limit = vmcs12->guest_gdtr_limit; 1832 evmcs->guest_idtr_limit = vmcs12->guest_idtr_limit; 1833 1834 evmcs->guest_es_ar_bytes = vmcs12->guest_es_ar_bytes; 1835 evmcs->guest_cs_ar_bytes = vmcs12->guest_cs_ar_bytes; 1836 evmcs->guest_ss_ar_bytes = vmcs12->guest_ss_ar_bytes; 1837 evmcs->guest_ds_ar_bytes = vmcs12->guest_ds_ar_bytes; 1838 evmcs->guest_fs_ar_bytes = vmcs12->guest_fs_ar_bytes; 1839 evmcs->guest_gs_ar_bytes = vmcs12->guest_gs_ar_bytes; 1840 evmcs->guest_ldtr_ar_bytes = vmcs12->guest_ldtr_ar_bytes; 1841 evmcs->guest_tr_ar_bytes = vmcs12->guest_tr_ar_bytes; 1842 1843 evmcs->guest_es_base = vmcs12->guest_es_base; 1844 evmcs->guest_cs_base = vmcs12->guest_cs_base; 1845 evmcs->guest_ss_base = vmcs12->guest_ss_base; 1846 evmcs->guest_ds_base = vmcs12->guest_ds_base; 1847 evmcs->guest_fs_base = vmcs12->guest_fs_base; 1848 evmcs->guest_gs_base = vmcs12->guest_gs_base; 1849 evmcs->guest_ldtr_base = vmcs12->guest_ldtr_base; 1850 evmcs->guest_tr_base = vmcs12->guest_tr_base; 1851 evmcs->guest_gdtr_base = vmcs12->guest_gdtr_base; 1852 evmcs->guest_idtr_base = vmcs12->guest_idtr_base; 1853 1854 evmcs->guest_ia32_pat = vmcs12->guest_ia32_pat; 1855 evmcs->guest_ia32_efer = vmcs12->guest_ia32_efer; 1856 1857 evmcs->guest_pdptr0 = vmcs12->guest_pdptr0; 1858 evmcs->guest_pdptr1 = vmcs12->guest_pdptr1; 1859 evmcs->guest_pdptr2 = vmcs12->guest_pdptr2; 1860 evmcs->guest_pdptr3 = vmcs12->guest_pdptr3; 1861 1862 evmcs->guest_pending_dbg_exceptions = 1863 vmcs12->guest_pending_dbg_exceptions; 1864 evmcs->guest_sysenter_esp = vmcs12->guest_sysenter_esp; 1865 evmcs->guest_sysenter_eip = vmcs12->guest_sysenter_eip; 1866 1867 evmcs->guest_activity_state = vmcs12->guest_activity_state; 1868 evmcs->guest_sysenter_cs = vmcs12->guest_sysenter_cs; 1869 1870 evmcs->guest_cr0 = vmcs12->guest_cr0; 1871 evmcs->guest_cr3 = vmcs12->guest_cr3; 1872 evmcs->guest_cr4 = vmcs12->guest_cr4; 1873 evmcs->guest_dr7 = vmcs12->guest_dr7; 1874 1875 evmcs->guest_physical_address = vmcs12->guest_physical_address; 1876 1877 evmcs->vm_instruction_error = vmcs12->vm_instruction_error; 1878 evmcs->vm_exit_reason = vmcs12->vm_exit_reason; 1879 evmcs->vm_exit_intr_info = vmcs12->vm_exit_intr_info; 1880 evmcs->vm_exit_intr_error_code = vmcs12->vm_exit_intr_error_code; 1881 evmcs->idt_vectoring_info_field = vmcs12->idt_vectoring_info_field; 1882 evmcs->idt_vectoring_error_code = vmcs12->idt_vectoring_error_code; 1883 evmcs->vm_exit_instruction_len = vmcs12->vm_exit_instruction_len; 1884 evmcs->vmx_instruction_info = vmcs12->vmx_instruction_info; 1885 1886 evmcs->exit_qualification = vmcs12->exit_qualification; 1887 1888 evmcs->guest_linear_address = vmcs12->guest_linear_address; 1889 evmcs->guest_rsp = vmcs12->guest_rsp; 1890 evmcs->guest_rflags = vmcs12->guest_rflags; 1891 1892 evmcs->guest_interruptibility_info = 1893 vmcs12->guest_interruptibility_info; 1894 evmcs->cpu_based_vm_exec_control = vmcs12->cpu_based_vm_exec_control; 1895 evmcs->vm_entry_controls = vmcs12->vm_entry_controls; 1896 evmcs->vm_entry_intr_info_field = vmcs12->vm_entry_intr_info_field; 1897 evmcs->vm_entry_exception_error_code = 1898 vmcs12->vm_entry_exception_error_code; 1899 evmcs->vm_entry_instruction_len = vmcs12->vm_entry_instruction_len; 1900 1901 evmcs->guest_rip = vmcs12->guest_rip; 1902 1903 evmcs->guest_bndcfgs = vmcs12->guest_bndcfgs; 1904 1905 return 0; 1906 } 1907 1908 /* 1909 * This is an equivalent of the nested hypervisor executing the vmptrld 1910 * instruction. 1911 */ 1912 static int nested_vmx_handle_enlightened_vmptrld(struct kvm_vcpu *vcpu, 1913 bool from_launch) 1914 { 1915 struct vcpu_vmx *vmx = to_vmx(vcpu); 1916 bool evmcs_gpa_changed = false; 1917 u64 evmcs_gpa; 1918 1919 if (likely(!vmx->nested.enlightened_vmcs_enabled)) 1920 return 1; 1921 1922 if (!nested_enlightened_vmentry(vcpu, &evmcs_gpa)) 1923 return 1; 1924 1925 if (unlikely(evmcs_gpa != vmx->nested.hv_evmcs_vmptr)) { 1926 if (!vmx->nested.hv_evmcs) 1927 vmx->nested.current_vmptr = -1ull; 1928 1929 nested_release_evmcs(vcpu); 1930 1931 if (kvm_vcpu_map(vcpu, gpa_to_gfn(evmcs_gpa), 1932 &vmx->nested.hv_evmcs_map)) 1933 return 0; 1934 1935 vmx->nested.hv_evmcs = vmx->nested.hv_evmcs_map.hva; 1936 1937 /* 1938 * Currently, KVM only supports eVMCS version 1 1939 * (== KVM_EVMCS_VERSION) and thus we expect guest to set this 1940 * value to first u32 field of eVMCS which should specify eVMCS 1941 * VersionNumber. 1942 * 1943 * Guest should be aware of supported eVMCS versions by host by 1944 * examining CPUID.0x4000000A.EAX[0:15]. Host userspace VMM is 1945 * expected to set this CPUID leaf according to the value 1946 * returned in vmcs_version from nested_enable_evmcs(). 1947 * 1948 * However, it turns out that Microsoft Hyper-V fails to comply 1949 * to their own invented interface: When Hyper-V use eVMCS, it 1950 * just sets first u32 field of eVMCS to revision_id specified 1951 * in MSR_IA32_VMX_BASIC. Instead of used eVMCS version number 1952 * which is one of the supported versions specified in 1953 * CPUID.0x4000000A.EAX[0:15]. 1954 * 1955 * To overcome Hyper-V bug, we accept here either a supported 1956 * eVMCS version or VMCS12 revision_id as valid values for first 1957 * u32 field of eVMCS. 1958 */ 1959 if ((vmx->nested.hv_evmcs->revision_id != KVM_EVMCS_VERSION) && 1960 (vmx->nested.hv_evmcs->revision_id != VMCS12_REVISION)) { 1961 nested_release_evmcs(vcpu); 1962 return 0; 1963 } 1964 1965 vmx->nested.dirty_vmcs12 = true; 1966 vmx->nested.hv_evmcs_vmptr = evmcs_gpa; 1967 1968 evmcs_gpa_changed = true; 1969 /* 1970 * Unlike normal vmcs12, enlightened vmcs12 is not fully 1971 * reloaded from guest's memory (read only fields, fields not 1972 * present in struct hv_enlightened_vmcs, ...). Make sure there 1973 * are no leftovers. 1974 */ 1975 if (from_launch) { 1976 struct vmcs12 *vmcs12 = get_vmcs12(vcpu); 1977 memset(vmcs12, 0, sizeof(*vmcs12)); 1978 vmcs12->hdr.revision_id = VMCS12_REVISION; 1979 } 1980 1981 } 1982 1983 /* 1984 * Clean fields data can't de used on VMLAUNCH and when we switch 1985 * between different L2 guests as KVM keeps a single VMCS12 per L1. 1986 */ 1987 if (from_launch || evmcs_gpa_changed) 1988 vmx->nested.hv_evmcs->hv_clean_fields &= 1989 ~HV_VMX_ENLIGHTENED_CLEAN_FIELD_ALL; 1990 1991 return 1; 1992 } 1993 1994 void nested_sync_vmcs12_to_shadow(struct kvm_vcpu *vcpu) 1995 { 1996 struct vcpu_vmx *vmx = to_vmx(vcpu); 1997 1998 /* 1999 * hv_evmcs may end up being not mapped after migration (when 2000 * L2 was running), map it here to make sure vmcs12 changes are 2001 * properly reflected. 2002 */ 2003 if (vmx->nested.enlightened_vmcs_enabled && !vmx->nested.hv_evmcs) 2004 nested_vmx_handle_enlightened_vmptrld(vcpu, false); 2005 2006 if (vmx->nested.hv_evmcs) { 2007 copy_vmcs12_to_enlightened(vmx); 2008 /* All fields are clean */ 2009 vmx->nested.hv_evmcs->hv_clean_fields |= 2010 HV_VMX_ENLIGHTENED_CLEAN_FIELD_ALL; 2011 } else { 2012 copy_vmcs12_to_shadow(vmx); 2013 } 2014 2015 vmx->nested.need_vmcs12_to_shadow_sync = false; 2016 } 2017 2018 static enum hrtimer_restart vmx_preemption_timer_fn(struct hrtimer *timer) 2019 { 2020 struct vcpu_vmx *vmx = 2021 container_of(timer, struct vcpu_vmx, nested.preemption_timer); 2022 2023 vmx->nested.preemption_timer_expired = true; 2024 kvm_make_request(KVM_REQ_EVENT, &vmx->vcpu); 2025 kvm_vcpu_kick(&vmx->vcpu); 2026 2027 return HRTIMER_NORESTART; 2028 } 2029 2030 static void vmx_start_preemption_timer(struct kvm_vcpu *vcpu) 2031 { 2032 u64 preemption_timeout = get_vmcs12(vcpu)->vmx_preemption_timer_value; 2033 struct vcpu_vmx *vmx = to_vmx(vcpu); 2034 2035 /* 2036 * A timer value of zero is architecturally guaranteed to cause 2037 * a VMExit prior to executing any instructions in the guest. 2038 */ 2039 if (preemption_timeout == 0) { 2040 vmx_preemption_timer_fn(&vmx->nested.preemption_timer); 2041 return; 2042 } 2043 2044 if (vcpu->arch.virtual_tsc_khz == 0) 2045 return; 2046 2047 preemption_timeout <<= VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE; 2048 preemption_timeout *= 1000000; 2049 do_div(preemption_timeout, vcpu->arch.virtual_tsc_khz); 2050 hrtimer_start(&vmx->nested.preemption_timer, 2051 ns_to_ktime(preemption_timeout), HRTIMER_MODE_REL); 2052 } 2053 2054 static u64 nested_vmx_calc_efer(struct vcpu_vmx *vmx, struct vmcs12 *vmcs12) 2055 { 2056 if (vmx->nested.nested_run_pending && 2057 (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER)) 2058 return vmcs12->guest_ia32_efer; 2059 else if (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE) 2060 return vmx->vcpu.arch.efer | (EFER_LMA | EFER_LME); 2061 else 2062 return vmx->vcpu.arch.efer & ~(EFER_LMA | EFER_LME); 2063 } 2064 2065 static void prepare_vmcs02_constant_state(struct vcpu_vmx *vmx) 2066 { 2067 /* 2068 * If vmcs02 hasn't been initialized, set the constant vmcs02 state 2069 * according to L0's settings (vmcs12 is irrelevant here). Host 2070 * fields that come from L0 and are not constant, e.g. HOST_CR3, 2071 * will be set as needed prior to VMLAUNCH/VMRESUME. 2072 */ 2073 if (vmx->nested.vmcs02_initialized) 2074 return; 2075 vmx->nested.vmcs02_initialized = true; 2076 2077 /* 2078 * We don't care what the EPTP value is we just need to guarantee 2079 * it's valid so we don't get a false positive when doing early 2080 * consistency checks. 2081 */ 2082 if (enable_ept && nested_early_check) 2083 vmcs_write64(EPT_POINTER, construct_eptp(&vmx->vcpu, 0)); 2084 2085 /* All VMFUNCs are currently emulated through L0 vmexits. */ 2086 if (cpu_has_vmx_vmfunc()) 2087 vmcs_write64(VM_FUNCTION_CONTROL, 0); 2088 2089 if (cpu_has_vmx_posted_intr()) 2090 vmcs_write16(POSTED_INTR_NV, POSTED_INTR_NESTED_VECTOR); 2091 2092 if (cpu_has_vmx_msr_bitmap()) 2093 vmcs_write64(MSR_BITMAP, __pa(vmx->nested.vmcs02.msr_bitmap)); 2094 2095 /* 2096 * The PML address never changes, so it is constant in vmcs02. 2097 * Conceptually we want to copy the PML index from vmcs01 here, 2098 * and then back to vmcs01 on nested vmexit. But since we flush 2099 * the log and reset GUEST_PML_INDEX on each vmexit, the PML 2100 * index is also effectively constant in vmcs02. 2101 */ 2102 if (enable_pml) { 2103 vmcs_write64(PML_ADDRESS, page_to_phys(vmx->pml_pg)); 2104 vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1); 2105 } 2106 2107 if (cpu_has_vmx_encls_vmexit()) 2108 vmcs_write64(ENCLS_EXITING_BITMAP, -1ull); 2109 2110 /* 2111 * Set the MSR load/store lists to match L0's settings. Only the 2112 * addresses are constant (for vmcs02), the counts can change based 2113 * on L2's behavior, e.g. switching to/from long mode. 2114 */ 2115 vmcs_write64(VM_EXIT_MSR_STORE_ADDR, __pa(vmx->msr_autostore.guest.val)); 2116 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host.val)); 2117 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest.val)); 2118 2119 vmx_set_constant_host_state(vmx); 2120 } 2121 2122 static void prepare_vmcs02_early_rare(struct vcpu_vmx *vmx, 2123 struct vmcs12 *vmcs12) 2124 { 2125 prepare_vmcs02_constant_state(vmx); 2126 2127 vmcs_write64(VMCS_LINK_POINTER, -1ull); 2128 2129 if (enable_vpid) { 2130 if (nested_cpu_has_vpid(vmcs12) && vmx->nested.vpid02) 2131 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->nested.vpid02); 2132 else 2133 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid); 2134 } 2135 } 2136 2137 static void prepare_vmcs02_early(struct vcpu_vmx *vmx, struct vmcs12 *vmcs12) 2138 { 2139 u32 exec_control, vmcs12_exec_ctrl; 2140 u64 guest_efer = nested_vmx_calc_efer(vmx, vmcs12); 2141 2142 if (vmx->nested.dirty_vmcs12 || vmx->nested.hv_evmcs) 2143 prepare_vmcs02_early_rare(vmx, vmcs12); 2144 2145 /* 2146 * PIN CONTROLS 2147 */ 2148 exec_control = vmx_pin_based_exec_ctrl(vmx); 2149 exec_control |= (vmcs12->pin_based_vm_exec_control & 2150 ~PIN_BASED_VMX_PREEMPTION_TIMER); 2151 2152 /* Posted interrupts setting is only taken from vmcs12. */ 2153 if (nested_cpu_has_posted_intr(vmcs12)) { 2154 vmx->nested.posted_intr_nv = vmcs12->posted_intr_nv; 2155 vmx->nested.pi_pending = false; 2156 } else { 2157 exec_control &= ~PIN_BASED_POSTED_INTR; 2158 } 2159 pin_controls_set(vmx, exec_control); 2160 2161 /* 2162 * EXEC CONTROLS 2163 */ 2164 exec_control = vmx_exec_control(vmx); /* L0's desires */ 2165 exec_control &= ~CPU_BASED_INTR_WINDOW_EXITING; 2166 exec_control &= ~CPU_BASED_NMI_WINDOW_EXITING; 2167 exec_control &= ~CPU_BASED_TPR_SHADOW; 2168 exec_control |= vmcs12->cpu_based_vm_exec_control; 2169 2170 vmx->nested.l1_tpr_threshold = -1; 2171 if (exec_control & CPU_BASED_TPR_SHADOW) 2172 vmcs_write32(TPR_THRESHOLD, vmcs12->tpr_threshold); 2173 #ifdef CONFIG_X86_64 2174 else 2175 exec_control |= CPU_BASED_CR8_LOAD_EXITING | 2176 CPU_BASED_CR8_STORE_EXITING; 2177 #endif 2178 2179 /* 2180 * A vmexit (to either L1 hypervisor or L0 userspace) is always needed 2181 * for I/O port accesses. 2182 */ 2183 exec_control |= CPU_BASED_UNCOND_IO_EXITING; 2184 exec_control &= ~CPU_BASED_USE_IO_BITMAPS; 2185 2186 /* 2187 * This bit will be computed in nested_get_vmcs12_pages, because 2188 * we do not have access to L1's MSR bitmap yet. For now, keep 2189 * the same bit as before, hoping to avoid multiple VMWRITEs that 2190 * only set/clear this bit. 2191 */ 2192 exec_control &= ~CPU_BASED_USE_MSR_BITMAPS; 2193 exec_control |= exec_controls_get(vmx) & CPU_BASED_USE_MSR_BITMAPS; 2194 2195 exec_controls_set(vmx, exec_control); 2196 2197 /* 2198 * SECONDARY EXEC CONTROLS 2199 */ 2200 if (cpu_has_secondary_exec_ctrls()) { 2201 exec_control = vmx->secondary_exec_control; 2202 2203 /* Take the following fields only from vmcs12 */ 2204 exec_control &= ~(SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 2205 SECONDARY_EXEC_ENABLE_INVPCID | 2206 SECONDARY_EXEC_RDTSCP | 2207 SECONDARY_EXEC_XSAVES | 2208 SECONDARY_EXEC_ENABLE_USR_WAIT_PAUSE | 2209 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 2210 SECONDARY_EXEC_APIC_REGISTER_VIRT | 2211 SECONDARY_EXEC_ENABLE_VMFUNC); 2212 if (nested_cpu_has(vmcs12, 2213 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS)) { 2214 vmcs12_exec_ctrl = vmcs12->secondary_vm_exec_control & 2215 ~SECONDARY_EXEC_ENABLE_PML; 2216 exec_control |= vmcs12_exec_ctrl; 2217 } 2218 2219 /* VMCS shadowing for L2 is emulated for now */ 2220 exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS; 2221 2222 /* 2223 * Preset *DT exiting when emulating UMIP, so that vmx_set_cr4() 2224 * will not have to rewrite the controls just for this bit. 2225 */ 2226 if (!boot_cpu_has(X86_FEATURE_UMIP) && vmx_umip_emulated() && 2227 (vmcs12->guest_cr4 & X86_CR4_UMIP)) 2228 exec_control |= SECONDARY_EXEC_DESC; 2229 2230 if (exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) 2231 vmcs_write16(GUEST_INTR_STATUS, 2232 vmcs12->guest_intr_status); 2233 2234 secondary_exec_controls_set(vmx, exec_control); 2235 } 2236 2237 /* 2238 * ENTRY CONTROLS 2239 * 2240 * vmcs12's VM_{ENTRY,EXIT}_LOAD_IA32_EFER and VM_ENTRY_IA32E_MODE 2241 * are emulated by vmx_set_efer() in prepare_vmcs02(), but speculate 2242 * on the related bits (if supported by the CPU) in the hope that 2243 * we can avoid VMWrites during vmx_set_efer(). 2244 */ 2245 exec_control = (vmcs12->vm_entry_controls | vmx_vmentry_ctrl()) & 2246 ~VM_ENTRY_IA32E_MODE & ~VM_ENTRY_LOAD_IA32_EFER; 2247 if (cpu_has_load_ia32_efer()) { 2248 if (guest_efer & EFER_LMA) 2249 exec_control |= VM_ENTRY_IA32E_MODE; 2250 if (guest_efer != host_efer) 2251 exec_control |= VM_ENTRY_LOAD_IA32_EFER; 2252 } 2253 vm_entry_controls_set(vmx, exec_control); 2254 2255 /* 2256 * EXIT CONTROLS 2257 * 2258 * L2->L1 exit controls are emulated - the hardware exit is to L0 so 2259 * we should use its exit controls. Note that VM_EXIT_LOAD_IA32_EFER 2260 * bits may be modified by vmx_set_efer() in prepare_vmcs02(). 2261 */ 2262 exec_control = vmx_vmexit_ctrl(); 2263 if (cpu_has_load_ia32_efer() && guest_efer != host_efer) 2264 exec_control |= VM_EXIT_LOAD_IA32_EFER; 2265 vm_exit_controls_set(vmx, exec_control); 2266 2267 /* 2268 * Interrupt/Exception Fields 2269 */ 2270 if (vmx->nested.nested_run_pending) { 2271 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 2272 vmcs12->vm_entry_intr_info_field); 2273 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, 2274 vmcs12->vm_entry_exception_error_code); 2275 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 2276 vmcs12->vm_entry_instruction_len); 2277 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 2278 vmcs12->guest_interruptibility_info); 2279 vmx->loaded_vmcs->nmi_known_unmasked = 2280 !(vmcs12->guest_interruptibility_info & GUEST_INTR_STATE_NMI); 2281 } else { 2282 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); 2283 } 2284 } 2285 2286 static void prepare_vmcs02_rare(struct vcpu_vmx *vmx, struct vmcs12 *vmcs12) 2287 { 2288 struct hv_enlightened_vmcs *hv_evmcs = vmx->nested.hv_evmcs; 2289 2290 if (!hv_evmcs || !(hv_evmcs->hv_clean_fields & 2291 HV_VMX_ENLIGHTENED_CLEAN_FIELD_GUEST_GRP2)) { 2292 vmcs_write16(GUEST_ES_SELECTOR, vmcs12->guest_es_selector); 2293 vmcs_write16(GUEST_CS_SELECTOR, vmcs12->guest_cs_selector); 2294 vmcs_write16(GUEST_SS_SELECTOR, vmcs12->guest_ss_selector); 2295 vmcs_write16(GUEST_DS_SELECTOR, vmcs12->guest_ds_selector); 2296 vmcs_write16(GUEST_FS_SELECTOR, vmcs12->guest_fs_selector); 2297 vmcs_write16(GUEST_GS_SELECTOR, vmcs12->guest_gs_selector); 2298 vmcs_write16(GUEST_LDTR_SELECTOR, vmcs12->guest_ldtr_selector); 2299 vmcs_write16(GUEST_TR_SELECTOR, vmcs12->guest_tr_selector); 2300 vmcs_write32(GUEST_ES_LIMIT, vmcs12->guest_es_limit); 2301 vmcs_write32(GUEST_CS_LIMIT, vmcs12->guest_cs_limit); 2302 vmcs_write32(GUEST_SS_LIMIT, vmcs12->guest_ss_limit); 2303 vmcs_write32(GUEST_DS_LIMIT, vmcs12->guest_ds_limit); 2304 vmcs_write32(GUEST_FS_LIMIT, vmcs12->guest_fs_limit); 2305 vmcs_write32(GUEST_GS_LIMIT, vmcs12->guest_gs_limit); 2306 vmcs_write32(GUEST_LDTR_LIMIT, vmcs12->guest_ldtr_limit); 2307 vmcs_write32(GUEST_TR_LIMIT, vmcs12->guest_tr_limit); 2308 vmcs_write32(GUEST_GDTR_LIMIT, vmcs12->guest_gdtr_limit); 2309 vmcs_write32(GUEST_IDTR_LIMIT, vmcs12->guest_idtr_limit); 2310 vmcs_write32(GUEST_CS_AR_BYTES, vmcs12->guest_cs_ar_bytes); 2311 vmcs_write32(GUEST_SS_AR_BYTES, vmcs12->guest_ss_ar_bytes); 2312 vmcs_write32(GUEST_ES_AR_BYTES, vmcs12->guest_es_ar_bytes); 2313 vmcs_write32(GUEST_DS_AR_BYTES, vmcs12->guest_ds_ar_bytes); 2314 vmcs_write32(GUEST_FS_AR_BYTES, vmcs12->guest_fs_ar_bytes); 2315 vmcs_write32(GUEST_GS_AR_BYTES, vmcs12->guest_gs_ar_bytes); 2316 vmcs_write32(GUEST_LDTR_AR_BYTES, vmcs12->guest_ldtr_ar_bytes); 2317 vmcs_write32(GUEST_TR_AR_BYTES, vmcs12->guest_tr_ar_bytes); 2318 vmcs_writel(GUEST_ES_BASE, vmcs12->guest_es_base); 2319 vmcs_writel(GUEST_CS_BASE, vmcs12->guest_cs_base); 2320 vmcs_writel(GUEST_SS_BASE, vmcs12->guest_ss_base); 2321 vmcs_writel(GUEST_DS_BASE, vmcs12->guest_ds_base); 2322 vmcs_writel(GUEST_FS_BASE, vmcs12->guest_fs_base); 2323 vmcs_writel(GUEST_GS_BASE, vmcs12->guest_gs_base); 2324 vmcs_writel(GUEST_LDTR_BASE, vmcs12->guest_ldtr_base); 2325 vmcs_writel(GUEST_TR_BASE, vmcs12->guest_tr_base); 2326 vmcs_writel(GUEST_GDTR_BASE, vmcs12->guest_gdtr_base); 2327 vmcs_writel(GUEST_IDTR_BASE, vmcs12->guest_idtr_base); 2328 } 2329 2330 if (!hv_evmcs || !(hv_evmcs->hv_clean_fields & 2331 HV_VMX_ENLIGHTENED_CLEAN_FIELD_GUEST_GRP1)) { 2332 vmcs_write32(GUEST_SYSENTER_CS, vmcs12->guest_sysenter_cs); 2333 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS, 2334 vmcs12->guest_pending_dbg_exceptions); 2335 vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->guest_sysenter_esp); 2336 vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->guest_sysenter_eip); 2337 2338 /* 2339 * L1 may access the L2's PDPTR, so save them to construct 2340 * vmcs12 2341 */ 2342 if (enable_ept) { 2343 vmcs_write64(GUEST_PDPTR0, vmcs12->guest_pdptr0); 2344 vmcs_write64(GUEST_PDPTR1, vmcs12->guest_pdptr1); 2345 vmcs_write64(GUEST_PDPTR2, vmcs12->guest_pdptr2); 2346 vmcs_write64(GUEST_PDPTR3, vmcs12->guest_pdptr3); 2347 } 2348 2349 if (kvm_mpx_supported() && vmx->nested.nested_run_pending && 2350 (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_BNDCFGS)) 2351 vmcs_write64(GUEST_BNDCFGS, vmcs12->guest_bndcfgs); 2352 } 2353 2354 if (nested_cpu_has_xsaves(vmcs12)) 2355 vmcs_write64(XSS_EXIT_BITMAP, vmcs12->xss_exit_bitmap); 2356 2357 /* 2358 * Whether page-faults are trapped is determined by a combination of 2359 * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF. 2360 * If enable_ept, L0 doesn't care about page faults and we should 2361 * set all of these to L1's desires. However, if !enable_ept, L0 does 2362 * care about (at least some) page faults, and because it is not easy 2363 * (if at all possible?) to merge L0 and L1's desires, we simply ask 2364 * to exit on each and every L2 page fault. This is done by setting 2365 * MASK=MATCH=0 and (see below) EB.PF=1. 2366 * Note that below we don't need special code to set EB.PF beyond the 2367 * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept, 2368 * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when 2369 * !enable_ept, EB.PF is 1, so the "or" will always be 1. 2370 */ 2371 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 2372 enable_ept ? vmcs12->page_fault_error_code_mask : 0); 2373 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 2374 enable_ept ? vmcs12->page_fault_error_code_match : 0); 2375 2376 if (cpu_has_vmx_apicv()) { 2377 vmcs_write64(EOI_EXIT_BITMAP0, vmcs12->eoi_exit_bitmap0); 2378 vmcs_write64(EOI_EXIT_BITMAP1, vmcs12->eoi_exit_bitmap1); 2379 vmcs_write64(EOI_EXIT_BITMAP2, vmcs12->eoi_exit_bitmap2); 2380 vmcs_write64(EOI_EXIT_BITMAP3, vmcs12->eoi_exit_bitmap3); 2381 } 2382 2383 /* 2384 * Make sure the msr_autostore list is up to date before we set the 2385 * count in the vmcs02. 2386 */ 2387 prepare_vmx_msr_autostore_list(&vmx->vcpu, MSR_IA32_TSC); 2388 2389 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, vmx->msr_autostore.guest.nr); 2390 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, vmx->msr_autoload.host.nr); 2391 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, vmx->msr_autoload.guest.nr); 2392 2393 set_cr4_guest_host_mask(vmx); 2394 } 2395 2396 /* 2397 * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested 2398 * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it 2399 * with L0's requirements for its guest (a.k.a. vmcs01), so we can run the L2 2400 * guest in a way that will both be appropriate to L1's requests, and our 2401 * needs. In addition to modifying the active vmcs (which is vmcs02), this 2402 * function also has additional necessary side-effects, like setting various 2403 * vcpu->arch fields. 2404 * Returns 0 on success, 1 on failure. Invalid state exit qualification code 2405 * is assigned to entry_failure_code on failure. 2406 */ 2407 static int prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12, 2408 u32 *entry_failure_code) 2409 { 2410 struct vcpu_vmx *vmx = to_vmx(vcpu); 2411 struct hv_enlightened_vmcs *hv_evmcs = vmx->nested.hv_evmcs; 2412 bool load_guest_pdptrs_vmcs12 = false; 2413 2414 if (vmx->nested.dirty_vmcs12 || hv_evmcs) { 2415 prepare_vmcs02_rare(vmx, vmcs12); 2416 vmx->nested.dirty_vmcs12 = false; 2417 2418 load_guest_pdptrs_vmcs12 = !hv_evmcs || 2419 !(hv_evmcs->hv_clean_fields & 2420 HV_VMX_ENLIGHTENED_CLEAN_FIELD_GUEST_GRP1); 2421 } 2422 2423 if (vmx->nested.nested_run_pending && 2424 (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS)) { 2425 kvm_set_dr(vcpu, 7, vmcs12->guest_dr7); 2426 vmcs_write64(GUEST_IA32_DEBUGCTL, vmcs12->guest_ia32_debugctl); 2427 } else { 2428 kvm_set_dr(vcpu, 7, vcpu->arch.dr7); 2429 vmcs_write64(GUEST_IA32_DEBUGCTL, vmx->nested.vmcs01_debugctl); 2430 } 2431 if (kvm_mpx_supported() && (!vmx->nested.nested_run_pending || 2432 !(vmcs12->vm_entry_controls & VM_ENTRY_LOAD_BNDCFGS))) 2433 vmcs_write64(GUEST_BNDCFGS, vmx->nested.vmcs01_guest_bndcfgs); 2434 vmx_set_rflags(vcpu, vmcs12->guest_rflags); 2435 2436 /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the 2437 * bitwise-or of what L1 wants to trap for L2, and what we want to 2438 * trap. Note that CR0.TS also needs updating - we do this later. 2439 */ 2440 update_exception_bitmap(vcpu); 2441 vcpu->arch.cr0_guest_owned_bits &= ~vmcs12->cr0_guest_host_mask; 2442 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits); 2443 2444 if (vmx->nested.nested_run_pending && 2445 (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PAT)) { 2446 vmcs_write64(GUEST_IA32_PAT, vmcs12->guest_ia32_pat); 2447 vcpu->arch.pat = vmcs12->guest_ia32_pat; 2448 } else if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) { 2449 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat); 2450 } 2451 2452 vmcs_write64(TSC_OFFSET, vcpu->arch.tsc_offset); 2453 2454 if (kvm_has_tsc_control) 2455 decache_tsc_multiplier(vmx); 2456 2457 if (enable_vpid) { 2458 /* 2459 * There is no direct mapping between vpid02 and vpid12, the 2460 * vpid02 is per-vCPU for L0 and reused while the value of 2461 * vpid12 is changed w/ one invvpid during nested vmentry. 2462 * The vpid12 is allocated by L1 for L2, so it will not 2463 * influence global bitmap(for vpid01 and vpid02 allocation) 2464 * even if spawn a lot of nested vCPUs. 2465 */ 2466 if (nested_cpu_has_vpid(vmcs12) && nested_has_guest_tlb_tag(vcpu)) { 2467 if (vmcs12->virtual_processor_id != vmx->nested.last_vpid) { 2468 vmx->nested.last_vpid = vmcs12->virtual_processor_id; 2469 __vmx_flush_tlb(vcpu, nested_get_vpid02(vcpu), false); 2470 } 2471 } else { 2472 /* 2473 * If L1 use EPT, then L0 needs to execute INVEPT on 2474 * EPTP02 instead of EPTP01. Therefore, delay TLB 2475 * flush until vmcs02->eptp is fully updated by 2476 * KVM_REQ_LOAD_CR3. Note that this assumes 2477 * KVM_REQ_TLB_FLUSH is evaluated after 2478 * KVM_REQ_LOAD_CR3 in vcpu_enter_guest(). 2479 */ 2480 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu); 2481 } 2482 } 2483 2484 if (nested_cpu_has_ept(vmcs12)) 2485 nested_ept_init_mmu_context(vcpu); 2486 2487 /* 2488 * This sets GUEST_CR0 to vmcs12->guest_cr0, possibly modifying those 2489 * bits which we consider mandatory enabled. 2490 * The CR0_READ_SHADOW is what L2 should have expected to read given 2491 * the specifications by L1; It's not enough to take 2492 * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we 2493 * have more bits than L1 expected. 2494 */ 2495 vmx_set_cr0(vcpu, vmcs12->guest_cr0); 2496 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12)); 2497 2498 vmx_set_cr4(vcpu, vmcs12->guest_cr4); 2499 vmcs_writel(CR4_READ_SHADOW, nested_read_cr4(vmcs12)); 2500 2501 vcpu->arch.efer = nested_vmx_calc_efer(vmx, vmcs12); 2502 /* Note: may modify VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */ 2503 vmx_set_efer(vcpu, vcpu->arch.efer); 2504 2505 /* 2506 * Guest state is invalid and unrestricted guest is disabled, 2507 * which means L1 attempted VMEntry to L2 with invalid state. 2508 * Fail the VMEntry. 2509 */ 2510 if (vmx->emulation_required) { 2511 *entry_failure_code = ENTRY_FAIL_DEFAULT; 2512 return -EINVAL; 2513 } 2514 2515 /* Shadow page tables on either EPT or shadow page tables. */ 2516 if (nested_vmx_load_cr3(vcpu, vmcs12->guest_cr3, nested_cpu_has_ept(vmcs12), 2517 entry_failure_code)) 2518 return -EINVAL; 2519 2520 /* 2521 * Immediately write vmcs02.GUEST_CR3. It will be propagated to vmcs12 2522 * on nested VM-Exit, which can occur without actually running L2 and 2523 * thus without hitting vmx_set_cr3(), e.g. if L1 is entering L2 with 2524 * vmcs12.GUEST_ACTIVITYSTATE=HLT, in which case KVM will intercept the 2525 * transition to HLT instead of running L2. 2526 */ 2527 if (enable_ept) 2528 vmcs_writel(GUEST_CR3, vmcs12->guest_cr3); 2529 2530 /* Late preparation of GUEST_PDPTRs now that EFER and CRs are set. */ 2531 if (load_guest_pdptrs_vmcs12 && nested_cpu_has_ept(vmcs12) && 2532 is_pae_paging(vcpu)) { 2533 vmcs_write64(GUEST_PDPTR0, vmcs12->guest_pdptr0); 2534 vmcs_write64(GUEST_PDPTR1, vmcs12->guest_pdptr1); 2535 vmcs_write64(GUEST_PDPTR2, vmcs12->guest_pdptr2); 2536 vmcs_write64(GUEST_PDPTR3, vmcs12->guest_pdptr3); 2537 } 2538 2539 if (!enable_ept) 2540 vcpu->arch.walk_mmu->inject_page_fault = vmx_inject_page_fault_nested; 2541 2542 if ((vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL) && 2543 WARN_ON_ONCE(kvm_set_msr(vcpu, MSR_CORE_PERF_GLOBAL_CTRL, 2544 vmcs12->guest_ia32_perf_global_ctrl))) 2545 return -EINVAL; 2546 2547 kvm_rsp_write(vcpu, vmcs12->guest_rsp); 2548 kvm_rip_write(vcpu, vmcs12->guest_rip); 2549 return 0; 2550 } 2551 2552 static int nested_vmx_check_nmi_controls(struct vmcs12 *vmcs12) 2553 { 2554 if (CC(!nested_cpu_has_nmi_exiting(vmcs12) && 2555 nested_cpu_has_virtual_nmis(vmcs12))) 2556 return -EINVAL; 2557 2558 if (CC(!nested_cpu_has_virtual_nmis(vmcs12) && 2559 nested_cpu_has(vmcs12, CPU_BASED_NMI_WINDOW_EXITING))) 2560 return -EINVAL; 2561 2562 return 0; 2563 } 2564 2565 static bool valid_ept_address(struct kvm_vcpu *vcpu, u64 address) 2566 { 2567 struct vcpu_vmx *vmx = to_vmx(vcpu); 2568 int maxphyaddr = cpuid_maxphyaddr(vcpu); 2569 2570 /* Check for memory type validity */ 2571 switch (address & VMX_EPTP_MT_MASK) { 2572 case VMX_EPTP_MT_UC: 2573 if (CC(!(vmx->nested.msrs.ept_caps & VMX_EPTP_UC_BIT))) 2574 return false; 2575 break; 2576 case VMX_EPTP_MT_WB: 2577 if (CC(!(vmx->nested.msrs.ept_caps & VMX_EPTP_WB_BIT))) 2578 return false; 2579 break; 2580 default: 2581 return false; 2582 } 2583 2584 /* only 4 levels page-walk length are valid */ 2585 if (CC((address & VMX_EPTP_PWL_MASK) != VMX_EPTP_PWL_4)) 2586 return false; 2587 2588 /* Reserved bits should not be set */ 2589 if (CC(address >> maxphyaddr || ((address >> 7) & 0x1f))) 2590 return false; 2591 2592 /* AD, if set, should be supported */ 2593 if (address & VMX_EPTP_AD_ENABLE_BIT) { 2594 if (CC(!(vmx->nested.msrs.ept_caps & VMX_EPT_AD_BIT))) 2595 return false; 2596 } 2597 2598 return true; 2599 } 2600 2601 /* 2602 * Checks related to VM-Execution Control Fields 2603 */ 2604 static int nested_check_vm_execution_controls(struct kvm_vcpu *vcpu, 2605 struct vmcs12 *vmcs12) 2606 { 2607 struct vcpu_vmx *vmx = to_vmx(vcpu); 2608 2609 if (CC(!vmx_control_verify(vmcs12->pin_based_vm_exec_control, 2610 vmx->nested.msrs.pinbased_ctls_low, 2611 vmx->nested.msrs.pinbased_ctls_high)) || 2612 CC(!vmx_control_verify(vmcs12->cpu_based_vm_exec_control, 2613 vmx->nested.msrs.procbased_ctls_low, 2614 vmx->nested.msrs.procbased_ctls_high))) 2615 return -EINVAL; 2616 2617 if (nested_cpu_has(vmcs12, CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) && 2618 CC(!vmx_control_verify(vmcs12->secondary_vm_exec_control, 2619 vmx->nested.msrs.secondary_ctls_low, 2620 vmx->nested.msrs.secondary_ctls_high))) 2621 return -EINVAL; 2622 2623 if (CC(vmcs12->cr3_target_count > nested_cpu_vmx_misc_cr3_count(vcpu)) || 2624 nested_vmx_check_io_bitmap_controls(vcpu, vmcs12) || 2625 nested_vmx_check_msr_bitmap_controls(vcpu, vmcs12) || 2626 nested_vmx_check_tpr_shadow_controls(vcpu, vmcs12) || 2627 nested_vmx_check_apic_access_controls(vcpu, vmcs12) || 2628 nested_vmx_check_apicv_controls(vcpu, vmcs12) || 2629 nested_vmx_check_nmi_controls(vmcs12) || 2630 nested_vmx_check_pml_controls(vcpu, vmcs12) || 2631 nested_vmx_check_unrestricted_guest_controls(vcpu, vmcs12) || 2632 nested_vmx_check_mode_based_ept_exec_controls(vcpu, vmcs12) || 2633 nested_vmx_check_shadow_vmcs_controls(vcpu, vmcs12) || 2634 CC(nested_cpu_has_vpid(vmcs12) && !vmcs12->virtual_processor_id)) 2635 return -EINVAL; 2636 2637 if (!nested_cpu_has_preemption_timer(vmcs12) && 2638 nested_cpu_has_save_preemption_timer(vmcs12)) 2639 return -EINVAL; 2640 2641 if (nested_cpu_has_ept(vmcs12) && 2642 CC(!valid_ept_address(vcpu, vmcs12->ept_pointer))) 2643 return -EINVAL; 2644 2645 if (nested_cpu_has_vmfunc(vmcs12)) { 2646 if (CC(vmcs12->vm_function_control & 2647 ~vmx->nested.msrs.vmfunc_controls)) 2648 return -EINVAL; 2649 2650 if (nested_cpu_has_eptp_switching(vmcs12)) { 2651 if (CC(!nested_cpu_has_ept(vmcs12)) || 2652 CC(!page_address_valid(vcpu, vmcs12->eptp_list_address))) 2653 return -EINVAL; 2654 } 2655 } 2656 2657 return 0; 2658 } 2659 2660 /* 2661 * Checks related to VM-Exit Control Fields 2662 */ 2663 static int nested_check_vm_exit_controls(struct kvm_vcpu *vcpu, 2664 struct vmcs12 *vmcs12) 2665 { 2666 struct vcpu_vmx *vmx = to_vmx(vcpu); 2667 2668 if (CC(!vmx_control_verify(vmcs12->vm_exit_controls, 2669 vmx->nested.msrs.exit_ctls_low, 2670 vmx->nested.msrs.exit_ctls_high)) || 2671 CC(nested_vmx_check_exit_msr_switch_controls(vcpu, vmcs12))) 2672 return -EINVAL; 2673 2674 return 0; 2675 } 2676 2677 /* 2678 * Checks related to VM-Entry Control Fields 2679 */ 2680 static int nested_check_vm_entry_controls(struct kvm_vcpu *vcpu, 2681 struct vmcs12 *vmcs12) 2682 { 2683 struct vcpu_vmx *vmx = to_vmx(vcpu); 2684 2685 if (CC(!vmx_control_verify(vmcs12->vm_entry_controls, 2686 vmx->nested.msrs.entry_ctls_low, 2687 vmx->nested.msrs.entry_ctls_high))) 2688 return -EINVAL; 2689 2690 /* 2691 * From the Intel SDM, volume 3: 2692 * Fields relevant to VM-entry event injection must be set properly. 2693 * These fields are the VM-entry interruption-information field, the 2694 * VM-entry exception error code, and the VM-entry instruction length. 2695 */ 2696 if (vmcs12->vm_entry_intr_info_field & INTR_INFO_VALID_MASK) { 2697 u32 intr_info = vmcs12->vm_entry_intr_info_field; 2698 u8 vector = intr_info & INTR_INFO_VECTOR_MASK; 2699 u32 intr_type = intr_info & INTR_INFO_INTR_TYPE_MASK; 2700 bool has_error_code = intr_info & INTR_INFO_DELIVER_CODE_MASK; 2701 bool should_have_error_code; 2702 bool urg = nested_cpu_has2(vmcs12, 2703 SECONDARY_EXEC_UNRESTRICTED_GUEST); 2704 bool prot_mode = !urg || vmcs12->guest_cr0 & X86_CR0_PE; 2705 2706 /* VM-entry interruption-info field: interruption type */ 2707 if (CC(intr_type == INTR_TYPE_RESERVED) || 2708 CC(intr_type == INTR_TYPE_OTHER_EVENT && 2709 !nested_cpu_supports_monitor_trap_flag(vcpu))) 2710 return -EINVAL; 2711 2712 /* VM-entry interruption-info field: vector */ 2713 if (CC(intr_type == INTR_TYPE_NMI_INTR && vector != NMI_VECTOR) || 2714 CC(intr_type == INTR_TYPE_HARD_EXCEPTION && vector > 31) || 2715 CC(intr_type == INTR_TYPE_OTHER_EVENT && vector != 0)) 2716 return -EINVAL; 2717 2718 /* VM-entry interruption-info field: deliver error code */ 2719 should_have_error_code = 2720 intr_type == INTR_TYPE_HARD_EXCEPTION && prot_mode && 2721 x86_exception_has_error_code(vector); 2722 if (CC(has_error_code != should_have_error_code)) 2723 return -EINVAL; 2724 2725 /* VM-entry exception error code */ 2726 if (CC(has_error_code && 2727 vmcs12->vm_entry_exception_error_code & GENMASK(31, 16))) 2728 return -EINVAL; 2729 2730 /* VM-entry interruption-info field: reserved bits */ 2731 if (CC(intr_info & INTR_INFO_RESVD_BITS_MASK)) 2732 return -EINVAL; 2733 2734 /* VM-entry instruction length */ 2735 switch (intr_type) { 2736 case INTR_TYPE_SOFT_EXCEPTION: 2737 case INTR_TYPE_SOFT_INTR: 2738 case INTR_TYPE_PRIV_SW_EXCEPTION: 2739 if (CC(vmcs12->vm_entry_instruction_len > 15) || 2740 CC(vmcs12->vm_entry_instruction_len == 0 && 2741 CC(!nested_cpu_has_zero_length_injection(vcpu)))) 2742 return -EINVAL; 2743 } 2744 } 2745 2746 if (nested_vmx_check_entry_msr_switch_controls(vcpu, vmcs12)) 2747 return -EINVAL; 2748 2749 return 0; 2750 } 2751 2752 static int nested_vmx_check_controls(struct kvm_vcpu *vcpu, 2753 struct vmcs12 *vmcs12) 2754 { 2755 if (nested_check_vm_execution_controls(vcpu, vmcs12) || 2756 nested_check_vm_exit_controls(vcpu, vmcs12) || 2757 nested_check_vm_entry_controls(vcpu, vmcs12)) 2758 return -EINVAL; 2759 2760 return 0; 2761 } 2762 2763 static int nested_vmx_check_host_state(struct kvm_vcpu *vcpu, 2764 struct vmcs12 *vmcs12) 2765 { 2766 bool ia32e; 2767 2768 if (CC(!nested_host_cr0_valid(vcpu, vmcs12->host_cr0)) || 2769 CC(!nested_host_cr4_valid(vcpu, vmcs12->host_cr4)) || 2770 CC(!nested_cr3_valid(vcpu, vmcs12->host_cr3))) 2771 return -EINVAL; 2772 2773 if (CC(is_noncanonical_address(vmcs12->host_ia32_sysenter_esp, vcpu)) || 2774 CC(is_noncanonical_address(vmcs12->host_ia32_sysenter_eip, vcpu))) 2775 return -EINVAL; 2776 2777 if ((vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PAT) && 2778 CC(!kvm_pat_valid(vmcs12->host_ia32_pat))) 2779 return -EINVAL; 2780 2781 if ((vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL) && 2782 CC(!kvm_valid_perf_global_ctrl(vcpu_to_pmu(vcpu), 2783 vmcs12->host_ia32_perf_global_ctrl))) 2784 return -EINVAL; 2785 2786 #ifdef CONFIG_X86_64 2787 ia32e = !!(vcpu->arch.efer & EFER_LMA); 2788 #else 2789 ia32e = false; 2790 #endif 2791 2792 if (ia32e) { 2793 if (CC(!(vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)) || 2794 CC(!(vmcs12->host_cr4 & X86_CR4_PAE))) 2795 return -EINVAL; 2796 } else { 2797 if (CC(vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE) || 2798 CC(vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE) || 2799 CC(vmcs12->host_cr4 & X86_CR4_PCIDE) || 2800 CC((vmcs12->host_rip) >> 32)) 2801 return -EINVAL; 2802 } 2803 2804 if (CC(vmcs12->host_cs_selector & (SEGMENT_RPL_MASK | SEGMENT_TI_MASK)) || 2805 CC(vmcs12->host_ss_selector & (SEGMENT_RPL_MASK | SEGMENT_TI_MASK)) || 2806 CC(vmcs12->host_ds_selector & (SEGMENT_RPL_MASK | SEGMENT_TI_MASK)) || 2807 CC(vmcs12->host_es_selector & (SEGMENT_RPL_MASK | SEGMENT_TI_MASK)) || 2808 CC(vmcs12->host_fs_selector & (SEGMENT_RPL_MASK | SEGMENT_TI_MASK)) || 2809 CC(vmcs12->host_gs_selector & (SEGMENT_RPL_MASK | SEGMENT_TI_MASK)) || 2810 CC(vmcs12->host_tr_selector & (SEGMENT_RPL_MASK | SEGMENT_TI_MASK)) || 2811 CC(vmcs12->host_cs_selector == 0) || 2812 CC(vmcs12->host_tr_selector == 0) || 2813 CC(vmcs12->host_ss_selector == 0 && !ia32e)) 2814 return -EINVAL; 2815 2816 if (CC(is_noncanonical_address(vmcs12->host_fs_base, vcpu)) || 2817 CC(is_noncanonical_address(vmcs12->host_gs_base, vcpu)) || 2818 CC(is_noncanonical_address(vmcs12->host_gdtr_base, vcpu)) || 2819 CC(is_noncanonical_address(vmcs12->host_idtr_base, vcpu)) || 2820 CC(is_noncanonical_address(vmcs12->host_tr_base, vcpu)) || 2821 CC(is_noncanonical_address(vmcs12->host_rip, vcpu))) 2822 return -EINVAL; 2823 2824 /* 2825 * If the load IA32_EFER VM-exit control is 1, bits reserved in the 2826 * IA32_EFER MSR must be 0 in the field for that register. In addition, 2827 * the values of the LMA and LME bits in the field must each be that of 2828 * the host address-space size VM-exit control. 2829 */ 2830 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER) { 2831 if (CC(!kvm_valid_efer(vcpu, vmcs12->host_ia32_efer)) || 2832 CC(ia32e != !!(vmcs12->host_ia32_efer & EFER_LMA)) || 2833 CC(ia32e != !!(vmcs12->host_ia32_efer & EFER_LME))) 2834 return -EINVAL; 2835 } 2836 2837 return 0; 2838 } 2839 2840 static int nested_vmx_check_vmcs_link_ptr(struct kvm_vcpu *vcpu, 2841 struct vmcs12 *vmcs12) 2842 { 2843 int r = 0; 2844 struct vmcs12 *shadow; 2845 struct kvm_host_map map; 2846 2847 if (vmcs12->vmcs_link_pointer == -1ull) 2848 return 0; 2849 2850 if (CC(!page_address_valid(vcpu, vmcs12->vmcs_link_pointer))) 2851 return -EINVAL; 2852 2853 if (CC(kvm_vcpu_map(vcpu, gpa_to_gfn(vmcs12->vmcs_link_pointer), &map))) 2854 return -EINVAL; 2855 2856 shadow = map.hva; 2857 2858 if (CC(shadow->hdr.revision_id != VMCS12_REVISION) || 2859 CC(shadow->hdr.shadow_vmcs != nested_cpu_has_shadow_vmcs(vmcs12))) 2860 r = -EINVAL; 2861 2862 kvm_vcpu_unmap(vcpu, &map, false); 2863 return r; 2864 } 2865 2866 /* 2867 * Checks related to Guest Non-register State 2868 */ 2869 static int nested_check_guest_non_reg_state(struct vmcs12 *vmcs12) 2870 { 2871 if (CC(vmcs12->guest_activity_state != GUEST_ACTIVITY_ACTIVE && 2872 vmcs12->guest_activity_state != GUEST_ACTIVITY_HLT)) 2873 return -EINVAL; 2874 2875 return 0; 2876 } 2877 2878 static int nested_vmx_check_guest_state(struct kvm_vcpu *vcpu, 2879 struct vmcs12 *vmcs12, 2880 u32 *exit_qual) 2881 { 2882 bool ia32e; 2883 2884 *exit_qual = ENTRY_FAIL_DEFAULT; 2885 2886 if (CC(!nested_guest_cr0_valid(vcpu, vmcs12->guest_cr0)) || 2887 CC(!nested_guest_cr4_valid(vcpu, vmcs12->guest_cr4))) 2888 return -EINVAL; 2889 2890 if ((vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS) && 2891 CC(!kvm_dr7_valid(vmcs12->guest_dr7))) 2892 return -EINVAL; 2893 2894 if ((vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PAT) && 2895 CC(!kvm_pat_valid(vmcs12->guest_ia32_pat))) 2896 return -EINVAL; 2897 2898 if (nested_vmx_check_vmcs_link_ptr(vcpu, vmcs12)) { 2899 *exit_qual = ENTRY_FAIL_VMCS_LINK_PTR; 2900 return -EINVAL; 2901 } 2902 2903 if ((vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL) && 2904 CC(!kvm_valid_perf_global_ctrl(vcpu_to_pmu(vcpu), 2905 vmcs12->guest_ia32_perf_global_ctrl))) 2906 return -EINVAL; 2907 2908 /* 2909 * If the load IA32_EFER VM-entry control is 1, the following checks 2910 * are performed on the field for the IA32_EFER MSR: 2911 * - Bits reserved in the IA32_EFER MSR must be 0. 2912 * - Bit 10 (corresponding to IA32_EFER.LMA) must equal the value of 2913 * the IA-32e mode guest VM-exit control. It must also be identical 2914 * to bit 8 (LME) if bit 31 in the CR0 field (corresponding to 2915 * CR0.PG) is 1. 2916 */ 2917 if (to_vmx(vcpu)->nested.nested_run_pending && 2918 (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER)) { 2919 ia32e = (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE) != 0; 2920 if (CC(!kvm_valid_efer(vcpu, vmcs12->guest_ia32_efer)) || 2921 CC(ia32e != !!(vmcs12->guest_ia32_efer & EFER_LMA)) || 2922 CC(((vmcs12->guest_cr0 & X86_CR0_PG) && 2923 ia32e != !!(vmcs12->guest_ia32_efer & EFER_LME)))) 2924 return -EINVAL; 2925 } 2926 2927 if ((vmcs12->vm_entry_controls & VM_ENTRY_LOAD_BNDCFGS) && 2928 (CC(is_noncanonical_address(vmcs12->guest_bndcfgs & PAGE_MASK, vcpu)) || 2929 CC((vmcs12->guest_bndcfgs & MSR_IA32_BNDCFGS_RSVD)))) 2930 return -EINVAL; 2931 2932 if (nested_check_guest_non_reg_state(vmcs12)) 2933 return -EINVAL; 2934 2935 return 0; 2936 } 2937 2938 static int nested_vmx_check_vmentry_hw(struct kvm_vcpu *vcpu) 2939 { 2940 struct vcpu_vmx *vmx = to_vmx(vcpu); 2941 unsigned long cr3, cr4; 2942 bool vm_fail; 2943 2944 if (!nested_early_check) 2945 return 0; 2946 2947 if (vmx->msr_autoload.host.nr) 2948 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0); 2949 if (vmx->msr_autoload.guest.nr) 2950 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0); 2951 2952 preempt_disable(); 2953 2954 vmx_prepare_switch_to_guest(vcpu); 2955 2956 /* 2957 * Induce a consistency check VMExit by clearing bit 1 in GUEST_RFLAGS, 2958 * which is reserved to '1' by hardware. GUEST_RFLAGS is guaranteed to 2959 * be written (by preparve_vmcs02()) before the "real" VMEnter, i.e. 2960 * there is no need to preserve other bits or save/restore the field. 2961 */ 2962 vmcs_writel(GUEST_RFLAGS, 0); 2963 2964 cr3 = __get_current_cr3_fast(); 2965 if (unlikely(cr3 != vmx->loaded_vmcs->host_state.cr3)) { 2966 vmcs_writel(HOST_CR3, cr3); 2967 vmx->loaded_vmcs->host_state.cr3 = cr3; 2968 } 2969 2970 cr4 = cr4_read_shadow(); 2971 if (unlikely(cr4 != vmx->loaded_vmcs->host_state.cr4)) { 2972 vmcs_writel(HOST_CR4, cr4); 2973 vmx->loaded_vmcs->host_state.cr4 = cr4; 2974 } 2975 2976 asm( 2977 "sub $%c[wordsize], %%" _ASM_SP "\n\t" /* temporarily adjust RSP for CALL */ 2978 "cmp %%" _ASM_SP ", %c[host_state_rsp](%[loaded_vmcs]) \n\t" 2979 "je 1f \n\t" 2980 __ex("vmwrite %%" _ASM_SP ", %[HOST_RSP]") "\n\t" 2981 "mov %%" _ASM_SP ", %c[host_state_rsp](%[loaded_vmcs]) \n\t" 2982 "1: \n\t" 2983 "add $%c[wordsize], %%" _ASM_SP "\n\t" /* un-adjust RSP */ 2984 2985 /* Check if vmlaunch or vmresume is needed */ 2986 "cmpb $0, %c[launched](%[loaded_vmcs])\n\t" 2987 2988 /* 2989 * VMLAUNCH and VMRESUME clear RFLAGS.{CF,ZF} on VM-Exit, set 2990 * RFLAGS.CF on VM-Fail Invalid and set RFLAGS.ZF on VM-Fail 2991 * Valid. vmx_vmenter() directly "returns" RFLAGS, and so the 2992 * results of VM-Enter is captured via CC_{SET,OUT} to vm_fail. 2993 */ 2994 "call vmx_vmenter\n\t" 2995 2996 CC_SET(be) 2997 : ASM_CALL_CONSTRAINT, CC_OUT(be) (vm_fail) 2998 : [HOST_RSP]"r"((unsigned long)HOST_RSP), 2999 [loaded_vmcs]"r"(vmx->loaded_vmcs), 3000 [launched]"i"(offsetof(struct loaded_vmcs, launched)), 3001 [host_state_rsp]"i"(offsetof(struct loaded_vmcs, host_state.rsp)), 3002 [wordsize]"i"(sizeof(ulong)) 3003 : "memory" 3004 ); 3005 3006 if (vmx->msr_autoload.host.nr) 3007 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, vmx->msr_autoload.host.nr); 3008 if (vmx->msr_autoload.guest.nr) 3009 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, vmx->msr_autoload.guest.nr); 3010 3011 if (vm_fail) { 3012 u32 error = vmcs_read32(VM_INSTRUCTION_ERROR); 3013 3014 preempt_enable(); 3015 3016 trace_kvm_nested_vmenter_failed( 3017 "early hardware check VM-instruction error: ", error); 3018 WARN_ON_ONCE(error != VMXERR_ENTRY_INVALID_CONTROL_FIELD); 3019 return 1; 3020 } 3021 3022 /* 3023 * VMExit clears RFLAGS.IF and DR7, even on a consistency check. 3024 */ 3025 local_irq_enable(); 3026 if (hw_breakpoint_active()) 3027 set_debugreg(__this_cpu_read(cpu_dr7), 7); 3028 preempt_enable(); 3029 3030 /* 3031 * A non-failing VMEntry means we somehow entered guest mode with 3032 * an illegal RIP, and that's just the tip of the iceberg. There 3033 * is no telling what memory has been modified or what state has 3034 * been exposed to unknown code. Hitting this all but guarantees 3035 * a (very critical) hardware issue. 3036 */ 3037 WARN_ON(!(vmcs_read32(VM_EXIT_REASON) & 3038 VMX_EXIT_REASONS_FAILED_VMENTRY)); 3039 3040 return 0; 3041 } 3042 3043 static bool nested_get_vmcs12_pages(struct kvm_vcpu *vcpu) 3044 { 3045 struct vmcs12 *vmcs12 = get_vmcs12(vcpu); 3046 struct vcpu_vmx *vmx = to_vmx(vcpu); 3047 struct kvm_host_map *map; 3048 struct page *page; 3049 u64 hpa; 3050 3051 if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) { 3052 /* 3053 * Translate L1 physical address to host physical 3054 * address for vmcs02. Keep the page pinned, so this 3055 * physical address remains valid. We keep a reference 3056 * to it so we can release it later. 3057 */ 3058 if (vmx->nested.apic_access_page) { /* shouldn't happen */ 3059 kvm_release_page_clean(vmx->nested.apic_access_page); 3060 vmx->nested.apic_access_page = NULL; 3061 } 3062 page = kvm_vcpu_gpa_to_page(vcpu, vmcs12->apic_access_addr); 3063 if (!is_error_page(page)) { 3064 vmx->nested.apic_access_page = page; 3065 hpa = page_to_phys(vmx->nested.apic_access_page); 3066 vmcs_write64(APIC_ACCESS_ADDR, hpa); 3067 } else { 3068 pr_debug_ratelimited("%s: no backing 'struct page' for APIC-access address in vmcs12\n", 3069 __func__); 3070 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR; 3071 vcpu->run->internal.suberror = 3072 KVM_INTERNAL_ERROR_EMULATION; 3073 vcpu->run->internal.ndata = 0; 3074 return false; 3075 } 3076 } 3077 3078 if (nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW)) { 3079 map = &vmx->nested.virtual_apic_map; 3080 3081 if (!kvm_vcpu_map(vcpu, gpa_to_gfn(vmcs12->virtual_apic_page_addr), map)) { 3082 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, pfn_to_hpa(map->pfn)); 3083 } else if (nested_cpu_has(vmcs12, CPU_BASED_CR8_LOAD_EXITING) && 3084 nested_cpu_has(vmcs12, CPU_BASED_CR8_STORE_EXITING) && 3085 !nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) { 3086 /* 3087 * The processor will never use the TPR shadow, simply 3088 * clear the bit from the execution control. Such a 3089 * configuration is useless, but it happens in tests. 3090 * For any other configuration, failing the vm entry is 3091 * _not_ what the processor does but it's basically the 3092 * only possibility we have. 3093 */ 3094 exec_controls_clearbit(vmx, CPU_BASED_TPR_SHADOW); 3095 } else { 3096 /* 3097 * Write an illegal value to VIRTUAL_APIC_PAGE_ADDR to 3098 * force VM-Entry to fail. 3099 */ 3100 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, -1ull); 3101 } 3102 } 3103 3104 if (nested_cpu_has_posted_intr(vmcs12)) { 3105 map = &vmx->nested.pi_desc_map; 3106 3107 if (!kvm_vcpu_map(vcpu, gpa_to_gfn(vmcs12->posted_intr_desc_addr), map)) { 3108 vmx->nested.pi_desc = 3109 (struct pi_desc *)(((void *)map->hva) + 3110 offset_in_page(vmcs12->posted_intr_desc_addr)); 3111 vmcs_write64(POSTED_INTR_DESC_ADDR, 3112 pfn_to_hpa(map->pfn) + offset_in_page(vmcs12->posted_intr_desc_addr)); 3113 } 3114 } 3115 if (nested_vmx_prepare_msr_bitmap(vcpu, vmcs12)) 3116 exec_controls_setbit(vmx, CPU_BASED_USE_MSR_BITMAPS); 3117 else 3118 exec_controls_clearbit(vmx, CPU_BASED_USE_MSR_BITMAPS); 3119 return true; 3120 } 3121 3122 /* 3123 * Intel's VMX Instruction Reference specifies a common set of prerequisites 3124 * for running VMX instructions (except VMXON, whose prerequisites are 3125 * slightly different). It also specifies what exception to inject otherwise. 3126 * Note that many of these exceptions have priority over VM exits, so they 3127 * don't have to be checked again here. 3128 */ 3129 static int nested_vmx_check_permission(struct kvm_vcpu *vcpu) 3130 { 3131 if (!to_vmx(vcpu)->nested.vmxon) { 3132 kvm_queue_exception(vcpu, UD_VECTOR); 3133 return 0; 3134 } 3135 3136 if (vmx_get_cpl(vcpu)) { 3137 kvm_inject_gp(vcpu, 0); 3138 return 0; 3139 } 3140 3141 return 1; 3142 } 3143 3144 static u8 vmx_has_apicv_interrupt(struct kvm_vcpu *vcpu) 3145 { 3146 u8 rvi = vmx_get_rvi(); 3147 u8 vppr = kvm_lapic_get_reg(vcpu->arch.apic, APIC_PROCPRI); 3148 3149 return ((rvi & 0xf0) > (vppr & 0xf0)); 3150 } 3151 3152 static void load_vmcs12_host_state(struct kvm_vcpu *vcpu, 3153 struct vmcs12 *vmcs12); 3154 3155 /* 3156 * If from_vmentry is false, this is being called from state restore (either RSM 3157 * or KVM_SET_NESTED_STATE). Otherwise it's called from vmlaunch/vmresume. 3158 * 3159 * Returns: 3160 * NVMX_ENTRY_SUCCESS: Entered VMX non-root mode 3161 * NVMX_ENTRY_VMFAIL: Consistency check VMFail 3162 * NVMX_ENTRY_VMEXIT: Consistency check VMExit 3163 * NVMX_ENTRY_KVM_INTERNAL_ERROR: KVM internal error 3164 */ 3165 enum nvmx_vmentry_status nested_vmx_enter_non_root_mode(struct kvm_vcpu *vcpu, 3166 bool from_vmentry) 3167 { 3168 struct vcpu_vmx *vmx = to_vmx(vcpu); 3169 struct vmcs12 *vmcs12 = get_vmcs12(vcpu); 3170 bool evaluate_pending_interrupts; 3171 u32 exit_reason = EXIT_REASON_INVALID_STATE; 3172 u32 exit_qual; 3173 3174 evaluate_pending_interrupts = exec_controls_get(vmx) & 3175 (CPU_BASED_INTR_WINDOW_EXITING | CPU_BASED_NMI_WINDOW_EXITING); 3176 if (likely(!evaluate_pending_interrupts) && kvm_vcpu_apicv_active(vcpu)) 3177 evaluate_pending_interrupts |= vmx_has_apicv_interrupt(vcpu); 3178 3179 if (!(vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS)) 3180 vmx->nested.vmcs01_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL); 3181 if (kvm_mpx_supported() && 3182 !(vmcs12->vm_entry_controls & VM_ENTRY_LOAD_BNDCFGS)) 3183 vmx->nested.vmcs01_guest_bndcfgs = vmcs_read64(GUEST_BNDCFGS); 3184 3185 /* 3186 * Overwrite vmcs01.GUEST_CR3 with L1's CR3 if EPT is disabled *and* 3187 * nested early checks are disabled. In the event of a "late" VM-Fail, 3188 * i.e. a VM-Fail detected by hardware but not KVM, KVM must unwind its 3189 * software model to the pre-VMEntry host state. When EPT is disabled, 3190 * GUEST_CR3 holds KVM's shadow CR3, not L1's "real" CR3, which causes 3191 * nested_vmx_restore_host_state() to corrupt vcpu->arch.cr3. Stuffing 3192 * vmcs01.GUEST_CR3 results in the unwind naturally setting arch.cr3 to 3193 * the correct value. Smashing vmcs01.GUEST_CR3 is safe because nested 3194 * VM-Exits, and the unwind, reset KVM's MMU, i.e. vmcs01.GUEST_CR3 is 3195 * guaranteed to be overwritten with a shadow CR3 prior to re-entering 3196 * L1. Don't stuff vmcs01.GUEST_CR3 when using nested early checks as 3197 * KVM modifies vcpu->arch.cr3 if and only if the early hardware checks 3198 * pass, and early VM-Fails do not reset KVM's MMU, i.e. the VM-Fail 3199 * path would need to manually save/restore vmcs01.GUEST_CR3. 3200 */ 3201 if (!enable_ept && !nested_early_check) 3202 vmcs_writel(GUEST_CR3, vcpu->arch.cr3); 3203 3204 vmx_switch_vmcs(vcpu, &vmx->nested.vmcs02); 3205 3206 prepare_vmcs02_early(vmx, vmcs12); 3207 3208 if (from_vmentry) { 3209 if (unlikely(!nested_get_vmcs12_pages(vcpu))) 3210 return NVMX_VMENTRY_KVM_INTERNAL_ERROR; 3211 3212 if (nested_vmx_check_vmentry_hw(vcpu)) { 3213 vmx_switch_vmcs(vcpu, &vmx->vmcs01); 3214 return NVMX_VMENTRY_VMFAIL; 3215 } 3216 3217 if (nested_vmx_check_guest_state(vcpu, vmcs12, &exit_qual)) 3218 goto vmentry_fail_vmexit; 3219 } 3220 3221 enter_guest_mode(vcpu); 3222 if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETTING) 3223 vcpu->arch.tsc_offset += vmcs12->tsc_offset; 3224 3225 if (prepare_vmcs02(vcpu, vmcs12, &exit_qual)) 3226 goto vmentry_fail_vmexit_guest_mode; 3227 3228 if (from_vmentry) { 3229 exit_reason = EXIT_REASON_MSR_LOAD_FAIL; 3230 exit_qual = nested_vmx_load_msr(vcpu, 3231 vmcs12->vm_entry_msr_load_addr, 3232 vmcs12->vm_entry_msr_load_count); 3233 if (exit_qual) 3234 goto vmentry_fail_vmexit_guest_mode; 3235 } else { 3236 /* 3237 * The MMU is not initialized to point at the right entities yet and 3238 * "get pages" would need to read data from the guest (i.e. we will 3239 * need to perform gpa to hpa translation). Request a call 3240 * to nested_get_vmcs12_pages before the next VM-entry. The MSRs 3241 * have already been set at vmentry time and should not be reset. 3242 */ 3243 kvm_make_request(KVM_REQ_GET_VMCS12_PAGES, vcpu); 3244 } 3245 3246 /* 3247 * If L1 had a pending IRQ/NMI until it executed 3248 * VMLAUNCH/VMRESUME which wasn't delivered because it was 3249 * disallowed (e.g. interrupts disabled), L0 needs to 3250 * evaluate if this pending event should cause an exit from L2 3251 * to L1 or delivered directly to L2 (e.g. In case L1 don't 3252 * intercept EXTERNAL_INTERRUPT). 3253 * 3254 * Usually this would be handled by the processor noticing an 3255 * IRQ/NMI window request, or checking RVI during evaluation of 3256 * pending virtual interrupts. However, this setting was done 3257 * on VMCS01 and now VMCS02 is active instead. Thus, we force L0 3258 * to perform pending event evaluation by requesting a KVM_REQ_EVENT. 3259 */ 3260 if (unlikely(evaluate_pending_interrupts)) 3261 kvm_make_request(KVM_REQ_EVENT, vcpu); 3262 3263 /* 3264 * Do not start the preemption timer hrtimer until after we know 3265 * we are successful, so that only nested_vmx_vmexit needs to cancel 3266 * the timer. 3267 */ 3268 vmx->nested.preemption_timer_expired = false; 3269 if (nested_cpu_has_preemption_timer(vmcs12)) 3270 vmx_start_preemption_timer(vcpu); 3271 3272 /* 3273 * Note no nested_vmx_succeed or nested_vmx_fail here. At this point 3274 * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet 3275 * returned as far as L1 is concerned. It will only return (and set 3276 * the success flag) when L2 exits (see nested_vmx_vmexit()). 3277 */ 3278 return NVMX_VMENTRY_SUCCESS; 3279 3280 /* 3281 * A failed consistency check that leads to a VMExit during L1's 3282 * VMEnter to L2 is a variation of a normal VMexit, as explained in 3283 * 26.7 "VM-entry failures during or after loading guest state". 3284 */ 3285 vmentry_fail_vmexit_guest_mode: 3286 if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETTING) 3287 vcpu->arch.tsc_offset -= vmcs12->tsc_offset; 3288 leave_guest_mode(vcpu); 3289 3290 vmentry_fail_vmexit: 3291 vmx_switch_vmcs(vcpu, &vmx->vmcs01); 3292 3293 if (!from_vmentry) 3294 return NVMX_VMENTRY_VMEXIT; 3295 3296 load_vmcs12_host_state(vcpu, vmcs12); 3297 vmcs12->vm_exit_reason = exit_reason | VMX_EXIT_REASONS_FAILED_VMENTRY; 3298 vmcs12->exit_qualification = exit_qual; 3299 if (enable_shadow_vmcs || vmx->nested.hv_evmcs) 3300 vmx->nested.need_vmcs12_to_shadow_sync = true; 3301 return NVMX_VMENTRY_VMEXIT; 3302 } 3303 3304 /* 3305 * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1 3306 * for running an L2 nested guest. 3307 */ 3308 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch) 3309 { 3310 struct vmcs12 *vmcs12; 3311 enum nvmx_vmentry_status status; 3312 struct vcpu_vmx *vmx = to_vmx(vcpu); 3313 u32 interrupt_shadow = vmx_get_interrupt_shadow(vcpu); 3314 3315 if (!nested_vmx_check_permission(vcpu)) 3316 return 1; 3317 3318 if (!nested_vmx_handle_enlightened_vmptrld(vcpu, launch)) 3319 return 1; 3320 3321 if (!vmx->nested.hv_evmcs && vmx->nested.current_vmptr == -1ull) 3322 return nested_vmx_failInvalid(vcpu); 3323 3324 vmcs12 = get_vmcs12(vcpu); 3325 3326 /* 3327 * Can't VMLAUNCH or VMRESUME a shadow VMCS. Despite the fact 3328 * that there *is* a valid VMCS pointer, RFLAGS.CF is set 3329 * rather than RFLAGS.ZF, and no error number is stored to the 3330 * VM-instruction error field. 3331 */ 3332 if (vmcs12->hdr.shadow_vmcs) 3333 return nested_vmx_failInvalid(vcpu); 3334 3335 if (vmx->nested.hv_evmcs) { 3336 copy_enlightened_to_vmcs12(vmx); 3337 /* Enlightened VMCS doesn't have launch state */ 3338 vmcs12->launch_state = !launch; 3339 } else if (enable_shadow_vmcs) { 3340 copy_shadow_to_vmcs12(vmx); 3341 } 3342 3343 /* 3344 * The nested entry process starts with enforcing various prerequisites 3345 * on vmcs12 as required by the Intel SDM, and act appropriately when 3346 * they fail: As the SDM explains, some conditions should cause the 3347 * instruction to fail, while others will cause the instruction to seem 3348 * to succeed, but return an EXIT_REASON_INVALID_STATE. 3349 * To speed up the normal (success) code path, we should avoid checking 3350 * for misconfigurations which will anyway be caught by the processor 3351 * when using the merged vmcs02. 3352 */ 3353 if (interrupt_shadow & KVM_X86_SHADOW_INT_MOV_SS) 3354 return nested_vmx_failValid(vcpu, 3355 VMXERR_ENTRY_EVENTS_BLOCKED_BY_MOV_SS); 3356 3357 if (vmcs12->launch_state == launch) 3358 return nested_vmx_failValid(vcpu, 3359 launch ? VMXERR_VMLAUNCH_NONCLEAR_VMCS 3360 : VMXERR_VMRESUME_NONLAUNCHED_VMCS); 3361 3362 if (nested_vmx_check_controls(vcpu, vmcs12)) 3363 return nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD); 3364 3365 if (nested_vmx_check_host_state(vcpu, vmcs12)) 3366 return nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_HOST_STATE_FIELD); 3367 3368 /* 3369 * We're finally done with prerequisite checking, and can start with 3370 * the nested entry. 3371 */ 3372 vmx->nested.nested_run_pending = 1; 3373 status = nested_vmx_enter_non_root_mode(vcpu, true); 3374 if (unlikely(status != NVMX_VMENTRY_SUCCESS)) 3375 goto vmentry_failed; 3376 3377 /* Hide L1D cache contents from the nested guest. */ 3378 vmx->vcpu.arch.l1tf_flush_l1d = true; 3379 3380 /* 3381 * Must happen outside of nested_vmx_enter_non_root_mode() as it will 3382 * also be used as part of restoring nVMX state for 3383 * snapshot restore (migration). 3384 * 3385 * In this flow, it is assumed that vmcs12 cache was 3386 * trasferred as part of captured nVMX state and should 3387 * therefore not be read from guest memory (which may not 3388 * exist on destination host yet). 3389 */ 3390 nested_cache_shadow_vmcs12(vcpu, vmcs12); 3391 3392 /* 3393 * If we're entering a halted L2 vcpu and the L2 vcpu won't be 3394 * awakened by event injection or by an NMI-window VM-exit or 3395 * by an interrupt-window VM-exit, halt the vcpu. 3396 */ 3397 if ((vmcs12->guest_activity_state == GUEST_ACTIVITY_HLT) && 3398 !(vmcs12->vm_entry_intr_info_field & INTR_INFO_VALID_MASK) && 3399 !(vmcs12->cpu_based_vm_exec_control & CPU_BASED_NMI_WINDOW_EXITING) && 3400 !((vmcs12->cpu_based_vm_exec_control & CPU_BASED_INTR_WINDOW_EXITING) && 3401 (vmcs12->guest_rflags & X86_EFLAGS_IF))) { 3402 vmx->nested.nested_run_pending = 0; 3403 return kvm_vcpu_halt(vcpu); 3404 } 3405 return 1; 3406 3407 vmentry_failed: 3408 vmx->nested.nested_run_pending = 0; 3409 if (status == NVMX_VMENTRY_KVM_INTERNAL_ERROR) 3410 return 0; 3411 if (status == NVMX_VMENTRY_VMEXIT) 3412 return 1; 3413 WARN_ON_ONCE(status != NVMX_VMENTRY_VMFAIL); 3414 return nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD); 3415 } 3416 3417 /* 3418 * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date 3419 * because L2 may have changed some cr0 bits directly (CR0_GUEST_HOST_MASK). 3420 * This function returns the new value we should put in vmcs12.guest_cr0. 3421 * It's not enough to just return the vmcs02 GUEST_CR0. Rather, 3422 * 1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now 3423 * available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0 3424 * didn't trap the bit, because if L1 did, so would L0). 3425 * 2. Bits that L1 asked to trap (and therefore L0 also did) could not have 3426 * been modified by L2, and L1 knows it. So just leave the old value of 3427 * the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0 3428 * isn't relevant, because if L0 traps this bit it can set it to anything. 3429 * 3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have 3430 * changed these bits, and therefore they need to be updated, but L0 3431 * didn't necessarily allow them to be changed in GUEST_CR0 - and rather 3432 * put them in vmcs02 CR0_READ_SHADOW. So take these bits from there. 3433 */ 3434 static inline unsigned long 3435 vmcs12_guest_cr0(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12) 3436 { 3437 return 3438 /*1*/ (vmcs_readl(GUEST_CR0) & vcpu->arch.cr0_guest_owned_bits) | 3439 /*2*/ (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask) | 3440 /*3*/ (vmcs_readl(CR0_READ_SHADOW) & ~(vmcs12->cr0_guest_host_mask | 3441 vcpu->arch.cr0_guest_owned_bits)); 3442 } 3443 3444 static inline unsigned long 3445 vmcs12_guest_cr4(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12) 3446 { 3447 return 3448 /*1*/ (vmcs_readl(GUEST_CR4) & vcpu->arch.cr4_guest_owned_bits) | 3449 /*2*/ (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask) | 3450 /*3*/ (vmcs_readl(CR4_READ_SHADOW) & ~(vmcs12->cr4_guest_host_mask | 3451 vcpu->arch.cr4_guest_owned_bits)); 3452 } 3453 3454 static void vmcs12_save_pending_event(struct kvm_vcpu *vcpu, 3455 struct vmcs12 *vmcs12) 3456 { 3457 u32 idt_vectoring; 3458 unsigned int nr; 3459 3460 if (vcpu->arch.exception.injected) { 3461 nr = vcpu->arch.exception.nr; 3462 idt_vectoring = nr | VECTORING_INFO_VALID_MASK; 3463 3464 if (kvm_exception_is_soft(nr)) { 3465 vmcs12->vm_exit_instruction_len = 3466 vcpu->arch.event_exit_inst_len; 3467 idt_vectoring |= INTR_TYPE_SOFT_EXCEPTION; 3468 } else 3469 idt_vectoring |= INTR_TYPE_HARD_EXCEPTION; 3470 3471 if (vcpu->arch.exception.has_error_code) { 3472 idt_vectoring |= VECTORING_INFO_DELIVER_CODE_MASK; 3473 vmcs12->idt_vectoring_error_code = 3474 vcpu->arch.exception.error_code; 3475 } 3476 3477 vmcs12->idt_vectoring_info_field = idt_vectoring; 3478 } else if (vcpu->arch.nmi_injected) { 3479 vmcs12->idt_vectoring_info_field = 3480 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR; 3481 } else if (vcpu->arch.interrupt.injected) { 3482 nr = vcpu->arch.interrupt.nr; 3483 idt_vectoring = nr | VECTORING_INFO_VALID_MASK; 3484 3485 if (vcpu->arch.interrupt.soft) { 3486 idt_vectoring |= INTR_TYPE_SOFT_INTR; 3487 vmcs12->vm_entry_instruction_len = 3488 vcpu->arch.event_exit_inst_len; 3489 } else 3490 idt_vectoring |= INTR_TYPE_EXT_INTR; 3491 3492 vmcs12->idt_vectoring_info_field = idt_vectoring; 3493 } 3494 } 3495 3496 3497 static void nested_mark_vmcs12_pages_dirty(struct kvm_vcpu *vcpu) 3498 { 3499 struct vmcs12 *vmcs12 = get_vmcs12(vcpu); 3500 gfn_t gfn; 3501 3502 /* 3503 * Don't need to mark the APIC access page dirty; it is never 3504 * written to by the CPU during APIC virtualization. 3505 */ 3506 3507 if (nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW)) { 3508 gfn = vmcs12->virtual_apic_page_addr >> PAGE_SHIFT; 3509 kvm_vcpu_mark_page_dirty(vcpu, gfn); 3510 } 3511 3512 if (nested_cpu_has_posted_intr(vmcs12)) { 3513 gfn = vmcs12->posted_intr_desc_addr >> PAGE_SHIFT; 3514 kvm_vcpu_mark_page_dirty(vcpu, gfn); 3515 } 3516 } 3517 3518 static void vmx_complete_nested_posted_interrupt(struct kvm_vcpu *vcpu) 3519 { 3520 struct vcpu_vmx *vmx = to_vmx(vcpu); 3521 int max_irr; 3522 void *vapic_page; 3523 u16 status; 3524 3525 if (!vmx->nested.pi_desc || !vmx->nested.pi_pending) 3526 return; 3527 3528 vmx->nested.pi_pending = false; 3529 if (!pi_test_and_clear_on(vmx->nested.pi_desc)) 3530 return; 3531 3532 max_irr = find_last_bit((unsigned long *)vmx->nested.pi_desc->pir, 256); 3533 if (max_irr != 256) { 3534 vapic_page = vmx->nested.virtual_apic_map.hva; 3535 if (!vapic_page) 3536 return; 3537 3538 __kvm_apic_update_irr(vmx->nested.pi_desc->pir, 3539 vapic_page, &max_irr); 3540 status = vmcs_read16(GUEST_INTR_STATUS); 3541 if ((u8)max_irr > ((u8)status & 0xff)) { 3542 status &= ~0xff; 3543 status |= (u8)max_irr; 3544 vmcs_write16(GUEST_INTR_STATUS, status); 3545 } 3546 } 3547 3548 nested_mark_vmcs12_pages_dirty(vcpu); 3549 } 3550 3551 static void nested_vmx_inject_exception_vmexit(struct kvm_vcpu *vcpu, 3552 unsigned long exit_qual) 3553 { 3554 struct vmcs12 *vmcs12 = get_vmcs12(vcpu); 3555 unsigned int nr = vcpu->arch.exception.nr; 3556 u32 intr_info = nr | INTR_INFO_VALID_MASK; 3557 3558 if (vcpu->arch.exception.has_error_code) { 3559 vmcs12->vm_exit_intr_error_code = vcpu->arch.exception.error_code; 3560 intr_info |= INTR_INFO_DELIVER_CODE_MASK; 3561 } 3562 3563 if (kvm_exception_is_soft(nr)) 3564 intr_info |= INTR_TYPE_SOFT_EXCEPTION; 3565 else 3566 intr_info |= INTR_TYPE_HARD_EXCEPTION; 3567 3568 if (!(vmcs12->idt_vectoring_info_field & VECTORING_INFO_VALID_MASK) && 3569 vmx_get_nmi_mask(vcpu)) 3570 intr_info |= INTR_INFO_UNBLOCK_NMI; 3571 3572 nested_vmx_vmexit(vcpu, EXIT_REASON_EXCEPTION_NMI, intr_info, exit_qual); 3573 } 3574 3575 static int vmx_check_nested_events(struct kvm_vcpu *vcpu, bool external_intr) 3576 { 3577 struct vcpu_vmx *vmx = to_vmx(vcpu); 3578 unsigned long exit_qual; 3579 bool block_nested_events = 3580 vmx->nested.nested_run_pending || kvm_event_needs_reinjection(vcpu); 3581 struct kvm_lapic *apic = vcpu->arch.apic; 3582 3583 if (lapic_in_kernel(vcpu) && 3584 test_bit(KVM_APIC_INIT, &apic->pending_events)) { 3585 if (block_nested_events) 3586 return -EBUSY; 3587 clear_bit(KVM_APIC_INIT, &apic->pending_events); 3588 nested_vmx_vmexit(vcpu, EXIT_REASON_INIT_SIGNAL, 0, 0); 3589 return 0; 3590 } 3591 3592 if (vcpu->arch.exception.pending && 3593 nested_vmx_check_exception(vcpu, &exit_qual)) { 3594 if (block_nested_events) 3595 return -EBUSY; 3596 nested_vmx_inject_exception_vmexit(vcpu, exit_qual); 3597 return 0; 3598 } 3599 3600 if (nested_cpu_has_preemption_timer(get_vmcs12(vcpu)) && 3601 vmx->nested.preemption_timer_expired) { 3602 if (block_nested_events) 3603 return -EBUSY; 3604 nested_vmx_vmexit(vcpu, EXIT_REASON_PREEMPTION_TIMER, 0, 0); 3605 return 0; 3606 } 3607 3608 if (vcpu->arch.nmi_pending && nested_exit_on_nmi(vcpu)) { 3609 if (block_nested_events) 3610 return -EBUSY; 3611 nested_vmx_vmexit(vcpu, EXIT_REASON_EXCEPTION_NMI, 3612 NMI_VECTOR | INTR_TYPE_NMI_INTR | 3613 INTR_INFO_VALID_MASK, 0); 3614 /* 3615 * The NMI-triggered VM exit counts as injection: 3616 * clear this one and block further NMIs. 3617 */ 3618 vcpu->arch.nmi_pending = 0; 3619 vmx_set_nmi_mask(vcpu, true); 3620 return 0; 3621 } 3622 3623 if ((kvm_cpu_has_interrupt(vcpu) || external_intr) && 3624 nested_exit_on_intr(vcpu)) { 3625 if (block_nested_events) 3626 return -EBUSY; 3627 nested_vmx_vmexit(vcpu, EXIT_REASON_EXTERNAL_INTERRUPT, 0, 0); 3628 return 0; 3629 } 3630 3631 vmx_complete_nested_posted_interrupt(vcpu); 3632 return 0; 3633 } 3634 3635 static u32 vmx_get_preemption_timer_value(struct kvm_vcpu *vcpu) 3636 { 3637 ktime_t remaining = 3638 hrtimer_get_remaining(&to_vmx(vcpu)->nested.preemption_timer); 3639 u64 value; 3640 3641 if (ktime_to_ns(remaining) <= 0) 3642 return 0; 3643 3644 value = ktime_to_ns(remaining) * vcpu->arch.virtual_tsc_khz; 3645 do_div(value, 1000000); 3646 return value >> VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE; 3647 } 3648 3649 static bool is_vmcs12_ext_field(unsigned long field) 3650 { 3651 switch (field) { 3652 case GUEST_ES_SELECTOR: 3653 case GUEST_CS_SELECTOR: 3654 case GUEST_SS_SELECTOR: 3655 case GUEST_DS_SELECTOR: 3656 case GUEST_FS_SELECTOR: 3657 case GUEST_GS_SELECTOR: 3658 case GUEST_LDTR_SELECTOR: 3659 case GUEST_TR_SELECTOR: 3660 case GUEST_ES_LIMIT: 3661 case GUEST_CS_LIMIT: 3662 case GUEST_SS_LIMIT: 3663 case GUEST_DS_LIMIT: 3664 case GUEST_FS_LIMIT: 3665 case GUEST_GS_LIMIT: 3666 case GUEST_LDTR_LIMIT: 3667 case GUEST_TR_LIMIT: 3668 case GUEST_GDTR_LIMIT: 3669 case GUEST_IDTR_LIMIT: 3670 case GUEST_ES_AR_BYTES: 3671 case GUEST_DS_AR_BYTES: 3672 case GUEST_FS_AR_BYTES: 3673 case GUEST_GS_AR_BYTES: 3674 case GUEST_LDTR_AR_BYTES: 3675 case GUEST_TR_AR_BYTES: 3676 case GUEST_ES_BASE: 3677 case GUEST_CS_BASE: 3678 case GUEST_SS_BASE: 3679 case GUEST_DS_BASE: 3680 case GUEST_FS_BASE: 3681 case GUEST_GS_BASE: 3682 case GUEST_LDTR_BASE: 3683 case GUEST_TR_BASE: 3684 case GUEST_GDTR_BASE: 3685 case GUEST_IDTR_BASE: 3686 case GUEST_PENDING_DBG_EXCEPTIONS: 3687 case GUEST_BNDCFGS: 3688 return true; 3689 default: 3690 break; 3691 } 3692 3693 return false; 3694 } 3695 3696 static void sync_vmcs02_to_vmcs12_rare(struct kvm_vcpu *vcpu, 3697 struct vmcs12 *vmcs12) 3698 { 3699 struct vcpu_vmx *vmx = to_vmx(vcpu); 3700 3701 vmcs12->guest_es_selector = vmcs_read16(GUEST_ES_SELECTOR); 3702 vmcs12->guest_cs_selector = vmcs_read16(GUEST_CS_SELECTOR); 3703 vmcs12->guest_ss_selector = vmcs_read16(GUEST_SS_SELECTOR); 3704 vmcs12->guest_ds_selector = vmcs_read16(GUEST_DS_SELECTOR); 3705 vmcs12->guest_fs_selector = vmcs_read16(GUEST_FS_SELECTOR); 3706 vmcs12->guest_gs_selector = vmcs_read16(GUEST_GS_SELECTOR); 3707 vmcs12->guest_ldtr_selector = vmcs_read16(GUEST_LDTR_SELECTOR); 3708 vmcs12->guest_tr_selector = vmcs_read16(GUEST_TR_SELECTOR); 3709 vmcs12->guest_es_limit = vmcs_read32(GUEST_ES_LIMIT); 3710 vmcs12->guest_cs_limit = vmcs_read32(GUEST_CS_LIMIT); 3711 vmcs12->guest_ss_limit = vmcs_read32(GUEST_SS_LIMIT); 3712 vmcs12->guest_ds_limit = vmcs_read32(GUEST_DS_LIMIT); 3713 vmcs12->guest_fs_limit = vmcs_read32(GUEST_FS_LIMIT); 3714 vmcs12->guest_gs_limit = vmcs_read32(GUEST_GS_LIMIT); 3715 vmcs12->guest_ldtr_limit = vmcs_read32(GUEST_LDTR_LIMIT); 3716 vmcs12->guest_tr_limit = vmcs_read32(GUEST_TR_LIMIT); 3717 vmcs12->guest_gdtr_limit = vmcs_read32(GUEST_GDTR_LIMIT); 3718 vmcs12->guest_idtr_limit = vmcs_read32(GUEST_IDTR_LIMIT); 3719 vmcs12->guest_es_ar_bytes = vmcs_read32(GUEST_ES_AR_BYTES); 3720 vmcs12->guest_ds_ar_bytes = vmcs_read32(GUEST_DS_AR_BYTES); 3721 vmcs12->guest_fs_ar_bytes = vmcs_read32(GUEST_FS_AR_BYTES); 3722 vmcs12->guest_gs_ar_bytes = vmcs_read32(GUEST_GS_AR_BYTES); 3723 vmcs12->guest_ldtr_ar_bytes = vmcs_read32(GUEST_LDTR_AR_BYTES); 3724 vmcs12->guest_tr_ar_bytes = vmcs_read32(GUEST_TR_AR_BYTES); 3725 vmcs12->guest_es_base = vmcs_readl(GUEST_ES_BASE); 3726 vmcs12->guest_cs_base = vmcs_readl(GUEST_CS_BASE); 3727 vmcs12->guest_ss_base = vmcs_readl(GUEST_SS_BASE); 3728 vmcs12->guest_ds_base = vmcs_readl(GUEST_DS_BASE); 3729 vmcs12->guest_fs_base = vmcs_readl(GUEST_FS_BASE); 3730 vmcs12->guest_gs_base = vmcs_readl(GUEST_GS_BASE); 3731 vmcs12->guest_ldtr_base = vmcs_readl(GUEST_LDTR_BASE); 3732 vmcs12->guest_tr_base = vmcs_readl(GUEST_TR_BASE); 3733 vmcs12->guest_gdtr_base = vmcs_readl(GUEST_GDTR_BASE); 3734 vmcs12->guest_idtr_base = vmcs_readl(GUEST_IDTR_BASE); 3735 vmcs12->guest_pending_dbg_exceptions = 3736 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS); 3737 if (kvm_mpx_supported()) 3738 vmcs12->guest_bndcfgs = vmcs_read64(GUEST_BNDCFGS); 3739 3740 vmx->nested.need_sync_vmcs02_to_vmcs12_rare = false; 3741 } 3742 3743 static void copy_vmcs02_to_vmcs12_rare(struct kvm_vcpu *vcpu, 3744 struct vmcs12 *vmcs12) 3745 { 3746 struct vcpu_vmx *vmx = to_vmx(vcpu); 3747 int cpu; 3748 3749 if (!vmx->nested.need_sync_vmcs02_to_vmcs12_rare) 3750 return; 3751 3752 3753 WARN_ON_ONCE(vmx->loaded_vmcs != &vmx->vmcs01); 3754 3755 cpu = get_cpu(); 3756 vmx->loaded_vmcs = &vmx->nested.vmcs02; 3757 vmx_vcpu_load(&vmx->vcpu, cpu); 3758 3759 sync_vmcs02_to_vmcs12_rare(vcpu, vmcs12); 3760 3761 vmx->loaded_vmcs = &vmx->vmcs01; 3762 vmx_vcpu_load(&vmx->vcpu, cpu); 3763 put_cpu(); 3764 } 3765 3766 /* 3767 * Update the guest state fields of vmcs12 to reflect changes that 3768 * occurred while L2 was running. (The "IA-32e mode guest" bit of the 3769 * VM-entry controls is also updated, since this is really a guest 3770 * state bit.) 3771 */ 3772 static void sync_vmcs02_to_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12) 3773 { 3774 struct vcpu_vmx *vmx = to_vmx(vcpu); 3775 3776 if (vmx->nested.hv_evmcs) 3777 sync_vmcs02_to_vmcs12_rare(vcpu, vmcs12); 3778 3779 vmx->nested.need_sync_vmcs02_to_vmcs12_rare = !vmx->nested.hv_evmcs; 3780 3781 vmcs12->guest_cr0 = vmcs12_guest_cr0(vcpu, vmcs12); 3782 vmcs12->guest_cr4 = vmcs12_guest_cr4(vcpu, vmcs12); 3783 3784 vmcs12->guest_rsp = kvm_rsp_read(vcpu); 3785 vmcs12->guest_rip = kvm_rip_read(vcpu); 3786 vmcs12->guest_rflags = vmcs_readl(GUEST_RFLAGS); 3787 3788 vmcs12->guest_cs_ar_bytes = vmcs_read32(GUEST_CS_AR_BYTES); 3789 vmcs12->guest_ss_ar_bytes = vmcs_read32(GUEST_SS_AR_BYTES); 3790 3791 vmcs12->guest_sysenter_cs = vmcs_read32(GUEST_SYSENTER_CS); 3792 vmcs12->guest_sysenter_esp = vmcs_readl(GUEST_SYSENTER_ESP); 3793 vmcs12->guest_sysenter_eip = vmcs_readl(GUEST_SYSENTER_EIP); 3794 3795 vmcs12->guest_interruptibility_info = 3796 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO); 3797 3798 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED) 3799 vmcs12->guest_activity_state = GUEST_ACTIVITY_HLT; 3800 else 3801 vmcs12->guest_activity_state = GUEST_ACTIVITY_ACTIVE; 3802 3803 if (nested_cpu_has_preemption_timer(vmcs12) && 3804 vmcs12->vm_exit_controls & VM_EXIT_SAVE_VMX_PREEMPTION_TIMER) 3805 vmcs12->vmx_preemption_timer_value = 3806 vmx_get_preemption_timer_value(vcpu); 3807 3808 /* 3809 * In some cases (usually, nested EPT), L2 is allowed to change its 3810 * own CR3 without exiting. If it has changed it, we must keep it. 3811 * Of course, if L0 is using shadow page tables, GUEST_CR3 was defined 3812 * by L0, not L1 or L2, so we mustn't unconditionally copy it to vmcs12. 3813 * 3814 * Additionally, restore L2's PDPTR to vmcs12. 3815 */ 3816 if (enable_ept) { 3817 vmcs12->guest_cr3 = vmcs_readl(GUEST_CR3); 3818 if (nested_cpu_has_ept(vmcs12) && is_pae_paging(vcpu)) { 3819 vmcs12->guest_pdptr0 = vmcs_read64(GUEST_PDPTR0); 3820 vmcs12->guest_pdptr1 = vmcs_read64(GUEST_PDPTR1); 3821 vmcs12->guest_pdptr2 = vmcs_read64(GUEST_PDPTR2); 3822 vmcs12->guest_pdptr3 = vmcs_read64(GUEST_PDPTR3); 3823 } 3824 } 3825 3826 vmcs12->guest_linear_address = vmcs_readl(GUEST_LINEAR_ADDRESS); 3827 3828 if (nested_cpu_has_vid(vmcs12)) 3829 vmcs12->guest_intr_status = vmcs_read16(GUEST_INTR_STATUS); 3830 3831 vmcs12->vm_entry_controls = 3832 (vmcs12->vm_entry_controls & ~VM_ENTRY_IA32E_MODE) | 3833 (vm_entry_controls_get(to_vmx(vcpu)) & VM_ENTRY_IA32E_MODE); 3834 3835 if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_DEBUG_CONTROLS) 3836 kvm_get_dr(vcpu, 7, (unsigned long *)&vmcs12->guest_dr7); 3837 3838 if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_EFER) 3839 vmcs12->guest_ia32_efer = vcpu->arch.efer; 3840 } 3841 3842 /* 3843 * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits 3844 * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12), 3845 * and this function updates it to reflect the changes to the guest state while 3846 * L2 was running (and perhaps made some exits which were handled directly by L0 3847 * without going back to L1), and to reflect the exit reason. 3848 * Note that we do not have to copy here all VMCS fields, just those that 3849 * could have changed by the L2 guest or the exit - i.e., the guest-state and 3850 * exit-information fields only. Other fields are modified by L1 with VMWRITE, 3851 * which already writes to vmcs12 directly. 3852 */ 3853 static void prepare_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12, 3854 u32 exit_reason, u32 exit_intr_info, 3855 unsigned long exit_qualification) 3856 { 3857 /* update exit information fields: */ 3858 vmcs12->vm_exit_reason = exit_reason; 3859 vmcs12->exit_qualification = exit_qualification; 3860 vmcs12->vm_exit_intr_info = exit_intr_info; 3861 3862 vmcs12->idt_vectoring_info_field = 0; 3863 vmcs12->vm_exit_instruction_len = vmcs_read32(VM_EXIT_INSTRUCTION_LEN); 3864 vmcs12->vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO); 3865 3866 if (!(vmcs12->vm_exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY)) { 3867 vmcs12->launch_state = 1; 3868 3869 /* vm_entry_intr_info_field is cleared on exit. Emulate this 3870 * instead of reading the real value. */ 3871 vmcs12->vm_entry_intr_info_field &= ~INTR_INFO_VALID_MASK; 3872 3873 /* 3874 * Transfer the event that L0 or L1 may wanted to inject into 3875 * L2 to IDT_VECTORING_INFO_FIELD. 3876 */ 3877 vmcs12_save_pending_event(vcpu, vmcs12); 3878 3879 /* 3880 * According to spec, there's no need to store the guest's 3881 * MSRs if the exit is due to a VM-entry failure that occurs 3882 * during or after loading the guest state. Since this exit 3883 * does not fall in that category, we need to save the MSRs. 3884 */ 3885 if (nested_vmx_store_msr(vcpu, 3886 vmcs12->vm_exit_msr_store_addr, 3887 vmcs12->vm_exit_msr_store_count)) 3888 nested_vmx_abort(vcpu, 3889 VMX_ABORT_SAVE_GUEST_MSR_FAIL); 3890 } 3891 3892 /* 3893 * Drop what we picked up for L2 via vmx_complete_interrupts. It is 3894 * preserved above and would only end up incorrectly in L1. 3895 */ 3896 vcpu->arch.nmi_injected = false; 3897 kvm_clear_exception_queue(vcpu); 3898 kvm_clear_interrupt_queue(vcpu); 3899 } 3900 3901 /* 3902 * A part of what we need to when the nested L2 guest exits and we want to 3903 * run its L1 parent, is to reset L1's guest state to the host state specified 3904 * in vmcs12. 3905 * This function is to be called not only on normal nested exit, but also on 3906 * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry 3907 * Failures During or After Loading Guest State"). 3908 * This function should be called when the active VMCS is L1's (vmcs01). 3909 */ 3910 static void load_vmcs12_host_state(struct kvm_vcpu *vcpu, 3911 struct vmcs12 *vmcs12) 3912 { 3913 struct kvm_segment seg; 3914 u32 entry_failure_code; 3915 3916 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER) 3917 vcpu->arch.efer = vmcs12->host_ia32_efer; 3918 else if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE) 3919 vcpu->arch.efer |= (EFER_LMA | EFER_LME); 3920 else 3921 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME); 3922 vmx_set_efer(vcpu, vcpu->arch.efer); 3923 3924 kvm_rsp_write(vcpu, vmcs12->host_rsp); 3925 kvm_rip_write(vcpu, vmcs12->host_rip); 3926 vmx_set_rflags(vcpu, X86_EFLAGS_FIXED); 3927 vmx_set_interrupt_shadow(vcpu, 0); 3928 3929 /* 3930 * Note that calling vmx_set_cr0 is important, even if cr0 hasn't 3931 * actually changed, because vmx_set_cr0 refers to efer set above. 3932 * 3933 * CR0_GUEST_HOST_MASK is already set in the original vmcs01 3934 * (KVM doesn't change it); 3935 */ 3936 vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS; 3937 vmx_set_cr0(vcpu, vmcs12->host_cr0); 3938 3939 /* Same as above - no reason to call set_cr4_guest_host_mask(). */ 3940 vcpu->arch.cr4_guest_owned_bits = ~vmcs_readl(CR4_GUEST_HOST_MASK); 3941 vmx_set_cr4(vcpu, vmcs12->host_cr4); 3942 3943 nested_ept_uninit_mmu_context(vcpu); 3944 3945 /* 3946 * Only PDPTE load can fail as the value of cr3 was checked on entry and 3947 * couldn't have changed. 3948 */ 3949 if (nested_vmx_load_cr3(vcpu, vmcs12->host_cr3, false, &entry_failure_code)) 3950 nested_vmx_abort(vcpu, VMX_ABORT_LOAD_HOST_PDPTE_FAIL); 3951 3952 if (!enable_ept) 3953 vcpu->arch.walk_mmu->inject_page_fault = kvm_inject_page_fault; 3954 3955 /* 3956 * If vmcs01 doesn't use VPID, CPU flushes TLB on every 3957 * VMEntry/VMExit. Thus, no need to flush TLB. 3958 * 3959 * If vmcs12 doesn't use VPID, L1 expects TLB to be 3960 * flushed on every VMEntry/VMExit. 3961 * 3962 * Otherwise, we can preserve TLB entries as long as we are 3963 * able to tag L1 TLB entries differently than L2 TLB entries. 3964 * 3965 * If vmcs12 uses EPT, we need to execute this flush on EPTP01 3966 * and therefore we request the TLB flush to happen only after VMCS EPTP 3967 * has been set by KVM_REQ_LOAD_CR3. 3968 */ 3969 if (enable_vpid && 3970 (!nested_cpu_has_vpid(vmcs12) || !nested_has_guest_tlb_tag(vcpu))) { 3971 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu); 3972 } 3973 3974 vmcs_write32(GUEST_SYSENTER_CS, vmcs12->host_ia32_sysenter_cs); 3975 vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->host_ia32_sysenter_esp); 3976 vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->host_ia32_sysenter_eip); 3977 vmcs_writel(GUEST_IDTR_BASE, vmcs12->host_idtr_base); 3978 vmcs_writel(GUEST_GDTR_BASE, vmcs12->host_gdtr_base); 3979 vmcs_write32(GUEST_IDTR_LIMIT, 0xFFFF); 3980 vmcs_write32(GUEST_GDTR_LIMIT, 0xFFFF); 3981 3982 /* If not VM_EXIT_CLEAR_BNDCFGS, the L2 value propagates to L1. */ 3983 if (vmcs12->vm_exit_controls & VM_EXIT_CLEAR_BNDCFGS) 3984 vmcs_write64(GUEST_BNDCFGS, 0); 3985 3986 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PAT) { 3987 vmcs_write64(GUEST_IA32_PAT, vmcs12->host_ia32_pat); 3988 vcpu->arch.pat = vmcs12->host_ia32_pat; 3989 } 3990 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL) 3991 WARN_ON_ONCE(kvm_set_msr(vcpu, MSR_CORE_PERF_GLOBAL_CTRL, 3992 vmcs12->host_ia32_perf_global_ctrl)); 3993 3994 /* Set L1 segment info according to Intel SDM 3995 27.5.2 Loading Host Segment and Descriptor-Table Registers */ 3996 seg = (struct kvm_segment) { 3997 .base = 0, 3998 .limit = 0xFFFFFFFF, 3999 .selector = vmcs12->host_cs_selector, 4000 .type = 11, 4001 .present = 1, 4002 .s = 1, 4003 .g = 1 4004 }; 4005 if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE) 4006 seg.l = 1; 4007 else 4008 seg.db = 1; 4009 vmx_set_segment(vcpu, &seg, VCPU_SREG_CS); 4010 seg = (struct kvm_segment) { 4011 .base = 0, 4012 .limit = 0xFFFFFFFF, 4013 .type = 3, 4014 .present = 1, 4015 .s = 1, 4016 .db = 1, 4017 .g = 1 4018 }; 4019 seg.selector = vmcs12->host_ds_selector; 4020 vmx_set_segment(vcpu, &seg, VCPU_SREG_DS); 4021 seg.selector = vmcs12->host_es_selector; 4022 vmx_set_segment(vcpu, &seg, VCPU_SREG_ES); 4023 seg.selector = vmcs12->host_ss_selector; 4024 vmx_set_segment(vcpu, &seg, VCPU_SREG_SS); 4025 seg.selector = vmcs12->host_fs_selector; 4026 seg.base = vmcs12->host_fs_base; 4027 vmx_set_segment(vcpu, &seg, VCPU_SREG_FS); 4028 seg.selector = vmcs12->host_gs_selector; 4029 seg.base = vmcs12->host_gs_base; 4030 vmx_set_segment(vcpu, &seg, VCPU_SREG_GS); 4031 seg = (struct kvm_segment) { 4032 .base = vmcs12->host_tr_base, 4033 .limit = 0x67, 4034 .selector = vmcs12->host_tr_selector, 4035 .type = 11, 4036 .present = 1 4037 }; 4038 vmx_set_segment(vcpu, &seg, VCPU_SREG_TR); 4039 4040 kvm_set_dr(vcpu, 7, 0x400); 4041 vmcs_write64(GUEST_IA32_DEBUGCTL, 0); 4042 4043 if (cpu_has_vmx_msr_bitmap()) 4044 vmx_update_msr_bitmap(vcpu); 4045 4046 if (nested_vmx_load_msr(vcpu, vmcs12->vm_exit_msr_load_addr, 4047 vmcs12->vm_exit_msr_load_count)) 4048 nested_vmx_abort(vcpu, VMX_ABORT_LOAD_HOST_MSR_FAIL); 4049 } 4050 4051 static inline u64 nested_vmx_get_vmcs01_guest_efer(struct vcpu_vmx *vmx) 4052 { 4053 struct shared_msr_entry *efer_msr; 4054 unsigned int i; 4055 4056 if (vm_entry_controls_get(vmx) & VM_ENTRY_LOAD_IA32_EFER) 4057 return vmcs_read64(GUEST_IA32_EFER); 4058 4059 if (cpu_has_load_ia32_efer()) 4060 return host_efer; 4061 4062 for (i = 0; i < vmx->msr_autoload.guest.nr; ++i) { 4063 if (vmx->msr_autoload.guest.val[i].index == MSR_EFER) 4064 return vmx->msr_autoload.guest.val[i].value; 4065 } 4066 4067 efer_msr = find_msr_entry(vmx, MSR_EFER); 4068 if (efer_msr) 4069 return efer_msr->data; 4070 4071 return host_efer; 4072 } 4073 4074 static void nested_vmx_restore_host_state(struct kvm_vcpu *vcpu) 4075 { 4076 struct vmcs12 *vmcs12 = get_vmcs12(vcpu); 4077 struct vcpu_vmx *vmx = to_vmx(vcpu); 4078 struct vmx_msr_entry g, h; 4079 gpa_t gpa; 4080 u32 i, j; 4081 4082 vcpu->arch.pat = vmcs_read64(GUEST_IA32_PAT); 4083 4084 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS) { 4085 /* 4086 * L1's host DR7 is lost if KVM_GUESTDBG_USE_HW_BP is set 4087 * as vmcs01.GUEST_DR7 contains a userspace defined value 4088 * and vcpu->arch.dr7 is not squirreled away before the 4089 * nested VMENTER (not worth adding a variable in nested_vmx). 4090 */ 4091 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) 4092 kvm_set_dr(vcpu, 7, DR7_FIXED_1); 4093 else 4094 WARN_ON(kvm_set_dr(vcpu, 7, vmcs_readl(GUEST_DR7))); 4095 } 4096 4097 /* 4098 * Note that calling vmx_set_{efer,cr0,cr4} is important as they 4099 * handle a variety of side effects to KVM's software model. 4100 */ 4101 vmx_set_efer(vcpu, nested_vmx_get_vmcs01_guest_efer(vmx)); 4102 4103 vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS; 4104 vmx_set_cr0(vcpu, vmcs_readl(CR0_READ_SHADOW)); 4105 4106 vcpu->arch.cr4_guest_owned_bits = ~vmcs_readl(CR4_GUEST_HOST_MASK); 4107 vmx_set_cr4(vcpu, vmcs_readl(CR4_READ_SHADOW)); 4108 4109 nested_ept_uninit_mmu_context(vcpu); 4110 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3); 4111 kvm_register_mark_available(vcpu, VCPU_EXREG_CR3); 4112 4113 /* 4114 * Use ept_save_pdptrs(vcpu) to load the MMU's cached PDPTRs 4115 * from vmcs01 (if necessary). The PDPTRs are not loaded on 4116 * VMFail, like everything else we just need to ensure our 4117 * software model is up-to-date. 4118 */ 4119 if (enable_ept) 4120 ept_save_pdptrs(vcpu); 4121 4122 kvm_mmu_reset_context(vcpu); 4123 4124 if (cpu_has_vmx_msr_bitmap()) 4125 vmx_update_msr_bitmap(vcpu); 4126 4127 /* 4128 * This nasty bit of open coding is a compromise between blindly 4129 * loading L1's MSRs using the exit load lists (incorrect emulation 4130 * of VMFail), leaving the nested VM's MSRs in the software model 4131 * (incorrect behavior) and snapshotting the modified MSRs (too 4132 * expensive since the lists are unbound by hardware). For each 4133 * MSR that was (prematurely) loaded from the nested VMEntry load 4134 * list, reload it from the exit load list if it exists and differs 4135 * from the guest value. The intent is to stuff host state as 4136 * silently as possible, not to fully process the exit load list. 4137 */ 4138 for (i = 0; i < vmcs12->vm_entry_msr_load_count; i++) { 4139 gpa = vmcs12->vm_entry_msr_load_addr + (i * sizeof(g)); 4140 if (kvm_vcpu_read_guest(vcpu, gpa, &g, sizeof(g))) { 4141 pr_debug_ratelimited( 4142 "%s read MSR index failed (%u, 0x%08llx)\n", 4143 __func__, i, gpa); 4144 goto vmabort; 4145 } 4146 4147 for (j = 0; j < vmcs12->vm_exit_msr_load_count; j++) { 4148 gpa = vmcs12->vm_exit_msr_load_addr + (j * sizeof(h)); 4149 if (kvm_vcpu_read_guest(vcpu, gpa, &h, sizeof(h))) { 4150 pr_debug_ratelimited( 4151 "%s read MSR failed (%u, 0x%08llx)\n", 4152 __func__, j, gpa); 4153 goto vmabort; 4154 } 4155 if (h.index != g.index) 4156 continue; 4157 if (h.value == g.value) 4158 break; 4159 4160 if (nested_vmx_load_msr_check(vcpu, &h)) { 4161 pr_debug_ratelimited( 4162 "%s check failed (%u, 0x%x, 0x%x)\n", 4163 __func__, j, h.index, h.reserved); 4164 goto vmabort; 4165 } 4166 4167 if (kvm_set_msr(vcpu, h.index, h.value)) { 4168 pr_debug_ratelimited( 4169 "%s WRMSR failed (%u, 0x%x, 0x%llx)\n", 4170 __func__, j, h.index, h.value); 4171 goto vmabort; 4172 } 4173 } 4174 } 4175 4176 return; 4177 4178 vmabort: 4179 nested_vmx_abort(vcpu, VMX_ABORT_LOAD_HOST_MSR_FAIL); 4180 } 4181 4182 /* 4183 * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1 4184 * and modify vmcs12 to make it see what it would expect to see there if 4185 * L2 was its real guest. Must only be called when in L2 (is_guest_mode()) 4186 */ 4187 void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason, 4188 u32 exit_intr_info, unsigned long exit_qualification) 4189 { 4190 struct vcpu_vmx *vmx = to_vmx(vcpu); 4191 struct vmcs12 *vmcs12 = get_vmcs12(vcpu); 4192 4193 /* trying to cancel vmlaunch/vmresume is a bug */ 4194 WARN_ON_ONCE(vmx->nested.nested_run_pending); 4195 4196 leave_guest_mode(vcpu); 4197 4198 if (nested_cpu_has_preemption_timer(vmcs12)) 4199 hrtimer_cancel(&to_vmx(vcpu)->nested.preemption_timer); 4200 4201 if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETTING) 4202 vcpu->arch.tsc_offset -= vmcs12->tsc_offset; 4203 4204 if (likely(!vmx->fail)) { 4205 sync_vmcs02_to_vmcs12(vcpu, vmcs12); 4206 4207 if (exit_reason != -1) 4208 prepare_vmcs12(vcpu, vmcs12, exit_reason, exit_intr_info, 4209 exit_qualification); 4210 4211 /* 4212 * Must happen outside of sync_vmcs02_to_vmcs12() as it will 4213 * also be used to capture vmcs12 cache as part of 4214 * capturing nVMX state for snapshot (migration). 4215 * 4216 * Otherwise, this flush will dirty guest memory at a 4217 * point it is already assumed by user-space to be 4218 * immutable. 4219 */ 4220 nested_flush_cached_shadow_vmcs12(vcpu, vmcs12); 4221 } else { 4222 /* 4223 * The only expected VM-instruction error is "VM entry with 4224 * invalid control field(s)." Anything else indicates a 4225 * problem with L0. And we should never get here with a 4226 * VMFail of any type if early consistency checks are enabled. 4227 */ 4228 WARN_ON_ONCE(vmcs_read32(VM_INSTRUCTION_ERROR) != 4229 VMXERR_ENTRY_INVALID_CONTROL_FIELD); 4230 WARN_ON_ONCE(nested_early_check); 4231 } 4232 4233 vmx_switch_vmcs(vcpu, &vmx->vmcs01); 4234 4235 /* Update any VMCS fields that might have changed while L2 ran */ 4236 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, vmx->msr_autoload.host.nr); 4237 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, vmx->msr_autoload.guest.nr); 4238 vmcs_write64(TSC_OFFSET, vcpu->arch.tsc_offset); 4239 if (vmx->nested.l1_tpr_threshold != -1) 4240 vmcs_write32(TPR_THRESHOLD, vmx->nested.l1_tpr_threshold); 4241 4242 if (kvm_has_tsc_control) 4243 decache_tsc_multiplier(vmx); 4244 4245 if (vmx->nested.change_vmcs01_virtual_apic_mode) { 4246 vmx->nested.change_vmcs01_virtual_apic_mode = false; 4247 vmx_set_virtual_apic_mode(vcpu); 4248 } 4249 4250 /* Unpin physical memory we referred to in vmcs02 */ 4251 if (vmx->nested.apic_access_page) { 4252 kvm_release_page_clean(vmx->nested.apic_access_page); 4253 vmx->nested.apic_access_page = NULL; 4254 } 4255 kvm_vcpu_unmap(vcpu, &vmx->nested.virtual_apic_map, true); 4256 kvm_vcpu_unmap(vcpu, &vmx->nested.pi_desc_map, true); 4257 vmx->nested.pi_desc = NULL; 4258 4259 /* 4260 * We are now running in L2, mmu_notifier will force to reload the 4261 * page's hpa for L2 vmcs. Need to reload it for L1 before entering L1. 4262 */ 4263 kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu); 4264 4265 if ((exit_reason != -1) && (enable_shadow_vmcs || vmx->nested.hv_evmcs)) 4266 vmx->nested.need_vmcs12_to_shadow_sync = true; 4267 4268 /* in case we halted in L2 */ 4269 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; 4270 4271 if (likely(!vmx->fail)) { 4272 /* 4273 * TODO: SDM says that with acknowledge interrupt on 4274 * exit, bit 31 of the VM-exit interrupt information 4275 * (valid interrupt) is always set to 1 on 4276 * EXIT_REASON_EXTERNAL_INTERRUPT, so we shouldn't 4277 * need kvm_cpu_has_interrupt(). See the commit 4278 * message for details. 4279 */ 4280 if (nested_exit_intr_ack_set(vcpu) && 4281 exit_reason == EXIT_REASON_EXTERNAL_INTERRUPT && 4282 kvm_cpu_has_interrupt(vcpu)) { 4283 int irq = kvm_cpu_get_interrupt(vcpu); 4284 WARN_ON(irq < 0); 4285 vmcs12->vm_exit_intr_info = irq | 4286 INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR; 4287 } 4288 4289 if (exit_reason != -1) 4290 trace_kvm_nested_vmexit_inject(vmcs12->vm_exit_reason, 4291 vmcs12->exit_qualification, 4292 vmcs12->idt_vectoring_info_field, 4293 vmcs12->vm_exit_intr_info, 4294 vmcs12->vm_exit_intr_error_code, 4295 KVM_ISA_VMX); 4296 4297 load_vmcs12_host_state(vcpu, vmcs12); 4298 4299 return; 4300 } 4301 4302 /* 4303 * After an early L2 VM-entry failure, we're now back 4304 * in L1 which thinks it just finished a VMLAUNCH or 4305 * VMRESUME instruction, so we need to set the failure 4306 * flag and the VM-instruction error field of the VMCS 4307 * accordingly, and skip the emulated instruction. 4308 */ 4309 (void)nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD); 4310 4311 /* 4312 * Restore L1's host state to KVM's software model. We're here 4313 * because a consistency check was caught by hardware, which 4314 * means some amount of guest state has been propagated to KVM's 4315 * model and needs to be unwound to the host's state. 4316 */ 4317 nested_vmx_restore_host_state(vcpu); 4318 4319 vmx->fail = 0; 4320 } 4321 4322 /* 4323 * Decode the memory-address operand of a vmx instruction, as recorded on an 4324 * exit caused by such an instruction (run by a guest hypervisor). 4325 * On success, returns 0. When the operand is invalid, returns 1 and throws 4326 * #UD or #GP. 4327 */ 4328 int get_vmx_mem_address(struct kvm_vcpu *vcpu, unsigned long exit_qualification, 4329 u32 vmx_instruction_info, bool wr, int len, gva_t *ret) 4330 { 4331 gva_t off; 4332 bool exn; 4333 struct kvm_segment s; 4334 4335 /* 4336 * According to Vol. 3B, "Information for VM Exits Due to Instruction 4337 * Execution", on an exit, vmx_instruction_info holds most of the 4338 * addressing components of the operand. Only the displacement part 4339 * is put in exit_qualification (see 3B, "Basic VM-Exit Information"). 4340 * For how an actual address is calculated from all these components, 4341 * refer to Vol. 1, "Operand Addressing". 4342 */ 4343 int scaling = vmx_instruction_info & 3; 4344 int addr_size = (vmx_instruction_info >> 7) & 7; 4345 bool is_reg = vmx_instruction_info & (1u << 10); 4346 int seg_reg = (vmx_instruction_info >> 15) & 7; 4347 int index_reg = (vmx_instruction_info >> 18) & 0xf; 4348 bool index_is_valid = !(vmx_instruction_info & (1u << 22)); 4349 int base_reg = (vmx_instruction_info >> 23) & 0xf; 4350 bool base_is_valid = !(vmx_instruction_info & (1u << 27)); 4351 4352 if (is_reg) { 4353 kvm_queue_exception(vcpu, UD_VECTOR); 4354 return 1; 4355 } 4356 4357 /* Addr = segment_base + offset */ 4358 /* offset = base + [index * scale] + displacement */ 4359 off = exit_qualification; /* holds the displacement */ 4360 if (addr_size == 1) 4361 off = (gva_t)sign_extend64(off, 31); 4362 else if (addr_size == 0) 4363 off = (gva_t)sign_extend64(off, 15); 4364 if (base_is_valid) 4365 off += kvm_register_read(vcpu, base_reg); 4366 if (index_is_valid) 4367 off += kvm_register_read(vcpu, index_reg)<<scaling; 4368 vmx_get_segment(vcpu, &s, seg_reg); 4369 4370 /* 4371 * The effective address, i.e. @off, of a memory operand is truncated 4372 * based on the address size of the instruction. Note that this is 4373 * the *effective address*, i.e. the address prior to accounting for 4374 * the segment's base. 4375 */ 4376 if (addr_size == 1) /* 32 bit */ 4377 off &= 0xffffffff; 4378 else if (addr_size == 0) /* 16 bit */ 4379 off &= 0xffff; 4380 4381 /* Checks for #GP/#SS exceptions. */ 4382 exn = false; 4383 if (is_long_mode(vcpu)) { 4384 /* 4385 * The virtual/linear address is never truncated in 64-bit 4386 * mode, e.g. a 32-bit address size can yield a 64-bit virtual 4387 * address when using FS/GS with a non-zero base. 4388 */ 4389 if (seg_reg == VCPU_SREG_FS || seg_reg == VCPU_SREG_GS) 4390 *ret = s.base + off; 4391 else 4392 *ret = off; 4393 4394 /* Long mode: #GP(0)/#SS(0) if the memory address is in a 4395 * non-canonical form. This is the only check on the memory 4396 * destination for long mode! 4397 */ 4398 exn = is_noncanonical_address(*ret, vcpu); 4399 } else { 4400 /* 4401 * When not in long mode, the virtual/linear address is 4402 * unconditionally truncated to 32 bits regardless of the 4403 * address size. 4404 */ 4405 *ret = (s.base + off) & 0xffffffff; 4406 4407 /* Protected mode: apply checks for segment validity in the 4408 * following order: 4409 * - segment type check (#GP(0) may be thrown) 4410 * - usability check (#GP(0)/#SS(0)) 4411 * - limit check (#GP(0)/#SS(0)) 4412 */ 4413 if (wr) 4414 /* #GP(0) if the destination operand is located in a 4415 * read-only data segment or any code segment. 4416 */ 4417 exn = ((s.type & 0xa) == 0 || (s.type & 8)); 4418 else 4419 /* #GP(0) if the source operand is located in an 4420 * execute-only code segment 4421 */ 4422 exn = ((s.type & 0xa) == 8); 4423 if (exn) { 4424 kvm_queue_exception_e(vcpu, GP_VECTOR, 0); 4425 return 1; 4426 } 4427 /* Protected mode: #GP(0)/#SS(0) if the segment is unusable. 4428 */ 4429 exn = (s.unusable != 0); 4430 4431 /* 4432 * Protected mode: #GP(0)/#SS(0) if the memory operand is 4433 * outside the segment limit. All CPUs that support VMX ignore 4434 * limit checks for flat segments, i.e. segments with base==0, 4435 * limit==0xffffffff and of type expand-up data or code. 4436 */ 4437 if (!(s.base == 0 && s.limit == 0xffffffff && 4438 ((s.type & 8) || !(s.type & 4)))) 4439 exn = exn || ((u64)off + len - 1 > s.limit); 4440 } 4441 if (exn) { 4442 kvm_queue_exception_e(vcpu, 4443 seg_reg == VCPU_SREG_SS ? 4444 SS_VECTOR : GP_VECTOR, 4445 0); 4446 return 1; 4447 } 4448 4449 return 0; 4450 } 4451 4452 void nested_vmx_pmu_entry_exit_ctls_update(struct kvm_vcpu *vcpu) 4453 { 4454 struct vcpu_vmx *vmx; 4455 4456 if (!nested_vmx_allowed(vcpu)) 4457 return; 4458 4459 vmx = to_vmx(vcpu); 4460 if (kvm_x86_ops->pmu_ops->is_valid_msr(vcpu, MSR_CORE_PERF_GLOBAL_CTRL)) { 4461 vmx->nested.msrs.entry_ctls_high |= 4462 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL; 4463 vmx->nested.msrs.exit_ctls_high |= 4464 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL; 4465 } else { 4466 vmx->nested.msrs.entry_ctls_high &= 4467 ~VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL; 4468 vmx->nested.msrs.exit_ctls_high &= 4469 ~VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL; 4470 } 4471 } 4472 4473 static int nested_vmx_get_vmptr(struct kvm_vcpu *vcpu, gpa_t *vmpointer) 4474 { 4475 gva_t gva; 4476 struct x86_exception e; 4477 4478 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION), 4479 vmcs_read32(VMX_INSTRUCTION_INFO), false, 4480 sizeof(*vmpointer), &gva)) 4481 return 1; 4482 4483 if (kvm_read_guest_virt(vcpu, gva, vmpointer, sizeof(*vmpointer), &e)) { 4484 kvm_inject_page_fault(vcpu, &e); 4485 return 1; 4486 } 4487 4488 return 0; 4489 } 4490 4491 /* 4492 * Allocate a shadow VMCS and associate it with the currently loaded 4493 * VMCS, unless such a shadow VMCS already exists. The newly allocated 4494 * VMCS is also VMCLEARed, so that it is ready for use. 4495 */ 4496 static struct vmcs *alloc_shadow_vmcs(struct kvm_vcpu *vcpu) 4497 { 4498 struct vcpu_vmx *vmx = to_vmx(vcpu); 4499 struct loaded_vmcs *loaded_vmcs = vmx->loaded_vmcs; 4500 4501 /* 4502 * We should allocate a shadow vmcs for vmcs01 only when L1 4503 * executes VMXON and free it when L1 executes VMXOFF. 4504 * As it is invalid to execute VMXON twice, we shouldn't reach 4505 * here when vmcs01 already have an allocated shadow vmcs. 4506 */ 4507 WARN_ON(loaded_vmcs == &vmx->vmcs01 && loaded_vmcs->shadow_vmcs); 4508 4509 if (!loaded_vmcs->shadow_vmcs) { 4510 loaded_vmcs->shadow_vmcs = alloc_vmcs(true); 4511 if (loaded_vmcs->shadow_vmcs) 4512 vmcs_clear(loaded_vmcs->shadow_vmcs); 4513 } 4514 return loaded_vmcs->shadow_vmcs; 4515 } 4516 4517 static int enter_vmx_operation(struct kvm_vcpu *vcpu) 4518 { 4519 struct vcpu_vmx *vmx = to_vmx(vcpu); 4520 int r; 4521 4522 r = alloc_loaded_vmcs(&vmx->nested.vmcs02); 4523 if (r < 0) 4524 goto out_vmcs02; 4525 4526 vmx->nested.cached_vmcs12 = kzalloc(VMCS12_SIZE, GFP_KERNEL_ACCOUNT); 4527 if (!vmx->nested.cached_vmcs12) 4528 goto out_cached_vmcs12; 4529 4530 vmx->nested.cached_shadow_vmcs12 = kzalloc(VMCS12_SIZE, GFP_KERNEL_ACCOUNT); 4531 if (!vmx->nested.cached_shadow_vmcs12) 4532 goto out_cached_shadow_vmcs12; 4533 4534 if (enable_shadow_vmcs && !alloc_shadow_vmcs(vcpu)) 4535 goto out_shadow_vmcs; 4536 4537 hrtimer_init(&vmx->nested.preemption_timer, CLOCK_MONOTONIC, 4538 HRTIMER_MODE_REL_PINNED); 4539 vmx->nested.preemption_timer.function = vmx_preemption_timer_fn; 4540 4541 vmx->nested.vpid02 = allocate_vpid(); 4542 4543 vmx->nested.vmcs02_initialized = false; 4544 vmx->nested.vmxon = true; 4545 4546 if (pt_mode == PT_MODE_HOST_GUEST) { 4547 vmx->pt_desc.guest.ctl = 0; 4548 pt_update_intercept_for_msr(vmx); 4549 } 4550 4551 return 0; 4552 4553 out_shadow_vmcs: 4554 kfree(vmx->nested.cached_shadow_vmcs12); 4555 4556 out_cached_shadow_vmcs12: 4557 kfree(vmx->nested.cached_vmcs12); 4558 4559 out_cached_vmcs12: 4560 free_loaded_vmcs(&vmx->nested.vmcs02); 4561 4562 out_vmcs02: 4563 return -ENOMEM; 4564 } 4565 4566 /* 4567 * Emulate the VMXON instruction. 4568 * Currently, we just remember that VMX is active, and do not save or even 4569 * inspect the argument to VMXON (the so-called "VMXON pointer") because we 4570 * do not currently need to store anything in that guest-allocated memory 4571 * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their 4572 * argument is different from the VMXON pointer (which the spec says they do). 4573 */ 4574 static int handle_vmon(struct kvm_vcpu *vcpu) 4575 { 4576 int ret; 4577 gpa_t vmptr; 4578 uint32_t revision; 4579 struct vcpu_vmx *vmx = to_vmx(vcpu); 4580 const u64 VMXON_NEEDED_FEATURES = FEAT_CTL_LOCKED 4581 | FEAT_CTL_VMX_ENABLED_OUTSIDE_SMX; 4582 4583 /* 4584 * The Intel VMX Instruction Reference lists a bunch of bits that are 4585 * prerequisite to running VMXON, most notably cr4.VMXE must be set to 4586 * 1 (see vmx_set_cr4() for when we allow the guest to set this). 4587 * Otherwise, we should fail with #UD. But most faulting conditions 4588 * have already been checked by hardware, prior to the VM-exit for 4589 * VMXON. We do test guest cr4.VMXE because processor CR4 always has 4590 * that bit set to 1 in non-root mode. 4591 */ 4592 if (!kvm_read_cr4_bits(vcpu, X86_CR4_VMXE)) { 4593 kvm_queue_exception(vcpu, UD_VECTOR); 4594 return 1; 4595 } 4596 4597 /* CPL=0 must be checked manually. */ 4598 if (vmx_get_cpl(vcpu)) { 4599 kvm_inject_gp(vcpu, 0); 4600 return 1; 4601 } 4602 4603 if (vmx->nested.vmxon) 4604 return nested_vmx_failValid(vcpu, 4605 VMXERR_VMXON_IN_VMX_ROOT_OPERATION); 4606 4607 if ((vmx->msr_ia32_feature_control & VMXON_NEEDED_FEATURES) 4608 != VMXON_NEEDED_FEATURES) { 4609 kvm_inject_gp(vcpu, 0); 4610 return 1; 4611 } 4612 4613 if (nested_vmx_get_vmptr(vcpu, &vmptr)) 4614 return 1; 4615 4616 /* 4617 * SDM 3: 24.11.5 4618 * The first 4 bytes of VMXON region contain the supported 4619 * VMCS revision identifier 4620 * 4621 * Note - IA32_VMX_BASIC[48] will never be 1 for the nested case; 4622 * which replaces physical address width with 32 4623 */ 4624 if (!page_address_valid(vcpu, vmptr)) 4625 return nested_vmx_failInvalid(vcpu); 4626 4627 if (kvm_read_guest(vcpu->kvm, vmptr, &revision, sizeof(revision)) || 4628 revision != VMCS12_REVISION) 4629 return nested_vmx_failInvalid(vcpu); 4630 4631 vmx->nested.vmxon_ptr = vmptr; 4632 ret = enter_vmx_operation(vcpu); 4633 if (ret) 4634 return ret; 4635 4636 return nested_vmx_succeed(vcpu); 4637 } 4638 4639 static inline void nested_release_vmcs12(struct kvm_vcpu *vcpu) 4640 { 4641 struct vcpu_vmx *vmx = to_vmx(vcpu); 4642 4643 if (vmx->nested.current_vmptr == -1ull) 4644 return; 4645 4646 copy_vmcs02_to_vmcs12_rare(vcpu, get_vmcs12(vcpu)); 4647 4648 if (enable_shadow_vmcs) { 4649 /* copy to memory all shadowed fields in case 4650 they were modified */ 4651 copy_shadow_to_vmcs12(vmx); 4652 vmx_disable_shadow_vmcs(vmx); 4653 } 4654 vmx->nested.posted_intr_nv = -1; 4655 4656 /* Flush VMCS12 to guest memory */ 4657 kvm_vcpu_write_guest_page(vcpu, 4658 vmx->nested.current_vmptr >> PAGE_SHIFT, 4659 vmx->nested.cached_vmcs12, 0, VMCS12_SIZE); 4660 4661 kvm_mmu_free_roots(vcpu, &vcpu->arch.guest_mmu, KVM_MMU_ROOTS_ALL); 4662 4663 vmx->nested.current_vmptr = -1ull; 4664 } 4665 4666 /* Emulate the VMXOFF instruction */ 4667 static int handle_vmoff(struct kvm_vcpu *vcpu) 4668 { 4669 if (!nested_vmx_check_permission(vcpu)) 4670 return 1; 4671 4672 free_nested(vcpu); 4673 4674 /* Process a latched INIT during time CPU was in VMX operation */ 4675 kvm_make_request(KVM_REQ_EVENT, vcpu); 4676 4677 return nested_vmx_succeed(vcpu); 4678 } 4679 4680 /* Emulate the VMCLEAR instruction */ 4681 static int handle_vmclear(struct kvm_vcpu *vcpu) 4682 { 4683 struct vcpu_vmx *vmx = to_vmx(vcpu); 4684 u32 zero = 0; 4685 gpa_t vmptr; 4686 u64 evmcs_gpa; 4687 4688 if (!nested_vmx_check_permission(vcpu)) 4689 return 1; 4690 4691 if (nested_vmx_get_vmptr(vcpu, &vmptr)) 4692 return 1; 4693 4694 if (!page_address_valid(vcpu, vmptr)) 4695 return nested_vmx_failValid(vcpu, 4696 VMXERR_VMCLEAR_INVALID_ADDRESS); 4697 4698 if (vmptr == vmx->nested.vmxon_ptr) 4699 return nested_vmx_failValid(vcpu, 4700 VMXERR_VMCLEAR_VMXON_POINTER); 4701 4702 /* 4703 * When Enlightened VMEntry is enabled on the calling CPU we treat 4704 * memory area pointer by vmptr as Enlightened VMCS (as there's no good 4705 * way to distinguish it from VMCS12) and we must not corrupt it by 4706 * writing to the non-existent 'launch_state' field. The area doesn't 4707 * have to be the currently active EVMCS on the calling CPU and there's 4708 * nothing KVM has to do to transition it from 'active' to 'non-active' 4709 * state. It is possible that the area will stay mapped as 4710 * vmx->nested.hv_evmcs but this shouldn't be a problem. 4711 */ 4712 if (likely(!vmx->nested.enlightened_vmcs_enabled || 4713 !nested_enlightened_vmentry(vcpu, &evmcs_gpa))) { 4714 if (vmptr == vmx->nested.current_vmptr) 4715 nested_release_vmcs12(vcpu); 4716 4717 kvm_vcpu_write_guest(vcpu, 4718 vmptr + offsetof(struct vmcs12, 4719 launch_state), 4720 &zero, sizeof(zero)); 4721 } 4722 4723 return nested_vmx_succeed(vcpu); 4724 } 4725 4726 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch); 4727 4728 /* Emulate the VMLAUNCH instruction */ 4729 static int handle_vmlaunch(struct kvm_vcpu *vcpu) 4730 { 4731 return nested_vmx_run(vcpu, true); 4732 } 4733 4734 /* Emulate the VMRESUME instruction */ 4735 static int handle_vmresume(struct kvm_vcpu *vcpu) 4736 { 4737 4738 return nested_vmx_run(vcpu, false); 4739 } 4740 4741 static int handle_vmread(struct kvm_vcpu *vcpu) 4742 { 4743 struct vmcs12 *vmcs12 = is_guest_mode(vcpu) ? get_shadow_vmcs12(vcpu) 4744 : get_vmcs12(vcpu); 4745 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION); 4746 u32 instr_info = vmcs_read32(VMX_INSTRUCTION_INFO); 4747 struct vcpu_vmx *vmx = to_vmx(vcpu); 4748 struct x86_exception e; 4749 unsigned long field; 4750 u64 value; 4751 gva_t gva = 0; 4752 short offset; 4753 int len; 4754 4755 if (!nested_vmx_check_permission(vcpu)) 4756 return 1; 4757 4758 /* 4759 * In VMX non-root operation, when the VMCS-link pointer is -1ull, 4760 * any VMREAD sets the ALU flags for VMfailInvalid. 4761 */ 4762 if (vmx->nested.current_vmptr == -1ull || 4763 (is_guest_mode(vcpu) && 4764 get_vmcs12(vcpu)->vmcs_link_pointer == -1ull)) 4765 return nested_vmx_failInvalid(vcpu); 4766 4767 /* Decode instruction info and find the field to read */ 4768 field = kvm_register_readl(vcpu, (((instr_info) >> 28) & 0xf)); 4769 4770 offset = vmcs_field_to_offset(field); 4771 if (offset < 0) 4772 return nested_vmx_failValid(vcpu, 4773 VMXERR_UNSUPPORTED_VMCS_COMPONENT); 4774 4775 if (!is_guest_mode(vcpu) && is_vmcs12_ext_field(field)) 4776 copy_vmcs02_to_vmcs12_rare(vcpu, vmcs12); 4777 4778 /* Read the field, zero-extended to a u64 value */ 4779 value = vmcs12_read_any(vmcs12, field, offset); 4780 4781 /* 4782 * Now copy part of this value to register or memory, as requested. 4783 * Note that the number of bits actually copied is 32 or 64 depending 4784 * on the guest's mode (32 or 64 bit), not on the given field's length. 4785 */ 4786 if (instr_info & BIT(10)) { 4787 kvm_register_writel(vcpu, (((instr_info) >> 3) & 0xf), value); 4788 } else { 4789 len = is_64_bit_mode(vcpu) ? 8 : 4; 4790 if (get_vmx_mem_address(vcpu, exit_qualification, 4791 instr_info, true, len, &gva)) 4792 return 1; 4793 /* _system ok, nested_vmx_check_permission has verified cpl=0 */ 4794 if (kvm_write_guest_virt_system(vcpu, gva, &value, len, &e)) { 4795 kvm_inject_page_fault(vcpu, &e); 4796 return 1; 4797 } 4798 } 4799 4800 return nested_vmx_succeed(vcpu); 4801 } 4802 4803 static bool is_shadow_field_rw(unsigned long field) 4804 { 4805 switch (field) { 4806 #define SHADOW_FIELD_RW(x, y) case x: 4807 #include "vmcs_shadow_fields.h" 4808 return true; 4809 default: 4810 break; 4811 } 4812 return false; 4813 } 4814 4815 static bool is_shadow_field_ro(unsigned long field) 4816 { 4817 switch (field) { 4818 #define SHADOW_FIELD_RO(x, y) case x: 4819 #include "vmcs_shadow_fields.h" 4820 return true; 4821 default: 4822 break; 4823 } 4824 return false; 4825 } 4826 4827 static int handle_vmwrite(struct kvm_vcpu *vcpu) 4828 { 4829 struct vmcs12 *vmcs12 = is_guest_mode(vcpu) ? get_shadow_vmcs12(vcpu) 4830 : get_vmcs12(vcpu); 4831 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION); 4832 u32 instr_info = vmcs_read32(VMX_INSTRUCTION_INFO); 4833 struct vcpu_vmx *vmx = to_vmx(vcpu); 4834 struct x86_exception e; 4835 unsigned long field; 4836 short offset; 4837 gva_t gva; 4838 int len; 4839 4840 /* 4841 * The value to write might be 32 or 64 bits, depending on L1's long 4842 * mode, and eventually we need to write that into a field of several 4843 * possible lengths. The code below first zero-extends the value to 64 4844 * bit (value), and then copies only the appropriate number of 4845 * bits into the vmcs12 field. 4846 */ 4847 u64 value = 0; 4848 4849 if (!nested_vmx_check_permission(vcpu)) 4850 return 1; 4851 4852 /* 4853 * In VMX non-root operation, when the VMCS-link pointer is -1ull, 4854 * any VMWRITE sets the ALU flags for VMfailInvalid. 4855 */ 4856 if (vmx->nested.current_vmptr == -1ull || 4857 (is_guest_mode(vcpu) && 4858 get_vmcs12(vcpu)->vmcs_link_pointer == -1ull)) 4859 return nested_vmx_failInvalid(vcpu); 4860 4861 if (instr_info & BIT(10)) 4862 value = kvm_register_readl(vcpu, (((instr_info) >> 3) & 0xf)); 4863 else { 4864 len = is_64_bit_mode(vcpu) ? 8 : 4; 4865 if (get_vmx_mem_address(vcpu, exit_qualification, 4866 instr_info, false, len, &gva)) 4867 return 1; 4868 if (kvm_read_guest_virt(vcpu, gva, &value, len, &e)) { 4869 kvm_inject_page_fault(vcpu, &e); 4870 return 1; 4871 } 4872 } 4873 4874 field = kvm_register_readl(vcpu, (((instr_info) >> 28) & 0xf)); 4875 4876 offset = vmcs_field_to_offset(field); 4877 if (offset < 0) 4878 return nested_vmx_failValid(vcpu, 4879 VMXERR_UNSUPPORTED_VMCS_COMPONENT); 4880 4881 /* 4882 * If the vCPU supports "VMWRITE to any supported field in the 4883 * VMCS," then the "read-only" fields are actually read/write. 4884 */ 4885 if (vmcs_field_readonly(field) && 4886 !nested_cpu_has_vmwrite_any_field(vcpu)) 4887 return nested_vmx_failValid(vcpu, 4888 VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT); 4889 4890 /* 4891 * Ensure vmcs12 is up-to-date before any VMWRITE that dirties 4892 * vmcs12, else we may crush a field or consume a stale value. 4893 */ 4894 if (!is_guest_mode(vcpu) && !is_shadow_field_rw(field)) 4895 copy_vmcs02_to_vmcs12_rare(vcpu, vmcs12); 4896 4897 /* 4898 * Some Intel CPUs intentionally drop the reserved bits of the AR byte 4899 * fields on VMWRITE. Emulate this behavior to ensure consistent KVM 4900 * behavior regardless of the underlying hardware, e.g. if an AR_BYTE 4901 * field is intercepted for VMWRITE but not VMREAD (in L1), then VMREAD 4902 * from L1 will return a different value than VMREAD from L2 (L1 sees 4903 * the stripped down value, L2 sees the full value as stored by KVM). 4904 */ 4905 if (field >= GUEST_ES_AR_BYTES && field <= GUEST_TR_AR_BYTES) 4906 value &= 0x1f0ff; 4907 4908 vmcs12_write_any(vmcs12, field, offset, value); 4909 4910 /* 4911 * Do not track vmcs12 dirty-state if in guest-mode as we actually 4912 * dirty shadow vmcs12 instead of vmcs12. Fields that can be updated 4913 * by L1 without a vmexit are always updated in the vmcs02, i.e. don't 4914 * "dirty" vmcs12, all others go down the prepare_vmcs02() slow path. 4915 */ 4916 if (!is_guest_mode(vcpu) && !is_shadow_field_rw(field)) { 4917 /* 4918 * L1 can read these fields without exiting, ensure the 4919 * shadow VMCS is up-to-date. 4920 */ 4921 if (enable_shadow_vmcs && is_shadow_field_ro(field)) { 4922 preempt_disable(); 4923 vmcs_load(vmx->vmcs01.shadow_vmcs); 4924 4925 __vmcs_writel(field, value); 4926 4927 vmcs_clear(vmx->vmcs01.shadow_vmcs); 4928 vmcs_load(vmx->loaded_vmcs->vmcs); 4929 preempt_enable(); 4930 } 4931 vmx->nested.dirty_vmcs12 = true; 4932 } 4933 4934 return nested_vmx_succeed(vcpu); 4935 } 4936 4937 static void set_current_vmptr(struct vcpu_vmx *vmx, gpa_t vmptr) 4938 { 4939 vmx->nested.current_vmptr = vmptr; 4940 if (enable_shadow_vmcs) { 4941 secondary_exec_controls_setbit(vmx, SECONDARY_EXEC_SHADOW_VMCS); 4942 vmcs_write64(VMCS_LINK_POINTER, 4943 __pa(vmx->vmcs01.shadow_vmcs)); 4944 vmx->nested.need_vmcs12_to_shadow_sync = true; 4945 } 4946 vmx->nested.dirty_vmcs12 = true; 4947 } 4948 4949 /* Emulate the VMPTRLD instruction */ 4950 static int handle_vmptrld(struct kvm_vcpu *vcpu) 4951 { 4952 struct vcpu_vmx *vmx = to_vmx(vcpu); 4953 gpa_t vmptr; 4954 4955 if (!nested_vmx_check_permission(vcpu)) 4956 return 1; 4957 4958 if (nested_vmx_get_vmptr(vcpu, &vmptr)) 4959 return 1; 4960 4961 if (!page_address_valid(vcpu, vmptr)) 4962 return nested_vmx_failValid(vcpu, 4963 VMXERR_VMPTRLD_INVALID_ADDRESS); 4964 4965 if (vmptr == vmx->nested.vmxon_ptr) 4966 return nested_vmx_failValid(vcpu, 4967 VMXERR_VMPTRLD_VMXON_POINTER); 4968 4969 /* Forbid normal VMPTRLD if Enlightened version was used */ 4970 if (vmx->nested.hv_evmcs) 4971 return 1; 4972 4973 if (vmx->nested.current_vmptr != vmptr) { 4974 struct kvm_host_map map; 4975 struct vmcs12 *new_vmcs12; 4976 4977 if (kvm_vcpu_map(vcpu, gpa_to_gfn(vmptr), &map)) { 4978 /* 4979 * Reads from an unbacked page return all 1s, 4980 * which means that the 32 bits located at the 4981 * given physical address won't match the required 4982 * VMCS12_REVISION identifier. 4983 */ 4984 return nested_vmx_failValid(vcpu, 4985 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID); 4986 } 4987 4988 new_vmcs12 = map.hva; 4989 4990 if (new_vmcs12->hdr.revision_id != VMCS12_REVISION || 4991 (new_vmcs12->hdr.shadow_vmcs && 4992 !nested_cpu_has_vmx_shadow_vmcs(vcpu))) { 4993 kvm_vcpu_unmap(vcpu, &map, false); 4994 return nested_vmx_failValid(vcpu, 4995 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID); 4996 } 4997 4998 nested_release_vmcs12(vcpu); 4999 5000 /* 5001 * Load VMCS12 from guest memory since it is not already 5002 * cached. 5003 */ 5004 memcpy(vmx->nested.cached_vmcs12, new_vmcs12, VMCS12_SIZE); 5005 kvm_vcpu_unmap(vcpu, &map, false); 5006 5007 set_current_vmptr(vmx, vmptr); 5008 } 5009 5010 return nested_vmx_succeed(vcpu); 5011 } 5012 5013 /* Emulate the VMPTRST instruction */ 5014 static int handle_vmptrst(struct kvm_vcpu *vcpu) 5015 { 5016 unsigned long exit_qual = vmcs_readl(EXIT_QUALIFICATION); 5017 u32 instr_info = vmcs_read32(VMX_INSTRUCTION_INFO); 5018 gpa_t current_vmptr = to_vmx(vcpu)->nested.current_vmptr; 5019 struct x86_exception e; 5020 gva_t gva; 5021 5022 if (!nested_vmx_check_permission(vcpu)) 5023 return 1; 5024 5025 if (unlikely(to_vmx(vcpu)->nested.hv_evmcs)) 5026 return 1; 5027 5028 if (get_vmx_mem_address(vcpu, exit_qual, instr_info, 5029 true, sizeof(gpa_t), &gva)) 5030 return 1; 5031 /* *_system ok, nested_vmx_check_permission has verified cpl=0 */ 5032 if (kvm_write_guest_virt_system(vcpu, gva, (void *)¤t_vmptr, 5033 sizeof(gpa_t), &e)) { 5034 kvm_inject_page_fault(vcpu, &e); 5035 return 1; 5036 } 5037 return nested_vmx_succeed(vcpu); 5038 } 5039 5040 /* Emulate the INVEPT instruction */ 5041 static int handle_invept(struct kvm_vcpu *vcpu) 5042 { 5043 struct vcpu_vmx *vmx = to_vmx(vcpu); 5044 u32 vmx_instruction_info, types; 5045 unsigned long type; 5046 gva_t gva; 5047 struct x86_exception e; 5048 struct { 5049 u64 eptp, gpa; 5050 } operand; 5051 5052 if (!(vmx->nested.msrs.secondary_ctls_high & 5053 SECONDARY_EXEC_ENABLE_EPT) || 5054 !(vmx->nested.msrs.ept_caps & VMX_EPT_INVEPT_BIT)) { 5055 kvm_queue_exception(vcpu, UD_VECTOR); 5056 return 1; 5057 } 5058 5059 if (!nested_vmx_check_permission(vcpu)) 5060 return 1; 5061 5062 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO); 5063 type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf); 5064 5065 types = (vmx->nested.msrs.ept_caps >> VMX_EPT_EXTENT_SHIFT) & 6; 5066 5067 if (type >= 32 || !(types & (1 << type))) 5068 return nested_vmx_failValid(vcpu, 5069 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID); 5070 5071 /* According to the Intel VMX instruction reference, the memory 5072 * operand is read even if it isn't needed (e.g., for type==global) 5073 */ 5074 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION), 5075 vmx_instruction_info, false, sizeof(operand), &gva)) 5076 return 1; 5077 if (kvm_read_guest_virt(vcpu, gva, &operand, sizeof(operand), &e)) { 5078 kvm_inject_page_fault(vcpu, &e); 5079 return 1; 5080 } 5081 5082 switch (type) { 5083 case VMX_EPT_EXTENT_GLOBAL: 5084 case VMX_EPT_EXTENT_CONTEXT: 5085 /* 5086 * TODO: Sync the necessary shadow EPT roots here, rather than 5087 * at the next emulated VM-entry. 5088 */ 5089 break; 5090 default: 5091 BUG_ON(1); 5092 break; 5093 } 5094 5095 return nested_vmx_succeed(vcpu); 5096 } 5097 5098 static int handle_invvpid(struct kvm_vcpu *vcpu) 5099 { 5100 struct vcpu_vmx *vmx = to_vmx(vcpu); 5101 u32 vmx_instruction_info; 5102 unsigned long type, types; 5103 gva_t gva; 5104 struct x86_exception e; 5105 struct { 5106 u64 vpid; 5107 u64 gla; 5108 } operand; 5109 u16 vpid02; 5110 5111 if (!(vmx->nested.msrs.secondary_ctls_high & 5112 SECONDARY_EXEC_ENABLE_VPID) || 5113 !(vmx->nested.msrs.vpid_caps & VMX_VPID_INVVPID_BIT)) { 5114 kvm_queue_exception(vcpu, UD_VECTOR); 5115 return 1; 5116 } 5117 5118 if (!nested_vmx_check_permission(vcpu)) 5119 return 1; 5120 5121 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO); 5122 type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf); 5123 5124 types = (vmx->nested.msrs.vpid_caps & 5125 VMX_VPID_EXTENT_SUPPORTED_MASK) >> 8; 5126 5127 if (type >= 32 || !(types & (1 << type))) 5128 return nested_vmx_failValid(vcpu, 5129 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID); 5130 5131 /* according to the intel vmx instruction reference, the memory 5132 * operand is read even if it isn't needed (e.g., for type==global) 5133 */ 5134 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION), 5135 vmx_instruction_info, false, sizeof(operand), &gva)) 5136 return 1; 5137 if (kvm_read_guest_virt(vcpu, gva, &operand, sizeof(operand), &e)) { 5138 kvm_inject_page_fault(vcpu, &e); 5139 return 1; 5140 } 5141 if (operand.vpid >> 16) 5142 return nested_vmx_failValid(vcpu, 5143 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID); 5144 5145 vpid02 = nested_get_vpid02(vcpu); 5146 switch (type) { 5147 case VMX_VPID_EXTENT_INDIVIDUAL_ADDR: 5148 if (!operand.vpid || 5149 is_noncanonical_address(operand.gla, vcpu)) 5150 return nested_vmx_failValid(vcpu, 5151 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID); 5152 if (cpu_has_vmx_invvpid_individual_addr()) { 5153 __invvpid(VMX_VPID_EXTENT_INDIVIDUAL_ADDR, 5154 vpid02, operand.gla); 5155 } else 5156 __vmx_flush_tlb(vcpu, vpid02, false); 5157 break; 5158 case VMX_VPID_EXTENT_SINGLE_CONTEXT: 5159 case VMX_VPID_EXTENT_SINGLE_NON_GLOBAL: 5160 if (!operand.vpid) 5161 return nested_vmx_failValid(vcpu, 5162 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID); 5163 __vmx_flush_tlb(vcpu, vpid02, false); 5164 break; 5165 case VMX_VPID_EXTENT_ALL_CONTEXT: 5166 __vmx_flush_tlb(vcpu, vpid02, false); 5167 break; 5168 default: 5169 WARN_ON_ONCE(1); 5170 return kvm_skip_emulated_instruction(vcpu); 5171 } 5172 5173 return nested_vmx_succeed(vcpu); 5174 } 5175 5176 static int nested_vmx_eptp_switching(struct kvm_vcpu *vcpu, 5177 struct vmcs12 *vmcs12) 5178 { 5179 u32 index = kvm_rcx_read(vcpu); 5180 u64 address; 5181 bool accessed_dirty; 5182 struct kvm_mmu *mmu = vcpu->arch.walk_mmu; 5183 5184 if (!nested_cpu_has_eptp_switching(vmcs12) || 5185 !nested_cpu_has_ept(vmcs12)) 5186 return 1; 5187 5188 if (index >= VMFUNC_EPTP_ENTRIES) 5189 return 1; 5190 5191 5192 if (kvm_vcpu_read_guest_page(vcpu, vmcs12->eptp_list_address >> PAGE_SHIFT, 5193 &address, index * 8, 8)) 5194 return 1; 5195 5196 accessed_dirty = !!(address & VMX_EPTP_AD_ENABLE_BIT); 5197 5198 /* 5199 * If the (L2) guest does a vmfunc to the currently 5200 * active ept pointer, we don't have to do anything else 5201 */ 5202 if (vmcs12->ept_pointer != address) { 5203 if (!valid_ept_address(vcpu, address)) 5204 return 1; 5205 5206 kvm_mmu_unload(vcpu); 5207 mmu->ept_ad = accessed_dirty; 5208 mmu->mmu_role.base.ad_disabled = !accessed_dirty; 5209 vmcs12->ept_pointer = address; 5210 /* 5211 * TODO: Check what's the correct approach in case 5212 * mmu reload fails. Currently, we just let the next 5213 * reload potentially fail 5214 */ 5215 kvm_mmu_reload(vcpu); 5216 } 5217 5218 return 0; 5219 } 5220 5221 static int handle_vmfunc(struct kvm_vcpu *vcpu) 5222 { 5223 struct vcpu_vmx *vmx = to_vmx(vcpu); 5224 struct vmcs12 *vmcs12; 5225 u32 function = kvm_rax_read(vcpu); 5226 5227 /* 5228 * VMFUNC is only supported for nested guests, but we always enable the 5229 * secondary control for simplicity; for non-nested mode, fake that we 5230 * didn't by injecting #UD. 5231 */ 5232 if (!is_guest_mode(vcpu)) { 5233 kvm_queue_exception(vcpu, UD_VECTOR); 5234 return 1; 5235 } 5236 5237 vmcs12 = get_vmcs12(vcpu); 5238 if ((vmcs12->vm_function_control & (1 << function)) == 0) 5239 goto fail; 5240 5241 switch (function) { 5242 case 0: 5243 if (nested_vmx_eptp_switching(vcpu, vmcs12)) 5244 goto fail; 5245 break; 5246 default: 5247 goto fail; 5248 } 5249 return kvm_skip_emulated_instruction(vcpu); 5250 5251 fail: 5252 nested_vmx_vmexit(vcpu, vmx->exit_reason, 5253 vmcs_read32(VM_EXIT_INTR_INFO), 5254 vmcs_readl(EXIT_QUALIFICATION)); 5255 return 1; 5256 } 5257 5258 5259 static bool nested_vmx_exit_handled_io(struct kvm_vcpu *vcpu, 5260 struct vmcs12 *vmcs12) 5261 { 5262 unsigned long exit_qualification; 5263 gpa_t bitmap, last_bitmap; 5264 unsigned int port; 5265 int size; 5266 u8 b; 5267 5268 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS)) 5269 return nested_cpu_has(vmcs12, CPU_BASED_UNCOND_IO_EXITING); 5270 5271 exit_qualification = vmcs_readl(EXIT_QUALIFICATION); 5272 5273 port = exit_qualification >> 16; 5274 size = (exit_qualification & 7) + 1; 5275 5276 last_bitmap = (gpa_t)-1; 5277 b = -1; 5278 5279 while (size > 0) { 5280 if (port < 0x8000) 5281 bitmap = vmcs12->io_bitmap_a; 5282 else if (port < 0x10000) 5283 bitmap = vmcs12->io_bitmap_b; 5284 else 5285 return true; 5286 bitmap += (port & 0x7fff) / 8; 5287 5288 if (last_bitmap != bitmap) 5289 if (kvm_vcpu_read_guest(vcpu, bitmap, &b, 1)) 5290 return true; 5291 if (b & (1 << (port & 7))) 5292 return true; 5293 5294 port++; 5295 size--; 5296 last_bitmap = bitmap; 5297 } 5298 5299 return false; 5300 } 5301 5302 /* 5303 * Return 1 if we should exit from L2 to L1 to handle an MSR access access, 5304 * rather than handle it ourselves in L0. I.e., check whether L1 expressed 5305 * disinterest in the current event (read or write a specific MSR) by using an 5306 * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps. 5307 */ 5308 static bool nested_vmx_exit_handled_msr(struct kvm_vcpu *vcpu, 5309 struct vmcs12 *vmcs12, u32 exit_reason) 5310 { 5311 u32 msr_index = kvm_rcx_read(vcpu); 5312 gpa_t bitmap; 5313 5314 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS)) 5315 return true; 5316 5317 /* 5318 * The MSR_BITMAP page is divided into four 1024-byte bitmaps, 5319 * for the four combinations of read/write and low/high MSR numbers. 5320 * First we need to figure out which of the four to use: 5321 */ 5322 bitmap = vmcs12->msr_bitmap; 5323 if (exit_reason == EXIT_REASON_MSR_WRITE) 5324 bitmap += 2048; 5325 if (msr_index >= 0xc0000000) { 5326 msr_index -= 0xc0000000; 5327 bitmap += 1024; 5328 } 5329 5330 /* Then read the msr_index'th bit from this bitmap: */ 5331 if (msr_index < 1024*8) { 5332 unsigned char b; 5333 if (kvm_vcpu_read_guest(vcpu, bitmap + msr_index/8, &b, 1)) 5334 return true; 5335 return 1 & (b >> (msr_index & 7)); 5336 } else 5337 return true; /* let L1 handle the wrong parameter */ 5338 } 5339 5340 /* 5341 * Return 1 if we should exit from L2 to L1 to handle a CR access exit, 5342 * rather than handle it ourselves in L0. I.e., check if L1 wanted to 5343 * intercept (via guest_host_mask etc.) the current event. 5344 */ 5345 static bool nested_vmx_exit_handled_cr(struct kvm_vcpu *vcpu, 5346 struct vmcs12 *vmcs12) 5347 { 5348 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION); 5349 int cr = exit_qualification & 15; 5350 int reg; 5351 unsigned long val; 5352 5353 switch ((exit_qualification >> 4) & 3) { 5354 case 0: /* mov to cr */ 5355 reg = (exit_qualification >> 8) & 15; 5356 val = kvm_register_readl(vcpu, reg); 5357 switch (cr) { 5358 case 0: 5359 if (vmcs12->cr0_guest_host_mask & 5360 (val ^ vmcs12->cr0_read_shadow)) 5361 return true; 5362 break; 5363 case 3: 5364 if ((vmcs12->cr3_target_count >= 1 && 5365 vmcs12->cr3_target_value0 == val) || 5366 (vmcs12->cr3_target_count >= 2 && 5367 vmcs12->cr3_target_value1 == val) || 5368 (vmcs12->cr3_target_count >= 3 && 5369 vmcs12->cr3_target_value2 == val) || 5370 (vmcs12->cr3_target_count >= 4 && 5371 vmcs12->cr3_target_value3 == val)) 5372 return false; 5373 if (nested_cpu_has(vmcs12, CPU_BASED_CR3_LOAD_EXITING)) 5374 return true; 5375 break; 5376 case 4: 5377 if (vmcs12->cr4_guest_host_mask & 5378 (vmcs12->cr4_read_shadow ^ val)) 5379 return true; 5380 break; 5381 case 8: 5382 if (nested_cpu_has(vmcs12, CPU_BASED_CR8_LOAD_EXITING)) 5383 return true; 5384 break; 5385 } 5386 break; 5387 case 2: /* clts */ 5388 if ((vmcs12->cr0_guest_host_mask & X86_CR0_TS) && 5389 (vmcs12->cr0_read_shadow & X86_CR0_TS)) 5390 return true; 5391 break; 5392 case 1: /* mov from cr */ 5393 switch (cr) { 5394 case 3: 5395 if (vmcs12->cpu_based_vm_exec_control & 5396 CPU_BASED_CR3_STORE_EXITING) 5397 return true; 5398 break; 5399 case 8: 5400 if (vmcs12->cpu_based_vm_exec_control & 5401 CPU_BASED_CR8_STORE_EXITING) 5402 return true; 5403 break; 5404 } 5405 break; 5406 case 3: /* lmsw */ 5407 /* 5408 * lmsw can change bits 1..3 of cr0, and only set bit 0 of 5409 * cr0. Other attempted changes are ignored, with no exit. 5410 */ 5411 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f; 5412 if (vmcs12->cr0_guest_host_mask & 0xe & 5413 (val ^ vmcs12->cr0_read_shadow)) 5414 return true; 5415 if ((vmcs12->cr0_guest_host_mask & 0x1) && 5416 !(vmcs12->cr0_read_shadow & 0x1) && 5417 (val & 0x1)) 5418 return true; 5419 break; 5420 } 5421 return false; 5422 } 5423 5424 static bool nested_vmx_exit_handled_vmcs_access(struct kvm_vcpu *vcpu, 5425 struct vmcs12 *vmcs12, gpa_t bitmap) 5426 { 5427 u32 vmx_instruction_info; 5428 unsigned long field; 5429 u8 b; 5430 5431 if (!nested_cpu_has_shadow_vmcs(vmcs12)) 5432 return true; 5433 5434 /* Decode instruction info and find the field to access */ 5435 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO); 5436 field = kvm_register_read(vcpu, (((vmx_instruction_info) >> 28) & 0xf)); 5437 5438 /* Out-of-range fields always cause a VM exit from L2 to L1 */ 5439 if (field >> 15) 5440 return true; 5441 5442 if (kvm_vcpu_read_guest(vcpu, bitmap + field/8, &b, 1)) 5443 return true; 5444 5445 return 1 & (b >> (field & 7)); 5446 } 5447 5448 /* 5449 * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we 5450 * should handle it ourselves in L0 (and then continue L2). Only call this 5451 * when in is_guest_mode (L2). 5452 */ 5453 bool nested_vmx_exit_reflected(struct kvm_vcpu *vcpu, u32 exit_reason) 5454 { 5455 u32 intr_info = vmcs_read32(VM_EXIT_INTR_INFO); 5456 struct vcpu_vmx *vmx = to_vmx(vcpu); 5457 struct vmcs12 *vmcs12 = get_vmcs12(vcpu); 5458 5459 if (vmx->nested.nested_run_pending) 5460 return false; 5461 5462 if (unlikely(vmx->fail)) { 5463 trace_kvm_nested_vmenter_failed( 5464 "hardware VM-instruction error: ", 5465 vmcs_read32(VM_INSTRUCTION_ERROR)); 5466 return true; 5467 } 5468 5469 /* 5470 * The host physical addresses of some pages of guest memory 5471 * are loaded into the vmcs02 (e.g. vmcs12's Virtual APIC 5472 * Page). The CPU may write to these pages via their host 5473 * physical address while L2 is running, bypassing any 5474 * address-translation-based dirty tracking (e.g. EPT write 5475 * protection). 5476 * 5477 * Mark them dirty on every exit from L2 to prevent them from 5478 * getting out of sync with dirty tracking. 5479 */ 5480 nested_mark_vmcs12_pages_dirty(vcpu); 5481 5482 trace_kvm_nested_vmexit(kvm_rip_read(vcpu), exit_reason, 5483 vmcs_readl(EXIT_QUALIFICATION), 5484 vmx->idt_vectoring_info, 5485 intr_info, 5486 vmcs_read32(VM_EXIT_INTR_ERROR_CODE), 5487 KVM_ISA_VMX); 5488 5489 switch (exit_reason) { 5490 case EXIT_REASON_EXCEPTION_NMI: 5491 if (is_nmi(intr_info)) 5492 return false; 5493 else if (is_page_fault(intr_info)) 5494 return !vmx->vcpu.arch.apf.host_apf_reason && enable_ept; 5495 else if (is_debug(intr_info) && 5496 vcpu->guest_debug & 5497 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) 5498 return false; 5499 else if (is_breakpoint(intr_info) && 5500 vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP) 5501 return false; 5502 return vmcs12->exception_bitmap & 5503 (1u << (intr_info & INTR_INFO_VECTOR_MASK)); 5504 case EXIT_REASON_EXTERNAL_INTERRUPT: 5505 return false; 5506 case EXIT_REASON_TRIPLE_FAULT: 5507 return true; 5508 case EXIT_REASON_INTERRUPT_WINDOW: 5509 return nested_cpu_has(vmcs12, CPU_BASED_INTR_WINDOW_EXITING); 5510 case EXIT_REASON_NMI_WINDOW: 5511 return nested_cpu_has(vmcs12, CPU_BASED_NMI_WINDOW_EXITING); 5512 case EXIT_REASON_TASK_SWITCH: 5513 return true; 5514 case EXIT_REASON_CPUID: 5515 return true; 5516 case EXIT_REASON_HLT: 5517 return nested_cpu_has(vmcs12, CPU_BASED_HLT_EXITING); 5518 case EXIT_REASON_INVD: 5519 return true; 5520 case EXIT_REASON_INVLPG: 5521 return nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING); 5522 case EXIT_REASON_RDPMC: 5523 return nested_cpu_has(vmcs12, CPU_BASED_RDPMC_EXITING); 5524 case EXIT_REASON_RDRAND: 5525 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_RDRAND_EXITING); 5526 case EXIT_REASON_RDSEED: 5527 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_RDSEED_EXITING); 5528 case EXIT_REASON_RDTSC: case EXIT_REASON_RDTSCP: 5529 return nested_cpu_has(vmcs12, CPU_BASED_RDTSC_EXITING); 5530 case EXIT_REASON_VMREAD: 5531 return nested_vmx_exit_handled_vmcs_access(vcpu, vmcs12, 5532 vmcs12->vmread_bitmap); 5533 case EXIT_REASON_VMWRITE: 5534 return nested_vmx_exit_handled_vmcs_access(vcpu, vmcs12, 5535 vmcs12->vmwrite_bitmap); 5536 case EXIT_REASON_VMCALL: case EXIT_REASON_VMCLEAR: 5537 case EXIT_REASON_VMLAUNCH: case EXIT_REASON_VMPTRLD: 5538 case EXIT_REASON_VMPTRST: case EXIT_REASON_VMRESUME: 5539 case EXIT_REASON_VMOFF: case EXIT_REASON_VMON: 5540 case EXIT_REASON_INVEPT: case EXIT_REASON_INVVPID: 5541 /* 5542 * VMX instructions trap unconditionally. This allows L1 to 5543 * emulate them for its L2 guest, i.e., allows 3-level nesting! 5544 */ 5545 return true; 5546 case EXIT_REASON_CR_ACCESS: 5547 return nested_vmx_exit_handled_cr(vcpu, vmcs12); 5548 case EXIT_REASON_DR_ACCESS: 5549 return nested_cpu_has(vmcs12, CPU_BASED_MOV_DR_EXITING); 5550 case EXIT_REASON_IO_INSTRUCTION: 5551 return nested_vmx_exit_handled_io(vcpu, vmcs12); 5552 case EXIT_REASON_GDTR_IDTR: case EXIT_REASON_LDTR_TR: 5553 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_DESC); 5554 case EXIT_REASON_MSR_READ: 5555 case EXIT_REASON_MSR_WRITE: 5556 return nested_vmx_exit_handled_msr(vcpu, vmcs12, exit_reason); 5557 case EXIT_REASON_INVALID_STATE: 5558 return true; 5559 case EXIT_REASON_MWAIT_INSTRUCTION: 5560 return nested_cpu_has(vmcs12, CPU_BASED_MWAIT_EXITING); 5561 case EXIT_REASON_MONITOR_TRAP_FLAG: 5562 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_TRAP_FLAG); 5563 case EXIT_REASON_MONITOR_INSTRUCTION: 5564 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_EXITING); 5565 case EXIT_REASON_PAUSE_INSTRUCTION: 5566 return nested_cpu_has(vmcs12, CPU_BASED_PAUSE_EXITING) || 5567 nested_cpu_has2(vmcs12, 5568 SECONDARY_EXEC_PAUSE_LOOP_EXITING); 5569 case EXIT_REASON_MCE_DURING_VMENTRY: 5570 return false; 5571 case EXIT_REASON_TPR_BELOW_THRESHOLD: 5572 return nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW); 5573 case EXIT_REASON_APIC_ACCESS: 5574 case EXIT_REASON_APIC_WRITE: 5575 case EXIT_REASON_EOI_INDUCED: 5576 /* 5577 * The controls for "virtualize APIC accesses," "APIC- 5578 * register virtualization," and "virtual-interrupt 5579 * delivery" only come from vmcs12. 5580 */ 5581 return true; 5582 case EXIT_REASON_EPT_VIOLATION: 5583 /* 5584 * L0 always deals with the EPT violation. If nested EPT is 5585 * used, and the nested mmu code discovers that the address is 5586 * missing in the guest EPT table (EPT12), the EPT violation 5587 * will be injected with nested_ept_inject_page_fault() 5588 */ 5589 return false; 5590 case EXIT_REASON_EPT_MISCONFIG: 5591 /* 5592 * L2 never uses directly L1's EPT, but rather L0's own EPT 5593 * table (shadow on EPT) or a merged EPT table that L0 built 5594 * (EPT on EPT). So any problems with the structure of the 5595 * table is L0's fault. 5596 */ 5597 return false; 5598 case EXIT_REASON_INVPCID: 5599 return 5600 nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_INVPCID) && 5601 nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING); 5602 case EXIT_REASON_WBINVD: 5603 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_WBINVD_EXITING); 5604 case EXIT_REASON_XSETBV: 5605 return true; 5606 case EXIT_REASON_XSAVES: case EXIT_REASON_XRSTORS: 5607 /* 5608 * This should never happen, since it is not possible to 5609 * set XSS to a non-zero value---neither in L1 nor in L2. 5610 * If if it were, XSS would have to be checked against 5611 * the XSS exit bitmap in vmcs12. 5612 */ 5613 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_XSAVES); 5614 case EXIT_REASON_PREEMPTION_TIMER: 5615 return false; 5616 case EXIT_REASON_PML_FULL: 5617 /* We emulate PML support to L1. */ 5618 return false; 5619 case EXIT_REASON_VMFUNC: 5620 /* VM functions are emulated through L2->L0 vmexits. */ 5621 return false; 5622 case EXIT_REASON_ENCLS: 5623 /* SGX is never exposed to L1 */ 5624 return false; 5625 case EXIT_REASON_UMWAIT: 5626 case EXIT_REASON_TPAUSE: 5627 return nested_cpu_has2(vmcs12, 5628 SECONDARY_EXEC_ENABLE_USR_WAIT_PAUSE); 5629 default: 5630 return true; 5631 } 5632 } 5633 5634 5635 static int vmx_get_nested_state(struct kvm_vcpu *vcpu, 5636 struct kvm_nested_state __user *user_kvm_nested_state, 5637 u32 user_data_size) 5638 { 5639 struct vcpu_vmx *vmx; 5640 struct vmcs12 *vmcs12; 5641 struct kvm_nested_state kvm_state = { 5642 .flags = 0, 5643 .format = KVM_STATE_NESTED_FORMAT_VMX, 5644 .size = sizeof(kvm_state), 5645 .hdr.vmx.vmxon_pa = -1ull, 5646 .hdr.vmx.vmcs12_pa = -1ull, 5647 }; 5648 struct kvm_vmx_nested_state_data __user *user_vmx_nested_state = 5649 &user_kvm_nested_state->data.vmx[0]; 5650 5651 if (!vcpu) 5652 return kvm_state.size + sizeof(*user_vmx_nested_state); 5653 5654 vmx = to_vmx(vcpu); 5655 vmcs12 = get_vmcs12(vcpu); 5656 5657 if (nested_vmx_allowed(vcpu) && 5658 (vmx->nested.vmxon || vmx->nested.smm.vmxon)) { 5659 kvm_state.hdr.vmx.vmxon_pa = vmx->nested.vmxon_ptr; 5660 kvm_state.hdr.vmx.vmcs12_pa = vmx->nested.current_vmptr; 5661 5662 if (vmx_has_valid_vmcs12(vcpu)) { 5663 kvm_state.size += sizeof(user_vmx_nested_state->vmcs12); 5664 5665 if (vmx->nested.hv_evmcs) 5666 kvm_state.flags |= KVM_STATE_NESTED_EVMCS; 5667 5668 if (is_guest_mode(vcpu) && 5669 nested_cpu_has_shadow_vmcs(vmcs12) && 5670 vmcs12->vmcs_link_pointer != -1ull) 5671 kvm_state.size += sizeof(user_vmx_nested_state->shadow_vmcs12); 5672 } 5673 5674 if (vmx->nested.smm.vmxon) 5675 kvm_state.hdr.vmx.smm.flags |= KVM_STATE_NESTED_SMM_VMXON; 5676 5677 if (vmx->nested.smm.guest_mode) 5678 kvm_state.hdr.vmx.smm.flags |= KVM_STATE_NESTED_SMM_GUEST_MODE; 5679 5680 if (is_guest_mode(vcpu)) { 5681 kvm_state.flags |= KVM_STATE_NESTED_GUEST_MODE; 5682 5683 if (vmx->nested.nested_run_pending) 5684 kvm_state.flags |= KVM_STATE_NESTED_RUN_PENDING; 5685 } 5686 } 5687 5688 if (user_data_size < kvm_state.size) 5689 goto out; 5690 5691 if (copy_to_user(user_kvm_nested_state, &kvm_state, sizeof(kvm_state))) 5692 return -EFAULT; 5693 5694 if (!vmx_has_valid_vmcs12(vcpu)) 5695 goto out; 5696 5697 /* 5698 * When running L2, the authoritative vmcs12 state is in the 5699 * vmcs02. When running L1, the authoritative vmcs12 state is 5700 * in the shadow or enlightened vmcs linked to vmcs01, unless 5701 * need_vmcs12_to_shadow_sync is set, in which case, the authoritative 5702 * vmcs12 state is in the vmcs12 already. 5703 */ 5704 if (is_guest_mode(vcpu)) { 5705 sync_vmcs02_to_vmcs12(vcpu, vmcs12); 5706 sync_vmcs02_to_vmcs12_rare(vcpu, vmcs12); 5707 } else if (!vmx->nested.need_vmcs12_to_shadow_sync) { 5708 if (vmx->nested.hv_evmcs) 5709 copy_enlightened_to_vmcs12(vmx); 5710 else if (enable_shadow_vmcs) 5711 copy_shadow_to_vmcs12(vmx); 5712 } 5713 5714 BUILD_BUG_ON(sizeof(user_vmx_nested_state->vmcs12) < VMCS12_SIZE); 5715 BUILD_BUG_ON(sizeof(user_vmx_nested_state->shadow_vmcs12) < VMCS12_SIZE); 5716 5717 /* 5718 * Copy over the full allocated size of vmcs12 rather than just the size 5719 * of the struct. 5720 */ 5721 if (copy_to_user(user_vmx_nested_state->vmcs12, vmcs12, VMCS12_SIZE)) 5722 return -EFAULT; 5723 5724 if (nested_cpu_has_shadow_vmcs(vmcs12) && 5725 vmcs12->vmcs_link_pointer != -1ull) { 5726 if (copy_to_user(user_vmx_nested_state->shadow_vmcs12, 5727 get_shadow_vmcs12(vcpu), VMCS12_SIZE)) 5728 return -EFAULT; 5729 } 5730 5731 out: 5732 return kvm_state.size; 5733 } 5734 5735 /* 5736 * Forcibly leave nested mode in order to be able to reset the VCPU later on. 5737 */ 5738 void vmx_leave_nested(struct kvm_vcpu *vcpu) 5739 { 5740 if (is_guest_mode(vcpu)) { 5741 to_vmx(vcpu)->nested.nested_run_pending = 0; 5742 nested_vmx_vmexit(vcpu, -1, 0, 0); 5743 } 5744 free_nested(vcpu); 5745 } 5746 5747 static int vmx_set_nested_state(struct kvm_vcpu *vcpu, 5748 struct kvm_nested_state __user *user_kvm_nested_state, 5749 struct kvm_nested_state *kvm_state) 5750 { 5751 struct vcpu_vmx *vmx = to_vmx(vcpu); 5752 struct vmcs12 *vmcs12; 5753 u32 exit_qual; 5754 struct kvm_vmx_nested_state_data __user *user_vmx_nested_state = 5755 &user_kvm_nested_state->data.vmx[0]; 5756 int ret; 5757 5758 if (kvm_state->format != KVM_STATE_NESTED_FORMAT_VMX) 5759 return -EINVAL; 5760 5761 if (kvm_state->hdr.vmx.vmxon_pa == -1ull) { 5762 if (kvm_state->hdr.vmx.smm.flags) 5763 return -EINVAL; 5764 5765 if (kvm_state->hdr.vmx.vmcs12_pa != -1ull) 5766 return -EINVAL; 5767 5768 /* 5769 * KVM_STATE_NESTED_EVMCS used to signal that KVM should 5770 * enable eVMCS capability on vCPU. However, since then 5771 * code was changed such that flag signals vmcs12 should 5772 * be copied into eVMCS in guest memory. 5773 * 5774 * To preserve backwards compatability, allow user 5775 * to set this flag even when there is no VMXON region. 5776 */ 5777 if (kvm_state->flags & ~KVM_STATE_NESTED_EVMCS) 5778 return -EINVAL; 5779 } else { 5780 if (!nested_vmx_allowed(vcpu)) 5781 return -EINVAL; 5782 5783 if (!page_address_valid(vcpu, kvm_state->hdr.vmx.vmxon_pa)) 5784 return -EINVAL; 5785 } 5786 5787 if ((kvm_state->hdr.vmx.smm.flags & KVM_STATE_NESTED_SMM_GUEST_MODE) && 5788 (kvm_state->flags & KVM_STATE_NESTED_GUEST_MODE)) 5789 return -EINVAL; 5790 5791 if (kvm_state->hdr.vmx.smm.flags & 5792 ~(KVM_STATE_NESTED_SMM_GUEST_MODE | KVM_STATE_NESTED_SMM_VMXON)) 5793 return -EINVAL; 5794 5795 /* 5796 * SMM temporarily disables VMX, so we cannot be in guest mode, 5797 * nor can VMLAUNCH/VMRESUME be pending. Outside SMM, SMM flags 5798 * must be zero. 5799 */ 5800 if (is_smm(vcpu) ? 5801 (kvm_state->flags & 5802 (KVM_STATE_NESTED_GUEST_MODE | KVM_STATE_NESTED_RUN_PENDING)) 5803 : kvm_state->hdr.vmx.smm.flags) 5804 return -EINVAL; 5805 5806 if ((kvm_state->hdr.vmx.smm.flags & KVM_STATE_NESTED_SMM_GUEST_MODE) && 5807 !(kvm_state->hdr.vmx.smm.flags & KVM_STATE_NESTED_SMM_VMXON)) 5808 return -EINVAL; 5809 5810 if ((kvm_state->flags & KVM_STATE_NESTED_EVMCS) && 5811 (!nested_vmx_allowed(vcpu) || !vmx->nested.enlightened_vmcs_enabled)) 5812 return -EINVAL; 5813 5814 vmx_leave_nested(vcpu); 5815 5816 if (kvm_state->hdr.vmx.vmxon_pa == -1ull) 5817 return 0; 5818 5819 vmx->nested.vmxon_ptr = kvm_state->hdr.vmx.vmxon_pa; 5820 ret = enter_vmx_operation(vcpu); 5821 if (ret) 5822 return ret; 5823 5824 /* Empty 'VMXON' state is permitted */ 5825 if (kvm_state->size < sizeof(*kvm_state) + sizeof(*vmcs12)) 5826 return 0; 5827 5828 if (kvm_state->hdr.vmx.vmcs12_pa != -1ull) { 5829 if (kvm_state->hdr.vmx.vmcs12_pa == kvm_state->hdr.vmx.vmxon_pa || 5830 !page_address_valid(vcpu, kvm_state->hdr.vmx.vmcs12_pa)) 5831 return -EINVAL; 5832 5833 set_current_vmptr(vmx, kvm_state->hdr.vmx.vmcs12_pa); 5834 } else if (kvm_state->flags & KVM_STATE_NESTED_EVMCS) { 5835 /* 5836 * Sync eVMCS upon entry as we may not have 5837 * HV_X64_MSR_VP_ASSIST_PAGE set up yet. 5838 */ 5839 vmx->nested.need_vmcs12_to_shadow_sync = true; 5840 } else { 5841 return -EINVAL; 5842 } 5843 5844 if (kvm_state->hdr.vmx.smm.flags & KVM_STATE_NESTED_SMM_VMXON) { 5845 vmx->nested.smm.vmxon = true; 5846 vmx->nested.vmxon = false; 5847 5848 if (kvm_state->hdr.vmx.smm.flags & KVM_STATE_NESTED_SMM_GUEST_MODE) 5849 vmx->nested.smm.guest_mode = true; 5850 } 5851 5852 vmcs12 = get_vmcs12(vcpu); 5853 if (copy_from_user(vmcs12, user_vmx_nested_state->vmcs12, sizeof(*vmcs12))) 5854 return -EFAULT; 5855 5856 if (vmcs12->hdr.revision_id != VMCS12_REVISION) 5857 return -EINVAL; 5858 5859 if (!(kvm_state->flags & KVM_STATE_NESTED_GUEST_MODE)) 5860 return 0; 5861 5862 vmx->nested.nested_run_pending = 5863 !!(kvm_state->flags & KVM_STATE_NESTED_RUN_PENDING); 5864 5865 ret = -EINVAL; 5866 if (nested_cpu_has_shadow_vmcs(vmcs12) && 5867 vmcs12->vmcs_link_pointer != -1ull) { 5868 struct vmcs12 *shadow_vmcs12 = get_shadow_vmcs12(vcpu); 5869 5870 if (kvm_state->size < 5871 sizeof(*kvm_state) + 5872 sizeof(user_vmx_nested_state->vmcs12) + sizeof(*shadow_vmcs12)) 5873 goto error_guest_mode; 5874 5875 if (copy_from_user(shadow_vmcs12, 5876 user_vmx_nested_state->shadow_vmcs12, 5877 sizeof(*shadow_vmcs12))) { 5878 ret = -EFAULT; 5879 goto error_guest_mode; 5880 } 5881 5882 if (shadow_vmcs12->hdr.revision_id != VMCS12_REVISION || 5883 !shadow_vmcs12->hdr.shadow_vmcs) 5884 goto error_guest_mode; 5885 } 5886 5887 if (nested_vmx_check_controls(vcpu, vmcs12) || 5888 nested_vmx_check_host_state(vcpu, vmcs12) || 5889 nested_vmx_check_guest_state(vcpu, vmcs12, &exit_qual)) 5890 goto error_guest_mode; 5891 5892 vmx->nested.dirty_vmcs12 = true; 5893 ret = nested_vmx_enter_non_root_mode(vcpu, false); 5894 if (ret) 5895 goto error_guest_mode; 5896 5897 return 0; 5898 5899 error_guest_mode: 5900 vmx->nested.nested_run_pending = 0; 5901 return ret; 5902 } 5903 5904 void nested_vmx_set_vmcs_shadowing_bitmap(void) 5905 { 5906 if (enable_shadow_vmcs) { 5907 vmcs_write64(VMREAD_BITMAP, __pa(vmx_vmread_bitmap)); 5908 vmcs_write64(VMWRITE_BITMAP, __pa(vmx_vmwrite_bitmap)); 5909 } 5910 } 5911 5912 /* 5913 * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be 5914 * returned for the various VMX controls MSRs when nested VMX is enabled. 5915 * The same values should also be used to verify that vmcs12 control fields are 5916 * valid during nested entry from L1 to L2. 5917 * Each of these control msrs has a low and high 32-bit half: A low bit is on 5918 * if the corresponding bit in the (32-bit) control field *must* be on, and a 5919 * bit in the high half is on if the corresponding bit in the control field 5920 * may be on. See also vmx_control_verify(). 5921 */ 5922 void nested_vmx_setup_ctls_msrs(struct nested_vmx_msrs *msrs, u32 ept_caps, 5923 bool apicv) 5924 { 5925 /* 5926 * Note that as a general rule, the high half of the MSRs (bits in 5927 * the control fields which may be 1) should be initialized by the 5928 * intersection of the underlying hardware's MSR (i.e., features which 5929 * can be supported) and the list of features we want to expose - 5930 * because they are known to be properly supported in our code. 5931 * Also, usually, the low half of the MSRs (bits which must be 1) can 5932 * be set to 0, meaning that L1 may turn off any of these bits. The 5933 * reason is that if one of these bits is necessary, it will appear 5934 * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control 5935 * fields of vmcs01 and vmcs02, will turn these bits off - and 5936 * nested_vmx_exit_reflected() will not pass related exits to L1. 5937 * These rules have exceptions below. 5938 */ 5939 5940 /* pin-based controls */ 5941 rdmsr(MSR_IA32_VMX_PINBASED_CTLS, 5942 msrs->pinbased_ctls_low, 5943 msrs->pinbased_ctls_high); 5944 msrs->pinbased_ctls_low |= 5945 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR; 5946 msrs->pinbased_ctls_high &= 5947 PIN_BASED_EXT_INTR_MASK | 5948 PIN_BASED_NMI_EXITING | 5949 PIN_BASED_VIRTUAL_NMIS | 5950 (apicv ? PIN_BASED_POSTED_INTR : 0); 5951 msrs->pinbased_ctls_high |= 5952 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR | 5953 PIN_BASED_VMX_PREEMPTION_TIMER; 5954 5955 /* exit controls */ 5956 rdmsr(MSR_IA32_VMX_EXIT_CTLS, 5957 msrs->exit_ctls_low, 5958 msrs->exit_ctls_high); 5959 msrs->exit_ctls_low = 5960 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR; 5961 5962 msrs->exit_ctls_high &= 5963 #ifdef CONFIG_X86_64 5964 VM_EXIT_HOST_ADDR_SPACE_SIZE | 5965 #endif 5966 VM_EXIT_LOAD_IA32_PAT | VM_EXIT_SAVE_IA32_PAT; 5967 msrs->exit_ctls_high |= 5968 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR | 5969 VM_EXIT_LOAD_IA32_EFER | VM_EXIT_SAVE_IA32_EFER | 5970 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER | VM_EXIT_ACK_INTR_ON_EXIT; 5971 5972 /* We support free control of debug control saving. */ 5973 msrs->exit_ctls_low &= ~VM_EXIT_SAVE_DEBUG_CONTROLS; 5974 5975 /* entry controls */ 5976 rdmsr(MSR_IA32_VMX_ENTRY_CTLS, 5977 msrs->entry_ctls_low, 5978 msrs->entry_ctls_high); 5979 msrs->entry_ctls_low = 5980 VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR; 5981 msrs->entry_ctls_high &= 5982 #ifdef CONFIG_X86_64 5983 VM_ENTRY_IA32E_MODE | 5984 #endif 5985 VM_ENTRY_LOAD_IA32_PAT; 5986 msrs->entry_ctls_high |= 5987 (VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR | VM_ENTRY_LOAD_IA32_EFER); 5988 5989 /* We support free control of debug control loading. */ 5990 msrs->entry_ctls_low &= ~VM_ENTRY_LOAD_DEBUG_CONTROLS; 5991 5992 /* cpu-based controls */ 5993 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS, 5994 msrs->procbased_ctls_low, 5995 msrs->procbased_ctls_high); 5996 msrs->procbased_ctls_low = 5997 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR; 5998 msrs->procbased_ctls_high &= 5999 CPU_BASED_INTR_WINDOW_EXITING | 6000 CPU_BASED_NMI_WINDOW_EXITING | CPU_BASED_USE_TSC_OFFSETTING | 6001 CPU_BASED_HLT_EXITING | CPU_BASED_INVLPG_EXITING | 6002 CPU_BASED_MWAIT_EXITING | CPU_BASED_CR3_LOAD_EXITING | 6003 CPU_BASED_CR3_STORE_EXITING | 6004 #ifdef CONFIG_X86_64 6005 CPU_BASED_CR8_LOAD_EXITING | CPU_BASED_CR8_STORE_EXITING | 6006 #endif 6007 CPU_BASED_MOV_DR_EXITING | CPU_BASED_UNCOND_IO_EXITING | 6008 CPU_BASED_USE_IO_BITMAPS | CPU_BASED_MONITOR_TRAP_FLAG | 6009 CPU_BASED_MONITOR_EXITING | CPU_BASED_RDPMC_EXITING | 6010 CPU_BASED_RDTSC_EXITING | CPU_BASED_PAUSE_EXITING | 6011 CPU_BASED_TPR_SHADOW | CPU_BASED_ACTIVATE_SECONDARY_CONTROLS; 6012 /* 6013 * We can allow some features even when not supported by the 6014 * hardware. For example, L1 can specify an MSR bitmap - and we 6015 * can use it to avoid exits to L1 - even when L0 runs L2 6016 * without MSR bitmaps. 6017 */ 6018 msrs->procbased_ctls_high |= 6019 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR | 6020 CPU_BASED_USE_MSR_BITMAPS; 6021 6022 /* We support free control of CR3 access interception. */ 6023 msrs->procbased_ctls_low &= 6024 ~(CPU_BASED_CR3_LOAD_EXITING | CPU_BASED_CR3_STORE_EXITING); 6025 6026 /* 6027 * secondary cpu-based controls. Do not include those that 6028 * depend on CPUID bits, they are added later by vmx_cpuid_update. 6029 */ 6030 if (msrs->procbased_ctls_high & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) 6031 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2, 6032 msrs->secondary_ctls_low, 6033 msrs->secondary_ctls_high); 6034 6035 msrs->secondary_ctls_low = 0; 6036 msrs->secondary_ctls_high &= 6037 SECONDARY_EXEC_DESC | 6038 SECONDARY_EXEC_RDTSCP | 6039 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 6040 SECONDARY_EXEC_WBINVD_EXITING | 6041 SECONDARY_EXEC_APIC_REGISTER_VIRT | 6042 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 6043 SECONDARY_EXEC_RDRAND_EXITING | 6044 SECONDARY_EXEC_ENABLE_INVPCID | 6045 SECONDARY_EXEC_RDSEED_EXITING | 6046 SECONDARY_EXEC_XSAVES; 6047 6048 /* 6049 * We can emulate "VMCS shadowing," even if the hardware 6050 * doesn't support it. 6051 */ 6052 msrs->secondary_ctls_high |= 6053 SECONDARY_EXEC_SHADOW_VMCS; 6054 6055 if (enable_ept) { 6056 /* nested EPT: emulate EPT also to L1 */ 6057 msrs->secondary_ctls_high |= 6058 SECONDARY_EXEC_ENABLE_EPT; 6059 msrs->ept_caps = VMX_EPT_PAGE_WALK_4_BIT | 6060 VMX_EPTP_WB_BIT | VMX_EPT_INVEPT_BIT; 6061 if (cpu_has_vmx_ept_execute_only()) 6062 msrs->ept_caps |= 6063 VMX_EPT_EXECUTE_ONLY_BIT; 6064 msrs->ept_caps &= ept_caps; 6065 msrs->ept_caps |= VMX_EPT_EXTENT_GLOBAL_BIT | 6066 VMX_EPT_EXTENT_CONTEXT_BIT | VMX_EPT_2MB_PAGE_BIT | 6067 VMX_EPT_1GB_PAGE_BIT; 6068 if (enable_ept_ad_bits) { 6069 msrs->secondary_ctls_high |= 6070 SECONDARY_EXEC_ENABLE_PML; 6071 msrs->ept_caps |= VMX_EPT_AD_BIT; 6072 } 6073 } 6074 6075 if (cpu_has_vmx_vmfunc()) { 6076 msrs->secondary_ctls_high |= 6077 SECONDARY_EXEC_ENABLE_VMFUNC; 6078 /* 6079 * Advertise EPTP switching unconditionally 6080 * since we emulate it 6081 */ 6082 if (enable_ept) 6083 msrs->vmfunc_controls = 6084 VMX_VMFUNC_EPTP_SWITCHING; 6085 } 6086 6087 /* 6088 * Old versions of KVM use the single-context version without 6089 * checking for support, so declare that it is supported even 6090 * though it is treated as global context. The alternative is 6091 * not failing the single-context invvpid, and it is worse. 6092 */ 6093 if (enable_vpid) { 6094 msrs->secondary_ctls_high |= 6095 SECONDARY_EXEC_ENABLE_VPID; 6096 msrs->vpid_caps = VMX_VPID_INVVPID_BIT | 6097 VMX_VPID_EXTENT_SUPPORTED_MASK; 6098 } 6099 6100 if (enable_unrestricted_guest) 6101 msrs->secondary_ctls_high |= 6102 SECONDARY_EXEC_UNRESTRICTED_GUEST; 6103 6104 if (flexpriority_enabled) 6105 msrs->secondary_ctls_high |= 6106 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES; 6107 6108 /* miscellaneous data */ 6109 rdmsr(MSR_IA32_VMX_MISC, 6110 msrs->misc_low, 6111 msrs->misc_high); 6112 msrs->misc_low &= VMX_MISC_SAVE_EFER_LMA; 6113 msrs->misc_low |= 6114 MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS | 6115 VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE | 6116 VMX_MISC_ACTIVITY_HLT; 6117 msrs->misc_high = 0; 6118 6119 /* 6120 * This MSR reports some information about VMX support. We 6121 * should return information about the VMX we emulate for the 6122 * guest, and the VMCS structure we give it - not about the 6123 * VMX support of the underlying hardware. 6124 */ 6125 msrs->basic = 6126 VMCS12_REVISION | 6127 VMX_BASIC_TRUE_CTLS | 6128 ((u64)VMCS12_SIZE << VMX_BASIC_VMCS_SIZE_SHIFT) | 6129 (VMX_BASIC_MEM_TYPE_WB << VMX_BASIC_MEM_TYPE_SHIFT); 6130 6131 if (cpu_has_vmx_basic_inout()) 6132 msrs->basic |= VMX_BASIC_INOUT; 6133 6134 /* 6135 * These MSRs specify bits which the guest must keep fixed on 6136 * while L1 is in VMXON mode (in L1's root mode, or running an L2). 6137 * We picked the standard core2 setting. 6138 */ 6139 #define VMXON_CR0_ALWAYSON (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE) 6140 #define VMXON_CR4_ALWAYSON X86_CR4_VMXE 6141 msrs->cr0_fixed0 = VMXON_CR0_ALWAYSON; 6142 msrs->cr4_fixed0 = VMXON_CR4_ALWAYSON; 6143 6144 /* These MSRs specify bits which the guest must keep fixed off. */ 6145 rdmsrl(MSR_IA32_VMX_CR0_FIXED1, msrs->cr0_fixed1); 6146 rdmsrl(MSR_IA32_VMX_CR4_FIXED1, msrs->cr4_fixed1); 6147 6148 /* highest index: VMX_PREEMPTION_TIMER_VALUE */ 6149 msrs->vmcs_enum = VMCS12_MAX_FIELD_INDEX << 1; 6150 } 6151 6152 void nested_vmx_hardware_unsetup(void) 6153 { 6154 int i; 6155 6156 if (enable_shadow_vmcs) { 6157 for (i = 0; i < VMX_BITMAP_NR; i++) 6158 free_page((unsigned long)vmx_bitmap[i]); 6159 } 6160 } 6161 6162 __init int nested_vmx_hardware_setup(int (*exit_handlers[])(struct kvm_vcpu *)) 6163 { 6164 int i; 6165 6166 if (!cpu_has_vmx_shadow_vmcs()) 6167 enable_shadow_vmcs = 0; 6168 if (enable_shadow_vmcs) { 6169 for (i = 0; i < VMX_BITMAP_NR; i++) { 6170 /* 6171 * The vmx_bitmap is not tied to a VM and so should 6172 * not be charged to a memcg. 6173 */ 6174 vmx_bitmap[i] = (unsigned long *) 6175 __get_free_page(GFP_KERNEL); 6176 if (!vmx_bitmap[i]) { 6177 nested_vmx_hardware_unsetup(); 6178 return -ENOMEM; 6179 } 6180 } 6181 6182 init_vmcs_shadow_fields(); 6183 } 6184 6185 exit_handlers[EXIT_REASON_VMCLEAR] = handle_vmclear; 6186 exit_handlers[EXIT_REASON_VMLAUNCH] = handle_vmlaunch; 6187 exit_handlers[EXIT_REASON_VMPTRLD] = handle_vmptrld; 6188 exit_handlers[EXIT_REASON_VMPTRST] = handle_vmptrst; 6189 exit_handlers[EXIT_REASON_VMREAD] = handle_vmread; 6190 exit_handlers[EXIT_REASON_VMRESUME] = handle_vmresume; 6191 exit_handlers[EXIT_REASON_VMWRITE] = handle_vmwrite; 6192 exit_handlers[EXIT_REASON_VMOFF] = handle_vmoff; 6193 exit_handlers[EXIT_REASON_VMON] = handle_vmon; 6194 exit_handlers[EXIT_REASON_INVEPT] = handle_invept; 6195 exit_handlers[EXIT_REASON_INVVPID] = handle_invvpid; 6196 exit_handlers[EXIT_REASON_VMFUNC] = handle_vmfunc; 6197 6198 kvm_x86_ops->check_nested_events = vmx_check_nested_events; 6199 kvm_x86_ops->get_nested_state = vmx_get_nested_state; 6200 kvm_x86_ops->set_nested_state = vmx_set_nested_state; 6201 kvm_x86_ops->get_vmcs12_pages = nested_get_vmcs12_pages; 6202 kvm_x86_ops->nested_enable_evmcs = nested_enable_evmcs; 6203 kvm_x86_ops->nested_get_evmcs_version = nested_get_evmcs_version; 6204 6205 return 0; 6206 } 6207