1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Kernel-based Virtual Machine driver for Linux 4 * 5 * AMD SVM support 6 * 7 * Copyright (C) 2006 Qumranet, Inc. 8 * Copyright 2010 Red Hat, Inc. and/or its affiliates. 9 * 10 * Authors: 11 * Yaniv Kamay <yaniv@qumranet.com> 12 * Avi Kivity <avi@qumranet.com> 13 */ 14 15 #ifndef __SVM_SVM_H 16 #define __SVM_SVM_H 17 18 #include <linux/kvm_types.h> 19 #include <linux/kvm_host.h> 20 #include <linux/bits.h> 21 22 #include <asm/svm.h> 23 #include <asm/sev-common.h> 24 25 #include "cpuid.h" 26 #include "kvm_cache_regs.h" 27 28 #define __sme_page_pa(x) __sme_set(page_to_pfn(x) << PAGE_SHIFT) 29 30 #define IOPM_SIZE PAGE_SIZE * 3 31 #define MSRPM_SIZE PAGE_SIZE * 2 32 33 #define MAX_DIRECT_ACCESS_MSRS 48 34 #define MSRPM_OFFSETS 32 35 extern u32 msrpm_offsets[MSRPM_OFFSETS] __read_mostly; 36 extern bool npt_enabled; 37 extern int nrips; 38 extern int vgif; 39 extern bool intercept_smi; 40 extern bool x2avic_enabled; 41 extern bool vnmi; 42 extern int lbrv; 43 44 /* 45 * Clean bits in VMCB. 46 * VMCB_ALL_CLEAN_MASK might also need to 47 * be updated if this enum is modified. 48 */ 49 enum { 50 VMCB_INTERCEPTS, /* Intercept vectors, TSC offset, 51 pause filter count */ 52 VMCB_PERM_MAP, /* IOPM Base and MSRPM Base */ 53 VMCB_ASID, /* ASID */ 54 VMCB_INTR, /* int_ctl, int_vector */ 55 VMCB_NPT, /* npt_en, nCR3, gPAT */ 56 VMCB_CR, /* CR0, CR3, CR4, EFER */ 57 VMCB_DR, /* DR6, DR7 */ 58 VMCB_DT, /* GDT, IDT */ 59 VMCB_SEG, /* CS, DS, SS, ES, CPL */ 60 VMCB_CR2, /* CR2 only */ 61 VMCB_LBR, /* DBGCTL, BR_FROM, BR_TO, LAST_EX_FROM, LAST_EX_TO */ 62 VMCB_AVIC, /* AVIC APIC_BAR, AVIC APIC_BACKING_PAGE, 63 * AVIC PHYSICAL_TABLE pointer, 64 * AVIC LOGICAL_TABLE pointer 65 */ 66 VMCB_SW = 31, /* Reserved for hypervisor/software use */ 67 }; 68 69 #define VMCB_ALL_CLEAN_MASK ( \ 70 (1U << VMCB_INTERCEPTS) | (1U << VMCB_PERM_MAP) | \ 71 (1U << VMCB_ASID) | (1U << VMCB_INTR) | \ 72 (1U << VMCB_NPT) | (1U << VMCB_CR) | (1U << VMCB_DR) | \ 73 (1U << VMCB_DT) | (1U << VMCB_SEG) | (1U << VMCB_CR2) | \ 74 (1U << VMCB_LBR) | (1U << VMCB_AVIC) | \ 75 (1U << VMCB_SW)) 76 77 /* TPR and CR2 are always written before VMRUN */ 78 #define VMCB_ALWAYS_DIRTY_MASK ((1U << VMCB_INTR) | (1U << VMCB_CR2)) 79 80 struct kvm_sev_info { 81 bool active; /* SEV enabled guest */ 82 bool es_active; /* SEV-ES enabled guest */ 83 bool need_init; /* waiting for SEV_INIT2 */ 84 unsigned int asid; /* ASID used for this guest */ 85 unsigned int handle; /* SEV firmware handle */ 86 int fd; /* SEV device fd */ 87 unsigned long pages_locked; /* Number of pages locked */ 88 struct list_head regions_list; /* List of registered regions */ 89 u64 ap_jump_table; /* SEV-ES AP Jump Table address */ 90 u64 vmsa_features; 91 u16 ghcb_version; /* Highest guest GHCB protocol version allowed */ 92 struct kvm *enc_context_owner; /* Owner of copied encryption context */ 93 struct list_head mirror_vms; /* List of VMs mirroring */ 94 struct list_head mirror_entry; /* Use as a list entry of mirrors */ 95 struct misc_cg *misc_cg; /* For misc cgroup accounting */ 96 atomic_t migration_in_progress; 97 }; 98 99 struct kvm_svm { 100 struct kvm kvm; 101 102 /* Struct members for AVIC */ 103 u32 avic_vm_id; 104 struct page *avic_logical_id_table_page; 105 struct page *avic_physical_id_table_page; 106 struct hlist_node hnode; 107 108 struct kvm_sev_info sev_info; 109 }; 110 111 struct kvm_vcpu; 112 113 struct kvm_vmcb_info { 114 struct vmcb *ptr; 115 unsigned long pa; 116 int cpu; 117 uint64_t asid_generation; 118 }; 119 120 struct vmcb_save_area_cached { 121 u64 efer; 122 u64 cr4; 123 u64 cr3; 124 u64 cr0; 125 u64 dr7; 126 u64 dr6; 127 }; 128 129 struct vmcb_ctrl_area_cached { 130 u32 intercepts[MAX_INTERCEPT]; 131 u16 pause_filter_thresh; 132 u16 pause_filter_count; 133 u64 iopm_base_pa; 134 u64 msrpm_base_pa; 135 u64 tsc_offset; 136 u32 asid; 137 u8 tlb_ctl; 138 u32 int_ctl; 139 u32 int_vector; 140 u32 int_state; 141 u32 exit_code; 142 u32 exit_code_hi; 143 u64 exit_info_1; 144 u64 exit_info_2; 145 u32 exit_int_info; 146 u32 exit_int_info_err; 147 u64 nested_ctl; 148 u32 event_inj; 149 u32 event_inj_err; 150 u64 next_rip; 151 u64 nested_cr3; 152 u64 virt_ext; 153 u32 clean; 154 union { 155 #if IS_ENABLED(CONFIG_HYPERV) || IS_ENABLED(CONFIG_KVM_HYPERV) 156 struct hv_vmcb_enlightenments hv_enlightenments; 157 #endif 158 u8 reserved_sw[32]; 159 }; 160 }; 161 162 struct svm_nested_state { 163 struct kvm_vmcb_info vmcb02; 164 u64 hsave_msr; 165 u64 vm_cr_msr; 166 u64 vmcb12_gpa; 167 u64 last_vmcb12_gpa; 168 169 /* These are the merged vectors */ 170 u32 *msrpm; 171 172 /* A VMRUN has started but has not yet been performed, so 173 * we cannot inject a nested vmexit yet. */ 174 bool nested_run_pending; 175 176 /* cache for control fields of the guest */ 177 struct vmcb_ctrl_area_cached ctl; 178 179 /* 180 * Note: this struct is not kept up-to-date while L2 runs; it is only 181 * valid within nested_svm_vmrun. 182 */ 183 struct vmcb_save_area_cached save; 184 185 bool initialized; 186 187 /* 188 * Indicates whether MSR bitmap for L2 needs to be rebuilt due to 189 * changes in MSR bitmap for L1 or switching to a different L2. Note, 190 * this flag can only be used reliably in conjunction with a paravirt L1 191 * which informs L0 whether any changes to MSR bitmap for L2 were done 192 * on its side. 193 */ 194 bool force_msr_bitmap_recalc; 195 }; 196 197 struct vcpu_sev_es_state { 198 /* SEV-ES support */ 199 struct sev_es_save_area *vmsa; 200 struct ghcb *ghcb; 201 u8 valid_bitmap[16]; 202 struct kvm_host_map ghcb_map; 203 bool received_first_sipi; 204 unsigned int ap_reset_hold_type; 205 206 /* SEV-ES scratch area support */ 207 u64 sw_scratch; 208 void *ghcb_sa; 209 u32 ghcb_sa_len; 210 bool ghcb_sa_sync; 211 bool ghcb_sa_free; 212 }; 213 214 struct vcpu_svm { 215 struct kvm_vcpu vcpu; 216 /* vmcb always points at current_vmcb->ptr, it's purely a shorthand. */ 217 struct vmcb *vmcb; 218 struct kvm_vmcb_info vmcb01; 219 struct kvm_vmcb_info *current_vmcb; 220 u32 asid; 221 u32 sysenter_esp_hi; 222 u32 sysenter_eip_hi; 223 uint64_t tsc_aux; 224 225 u64 msr_decfg; 226 227 u64 next_rip; 228 229 u64 spec_ctrl; 230 231 u64 tsc_ratio_msr; 232 /* 233 * Contains guest-controlled bits of VIRT_SPEC_CTRL, which will be 234 * translated into the appropriate L2_CFG bits on the host to 235 * perform speculative control. 236 */ 237 u64 virt_spec_ctrl; 238 239 u32 *msrpm; 240 241 ulong nmi_iret_rip; 242 243 struct svm_nested_state nested; 244 245 /* NMI mask value, used when vNMI is not enabled */ 246 bool nmi_masked; 247 248 /* 249 * True when NMIs are still masked but guest IRET was just intercepted 250 * and KVM is waiting for RIP to change, which will signal that the 251 * intercepted IRET was retired and thus NMI can be unmasked. 252 */ 253 bool awaiting_iret_completion; 254 255 /* 256 * Set when KVM is awaiting IRET completion and needs to inject NMIs as 257 * soon as the IRET completes (e.g. NMI is pending injection). KVM 258 * temporarily steals RFLAGS.TF to single-step the guest in this case 259 * in order to regain control as soon as the NMI-blocking condition 260 * goes away. 261 */ 262 bool nmi_singlestep; 263 u64 nmi_singlestep_guest_rflags; 264 265 bool nmi_l1_to_l2; 266 267 unsigned long soft_int_csbase; 268 unsigned long soft_int_old_rip; 269 unsigned long soft_int_next_rip; 270 bool soft_int_injected; 271 272 u32 ldr_reg; 273 u32 dfr_reg; 274 struct page *avic_backing_page; 275 u64 *avic_physical_id_cache; 276 277 /* 278 * Per-vcpu list of struct amd_svm_iommu_ir: 279 * This is used mainly to store interrupt remapping information used 280 * when update the vcpu affinity. This avoids the need to scan for 281 * IRTE and try to match ga_tag in the IOMMU driver. 282 */ 283 struct list_head ir_list; 284 spinlock_t ir_list_lock; 285 286 /* Save desired MSR intercept (read: pass-through) state */ 287 struct { 288 DECLARE_BITMAP(read, MAX_DIRECT_ACCESS_MSRS); 289 DECLARE_BITMAP(write, MAX_DIRECT_ACCESS_MSRS); 290 } shadow_msr_intercept; 291 292 struct vcpu_sev_es_state sev_es; 293 294 bool guest_state_loaded; 295 296 bool x2avic_msrs_intercepted; 297 298 /* Guest GIF value, used when vGIF is not enabled */ 299 bool guest_gif; 300 }; 301 302 struct svm_cpu_data { 303 u64 asid_generation; 304 u32 max_asid; 305 u32 next_asid; 306 u32 min_asid; 307 308 struct page *save_area; 309 unsigned long save_area_pa; 310 311 struct vmcb *current_vmcb; 312 313 /* index = sev_asid, value = vmcb pointer */ 314 struct vmcb **sev_vmcbs; 315 }; 316 317 DECLARE_PER_CPU(struct svm_cpu_data, svm_data); 318 319 void recalc_intercepts(struct vcpu_svm *svm); 320 321 static __always_inline struct kvm_svm *to_kvm_svm(struct kvm *kvm) 322 { 323 return container_of(kvm, struct kvm_svm, kvm); 324 } 325 326 static __always_inline struct kvm_sev_info *to_kvm_sev_info(struct kvm *kvm) 327 { 328 return &to_kvm_svm(kvm)->sev_info; 329 } 330 331 static __always_inline bool sev_guest(struct kvm *kvm) 332 { 333 #ifdef CONFIG_KVM_AMD_SEV 334 struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info; 335 336 return sev->active; 337 #else 338 return false; 339 #endif 340 } 341 342 static __always_inline bool sev_es_guest(struct kvm *kvm) 343 { 344 #ifdef CONFIG_KVM_AMD_SEV 345 struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info; 346 347 return sev->es_active && !WARN_ON_ONCE(!sev->active); 348 #else 349 return false; 350 #endif 351 } 352 353 static inline void vmcb_mark_all_dirty(struct vmcb *vmcb) 354 { 355 vmcb->control.clean = 0; 356 } 357 358 static inline void vmcb_mark_all_clean(struct vmcb *vmcb) 359 { 360 vmcb->control.clean = VMCB_ALL_CLEAN_MASK 361 & ~VMCB_ALWAYS_DIRTY_MASK; 362 } 363 364 static inline void vmcb_mark_dirty(struct vmcb *vmcb, int bit) 365 { 366 vmcb->control.clean &= ~(1 << bit); 367 } 368 369 static inline bool vmcb_is_dirty(struct vmcb *vmcb, int bit) 370 { 371 return !test_bit(bit, (unsigned long *)&vmcb->control.clean); 372 } 373 374 static __always_inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu) 375 { 376 return container_of(vcpu, struct vcpu_svm, vcpu); 377 } 378 379 /* 380 * Only the PDPTRs are loaded on demand into the shadow MMU. All other 381 * fields are synchronized on VM-Exit, because accessing the VMCB is cheap. 382 * 383 * CR3 might be out of date in the VMCB but it is not marked dirty; instead, 384 * KVM_REQ_LOAD_MMU_PGD is always requested when the cached vcpu->arch.cr3 385 * is changed. svm_load_mmu_pgd() then syncs the new CR3 value into the VMCB. 386 */ 387 #define SVM_REGS_LAZY_LOAD_SET (1 << VCPU_EXREG_PDPTR) 388 389 static inline void vmcb_set_intercept(struct vmcb_control_area *control, u32 bit) 390 { 391 WARN_ON_ONCE(bit >= 32 * MAX_INTERCEPT); 392 __set_bit(bit, (unsigned long *)&control->intercepts); 393 } 394 395 static inline void vmcb_clr_intercept(struct vmcb_control_area *control, u32 bit) 396 { 397 WARN_ON_ONCE(bit >= 32 * MAX_INTERCEPT); 398 __clear_bit(bit, (unsigned long *)&control->intercepts); 399 } 400 401 static inline bool vmcb_is_intercept(struct vmcb_control_area *control, u32 bit) 402 { 403 WARN_ON_ONCE(bit >= 32 * MAX_INTERCEPT); 404 return test_bit(bit, (unsigned long *)&control->intercepts); 405 } 406 407 static inline bool vmcb12_is_intercept(struct vmcb_ctrl_area_cached *control, u32 bit) 408 { 409 WARN_ON_ONCE(bit >= 32 * MAX_INTERCEPT); 410 return test_bit(bit, (unsigned long *)&control->intercepts); 411 } 412 413 static inline void set_exception_intercept(struct vcpu_svm *svm, u32 bit) 414 { 415 struct vmcb *vmcb = svm->vmcb01.ptr; 416 417 WARN_ON_ONCE(bit >= 32); 418 vmcb_set_intercept(&vmcb->control, INTERCEPT_EXCEPTION_OFFSET + bit); 419 420 recalc_intercepts(svm); 421 } 422 423 static inline void clr_exception_intercept(struct vcpu_svm *svm, u32 bit) 424 { 425 struct vmcb *vmcb = svm->vmcb01.ptr; 426 427 WARN_ON_ONCE(bit >= 32); 428 vmcb_clr_intercept(&vmcb->control, INTERCEPT_EXCEPTION_OFFSET + bit); 429 430 recalc_intercepts(svm); 431 } 432 433 static inline void svm_set_intercept(struct vcpu_svm *svm, int bit) 434 { 435 struct vmcb *vmcb = svm->vmcb01.ptr; 436 437 vmcb_set_intercept(&vmcb->control, bit); 438 439 recalc_intercepts(svm); 440 } 441 442 static inline void svm_clr_intercept(struct vcpu_svm *svm, int bit) 443 { 444 struct vmcb *vmcb = svm->vmcb01.ptr; 445 446 vmcb_clr_intercept(&vmcb->control, bit); 447 448 recalc_intercepts(svm); 449 } 450 451 static inline bool svm_is_intercept(struct vcpu_svm *svm, int bit) 452 { 453 return vmcb_is_intercept(&svm->vmcb->control, bit); 454 } 455 456 static inline bool nested_vgif_enabled(struct vcpu_svm *svm) 457 { 458 return guest_can_use(&svm->vcpu, X86_FEATURE_VGIF) && 459 (svm->nested.ctl.int_ctl & V_GIF_ENABLE_MASK); 460 } 461 462 static inline struct vmcb *get_vgif_vmcb(struct vcpu_svm *svm) 463 { 464 if (!vgif) 465 return NULL; 466 467 if (is_guest_mode(&svm->vcpu) && !nested_vgif_enabled(svm)) 468 return svm->nested.vmcb02.ptr; 469 else 470 return svm->vmcb01.ptr; 471 } 472 473 static inline void enable_gif(struct vcpu_svm *svm) 474 { 475 struct vmcb *vmcb = get_vgif_vmcb(svm); 476 477 if (vmcb) 478 vmcb->control.int_ctl |= V_GIF_MASK; 479 else 480 svm->guest_gif = true; 481 } 482 483 static inline void disable_gif(struct vcpu_svm *svm) 484 { 485 struct vmcb *vmcb = get_vgif_vmcb(svm); 486 487 if (vmcb) 488 vmcb->control.int_ctl &= ~V_GIF_MASK; 489 else 490 svm->guest_gif = false; 491 } 492 493 static inline bool gif_set(struct vcpu_svm *svm) 494 { 495 struct vmcb *vmcb = get_vgif_vmcb(svm); 496 497 if (vmcb) 498 return !!(vmcb->control.int_ctl & V_GIF_MASK); 499 else 500 return svm->guest_gif; 501 } 502 503 static inline bool nested_npt_enabled(struct vcpu_svm *svm) 504 { 505 return svm->nested.ctl.nested_ctl & SVM_NESTED_CTL_NP_ENABLE; 506 } 507 508 static inline bool nested_vnmi_enabled(struct vcpu_svm *svm) 509 { 510 return guest_can_use(&svm->vcpu, X86_FEATURE_VNMI) && 511 (svm->nested.ctl.int_ctl & V_NMI_ENABLE_MASK); 512 } 513 514 static inline bool is_x2apic_msrpm_offset(u32 offset) 515 { 516 /* 4 msrs per u8, and 4 u8 in u32 */ 517 u32 msr = offset * 16; 518 519 return (msr >= APIC_BASE_MSR) && 520 (msr < (APIC_BASE_MSR + 0x100)); 521 } 522 523 static inline struct vmcb *get_vnmi_vmcb_l1(struct vcpu_svm *svm) 524 { 525 if (!vnmi) 526 return NULL; 527 528 if (is_guest_mode(&svm->vcpu)) 529 return NULL; 530 else 531 return svm->vmcb01.ptr; 532 } 533 534 static inline bool is_vnmi_enabled(struct vcpu_svm *svm) 535 { 536 struct vmcb *vmcb = get_vnmi_vmcb_l1(svm); 537 538 if (vmcb) 539 return !!(vmcb->control.int_ctl & V_NMI_ENABLE_MASK); 540 else 541 return false; 542 } 543 544 /* svm.c */ 545 #define MSR_INVALID 0xffffffffU 546 547 #define DEBUGCTL_RESERVED_BITS (~(0x3fULL)) 548 549 extern bool dump_invalid_vmcb; 550 551 u32 svm_msrpm_offset(u32 msr); 552 u32 *svm_vcpu_alloc_msrpm(void); 553 void svm_vcpu_init_msrpm(struct kvm_vcpu *vcpu, u32 *msrpm); 554 void svm_vcpu_free_msrpm(u32 *msrpm); 555 void svm_copy_lbrs(struct vmcb *to_vmcb, struct vmcb *from_vmcb); 556 void svm_enable_lbrv(struct kvm_vcpu *vcpu); 557 void svm_update_lbrv(struct kvm_vcpu *vcpu); 558 559 int svm_set_efer(struct kvm_vcpu *vcpu, u64 efer); 560 void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0); 561 void svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4); 562 void disable_nmi_singlestep(struct vcpu_svm *svm); 563 bool svm_smi_blocked(struct kvm_vcpu *vcpu); 564 bool svm_nmi_blocked(struct kvm_vcpu *vcpu); 565 bool svm_interrupt_blocked(struct kvm_vcpu *vcpu); 566 void svm_set_gif(struct vcpu_svm *svm, bool value); 567 int svm_invoke_exit_handler(struct kvm_vcpu *vcpu, u64 exit_code); 568 void set_msr_interception(struct kvm_vcpu *vcpu, u32 *msrpm, u32 msr, 569 int read, int write); 570 void svm_set_x2apic_msr_interception(struct vcpu_svm *svm, bool disable); 571 void svm_complete_interrupt_delivery(struct kvm_vcpu *vcpu, int delivery_mode, 572 int trig_mode, int vec); 573 574 /* nested.c */ 575 576 #define NESTED_EXIT_HOST 0 /* Exit handled on host level */ 577 #define NESTED_EXIT_DONE 1 /* Exit caused nested vmexit */ 578 #define NESTED_EXIT_CONTINUE 2 /* Further checks needed */ 579 580 static inline bool nested_svm_virtualize_tpr(struct kvm_vcpu *vcpu) 581 { 582 struct vcpu_svm *svm = to_svm(vcpu); 583 584 return is_guest_mode(vcpu) && (svm->nested.ctl.int_ctl & V_INTR_MASKING_MASK); 585 } 586 587 static inline bool nested_exit_on_smi(struct vcpu_svm *svm) 588 { 589 return vmcb12_is_intercept(&svm->nested.ctl, INTERCEPT_SMI); 590 } 591 592 static inline bool nested_exit_on_intr(struct vcpu_svm *svm) 593 { 594 return vmcb12_is_intercept(&svm->nested.ctl, INTERCEPT_INTR); 595 } 596 597 static inline bool nested_exit_on_nmi(struct vcpu_svm *svm) 598 { 599 return vmcb12_is_intercept(&svm->nested.ctl, INTERCEPT_NMI); 600 } 601 602 int enter_svm_guest_mode(struct kvm_vcpu *vcpu, 603 u64 vmcb_gpa, struct vmcb *vmcb12, bool from_vmrun); 604 void svm_leave_nested(struct kvm_vcpu *vcpu); 605 void svm_free_nested(struct vcpu_svm *svm); 606 int svm_allocate_nested(struct vcpu_svm *svm); 607 int nested_svm_vmrun(struct kvm_vcpu *vcpu); 608 void svm_copy_vmrun_state(struct vmcb_save_area *to_save, 609 struct vmcb_save_area *from_save); 610 void svm_copy_vmloadsave_state(struct vmcb *to_vmcb, struct vmcb *from_vmcb); 611 int nested_svm_vmexit(struct vcpu_svm *svm); 612 613 static inline int nested_svm_simple_vmexit(struct vcpu_svm *svm, u32 exit_code) 614 { 615 svm->vmcb->control.exit_code = exit_code; 616 svm->vmcb->control.exit_info_1 = 0; 617 svm->vmcb->control.exit_info_2 = 0; 618 return nested_svm_vmexit(svm); 619 } 620 621 int nested_svm_exit_handled(struct vcpu_svm *svm); 622 int nested_svm_check_permissions(struct kvm_vcpu *vcpu); 623 int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr, 624 bool has_error_code, u32 error_code); 625 int nested_svm_exit_special(struct vcpu_svm *svm); 626 void nested_svm_update_tsc_ratio_msr(struct kvm_vcpu *vcpu); 627 void svm_write_tsc_multiplier(struct kvm_vcpu *vcpu); 628 void nested_copy_vmcb_control_to_cache(struct vcpu_svm *svm, 629 struct vmcb_control_area *control); 630 void nested_copy_vmcb_save_to_cache(struct vcpu_svm *svm, 631 struct vmcb_save_area *save); 632 void nested_sync_control_from_vmcb02(struct vcpu_svm *svm); 633 void nested_vmcb02_compute_g_pat(struct vcpu_svm *svm); 634 void svm_switch_vmcb(struct vcpu_svm *svm, struct kvm_vmcb_info *target_vmcb); 635 636 extern struct kvm_x86_nested_ops svm_nested_ops; 637 638 /* avic.c */ 639 #define AVIC_REQUIRED_APICV_INHIBITS \ 640 ( \ 641 BIT(APICV_INHIBIT_REASON_DISABLE) | \ 642 BIT(APICV_INHIBIT_REASON_ABSENT) | \ 643 BIT(APICV_INHIBIT_REASON_HYPERV) | \ 644 BIT(APICV_INHIBIT_REASON_NESTED) | \ 645 BIT(APICV_INHIBIT_REASON_IRQWIN) | \ 646 BIT(APICV_INHIBIT_REASON_PIT_REINJ) | \ 647 BIT(APICV_INHIBIT_REASON_BLOCKIRQ) | \ 648 BIT(APICV_INHIBIT_REASON_SEV) | \ 649 BIT(APICV_INHIBIT_REASON_PHYSICAL_ID_ALIASED) | \ 650 BIT(APICV_INHIBIT_REASON_APIC_ID_MODIFIED) | \ 651 BIT(APICV_INHIBIT_REASON_APIC_BASE_MODIFIED) | \ 652 BIT(APICV_INHIBIT_REASON_LOGICAL_ID_ALIASED) \ 653 ) 654 655 bool avic_hardware_setup(void); 656 int avic_ga_log_notifier(u32 ga_tag); 657 void avic_vm_destroy(struct kvm *kvm); 658 int avic_vm_init(struct kvm *kvm); 659 void avic_init_vmcb(struct vcpu_svm *svm, struct vmcb *vmcb); 660 int avic_incomplete_ipi_interception(struct kvm_vcpu *vcpu); 661 int avic_unaccelerated_access_interception(struct kvm_vcpu *vcpu); 662 int avic_init_vcpu(struct vcpu_svm *svm); 663 void avic_vcpu_load(struct kvm_vcpu *vcpu, int cpu); 664 void avic_vcpu_put(struct kvm_vcpu *vcpu); 665 void avic_apicv_post_state_restore(struct kvm_vcpu *vcpu); 666 void avic_refresh_apicv_exec_ctrl(struct kvm_vcpu *vcpu); 667 int avic_pi_update_irte(struct kvm *kvm, unsigned int host_irq, 668 uint32_t guest_irq, bool set); 669 void avic_vcpu_blocking(struct kvm_vcpu *vcpu); 670 void avic_vcpu_unblocking(struct kvm_vcpu *vcpu); 671 void avic_ring_doorbell(struct kvm_vcpu *vcpu); 672 unsigned long avic_vcpu_get_apicv_inhibit_reasons(struct kvm_vcpu *vcpu); 673 void avic_refresh_virtual_apic_mode(struct kvm_vcpu *vcpu); 674 675 676 /* sev.c */ 677 678 void pre_sev_run(struct vcpu_svm *svm, int cpu); 679 void sev_init_vmcb(struct vcpu_svm *svm); 680 void sev_vcpu_after_set_cpuid(struct vcpu_svm *svm); 681 int sev_es_string_io(struct vcpu_svm *svm, int size, unsigned int port, int in); 682 void sev_es_vcpu_reset(struct vcpu_svm *svm); 683 void sev_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector); 684 void sev_es_prepare_switch_to_guest(struct vcpu_svm *svm, struct sev_es_save_area *hostsa); 685 void sev_es_unmap_ghcb(struct vcpu_svm *svm); 686 687 #ifdef CONFIG_KVM_AMD_SEV 688 int sev_mem_enc_ioctl(struct kvm *kvm, void __user *argp); 689 int sev_mem_enc_register_region(struct kvm *kvm, 690 struct kvm_enc_region *range); 691 int sev_mem_enc_unregister_region(struct kvm *kvm, 692 struct kvm_enc_region *range); 693 int sev_vm_copy_enc_context_from(struct kvm *kvm, unsigned int source_fd); 694 int sev_vm_move_enc_context_from(struct kvm *kvm, unsigned int source_fd); 695 void sev_guest_memory_reclaimed(struct kvm *kvm); 696 int sev_handle_vmgexit(struct kvm_vcpu *vcpu); 697 698 /* These symbols are used in common code and are stubbed below. */ 699 struct page *snp_safe_alloc_page(struct kvm_vcpu *vcpu); 700 void sev_free_vcpu(struct kvm_vcpu *vcpu); 701 void sev_vm_destroy(struct kvm *kvm); 702 void __init sev_set_cpu_caps(void); 703 void __init sev_hardware_setup(void); 704 void sev_hardware_unsetup(void); 705 int sev_cpu_init(struct svm_cpu_data *sd); 706 int sev_dev_get_attr(u32 group, u64 attr, u64 *val); 707 extern unsigned int max_sev_asid; 708 #else 709 static inline struct page *snp_safe_alloc_page(struct kvm_vcpu *vcpu) { 710 return alloc_page(GFP_KERNEL_ACCOUNT | __GFP_ZERO); 711 } 712 713 static inline void sev_free_vcpu(struct kvm_vcpu *vcpu) {} 714 static inline void sev_vm_destroy(struct kvm *kvm) {} 715 static inline void __init sev_set_cpu_caps(void) {} 716 static inline void __init sev_hardware_setup(void) {} 717 static inline void sev_hardware_unsetup(void) {} 718 static inline int sev_cpu_init(struct svm_cpu_data *sd) { return 0; } 719 static inline int sev_dev_get_attr(u32 group, u64 attr, u64 *val) { return -ENXIO; } 720 #define max_sev_asid 0 721 #endif 722 723 /* vmenter.S */ 724 725 void __svm_sev_es_vcpu_run(struct vcpu_svm *svm, bool spec_ctrl_intercepted, 726 struct sev_es_save_area *hostsa); 727 void __svm_vcpu_run(struct vcpu_svm *svm, bool spec_ctrl_intercepted); 728 729 #define DEFINE_KVM_GHCB_ACCESSORS(field) \ 730 static __always_inline bool kvm_ghcb_##field##_is_valid(const struct vcpu_svm *svm) \ 731 { \ 732 return test_bit(GHCB_BITMAP_IDX(field), \ 733 (unsigned long *)&svm->sev_es.valid_bitmap); \ 734 } \ 735 \ 736 static __always_inline u64 kvm_ghcb_get_##field##_if_valid(struct vcpu_svm *svm, struct ghcb *ghcb) \ 737 { \ 738 return kvm_ghcb_##field##_is_valid(svm) ? ghcb->save.field : 0; \ 739 } \ 740 741 DEFINE_KVM_GHCB_ACCESSORS(cpl) 742 DEFINE_KVM_GHCB_ACCESSORS(rax) 743 DEFINE_KVM_GHCB_ACCESSORS(rcx) 744 DEFINE_KVM_GHCB_ACCESSORS(rdx) 745 DEFINE_KVM_GHCB_ACCESSORS(rbx) 746 DEFINE_KVM_GHCB_ACCESSORS(rsi) 747 DEFINE_KVM_GHCB_ACCESSORS(sw_exit_code) 748 DEFINE_KVM_GHCB_ACCESSORS(sw_exit_info_1) 749 DEFINE_KVM_GHCB_ACCESSORS(sw_exit_info_2) 750 DEFINE_KVM_GHCB_ACCESSORS(sw_scratch) 751 DEFINE_KVM_GHCB_ACCESSORS(xcr0) 752 753 #endif 754