1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Kernel-based Virtual Machine driver for Linux 4 * 5 * AMD SVM support 6 * 7 * Copyright (C) 2006 Qumranet, Inc. 8 * Copyright 2010 Red Hat, Inc. and/or its affiliates. 9 * 10 * Authors: 11 * Yaniv Kamay <yaniv@qumranet.com> 12 * Avi Kivity <avi@qumranet.com> 13 */ 14 15 #ifndef __SVM_SVM_H 16 #define __SVM_SVM_H 17 18 #include <linux/kvm_types.h> 19 #include <linux/kvm_host.h> 20 #include <linux/bits.h> 21 22 #include <asm/svm.h> 23 #include <asm/sev-common.h> 24 25 #include "cpuid.h" 26 #include "regs.h" 27 #include "x86.h" 28 #include "pmu.h" 29 30 /* 31 * Helpers to convert to/from physical addresses for pages whose address is 32 * consumed directly by hardware. Even though it's a physical address, SVM 33 * often restricts the address to the natural width, hence 'unsigned long' 34 * instead of 'hpa_t'. 35 */ 36 static inline unsigned long __sme_page_pa(struct page *page) 37 { 38 return __sme_set(page_to_pfn(page) << PAGE_SHIFT); 39 } 40 41 static inline struct page *__sme_pa_to_page(unsigned long pa) 42 { 43 return pfn_to_page(__sme_clr(pa) >> PAGE_SHIFT); 44 } 45 46 #define IOPM_SIZE PAGE_SIZE * 3 47 #define MSRPM_SIZE PAGE_SIZE * 2 48 49 extern bool gmet_enabled; 50 extern bool npt_enabled; 51 extern int nrips; 52 extern int vgif; 53 extern bool intercept_smi; 54 extern bool vnmi; 55 extern int lbrv; 56 57 extern int tsc_aux_uret_slot __ro_after_init; 58 59 extern struct kvm_x86_ops svm_x86_ops __initdata; 60 61 /* 62 * Clean bits in VMCB. 63 * VMCB_ALL_CLEAN_MASK might also need to 64 * be updated if this enum is modified. 65 */ 66 enum { 67 VMCB_INTERCEPTS, /* Intercept vectors, TSC offset, 68 pause filter count */ 69 VMCB_PERM_MAP, /* IOPM Base and MSRPM Base */ 70 VMCB_ASID, /* ASID */ 71 VMCB_INTR, /* int_ctl, int_vector */ 72 VMCB_NPT, /* npt_en, nCR3, gPAT */ 73 VMCB_CR, /* CR0, CR3, CR4, EFER */ 74 VMCB_DR, /* DR6, DR7 */ 75 VMCB_DT, /* GDT, IDT */ 76 VMCB_SEG, /* CS, DS, SS, ES, CPL */ 77 VMCB_CR2, /* CR2 only */ 78 VMCB_LBR, /* DBGCTL, BR_FROM, BR_TO, LAST_EX_FROM, LAST_EX_TO */ 79 VMCB_AVIC, /* AVIC APIC_BAR, AVIC APIC_BACKING_PAGE, 80 * AVIC PHYSICAL_TABLE pointer, 81 * AVIC LOGICAL_TABLE pointer 82 */ 83 VMCB_CET, /* S_CET, SSP, ISST_ADDR */ 84 VMCB_SW = 31, /* Reserved for hypervisor/software use */ 85 }; 86 87 #define VMCB_ALL_CLEAN_MASK ( \ 88 (1U << VMCB_INTERCEPTS) | (1U << VMCB_PERM_MAP) | \ 89 (1U << VMCB_ASID) | (1U << VMCB_INTR) | \ 90 (1U << VMCB_NPT) | (1U << VMCB_CR) | (1U << VMCB_DR) | \ 91 (1U << VMCB_DT) | (1U << VMCB_SEG) | (1U << VMCB_CR2) | \ 92 (1U << VMCB_LBR) | (1U << VMCB_AVIC) | (1U << VMCB_CET) | \ 93 (1U << VMCB_SW)) 94 95 /* TPR and CR2 are always written before VMRUN */ 96 #define VMCB_ALWAYS_DIRTY_MASK ((1U << VMCB_INTR) | (1U << VMCB_CR2)) 97 98 #ifdef CONFIG_KVM_AMD_SEV 99 struct kvm_sev_info { 100 bool active; /* SEV enabled guest */ 101 bool es_active; /* SEV-ES enabled guest */ 102 bool need_init; /* waiting for SEV_INIT2 */ 103 unsigned int asid; /* ASID used for this guest */ 104 unsigned int handle; /* SEV firmware handle */ 105 int fd; /* SEV device fd */ 106 unsigned long policy; 107 unsigned long pages_locked; /* Number of pages locked */ 108 struct list_head regions_list; /* List of registered regions */ 109 u64 ap_jump_table; /* SEV-ES AP Jump Table address */ 110 u64 vmsa_features; 111 u16 ghcb_version; /* Highest guest GHCB protocol version allowed */ 112 /* The three fields below are protected by sev_mirror_lock */ 113 struct kvm *enc_context_owner; /* Owner of copied encryption context */ 114 struct list_head mirror_vms; /* List of VMs mirroring */ 115 struct list_head mirror_entry; /* Use as a list entry of mirrors */ 116 struct misc_cg *misc_cg; /* For misc cgroup accounting */ 117 atomic_t migration_in_progress; 118 void *snp_context; /* SNP guest context page */ 119 void *guest_req_buf; /* Bounce buffer for SNP Guest Request input */ 120 void *guest_resp_buf; /* Bounce buffer for SNP Guest Request output */ 121 struct mutex guest_req_mutex; /* Must acquire before using bounce buffers */ 122 cpumask_var_t have_run_cpus; /* CPUs that have done VMRUN for this VM. */ 123 bool snp_certs_enabled; /* SNP certificate-fetching support. */ 124 }; 125 #endif 126 127 struct kvm_svm { 128 struct kvm kvm; 129 130 /* Struct members for AVIC */ 131 u32 avic_vm_id; 132 u32 *avic_logical_id_table; 133 u64 *avic_physical_id_table; 134 struct hlist_node hnode; 135 136 #ifdef CONFIG_KVM_AMD_SEV 137 struct kvm_sev_info sev_info; 138 #endif 139 }; 140 141 struct kvm_vcpu; 142 143 struct kvm_vmcb_info { 144 struct vmcb *ptr; 145 unsigned long pa; 146 int cpu; 147 uint64_t asid_generation; 148 }; 149 150 struct vmcb_save_area_cached { 151 struct vmcb_seg es; 152 struct vmcb_seg cs; 153 struct vmcb_seg ss; 154 struct vmcb_seg ds; 155 struct vmcb_seg gdtr; 156 struct vmcb_seg idtr; 157 u8 cpl; 158 u64 efer; 159 u64 cr4; 160 u64 cr3; 161 u64 cr0; 162 u64 dr7; 163 u64 dr6; 164 u64 rflags; 165 u64 rip; 166 u64 rsp; 167 u64 s_cet; 168 u64 ssp; 169 u64 isst_addr; 170 u64 rax; 171 u64 cr2; 172 u64 g_pat; 173 u64 dbgctl; 174 u64 br_from; 175 u64 br_to; 176 u64 last_excp_from; 177 u64 last_excp_to; 178 }; 179 180 struct vmcb_ctrl_area_cached { 181 u32 intercepts[MAX_INTERCEPT]; 182 u16 pause_filter_thresh; 183 u16 pause_filter_count; 184 u64 iopm_base_pa; 185 u64 msrpm_base_pa; 186 u64 tsc_offset; 187 u32 asid; 188 u8 tlb_ctl; 189 u8 erap_ctl; 190 u32 int_ctl; 191 u32 int_vector; 192 u32 int_state; 193 u64 exit_code; 194 u64 exit_info_1; 195 u64 exit_info_2; 196 u32 exit_int_info; 197 u32 exit_int_info_err; 198 u64 misc_ctl; 199 u32 event_inj; 200 u32 event_inj_err; 201 u64 next_rip; 202 u64 nested_cr3; 203 u64 misc_ctl2; 204 u32 clean; 205 union { 206 #if IS_ENABLED(CONFIG_HYPERV) || IS_ENABLED(CONFIG_KVM_HYPERV) 207 struct hv_vmcb_enlightenments hv_enlightenments; 208 #endif 209 u8 reserved_sw[32]; 210 }; 211 }; 212 213 struct svm_nested_state { 214 struct kvm_vmcb_info vmcb02; 215 u64 hsave_msr; 216 u64 vm_cr_msr; 217 u64 vmcb12_gpa; 218 u64 last_vmcb12_gpa; 219 u64 last_bus_lock_rip; 220 221 /* 222 * The MSR permissions map used for vmcb02, which is the merge result 223 * of vmcb01 and vmcb12 224 */ 225 void *msrpm; 226 227 /* cache for control fields of the guest */ 228 struct vmcb_ctrl_area_cached ctl; 229 230 /* 231 * Note: this struct is not kept up-to-date while L2 runs; it is only 232 * valid within nested_svm_vmrun. 233 */ 234 struct vmcb_save_area_cached save; 235 236 bool initialized; 237 238 /* 239 * Indicates whether MSR bitmap for L2 needs to be rebuilt due to 240 * changes in MSR bitmap for L1 or switching to a different L2. Note, 241 * this flag can only be used reliably in conjunction with a paravirt L1 242 * which informs L0 whether any changes to MSR bitmap for L2 were done 243 * on its side. 244 */ 245 bool force_msr_bitmap_recalc; 246 }; 247 248 struct vcpu_sev_es_state { 249 /* SEV-ES support */ 250 struct sev_es_save_area *vmsa; 251 struct ghcb *ghcb; 252 u8 valid_bitmap[16]; 253 struct kvm_host_map ghcb_map; 254 bool received_first_sipi; 255 unsigned int ap_reset_hold_type; 256 257 /* SEV-ES scratch area support */ 258 u64 sw_scratch; 259 void *ghcb_sa; 260 u32 ghcb_sa_len; 261 bool ghcb_sa_sync; 262 bool ghcb_sa_free; 263 264 /* SNP Page-State-Change buffer entries currently being processed */ 265 struct { 266 u16 cur_idx; 267 u16 end_idx; 268 u16 batch_size; 269 bool is_2m; 270 } psc; 271 272 u64 ghcb_registered_gpa; 273 274 struct mutex snp_vmsa_mutex; /* Used to handle concurrent updates of VMSA. */ 275 gpa_t snp_vmsa_gpa; 276 bool snp_ap_waiting_for_reset; 277 bool snp_has_guest_vmsa; 278 }; 279 280 struct vcpu_svm { 281 struct kvm_vcpu vcpu; 282 /* vmcb always points at current_vmcb->ptr, it's purely a shorthand. */ 283 struct vmcb *vmcb; 284 struct kvm_vmcb_info vmcb01; 285 struct kvm_vmcb_info *current_vmcb; 286 u32 asid; 287 u32 sysenter_esp_hi; 288 u32 sysenter_eip_hi; 289 uint64_t tsc_aux; 290 291 u64 msr_decfg; 292 293 u64 next_rip; 294 295 u64 spec_ctrl; 296 297 u64 tsc_ratio_msr; 298 /* 299 * Contains guest-controlled bits of VIRT_SPEC_CTRL, which will be 300 * translated into the appropriate L2_CFG bits on the host to 301 * perform speculative control. 302 */ 303 u64 virt_spec_ctrl; 304 305 void *msrpm; 306 307 ulong nmi_iret_rip; 308 309 struct svm_nested_state nested; 310 311 /* NMI mask value, used when vNMI is not enabled */ 312 bool nmi_masked; 313 314 /* 315 * True when NMIs are still masked but guest IRET was just intercepted 316 * and KVM is waiting for RIP to change, which will signal that the 317 * intercepted IRET was retired and thus NMI can be unmasked. 318 */ 319 bool awaiting_iret_completion; 320 321 /* 322 * Set when KVM is awaiting IRET completion and needs to inject NMIs as 323 * soon as the IRET completes (e.g. NMI is pending injection). KVM 324 * temporarily steals RFLAGS.TF to single-step the guest in this case 325 * in order to regain control as soon as the NMI-blocking condition 326 * goes away. 327 */ 328 bool nmi_singlestep; 329 u64 nmi_singlestep_guest_rflags; 330 331 bool nmi_l1_to_l2; 332 333 unsigned long soft_int_csbase; 334 unsigned long soft_int_old_rip; 335 unsigned long soft_int_next_rip; 336 bool soft_int_injected; 337 338 u32 ldr_reg; 339 u32 dfr_reg; 340 341 /* This is essentially a shadow of the vCPU's actual entry in the 342 * Physical ID table that is programmed into the VMCB, i.e. that is 343 * seen by the CPU. If IPI virtualization is disabled, IsRunning is 344 * only ever set in the shadow, i.e. is never propagated to the "real" 345 * table, so that hardware never sees IsRunning=1. 346 */ 347 u64 avic_physical_id_entry; 348 349 /* 350 * Per-vCPU list of irqfds that are eligible to post IRQs directly to 351 * the vCPU (a.k.a. device posted IRQs, a.k.a. IRQ bypass). The list 352 * is used to reconfigure IRTEs when the vCPU is loaded/put (to set the 353 * target pCPU), when AVIC is toggled on/off (to (de)activate bypass), 354 * and if the irqfd becomes ineligible for posting (to put the IRTE 355 * back into remapped mode). 356 */ 357 struct list_head ir_list; 358 raw_spinlock_t ir_list_lock; 359 360 struct vcpu_sev_es_state sev_es; 361 362 bool guest_state_loaded; 363 364 bool avic_irq_window; 365 bool x2avic_msrs_intercepted; 366 bool lbr_msrs_intercepted; 367 368 /* Guest GIF value, used when vGIF is not enabled */ 369 bool guest_gif; 370 }; 371 372 struct svm_cpu_data { 373 u64 asid_generation; 374 u32 max_asid; 375 u32 next_asid; 376 u32 min_asid; 377 378 bool bp_spec_reduce_set; 379 380 struct vmcb *save_area; 381 unsigned long save_area_pa; 382 383 /* index = sev_asid, value = vmcb pointer */ 384 struct vmcb **sev_vmcbs; 385 }; 386 387 DECLARE_PER_CPU(struct svm_cpu_data, svm_data); 388 389 static __always_inline struct kvm_svm *to_kvm_svm(struct kvm *kvm) 390 { 391 return container_of(kvm, struct kvm_svm, kvm); 392 } 393 394 #ifdef CONFIG_KVM_AMD_SEV 395 static __always_inline struct kvm_sev_info *to_kvm_sev_info(struct kvm *kvm) 396 { 397 return &to_kvm_svm(kvm)->sev_info; 398 } 399 400 static __always_inline bool ____sev_guest(struct kvm *kvm) 401 { 402 return to_kvm_sev_info(kvm)->active; 403 } 404 static __always_inline bool ____sev_es_guest(struct kvm *kvm) 405 { 406 struct kvm_sev_info *sev = to_kvm_sev_info(kvm); 407 408 return sev->es_active && !WARN_ON_ONCE(!sev->active); 409 } 410 411 static __always_inline bool ____sev_snp_guest(struct kvm *kvm) 412 { 413 struct kvm_sev_info *sev = to_kvm_sev_info(kvm); 414 415 return (sev->vmsa_features & SVM_SEV_FEAT_SNP_ACTIVE) && 416 !WARN_ON_ONCE(!____sev_es_guest(kvm)); 417 } 418 419 static __always_inline bool is_sev_guest(struct kvm_vcpu *vcpu) 420 { 421 return ____sev_guest(vcpu->kvm); 422 } 423 static __always_inline bool is_sev_es_guest(struct kvm_vcpu *vcpu) 424 { 425 return ____sev_es_guest(vcpu->kvm); 426 } 427 428 static __always_inline bool is_sev_snp_guest(struct kvm_vcpu *vcpu) 429 { 430 return ____sev_snp_guest(vcpu->kvm); 431 } 432 #else 433 static __always_inline bool is_sev_guest(struct kvm_vcpu *vcpu) 434 { 435 return false; 436 } 437 static __always_inline bool is_sev_es_guest(struct kvm_vcpu *vcpu) 438 { 439 return false; 440 } 441 442 static __always_inline bool is_sev_snp_guest(struct kvm_vcpu *vcpu) 443 { 444 return false; 445 } 446 #endif 447 448 static inline bool ghcb_gpa_is_registered(struct vcpu_svm *svm, u64 val) 449 { 450 return svm->sev_es.ghcb_registered_gpa == val; 451 } 452 453 static inline void vmcb_mark_all_dirty(struct vmcb *vmcb) 454 { 455 vmcb->control.clean = 0; 456 } 457 458 static inline void vmcb_mark_all_clean(struct vmcb *vmcb) 459 { 460 vmcb->control.clean = VMCB_ALL_CLEAN_MASK 461 & ~VMCB_ALWAYS_DIRTY_MASK; 462 } 463 464 static inline void vmcb_mark_dirty(struct vmcb *vmcb, int bit) 465 { 466 vmcb->control.clean &= ~(1 << bit); 467 } 468 469 static inline bool vmcb12_is_dirty(struct vmcb_ctrl_area_cached *control, int bit) 470 { 471 return !test_bit(bit, (unsigned long *)&control->clean); 472 } 473 474 static inline void vmcb_set_gpat(struct vmcb *vmcb, u64 data) 475 { 476 vmcb->save.g_pat = data; 477 vmcb_mark_dirty(vmcb, VMCB_NPT); 478 } 479 480 static __always_inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu) 481 { 482 return container_of(vcpu, struct vcpu_svm, vcpu); 483 } 484 485 static inline bool svm_is_vmrun_failure(u64 exit_code) 486 { 487 if (cpu_feature_enabled(X86_FEATURE_HYPERVISOR)) 488 return (u32)exit_code == (u32)SVM_EXIT_ERR; 489 490 return exit_code == SVM_EXIT_ERR; 491 } 492 493 /* 494 * Only the PDPTRs are loaded on demand into the shadow MMU. All other 495 * fields are synchronized on VM-Exit, because accessing the VMCB is cheap. 496 * 497 * CR3 might be out of date in the VMCB but it is not marked dirty; instead, 498 * KVM_REQ_LOAD_MMU_PGD is always requested when the cached vcpu->arch.cr3 499 * is changed. svm_load_mmu_pgd() then syncs the new CR3 value into the VMCB. 500 */ 501 #define SVM_REGS_LAZY_LOAD_SET (BIT(VCPU_REG_PDPTR)) 502 503 static inline void __vmcb_set_intercept(unsigned long *intercepts, u32 bit) 504 { 505 WARN_ON_ONCE(bit >= 32 * MAX_INTERCEPT); 506 __set_bit(bit, intercepts); 507 } 508 509 static inline void __vmcb_clr_intercept(unsigned long *intercepts, u32 bit) 510 { 511 WARN_ON_ONCE(bit >= 32 * MAX_INTERCEPT); 512 __clear_bit(bit, intercepts); 513 } 514 515 static inline bool __vmcb_is_intercept(unsigned long *intercepts, u32 bit) 516 { 517 WARN_ON_ONCE(bit >= 32 * MAX_INTERCEPT); 518 return test_bit(bit, intercepts); 519 } 520 521 static inline void vmcb_set_intercept(struct vmcb_control_area *control, u32 bit) 522 { 523 __vmcb_set_intercept((unsigned long *)&control->intercepts, bit); 524 } 525 526 static inline void vmcb_clr_intercept(struct vmcb_control_area *control, u32 bit) 527 { 528 __vmcb_clr_intercept((unsigned long *)&control->intercepts, bit); 529 } 530 531 static inline bool vmcb_is_intercept(struct vmcb_control_area *control, u32 bit) 532 { 533 return __vmcb_is_intercept((unsigned long *)&control->intercepts, bit); 534 } 535 536 static inline void vmcb12_clr_intercept(struct vmcb_ctrl_area_cached *control, u32 bit) 537 { 538 __vmcb_clr_intercept((unsigned long *)&control->intercepts, bit); 539 } 540 541 static inline bool vmcb12_is_intercept(struct vmcb_ctrl_area_cached *control, u32 bit) 542 { 543 return __vmcb_is_intercept((unsigned long *)&control->intercepts, bit); 544 } 545 546 void nested_vmcb02_recalc_intercepts(struct vcpu_svm *svm); 547 548 static inline void svm_mark_intercepts_dirty(struct vcpu_svm *svm) 549 { 550 vmcb_mark_dirty(svm->vmcb01.ptr, VMCB_INTERCEPTS); 551 552 /* 553 * If L2 is active, recalculate the intercepts for vmcb02 to account 554 * for the changes made to vmcb01. All intercept configuration is done 555 * for vmcb01 and then propagated to vmcb02 to combine KVM's intercepts 556 * with L1's intercepts (from the vmcb12 snapshot). 557 */ 558 if (is_guest_mode(&svm->vcpu)) 559 nested_vmcb02_recalc_intercepts(svm); 560 } 561 562 static inline void set_exception_intercept(struct vcpu_svm *svm, u32 bit) 563 { 564 struct vmcb *vmcb = svm->vmcb01.ptr; 565 566 WARN_ON_ONCE(bit >= 32); 567 vmcb_set_intercept(&vmcb->control, INTERCEPT_EXCEPTION_OFFSET + bit); 568 569 svm_mark_intercepts_dirty(svm); 570 } 571 572 static inline void clr_exception_intercept(struct vcpu_svm *svm, u32 bit) 573 { 574 struct vmcb *vmcb = svm->vmcb01.ptr; 575 576 WARN_ON_ONCE(bit >= 32); 577 vmcb_clr_intercept(&vmcb->control, INTERCEPT_EXCEPTION_OFFSET + bit); 578 579 svm_mark_intercepts_dirty(svm); 580 } 581 582 static inline void svm_set_intercept(struct vcpu_svm *svm, int bit) 583 { 584 struct vmcb *vmcb = svm->vmcb01.ptr; 585 586 vmcb_set_intercept(&vmcb->control, bit); 587 588 svm_mark_intercepts_dirty(svm); 589 } 590 591 static inline void svm_clr_intercept(struct vcpu_svm *svm, int bit) 592 { 593 struct vmcb *vmcb = svm->vmcb01.ptr; 594 595 vmcb_clr_intercept(&vmcb->control, bit); 596 597 svm_mark_intercepts_dirty(svm); 598 } 599 600 static inline bool svm_is_intercept(struct vcpu_svm *svm, int bit) 601 { 602 return vmcb_is_intercept(&svm->vmcb->control, bit); 603 } 604 605 static inline bool nested_vgif_enabled(struct vcpu_svm *svm) 606 { 607 return guest_cpu_cap_has(&svm->vcpu, X86_FEATURE_VGIF) && 608 (svm->nested.ctl.int_ctl & V_GIF_ENABLE_MASK); 609 } 610 611 static inline struct vmcb *get_vgif_vmcb(struct vcpu_svm *svm) 612 { 613 if (!vgif) 614 return NULL; 615 616 if (is_guest_mode(&svm->vcpu) && !nested_vgif_enabled(svm)) 617 return svm->nested.vmcb02.ptr; 618 else 619 return svm->vmcb01.ptr; 620 } 621 622 static inline void enable_gif(struct vcpu_svm *svm) 623 { 624 struct vmcb *vmcb = get_vgif_vmcb(svm); 625 626 if (vmcb) 627 vmcb->control.int_ctl |= V_GIF_MASK; 628 else 629 svm->guest_gif = true; 630 } 631 632 static inline void disable_gif(struct vcpu_svm *svm) 633 { 634 struct vmcb *vmcb = get_vgif_vmcb(svm); 635 636 if (vmcb) 637 vmcb->control.int_ctl &= ~V_GIF_MASK; 638 else 639 svm->guest_gif = false; 640 } 641 642 static inline bool gif_set(struct vcpu_svm *svm) 643 { 644 struct vmcb *vmcb = get_vgif_vmcb(svm); 645 646 if (vmcb) 647 return !!(vmcb->control.int_ctl & V_GIF_MASK); 648 else 649 return svm->guest_gif; 650 } 651 652 static inline bool nested_npt_enabled(struct vcpu_svm *svm) 653 { 654 return svm->nested.ctl.misc_ctl & SVM_MISC_ENABLE_NP; 655 } 656 657 static inline bool l2_has_separate_pat(struct kvm_vcpu *vcpu) 658 { 659 /* 660 * If KVM_X86_QUIRK_NESTED_SVM_SHARED_PAT is disabled while a vCPU 661 * is running, the L2 IA32_PAT semantics for that vCPU are undefined. 662 */ 663 return nested_npt_enabled(to_svm(vcpu)) && 664 !kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_NESTED_SVM_SHARED_PAT); 665 } 666 667 static inline bool nested_vnmi_enabled(struct vcpu_svm *svm) 668 { 669 return guest_cpu_cap_has(&svm->vcpu, X86_FEATURE_VNMI) && 670 (svm->nested.ctl.int_ctl & V_NMI_ENABLE_MASK); 671 } 672 673 static inline bool is_x2apic_msrpm_offset(u32 offset) 674 { 675 /* 4 msrs per u8, and 4 u8 in u32 */ 676 u32 msr = offset * 16; 677 678 return (msr >= APIC_BASE_MSR) && 679 (msr < (APIC_BASE_MSR + 0x100)); 680 } 681 682 static inline struct vmcb *get_vnmi_vmcb_l1(struct vcpu_svm *svm) 683 { 684 if (!vnmi) 685 return NULL; 686 687 if (is_guest_mode(&svm->vcpu)) 688 return NULL; 689 else 690 return svm->vmcb01.ptr; 691 } 692 693 static inline bool is_vnmi_enabled(struct vcpu_svm *svm) 694 { 695 struct vmcb *vmcb = get_vnmi_vmcb_l1(svm); 696 697 if (vmcb) 698 return !!(vmcb->control.int_ctl & V_NMI_ENABLE_MASK); 699 else 700 return false; 701 } 702 703 static inline void svm_vmgexit_set_return_code(struct vcpu_svm *svm, 704 u64 response, u64 data) 705 { 706 ghcb_set_sw_exit_info_1(svm->sev_es.ghcb, response); 707 ghcb_set_sw_exit_info_2(svm->sev_es.ghcb, data); 708 } 709 710 static inline void svm_vmgexit_inject_exception(struct vcpu_svm *svm, u8 vector) 711 { 712 u64 data = SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_EXEPT | vector; 713 714 svm_vmgexit_set_return_code(svm, GHCB_HV_RESP_ISSUE_EXCEPTION, data); 715 } 716 717 static inline void svm_vmgexit_bad_input(struct vcpu_svm *svm, u64 suberror) 718 { 719 svm_vmgexit_set_return_code(svm, GHCB_HV_RESP_MALFORMED_INPUT, suberror); 720 } 721 722 static inline void svm_vmgexit_success(struct vcpu_svm *svm, u64 data) 723 { 724 svm_vmgexit_set_return_code(svm, GHCB_HV_RESP_NO_ACTION, data); 725 } 726 727 static inline void svm_vmgexit_no_action(struct vcpu_svm *svm, u64 data) 728 { 729 svm_vmgexit_set_return_code(svm, GHCB_HV_RESP_NO_ACTION, data); 730 } 731 732 /* 733 * The MSRPM is 8KiB in size, divided into four 2KiB ranges (the fourth range 734 * is reserved). Each MSR within a range is covered by two bits, one each for 735 * read (bit 0) and write (bit 1), where a bit value of '1' means intercepted. 736 */ 737 #define SVM_MSRPM_BYTES_PER_RANGE 2048 738 #define SVM_BITS_PER_MSR 2 739 #define SVM_MSRS_PER_BYTE (BITS_PER_BYTE / SVM_BITS_PER_MSR) 740 #define SVM_MSRS_PER_RANGE (SVM_MSRPM_BYTES_PER_RANGE * SVM_MSRS_PER_BYTE) 741 static_assert(SVM_MSRS_PER_RANGE == 8192); 742 #define SVM_MSRPM_OFFSET_MASK (SVM_MSRS_PER_RANGE - 1) 743 744 static __always_inline int svm_msrpm_bit_nr(u32 msr) 745 { 746 int range_nr; 747 748 switch (msr & ~SVM_MSRPM_OFFSET_MASK) { 749 case 0: 750 range_nr = 0; 751 break; 752 case 0xc0000000: 753 range_nr = 1; 754 break; 755 case 0xc0010000: 756 range_nr = 2; 757 break; 758 default: 759 return -EINVAL; 760 } 761 762 return range_nr * SVM_MSRPM_BYTES_PER_RANGE * BITS_PER_BYTE + 763 (msr & SVM_MSRPM_OFFSET_MASK) * SVM_BITS_PER_MSR; 764 } 765 766 #define __BUILD_SVM_MSR_BITMAP_HELPER(rtype, action, bitop, access, bit_rw) \ 767 static inline rtype svm_##action##_msr_bitmap_##access(unsigned long *bitmap, \ 768 u32 msr) \ 769 { \ 770 int bit_nr; \ 771 \ 772 bit_nr = svm_msrpm_bit_nr(msr); \ 773 if (bit_nr < 0) \ 774 return (rtype)true; \ 775 \ 776 return bitop##_bit(bit_nr + bit_rw, bitmap); \ 777 } 778 779 #define BUILD_SVM_MSR_BITMAP_HELPERS(ret_type, action, bitop) \ 780 __BUILD_SVM_MSR_BITMAP_HELPER(ret_type, action, bitop, read, 0) \ 781 __BUILD_SVM_MSR_BITMAP_HELPER(ret_type, action, bitop, write, 1) 782 783 BUILD_SVM_MSR_BITMAP_HELPERS(bool, test, test) 784 BUILD_SVM_MSR_BITMAP_HELPERS(void, clear, __clear) 785 BUILD_SVM_MSR_BITMAP_HELPERS(void, set, __set) 786 787 #define DEBUGCTL_RESERVED_BITS (~DEBUGCTLMSR_LBR) 788 789 /* svm.c */ 790 extern bool dump_invalid_vmcb; 791 792 void *svm_alloc_permissions_map(unsigned long size, gfp_t gfp_mask); 793 794 static inline void *svm_vcpu_alloc_msrpm(void) 795 { 796 return svm_alloc_permissions_map(MSRPM_SIZE, GFP_KERNEL_ACCOUNT); 797 } 798 799 #define svm_copy_lbrs(to, from) \ 800 do { \ 801 (to)->dbgctl = (from)->dbgctl; \ 802 (to)->br_from = (from)->br_from; \ 803 (to)->br_to = (from)->br_to; \ 804 (to)->last_excp_from = (from)->last_excp_from; \ 805 (to)->last_excp_to = (from)->last_excp_to; \ 806 } while (0) 807 808 void svm_vcpu_free_msrpm(void *msrpm); 809 void svm_enable_lbrv(struct kvm_vcpu *vcpu); 810 void svm_update_lbrv(struct kvm_vcpu *vcpu); 811 812 int svm_set_efer(struct kvm_vcpu *vcpu, u64 efer); 813 void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0); 814 void svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4); 815 void disable_nmi_singlestep(struct vcpu_svm *svm); 816 bool svm_smi_blocked(struct kvm_vcpu *vcpu); 817 bool svm_nmi_blocked(struct kvm_vcpu *vcpu); 818 bool svm_interrupt_blocked(struct kvm_vcpu *vcpu); 819 void svm_set_gif(struct vcpu_svm *svm, bool value); 820 int svm_invoke_exit_handler(struct kvm_vcpu *vcpu, u64 exit_code); 821 void set_msr_interception(struct kvm_vcpu *vcpu, u32 *msrpm, u32 msr, 822 int read, int write); 823 void svm_complete_interrupt_delivery(struct kvm_vcpu *vcpu, int delivery_mode, 824 int trig_mode, int vec); 825 826 void svm_set_intercept_for_msr(struct kvm_vcpu *vcpu, u32 msr, int type, bool set); 827 828 static inline void svm_disable_intercept_for_msr(struct kvm_vcpu *vcpu, 829 u32 msr, int type) 830 { 831 svm_set_intercept_for_msr(vcpu, msr, type, false); 832 } 833 834 static inline void svm_enable_intercept_for_msr(struct kvm_vcpu *vcpu, 835 u32 msr, int type) 836 { 837 svm_set_intercept_for_msr(vcpu, msr, type, true); 838 } 839 840 int svm_skip_emulated_instruction(struct kvm_vcpu *vcpu); 841 842 /* nested.c */ 843 844 #define NESTED_EXIT_HOST 0 /* Exit handled on host level */ 845 #define NESTED_EXIT_DONE 1 /* Exit caused nested vmexit */ 846 #define NESTED_EXIT_CONTINUE 2 /* Further checks needed */ 847 848 static inline bool nested_svm_virtualize_tpr(struct kvm_vcpu *vcpu) 849 { 850 struct vcpu_svm *svm = to_svm(vcpu); 851 852 return is_guest_mode(vcpu) && (svm->nested.ctl.int_ctl & V_INTR_MASKING_MASK); 853 } 854 855 static inline bool nested_exit_on_smi(struct vcpu_svm *svm) 856 { 857 return vmcb12_is_intercept(&svm->nested.ctl, INTERCEPT_SMI); 858 } 859 860 static inline bool nested_exit_on_intr(struct vcpu_svm *svm) 861 { 862 return vmcb12_is_intercept(&svm->nested.ctl, INTERCEPT_INTR); 863 } 864 865 static inline bool nested_exit_on_nmi(struct vcpu_svm *svm) 866 { 867 return vmcb12_is_intercept(&svm->nested.ctl, INTERCEPT_NMI); 868 } 869 870 int __init nested_svm_init_msrpm_merge_offsets(void); 871 872 int enter_svm_guest_mode(struct kvm_vcpu *vcpu, u64 vmcb_gpa, bool from_vmrun); 873 void svm_leave_nested(struct kvm_vcpu *vcpu); 874 void svm_free_nested(struct vcpu_svm *svm); 875 int svm_allocate_nested(struct vcpu_svm *svm); 876 int nested_svm_vmrun(struct kvm_vcpu *vcpu); 877 void svm_copy_vmrun_state(struct vmcb_save_area *to_save, 878 struct vmcb_save_area *from_save); 879 void svm_copy_vmloadsave_state(struct vmcb *to_vmcb, struct vmcb *from_vmcb); 880 void nested_svm_vmexit(struct vcpu_svm *svm); 881 882 static inline void nested_svm_simple_vmexit(struct vcpu_svm *svm, u32 exit_code) 883 { 884 svm->vmcb->control.exit_code = exit_code; 885 svm->vmcb->control.exit_info_1 = 0; 886 svm->vmcb->control.exit_info_2 = 0; 887 nested_svm_vmexit(svm); 888 } 889 890 int nested_svm_exit_handled(struct vcpu_svm *svm); 891 int nested_svm_check_permissions(struct kvm_vcpu *vcpu); 892 int nested_svm_check_cached_vmcb12(struct kvm_vcpu *vcpu); 893 int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr, 894 bool has_error_code, u32 error_code); 895 int nested_svm_exit_special(struct vcpu_svm *svm); 896 void nested_svm_update_tsc_ratio_msr(struct kvm_vcpu *vcpu); 897 void svm_write_tsc_multiplier(struct kvm_vcpu *vcpu); 898 void nested_copy_vmcb_control_to_cache(struct vcpu_svm *svm, 899 struct vmcb_control_area *control); 900 void nested_copy_vmcb_save_to_cache(struct vcpu_svm *svm, 901 struct vmcb_save_area *save); 902 void nested_sync_control_from_vmcb02(struct vcpu_svm *svm); 903 void svm_switch_vmcb(struct vcpu_svm *svm, struct kvm_vmcb_info *target_vmcb); 904 905 906 static inline void __svm_pmu_handle_nested_transition(struct vcpu_svm *svm, 907 bool defer) 908 { 909 struct kvm_pmu *pmu = vcpu_to_pmu(&svm->vcpu); 910 u64 counters = *(u64 *)pmu->pmc_has_mode_specific_enables; 911 912 __kvm_pmu_reprogram_counters(pmu, counters, defer); 913 } 914 915 static inline void svm_pmu_handle_nested_transition(struct vcpu_svm *svm) 916 { 917 /* 918 * Do NOT defer reprogramming the counters by default. Instructions 919 * causing a state change are counted based on the _new_ CPU state 920 * (e.g. a successful VMRUN is counted in guest mode). Hence, the 921 * counters should be reprogrammed with the new state _before_ the 922 * instruction is potentially counted upon emulation completion. 923 */ 924 __svm_pmu_handle_nested_transition(svm, false); 925 } 926 927 extern struct kvm_x86_nested_ops svm_nested_ops; 928 929 /* avic.c */ 930 #define AVIC_REQUIRED_APICV_INHIBITS \ 931 ( \ 932 BIT(APICV_INHIBIT_REASON_DISABLED) | \ 933 BIT(APICV_INHIBIT_REASON_ABSENT) | \ 934 BIT(APICV_INHIBIT_REASON_HYPERV) | \ 935 BIT(APICV_INHIBIT_REASON_NESTED) | \ 936 BIT(APICV_INHIBIT_REASON_IRQWIN) | \ 937 BIT(APICV_INHIBIT_REASON_PIT_REINJ) | \ 938 BIT(APICV_INHIBIT_REASON_BLOCKIRQ) | \ 939 BIT(APICV_INHIBIT_REASON_SEV) | \ 940 BIT(APICV_INHIBIT_REASON_PHYSICAL_ID_ALIASED) | \ 941 BIT(APICV_INHIBIT_REASON_APIC_ID_MODIFIED) | \ 942 BIT(APICV_INHIBIT_REASON_APIC_BASE_MODIFIED) | \ 943 BIT(APICV_INHIBIT_REASON_LOGICAL_ID_ALIASED) | \ 944 BIT(APICV_INHIBIT_REASON_PHYSICAL_ID_TOO_BIG) \ 945 ) 946 947 bool __init avic_hardware_setup(void); 948 void avic_hardware_unsetup(void); 949 int avic_alloc_physical_id_table(struct kvm *kvm); 950 void avic_vm_destroy(struct kvm *kvm); 951 int avic_vm_init(struct kvm *kvm); 952 void avic_init_vmcb(struct vcpu_svm *svm, struct vmcb *vmcb); 953 int avic_incomplete_ipi_interception(struct kvm_vcpu *vcpu); 954 int avic_unaccelerated_access_interception(struct kvm_vcpu *vcpu); 955 int avic_init_vcpu(struct vcpu_svm *svm); 956 void avic_vcpu_load(struct kvm_vcpu *vcpu, int cpu); 957 void avic_vcpu_put(struct kvm_vcpu *vcpu); 958 void avic_apicv_post_state_restore(struct kvm_vcpu *vcpu); 959 void avic_refresh_apicv_exec_ctrl(struct kvm_vcpu *vcpu); 960 int avic_pi_update_irte(struct kvm_kernel_irqfd *irqfd, struct kvm *kvm, 961 unsigned int host_irq, uint32_t guest_irq, 962 struct kvm_vcpu *vcpu, u32 vector); 963 void avic_vcpu_blocking(struct kvm_vcpu *vcpu); 964 void avic_vcpu_unblocking(struct kvm_vcpu *vcpu); 965 void avic_ring_doorbell(struct kvm_vcpu *vcpu); 966 unsigned long avic_vcpu_get_apicv_inhibit_reasons(struct kvm_vcpu *vcpu); 967 void avic_refresh_virtual_apic_mode(struct kvm_vcpu *vcpu); 968 969 970 /* sev.c */ 971 972 int pre_sev_run(struct vcpu_svm *svm, int cpu); 973 void sev_init_vmcb(struct vcpu_svm *svm, bool init_event); 974 void sev_vcpu_after_set_cpuid(struct vcpu_svm *svm); 975 int sev_es_string_io(struct vcpu_svm *svm, int size, unsigned int port, int in); 976 void sev_es_recalc_msr_intercepts(struct kvm_vcpu *vcpu); 977 void sev_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector); 978 void sev_es_prepare_switch_to_guest(struct vcpu_svm *svm, struct sev_es_save_area *hostsa); 979 void sev_es_unmap_ghcb(struct vcpu_svm *svm); 980 981 #ifdef CONFIG_KVM_AMD_SEV 982 int sev_mem_enc_ioctl(struct kvm *kvm, void __user *argp); 983 int sev_mem_enc_register_region(struct kvm *kvm, 984 struct kvm_enc_region *range); 985 int sev_mem_enc_unregister_region(struct kvm *kvm, 986 struct kvm_enc_region *range); 987 int sev_vm_copy_enc_context_from(struct kvm *kvm, unsigned int source_fd); 988 int sev_vm_move_enc_context_from(struct kvm *kvm, unsigned int source_fd); 989 void sev_guest_memory_reclaimed(struct kvm *kvm); 990 int sev_handle_vmgexit(struct kvm_vcpu *vcpu); 991 992 /* These symbols are used in common code and are stubbed below. */ 993 994 struct page *snp_safe_alloc_page_node(int node, gfp_t gfp); 995 static inline struct page *snp_safe_alloc_page(void) 996 { 997 return snp_safe_alloc_page_node(numa_node_id(), GFP_KERNEL_ACCOUNT); 998 } 999 1000 int sev_vcpu_create(struct kvm_vcpu *vcpu); 1001 void sev_free_vcpu(struct kvm_vcpu *vcpu); 1002 void sev_vm_init(struct kvm *kvm); 1003 void sev_vm_destroy(struct kvm *kvm); 1004 void __init sev_set_cpu_caps(void); 1005 void __init sev_hardware_setup(void); 1006 void sev_hardware_unsetup(void); 1007 int sev_cpu_init(struct svm_cpu_data *sd); 1008 int sev_dev_get_attr(u32 group, u64 attr, u64 *val); 1009 extern unsigned int max_sev_asid; 1010 void sev_handle_rmp_fault(struct kvm_vcpu *vcpu, gpa_t gpa, u64 error_code); 1011 int sev_gmem_prepare(struct kvm *kvm, kvm_pfn_t pfn, gfn_t gfn, int max_order); 1012 void sev_gmem_invalidate(kvm_pfn_t start, kvm_pfn_t end); 1013 int sev_gmem_max_mapping_level(struct kvm *kvm, kvm_pfn_t pfn, bool is_private); 1014 struct vmcb_save_area *sev_decrypt_vmsa(struct kvm_vcpu *vcpu); 1015 void sev_free_decrypted_vmsa(struct kvm_vcpu *vcpu, struct vmcb_save_area *vmsa); 1016 #else 1017 static inline struct page *snp_safe_alloc_page_node(int node, gfp_t gfp) 1018 { 1019 return alloc_pages_node(node, gfp | __GFP_ZERO, 0); 1020 } 1021 1022 static inline struct page *snp_safe_alloc_page(void) 1023 { 1024 return snp_safe_alloc_page_node(numa_node_id(), GFP_KERNEL_ACCOUNT); 1025 } 1026 1027 static inline int sev_vcpu_create(struct kvm_vcpu *vcpu) { return 0; } 1028 static inline void sev_free_vcpu(struct kvm_vcpu *vcpu) {} 1029 static inline void sev_vm_init(struct kvm *kvm) {} 1030 static inline void sev_vm_destroy(struct kvm *kvm) {} 1031 static inline void __init sev_set_cpu_caps(void) {} 1032 static inline void __init sev_hardware_setup(void) {} 1033 static inline void sev_hardware_unsetup(void) {} 1034 static inline int sev_cpu_init(struct svm_cpu_data *sd) { return 0; } 1035 static inline int sev_dev_get_attr(u32 group, u64 attr, u64 *val) { return -ENXIO; } 1036 #define max_sev_asid 0 1037 static inline void sev_handle_rmp_fault(struct kvm_vcpu *vcpu, gpa_t gpa, u64 error_code) {} 1038 static inline int sev_gmem_prepare(struct kvm *kvm, kvm_pfn_t pfn, gfn_t gfn, int max_order) 1039 { 1040 return 0; 1041 } 1042 static inline void sev_gmem_invalidate(kvm_pfn_t start, kvm_pfn_t end) {} 1043 static inline int sev_gmem_max_mapping_level(struct kvm *kvm, kvm_pfn_t pfn, bool is_private) 1044 { 1045 return 0; 1046 } 1047 1048 static inline struct vmcb_save_area *sev_decrypt_vmsa(struct kvm_vcpu *vcpu) 1049 { 1050 return NULL; 1051 } 1052 static inline void sev_free_decrypted_vmsa(struct kvm_vcpu *vcpu, struct vmcb_save_area *vmsa) {} 1053 #endif 1054 1055 /* vmenter.S */ 1056 1057 void __svm_sev_es_vcpu_run(struct vcpu_svm *svm, unsigned int flags, 1058 struct sev_es_save_area *hostsa); 1059 void __svm_vcpu_run(struct vcpu_svm *svm, unsigned int flags); 1060 1061 #define DEFINE_KVM_GHCB_ACCESSORS(field) \ 1062 static __always_inline u64 kvm_ghcb_get_##field(struct vcpu_svm *svm) \ 1063 { \ 1064 return READ_ONCE(svm->sev_es.ghcb->save.field); \ 1065 } \ 1066 \ 1067 static __always_inline bool kvm_ghcb_##field##_is_valid(const struct vcpu_svm *svm) \ 1068 { \ 1069 return test_bit(GHCB_BITMAP_IDX(field), \ 1070 (unsigned long *)&svm->sev_es.valid_bitmap); \ 1071 } \ 1072 \ 1073 static __always_inline u64 kvm_ghcb_get_##field##_if_valid(struct vcpu_svm *svm) \ 1074 { \ 1075 return kvm_ghcb_##field##_is_valid(svm) ? kvm_ghcb_get_##field(svm) : 0; \ 1076 } 1077 1078 DEFINE_KVM_GHCB_ACCESSORS(cpl) 1079 DEFINE_KVM_GHCB_ACCESSORS(rax) 1080 DEFINE_KVM_GHCB_ACCESSORS(rcx) 1081 DEFINE_KVM_GHCB_ACCESSORS(rdx) 1082 DEFINE_KVM_GHCB_ACCESSORS(rbx) 1083 DEFINE_KVM_GHCB_ACCESSORS(rsi) 1084 DEFINE_KVM_GHCB_ACCESSORS(sw_exit_code) 1085 DEFINE_KVM_GHCB_ACCESSORS(sw_exit_info_1) 1086 DEFINE_KVM_GHCB_ACCESSORS(sw_exit_info_2) 1087 DEFINE_KVM_GHCB_ACCESSORS(sw_scratch) 1088 DEFINE_KVM_GHCB_ACCESSORS(xcr0) 1089 DEFINE_KVM_GHCB_ACCESSORS(xss) 1090 1091 #endif 1092