1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Kernel-based Virtual Machine driver for Linux 4 * 5 * AMD SVM support 6 * 7 * Copyright (C) 2006 Qumranet, Inc. 8 * Copyright 2010 Red Hat, Inc. and/or its affiliates. 9 * 10 * Authors: 11 * Yaniv Kamay <yaniv@qumranet.com> 12 * Avi Kivity <avi@qumranet.com> 13 */ 14 15 #ifndef __SVM_SVM_H 16 #define __SVM_SVM_H 17 18 #include <linux/kvm_types.h> 19 #include <linux/kvm_host.h> 20 #include <linux/bits.h> 21 22 #include <asm/svm.h> 23 24 #define __sme_page_pa(x) __sme_set(page_to_pfn(x) << PAGE_SHIFT) 25 26 static const u32 host_save_user_msrs[] = { 27 MSR_TSC_AUX, 28 }; 29 #define NR_HOST_SAVE_USER_MSRS ARRAY_SIZE(host_save_user_msrs) 30 31 #define MAX_DIRECT_ACCESS_MSRS 18 32 #define MSRPM_OFFSETS 16 33 extern u32 msrpm_offsets[MSRPM_OFFSETS] __read_mostly; 34 extern bool npt_enabled; 35 36 enum { 37 VMCB_INTERCEPTS, /* Intercept vectors, TSC offset, 38 pause filter count */ 39 VMCB_PERM_MAP, /* IOPM Base and MSRPM Base */ 40 VMCB_ASID, /* ASID */ 41 VMCB_INTR, /* int_ctl, int_vector */ 42 VMCB_NPT, /* npt_en, nCR3, gPAT */ 43 VMCB_CR, /* CR0, CR3, CR4, EFER */ 44 VMCB_DR, /* DR6, DR7 */ 45 VMCB_DT, /* GDT, IDT */ 46 VMCB_SEG, /* CS, DS, SS, ES, CPL */ 47 VMCB_CR2, /* CR2 only */ 48 VMCB_LBR, /* DBGCTL, BR_FROM, BR_TO, LAST_EX_FROM, LAST_EX_TO */ 49 VMCB_AVIC, /* AVIC APIC_BAR, AVIC APIC_BACKING_PAGE, 50 * AVIC PHYSICAL_TABLE pointer, 51 * AVIC LOGICAL_TABLE pointer 52 */ 53 VMCB_DIRTY_MAX, 54 }; 55 56 /* TPR and CR2 are always written before VMRUN */ 57 #define VMCB_ALWAYS_DIRTY_MASK ((1U << VMCB_INTR) | (1U << VMCB_CR2)) 58 59 struct kvm_sev_info { 60 bool active; /* SEV enabled guest */ 61 bool es_active; /* SEV-ES enabled guest */ 62 unsigned int asid; /* ASID used for this guest */ 63 unsigned int handle; /* SEV firmware handle */ 64 int fd; /* SEV device fd */ 65 unsigned long pages_locked; /* Number of pages locked */ 66 struct list_head regions_list; /* List of registered regions */ 67 u64 ap_jump_table; /* SEV-ES AP Jump Table address */ 68 struct misc_cg *misc_cg; /* For misc cgroup accounting */ 69 }; 70 71 struct kvm_svm { 72 struct kvm kvm; 73 74 /* Struct members for AVIC */ 75 u32 avic_vm_id; 76 struct page *avic_logical_id_table_page; 77 struct page *avic_physical_id_table_page; 78 struct hlist_node hnode; 79 80 struct kvm_sev_info sev_info; 81 }; 82 83 struct kvm_vcpu; 84 85 struct svm_nested_state { 86 struct vmcb *hsave; 87 u64 hsave_msr; 88 u64 vm_cr_msr; 89 u64 vmcb12_gpa; 90 91 /* These are the merged vectors */ 92 u32 *msrpm; 93 94 /* A VMRUN has started but has not yet been performed, so 95 * we cannot inject a nested vmexit yet. */ 96 bool nested_run_pending; 97 98 /* cache for control fields of the guest */ 99 struct vmcb_control_area ctl; 100 101 bool initialized; 102 }; 103 104 struct vcpu_svm { 105 struct kvm_vcpu vcpu; 106 struct vmcb *vmcb; 107 unsigned long vmcb_pa; 108 struct svm_cpu_data *svm_data; 109 u32 asid; 110 uint64_t asid_generation; 111 uint64_t sysenter_esp; 112 uint64_t sysenter_eip; 113 uint64_t tsc_aux; 114 115 u64 msr_decfg; 116 117 u64 next_rip; 118 119 u64 host_user_msrs[NR_HOST_SAVE_USER_MSRS]; 120 121 u64 spec_ctrl; 122 /* 123 * Contains guest-controlled bits of VIRT_SPEC_CTRL, which will be 124 * translated into the appropriate L2_CFG bits on the host to 125 * perform speculative control. 126 */ 127 u64 virt_spec_ctrl; 128 129 u32 *msrpm; 130 131 ulong nmi_iret_rip; 132 133 struct svm_nested_state nested; 134 135 bool nmi_singlestep; 136 u64 nmi_singlestep_guest_rflags; 137 138 unsigned int3_injected; 139 unsigned long int3_rip; 140 141 /* cached guest cpuid flags for faster access */ 142 bool nrips_enabled : 1; 143 144 u32 ldr_reg; 145 u32 dfr_reg; 146 struct page *avic_backing_page; 147 u64 *avic_physical_id_cache; 148 bool avic_is_running; 149 150 /* 151 * Per-vcpu list of struct amd_svm_iommu_ir: 152 * This is used mainly to store interrupt remapping information used 153 * when update the vcpu affinity. This avoids the need to scan for 154 * IRTE and try to match ga_tag in the IOMMU driver. 155 */ 156 struct list_head ir_list; 157 spinlock_t ir_list_lock; 158 159 /* Save desired MSR intercept (read: pass-through) state */ 160 struct { 161 DECLARE_BITMAP(read, MAX_DIRECT_ACCESS_MSRS); 162 DECLARE_BITMAP(write, MAX_DIRECT_ACCESS_MSRS); 163 } shadow_msr_intercept; 164 165 /* SEV-ES support */ 166 struct vmcb_save_area *vmsa; 167 struct ghcb *ghcb; 168 struct kvm_host_map ghcb_map; 169 bool received_first_sipi; 170 171 /* SEV-ES scratch area support */ 172 void *ghcb_sa; 173 u64 ghcb_sa_len; 174 bool ghcb_sa_sync; 175 bool ghcb_sa_free; 176 177 bool guest_state_loaded; 178 }; 179 180 struct svm_cpu_data { 181 int cpu; 182 183 u64 asid_generation; 184 u32 max_asid; 185 u32 next_asid; 186 u32 min_asid; 187 struct kvm_ldttss_desc *tss_desc; 188 189 struct page *save_area; 190 struct vmcb *current_vmcb; 191 192 /* index = sev_asid, value = vmcb pointer */ 193 struct vmcb **sev_vmcbs; 194 }; 195 196 DECLARE_PER_CPU(struct svm_cpu_data *, svm_data); 197 198 void recalc_intercepts(struct vcpu_svm *svm); 199 200 static inline struct kvm_svm *to_kvm_svm(struct kvm *kvm) 201 { 202 return container_of(kvm, struct kvm_svm, kvm); 203 } 204 205 static inline bool sev_guest(struct kvm *kvm) 206 { 207 #ifdef CONFIG_KVM_AMD_SEV 208 struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info; 209 210 return sev->active; 211 #else 212 return false; 213 #endif 214 } 215 216 static inline bool sev_es_guest(struct kvm *kvm) 217 { 218 #ifdef CONFIG_KVM_AMD_SEV 219 struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info; 220 221 return sev_guest(kvm) && sev->es_active; 222 #else 223 return false; 224 #endif 225 } 226 227 static inline void vmcb_mark_all_dirty(struct vmcb *vmcb) 228 { 229 vmcb->control.clean = 0; 230 } 231 232 static inline void vmcb_mark_all_clean(struct vmcb *vmcb) 233 { 234 vmcb->control.clean = ((1 << VMCB_DIRTY_MAX) - 1) 235 & ~VMCB_ALWAYS_DIRTY_MASK; 236 } 237 238 static inline void vmcb_mark_dirty(struct vmcb *vmcb, int bit) 239 { 240 vmcb->control.clean &= ~(1 << bit); 241 } 242 243 static inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu) 244 { 245 return container_of(vcpu, struct vcpu_svm, vcpu); 246 } 247 248 static inline struct vmcb *get_host_vmcb(struct vcpu_svm *svm) 249 { 250 if (is_guest_mode(&svm->vcpu)) 251 return svm->nested.hsave; 252 else 253 return svm->vmcb; 254 } 255 256 static inline void vmcb_set_intercept(struct vmcb_control_area *control, u32 bit) 257 { 258 WARN_ON_ONCE(bit >= 32 * MAX_INTERCEPT); 259 __set_bit(bit, (unsigned long *)&control->intercepts); 260 } 261 262 static inline void vmcb_clr_intercept(struct vmcb_control_area *control, u32 bit) 263 { 264 WARN_ON_ONCE(bit >= 32 * MAX_INTERCEPT); 265 __clear_bit(bit, (unsigned long *)&control->intercepts); 266 } 267 268 static inline bool vmcb_is_intercept(struct vmcb_control_area *control, u32 bit) 269 { 270 WARN_ON_ONCE(bit >= 32 * MAX_INTERCEPT); 271 return test_bit(bit, (unsigned long *)&control->intercepts); 272 } 273 274 static inline void set_dr_intercepts(struct vcpu_svm *svm) 275 { 276 struct vmcb *vmcb = get_host_vmcb(svm); 277 278 if (!sev_es_guest(svm->vcpu.kvm)) { 279 vmcb_set_intercept(&vmcb->control, INTERCEPT_DR0_READ); 280 vmcb_set_intercept(&vmcb->control, INTERCEPT_DR1_READ); 281 vmcb_set_intercept(&vmcb->control, INTERCEPT_DR2_READ); 282 vmcb_set_intercept(&vmcb->control, INTERCEPT_DR3_READ); 283 vmcb_set_intercept(&vmcb->control, INTERCEPT_DR4_READ); 284 vmcb_set_intercept(&vmcb->control, INTERCEPT_DR5_READ); 285 vmcb_set_intercept(&vmcb->control, INTERCEPT_DR6_READ); 286 vmcb_set_intercept(&vmcb->control, INTERCEPT_DR0_WRITE); 287 vmcb_set_intercept(&vmcb->control, INTERCEPT_DR1_WRITE); 288 vmcb_set_intercept(&vmcb->control, INTERCEPT_DR2_WRITE); 289 vmcb_set_intercept(&vmcb->control, INTERCEPT_DR3_WRITE); 290 vmcb_set_intercept(&vmcb->control, INTERCEPT_DR4_WRITE); 291 vmcb_set_intercept(&vmcb->control, INTERCEPT_DR5_WRITE); 292 vmcb_set_intercept(&vmcb->control, INTERCEPT_DR6_WRITE); 293 } 294 295 vmcb_set_intercept(&vmcb->control, INTERCEPT_DR7_READ); 296 vmcb_set_intercept(&vmcb->control, INTERCEPT_DR7_WRITE); 297 298 recalc_intercepts(svm); 299 } 300 301 static inline void clr_dr_intercepts(struct vcpu_svm *svm) 302 { 303 struct vmcb *vmcb = get_host_vmcb(svm); 304 305 vmcb->control.intercepts[INTERCEPT_DR] = 0; 306 307 /* DR7 access must remain intercepted for an SEV-ES guest */ 308 if (sev_es_guest(svm->vcpu.kvm)) { 309 vmcb_set_intercept(&vmcb->control, INTERCEPT_DR7_READ); 310 vmcb_set_intercept(&vmcb->control, INTERCEPT_DR7_WRITE); 311 } 312 313 recalc_intercepts(svm); 314 } 315 316 static inline void set_exception_intercept(struct vcpu_svm *svm, u32 bit) 317 { 318 struct vmcb *vmcb = get_host_vmcb(svm); 319 320 WARN_ON_ONCE(bit >= 32); 321 vmcb_set_intercept(&vmcb->control, INTERCEPT_EXCEPTION_OFFSET + bit); 322 323 recalc_intercepts(svm); 324 } 325 326 static inline void clr_exception_intercept(struct vcpu_svm *svm, u32 bit) 327 { 328 struct vmcb *vmcb = get_host_vmcb(svm); 329 330 WARN_ON_ONCE(bit >= 32); 331 vmcb_clr_intercept(&vmcb->control, INTERCEPT_EXCEPTION_OFFSET + bit); 332 333 recalc_intercepts(svm); 334 } 335 336 static inline void svm_set_intercept(struct vcpu_svm *svm, int bit) 337 { 338 struct vmcb *vmcb = get_host_vmcb(svm); 339 340 vmcb_set_intercept(&vmcb->control, bit); 341 342 recalc_intercepts(svm); 343 } 344 345 static inline void svm_clr_intercept(struct vcpu_svm *svm, int bit) 346 { 347 struct vmcb *vmcb = get_host_vmcb(svm); 348 349 vmcb_clr_intercept(&vmcb->control, bit); 350 351 recalc_intercepts(svm); 352 } 353 354 static inline bool svm_is_intercept(struct vcpu_svm *svm, int bit) 355 { 356 return vmcb_is_intercept(&svm->vmcb->control, bit); 357 } 358 359 static inline bool vgif_enabled(struct vcpu_svm *svm) 360 { 361 return !!(svm->vmcb->control.int_ctl & V_GIF_ENABLE_MASK); 362 } 363 364 static inline void enable_gif(struct vcpu_svm *svm) 365 { 366 if (vgif_enabled(svm)) 367 svm->vmcb->control.int_ctl |= V_GIF_MASK; 368 else 369 svm->vcpu.arch.hflags |= HF_GIF_MASK; 370 } 371 372 static inline void disable_gif(struct vcpu_svm *svm) 373 { 374 if (vgif_enabled(svm)) 375 svm->vmcb->control.int_ctl &= ~V_GIF_MASK; 376 else 377 svm->vcpu.arch.hflags &= ~HF_GIF_MASK; 378 } 379 380 static inline bool gif_set(struct vcpu_svm *svm) 381 { 382 if (vgif_enabled(svm)) 383 return !!(svm->vmcb->control.int_ctl & V_GIF_MASK); 384 else 385 return !!(svm->vcpu.arch.hflags & HF_GIF_MASK); 386 } 387 388 /* svm.c */ 389 #define MSR_INVALID 0xffffffffU 390 391 extern int sev; 392 extern int sev_es; 393 extern bool dump_invalid_vmcb; 394 395 u32 svm_msrpm_offset(u32 msr); 396 u32 *svm_vcpu_alloc_msrpm(void); 397 void svm_vcpu_init_msrpm(struct kvm_vcpu *vcpu, u32 *msrpm); 398 void svm_vcpu_free_msrpm(u32 *msrpm); 399 400 int svm_set_efer(struct kvm_vcpu *vcpu, u64 efer); 401 void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0); 402 void svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4); 403 void svm_flush_tlb(struct kvm_vcpu *vcpu); 404 void disable_nmi_singlestep(struct vcpu_svm *svm); 405 bool svm_smi_blocked(struct kvm_vcpu *vcpu); 406 bool svm_nmi_blocked(struct kvm_vcpu *vcpu); 407 bool svm_interrupt_blocked(struct kvm_vcpu *vcpu); 408 void svm_set_gif(struct vcpu_svm *svm, bool value); 409 int svm_invoke_exit_handler(struct vcpu_svm *svm, u64 exit_code); 410 void set_msr_interception(struct kvm_vcpu *vcpu, u32 *msrpm, u32 msr, 411 int read, int write); 412 413 /* nested.c */ 414 415 #define NESTED_EXIT_HOST 0 /* Exit handled on host level */ 416 #define NESTED_EXIT_DONE 1 /* Exit caused nested vmexit */ 417 #define NESTED_EXIT_CONTINUE 2 /* Further checks needed */ 418 419 static inline bool nested_svm_virtualize_tpr(struct kvm_vcpu *vcpu) 420 { 421 struct vcpu_svm *svm = to_svm(vcpu); 422 423 return is_guest_mode(vcpu) && (svm->nested.ctl.int_ctl & V_INTR_MASKING_MASK); 424 } 425 426 static inline bool nested_exit_on_smi(struct vcpu_svm *svm) 427 { 428 return vmcb_is_intercept(&svm->nested.ctl, INTERCEPT_SMI); 429 } 430 431 static inline bool nested_exit_on_intr(struct vcpu_svm *svm) 432 { 433 return vmcb_is_intercept(&svm->nested.ctl, INTERCEPT_INTR); 434 } 435 436 static inline bool nested_exit_on_nmi(struct vcpu_svm *svm) 437 { 438 return vmcb_is_intercept(&svm->nested.ctl, INTERCEPT_NMI); 439 } 440 441 int enter_svm_guest_mode(struct vcpu_svm *svm, u64 vmcb_gpa, 442 struct vmcb *nested_vmcb); 443 void svm_leave_nested(struct vcpu_svm *svm); 444 void svm_free_nested(struct vcpu_svm *svm); 445 int svm_allocate_nested(struct vcpu_svm *svm); 446 int nested_svm_vmrun(struct vcpu_svm *svm); 447 void nested_svm_vmloadsave(struct vmcb *from_vmcb, struct vmcb *to_vmcb); 448 int nested_svm_vmexit(struct vcpu_svm *svm); 449 int nested_svm_exit_handled(struct vcpu_svm *svm); 450 int nested_svm_check_permissions(struct vcpu_svm *svm); 451 int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr, 452 bool has_error_code, u32 error_code); 453 int nested_svm_exit_special(struct vcpu_svm *svm); 454 void sync_nested_vmcb_control(struct vcpu_svm *svm); 455 456 extern struct kvm_x86_nested_ops svm_nested_ops; 457 458 /* avic.c */ 459 460 #define AVIC_LOGICAL_ID_ENTRY_GUEST_PHYSICAL_ID_MASK (0xFF) 461 #define AVIC_LOGICAL_ID_ENTRY_VALID_BIT 31 462 #define AVIC_LOGICAL_ID_ENTRY_VALID_MASK (1 << 31) 463 464 #define AVIC_PHYSICAL_ID_ENTRY_HOST_PHYSICAL_ID_MASK (0xFFULL) 465 #define AVIC_PHYSICAL_ID_ENTRY_BACKING_PAGE_MASK (0xFFFFFFFFFFULL << 12) 466 #define AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK (1ULL << 62) 467 #define AVIC_PHYSICAL_ID_ENTRY_VALID_MASK (1ULL << 63) 468 469 #define VMCB_AVIC_APIC_BAR_MASK 0xFFFFFFFFFF000ULL 470 471 extern int avic; 472 473 static inline void avic_update_vapic_bar(struct vcpu_svm *svm, u64 data) 474 { 475 svm->vmcb->control.avic_vapic_bar = data & VMCB_AVIC_APIC_BAR_MASK; 476 vmcb_mark_dirty(svm->vmcb, VMCB_AVIC); 477 } 478 479 static inline bool avic_vcpu_is_running(struct kvm_vcpu *vcpu) 480 { 481 struct vcpu_svm *svm = to_svm(vcpu); 482 u64 *entry = svm->avic_physical_id_cache; 483 484 if (!entry) 485 return false; 486 487 return (READ_ONCE(*entry) & AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK); 488 } 489 490 int avic_ga_log_notifier(u32 ga_tag); 491 void avic_vm_destroy(struct kvm *kvm); 492 int avic_vm_init(struct kvm *kvm); 493 void avic_init_vmcb(struct vcpu_svm *svm); 494 void svm_toggle_avic_for_irq_window(struct kvm_vcpu *vcpu, bool activate); 495 int avic_incomplete_ipi_interception(struct vcpu_svm *svm); 496 int avic_unaccelerated_access_interception(struct vcpu_svm *svm); 497 int avic_init_vcpu(struct vcpu_svm *svm); 498 void avic_vcpu_load(struct kvm_vcpu *vcpu, int cpu); 499 void avic_vcpu_put(struct kvm_vcpu *vcpu); 500 void avic_post_state_restore(struct kvm_vcpu *vcpu); 501 void svm_set_virtual_apic_mode(struct kvm_vcpu *vcpu); 502 void svm_refresh_apicv_exec_ctrl(struct kvm_vcpu *vcpu); 503 bool svm_check_apicv_inhibit_reasons(ulong bit); 504 void svm_pre_update_apicv_exec_ctrl(struct kvm *kvm, bool activate); 505 void svm_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap); 506 void svm_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr); 507 void svm_hwapic_isr_update(struct kvm_vcpu *vcpu, int max_isr); 508 int svm_deliver_avic_intr(struct kvm_vcpu *vcpu, int vec); 509 bool svm_dy_apicv_has_pending_interrupt(struct kvm_vcpu *vcpu); 510 int svm_update_pi_irte(struct kvm *kvm, unsigned int host_irq, 511 uint32_t guest_irq, bool set); 512 void svm_vcpu_blocking(struct kvm_vcpu *vcpu); 513 void svm_vcpu_unblocking(struct kvm_vcpu *vcpu); 514 515 /* sev.c */ 516 517 #define GHCB_VERSION_MAX 1ULL 518 #define GHCB_VERSION_MIN 1ULL 519 520 #define GHCB_MSR_INFO_POS 0 521 #define GHCB_MSR_INFO_MASK (BIT_ULL(12) - 1) 522 523 #define GHCB_MSR_SEV_INFO_RESP 0x001 524 #define GHCB_MSR_SEV_INFO_REQ 0x002 525 #define GHCB_MSR_VER_MAX_POS 48 526 #define GHCB_MSR_VER_MAX_MASK 0xffff 527 #define GHCB_MSR_VER_MIN_POS 32 528 #define GHCB_MSR_VER_MIN_MASK 0xffff 529 #define GHCB_MSR_CBIT_POS 24 530 #define GHCB_MSR_CBIT_MASK 0xff 531 #define GHCB_MSR_SEV_INFO(_max, _min, _cbit) \ 532 ((((_max) & GHCB_MSR_VER_MAX_MASK) << GHCB_MSR_VER_MAX_POS) | \ 533 (((_min) & GHCB_MSR_VER_MIN_MASK) << GHCB_MSR_VER_MIN_POS) | \ 534 (((_cbit) & GHCB_MSR_CBIT_MASK) << GHCB_MSR_CBIT_POS) | \ 535 GHCB_MSR_SEV_INFO_RESP) 536 537 #define GHCB_MSR_CPUID_REQ 0x004 538 #define GHCB_MSR_CPUID_RESP 0x005 539 #define GHCB_MSR_CPUID_FUNC_POS 32 540 #define GHCB_MSR_CPUID_FUNC_MASK 0xffffffff 541 #define GHCB_MSR_CPUID_VALUE_POS 32 542 #define GHCB_MSR_CPUID_VALUE_MASK 0xffffffff 543 #define GHCB_MSR_CPUID_REG_POS 30 544 #define GHCB_MSR_CPUID_REG_MASK 0x3 545 546 #define GHCB_MSR_TERM_REQ 0x100 547 #define GHCB_MSR_TERM_REASON_SET_POS 12 548 #define GHCB_MSR_TERM_REASON_SET_MASK 0xf 549 #define GHCB_MSR_TERM_REASON_POS 16 550 #define GHCB_MSR_TERM_REASON_MASK 0xff 551 552 extern unsigned int max_sev_asid; 553 554 static inline bool svm_sev_enabled(void) 555 { 556 return IS_ENABLED(CONFIG_KVM_AMD_SEV) ? max_sev_asid : 0; 557 } 558 559 void sev_vm_destroy(struct kvm *kvm); 560 int svm_mem_enc_op(struct kvm *kvm, void __user *argp); 561 int svm_register_enc_region(struct kvm *kvm, 562 struct kvm_enc_region *range); 563 int svm_unregister_enc_region(struct kvm *kvm, 564 struct kvm_enc_region *range); 565 void pre_sev_run(struct vcpu_svm *svm, int cpu); 566 void __init sev_hardware_setup(void); 567 void sev_hardware_teardown(void); 568 void sev_free_vcpu(struct kvm_vcpu *vcpu); 569 int sev_handle_vmgexit(struct vcpu_svm *svm); 570 int sev_es_string_io(struct vcpu_svm *svm, int size, unsigned int port, int in); 571 void sev_es_init_vmcb(struct vcpu_svm *svm); 572 void sev_es_create_vcpu(struct vcpu_svm *svm); 573 void sev_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector); 574 void sev_es_prepare_guest_switch(struct vcpu_svm *svm, unsigned int cpu); 575 576 /* vmenter.S */ 577 578 void __svm_sev_es_vcpu_run(unsigned long vmcb_pa); 579 void __svm_vcpu_run(unsigned long vmcb_pa, unsigned long *regs); 580 581 #endif 582