1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Kernel-based Virtual Machine driver for Linux 4 * 5 * AMD SVM support 6 * 7 * Copyright (C) 2006 Qumranet, Inc. 8 * Copyright 2010 Red Hat, Inc. and/or its affiliates. 9 * 10 * Authors: 11 * Yaniv Kamay <yaniv@qumranet.com> 12 * Avi Kivity <avi@qumranet.com> 13 */ 14 15 #ifndef __SVM_SVM_H 16 #define __SVM_SVM_H 17 18 #include <linux/kvm_types.h> 19 #include <linux/kvm_host.h> 20 #include <linux/bits.h> 21 22 #include <asm/svm.h> 23 #include <asm/sev-common.h> 24 25 #include "cpuid.h" 26 #include "kvm_cache_regs.h" 27 28 /* 29 * Helpers to convert to/from physical addresses for pages whose address is 30 * consumed directly by hardware. Even though it's a physical address, SVM 31 * often restricts the address to the natural width, hence 'unsigned long' 32 * instead of 'hpa_t'. 33 */ 34 static inline unsigned long __sme_page_pa(struct page *page) 35 { 36 return __sme_set(page_to_pfn(page) << PAGE_SHIFT); 37 } 38 39 static inline struct page *__sme_pa_to_page(unsigned long pa) 40 { 41 return pfn_to_page(__sme_clr(pa) >> PAGE_SHIFT); 42 } 43 44 #define IOPM_SIZE PAGE_SIZE * 3 45 #define MSRPM_SIZE PAGE_SIZE * 2 46 47 extern bool npt_enabled; 48 extern int nrips; 49 extern int vgif; 50 extern bool intercept_smi; 51 extern bool x2avic_enabled; 52 extern bool vnmi; 53 extern int lbrv; 54 55 /* 56 * Clean bits in VMCB. 57 * VMCB_ALL_CLEAN_MASK might also need to 58 * be updated if this enum is modified. 59 */ 60 enum { 61 VMCB_INTERCEPTS, /* Intercept vectors, TSC offset, 62 pause filter count */ 63 VMCB_PERM_MAP, /* IOPM Base and MSRPM Base */ 64 VMCB_ASID, /* ASID */ 65 VMCB_INTR, /* int_ctl, int_vector */ 66 VMCB_NPT, /* npt_en, nCR3, gPAT */ 67 VMCB_CR, /* CR0, CR3, CR4, EFER */ 68 VMCB_DR, /* DR6, DR7 */ 69 VMCB_DT, /* GDT, IDT */ 70 VMCB_SEG, /* CS, DS, SS, ES, CPL */ 71 VMCB_CR2, /* CR2 only */ 72 VMCB_LBR, /* DBGCTL, BR_FROM, BR_TO, LAST_EX_FROM, LAST_EX_TO */ 73 VMCB_AVIC, /* AVIC APIC_BAR, AVIC APIC_BACKING_PAGE, 74 * AVIC PHYSICAL_TABLE pointer, 75 * AVIC LOGICAL_TABLE pointer 76 */ 77 VMCB_SW = 31, /* Reserved for hypervisor/software use */ 78 }; 79 80 #define VMCB_ALL_CLEAN_MASK ( \ 81 (1U << VMCB_INTERCEPTS) | (1U << VMCB_PERM_MAP) | \ 82 (1U << VMCB_ASID) | (1U << VMCB_INTR) | \ 83 (1U << VMCB_NPT) | (1U << VMCB_CR) | (1U << VMCB_DR) | \ 84 (1U << VMCB_DT) | (1U << VMCB_SEG) | (1U << VMCB_CR2) | \ 85 (1U << VMCB_LBR) | (1U << VMCB_AVIC) | \ 86 (1U << VMCB_SW)) 87 88 /* TPR and CR2 are always written before VMRUN */ 89 #define VMCB_ALWAYS_DIRTY_MASK ((1U << VMCB_INTR) | (1U << VMCB_CR2)) 90 91 struct kvm_sev_info { 92 bool active; /* SEV enabled guest */ 93 bool es_active; /* SEV-ES enabled guest */ 94 bool need_init; /* waiting for SEV_INIT2 */ 95 unsigned int asid; /* ASID used for this guest */ 96 unsigned int handle; /* SEV firmware handle */ 97 int fd; /* SEV device fd */ 98 unsigned long policy; 99 unsigned long pages_locked; /* Number of pages locked */ 100 struct list_head regions_list; /* List of registered regions */ 101 u64 ap_jump_table; /* SEV-ES AP Jump Table address */ 102 u64 vmsa_features; 103 u16 ghcb_version; /* Highest guest GHCB protocol version allowed */ 104 struct kvm *enc_context_owner; /* Owner of copied encryption context */ 105 struct list_head mirror_vms; /* List of VMs mirroring */ 106 struct list_head mirror_entry; /* Use as a list entry of mirrors */ 107 struct misc_cg *misc_cg; /* For misc cgroup accounting */ 108 atomic_t migration_in_progress; 109 void *snp_context; /* SNP guest context page */ 110 void *guest_req_buf; /* Bounce buffer for SNP Guest Request input */ 111 void *guest_resp_buf; /* Bounce buffer for SNP Guest Request output */ 112 struct mutex guest_req_mutex; /* Must acquire before using bounce buffers */ 113 cpumask_var_t have_run_cpus; /* CPUs that have done VMRUN for this VM. */ 114 }; 115 116 #define SEV_POLICY_NODBG BIT_ULL(0) 117 #define SNP_POLICY_DEBUG BIT_ULL(19) 118 119 struct kvm_svm { 120 struct kvm kvm; 121 122 /* Struct members for AVIC */ 123 u32 avic_vm_id; 124 u32 *avic_logical_id_table; 125 u64 *avic_physical_id_table; 126 struct hlist_node hnode; 127 128 struct kvm_sev_info sev_info; 129 }; 130 131 struct kvm_vcpu; 132 133 struct kvm_vmcb_info { 134 struct vmcb *ptr; 135 unsigned long pa; 136 int cpu; 137 uint64_t asid_generation; 138 }; 139 140 struct vmcb_save_area_cached { 141 u64 efer; 142 u64 cr4; 143 u64 cr3; 144 u64 cr0; 145 u64 dr7; 146 u64 dr6; 147 }; 148 149 struct vmcb_ctrl_area_cached { 150 u32 intercepts[MAX_INTERCEPT]; 151 u16 pause_filter_thresh; 152 u16 pause_filter_count; 153 u64 iopm_base_pa; 154 u64 msrpm_base_pa; 155 u64 tsc_offset; 156 u32 asid; 157 u8 tlb_ctl; 158 u32 int_ctl; 159 u32 int_vector; 160 u32 int_state; 161 u32 exit_code; 162 u32 exit_code_hi; 163 u64 exit_info_1; 164 u64 exit_info_2; 165 u32 exit_int_info; 166 u32 exit_int_info_err; 167 u64 nested_ctl; 168 u32 event_inj; 169 u32 event_inj_err; 170 u64 next_rip; 171 u64 nested_cr3; 172 u64 virt_ext; 173 u32 clean; 174 u64 bus_lock_rip; 175 union { 176 #if IS_ENABLED(CONFIG_HYPERV) || IS_ENABLED(CONFIG_KVM_HYPERV) 177 struct hv_vmcb_enlightenments hv_enlightenments; 178 #endif 179 u8 reserved_sw[32]; 180 }; 181 }; 182 183 struct svm_nested_state { 184 struct kvm_vmcb_info vmcb02; 185 u64 hsave_msr; 186 u64 vm_cr_msr; 187 u64 vmcb12_gpa; 188 u64 last_vmcb12_gpa; 189 190 /* 191 * The MSR permissions map used for vmcb02, which is the merge result 192 * of vmcb01 and vmcb12 193 */ 194 void *msrpm; 195 196 /* A VMRUN has started but has not yet been performed, so 197 * we cannot inject a nested vmexit yet. */ 198 bool nested_run_pending; 199 200 /* cache for control fields of the guest */ 201 struct vmcb_ctrl_area_cached ctl; 202 203 /* 204 * Note: this struct is not kept up-to-date while L2 runs; it is only 205 * valid within nested_svm_vmrun. 206 */ 207 struct vmcb_save_area_cached save; 208 209 bool initialized; 210 211 /* 212 * Indicates whether MSR bitmap for L2 needs to be rebuilt due to 213 * changes in MSR bitmap for L1 or switching to a different L2. Note, 214 * this flag can only be used reliably in conjunction with a paravirt L1 215 * which informs L0 whether any changes to MSR bitmap for L2 were done 216 * on its side. 217 */ 218 bool force_msr_bitmap_recalc; 219 }; 220 221 struct vcpu_sev_es_state { 222 /* SEV-ES support */ 223 struct sev_es_save_area *vmsa; 224 struct ghcb *ghcb; 225 u8 valid_bitmap[16]; 226 struct kvm_host_map ghcb_map; 227 bool received_first_sipi; 228 unsigned int ap_reset_hold_type; 229 230 /* SEV-ES scratch area support */ 231 u64 sw_scratch; 232 void *ghcb_sa; 233 u32 ghcb_sa_len; 234 bool ghcb_sa_sync; 235 bool ghcb_sa_free; 236 237 /* SNP Page-State-Change buffer entries currently being processed */ 238 u16 psc_idx; 239 u16 psc_inflight; 240 bool psc_2m; 241 242 u64 ghcb_registered_gpa; 243 244 struct mutex snp_vmsa_mutex; /* Used to handle concurrent updates of VMSA. */ 245 gpa_t snp_vmsa_gpa; 246 bool snp_ap_waiting_for_reset; 247 bool snp_has_guest_vmsa; 248 }; 249 250 struct vcpu_svm { 251 struct kvm_vcpu vcpu; 252 /* vmcb always points at current_vmcb->ptr, it's purely a shorthand. */ 253 struct vmcb *vmcb; 254 struct kvm_vmcb_info vmcb01; 255 struct kvm_vmcb_info *current_vmcb; 256 u32 asid; 257 u32 sysenter_esp_hi; 258 u32 sysenter_eip_hi; 259 uint64_t tsc_aux; 260 261 u64 msr_decfg; 262 263 u64 next_rip; 264 265 u64 spec_ctrl; 266 267 u64 tsc_ratio_msr; 268 /* 269 * Contains guest-controlled bits of VIRT_SPEC_CTRL, which will be 270 * translated into the appropriate L2_CFG bits on the host to 271 * perform speculative control. 272 */ 273 u64 virt_spec_ctrl; 274 275 void *msrpm; 276 277 ulong nmi_iret_rip; 278 279 struct svm_nested_state nested; 280 281 /* NMI mask value, used when vNMI is not enabled */ 282 bool nmi_masked; 283 284 /* 285 * True when NMIs are still masked but guest IRET was just intercepted 286 * and KVM is waiting for RIP to change, which will signal that the 287 * intercepted IRET was retired and thus NMI can be unmasked. 288 */ 289 bool awaiting_iret_completion; 290 291 /* 292 * Set when KVM is awaiting IRET completion and needs to inject NMIs as 293 * soon as the IRET completes (e.g. NMI is pending injection). KVM 294 * temporarily steals RFLAGS.TF to single-step the guest in this case 295 * in order to regain control as soon as the NMI-blocking condition 296 * goes away. 297 */ 298 bool nmi_singlestep; 299 u64 nmi_singlestep_guest_rflags; 300 301 bool nmi_l1_to_l2; 302 303 unsigned long soft_int_csbase; 304 unsigned long soft_int_old_rip; 305 unsigned long soft_int_next_rip; 306 bool soft_int_injected; 307 308 u32 ldr_reg; 309 u32 dfr_reg; 310 311 /* This is essentially a shadow of the vCPU's actual entry in the 312 * Physical ID table that is programmed into the VMCB, i.e. that is 313 * seen by the CPU. If IPI virtualization is disabled, IsRunning is 314 * only ever set in the shadow, i.e. is never propagated to the "real" 315 * table, so that hardware never sees IsRunning=1. 316 */ 317 u64 avic_physical_id_entry; 318 319 /* 320 * Per-vCPU list of irqfds that are eligible to post IRQs directly to 321 * the vCPU (a.k.a. device posted IRQs, a.k.a. IRQ bypass). The list 322 * is used to reconfigure IRTEs when the vCPU is loaded/put (to set the 323 * target pCPU), when AVIC is toggled on/off (to (de)activate bypass), 324 * and if the irqfd becomes ineligible for posting (to put the IRTE 325 * back into remapped mode). 326 */ 327 struct list_head ir_list; 328 spinlock_t ir_list_lock; 329 330 struct vcpu_sev_es_state sev_es; 331 332 bool guest_state_loaded; 333 334 bool x2avic_msrs_intercepted; 335 336 /* Guest GIF value, used when vGIF is not enabled */ 337 bool guest_gif; 338 }; 339 340 struct svm_cpu_data { 341 u64 asid_generation; 342 u32 max_asid; 343 u32 next_asid; 344 u32 min_asid; 345 346 bool bp_spec_reduce_set; 347 348 struct vmcb *save_area; 349 unsigned long save_area_pa; 350 351 /* index = sev_asid, value = vmcb pointer */ 352 struct vmcb **sev_vmcbs; 353 }; 354 355 DECLARE_PER_CPU(struct svm_cpu_data, svm_data); 356 357 void recalc_intercepts(struct vcpu_svm *svm); 358 359 static __always_inline struct kvm_svm *to_kvm_svm(struct kvm *kvm) 360 { 361 return container_of(kvm, struct kvm_svm, kvm); 362 } 363 364 static __always_inline struct kvm_sev_info *to_kvm_sev_info(struct kvm *kvm) 365 { 366 return &to_kvm_svm(kvm)->sev_info; 367 } 368 369 #ifdef CONFIG_KVM_AMD_SEV 370 static __always_inline bool sev_guest(struct kvm *kvm) 371 { 372 return to_kvm_sev_info(kvm)->active; 373 } 374 static __always_inline bool sev_es_guest(struct kvm *kvm) 375 { 376 struct kvm_sev_info *sev = to_kvm_sev_info(kvm); 377 378 return sev->es_active && !WARN_ON_ONCE(!sev->active); 379 } 380 381 static __always_inline bool sev_snp_guest(struct kvm *kvm) 382 { 383 struct kvm_sev_info *sev = to_kvm_sev_info(kvm); 384 385 return (sev->vmsa_features & SVM_SEV_FEAT_SNP_ACTIVE) && 386 !WARN_ON_ONCE(!sev_es_guest(kvm)); 387 } 388 #else 389 #define sev_guest(kvm) false 390 #define sev_es_guest(kvm) false 391 #define sev_snp_guest(kvm) false 392 #endif 393 394 static inline bool ghcb_gpa_is_registered(struct vcpu_svm *svm, u64 val) 395 { 396 return svm->sev_es.ghcb_registered_gpa == val; 397 } 398 399 static inline void vmcb_mark_all_dirty(struct vmcb *vmcb) 400 { 401 vmcb->control.clean = 0; 402 } 403 404 static inline void vmcb_mark_all_clean(struct vmcb *vmcb) 405 { 406 vmcb->control.clean = VMCB_ALL_CLEAN_MASK 407 & ~VMCB_ALWAYS_DIRTY_MASK; 408 } 409 410 static inline void vmcb_mark_dirty(struct vmcb *vmcb, int bit) 411 { 412 vmcb->control.clean &= ~(1 << bit); 413 } 414 415 static inline bool vmcb_is_dirty(struct vmcb *vmcb, int bit) 416 { 417 return !test_bit(bit, (unsigned long *)&vmcb->control.clean); 418 } 419 420 static __always_inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu) 421 { 422 return container_of(vcpu, struct vcpu_svm, vcpu); 423 } 424 425 /* 426 * Only the PDPTRs are loaded on demand into the shadow MMU. All other 427 * fields are synchronized on VM-Exit, because accessing the VMCB is cheap. 428 * 429 * CR3 might be out of date in the VMCB but it is not marked dirty; instead, 430 * KVM_REQ_LOAD_MMU_PGD is always requested when the cached vcpu->arch.cr3 431 * is changed. svm_load_mmu_pgd() then syncs the new CR3 value into the VMCB. 432 */ 433 #define SVM_REGS_LAZY_LOAD_SET (1 << VCPU_EXREG_PDPTR) 434 435 static inline void vmcb_set_intercept(struct vmcb_control_area *control, u32 bit) 436 { 437 WARN_ON_ONCE(bit >= 32 * MAX_INTERCEPT); 438 __set_bit(bit, (unsigned long *)&control->intercepts); 439 } 440 441 static inline void vmcb_clr_intercept(struct vmcb_control_area *control, u32 bit) 442 { 443 WARN_ON_ONCE(bit >= 32 * MAX_INTERCEPT); 444 __clear_bit(bit, (unsigned long *)&control->intercepts); 445 } 446 447 static inline bool vmcb_is_intercept(struct vmcb_control_area *control, u32 bit) 448 { 449 WARN_ON_ONCE(bit >= 32 * MAX_INTERCEPT); 450 return test_bit(bit, (unsigned long *)&control->intercepts); 451 } 452 453 static inline bool vmcb12_is_intercept(struct vmcb_ctrl_area_cached *control, u32 bit) 454 { 455 WARN_ON_ONCE(bit >= 32 * MAX_INTERCEPT); 456 return test_bit(bit, (unsigned long *)&control->intercepts); 457 } 458 459 static inline void set_exception_intercept(struct vcpu_svm *svm, u32 bit) 460 { 461 struct vmcb *vmcb = svm->vmcb01.ptr; 462 463 WARN_ON_ONCE(bit >= 32); 464 vmcb_set_intercept(&vmcb->control, INTERCEPT_EXCEPTION_OFFSET + bit); 465 466 recalc_intercepts(svm); 467 } 468 469 static inline void clr_exception_intercept(struct vcpu_svm *svm, u32 bit) 470 { 471 struct vmcb *vmcb = svm->vmcb01.ptr; 472 473 WARN_ON_ONCE(bit >= 32); 474 vmcb_clr_intercept(&vmcb->control, INTERCEPT_EXCEPTION_OFFSET + bit); 475 476 recalc_intercepts(svm); 477 } 478 479 static inline void svm_set_intercept(struct vcpu_svm *svm, int bit) 480 { 481 struct vmcb *vmcb = svm->vmcb01.ptr; 482 483 vmcb_set_intercept(&vmcb->control, bit); 484 485 recalc_intercepts(svm); 486 } 487 488 static inline void svm_clr_intercept(struct vcpu_svm *svm, int bit) 489 { 490 struct vmcb *vmcb = svm->vmcb01.ptr; 491 492 vmcb_clr_intercept(&vmcb->control, bit); 493 494 recalc_intercepts(svm); 495 } 496 497 static inline bool svm_is_intercept(struct vcpu_svm *svm, int bit) 498 { 499 return vmcb_is_intercept(&svm->vmcb->control, bit); 500 } 501 502 static inline bool nested_vgif_enabled(struct vcpu_svm *svm) 503 { 504 return guest_cpu_cap_has(&svm->vcpu, X86_FEATURE_VGIF) && 505 (svm->nested.ctl.int_ctl & V_GIF_ENABLE_MASK); 506 } 507 508 static inline struct vmcb *get_vgif_vmcb(struct vcpu_svm *svm) 509 { 510 if (!vgif) 511 return NULL; 512 513 if (is_guest_mode(&svm->vcpu) && !nested_vgif_enabled(svm)) 514 return svm->nested.vmcb02.ptr; 515 else 516 return svm->vmcb01.ptr; 517 } 518 519 static inline void enable_gif(struct vcpu_svm *svm) 520 { 521 struct vmcb *vmcb = get_vgif_vmcb(svm); 522 523 if (vmcb) 524 vmcb->control.int_ctl |= V_GIF_MASK; 525 else 526 svm->guest_gif = true; 527 } 528 529 static inline void disable_gif(struct vcpu_svm *svm) 530 { 531 struct vmcb *vmcb = get_vgif_vmcb(svm); 532 533 if (vmcb) 534 vmcb->control.int_ctl &= ~V_GIF_MASK; 535 else 536 svm->guest_gif = false; 537 } 538 539 static inline bool gif_set(struct vcpu_svm *svm) 540 { 541 struct vmcb *vmcb = get_vgif_vmcb(svm); 542 543 if (vmcb) 544 return !!(vmcb->control.int_ctl & V_GIF_MASK); 545 else 546 return svm->guest_gif; 547 } 548 549 static inline bool nested_npt_enabled(struct vcpu_svm *svm) 550 { 551 return svm->nested.ctl.nested_ctl & SVM_NESTED_CTL_NP_ENABLE; 552 } 553 554 static inline bool nested_vnmi_enabled(struct vcpu_svm *svm) 555 { 556 return guest_cpu_cap_has(&svm->vcpu, X86_FEATURE_VNMI) && 557 (svm->nested.ctl.int_ctl & V_NMI_ENABLE_MASK); 558 } 559 560 static inline bool is_x2apic_msrpm_offset(u32 offset) 561 { 562 /* 4 msrs per u8, and 4 u8 in u32 */ 563 u32 msr = offset * 16; 564 565 return (msr >= APIC_BASE_MSR) && 566 (msr < (APIC_BASE_MSR + 0x100)); 567 } 568 569 static inline struct vmcb *get_vnmi_vmcb_l1(struct vcpu_svm *svm) 570 { 571 if (!vnmi) 572 return NULL; 573 574 if (is_guest_mode(&svm->vcpu)) 575 return NULL; 576 else 577 return svm->vmcb01.ptr; 578 } 579 580 static inline bool is_vnmi_enabled(struct vcpu_svm *svm) 581 { 582 struct vmcb *vmcb = get_vnmi_vmcb_l1(svm); 583 584 if (vmcb) 585 return !!(vmcb->control.int_ctl & V_NMI_ENABLE_MASK); 586 else 587 return false; 588 } 589 590 static inline void svm_vmgexit_set_return_code(struct vcpu_svm *svm, 591 u64 response, u64 data) 592 { 593 ghcb_set_sw_exit_info_1(svm->sev_es.ghcb, response); 594 ghcb_set_sw_exit_info_2(svm->sev_es.ghcb, data); 595 } 596 597 static inline void svm_vmgexit_inject_exception(struct vcpu_svm *svm, u8 vector) 598 { 599 u64 data = SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_EXEPT | vector; 600 601 svm_vmgexit_set_return_code(svm, GHCB_HV_RESP_ISSUE_EXCEPTION, data); 602 } 603 604 static inline void svm_vmgexit_bad_input(struct vcpu_svm *svm, u64 suberror) 605 { 606 svm_vmgexit_set_return_code(svm, GHCB_HV_RESP_MALFORMED_INPUT, suberror); 607 } 608 609 static inline void svm_vmgexit_success(struct vcpu_svm *svm, u64 data) 610 { 611 svm_vmgexit_set_return_code(svm, GHCB_HV_RESP_NO_ACTION, data); 612 } 613 614 static inline void svm_vmgexit_no_action(struct vcpu_svm *svm, u64 data) 615 { 616 svm_vmgexit_set_return_code(svm, GHCB_HV_RESP_NO_ACTION, data); 617 } 618 619 /* 620 * The MSRPM is 8KiB in size, divided into four 2KiB ranges (the fourth range 621 * is reserved). Each MSR within a range is covered by two bits, one each for 622 * read (bit 0) and write (bit 1), where a bit value of '1' means intercepted. 623 */ 624 #define SVM_MSRPM_BYTES_PER_RANGE 2048 625 #define SVM_BITS_PER_MSR 2 626 #define SVM_MSRS_PER_BYTE (BITS_PER_BYTE / SVM_BITS_PER_MSR) 627 #define SVM_MSRS_PER_RANGE (SVM_MSRPM_BYTES_PER_RANGE * SVM_MSRS_PER_BYTE) 628 static_assert(SVM_MSRS_PER_RANGE == 8192); 629 #define SVM_MSRPM_OFFSET_MASK (SVM_MSRS_PER_RANGE - 1) 630 631 static __always_inline int svm_msrpm_bit_nr(u32 msr) 632 { 633 int range_nr; 634 635 switch (msr & ~SVM_MSRPM_OFFSET_MASK) { 636 case 0: 637 range_nr = 0; 638 break; 639 case 0xc0000000: 640 range_nr = 1; 641 break; 642 case 0xc0010000: 643 range_nr = 2; 644 break; 645 default: 646 return -EINVAL; 647 } 648 649 return range_nr * SVM_MSRPM_BYTES_PER_RANGE * BITS_PER_BYTE + 650 (msr & SVM_MSRPM_OFFSET_MASK) * SVM_BITS_PER_MSR; 651 } 652 653 #define __BUILD_SVM_MSR_BITMAP_HELPER(rtype, action, bitop, access, bit_rw) \ 654 static inline rtype svm_##action##_msr_bitmap_##access(unsigned long *bitmap, \ 655 u32 msr) \ 656 { \ 657 int bit_nr; \ 658 \ 659 bit_nr = svm_msrpm_bit_nr(msr); \ 660 if (bit_nr < 0) \ 661 return (rtype)true; \ 662 \ 663 return bitop##_bit(bit_nr + bit_rw, bitmap); \ 664 } 665 666 #define BUILD_SVM_MSR_BITMAP_HELPERS(ret_type, action, bitop) \ 667 __BUILD_SVM_MSR_BITMAP_HELPER(ret_type, action, bitop, read, 0) \ 668 __BUILD_SVM_MSR_BITMAP_HELPER(ret_type, action, bitop, write, 1) 669 670 BUILD_SVM_MSR_BITMAP_HELPERS(bool, test, test) 671 BUILD_SVM_MSR_BITMAP_HELPERS(void, clear, __clear) 672 BUILD_SVM_MSR_BITMAP_HELPERS(void, set, __set) 673 674 #define DEBUGCTL_RESERVED_BITS (~DEBUGCTLMSR_LBR) 675 676 /* svm.c */ 677 extern bool dump_invalid_vmcb; 678 679 void *svm_alloc_permissions_map(unsigned long size, gfp_t gfp_mask); 680 681 static inline void *svm_vcpu_alloc_msrpm(void) 682 { 683 return svm_alloc_permissions_map(MSRPM_SIZE, GFP_KERNEL_ACCOUNT); 684 } 685 686 void svm_vcpu_free_msrpm(void *msrpm); 687 void svm_copy_lbrs(struct vmcb *to_vmcb, struct vmcb *from_vmcb); 688 void svm_enable_lbrv(struct kvm_vcpu *vcpu); 689 void svm_update_lbrv(struct kvm_vcpu *vcpu); 690 691 int svm_set_efer(struct kvm_vcpu *vcpu, u64 efer); 692 void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0); 693 void svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4); 694 void disable_nmi_singlestep(struct vcpu_svm *svm); 695 bool svm_smi_blocked(struct kvm_vcpu *vcpu); 696 bool svm_nmi_blocked(struct kvm_vcpu *vcpu); 697 bool svm_interrupt_blocked(struct kvm_vcpu *vcpu); 698 void svm_set_gif(struct vcpu_svm *svm, bool value); 699 int svm_invoke_exit_handler(struct kvm_vcpu *vcpu, u64 exit_code); 700 void set_msr_interception(struct kvm_vcpu *vcpu, u32 *msrpm, u32 msr, 701 int read, int write); 702 void svm_set_x2apic_msr_interception(struct vcpu_svm *svm, bool disable); 703 void svm_complete_interrupt_delivery(struct kvm_vcpu *vcpu, int delivery_mode, 704 int trig_mode, int vec); 705 706 void svm_set_intercept_for_msr(struct kvm_vcpu *vcpu, u32 msr, int type, bool set); 707 708 static inline void svm_disable_intercept_for_msr(struct kvm_vcpu *vcpu, 709 u32 msr, int type) 710 { 711 svm_set_intercept_for_msr(vcpu, msr, type, false); 712 } 713 714 static inline void svm_enable_intercept_for_msr(struct kvm_vcpu *vcpu, 715 u32 msr, int type) 716 { 717 svm_set_intercept_for_msr(vcpu, msr, type, true); 718 } 719 720 /* nested.c */ 721 722 #define NESTED_EXIT_HOST 0 /* Exit handled on host level */ 723 #define NESTED_EXIT_DONE 1 /* Exit caused nested vmexit */ 724 #define NESTED_EXIT_CONTINUE 2 /* Further checks needed */ 725 726 static inline bool nested_svm_virtualize_tpr(struct kvm_vcpu *vcpu) 727 { 728 struct vcpu_svm *svm = to_svm(vcpu); 729 730 return is_guest_mode(vcpu) && (svm->nested.ctl.int_ctl & V_INTR_MASKING_MASK); 731 } 732 733 static inline bool nested_exit_on_smi(struct vcpu_svm *svm) 734 { 735 return vmcb12_is_intercept(&svm->nested.ctl, INTERCEPT_SMI); 736 } 737 738 static inline bool nested_exit_on_intr(struct vcpu_svm *svm) 739 { 740 return vmcb12_is_intercept(&svm->nested.ctl, INTERCEPT_INTR); 741 } 742 743 static inline bool nested_exit_on_nmi(struct vcpu_svm *svm) 744 { 745 return vmcb12_is_intercept(&svm->nested.ctl, INTERCEPT_NMI); 746 } 747 748 int __init nested_svm_init_msrpm_merge_offsets(void); 749 750 int enter_svm_guest_mode(struct kvm_vcpu *vcpu, 751 u64 vmcb_gpa, struct vmcb *vmcb12, bool from_vmrun); 752 void svm_leave_nested(struct kvm_vcpu *vcpu); 753 void svm_free_nested(struct vcpu_svm *svm); 754 int svm_allocate_nested(struct vcpu_svm *svm); 755 int nested_svm_vmrun(struct kvm_vcpu *vcpu); 756 void svm_copy_vmrun_state(struct vmcb_save_area *to_save, 757 struct vmcb_save_area *from_save); 758 void svm_copy_vmloadsave_state(struct vmcb *to_vmcb, struct vmcb *from_vmcb); 759 int nested_svm_vmexit(struct vcpu_svm *svm); 760 761 static inline int nested_svm_simple_vmexit(struct vcpu_svm *svm, u32 exit_code) 762 { 763 svm->vmcb->control.exit_code = exit_code; 764 svm->vmcb->control.exit_info_1 = 0; 765 svm->vmcb->control.exit_info_2 = 0; 766 return nested_svm_vmexit(svm); 767 } 768 769 int nested_svm_exit_handled(struct vcpu_svm *svm); 770 int nested_svm_check_permissions(struct kvm_vcpu *vcpu); 771 int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr, 772 bool has_error_code, u32 error_code); 773 int nested_svm_exit_special(struct vcpu_svm *svm); 774 void nested_svm_update_tsc_ratio_msr(struct kvm_vcpu *vcpu); 775 void svm_write_tsc_multiplier(struct kvm_vcpu *vcpu); 776 void nested_copy_vmcb_control_to_cache(struct vcpu_svm *svm, 777 struct vmcb_control_area *control); 778 void nested_copy_vmcb_save_to_cache(struct vcpu_svm *svm, 779 struct vmcb_save_area *save); 780 void nested_sync_control_from_vmcb02(struct vcpu_svm *svm); 781 void nested_vmcb02_compute_g_pat(struct vcpu_svm *svm); 782 void svm_switch_vmcb(struct vcpu_svm *svm, struct kvm_vmcb_info *target_vmcb); 783 784 extern struct kvm_x86_nested_ops svm_nested_ops; 785 786 /* avic.c */ 787 #define AVIC_REQUIRED_APICV_INHIBITS \ 788 ( \ 789 BIT(APICV_INHIBIT_REASON_DISABLED) | \ 790 BIT(APICV_INHIBIT_REASON_ABSENT) | \ 791 BIT(APICV_INHIBIT_REASON_HYPERV) | \ 792 BIT(APICV_INHIBIT_REASON_NESTED) | \ 793 BIT(APICV_INHIBIT_REASON_IRQWIN) | \ 794 BIT(APICV_INHIBIT_REASON_PIT_REINJ) | \ 795 BIT(APICV_INHIBIT_REASON_BLOCKIRQ) | \ 796 BIT(APICV_INHIBIT_REASON_SEV) | \ 797 BIT(APICV_INHIBIT_REASON_PHYSICAL_ID_ALIASED) | \ 798 BIT(APICV_INHIBIT_REASON_APIC_ID_MODIFIED) | \ 799 BIT(APICV_INHIBIT_REASON_APIC_BASE_MODIFIED) | \ 800 BIT(APICV_INHIBIT_REASON_LOGICAL_ID_ALIASED) | \ 801 BIT(APICV_INHIBIT_REASON_PHYSICAL_ID_TOO_BIG) \ 802 ) 803 804 bool avic_hardware_setup(void); 805 int avic_ga_log_notifier(u32 ga_tag); 806 void avic_vm_destroy(struct kvm *kvm); 807 int avic_vm_init(struct kvm *kvm); 808 void avic_init_vmcb(struct vcpu_svm *svm, struct vmcb *vmcb); 809 int avic_incomplete_ipi_interception(struct kvm_vcpu *vcpu); 810 int avic_unaccelerated_access_interception(struct kvm_vcpu *vcpu); 811 int avic_init_vcpu(struct vcpu_svm *svm); 812 void avic_vcpu_load(struct kvm_vcpu *vcpu, int cpu); 813 void avic_vcpu_put(struct kvm_vcpu *vcpu); 814 void avic_apicv_post_state_restore(struct kvm_vcpu *vcpu); 815 void avic_refresh_apicv_exec_ctrl(struct kvm_vcpu *vcpu); 816 int avic_pi_update_irte(struct kvm_kernel_irqfd *irqfd, struct kvm *kvm, 817 unsigned int host_irq, uint32_t guest_irq, 818 struct kvm_vcpu *vcpu, u32 vector); 819 void avic_vcpu_blocking(struct kvm_vcpu *vcpu); 820 void avic_vcpu_unblocking(struct kvm_vcpu *vcpu); 821 void avic_ring_doorbell(struct kvm_vcpu *vcpu); 822 unsigned long avic_vcpu_get_apicv_inhibit_reasons(struct kvm_vcpu *vcpu); 823 void avic_refresh_virtual_apic_mode(struct kvm_vcpu *vcpu); 824 825 826 /* sev.c */ 827 828 int pre_sev_run(struct vcpu_svm *svm, int cpu); 829 void sev_init_vmcb(struct vcpu_svm *svm); 830 void sev_vcpu_after_set_cpuid(struct vcpu_svm *svm); 831 int sev_es_string_io(struct vcpu_svm *svm, int size, unsigned int port, int in); 832 void sev_es_vcpu_reset(struct vcpu_svm *svm); 833 void sev_es_recalc_msr_intercepts(struct kvm_vcpu *vcpu); 834 void sev_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector); 835 void sev_es_prepare_switch_to_guest(struct vcpu_svm *svm, struct sev_es_save_area *hostsa); 836 void sev_es_unmap_ghcb(struct vcpu_svm *svm); 837 838 #ifdef CONFIG_KVM_AMD_SEV 839 int sev_mem_enc_ioctl(struct kvm *kvm, void __user *argp); 840 int sev_mem_enc_register_region(struct kvm *kvm, 841 struct kvm_enc_region *range); 842 int sev_mem_enc_unregister_region(struct kvm *kvm, 843 struct kvm_enc_region *range); 844 int sev_vm_copy_enc_context_from(struct kvm *kvm, unsigned int source_fd); 845 int sev_vm_move_enc_context_from(struct kvm *kvm, unsigned int source_fd); 846 void sev_guest_memory_reclaimed(struct kvm *kvm); 847 int sev_handle_vmgexit(struct kvm_vcpu *vcpu); 848 849 /* These symbols are used in common code and are stubbed below. */ 850 851 struct page *snp_safe_alloc_page_node(int node, gfp_t gfp); 852 static inline struct page *snp_safe_alloc_page(void) 853 { 854 return snp_safe_alloc_page_node(numa_node_id(), GFP_KERNEL_ACCOUNT); 855 } 856 857 void sev_free_vcpu(struct kvm_vcpu *vcpu); 858 void sev_vm_destroy(struct kvm *kvm); 859 void __init sev_set_cpu_caps(void); 860 void __init sev_hardware_setup(void); 861 void sev_hardware_unsetup(void); 862 int sev_cpu_init(struct svm_cpu_data *sd); 863 int sev_dev_get_attr(u32 group, u64 attr, u64 *val); 864 extern unsigned int max_sev_asid; 865 void sev_handle_rmp_fault(struct kvm_vcpu *vcpu, gpa_t gpa, u64 error_code); 866 void sev_snp_init_protected_guest_state(struct kvm_vcpu *vcpu); 867 int sev_gmem_prepare(struct kvm *kvm, kvm_pfn_t pfn, gfn_t gfn, int max_order); 868 void sev_gmem_invalidate(kvm_pfn_t start, kvm_pfn_t end); 869 int sev_private_max_mapping_level(struct kvm *kvm, kvm_pfn_t pfn); 870 struct vmcb_save_area *sev_decrypt_vmsa(struct kvm_vcpu *vcpu); 871 void sev_free_decrypted_vmsa(struct kvm_vcpu *vcpu, struct vmcb_save_area *vmsa); 872 #else 873 static inline struct page *snp_safe_alloc_page_node(int node, gfp_t gfp) 874 { 875 return alloc_pages_node(node, gfp | __GFP_ZERO, 0); 876 } 877 878 static inline struct page *snp_safe_alloc_page(void) 879 { 880 return snp_safe_alloc_page_node(numa_node_id(), GFP_KERNEL_ACCOUNT); 881 } 882 883 static inline void sev_free_vcpu(struct kvm_vcpu *vcpu) {} 884 static inline void sev_vm_destroy(struct kvm *kvm) {} 885 static inline void __init sev_set_cpu_caps(void) {} 886 static inline void __init sev_hardware_setup(void) {} 887 static inline void sev_hardware_unsetup(void) {} 888 static inline int sev_cpu_init(struct svm_cpu_data *sd) { return 0; } 889 static inline int sev_dev_get_attr(u32 group, u64 attr, u64 *val) { return -ENXIO; } 890 #define max_sev_asid 0 891 static inline void sev_handle_rmp_fault(struct kvm_vcpu *vcpu, gpa_t gpa, u64 error_code) {} 892 static inline void sev_snp_init_protected_guest_state(struct kvm_vcpu *vcpu) {} 893 static inline int sev_gmem_prepare(struct kvm *kvm, kvm_pfn_t pfn, gfn_t gfn, int max_order) 894 { 895 return 0; 896 } 897 static inline void sev_gmem_invalidate(kvm_pfn_t start, kvm_pfn_t end) {} 898 static inline int sev_private_max_mapping_level(struct kvm *kvm, kvm_pfn_t pfn) 899 { 900 return 0; 901 } 902 903 static inline struct vmcb_save_area *sev_decrypt_vmsa(struct kvm_vcpu *vcpu) 904 { 905 return NULL; 906 } 907 static inline void sev_free_decrypted_vmsa(struct kvm_vcpu *vcpu, struct vmcb_save_area *vmsa) {} 908 #endif 909 910 /* vmenter.S */ 911 912 void __svm_sev_es_vcpu_run(struct vcpu_svm *svm, bool spec_ctrl_intercepted, 913 struct sev_es_save_area *hostsa); 914 void __svm_vcpu_run(struct vcpu_svm *svm, bool spec_ctrl_intercepted); 915 916 #define DEFINE_KVM_GHCB_ACCESSORS(field) \ 917 static __always_inline bool kvm_ghcb_##field##_is_valid(const struct vcpu_svm *svm) \ 918 { \ 919 return test_bit(GHCB_BITMAP_IDX(field), \ 920 (unsigned long *)&svm->sev_es.valid_bitmap); \ 921 } \ 922 \ 923 static __always_inline u64 kvm_ghcb_get_##field##_if_valid(struct vcpu_svm *svm, struct ghcb *ghcb) \ 924 { \ 925 return kvm_ghcb_##field##_is_valid(svm) ? ghcb->save.field : 0; \ 926 } \ 927 928 DEFINE_KVM_GHCB_ACCESSORS(cpl) 929 DEFINE_KVM_GHCB_ACCESSORS(rax) 930 DEFINE_KVM_GHCB_ACCESSORS(rcx) 931 DEFINE_KVM_GHCB_ACCESSORS(rdx) 932 DEFINE_KVM_GHCB_ACCESSORS(rbx) 933 DEFINE_KVM_GHCB_ACCESSORS(rsi) 934 DEFINE_KVM_GHCB_ACCESSORS(sw_exit_code) 935 DEFINE_KVM_GHCB_ACCESSORS(sw_exit_info_1) 936 DEFINE_KVM_GHCB_ACCESSORS(sw_exit_info_2) 937 DEFINE_KVM_GHCB_ACCESSORS(sw_scratch) 938 DEFINE_KVM_GHCB_ACCESSORS(xcr0) 939 940 #endif 941