1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Kernel-based Virtual Machine driver for Linux 4 * 5 * AMD SVM support 6 * 7 * Copyright (C) 2006 Qumranet, Inc. 8 * Copyright 2010 Red Hat, Inc. and/or its affiliates. 9 * 10 * Authors: 11 * Yaniv Kamay <yaniv@qumranet.com> 12 * Avi Kivity <avi@qumranet.com> 13 */ 14 15 #ifndef __SVM_SVM_H 16 #define __SVM_SVM_H 17 18 #include <linux/kvm_types.h> 19 #include <linux/kvm_host.h> 20 #include <linux/bits.h> 21 22 #include <asm/svm.h> 23 #include <asm/sev-common.h> 24 25 #include "cpuid.h" 26 #include "kvm_cache_regs.h" 27 28 /* 29 * Helpers to convert to/from physical addresses for pages whose address is 30 * consumed directly by hardware. Even though it's a physical address, SVM 31 * often restricts the address to the natural width, hence 'unsigned long' 32 * instead of 'hpa_t'. 33 */ 34 static inline unsigned long __sme_page_pa(struct page *page) 35 { 36 return __sme_set(page_to_pfn(page) << PAGE_SHIFT); 37 } 38 39 static inline struct page *__sme_pa_to_page(unsigned long pa) 40 { 41 return pfn_to_page(__sme_clr(pa) >> PAGE_SHIFT); 42 } 43 44 #define IOPM_SIZE PAGE_SIZE * 3 45 #define MSRPM_SIZE PAGE_SIZE * 2 46 47 extern bool npt_enabled; 48 extern int nrips; 49 extern int vgif; 50 extern bool intercept_smi; 51 extern bool vnmi; 52 extern int lbrv; 53 54 extern int tsc_aux_uret_slot __ro_after_init; 55 56 extern struct kvm_x86_ops svm_x86_ops __initdata; 57 58 /* 59 * Clean bits in VMCB. 60 * VMCB_ALL_CLEAN_MASK might also need to 61 * be updated if this enum is modified. 62 */ 63 enum { 64 VMCB_INTERCEPTS, /* Intercept vectors, TSC offset, 65 pause filter count */ 66 VMCB_PERM_MAP, /* IOPM Base and MSRPM Base */ 67 VMCB_ASID, /* ASID */ 68 VMCB_INTR, /* int_ctl, int_vector */ 69 VMCB_NPT, /* npt_en, nCR3, gPAT */ 70 VMCB_CR, /* CR0, CR3, CR4, EFER */ 71 VMCB_DR, /* DR6, DR7 */ 72 VMCB_DT, /* GDT, IDT */ 73 VMCB_SEG, /* CS, DS, SS, ES, CPL */ 74 VMCB_CR2, /* CR2 only */ 75 VMCB_LBR, /* DBGCTL, BR_FROM, BR_TO, LAST_EX_FROM, LAST_EX_TO */ 76 VMCB_AVIC, /* AVIC APIC_BAR, AVIC APIC_BACKING_PAGE, 77 * AVIC PHYSICAL_TABLE pointer, 78 * AVIC LOGICAL_TABLE pointer 79 */ 80 VMCB_CET, /* S_CET, SSP, ISST_ADDR */ 81 VMCB_SW = 31, /* Reserved for hypervisor/software use */ 82 }; 83 84 #define VMCB_ALL_CLEAN_MASK ( \ 85 (1U << VMCB_INTERCEPTS) | (1U << VMCB_PERM_MAP) | \ 86 (1U << VMCB_ASID) | (1U << VMCB_INTR) | \ 87 (1U << VMCB_NPT) | (1U << VMCB_CR) | (1U << VMCB_DR) | \ 88 (1U << VMCB_DT) | (1U << VMCB_SEG) | (1U << VMCB_CR2) | \ 89 (1U << VMCB_LBR) | (1U << VMCB_AVIC) | (1U << VMCB_CET) | \ 90 (1U << VMCB_SW)) 91 92 /* TPR and CR2 are always written before VMRUN */ 93 #define VMCB_ALWAYS_DIRTY_MASK ((1U << VMCB_INTR) | (1U << VMCB_CR2)) 94 95 struct kvm_sev_info { 96 bool active; /* SEV enabled guest */ 97 bool es_active; /* SEV-ES enabled guest */ 98 bool need_init; /* waiting for SEV_INIT2 */ 99 unsigned int asid; /* ASID used for this guest */ 100 unsigned int handle; /* SEV firmware handle */ 101 int fd; /* SEV device fd */ 102 unsigned long policy; 103 unsigned long pages_locked; /* Number of pages locked */ 104 struct list_head regions_list; /* List of registered regions */ 105 u64 ap_jump_table; /* SEV-ES AP Jump Table address */ 106 u64 vmsa_features; 107 u16 ghcb_version; /* Highest guest GHCB protocol version allowed */ 108 struct kvm *enc_context_owner; /* Owner of copied encryption context */ 109 struct list_head mirror_vms; /* List of VMs mirroring */ 110 struct list_head mirror_entry; /* Use as a list entry of mirrors */ 111 struct misc_cg *misc_cg; /* For misc cgroup accounting */ 112 atomic_t migration_in_progress; 113 void *snp_context; /* SNP guest context page */ 114 void *guest_req_buf; /* Bounce buffer for SNP Guest Request input */ 115 void *guest_resp_buf; /* Bounce buffer for SNP Guest Request output */ 116 struct mutex guest_req_mutex; /* Must acquire before using bounce buffers */ 117 cpumask_var_t have_run_cpus; /* CPUs that have done VMRUN for this VM. */ 118 }; 119 120 #define SEV_POLICY_NODBG BIT_ULL(0) 121 #define SNP_POLICY_DEBUG BIT_ULL(19) 122 123 struct kvm_svm { 124 struct kvm kvm; 125 126 /* Struct members for AVIC */ 127 u32 avic_vm_id; 128 u32 *avic_logical_id_table; 129 u64 *avic_physical_id_table; 130 struct hlist_node hnode; 131 132 struct kvm_sev_info sev_info; 133 }; 134 135 struct kvm_vcpu; 136 137 struct kvm_vmcb_info { 138 struct vmcb *ptr; 139 unsigned long pa; 140 int cpu; 141 uint64_t asid_generation; 142 }; 143 144 struct vmcb_save_area_cached { 145 u64 efer; 146 u64 cr4; 147 u64 cr3; 148 u64 cr0; 149 u64 dr7; 150 u64 dr6; 151 }; 152 153 struct vmcb_ctrl_area_cached { 154 u32 intercepts[MAX_INTERCEPT]; 155 u16 pause_filter_thresh; 156 u16 pause_filter_count; 157 u64 iopm_base_pa; 158 u64 msrpm_base_pa; 159 u64 tsc_offset; 160 u32 asid; 161 u8 tlb_ctl; 162 u32 int_ctl; 163 u32 int_vector; 164 u32 int_state; 165 u32 exit_code; 166 u32 exit_code_hi; 167 u64 exit_info_1; 168 u64 exit_info_2; 169 u32 exit_int_info; 170 u32 exit_int_info_err; 171 u64 nested_ctl; 172 u32 event_inj; 173 u32 event_inj_err; 174 u64 next_rip; 175 u64 nested_cr3; 176 u64 virt_ext; 177 u32 clean; 178 u64 bus_lock_rip; 179 union { 180 #if IS_ENABLED(CONFIG_HYPERV) || IS_ENABLED(CONFIG_KVM_HYPERV) 181 struct hv_vmcb_enlightenments hv_enlightenments; 182 #endif 183 u8 reserved_sw[32]; 184 }; 185 }; 186 187 struct svm_nested_state { 188 struct kvm_vmcb_info vmcb02; 189 u64 hsave_msr; 190 u64 vm_cr_msr; 191 u64 vmcb12_gpa; 192 u64 last_vmcb12_gpa; 193 194 /* 195 * The MSR permissions map used for vmcb02, which is the merge result 196 * of vmcb01 and vmcb12 197 */ 198 void *msrpm; 199 200 /* A VMRUN has started but has not yet been performed, so 201 * we cannot inject a nested vmexit yet. */ 202 bool nested_run_pending; 203 204 /* cache for control fields of the guest */ 205 struct vmcb_ctrl_area_cached ctl; 206 207 /* 208 * Note: this struct is not kept up-to-date while L2 runs; it is only 209 * valid within nested_svm_vmrun. 210 */ 211 struct vmcb_save_area_cached save; 212 213 bool initialized; 214 215 /* 216 * Indicates whether MSR bitmap for L2 needs to be rebuilt due to 217 * changes in MSR bitmap for L1 or switching to a different L2. Note, 218 * this flag can only be used reliably in conjunction with a paravirt L1 219 * which informs L0 whether any changes to MSR bitmap for L2 were done 220 * on its side. 221 */ 222 bool force_msr_bitmap_recalc; 223 }; 224 225 struct vcpu_sev_es_state { 226 /* SEV-ES support */ 227 struct sev_es_save_area *vmsa; 228 struct ghcb *ghcb; 229 u8 valid_bitmap[16]; 230 struct kvm_host_map ghcb_map; 231 bool received_first_sipi; 232 unsigned int ap_reset_hold_type; 233 234 /* SEV-ES scratch area support */ 235 u64 sw_scratch; 236 void *ghcb_sa; 237 u32 ghcb_sa_len; 238 bool ghcb_sa_sync; 239 bool ghcb_sa_free; 240 241 /* SNP Page-State-Change buffer entries currently being processed */ 242 u16 psc_idx; 243 u16 psc_inflight; 244 bool psc_2m; 245 246 u64 ghcb_registered_gpa; 247 248 struct mutex snp_vmsa_mutex; /* Used to handle concurrent updates of VMSA. */ 249 gpa_t snp_vmsa_gpa; 250 bool snp_ap_waiting_for_reset; 251 bool snp_has_guest_vmsa; 252 }; 253 254 struct vcpu_svm { 255 struct kvm_vcpu vcpu; 256 /* vmcb always points at current_vmcb->ptr, it's purely a shorthand. */ 257 struct vmcb *vmcb; 258 struct kvm_vmcb_info vmcb01; 259 struct kvm_vmcb_info *current_vmcb; 260 u32 asid; 261 u32 sysenter_esp_hi; 262 u32 sysenter_eip_hi; 263 uint64_t tsc_aux; 264 265 u64 msr_decfg; 266 267 u64 next_rip; 268 269 u64 spec_ctrl; 270 271 u64 tsc_ratio_msr; 272 /* 273 * Contains guest-controlled bits of VIRT_SPEC_CTRL, which will be 274 * translated into the appropriate L2_CFG bits on the host to 275 * perform speculative control. 276 */ 277 u64 virt_spec_ctrl; 278 279 void *msrpm; 280 281 ulong nmi_iret_rip; 282 283 struct svm_nested_state nested; 284 285 /* NMI mask value, used when vNMI is not enabled */ 286 bool nmi_masked; 287 288 /* 289 * True when NMIs are still masked but guest IRET was just intercepted 290 * and KVM is waiting for RIP to change, which will signal that the 291 * intercepted IRET was retired and thus NMI can be unmasked. 292 */ 293 bool awaiting_iret_completion; 294 295 /* 296 * Set when KVM is awaiting IRET completion and needs to inject NMIs as 297 * soon as the IRET completes (e.g. NMI is pending injection). KVM 298 * temporarily steals RFLAGS.TF to single-step the guest in this case 299 * in order to regain control as soon as the NMI-blocking condition 300 * goes away. 301 */ 302 bool nmi_singlestep; 303 u64 nmi_singlestep_guest_rflags; 304 305 bool nmi_l1_to_l2; 306 307 unsigned long soft_int_csbase; 308 unsigned long soft_int_old_rip; 309 unsigned long soft_int_next_rip; 310 bool soft_int_injected; 311 312 u32 ldr_reg; 313 u32 dfr_reg; 314 315 /* This is essentially a shadow of the vCPU's actual entry in the 316 * Physical ID table that is programmed into the VMCB, i.e. that is 317 * seen by the CPU. If IPI virtualization is disabled, IsRunning is 318 * only ever set in the shadow, i.e. is never propagated to the "real" 319 * table, so that hardware never sees IsRunning=1. 320 */ 321 u64 avic_physical_id_entry; 322 323 /* 324 * Per-vCPU list of irqfds that are eligible to post IRQs directly to 325 * the vCPU (a.k.a. device posted IRQs, a.k.a. IRQ bypass). The list 326 * is used to reconfigure IRTEs when the vCPU is loaded/put (to set the 327 * target pCPU), when AVIC is toggled on/off (to (de)activate bypass), 328 * and if the irqfd becomes ineligible for posting (to put the IRTE 329 * back into remapped mode). 330 */ 331 struct list_head ir_list; 332 raw_spinlock_t ir_list_lock; 333 334 struct vcpu_sev_es_state sev_es; 335 336 bool guest_state_loaded; 337 338 bool x2avic_msrs_intercepted; 339 bool lbr_msrs_intercepted; 340 341 /* Guest GIF value, used when vGIF is not enabled */ 342 bool guest_gif; 343 }; 344 345 struct svm_cpu_data { 346 u64 asid_generation; 347 u32 max_asid; 348 u32 next_asid; 349 u32 min_asid; 350 351 bool bp_spec_reduce_set; 352 353 struct vmcb *save_area; 354 unsigned long save_area_pa; 355 356 /* index = sev_asid, value = vmcb pointer */ 357 struct vmcb **sev_vmcbs; 358 }; 359 360 DECLARE_PER_CPU(struct svm_cpu_data, svm_data); 361 362 void recalc_intercepts(struct vcpu_svm *svm); 363 364 static __always_inline struct kvm_svm *to_kvm_svm(struct kvm *kvm) 365 { 366 return container_of(kvm, struct kvm_svm, kvm); 367 } 368 369 static __always_inline struct kvm_sev_info *to_kvm_sev_info(struct kvm *kvm) 370 { 371 return &to_kvm_svm(kvm)->sev_info; 372 } 373 374 #ifdef CONFIG_KVM_AMD_SEV 375 static __always_inline bool sev_guest(struct kvm *kvm) 376 { 377 return to_kvm_sev_info(kvm)->active; 378 } 379 static __always_inline bool sev_es_guest(struct kvm *kvm) 380 { 381 struct kvm_sev_info *sev = to_kvm_sev_info(kvm); 382 383 return sev->es_active && !WARN_ON_ONCE(!sev->active); 384 } 385 386 static __always_inline bool sev_snp_guest(struct kvm *kvm) 387 { 388 struct kvm_sev_info *sev = to_kvm_sev_info(kvm); 389 390 return (sev->vmsa_features & SVM_SEV_FEAT_SNP_ACTIVE) && 391 !WARN_ON_ONCE(!sev_es_guest(kvm)); 392 } 393 #else 394 #define sev_guest(kvm) false 395 #define sev_es_guest(kvm) false 396 #define sev_snp_guest(kvm) false 397 #endif 398 399 static inline bool ghcb_gpa_is_registered(struct vcpu_svm *svm, u64 val) 400 { 401 return svm->sev_es.ghcb_registered_gpa == val; 402 } 403 404 static inline void vmcb_mark_all_dirty(struct vmcb *vmcb) 405 { 406 vmcb->control.clean = 0; 407 } 408 409 static inline void vmcb_mark_all_clean(struct vmcb *vmcb) 410 { 411 vmcb->control.clean = VMCB_ALL_CLEAN_MASK 412 & ~VMCB_ALWAYS_DIRTY_MASK; 413 } 414 415 static inline void vmcb_mark_dirty(struct vmcb *vmcb, int bit) 416 { 417 vmcb->control.clean &= ~(1 << bit); 418 } 419 420 static inline bool vmcb_is_dirty(struct vmcb *vmcb, int bit) 421 { 422 return !test_bit(bit, (unsigned long *)&vmcb->control.clean); 423 } 424 425 static __always_inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu) 426 { 427 return container_of(vcpu, struct vcpu_svm, vcpu); 428 } 429 430 /* 431 * Only the PDPTRs are loaded on demand into the shadow MMU. All other 432 * fields are synchronized on VM-Exit, because accessing the VMCB is cheap. 433 * 434 * CR3 might be out of date in the VMCB but it is not marked dirty; instead, 435 * KVM_REQ_LOAD_MMU_PGD is always requested when the cached vcpu->arch.cr3 436 * is changed. svm_load_mmu_pgd() then syncs the new CR3 value into the VMCB. 437 */ 438 #define SVM_REGS_LAZY_LOAD_SET (1 << VCPU_EXREG_PDPTR) 439 440 static inline void vmcb_set_intercept(struct vmcb_control_area *control, u32 bit) 441 { 442 WARN_ON_ONCE(bit >= 32 * MAX_INTERCEPT); 443 __set_bit(bit, (unsigned long *)&control->intercepts); 444 } 445 446 static inline void vmcb_clr_intercept(struct vmcb_control_area *control, u32 bit) 447 { 448 WARN_ON_ONCE(bit >= 32 * MAX_INTERCEPT); 449 __clear_bit(bit, (unsigned long *)&control->intercepts); 450 } 451 452 static inline bool vmcb_is_intercept(struct vmcb_control_area *control, u32 bit) 453 { 454 WARN_ON_ONCE(bit >= 32 * MAX_INTERCEPT); 455 return test_bit(bit, (unsigned long *)&control->intercepts); 456 } 457 458 static inline bool vmcb12_is_intercept(struct vmcb_ctrl_area_cached *control, u32 bit) 459 { 460 WARN_ON_ONCE(bit >= 32 * MAX_INTERCEPT); 461 return test_bit(bit, (unsigned long *)&control->intercepts); 462 } 463 464 static inline void set_exception_intercept(struct vcpu_svm *svm, u32 bit) 465 { 466 struct vmcb *vmcb = svm->vmcb01.ptr; 467 468 WARN_ON_ONCE(bit >= 32); 469 vmcb_set_intercept(&vmcb->control, INTERCEPT_EXCEPTION_OFFSET + bit); 470 471 recalc_intercepts(svm); 472 } 473 474 static inline void clr_exception_intercept(struct vcpu_svm *svm, u32 bit) 475 { 476 struct vmcb *vmcb = svm->vmcb01.ptr; 477 478 WARN_ON_ONCE(bit >= 32); 479 vmcb_clr_intercept(&vmcb->control, INTERCEPT_EXCEPTION_OFFSET + bit); 480 481 recalc_intercepts(svm); 482 } 483 484 static inline void svm_set_intercept(struct vcpu_svm *svm, int bit) 485 { 486 struct vmcb *vmcb = svm->vmcb01.ptr; 487 488 vmcb_set_intercept(&vmcb->control, bit); 489 490 recalc_intercepts(svm); 491 } 492 493 static inline void svm_clr_intercept(struct vcpu_svm *svm, int bit) 494 { 495 struct vmcb *vmcb = svm->vmcb01.ptr; 496 497 vmcb_clr_intercept(&vmcb->control, bit); 498 499 recalc_intercepts(svm); 500 } 501 502 static inline bool svm_is_intercept(struct vcpu_svm *svm, int bit) 503 { 504 return vmcb_is_intercept(&svm->vmcb->control, bit); 505 } 506 507 static inline bool nested_vgif_enabled(struct vcpu_svm *svm) 508 { 509 return guest_cpu_cap_has(&svm->vcpu, X86_FEATURE_VGIF) && 510 (svm->nested.ctl.int_ctl & V_GIF_ENABLE_MASK); 511 } 512 513 static inline struct vmcb *get_vgif_vmcb(struct vcpu_svm *svm) 514 { 515 if (!vgif) 516 return NULL; 517 518 if (is_guest_mode(&svm->vcpu) && !nested_vgif_enabled(svm)) 519 return svm->nested.vmcb02.ptr; 520 else 521 return svm->vmcb01.ptr; 522 } 523 524 static inline void enable_gif(struct vcpu_svm *svm) 525 { 526 struct vmcb *vmcb = get_vgif_vmcb(svm); 527 528 if (vmcb) 529 vmcb->control.int_ctl |= V_GIF_MASK; 530 else 531 svm->guest_gif = true; 532 } 533 534 static inline void disable_gif(struct vcpu_svm *svm) 535 { 536 struct vmcb *vmcb = get_vgif_vmcb(svm); 537 538 if (vmcb) 539 vmcb->control.int_ctl &= ~V_GIF_MASK; 540 else 541 svm->guest_gif = false; 542 } 543 544 static inline bool gif_set(struct vcpu_svm *svm) 545 { 546 struct vmcb *vmcb = get_vgif_vmcb(svm); 547 548 if (vmcb) 549 return !!(vmcb->control.int_ctl & V_GIF_MASK); 550 else 551 return svm->guest_gif; 552 } 553 554 static inline bool nested_npt_enabled(struct vcpu_svm *svm) 555 { 556 return svm->nested.ctl.nested_ctl & SVM_NESTED_CTL_NP_ENABLE; 557 } 558 559 static inline bool nested_vnmi_enabled(struct vcpu_svm *svm) 560 { 561 return guest_cpu_cap_has(&svm->vcpu, X86_FEATURE_VNMI) && 562 (svm->nested.ctl.int_ctl & V_NMI_ENABLE_MASK); 563 } 564 565 static inline bool is_x2apic_msrpm_offset(u32 offset) 566 { 567 /* 4 msrs per u8, and 4 u8 in u32 */ 568 u32 msr = offset * 16; 569 570 return (msr >= APIC_BASE_MSR) && 571 (msr < (APIC_BASE_MSR + 0x100)); 572 } 573 574 static inline struct vmcb *get_vnmi_vmcb_l1(struct vcpu_svm *svm) 575 { 576 if (!vnmi) 577 return NULL; 578 579 if (is_guest_mode(&svm->vcpu)) 580 return NULL; 581 else 582 return svm->vmcb01.ptr; 583 } 584 585 static inline bool is_vnmi_enabled(struct vcpu_svm *svm) 586 { 587 struct vmcb *vmcb = get_vnmi_vmcb_l1(svm); 588 589 if (vmcb) 590 return !!(vmcb->control.int_ctl & V_NMI_ENABLE_MASK); 591 else 592 return false; 593 } 594 595 static inline void svm_vmgexit_set_return_code(struct vcpu_svm *svm, 596 u64 response, u64 data) 597 { 598 ghcb_set_sw_exit_info_1(svm->sev_es.ghcb, response); 599 ghcb_set_sw_exit_info_2(svm->sev_es.ghcb, data); 600 } 601 602 static inline void svm_vmgexit_inject_exception(struct vcpu_svm *svm, u8 vector) 603 { 604 u64 data = SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_EXEPT | vector; 605 606 svm_vmgexit_set_return_code(svm, GHCB_HV_RESP_ISSUE_EXCEPTION, data); 607 } 608 609 static inline void svm_vmgexit_bad_input(struct vcpu_svm *svm, u64 suberror) 610 { 611 svm_vmgexit_set_return_code(svm, GHCB_HV_RESP_MALFORMED_INPUT, suberror); 612 } 613 614 static inline void svm_vmgexit_success(struct vcpu_svm *svm, u64 data) 615 { 616 svm_vmgexit_set_return_code(svm, GHCB_HV_RESP_NO_ACTION, data); 617 } 618 619 static inline void svm_vmgexit_no_action(struct vcpu_svm *svm, u64 data) 620 { 621 svm_vmgexit_set_return_code(svm, GHCB_HV_RESP_NO_ACTION, data); 622 } 623 624 /* 625 * The MSRPM is 8KiB in size, divided into four 2KiB ranges (the fourth range 626 * is reserved). Each MSR within a range is covered by two bits, one each for 627 * read (bit 0) and write (bit 1), where a bit value of '1' means intercepted. 628 */ 629 #define SVM_MSRPM_BYTES_PER_RANGE 2048 630 #define SVM_BITS_PER_MSR 2 631 #define SVM_MSRS_PER_BYTE (BITS_PER_BYTE / SVM_BITS_PER_MSR) 632 #define SVM_MSRS_PER_RANGE (SVM_MSRPM_BYTES_PER_RANGE * SVM_MSRS_PER_BYTE) 633 static_assert(SVM_MSRS_PER_RANGE == 8192); 634 #define SVM_MSRPM_OFFSET_MASK (SVM_MSRS_PER_RANGE - 1) 635 636 static __always_inline int svm_msrpm_bit_nr(u32 msr) 637 { 638 int range_nr; 639 640 switch (msr & ~SVM_MSRPM_OFFSET_MASK) { 641 case 0: 642 range_nr = 0; 643 break; 644 case 0xc0000000: 645 range_nr = 1; 646 break; 647 case 0xc0010000: 648 range_nr = 2; 649 break; 650 default: 651 return -EINVAL; 652 } 653 654 return range_nr * SVM_MSRPM_BYTES_PER_RANGE * BITS_PER_BYTE + 655 (msr & SVM_MSRPM_OFFSET_MASK) * SVM_BITS_PER_MSR; 656 } 657 658 #define __BUILD_SVM_MSR_BITMAP_HELPER(rtype, action, bitop, access, bit_rw) \ 659 static inline rtype svm_##action##_msr_bitmap_##access(unsigned long *bitmap, \ 660 u32 msr) \ 661 { \ 662 int bit_nr; \ 663 \ 664 bit_nr = svm_msrpm_bit_nr(msr); \ 665 if (bit_nr < 0) \ 666 return (rtype)true; \ 667 \ 668 return bitop##_bit(bit_nr + bit_rw, bitmap); \ 669 } 670 671 #define BUILD_SVM_MSR_BITMAP_HELPERS(ret_type, action, bitop) \ 672 __BUILD_SVM_MSR_BITMAP_HELPER(ret_type, action, bitop, read, 0) \ 673 __BUILD_SVM_MSR_BITMAP_HELPER(ret_type, action, bitop, write, 1) 674 675 BUILD_SVM_MSR_BITMAP_HELPERS(bool, test, test) 676 BUILD_SVM_MSR_BITMAP_HELPERS(void, clear, __clear) 677 BUILD_SVM_MSR_BITMAP_HELPERS(void, set, __set) 678 679 #define DEBUGCTL_RESERVED_BITS (~DEBUGCTLMSR_LBR) 680 681 /* svm.c */ 682 extern bool dump_invalid_vmcb; 683 684 void *svm_alloc_permissions_map(unsigned long size, gfp_t gfp_mask); 685 686 static inline void *svm_vcpu_alloc_msrpm(void) 687 { 688 return svm_alloc_permissions_map(MSRPM_SIZE, GFP_KERNEL_ACCOUNT); 689 } 690 691 void svm_vcpu_free_msrpm(void *msrpm); 692 void svm_copy_lbrs(struct vmcb *to_vmcb, struct vmcb *from_vmcb); 693 void svm_enable_lbrv(struct kvm_vcpu *vcpu); 694 void svm_update_lbrv(struct kvm_vcpu *vcpu); 695 696 int svm_set_efer(struct kvm_vcpu *vcpu, u64 efer); 697 void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0); 698 void svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4); 699 void disable_nmi_singlestep(struct vcpu_svm *svm); 700 bool svm_smi_blocked(struct kvm_vcpu *vcpu); 701 bool svm_nmi_blocked(struct kvm_vcpu *vcpu); 702 bool svm_interrupt_blocked(struct kvm_vcpu *vcpu); 703 void svm_set_gif(struct vcpu_svm *svm, bool value); 704 int svm_invoke_exit_handler(struct kvm_vcpu *vcpu, u64 exit_code); 705 void set_msr_interception(struct kvm_vcpu *vcpu, u32 *msrpm, u32 msr, 706 int read, int write); 707 void svm_complete_interrupt_delivery(struct kvm_vcpu *vcpu, int delivery_mode, 708 int trig_mode, int vec); 709 710 void svm_set_intercept_for_msr(struct kvm_vcpu *vcpu, u32 msr, int type, bool set); 711 712 static inline void svm_disable_intercept_for_msr(struct kvm_vcpu *vcpu, 713 u32 msr, int type) 714 { 715 svm_set_intercept_for_msr(vcpu, msr, type, false); 716 } 717 718 static inline void svm_enable_intercept_for_msr(struct kvm_vcpu *vcpu, 719 u32 msr, int type) 720 { 721 svm_set_intercept_for_msr(vcpu, msr, type, true); 722 } 723 724 /* nested.c */ 725 726 #define NESTED_EXIT_HOST 0 /* Exit handled on host level */ 727 #define NESTED_EXIT_DONE 1 /* Exit caused nested vmexit */ 728 #define NESTED_EXIT_CONTINUE 2 /* Further checks needed */ 729 730 static inline bool nested_svm_virtualize_tpr(struct kvm_vcpu *vcpu) 731 { 732 struct vcpu_svm *svm = to_svm(vcpu); 733 734 return is_guest_mode(vcpu) && (svm->nested.ctl.int_ctl & V_INTR_MASKING_MASK); 735 } 736 737 static inline bool nested_exit_on_smi(struct vcpu_svm *svm) 738 { 739 return vmcb12_is_intercept(&svm->nested.ctl, INTERCEPT_SMI); 740 } 741 742 static inline bool nested_exit_on_intr(struct vcpu_svm *svm) 743 { 744 return vmcb12_is_intercept(&svm->nested.ctl, INTERCEPT_INTR); 745 } 746 747 static inline bool nested_exit_on_nmi(struct vcpu_svm *svm) 748 { 749 return vmcb12_is_intercept(&svm->nested.ctl, INTERCEPT_NMI); 750 } 751 752 int __init nested_svm_init_msrpm_merge_offsets(void); 753 754 int enter_svm_guest_mode(struct kvm_vcpu *vcpu, 755 u64 vmcb_gpa, struct vmcb *vmcb12, bool from_vmrun); 756 void svm_leave_nested(struct kvm_vcpu *vcpu); 757 void svm_free_nested(struct vcpu_svm *svm); 758 int svm_allocate_nested(struct vcpu_svm *svm); 759 int nested_svm_vmrun(struct kvm_vcpu *vcpu); 760 void svm_copy_vmrun_state(struct vmcb_save_area *to_save, 761 struct vmcb_save_area *from_save); 762 void svm_copy_vmloadsave_state(struct vmcb *to_vmcb, struct vmcb *from_vmcb); 763 int nested_svm_vmexit(struct vcpu_svm *svm); 764 765 static inline int nested_svm_simple_vmexit(struct vcpu_svm *svm, u32 exit_code) 766 { 767 svm->vmcb->control.exit_code = exit_code; 768 svm->vmcb->control.exit_info_1 = 0; 769 svm->vmcb->control.exit_info_2 = 0; 770 return nested_svm_vmexit(svm); 771 } 772 773 int nested_svm_exit_handled(struct vcpu_svm *svm); 774 int nested_svm_check_permissions(struct kvm_vcpu *vcpu); 775 int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr, 776 bool has_error_code, u32 error_code); 777 int nested_svm_exit_special(struct vcpu_svm *svm); 778 void nested_svm_update_tsc_ratio_msr(struct kvm_vcpu *vcpu); 779 void svm_write_tsc_multiplier(struct kvm_vcpu *vcpu); 780 void nested_copy_vmcb_control_to_cache(struct vcpu_svm *svm, 781 struct vmcb_control_area *control); 782 void nested_copy_vmcb_save_to_cache(struct vcpu_svm *svm, 783 struct vmcb_save_area *save); 784 void nested_sync_control_from_vmcb02(struct vcpu_svm *svm); 785 void nested_vmcb02_compute_g_pat(struct vcpu_svm *svm); 786 void svm_switch_vmcb(struct vcpu_svm *svm, struct kvm_vmcb_info *target_vmcb); 787 788 extern struct kvm_x86_nested_ops svm_nested_ops; 789 790 /* avic.c */ 791 #define AVIC_REQUIRED_APICV_INHIBITS \ 792 ( \ 793 BIT(APICV_INHIBIT_REASON_DISABLED) | \ 794 BIT(APICV_INHIBIT_REASON_ABSENT) | \ 795 BIT(APICV_INHIBIT_REASON_HYPERV) | \ 796 BIT(APICV_INHIBIT_REASON_NESTED) | \ 797 BIT(APICV_INHIBIT_REASON_IRQWIN) | \ 798 BIT(APICV_INHIBIT_REASON_PIT_REINJ) | \ 799 BIT(APICV_INHIBIT_REASON_BLOCKIRQ) | \ 800 BIT(APICV_INHIBIT_REASON_SEV) | \ 801 BIT(APICV_INHIBIT_REASON_PHYSICAL_ID_ALIASED) | \ 802 BIT(APICV_INHIBIT_REASON_APIC_ID_MODIFIED) | \ 803 BIT(APICV_INHIBIT_REASON_APIC_BASE_MODIFIED) | \ 804 BIT(APICV_INHIBIT_REASON_LOGICAL_ID_ALIASED) | \ 805 BIT(APICV_INHIBIT_REASON_PHYSICAL_ID_TOO_BIG) \ 806 ) 807 808 bool __init avic_hardware_setup(void); 809 void avic_hardware_unsetup(void); 810 void avic_vm_destroy(struct kvm *kvm); 811 int avic_vm_init(struct kvm *kvm); 812 void avic_init_vmcb(struct vcpu_svm *svm, struct vmcb *vmcb); 813 int avic_incomplete_ipi_interception(struct kvm_vcpu *vcpu); 814 int avic_unaccelerated_access_interception(struct kvm_vcpu *vcpu); 815 int avic_init_vcpu(struct vcpu_svm *svm); 816 void avic_vcpu_load(struct kvm_vcpu *vcpu, int cpu); 817 void avic_vcpu_put(struct kvm_vcpu *vcpu); 818 void avic_apicv_post_state_restore(struct kvm_vcpu *vcpu); 819 void avic_refresh_apicv_exec_ctrl(struct kvm_vcpu *vcpu); 820 int avic_pi_update_irte(struct kvm_kernel_irqfd *irqfd, struct kvm *kvm, 821 unsigned int host_irq, uint32_t guest_irq, 822 struct kvm_vcpu *vcpu, u32 vector); 823 void avic_vcpu_blocking(struct kvm_vcpu *vcpu); 824 void avic_vcpu_unblocking(struct kvm_vcpu *vcpu); 825 void avic_ring_doorbell(struct kvm_vcpu *vcpu); 826 unsigned long avic_vcpu_get_apicv_inhibit_reasons(struct kvm_vcpu *vcpu); 827 void avic_refresh_virtual_apic_mode(struct kvm_vcpu *vcpu); 828 829 830 /* sev.c */ 831 832 int pre_sev_run(struct vcpu_svm *svm, int cpu); 833 void sev_init_vmcb(struct vcpu_svm *svm, bool init_event); 834 void sev_vcpu_after_set_cpuid(struct vcpu_svm *svm); 835 int sev_es_string_io(struct vcpu_svm *svm, int size, unsigned int port, int in); 836 void sev_es_recalc_msr_intercepts(struct kvm_vcpu *vcpu); 837 void sev_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector); 838 void sev_es_prepare_switch_to_guest(struct vcpu_svm *svm, struct sev_es_save_area *hostsa); 839 void sev_es_unmap_ghcb(struct vcpu_svm *svm); 840 841 #ifdef CONFIG_KVM_AMD_SEV 842 int sev_mem_enc_ioctl(struct kvm *kvm, void __user *argp); 843 int sev_mem_enc_register_region(struct kvm *kvm, 844 struct kvm_enc_region *range); 845 int sev_mem_enc_unregister_region(struct kvm *kvm, 846 struct kvm_enc_region *range); 847 int sev_vm_copy_enc_context_from(struct kvm *kvm, unsigned int source_fd); 848 int sev_vm_move_enc_context_from(struct kvm *kvm, unsigned int source_fd); 849 void sev_guest_memory_reclaimed(struct kvm *kvm); 850 int sev_handle_vmgexit(struct kvm_vcpu *vcpu); 851 852 /* These symbols are used in common code and are stubbed below. */ 853 854 struct page *snp_safe_alloc_page_node(int node, gfp_t gfp); 855 static inline struct page *snp_safe_alloc_page(void) 856 { 857 return snp_safe_alloc_page_node(numa_node_id(), GFP_KERNEL_ACCOUNT); 858 } 859 860 int sev_vcpu_create(struct kvm_vcpu *vcpu); 861 void sev_free_vcpu(struct kvm_vcpu *vcpu); 862 void sev_vm_destroy(struct kvm *kvm); 863 void __init sev_set_cpu_caps(void); 864 void __init sev_hardware_setup(void); 865 void sev_hardware_unsetup(void); 866 int sev_cpu_init(struct svm_cpu_data *sd); 867 int sev_dev_get_attr(u32 group, u64 attr, u64 *val); 868 extern unsigned int max_sev_asid; 869 void sev_handle_rmp_fault(struct kvm_vcpu *vcpu, gpa_t gpa, u64 error_code); 870 int sev_gmem_prepare(struct kvm *kvm, kvm_pfn_t pfn, gfn_t gfn, int max_order); 871 void sev_gmem_invalidate(kvm_pfn_t start, kvm_pfn_t end); 872 int sev_gmem_max_mapping_level(struct kvm *kvm, kvm_pfn_t pfn, bool is_private); 873 struct vmcb_save_area *sev_decrypt_vmsa(struct kvm_vcpu *vcpu); 874 void sev_free_decrypted_vmsa(struct kvm_vcpu *vcpu, struct vmcb_save_area *vmsa); 875 #else 876 static inline struct page *snp_safe_alloc_page_node(int node, gfp_t gfp) 877 { 878 return alloc_pages_node(node, gfp | __GFP_ZERO, 0); 879 } 880 881 static inline struct page *snp_safe_alloc_page(void) 882 { 883 return snp_safe_alloc_page_node(numa_node_id(), GFP_KERNEL_ACCOUNT); 884 } 885 886 static inline int sev_vcpu_create(struct kvm_vcpu *vcpu) { return 0; } 887 static inline void sev_free_vcpu(struct kvm_vcpu *vcpu) {} 888 static inline void sev_vm_destroy(struct kvm *kvm) {} 889 static inline void __init sev_set_cpu_caps(void) {} 890 static inline void __init sev_hardware_setup(void) {} 891 static inline void sev_hardware_unsetup(void) {} 892 static inline int sev_cpu_init(struct svm_cpu_data *sd) { return 0; } 893 static inline int sev_dev_get_attr(u32 group, u64 attr, u64 *val) { return -ENXIO; } 894 #define max_sev_asid 0 895 static inline void sev_handle_rmp_fault(struct kvm_vcpu *vcpu, gpa_t gpa, u64 error_code) {} 896 static inline int sev_gmem_prepare(struct kvm *kvm, kvm_pfn_t pfn, gfn_t gfn, int max_order) 897 { 898 return 0; 899 } 900 static inline void sev_gmem_invalidate(kvm_pfn_t start, kvm_pfn_t end) {} 901 static inline int sev_gmem_max_mapping_level(struct kvm *kvm, kvm_pfn_t pfn, bool is_private) 902 { 903 return 0; 904 } 905 906 static inline struct vmcb_save_area *sev_decrypt_vmsa(struct kvm_vcpu *vcpu) 907 { 908 return NULL; 909 } 910 static inline void sev_free_decrypted_vmsa(struct kvm_vcpu *vcpu, struct vmcb_save_area *vmsa) {} 911 #endif 912 913 /* vmenter.S */ 914 915 void __svm_sev_es_vcpu_run(struct vcpu_svm *svm, bool spec_ctrl_intercepted, 916 struct sev_es_save_area *hostsa); 917 void __svm_vcpu_run(struct vcpu_svm *svm, bool spec_ctrl_intercepted); 918 919 #define DEFINE_KVM_GHCB_ACCESSORS(field) \ 920 static __always_inline u64 kvm_ghcb_get_##field(struct vcpu_svm *svm) \ 921 { \ 922 return READ_ONCE(svm->sev_es.ghcb->save.field); \ 923 } \ 924 \ 925 static __always_inline bool kvm_ghcb_##field##_is_valid(const struct vcpu_svm *svm) \ 926 { \ 927 return test_bit(GHCB_BITMAP_IDX(field), \ 928 (unsigned long *)&svm->sev_es.valid_bitmap); \ 929 } \ 930 \ 931 static __always_inline u64 kvm_ghcb_get_##field##_if_valid(struct vcpu_svm *svm) \ 932 { \ 933 return kvm_ghcb_##field##_is_valid(svm) ? kvm_ghcb_get_##field(svm) : 0; \ 934 } 935 936 DEFINE_KVM_GHCB_ACCESSORS(cpl) 937 DEFINE_KVM_GHCB_ACCESSORS(rax) 938 DEFINE_KVM_GHCB_ACCESSORS(rcx) 939 DEFINE_KVM_GHCB_ACCESSORS(rdx) 940 DEFINE_KVM_GHCB_ACCESSORS(rbx) 941 DEFINE_KVM_GHCB_ACCESSORS(rsi) 942 DEFINE_KVM_GHCB_ACCESSORS(sw_exit_code) 943 DEFINE_KVM_GHCB_ACCESSORS(sw_exit_info_1) 944 DEFINE_KVM_GHCB_ACCESSORS(sw_exit_info_2) 945 DEFINE_KVM_GHCB_ACCESSORS(sw_scratch) 946 DEFINE_KVM_GHCB_ACCESSORS(xcr0) 947 DEFINE_KVM_GHCB_ACCESSORS(xss) 948 949 #endif 950