1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Kernel-based Virtual Machine driver for Linux 4 * 5 * AMD SVM support 6 * 7 * Copyright (C) 2006 Qumranet, Inc. 8 * Copyright 2010 Red Hat, Inc. and/or its affiliates. 9 * 10 * Authors: 11 * Yaniv Kamay <yaniv@qumranet.com> 12 * Avi Kivity <avi@qumranet.com> 13 */ 14 15 #ifndef __SVM_SVM_H 16 #define __SVM_SVM_H 17 18 #include <linux/kvm_types.h> 19 #include <linux/kvm_host.h> 20 #include <linux/bits.h> 21 22 #include <asm/svm.h> 23 #include <asm/sev-common.h> 24 25 #include "cpuid.h" 26 #include "kvm_cache_regs.h" 27 28 #define __sme_page_pa(x) __sme_set(page_to_pfn(x) << PAGE_SHIFT) 29 30 #define IOPM_SIZE PAGE_SIZE * 3 31 #define MSRPM_SIZE PAGE_SIZE * 2 32 33 #define MAX_DIRECT_ACCESS_MSRS 47 34 #define MSRPM_OFFSETS 32 35 extern u32 msrpm_offsets[MSRPM_OFFSETS] __read_mostly; 36 extern bool npt_enabled; 37 extern int nrips; 38 extern int vgif; 39 extern bool intercept_smi; 40 extern bool x2avic_enabled; 41 extern bool vnmi; 42 43 /* 44 * Clean bits in VMCB. 45 * VMCB_ALL_CLEAN_MASK might also need to 46 * be updated if this enum is modified. 47 */ 48 enum { 49 VMCB_INTERCEPTS, /* Intercept vectors, TSC offset, 50 pause filter count */ 51 VMCB_PERM_MAP, /* IOPM Base and MSRPM Base */ 52 VMCB_ASID, /* ASID */ 53 VMCB_INTR, /* int_ctl, int_vector */ 54 VMCB_NPT, /* npt_en, nCR3, gPAT */ 55 VMCB_CR, /* CR0, CR3, CR4, EFER */ 56 VMCB_DR, /* DR6, DR7 */ 57 VMCB_DT, /* GDT, IDT */ 58 VMCB_SEG, /* CS, DS, SS, ES, CPL */ 59 VMCB_CR2, /* CR2 only */ 60 VMCB_LBR, /* DBGCTL, BR_FROM, BR_TO, LAST_EX_FROM, LAST_EX_TO */ 61 VMCB_AVIC, /* AVIC APIC_BAR, AVIC APIC_BACKING_PAGE, 62 * AVIC PHYSICAL_TABLE pointer, 63 * AVIC LOGICAL_TABLE pointer 64 */ 65 VMCB_SW = 31, /* Reserved for hypervisor/software use */ 66 }; 67 68 #define VMCB_ALL_CLEAN_MASK ( \ 69 (1U << VMCB_INTERCEPTS) | (1U << VMCB_PERM_MAP) | \ 70 (1U << VMCB_ASID) | (1U << VMCB_INTR) | \ 71 (1U << VMCB_NPT) | (1U << VMCB_CR) | (1U << VMCB_DR) | \ 72 (1U << VMCB_DT) | (1U << VMCB_SEG) | (1U << VMCB_CR2) | \ 73 (1U << VMCB_LBR) | (1U << VMCB_AVIC) | \ 74 (1U << VMCB_SW)) 75 76 /* TPR and CR2 are always written before VMRUN */ 77 #define VMCB_ALWAYS_DIRTY_MASK ((1U << VMCB_INTR) | (1U << VMCB_CR2)) 78 79 struct kvm_sev_info { 80 bool active; /* SEV enabled guest */ 81 bool es_active; /* SEV-ES enabled guest */ 82 bool need_init; /* waiting for SEV_INIT2 */ 83 unsigned int asid; /* ASID used for this guest */ 84 unsigned int handle; /* SEV firmware handle */ 85 int fd; /* SEV device fd */ 86 unsigned long pages_locked; /* Number of pages locked */ 87 struct list_head regions_list; /* List of registered regions */ 88 u64 ap_jump_table; /* SEV-ES AP Jump Table address */ 89 u64 vmsa_features; 90 u16 ghcb_version; /* Highest guest GHCB protocol version allowed */ 91 struct kvm *enc_context_owner; /* Owner of copied encryption context */ 92 struct list_head mirror_vms; /* List of VMs mirroring */ 93 struct list_head mirror_entry; /* Use as a list entry of mirrors */ 94 struct misc_cg *misc_cg; /* For misc cgroup accounting */ 95 atomic_t migration_in_progress; 96 }; 97 98 struct kvm_svm { 99 struct kvm kvm; 100 101 /* Struct members for AVIC */ 102 u32 avic_vm_id; 103 struct page *avic_logical_id_table_page; 104 struct page *avic_physical_id_table_page; 105 struct hlist_node hnode; 106 107 struct kvm_sev_info sev_info; 108 }; 109 110 struct kvm_vcpu; 111 112 struct kvm_vmcb_info { 113 struct vmcb *ptr; 114 unsigned long pa; 115 int cpu; 116 uint64_t asid_generation; 117 }; 118 119 struct vmcb_save_area_cached { 120 u64 efer; 121 u64 cr4; 122 u64 cr3; 123 u64 cr0; 124 u64 dr7; 125 u64 dr6; 126 }; 127 128 struct vmcb_ctrl_area_cached { 129 u32 intercepts[MAX_INTERCEPT]; 130 u16 pause_filter_thresh; 131 u16 pause_filter_count; 132 u64 iopm_base_pa; 133 u64 msrpm_base_pa; 134 u64 tsc_offset; 135 u32 asid; 136 u8 tlb_ctl; 137 u32 int_ctl; 138 u32 int_vector; 139 u32 int_state; 140 u32 exit_code; 141 u32 exit_code_hi; 142 u64 exit_info_1; 143 u64 exit_info_2; 144 u32 exit_int_info; 145 u32 exit_int_info_err; 146 u64 nested_ctl; 147 u32 event_inj; 148 u32 event_inj_err; 149 u64 next_rip; 150 u64 nested_cr3; 151 u64 virt_ext; 152 u32 clean; 153 union { 154 #if IS_ENABLED(CONFIG_HYPERV) || IS_ENABLED(CONFIG_KVM_HYPERV) 155 struct hv_vmcb_enlightenments hv_enlightenments; 156 #endif 157 u8 reserved_sw[32]; 158 }; 159 }; 160 161 struct svm_nested_state { 162 struct kvm_vmcb_info vmcb02; 163 u64 hsave_msr; 164 u64 vm_cr_msr; 165 u64 vmcb12_gpa; 166 u64 last_vmcb12_gpa; 167 168 /* These are the merged vectors */ 169 u32 *msrpm; 170 171 /* A VMRUN has started but has not yet been performed, so 172 * we cannot inject a nested vmexit yet. */ 173 bool nested_run_pending; 174 175 /* cache for control fields of the guest */ 176 struct vmcb_ctrl_area_cached ctl; 177 178 /* 179 * Note: this struct is not kept up-to-date while L2 runs; it is only 180 * valid within nested_svm_vmrun. 181 */ 182 struct vmcb_save_area_cached save; 183 184 bool initialized; 185 186 /* 187 * Indicates whether MSR bitmap for L2 needs to be rebuilt due to 188 * changes in MSR bitmap for L1 or switching to a different L2. Note, 189 * this flag can only be used reliably in conjunction with a paravirt L1 190 * which informs L0 whether any changes to MSR bitmap for L2 were done 191 * on its side. 192 */ 193 bool force_msr_bitmap_recalc; 194 }; 195 196 struct vcpu_sev_es_state { 197 /* SEV-ES support */ 198 struct sev_es_save_area *vmsa; 199 struct ghcb *ghcb; 200 u8 valid_bitmap[16]; 201 struct kvm_host_map ghcb_map; 202 bool received_first_sipi; 203 unsigned int ap_reset_hold_type; 204 205 /* SEV-ES scratch area support */ 206 u64 sw_scratch; 207 void *ghcb_sa; 208 u32 ghcb_sa_len; 209 bool ghcb_sa_sync; 210 bool ghcb_sa_free; 211 }; 212 213 struct vcpu_svm { 214 struct kvm_vcpu vcpu; 215 /* vmcb always points at current_vmcb->ptr, it's purely a shorthand. */ 216 struct vmcb *vmcb; 217 struct kvm_vmcb_info vmcb01; 218 struct kvm_vmcb_info *current_vmcb; 219 u32 asid; 220 u32 sysenter_esp_hi; 221 u32 sysenter_eip_hi; 222 uint64_t tsc_aux; 223 224 u64 msr_decfg; 225 226 u64 next_rip; 227 228 u64 spec_ctrl; 229 230 u64 tsc_ratio_msr; 231 /* 232 * Contains guest-controlled bits of VIRT_SPEC_CTRL, which will be 233 * translated into the appropriate L2_CFG bits on the host to 234 * perform speculative control. 235 */ 236 u64 virt_spec_ctrl; 237 238 u32 *msrpm; 239 240 ulong nmi_iret_rip; 241 242 struct svm_nested_state nested; 243 244 /* NMI mask value, used when vNMI is not enabled */ 245 bool nmi_masked; 246 247 /* 248 * True when NMIs are still masked but guest IRET was just intercepted 249 * and KVM is waiting for RIP to change, which will signal that the 250 * intercepted IRET was retired and thus NMI can be unmasked. 251 */ 252 bool awaiting_iret_completion; 253 254 /* 255 * Set when KVM is awaiting IRET completion and needs to inject NMIs as 256 * soon as the IRET completes (e.g. NMI is pending injection). KVM 257 * temporarily steals RFLAGS.TF to single-step the guest in this case 258 * in order to regain control as soon as the NMI-blocking condition 259 * goes away. 260 */ 261 bool nmi_singlestep; 262 u64 nmi_singlestep_guest_rflags; 263 264 bool nmi_l1_to_l2; 265 266 unsigned long soft_int_csbase; 267 unsigned long soft_int_old_rip; 268 unsigned long soft_int_next_rip; 269 bool soft_int_injected; 270 271 u32 ldr_reg; 272 u32 dfr_reg; 273 struct page *avic_backing_page; 274 u64 *avic_physical_id_cache; 275 276 /* 277 * Per-vcpu list of struct amd_svm_iommu_ir: 278 * This is used mainly to store interrupt remapping information used 279 * when update the vcpu affinity. This avoids the need to scan for 280 * IRTE and try to match ga_tag in the IOMMU driver. 281 */ 282 struct list_head ir_list; 283 spinlock_t ir_list_lock; 284 285 /* Save desired MSR intercept (read: pass-through) state */ 286 struct { 287 DECLARE_BITMAP(read, MAX_DIRECT_ACCESS_MSRS); 288 DECLARE_BITMAP(write, MAX_DIRECT_ACCESS_MSRS); 289 } shadow_msr_intercept; 290 291 struct vcpu_sev_es_state sev_es; 292 293 bool guest_state_loaded; 294 295 bool x2avic_msrs_intercepted; 296 297 /* Guest GIF value, used when vGIF is not enabled */ 298 bool guest_gif; 299 }; 300 301 struct svm_cpu_data { 302 u64 asid_generation; 303 u32 max_asid; 304 u32 next_asid; 305 u32 min_asid; 306 307 struct page *save_area; 308 unsigned long save_area_pa; 309 310 struct vmcb *current_vmcb; 311 312 /* index = sev_asid, value = vmcb pointer */ 313 struct vmcb **sev_vmcbs; 314 }; 315 316 DECLARE_PER_CPU(struct svm_cpu_data, svm_data); 317 318 void recalc_intercepts(struct vcpu_svm *svm); 319 320 static __always_inline struct kvm_svm *to_kvm_svm(struct kvm *kvm) 321 { 322 return container_of(kvm, struct kvm_svm, kvm); 323 } 324 325 static __always_inline struct kvm_sev_info *to_kvm_sev_info(struct kvm *kvm) 326 { 327 return &to_kvm_svm(kvm)->sev_info; 328 } 329 330 static __always_inline bool sev_guest(struct kvm *kvm) 331 { 332 #ifdef CONFIG_KVM_AMD_SEV 333 struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info; 334 335 return sev->active; 336 #else 337 return false; 338 #endif 339 } 340 341 static __always_inline bool sev_es_guest(struct kvm *kvm) 342 { 343 #ifdef CONFIG_KVM_AMD_SEV 344 struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info; 345 346 return sev->es_active && !WARN_ON_ONCE(!sev->active); 347 #else 348 return false; 349 #endif 350 } 351 352 static inline void vmcb_mark_all_dirty(struct vmcb *vmcb) 353 { 354 vmcb->control.clean = 0; 355 } 356 357 static inline void vmcb_mark_all_clean(struct vmcb *vmcb) 358 { 359 vmcb->control.clean = VMCB_ALL_CLEAN_MASK 360 & ~VMCB_ALWAYS_DIRTY_MASK; 361 } 362 363 static inline void vmcb_mark_dirty(struct vmcb *vmcb, int bit) 364 { 365 vmcb->control.clean &= ~(1 << bit); 366 } 367 368 static inline bool vmcb_is_dirty(struct vmcb *vmcb, int bit) 369 { 370 return !test_bit(bit, (unsigned long *)&vmcb->control.clean); 371 } 372 373 static __always_inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu) 374 { 375 return container_of(vcpu, struct vcpu_svm, vcpu); 376 } 377 378 /* 379 * Only the PDPTRs are loaded on demand into the shadow MMU. All other 380 * fields are synchronized on VM-Exit, because accessing the VMCB is cheap. 381 * 382 * CR3 might be out of date in the VMCB but it is not marked dirty; instead, 383 * KVM_REQ_LOAD_MMU_PGD is always requested when the cached vcpu->arch.cr3 384 * is changed. svm_load_mmu_pgd() then syncs the new CR3 value into the VMCB. 385 */ 386 #define SVM_REGS_LAZY_LOAD_SET (1 << VCPU_EXREG_PDPTR) 387 388 static inline void vmcb_set_intercept(struct vmcb_control_area *control, u32 bit) 389 { 390 WARN_ON_ONCE(bit >= 32 * MAX_INTERCEPT); 391 __set_bit(bit, (unsigned long *)&control->intercepts); 392 } 393 394 static inline void vmcb_clr_intercept(struct vmcb_control_area *control, u32 bit) 395 { 396 WARN_ON_ONCE(bit >= 32 * MAX_INTERCEPT); 397 __clear_bit(bit, (unsigned long *)&control->intercepts); 398 } 399 400 static inline bool vmcb_is_intercept(struct vmcb_control_area *control, u32 bit) 401 { 402 WARN_ON_ONCE(bit >= 32 * MAX_INTERCEPT); 403 return test_bit(bit, (unsigned long *)&control->intercepts); 404 } 405 406 static inline bool vmcb12_is_intercept(struct vmcb_ctrl_area_cached *control, u32 bit) 407 { 408 WARN_ON_ONCE(bit >= 32 * MAX_INTERCEPT); 409 return test_bit(bit, (unsigned long *)&control->intercepts); 410 } 411 412 static inline void set_exception_intercept(struct vcpu_svm *svm, u32 bit) 413 { 414 struct vmcb *vmcb = svm->vmcb01.ptr; 415 416 WARN_ON_ONCE(bit >= 32); 417 vmcb_set_intercept(&vmcb->control, INTERCEPT_EXCEPTION_OFFSET + bit); 418 419 recalc_intercepts(svm); 420 } 421 422 static inline void clr_exception_intercept(struct vcpu_svm *svm, u32 bit) 423 { 424 struct vmcb *vmcb = svm->vmcb01.ptr; 425 426 WARN_ON_ONCE(bit >= 32); 427 vmcb_clr_intercept(&vmcb->control, INTERCEPT_EXCEPTION_OFFSET + bit); 428 429 recalc_intercepts(svm); 430 } 431 432 static inline void svm_set_intercept(struct vcpu_svm *svm, int bit) 433 { 434 struct vmcb *vmcb = svm->vmcb01.ptr; 435 436 vmcb_set_intercept(&vmcb->control, bit); 437 438 recalc_intercepts(svm); 439 } 440 441 static inline void svm_clr_intercept(struct vcpu_svm *svm, int bit) 442 { 443 struct vmcb *vmcb = svm->vmcb01.ptr; 444 445 vmcb_clr_intercept(&vmcb->control, bit); 446 447 recalc_intercepts(svm); 448 } 449 450 static inline bool svm_is_intercept(struct vcpu_svm *svm, int bit) 451 { 452 return vmcb_is_intercept(&svm->vmcb->control, bit); 453 } 454 455 static inline bool nested_vgif_enabled(struct vcpu_svm *svm) 456 { 457 return guest_can_use(&svm->vcpu, X86_FEATURE_VGIF) && 458 (svm->nested.ctl.int_ctl & V_GIF_ENABLE_MASK); 459 } 460 461 static inline struct vmcb *get_vgif_vmcb(struct vcpu_svm *svm) 462 { 463 if (!vgif) 464 return NULL; 465 466 if (is_guest_mode(&svm->vcpu) && !nested_vgif_enabled(svm)) 467 return svm->nested.vmcb02.ptr; 468 else 469 return svm->vmcb01.ptr; 470 } 471 472 static inline void enable_gif(struct vcpu_svm *svm) 473 { 474 struct vmcb *vmcb = get_vgif_vmcb(svm); 475 476 if (vmcb) 477 vmcb->control.int_ctl |= V_GIF_MASK; 478 else 479 svm->guest_gif = true; 480 } 481 482 static inline void disable_gif(struct vcpu_svm *svm) 483 { 484 struct vmcb *vmcb = get_vgif_vmcb(svm); 485 486 if (vmcb) 487 vmcb->control.int_ctl &= ~V_GIF_MASK; 488 else 489 svm->guest_gif = false; 490 } 491 492 static inline bool gif_set(struct vcpu_svm *svm) 493 { 494 struct vmcb *vmcb = get_vgif_vmcb(svm); 495 496 if (vmcb) 497 return !!(vmcb->control.int_ctl & V_GIF_MASK); 498 else 499 return svm->guest_gif; 500 } 501 502 static inline bool nested_npt_enabled(struct vcpu_svm *svm) 503 { 504 return svm->nested.ctl.nested_ctl & SVM_NESTED_CTL_NP_ENABLE; 505 } 506 507 static inline bool nested_vnmi_enabled(struct vcpu_svm *svm) 508 { 509 return guest_can_use(&svm->vcpu, X86_FEATURE_VNMI) && 510 (svm->nested.ctl.int_ctl & V_NMI_ENABLE_MASK); 511 } 512 513 static inline bool is_x2apic_msrpm_offset(u32 offset) 514 { 515 /* 4 msrs per u8, and 4 u8 in u32 */ 516 u32 msr = offset * 16; 517 518 return (msr >= APIC_BASE_MSR) && 519 (msr < (APIC_BASE_MSR + 0x100)); 520 } 521 522 static inline struct vmcb *get_vnmi_vmcb_l1(struct vcpu_svm *svm) 523 { 524 if (!vnmi) 525 return NULL; 526 527 if (is_guest_mode(&svm->vcpu)) 528 return NULL; 529 else 530 return svm->vmcb01.ptr; 531 } 532 533 static inline bool is_vnmi_enabled(struct vcpu_svm *svm) 534 { 535 struct vmcb *vmcb = get_vnmi_vmcb_l1(svm); 536 537 if (vmcb) 538 return !!(vmcb->control.int_ctl & V_NMI_ENABLE_MASK); 539 else 540 return false; 541 } 542 543 /* svm.c */ 544 #define MSR_INVALID 0xffffffffU 545 546 #define DEBUGCTL_RESERVED_BITS (~(0x3fULL)) 547 548 extern bool dump_invalid_vmcb; 549 550 u32 svm_msrpm_offset(u32 msr); 551 u32 *svm_vcpu_alloc_msrpm(void); 552 void svm_vcpu_init_msrpm(struct kvm_vcpu *vcpu, u32 *msrpm); 553 void svm_vcpu_free_msrpm(u32 *msrpm); 554 void svm_copy_lbrs(struct vmcb *to_vmcb, struct vmcb *from_vmcb); 555 void svm_update_lbrv(struct kvm_vcpu *vcpu); 556 557 int svm_set_efer(struct kvm_vcpu *vcpu, u64 efer); 558 void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0); 559 void svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4); 560 void disable_nmi_singlestep(struct vcpu_svm *svm); 561 bool svm_smi_blocked(struct kvm_vcpu *vcpu); 562 bool svm_nmi_blocked(struct kvm_vcpu *vcpu); 563 bool svm_interrupt_blocked(struct kvm_vcpu *vcpu); 564 void svm_set_gif(struct vcpu_svm *svm, bool value); 565 int svm_invoke_exit_handler(struct kvm_vcpu *vcpu, u64 exit_code); 566 void set_msr_interception(struct kvm_vcpu *vcpu, u32 *msrpm, u32 msr, 567 int read, int write); 568 void svm_set_x2apic_msr_interception(struct vcpu_svm *svm, bool disable); 569 void svm_complete_interrupt_delivery(struct kvm_vcpu *vcpu, int delivery_mode, 570 int trig_mode, int vec); 571 572 /* nested.c */ 573 574 #define NESTED_EXIT_HOST 0 /* Exit handled on host level */ 575 #define NESTED_EXIT_DONE 1 /* Exit caused nested vmexit */ 576 #define NESTED_EXIT_CONTINUE 2 /* Further checks needed */ 577 578 static inline bool nested_svm_virtualize_tpr(struct kvm_vcpu *vcpu) 579 { 580 struct vcpu_svm *svm = to_svm(vcpu); 581 582 return is_guest_mode(vcpu) && (svm->nested.ctl.int_ctl & V_INTR_MASKING_MASK); 583 } 584 585 static inline bool nested_exit_on_smi(struct vcpu_svm *svm) 586 { 587 return vmcb12_is_intercept(&svm->nested.ctl, INTERCEPT_SMI); 588 } 589 590 static inline bool nested_exit_on_intr(struct vcpu_svm *svm) 591 { 592 return vmcb12_is_intercept(&svm->nested.ctl, INTERCEPT_INTR); 593 } 594 595 static inline bool nested_exit_on_nmi(struct vcpu_svm *svm) 596 { 597 return vmcb12_is_intercept(&svm->nested.ctl, INTERCEPT_NMI); 598 } 599 600 int enter_svm_guest_mode(struct kvm_vcpu *vcpu, 601 u64 vmcb_gpa, struct vmcb *vmcb12, bool from_vmrun); 602 void svm_leave_nested(struct kvm_vcpu *vcpu); 603 void svm_free_nested(struct vcpu_svm *svm); 604 int svm_allocate_nested(struct vcpu_svm *svm); 605 int nested_svm_vmrun(struct kvm_vcpu *vcpu); 606 void svm_copy_vmrun_state(struct vmcb_save_area *to_save, 607 struct vmcb_save_area *from_save); 608 void svm_copy_vmloadsave_state(struct vmcb *to_vmcb, struct vmcb *from_vmcb); 609 int nested_svm_vmexit(struct vcpu_svm *svm); 610 611 static inline int nested_svm_simple_vmexit(struct vcpu_svm *svm, u32 exit_code) 612 { 613 svm->vmcb->control.exit_code = exit_code; 614 svm->vmcb->control.exit_info_1 = 0; 615 svm->vmcb->control.exit_info_2 = 0; 616 return nested_svm_vmexit(svm); 617 } 618 619 int nested_svm_exit_handled(struct vcpu_svm *svm); 620 int nested_svm_check_permissions(struct kvm_vcpu *vcpu); 621 int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr, 622 bool has_error_code, u32 error_code); 623 int nested_svm_exit_special(struct vcpu_svm *svm); 624 void nested_svm_update_tsc_ratio_msr(struct kvm_vcpu *vcpu); 625 void svm_write_tsc_multiplier(struct kvm_vcpu *vcpu); 626 void nested_copy_vmcb_control_to_cache(struct vcpu_svm *svm, 627 struct vmcb_control_area *control); 628 void nested_copy_vmcb_save_to_cache(struct vcpu_svm *svm, 629 struct vmcb_save_area *save); 630 void nested_sync_control_from_vmcb02(struct vcpu_svm *svm); 631 void nested_vmcb02_compute_g_pat(struct vcpu_svm *svm); 632 void svm_switch_vmcb(struct vcpu_svm *svm, struct kvm_vmcb_info *target_vmcb); 633 634 extern struct kvm_x86_nested_ops svm_nested_ops; 635 636 /* avic.c */ 637 #define AVIC_REQUIRED_APICV_INHIBITS \ 638 ( \ 639 BIT(APICV_INHIBIT_REASON_DISABLE) | \ 640 BIT(APICV_INHIBIT_REASON_ABSENT) | \ 641 BIT(APICV_INHIBIT_REASON_HYPERV) | \ 642 BIT(APICV_INHIBIT_REASON_NESTED) | \ 643 BIT(APICV_INHIBIT_REASON_IRQWIN) | \ 644 BIT(APICV_INHIBIT_REASON_PIT_REINJ) | \ 645 BIT(APICV_INHIBIT_REASON_BLOCKIRQ) | \ 646 BIT(APICV_INHIBIT_REASON_SEV) | \ 647 BIT(APICV_INHIBIT_REASON_PHYSICAL_ID_ALIASED) | \ 648 BIT(APICV_INHIBIT_REASON_APIC_ID_MODIFIED) | \ 649 BIT(APICV_INHIBIT_REASON_APIC_BASE_MODIFIED) | \ 650 BIT(APICV_INHIBIT_REASON_LOGICAL_ID_ALIASED) \ 651 ) 652 653 bool avic_hardware_setup(void); 654 int avic_ga_log_notifier(u32 ga_tag); 655 void avic_vm_destroy(struct kvm *kvm); 656 int avic_vm_init(struct kvm *kvm); 657 void avic_init_vmcb(struct vcpu_svm *svm, struct vmcb *vmcb); 658 int avic_incomplete_ipi_interception(struct kvm_vcpu *vcpu); 659 int avic_unaccelerated_access_interception(struct kvm_vcpu *vcpu); 660 int avic_init_vcpu(struct vcpu_svm *svm); 661 void avic_vcpu_load(struct kvm_vcpu *vcpu, int cpu); 662 void avic_vcpu_put(struct kvm_vcpu *vcpu); 663 void avic_apicv_post_state_restore(struct kvm_vcpu *vcpu); 664 void avic_refresh_apicv_exec_ctrl(struct kvm_vcpu *vcpu); 665 int avic_pi_update_irte(struct kvm *kvm, unsigned int host_irq, 666 uint32_t guest_irq, bool set); 667 void avic_vcpu_blocking(struct kvm_vcpu *vcpu); 668 void avic_vcpu_unblocking(struct kvm_vcpu *vcpu); 669 void avic_ring_doorbell(struct kvm_vcpu *vcpu); 670 unsigned long avic_vcpu_get_apicv_inhibit_reasons(struct kvm_vcpu *vcpu); 671 void avic_refresh_virtual_apic_mode(struct kvm_vcpu *vcpu); 672 673 674 /* sev.c */ 675 676 void pre_sev_run(struct vcpu_svm *svm, int cpu); 677 void sev_init_vmcb(struct vcpu_svm *svm); 678 void sev_vcpu_after_set_cpuid(struct vcpu_svm *svm); 679 int sev_es_string_io(struct vcpu_svm *svm, int size, unsigned int port, int in); 680 void sev_es_vcpu_reset(struct vcpu_svm *svm); 681 void sev_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector); 682 void sev_es_prepare_switch_to_guest(struct vcpu_svm *svm, struct sev_es_save_area *hostsa); 683 void sev_es_unmap_ghcb(struct vcpu_svm *svm); 684 685 #ifdef CONFIG_KVM_AMD_SEV 686 int sev_mem_enc_ioctl(struct kvm *kvm, void __user *argp); 687 int sev_mem_enc_register_region(struct kvm *kvm, 688 struct kvm_enc_region *range); 689 int sev_mem_enc_unregister_region(struct kvm *kvm, 690 struct kvm_enc_region *range); 691 int sev_vm_copy_enc_context_from(struct kvm *kvm, unsigned int source_fd); 692 int sev_vm_move_enc_context_from(struct kvm *kvm, unsigned int source_fd); 693 void sev_guest_memory_reclaimed(struct kvm *kvm); 694 int sev_handle_vmgexit(struct kvm_vcpu *vcpu); 695 696 /* These symbols are used in common code and are stubbed below. */ 697 struct page *snp_safe_alloc_page(struct kvm_vcpu *vcpu); 698 void sev_free_vcpu(struct kvm_vcpu *vcpu); 699 void sev_vm_destroy(struct kvm *kvm); 700 void __init sev_set_cpu_caps(void); 701 void __init sev_hardware_setup(void); 702 void sev_hardware_unsetup(void); 703 int sev_cpu_init(struct svm_cpu_data *sd); 704 int sev_dev_get_attr(u32 group, u64 attr, u64 *val); 705 extern unsigned int max_sev_asid; 706 #else 707 static inline struct page *snp_safe_alloc_page(struct kvm_vcpu *vcpu) { 708 return alloc_page(GFP_KERNEL_ACCOUNT | __GFP_ZERO); 709 } 710 711 static inline void sev_free_vcpu(struct kvm_vcpu *vcpu) {} 712 static inline void sev_vm_destroy(struct kvm *kvm) {} 713 static inline void __init sev_set_cpu_caps(void) {} 714 static inline void __init sev_hardware_setup(void) {} 715 static inline void sev_hardware_unsetup(void) {} 716 static inline int sev_cpu_init(struct svm_cpu_data *sd) { return 0; } 717 static inline int sev_dev_get_attr(u32 group, u64 attr, u64 *val) { return -ENXIO; } 718 #define max_sev_asid 0 719 #endif 720 721 /* vmenter.S */ 722 723 void __svm_sev_es_vcpu_run(struct vcpu_svm *svm, bool spec_ctrl_intercepted, 724 struct sev_es_save_area *hostsa); 725 void __svm_vcpu_run(struct vcpu_svm *svm, bool spec_ctrl_intercepted); 726 727 #define DEFINE_KVM_GHCB_ACCESSORS(field) \ 728 static __always_inline bool kvm_ghcb_##field##_is_valid(const struct vcpu_svm *svm) \ 729 { \ 730 return test_bit(GHCB_BITMAP_IDX(field), \ 731 (unsigned long *)&svm->sev_es.valid_bitmap); \ 732 } \ 733 \ 734 static __always_inline u64 kvm_ghcb_get_##field##_if_valid(struct vcpu_svm *svm, struct ghcb *ghcb) \ 735 { \ 736 return kvm_ghcb_##field##_is_valid(svm) ? ghcb->save.field : 0; \ 737 } \ 738 739 DEFINE_KVM_GHCB_ACCESSORS(cpl) 740 DEFINE_KVM_GHCB_ACCESSORS(rax) 741 DEFINE_KVM_GHCB_ACCESSORS(rcx) 742 DEFINE_KVM_GHCB_ACCESSORS(rdx) 743 DEFINE_KVM_GHCB_ACCESSORS(rbx) 744 DEFINE_KVM_GHCB_ACCESSORS(rsi) 745 DEFINE_KVM_GHCB_ACCESSORS(sw_exit_code) 746 DEFINE_KVM_GHCB_ACCESSORS(sw_exit_info_1) 747 DEFINE_KVM_GHCB_ACCESSORS(sw_exit_info_2) 748 DEFINE_KVM_GHCB_ACCESSORS(sw_scratch) 749 DEFINE_KVM_GHCB_ACCESSORS(xcr0) 750 751 #endif 752