1 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 2 3 #include <linux/kvm_host.h> 4 5 #include "irq.h" 6 #include "mmu.h" 7 #include "kvm_cache_regs.h" 8 #include "x86.h" 9 #include "smm.h" 10 #include "cpuid.h" 11 #include "pmu.h" 12 13 #include <linux/module.h> 14 #include <linux/mod_devicetable.h> 15 #include <linux/kernel.h> 16 #include <linux/vmalloc.h> 17 #include <linux/highmem.h> 18 #include <linux/amd-iommu.h> 19 #include <linux/sched.h> 20 #include <linux/trace_events.h> 21 #include <linux/slab.h> 22 #include <linux/hashtable.h> 23 #include <linux/objtool.h> 24 #include <linux/psp-sev.h> 25 #include <linux/file.h> 26 #include <linux/pagemap.h> 27 #include <linux/swap.h> 28 #include <linux/rwsem.h> 29 #include <linux/cc_platform.h> 30 #include <linux/smp.h> 31 32 #include <asm/apic.h> 33 #include <asm/perf_event.h> 34 #include <asm/tlbflush.h> 35 #include <asm/desc.h> 36 #include <asm/debugreg.h> 37 #include <asm/kvm_para.h> 38 #include <asm/irq_remapping.h> 39 #include <asm/spec-ctrl.h> 40 #include <asm/cpu_device_id.h> 41 #include <asm/traps.h> 42 #include <asm/reboot.h> 43 #include <asm/fpu/api.h> 44 45 #include <trace/events/ipi.h> 46 47 #include "trace.h" 48 49 #include "svm.h" 50 #include "svm_ops.h" 51 52 #include "kvm_onhyperv.h" 53 #include "svm_onhyperv.h" 54 55 MODULE_AUTHOR("Qumranet"); 56 MODULE_LICENSE("GPL"); 57 58 #ifdef MODULE 59 static const struct x86_cpu_id svm_cpu_id[] = { 60 X86_MATCH_FEATURE(X86_FEATURE_SVM, NULL), 61 {} 62 }; 63 MODULE_DEVICE_TABLE(x86cpu, svm_cpu_id); 64 #endif 65 66 #define SEG_TYPE_LDT 2 67 #define SEG_TYPE_BUSY_TSS16 3 68 69 static bool erratum_383_found __read_mostly; 70 71 u32 msrpm_offsets[MSRPM_OFFSETS] __read_mostly; 72 73 /* 74 * Set osvw_len to higher value when updated Revision Guides 75 * are published and we know what the new status bits are 76 */ 77 static uint64_t osvw_len = 4, osvw_status; 78 79 static DEFINE_PER_CPU(u64, current_tsc_ratio); 80 81 #define X2APIC_MSR(x) (APIC_BASE_MSR + (x >> 4)) 82 83 static const struct svm_direct_access_msrs { 84 u32 index; /* Index of the MSR */ 85 bool always; /* True if intercept is initially cleared */ 86 } direct_access_msrs[MAX_DIRECT_ACCESS_MSRS] = { 87 { .index = MSR_STAR, .always = true }, 88 { .index = MSR_IA32_SYSENTER_CS, .always = true }, 89 { .index = MSR_IA32_SYSENTER_EIP, .always = false }, 90 { .index = MSR_IA32_SYSENTER_ESP, .always = false }, 91 #ifdef CONFIG_X86_64 92 { .index = MSR_GS_BASE, .always = true }, 93 { .index = MSR_FS_BASE, .always = true }, 94 { .index = MSR_KERNEL_GS_BASE, .always = true }, 95 { .index = MSR_LSTAR, .always = true }, 96 { .index = MSR_CSTAR, .always = true }, 97 { .index = MSR_SYSCALL_MASK, .always = true }, 98 #endif 99 { .index = MSR_IA32_SPEC_CTRL, .always = false }, 100 { .index = MSR_IA32_PRED_CMD, .always = false }, 101 { .index = MSR_IA32_FLUSH_CMD, .always = false }, 102 { .index = MSR_IA32_LASTBRANCHFROMIP, .always = false }, 103 { .index = MSR_IA32_LASTBRANCHTOIP, .always = false }, 104 { .index = MSR_IA32_LASTINTFROMIP, .always = false }, 105 { .index = MSR_IA32_LASTINTTOIP, .always = false }, 106 { .index = MSR_EFER, .always = false }, 107 { .index = MSR_IA32_CR_PAT, .always = false }, 108 { .index = MSR_AMD64_SEV_ES_GHCB, .always = true }, 109 { .index = MSR_TSC_AUX, .always = false }, 110 { .index = X2APIC_MSR(APIC_ID), .always = false }, 111 { .index = X2APIC_MSR(APIC_LVR), .always = false }, 112 { .index = X2APIC_MSR(APIC_TASKPRI), .always = false }, 113 { .index = X2APIC_MSR(APIC_ARBPRI), .always = false }, 114 { .index = X2APIC_MSR(APIC_PROCPRI), .always = false }, 115 { .index = X2APIC_MSR(APIC_EOI), .always = false }, 116 { .index = X2APIC_MSR(APIC_RRR), .always = false }, 117 { .index = X2APIC_MSR(APIC_LDR), .always = false }, 118 { .index = X2APIC_MSR(APIC_DFR), .always = false }, 119 { .index = X2APIC_MSR(APIC_SPIV), .always = false }, 120 { .index = X2APIC_MSR(APIC_ISR), .always = false }, 121 { .index = X2APIC_MSR(APIC_TMR), .always = false }, 122 { .index = X2APIC_MSR(APIC_IRR), .always = false }, 123 { .index = X2APIC_MSR(APIC_ESR), .always = false }, 124 { .index = X2APIC_MSR(APIC_ICR), .always = false }, 125 { .index = X2APIC_MSR(APIC_ICR2), .always = false }, 126 127 /* 128 * Note: 129 * AMD does not virtualize APIC TSC-deadline timer mode, but it is 130 * emulated by KVM. When setting APIC LVTT (0x832) register bit 18, 131 * the AVIC hardware would generate GP fault. Therefore, always 132 * intercept the MSR 0x832, and do not setup direct_access_msr. 133 */ 134 { .index = X2APIC_MSR(APIC_LVTTHMR), .always = false }, 135 { .index = X2APIC_MSR(APIC_LVTPC), .always = false }, 136 { .index = X2APIC_MSR(APIC_LVT0), .always = false }, 137 { .index = X2APIC_MSR(APIC_LVT1), .always = false }, 138 { .index = X2APIC_MSR(APIC_LVTERR), .always = false }, 139 { .index = X2APIC_MSR(APIC_TMICT), .always = false }, 140 { .index = X2APIC_MSR(APIC_TMCCT), .always = false }, 141 { .index = X2APIC_MSR(APIC_TDCR), .always = false }, 142 { .index = MSR_INVALID, .always = false }, 143 }; 144 145 /* 146 * These 2 parameters are used to config the controls for Pause-Loop Exiting: 147 * pause_filter_count: On processors that support Pause filtering(indicated 148 * by CPUID Fn8000_000A_EDX), the VMCB provides a 16 bit pause filter 149 * count value. On VMRUN this value is loaded into an internal counter. 150 * Each time a pause instruction is executed, this counter is decremented 151 * until it reaches zero at which time a #VMEXIT is generated if pause 152 * intercept is enabled. Refer to AMD APM Vol 2 Section 15.14.4 Pause 153 * Intercept Filtering for more details. 154 * This also indicate if ple logic enabled. 155 * 156 * pause_filter_thresh: In addition, some processor families support advanced 157 * pause filtering (indicated by CPUID Fn8000_000A_EDX) upper bound on 158 * the amount of time a guest is allowed to execute in a pause loop. 159 * In this mode, a 16-bit pause filter threshold field is added in the 160 * VMCB. The threshold value is a cycle count that is used to reset the 161 * pause counter. As with simple pause filtering, VMRUN loads the pause 162 * count value from VMCB into an internal counter. Then, on each pause 163 * instruction the hardware checks the elapsed number of cycles since 164 * the most recent pause instruction against the pause filter threshold. 165 * If the elapsed cycle count is greater than the pause filter threshold, 166 * then the internal pause count is reloaded from the VMCB and execution 167 * continues. If the elapsed cycle count is less than the pause filter 168 * threshold, then the internal pause count is decremented. If the count 169 * value is less than zero and PAUSE intercept is enabled, a #VMEXIT is 170 * triggered. If advanced pause filtering is supported and pause filter 171 * threshold field is set to zero, the filter will operate in the simpler, 172 * count only mode. 173 */ 174 175 static unsigned short pause_filter_thresh = KVM_DEFAULT_PLE_GAP; 176 module_param(pause_filter_thresh, ushort, 0444); 177 178 static unsigned short pause_filter_count = KVM_SVM_DEFAULT_PLE_WINDOW; 179 module_param(pause_filter_count, ushort, 0444); 180 181 /* Default doubles per-vcpu window every exit. */ 182 static unsigned short pause_filter_count_grow = KVM_DEFAULT_PLE_WINDOW_GROW; 183 module_param(pause_filter_count_grow, ushort, 0444); 184 185 /* Default resets per-vcpu window every exit to pause_filter_count. */ 186 static unsigned short pause_filter_count_shrink = KVM_DEFAULT_PLE_WINDOW_SHRINK; 187 module_param(pause_filter_count_shrink, ushort, 0444); 188 189 /* Default is to compute the maximum so we can never overflow. */ 190 static unsigned short pause_filter_count_max = KVM_SVM_DEFAULT_PLE_WINDOW_MAX; 191 module_param(pause_filter_count_max, ushort, 0444); 192 193 /* 194 * Use nested page tables by default. Note, NPT may get forced off by 195 * svm_hardware_setup() if it's unsupported by hardware or the host kernel. 196 */ 197 bool npt_enabled = true; 198 module_param_named(npt, npt_enabled, bool, 0444); 199 200 /* allow nested virtualization in KVM/SVM */ 201 static int nested = true; 202 module_param(nested, int, 0444); 203 204 /* enable/disable Next RIP Save */ 205 int nrips = true; 206 module_param(nrips, int, 0444); 207 208 /* enable/disable Virtual VMLOAD VMSAVE */ 209 static int vls = true; 210 module_param(vls, int, 0444); 211 212 /* enable/disable Virtual GIF */ 213 int vgif = true; 214 module_param(vgif, int, 0444); 215 216 /* enable/disable LBR virtualization */ 217 static int lbrv = true; 218 module_param(lbrv, int, 0444); 219 220 static int tsc_scaling = true; 221 module_param(tsc_scaling, int, 0444); 222 223 /* 224 * enable / disable AVIC. Because the defaults differ for APICv 225 * support between VMX and SVM we cannot use module_param_named. 226 */ 227 static bool avic; 228 module_param(avic, bool, 0444); 229 230 bool __read_mostly dump_invalid_vmcb; 231 module_param(dump_invalid_vmcb, bool, 0644); 232 233 234 bool intercept_smi = true; 235 module_param(intercept_smi, bool, 0444); 236 237 bool vnmi = true; 238 module_param(vnmi, bool, 0444); 239 240 static bool svm_gp_erratum_intercept = true; 241 242 static u8 rsm_ins_bytes[] = "\x0f\xaa"; 243 244 static unsigned long iopm_base; 245 246 DEFINE_PER_CPU(struct svm_cpu_data, svm_data); 247 248 /* 249 * Only MSR_TSC_AUX is switched via the user return hook. EFER is switched via 250 * the VMCB, and the SYSCALL/SYSENTER MSRs are handled by VMLOAD/VMSAVE. 251 * 252 * RDTSCP and RDPID are not used in the kernel, specifically to allow KVM to 253 * defer the restoration of TSC_AUX until the CPU returns to userspace. 254 */ 255 static int tsc_aux_uret_slot __read_mostly = -1; 256 257 static const u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000}; 258 259 #define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges) 260 #define MSRS_RANGE_SIZE 2048 261 #define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2) 262 263 u32 svm_msrpm_offset(u32 msr) 264 { 265 u32 offset; 266 int i; 267 268 for (i = 0; i < NUM_MSR_MAPS; i++) { 269 if (msr < msrpm_ranges[i] || 270 msr >= msrpm_ranges[i] + MSRS_IN_RANGE) 271 continue; 272 273 offset = (msr - msrpm_ranges[i]) / 4; /* 4 msrs per u8 */ 274 offset += (i * MSRS_RANGE_SIZE); /* add range offset */ 275 276 /* Now we have the u8 offset - but need the u32 offset */ 277 return offset / 4; 278 } 279 280 /* MSR not in any range */ 281 return MSR_INVALID; 282 } 283 284 static void svm_flush_tlb_current(struct kvm_vcpu *vcpu); 285 286 static int get_npt_level(void) 287 { 288 #ifdef CONFIG_X86_64 289 return pgtable_l5_enabled() ? PT64_ROOT_5LEVEL : PT64_ROOT_4LEVEL; 290 #else 291 return PT32E_ROOT_LEVEL; 292 #endif 293 } 294 295 int svm_set_efer(struct kvm_vcpu *vcpu, u64 efer) 296 { 297 struct vcpu_svm *svm = to_svm(vcpu); 298 u64 old_efer = vcpu->arch.efer; 299 vcpu->arch.efer = efer; 300 301 if (!npt_enabled) { 302 /* Shadow paging assumes NX to be available. */ 303 efer |= EFER_NX; 304 305 if (!(efer & EFER_LMA)) 306 efer &= ~EFER_LME; 307 } 308 309 if ((old_efer & EFER_SVME) != (efer & EFER_SVME)) { 310 if (!(efer & EFER_SVME)) { 311 svm_leave_nested(vcpu); 312 svm_set_gif(svm, true); 313 /* #GP intercept is still needed for vmware backdoor */ 314 if (!enable_vmware_backdoor) 315 clr_exception_intercept(svm, GP_VECTOR); 316 317 /* 318 * Free the nested guest state, unless we are in SMM. 319 * In this case we will return to the nested guest 320 * as soon as we leave SMM. 321 */ 322 if (!is_smm(vcpu)) 323 svm_free_nested(svm); 324 325 } else { 326 int ret = svm_allocate_nested(svm); 327 328 if (ret) { 329 vcpu->arch.efer = old_efer; 330 return ret; 331 } 332 333 /* 334 * Never intercept #GP for SEV guests, KVM can't 335 * decrypt guest memory to workaround the erratum. 336 */ 337 if (svm_gp_erratum_intercept && !sev_guest(vcpu->kvm)) 338 set_exception_intercept(svm, GP_VECTOR); 339 } 340 } 341 342 svm->vmcb->save.efer = efer | EFER_SVME; 343 vmcb_mark_dirty(svm->vmcb, VMCB_CR); 344 return 0; 345 } 346 347 static u32 svm_get_interrupt_shadow(struct kvm_vcpu *vcpu) 348 { 349 struct vcpu_svm *svm = to_svm(vcpu); 350 u32 ret = 0; 351 352 if (svm->vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) 353 ret = KVM_X86_SHADOW_INT_STI | KVM_X86_SHADOW_INT_MOV_SS; 354 return ret; 355 } 356 357 static void svm_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask) 358 { 359 struct vcpu_svm *svm = to_svm(vcpu); 360 361 if (mask == 0) 362 svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK; 363 else 364 svm->vmcb->control.int_state |= SVM_INTERRUPT_SHADOW_MASK; 365 366 } 367 368 static int __svm_skip_emulated_instruction(struct kvm_vcpu *vcpu, 369 bool commit_side_effects) 370 { 371 struct vcpu_svm *svm = to_svm(vcpu); 372 unsigned long old_rflags; 373 374 /* 375 * SEV-ES does not expose the next RIP. The RIP update is controlled by 376 * the type of exit and the #VC handler in the guest. 377 */ 378 if (sev_es_guest(vcpu->kvm)) 379 goto done; 380 381 if (nrips && svm->vmcb->control.next_rip != 0) { 382 WARN_ON_ONCE(!static_cpu_has(X86_FEATURE_NRIPS)); 383 svm->next_rip = svm->vmcb->control.next_rip; 384 } 385 386 if (!svm->next_rip) { 387 if (unlikely(!commit_side_effects)) 388 old_rflags = svm->vmcb->save.rflags; 389 390 if (!kvm_emulate_instruction(vcpu, EMULTYPE_SKIP)) 391 return 0; 392 393 if (unlikely(!commit_side_effects)) 394 svm->vmcb->save.rflags = old_rflags; 395 } else { 396 kvm_rip_write(vcpu, svm->next_rip); 397 } 398 399 done: 400 if (likely(commit_side_effects)) 401 svm_set_interrupt_shadow(vcpu, 0); 402 403 return 1; 404 } 405 406 static int svm_skip_emulated_instruction(struct kvm_vcpu *vcpu) 407 { 408 return __svm_skip_emulated_instruction(vcpu, true); 409 } 410 411 static int svm_update_soft_interrupt_rip(struct kvm_vcpu *vcpu) 412 { 413 unsigned long rip, old_rip = kvm_rip_read(vcpu); 414 struct vcpu_svm *svm = to_svm(vcpu); 415 416 /* 417 * Due to architectural shortcomings, the CPU doesn't always provide 418 * NextRIP, e.g. if KVM intercepted an exception that occurred while 419 * the CPU was vectoring an INTO/INT3 in the guest. Temporarily skip 420 * the instruction even if NextRIP is supported to acquire the next 421 * RIP so that it can be shoved into the NextRIP field, otherwise 422 * hardware will fail to advance guest RIP during event injection. 423 * Drop the exception/interrupt if emulation fails and effectively 424 * retry the instruction, it's the least awful option. If NRIPS is 425 * in use, the skip must not commit any side effects such as clearing 426 * the interrupt shadow or RFLAGS.RF. 427 */ 428 if (!__svm_skip_emulated_instruction(vcpu, !nrips)) 429 return -EIO; 430 431 rip = kvm_rip_read(vcpu); 432 433 /* 434 * Save the injection information, even when using next_rip, as the 435 * VMCB's next_rip will be lost (cleared on VM-Exit) if the injection 436 * doesn't complete due to a VM-Exit occurring while the CPU is 437 * vectoring the event. Decoding the instruction isn't guaranteed to 438 * work as there may be no backing instruction, e.g. if the event is 439 * being injected by L1 for L2, or if the guest is patching INT3 into 440 * a different instruction. 441 */ 442 svm->soft_int_injected = true; 443 svm->soft_int_csbase = svm->vmcb->save.cs.base; 444 svm->soft_int_old_rip = old_rip; 445 svm->soft_int_next_rip = rip; 446 447 if (nrips) 448 kvm_rip_write(vcpu, old_rip); 449 450 if (static_cpu_has(X86_FEATURE_NRIPS)) 451 svm->vmcb->control.next_rip = rip; 452 453 return 0; 454 } 455 456 static void svm_inject_exception(struct kvm_vcpu *vcpu) 457 { 458 struct kvm_queued_exception *ex = &vcpu->arch.exception; 459 struct vcpu_svm *svm = to_svm(vcpu); 460 461 kvm_deliver_exception_payload(vcpu, ex); 462 463 if (kvm_exception_is_soft(ex->vector) && 464 svm_update_soft_interrupt_rip(vcpu)) 465 return; 466 467 svm->vmcb->control.event_inj = ex->vector 468 | SVM_EVTINJ_VALID 469 | (ex->has_error_code ? SVM_EVTINJ_VALID_ERR : 0) 470 | SVM_EVTINJ_TYPE_EXEPT; 471 svm->vmcb->control.event_inj_err = ex->error_code; 472 } 473 474 static void svm_init_erratum_383(void) 475 { 476 u32 low, high; 477 int err; 478 u64 val; 479 480 if (!static_cpu_has_bug(X86_BUG_AMD_TLB_MMATCH)) 481 return; 482 483 /* Use _safe variants to not break nested virtualization */ 484 val = native_read_msr_safe(MSR_AMD64_DC_CFG, &err); 485 if (err) 486 return; 487 488 val |= (1ULL << 47); 489 490 low = lower_32_bits(val); 491 high = upper_32_bits(val); 492 493 native_write_msr_safe(MSR_AMD64_DC_CFG, low, high); 494 495 erratum_383_found = true; 496 } 497 498 static void svm_init_osvw(struct kvm_vcpu *vcpu) 499 { 500 /* 501 * Guests should see errata 400 and 415 as fixed (assuming that 502 * HLT and IO instructions are intercepted). 503 */ 504 vcpu->arch.osvw.length = (osvw_len >= 3) ? (osvw_len) : 3; 505 vcpu->arch.osvw.status = osvw_status & ~(6ULL); 506 507 /* 508 * By increasing VCPU's osvw.length to 3 we are telling the guest that 509 * all osvw.status bits inside that length, including bit 0 (which is 510 * reserved for erratum 298), are valid. However, if host processor's 511 * osvw_len is 0 then osvw_status[0] carries no information. We need to 512 * be conservative here and therefore we tell the guest that erratum 298 513 * is present (because we really don't know). 514 */ 515 if (osvw_len == 0 && boot_cpu_data.x86 == 0x10) 516 vcpu->arch.osvw.status |= 1; 517 } 518 519 static bool __kvm_is_svm_supported(void) 520 { 521 int cpu = smp_processor_id(); 522 struct cpuinfo_x86 *c = &cpu_data(cpu); 523 524 if (c->x86_vendor != X86_VENDOR_AMD && 525 c->x86_vendor != X86_VENDOR_HYGON) { 526 pr_err("CPU %d isn't AMD or Hygon\n", cpu); 527 return false; 528 } 529 530 if (!cpu_has(c, X86_FEATURE_SVM)) { 531 pr_err("SVM not supported by CPU %d\n", cpu); 532 return false; 533 } 534 535 if (cc_platform_has(CC_ATTR_GUEST_MEM_ENCRYPT)) { 536 pr_info("KVM is unsupported when running as an SEV guest\n"); 537 return false; 538 } 539 540 return true; 541 } 542 543 static bool kvm_is_svm_supported(void) 544 { 545 bool supported; 546 547 migrate_disable(); 548 supported = __kvm_is_svm_supported(); 549 migrate_enable(); 550 551 return supported; 552 } 553 554 static int svm_check_processor_compat(void) 555 { 556 if (!__kvm_is_svm_supported()) 557 return -EIO; 558 559 return 0; 560 } 561 562 static void __svm_write_tsc_multiplier(u64 multiplier) 563 { 564 if (multiplier == __this_cpu_read(current_tsc_ratio)) 565 return; 566 567 wrmsrl(MSR_AMD64_TSC_RATIO, multiplier); 568 __this_cpu_write(current_tsc_ratio, multiplier); 569 } 570 571 static inline void kvm_cpu_svm_disable(void) 572 { 573 uint64_t efer; 574 575 wrmsrl(MSR_VM_HSAVE_PA, 0); 576 rdmsrl(MSR_EFER, efer); 577 if (efer & EFER_SVME) { 578 /* 579 * Force GIF=1 prior to disabling SVM, e.g. to ensure INIT and 580 * NMI aren't blocked. 581 */ 582 stgi(); 583 wrmsrl(MSR_EFER, efer & ~EFER_SVME); 584 } 585 } 586 587 static void svm_emergency_disable(void) 588 { 589 kvm_rebooting = true; 590 591 kvm_cpu_svm_disable(); 592 } 593 594 static void svm_hardware_disable(void) 595 { 596 /* Make sure we clean up behind us */ 597 if (tsc_scaling) 598 __svm_write_tsc_multiplier(SVM_TSC_RATIO_DEFAULT); 599 600 kvm_cpu_svm_disable(); 601 602 amd_pmu_disable_virt(); 603 } 604 605 static int svm_hardware_enable(void) 606 { 607 608 struct svm_cpu_data *sd; 609 uint64_t efer; 610 int me = raw_smp_processor_id(); 611 612 rdmsrl(MSR_EFER, efer); 613 if (efer & EFER_SVME) 614 return -EBUSY; 615 616 sd = per_cpu_ptr(&svm_data, me); 617 sd->asid_generation = 1; 618 sd->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1; 619 sd->next_asid = sd->max_asid + 1; 620 sd->min_asid = max_sev_asid + 1; 621 622 wrmsrl(MSR_EFER, efer | EFER_SVME); 623 624 wrmsrl(MSR_VM_HSAVE_PA, sd->save_area_pa); 625 626 if (static_cpu_has(X86_FEATURE_TSCRATEMSR)) { 627 /* 628 * Set the default value, even if we don't use TSC scaling 629 * to avoid having stale value in the msr 630 */ 631 __svm_write_tsc_multiplier(SVM_TSC_RATIO_DEFAULT); 632 } 633 634 635 /* 636 * Get OSVW bits. 637 * 638 * Note that it is possible to have a system with mixed processor 639 * revisions and therefore different OSVW bits. If bits are not the same 640 * on different processors then choose the worst case (i.e. if erratum 641 * is present on one processor and not on another then assume that the 642 * erratum is present everywhere). 643 */ 644 if (cpu_has(&boot_cpu_data, X86_FEATURE_OSVW)) { 645 uint64_t len, status = 0; 646 int err; 647 648 len = native_read_msr_safe(MSR_AMD64_OSVW_ID_LENGTH, &err); 649 if (!err) 650 status = native_read_msr_safe(MSR_AMD64_OSVW_STATUS, 651 &err); 652 653 if (err) 654 osvw_status = osvw_len = 0; 655 else { 656 if (len < osvw_len) 657 osvw_len = len; 658 osvw_status |= status; 659 osvw_status &= (1ULL << osvw_len) - 1; 660 } 661 } else 662 osvw_status = osvw_len = 0; 663 664 svm_init_erratum_383(); 665 666 amd_pmu_enable_virt(); 667 668 /* 669 * If TSC_AUX virtualization is supported, TSC_AUX becomes a swap type 670 * "B" field (see sev_es_prepare_switch_to_guest()) for SEV-ES guests. 671 * Since Linux does not change the value of TSC_AUX once set, prime the 672 * TSC_AUX field now to avoid a RDMSR on every vCPU run. 673 */ 674 if (boot_cpu_has(X86_FEATURE_V_TSC_AUX)) { 675 struct sev_es_save_area *hostsa; 676 u32 __maybe_unused msr_hi; 677 678 hostsa = (struct sev_es_save_area *)(page_address(sd->save_area) + 0x400); 679 680 rdmsr(MSR_TSC_AUX, hostsa->tsc_aux, msr_hi); 681 } 682 683 return 0; 684 } 685 686 static void svm_cpu_uninit(int cpu) 687 { 688 struct svm_cpu_data *sd = per_cpu_ptr(&svm_data, cpu); 689 690 if (!sd->save_area) 691 return; 692 693 kfree(sd->sev_vmcbs); 694 __free_page(sd->save_area); 695 sd->save_area_pa = 0; 696 sd->save_area = NULL; 697 } 698 699 static int svm_cpu_init(int cpu) 700 { 701 struct svm_cpu_data *sd = per_cpu_ptr(&svm_data, cpu); 702 int ret = -ENOMEM; 703 704 memset(sd, 0, sizeof(struct svm_cpu_data)); 705 sd->save_area = alloc_page(GFP_KERNEL | __GFP_ZERO); 706 if (!sd->save_area) 707 return ret; 708 709 ret = sev_cpu_init(sd); 710 if (ret) 711 goto free_save_area; 712 713 sd->save_area_pa = __sme_page_pa(sd->save_area); 714 return 0; 715 716 free_save_area: 717 __free_page(sd->save_area); 718 sd->save_area = NULL; 719 return ret; 720 721 } 722 723 static void set_dr_intercepts(struct vcpu_svm *svm) 724 { 725 struct vmcb *vmcb = svm->vmcb01.ptr; 726 727 vmcb_set_intercept(&vmcb->control, INTERCEPT_DR0_READ); 728 vmcb_set_intercept(&vmcb->control, INTERCEPT_DR1_READ); 729 vmcb_set_intercept(&vmcb->control, INTERCEPT_DR2_READ); 730 vmcb_set_intercept(&vmcb->control, INTERCEPT_DR3_READ); 731 vmcb_set_intercept(&vmcb->control, INTERCEPT_DR4_READ); 732 vmcb_set_intercept(&vmcb->control, INTERCEPT_DR5_READ); 733 vmcb_set_intercept(&vmcb->control, INTERCEPT_DR6_READ); 734 vmcb_set_intercept(&vmcb->control, INTERCEPT_DR0_WRITE); 735 vmcb_set_intercept(&vmcb->control, INTERCEPT_DR1_WRITE); 736 vmcb_set_intercept(&vmcb->control, INTERCEPT_DR2_WRITE); 737 vmcb_set_intercept(&vmcb->control, INTERCEPT_DR3_WRITE); 738 vmcb_set_intercept(&vmcb->control, INTERCEPT_DR4_WRITE); 739 vmcb_set_intercept(&vmcb->control, INTERCEPT_DR5_WRITE); 740 vmcb_set_intercept(&vmcb->control, INTERCEPT_DR6_WRITE); 741 vmcb_set_intercept(&vmcb->control, INTERCEPT_DR7_READ); 742 vmcb_set_intercept(&vmcb->control, INTERCEPT_DR7_WRITE); 743 744 recalc_intercepts(svm); 745 } 746 747 static void clr_dr_intercepts(struct vcpu_svm *svm) 748 { 749 struct vmcb *vmcb = svm->vmcb01.ptr; 750 751 vmcb->control.intercepts[INTERCEPT_DR] = 0; 752 753 recalc_intercepts(svm); 754 } 755 756 static int direct_access_msr_slot(u32 msr) 757 { 758 u32 i; 759 760 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) 761 if (direct_access_msrs[i].index == msr) 762 return i; 763 764 return -ENOENT; 765 } 766 767 static void set_shadow_msr_intercept(struct kvm_vcpu *vcpu, u32 msr, int read, 768 int write) 769 { 770 struct vcpu_svm *svm = to_svm(vcpu); 771 int slot = direct_access_msr_slot(msr); 772 773 if (slot == -ENOENT) 774 return; 775 776 /* Set the shadow bitmaps to the desired intercept states */ 777 if (read) 778 set_bit(slot, svm->shadow_msr_intercept.read); 779 else 780 clear_bit(slot, svm->shadow_msr_intercept.read); 781 782 if (write) 783 set_bit(slot, svm->shadow_msr_intercept.write); 784 else 785 clear_bit(slot, svm->shadow_msr_intercept.write); 786 } 787 788 static bool valid_msr_intercept(u32 index) 789 { 790 return direct_access_msr_slot(index) != -ENOENT; 791 } 792 793 static bool msr_write_intercepted(struct kvm_vcpu *vcpu, u32 msr) 794 { 795 u8 bit_write; 796 unsigned long tmp; 797 u32 offset; 798 u32 *msrpm; 799 800 /* 801 * For non-nested case: 802 * If the L01 MSR bitmap does not intercept the MSR, then we need to 803 * save it. 804 * 805 * For nested case: 806 * If the L02 MSR bitmap does not intercept the MSR, then we need to 807 * save it. 808 */ 809 msrpm = is_guest_mode(vcpu) ? to_svm(vcpu)->nested.msrpm: 810 to_svm(vcpu)->msrpm; 811 812 offset = svm_msrpm_offset(msr); 813 bit_write = 2 * (msr & 0x0f) + 1; 814 tmp = msrpm[offset]; 815 816 BUG_ON(offset == MSR_INVALID); 817 818 return test_bit(bit_write, &tmp); 819 } 820 821 static void set_msr_interception_bitmap(struct kvm_vcpu *vcpu, u32 *msrpm, 822 u32 msr, int read, int write) 823 { 824 struct vcpu_svm *svm = to_svm(vcpu); 825 u8 bit_read, bit_write; 826 unsigned long tmp; 827 u32 offset; 828 829 /* 830 * If this warning triggers extend the direct_access_msrs list at the 831 * beginning of the file 832 */ 833 WARN_ON(!valid_msr_intercept(msr)); 834 835 /* Enforce non allowed MSRs to trap */ 836 if (read && !kvm_msr_allowed(vcpu, msr, KVM_MSR_FILTER_READ)) 837 read = 0; 838 839 if (write && !kvm_msr_allowed(vcpu, msr, KVM_MSR_FILTER_WRITE)) 840 write = 0; 841 842 offset = svm_msrpm_offset(msr); 843 bit_read = 2 * (msr & 0x0f); 844 bit_write = 2 * (msr & 0x0f) + 1; 845 tmp = msrpm[offset]; 846 847 BUG_ON(offset == MSR_INVALID); 848 849 read ? clear_bit(bit_read, &tmp) : set_bit(bit_read, &tmp); 850 write ? clear_bit(bit_write, &tmp) : set_bit(bit_write, &tmp); 851 852 msrpm[offset] = tmp; 853 854 svm_hv_vmcb_dirty_nested_enlightenments(vcpu); 855 svm->nested.force_msr_bitmap_recalc = true; 856 } 857 858 void set_msr_interception(struct kvm_vcpu *vcpu, u32 *msrpm, u32 msr, 859 int read, int write) 860 { 861 set_shadow_msr_intercept(vcpu, msr, read, write); 862 set_msr_interception_bitmap(vcpu, msrpm, msr, read, write); 863 } 864 865 u32 *svm_vcpu_alloc_msrpm(void) 866 { 867 unsigned int order = get_order(MSRPM_SIZE); 868 struct page *pages = alloc_pages(GFP_KERNEL_ACCOUNT, order); 869 u32 *msrpm; 870 871 if (!pages) 872 return NULL; 873 874 msrpm = page_address(pages); 875 memset(msrpm, 0xff, PAGE_SIZE * (1 << order)); 876 877 return msrpm; 878 } 879 880 void svm_vcpu_init_msrpm(struct kvm_vcpu *vcpu, u32 *msrpm) 881 { 882 int i; 883 884 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) { 885 if (!direct_access_msrs[i].always) 886 continue; 887 set_msr_interception(vcpu, msrpm, direct_access_msrs[i].index, 1, 1); 888 } 889 } 890 891 void svm_set_x2apic_msr_interception(struct vcpu_svm *svm, bool intercept) 892 { 893 int i; 894 895 if (intercept == svm->x2avic_msrs_intercepted) 896 return; 897 898 if (!x2avic_enabled) 899 return; 900 901 for (i = 0; i < MAX_DIRECT_ACCESS_MSRS; i++) { 902 int index = direct_access_msrs[i].index; 903 904 if ((index < APIC_BASE_MSR) || 905 (index > APIC_BASE_MSR + 0xff)) 906 continue; 907 set_msr_interception(&svm->vcpu, svm->msrpm, index, 908 !intercept, !intercept); 909 } 910 911 svm->x2avic_msrs_intercepted = intercept; 912 } 913 914 void svm_vcpu_free_msrpm(u32 *msrpm) 915 { 916 __free_pages(virt_to_page(msrpm), get_order(MSRPM_SIZE)); 917 } 918 919 static void svm_msr_filter_changed(struct kvm_vcpu *vcpu) 920 { 921 struct vcpu_svm *svm = to_svm(vcpu); 922 u32 i; 923 924 /* 925 * Set intercept permissions for all direct access MSRs again. They 926 * will automatically get filtered through the MSR filter, so we are 927 * back in sync after this. 928 */ 929 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) { 930 u32 msr = direct_access_msrs[i].index; 931 u32 read = test_bit(i, svm->shadow_msr_intercept.read); 932 u32 write = test_bit(i, svm->shadow_msr_intercept.write); 933 934 set_msr_interception_bitmap(vcpu, svm->msrpm, msr, read, write); 935 } 936 } 937 938 static void add_msr_offset(u32 offset) 939 { 940 int i; 941 942 for (i = 0; i < MSRPM_OFFSETS; ++i) { 943 944 /* Offset already in list? */ 945 if (msrpm_offsets[i] == offset) 946 return; 947 948 /* Slot used by another offset? */ 949 if (msrpm_offsets[i] != MSR_INVALID) 950 continue; 951 952 /* Add offset to list */ 953 msrpm_offsets[i] = offset; 954 955 return; 956 } 957 958 /* 959 * If this BUG triggers the msrpm_offsets table has an overflow. Just 960 * increase MSRPM_OFFSETS in this case. 961 */ 962 BUG(); 963 } 964 965 static void init_msrpm_offsets(void) 966 { 967 int i; 968 969 memset(msrpm_offsets, 0xff, sizeof(msrpm_offsets)); 970 971 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) { 972 u32 offset; 973 974 offset = svm_msrpm_offset(direct_access_msrs[i].index); 975 BUG_ON(offset == MSR_INVALID); 976 977 add_msr_offset(offset); 978 } 979 } 980 981 void svm_copy_lbrs(struct vmcb *to_vmcb, struct vmcb *from_vmcb) 982 { 983 to_vmcb->save.dbgctl = from_vmcb->save.dbgctl; 984 to_vmcb->save.br_from = from_vmcb->save.br_from; 985 to_vmcb->save.br_to = from_vmcb->save.br_to; 986 to_vmcb->save.last_excp_from = from_vmcb->save.last_excp_from; 987 to_vmcb->save.last_excp_to = from_vmcb->save.last_excp_to; 988 989 vmcb_mark_dirty(to_vmcb, VMCB_LBR); 990 } 991 992 static void svm_enable_lbrv(struct kvm_vcpu *vcpu) 993 { 994 struct vcpu_svm *svm = to_svm(vcpu); 995 996 svm->vmcb->control.virt_ext |= LBR_CTL_ENABLE_MASK; 997 set_msr_interception(vcpu, svm->msrpm, MSR_IA32_LASTBRANCHFROMIP, 1, 1); 998 set_msr_interception(vcpu, svm->msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1); 999 set_msr_interception(vcpu, svm->msrpm, MSR_IA32_LASTINTFROMIP, 1, 1); 1000 set_msr_interception(vcpu, svm->msrpm, MSR_IA32_LASTINTTOIP, 1, 1); 1001 1002 /* Move the LBR msrs to the vmcb02 so that the guest can see them. */ 1003 if (is_guest_mode(vcpu)) 1004 svm_copy_lbrs(svm->vmcb, svm->vmcb01.ptr); 1005 } 1006 1007 static void svm_disable_lbrv(struct kvm_vcpu *vcpu) 1008 { 1009 struct vcpu_svm *svm = to_svm(vcpu); 1010 1011 svm->vmcb->control.virt_ext &= ~LBR_CTL_ENABLE_MASK; 1012 set_msr_interception(vcpu, svm->msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0); 1013 set_msr_interception(vcpu, svm->msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0); 1014 set_msr_interception(vcpu, svm->msrpm, MSR_IA32_LASTINTFROMIP, 0, 0); 1015 set_msr_interception(vcpu, svm->msrpm, MSR_IA32_LASTINTTOIP, 0, 0); 1016 1017 /* 1018 * Move the LBR msrs back to the vmcb01 to avoid copying them 1019 * on nested guest entries. 1020 */ 1021 if (is_guest_mode(vcpu)) 1022 svm_copy_lbrs(svm->vmcb01.ptr, svm->vmcb); 1023 } 1024 1025 static struct vmcb *svm_get_lbr_vmcb(struct vcpu_svm *svm) 1026 { 1027 /* 1028 * If LBR virtualization is disabled, the LBR MSRs are always kept in 1029 * vmcb01. If LBR virtualization is enabled and L1 is running VMs of 1030 * its own, the MSRs are moved between vmcb01 and vmcb02 as needed. 1031 */ 1032 return svm->vmcb->control.virt_ext & LBR_CTL_ENABLE_MASK ? svm->vmcb : 1033 svm->vmcb01.ptr; 1034 } 1035 1036 void svm_update_lbrv(struct kvm_vcpu *vcpu) 1037 { 1038 struct vcpu_svm *svm = to_svm(vcpu); 1039 bool current_enable_lbrv = svm->vmcb->control.virt_ext & LBR_CTL_ENABLE_MASK; 1040 bool enable_lbrv = (svm_get_lbr_vmcb(svm)->save.dbgctl & DEBUGCTLMSR_LBR) || 1041 (is_guest_mode(vcpu) && guest_can_use(vcpu, X86_FEATURE_LBRV) && 1042 (svm->nested.ctl.virt_ext & LBR_CTL_ENABLE_MASK)); 1043 1044 if (enable_lbrv == current_enable_lbrv) 1045 return; 1046 1047 if (enable_lbrv) 1048 svm_enable_lbrv(vcpu); 1049 else 1050 svm_disable_lbrv(vcpu); 1051 } 1052 1053 void disable_nmi_singlestep(struct vcpu_svm *svm) 1054 { 1055 svm->nmi_singlestep = false; 1056 1057 if (!(svm->vcpu.guest_debug & KVM_GUESTDBG_SINGLESTEP)) { 1058 /* Clear our flags if they were not set by the guest */ 1059 if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_TF)) 1060 svm->vmcb->save.rflags &= ~X86_EFLAGS_TF; 1061 if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_RF)) 1062 svm->vmcb->save.rflags &= ~X86_EFLAGS_RF; 1063 } 1064 } 1065 1066 static void grow_ple_window(struct kvm_vcpu *vcpu) 1067 { 1068 struct vcpu_svm *svm = to_svm(vcpu); 1069 struct vmcb_control_area *control = &svm->vmcb->control; 1070 int old = control->pause_filter_count; 1071 1072 if (kvm_pause_in_guest(vcpu->kvm)) 1073 return; 1074 1075 control->pause_filter_count = __grow_ple_window(old, 1076 pause_filter_count, 1077 pause_filter_count_grow, 1078 pause_filter_count_max); 1079 1080 if (control->pause_filter_count != old) { 1081 vmcb_mark_dirty(svm->vmcb, VMCB_INTERCEPTS); 1082 trace_kvm_ple_window_update(vcpu->vcpu_id, 1083 control->pause_filter_count, old); 1084 } 1085 } 1086 1087 static void shrink_ple_window(struct kvm_vcpu *vcpu) 1088 { 1089 struct vcpu_svm *svm = to_svm(vcpu); 1090 struct vmcb_control_area *control = &svm->vmcb->control; 1091 int old = control->pause_filter_count; 1092 1093 if (kvm_pause_in_guest(vcpu->kvm)) 1094 return; 1095 1096 control->pause_filter_count = 1097 __shrink_ple_window(old, 1098 pause_filter_count, 1099 pause_filter_count_shrink, 1100 pause_filter_count); 1101 if (control->pause_filter_count != old) { 1102 vmcb_mark_dirty(svm->vmcb, VMCB_INTERCEPTS); 1103 trace_kvm_ple_window_update(vcpu->vcpu_id, 1104 control->pause_filter_count, old); 1105 } 1106 } 1107 1108 static void svm_hardware_unsetup(void) 1109 { 1110 int cpu; 1111 1112 sev_hardware_unsetup(); 1113 1114 for_each_possible_cpu(cpu) 1115 svm_cpu_uninit(cpu); 1116 1117 __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), 1118 get_order(IOPM_SIZE)); 1119 iopm_base = 0; 1120 } 1121 1122 static void init_seg(struct vmcb_seg *seg) 1123 { 1124 seg->selector = 0; 1125 seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK | 1126 SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */ 1127 seg->limit = 0xffff; 1128 seg->base = 0; 1129 } 1130 1131 static void init_sys_seg(struct vmcb_seg *seg, uint32_t type) 1132 { 1133 seg->selector = 0; 1134 seg->attrib = SVM_SELECTOR_P_MASK | type; 1135 seg->limit = 0xffff; 1136 seg->base = 0; 1137 } 1138 1139 static u64 svm_get_l2_tsc_offset(struct kvm_vcpu *vcpu) 1140 { 1141 struct vcpu_svm *svm = to_svm(vcpu); 1142 1143 return svm->nested.ctl.tsc_offset; 1144 } 1145 1146 static u64 svm_get_l2_tsc_multiplier(struct kvm_vcpu *vcpu) 1147 { 1148 struct vcpu_svm *svm = to_svm(vcpu); 1149 1150 return svm->tsc_ratio_msr; 1151 } 1152 1153 static void svm_write_tsc_offset(struct kvm_vcpu *vcpu) 1154 { 1155 struct vcpu_svm *svm = to_svm(vcpu); 1156 1157 svm->vmcb01.ptr->control.tsc_offset = vcpu->arch.l1_tsc_offset; 1158 svm->vmcb->control.tsc_offset = vcpu->arch.tsc_offset; 1159 vmcb_mark_dirty(svm->vmcb, VMCB_INTERCEPTS); 1160 } 1161 1162 void svm_write_tsc_multiplier(struct kvm_vcpu *vcpu) 1163 { 1164 preempt_disable(); 1165 if (to_svm(vcpu)->guest_state_loaded) 1166 __svm_write_tsc_multiplier(vcpu->arch.tsc_scaling_ratio); 1167 preempt_enable(); 1168 } 1169 1170 /* Evaluate instruction intercepts that depend on guest CPUID features. */ 1171 static void svm_recalc_instruction_intercepts(struct kvm_vcpu *vcpu, 1172 struct vcpu_svm *svm) 1173 { 1174 /* 1175 * Intercept INVPCID if shadow paging is enabled to sync/free shadow 1176 * roots, or if INVPCID is disabled in the guest to inject #UD. 1177 */ 1178 if (kvm_cpu_cap_has(X86_FEATURE_INVPCID)) { 1179 if (!npt_enabled || 1180 !guest_cpuid_has(&svm->vcpu, X86_FEATURE_INVPCID)) 1181 svm_set_intercept(svm, INTERCEPT_INVPCID); 1182 else 1183 svm_clr_intercept(svm, INTERCEPT_INVPCID); 1184 } 1185 1186 if (kvm_cpu_cap_has(X86_FEATURE_RDTSCP)) { 1187 if (guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP)) 1188 svm_clr_intercept(svm, INTERCEPT_RDTSCP); 1189 else 1190 svm_set_intercept(svm, INTERCEPT_RDTSCP); 1191 } 1192 } 1193 1194 static inline void init_vmcb_after_set_cpuid(struct kvm_vcpu *vcpu) 1195 { 1196 struct vcpu_svm *svm = to_svm(vcpu); 1197 1198 if (guest_cpuid_is_intel(vcpu)) { 1199 /* 1200 * We must intercept SYSENTER_EIP and SYSENTER_ESP 1201 * accesses because the processor only stores 32 bits. 1202 * For the same reason we cannot use virtual VMLOAD/VMSAVE. 1203 */ 1204 svm_set_intercept(svm, INTERCEPT_VMLOAD); 1205 svm_set_intercept(svm, INTERCEPT_VMSAVE); 1206 svm->vmcb->control.virt_ext &= ~VIRTUAL_VMLOAD_VMSAVE_ENABLE_MASK; 1207 1208 set_msr_interception(vcpu, svm->msrpm, MSR_IA32_SYSENTER_EIP, 0, 0); 1209 set_msr_interception(vcpu, svm->msrpm, MSR_IA32_SYSENTER_ESP, 0, 0); 1210 } else { 1211 /* 1212 * If hardware supports Virtual VMLOAD VMSAVE then enable it 1213 * in VMCB and clear intercepts to avoid #VMEXIT. 1214 */ 1215 if (vls) { 1216 svm_clr_intercept(svm, INTERCEPT_VMLOAD); 1217 svm_clr_intercept(svm, INTERCEPT_VMSAVE); 1218 svm->vmcb->control.virt_ext |= VIRTUAL_VMLOAD_VMSAVE_ENABLE_MASK; 1219 } 1220 /* No need to intercept these MSRs */ 1221 set_msr_interception(vcpu, svm->msrpm, MSR_IA32_SYSENTER_EIP, 1, 1); 1222 set_msr_interception(vcpu, svm->msrpm, MSR_IA32_SYSENTER_ESP, 1, 1); 1223 } 1224 } 1225 1226 static void init_vmcb(struct kvm_vcpu *vcpu) 1227 { 1228 struct vcpu_svm *svm = to_svm(vcpu); 1229 struct vmcb *vmcb = svm->vmcb01.ptr; 1230 struct vmcb_control_area *control = &vmcb->control; 1231 struct vmcb_save_area *save = &vmcb->save; 1232 1233 svm_set_intercept(svm, INTERCEPT_CR0_READ); 1234 svm_set_intercept(svm, INTERCEPT_CR3_READ); 1235 svm_set_intercept(svm, INTERCEPT_CR4_READ); 1236 svm_set_intercept(svm, INTERCEPT_CR0_WRITE); 1237 svm_set_intercept(svm, INTERCEPT_CR3_WRITE); 1238 svm_set_intercept(svm, INTERCEPT_CR4_WRITE); 1239 if (!kvm_vcpu_apicv_active(vcpu)) 1240 svm_set_intercept(svm, INTERCEPT_CR8_WRITE); 1241 1242 set_dr_intercepts(svm); 1243 1244 set_exception_intercept(svm, PF_VECTOR); 1245 set_exception_intercept(svm, UD_VECTOR); 1246 set_exception_intercept(svm, MC_VECTOR); 1247 set_exception_intercept(svm, AC_VECTOR); 1248 set_exception_intercept(svm, DB_VECTOR); 1249 /* 1250 * Guest access to VMware backdoor ports could legitimately 1251 * trigger #GP because of TSS I/O permission bitmap. 1252 * We intercept those #GP and allow access to them anyway 1253 * as VMware does. 1254 */ 1255 if (enable_vmware_backdoor) 1256 set_exception_intercept(svm, GP_VECTOR); 1257 1258 svm_set_intercept(svm, INTERCEPT_INTR); 1259 svm_set_intercept(svm, INTERCEPT_NMI); 1260 1261 if (intercept_smi) 1262 svm_set_intercept(svm, INTERCEPT_SMI); 1263 1264 svm_set_intercept(svm, INTERCEPT_SELECTIVE_CR0); 1265 svm_set_intercept(svm, INTERCEPT_RDPMC); 1266 svm_set_intercept(svm, INTERCEPT_CPUID); 1267 svm_set_intercept(svm, INTERCEPT_INVD); 1268 svm_set_intercept(svm, INTERCEPT_INVLPG); 1269 svm_set_intercept(svm, INTERCEPT_INVLPGA); 1270 svm_set_intercept(svm, INTERCEPT_IOIO_PROT); 1271 svm_set_intercept(svm, INTERCEPT_MSR_PROT); 1272 svm_set_intercept(svm, INTERCEPT_TASK_SWITCH); 1273 svm_set_intercept(svm, INTERCEPT_SHUTDOWN); 1274 svm_set_intercept(svm, INTERCEPT_VMRUN); 1275 svm_set_intercept(svm, INTERCEPT_VMMCALL); 1276 svm_set_intercept(svm, INTERCEPT_VMLOAD); 1277 svm_set_intercept(svm, INTERCEPT_VMSAVE); 1278 svm_set_intercept(svm, INTERCEPT_STGI); 1279 svm_set_intercept(svm, INTERCEPT_CLGI); 1280 svm_set_intercept(svm, INTERCEPT_SKINIT); 1281 svm_set_intercept(svm, INTERCEPT_WBINVD); 1282 svm_set_intercept(svm, INTERCEPT_XSETBV); 1283 svm_set_intercept(svm, INTERCEPT_RDPRU); 1284 svm_set_intercept(svm, INTERCEPT_RSM); 1285 1286 if (!kvm_mwait_in_guest(vcpu->kvm)) { 1287 svm_set_intercept(svm, INTERCEPT_MONITOR); 1288 svm_set_intercept(svm, INTERCEPT_MWAIT); 1289 } 1290 1291 if (!kvm_hlt_in_guest(vcpu->kvm)) 1292 svm_set_intercept(svm, INTERCEPT_HLT); 1293 1294 control->iopm_base_pa = __sme_set(iopm_base); 1295 control->msrpm_base_pa = __sme_set(__pa(svm->msrpm)); 1296 control->int_ctl = V_INTR_MASKING_MASK; 1297 1298 init_seg(&save->es); 1299 init_seg(&save->ss); 1300 init_seg(&save->ds); 1301 init_seg(&save->fs); 1302 init_seg(&save->gs); 1303 1304 save->cs.selector = 0xf000; 1305 save->cs.base = 0xffff0000; 1306 /* Executable/Readable Code Segment */ 1307 save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK | 1308 SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK; 1309 save->cs.limit = 0xffff; 1310 1311 save->gdtr.base = 0; 1312 save->gdtr.limit = 0xffff; 1313 save->idtr.base = 0; 1314 save->idtr.limit = 0xffff; 1315 1316 init_sys_seg(&save->ldtr, SEG_TYPE_LDT); 1317 init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16); 1318 1319 if (npt_enabled) { 1320 /* Setup VMCB for Nested Paging */ 1321 control->nested_ctl |= SVM_NESTED_CTL_NP_ENABLE; 1322 svm_clr_intercept(svm, INTERCEPT_INVLPG); 1323 clr_exception_intercept(svm, PF_VECTOR); 1324 svm_clr_intercept(svm, INTERCEPT_CR3_READ); 1325 svm_clr_intercept(svm, INTERCEPT_CR3_WRITE); 1326 save->g_pat = vcpu->arch.pat; 1327 save->cr3 = 0; 1328 } 1329 svm->current_vmcb->asid_generation = 0; 1330 svm->asid = 0; 1331 1332 svm->nested.vmcb12_gpa = INVALID_GPA; 1333 svm->nested.last_vmcb12_gpa = INVALID_GPA; 1334 1335 if (!kvm_pause_in_guest(vcpu->kvm)) { 1336 control->pause_filter_count = pause_filter_count; 1337 if (pause_filter_thresh) 1338 control->pause_filter_thresh = pause_filter_thresh; 1339 svm_set_intercept(svm, INTERCEPT_PAUSE); 1340 } else { 1341 svm_clr_intercept(svm, INTERCEPT_PAUSE); 1342 } 1343 1344 svm_recalc_instruction_intercepts(vcpu, svm); 1345 1346 /* 1347 * If the host supports V_SPEC_CTRL then disable the interception 1348 * of MSR_IA32_SPEC_CTRL. 1349 */ 1350 if (boot_cpu_has(X86_FEATURE_V_SPEC_CTRL)) 1351 set_msr_interception(vcpu, svm->msrpm, MSR_IA32_SPEC_CTRL, 1, 1); 1352 1353 if (kvm_vcpu_apicv_active(vcpu)) 1354 avic_init_vmcb(svm, vmcb); 1355 1356 if (vnmi) 1357 svm->vmcb->control.int_ctl |= V_NMI_ENABLE_MASK; 1358 1359 if (vgif) { 1360 svm_clr_intercept(svm, INTERCEPT_STGI); 1361 svm_clr_intercept(svm, INTERCEPT_CLGI); 1362 svm->vmcb->control.int_ctl |= V_GIF_ENABLE_MASK; 1363 } 1364 1365 if (sev_guest(vcpu->kvm)) 1366 sev_init_vmcb(svm); 1367 1368 svm_hv_init_vmcb(vmcb); 1369 init_vmcb_after_set_cpuid(vcpu); 1370 1371 vmcb_mark_all_dirty(vmcb); 1372 1373 enable_gif(svm); 1374 } 1375 1376 static void __svm_vcpu_reset(struct kvm_vcpu *vcpu) 1377 { 1378 struct vcpu_svm *svm = to_svm(vcpu); 1379 1380 svm_vcpu_init_msrpm(vcpu, svm->msrpm); 1381 1382 svm_init_osvw(vcpu); 1383 vcpu->arch.microcode_version = 0x01000065; 1384 svm->tsc_ratio_msr = kvm_caps.default_tsc_scaling_ratio; 1385 1386 svm->nmi_masked = false; 1387 svm->awaiting_iret_completion = false; 1388 1389 if (sev_es_guest(vcpu->kvm)) 1390 sev_es_vcpu_reset(svm); 1391 } 1392 1393 static void svm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event) 1394 { 1395 struct vcpu_svm *svm = to_svm(vcpu); 1396 1397 svm->spec_ctrl = 0; 1398 svm->virt_spec_ctrl = 0; 1399 1400 init_vmcb(vcpu); 1401 1402 if (!init_event) 1403 __svm_vcpu_reset(vcpu); 1404 } 1405 1406 void svm_switch_vmcb(struct vcpu_svm *svm, struct kvm_vmcb_info *target_vmcb) 1407 { 1408 svm->current_vmcb = target_vmcb; 1409 svm->vmcb = target_vmcb->ptr; 1410 } 1411 1412 static int svm_vcpu_create(struct kvm_vcpu *vcpu) 1413 { 1414 struct vcpu_svm *svm; 1415 struct page *vmcb01_page; 1416 struct page *vmsa_page = NULL; 1417 int err; 1418 1419 BUILD_BUG_ON(offsetof(struct vcpu_svm, vcpu) != 0); 1420 svm = to_svm(vcpu); 1421 1422 err = -ENOMEM; 1423 vmcb01_page = alloc_page(GFP_KERNEL_ACCOUNT | __GFP_ZERO); 1424 if (!vmcb01_page) 1425 goto out; 1426 1427 if (sev_es_guest(vcpu->kvm)) { 1428 /* 1429 * SEV-ES guests require a separate VMSA page used to contain 1430 * the encrypted register state of the guest. 1431 */ 1432 vmsa_page = alloc_page(GFP_KERNEL_ACCOUNT | __GFP_ZERO); 1433 if (!vmsa_page) 1434 goto error_free_vmcb_page; 1435 1436 /* 1437 * SEV-ES guests maintain an encrypted version of their FPU 1438 * state which is restored and saved on VMRUN and VMEXIT. 1439 * Mark vcpu->arch.guest_fpu->fpstate as scratch so it won't 1440 * do xsave/xrstor on it. 1441 */ 1442 fpstate_set_confidential(&vcpu->arch.guest_fpu); 1443 } 1444 1445 err = avic_init_vcpu(svm); 1446 if (err) 1447 goto error_free_vmsa_page; 1448 1449 svm->msrpm = svm_vcpu_alloc_msrpm(); 1450 if (!svm->msrpm) { 1451 err = -ENOMEM; 1452 goto error_free_vmsa_page; 1453 } 1454 1455 svm->x2avic_msrs_intercepted = true; 1456 1457 svm->vmcb01.ptr = page_address(vmcb01_page); 1458 svm->vmcb01.pa = __sme_set(page_to_pfn(vmcb01_page) << PAGE_SHIFT); 1459 svm_switch_vmcb(svm, &svm->vmcb01); 1460 1461 if (vmsa_page) 1462 svm->sev_es.vmsa = page_address(vmsa_page); 1463 1464 svm->guest_state_loaded = false; 1465 1466 return 0; 1467 1468 error_free_vmsa_page: 1469 if (vmsa_page) 1470 __free_page(vmsa_page); 1471 error_free_vmcb_page: 1472 __free_page(vmcb01_page); 1473 out: 1474 return err; 1475 } 1476 1477 static void svm_clear_current_vmcb(struct vmcb *vmcb) 1478 { 1479 int i; 1480 1481 for_each_online_cpu(i) 1482 cmpxchg(per_cpu_ptr(&svm_data.current_vmcb, i), vmcb, NULL); 1483 } 1484 1485 static void svm_vcpu_free(struct kvm_vcpu *vcpu) 1486 { 1487 struct vcpu_svm *svm = to_svm(vcpu); 1488 1489 /* 1490 * The vmcb page can be recycled, causing a false negative in 1491 * svm_vcpu_load(). So, ensure that no logical CPU has this 1492 * vmcb page recorded as its current vmcb. 1493 */ 1494 svm_clear_current_vmcb(svm->vmcb); 1495 1496 svm_leave_nested(vcpu); 1497 svm_free_nested(svm); 1498 1499 sev_free_vcpu(vcpu); 1500 1501 __free_page(pfn_to_page(__sme_clr(svm->vmcb01.pa) >> PAGE_SHIFT)); 1502 __free_pages(virt_to_page(svm->msrpm), get_order(MSRPM_SIZE)); 1503 } 1504 1505 static void svm_prepare_switch_to_guest(struct kvm_vcpu *vcpu) 1506 { 1507 struct vcpu_svm *svm = to_svm(vcpu); 1508 struct svm_cpu_data *sd = per_cpu_ptr(&svm_data, vcpu->cpu); 1509 1510 if (sev_es_guest(vcpu->kvm)) 1511 sev_es_unmap_ghcb(svm); 1512 1513 if (svm->guest_state_loaded) 1514 return; 1515 1516 /* 1517 * Save additional host state that will be restored on VMEXIT (sev-es) 1518 * or subsequent vmload of host save area. 1519 */ 1520 vmsave(sd->save_area_pa); 1521 if (sev_es_guest(vcpu->kvm)) { 1522 struct sev_es_save_area *hostsa; 1523 hostsa = (struct sev_es_save_area *)(page_address(sd->save_area) + 0x400); 1524 1525 sev_es_prepare_switch_to_guest(hostsa); 1526 } 1527 1528 if (tsc_scaling) 1529 __svm_write_tsc_multiplier(vcpu->arch.tsc_scaling_ratio); 1530 1531 /* 1532 * TSC_AUX is always virtualized for SEV-ES guests when the feature is 1533 * available. The user return MSR support is not required in this case 1534 * because TSC_AUX is restored on #VMEXIT from the host save area 1535 * (which has been initialized in svm_hardware_enable()). 1536 */ 1537 if (likely(tsc_aux_uret_slot >= 0) && 1538 (!boot_cpu_has(X86_FEATURE_V_TSC_AUX) || !sev_es_guest(vcpu->kvm))) 1539 kvm_set_user_return_msr(tsc_aux_uret_slot, svm->tsc_aux, -1ull); 1540 1541 svm->guest_state_loaded = true; 1542 } 1543 1544 static void svm_prepare_host_switch(struct kvm_vcpu *vcpu) 1545 { 1546 to_svm(vcpu)->guest_state_loaded = false; 1547 } 1548 1549 static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu) 1550 { 1551 struct vcpu_svm *svm = to_svm(vcpu); 1552 struct svm_cpu_data *sd = per_cpu_ptr(&svm_data, cpu); 1553 1554 if (sd->current_vmcb != svm->vmcb) { 1555 sd->current_vmcb = svm->vmcb; 1556 1557 if (!cpu_feature_enabled(X86_FEATURE_IBPB_ON_VMEXIT)) 1558 indirect_branch_prediction_barrier(); 1559 } 1560 if (kvm_vcpu_apicv_active(vcpu)) 1561 avic_vcpu_load(vcpu, cpu); 1562 } 1563 1564 static void svm_vcpu_put(struct kvm_vcpu *vcpu) 1565 { 1566 if (kvm_vcpu_apicv_active(vcpu)) 1567 avic_vcpu_put(vcpu); 1568 1569 svm_prepare_host_switch(vcpu); 1570 1571 ++vcpu->stat.host_state_reload; 1572 } 1573 1574 static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu) 1575 { 1576 struct vcpu_svm *svm = to_svm(vcpu); 1577 unsigned long rflags = svm->vmcb->save.rflags; 1578 1579 if (svm->nmi_singlestep) { 1580 /* Hide our flags if they were not set by the guest */ 1581 if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_TF)) 1582 rflags &= ~X86_EFLAGS_TF; 1583 if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_RF)) 1584 rflags &= ~X86_EFLAGS_RF; 1585 } 1586 return rflags; 1587 } 1588 1589 static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags) 1590 { 1591 if (to_svm(vcpu)->nmi_singlestep) 1592 rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF); 1593 1594 /* 1595 * Any change of EFLAGS.VM is accompanied by a reload of SS 1596 * (caused by either a task switch or an inter-privilege IRET), 1597 * so we do not need to update the CPL here. 1598 */ 1599 to_svm(vcpu)->vmcb->save.rflags = rflags; 1600 } 1601 1602 static bool svm_get_if_flag(struct kvm_vcpu *vcpu) 1603 { 1604 struct vmcb *vmcb = to_svm(vcpu)->vmcb; 1605 1606 return sev_es_guest(vcpu->kvm) 1607 ? vmcb->control.int_state & SVM_GUEST_INTERRUPT_MASK 1608 : kvm_get_rflags(vcpu) & X86_EFLAGS_IF; 1609 } 1610 1611 static void svm_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg) 1612 { 1613 kvm_register_mark_available(vcpu, reg); 1614 1615 switch (reg) { 1616 case VCPU_EXREG_PDPTR: 1617 /* 1618 * When !npt_enabled, mmu->pdptrs[] is already available since 1619 * it is always updated per SDM when moving to CRs. 1620 */ 1621 if (npt_enabled) 1622 load_pdptrs(vcpu, kvm_read_cr3(vcpu)); 1623 break; 1624 default: 1625 KVM_BUG_ON(1, vcpu->kvm); 1626 } 1627 } 1628 1629 static void svm_set_vintr(struct vcpu_svm *svm) 1630 { 1631 struct vmcb_control_area *control; 1632 1633 /* 1634 * The following fields are ignored when AVIC is enabled 1635 */ 1636 WARN_ON(kvm_vcpu_apicv_activated(&svm->vcpu)); 1637 1638 svm_set_intercept(svm, INTERCEPT_VINTR); 1639 1640 /* 1641 * Recalculating intercepts may have cleared the VINTR intercept. If 1642 * V_INTR_MASKING is enabled in vmcb12, then the effective RFLAGS.IF 1643 * for L1 physical interrupts is L1's RFLAGS.IF at the time of VMRUN. 1644 * Requesting an interrupt window if save.RFLAGS.IF=0 is pointless as 1645 * interrupts will never be unblocked while L2 is running. 1646 */ 1647 if (!svm_is_intercept(svm, INTERCEPT_VINTR)) 1648 return; 1649 1650 /* 1651 * This is just a dummy VINTR to actually cause a vmexit to happen. 1652 * Actual injection of virtual interrupts happens through EVENTINJ. 1653 */ 1654 control = &svm->vmcb->control; 1655 control->int_vector = 0x0; 1656 control->int_ctl &= ~V_INTR_PRIO_MASK; 1657 control->int_ctl |= V_IRQ_MASK | 1658 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT); 1659 vmcb_mark_dirty(svm->vmcb, VMCB_INTR); 1660 } 1661 1662 static void svm_clear_vintr(struct vcpu_svm *svm) 1663 { 1664 svm_clr_intercept(svm, INTERCEPT_VINTR); 1665 1666 /* Drop int_ctl fields related to VINTR injection. */ 1667 svm->vmcb->control.int_ctl &= ~V_IRQ_INJECTION_BITS_MASK; 1668 if (is_guest_mode(&svm->vcpu)) { 1669 svm->vmcb01.ptr->control.int_ctl &= ~V_IRQ_INJECTION_BITS_MASK; 1670 1671 WARN_ON((svm->vmcb->control.int_ctl & V_TPR_MASK) != 1672 (svm->nested.ctl.int_ctl & V_TPR_MASK)); 1673 1674 svm->vmcb->control.int_ctl |= svm->nested.ctl.int_ctl & 1675 V_IRQ_INJECTION_BITS_MASK; 1676 1677 svm->vmcb->control.int_vector = svm->nested.ctl.int_vector; 1678 } 1679 1680 vmcb_mark_dirty(svm->vmcb, VMCB_INTR); 1681 } 1682 1683 static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg) 1684 { 1685 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save; 1686 struct vmcb_save_area *save01 = &to_svm(vcpu)->vmcb01.ptr->save; 1687 1688 switch (seg) { 1689 case VCPU_SREG_CS: return &save->cs; 1690 case VCPU_SREG_DS: return &save->ds; 1691 case VCPU_SREG_ES: return &save->es; 1692 case VCPU_SREG_FS: return &save01->fs; 1693 case VCPU_SREG_GS: return &save01->gs; 1694 case VCPU_SREG_SS: return &save->ss; 1695 case VCPU_SREG_TR: return &save01->tr; 1696 case VCPU_SREG_LDTR: return &save01->ldtr; 1697 } 1698 BUG(); 1699 return NULL; 1700 } 1701 1702 static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg) 1703 { 1704 struct vmcb_seg *s = svm_seg(vcpu, seg); 1705 1706 return s->base; 1707 } 1708 1709 static void svm_get_segment(struct kvm_vcpu *vcpu, 1710 struct kvm_segment *var, int seg) 1711 { 1712 struct vmcb_seg *s = svm_seg(vcpu, seg); 1713 1714 var->base = s->base; 1715 var->limit = s->limit; 1716 var->selector = s->selector; 1717 var->type = s->attrib & SVM_SELECTOR_TYPE_MASK; 1718 var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1; 1719 var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3; 1720 var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1; 1721 var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1; 1722 var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1; 1723 var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1; 1724 1725 /* 1726 * AMD CPUs circa 2014 track the G bit for all segments except CS. 1727 * However, the SVM spec states that the G bit is not observed by the 1728 * CPU, and some VMware virtual CPUs drop the G bit for all segments. 1729 * So let's synthesize a legal G bit for all segments, this helps 1730 * running KVM nested. It also helps cross-vendor migration, because 1731 * Intel's vmentry has a check on the 'G' bit. 1732 */ 1733 var->g = s->limit > 0xfffff; 1734 1735 /* 1736 * AMD's VMCB does not have an explicit unusable field, so emulate it 1737 * for cross vendor migration purposes by "not present" 1738 */ 1739 var->unusable = !var->present; 1740 1741 switch (seg) { 1742 case VCPU_SREG_TR: 1743 /* 1744 * Work around a bug where the busy flag in the tr selector 1745 * isn't exposed 1746 */ 1747 var->type |= 0x2; 1748 break; 1749 case VCPU_SREG_DS: 1750 case VCPU_SREG_ES: 1751 case VCPU_SREG_FS: 1752 case VCPU_SREG_GS: 1753 /* 1754 * The accessed bit must always be set in the segment 1755 * descriptor cache, although it can be cleared in the 1756 * descriptor, the cached bit always remains at 1. Since 1757 * Intel has a check on this, set it here to support 1758 * cross-vendor migration. 1759 */ 1760 if (!var->unusable) 1761 var->type |= 0x1; 1762 break; 1763 case VCPU_SREG_SS: 1764 /* 1765 * On AMD CPUs sometimes the DB bit in the segment 1766 * descriptor is left as 1, although the whole segment has 1767 * been made unusable. Clear it here to pass an Intel VMX 1768 * entry check when cross vendor migrating. 1769 */ 1770 if (var->unusable) 1771 var->db = 0; 1772 /* This is symmetric with svm_set_segment() */ 1773 var->dpl = to_svm(vcpu)->vmcb->save.cpl; 1774 break; 1775 } 1776 } 1777 1778 static int svm_get_cpl(struct kvm_vcpu *vcpu) 1779 { 1780 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save; 1781 1782 return save->cpl; 1783 } 1784 1785 static void svm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l) 1786 { 1787 struct kvm_segment cs; 1788 1789 svm_get_segment(vcpu, &cs, VCPU_SREG_CS); 1790 *db = cs.db; 1791 *l = cs.l; 1792 } 1793 1794 static void svm_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt) 1795 { 1796 struct vcpu_svm *svm = to_svm(vcpu); 1797 1798 dt->size = svm->vmcb->save.idtr.limit; 1799 dt->address = svm->vmcb->save.idtr.base; 1800 } 1801 1802 static void svm_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt) 1803 { 1804 struct vcpu_svm *svm = to_svm(vcpu); 1805 1806 svm->vmcb->save.idtr.limit = dt->size; 1807 svm->vmcb->save.idtr.base = dt->address ; 1808 vmcb_mark_dirty(svm->vmcb, VMCB_DT); 1809 } 1810 1811 static void svm_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt) 1812 { 1813 struct vcpu_svm *svm = to_svm(vcpu); 1814 1815 dt->size = svm->vmcb->save.gdtr.limit; 1816 dt->address = svm->vmcb->save.gdtr.base; 1817 } 1818 1819 static void svm_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt) 1820 { 1821 struct vcpu_svm *svm = to_svm(vcpu); 1822 1823 svm->vmcb->save.gdtr.limit = dt->size; 1824 svm->vmcb->save.gdtr.base = dt->address ; 1825 vmcb_mark_dirty(svm->vmcb, VMCB_DT); 1826 } 1827 1828 static void sev_post_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3) 1829 { 1830 struct vcpu_svm *svm = to_svm(vcpu); 1831 1832 /* 1833 * For guests that don't set guest_state_protected, the cr3 update is 1834 * handled via kvm_mmu_load() while entering the guest. For guests 1835 * that do (SEV-ES/SEV-SNP), the cr3 update needs to be written to 1836 * VMCB save area now, since the save area will become the initial 1837 * contents of the VMSA, and future VMCB save area updates won't be 1838 * seen. 1839 */ 1840 if (sev_es_guest(vcpu->kvm)) { 1841 svm->vmcb->save.cr3 = cr3; 1842 vmcb_mark_dirty(svm->vmcb, VMCB_CR); 1843 } 1844 } 1845 1846 static bool svm_is_valid_cr0(struct kvm_vcpu *vcpu, unsigned long cr0) 1847 { 1848 return true; 1849 } 1850 1851 void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0) 1852 { 1853 struct vcpu_svm *svm = to_svm(vcpu); 1854 u64 hcr0 = cr0; 1855 bool old_paging = is_paging(vcpu); 1856 1857 #ifdef CONFIG_X86_64 1858 if (vcpu->arch.efer & EFER_LME && !vcpu->arch.guest_state_protected) { 1859 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) { 1860 vcpu->arch.efer |= EFER_LMA; 1861 svm->vmcb->save.efer |= EFER_LMA | EFER_LME; 1862 } 1863 1864 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) { 1865 vcpu->arch.efer &= ~EFER_LMA; 1866 svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME); 1867 } 1868 } 1869 #endif 1870 vcpu->arch.cr0 = cr0; 1871 1872 if (!npt_enabled) { 1873 hcr0 |= X86_CR0_PG | X86_CR0_WP; 1874 if (old_paging != is_paging(vcpu)) 1875 svm_set_cr4(vcpu, kvm_read_cr4(vcpu)); 1876 } 1877 1878 /* 1879 * re-enable caching here because the QEMU bios 1880 * does not do it - this results in some delay at 1881 * reboot 1882 */ 1883 if (kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED)) 1884 hcr0 &= ~(X86_CR0_CD | X86_CR0_NW); 1885 1886 svm->vmcb->save.cr0 = hcr0; 1887 vmcb_mark_dirty(svm->vmcb, VMCB_CR); 1888 1889 /* 1890 * SEV-ES guests must always keep the CR intercepts cleared. CR 1891 * tracking is done using the CR write traps. 1892 */ 1893 if (sev_es_guest(vcpu->kvm)) 1894 return; 1895 1896 if (hcr0 == cr0) { 1897 /* Selective CR0 write remains on. */ 1898 svm_clr_intercept(svm, INTERCEPT_CR0_READ); 1899 svm_clr_intercept(svm, INTERCEPT_CR0_WRITE); 1900 } else { 1901 svm_set_intercept(svm, INTERCEPT_CR0_READ); 1902 svm_set_intercept(svm, INTERCEPT_CR0_WRITE); 1903 } 1904 } 1905 1906 static bool svm_is_valid_cr4(struct kvm_vcpu *vcpu, unsigned long cr4) 1907 { 1908 return true; 1909 } 1910 1911 void svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4) 1912 { 1913 unsigned long host_cr4_mce = cr4_read_shadow() & X86_CR4_MCE; 1914 unsigned long old_cr4 = vcpu->arch.cr4; 1915 1916 if (npt_enabled && ((old_cr4 ^ cr4) & X86_CR4_PGE)) 1917 svm_flush_tlb_current(vcpu); 1918 1919 vcpu->arch.cr4 = cr4; 1920 if (!npt_enabled) { 1921 cr4 |= X86_CR4_PAE; 1922 1923 if (!is_paging(vcpu)) 1924 cr4 &= ~(X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE); 1925 } 1926 cr4 |= host_cr4_mce; 1927 to_svm(vcpu)->vmcb->save.cr4 = cr4; 1928 vmcb_mark_dirty(to_svm(vcpu)->vmcb, VMCB_CR); 1929 1930 if ((cr4 ^ old_cr4) & (X86_CR4_OSXSAVE | X86_CR4_PKE)) 1931 kvm_update_cpuid_runtime(vcpu); 1932 } 1933 1934 static void svm_set_segment(struct kvm_vcpu *vcpu, 1935 struct kvm_segment *var, int seg) 1936 { 1937 struct vcpu_svm *svm = to_svm(vcpu); 1938 struct vmcb_seg *s = svm_seg(vcpu, seg); 1939 1940 s->base = var->base; 1941 s->limit = var->limit; 1942 s->selector = var->selector; 1943 s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK); 1944 s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT; 1945 s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT; 1946 s->attrib |= ((var->present & 1) && !var->unusable) << SVM_SELECTOR_P_SHIFT; 1947 s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT; 1948 s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT; 1949 s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT; 1950 s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT; 1951 1952 /* 1953 * This is always accurate, except if SYSRET returned to a segment 1954 * with SS.DPL != 3. Intel does not have this quirk, and always 1955 * forces SS.DPL to 3 on sysret, so we ignore that case; fixing it 1956 * would entail passing the CPL to userspace and back. 1957 */ 1958 if (seg == VCPU_SREG_SS) 1959 /* This is symmetric with svm_get_segment() */ 1960 svm->vmcb->save.cpl = (var->dpl & 3); 1961 1962 vmcb_mark_dirty(svm->vmcb, VMCB_SEG); 1963 } 1964 1965 static void svm_update_exception_bitmap(struct kvm_vcpu *vcpu) 1966 { 1967 struct vcpu_svm *svm = to_svm(vcpu); 1968 1969 clr_exception_intercept(svm, BP_VECTOR); 1970 1971 if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) { 1972 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP) 1973 set_exception_intercept(svm, BP_VECTOR); 1974 } 1975 } 1976 1977 static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *sd) 1978 { 1979 if (sd->next_asid > sd->max_asid) { 1980 ++sd->asid_generation; 1981 sd->next_asid = sd->min_asid; 1982 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID; 1983 vmcb_mark_dirty(svm->vmcb, VMCB_ASID); 1984 } 1985 1986 svm->current_vmcb->asid_generation = sd->asid_generation; 1987 svm->asid = sd->next_asid++; 1988 } 1989 1990 static void svm_set_dr6(struct vcpu_svm *svm, unsigned long value) 1991 { 1992 struct vmcb *vmcb = svm->vmcb; 1993 1994 if (svm->vcpu.arch.guest_state_protected) 1995 return; 1996 1997 if (unlikely(value != vmcb->save.dr6)) { 1998 vmcb->save.dr6 = value; 1999 vmcb_mark_dirty(vmcb, VMCB_DR); 2000 } 2001 } 2002 2003 static void svm_sync_dirty_debug_regs(struct kvm_vcpu *vcpu) 2004 { 2005 struct vcpu_svm *svm = to_svm(vcpu); 2006 2007 if (WARN_ON_ONCE(sev_es_guest(vcpu->kvm))) 2008 return; 2009 2010 get_debugreg(vcpu->arch.db[0], 0); 2011 get_debugreg(vcpu->arch.db[1], 1); 2012 get_debugreg(vcpu->arch.db[2], 2); 2013 get_debugreg(vcpu->arch.db[3], 3); 2014 /* 2015 * We cannot reset svm->vmcb->save.dr6 to DR6_ACTIVE_LOW here, 2016 * because db_interception might need it. We can do it before vmentry. 2017 */ 2018 vcpu->arch.dr6 = svm->vmcb->save.dr6; 2019 vcpu->arch.dr7 = svm->vmcb->save.dr7; 2020 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT; 2021 set_dr_intercepts(svm); 2022 } 2023 2024 static void svm_set_dr7(struct kvm_vcpu *vcpu, unsigned long value) 2025 { 2026 struct vcpu_svm *svm = to_svm(vcpu); 2027 2028 if (vcpu->arch.guest_state_protected) 2029 return; 2030 2031 svm->vmcb->save.dr7 = value; 2032 vmcb_mark_dirty(svm->vmcb, VMCB_DR); 2033 } 2034 2035 static int pf_interception(struct kvm_vcpu *vcpu) 2036 { 2037 struct vcpu_svm *svm = to_svm(vcpu); 2038 2039 u64 fault_address = svm->vmcb->control.exit_info_2; 2040 u64 error_code = svm->vmcb->control.exit_info_1; 2041 2042 return kvm_handle_page_fault(vcpu, error_code, fault_address, 2043 static_cpu_has(X86_FEATURE_DECODEASSISTS) ? 2044 svm->vmcb->control.insn_bytes : NULL, 2045 svm->vmcb->control.insn_len); 2046 } 2047 2048 static int npf_interception(struct kvm_vcpu *vcpu) 2049 { 2050 struct vcpu_svm *svm = to_svm(vcpu); 2051 2052 u64 fault_address = svm->vmcb->control.exit_info_2; 2053 u64 error_code = svm->vmcb->control.exit_info_1; 2054 2055 trace_kvm_page_fault(vcpu, fault_address, error_code); 2056 return kvm_mmu_page_fault(vcpu, fault_address, error_code, 2057 static_cpu_has(X86_FEATURE_DECODEASSISTS) ? 2058 svm->vmcb->control.insn_bytes : NULL, 2059 svm->vmcb->control.insn_len); 2060 } 2061 2062 static int db_interception(struct kvm_vcpu *vcpu) 2063 { 2064 struct kvm_run *kvm_run = vcpu->run; 2065 struct vcpu_svm *svm = to_svm(vcpu); 2066 2067 if (!(vcpu->guest_debug & 2068 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) && 2069 !svm->nmi_singlestep) { 2070 u32 payload = svm->vmcb->save.dr6 ^ DR6_ACTIVE_LOW; 2071 kvm_queue_exception_p(vcpu, DB_VECTOR, payload); 2072 return 1; 2073 } 2074 2075 if (svm->nmi_singlestep) { 2076 disable_nmi_singlestep(svm); 2077 /* Make sure we check for pending NMIs upon entry */ 2078 kvm_make_request(KVM_REQ_EVENT, vcpu); 2079 } 2080 2081 if (vcpu->guest_debug & 2082 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) { 2083 kvm_run->exit_reason = KVM_EXIT_DEBUG; 2084 kvm_run->debug.arch.dr6 = svm->vmcb->save.dr6; 2085 kvm_run->debug.arch.dr7 = svm->vmcb->save.dr7; 2086 kvm_run->debug.arch.pc = 2087 svm->vmcb->save.cs.base + svm->vmcb->save.rip; 2088 kvm_run->debug.arch.exception = DB_VECTOR; 2089 return 0; 2090 } 2091 2092 return 1; 2093 } 2094 2095 static int bp_interception(struct kvm_vcpu *vcpu) 2096 { 2097 struct vcpu_svm *svm = to_svm(vcpu); 2098 struct kvm_run *kvm_run = vcpu->run; 2099 2100 kvm_run->exit_reason = KVM_EXIT_DEBUG; 2101 kvm_run->debug.arch.pc = svm->vmcb->save.cs.base + svm->vmcb->save.rip; 2102 kvm_run->debug.arch.exception = BP_VECTOR; 2103 return 0; 2104 } 2105 2106 static int ud_interception(struct kvm_vcpu *vcpu) 2107 { 2108 return handle_ud(vcpu); 2109 } 2110 2111 static int ac_interception(struct kvm_vcpu *vcpu) 2112 { 2113 kvm_queue_exception_e(vcpu, AC_VECTOR, 0); 2114 return 1; 2115 } 2116 2117 static bool is_erratum_383(void) 2118 { 2119 int err, i; 2120 u64 value; 2121 2122 if (!erratum_383_found) 2123 return false; 2124 2125 value = native_read_msr_safe(MSR_IA32_MC0_STATUS, &err); 2126 if (err) 2127 return false; 2128 2129 /* Bit 62 may or may not be set for this mce */ 2130 value &= ~(1ULL << 62); 2131 2132 if (value != 0xb600000000010015ULL) 2133 return false; 2134 2135 /* Clear MCi_STATUS registers */ 2136 for (i = 0; i < 6; ++i) 2137 native_write_msr_safe(MSR_IA32_MCx_STATUS(i), 0, 0); 2138 2139 value = native_read_msr_safe(MSR_IA32_MCG_STATUS, &err); 2140 if (!err) { 2141 u32 low, high; 2142 2143 value &= ~(1ULL << 2); 2144 low = lower_32_bits(value); 2145 high = upper_32_bits(value); 2146 2147 native_write_msr_safe(MSR_IA32_MCG_STATUS, low, high); 2148 } 2149 2150 /* Flush tlb to evict multi-match entries */ 2151 __flush_tlb_all(); 2152 2153 return true; 2154 } 2155 2156 static void svm_handle_mce(struct kvm_vcpu *vcpu) 2157 { 2158 if (is_erratum_383()) { 2159 /* 2160 * Erratum 383 triggered. Guest state is corrupt so kill the 2161 * guest. 2162 */ 2163 pr_err("Guest triggered AMD Erratum 383\n"); 2164 2165 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); 2166 2167 return; 2168 } 2169 2170 /* 2171 * On an #MC intercept the MCE handler is not called automatically in 2172 * the host. So do it by hand here. 2173 */ 2174 kvm_machine_check(); 2175 } 2176 2177 static int mc_interception(struct kvm_vcpu *vcpu) 2178 { 2179 return 1; 2180 } 2181 2182 static int shutdown_interception(struct kvm_vcpu *vcpu) 2183 { 2184 struct kvm_run *kvm_run = vcpu->run; 2185 struct vcpu_svm *svm = to_svm(vcpu); 2186 2187 2188 /* 2189 * VMCB is undefined after a SHUTDOWN intercept. INIT the vCPU to put 2190 * the VMCB in a known good state. Unfortuately, KVM doesn't have 2191 * KVM_MP_STATE_SHUTDOWN and can't add it without potentially breaking 2192 * userspace. At a platform view, INIT is acceptable behavior as 2193 * there exist bare metal platforms that automatically INIT the CPU 2194 * in response to shutdown. 2195 * 2196 * The VM save area for SEV-ES guests has already been encrypted so it 2197 * cannot be reinitialized, i.e. synthesizing INIT is futile. 2198 */ 2199 if (!sev_es_guest(vcpu->kvm)) { 2200 clear_page(svm->vmcb); 2201 kvm_vcpu_reset(vcpu, true); 2202 } 2203 2204 kvm_run->exit_reason = KVM_EXIT_SHUTDOWN; 2205 return 0; 2206 } 2207 2208 static int io_interception(struct kvm_vcpu *vcpu) 2209 { 2210 struct vcpu_svm *svm = to_svm(vcpu); 2211 u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */ 2212 int size, in, string; 2213 unsigned port; 2214 2215 ++vcpu->stat.io_exits; 2216 string = (io_info & SVM_IOIO_STR_MASK) != 0; 2217 in = (io_info & SVM_IOIO_TYPE_MASK) != 0; 2218 port = io_info >> 16; 2219 size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT; 2220 2221 if (string) { 2222 if (sev_es_guest(vcpu->kvm)) 2223 return sev_es_string_io(svm, size, port, in); 2224 else 2225 return kvm_emulate_instruction(vcpu, 0); 2226 } 2227 2228 svm->next_rip = svm->vmcb->control.exit_info_2; 2229 2230 return kvm_fast_pio(vcpu, size, port, in); 2231 } 2232 2233 static int nmi_interception(struct kvm_vcpu *vcpu) 2234 { 2235 return 1; 2236 } 2237 2238 static int smi_interception(struct kvm_vcpu *vcpu) 2239 { 2240 return 1; 2241 } 2242 2243 static int intr_interception(struct kvm_vcpu *vcpu) 2244 { 2245 ++vcpu->stat.irq_exits; 2246 return 1; 2247 } 2248 2249 static int vmload_vmsave_interception(struct kvm_vcpu *vcpu, bool vmload) 2250 { 2251 struct vcpu_svm *svm = to_svm(vcpu); 2252 struct vmcb *vmcb12; 2253 struct kvm_host_map map; 2254 int ret; 2255 2256 if (nested_svm_check_permissions(vcpu)) 2257 return 1; 2258 2259 ret = kvm_vcpu_map(vcpu, gpa_to_gfn(svm->vmcb->save.rax), &map); 2260 if (ret) { 2261 if (ret == -EINVAL) 2262 kvm_inject_gp(vcpu, 0); 2263 return 1; 2264 } 2265 2266 vmcb12 = map.hva; 2267 2268 ret = kvm_skip_emulated_instruction(vcpu); 2269 2270 if (vmload) { 2271 svm_copy_vmloadsave_state(svm->vmcb, vmcb12); 2272 svm->sysenter_eip_hi = 0; 2273 svm->sysenter_esp_hi = 0; 2274 } else { 2275 svm_copy_vmloadsave_state(vmcb12, svm->vmcb); 2276 } 2277 2278 kvm_vcpu_unmap(vcpu, &map, true); 2279 2280 return ret; 2281 } 2282 2283 static int vmload_interception(struct kvm_vcpu *vcpu) 2284 { 2285 return vmload_vmsave_interception(vcpu, true); 2286 } 2287 2288 static int vmsave_interception(struct kvm_vcpu *vcpu) 2289 { 2290 return vmload_vmsave_interception(vcpu, false); 2291 } 2292 2293 static int vmrun_interception(struct kvm_vcpu *vcpu) 2294 { 2295 if (nested_svm_check_permissions(vcpu)) 2296 return 1; 2297 2298 return nested_svm_vmrun(vcpu); 2299 } 2300 2301 enum { 2302 NONE_SVM_INSTR, 2303 SVM_INSTR_VMRUN, 2304 SVM_INSTR_VMLOAD, 2305 SVM_INSTR_VMSAVE, 2306 }; 2307 2308 /* Return NONE_SVM_INSTR if not SVM instrs, otherwise return decode result */ 2309 static int svm_instr_opcode(struct kvm_vcpu *vcpu) 2310 { 2311 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt; 2312 2313 if (ctxt->b != 0x1 || ctxt->opcode_len != 2) 2314 return NONE_SVM_INSTR; 2315 2316 switch (ctxt->modrm) { 2317 case 0xd8: /* VMRUN */ 2318 return SVM_INSTR_VMRUN; 2319 case 0xda: /* VMLOAD */ 2320 return SVM_INSTR_VMLOAD; 2321 case 0xdb: /* VMSAVE */ 2322 return SVM_INSTR_VMSAVE; 2323 default: 2324 break; 2325 } 2326 2327 return NONE_SVM_INSTR; 2328 } 2329 2330 static int emulate_svm_instr(struct kvm_vcpu *vcpu, int opcode) 2331 { 2332 const int guest_mode_exit_codes[] = { 2333 [SVM_INSTR_VMRUN] = SVM_EXIT_VMRUN, 2334 [SVM_INSTR_VMLOAD] = SVM_EXIT_VMLOAD, 2335 [SVM_INSTR_VMSAVE] = SVM_EXIT_VMSAVE, 2336 }; 2337 int (*const svm_instr_handlers[])(struct kvm_vcpu *vcpu) = { 2338 [SVM_INSTR_VMRUN] = vmrun_interception, 2339 [SVM_INSTR_VMLOAD] = vmload_interception, 2340 [SVM_INSTR_VMSAVE] = vmsave_interception, 2341 }; 2342 struct vcpu_svm *svm = to_svm(vcpu); 2343 int ret; 2344 2345 if (is_guest_mode(vcpu)) { 2346 /* Returns '1' or -errno on failure, '0' on success. */ 2347 ret = nested_svm_simple_vmexit(svm, guest_mode_exit_codes[opcode]); 2348 if (ret) 2349 return ret; 2350 return 1; 2351 } 2352 return svm_instr_handlers[opcode](vcpu); 2353 } 2354 2355 /* 2356 * #GP handling code. Note that #GP can be triggered under the following two 2357 * cases: 2358 * 1) SVM VM-related instructions (VMRUN/VMSAVE/VMLOAD) that trigger #GP on 2359 * some AMD CPUs when EAX of these instructions are in the reserved memory 2360 * regions (e.g. SMM memory on host). 2361 * 2) VMware backdoor 2362 */ 2363 static int gp_interception(struct kvm_vcpu *vcpu) 2364 { 2365 struct vcpu_svm *svm = to_svm(vcpu); 2366 u32 error_code = svm->vmcb->control.exit_info_1; 2367 int opcode; 2368 2369 /* Both #GP cases have zero error_code */ 2370 if (error_code) 2371 goto reinject; 2372 2373 /* Decode the instruction for usage later */ 2374 if (x86_decode_emulated_instruction(vcpu, 0, NULL, 0) != EMULATION_OK) 2375 goto reinject; 2376 2377 opcode = svm_instr_opcode(vcpu); 2378 2379 if (opcode == NONE_SVM_INSTR) { 2380 if (!enable_vmware_backdoor) 2381 goto reinject; 2382 2383 /* 2384 * VMware backdoor emulation on #GP interception only handles 2385 * IN{S}, OUT{S}, and RDPMC. 2386 */ 2387 if (!is_guest_mode(vcpu)) 2388 return kvm_emulate_instruction(vcpu, 2389 EMULTYPE_VMWARE_GP | EMULTYPE_NO_DECODE); 2390 } else { 2391 /* All SVM instructions expect page aligned RAX */ 2392 if (svm->vmcb->save.rax & ~PAGE_MASK) 2393 goto reinject; 2394 2395 return emulate_svm_instr(vcpu, opcode); 2396 } 2397 2398 reinject: 2399 kvm_queue_exception_e(vcpu, GP_VECTOR, error_code); 2400 return 1; 2401 } 2402 2403 void svm_set_gif(struct vcpu_svm *svm, bool value) 2404 { 2405 if (value) { 2406 /* 2407 * If VGIF is enabled, the STGI intercept is only added to 2408 * detect the opening of the SMI/NMI window; remove it now. 2409 * Likewise, clear the VINTR intercept, we will set it 2410 * again while processing KVM_REQ_EVENT if needed. 2411 */ 2412 if (vgif) 2413 svm_clr_intercept(svm, INTERCEPT_STGI); 2414 if (svm_is_intercept(svm, INTERCEPT_VINTR)) 2415 svm_clear_vintr(svm); 2416 2417 enable_gif(svm); 2418 if (svm->vcpu.arch.smi_pending || 2419 svm->vcpu.arch.nmi_pending || 2420 kvm_cpu_has_injectable_intr(&svm->vcpu) || 2421 kvm_apic_has_pending_init_or_sipi(&svm->vcpu)) 2422 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu); 2423 } else { 2424 disable_gif(svm); 2425 2426 /* 2427 * After a CLGI no interrupts should come. But if vGIF is 2428 * in use, we still rely on the VINTR intercept (rather than 2429 * STGI) to detect an open interrupt window. 2430 */ 2431 if (!vgif) 2432 svm_clear_vintr(svm); 2433 } 2434 } 2435 2436 static int stgi_interception(struct kvm_vcpu *vcpu) 2437 { 2438 int ret; 2439 2440 if (nested_svm_check_permissions(vcpu)) 2441 return 1; 2442 2443 ret = kvm_skip_emulated_instruction(vcpu); 2444 svm_set_gif(to_svm(vcpu), true); 2445 return ret; 2446 } 2447 2448 static int clgi_interception(struct kvm_vcpu *vcpu) 2449 { 2450 int ret; 2451 2452 if (nested_svm_check_permissions(vcpu)) 2453 return 1; 2454 2455 ret = kvm_skip_emulated_instruction(vcpu); 2456 svm_set_gif(to_svm(vcpu), false); 2457 return ret; 2458 } 2459 2460 static int invlpga_interception(struct kvm_vcpu *vcpu) 2461 { 2462 gva_t gva = kvm_rax_read(vcpu); 2463 u32 asid = kvm_rcx_read(vcpu); 2464 2465 /* FIXME: Handle an address size prefix. */ 2466 if (!is_long_mode(vcpu)) 2467 gva = (u32)gva; 2468 2469 trace_kvm_invlpga(to_svm(vcpu)->vmcb->save.rip, asid, gva); 2470 2471 /* Let's treat INVLPGA the same as INVLPG (can be optimized!) */ 2472 kvm_mmu_invlpg(vcpu, gva); 2473 2474 return kvm_skip_emulated_instruction(vcpu); 2475 } 2476 2477 static int skinit_interception(struct kvm_vcpu *vcpu) 2478 { 2479 trace_kvm_skinit(to_svm(vcpu)->vmcb->save.rip, kvm_rax_read(vcpu)); 2480 2481 kvm_queue_exception(vcpu, UD_VECTOR); 2482 return 1; 2483 } 2484 2485 static int task_switch_interception(struct kvm_vcpu *vcpu) 2486 { 2487 struct vcpu_svm *svm = to_svm(vcpu); 2488 u16 tss_selector; 2489 int reason; 2490 int int_type = svm->vmcb->control.exit_int_info & 2491 SVM_EXITINTINFO_TYPE_MASK; 2492 int int_vec = svm->vmcb->control.exit_int_info & SVM_EVTINJ_VEC_MASK; 2493 uint32_t type = 2494 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_TYPE_MASK; 2495 uint32_t idt_v = 2496 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID; 2497 bool has_error_code = false; 2498 u32 error_code = 0; 2499 2500 tss_selector = (u16)svm->vmcb->control.exit_info_1; 2501 2502 if (svm->vmcb->control.exit_info_2 & 2503 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET)) 2504 reason = TASK_SWITCH_IRET; 2505 else if (svm->vmcb->control.exit_info_2 & 2506 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP)) 2507 reason = TASK_SWITCH_JMP; 2508 else if (idt_v) 2509 reason = TASK_SWITCH_GATE; 2510 else 2511 reason = TASK_SWITCH_CALL; 2512 2513 if (reason == TASK_SWITCH_GATE) { 2514 switch (type) { 2515 case SVM_EXITINTINFO_TYPE_NMI: 2516 vcpu->arch.nmi_injected = false; 2517 break; 2518 case SVM_EXITINTINFO_TYPE_EXEPT: 2519 if (svm->vmcb->control.exit_info_2 & 2520 (1ULL << SVM_EXITINFOSHIFT_TS_HAS_ERROR_CODE)) { 2521 has_error_code = true; 2522 error_code = 2523 (u32)svm->vmcb->control.exit_info_2; 2524 } 2525 kvm_clear_exception_queue(vcpu); 2526 break; 2527 case SVM_EXITINTINFO_TYPE_INTR: 2528 case SVM_EXITINTINFO_TYPE_SOFT: 2529 kvm_clear_interrupt_queue(vcpu); 2530 break; 2531 default: 2532 break; 2533 } 2534 } 2535 2536 if (reason != TASK_SWITCH_GATE || 2537 int_type == SVM_EXITINTINFO_TYPE_SOFT || 2538 (int_type == SVM_EXITINTINFO_TYPE_EXEPT && 2539 (int_vec == OF_VECTOR || int_vec == BP_VECTOR))) { 2540 if (!svm_skip_emulated_instruction(vcpu)) 2541 return 0; 2542 } 2543 2544 if (int_type != SVM_EXITINTINFO_TYPE_SOFT) 2545 int_vec = -1; 2546 2547 return kvm_task_switch(vcpu, tss_selector, int_vec, reason, 2548 has_error_code, error_code); 2549 } 2550 2551 static void svm_clr_iret_intercept(struct vcpu_svm *svm) 2552 { 2553 if (!sev_es_guest(svm->vcpu.kvm)) 2554 svm_clr_intercept(svm, INTERCEPT_IRET); 2555 } 2556 2557 static void svm_set_iret_intercept(struct vcpu_svm *svm) 2558 { 2559 if (!sev_es_guest(svm->vcpu.kvm)) 2560 svm_set_intercept(svm, INTERCEPT_IRET); 2561 } 2562 2563 static int iret_interception(struct kvm_vcpu *vcpu) 2564 { 2565 struct vcpu_svm *svm = to_svm(vcpu); 2566 2567 WARN_ON_ONCE(sev_es_guest(vcpu->kvm)); 2568 2569 ++vcpu->stat.nmi_window_exits; 2570 svm->awaiting_iret_completion = true; 2571 2572 svm_clr_iret_intercept(svm); 2573 svm->nmi_iret_rip = kvm_rip_read(vcpu); 2574 2575 kvm_make_request(KVM_REQ_EVENT, vcpu); 2576 return 1; 2577 } 2578 2579 static int invlpg_interception(struct kvm_vcpu *vcpu) 2580 { 2581 if (!static_cpu_has(X86_FEATURE_DECODEASSISTS)) 2582 return kvm_emulate_instruction(vcpu, 0); 2583 2584 kvm_mmu_invlpg(vcpu, to_svm(vcpu)->vmcb->control.exit_info_1); 2585 return kvm_skip_emulated_instruction(vcpu); 2586 } 2587 2588 static int emulate_on_interception(struct kvm_vcpu *vcpu) 2589 { 2590 return kvm_emulate_instruction(vcpu, 0); 2591 } 2592 2593 static int rsm_interception(struct kvm_vcpu *vcpu) 2594 { 2595 return kvm_emulate_instruction_from_buffer(vcpu, rsm_ins_bytes, 2); 2596 } 2597 2598 static bool check_selective_cr0_intercepted(struct kvm_vcpu *vcpu, 2599 unsigned long val) 2600 { 2601 struct vcpu_svm *svm = to_svm(vcpu); 2602 unsigned long cr0 = vcpu->arch.cr0; 2603 bool ret = false; 2604 2605 if (!is_guest_mode(vcpu) || 2606 (!(vmcb12_is_intercept(&svm->nested.ctl, INTERCEPT_SELECTIVE_CR0)))) 2607 return false; 2608 2609 cr0 &= ~SVM_CR0_SELECTIVE_MASK; 2610 val &= ~SVM_CR0_SELECTIVE_MASK; 2611 2612 if (cr0 ^ val) { 2613 svm->vmcb->control.exit_code = SVM_EXIT_CR0_SEL_WRITE; 2614 ret = (nested_svm_exit_handled(svm) == NESTED_EXIT_DONE); 2615 } 2616 2617 return ret; 2618 } 2619 2620 #define CR_VALID (1ULL << 63) 2621 2622 static int cr_interception(struct kvm_vcpu *vcpu) 2623 { 2624 struct vcpu_svm *svm = to_svm(vcpu); 2625 int reg, cr; 2626 unsigned long val; 2627 int err; 2628 2629 if (!static_cpu_has(X86_FEATURE_DECODEASSISTS)) 2630 return emulate_on_interception(vcpu); 2631 2632 if (unlikely((svm->vmcb->control.exit_info_1 & CR_VALID) == 0)) 2633 return emulate_on_interception(vcpu); 2634 2635 reg = svm->vmcb->control.exit_info_1 & SVM_EXITINFO_REG_MASK; 2636 if (svm->vmcb->control.exit_code == SVM_EXIT_CR0_SEL_WRITE) 2637 cr = SVM_EXIT_WRITE_CR0 - SVM_EXIT_READ_CR0; 2638 else 2639 cr = svm->vmcb->control.exit_code - SVM_EXIT_READ_CR0; 2640 2641 err = 0; 2642 if (cr >= 16) { /* mov to cr */ 2643 cr -= 16; 2644 val = kvm_register_read(vcpu, reg); 2645 trace_kvm_cr_write(cr, val); 2646 switch (cr) { 2647 case 0: 2648 if (!check_selective_cr0_intercepted(vcpu, val)) 2649 err = kvm_set_cr0(vcpu, val); 2650 else 2651 return 1; 2652 2653 break; 2654 case 3: 2655 err = kvm_set_cr3(vcpu, val); 2656 break; 2657 case 4: 2658 err = kvm_set_cr4(vcpu, val); 2659 break; 2660 case 8: 2661 err = kvm_set_cr8(vcpu, val); 2662 break; 2663 default: 2664 WARN(1, "unhandled write to CR%d", cr); 2665 kvm_queue_exception(vcpu, UD_VECTOR); 2666 return 1; 2667 } 2668 } else { /* mov from cr */ 2669 switch (cr) { 2670 case 0: 2671 val = kvm_read_cr0(vcpu); 2672 break; 2673 case 2: 2674 val = vcpu->arch.cr2; 2675 break; 2676 case 3: 2677 val = kvm_read_cr3(vcpu); 2678 break; 2679 case 4: 2680 val = kvm_read_cr4(vcpu); 2681 break; 2682 case 8: 2683 val = kvm_get_cr8(vcpu); 2684 break; 2685 default: 2686 WARN(1, "unhandled read from CR%d", cr); 2687 kvm_queue_exception(vcpu, UD_VECTOR); 2688 return 1; 2689 } 2690 kvm_register_write(vcpu, reg, val); 2691 trace_kvm_cr_read(cr, val); 2692 } 2693 return kvm_complete_insn_gp(vcpu, err); 2694 } 2695 2696 static int cr_trap(struct kvm_vcpu *vcpu) 2697 { 2698 struct vcpu_svm *svm = to_svm(vcpu); 2699 unsigned long old_value, new_value; 2700 unsigned int cr; 2701 int ret = 0; 2702 2703 new_value = (unsigned long)svm->vmcb->control.exit_info_1; 2704 2705 cr = svm->vmcb->control.exit_code - SVM_EXIT_CR0_WRITE_TRAP; 2706 switch (cr) { 2707 case 0: 2708 old_value = kvm_read_cr0(vcpu); 2709 svm_set_cr0(vcpu, new_value); 2710 2711 kvm_post_set_cr0(vcpu, old_value, new_value); 2712 break; 2713 case 4: 2714 old_value = kvm_read_cr4(vcpu); 2715 svm_set_cr4(vcpu, new_value); 2716 2717 kvm_post_set_cr4(vcpu, old_value, new_value); 2718 break; 2719 case 8: 2720 ret = kvm_set_cr8(vcpu, new_value); 2721 break; 2722 default: 2723 WARN(1, "unhandled CR%d write trap", cr); 2724 kvm_queue_exception(vcpu, UD_VECTOR); 2725 return 1; 2726 } 2727 2728 return kvm_complete_insn_gp(vcpu, ret); 2729 } 2730 2731 static int dr_interception(struct kvm_vcpu *vcpu) 2732 { 2733 struct vcpu_svm *svm = to_svm(vcpu); 2734 int reg, dr; 2735 unsigned long val; 2736 int err = 0; 2737 2738 /* 2739 * SEV-ES intercepts DR7 only to disable guest debugging and the guest issues a VMGEXIT 2740 * for DR7 write only. KVM cannot change DR7 (always swapped as type 'A') so return early. 2741 */ 2742 if (sev_es_guest(vcpu->kvm)) 2743 return 1; 2744 2745 if (vcpu->guest_debug == 0) { 2746 /* 2747 * No more DR vmexits; force a reload of the debug registers 2748 * and reenter on this instruction. The next vmexit will 2749 * retrieve the full state of the debug registers. 2750 */ 2751 clr_dr_intercepts(svm); 2752 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT; 2753 return 1; 2754 } 2755 2756 if (!boot_cpu_has(X86_FEATURE_DECODEASSISTS)) 2757 return emulate_on_interception(vcpu); 2758 2759 reg = svm->vmcb->control.exit_info_1 & SVM_EXITINFO_REG_MASK; 2760 dr = svm->vmcb->control.exit_code - SVM_EXIT_READ_DR0; 2761 if (dr >= 16) { /* mov to DRn */ 2762 dr -= 16; 2763 val = kvm_register_read(vcpu, reg); 2764 err = kvm_set_dr(vcpu, dr, val); 2765 } else { 2766 kvm_get_dr(vcpu, dr, &val); 2767 kvm_register_write(vcpu, reg, val); 2768 } 2769 2770 return kvm_complete_insn_gp(vcpu, err); 2771 } 2772 2773 static int cr8_write_interception(struct kvm_vcpu *vcpu) 2774 { 2775 int r; 2776 2777 u8 cr8_prev = kvm_get_cr8(vcpu); 2778 /* instruction emulation calls kvm_set_cr8() */ 2779 r = cr_interception(vcpu); 2780 if (lapic_in_kernel(vcpu)) 2781 return r; 2782 if (cr8_prev <= kvm_get_cr8(vcpu)) 2783 return r; 2784 vcpu->run->exit_reason = KVM_EXIT_SET_TPR; 2785 return 0; 2786 } 2787 2788 static int efer_trap(struct kvm_vcpu *vcpu) 2789 { 2790 struct msr_data msr_info; 2791 int ret; 2792 2793 /* 2794 * Clear the EFER_SVME bit from EFER. The SVM code always sets this 2795 * bit in svm_set_efer(), but __kvm_valid_efer() checks it against 2796 * whether the guest has X86_FEATURE_SVM - this avoids a failure if 2797 * the guest doesn't have X86_FEATURE_SVM. 2798 */ 2799 msr_info.host_initiated = false; 2800 msr_info.index = MSR_EFER; 2801 msr_info.data = to_svm(vcpu)->vmcb->control.exit_info_1 & ~EFER_SVME; 2802 ret = kvm_set_msr_common(vcpu, &msr_info); 2803 2804 return kvm_complete_insn_gp(vcpu, ret); 2805 } 2806 2807 static int svm_get_msr_feature(struct kvm_msr_entry *msr) 2808 { 2809 msr->data = 0; 2810 2811 switch (msr->index) { 2812 case MSR_AMD64_DE_CFG: 2813 if (cpu_feature_enabled(X86_FEATURE_LFENCE_RDTSC)) 2814 msr->data |= MSR_AMD64_DE_CFG_LFENCE_SERIALIZE; 2815 break; 2816 default: 2817 return KVM_MSR_RET_INVALID; 2818 } 2819 2820 return 0; 2821 } 2822 2823 static int svm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info) 2824 { 2825 struct vcpu_svm *svm = to_svm(vcpu); 2826 2827 switch (msr_info->index) { 2828 case MSR_AMD64_TSC_RATIO: 2829 if (!msr_info->host_initiated && 2830 !guest_can_use(vcpu, X86_FEATURE_TSCRATEMSR)) 2831 return 1; 2832 msr_info->data = svm->tsc_ratio_msr; 2833 break; 2834 case MSR_STAR: 2835 msr_info->data = svm->vmcb01.ptr->save.star; 2836 break; 2837 #ifdef CONFIG_X86_64 2838 case MSR_LSTAR: 2839 msr_info->data = svm->vmcb01.ptr->save.lstar; 2840 break; 2841 case MSR_CSTAR: 2842 msr_info->data = svm->vmcb01.ptr->save.cstar; 2843 break; 2844 case MSR_KERNEL_GS_BASE: 2845 msr_info->data = svm->vmcb01.ptr->save.kernel_gs_base; 2846 break; 2847 case MSR_SYSCALL_MASK: 2848 msr_info->data = svm->vmcb01.ptr->save.sfmask; 2849 break; 2850 #endif 2851 case MSR_IA32_SYSENTER_CS: 2852 msr_info->data = svm->vmcb01.ptr->save.sysenter_cs; 2853 break; 2854 case MSR_IA32_SYSENTER_EIP: 2855 msr_info->data = (u32)svm->vmcb01.ptr->save.sysenter_eip; 2856 if (guest_cpuid_is_intel(vcpu)) 2857 msr_info->data |= (u64)svm->sysenter_eip_hi << 32; 2858 break; 2859 case MSR_IA32_SYSENTER_ESP: 2860 msr_info->data = svm->vmcb01.ptr->save.sysenter_esp; 2861 if (guest_cpuid_is_intel(vcpu)) 2862 msr_info->data |= (u64)svm->sysenter_esp_hi << 32; 2863 break; 2864 case MSR_TSC_AUX: 2865 msr_info->data = svm->tsc_aux; 2866 break; 2867 case MSR_IA32_DEBUGCTLMSR: 2868 msr_info->data = svm_get_lbr_vmcb(svm)->save.dbgctl; 2869 break; 2870 case MSR_IA32_LASTBRANCHFROMIP: 2871 msr_info->data = svm_get_lbr_vmcb(svm)->save.br_from; 2872 break; 2873 case MSR_IA32_LASTBRANCHTOIP: 2874 msr_info->data = svm_get_lbr_vmcb(svm)->save.br_to; 2875 break; 2876 case MSR_IA32_LASTINTFROMIP: 2877 msr_info->data = svm_get_lbr_vmcb(svm)->save.last_excp_from; 2878 break; 2879 case MSR_IA32_LASTINTTOIP: 2880 msr_info->data = svm_get_lbr_vmcb(svm)->save.last_excp_to; 2881 break; 2882 case MSR_VM_HSAVE_PA: 2883 msr_info->data = svm->nested.hsave_msr; 2884 break; 2885 case MSR_VM_CR: 2886 msr_info->data = svm->nested.vm_cr_msr; 2887 break; 2888 case MSR_IA32_SPEC_CTRL: 2889 if (!msr_info->host_initiated && 2890 !guest_has_spec_ctrl_msr(vcpu)) 2891 return 1; 2892 2893 if (boot_cpu_has(X86_FEATURE_V_SPEC_CTRL)) 2894 msr_info->data = svm->vmcb->save.spec_ctrl; 2895 else 2896 msr_info->data = svm->spec_ctrl; 2897 break; 2898 case MSR_AMD64_VIRT_SPEC_CTRL: 2899 if (!msr_info->host_initiated && 2900 !guest_cpuid_has(vcpu, X86_FEATURE_VIRT_SSBD)) 2901 return 1; 2902 2903 msr_info->data = svm->virt_spec_ctrl; 2904 break; 2905 case MSR_F15H_IC_CFG: { 2906 2907 int family, model; 2908 2909 family = guest_cpuid_family(vcpu); 2910 model = guest_cpuid_model(vcpu); 2911 2912 if (family < 0 || model < 0) 2913 return kvm_get_msr_common(vcpu, msr_info); 2914 2915 msr_info->data = 0; 2916 2917 if (family == 0x15 && 2918 (model >= 0x2 && model < 0x20)) 2919 msr_info->data = 0x1E; 2920 } 2921 break; 2922 case MSR_AMD64_DE_CFG: 2923 msr_info->data = svm->msr_decfg; 2924 break; 2925 default: 2926 return kvm_get_msr_common(vcpu, msr_info); 2927 } 2928 return 0; 2929 } 2930 2931 static int svm_complete_emulated_msr(struct kvm_vcpu *vcpu, int err) 2932 { 2933 struct vcpu_svm *svm = to_svm(vcpu); 2934 if (!err || !sev_es_guest(vcpu->kvm) || WARN_ON_ONCE(!svm->sev_es.ghcb)) 2935 return kvm_complete_insn_gp(vcpu, err); 2936 2937 ghcb_set_sw_exit_info_1(svm->sev_es.ghcb, 1); 2938 ghcb_set_sw_exit_info_2(svm->sev_es.ghcb, 2939 X86_TRAP_GP | 2940 SVM_EVTINJ_TYPE_EXEPT | 2941 SVM_EVTINJ_VALID); 2942 return 1; 2943 } 2944 2945 static int svm_set_vm_cr(struct kvm_vcpu *vcpu, u64 data) 2946 { 2947 struct vcpu_svm *svm = to_svm(vcpu); 2948 int svm_dis, chg_mask; 2949 2950 if (data & ~SVM_VM_CR_VALID_MASK) 2951 return 1; 2952 2953 chg_mask = SVM_VM_CR_VALID_MASK; 2954 2955 if (svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK) 2956 chg_mask &= ~(SVM_VM_CR_SVM_LOCK_MASK | SVM_VM_CR_SVM_DIS_MASK); 2957 2958 svm->nested.vm_cr_msr &= ~chg_mask; 2959 svm->nested.vm_cr_msr |= (data & chg_mask); 2960 2961 svm_dis = svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK; 2962 2963 /* check for svm_disable while efer.svme is set */ 2964 if (svm_dis && (vcpu->arch.efer & EFER_SVME)) 2965 return 1; 2966 2967 return 0; 2968 } 2969 2970 static int svm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr) 2971 { 2972 struct vcpu_svm *svm = to_svm(vcpu); 2973 int ret = 0; 2974 2975 u32 ecx = msr->index; 2976 u64 data = msr->data; 2977 switch (ecx) { 2978 case MSR_AMD64_TSC_RATIO: 2979 2980 if (!guest_can_use(vcpu, X86_FEATURE_TSCRATEMSR)) { 2981 2982 if (!msr->host_initiated) 2983 return 1; 2984 /* 2985 * In case TSC scaling is not enabled, always 2986 * leave this MSR at the default value. 2987 * 2988 * Due to bug in qemu 6.2.0, it would try to set 2989 * this msr to 0 if tsc scaling is not enabled. 2990 * Ignore this value as well. 2991 */ 2992 if (data != 0 && data != svm->tsc_ratio_msr) 2993 return 1; 2994 break; 2995 } 2996 2997 if (data & SVM_TSC_RATIO_RSVD) 2998 return 1; 2999 3000 svm->tsc_ratio_msr = data; 3001 3002 if (guest_can_use(vcpu, X86_FEATURE_TSCRATEMSR) && 3003 is_guest_mode(vcpu)) 3004 nested_svm_update_tsc_ratio_msr(vcpu); 3005 3006 break; 3007 case MSR_IA32_CR_PAT: 3008 ret = kvm_set_msr_common(vcpu, msr); 3009 if (ret) 3010 break; 3011 3012 svm->vmcb01.ptr->save.g_pat = data; 3013 if (is_guest_mode(vcpu)) 3014 nested_vmcb02_compute_g_pat(svm); 3015 vmcb_mark_dirty(svm->vmcb, VMCB_NPT); 3016 break; 3017 case MSR_IA32_SPEC_CTRL: 3018 if (!msr->host_initiated && 3019 !guest_has_spec_ctrl_msr(vcpu)) 3020 return 1; 3021 3022 if (kvm_spec_ctrl_test_value(data)) 3023 return 1; 3024 3025 if (boot_cpu_has(X86_FEATURE_V_SPEC_CTRL)) 3026 svm->vmcb->save.spec_ctrl = data; 3027 else 3028 svm->spec_ctrl = data; 3029 if (!data) 3030 break; 3031 3032 /* 3033 * For non-nested: 3034 * When it's written (to non-zero) for the first time, pass 3035 * it through. 3036 * 3037 * For nested: 3038 * The handling of the MSR bitmap for L2 guests is done in 3039 * nested_svm_vmrun_msrpm. 3040 * We update the L1 MSR bit as well since it will end up 3041 * touching the MSR anyway now. 3042 */ 3043 set_msr_interception(vcpu, svm->msrpm, MSR_IA32_SPEC_CTRL, 1, 1); 3044 break; 3045 case MSR_AMD64_VIRT_SPEC_CTRL: 3046 if (!msr->host_initiated && 3047 !guest_cpuid_has(vcpu, X86_FEATURE_VIRT_SSBD)) 3048 return 1; 3049 3050 if (data & ~SPEC_CTRL_SSBD) 3051 return 1; 3052 3053 svm->virt_spec_ctrl = data; 3054 break; 3055 case MSR_STAR: 3056 svm->vmcb01.ptr->save.star = data; 3057 break; 3058 #ifdef CONFIG_X86_64 3059 case MSR_LSTAR: 3060 svm->vmcb01.ptr->save.lstar = data; 3061 break; 3062 case MSR_CSTAR: 3063 svm->vmcb01.ptr->save.cstar = data; 3064 break; 3065 case MSR_KERNEL_GS_BASE: 3066 svm->vmcb01.ptr->save.kernel_gs_base = data; 3067 break; 3068 case MSR_SYSCALL_MASK: 3069 svm->vmcb01.ptr->save.sfmask = data; 3070 break; 3071 #endif 3072 case MSR_IA32_SYSENTER_CS: 3073 svm->vmcb01.ptr->save.sysenter_cs = data; 3074 break; 3075 case MSR_IA32_SYSENTER_EIP: 3076 svm->vmcb01.ptr->save.sysenter_eip = (u32)data; 3077 /* 3078 * We only intercept the MSR_IA32_SYSENTER_{EIP|ESP} msrs 3079 * when we spoof an Intel vendor ID (for cross vendor migration). 3080 * In this case we use this intercept to track the high 3081 * 32 bit part of these msrs to support Intel's 3082 * implementation of SYSENTER/SYSEXIT. 3083 */ 3084 svm->sysenter_eip_hi = guest_cpuid_is_intel(vcpu) ? (data >> 32) : 0; 3085 break; 3086 case MSR_IA32_SYSENTER_ESP: 3087 svm->vmcb01.ptr->save.sysenter_esp = (u32)data; 3088 svm->sysenter_esp_hi = guest_cpuid_is_intel(vcpu) ? (data >> 32) : 0; 3089 break; 3090 case MSR_TSC_AUX: 3091 /* 3092 * TSC_AUX is always virtualized for SEV-ES guests when the 3093 * feature is available. The user return MSR support is not 3094 * required in this case because TSC_AUX is restored on #VMEXIT 3095 * from the host save area (which has been initialized in 3096 * svm_hardware_enable()). 3097 */ 3098 if (boot_cpu_has(X86_FEATURE_V_TSC_AUX) && sev_es_guest(vcpu->kvm)) 3099 break; 3100 3101 /* 3102 * TSC_AUX is usually changed only during boot and never read 3103 * directly. Intercept TSC_AUX instead of exposing it to the 3104 * guest via direct_access_msrs, and switch it via user return. 3105 */ 3106 preempt_disable(); 3107 ret = kvm_set_user_return_msr(tsc_aux_uret_slot, data, -1ull); 3108 preempt_enable(); 3109 if (ret) 3110 break; 3111 3112 svm->tsc_aux = data; 3113 break; 3114 case MSR_IA32_DEBUGCTLMSR: 3115 if (!lbrv) { 3116 kvm_pr_unimpl_wrmsr(vcpu, ecx, data); 3117 break; 3118 } 3119 if (data & DEBUGCTL_RESERVED_BITS) 3120 return 1; 3121 3122 svm_get_lbr_vmcb(svm)->save.dbgctl = data; 3123 svm_update_lbrv(vcpu); 3124 break; 3125 case MSR_VM_HSAVE_PA: 3126 /* 3127 * Old kernels did not validate the value written to 3128 * MSR_VM_HSAVE_PA. Allow KVM_SET_MSR to set an invalid 3129 * value to allow live migrating buggy or malicious guests 3130 * originating from those kernels. 3131 */ 3132 if (!msr->host_initiated && !page_address_valid(vcpu, data)) 3133 return 1; 3134 3135 svm->nested.hsave_msr = data & PAGE_MASK; 3136 break; 3137 case MSR_VM_CR: 3138 return svm_set_vm_cr(vcpu, data); 3139 case MSR_VM_IGNNE: 3140 kvm_pr_unimpl_wrmsr(vcpu, ecx, data); 3141 break; 3142 case MSR_AMD64_DE_CFG: { 3143 struct kvm_msr_entry msr_entry; 3144 3145 msr_entry.index = msr->index; 3146 if (svm_get_msr_feature(&msr_entry)) 3147 return 1; 3148 3149 /* Check the supported bits */ 3150 if (data & ~msr_entry.data) 3151 return 1; 3152 3153 /* Don't allow the guest to change a bit, #GP */ 3154 if (!msr->host_initiated && (data ^ msr_entry.data)) 3155 return 1; 3156 3157 svm->msr_decfg = data; 3158 break; 3159 } 3160 default: 3161 return kvm_set_msr_common(vcpu, msr); 3162 } 3163 return ret; 3164 } 3165 3166 static int msr_interception(struct kvm_vcpu *vcpu) 3167 { 3168 if (to_svm(vcpu)->vmcb->control.exit_info_1) 3169 return kvm_emulate_wrmsr(vcpu); 3170 else 3171 return kvm_emulate_rdmsr(vcpu); 3172 } 3173 3174 static int interrupt_window_interception(struct kvm_vcpu *vcpu) 3175 { 3176 kvm_make_request(KVM_REQ_EVENT, vcpu); 3177 svm_clear_vintr(to_svm(vcpu)); 3178 3179 /* 3180 * If not running nested, for AVIC, the only reason to end up here is ExtINTs. 3181 * In this case AVIC was temporarily disabled for 3182 * requesting the IRQ window and we have to re-enable it. 3183 * 3184 * If running nested, still remove the VM wide AVIC inhibit to 3185 * support case in which the interrupt window was requested when the 3186 * vCPU was not running nested. 3187 3188 * All vCPUs which run still run nested, will remain to have their 3189 * AVIC still inhibited due to per-cpu AVIC inhibition. 3190 */ 3191 kvm_clear_apicv_inhibit(vcpu->kvm, APICV_INHIBIT_REASON_IRQWIN); 3192 3193 ++vcpu->stat.irq_window_exits; 3194 return 1; 3195 } 3196 3197 static int pause_interception(struct kvm_vcpu *vcpu) 3198 { 3199 bool in_kernel; 3200 /* 3201 * CPL is not made available for an SEV-ES guest, therefore 3202 * vcpu->arch.preempted_in_kernel can never be true. Just 3203 * set in_kernel to false as well. 3204 */ 3205 in_kernel = !sev_es_guest(vcpu->kvm) && svm_get_cpl(vcpu) == 0; 3206 3207 grow_ple_window(vcpu); 3208 3209 kvm_vcpu_on_spin(vcpu, in_kernel); 3210 return kvm_skip_emulated_instruction(vcpu); 3211 } 3212 3213 static int invpcid_interception(struct kvm_vcpu *vcpu) 3214 { 3215 struct vcpu_svm *svm = to_svm(vcpu); 3216 unsigned long type; 3217 gva_t gva; 3218 3219 if (!guest_cpuid_has(vcpu, X86_FEATURE_INVPCID)) { 3220 kvm_queue_exception(vcpu, UD_VECTOR); 3221 return 1; 3222 } 3223 3224 /* 3225 * For an INVPCID intercept: 3226 * EXITINFO1 provides the linear address of the memory operand. 3227 * EXITINFO2 provides the contents of the register operand. 3228 */ 3229 type = svm->vmcb->control.exit_info_2; 3230 gva = svm->vmcb->control.exit_info_1; 3231 3232 return kvm_handle_invpcid(vcpu, type, gva); 3233 } 3234 3235 static int (*const svm_exit_handlers[])(struct kvm_vcpu *vcpu) = { 3236 [SVM_EXIT_READ_CR0] = cr_interception, 3237 [SVM_EXIT_READ_CR3] = cr_interception, 3238 [SVM_EXIT_READ_CR4] = cr_interception, 3239 [SVM_EXIT_READ_CR8] = cr_interception, 3240 [SVM_EXIT_CR0_SEL_WRITE] = cr_interception, 3241 [SVM_EXIT_WRITE_CR0] = cr_interception, 3242 [SVM_EXIT_WRITE_CR3] = cr_interception, 3243 [SVM_EXIT_WRITE_CR4] = cr_interception, 3244 [SVM_EXIT_WRITE_CR8] = cr8_write_interception, 3245 [SVM_EXIT_READ_DR0] = dr_interception, 3246 [SVM_EXIT_READ_DR1] = dr_interception, 3247 [SVM_EXIT_READ_DR2] = dr_interception, 3248 [SVM_EXIT_READ_DR3] = dr_interception, 3249 [SVM_EXIT_READ_DR4] = dr_interception, 3250 [SVM_EXIT_READ_DR5] = dr_interception, 3251 [SVM_EXIT_READ_DR6] = dr_interception, 3252 [SVM_EXIT_READ_DR7] = dr_interception, 3253 [SVM_EXIT_WRITE_DR0] = dr_interception, 3254 [SVM_EXIT_WRITE_DR1] = dr_interception, 3255 [SVM_EXIT_WRITE_DR2] = dr_interception, 3256 [SVM_EXIT_WRITE_DR3] = dr_interception, 3257 [SVM_EXIT_WRITE_DR4] = dr_interception, 3258 [SVM_EXIT_WRITE_DR5] = dr_interception, 3259 [SVM_EXIT_WRITE_DR6] = dr_interception, 3260 [SVM_EXIT_WRITE_DR7] = dr_interception, 3261 [SVM_EXIT_EXCP_BASE + DB_VECTOR] = db_interception, 3262 [SVM_EXIT_EXCP_BASE + BP_VECTOR] = bp_interception, 3263 [SVM_EXIT_EXCP_BASE + UD_VECTOR] = ud_interception, 3264 [SVM_EXIT_EXCP_BASE + PF_VECTOR] = pf_interception, 3265 [SVM_EXIT_EXCP_BASE + MC_VECTOR] = mc_interception, 3266 [SVM_EXIT_EXCP_BASE + AC_VECTOR] = ac_interception, 3267 [SVM_EXIT_EXCP_BASE + GP_VECTOR] = gp_interception, 3268 [SVM_EXIT_INTR] = intr_interception, 3269 [SVM_EXIT_NMI] = nmi_interception, 3270 [SVM_EXIT_SMI] = smi_interception, 3271 [SVM_EXIT_VINTR] = interrupt_window_interception, 3272 [SVM_EXIT_RDPMC] = kvm_emulate_rdpmc, 3273 [SVM_EXIT_CPUID] = kvm_emulate_cpuid, 3274 [SVM_EXIT_IRET] = iret_interception, 3275 [SVM_EXIT_INVD] = kvm_emulate_invd, 3276 [SVM_EXIT_PAUSE] = pause_interception, 3277 [SVM_EXIT_HLT] = kvm_emulate_halt, 3278 [SVM_EXIT_INVLPG] = invlpg_interception, 3279 [SVM_EXIT_INVLPGA] = invlpga_interception, 3280 [SVM_EXIT_IOIO] = io_interception, 3281 [SVM_EXIT_MSR] = msr_interception, 3282 [SVM_EXIT_TASK_SWITCH] = task_switch_interception, 3283 [SVM_EXIT_SHUTDOWN] = shutdown_interception, 3284 [SVM_EXIT_VMRUN] = vmrun_interception, 3285 [SVM_EXIT_VMMCALL] = kvm_emulate_hypercall, 3286 [SVM_EXIT_VMLOAD] = vmload_interception, 3287 [SVM_EXIT_VMSAVE] = vmsave_interception, 3288 [SVM_EXIT_STGI] = stgi_interception, 3289 [SVM_EXIT_CLGI] = clgi_interception, 3290 [SVM_EXIT_SKINIT] = skinit_interception, 3291 [SVM_EXIT_RDTSCP] = kvm_handle_invalid_op, 3292 [SVM_EXIT_WBINVD] = kvm_emulate_wbinvd, 3293 [SVM_EXIT_MONITOR] = kvm_emulate_monitor, 3294 [SVM_EXIT_MWAIT] = kvm_emulate_mwait, 3295 [SVM_EXIT_XSETBV] = kvm_emulate_xsetbv, 3296 [SVM_EXIT_RDPRU] = kvm_handle_invalid_op, 3297 [SVM_EXIT_EFER_WRITE_TRAP] = efer_trap, 3298 [SVM_EXIT_CR0_WRITE_TRAP] = cr_trap, 3299 [SVM_EXIT_CR4_WRITE_TRAP] = cr_trap, 3300 [SVM_EXIT_CR8_WRITE_TRAP] = cr_trap, 3301 [SVM_EXIT_INVPCID] = invpcid_interception, 3302 [SVM_EXIT_NPF] = npf_interception, 3303 [SVM_EXIT_RSM] = rsm_interception, 3304 [SVM_EXIT_AVIC_INCOMPLETE_IPI] = avic_incomplete_ipi_interception, 3305 [SVM_EXIT_AVIC_UNACCELERATED_ACCESS] = avic_unaccelerated_access_interception, 3306 [SVM_EXIT_VMGEXIT] = sev_handle_vmgexit, 3307 }; 3308 3309 static void dump_vmcb(struct kvm_vcpu *vcpu) 3310 { 3311 struct vcpu_svm *svm = to_svm(vcpu); 3312 struct vmcb_control_area *control = &svm->vmcb->control; 3313 struct vmcb_save_area *save = &svm->vmcb->save; 3314 struct vmcb_save_area *save01 = &svm->vmcb01.ptr->save; 3315 3316 if (!dump_invalid_vmcb) { 3317 pr_warn_ratelimited("set kvm_amd.dump_invalid_vmcb=1 to dump internal KVM state.\n"); 3318 return; 3319 } 3320 3321 pr_err("VMCB %p, last attempted VMRUN on CPU %d\n", 3322 svm->current_vmcb->ptr, vcpu->arch.last_vmentry_cpu); 3323 pr_err("VMCB Control Area:\n"); 3324 pr_err("%-20s%04x\n", "cr_read:", control->intercepts[INTERCEPT_CR] & 0xffff); 3325 pr_err("%-20s%04x\n", "cr_write:", control->intercepts[INTERCEPT_CR] >> 16); 3326 pr_err("%-20s%04x\n", "dr_read:", control->intercepts[INTERCEPT_DR] & 0xffff); 3327 pr_err("%-20s%04x\n", "dr_write:", control->intercepts[INTERCEPT_DR] >> 16); 3328 pr_err("%-20s%08x\n", "exceptions:", control->intercepts[INTERCEPT_EXCEPTION]); 3329 pr_err("%-20s%08x %08x\n", "intercepts:", 3330 control->intercepts[INTERCEPT_WORD3], 3331 control->intercepts[INTERCEPT_WORD4]); 3332 pr_err("%-20s%d\n", "pause filter count:", control->pause_filter_count); 3333 pr_err("%-20s%d\n", "pause filter threshold:", 3334 control->pause_filter_thresh); 3335 pr_err("%-20s%016llx\n", "iopm_base_pa:", control->iopm_base_pa); 3336 pr_err("%-20s%016llx\n", "msrpm_base_pa:", control->msrpm_base_pa); 3337 pr_err("%-20s%016llx\n", "tsc_offset:", control->tsc_offset); 3338 pr_err("%-20s%d\n", "asid:", control->asid); 3339 pr_err("%-20s%d\n", "tlb_ctl:", control->tlb_ctl); 3340 pr_err("%-20s%08x\n", "int_ctl:", control->int_ctl); 3341 pr_err("%-20s%08x\n", "int_vector:", control->int_vector); 3342 pr_err("%-20s%08x\n", "int_state:", control->int_state); 3343 pr_err("%-20s%08x\n", "exit_code:", control->exit_code); 3344 pr_err("%-20s%016llx\n", "exit_info1:", control->exit_info_1); 3345 pr_err("%-20s%016llx\n", "exit_info2:", control->exit_info_2); 3346 pr_err("%-20s%08x\n", "exit_int_info:", control->exit_int_info); 3347 pr_err("%-20s%08x\n", "exit_int_info_err:", control->exit_int_info_err); 3348 pr_err("%-20s%lld\n", "nested_ctl:", control->nested_ctl); 3349 pr_err("%-20s%016llx\n", "nested_cr3:", control->nested_cr3); 3350 pr_err("%-20s%016llx\n", "avic_vapic_bar:", control->avic_vapic_bar); 3351 pr_err("%-20s%016llx\n", "ghcb:", control->ghcb_gpa); 3352 pr_err("%-20s%08x\n", "event_inj:", control->event_inj); 3353 pr_err("%-20s%08x\n", "event_inj_err:", control->event_inj_err); 3354 pr_err("%-20s%lld\n", "virt_ext:", control->virt_ext); 3355 pr_err("%-20s%016llx\n", "next_rip:", control->next_rip); 3356 pr_err("%-20s%016llx\n", "avic_backing_page:", control->avic_backing_page); 3357 pr_err("%-20s%016llx\n", "avic_logical_id:", control->avic_logical_id); 3358 pr_err("%-20s%016llx\n", "avic_physical_id:", control->avic_physical_id); 3359 pr_err("%-20s%016llx\n", "vmsa_pa:", control->vmsa_pa); 3360 pr_err("VMCB State Save Area:\n"); 3361 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n", 3362 "es:", 3363 save->es.selector, save->es.attrib, 3364 save->es.limit, save->es.base); 3365 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n", 3366 "cs:", 3367 save->cs.selector, save->cs.attrib, 3368 save->cs.limit, save->cs.base); 3369 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n", 3370 "ss:", 3371 save->ss.selector, save->ss.attrib, 3372 save->ss.limit, save->ss.base); 3373 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n", 3374 "ds:", 3375 save->ds.selector, save->ds.attrib, 3376 save->ds.limit, save->ds.base); 3377 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n", 3378 "fs:", 3379 save01->fs.selector, save01->fs.attrib, 3380 save01->fs.limit, save01->fs.base); 3381 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n", 3382 "gs:", 3383 save01->gs.selector, save01->gs.attrib, 3384 save01->gs.limit, save01->gs.base); 3385 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n", 3386 "gdtr:", 3387 save->gdtr.selector, save->gdtr.attrib, 3388 save->gdtr.limit, save->gdtr.base); 3389 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n", 3390 "ldtr:", 3391 save01->ldtr.selector, save01->ldtr.attrib, 3392 save01->ldtr.limit, save01->ldtr.base); 3393 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n", 3394 "idtr:", 3395 save->idtr.selector, save->idtr.attrib, 3396 save->idtr.limit, save->idtr.base); 3397 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n", 3398 "tr:", 3399 save01->tr.selector, save01->tr.attrib, 3400 save01->tr.limit, save01->tr.base); 3401 pr_err("vmpl: %d cpl: %d efer: %016llx\n", 3402 save->vmpl, save->cpl, save->efer); 3403 pr_err("%-15s %016llx %-13s %016llx\n", 3404 "cr0:", save->cr0, "cr2:", save->cr2); 3405 pr_err("%-15s %016llx %-13s %016llx\n", 3406 "cr3:", save->cr3, "cr4:", save->cr4); 3407 pr_err("%-15s %016llx %-13s %016llx\n", 3408 "dr6:", save->dr6, "dr7:", save->dr7); 3409 pr_err("%-15s %016llx %-13s %016llx\n", 3410 "rip:", save->rip, "rflags:", save->rflags); 3411 pr_err("%-15s %016llx %-13s %016llx\n", 3412 "rsp:", save->rsp, "rax:", save->rax); 3413 pr_err("%-15s %016llx %-13s %016llx\n", 3414 "star:", save01->star, "lstar:", save01->lstar); 3415 pr_err("%-15s %016llx %-13s %016llx\n", 3416 "cstar:", save01->cstar, "sfmask:", save01->sfmask); 3417 pr_err("%-15s %016llx %-13s %016llx\n", 3418 "kernel_gs_base:", save01->kernel_gs_base, 3419 "sysenter_cs:", save01->sysenter_cs); 3420 pr_err("%-15s %016llx %-13s %016llx\n", 3421 "sysenter_esp:", save01->sysenter_esp, 3422 "sysenter_eip:", save01->sysenter_eip); 3423 pr_err("%-15s %016llx %-13s %016llx\n", 3424 "gpat:", save->g_pat, "dbgctl:", save->dbgctl); 3425 pr_err("%-15s %016llx %-13s %016llx\n", 3426 "br_from:", save->br_from, "br_to:", save->br_to); 3427 pr_err("%-15s %016llx %-13s %016llx\n", 3428 "excp_from:", save->last_excp_from, 3429 "excp_to:", save->last_excp_to); 3430 } 3431 3432 static bool svm_check_exit_valid(u64 exit_code) 3433 { 3434 return (exit_code < ARRAY_SIZE(svm_exit_handlers) && 3435 svm_exit_handlers[exit_code]); 3436 } 3437 3438 static int svm_handle_invalid_exit(struct kvm_vcpu *vcpu, u64 exit_code) 3439 { 3440 vcpu_unimpl(vcpu, "svm: unexpected exit reason 0x%llx\n", exit_code); 3441 dump_vmcb(vcpu); 3442 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR; 3443 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_UNEXPECTED_EXIT_REASON; 3444 vcpu->run->internal.ndata = 2; 3445 vcpu->run->internal.data[0] = exit_code; 3446 vcpu->run->internal.data[1] = vcpu->arch.last_vmentry_cpu; 3447 return 0; 3448 } 3449 3450 int svm_invoke_exit_handler(struct kvm_vcpu *vcpu, u64 exit_code) 3451 { 3452 if (!svm_check_exit_valid(exit_code)) 3453 return svm_handle_invalid_exit(vcpu, exit_code); 3454 3455 #ifdef CONFIG_RETPOLINE 3456 if (exit_code == SVM_EXIT_MSR) 3457 return msr_interception(vcpu); 3458 else if (exit_code == SVM_EXIT_VINTR) 3459 return interrupt_window_interception(vcpu); 3460 else if (exit_code == SVM_EXIT_INTR) 3461 return intr_interception(vcpu); 3462 else if (exit_code == SVM_EXIT_HLT) 3463 return kvm_emulate_halt(vcpu); 3464 else if (exit_code == SVM_EXIT_NPF) 3465 return npf_interception(vcpu); 3466 #endif 3467 return svm_exit_handlers[exit_code](vcpu); 3468 } 3469 3470 static void svm_get_exit_info(struct kvm_vcpu *vcpu, u32 *reason, 3471 u64 *info1, u64 *info2, 3472 u32 *intr_info, u32 *error_code) 3473 { 3474 struct vmcb_control_area *control = &to_svm(vcpu)->vmcb->control; 3475 3476 *reason = control->exit_code; 3477 *info1 = control->exit_info_1; 3478 *info2 = control->exit_info_2; 3479 *intr_info = control->exit_int_info; 3480 if ((*intr_info & SVM_EXITINTINFO_VALID) && 3481 (*intr_info & SVM_EXITINTINFO_VALID_ERR)) 3482 *error_code = control->exit_int_info_err; 3483 else 3484 *error_code = 0; 3485 } 3486 3487 static int svm_handle_exit(struct kvm_vcpu *vcpu, fastpath_t exit_fastpath) 3488 { 3489 struct vcpu_svm *svm = to_svm(vcpu); 3490 struct kvm_run *kvm_run = vcpu->run; 3491 u32 exit_code = svm->vmcb->control.exit_code; 3492 3493 /* SEV-ES guests must use the CR write traps to track CR registers. */ 3494 if (!sev_es_guest(vcpu->kvm)) { 3495 if (!svm_is_intercept(svm, INTERCEPT_CR0_WRITE)) 3496 vcpu->arch.cr0 = svm->vmcb->save.cr0; 3497 if (npt_enabled) 3498 vcpu->arch.cr3 = svm->vmcb->save.cr3; 3499 } 3500 3501 if (is_guest_mode(vcpu)) { 3502 int vmexit; 3503 3504 trace_kvm_nested_vmexit(vcpu, KVM_ISA_SVM); 3505 3506 vmexit = nested_svm_exit_special(svm); 3507 3508 if (vmexit == NESTED_EXIT_CONTINUE) 3509 vmexit = nested_svm_exit_handled(svm); 3510 3511 if (vmexit == NESTED_EXIT_DONE) 3512 return 1; 3513 } 3514 3515 if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) { 3516 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY; 3517 kvm_run->fail_entry.hardware_entry_failure_reason 3518 = svm->vmcb->control.exit_code; 3519 kvm_run->fail_entry.cpu = vcpu->arch.last_vmentry_cpu; 3520 dump_vmcb(vcpu); 3521 return 0; 3522 } 3523 3524 if (exit_fastpath != EXIT_FASTPATH_NONE) 3525 return 1; 3526 3527 return svm_invoke_exit_handler(vcpu, exit_code); 3528 } 3529 3530 static void pre_svm_run(struct kvm_vcpu *vcpu) 3531 { 3532 struct svm_cpu_data *sd = per_cpu_ptr(&svm_data, vcpu->cpu); 3533 struct vcpu_svm *svm = to_svm(vcpu); 3534 3535 /* 3536 * If the previous vmrun of the vmcb occurred on a different physical 3537 * cpu, then mark the vmcb dirty and assign a new asid. Hardware's 3538 * vmcb clean bits are per logical CPU, as are KVM's asid assignments. 3539 */ 3540 if (unlikely(svm->current_vmcb->cpu != vcpu->cpu)) { 3541 svm->current_vmcb->asid_generation = 0; 3542 vmcb_mark_all_dirty(svm->vmcb); 3543 svm->current_vmcb->cpu = vcpu->cpu; 3544 } 3545 3546 if (sev_guest(vcpu->kvm)) 3547 return pre_sev_run(svm, vcpu->cpu); 3548 3549 /* FIXME: handle wraparound of asid_generation */ 3550 if (svm->current_vmcb->asid_generation != sd->asid_generation) 3551 new_asid(svm, sd); 3552 } 3553 3554 static void svm_inject_nmi(struct kvm_vcpu *vcpu) 3555 { 3556 struct vcpu_svm *svm = to_svm(vcpu); 3557 3558 svm->vmcb->control.event_inj = SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_NMI; 3559 3560 if (svm->nmi_l1_to_l2) 3561 return; 3562 3563 svm->nmi_masked = true; 3564 svm_set_iret_intercept(svm); 3565 ++vcpu->stat.nmi_injections; 3566 } 3567 3568 static bool svm_is_vnmi_pending(struct kvm_vcpu *vcpu) 3569 { 3570 struct vcpu_svm *svm = to_svm(vcpu); 3571 3572 if (!is_vnmi_enabled(svm)) 3573 return false; 3574 3575 return !!(svm->vmcb->control.int_ctl & V_NMI_PENDING_MASK); 3576 } 3577 3578 static bool svm_set_vnmi_pending(struct kvm_vcpu *vcpu) 3579 { 3580 struct vcpu_svm *svm = to_svm(vcpu); 3581 3582 if (!is_vnmi_enabled(svm)) 3583 return false; 3584 3585 if (svm->vmcb->control.int_ctl & V_NMI_PENDING_MASK) 3586 return false; 3587 3588 svm->vmcb->control.int_ctl |= V_NMI_PENDING_MASK; 3589 vmcb_mark_dirty(svm->vmcb, VMCB_INTR); 3590 3591 /* 3592 * Because the pending NMI is serviced by hardware, KVM can't know when 3593 * the NMI is "injected", but for all intents and purposes, passing the 3594 * NMI off to hardware counts as injection. 3595 */ 3596 ++vcpu->stat.nmi_injections; 3597 3598 return true; 3599 } 3600 3601 static void svm_inject_irq(struct kvm_vcpu *vcpu, bool reinjected) 3602 { 3603 struct vcpu_svm *svm = to_svm(vcpu); 3604 u32 type; 3605 3606 if (vcpu->arch.interrupt.soft) { 3607 if (svm_update_soft_interrupt_rip(vcpu)) 3608 return; 3609 3610 type = SVM_EVTINJ_TYPE_SOFT; 3611 } else { 3612 type = SVM_EVTINJ_TYPE_INTR; 3613 } 3614 3615 trace_kvm_inj_virq(vcpu->arch.interrupt.nr, 3616 vcpu->arch.interrupt.soft, reinjected); 3617 ++vcpu->stat.irq_injections; 3618 3619 svm->vmcb->control.event_inj = vcpu->arch.interrupt.nr | 3620 SVM_EVTINJ_VALID | type; 3621 } 3622 3623 void svm_complete_interrupt_delivery(struct kvm_vcpu *vcpu, int delivery_mode, 3624 int trig_mode, int vector) 3625 { 3626 /* 3627 * apic->apicv_active must be read after vcpu->mode. 3628 * Pairs with smp_store_release in vcpu_enter_guest. 3629 */ 3630 bool in_guest_mode = (smp_load_acquire(&vcpu->mode) == IN_GUEST_MODE); 3631 3632 /* Note, this is called iff the local APIC is in-kernel. */ 3633 if (!READ_ONCE(vcpu->arch.apic->apicv_active)) { 3634 /* Process the interrupt via kvm_check_and_inject_events(). */ 3635 kvm_make_request(KVM_REQ_EVENT, vcpu); 3636 kvm_vcpu_kick(vcpu); 3637 return; 3638 } 3639 3640 trace_kvm_apicv_accept_irq(vcpu->vcpu_id, delivery_mode, trig_mode, vector); 3641 if (in_guest_mode) { 3642 /* 3643 * Signal the doorbell to tell hardware to inject the IRQ. If 3644 * the vCPU exits the guest before the doorbell chimes, hardware 3645 * will automatically process AVIC interrupts at the next VMRUN. 3646 */ 3647 avic_ring_doorbell(vcpu); 3648 } else { 3649 /* 3650 * Wake the vCPU if it was blocking. KVM will then detect the 3651 * pending IRQ when checking if the vCPU has a wake event. 3652 */ 3653 kvm_vcpu_wake_up(vcpu); 3654 } 3655 } 3656 3657 static void svm_deliver_interrupt(struct kvm_lapic *apic, int delivery_mode, 3658 int trig_mode, int vector) 3659 { 3660 kvm_lapic_set_irr(vector, apic); 3661 3662 /* 3663 * Pairs with the smp_mb_*() after setting vcpu->guest_mode in 3664 * vcpu_enter_guest() to ensure the write to the vIRR is ordered before 3665 * the read of guest_mode. This guarantees that either VMRUN will see 3666 * and process the new vIRR entry, or that svm_complete_interrupt_delivery 3667 * will signal the doorbell if the CPU has already entered the guest. 3668 */ 3669 smp_mb__after_atomic(); 3670 svm_complete_interrupt_delivery(apic->vcpu, delivery_mode, trig_mode, vector); 3671 } 3672 3673 static void svm_update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr) 3674 { 3675 struct vcpu_svm *svm = to_svm(vcpu); 3676 3677 /* 3678 * SEV-ES guests must always keep the CR intercepts cleared. CR 3679 * tracking is done using the CR write traps. 3680 */ 3681 if (sev_es_guest(vcpu->kvm)) 3682 return; 3683 3684 if (nested_svm_virtualize_tpr(vcpu)) 3685 return; 3686 3687 svm_clr_intercept(svm, INTERCEPT_CR8_WRITE); 3688 3689 if (irr == -1) 3690 return; 3691 3692 if (tpr >= irr) 3693 svm_set_intercept(svm, INTERCEPT_CR8_WRITE); 3694 } 3695 3696 static bool svm_get_nmi_mask(struct kvm_vcpu *vcpu) 3697 { 3698 struct vcpu_svm *svm = to_svm(vcpu); 3699 3700 if (is_vnmi_enabled(svm)) 3701 return svm->vmcb->control.int_ctl & V_NMI_BLOCKING_MASK; 3702 else 3703 return svm->nmi_masked; 3704 } 3705 3706 static void svm_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked) 3707 { 3708 struct vcpu_svm *svm = to_svm(vcpu); 3709 3710 if (is_vnmi_enabled(svm)) { 3711 if (masked) 3712 svm->vmcb->control.int_ctl |= V_NMI_BLOCKING_MASK; 3713 else 3714 svm->vmcb->control.int_ctl &= ~V_NMI_BLOCKING_MASK; 3715 3716 } else { 3717 svm->nmi_masked = masked; 3718 if (masked) 3719 svm_set_iret_intercept(svm); 3720 else 3721 svm_clr_iret_intercept(svm); 3722 } 3723 } 3724 3725 bool svm_nmi_blocked(struct kvm_vcpu *vcpu) 3726 { 3727 struct vcpu_svm *svm = to_svm(vcpu); 3728 struct vmcb *vmcb = svm->vmcb; 3729 3730 if (!gif_set(svm)) 3731 return true; 3732 3733 if (is_guest_mode(vcpu) && nested_exit_on_nmi(svm)) 3734 return false; 3735 3736 if (svm_get_nmi_mask(vcpu)) 3737 return true; 3738 3739 return vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK; 3740 } 3741 3742 static int svm_nmi_allowed(struct kvm_vcpu *vcpu, bool for_injection) 3743 { 3744 struct vcpu_svm *svm = to_svm(vcpu); 3745 if (svm->nested.nested_run_pending) 3746 return -EBUSY; 3747 3748 if (svm_nmi_blocked(vcpu)) 3749 return 0; 3750 3751 /* An NMI must not be injected into L2 if it's supposed to VM-Exit. */ 3752 if (for_injection && is_guest_mode(vcpu) && nested_exit_on_nmi(svm)) 3753 return -EBUSY; 3754 return 1; 3755 } 3756 3757 bool svm_interrupt_blocked(struct kvm_vcpu *vcpu) 3758 { 3759 struct vcpu_svm *svm = to_svm(vcpu); 3760 struct vmcb *vmcb = svm->vmcb; 3761 3762 if (!gif_set(svm)) 3763 return true; 3764 3765 if (is_guest_mode(vcpu)) { 3766 /* As long as interrupts are being delivered... */ 3767 if ((svm->nested.ctl.int_ctl & V_INTR_MASKING_MASK) 3768 ? !(svm->vmcb01.ptr->save.rflags & X86_EFLAGS_IF) 3769 : !(kvm_get_rflags(vcpu) & X86_EFLAGS_IF)) 3770 return true; 3771 3772 /* ... vmexits aren't blocked by the interrupt shadow */ 3773 if (nested_exit_on_intr(svm)) 3774 return false; 3775 } else { 3776 if (!svm_get_if_flag(vcpu)) 3777 return true; 3778 } 3779 3780 return (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK); 3781 } 3782 3783 static int svm_interrupt_allowed(struct kvm_vcpu *vcpu, bool for_injection) 3784 { 3785 struct vcpu_svm *svm = to_svm(vcpu); 3786 3787 if (svm->nested.nested_run_pending) 3788 return -EBUSY; 3789 3790 if (svm_interrupt_blocked(vcpu)) 3791 return 0; 3792 3793 /* 3794 * An IRQ must not be injected into L2 if it's supposed to VM-Exit, 3795 * e.g. if the IRQ arrived asynchronously after checking nested events. 3796 */ 3797 if (for_injection && is_guest_mode(vcpu) && nested_exit_on_intr(svm)) 3798 return -EBUSY; 3799 3800 return 1; 3801 } 3802 3803 static void svm_enable_irq_window(struct kvm_vcpu *vcpu) 3804 { 3805 struct vcpu_svm *svm = to_svm(vcpu); 3806 3807 /* 3808 * In case GIF=0 we can't rely on the CPU to tell us when GIF becomes 3809 * 1, because that's a separate STGI/VMRUN intercept. The next time we 3810 * get that intercept, this function will be called again though and 3811 * we'll get the vintr intercept. However, if the vGIF feature is 3812 * enabled, the STGI interception will not occur. Enable the irq 3813 * window under the assumption that the hardware will set the GIF. 3814 */ 3815 if (vgif || gif_set(svm)) { 3816 /* 3817 * IRQ window is not needed when AVIC is enabled, 3818 * unless we have pending ExtINT since it cannot be injected 3819 * via AVIC. In such case, KVM needs to temporarily disable AVIC, 3820 * and fallback to injecting IRQ via V_IRQ. 3821 * 3822 * If running nested, AVIC is already locally inhibited 3823 * on this vCPU, therefore there is no need to request 3824 * the VM wide AVIC inhibition. 3825 */ 3826 if (!is_guest_mode(vcpu)) 3827 kvm_set_apicv_inhibit(vcpu->kvm, APICV_INHIBIT_REASON_IRQWIN); 3828 3829 svm_set_vintr(svm); 3830 } 3831 } 3832 3833 static void svm_enable_nmi_window(struct kvm_vcpu *vcpu) 3834 { 3835 struct vcpu_svm *svm = to_svm(vcpu); 3836 3837 /* 3838 * KVM should never request an NMI window when vNMI is enabled, as KVM 3839 * allows at most one to-be-injected NMI and one pending NMI, i.e. if 3840 * two NMIs arrive simultaneously, KVM will inject one and set 3841 * V_NMI_PENDING for the other. WARN, but continue with the standard 3842 * single-step approach to try and salvage the pending NMI. 3843 */ 3844 WARN_ON_ONCE(is_vnmi_enabled(svm)); 3845 3846 if (svm_get_nmi_mask(vcpu) && !svm->awaiting_iret_completion) 3847 return; /* IRET will cause a vm exit */ 3848 3849 /* 3850 * SEV-ES guests are responsible for signaling when a vCPU is ready to 3851 * receive a new NMI, as SEV-ES guests can't be single-stepped, i.e. 3852 * KVM can't intercept and single-step IRET to detect when NMIs are 3853 * unblocked (architecturally speaking). See SVM_VMGEXIT_NMI_COMPLETE. 3854 * 3855 * Note, GIF is guaranteed to be '1' for SEV-ES guests as hardware 3856 * ignores SEV-ES guest writes to EFER.SVME *and* CLGI/STGI are not 3857 * supported NAEs in the GHCB protocol. 3858 */ 3859 if (sev_es_guest(vcpu->kvm)) 3860 return; 3861 3862 if (!gif_set(svm)) { 3863 if (vgif) 3864 svm_set_intercept(svm, INTERCEPT_STGI); 3865 return; /* STGI will cause a vm exit */ 3866 } 3867 3868 /* 3869 * Something prevents NMI from been injected. Single step over possible 3870 * problem (IRET or exception injection or interrupt shadow) 3871 */ 3872 svm->nmi_singlestep_guest_rflags = svm_get_rflags(vcpu); 3873 svm->nmi_singlestep = true; 3874 svm->vmcb->save.rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF); 3875 } 3876 3877 static void svm_flush_tlb_asid(struct kvm_vcpu *vcpu) 3878 { 3879 struct vcpu_svm *svm = to_svm(vcpu); 3880 3881 /* 3882 * Unlike VMX, SVM doesn't provide a way to flush only NPT TLB entries. 3883 * A TLB flush for the current ASID flushes both "host" and "guest" TLB 3884 * entries, and thus is a superset of Hyper-V's fine grained flushing. 3885 */ 3886 kvm_hv_vcpu_purge_flush_tlb(vcpu); 3887 3888 /* 3889 * Flush only the current ASID even if the TLB flush was invoked via 3890 * kvm_flush_remote_tlbs(). Although flushing remote TLBs requires all 3891 * ASIDs to be flushed, KVM uses a single ASID for L1 and L2, and 3892 * unconditionally does a TLB flush on both nested VM-Enter and nested 3893 * VM-Exit (via kvm_mmu_reset_context()). 3894 */ 3895 if (static_cpu_has(X86_FEATURE_FLUSHBYASID)) 3896 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ASID; 3897 else 3898 svm->current_vmcb->asid_generation--; 3899 } 3900 3901 static void svm_flush_tlb_current(struct kvm_vcpu *vcpu) 3902 { 3903 hpa_t root_tdp = vcpu->arch.mmu->root.hpa; 3904 3905 /* 3906 * When running on Hyper-V with EnlightenedNptTlb enabled, explicitly 3907 * flush the NPT mappings via hypercall as flushing the ASID only 3908 * affects virtual to physical mappings, it does not invalidate guest 3909 * physical to host physical mappings. 3910 */ 3911 if (svm_hv_is_enlightened_tlb_enabled(vcpu) && VALID_PAGE(root_tdp)) 3912 hyperv_flush_guest_mapping(root_tdp); 3913 3914 svm_flush_tlb_asid(vcpu); 3915 } 3916 3917 static void svm_flush_tlb_all(struct kvm_vcpu *vcpu) 3918 { 3919 /* 3920 * When running on Hyper-V with EnlightenedNptTlb enabled, remote TLB 3921 * flushes should be routed to hv_flush_remote_tlbs() without requesting 3922 * a "regular" remote flush. Reaching this point means either there's 3923 * a KVM bug or a prior hv_flush_remote_tlbs() call failed, both of 3924 * which might be fatal to the guest. Yell, but try to recover. 3925 */ 3926 if (WARN_ON_ONCE(svm_hv_is_enlightened_tlb_enabled(vcpu))) 3927 hv_flush_remote_tlbs(vcpu->kvm); 3928 3929 svm_flush_tlb_asid(vcpu); 3930 } 3931 3932 static void svm_flush_tlb_gva(struct kvm_vcpu *vcpu, gva_t gva) 3933 { 3934 struct vcpu_svm *svm = to_svm(vcpu); 3935 3936 invlpga(gva, svm->vmcb->control.asid); 3937 } 3938 3939 static inline void sync_cr8_to_lapic(struct kvm_vcpu *vcpu) 3940 { 3941 struct vcpu_svm *svm = to_svm(vcpu); 3942 3943 if (nested_svm_virtualize_tpr(vcpu)) 3944 return; 3945 3946 if (!svm_is_intercept(svm, INTERCEPT_CR8_WRITE)) { 3947 int cr8 = svm->vmcb->control.int_ctl & V_TPR_MASK; 3948 kvm_set_cr8(vcpu, cr8); 3949 } 3950 } 3951 3952 static inline void sync_lapic_to_cr8(struct kvm_vcpu *vcpu) 3953 { 3954 struct vcpu_svm *svm = to_svm(vcpu); 3955 u64 cr8; 3956 3957 if (nested_svm_virtualize_tpr(vcpu) || 3958 kvm_vcpu_apicv_active(vcpu)) 3959 return; 3960 3961 cr8 = kvm_get_cr8(vcpu); 3962 svm->vmcb->control.int_ctl &= ~V_TPR_MASK; 3963 svm->vmcb->control.int_ctl |= cr8 & V_TPR_MASK; 3964 } 3965 3966 static void svm_complete_soft_interrupt(struct kvm_vcpu *vcpu, u8 vector, 3967 int type) 3968 { 3969 bool is_exception = (type == SVM_EXITINTINFO_TYPE_EXEPT); 3970 bool is_soft = (type == SVM_EXITINTINFO_TYPE_SOFT); 3971 struct vcpu_svm *svm = to_svm(vcpu); 3972 3973 /* 3974 * If NRIPS is enabled, KVM must snapshot the pre-VMRUN next_rip that's 3975 * associated with the original soft exception/interrupt. next_rip is 3976 * cleared on all exits that can occur while vectoring an event, so KVM 3977 * needs to manually set next_rip for re-injection. Unlike the !nrips 3978 * case below, this needs to be done if and only if KVM is re-injecting 3979 * the same event, i.e. if the event is a soft exception/interrupt, 3980 * otherwise next_rip is unused on VMRUN. 3981 */ 3982 if (nrips && (is_soft || (is_exception && kvm_exception_is_soft(vector))) && 3983 kvm_is_linear_rip(vcpu, svm->soft_int_old_rip + svm->soft_int_csbase)) 3984 svm->vmcb->control.next_rip = svm->soft_int_next_rip; 3985 /* 3986 * If NRIPS isn't enabled, KVM must manually advance RIP prior to 3987 * injecting the soft exception/interrupt. That advancement needs to 3988 * be unwound if vectoring didn't complete. Note, the new event may 3989 * not be the injected event, e.g. if KVM injected an INTn, the INTn 3990 * hit a #NP in the guest, and the #NP encountered a #PF, the #NP will 3991 * be the reported vectored event, but RIP still needs to be unwound. 3992 */ 3993 else if (!nrips && (is_soft || is_exception) && 3994 kvm_is_linear_rip(vcpu, svm->soft_int_next_rip + svm->soft_int_csbase)) 3995 kvm_rip_write(vcpu, svm->soft_int_old_rip); 3996 } 3997 3998 static void svm_complete_interrupts(struct kvm_vcpu *vcpu) 3999 { 4000 struct vcpu_svm *svm = to_svm(vcpu); 4001 u8 vector; 4002 int type; 4003 u32 exitintinfo = svm->vmcb->control.exit_int_info; 4004 bool nmi_l1_to_l2 = svm->nmi_l1_to_l2; 4005 bool soft_int_injected = svm->soft_int_injected; 4006 4007 svm->nmi_l1_to_l2 = false; 4008 svm->soft_int_injected = false; 4009 4010 /* 4011 * If we've made progress since setting awaiting_iret_completion, we've 4012 * executed an IRET and can allow NMI injection. 4013 */ 4014 if (svm->awaiting_iret_completion && 4015 kvm_rip_read(vcpu) != svm->nmi_iret_rip) { 4016 svm->awaiting_iret_completion = false; 4017 svm->nmi_masked = false; 4018 kvm_make_request(KVM_REQ_EVENT, vcpu); 4019 } 4020 4021 vcpu->arch.nmi_injected = false; 4022 kvm_clear_exception_queue(vcpu); 4023 kvm_clear_interrupt_queue(vcpu); 4024 4025 if (!(exitintinfo & SVM_EXITINTINFO_VALID)) 4026 return; 4027 4028 kvm_make_request(KVM_REQ_EVENT, vcpu); 4029 4030 vector = exitintinfo & SVM_EXITINTINFO_VEC_MASK; 4031 type = exitintinfo & SVM_EXITINTINFO_TYPE_MASK; 4032 4033 if (soft_int_injected) 4034 svm_complete_soft_interrupt(vcpu, vector, type); 4035 4036 switch (type) { 4037 case SVM_EXITINTINFO_TYPE_NMI: 4038 vcpu->arch.nmi_injected = true; 4039 svm->nmi_l1_to_l2 = nmi_l1_to_l2; 4040 break; 4041 case SVM_EXITINTINFO_TYPE_EXEPT: 4042 /* 4043 * Never re-inject a #VC exception. 4044 */ 4045 if (vector == X86_TRAP_VC) 4046 break; 4047 4048 if (exitintinfo & SVM_EXITINTINFO_VALID_ERR) { 4049 u32 err = svm->vmcb->control.exit_int_info_err; 4050 kvm_requeue_exception_e(vcpu, vector, err); 4051 4052 } else 4053 kvm_requeue_exception(vcpu, vector); 4054 break; 4055 case SVM_EXITINTINFO_TYPE_INTR: 4056 kvm_queue_interrupt(vcpu, vector, false); 4057 break; 4058 case SVM_EXITINTINFO_TYPE_SOFT: 4059 kvm_queue_interrupt(vcpu, vector, true); 4060 break; 4061 default: 4062 break; 4063 } 4064 4065 } 4066 4067 static void svm_cancel_injection(struct kvm_vcpu *vcpu) 4068 { 4069 struct vcpu_svm *svm = to_svm(vcpu); 4070 struct vmcb_control_area *control = &svm->vmcb->control; 4071 4072 control->exit_int_info = control->event_inj; 4073 control->exit_int_info_err = control->event_inj_err; 4074 control->event_inj = 0; 4075 svm_complete_interrupts(vcpu); 4076 } 4077 4078 static int svm_vcpu_pre_run(struct kvm_vcpu *vcpu) 4079 { 4080 return 1; 4081 } 4082 4083 static fastpath_t svm_exit_handlers_fastpath(struct kvm_vcpu *vcpu) 4084 { 4085 if (to_svm(vcpu)->vmcb->control.exit_code == SVM_EXIT_MSR && 4086 to_svm(vcpu)->vmcb->control.exit_info_1) 4087 return handle_fastpath_set_msr_irqoff(vcpu); 4088 4089 return EXIT_FASTPATH_NONE; 4090 } 4091 4092 static noinstr void svm_vcpu_enter_exit(struct kvm_vcpu *vcpu, bool spec_ctrl_intercepted) 4093 { 4094 struct vcpu_svm *svm = to_svm(vcpu); 4095 4096 guest_state_enter_irqoff(); 4097 4098 amd_clear_divider(); 4099 4100 if (sev_es_guest(vcpu->kvm)) 4101 __svm_sev_es_vcpu_run(svm, spec_ctrl_intercepted); 4102 else 4103 __svm_vcpu_run(svm, spec_ctrl_intercepted); 4104 4105 guest_state_exit_irqoff(); 4106 } 4107 4108 static __no_kcsan fastpath_t svm_vcpu_run(struct kvm_vcpu *vcpu) 4109 { 4110 struct vcpu_svm *svm = to_svm(vcpu); 4111 bool spec_ctrl_intercepted = msr_write_intercepted(vcpu, MSR_IA32_SPEC_CTRL); 4112 4113 trace_kvm_entry(vcpu); 4114 4115 svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX]; 4116 svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP]; 4117 svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP]; 4118 4119 /* 4120 * Disable singlestep if we're injecting an interrupt/exception. 4121 * We don't want our modified rflags to be pushed on the stack where 4122 * we might not be able to easily reset them if we disabled NMI 4123 * singlestep later. 4124 */ 4125 if (svm->nmi_singlestep && svm->vmcb->control.event_inj) { 4126 /* 4127 * Event injection happens before external interrupts cause a 4128 * vmexit and interrupts are disabled here, so smp_send_reschedule 4129 * is enough to force an immediate vmexit. 4130 */ 4131 disable_nmi_singlestep(svm); 4132 smp_send_reschedule(vcpu->cpu); 4133 } 4134 4135 pre_svm_run(vcpu); 4136 4137 sync_lapic_to_cr8(vcpu); 4138 4139 if (unlikely(svm->asid != svm->vmcb->control.asid)) { 4140 svm->vmcb->control.asid = svm->asid; 4141 vmcb_mark_dirty(svm->vmcb, VMCB_ASID); 4142 } 4143 svm->vmcb->save.cr2 = vcpu->arch.cr2; 4144 4145 svm_hv_update_vp_id(svm->vmcb, vcpu); 4146 4147 /* 4148 * Run with all-zero DR6 unless needed, so that we can get the exact cause 4149 * of a #DB. 4150 */ 4151 if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) 4152 svm_set_dr6(svm, vcpu->arch.dr6); 4153 else 4154 svm_set_dr6(svm, DR6_ACTIVE_LOW); 4155 4156 clgi(); 4157 kvm_load_guest_xsave_state(vcpu); 4158 4159 kvm_wait_lapic_expire(vcpu); 4160 4161 /* 4162 * If this vCPU has touched SPEC_CTRL, restore the guest's value if 4163 * it's non-zero. Since vmentry is serialising on affected CPUs, there 4164 * is no need to worry about the conditional branch over the wrmsr 4165 * being speculatively taken. 4166 */ 4167 if (!static_cpu_has(X86_FEATURE_V_SPEC_CTRL)) 4168 x86_spec_ctrl_set_guest(svm->virt_spec_ctrl); 4169 4170 svm_vcpu_enter_exit(vcpu, spec_ctrl_intercepted); 4171 4172 if (!static_cpu_has(X86_FEATURE_V_SPEC_CTRL)) 4173 x86_spec_ctrl_restore_host(svm->virt_spec_ctrl); 4174 4175 if (!sev_es_guest(vcpu->kvm)) { 4176 vcpu->arch.cr2 = svm->vmcb->save.cr2; 4177 vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax; 4178 vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp; 4179 vcpu->arch.regs[VCPU_REGS_RIP] = svm->vmcb->save.rip; 4180 } 4181 vcpu->arch.regs_dirty = 0; 4182 4183 if (unlikely(svm->vmcb->control.exit_code == SVM_EXIT_NMI)) 4184 kvm_before_interrupt(vcpu, KVM_HANDLING_NMI); 4185 4186 kvm_load_host_xsave_state(vcpu); 4187 stgi(); 4188 4189 /* Any pending NMI will happen here */ 4190 4191 if (unlikely(svm->vmcb->control.exit_code == SVM_EXIT_NMI)) 4192 kvm_after_interrupt(vcpu); 4193 4194 sync_cr8_to_lapic(vcpu); 4195 4196 svm->next_rip = 0; 4197 if (is_guest_mode(vcpu)) { 4198 nested_sync_control_from_vmcb02(svm); 4199 4200 /* Track VMRUNs that have made past consistency checking */ 4201 if (svm->nested.nested_run_pending && 4202 svm->vmcb->control.exit_code != SVM_EXIT_ERR) 4203 ++vcpu->stat.nested_run; 4204 4205 svm->nested.nested_run_pending = 0; 4206 } 4207 4208 svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING; 4209 vmcb_mark_all_clean(svm->vmcb); 4210 4211 /* if exit due to PF check for async PF */ 4212 if (svm->vmcb->control.exit_code == SVM_EXIT_EXCP_BASE + PF_VECTOR) 4213 vcpu->arch.apf.host_apf_flags = 4214 kvm_read_and_reset_apf_flags(); 4215 4216 vcpu->arch.regs_avail &= ~SVM_REGS_LAZY_LOAD_SET; 4217 4218 /* 4219 * We need to handle MC intercepts here before the vcpu has a chance to 4220 * change the physical cpu 4221 */ 4222 if (unlikely(svm->vmcb->control.exit_code == 4223 SVM_EXIT_EXCP_BASE + MC_VECTOR)) 4224 svm_handle_mce(vcpu); 4225 4226 trace_kvm_exit(vcpu, KVM_ISA_SVM); 4227 4228 svm_complete_interrupts(vcpu); 4229 4230 if (is_guest_mode(vcpu)) 4231 return EXIT_FASTPATH_NONE; 4232 4233 return svm_exit_handlers_fastpath(vcpu); 4234 } 4235 4236 static void svm_load_mmu_pgd(struct kvm_vcpu *vcpu, hpa_t root_hpa, 4237 int root_level) 4238 { 4239 struct vcpu_svm *svm = to_svm(vcpu); 4240 unsigned long cr3; 4241 4242 if (npt_enabled) { 4243 svm->vmcb->control.nested_cr3 = __sme_set(root_hpa); 4244 vmcb_mark_dirty(svm->vmcb, VMCB_NPT); 4245 4246 hv_track_root_tdp(vcpu, root_hpa); 4247 4248 cr3 = vcpu->arch.cr3; 4249 } else if (root_level >= PT64_ROOT_4LEVEL) { 4250 cr3 = __sme_set(root_hpa) | kvm_get_active_pcid(vcpu); 4251 } else { 4252 /* PCID in the guest should be impossible with a 32-bit MMU. */ 4253 WARN_ON_ONCE(kvm_get_active_pcid(vcpu)); 4254 cr3 = root_hpa; 4255 } 4256 4257 svm->vmcb->save.cr3 = cr3; 4258 vmcb_mark_dirty(svm->vmcb, VMCB_CR); 4259 } 4260 4261 static void 4262 svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall) 4263 { 4264 /* 4265 * Patch in the VMMCALL instruction: 4266 */ 4267 hypercall[0] = 0x0f; 4268 hypercall[1] = 0x01; 4269 hypercall[2] = 0xd9; 4270 } 4271 4272 /* 4273 * The kvm parameter can be NULL (module initialization, or invocation before 4274 * VM creation). Be sure to check the kvm parameter before using it. 4275 */ 4276 static bool svm_has_emulated_msr(struct kvm *kvm, u32 index) 4277 { 4278 switch (index) { 4279 case MSR_IA32_MCG_EXT_CTL: 4280 case KVM_FIRST_EMULATED_VMX_MSR ... KVM_LAST_EMULATED_VMX_MSR: 4281 return false; 4282 case MSR_IA32_SMBASE: 4283 if (!IS_ENABLED(CONFIG_KVM_SMM)) 4284 return false; 4285 /* SEV-ES guests do not support SMM, so report false */ 4286 if (kvm && sev_es_guest(kvm)) 4287 return false; 4288 break; 4289 default: 4290 break; 4291 } 4292 4293 return true; 4294 } 4295 4296 static void svm_vcpu_after_set_cpuid(struct kvm_vcpu *vcpu) 4297 { 4298 struct vcpu_svm *svm = to_svm(vcpu); 4299 4300 /* 4301 * SVM doesn't provide a way to disable just XSAVES in the guest, KVM 4302 * can only disable all variants of by disallowing CR4.OSXSAVE from 4303 * being set. As a result, if the host has XSAVE and XSAVES, and the 4304 * guest has XSAVE enabled, the guest can execute XSAVES without 4305 * faulting. Treat XSAVES as enabled in this case regardless of 4306 * whether it's advertised to the guest so that KVM context switches 4307 * XSS on VM-Enter/VM-Exit. Failure to do so would effectively give 4308 * the guest read/write access to the host's XSS. 4309 */ 4310 if (boot_cpu_has(X86_FEATURE_XSAVE) && 4311 boot_cpu_has(X86_FEATURE_XSAVES) && 4312 guest_cpuid_has(vcpu, X86_FEATURE_XSAVE)) 4313 kvm_governed_feature_set(vcpu, X86_FEATURE_XSAVES); 4314 4315 kvm_governed_feature_check_and_set(vcpu, X86_FEATURE_NRIPS); 4316 kvm_governed_feature_check_and_set(vcpu, X86_FEATURE_TSCRATEMSR); 4317 kvm_governed_feature_check_and_set(vcpu, X86_FEATURE_LBRV); 4318 4319 /* 4320 * Intercept VMLOAD if the vCPU mode is Intel in order to emulate that 4321 * VMLOAD drops bits 63:32 of SYSENTER (ignoring the fact that exposing 4322 * SVM on Intel is bonkers and extremely unlikely to work). 4323 */ 4324 if (!guest_cpuid_is_intel(vcpu)) 4325 kvm_governed_feature_check_and_set(vcpu, X86_FEATURE_V_VMSAVE_VMLOAD); 4326 4327 kvm_governed_feature_check_and_set(vcpu, X86_FEATURE_PAUSEFILTER); 4328 kvm_governed_feature_check_and_set(vcpu, X86_FEATURE_PFTHRESHOLD); 4329 kvm_governed_feature_check_and_set(vcpu, X86_FEATURE_VGIF); 4330 kvm_governed_feature_check_and_set(vcpu, X86_FEATURE_VNMI); 4331 4332 svm_recalc_instruction_intercepts(vcpu, svm); 4333 4334 if (boot_cpu_has(X86_FEATURE_IBPB)) 4335 set_msr_interception(vcpu, svm->msrpm, MSR_IA32_PRED_CMD, 0, 4336 !!guest_has_pred_cmd_msr(vcpu)); 4337 4338 if (boot_cpu_has(X86_FEATURE_FLUSH_L1D)) 4339 set_msr_interception(vcpu, svm->msrpm, MSR_IA32_FLUSH_CMD, 0, 4340 !!guest_cpuid_has(vcpu, X86_FEATURE_FLUSH_L1D)); 4341 4342 if (sev_guest(vcpu->kvm)) 4343 sev_vcpu_after_set_cpuid(svm); 4344 4345 init_vmcb_after_set_cpuid(vcpu); 4346 } 4347 4348 static bool svm_has_wbinvd_exit(void) 4349 { 4350 return true; 4351 } 4352 4353 #define PRE_EX(exit) { .exit_code = (exit), \ 4354 .stage = X86_ICPT_PRE_EXCEPT, } 4355 #define POST_EX(exit) { .exit_code = (exit), \ 4356 .stage = X86_ICPT_POST_EXCEPT, } 4357 #define POST_MEM(exit) { .exit_code = (exit), \ 4358 .stage = X86_ICPT_POST_MEMACCESS, } 4359 4360 static const struct __x86_intercept { 4361 u32 exit_code; 4362 enum x86_intercept_stage stage; 4363 } x86_intercept_map[] = { 4364 [x86_intercept_cr_read] = POST_EX(SVM_EXIT_READ_CR0), 4365 [x86_intercept_cr_write] = POST_EX(SVM_EXIT_WRITE_CR0), 4366 [x86_intercept_clts] = POST_EX(SVM_EXIT_WRITE_CR0), 4367 [x86_intercept_lmsw] = POST_EX(SVM_EXIT_WRITE_CR0), 4368 [x86_intercept_smsw] = POST_EX(SVM_EXIT_READ_CR0), 4369 [x86_intercept_dr_read] = POST_EX(SVM_EXIT_READ_DR0), 4370 [x86_intercept_dr_write] = POST_EX(SVM_EXIT_WRITE_DR0), 4371 [x86_intercept_sldt] = POST_EX(SVM_EXIT_LDTR_READ), 4372 [x86_intercept_str] = POST_EX(SVM_EXIT_TR_READ), 4373 [x86_intercept_lldt] = POST_EX(SVM_EXIT_LDTR_WRITE), 4374 [x86_intercept_ltr] = POST_EX(SVM_EXIT_TR_WRITE), 4375 [x86_intercept_sgdt] = POST_EX(SVM_EXIT_GDTR_READ), 4376 [x86_intercept_sidt] = POST_EX(SVM_EXIT_IDTR_READ), 4377 [x86_intercept_lgdt] = POST_EX(SVM_EXIT_GDTR_WRITE), 4378 [x86_intercept_lidt] = POST_EX(SVM_EXIT_IDTR_WRITE), 4379 [x86_intercept_vmrun] = POST_EX(SVM_EXIT_VMRUN), 4380 [x86_intercept_vmmcall] = POST_EX(SVM_EXIT_VMMCALL), 4381 [x86_intercept_vmload] = POST_EX(SVM_EXIT_VMLOAD), 4382 [x86_intercept_vmsave] = POST_EX(SVM_EXIT_VMSAVE), 4383 [x86_intercept_stgi] = POST_EX(SVM_EXIT_STGI), 4384 [x86_intercept_clgi] = POST_EX(SVM_EXIT_CLGI), 4385 [x86_intercept_skinit] = POST_EX(SVM_EXIT_SKINIT), 4386 [x86_intercept_invlpga] = POST_EX(SVM_EXIT_INVLPGA), 4387 [x86_intercept_rdtscp] = POST_EX(SVM_EXIT_RDTSCP), 4388 [x86_intercept_monitor] = POST_MEM(SVM_EXIT_MONITOR), 4389 [x86_intercept_mwait] = POST_EX(SVM_EXIT_MWAIT), 4390 [x86_intercept_invlpg] = POST_EX(SVM_EXIT_INVLPG), 4391 [x86_intercept_invd] = POST_EX(SVM_EXIT_INVD), 4392 [x86_intercept_wbinvd] = POST_EX(SVM_EXIT_WBINVD), 4393 [x86_intercept_wrmsr] = POST_EX(SVM_EXIT_MSR), 4394 [x86_intercept_rdtsc] = POST_EX(SVM_EXIT_RDTSC), 4395 [x86_intercept_rdmsr] = POST_EX(SVM_EXIT_MSR), 4396 [x86_intercept_rdpmc] = POST_EX(SVM_EXIT_RDPMC), 4397 [x86_intercept_cpuid] = PRE_EX(SVM_EXIT_CPUID), 4398 [x86_intercept_rsm] = PRE_EX(SVM_EXIT_RSM), 4399 [x86_intercept_pause] = PRE_EX(SVM_EXIT_PAUSE), 4400 [x86_intercept_pushf] = PRE_EX(SVM_EXIT_PUSHF), 4401 [x86_intercept_popf] = PRE_EX(SVM_EXIT_POPF), 4402 [x86_intercept_intn] = PRE_EX(SVM_EXIT_SWINT), 4403 [x86_intercept_iret] = PRE_EX(SVM_EXIT_IRET), 4404 [x86_intercept_icebp] = PRE_EX(SVM_EXIT_ICEBP), 4405 [x86_intercept_hlt] = POST_EX(SVM_EXIT_HLT), 4406 [x86_intercept_in] = POST_EX(SVM_EXIT_IOIO), 4407 [x86_intercept_ins] = POST_EX(SVM_EXIT_IOIO), 4408 [x86_intercept_out] = POST_EX(SVM_EXIT_IOIO), 4409 [x86_intercept_outs] = POST_EX(SVM_EXIT_IOIO), 4410 [x86_intercept_xsetbv] = PRE_EX(SVM_EXIT_XSETBV), 4411 }; 4412 4413 #undef PRE_EX 4414 #undef POST_EX 4415 #undef POST_MEM 4416 4417 static int svm_check_intercept(struct kvm_vcpu *vcpu, 4418 struct x86_instruction_info *info, 4419 enum x86_intercept_stage stage, 4420 struct x86_exception *exception) 4421 { 4422 struct vcpu_svm *svm = to_svm(vcpu); 4423 int vmexit, ret = X86EMUL_CONTINUE; 4424 struct __x86_intercept icpt_info; 4425 struct vmcb *vmcb = svm->vmcb; 4426 4427 if (info->intercept >= ARRAY_SIZE(x86_intercept_map)) 4428 goto out; 4429 4430 icpt_info = x86_intercept_map[info->intercept]; 4431 4432 if (stage != icpt_info.stage) 4433 goto out; 4434 4435 switch (icpt_info.exit_code) { 4436 case SVM_EXIT_READ_CR0: 4437 if (info->intercept == x86_intercept_cr_read) 4438 icpt_info.exit_code += info->modrm_reg; 4439 break; 4440 case SVM_EXIT_WRITE_CR0: { 4441 unsigned long cr0, val; 4442 4443 if (info->intercept == x86_intercept_cr_write) 4444 icpt_info.exit_code += info->modrm_reg; 4445 4446 if (icpt_info.exit_code != SVM_EXIT_WRITE_CR0 || 4447 info->intercept == x86_intercept_clts) 4448 break; 4449 4450 if (!(vmcb12_is_intercept(&svm->nested.ctl, 4451 INTERCEPT_SELECTIVE_CR0))) 4452 break; 4453 4454 cr0 = vcpu->arch.cr0 & ~SVM_CR0_SELECTIVE_MASK; 4455 val = info->src_val & ~SVM_CR0_SELECTIVE_MASK; 4456 4457 if (info->intercept == x86_intercept_lmsw) { 4458 cr0 &= 0xfUL; 4459 val &= 0xfUL; 4460 /* lmsw can't clear PE - catch this here */ 4461 if (cr0 & X86_CR0_PE) 4462 val |= X86_CR0_PE; 4463 } 4464 4465 if (cr0 ^ val) 4466 icpt_info.exit_code = SVM_EXIT_CR0_SEL_WRITE; 4467 4468 break; 4469 } 4470 case SVM_EXIT_READ_DR0: 4471 case SVM_EXIT_WRITE_DR0: 4472 icpt_info.exit_code += info->modrm_reg; 4473 break; 4474 case SVM_EXIT_MSR: 4475 if (info->intercept == x86_intercept_wrmsr) 4476 vmcb->control.exit_info_1 = 1; 4477 else 4478 vmcb->control.exit_info_1 = 0; 4479 break; 4480 case SVM_EXIT_PAUSE: 4481 /* 4482 * We get this for NOP only, but pause 4483 * is rep not, check this here 4484 */ 4485 if (info->rep_prefix != REPE_PREFIX) 4486 goto out; 4487 break; 4488 case SVM_EXIT_IOIO: { 4489 u64 exit_info; 4490 u32 bytes; 4491 4492 if (info->intercept == x86_intercept_in || 4493 info->intercept == x86_intercept_ins) { 4494 exit_info = ((info->src_val & 0xffff) << 16) | 4495 SVM_IOIO_TYPE_MASK; 4496 bytes = info->dst_bytes; 4497 } else { 4498 exit_info = (info->dst_val & 0xffff) << 16; 4499 bytes = info->src_bytes; 4500 } 4501 4502 if (info->intercept == x86_intercept_outs || 4503 info->intercept == x86_intercept_ins) 4504 exit_info |= SVM_IOIO_STR_MASK; 4505 4506 if (info->rep_prefix) 4507 exit_info |= SVM_IOIO_REP_MASK; 4508 4509 bytes = min(bytes, 4u); 4510 4511 exit_info |= bytes << SVM_IOIO_SIZE_SHIFT; 4512 4513 exit_info |= (u32)info->ad_bytes << (SVM_IOIO_ASIZE_SHIFT - 1); 4514 4515 vmcb->control.exit_info_1 = exit_info; 4516 vmcb->control.exit_info_2 = info->next_rip; 4517 4518 break; 4519 } 4520 default: 4521 break; 4522 } 4523 4524 /* TODO: Advertise NRIPS to guest hypervisor unconditionally */ 4525 if (static_cpu_has(X86_FEATURE_NRIPS)) 4526 vmcb->control.next_rip = info->next_rip; 4527 vmcb->control.exit_code = icpt_info.exit_code; 4528 vmexit = nested_svm_exit_handled(svm); 4529 4530 ret = (vmexit == NESTED_EXIT_DONE) ? X86EMUL_INTERCEPTED 4531 : X86EMUL_CONTINUE; 4532 4533 out: 4534 return ret; 4535 } 4536 4537 static void svm_handle_exit_irqoff(struct kvm_vcpu *vcpu) 4538 { 4539 if (to_svm(vcpu)->vmcb->control.exit_code == SVM_EXIT_INTR) 4540 vcpu->arch.at_instruction_boundary = true; 4541 } 4542 4543 static void svm_sched_in(struct kvm_vcpu *vcpu, int cpu) 4544 { 4545 if (!kvm_pause_in_guest(vcpu->kvm)) 4546 shrink_ple_window(vcpu); 4547 } 4548 4549 static void svm_setup_mce(struct kvm_vcpu *vcpu) 4550 { 4551 /* [63:9] are reserved. */ 4552 vcpu->arch.mcg_cap &= 0x1ff; 4553 } 4554 4555 #ifdef CONFIG_KVM_SMM 4556 bool svm_smi_blocked(struct kvm_vcpu *vcpu) 4557 { 4558 struct vcpu_svm *svm = to_svm(vcpu); 4559 4560 /* Per APM Vol.2 15.22.2 "Response to SMI" */ 4561 if (!gif_set(svm)) 4562 return true; 4563 4564 return is_smm(vcpu); 4565 } 4566 4567 static int svm_smi_allowed(struct kvm_vcpu *vcpu, bool for_injection) 4568 { 4569 struct vcpu_svm *svm = to_svm(vcpu); 4570 if (svm->nested.nested_run_pending) 4571 return -EBUSY; 4572 4573 if (svm_smi_blocked(vcpu)) 4574 return 0; 4575 4576 /* An SMI must not be injected into L2 if it's supposed to VM-Exit. */ 4577 if (for_injection && is_guest_mode(vcpu) && nested_exit_on_smi(svm)) 4578 return -EBUSY; 4579 4580 return 1; 4581 } 4582 4583 static int svm_enter_smm(struct kvm_vcpu *vcpu, union kvm_smram *smram) 4584 { 4585 struct vcpu_svm *svm = to_svm(vcpu); 4586 struct kvm_host_map map_save; 4587 int ret; 4588 4589 if (!is_guest_mode(vcpu)) 4590 return 0; 4591 4592 /* 4593 * 32-bit SMRAM format doesn't preserve EFER and SVM state. Userspace is 4594 * responsible for ensuring nested SVM and SMIs are mutually exclusive. 4595 */ 4596 4597 if (!guest_cpuid_has(vcpu, X86_FEATURE_LM)) 4598 return 1; 4599 4600 smram->smram64.svm_guest_flag = 1; 4601 smram->smram64.svm_guest_vmcb_gpa = svm->nested.vmcb12_gpa; 4602 4603 svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX]; 4604 svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP]; 4605 svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP]; 4606 4607 ret = nested_svm_simple_vmexit(svm, SVM_EXIT_SW); 4608 if (ret) 4609 return ret; 4610 4611 /* 4612 * KVM uses VMCB01 to store L1 host state while L2 runs but 4613 * VMCB01 is going to be used during SMM and thus the state will 4614 * be lost. Temporary save non-VMLOAD/VMSAVE state to the host save 4615 * area pointed to by MSR_VM_HSAVE_PA. APM guarantees that the 4616 * format of the area is identical to guest save area offsetted 4617 * by 0x400 (matches the offset of 'struct vmcb_save_area' 4618 * within 'struct vmcb'). Note: HSAVE area may also be used by 4619 * L1 hypervisor to save additional host context (e.g. KVM does 4620 * that, see svm_prepare_switch_to_guest()) which must be 4621 * preserved. 4622 */ 4623 if (kvm_vcpu_map(vcpu, gpa_to_gfn(svm->nested.hsave_msr), &map_save)) 4624 return 1; 4625 4626 BUILD_BUG_ON(offsetof(struct vmcb, save) != 0x400); 4627 4628 svm_copy_vmrun_state(map_save.hva + 0x400, 4629 &svm->vmcb01.ptr->save); 4630 4631 kvm_vcpu_unmap(vcpu, &map_save, true); 4632 return 0; 4633 } 4634 4635 static int svm_leave_smm(struct kvm_vcpu *vcpu, const union kvm_smram *smram) 4636 { 4637 struct vcpu_svm *svm = to_svm(vcpu); 4638 struct kvm_host_map map, map_save; 4639 struct vmcb *vmcb12; 4640 int ret; 4641 4642 const struct kvm_smram_state_64 *smram64 = &smram->smram64; 4643 4644 if (!guest_cpuid_has(vcpu, X86_FEATURE_LM)) 4645 return 0; 4646 4647 /* Non-zero if SMI arrived while vCPU was in guest mode. */ 4648 if (!smram64->svm_guest_flag) 4649 return 0; 4650 4651 if (!guest_cpuid_has(vcpu, X86_FEATURE_SVM)) 4652 return 1; 4653 4654 if (!(smram64->efer & EFER_SVME)) 4655 return 1; 4656 4657 if (kvm_vcpu_map(vcpu, gpa_to_gfn(smram64->svm_guest_vmcb_gpa), &map)) 4658 return 1; 4659 4660 ret = 1; 4661 if (kvm_vcpu_map(vcpu, gpa_to_gfn(svm->nested.hsave_msr), &map_save)) 4662 goto unmap_map; 4663 4664 if (svm_allocate_nested(svm)) 4665 goto unmap_save; 4666 4667 /* 4668 * Restore L1 host state from L1 HSAVE area as VMCB01 was 4669 * used during SMM (see svm_enter_smm()) 4670 */ 4671 4672 svm_copy_vmrun_state(&svm->vmcb01.ptr->save, map_save.hva + 0x400); 4673 4674 /* 4675 * Enter the nested guest now 4676 */ 4677 4678 vmcb_mark_all_dirty(svm->vmcb01.ptr); 4679 4680 vmcb12 = map.hva; 4681 nested_copy_vmcb_control_to_cache(svm, &vmcb12->control); 4682 nested_copy_vmcb_save_to_cache(svm, &vmcb12->save); 4683 ret = enter_svm_guest_mode(vcpu, smram64->svm_guest_vmcb_gpa, vmcb12, false); 4684 4685 if (ret) 4686 goto unmap_save; 4687 4688 svm->nested.nested_run_pending = 1; 4689 4690 unmap_save: 4691 kvm_vcpu_unmap(vcpu, &map_save, true); 4692 unmap_map: 4693 kvm_vcpu_unmap(vcpu, &map, true); 4694 return ret; 4695 } 4696 4697 static void svm_enable_smi_window(struct kvm_vcpu *vcpu) 4698 { 4699 struct vcpu_svm *svm = to_svm(vcpu); 4700 4701 if (!gif_set(svm)) { 4702 if (vgif) 4703 svm_set_intercept(svm, INTERCEPT_STGI); 4704 /* STGI will cause a vm exit */ 4705 } else { 4706 /* We must be in SMM; RSM will cause a vmexit anyway. */ 4707 } 4708 } 4709 #endif 4710 4711 static int svm_check_emulate_instruction(struct kvm_vcpu *vcpu, int emul_type, 4712 void *insn, int insn_len) 4713 { 4714 bool smep, smap, is_user; 4715 u64 error_code; 4716 4717 /* Emulation is always possible when KVM has access to all guest state. */ 4718 if (!sev_guest(vcpu->kvm)) 4719 return X86EMUL_CONTINUE; 4720 4721 /* #UD and #GP should never be intercepted for SEV guests. */ 4722 WARN_ON_ONCE(emul_type & (EMULTYPE_TRAP_UD | 4723 EMULTYPE_TRAP_UD_FORCED | 4724 EMULTYPE_VMWARE_GP)); 4725 4726 /* 4727 * Emulation is impossible for SEV-ES guests as KVM doesn't have access 4728 * to guest register state. 4729 */ 4730 if (sev_es_guest(vcpu->kvm)) 4731 return X86EMUL_RETRY_INSTR; 4732 4733 /* 4734 * Emulation is possible if the instruction is already decoded, e.g. 4735 * when completing I/O after returning from userspace. 4736 */ 4737 if (emul_type & EMULTYPE_NO_DECODE) 4738 return X86EMUL_CONTINUE; 4739 4740 /* 4741 * Emulation is possible for SEV guests if and only if a prefilled 4742 * buffer containing the bytes of the intercepted instruction is 4743 * available. SEV guest memory is encrypted with a guest specific key 4744 * and cannot be decrypted by KVM, i.e. KVM would read cyphertext and 4745 * decode garbage. 4746 * 4747 * If KVM is NOT trying to simply skip an instruction, inject #UD if 4748 * KVM reached this point without an instruction buffer. In practice, 4749 * this path should never be hit by a well-behaved guest, e.g. KVM 4750 * doesn't intercept #UD or #GP for SEV guests, but this path is still 4751 * theoretically reachable, e.g. via unaccelerated fault-like AVIC 4752 * access, and needs to be handled by KVM to avoid putting the guest 4753 * into an infinite loop. Injecting #UD is somewhat arbitrary, but 4754 * its the least awful option given lack of insight into the guest. 4755 * 4756 * If KVM is trying to skip an instruction, simply resume the guest. 4757 * If a #NPF occurs while the guest is vectoring an INT3/INTO, then KVM 4758 * will attempt to re-inject the INT3/INTO and skip the instruction. 4759 * In that scenario, retrying the INT3/INTO and hoping the guest will 4760 * make forward progress is the only option that has a chance of 4761 * success (and in practice it will work the vast majority of the time). 4762 */ 4763 if (unlikely(!insn)) { 4764 if (emul_type & EMULTYPE_SKIP) 4765 return X86EMUL_UNHANDLEABLE; 4766 4767 kvm_queue_exception(vcpu, UD_VECTOR); 4768 return X86EMUL_PROPAGATE_FAULT; 4769 } 4770 4771 /* 4772 * Emulate for SEV guests if the insn buffer is not empty. The buffer 4773 * will be empty if the DecodeAssist microcode cannot fetch bytes for 4774 * the faulting instruction because the code fetch itself faulted, e.g. 4775 * the guest attempted to fetch from emulated MMIO or a guest page 4776 * table used to translate CS:RIP resides in emulated MMIO. 4777 */ 4778 if (likely(insn_len)) 4779 return X86EMUL_CONTINUE; 4780 4781 /* 4782 * Detect and workaround Errata 1096 Fam_17h_00_0Fh. 4783 * 4784 * Errata: 4785 * When CPU raises #NPF on guest data access and vCPU CR4.SMAP=1, it is 4786 * possible that CPU microcode implementing DecodeAssist will fail to 4787 * read guest memory at CS:RIP and vmcb.GuestIntrBytes will incorrectly 4788 * be '0'. This happens because microcode reads CS:RIP using a _data_ 4789 * loap uop with CPL=0 privileges. If the load hits a SMAP #PF, ucode 4790 * gives up and does not fill the instruction bytes buffer. 4791 * 4792 * As above, KVM reaches this point iff the VM is an SEV guest, the CPU 4793 * supports DecodeAssist, a #NPF was raised, KVM's page fault handler 4794 * triggered emulation (e.g. for MMIO), and the CPU returned 0 in the 4795 * GuestIntrBytes field of the VMCB. 4796 * 4797 * This does _not_ mean that the erratum has been encountered, as the 4798 * DecodeAssist will also fail if the load for CS:RIP hits a legitimate 4799 * #PF, e.g. if the guest attempt to execute from emulated MMIO and 4800 * encountered a reserved/not-present #PF. 4801 * 4802 * To hit the erratum, the following conditions must be true: 4803 * 1. CR4.SMAP=1 (obviously). 4804 * 2. CR4.SMEP=0 || CPL=3. If SMEP=1 and CPL<3, the erratum cannot 4805 * have been hit as the guest would have encountered a SMEP 4806 * violation #PF, not a #NPF. 4807 * 3. The #NPF is not due to a code fetch, in which case failure to 4808 * retrieve the instruction bytes is legitimate (see abvoe). 4809 * 4810 * In addition, don't apply the erratum workaround if the #NPF occurred 4811 * while translating guest page tables (see below). 4812 */ 4813 error_code = to_svm(vcpu)->vmcb->control.exit_info_1; 4814 if (error_code & (PFERR_GUEST_PAGE_MASK | PFERR_FETCH_MASK)) 4815 goto resume_guest; 4816 4817 smep = kvm_is_cr4_bit_set(vcpu, X86_CR4_SMEP); 4818 smap = kvm_is_cr4_bit_set(vcpu, X86_CR4_SMAP); 4819 is_user = svm_get_cpl(vcpu) == 3; 4820 if (smap && (!smep || is_user)) { 4821 pr_err_ratelimited("SEV Guest triggered AMD Erratum 1096\n"); 4822 4823 /* 4824 * If the fault occurred in userspace, arbitrarily inject #GP 4825 * to avoid killing the guest and to hopefully avoid confusing 4826 * the guest kernel too much, e.g. injecting #PF would not be 4827 * coherent with respect to the guest's page tables. Request 4828 * triple fault if the fault occurred in the kernel as there's 4829 * no fault that KVM can inject without confusing the guest. 4830 * In practice, the triple fault is moot as no sane SEV kernel 4831 * will execute from user memory while also running with SMAP=1. 4832 */ 4833 if (is_user) 4834 kvm_inject_gp(vcpu, 0); 4835 else 4836 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); 4837 return X86EMUL_PROPAGATE_FAULT; 4838 } 4839 4840 resume_guest: 4841 /* 4842 * If the erratum was not hit, simply resume the guest and let it fault 4843 * again. While awful, e.g. the vCPU may get stuck in an infinite loop 4844 * if the fault is at CPL=0, it's the lesser of all evils. Exiting to 4845 * userspace will kill the guest, and letting the emulator read garbage 4846 * will yield random behavior and potentially corrupt the guest. 4847 * 4848 * Simply resuming the guest is technically not a violation of the SEV 4849 * architecture. AMD's APM states that all code fetches and page table 4850 * accesses for SEV guest are encrypted, regardless of the C-Bit. The 4851 * APM also states that encrypted accesses to MMIO are "ignored", but 4852 * doesn't explicitly define "ignored", i.e. doing nothing and letting 4853 * the guest spin is technically "ignoring" the access. 4854 */ 4855 return X86EMUL_RETRY_INSTR; 4856 } 4857 4858 static bool svm_apic_init_signal_blocked(struct kvm_vcpu *vcpu) 4859 { 4860 struct vcpu_svm *svm = to_svm(vcpu); 4861 4862 return !gif_set(svm); 4863 } 4864 4865 static void svm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector) 4866 { 4867 if (!sev_es_guest(vcpu->kvm)) 4868 return kvm_vcpu_deliver_sipi_vector(vcpu, vector); 4869 4870 sev_vcpu_deliver_sipi_vector(vcpu, vector); 4871 } 4872 4873 static void svm_vm_destroy(struct kvm *kvm) 4874 { 4875 avic_vm_destroy(kvm); 4876 sev_vm_destroy(kvm); 4877 } 4878 4879 static int svm_vm_init(struct kvm *kvm) 4880 { 4881 if (!pause_filter_count || !pause_filter_thresh) 4882 kvm->arch.pause_in_guest = true; 4883 4884 if (enable_apicv) { 4885 int ret = avic_vm_init(kvm); 4886 if (ret) 4887 return ret; 4888 } 4889 4890 return 0; 4891 } 4892 4893 static struct kvm_x86_ops svm_x86_ops __initdata = { 4894 .name = KBUILD_MODNAME, 4895 4896 .check_processor_compatibility = svm_check_processor_compat, 4897 4898 .hardware_unsetup = svm_hardware_unsetup, 4899 .hardware_enable = svm_hardware_enable, 4900 .hardware_disable = svm_hardware_disable, 4901 .has_emulated_msr = svm_has_emulated_msr, 4902 4903 .vcpu_create = svm_vcpu_create, 4904 .vcpu_free = svm_vcpu_free, 4905 .vcpu_reset = svm_vcpu_reset, 4906 4907 .vm_size = sizeof(struct kvm_svm), 4908 .vm_init = svm_vm_init, 4909 .vm_destroy = svm_vm_destroy, 4910 4911 .prepare_switch_to_guest = svm_prepare_switch_to_guest, 4912 .vcpu_load = svm_vcpu_load, 4913 .vcpu_put = svm_vcpu_put, 4914 .vcpu_blocking = avic_vcpu_blocking, 4915 .vcpu_unblocking = avic_vcpu_unblocking, 4916 4917 .update_exception_bitmap = svm_update_exception_bitmap, 4918 .get_msr_feature = svm_get_msr_feature, 4919 .get_msr = svm_get_msr, 4920 .set_msr = svm_set_msr, 4921 .get_segment_base = svm_get_segment_base, 4922 .get_segment = svm_get_segment, 4923 .set_segment = svm_set_segment, 4924 .get_cpl = svm_get_cpl, 4925 .get_cs_db_l_bits = svm_get_cs_db_l_bits, 4926 .is_valid_cr0 = svm_is_valid_cr0, 4927 .set_cr0 = svm_set_cr0, 4928 .post_set_cr3 = sev_post_set_cr3, 4929 .is_valid_cr4 = svm_is_valid_cr4, 4930 .set_cr4 = svm_set_cr4, 4931 .set_efer = svm_set_efer, 4932 .get_idt = svm_get_idt, 4933 .set_idt = svm_set_idt, 4934 .get_gdt = svm_get_gdt, 4935 .set_gdt = svm_set_gdt, 4936 .set_dr7 = svm_set_dr7, 4937 .sync_dirty_debug_regs = svm_sync_dirty_debug_regs, 4938 .cache_reg = svm_cache_reg, 4939 .get_rflags = svm_get_rflags, 4940 .set_rflags = svm_set_rflags, 4941 .get_if_flag = svm_get_if_flag, 4942 4943 .flush_tlb_all = svm_flush_tlb_all, 4944 .flush_tlb_current = svm_flush_tlb_current, 4945 .flush_tlb_gva = svm_flush_tlb_gva, 4946 .flush_tlb_guest = svm_flush_tlb_asid, 4947 4948 .vcpu_pre_run = svm_vcpu_pre_run, 4949 .vcpu_run = svm_vcpu_run, 4950 .handle_exit = svm_handle_exit, 4951 .skip_emulated_instruction = svm_skip_emulated_instruction, 4952 .update_emulated_instruction = NULL, 4953 .set_interrupt_shadow = svm_set_interrupt_shadow, 4954 .get_interrupt_shadow = svm_get_interrupt_shadow, 4955 .patch_hypercall = svm_patch_hypercall, 4956 .inject_irq = svm_inject_irq, 4957 .inject_nmi = svm_inject_nmi, 4958 .is_vnmi_pending = svm_is_vnmi_pending, 4959 .set_vnmi_pending = svm_set_vnmi_pending, 4960 .inject_exception = svm_inject_exception, 4961 .cancel_injection = svm_cancel_injection, 4962 .interrupt_allowed = svm_interrupt_allowed, 4963 .nmi_allowed = svm_nmi_allowed, 4964 .get_nmi_mask = svm_get_nmi_mask, 4965 .set_nmi_mask = svm_set_nmi_mask, 4966 .enable_nmi_window = svm_enable_nmi_window, 4967 .enable_irq_window = svm_enable_irq_window, 4968 .update_cr8_intercept = svm_update_cr8_intercept, 4969 .set_virtual_apic_mode = avic_refresh_virtual_apic_mode, 4970 .refresh_apicv_exec_ctrl = avic_refresh_apicv_exec_ctrl, 4971 .apicv_post_state_restore = avic_apicv_post_state_restore, 4972 .required_apicv_inhibits = AVIC_REQUIRED_APICV_INHIBITS, 4973 4974 .get_exit_info = svm_get_exit_info, 4975 4976 .vcpu_after_set_cpuid = svm_vcpu_after_set_cpuid, 4977 4978 .has_wbinvd_exit = svm_has_wbinvd_exit, 4979 4980 .get_l2_tsc_offset = svm_get_l2_tsc_offset, 4981 .get_l2_tsc_multiplier = svm_get_l2_tsc_multiplier, 4982 .write_tsc_offset = svm_write_tsc_offset, 4983 .write_tsc_multiplier = svm_write_tsc_multiplier, 4984 4985 .load_mmu_pgd = svm_load_mmu_pgd, 4986 4987 .check_intercept = svm_check_intercept, 4988 .handle_exit_irqoff = svm_handle_exit_irqoff, 4989 4990 .request_immediate_exit = __kvm_request_immediate_exit, 4991 4992 .sched_in = svm_sched_in, 4993 4994 .nested_ops = &svm_nested_ops, 4995 4996 .deliver_interrupt = svm_deliver_interrupt, 4997 .pi_update_irte = avic_pi_update_irte, 4998 .setup_mce = svm_setup_mce, 4999 5000 #ifdef CONFIG_KVM_SMM 5001 .smi_allowed = svm_smi_allowed, 5002 .enter_smm = svm_enter_smm, 5003 .leave_smm = svm_leave_smm, 5004 .enable_smi_window = svm_enable_smi_window, 5005 #endif 5006 5007 .mem_enc_ioctl = sev_mem_enc_ioctl, 5008 .mem_enc_register_region = sev_mem_enc_register_region, 5009 .mem_enc_unregister_region = sev_mem_enc_unregister_region, 5010 .guest_memory_reclaimed = sev_guest_memory_reclaimed, 5011 5012 .vm_copy_enc_context_from = sev_vm_copy_enc_context_from, 5013 .vm_move_enc_context_from = sev_vm_move_enc_context_from, 5014 5015 .check_emulate_instruction = svm_check_emulate_instruction, 5016 5017 .apic_init_signal_blocked = svm_apic_init_signal_blocked, 5018 5019 .msr_filter_changed = svm_msr_filter_changed, 5020 .complete_emulated_msr = svm_complete_emulated_msr, 5021 5022 .vcpu_deliver_sipi_vector = svm_vcpu_deliver_sipi_vector, 5023 .vcpu_get_apicv_inhibit_reasons = avic_vcpu_get_apicv_inhibit_reasons, 5024 }; 5025 5026 /* 5027 * The default MMIO mask is a single bit (excluding the present bit), 5028 * which could conflict with the memory encryption bit. Check for 5029 * memory encryption support and override the default MMIO mask if 5030 * memory encryption is enabled. 5031 */ 5032 static __init void svm_adjust_mmio_mask(void) 5033 { 5034 unsigned int enc_bit, mask_bit; 5035 u64 msr, mask; 5036 5037 /* If there is no memory encryption support, use existing mask */ 5038 if (cpuid_eax(0x80000000) < 0x8000001f) 5039 return; 5040 5041 /* If memory encryption is not enabled, use existing mask */ 5042 rdmsrl(MSR_AMD64_SYSCFG, msr); 5043 if (!(msr & MSR_AMD64_SYSCFG_MEM_ENCRYPT)) 5044 return; 5045 5046 enc_bit = cpuid_ebx(0x8000001f) & 0x3f; 5047 mask_bit = boot_cpu_data.x86_phys_bits; 5048 5049 /* Increment the mask bit if it is the same as the encryption bit */ 5050 if (enc_bit == mask_bit) 5051 mask_bit++; 5052 5053 /* 5054 * If the mask bit location is below 52, then some bits above the 5055 * physical addressing limit will always be reserved, so use the 5056 * rsvd_bits() function to generate the mask. This mask, along with 5057 * the present bit, will be used to generate a page fault with 5058 * PFER.RSV = 1. 5059 * 5060 * If the mask bit location is 52 (or above), then clear the mask. 5061 */ 5062 mask = (mask_bit < 52) ? rsvd_bits(mask_bit, 51) | PT_PRESENT_MASK : 0; 5063 5064 kvm_mmu_set_mmio_spte_mask(mask, mask, PT_WRITABLE_MASK | PT_USER_MASK); 5065 } 5066 5067 static __init void svm_set_cpu_caps(void) 5068 { 5069 kvm_set_cpu_caps(); 5070 5071 kvm_caps.supported_perf_cap = 0; 5072 kvm_caps.supported_xss = 0; 5073 5074 /* CPUID 0x80000001 and 0x8000000A (SVM features) */ 5075 if (nested) { 5076 kvm_cpu_cap_set(X86_FEATURE_SVM); 5077 kvm_cpu_cap_set(X86_FEATURE_VMCBCLEAN); 5078 5079 if (nrips) 5080 kvm_cpu_cap_set(X86_FEATURE_NRIPS); 5081 5082 if (npt_enabled) 5083 kvm_cpu_cap_set(X86_FEATURE_NPT); 5084 5085 if (tsc_scaling) 5086 kvm_cpu_cap_set(X86_FEATURE_TSCRATEMSR); 5087 5088 if (vls) 5089 kvm_cpu_cap_set(X86_FEATURE_V_VMSAVE_VMLOAD); 5090 if (lbrv) 5091 kvm_cpu_cap_set(X86_FEATURE_LBRV); 5092 5093 if (boot_cpu_has(X86_FEATURE_PAUSEFILTER)) 5094 kvm_cpu_cap_set(X86_FEATURE_PAUSEFILTER); 5095 5096 if (boot_cpu_has(X86_FEATURE_PFTHRESHOLD)) 5097 kvm_cpu_cap_set(X86_FEATURE_PFTHRESHOLD); 5098 5099 if (vgif) 5100 kvm_cpu_cap_set(X86_FEATURE_VGIF); 5101 5102 if (vnmi) 5103 kvm_cpu_cap_set(X86_FEATURE_VNMI); 5104 5105 /* Nested VM can receive #VMEXIT instead of triggering #GP */ 5106 kvm_cpu_cap_set(X86_FEATURE_SVME_ADDR_CHK); 5107 } 5108 5109 /* CPUID 0x80000008 */ 5110 if (boot_cpu_has(X86_FEATURE_LS_CFG_SSBD) || 5111 boot_cpu_has(X86_FEATURE_AMD_SSBD)) 5112 kvm_cpu_cap_set(X86_FEATURE_VIRT_SSBD); 5113 5114 if (enable_pmu) { 5115 /* 5116 * Enumerate support for PERFCTR_CORE if and only if KVM has 5117 * access to enough counters to virtualize "core" support, 5118 * otherwise limit vPMU support to the legacy number of counters. 5119 */ 5120 if (kvm_pmu_cap.num_counters_gp < AMD64_NUM_COUNTERS_CORE) 5121 kvm_pmu_cap.num_counters_gp = min(AMD64_NUM_COUNTERS, 5122 kvm_pmu_cap.num_counters_gp); 5123 else 5124 kvm_cpu_cap_check_and_set(X86_FEATURE_PERFCTR_CORE); 5125 5126 if (kvm_pmu_cap.version != 2 || 5127 !kvm_cpu_cap_has(X86_FEATURE_PERFCTR_CORE)) 5128 kvm_cpu_cap_clear(X86_FEATURE_PERFMON_V2); 5129 } 5130 5131 /* CPUID 0x8000001F (SME/SEV features) */ 5132 sev_set_cpu_caps(); 5133 } 5134 5135 static __init int svm_hardware_setup(void) 5136 { 5137 int cpu; 5138 struct page *iopm_pages; 5139 void *iopm_va; 5140 int r; 5141 unsigned int order = get_order(IOPM_SIZE); 5142 5143 /* 5144 * NX is required for shadow paging and for NPT if the NX huge pages 5145 * mitigation is enabled. 5146 */ 5147 if (!boot_cpu_has(X86_FEATURE_NX)) { 5148 pr_err_ratelimited("NX (Execute Disable) not supported\n"); 5149 return -EOPNOTSUPP; 5150 } 5151 kvm_enable_efer_bits(EFER_NX); 5152 5153 iopm_pages = alloc_pages(GFP_KERNEL, order); 5154 5155 if (!iopm_pages) 5156 return -ENOMEM; 5157 5158 iopm_va = page_address(iopm_pages); 5159 memset(iopm_va, 0xff, PAGE_SIZE * (1 << order)); 5160 iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT; 5161 5162 init_msrpm_offsets(); 5163 5164 kvm_caps.supported_xcr0 &= ~(XFEATURE_MASK_BNDREGS | 5165 XFEATURE_MASK_BNDCSR); 5166 5167 if (boot_cpu_has(X86_FEATURE_FXSR_OPT)) 5168 kvm_enable_efer_bits(EFER_FFXSR); 5169 5170 if (tsc_scaling) { 5171 if (!boot_cpu_has(X86_FEATURE_TSCRATEMSR)) { 5172 tsc_scaling = false; 5173 } else { 5174 pr_info("TSC scaling supported\n"); 5175 kvm_caps.has_tsc_control = true; 5176 } 5177 } 5178 kvm_caps.max_tsc_scaling_ratio = SVM_TSC_RATIO_MAX; 5179 kvm_caps.tsc_scaling_ratio_frac_bits = 32; 5180 5181 tsc_aux_uret_slot = kvm_add_user_return_msr(MSR_TSC_AUX); 5182 5183 if (boot_cpu_has(X86_FEATURE_AUTOIBRS)) 5184 kvm_enable_efer_bits(EFER_AUTOIBRS); 5185 5186 /* Check for pause filtering support */ 5187 if (!boot_cpu_has(X86_FEATURE_PAUSEFILTER)) { 5188 pause_filter_count = 0; 5189 pause_filter_thresh = 0; 5190 } else if (!boot_cpu_has(X86_FEATURE_PFTHRESHOLD)) { 5191 pause_filter_thresh = 0; 5192 } 5193 5194 if (nested) { 5195 pr_info("Nested Virtualization enabled\n"); 5196 kvm_enable_efer_bits(EFER_SVME | EFER_LMSLE); 5197 } 5198 5199 /* 5200 * KVM's MMU doesn't support using 2-level paging for itself, and thus 5201 * NPT isn't supported if the host is using 2-level paging since host 5202 * CR4 is unchanged on VMRUN. 5203 */ 5204 if (!IS_ENABLED(CONFIG_X86_64) && !IS_ENABLED(CONFIG_X86_PAE)) 5205 npt_enabled = false; 5206 5207 if (!boot_cpu_has(X86_FEATURE_NPT)) 5208 npt_enabled = false; 5209 5210 /* Force VM NPT level equal to the host's paging level */ 5211 kvm_configure_mmu(npt_enabled, get_npt_level(), 5212 get_npt_level(), PG_LEVEL_1G); 5213 pr_info("Nested Paging %sabled\n", npt_enabled ? "en" : "dis"); 5214 5215 /* Setup shadow_me_value and shadow_me_mask */ 5216 kvm_mmu_set_me_spte_mask(sme_me_mask, sme_me_mask); 5217 5218 svm_adjust_mmio_mask(); 5219 5220 nrips = nrips && boot_cpu_has(X86_FEATURE_NRIPS); 5221 5222 /* 5223 * Note, SEV setup consumes npt_enabled and enable_mmio_caching (which 5224 * may be modified by svm_adjust_mmio_mask()), as well as nrips. 5225 */ 5226 sev_hardware_setup(); 5227 5228 svm_hv_hardware_setup(); 5229 5230 for_each_possible_cpu(cpu) { 5231 r = svm_cpu_init(cpu); 5232 if (r) 5233 goto err; 5234 } 5235 5236 enable_apicv = avic = avic && avic_hardware_setup(); 5237 5238 if (!enable_apicv) { 5239 svm_x86_ops.vcpu_blocking = NULL; 5240 svm_x86_ops.vcpu_unblocking = NULL; 5241 svm_x86_ops.vcpu_get_apicv_inhibit_reasons = NULL; 5242 } else if (!x2avic_enabled) { 5243 svm_x86_ops.allow_apicv_in_x2apic_without_x2apic_virtualization = true; 5244 } 5245 5246 if (vls) { 5247 if (!npt_enabled || 5248 !boot_cpu_has(X86_FEATURE_V_VMSAVE_VMLOAD) || 5249 !IS_ENABLED(CONFIG_X86_64)) { 5250 vls = false; 5251 } else { 5252 pr_info("Virtual VMLOAD VMSAVE supported\n"); 5253 } 5254 } 5255 5256 if (boot_cpu_has(X86_FEATURE_SVME_ADDR_CHK)) 5257 svm_gp_erratum_intercept = false; 5258 5259 if (vgif) { 5260 if (!boot_cpu_has(X86_FEATURE_VGIF)) 5261 vgif = false; 5262 else 5263 pr_info("Virtual GIF supported\n"); 5264 } 5265 5266 vnmi = vgif && vnmi && boot_cpu_has(X86_FEATURE_VNMI); 5267 if (vnmi) 5268 pr_info("Virtual NMI enabled\n"); 5269 5270 if (!vnmi) { 5271 svm_x86_ops.is_vnmi_pending = NULL; 5272 svm_x86_ops.set_vnmi_pending = NULL; 5273 } 5274 5275 5276 if (lbrv) { 5277 if (!boot_cpu_has(X86_FEATURE_LBRV)) 5278 lbrv = false; 5279 else 5280 pr_info("LBR virtualization supported\n"); 5281 } 5282 5283 if (!enable_pmu) 5284 pr_info("PMU virtualization is disabled\n"); 5285 5286 svm_set_cpu_caps(); 5287 5288 /* 5289 * It seems that on AMD processors PTE's accessed bit is 5290 * being set by the CPU hardware before the NPF vmexit. 5291 * This is not expected behaviour and our tests fail because 5292 * of it. 5293 * A workaround here is to disable support for 5294 * GUEST_MAXPHYADDR < HOST_MAXPHYADDR if NPT is enabled. 5295 * In this case userspace can know if there is support using 5296 * KVM_CAP_SMALLER_MAXPHYADDR extension and decide how to handle 5297 * it 5298 * If future AMD CPU models change the behaviour described above, 5299 * this variable can be changed accordingly 5300 */ 5301 allow_smaller_maxphyaddr = !npt_enabled; 5302 5303 return 0; 5304 5305 err: 5306 svm_hardware_unsetup(); 5307 return r; 5308 } 5309 5310 5311 static struct kvm_x86_init_ops svm_init_ops __initdata = { 5312 .hardware_setup = svm_hardware_setup, 5313 5314 .runtime_ops = &svm_x86_ops, 5315 .pmu_ops = &amd_pmu_ops, 5316 }; 5317 5318 static void __svm_exit(void) 5319 { 5320 kvm_x86_vendor_exit(); 5321 5322 cpu_emergency_unregister_virt_callback(svm_emergency_disable); 5323 } 5324 5325 static int __init svm_init(void) 5326 { 5327 int r; 5328 5329 __unused_size_checks(); 5330 5331 if (!kvm_is_svm_supported()) 5332 return -EOPNOTSUPP; 5333 5334 r = kvm_x86_vendor_init(&svm_init_ops); 5335 if (r) 5336 return r; 5337 5338 cpu_emergency_register_virt_callback(svm_emergency_disable); 5339 5340 /* 5341 * Common KVM initialization _must_ come last, after this, /dev/kvm is 5342 * exposed to userspace! 5343 */ 5344 r = kvm_init(sizeof(struct vcpu_svm), __alignof__(struct vcpu_svm), 5345 THIS_MODULE); 5346 if (r) 5347 goto err_kvm_init; 5348 5349 return 0; 5350 5351 err_kvm_init: 5352 __svm_exit(); 5353 return r; 5354 } 5355 5356 static void __exit svm_exit(void) 5357 { 5358 kvm_exit(); 5359 __svm_exit(); 5360 } 5361 5362 module_init(svm_init) 5363 module_exit(svm_exit) 5364