1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * KVM PMU support for AMD 4 * 5 * Copyright 2015, Red Hat, Inc. and/or its affiliates. 6 * 7 * Author: 8 * Wei Huang <wei@redhat.com> 9 * 10 * Implementation is based on pmu_intel.c file 11 */ 12 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 13 14 #include <linux/types.h> 15 #include <linux/kvm_host.h> 16 #include <linux/perf_event.h> 17 #include "x86.h" 18 #include "cpuid.h" 19 #include "lapic.h" 20 #include "pmu.h" 21 #include "svm.h" 22 23 enum pmu_type { 24 PMU_TYPE_COUNTER = 0, 25 PMU_TYPE_EVNTSEL, 26 }; 27 28 static struct kvm_pmc *amd_pmu_get_pmc(struct kvm_pmu *pmu, int pmc_idx) 29 { 30 unsigned int num_counters = pmu->nr_arch_gp_counters; 31 32 if (pmc_idx >= num_counters) 33 return NULL; 34 35 return &pmu->gp_counters[array_index_nospec(pmc_idx, num_counters)]; 36 } 37 38 static inline struct kvm_pmc *get_gp_pmc_amd(struct kvm_pmu *pmu, u32 msr, 39 enum pmu_type type) 40 { 41 struct kvm_vcpu *vcpu = pmu_to_vcpu(pmu); 42 unsigned int idx; 43 44 if (!pmu->version) 45 return NULL; 46 47 switch (msr) { 48 case MSR_F15H_PERF_CTL0 ... MSR_F15H_PERF_CTR5: 49 if (!guest_cpu_cap_has(vcpu, X86_FEATURE_PERFCTR_CORE)) 50 return NULL; 51 /* 52 * Each PMU counter has a pair of CTL and CTR MSRs. CTLn 53 * MSRs (accessed via EVNTSEL) are even, CTRn MSRs are odd. 54 */ 55 idx = (unsigned int)((msr - MSR_F15H_PERF_CTL0) / 2); 56 if (!(msr & 0x1) != (type == PMU_TYPE_EVNTSEL)) 57 return NULL; 58 break; 59 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3: 60 if (type != PMU_TYPE_EVNTSEL) 61 return NULL; 62 idx = msr - MSR_K7_EVNTSEL0; 63 break; 64 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3: 65 if (type != PMU_TYPE_COUNTER) 66 return NULL; 67 idx = msr - MSR_K7_PERFCTR0; 68 break; 69 default: 70 return NULL; 71 } 72 73 return amd_pmu_get_pmc(pmu, idx); 74 } 75 76 static int amd_check_rdpmc_early(struct kvm_vcpu *vcpu, unsigned int idx) 77 { 78 struct kvm_pmu *pmu = vcpu_to_pmu(vcpu); 79 80 if (idx >= pmu->nr_arch_gp_counters) 81 return -EINVAL; 82 83 return 0; 84 } 85 86 /* idx is the ECX register of RDPMC instruction */ 87 static struct kvm_pmc *amd_rdpmc_ecx_to_pmc(struct kvm_vcpu *vcpu, 88 unsigned int idx, u64 *mask) 89 { 90 return amd_pmu_get_pmc(vcpu_to_pmu(vcpu), idx); 91 } 92 93 static struct kvm_pmc *amd_msr_idx_to_pmc(struct kvm_vcpu *vcpu, u32 msr) 94 { 95 struct kvm_pmu *pmu = vcpu_to_pmu(vcpu); 96 struct kvm_pmc *pmc; 97 98 pmc = get_gp_pmc_amd(pmu, msr, PMU_TYPE_COUNTER); 99 pmc = pmc ? pmc : get_gp_pmc_amd(pmu, msr, PMU_TYPE_EVNTSEL); 100 101 return pmc; 102 } 103 104 static bool amd_is_valid_msr(struct kvm_vcpu *vcpu, u32 msr) 105 { 106 struct kvm_pmu *pmu = vcpu_to_pmu(vcpu); 107 108 switch (msr) { 109 case MSR_K7_EVNTSEL0 ... MSR_K7_PERFCTR3: 110 return pmu->version > 0; 111 case MSR_F15H_PERF_CTL0 ... MSR_F15H_PERF_CTR5: 112 return guest_cpu_cap_has(vcpu, X86_FEATURE_PERFCTR_CORE); 113 case MSR_AMD64_PERF_CNTR_GLOBAL_STATUS: 114 case MSR_AMD64_PERF_CNTR_GLOBAL_CTL: 115 case MSR_AMD64_PERF_CNTR_GLOBAL_STATUS_CLR: 116 case MSR_AMD64_PERF_CNTR_GLOBAL_STATUS_SET: 117 return pmu->version > 1; 118 default: 119 if (msr > MSR_F15H_PERF_CTR5 && 120 msr < MSR_F15H_PERF_CTL0 + 2 * pmu->nr_arch_gp_counters) 121 return pmu->version > 1; 122 break; 123 } 124 125 return amd_msr_idx_to_pmc(vcpu, msr); 126 } 127 128 static int amd_pmu_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info) 129 { 130 struct kvm_pmu *pmu = vcpu_to_pmu(vcpu); 131 struct kvm_pmc *pmc; 132 u32 msr = msr_info->index; 133 134 /* MSR_PERFCTRn */ 135 pmc = get_gp_pmc_amd(pmu, msr, PMU_TYPE_COUNTER); 136 if (pmc) { 137 msr_info->data = pmc_read_counter(pmc); 138 return 0; 139 } 140 /* MSR_EVNTSELn */ 141 pmc = get_gp_pmc_amd(pmu, msr, PMU_TYPE_EVNTSEL); 142 if (pmc) { 143 msr_info->data = pmc->eventsel; 144 return 0; 145 } 146 147 return 1; 148 } 149 150 static int amd_pmu_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info) 151 { 152 struct kvm_pmu *pmu = vcpu_to_pmu(vcpu); 153 struct kvm_pmc *pmc; 154 u32 msr = msr_info->index; 155 u64 data = msr_info->data; 156 157 /* MSR_PERFCTRn */ 158 pmc = get_gp_pmc_amd(pmu, msr, PMU_TYPE_COUNTER); 159 if (pmc) { 160 pmc_write_counter(pmc, data); 161 return 0; 162 } 163 /* MSR_EVNTSELn */ 164 pmc = get_gp_pmc_amd(pmu, msr, PMU_TYPE_EVNTSEL); 165 if (pmc) { 166 data &= ~pmu->reserved_bits; 167 if (data != pmc->eventsel) { 168 pmc->eventsel = data; 169 pmc->eventsel_hw = (data & ~AMD64_EVENTSEL_HOSTONLY) | 170 AMD64_EVENTSEL_GUESTONLY; 171 172 if (data & AMD64_EVENTSEL_HOST_GUEST_MASK) 173 __set_bit(pmc->idx, pmu->pmc_has_mode_specific_enables); 174 else 175 __clear_bit(pmc->idx, pmu->pmc_has_mode_specific_enables); 176 177 kvm_pmu_request_counter_reprogram(pmc); 178 } 179 return 0; 180 } 181 182 return 1; 183 } 184 185 static void amd_pmu_refresh(struct kvm_vcpu *vcpu) 186 { 187 struct kvm_pmu *pmu = vcpu_to_pmu(vcpu); 188 union cpuid_0x80000022_ebx ebx; 189 190 pmu->version = 1; 191 if (guest_cpu_cap_has(vcpu, X86_FEATURE_PERFMON_V2)) { 192 pmu->version = 2; 193 /* 194 * Note, PERFMON_V2 is also in 0x80000022.0x0, i.e. the guest 195 * CPUID entry is guaranteed to be non-NULL. 196 */ 197 BUILD_BUG_ON(x86_feature_cpuid(X86_FEATURE_PERFMON_V2).function != 0x80000022 || 198 x86_feature_cpuid(X86_FEATURE_PERFMON_V2).index); 199 ebx.full = kvm_find_cpuid_entry_index(vcpu, 0x80000022, 0)->ebx; 200 pmu->nr_arch_gp_counters = ebx.split.num_core_pmc; 201 } else if (guest_cpu_cap_has(vcpu, X86_FEATURE_PERFCTR_CORE)) { 202 pmu->nr_arch_gp_counters = AMD64_NUM_COUNTERS_CORE; 203 } else { 204 pmu->nr_arch_gp_counters = AMD64_NUM_COUNTERS; 205 } 206 207 pmu->nr_arch_gp_counters = min_t(unsigned int, pmu->nr_arch_gp_counters, 208 kvm_pmu_cap.num_counters_gp); 209 210 if (pmu->version > 1) { 211 pmu->global_ctrl_rsvd = ~(BIT_ULL(pmu->nr_arch_gp_counters) - 1); 212 pmu->global_status_rsvd = pmu->global_ctrl_rsvd; 213 } 214 215 pmu->counter_bitmask[KVM_PMC_GP] = BIT_ULL(48) - 1; 216 217 pmu->reserved_bits = 0xfffffff000280000ull; 218 if (guest_cpu_cap_has(vcpu, X86_FEATURE_SVM) && kvm_vcpu_has_mediated_pmu(vcpu)) 219 pmu->reserved_bits &= ~AMD64_EVENTSEL_HOST_GUEST_MASK; 220 221 pmu->raw_event_mask = AMD64_RAW_EVENT_MASK; 222 /* not applicable to AMD; but clean them to prevent any fall out */ 223 pmu->counter_bitmask[KVM_PMC_FIXED] = 0; 224 pmu->nr_arch_fixed_counters = 0; 225 } 226 227 static void amd_pmu_init(struct kvm_vcpu *vcpu) 228 { 229 struct kvm_pmu *pmu = vcpu_to_pmu(vcpu); 230 int i; 231 232 BUILD_BUG_ON(KVM_MAX_NR_AMD_GP_COUNTERS > AMD64_NUM_COUNTERS_CORE); 233 234 for (i = 0; i < KVM_MAX_NR_AMD_GP_COUNTERS; i++) { 235 pmu->gp_counters[i].type = KVM_PMC_GP; 236 pmu->gp_counters[i].vcpu = vcpu; 237 pmu->gp_counters[i].idx = i; 238 pmu->gp_counters[i].current_config = 0; 239 } 240 } 241 242 static bool amd_pmu_is_mediated_pmu_supported(struct x86_pmu_capability *host_pmu) 243 { 244 return host_pmu->version >= 2; 245 } 246 247 static void amd_mediated_pmu_load(struct kvm_vcpu *vcpu) 248 { 249 struct kvm_pmu *pmu = vcpu_to_pmu(vcpu); 250 u64 global_status; 251 252 rdmsrq(MSR_AMD64_PERF_CNTR_GLOBAL_STATUS, global_status); 253 /* Clear host global_status MSR if non-zero. */ 254 if (global_status) 255 wrmsrq(MSR_AMD64_PERF_CNTR_GLOBAL_STATUS_CLR, global_status); 256 257 wrmsrq(MSR_AMD64_PERF_CNTR_GLOBAL_STATUS_SET, pmu->global_status); 258 wrmsrq(MSR_AMD64_PERF_CNTR_GLOBAL_CTL, pmu->global_ctrl); 259 } 260 261 static void amd_mediated_pmu_put(struct kvm_vcpu *vcpu) 262 { 263 struct kvm_pmu *pmu = vcpu_to_pmu(vcpu); 264 265 wrmsrq(MSR_AMD64_PERF_CNTR_GLOBAL_CTL, 0); 266 rdmsrq(MSR_AMD64_PERF_CNTR_GLOBAL_STATUS, pmu->global_status); 267 268 /* Clear global status bits if non-zero */ 269 if (pmu->global_status) 270 wrmsrq(MSR_AMD64_PERF_CNTR_GLOBAL_STATUS_CLR, pmu->global_status); 271 } 272 273 static bool amd_pmc_is_disabled_in_current_mode(struct kvm_pmc *pmc) 274 { 275 struct kvm_vcpu *vcpu = pmc->vcpu; 276 u64 host_guest_bits; 277 278 if (!kvm_vcpu_has_mediated_pmu(vcpu)) 279 return false; 280 281 /* Common code is supposed to check the common enable bit */ 282 if (WARN_ON_ONCE(!(pmc->eventsel & ARCH_PERFMON_EVENTSEL_ENABLE))) 283 return false; 284 285 /* If both bits are cleared, the counter is always enabled */ 286 host_guest_bits = pmc->eventsel & AMD64_EVENTSEL_HOST_GUEST_MASK; 287 if (!host_guest_bits) 288 return false; 289 290 /* If EFER.SVME=0 and either bit is set, the counter is disabled */ 291 if (!(vcpu->arch.efer & EFER_SVME)) 292 return true; 293 294 /* 295 * If EFER.SVME=1, the counter is disabled iff only one of the bits is 296 * set AND the set bit doesn't match the vCPU mode. 297 */ 298 if (host_guest_bits == AMD64_EVENTSEL_HOST_GUEST_MASK) 299 return false; 300 301 return !!(host_guest_bits & AMD64_EVENTSEL_GUESTONLY) != is_guest_mode(vcpu); 302 } 303 304 struct kvm_pmu_ops amd_pmu_ops __initdata = { 305 .rdpmc_ecx_to_pmc = amd_rdpmc_ecx_to_pmc, 306 .msr_idx_to_pmc = amd_msr_idx_to_pmc, 307 .check_rdpmc_early = amd_check_rdpmc_early, 308 .is_valid_msr = amd_is_valid_msr, 309 .get_msr = amd_pmu_get_msr, 310 .set_msr = amd_pmu_set_msr, 311 .refresh = amd_pmu_refresh, 312 .init = amd_pmu_init, 313 .pmc_is_disabled_in_current_mode = amd_pmc_is_disabled_in_current_mode, 314 315 .is_mediated_pmu_supported = amd_pmu_is_mediated_pmu_supported, 316 .mediated_load = amd_mediated_pmu_load, 317 .mediated_put = amd_mediated_pmu_put, 318 319 .EVENTSEL_EVENT = AMD64_EVENTSEL_EVENT, 320 .MAX_NR_GP_COUNTERS = KVM_MAX_NR_AMD_GP_COUNTERS, 321 .MIN_NR_GP_COUNTERS = AMD64_NUM_COUNTERS, 322 323 .PERF_GLOBAL_CTRL = MSR_AMD64_PERF_CNTR_GLOBAL_CTL, 324 .GP_EVENTSEL_BASE = MSR_F15H_PERF_CTL0, 325 .GP_COUNTER_BASE = MSR_F15H_PERF_CTR0, 326 .FIXED_COUNTER_BASE = 0, 327 .MSR_STRIDE = 2, 328 }; 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