1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Kernel-based Virtual Machine driver for Linux 4 * 5 * AMD SVM support 6 * 7 * Copyright (C) 2006 Qumranet, Inc. 8 * Copyright 2010 Red Hat, Inc. and/or its affiliates. 9 * 10 * Authors: 11 * Yaniv Kamay <yaniv@qumranet.com> 12 * Avi Kivity <avi@qumranet.com> 13 */ 14 15 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 16 17 #include <linux/kvm_types.h> 18 #include <linux/kvm_host.h> 19 #include <linux/kernel.h> 20 21 #include <asm/msr-index.h> 22 #include <asm/debugreg.h> 23 24 #include "kvm_emulate.h" 25 #include "trace.h" 26 #include "mmu.h" 27 #include "x86.h" 28 #include "smm.h" 29 #include "cpuid.h" 30 #include "lapic.h" 31 #include "svm.h" 32 #include "hyperv.h" 33 34 #define CC KVM_NESTED_VMENTER_CONSISTENCY_CHECK 35 36 static void nested_svm_inject_npf_exit(struct kvm_vcpu *vcpu, 37 struct x86_exception *fault) 38 { 39 struct vcpu_svm *svm = to_svm(vcpu); 40 struct vmcb *vmcb = svm->vmcb; 41 42 if (vmcb->control.exit_code != SVM_EXIT_NPF) { 43 /* 44 * TODO: track the cause of the nested page fault, and 45 * correctly fill in the high bits of exit_info_1. 46 */ 47 vmcb->control.exit_code = SVM_EXIT_NPF; 48 vmcb->control.exit_info_1 = (1ULL << 32); 49 vmcb->control.exit_info_2 = fault->address; 50 } 51 52 vmcb->control.exit_info_1 &= ~0xffffffffULL; 53 vmcb->control.exit_info_1 |= fault->error_code; 54 55 nested_svm_vmexit(svm); 56 } 57 58 static u64 nested_svm_get_tdp_pdptr(struct kvm_vcpu *vcpu, int index) 59 { 60 struct vcpu_svm *svm = to_svm(vcpu); 61 u64 cr3 = svm->nested.ctl.nested_cr3; 62 u64 pdpte; 63 int ret; 64 65 /* 66 * Note, nCR3 is "assumed" to be 32-byte aligned, i.e. the CPU ignores 67 * nCR3[4:0] when loading PDPTEs from memory. 68 */ 69 ret = kvm_vcpu_read_guest_page(vcpu, gpa_to_gfn(cr3), &pdpte, 70 (cr3 & GENMASK(11, 5)) + index * 8, 8); 71 if (ret) 72 return 0; 73 return pdpte; 74 } 75 76 static unsigned long nested_svm_get_tdp_cr3(struct kvm_vcpu *vcpu) 77 { 78 struct vcpu_svm *svm = to_svm(vcpu); 79 80 return svm->nested.ctl.nested_cr3; 81 } 82 83 static void nested_svm_init_mmu_context(struct kvm_vcpu *vcpu) 84 { 85 struct vcpu_svm *svm = to_svm(vcpu); 86 87 WARN_ON(mmu_is_nested(vcpu)); 88 89 vcpu->arch.mmu = &vcpu->arch.guest_mmu; 90 91 /* 92 * The NPT format depends on L1's CR4 and EFER, which is in vmcb01. Note, 93 * when called via KVM_SET_NESTED_STATE, that state may _not_ match current 94 * vCPU state. CR0.WP is explicitly ignored, while CR0.PG is required. 95 */ 96 kvm_init_shadow_npt_mmu(vcpu, svm->vmcb01.ptr->save.cr4, 97 svm->vmcb01.ptr->save.efer, 98 svm->nested.ctl.nested_cr3, 99 svm->nested.ctl.misc_ctl); 100 vcpu->arch.mmu->get_guest_pgd = nested_svm_get_tdp_cr3; 101 vcpu->arch.mmu->get_pdptr = nested_svm_get_tdp_pdptr; 102 vcpu->arch.mmu->inject_page_fault = nested_svm_inject_npf_exit; 103 vcpu->arch.walk_mmu = &vcpu->arch.nested_mmu; 104 } 105 106 static void nested_svm_uninit_mmu_context(struct kvm_vcpu *vcpu) 107 { 108 vcpu->arch.mmu = &vcpu->arch.root_mmu; 109 vcpu->arch.walk_mmu = &vcpu->arch.root_mmu; 110 } 111 112 static bool nested_vmcb_needs_vls_intercept(struct vcpu_svm *svm) 113 { 114 if (!guest_cpu_cap_has(&svm->vcpu, X86_FEATURE_V_VMSAVE_VMLOAD)) 115 return true; 116 117 if (!nested_npt_enabled(svm)) 118 return true; 119 120 if (!(svm->nested.ctl.misc_ctl2 & SVM_MISC2_ENABLE_V_VMLOAD_VMSAVE)) 121 return true; 122 123 return false; 124 } 125 126 void nested_vmcb02_recalc_intercepts(struct vcpu_svm *svm) 127 { 128 struct vmcb_ctrl_area_cached *vmcb12_ctrl = &svm->nested.ctl; 129 struct vmcb *vmcb02 = svm->nested.vmcb02.ptr; 130 struct vmcb *vmcb01 = svm->vmcb01.ptr; 131 unsigned int i; 132 133 if (WARN_ON_ONCE(svm->vmcb != vmcb02)) 134 return; 135 136 vmcb_mark_dirty(vmcb02, VMCB_INTERCEPTS); 137 138 for (i = 0; i < MAX_INTERCEPT; i++) 139 vmcb02->control.intercepts[i] = vmcb01->control.intercepts[i]; 140 141 if (vmcb12_ctrl->int_ctl & V_INTR_MASKING_MASK) { 142 /* 143 * If L2 is active and V_INTR_MASKING is enabled in vmcb12, 144 * disable intercept of CR8 writes as L2's CR8 does not affect 145 * any interrupt KVM may want to inject. 146 * 147 * Similarly, disable intercept of virtual interrupts (used to 148 * detect interrupt windows) if the saved RFLAGS.IF is '0', as 149 * the effective RFLAGS.IF for L1 interrupts will never be set 150 * while L2 is running (L2's RFLAGS.IF doesn't affect L1 IRQs). 151 */ 152 vmcb_clr_intercept(&vmcb02->control, INTERCEPT_CR8_WRITE); 153 if (!(vmcb01->save.rflags & X86_EFLAGS_IF)) 154 vmcb_clr_intercept(&vmcb02->control, INTERCEPT_VINTR); 155 } 156 157 for (i = 0; i < MAX_INTERCEPT; i++) 158 vmcb02->control.intercepts[i] |= vmcb12_ctrl->intercepts[i]; 159 160 /* If SMI is not intercepted, ignore guest SMI intercept as well */ 161 if (!intercept_smi) 162 vmcb_clr_intercept(&vmcb02->control, INTERCEPT_SMI); 163 164 /* 165 * Intercept PAUSE if and only if L1 wants to. KVM intercepts PAUSE so 166 * that a vCPU that may be spinning waiting for a lock can be scheduled 167 * out in favor of the vCPU that holds said lock. KVM doesn't support 168 * yielding across L2 vCPUs, as KVM has limited visilibity into which 169 * L2 vCPUs are in the same L2 VM, i.e. may be contending for locks. 170 */ 171 if (!vmcb12_is_intercept(&svm->nested.ctl, INTERCEPT_PAUSE)) 172 vmcb_clr_intercept(&vmcb02->control, INTERCEPT_PAUSE); 173 174 if (nested_vmcb_needs_vls_intercept(svm)) { 175 /* 176 * If the virtual VMLOAD/VMSAVE is not enabled for the L2, 177 * we must intercept these instructions to correctly 178 * emulate them in case L1 doesn't intercept them. 179 */ 180 vmcb_set_intercept(&vmcb02->control, INTERCEPT_VMLOAD); 181 vmcb_set_intercept(&vmcb02->control, INTERCEPT_VMSAVE); 182 } else { 183 WARN_ON_ONCE(!(vmcb02->control.misc_ctl2 & SVM_MISC2_ENABLE_V_VMLOAD_VMSAVE)); 184 } 185 } 186 187 /* 188 * This array (and its actual size) holds the set of offsets (indexing by chunk 189 * size) to process when merging vmcb12's MSRPM with vmcb01's MSRPM. Note, the 190 * set of MSRs for which interception is disabled in vmcb01 is per-vCPU, e.g. 191 * based on CPUID features. This array only tracks MSRs that *might* be passed 192 * through to the guest. 193 * 194 * Hardcode the capacity of the array based on the maximum number of _offsets_. 195 * MSRs are batched together, so there are fewer offsets than MSRs. 196 */ 197 static int nested_svm_msrpm_merge_offsets[10] __ro_after_init; 198 static int nested_svm_nr_msrpm_merge_offsets __ro_after_init; 199 typedef unsigned long nsvm_msrpm_merge_t; 200 201 int __init nested_svm_init_msrpm_merge_offsets(void) 202 { 203 static const u32 merge_msrs[] __initconst = { 204 MSR_STAR, 205 MSR_IA32_SYSENTER_CS, 206 MSR_IA32_SYSENTER_EIP, 207 MSR_IA32_SYSENTER_ESP, 208 #ifdef CONFIG_X86_64 209 MSR_GS_BASE, 210 MSR_FS_BASE, 211 MSR_KERNEL_GS_BASE, 212 MSR_LSTAR, 213 MSR_CSTAR, 214 MSR_SYSCALL_MASK, 215 #endif 216 MSR_IA32_SPEC_CTRL, 217 MSR_IA32_PRED_CMD, 218 MSR_IA32_FLUSH_CMD, 219 MSR_IA32_APERF, 220 MSR_IA32_MPERF, 221 MSR_IA32_LASTBRANCHFROMIP, 222 MSR_IA32_LASTBRANCHTOIP, 223 MSR_IA32_LASTINTFROMIP, 224 MSR_IA32_LASTINTTOIP, 225 226 MSR_K7_PERFCTR0, 227 MSR_K7_PERFCTR1, 228 MSR_K7_PERFCTR2, 229 MSR_K7_PERFCTR3, 230 MSR_F15H_PERF_CTR0, 231 MSR_F15H_PERF_CTR1, 232 MSR_F15H_PERF_CTR2, 233 MSR_F15H_PERF_CTR3, 234 MSR_F15H_PERF_CTR4, 235 MSR_F15H_PERF_CTR5, 236 237 MSR_AMD64_PERF_CNTR_GLOBAL_CTL, 238 MSR_AMD64_PERF_CNTR_GLOBAL_STATUS, 239 MSR_AMD64_PERF_CNTR_GLOBAL_STATUS_CLR, 240 MSR_AMD64_PERF_CNTR_GLOBAL_STATUS_SET, 241 }; 242 int i, j; 243 244 for (i = 0; i < ARRAY_SIZE(merge_msrs); i++) { 245 int bit_nr = svm_msrpm_bit_nr(merge_msrs[i]); 246 u32 offset; 247 248 if (WARN_ON(bit_nr < 0)) 249 return -EIO; 250 251 /* 252 * Merging is done in chunks to reduce the number of accesses 253 * to L1's bitmap. 254 */ 255 offset = bit_nr / BITS_PER_BYTE / sizeof(nsvm_msrpm_merge_t); 256 257 for (j = 0; j < nested_svm_nr_msrpm_merge_offsets; j++) { 258 if (nested_svm_msrpm_merge_offsets[j] == offset) 259 break; 260 } 261 262 if (j < nested_svm_nr_msrpm_merge_offsets) 263 continue; 264 265 if (WARN_ON(j >= ARRAY_SIZE(nested_svm_msrpm_merge_offsets))) 266 return -EIO; 267 268 nested_svm_msrpm_merge_offsets[j] = offset; 269 nested_svm_nr_msrpm_merge_offsets++; 270 } 271 272 return 0; 273 } 274 275 /* 276 * Merge L0's (KVM) and L1's (Nested VMCB) MSR permission bitmaps. The function 277 * is optimized in that it only merges the parts where KVM MSR permission bitmap 278 * may contain zero bits. 279 */ 280 static bool nested_svm_merge_msrpm(struct kvm_vcpu *vcpu) 281 { 282 struct vcpu_svm *svm = to_svm(vcpu); 283 nsvm_msrpm_merge_t *msrpm02 = svm->nested.msrpm; 284 nsvm_msrpm_merge_t *msrpm01 = svm->msrpm; 285 int i; 286 287 /* 288 * MSR bitmap update can be skipped when: 289 * - MSR bitmap for L1 hasn't changed. 290 * - Nested hypervisor (L1) is attempting to launch the same L2 as 291 * before. 292 * - Nested hypervisor (L1) is using Hyper-V emulation interface and 293 * tells KVM (L0) there were no changes in MSR bitmap for L2. 294 */ 295 #ifdef CONFIG_KVM_HYPERV 296 if (!svm->nested.force_msr_bitmap_recalc) { 297 struct hv_vmcb_enlightenments *hve = &svm->nested.ctl.hv_enlightenments; 298 299 if (kvm_hv_hypercall_enabled(vcpu) && 300 hve->hv_enlightenments_control.msr_bitmap && 301 (svm->nested.ctl.clean & BIT(HV_VMCB_NESTED_ENLIGHTENMENTS))) 302 goto set_msrpm_base_pa; 303 } 304 #endif 305 306 if (!(vmcb12_is_intercept(&svm->nested.ctl, INTERCEPT_MSR_PROT))) 307 return true; 308 309 for (i = 0; i < nested_svm_nr_msrpm_merge_offsets; i++) { 310 const int p = nested_svm_msrpm_merge_offsets[i]; 311 nsvm_msrpm_merge_t l1_val; 312 gpa_t gpa; 313 314 gpa = svm->nested.ctl.msrpm_base_pa + (p * sizeof(l1_val)); 315 316 if (kvm_vcpu_read_guest(vcpu, gpa, &l1_val, sizeof(l1_val))) 317 return false; 318 319 msrpm02[p] = msrpm01[p] | l1_val; 320 } 321 322 svm->nested.force_msr_bitmap_recalc = false; 323 324 #ifdef CONFIG_KVM_HYPERV 325 set_msrpm_base_pa: 326 #endif 327 svm->vmcb->control.msrpm_base_pa = __sme_set(__pa(svm->nested.msrpm)); 328 329 return true; 330 } 331 332 /* 333 * Bits 11:0 of bitmap address are ignored by hardware 334 */ 335 static bool nested_svm_check_bitmap_pa(struct kvm_vcpu *vcpu, u64 pa, u32 size) 336 { 337 u64 addr = PAGE_ALIGN(pa); 338 339 return kvm_vcpu_is_legal_gpa(vcpu, addr) && 340 kvm_vcpu_is_legal_gpa(vcpu, addr + size - 1); 341 } 342 343 static bool nested_svm_event_inj_valid_exept(struct kvm_vcpu *vcpu, u8 vector) 344 { 345 /* 346 * Vectors that do not correspond to a defined exception are invalid 347 * (including #NMI and reserved vectors). In a best effort to define 348 * valid exceptions based on the virtual CPU, make all exceptions always 349 * valid except those obviously tied to a CPU feature. 350 */ 351 switch (vector) { 352 case DE_VECTOR: case DB_VECTOR: case BP_VECTOR: case OF_VECTOR: 353 case BR_VECTOR: case UD_VECTOR: case NM_VECTOR: case DF_VECTOR: 354 case TS_VECTOR: case NP_VECTOR: case SS_VECTOR: case GP_VECTOR: 355 case PF_VECTOR: case MF_VECTOR: case AC_VECTOR: case MC_VECTOR: 356 case XM_VECTOR: case HV_VECTOR: case SX_VECTOR: 357 return true; 358 case CP_VECTOR: 359 return guest_cpu_cap_has(vcpu, X86_FEATURE_SHSTK); 360 case VC_VECTOR: 361 return guest_cpu_cap_has(vcpu, X86_FEATURE_SEV_ES); 362 } 363 return false; 364 } 365 366 /* 367 * According to the APM, VMRUN exits with SVM_EXIT_ERR if SVM_EVTINJ_VALID is 368 * set and: 369 * - The type of event_inj is not one of the defined values. 370 * - The type is SVM_EVTINJ_TYPE_EXEPT, but the vector is not a valid exception. 371 */ 372 static bool nested_svm_check_event_inj(struct kvm_vcpu *vcpu, u32 event_inj) 373 { 374 u32 type = event_inj & SVM_EVTINJ_TYPE_MASK; 375 u8 vector = event_inj & SVM_EVTINJ_VEC_MASK; 376 377 if (!(event_inj & SVM_EVTINJ_VALID)) 378 return true; 379 380 if (type != SVM_EVTINJ_TYPE_INTR && type != SVM_EVTINJ_TYPE_NMI && 381 type != SVM_EVTINJ_TYPE_EXEPT && type != SVM_EVTINJ_TYPE_SOFT) 382 return false; 383 384 if (type == SVM_EVTINJ_TYPE_EXEPT && 385 !nested_svm_event_inj_valid_exept(vcpu, vector)) 386 return false; 387 388 return true; 389 } 390 391 static bool nested_vmcb_check_controls(struct kvm_vcpu *vcpu, 392 struct vmcb_ctrl_area_cached *control) 393 { 394 if (CC(!vmcb12_is_intercept(control, INTERCEPT_VMRUN))) 395 return false; 396 397 if (CC(control->asid == 0)) 398 return false; 399 400 if (CC((control->misc_ctl & SVM_MISC_ENABLE_NP) && 401 !kvm_vcpu_is_legal_gpa(vcpu, control->nested_cr3))) 402 return false; 403 404 if (CC(!nested_svm_check_bitmap_pa(vcpu, control->msrpm_base_pa, 405 MSRPM_SIZE))) 406 return false; 407 if (CC(!nested_svm_check_bitmap_pa(vcpu, control->iopm_base_pa, 408 IOPM_SIZE))) 409 return false; 410 411 if (CC((control->int_ctl & V_NMI_ENABLE_MASK) && 412 !vmcb12_is_intercept(control, INTERCEPT_NMI))) { 413 return false; 414 } 415 416 if (CC(!nested_svm_check_event_inj(vcpu, control->event_inj))) 417 return false; 418 419 return true; 420 } 421 422 /* Common checks that apply to both L1 and L2 state. */ 423 static bool nested_vmcb_check_save(struct kvm_vcpu *vcpu, 424 struct vmcb_save_area_cached *save) 425 { 426 if (CC(!(save->efer & EFER_SVME))) 427 return false; 428 429 if (CC((save->cr0 & X86_CR0_CD) == 0 && (save->cr0 & X86_CR0_NW)) || 430 CC(save->cr0 & ~0xffffffffULL)) 431 return false; 432 433 if (CC(!kvm_dr6_valid(save->dr6)) || CC(!kvm_dr7_valid(save->dr7))) 434 return false; 435 436 /* 437 * These checks are also performed by KVM_SET_SREGS, 438 * except that EFER.LMA is not checked by SVM against 439 * CR0.PG && EFER.LME. 440 */ 441 if ((save->efer & EFER_LME) && (save->cr0 & X86_CR0_PG)) { 442 if (CC(!(save->cr4 & X86_CR4_PAE)) || 443 CC(!(save->cr0 & X86_CR0_PE)) || 444 CC(!kvm_vcpu_is_legal_cr3(vcpu, save->cr3))) 445 return false; 446 447 if (CC((save->cs.attrib & SVM_SELECTOR_L_MASK) && 448 (save->cs.attrib & SVM_SELECTOR_DB_MASK))) 449 return false; 450 } 451 452 /* Note, SVM doesn't have any additional restrictions on CR4. */ 453 if (CC(!__kvm_is_valid_cr4(vcpu, save->cr4))) 454 return false; 455 456 if (CC(!kvm_valid_efer(vcpu, save->efer))) 457 return false; 458 459 return true; 460 } 461 462 int nested_svm_check_cached_vmcb12(struct kvm_vcpu *vcpu) 463 { 464 struct vcpu_svm *svm = to_svm(vcpu); 465 466 if (!nested_vmcb_check_save(vcpu, &svm->nested.save) || 467 !nested_vmcb_check_controls(vcpu, &svm->nested.ctl)) 468 return -EINVAL; 469 470 return 0; 471 } 472 473 /* 474 * If a feature is not advertised to L1, clear the corresponding vmcb12 475 * intercept. 476 */ 477 #define __nested_svm_sanitize_intercept(__vcpu, __control, fname, iname) \ 478 do { \ 479 if (!guest_cpu_cap_has(__vcpu, X86_FEATURE_##fname)) \ 480 vmcb12_clr_intercept(__control, INTERCEPT_##iname); \ 481 } while (0) 482 483 #define nested_svm_sanitize_intercept(__vcpu, __control, name) \ 484 __nested_svm_sanitize_intercept(__vcpu, __control, name, name) 485 486 static 487 void __nested_copy_vmcb_control_to_cache(struct kvm_vcpu *vcpu, 488 struct vmcb_ctrl_area_cached *to, 489 struct vmcb_control_area *from) 490 { 491 unsigned int i; 492 493 for (i = 0; i < MAX_INTERCEPT; i++) 494 to->intercepts[i] = from->intercepts[i]; 495 496 __nested_svm_sanitize_intercept(vcpu, to, XSAVE, XSETBV); 497 nested_svm_sanitize_intercept(vcpu, to, INVPCID); 498 nested_svm_sanitize_intercept(vcpu, to, RDTSCP); 499 nested_svm_sanitize_intercept(vcpu, to, SKINIT); 500 nested_svm_sanitize_intercept(vcpu, to, RDPRU); 501 502 /* Always clear misc_ctl bits that the guest cannot use */ 503 to->misc_ctl = from->misc_ctl; 504 if (!guest_cpu_cap_has(vcpu, X86_FEATURE_NPT)) 505 to->misc_ctl &= ~SVM_MISC_ENABLE_NP; 506 507 if (!gmet_enabled || !guest_cpu_cap_has(vcpu, X86_FEATURE_GMET)) 508 to->misc_ctl &= ~SVM_MISC_ENABLE_GMET; 509 510 to->iopm_base_pa = from->iopm_base_pa & PAGE_MASK; 511 to->msrpm_base_pa = from->msrpm_base_pa & PAGE_MASK; 512 to->tsc_offset = from->tsc_offset; 513 to->tlb_ctl = from->tlb_ctl & TLB_CONTROL_MASK; 514 to->erap_ctl = from->erap_ctl; 515 to->int_ctl = from->int_ctl; 516 to->int_vector = from->int_vector & SVM_INT_VECTOR_MASK; 517 to->int_state = from->int_state & SVM_INTERRUPT_SHADOW_MASK; 518 to->exit_code = from->exit_code; 519 to->exit_info_1 = from->exit_info_1; 520 to->exit_info_2 = from->exit_info_2; 521 to->exit_int_info = from->exit_int_info; 522 to->exit_int_info_err = from->exit_int_info_err; 523 to->event_inj = from->event_inj & ~SVM_EVTINJ_RESERVED_BITS; 524 to->event_inj_err = from->event_inj_err; 525 to->next_rip = from->next_rip; 526 to->nested_cr3 = from->nested_cr3; 527 to->misc_ctl2 = from->misc_ctl2; 528 to->pause_filter_count = from->pause_filter_count; 529 to->pause_filter_thresh = from->pause_filter_thresh; 530 531 /* Copy asid here because nested_vmcb_check_controls() will check it */ 532 to->asid = from->asid; 533 to->clean = from->clean; 534 535 #ifdef CONFIG_KVM_HYPERV 536 /* Hyper-V extensions (Enlightened VMCB) */ 537 if (kvm_hv_hypercall_enabled(vcpu)) { 538 memcpy(&to->hv_enlightenments, &from->hv_enlightenments, 539 sizeof(to->hv_enlightenments)); 540 } 541 #endif 542 } 543 544 void nested_copy_vmcb_control_to_cache(struct vcpu_svm *svm, 545 struct vmcb_control_area *control) 546 { 547 __nested_copy_vmcb_control_to_cache(&svm->vcpu, &svm->nested.ctl, control); 548 } 549 550 static void __nested_copy_vmcb_save_to_cache(struct vmcb_save_area_cached *to, 551 struct vmcb_save_area *from) 552 { 553 to->es = from->es; 554 to->cs = from->cs; 555 to->ss = from->ss; 556 to->ds = from->ds; 557 to->gdtr = from->gdtr; 558 to->idtr = from->idtr; 559 560 to->cpl = from->cpl; 561 562 to->efer = from->efer; 563 to->cr4 = from->cr4; 564 to->cr3 = from->cr3; 565 to->cr0 = from->cr0; 566 to->dr7 = from->dr7; 567 to->dr6 = from->dr6; 568 569 to->rflags = from->rflags; 570 to->rip = from->rip; 571 to->rsp = from->rsp; 572 573 to->s_cet = from->s_cet; 574 to->ssp = from->ssp; 575 to->isst_addr = from->isst_addr; 576 577 to->rax = from->rax; 578 to->cr2 = from->cr2; 579 580 svm_copy_lbrs(to, from); 581 } 582 583 void nested_copy_vmcb_save_to_cache(struct vcpu_svm *svm, 584 struct vmcb_save_area *save) 585 { 586 __nested_copy_vmcb_save_to_cache(&svm->nested.save, save); 587 } 588 589 /* 590 * Synchronize fields that are written by the processor, so that 591 * they can be copied back into the vmcb12. 592 */ 593 void nested_sync_control_from_vmcb02(struct vcpu_svm *svm) 594 { 595 u32 mask; 596 svm->nested.ctl.event_inj = svm->vmcb->control.event_inj; 597 svm->nested.ctl.event_inj_err = svm->vmcb->control.event_inj_err; 598 svm->nested.ctl.int_state = svm->vmcb->control.int_state; 599 600 /* Only a few fields of int_ctl are written by the processor. */ 601 mask = V_IRQ_MASK | V_TPR_MASK; 602 /* 603 * Don't sync vmcb02 V_IRQ back to vmcb12 if KVM (L0) is intercepting 604 * virtual interrupts in order to request an interrupt window, as KVM 605 * has usurped vmcb02's int_ctl. If an interrupt window opens before 606 * the next VM-Exit, svm_clear_vintr() will restore vmcb12's int_ctl. 607 * If no window opens, V_IRQ will be correctly preserved in vmcb12's 608 * int_ctl (because it was never recognized while L2 was running). 609 */ 610 if (svm_is_intercept(svm, INTERCEPT_VINTR) && 611 !vmcb12_is_intercept(&svm->nested.ctl, INTERCEPT_VINTR)) 612 mask &= ~V_IRQ_MASK; 613 614 if (nested_vgif_enabled(svm)) 615 mask |= V_GIF_MASK; 616 617 if (nested_vnmi_enabled(svm)) 618 mask |= V_NMI_BLOCKING_MASK | V_NMI_PENDING_MASK; 619 620 svm->nested.ctl.int_ctl &= ~mask; 621 svm->nested.ctl.int_ctl |= svm->vmcb->control.int_ctl & mask; 622 } 623 624 /* 625 * Transfer any event that L0 or L1 wanted to inject into L2 to 626 * EXIT_INT_INFO. 627 */ 628 static void nested_save_pending_event_to_vmcb12(struct vcpu_svm *svm, 629 struct vmcb *vmcb12) 630 { 631 struct kvm_vcpu *vcpu = &svm->vcpu; 632 u32 exit_int_info = 0; 633 unsigned int nr; 634 635 if (vcpu->arch.exception.injected) { 636 nr = vcpu->arch.exception.vector; 637 exit_int_info = nr | SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_EXEPT; 638 639 if (vcpu->arch.exception.has_error_code) { 640 exit_int_info |= SVM_EVTINJ_VALID_ERR; 641 vmcb12->control.exit_int_info_err = 642 vcpu->arch.exception.error_code; 643 } 644 645 } else if (vcpu->arch.nmi_injected) { 646 exit_int_info = SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_NMI; 647 648 } else if (vcpu->arch.interrupt.injected) { 649 nr = vcpu->arch.interrupt.nr; 650 exit_int_info = nr | SVM_EVTINJ_VALID; 651 652 if (vcpu->arch.interrupt.soft) 653 exit_int_info |= SVM_EVTINJ_TYPE_SOFT; 654 else 655 exit_int_info |= SVM_EVTINJ_TYPE_INTR; 656 } 657 658 vmcb12->control.exit_int_info = exit_int_info; 659 } 660 661 static void nested_svm_transition_tlb_flush(struct kvm_vcpu *vcpu) 662 { 663 /* Handle pending Hyper-V TLB flush requests */ 664 kvm_hv_nested_transtion_tlb_flush(vcpu, npt_enabled); 665 666 /* 667 * TODO: optimize unconditional TLB flush/MMU sync. A partial list of 668 * things to fix before this can be conditional: 669 * 670 * - Flush TLBs for both L1 and L2 remote TLB flush 671 * - Honor L1's request to flush an ASID on nested VMRUN 672 * - Sync nested NPT MMU on VMRUN that flushes L2's ASID[*] 673 * - Don't crush a pending TLB flush in vmcb02 on nested VMRUN 674 * - Flush L1's ASID on KVM_REQ_TLB_FLUSH_GUEST 675 * 676 * [*] Unlike nested EPT, SVM's ASID management can invalidate nested 677 * NPT guest-physical mappings on VMRUN. 678 */ 679 kvm_make_request(KVM_REQ_MMU_SYNC, vcpu); 680 kvm_make_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu); 681 } 682 683 /* 684 * Load guest's/host's cr3 on nested vmentry or vmexit. @nested_npt is true 685 * if we are emulating VM-Entry into a guest with NPT enabled. 686 */ 687 static int nested_svm_load_cr3(struct kvm_vcpu *vcpu, unsigned long cr3, 688 bool nested_npt, bool reload_pdptrs) 689 { 690 if (CC(!kvm_vcpu_is_legal_cr3(vcpu, cr3))) 691 return -EINVAL; 692 693 if (reload_pdptrs && !nested_npt && is_pae_paging(vcpu) && 694 CC(!load_pdptrs(vcpu, cr3))) 695 return -EINVAL; 696 697 vcpu->arch.cr3 = cr3; 698 699 /* Re-initialize the MMU, e.g. to pick up CR4 MMU role changes. */ 700 kvm_init_mmu(vcpu); 701 702 if (!nested_npt) 703 kvm_mmu_new_pgd(vcpu, cr3); 704 705 return 0; 706 } 707 708 void nested_vmcb02_compute_g_pat(struct vcpu_svm *svm) 709 { 710 if (!svm->nested.vmcb02.ptr) 711 return; 712 713 /* FIXME: merge g_pat from vmcb01 and vmcb12. */ 714 svm->nested.vmcb02.ptr->save.g_pat = svm->vmcb01.ptr->save.g_pat; 715 } 716 717 static bool nested_vmcb12_has_lbrv(struct kvm_vcpu *vcpu) 718 { 719 return guest_cpu_cap_has(vcpu, X86_FEATURE_LBRV) && 720 (to_svm(vcpu)->nested.ctl.misc_ctl2 & SVM_MISC2_ENABLE_V_LBR); 721 } 722 723 static void nested_vmcb02_prepare_save(struct vcpu_svm *svm) 724 { 725 struct vmcb_ctrl_area_cached *control = &svm->nested.ctl; 726 struct vmcb_save_area_cached *save = &svm->nested.save; 727 bool new_vmcb12 = false; 728 struct vmcb *vmcb01 = svm->vmcb01.ptr; 729 struct vmcb *vmcb02 = svm->nested.vmcb02.ptr; 730 struct kvm_vcpu *vcpu = &svm->vcpu; 731 732 nested_vmcb02_compute_g_pat(svm); 733 vmcb_mark_dirty(vmcb02, VMCB_NPT); 734 735 /* Load the nested guest state */ 736 if (svm->nested.vmcb12_gpa != svm->nested.last_vmcb12_gpa) { 737 new_vmcb12 = true; 738 svm->nested.last_vmcb12_gpa = svm->nested.vmcb12_gpa; 739 svm->nested.force_msr_bitmap_recalc = true; 740 } 741 742 if (unlikely(new_vmcb12 || vmcb12_is_dirty(control, VMCB_SEG))) { 743 vmcb02->save.es = save->es; 744 vmcb02->save.cs = save->cs; 745 vmcb02->save.ss = save->ss; 746 vmcb02->save.ds = save->ds; 747 vmcb02->save.cpl = save->cpl; 748 vmcb_mark_dirty(vmcb02, VMCB_SEG); 749 } 750 751 if (unlikely(new_vmcb12 || vmcb12_is_dirty(control, VMCB_DT))) { 752 vmcb02->save.gdtr = save->gdtr; 753 vmcb02->save.idtr = save->idtr; 754 vmcb_mark_dirty(vmcb02, VMCB_DT); 755 } 756 757 if (guest_cpu_cap_has(vcpu, X86_FEATURE_SHSTK) && 758 (unlikely(new_vmcb12 || vmcb12_is_dirty(control, VMCB_CET)))) { 759 vmcb02->save.s_cet = save->s_cet; 760 vmcb02->save.isst_addr = save->isst_addr; 761 vmcb02->save.ssp = save->ssp; 762 vmcb_mark_dirty(vmcb02, VMCB_CET); 763 } 764 765 kvm_set_rflags(vcpu, save->rflags | X86_EFLAGS_FIXED); 766 767 svm_set_efer(vcpu, svm->nested.save.efer); 768 769 svm_set_cr0(vcpu, svm->nested.save.cr0); 770 svm_set_cr4(vcpu, svm->nested.save.cr4); 771 772 svm->vcpu.arch.cr2 = save->cr2; 773 774 kvm_rax_write(vcpu, save->rax); 775 kvm_rsp_write(vcpu, save->rsp); 776 kvm_rip_write(vcpu, save->rip); 777 778 /* In case we don't even reach vcpu_run, the fields are not updated */ 779 vmcb02->save.rax = save->rax; 780 vmcb02->save.rsp = save->rsp; 781 vmcb02->save.rip = save->rip; 782 783 if (unlikely(new_vmcb12 || vmcb12_is_dirty(control, VMCB_DR))) { 784 vmcb02->save.dr7 = svm->nested.save.dr7 | DR7_FIXED_1; 785 svm->vcpu.arch.dr6 = svm->nested.save.dr6 | DR6_ACTIVE_LOW; 786 vmcb_mark_dirty(vmcb02, VMCB_DR); 787 } 788 789 if (nested_vmcb12_has_lbrv(vcpu)) { 790 /* 791 * Reserved bits of DEBUGCTL are ignored. Be consistent with 792 * svm_set_msr's definition of reserved bits. 793 */ 794 svm_copy_lbrs(&vmcb02->save, save); 795 vmcb02->save.dbgctl &= ~DEBUGCTL_RESERVED_BITS; 796 } else { 797 svm_copy_lbrs(&vmcb02->save, &vmcb01->save); 798 } 799 vmcb_mark_dirty(vmcb02, VMCB_LBR); 800 svm_update_lbrv(&svm->vcpu); 801 } 802 803 static inline bool is_evtinj_soft(u32 evtinj) 804 { 805 u32 type = evtinj & SVM_EVTINJ_TYPE_MASK; 806 u8 vector = evtinj & SVM_EVTINJ_VEC_MASK; 807 808 if (!(evtinj & SVM_EVTINJ_VALID)) 809 return false; 810 811 if (type == SVM_EVTINJ_TYPE_SOFT) 812 return true; 813 814 return type == SVM_EVTINJ_TYPE_EXEPT && kvm_exception_is_soft(vector); 815 } 816 817 static bool is_evtinj_nmi(u32 evtinj) 818 { 819 u32 type = evtinj & SVM_EVTINJ_TYPE_MASK; 820 821 if (!(evtinj & SVM_EVTINJ_VALID)) 822 return false; 823 824 return type == SVM_EVTINJ_TYPE_NMI; 825 } 826 827 static void nested_vmcb02_prepare_control(struct vcpu_svm *svm) 828 { 829 u32 int_ctl_vmcb01_bits = V_INTR_MASKING_MASK; 830 u32 int_ctl_vmcb12_bits = V_TPR_MASK | V_IRQ_INJECTION_BITS_MASK; 831 832 struct vmcb_ctrl_area_cached *vmcb12_ctrl = &svm->nested.ctl; 833 struct vmcb *vmcb02 = svm->nested.vmcb02.ptr; 834 struct vmcb *vmcb01 = svm->vmcb01.ptr; 835 struct kvm_vcpu *vcpu = &svm->vcpu; 836 837 nested_svm_transition_tlb_flush(vcpu); 838 839 /* Enter Guest-Mode */ 840 enter_guest_mode(vcpu); 841 842 /* 843 * Filled at exit: exit_code, exit_info_1, exit_info_2, exit_int_info, 844 * exit_int_info_err, next_rip, insn_len, insn_bytes. 845 */ 846 847 if (guest_cpu_cap_has(vcpu, X86_FEATURE_VGIF) && 848 (vmcb12_ctrl->int_ctl & V_GIF_ENABLE_MASK)) 849 int_ctl_vmcb12_bits |= (V_GIF_MASK | V_GIF_ENABLE_MASK); 850 else 851 int_ctl_vmcb01_bits |= (V_GIF_MASK | V_GIF_ENABLE_MASK); 852 853 if (vnmi) { 854 if (vmcb01->control.int_ctl & V_NMI_PENDING_MASK) { 855 svm->vcpu.arch.nmi_pending++; 856 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu); 857 } 858 if (nested_vnmi_enabled(svm)) 859 int_ctl_vmcb12_bits |= (V_NMI_PENDING_MASK | 860 V_NMI_ENABLE_MASK | 861 V_NMI_BLOCKING_MASK); 862 } 863 864 /* 865 * Copied from vmcb01. msrpm_base can be overwritten later. 866 * 867 * SVM_MISC_ENABLE_NP in vmcb12 is only used for consistency checks. If 868 * L1 enables NPTs, KVM shadows L1's NPTs and uses those to run L2. If 869 * L1 disables NPT, KVM runs L2 with the same NPTs used to run L1. For 870 * the latter, L1 runs L2 with shadow page tables that translate L2 GVAs 871 * to L1 GPAs, so the same NPTs can be used for L1 and L2. 872 */ 873 vmcb02->control.misc_ctl = vmcb01->control.misc_ctl & (SVM_MISC_ENABLE_NP | SVM_MISC_ENABLE_GMET); 874 vmcb02->control.iopm_base_pa = vmcb01->control.iopm_base_pa; 875 vmcb02->control.msrpm_base_pa = vmcb01->control.msrpm_base_pa; 876 vmcb_mark_dirty(vmcb02, VMCB_PERM_MAP); 877 878 /* 879 * Stash vmcb02's counter if the guest hasn't moved past the guilty 880 * instruction; otherwise, reset the counter to '0'. 881 * 882 * In order to detect if L2 has made forward progress or not, track the 883 * RIP at which a bus lock has occurred on a per-vmcb12 basis. If RIP 884 * is changed, guest has clearly made forward progress, bus_lock_counter 885 * still remained '1', so reset bus_lock_counter to '0'. Eg. In the 886 * scenario, where a buslock happened in L1 before VMRUN, the bus lock 887 * firmly happened on an instruction in the past. Even if vmcb01's 888 * counter is still '1', (because the guilty instruction got patched), 889 * the vCPU has clearly made forward progress and so KVM should reset 890 * vmcb02's counter to '0'. 891 * 892 * If the RIP hasn't changed, stash the bus lock counter at nested VMRUN 893 * to prevent the same guilty instruction from triggering a VM-Exit. Eg. 894 * if userspace rate-limits the vCPU, then it's entirely possible that 895 * L1's tick interrupt is pending by the time userspace re-runs the 896 * vCPU. If KVM unconditionally clears the counter on VMRUN, then when 897 * L1 re-enters L2, the same instruction will trigger a VM-Exit and the 898 * entire cycle start over. 899 */ 900 if (vmcb02->save.rip && (svm->nested.last_bus_lock_rip == vmcb02->save.rip)) 901 vmcb02->control.bus_lock_counter = 1; 902 else 903 vmcb02->control.bus_lock_counter = 0; 904 905 /* Done at vmrun: asid. */ 906 907 /* Also overwritten later if necessary. */ 908 vmcb02->control.tlb_ctl = TLB_CONTROL_DO_NOTHING; 909 910 /* Use vmcb01 MMU and format if guest does not use nNPT */ 911 if (nested_npt_enabled(svm)) { 912 vmcb02->control.misc_ctl &= ~SVM_MISC_ENABLE_GMET; 913 vmcb02->control.misc_ctl |= (svm->nested.ctl.misc_ctl & SVM_MISC_ENABLE_GMET); 914 915 nested_svm_init_mmu_context(vcpu); 916 } 917 918 vcpu->arch.tsc_offset = kvm_calc_nested_tsc_offset(vcpu->arch.l1_tsc_offset, 919 vmcb12_ctrl->tsc_offset, 920 svm->tsc_ratio_msr); 921 922 vmcb02->control.tsc_offset = vcpu->arch.tsc_offset; 923 924 if (guest_cpu_cap_has(vcpu, X86_FEATURE_TSCRATEMSR) && 925 svm->tsc_ratio_msr != kvm_caps.default_tsc_scaling_ratio) 926 nested_svm_update_tsc_ratio_msr(vcpu); 927 928 vmcb02->control.int_ctl = 929 (vmcb12_ctrl->int_ctl & int_ctl_vmcb12_bits) | 930 (vmcb01->control.int_ctl & int_ctl_vmcb01_bits); 931 932 vmcb02->control.int_vector = vmcb12_ctrl->int_vector; 933 vmcb02->control.int_state = vmcb12_ctrl->int_state; 934 vmcb02->control.event_inj = vmcb12_ctrl->event_inj; 935 vmcb02->control.event_inj_err = vmcb12_ctrl->event_inj_err; 936 937 /* 938 * If nrips is exposed to L1, take NextRIP as-is. Otherwise, L1 939 * advances L2's RIP before VMRUN instead of using NextRIP. KVM will 940 * stuff the current RIP as vmcb02's NextRIP before L2 is run. After 941 * the first run of L2 (e.g. after save+restore), NextRIP is updated by 942 * the CPU and/or KVM and should be used regardless of L1's support. 943 */ 944 if (guest_cpu_cap_has(vcpu, X86_FEATURE_NRIPS) || 945 !vcpu->arch.nested_run_pending) 946 vmcb02->control.next_rip = vmcb12_ctrl->next_rip; 947 948 svm->nmi_l1_to_l2 = is_evtinj_nmi(vmcb02->control.event_inj); 949 950 /* 951 * soft_int_csbase, soft_int_old_rip, and soft_int_next_rip (if L1 952 * doesn't have NRIPS) are initialized later, before the vCPU is run. 953 */ 954 if (is_evtinj_soft(vmcb02->control.event_inj)) { 955 svm->soft_int_injected = true; 956 if (guest_cpu_cap_has(vcpu, X86_FEATURE_NRIPS) || 957 !vcpu->arch.nested_run_pending) 958 svm->soft_int_next_rip = vmcb12_ctrl->next_rip; 959 } 960 961 /* SVM_MISC2_ENABLE_V_LBR is controlled by svm_update_lbrv() */ 962 963 if (!nested_vmcb_needs_vls_intercept(svm)) 964 vmcb02->control.misc_ctl2 |= SVM_MISC2_ENABLE_V_VMLOAD_VMSAVE; 965 966 if (guest_cpu_cap_has(vcpu, X86_FEATURE_PAUSEFILTER)) 967 vmcb02->control.pause_filter_count = vmcb12_ctrl->pause_filter_count; 968 else 969 vmcb02->control.pause_filter_count = 0; 970 if (guest_cpu_cap_has(vcpu, X86_FEATURE_PFTHRESHOLD)) 971 vmcb02->control.pause_filter_thresh = vmcb12_ctrl->pause_filter_thresh; 972 else 973 vmcb02->control.pause_filter_thresh = 0; 974 975 /* 976 * Take ALLOW_LARGER_RAP from vmcb12 even though it should be safe to 977 * let L2 use a larger RAP since KVM will emulate the necessary clears, 978 * as it's possible L1 deliberately wants to restrict L2 to the legacy 979 * RAP size. Unconditionally clear the RAP on nested VMRUN, as KVM is 980 * responsible for emulating the host vs. guest tags (L1 is the "host", 981 * L2 is the "guest"). 982 */ 983 if (guest_cpu_cap_has(vcpu, X86_FEATURE_ERAPS)) 984 vmcb02->control.erap_ctl = (vmcb12_ctrl->erap_ctl & 985 ERAP_CONTROL_ALLOW_LARGER_RAP) | 986 ERAP_CONTROL_CLEAR_RAP; 987 988 /* 989 * Merge guest and host intercepts - must be called with vcpu in 990 * guest-mode to take effect. 991 */ 992 nested_vmcb02_recalc_intercepts(svm); 993 } 994 995 static void nested_svm_copy_common_state(struct vmcb *from_vmcb, struct vmcb *to_vmcb) 996 { 997 /* 998 * Some VMCB state is shared between L1 and L2 and thus has to be 999 * moved at the time of nested vmrun and vmexit. 1000 * 1001 * VMLOAD/VMSAVE state would also belong in this category, but KVM 1002 * always performs VMLOAD and VMSAVE from the VMCB01. 1003 */ 1004 to_vmcb->save.spec_ctrl = from_vmcb->save.spec_ctrl; 1005 } 1006 1007 int enter_svm_guest_mode(struct kvm_vcpu *vcpu, u64 vmcb12_gpa, bool from_vmrun) 1008 { 1009 struct vcpu_svm *svm = to_svm(vcpu); 1010 struct vmcb_ctrl_area_cached *control = &svm->nested.ctl; 1011 struct vmcb_save_area_cached *save = &svm->nested.save; 1012 int ret; 1013 1014 trace_kvm_nested_vmenter(svm->vmcb->save.rip, 1015 vmcb12_gpa, 1016 save->rip, 1017 control->int_ctl, 1018 control->event_inj, 1019 control->misc_ctl, 1020 control->nested_cr3, 1021 save->cr3, 1022 KVM_ISA_SVM); 1023 1024 trace_kvm_nested_intercepts(control->intercepts[INTERCEPT_CR] & 0xffff, 1025 control->intercepts[INTERCEPT_CR] >> 16, 1026 control->intercepts[INTERCEPT_EXCEPTION], 1027 control->intercepts[INTERCEPT_WORD3], 1028 control->intercepts[INTERCEPT_WORD4], 1029 control->intercepts[INTERCEPT_WORD5]); 1030 1031 1032 svm->nested.vmcb12_gpa = vmcb12_gpa; 1033 1034 WARN_ON(svm->vmcb == svm->nested.vmcb02.ptr); 1035 1036 nested_svm_copy_common_state(svm->vmcb01.ptr, svm->nested.vmcb02.ptr); 1037 1038 svm_switch_vmcb(svm, &svm->nested.vmcb02); 1039 nested_vmcb02_prepare_control(svm); 1040 nested_vmcb02_prepare_save(svm); 1041 1042 ret = nested_svm_load_cr3(&svm->vcpu, svm->nested.save.cr3, 1043 nested_npt_enabled(svm), from_vmrun); 1044 if (ret) 1045 return ret; 1046 1047 if (!from_vmrun) 1048 kvm_make_request(KVM_REQ_GET_NESTED_STATE_PAGES, vcpu); 1049 1050 svm_set_gif(svm, true); 1051 1052 if (kvm_vcpu_apicv_active(vcpu)) 1053 kvm_make_request(KVM_REQ_APICV_UPDATE, vcpu); 1054 1055 nested_svm_hv_update_vm_vp_ids(vcpu); 1056 1057 return 0; 1058 } 1059 1060 static int nested_svm_copy_vmcb12_to_cache(struct kvm_vcpu *vcpu, u64 vmcb12_gpa) 1061 { 1062 struct vcpu_svm *svm = to_svm(vcpu); 1063 struct kvm_host_map map; 1064 struct vmcb *vmcb12; 1065 int r = 0; 1066 1067 if (kvm_vcpu_map(vcpu, gpa_to_gfn(vmcb12_gpa), &map)) 1068 return -EFAULT; 1069 1070 vmcb12 = map.hva; 1071 nested_copy_vmcb_control_to_cache(svm, &vmcb12->control); 1072 nested_copy_vmcb_save_to_cache(svm, &vmcb12->save); 1073 1074 if (nested_svm_check_cached_vmcb12(vcpu) < 0) { 1075 vmcb12->control.exit_code = SVM_EXIT_ERR; 1076 vmcb12->control.exit_info_1 = 0; 1077 vmcb12->control.exit_info_2 = 0; 1078 vmcb12->control.event_inj = 0; 1079 vmcb12->control.event_inj_err = 0; 1080 svm_set_gif(svm, false); 1081 r = -EINVAL; 1082 } 1083 1084 kvm_vcpu_unmap(vcpu, &map); 1085 return r; 1086 } 1087 1088 int nested_svm_vmrun(struct kvm_vcpu *vcpu) 1089 { 1090 struct vcpu_svm *svm = to_svm(vcpu); 1091 int ret; 1092 u64 vmcb12_gpa; 1093 struct vmcb *vmcb01 = svm->vmcb01.ptr; 1094 1095 if (!svm->nested.hsave_msr) { 1096 kvm_inject_gp(vcpu, 0); 1097 return 1; 1098 } 1099 1100 if (is_smm(vcpu)) { 1101 kvm_queue_exception(vcpu, UD_VECTOR); 1102 return 1; 1103 } 1104 1105 /* This fails when VP assist page is enabled but the supplied GPA is bogus */ 1106 ret = kvm_hv_verify_vp_assist(vcpu); 1107 if (ret) { 1108 kvm_inject_gp(vcpu, 0); 1109 return ret; 1110 } 1111 1112 if (WARN_ON_ONCE(!svm->nested.initialized)) 1113 return -EINVAL; 1114 1115 vmcb12_gpa = kvm_register_read(vcpu, VCPU_REGS_RAX); 1116 if (!page_address_valid(vcpu, vmcb12_gpa)) { 1117 kvm_inject_gp(vcpu, 0); 1118 return 1; 1119 } 1120 1121 ret = nested_svm_copy_vmcb12_to_cache(vcpu, vmcb12_gpa); 1122 if (ret) { 1123 if (ret == -EFAULT) 1124 return kvm_handle_memory_failure(vcpu, X86EMUL_IO_NEEDED, NULL); 1125 1126 /* Advance RIP past VMRUN as part of the nested #VMEXIT. */ 1127 return kvm_skip_emulated_instruction(vcpu); 1128 } 1129 1130 /* At this point, VMRUN is guaranteed to not fault; advance RIP. */ 1131 ret = kvm_skip_emulated_instruction(vcpu); 1132 1133 /* 1134 * Since vmcb01 is not in use, we can use it to store some of the L1 1135 * state. 1136 */ 1137 vmcb01->save.efer = vcpu->arch.efer; 1138 vmcb01->save.cr0 = kvm_read_cr0(vcpu); 1139 vmcb01->save.cr4 = vcpu->arch.cr4; 1140 vmcb01->save.rflags = kvm_get_rflags(vcpu); 1141 vmcb01->save.rip = kvm_rip_read(vcpu); 1142 1143 if (!npt_enabled) 1144 vmcb01->save.cr3 = kvm_read_cr3(vcpu); 1145 1146 vcpu->arch.nested_run_pending = KVM_NESTED_RUN_PENDING; 1147 1148 if (enter_svm_guest_mode(vcpu, vmcb12_gpa, true) || 1149 !nested_svm_merge_msrpm(vcpu)) { 1150 vcpu->arch.nested_run_pending = 0; 1151 svm->nmi_l1_to_l2 = false; 1152 svm->soft_int_injected = false; 1153 1154 svm->vmcb->control.exit_code = SVM_EXIT_ERR; 1155 svm->vmcb->control.exit_info_1 = 0; 1156 svm->vmcb->control.exit_info_2 = 0; 1157 1158 nested_svm_vmexit(svm); 1159 } 1160 1161 return ret; 1162 } 1163 1164 /* Copy state save area fields which are handled by VMRUN */ 1165 void svm_copy_vmrun_state(struct vmcb_save_area *to_save, 1166 struct vmcb_save_area *from_save) 1167 { 1168 to_save->es = from_save->es; 1169 to_save->cs = from_save->cs; 1170 to_save->ss = from_save->ss; 1171 to_save->ds = from_save->ds; 1172 to_save->gdtr = from_save->gdtr; 1173 to_save->idtr = from_save->idtr; 1174 to_save->rflags = from_save->rflags | X86_EFLAGS_FIXED; 1175 to_save->efer = from_save->efer; 1176 to_save->cr0 = from_save->cr0; 1177 to_save->cr3 = from_save->cr3; 1178 to_save->cr4 = from_save->cr4; 1179 to_save->rax = from_save->rax; 1180 to_save->rsp = from_save->rsp; 1181 to_save->rip = from_save->rip; 1182 to_save->cpl = 0; 1183 1184 if (kvm_cpu_cap_has(X86_FEATURE_SHSTK)) { 1185 to_save->s_cet = from_save->s_cet; 1186 to_save->isst_addr = from_save->isst_addr; 1187 to_save->ssp = from_save->ssp; 1188 } 1189 1190 if (kvm_cpu_cap_has(X86_FEATURE_LBRV)) { 1191 svm_copy_lbrs(to_save, from_save); 1192 to_save->dbgctl &= ~DEBUGCTL_RESERVED_BITS; 1193 } 1194 } 1195 1196 void svm_copy_vmloadsave_state(struct vmcb *to_vmcb, struct vmcb *from_vmcb) 1197 { 1198 to_vmcb->save.fs = from_vmcb->save.fs; 1199 to_vmcb->save.gs = from_vmcb->save.gs; 1200 to_vmcb->save.tr = from_vmcb->save.tr; 1201 to_vmcb->save.ldtr = from_vmcb->save.ldtr; 1202 to_vmcb->save.kernel_gs_base = from_vmcb->save.kernel_gs_base; 1203 to_vmcb->save.star = from_vmcb->save.star; 1204 to_vmcb->save.lstar = from_vmcb->save.lstar; 1205 to_vmcb->save.cstar = from_vmcb->save.cstar; 1206 to_vmcb->save.sfmask = from_vmcb->save.sfmask; 1207 to_vmcb->save.sysenter_cs = from_vmcb->save.sysenter_cs; 1208 to_vmcb->save.sysenter_esp = from_vmcb->save.sysenter_esp; 1209 to_vmcb->save.sysenter_eip = from_vmcb->save.sysenter_eip; 1210 } 1211 1212 static int nested_svm_vmexit_update_vmcb12(struct kvm_vcpu *vcpu) 1213 { 1214 struct vcpu_svm *svm = to_svm(vcpu); 1215 struct vmcb *vmcb02 = svm->nested.vmcb02.ptr; 1216 struct kvm_host_map map; 1217 struct vmcb *vmcb12; 1218 int rc; 1219 1220 rc = kvm_vcpu_map(vcpu, gpa_to_gfn(svm->nested.vmcb12_gpa), &map); 1221 if (rc) 1222 return rc; 1223 1224 vmcb12 = map.hva; 1225 1226 vmcb12->save.es = vmcb02->save.es; 1227 vmcb12->save.cs = vmcb02->save.cs; 1228 vmcb12->save.ss = vmcb02->save.ss; 1229 vmcb12->save.ds = vmcb02->save.ds; 1230 vmcb12->save.gdtr = vmcb02->save.gdtr; 1231 vmcb12->save.idtr = vmcb02->save.idtr; 1232 vmcb12->save.efer = svm->vcpu.arch.efer; 1233 vmcb12->save.cr0 = kvm_read_cr0(vcpu); 1234 vmcb12->save.cr3 = kvm_read_cr3(vcpu); 1235 vmcb12->save.cr2 = vcpu->arch.cr2; 1236 vmcb12->save.cr4 = svm->vcpu.arch.cr4; 1237 vmcb12->save.rflags = kvm_get_rflags(vcpu); 1238 vmcb12->save.rip = kvm_rip_read(vcpu); 1239 vmcb12->save.rsp = kvm_rsp_read(vcpu); 1240 vmcb12->save.rax = kvm_rax_read(vcpu); 1241 vmcb12->save.dr7 = vmcb02->save.dr7; 1242 vmcb12->save.dr6 = svm->vcpu.arch.dr6; 1243 vmcb12->save.cpl = vmcb02->save.cpl; 1244 1245 if (guest_cpu_cap_has(vcpu, X86_FEATURE_SHSTK)) { 1246 vmcb12->save.s_cet = vmcb02->save.s_cet; 1247 vmcb12->save.isst_addr = vmcb02->save.isst_addr; 1248 vmcb12->save.ssp = vmcb02->save.ssp; 1249 } 1250 1251 vmcb12->control.int_state = vmcb02->control.int_state; 1252 vmcb12->control.exit_code = vmcb02->control.exit_code; 1253 vmcb12->control.exit_info_1 = vmcb02->control.exit_info_1; 1254 vmcb12->control.exit_info_2 = vmcb02->control.exit_info_2; 1255 1256 if (!svm_is_vmrun_failure(vmcb12->control.exit_code)) 1257 nested_save_pending_event_to_vmcb12(svm, vmcb12); 1258 1259 if (guest_cpu_cap_has(vcpu, X86_FEATURE_NRIPS)) 1260 vmcb12->control.next_rip = vmcb02->control.next_rip; 1261 1262 if (nested_vmcb12_has_lbrv(vcpu)) 1263 svm_copy_lbrs(&vmcb12->save, &vmcb02->save); 1264 1265 vmcb12->control.event_inj = 0; 1266 vmcb12->control.event_inj_err = 0; 1267 vmcb12->control.int_ctl = svm->nested.ctl.int_ctl; 1268 1269 trace_kvm_nested_vmexit_inject(vmcb12->control.exit_code, 1270 vmcb12->control.exit_info_1, 1271 vmcb12->control.exit_info_2, 1272 vmcb12->control.exit_int_info, 1273 vmcb12->control.exit_int_info_err, 1274 KVM_ISA_SVM); 1275 1276 kvm_vcpu_unmap(vcpu, &map); 1277 return 0; 1278 } 1279 1280 void nested_svm_vmexit(struct vcpu_svm *svm) 1281 { 1282 struct kvm_vcpu *vcpu = &svm->vcpu; 1283 struct vmcb *vmcb01 = svm->vmcb01.ptr; 1284 struct vmcb *vmcb02 = svm->nested.vmcb02.ptr; 1285 1286 if (nested_svm_vmexit_update_vmcb12(vcpu)) 1287 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); 1288 1289 /* Exit Guest-Mode */ 1290 leave_guest_mode(vcpu); 1291 svm->nested.vmcb12_gpa = 0; 1292 1293 kvm_warn_on_nested_run_pending(vcpu); 1294 1295 kvm_clear_request(KVM_REQ_GET_NESTED_STATE_PAGES, vcpu); 1296 1297 /* in case we halted in L2 */ 1298 kvm_set_mp_state(vcpu, KVM_MP_STATE_RUNNABLE); 1299 1300 /* 1301 * Invalidate last_bus_lock_rip unless KVM is still waiting for the 1302 * guest to make forward progress before re-enabling bus lock detection. 1303 */ 1304 if (!vmcb02->control.bus_lock_counter) 1305 svm->nested.last_bus_lock_rip = INVALID_GPA; 1306 1307 nested_svm_copy_common_state(svm->nested.vmcb02.ptr, svm->vmcb01.ptr); 1308 1309 kvm_nested_vmexit_handle_ibrs(vcpu); 1310 1311 if (guest_cpu_cap_has(vcpu, X86_FEATURE_ERAPS)) 1312 vmcb01->control.erap_ctl |= ERAP_CONTROL_CLEAR_RAP; 1313 1314 svm_switch_vmcb(svm, &svm->vmcb01); 1315 1316 /* 1317 * Rules for synchronizing int_ctl bits from vmcb02 to vmcb01: 1318 * 1319 * V_IRQ, V_IRQ_VECTOR, V_INTR_PRIO_MASK, V_IGN_TPR: If L1 doesn't 1320 * intercept interrupts, then KVM will use vmcb02's V_IRQ (and related 1321 * flags) to detect interrupt windows for L1 IRQs (even if L1 uses 1322 * virtual interrupt masking). Raise KVM_REQ_EVENT to ensure that 1323 * KVM re-requests an interrupt window if necessary, which implicitly 1324 * copies this bits from vmcb02 to vmcb01. 1325 * 1326 * V_TPR: If L1 doesn't use virtual interrupt masking, then L1's vTPR 1327 * is stored in vmcb02, but its value doesn't need to be copied from/to 1328 * vmcb01 because it is copied from/to the virtual APIC's TPR register 1329 * on each VM entry/exit. 1330 * 1331 * V_GIF: If nested vGIF is not used, KVM uses vmcb02's V_GIF for L1's 1332 * V_GIF. However, GIF is architecturally clear on each VM exit, thus 1333 * there is no need to copy V_GIF from vmcb02 to vmcb01. 1334 */ 1335 if (!nested_exit_on_intr(svm)) 1336 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu); 1337 1338 if (!nested_vmcb12_has_lbrv(vcpu)) { 1339 svm_copy_lbrs(&vmcb01->save, &vmcb02->save); 1340 vmcb_mark_dirty(vmcb01, VMCB_LBR); 1341 } 1342 1343 svm_update_lbrv(vcpu); 1344 1345 if (vnmi) { 1346 if (vmcb02->control.int_ctl & V_NMI_BLOCKING_MASK) 1347 vmcb01->control.int_ctl |= V_NMI_BLOCKING_MASK; 1348 else 1349 vmcb01->control.int_ctl &= ~V_NMI_BLOCKING_MASK; 1350 1351 if (vcpu->arch.nmi_pending) { 1352 vcpu->arch.nmi_pending--; 1353 vmcb01->control.int_ctl |= V_NMI_PENDING_MASK; 1354 } else { 1355 vmcb01->control.int_ctl &= ~V_NMI_PENDING_MASK; 1356 } 1357 } 1358 1359 /* 1360 * On vmexit the GIF is set to false and 1361 * no event can be injected in L1. 1362 */ 1363 svm_set_gif(svm, false); 1364 vmcb01->control.exit_int_info = 0; 1365 1366 svm->vcpu.arch.tsc_offset = svm->vcpu.arch.l1_tsc_offset; 1367 if (vmcb01->control.tsc_offset != svm->vcpu.arch.tsc_offset) { 1368 vmcb01->control.tsc_offset = svm->vcpu.arch.tsc_offset; 1369 vmcb_mark_dirty(vmcb01, VMCB_INTERCEPTS); 1370 } 1371 1372 if (kvm_caps.has_tsc_control && 1373 vcpu->arch.tsc_scaling_ratio != vcpu->arch.l1_tsc_scaling_ratio) { 1374 vcpu->arch.tsc_scaling_ratio = vcpu->arch.l1_tsc_scaling_ratio; 1375 svm_write_tsc_multiplier(vcpu); 1376 } 1377 1378 svm->nested.ctl.nested_cr3 = 0; 1379 1380 /* 1381 * Restore processor state that had been saved in vmcb01 1382 */ 1383 kvm_set_rflags(vcpu, vmcb01->save.rflags); 1384 svm_set_efer(vcpu, vmcb01->save.efer); 1385 svm_set_cr0(vcpu, vmcb01->save.cr0 | X86_CR0_PE); 1386 svm_set_cr4(vcpu, vmcb01->save.cr4); 1387 kvm_rax_write(vcpu, vmcb01->save.rax); 1388 kvm_rsp_write(vcpu, vmcb01->save.rsp); 1389 kvm_rip_write(vcpu, vmcb01->save.rip); 1390 1391 svm->vcpu.arch.dr7 = DR7_FIXED_1; 1392 kvm_update_dr7(&svm->vcpu); 1393 1394 nested_svm_transition_tlb_flush(vcpu); 1395 1396 nested_svm_uninit_mmu_context(vcpu); 1397 1398 if (nested_svm_load_cr3(vcpu, vmcb01->save.cr3, false, true)) 1399 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); 1400 1401 /* Drop tracking for L1->L2 injected NMIs and soft IRQs */ 1402 svm->nmi_l1_to_l2 = false; 1403 svm->soft_int_injected = false; 1404 1405 /* 1406 * Drop what we picked up for L2 via svm_complete_interrupts() so it 1407 * doesn't end up in L1. 1408 */ 1409 svm->vcpu.arch.nmi_injected = false; 1410 kvm_clear_exception_queue(vcpu); 1411 kvm_clear_interrupt_queue(vcpu); 1412 1413 /* 1414 * If we are here following the completion of a VMRUN that 1415 * is being single-stepped, queue the pending #DB intercept 1416 * right now so that it an be accounted for before we execute 1417 * L1's next instruction. 1418 */ 1419 if (unlikely(vmcb01->save.rflags & X86_EFLAGS_TF)) 1420 kvm_queue_exception(&(svm->vcpu), DB_VECTOR); 1421 1422 /* 1423 * Un-inhibit the AVIC right away, so that other vCPUs can start 1424 * to benefit from it right away. 1425 */ 1426 if (kvm_apicv_activated(vcpu->kvm)) 1427 __kvm_vcpu_update_apicv(vcpu); 1428 } 1429 1430 static void nested_svm_triple_fault(struct kvm_vcpu *vcpu) 1431 { 1432 struct vcpu_svm *svm = to_svm(vcpu); 1433 1434 if (!vmcb12_is_intercept(&svm->nested.ctl, INTERCEPT_SHUTDOWN)) 1435 return; 1436 1437 kvm_clear_request(KVM_REQ_TRIPLE_FAULT, vcpu); 1438 nested_svm_simple_vmexit(to_svm(vcpu), SVM_EXIT_SHUTDOWN); 1439 } 1440 1441 int svm_allocate_nested(struct vcpu_svm *svm) 1442 { 1443 struct page *vmcb02_page; 1444 1445 if (svm->nested.initialized) 1446 return 0; 1447 1448 vmcb02_page = snp_safe_alloc_page(); 1449 if (!vmcb02_page) 1450 return -ENOMEM; 1451 svm->nested.vmcb02.ptr = page_address(vmcb02_page); 1452 svm->nested.vmcb02.pa = __sme_set(page_to_pfn(vmcb02_page) << PAGE_SHIFT); 1453 1454 svm->nested.msrpm = svm_vcpu_alloc_msrpm(); 1455 if (!svm->nested.msrpm) 1456 goto err_free_vmcb02; 1457 1458 svm->nested.initialized = true; 1459 return 0; 1460 1461 err_free_vmcb02: 1462 __free_page(vmcb02_page); 1463 return -ENOMEM; 1464 } 1465 1466 void svm_free_nested(struct vcpu_svm *svm) 1467 { 1468 if (!svm->nested.initialized) 1469 return; 1470 1471 if (WARN_ON_ONCE(svm->vmcb != svm->vmcb01.ptr)) 1472 svm_switch_vmcb(svm, &svm->vmcb01); 1473 1474 svm_vcpu_free_msrpm(svm->nested.msrpm); 1475 svm->nested.msrpm = NULL; 1476 1477 __free_page(virt_to_page(svm->nested.vmcb02.ptr)); 1478 svm->nested.vmcb02.ptr = NULL; 1479 1480 /* 1481 * When last_vmcb12_gpa matches the current vmcb12 gpa, 1482 * some vmcb12 fields are not loaded if they are marked clean 1483 * in the vmcb12, since in this case they are up to date already. 1484 * 1485 * When the vmcb02 is freed, this optimization becomes invalid. 1486 */ 1487 svm->nested.last_vmcb12_gpa = INVALID_GPA; 1488 1489 svm->nested.initialized = false; 1490 } 1491 1492 void svm_leave_nested(struct kvm_vcpu *vcpu) 1493 { 1494 struct vcpu_svm *svm = to_svm(vcpu); 1495 1496 if (is_guest_mode(vcpu)) { 1497 vcpu->arch.nested_run_pending = 0; 1498 svm->nested.vmcb12_gpa = INVALID_GPA; 1499 1500 leave_guest_mode(vcpu); 1501 1502 svm_switch_vmcb(svm, &svm->vmcb01); 1503 1504 nested_svm_uninit_mmu_context(vcpu); 1505 vmcb_mark_all_dirty(svm->vmcb); 1506 1507 svm_set_gif(svm, true); 1508 1509 if (kvm_apicv_activated(vcpu->kvm)) 1510 kvm_make_request(KVM_REQ_APICV_UPDATE, vcpu); 1511 } 1512 1513 kvm_clear_request(KVM_REQ_GET_NESTED_STATE_PAGES, vcpu); 1514 } 1515 1516 static int nested_svm_exit_handled_msr(struct vcpu_svm *svm) 1517 { 1518 gpa_t base = svm->nested.ctl.msrpm_base_pa; 1519 int write, bit_nr; 1520 u8 value, mask; 1521 u32 msr; 1522 1523 if (!(vmcb12_is_intercept(&svm->nested.ctl, INTERCEPT_MSR_PROT))) 1524 return NESTED_EXIT_HOST; 1525 1526 msr = svm->vcpu.arch.regs[VCPU_REGS_RCX]; 1527 bit_nr = svm_msrpm_bit_nr(msr); 1528 write = svm->vmcb->control.exit_info_1 & 1; 1529 1530 if (bit_nr < 0) 1531 return NESTED_EXIT_DONE; 1532 1533 if (kvm_vcpu_read_guest(&svm->vcpu, base + bit_nr / BITS_PER_BYTE, 1534 &value, sizeof(value))) 1535 return NESTED_EXIT_DONE; 1536 1537 mask = BIT(write) << (bit_nr & (BITS_PER_BYTE - 1)); 1538 return (value & mask) ? NESTED_EXIT_DONE : NESTED_EXIT_HOST; 1539 } 1540 1541 static int nested_svm_intercept_ioio(struct vcpu_svm *svm) 1542 { 1543 unsigned port, size, iopm_len; 1544 u16 val, mask; 1545 u8 start_bit; 1546 u64 gpa; 1547 1548 if (!(vmcb12_is_intercept(&svm->nested.ctl, INTERCEPT_IOIO_PROT))) 1549 return NESTED_EXIT_HOST; 1550 1551 port = svm->vmcb->control.exit_info_1 >> 16; 1552 size = (svm->vmcb->control.exit_info_1 & SVM_IOIO_SIZE_MASK) >> 1553 SVM_IOIO_SIZE_SHIFT; 1554 gpa = svm->nested.ctl.iopm_base_pa + (port / 8); 1555 start_bit = port % 8; 1556 iopm_len = (start_bit + size > 8) ? 2 : 1; 1557 mask = (0xf >> (4 - size)) << start_bit; 1558 val = 0; 1559 1560 if (kvm_vcpu_read_guest(&svm->vcpu, gpa, &val, iopm_len)) 1561 return NESTED_EXIT_DONE; 1562 1563 return (val & mask) ? NESTED_EXIT_DONE : NESTED_EXIT_HOST; 1564 } 1565 1566 static int nested_svm_intercept(struct vcpu_svm *svm) 1567 { 1568 u64 exit_code = svm->vmcb->control.exit_code; 1569 int vmexit = NESTED_EXIT_HOST; 1570 1571 if (svm_is_vmrun_failure(exit_code)) 1572 return NESTED_EXIT_DONE; 1573 1574 switch (exit_code) { 1575 case SVM_EXIT_MSR: 1576 vmexit = nested_svm_exit_handled_msr(svm); 1577 break; 1578 case SVM_EXIT_IOIO: 1579 vmexit = nested_svm_intercept_ioio(svm); 1580 break; 1581 case SVM_EXIT_EXCP_BASE ... SVM_EXIT_EXCP_BASE + 0x1f: 1582 /* 1583 * Host-intercepted exceptions have been checked already in 1584 * nested_svm_exit_special. There is nothing to do here, 1585 * the vmexit is injected by svm_check_nested_events. 1586 */ 1587 vmexit = NESTED_EXIT_DONE; 1588 break; 1589 default: 1590 if (vmcb12_is_intercept(&svm->nested.ctl, exit_code)) 1591 vmexit = NESTED_EXIT_DONE; 1592 break; 1593 } 1594 1595 return vmexit; 1596 } 1597 1598 int nested_svm_exit_handled(struct vcpu_svm *svm) 1599 { 1600 int vmexit; 1601 1602 vmexit = nested_svm_intercept(svm); 1603 1604 if (vmexit == NESTED_EXIT_DONE) 1605 nested_svm_vmexit(svm); 1606 1607 return vmexit; 1608 } 1609 1610 int nested_svm_check_permissions(struct kvm_vcpu *vcpu) 1611 { 1612 if (!(vcpu->arch.efer & EFER_SVME) || !is_paging(vcpu)) { 1613 kvm_queue_exception(vcpu, UD_VECTOR); 1614 return 1; 1615 } 1616 1617 if (to_svm(vcpu)->vmcb->save.cpl) { 1618 kvm_inject_gp(vcpu, 0); 1619 return 1; 1620 } 1621 1622 return 0; 1623 } 1624 1625 static bool nested_svm_is_exception_vmexit(struct kvm_vcpu *vcpu, u8 vector, 1626 u32 error_code) 1627 { 1628 struct vcpu_svm *svm = to_svm(vcpu); 1629 1630 return (svm->nested.ctl.intercepts[INTERCEPT_EXCEPTION] & BIT(vector)); 1631 } 1632 1633 static void nested_svm_inject_exception_vmexit(struct kvm_vcpu *vcpu) 1634 { 1635 struct kvm_queued_exception *ex = &vcpu->arch.exception_vmexit; 1636 struct vcpu_svm *svm = to_svm(vcpu); 1637 struct vmcb *vmcb = svm->vmcb; 1638 1639 vmcb->control.exit_code = SVM_EXIT_EXCP_BASE + ex->vector; 1640 1641 if (ex->has_error_code) 1642 vmcb->control.exit_info_1 = ex->error_code; 1643 1644 /* 1645 * EXITINFO2 is undefined for all exception intercepts other 1646 * than #PF. 1647 */ 1648 if (ex->vector == PF_VECTOR) { 1649 if (ex->has_payload) 1650 vmcb->control.exit_info_2 = ex->payload; 1651 else 1652 vmcb->control.exit_info_2 = vcpu->arch.cr2; 1653 } else if (ex->vector == DB_VECTOR) { 1654 /* See kvm_check_and_inject_events(). */ 1655 kvm_deliver_exception_payload(vcpu, ex); 1656 1657 if (vcpu->arch.dr7 & DR7_GD) { 1658 vcpu->arch.dr7 &= ~DR7_GD; 1659 kvm_update_dr7(vcpu); 1660 } 1661 } else { 1662 WARN_ON(ex->has_payload); 1663 } 1664 1665 nested_svm_vmexit(svm); 1666 } 1667 1668 static inline bool nested_exit_on_init(struct vcpu_svm *svm) 1669 { 1670 return vmcb12_is_intercept(&svm->nested.ctl, INTERCEPT_INIT); 1671 } 1672 1673 static int svm_check_nested_events(struct kvm_vcpu *vcpu) 1674 { 1675 struct kvm_lapic *apic = vcpu->arch.apic; 1676 struct vcpu_svm *svm = to_svm(vcpu); 1677 /* 1678 * Only a pending nested run blocks a pending exception. If there is a 1679 * previously injected event, the pending exception occurred while said 1680 * event was being delivered and thus needs to be handled. 1681 */ 1682 bool block_nested_exceptions = vcpu->arch.nested_run_pending; 1683 /* 1684 * New events (not exceptions) are only recognized at instruction 1685 * boundaries. If an event needs reinjection, then KVM is handling a 1686 * VM-Exit that occurred _during_ instruction execution; new events are 1687 * blocked until the instruction completes. 1688 */ 1689 bool block_nested_events = block_nested_exceptions || 1690 kvm_event_needs_reinjection(vcpu); 1691 1692 if (lapic_in_kernel(vcpu) && 1693 test_bit(KVM_APIC_INIT, &apic->pending_events)) { 1694 if (block_nested_events) 1695 return -EBUSY; 1696 if (!nested_exit_on_init(svm)) 1697 return 0; 1698 nested_svm_simple_vmexit(svm, SVM_EXIT_INIT); 1699 return 0; 1700 } 1701 1702 if (vcpu->arch.exception_vmexit.pending) { 1703 if (block_nested_exceptions) 1704 return -EBUSY; 1705 nested_svm_inject_exception_vmexit(vcpu); 1706 return 0; 1707 } 1708 1709 if (vcpu->arch.exception.pending) { 1710 if (block_nested_exceptions) 1711 return -EBUSY; 1712 return 0; 1713 } 1714 1715 #ifdef CONFIG_KVM_SMM 1716 if (vcpu->arch.smi_pending && !svm_smi_blocked(vcpu)) { 1717 if (block_nested_events) 1718 return -EBUSY; 1719 if (!nested_exit_on_smi(svm)) 1720 return 0; 1721 nested_svm_simple_vmexit(svm, SVM_EXIT_SMI); 1722 return 0; 1723 } 1724 #endif 1725 1726 if (vcpu->arch.nmi_pending && !svm_nmi_blocked(vcpu)) { 1727 if (block_nested_events) 1728 return -EBUSY; 1729 if (!nested_exit_on_nmi(svm)) 1730 return 0; 1731 nested_svm_simple_vmexit(svm, SVM_EXIT_NMI); 1732 return 0; 1733 } 1734 1735 if (kvm_cpu_has_interrupt(vcpu) && !svm_interrupt_blocked(vcpu)) { 1736 if (block_nested_events) 1737 return -EBUSY; 1738 if (!nested_exit_on_intr(svm)) 1739 return 0; 1740 trace_kvm_nested_intr_vmexit(svm->vmcb->save.rip); 1741 nested_svm_simple_vmexit(svm, SVM_EXIT_INTR); 1742 return 0; 1743 } 1744 1745 return 0; 1746 } 1747 1748 int nested_svm_exit_special(struct vcpu_svm *svm) 1749 { 1750 u32 exit_code = svm->vmcb->control.exit_code; 1751 struct kvm_vcpu *vcpu = &svm->vcpu; 1752 1753 switch (exit_code) { 1754 case SVM_EXIT_INTR: 1755 case SVM_EXIT_NMI: 1756 case SVM_EXIT_NPF: 1757 return NESTED_EXIT_HOST; 1758 case SVM_EXIT_EXCP_BASE ... SVM_EXIT_EXCP_BASE + 0x1f: { 1759 u32 excp_bits = 1 << (exit_code - SVM_EXIT_EXCP_BASE); 1760 1761 if (svm->vmcb01.ptr->control.intercepts[INTERCEPT_EXCEPTION] & 1762 excp_bits) 1763 return NESTED_EXIT_HOST; 1764 else if (exit_code == SVM_EXIT_EXCP_BASE + PF_VECTOR && 1765 svm->vcpu.arch.apf.host_apf_flags) 1766 /* Trap async PF even if not shadowing */ 1767 return NESTED_EXIT_HOST; 1768 break; 1769 } 1770 case SVM_EXIT_VMMCALL: 1771 /* Hyper-V L2 TLB flush hypercall is handled by L0 */ 1772 if (nested_svm_is_l2_tlb_flush_hcall(vcpu)) 1773 return NESTED_EXIT_HOST; 1774 break; 1775 default: 1776 break; 1777 } 1778 1779 return NESTED_EXIT_CONTINUE; 1780 } 1781 1782 void nested_svm_update_tsc_ratio_msr(struct kvm_vcpu *vcpu) 1783 { 1784 struct vcpu_svm *svm = to_svm(vcpu); 1785 1786 vcpu->arch.tsc_scaling_ratio = 1787 kvm_calc_nested_tsc_multiplier(vcpu->arch.l1_tsc_scaling_ratio, 1788 svm->tsc_ratio_msr); 1789 svm_write_tsc_multiplier(vcpu); 1790 } 1791 1792 /* Inverse operation of nested_copy_vmcb_control_to_cache(). asid is copied too. */ 1793 static void nested_copy_vmcb_cache_to_control(struct vmcb_control_area *dst, 1794 struct vmcb_ctrl_area_cached *from) 1795 { 1796 unsigned int i; 1797 1798 memset(dst, 0, sizeof(struct vmcb_control_area)); 1799 1800 for (i = 0; i < MAX_INTERCEPT; i++) 1801 dst->intercepts[i] = from->intercepts[i]; 1802 1803 dst->iopm_base_pa = from->iopm_base_pa; 1804 dst->msrpm_base_pa = from->msrpm_base_pa; 1805 dst->tsc_offset = from->tsc_offset; 1806 dst->asid = from->asid; 1807 dst->tlb_ctl = from->tlb_ctl; 1808 dst->erap_ctl = from->erap_ctl; 1809 dst->int_ctl = from->int_ctl; 1810 dst->int_vector = from->int_vector; 1811 dst->int_state = from->int_state; 1812 dst->exit_code = from->exit_code; 1813 dst->exit_info_1 = from->exit_info_1; 1814 dst->exit_info_2 = from->exit_info_2; 1815 dst->exit_int_info = from->exit_int_info; 1816 dst->exit_int_info_err = from->exit_int_info_err; 1817 dst->misc_ctl = from->misc_ctl; 1818 dst->event_inj = from->event_inj; 1819 dst->event_inj_err = from->event_inj_err; 1820 dst->next_rip = from->next_rip; 1821 dst->nested_cr3 = from->nested_cr3; 1822 dst->misc_ctl2 = from->misc_ctl2; 1823 dst->pause_filter_count = from->pause_filter_count; 1824 dst->pause_filter_thresh = from->pause_filter_thresh; 1825 /* 'clean' and 'hv_enlightenments' are not changed by KVM */ 1826 } 1827 1828 static int svm_get_nested_state(struct kvm_vcpu *vcpu, 1829 struct kvm_nested_state __user *user_kvm_nested_state, 1830 u32 user_data_size) 1831 { 1832 struct vcpu_svm *svm; 1833 struct vmcb_control_area *ctl; 1834 unsigned long r; 1835 struct kvm_nested_state kvm_state = { 1836 .flags = 0, 1837 .format = KVM_STATE_NESTED_FORMAT_SVM, 1838 .size = sizeof(kvm_state), 1839 }; 1840 struct vmcb __user *user_vmcb = (struct vmcb __user *) 1841 &user_kvm_nested_state->data.svm[0]; 1842 1843 if (!vcpu) 1844 return kvm_state.size + KVM_STATE_NESTED_SVM_VMCB_SIZE; 1845 1846 svm = to_svm(vcpu); 1847 1848 if (user_data_size < kvm_state.size) 1849 goto out; 1850 1851 /* First fill in the header and copy it out. */ 1852 if (is_guest_mode(vcpu)) { 1853 kvm_state.hdr.svm.vmcb_pa = svm->nested.vmcb12_gpa; 1854 kvm_state.size += KVM_STATE_NESTED_SVM_VMCB_SIZE; 1855 kvm_state.flags |= KVM_STATE_NESTED_GUEST_MODE; 1856 1857 if (vcpu->arch.nested_run_pending) 1858 kvm_state.flags |= KVM_STATE_NESTED_RUN_PENDING; 1859 } 1860 1861 if (gif_set(svm)) 1862 kvm_state.flags |= KVM_STATE_NESTED_GIF_SET; 1863 1864 if (copy_to_user(user_kvm_nested_state, &kvm_state, sizeof(kvm_state))) 1865 return -EFAULT; 1866 1867 if (!is_guest_mode(vcpu)) 1868 goto out; 1869 1870 /* 1871 * Copy over the full size of the VMCB rather than just the size 1872 * of the structs. 1873 */ 1874 if (clear_user(user_vmcb, KVM_STATE_NESTED_SVM_VMCB_SIZE)) 1875 return -EFAULT; 1876 1877 ctl = kzalloc_obj(*ctl); 1878 if (!ctl) 1879 return -ENOMEM; 1880 1881 nested_copy_vmcb_cache_to_control(ctl, &svm->nested.ctl); 1882 r = copy_to_user(&user_vmcb->control, ctl, 1883 sizeof(user_vmcb->control)); 1884 kfree(ctl); 1885 if (r) 1886 return -EFAULT; 1887 1888 if (copy_to_user(&user_vmcb->save, &svm->vmcb01.ptr->save, 1889 sizeof(user_vmcb->save))) 1890 return -EFAULT; 1891 out: 1892 return kvm_state.size; 1893 } 1894 1895 static int svm_set_nested_state(struct kvm_vcpu *vcpu, 1896 struct kvm_nested_state __user *user_kvm_nested_state, 1897 struct kvm_nested_state *kvm_state) 1898 { 1899 struct vcpu_svm *svm = to_svm(vcpu); 1900 struct vmcb __user *user_vmcb = (struct vmcb __user *) 1901 &user_kvm_nested_state->data.svm[0]; 1902 struct vmcb_control_area *ctl; 1903 struct vmcb_save_area *save; 1904 struct vmcb_save_area_cached save_cached; 1905 struct vmcb_ctrl_area_cached ctl_cached; 1906 unsigned long cr0; 1907 int ret; 1908 1909 BUILD_BUG_ON(sizeof(struct vmcb_control_area) + sizeof(struct vmcb_save_area) > 1910 KVM_STATE_NESTED_SVM_VMCB_SIZE); 1911 1912 if (kvm_state->format != KVM_STATE_NESTED_FORMAT_SVM) 1913 return -EINVAL; 1914 1915 if (kvm_state->flags & ~(KVM_STATE_NESTED_GUEST_MODE | 1916 KVM_STATE_NESTED_RUN_PENDING | 1917 KVM_STATE_NESTED_GIF_SET)) 1918 return -EINVAL; 1919 1920 /* 1921 * If in guest mode, vcpu->arch.efer actually refers to the L2 guest's 1922 * EFER.SVME, but EFER.SVME still has to be 1 for VMRUN to succeed. 1923 * If SVME is disabled, the only valid states are "none" and GIF=1 1924 * (clearing SVME does NOT set GIF, i.e. GIF=0 is allowed). 1925 */ 1926 if (!(vcpu->arch.efer & EFER_SVME) && kvm_state->flags && 1927 kvm_state->flags != KVM_STATE_NESTED_GIF_SET) 1928 return -EINVAL; 1929 1930 /* SMM temporarily disables SVM, so we cannot be in guest mode. */ 1931 if (is_smm(vcpu) && (kvm_state->flags & KVM_STATE_NESTED_GUEST_MODE)) 1932 return -EINVAL; 1933 1934 if (!(kvm_state->flags & KVM_STATE_NESTED_GUEST_MODE)) { 1935 svm_leave_nested(vcpu); 1936 svm_set_gif(svm, !!(kvm_state->flags & KVM_STATE_NESTED_GIF_SET)); 1937 return 0; 1938 } 1939 1940 if (!page_address_valid(vcpu, kvm_state->hdr.svm.vmcb_pa)) 1941 return -EINVAL; 1942 if (kvm_state->size < sizeof(*kvm_state) + KVM_STATE_NESTED_SVM_VMCB_SIZE) 1943 return -EINVAL; 1944 1945 ctl = memdup_user(&user_vmcb->control, sizeof(*ctl)); 1946 if (IS_ERR(ctl)) 1947 return PTR_ERR(ctl); 1948 1949 save = memdup_user(&user_vmcb->save, sizeof(*save)); 1950 if (IS_ERR(save)) { 1951 kfree(ctl); 1952 return PTR_ERR(save); 1953 } 1954 1955 ret = -EINVAL; 1956 __nested_copy_vmcb_control_to_cache(vcpu, &ctl_cached, ctl); 1957 if (!nested_vmcb_check_controls(vcpu, &ctl_cached)) 1958 goto out_free; 1959 1960 /* 1961 * Processor state contains L2 state. Check that it is 1962 * valid for guest mode (see nested_vmcb_check_save()). 1963 */ 1964 cr0 = kvm_read_cr0(vcpu); 1965 if (((cr0 & X86_CR0_CD) == 0) && (cr0 & X86_CR0_NW)) 1966 goto out_free; 1967 1968 /* 1969 * Validate host state saved from before VMRUN (see 1970 * nested_svm_check_permissions). 1971 */ 1972 __nested_copy_vmcb_save_to_cache(&save_cached, save); 1973 if (!(save->cr0 & X86_CR0_PG) || 1974 !(save->cr0 & X86_CR0_PE) || 1975 (save->rflags & X86_EFLAGS_VM) || 1976 !nested_vmcb_check_save(vcpu, &save_cached)) 1977 goto out_free; 1978 1979 1980 /* 1981 * All checks done, we can enter guest mode. Userspace provides 1982 * vmcb12.control, which will be combined with L1 and stored into 1983 * vmcb02, and the L1 save state which we store in vmcb01. 1984 * L2 registers if needed are moved from the current VMCB to VMCB02. 1985 */ 1986 1987 if (is_guest_mode(vcpu)) 1988 svm_leave_nested(vcpu); 1989 else 1990 svm->nested.vmcb02.ptr->save = svm->vmcb01.ptr->save; 1991 1992 svm_set_gif(svm, !!(kvm_state->flags & KVM_STATE_NESTED_GIF_SET)); 1993 1994 if (kvm_state->flags & KVM_STATE_NESTED_RUN_PENDING) 1995 vcpu->arch.nested_run_pending = KVM_NESTED_RUN_PENDING_UNTRUSTED; 1996 else 1997 vcpu->arch.nested_run_pending = 0; 1998 1999 svm->nested.vmcb12_gpa = kvm_state->hdr.svm.vmcb_pa; 2000 2001 svm_copy_vmrun_state(&svm->vmcb01.ptr->save, save); 2002 nested_copy_vmcb_control_to_cache(svm, ctl); 2003 2004 svm_switch_vmcb(svm, &svm->nested.vmcb02); 2005 nested_vmcb02_prepare_control(svm); 2006 2007 /* 2008 * Any previously restored state (e.g. KVM_SET_SREGS) would mark fields 2009 * dirty in vmcb01 instead of vmcb02, so mark all of vmcb02 dirty here. 2010 */ 2011 vmcb_mark_all_dirty(svm->vmcb); 2012 2013 /* 2014 * While the nested guest CR3 is already checked and set by 2015 * KVM_SET_SREGS, it was set when nested state was yet loaded, 2016 * thus MMU might not be initialized correctly. 2017 * Set it again to fix this. 2018 */ 2019 ret = nested_svm_load_cr3(&svm->vcpu, vcpu->arch.cr3, 2020 nested_npt_enabled(svm), false); 2021 if (ret) 2022 goto out_free; 2023 2024 svm->nested.force_msr_bitmap_recalc = true; 2025 2026 if (kvm_vcpu_apicv_active(vcpu)) 2027 kvm_make_request(KVM_REQ_APICV_UPDATE, vcpu); 2028 2029 kvm_make_request(KVM_REQ_GET_NESTED_STATE_PAGES, vcpu); 2030 ret = 0; 2031 out_free: 2032 kfree(save); 2033 kfree(ctl); 2034 2035 return ret; 2036 } 2037 2038 static bool svm_get_nested_state_pages(struct kvm_vcpu *vcpu) 2039 { 2040 if (WARN_ON(!is_guest_mode(vcpu))) 2041 return true; 2042 2043 if (!vcpu->arch.pdptrs_from_userspace && 2044 !nested_npt_enabled(to_svm(vcpu)) && is_pae_paging(vcpu)) 2045 /* 2046 * Reload the guest's PDPTRs since after a migration 2047 * the guest CR3 might be restored prior to setting the nested 2048 * state which can lead to a load of wrong PDPTRs. 2049 */ 2050 if (CC(!load_pdptrs(vcpu, vcpu->arch.cr3))) 2051 return false; 2052 2053 if (!nested_svm_merge_msrpm(vcpu)) { 2054 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR; 2055 vcpu->run->internal.suberror = 2056 KVM_INTERNAL_ERROR_EMULATION; 2057 vcpu->run->internal.ndata = 0; 2058 return false; 2059 } 2060 2061 if (kvm_hv_verify_vp_assist(vcpu)) 2062 return false; 2063 2064 return true; 2065 } 2066 2067 static gpa_t svm_translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, 2068 u64 access, 2069 struct x86_exception *exception, 2070 u64 pte_access) 2071 { 2072 struct vcpu_svm *svm = to_svm(vcpu); 2073 struct kvm_mmu *mmu = vcpu->arch.mmu; 2074 2075 BUG_ON(!mmu_is_nested(vcpu)); 2076 2077 /* Non-GMET walks are always user-walks */ 2078 if (!(svm->nested.ctl.misc_ctl & SVM_MISC_ENABLE_GMET)) 2079 access |= PFERR_USER_MASK; 2080 2081 return mmu->gva_to_gpa(vcpu, mmu, gpa, access, exception); 2082 } 2083 2084 struct kvm_x86_nested_ops svm_nested_ops = { 2085 .leave_nested = svm_leave_nested, 2086 .translate_nested_gpa = svm_translate_nested_gpa, 2087 .is_exception_vmexit = nested_svm_is_exception_vmexit, 2088 .check_events = svm_check_nested_events, 2089 .triple_fault = nested_svm_triple_fault, 2090 .get_nested_state_pages = svm_get_nested_state_pages, 2091 .get_state = svm_get_nested_state, 2092 .set_state = svm_set_nested_state, 2093 .hv_inject_synthetic_vmexit_post_tlb_flush = svm_hv_inject_synthetic_vmexit_post_tlb_flush, 2094 }; 2095