1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef ARCH_X86_KVM_REVERSE_CPUID_H 3 #define ARCH_X86_KVM_REVERSE_CPUID_H 4 5 #include <uapi/asm/kvm.h> 6 7 #include <asm/cpufeature.h> 8 #include <asm/cpufeatures.h> 9 #include <asm/cpuid/types.h> 10 11 /* 12 * Define a KVM-only feature flag. 13 * 14 * For features that are scattered by cpufeatures.h, __feature_translate() also 15 * needs to be updated to translate the kernel-defined feature into the 16 * KVM-defined feature. 17 * 18 * For features that are 100% KVM-only, i.e. not defined by cpufeatures.h, 19 * forego the intermediate KVM_X86_FEATURE and directly define X86_FEATURE_* so 20 * that X86_FEATURE_* can be used in KVM. No __feature_translate() handling is 21 * needed in this case. 22 */ 23 #define KVM_X86_FEATURE(w, f) ((w)*32 + (f)) 24 25 /* Intel-defined SGX sub-features, CPUID level 0x12 (EAX). */ 26 #define KVM_X86_FEATURE_SGX1 KVM_X86_FEATURE(CPUID_12_EAX, 0) 27 #define KVM_X86_FEATURE_SGX2 KVM_X86_FEATURE(CPUID_12_EAX, 1) 28 #define KVM_X86_FEATURE_SGX_EDECCSSA KVM_X86_FEATURE(CPUID_12_EAX, 11) 29 30 /* Intel-defined sub-features, CPUID level 0x00000007:1 (ECX) */ 31 #define KVM_X86_FEATURE_MSR_IMM KVM_X86_FEATURE(CPUID_7_1_ECX, 5) 32 33 /* Intel-defined sub-features, CPUID level 0x00000007:1 (EDX) */ 34 #define X86_FEATURE_AVX_VNNI_INT8 KVM_X86_FEATURE(CPUID_7_1_EDX, 4) 35 #define X86_FEATURE_AVX_NE_CONVERT KVM_X86_FEATURE(CPUID_7_1_EDX, 5) 36 #define X86_FEATURE_AMX_COMPLEX KVM_X86_FEATURE(CPUID_7_1_EDX, 8) 37 #define X86_FEATURE_AVX_VNNI_INT16 KVM_X86_FEATURE(CPUID_7_1_EDX, 10) 38 #define X86_FEATURE_PREFETCHITI KVM_X86_FEATURE(CPUID_7_1_EDX, 14) 39 #define X86_FEATURE_AVX10 KVM_X86_FEATURE(CPUID_7_1_EDX, 19) 40 41 /* Intel-defined sub-features, CPUID level 0x00000007:2 (EDX) */ 42 #define X86_FEATURE_INTEL_PSFD KVM_X86_FEATURE(CPUID_7_2_EDX, 0) 43 #define X86_FEATURE_IPRED_CTRL KVM_X86_FEATURE(CPUID_7_2_EDX, 1) 44 #define KVM_X86_FEATURE_RRSBA_CTRL KVM_X86_FEATURE(CPUID_7_2_EDX, 2) 45 #define X86_FEATURE_DDPD_U KVM_X86_FEATURE(CPUID_7_2_EDX, 3) 46 #define KVM_X86_FEATURE_BHI_CTRL KVM_X86_FEATURE(CPUID_7_2_EDX, 4) 47 #define X86_FEATURE_MCDT_NO KVM_X86_FEATURE(CPUID_7_2_EDX, 5) 48 49 /* 50 * Intel-defined sub-features, CPUID level 0x0000001E:1 (EAX). Note, several 51 * of the bits are aliases to features of the same name that are enumerated via 52 * various CPUID.0x7 sub-leafs. 53 */ 54 #define X86_FEATURE_AMX_INT8_ALIAS KVM_X86_FEATURE(CPUID_1E_1_EAX, 0) 55 #define X86_FEATURE_AMX_BF16_ALIAS KVM_X86_FEATURE(CPUID_1E_1_EAX, 1) 56 #define X86_FEATURE_AMX_COMPLEX_ALIAS KVM_X86_FEATURE(CPUID_1E_1_EAX, 2) 57 #define X86_FEATURE_AMX_FP16_ALIAS KVM_X86_FEATURE(CPUID_1E_1_EAX, 3) 58 #define X86_FEATURE_AMX_FP8 KVM_X86_FEATURE(CPUID_1E_1_EAX, 4) 59 #define X86_FEATURE_AMX_TF32 KVM_X86_FEATURE(CPUID_1E_1_EAX, 6) 60 #define X86_FEATURE_AMX_AVX512 KVM_X86_FEATURE(CPUID_1E_1_EAX, 7) 61 #define X86_FEATURE_AMX_MOVRS KVM_X86_FEATURE(CPUID_1E_1_EAX, 8) 62 63 /* Intel-defined sub-features, CPUID level 0x00000024:0 (EBX) */ 64 #define X86_FEATURE_AVX10_128 KVM_X86_FEATURE(CPUID_24_0_EBX, 16) 65 #define X86_FEATURE_AVX10_256 KVM_X86_FEATURE(CPUID_24_0_EBX, 17) 66 #define X86_FEATURE_AVX10_512 KVM_X86_FEATURE(CPUID_24_0_EBX, 18) 67 68 /* Intel-defined sub-features, CPUID level 0x00000024:1 (ECX) */ 69 #define X86_FEATURE_AVX10_VNNI_INT KVM_X86_FEATURE(CPUID_24_1_ECX, 2) 70 71 /* CPUID level 0x80000007 (EDX). */ 72 #define KVM_X86_FEATURE_CONSTANT_TSC KVM_X86_FEATURE(CPUID_8000_0007_EDX, 8) 73 74 /* CPUID level 0x80000022 (EAX) */ 75 #define KVM_X86_FEATURE_PERFMON_V2 KVM_X86_FEATURE(CPUID_8000_0022_EAX, 0) 76 77 /* CPUID level 0x80000021 (ECX) */ 78 #define KVM_X86_FEATURE_TSA_SQ_NO KVM_X86_FEATURE(CPUID_8000_0021_ECX, 1) 79 #define KVM_X86_FEATURE_TSA_L1_NO KVM_X86_FEATURE(CPUID_8000_0021_ECX, 2) 80 81 struct cpuid_reg { 82 u32 function; 83 u32 index; 84 int reg; 85 }; 86 87 static const struct cpuid_reg reverse_cpuid[] = { 88 [CPUID_1_EDX] = { 1, 0, CPUID_EDX}, 89 [CPUID_8000_0001_EDX] = {0x80000001, 0, CPUID_EDX}, 90 [CPUID_8086_0001_EDX] = {0x80860001, 0, CPUID_EDX}, 91 [CPUID_1_ECX] = { 1, 0, CPUID_ECX}, 92 [CPUID_C000_0001_EDX] = {0xc0000001, 0, CPUID_EDX}, 93 [CPUID_8000_0001_ECX] = {0x80000001, 0, CPUID_ECX}, 94 [CPUID_7_0_EBX] = { 7, 0, CPUID_EBX}, 95 [CPUID_D_1_EAX] = { 0xd, 1, CPUID_EAX}, 96 [CPUID_8000_0008_EBX] = {0x80000008, 0, CPUID_EBX}, 97 [CPUID_6_EAX] = { 6, 0, CPUID_EAX}, 98 [CPUID_8000_000A_EDX] = {0x8000000a, 0, CPUID_EDX}, 99 [CPUID_7_ECX] = { 7, 0, CPUID_ECX}, 100 [CPUID_7_EDX] = { 7, 0, CPUID_EDX}, 101 [CPUID_7_1_EAX] = { 7, 1, CPUID_EAX}, 102 [CPUID_12_EAX] = {0x00000012, 0, CPUID_EAX}, 103 [CPUID_8000_001F_EAX] = {0x8000001f, 0, CPUID_EAX}, 104 [CPUID_7_1_EDX] = { 7, 1, CPUID_EDX}, 105 [CPUID_8000_0007_EDX] = {0x80000007, 0, CPUID_EDX}, 106 [CPUID_8000_0021_EAX] = {0x80000021, 0, CPUID_EAX}, 107 [CPUID_8000_0022_EAX] = {0x80000022, 0, CPUID_EAX}, 108 [CPUID_7_2_EDX] = { 7, 2, CPUID_EDX}, 109 [CPUID_24_0_EBX] = { 0x24, 0, CPUID_EBX}, 110 [CPUID_8000_0021_ECX] = {0x80000021, 0, CPUID_ECX}, 111 [CPUID_7_1_ECX] = { 7, 1, CPUID_ECX}, 112 [CPUID_1E_1_EAX] = { 0x1e, 1, CPUID_EAX}, 113 [CPUID_24_1_ECX] = { 0x24, 1, CPUID_ECX}, 114 }; 115 116 /* 117 * Reverse CPUID and its derivatives can only be used for hardware-defined 118 * feature words, i.e. words whose bits directly correspond to a CPUID leaf. 119 * Retrieving a feature bit or masking guest CPUID from a Linux-defined word 120 * is nonsensical as the bit number/mask is an arbitrary software-defined value 121 * and can't be used by KVM to query/control guest capabilities. And obviously 122 * the leaf being queried must have an entry in the lookup table. 123 */ 124 static __always_inline void reverse_cpuid_check(unsigned int x86_leaf) 125 { 126 BUILD_BUG_ON(NR_CPUID_WORDS != NCAPINTS); 127 BUILD_BUG_ON(x86_leaf == CPUID_LNX_1); 128 BUILD_BUG_ON(x86_leaf == CPUID_LNX_2); 129 BUILD_BUG_ON(x86_leaf == CPUID_LNX_3); 130 BUILD_BUG_ON(x86_leaf == CPUID_LNX_4); 131 BUILD_BUG_ON(x86_leaf == CPUID_LNX_5); 132 BUILD_BUG_ON(x86_leaf >= ARRAY_SIZE(reverse_cpuid)); 133 BUILD_BUG_ON(reverse_cpuid[x86_leaf].function == 0); 134 } 135 136 /* 137 * Translate feature bits that are scattered in the kernel's cpufeatures word 138 * into KVM feature words that align with hardware's definitions. 139 */ 140 static __always_inline u32 __feature_translate(int x86_feature) 141 { 142 #define KVM_X86_TRANSLATE_FEATURE(f) \ 143 case X86_FEATURE_##f: return KVM_X86_FEATURE_##f 144 145 switch (x86_feature) { 146 KVM_X86_TRANSLATE_FEATURE(SGX1); 147 KVM_X86_TRANSLATE_FEATURE(SGX2); 148 KVM_X86_TRANSLATE_FEATURE(SGX_EDECCSSA); 149 KVM_X86_TRANSLATE_FEATURE(CONSTANT_TSC); 150 KVM_X86_TRANSLATE_FEATURE(PERFMON_V2); 151 KVM_X86_TRANSLATE_FEATURE(RRSBA_CTRL); 152 KVM_X86_TRANSLATE_FEATURE(BHI_CTRL); 153 KVM_X86_TRANSLATE_FEATURE(TSA_SQ_NO); 154 KVM_X86_TRANSLATE_FEATURE(TSA_L1_NO); 155 KVM_X86_TRANSLATE_FEATURE(MSR_IMM); 156 default: 157 return x86_feature; 158 } 159 } 160 161 static __always_inline u32 __feature_leaf(int x86_feature) 162 { 163 u32 x86_leaf = __feature_translate(x86_feature) / 32; 164 165 reverse_cpuid_check(x86_leaf); 166 return x86_leaf; 167 } 168 169 /* 170 * Retrieve the bit mask from an X86_FEATURE_* definition. Features contain 171 * the hardware defined bit number (stored in bits 4:0) and a software defined 172 * "word" (stored in bits 31:5). The word is used to index into arrays of 173 * bit masks that hold the per-cpu feature capabilities, e.g. this_cpu_has(). 174 */ 175 static __always_inline u32 __feature_bit(int x86_feature) 176 { 177 x86_feature = __feature_translate(x86_feature); 178 179 reverse_cpuid_check(x86_feature / 32); 180 return 1 << (x86_feature & 31); 181 } 182 183 #define feature_bit(name) __feature_bit(X86_FEATURE_##name) 184 185 static __always_inline struct cpuid_reg x86_feature_cpuid(unsigned int x86_feature) 186 { 187 unsigned int x86_leaf = __feature_leaf(x86_feature); 188 189 return reverse_cpuid[x86_leaf]; 190 } 191 192 static __always_inline u32 *__cpuid_entry_get_reg(struct kvm_cpuid_entry2 *entry, 193 u32 reg) 194 { 195 switch (reg) { 196 case CPUID_EAX: 197 return &entry->eax; 198 case CPUID_EBX: 199 return &entry->ebx; 200 case CPUID_ECX: 201 return &entry->ecx; 202 case CPUID_EDX: 203 return &entry->edx; 204 default: 205 BUILD_BUG(); 206 return NULL; 207 } 208 } 209 210 static __always_inline u32 *cpuid_entry_get_reg(struct kvm_cpuid_entry2 *entry, 211 unsigned int x86_feature) 212 { 213 const struct cpuid_reg cpuid = x86_feature_cpuid(x86_feature); 214 215 return __cpuid_entry_get_reg(entry, cpuid.reg); 216 } 217 218 static __always_inline u32 cpuid_entry_get(struct kvm_cpuid_entry2 *entry, 219 unsigned int x86_feature) 220 { 221 u32 *reg = cpuid_entry_get_reg(entry, x86_feature); 222 223 return *reg & __feature_bit(x86_feature); 224 } 225 226 static __always_inline bool cpuid_entry_has(struct kvm_cpuid_entry2 *entry, 227 unsigned int x86_feature) 228 { 229 return cpuid_entry_get(entry, x86_feature); 230 } 231 232 static __always_inline void cpuid_entry_clear(struct kvm_cpuid_entry2 *entry, 233 unsigned int x86_feature) 234 { 235 u32 *reg = cpuid_entry_get_reg(entry, x86_feature); 236 237 *reg &= ~__feature_bit(x86_feature); 238 } 239 240 static __always_inline void cpuid_entry_set(struct kvm_cpuid_entry2 *entry, 241 unsigned int x86_feature) 242 { 243 u32 *reg = cpuid_entry_get_reg(entry, x86_feature); 244 245 *reg |= __feature_bit(x86_feature); 246 } 247 248 static __always_inline void cpuid_entry_change(struct kvm_cpuid_entry2 *entry, 249 unsigned int x86_feature, 250 bool set) 251 { 252 u32 *reg = cpuid_entry_get_reg(entry, x86_feature); 253 254 /* 255 * Open coded instead of using cpuid_entry_{clear,set}() to coerce the 256 * compiler into using CMOV instead of Jcc when possible. 257 */ 258 if (set) 259 *reg |= __feature_bit(x86_feature); 260 else 261 *reg &= ~__feature_bit(x86_feature); 262 } 263 264 #endif /* ARCH_X86_KVM_REVERSE_CPUID_H */ 265