1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef ARCH_X86_KVM_REGS_H 3 #define ARCH_X86_KVM_REGS_H 4 5 #include <linux/kvm_host.h> 6 7 #define KVM_POSSIBLE_CR0_GUEST_BITS (X86_CR0_TS | X86_CR0_WP) 8 #define KVM_POSSIBLE_CR4_GUEST_BITS \ 9 (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \ 10 | X86_CR4_OSXMMEXCPT | X86_CR4_PGE | X86_CR4_TSD | X86_CR4_FSGSBASE \ 11 | X86_CR4_CET) 12 13 #define X86_CR0_PDPTR_BITS (X86_CR0_CD | X86_CR0_NW | X86_CR0_PG) 14 #define X86_CR4_TLBFLUSH_BITS (X86_CR4_PGE | X86_CR4_PCIDE | X86_CR4_PAE | X86_CR4_SMEP) 15 #define X86_CR4_PDPTR_BITS (X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE | X86_CR4_SMEP) 16 17 static_assert(!(KVM_POSSIBLE_CR0_GUEST_BITS & X86_CR0_PDPTR_BITS)); 18 19 #define CR0_RESERVED_BITS \ 20 (~(unsigned long)(X86_CR0_PE | X86_CR0_MP | X86_CR0_EM | X86_CR0_TS \ 21 | X86_CR0_ET | X86_CR0_NE | X86_CR0_WP | X86_CR0_AM \ 22 | X86_CR0_NW | X86_CR0_CD | X86_CR0_PG)) 23 24 #define CR4_RESERVED_BITS \ 25 (~(unsigned long)(X86_CR4_VME | X86_CR4_PVI | X86_CR4_TSD | X86_CR4_DE\ 26 | X86_CR4_PSE | X86_CR4_PAE | X86_CR4_MCE \ 27 | X86_CR4_PGE | X86_CR4_PCE | X86_CR4_OSFXSR | X86_CR4_PCIDE \ 28 | X86_CR4_OSXSAVE | X86_CR4_SMEP | X86_CR4_FSGSBASE \ 29 | X86_CR4_OSXMMEXCPT | X86_CR4_LA57 | X86_CR4_VMXE \ 30 | X86_CR4_SMAP | X86_CR4_PKE | X86_CR4_UMIP \ 31 | X86_CR4_LAM_SUP | X86_CR4_CET)) 32 33 #define CR8_RESERVED_BITS (~(unsigned long)X86_CR8_TPR) 34 35 #define DR6_BUS_LOCK (1 << 11) 36 #define DR6_BD (1 << 13) 37 #define DR6_BS (1 << 14) 38 #define DR6_BT (1 << 15) 39 #define DR6_RTM (1 << 16) 40 /* 41 * DR6_ACTIVE_LOW combines fixed-1 and active-low bits. 42 * We can regard all the bits in DR6_FIXED_1 as active_low bits; 43 * they will never be 0 for now, but when they are defined 44 * in the future it will require no code change. 45 * 46 * DR6_ACTIVE_LOW is also used as the init/reset value for DR6. 47 */ 48 #define DR6_ACTIVE_LOW 0xffff0ff0 49 #define DR6_VOLATILE 0x0001e80f 50 #define DR6_FIXED_1 (DR6_ACTIVE_LOW & ~DR6_VOLATILE) 51 52 #define DR7_BP_EN_MASK 0x000000ff 53 #define DR7_GE (1 << 9) 54 #define DR7_GD (1 << 13) 55 #define DR7_VOLATILE 0xffff2bff 56 57 void kvm_post_set_cr0(struct kvm_vcpu *vcpu, unsigned long old_cr0, unsigned long cr0); 58 void kvm_post_set_cr4(struct kvm_vcpu *vcpu, unsigned long old_cr4, unsigned long cr4); 59 int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0); 60 int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3); 61 int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4); 62 int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8); 63 int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val); 64 unsigned long kvm_get_dr(struct kvm_vcpu *vcpu, int dr); 65 unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu); 66 void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw); 67 int load_pdptrs(struct kvm_vcpu *vcpu, unsigned long cr3); 68 69 static inline bool is_long_mode(struct kvm_vcpu *vcpu) 70 { 71 #ifdef CONFIG_X86_64 72 return !!(vcpu->arch.efer & EFER_LMA); 73 #else 74 return false; 75 #endif 76 } 77 78 static inline bool is_64_bit_mode(struct kvm_vcpu *vcpu) 79 { 80 int cs_db, cs_l; 81 82 WARN_ON_ONCE(vcpu->arch.guest_state_protected); 83 84 if (!is_long_mode(vcpu)) 85 return false; 86 kvm_x86_call(get_cs_db_l_bits)(vcpu, &cs_db, &cs_l); 87 return cs_l; 88 } 89 90 static inline bool is_64_bit_hypercall(struct kvm_vcpu *vcpu) 91 { 92 #ifdef CONFIG_X86_64 93 /* 94 * If running with protected guest state, the CS register is not 95 * accessible. The hypercall register values will have had to been 96 * provided in 64-bit mode, so assume the guest is in 64-bit. 97 */ 98 return vcpu->arch.guest_state_protected || is_64_bit_mode(vcpu); 99 #else 100 return false; 101 #endif 102 } 103 104 static __always_inline unsigned long kvm_reg_mode_mask(struct kvm_vcpu *vcpu) 105 { 106 #ifdef CONFIG_X86_64 107 return is_64_bit_mode(vcpu) ? GENMASK(63, 0) : GENMASK(31, 0); 108 #else 109 return GENMASK(31, 0); 110 #endif 111 } 112 113 #define __BUILD_KVM_GPR_ACCESSORS(lname, uname) \ 114 static __always_inline unsigned long kvm_##lname##_read(struct kvm_vcpu *vcpu) \ 115 { \ 116 return vcpu->arch.regs[VCPU_REGS_##uname] & kvm_reg_mode_mask(vcpu); \ 117 } \ 118 static __always_inline unsigned long kvm_##lname##_read_raw(struct kvm_vcpu *vcpu) \ 119 { \ 120 return vcpu->arch.regs[VCPU_REGS_##uname]; \ 121 } \ 122 static __always_inline void kvm_##lname##_write_raw(struct kvm_vcpu *vcpu, \ 123 unsigned long val) \ 124 { \ 125 vcpu->arch.regs[VCPU_REGS_##uname] = val; \ 126 } 127 #define BUILD_KVM_GPR_ACCESSORS(lname, uname) \ 128 static __always_inline u32 kvm_e##lname##_read(struct kvm_vcpu *vcpu) \ 129 { \ 130 return vcpu->arch.regs[VCPU_REGS_##uname]; \ 131 } \ 132 static __always_inline void kvm_e##lname##_write(struct kvm_vcpu *vcpu, u32 val) \ 133 { \ 134 vcpu->arch.regs[VCPU_REGS_##uname] = val; \ 135 } \ 136 __BUILD_KVM_GPR_ACCESSORS(r##lname, uname) 137 138 BUILD_KVM_GPR_ACCESSORS(ax, RAX) 139 BUILD_KVM_GPR_ACCESSORS(bx, RBX) 140 BUILD_KVM_GPR_ACCESSORS(cx, RCX) 141 BUILD_KVM_GPR_ACCESSORS(dx, RDX) 142 BUILD_KVM_GPR_ACCESSORS(bp, RBP) 143 BUILD_KVM_GPR_ACCESSORS(si, RSI) 144 BUILD_KVM_GPR_ACCESSORS(di, RDI) 145 #ifdef CONFIG_X86_64 146 __BUILD_KVM_GPR_ACCESSORS(r8, R8) 147 __BUILD_KVM_GPR_ACCESSORS(r9, R9) 148 __BUILD_KVM_GPR_ACCESSORS(r10, R10) 149 __BUILD_KVM_GPR_ACCESSORS(r11, R11) 150 __BUILD_KVM_GPR_ACCESSORS(r12, R12) 151 __BUILD_KVM_GPR_ACCESSORS(r13, R13) 152 __BUILD_KVM_GPR_ACCESSORS(r14, R14) 153 __BUILD_KVM_GPR_ACCESSORS(r15, R15) 154 #endif 155 156 /* 157 * Using the register cache from interrupt context is generally not allowed, as 158 * caching a register and marking it available/dirty can't be done atomically, 159 * i.e. accesses from interrupt context may clobber state or read stale data if 160 * the vCPU task is in the process of updating the cache. The exception is if 161 * KVM is handling a PMI IRQ/NMI VM-Exit, as that bound code sequence doesn't 162 * touch the cache, it runs after the cache is reset (post VM-Exit), and PMIs 163 * need to access several registers that are cacheable. 164 */ 165 #define kvm_assert_register_caching_allowed(vcpu) \ 166 lockdep_assert_once(in_task() || kvm_arch_pmi_in_guest(vcpu)) 167 168 /* 169 * avail dirty 170 * 0 0 register in VMCS/VMCB 171 * 0 1 *INVALID* 172 * 1 0 register in vcpu->arch 173 * 1 1 register in vcpu->arch, needs to be stored back 174 */ 175 static inline bool kvm_register_is_available(struct kvm_vcpu *vcpu, 176 enum kvm_reg reg) 177 { 178 kvm_assert_register_caching_allowed(vcpu); 179 return test_bit(reg, vcpu->arch.regs_avail); 180 } 181 182 static inline bool kvm_register_is_dirty(struct kvm_vcpu *vcpu, 183 enum kvm_reg reg) 184 { 185 kvm_assert_register_caching_allowed(vcpu); 186 return test_bit(reg, vcpu->arch.regs_dirty); 187 } 188 189 static inline void kvm_register_mark_for_reload(struct kvm_vcpu *vcpu, 190 enum kvm_reg reg) 191 { 192 kvm_assert_register_caching_allowed(vcpu); 193 __clear_bit(reg, vcpu->arch.regs_avail); 194 __clear_bit(reg, vcpu->arch.regs_dirty); 195 } 196 197 static inline void kvm_register_mark_available(struct kvm_vcpu *vcpu, 198 enum kvm_reg reg) 199 { 200 kvm_assert_register_caching_allowed(vcpu); 201 __set_bit(reg, vcpu->arch.regs_avail); 202 } 203 204 static inline void kvm_register_mark_dirty(struct kvm_vcpu *vcpu, 205 enum kvm_reg reg) 206 { 207 kvm_assert_register_caching_allowed(vcpu); 208 __set_bit(reg, vcpu->arch.regs_avail); 209 __set_bit(reg, vcpu->arch.regs_dirty); 210 } 211 212 /* 213 * kvm_register_test_and_mark_available() is a special snowflake that uses an 214 * arch bitop directly to avoid the explicit instrumentation that comes with 215 * the generic bitops. This allows code that cannot be instrumented (noinstr 216 * functions), e.g. the low level VM-Enter/VM-Exit paths, to cache registers. 217 */ 218 static __always_inline bool kvm_register_test_and_mark_available(struct kvm_vcpu *vcpu, 219 enum kvm_reg reg) 220 { 221 kvm_assert_register_caching_allowed(vcpu); 222 return arch___test_and_set_bit(reg, vcpu->arch.regs_avail); 223 } 224 225 static __always_inline void kvm_clear_available_registers(struct kvm_vcpu *vcpu, 226 unsigned long clear_mask) 227 { 228 BUILD_BUG_ON(sizeof(clear_mask) != sizeof(vcpu->arch.regs_avail[0])); 229 BUILD_BUG_ON(ARRAY_SIZE(vcpu->arch.regs_avail) != 1); 230 231 /* 232 * Note the bitwise-AND! In practice, a straight write would also work 233 * as KVM initializes the mask to all ones and never clears registers 234 * that are eagerly synchronized. Using a bitwise-AND adds a bit of 235 * sanity checking as incorrectly marking an eagerly sync'd register 236 * unavailable will generate a WARN due to an unexpected cache request. 237 */ 238 vcpu->arch.regs_avail[0] &= ~clear_mask; 239 } 240 241 static __always_inline void kvm_reset_dirty_registers(struct kvm_vcpu *vcpu) 242 { 243 BUILD_BUG_ON(ARRAY_SIZE(vcpu->arch.regs_dirty) != 1); 244 vcpu->arch.regs_dirty[0] = 0; 245 } 246 247 /* 248 * The "raw" register helpers are only for cases where the full 64 bits of a 249 * register are read/written irrespective of current vCPU mode. In other words, 250 * odds are good you shouldn't be using the raw variants. 251 */ 252 static inline unsigned long kvm_register_read_raw(struct kvm_vcpu *vcpu, int reg) 253 { 254 if (WARN_ON_ONCE((unsigned int)reg >= NR_VCPU_GENERAL_PURPOSE_REGS)) 255 return 0; 256 257 if (!kvm_register_is_available(vcpu, reg)) 258 kvm_x86_call(cache_reg)(vcpu, reg); 259 260 return vcpu->arch.regs[reg]; 261 } 262 263 static inline unsigned long kvm_register_read(struct kvm_vcpu *vcpu, int reg) 264 { 265 return kvm_register_read_raw(vcpu, reg) & kvm_reg_mode_mask(vcpu); 266 } 267 268 static inline void kvm_register_write_raw(struct kvm_vcpu *vcpu, int reg, 269 unsigned long val) 270 { 271 if (WARN_ON_ONCE((unsigned int)reg >= NR_VCPU_GENERAL_PURPOSE_REGS)) 272 return; 273 274 vcpu->arch.regs[reg] = val; 275 kvm_register_mark_dirty(vcpu, reg); 276 } 277 278 static inline void kvm_register_write(struct kvm_vcpu *vcpu, 279 int reg, unsigned long val) 280 { 281 return kvm_register_write_raw(vcpu, reg, val & kvm_reg_mode_mask(vcpu)); 282 } 283 284 static inline unsigned long kvm_rip_read(struct kvm_vcpu *vcpu) 285 { 286 if (!kvm_register_is_available(vcpu, VCPU_REG_RIP)) 287 kvm_x86_call(cache_reg)(vcpu, VCPU_REG_RIP); 288 289 return vcpu->arch.rip; 290 } 291 292 static inline void kvm_rip_write(struct kvm_vcpu *vcpu, unsigned long val) 293 { 294 vcpu->arch.rip = val; 295 kvm_register_mark_dirty(vcpu, VCPU_REG_RIP); 296 } 297 298 static inline unsigned long kvm_rsp_read(struct kvm_vcpu *vcpu) 299 { 300 return kvm_register_read_raw(vcpu, VCPU_REGS_RSP); 301 } 302 303 static inline void kvm_rsp_write(struct kvm_vcpu *vcpu, unsigned long val) 304 { 305 kvm_register_write_raw(vcpu, VCPU_REGS_RSP, val); 306 } 307 308 static inline u64 kvm_read_edx_eax(struct kvm_vcpu *vcpu) 309 { 310 return kvm_eax_read(vcpu) | (u64)(kvm_edx_read(vcpu)) << 32; 311 } 312 313 static inline u64 kvm_pdptr_read(struct kvm_vcpu *vcpu, int index) 314 { 315 might_sleep(); /* on svm */ 316 317 if (!kvm_register_is_available(vcpu, VCPU_REG_PDPTR)) 318 kvm_x86_call(cache_reg)(vcpu, VCPU_REG_PDPTR); 319 320 return vcpu->arch.pdptrs[index]; 321 } 322 323 static inline void kvm_pdptr_write(struct kvm_vcpu *vcpu, int index, u64 value) 324 { 325 vcpu->arch.pdptrs[index] = value; 326 } 327 328 static inline ulong kvm_read_cr0_bits(struct kvm_vcpu *vcpu, ulong mask) 329 { 330 ulong tmask = mask & KVM_POSSIBLE_CR0_GUEST_BITS; 331 if ((tmask & vcpu->arch.cr0_guest_owned_bits) && 332 !kvm_register_is_available(vcpu, VCPU_REG_CR0)) 333 kvm_x86_call(cache_reg)(vcpu, VCPU_REG_CR0); 334 return vcpu->arch.cr0 & mask; 335 } 336 337 static __always_inline bool kvm_is_cr0_bit_set(struct kvm_vcpu *vcpu, 338 unsigned long cr0_bit) 339 { 340 BUILD_BUG_ON(!is_power_of_2(cr0_bit)); 341 342 return !!kvm_read_cr0_bits(vcpu, cr0_bit); 343 } 344 345 static inline ulong kvm_read_cr0(struct kvm_vcpu *vcpu) 346 { 347 return kvm_read_cr0_bits(vcpu, ~0UL); 348 } 349 350 static inline ulong kvm_read_cr4_bits(struct kvm_vcpu *vcpu, ulong mask) 351 { 352 ulong tmask = mask & KVM_POSSIBLE_CR4_GUEST_BITS; 353 if ((tmask & vcpu->arch.cr4_guest_owned_bits) && 354 !kvm_register_is_available(vcpu, VCPU_REG_CR4)) 355 kvm_x86_call(cache_reg)(vcpu, VCPU_REG_CR4); 356 return vcpu->arch.cr4 & mask; 357 } 358 359 static __always_inline bool kvm_is_cr4_bit_set(struct kvm_vcpu *vcpu, 360 unsigned long cr4_bit) 361 { 362 BUILD_BUG_ON(!is_power_of_2(cr4_bit)); 363 364 return !!kvm_read_cr4_bits(vcpu, cr4_bit); 365 } 366 367 static inline ulong kvm_read_cr3(struct kvm_vcpu *vcpu) 368 { 369 if (!kvm_register_is_available(vcpu, VCPU_REG_CR3)) 370 kvm_x86_call(cache_reg)(vcpu, VCPU_REG_CR3); 371 return vcpu->arch.cr3; 372 } 373 374 static inline ulong kvm_read_cr4(struct kvm_vcpu *vcpu) 375 { 376 return kvm_read_cr4_bits(vcpu, ~0UL); 377 } 378 379 static inline bool __kvm_is_valid_cr4(struct kvm_vcpu *vcpu, unsigned long cr4) 380 { 381 return !(cr4 & vcpu->arch.cr4_guest_rsvd_bits); 382 } 383 384 #define __cr4_reserved_bits(__cpu_has, __c) \ 385 ({ \ 386 u64 __reserved_bits = CR4_RESERVED_BITS; \ 387 \ 388 if (!__cpu_has(__c, X86_FEATURE_XSAVE)) \ 389 __reserved_bits |= X86_CR4_OSXSAVE; \ 390 if (!__cpu_has(__c, X86_FEATURE_SMEP)) \ 391 __reserved_bits |= X86_CR4_SMEP; \ 392 if (!__cpu_has(__c, X86_FEATURE_SMAP)) \ 393 __reserved_bits |= X86_CR4_SMAP; \ 394 if (!__cpu_has(__c, X86_FEATURE_FSGSBASE)) \ 395 __reserved_bits |= X86_CR4_FSGSBASE; \ 396 if (!__cpu_has(__c, X86_FEATURE_PKU)) \ 397 __reserved_bits |= X86_CR4_PKE; \ 398 if (!__cpu_has(__c, X86_FEATURE_LA57)) \ 399 __reserved_bits |= X86_CR4_LA57; \ 400 if (!__cpu_has(__c, X86_FEATURE_UMIP)) \ 401 __reserved_bits |= X86_CR4_UMIP; \ 402 if (!__cpu_has(__c, X86_FEATURE_VMX)) \ 403 __reserved_bits |= X86_CR4_VMXE; \ 404 if (!__cpu_has(__c, X86_FEATURE_PCID)) \ 405 __reserved_bits |= X86_CR4_PCIDE; \ 406 if (!__cpu_has(__c, X86_FEATURE_LAM)) \ 407 __reserved_bits |= X86_CR4_LAM_SUP; \ 408 if (!__cpu_has(__c, X86_FEATURE_SHSTK) && \ 409 !__cpu_has(__c, X86_FEATURE_IBT)) \ 410 __reserved_bits |= X86_CR4_CET; \ 411 __reserved_bits; \ 412 }) 413 414 static inline bool is_protmode(struct kvm_vcpu *vcpu) 415 { 416 return kvm_is_cr0_bit_set(vcpu, X86_CR0_PE); 417 } 418 419 static inline bool is_pae(struct kvm_vcpu *vcpu) 420 { 421 return kvm_is_cr4_bit_set(vcpu, X86_CR4_PAE); 422 } 423 424 static inline bool is_pse(struct kvm_vcpu *vcpu) 425 { 426 return kvm_is_cr4_bit_set(vcpu, X86_CR4_PSE); 427 } 428 429 static inline bool is_paging(struct kvm_vcpu *vcpu) 430 { 431 return likely(kvm_is_cr0_bit_set(vcpu, X86_CR0_PG)); 432 } 433 434 static inline bool is_pae_paging(struct kvm_vcpu *vcpu) 435 { 436 return !is_long_mode(vcpu) && is_pae(vcpu) && is_paging(vcpu); 437 } 438 439 static inline bool kvm_dr7_valid(u64 data) 440 { 441 /* Bits [63:32] are reserved */ 442 return !(data >> 32); 443 } 444 static inline bool kvm_dr6_valid(u64 data) 445 { 446 /* Bits [63:32] are reserved */ 447 return !(data >> 32); 448 } 449 450 static inline unsigned long kvm_get_effective_dr7(struct kvm_vcpu *vcpu) 451 { 452 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) 453 return vcpu->arch.guest_debug_dr7; 454 455 return vcpu->arch.dr7; 456 } 457 458 static inline void enter_guest_mode(struct kvm_vcpu *vcpu) 459 { 460 vcpu->arch.hflags |= HF_GUEST_MASK; 461 vcpu->stat.guest_mode = 1; 462 } 463 464 static inline void leave_guest_mode(struct kvm_vcpu *vcpu) 465 { 466 vcpu->arch.hflags &= ~HF_GUEST_MASK; 467 468 if (vcpu->arch.load_eoi_exitmap_pending) { 469 vcpu->arch.load_eoi_exitmap_pending = false; 470 kvm_make_request(KVM_REQ_LOAD_EOI_EXITMAP, vcpu); 471 } 472 473 vcpu->stat.guest_mode = 0; 474 } 475 476 static inline bool is_guest_mode(struct kvm_vcpu *vcpu) 477 { 478 return vcpu->arch.hflags & HF_GUEST_MASK; 479 } 480 481 static inline unsigned long kvm_get_segment_base(struct kvm_vcpu *vcpu, int seg) 482 { 483 return kvm_x86_call(get_segment_base)(vcpu, seg); 484 } 485 486 static inline void kvm_set_segment(struct kvm_vcpu *vcpu, 487 struct kvm_segment *var, int seg) 488 { 489 kvm_x86_call(set_segment)(vcpu, var, seg); 490 } 491 492 static inline void kvm_get_segment(struct kvm_vcpu *vcpu, 493 struct kvm_segment *var, int seg) 494 { 495 kvm_x86_call(get_segment)(vcpu, var, seg); 496 } 497 498 unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu); 499 bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip); 500 501 unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu); 502 void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags); 503 void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags); 504 505 void kvm_vcpu_ioctl_x86_get_sregs2(struct kvm_vcpu *vcpu, 506 struct kvm_sregs2 *sregs2); 507 int kvm_vcpu_ioctl_x86_set_sregs2(struct kvm_vcpu *vcpu, 508 struct kvm_sregs2 *sregs2); 509 510 void kvm_run_sync_regs_to_user(struct kvm_vcpu *vcpu); 511 int kvm_run_sync_regs_from_user(struct kvm_vcpu *vcpu); 512 513 void kvm_update_dr0123(struct kvm_vcpu *vcpu); 514 void kvm_update_dr7(struct kvm_vcpu *vcpu); 515 int kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu, 516 struct kvm_debugregs *dbgregs); 517 int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu, 518 struct kvm_debugregs *dbgregs); 519 520 521 #endif 522