1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef __KVM_X86_PMU_H 3 #define __KVM_X86_PMU_H 4 5 #include <linux/nospec.h> 6 7 #include <asm/kvm_host.h> 8 9 #define vcpu_to_pmu(vcpu) (&(vcpu)->arch.pmu) 10 #define pmu_to_vcpu(pmu) (container_of((pmu), struct kvm_vcpu, arch.pmu)) 11 #define pmc_to_pmu(pmc) (&(pmc)->vcpu->arch.pmu) 12 13 #define MSR_IA32_MISC_ENABLE_PMU_RO_MASK (MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL | \ 14 MSR_IA32_MISC_ENABLE_BTS_UNAVAIL) 15 16 /* retrieve a fixed counter bits out of IA32_FIXED_CTR_CTRL */ 17 #define fixed_ctrl_field(ctrl_reg, idx) \ 18 (((ctrl_reg) >> ((idx) * INTEL_FIXED_BITS_STRIDE)) & INTEL_FIXED_BITS_MASK) 19 20 #define VMWARE_BACKDOOR_PMC_HOST_TSC 0x10000 21 #define VMWARE_BACKDOOR_PMC_REAL_TIME 0x10001 22 #define VMWARE_BACKDOOR_PMC_APPARENT_TIME 0x10002 23 24 #define KVM_FIXED_PMC_BASE_IDX INTEL_PMC_IDX_FIXED 25 26 struct kvm_pmu_ops { 27 struct kvm_pmc *(*rdpmc_ecx_to_pmc)(struct kvm_vcpu *vcpu, 28 unsigned int idx, u64 *mask); 29 struct kvm_pmc *(*msr_idx_to_pmc)(struct kvm_vcpu *vcpu, u32 msr); 30 int (*check_rdpmc_early)(struct kvm_vcpu *vcpu, unsigned int idx); 31 bool (*is_valid_msr)(struct kvm_vcpu *vcpu, u32 msr); 32 int (*get_msr)(struct kvm_vcpu *vcpu, struct msr_data *msr_info); 33 int (*set_msr)(struct kvm_vcpu *vcpu, struct msr_data *msr_info); 34 void (*refresh)(struct kvm_vcpu *vcpu); 35 void (*init)(struct kvm_vcpu *vcpu); 36 void (*reset)(struct kvm_vcpu *vcpu); 37 void (*deliver_pmi)(struct kvm_vcpu *vcpu); 38 void (*cleanup)(struct kvm_vcpu *vcpu); 39 bool (*pmc_is_disabled_in_current_mode)(struct kvm_pmc *pmc); 40 41 bool (*is_mediated_pmu_supported)(struct x86_pmu_capability *host_pmu); 42 void (*mediated_load)(struct kvm_vcpu *vcpu); 43 void (*mediated_put)(struct kvm_vcpu *vcpu); 44 void (*write_global_ctrl)(u64 global_ctrl); 45 46 const u64 EVENTSEL_EVENT; 47 const int MAX_NR_GP_COUNTERS; 48 const int MIN_NR_GP_COUNTERS; 49 50 const u32 PERF_GLOBAL_CTRL; 51 const u32 GP_EVENTSEL_BASE; 52 const u32 GP_COUNTER_BASE; 53 const u32 FIXED_COUNTER_BASE; 54 const u32 MSR_STRIDE; 55 }; 56 57 #define kvm_pmu_call(func) static_call(kvm_x86_pmu_##func) 58 59 #define KVM_X86_PMU_OP(func) \ 60 DECLARE_STATIC_CALL(kvm_x86_pmu_##func, *(((struct kvm_pmu_ops *)0)->func)); 61 #define KVM_X86_PMU_OP_OPTIONAL KVM_X86_PMU_OP 62 #define KVM_X86_PMU_OP_OPTIONAL_RET0 KVM_X86_PMU_OP 63 #include <asm/kvm-x86-pmu-ops.h> 64 65 extern bool enable_pmu; 66 extern bool enable_mediated_pmu; 67 68 void kvm_pmu_ops_update(const struct kvm_pmu_ops *pmu_ops); 69 70 void kvm_handle_guest_mediated_pmi(void); 71 72 static inline bool kvm_pmu_has_perf_global_ctrl(struct kvm_pmu *pmu) 73 { 74 /* 75 * Architecturally, Intel's SDM states that IA32_PERF_GLOBAL_CTRL is 76 * supported if "CPUID.0AH: EAX[7:0] > 0", i.e. if the PMU version is 77 * greater than zero. However, KVM only exposes and emulates the MSR 78 * to/for the guest if the guest PMU supports at least "Architectural 79 * Performance Monitoring Version 2". 80 * 81 * AMD's version of PERF_GLOBAL_CTRL conveniently shows up with v2. 82 */ 83 return pmu->version > 1; 84 } 85 86 static inline bool kvm_vcpu_has_mediated_pmu(struct kvm_vcpu *vcpu) 87 { 88 return enable_mediated_pmu && vcpu_to_pmu(vcpu)->version; 89 } 90 91 /* 92 * KVM tracks all counters in 64-bit bitmaps, with general purpose counters 93 * mapped to bits 31:0 and fixed counters mapped to 63:32, e.g. fixed counter 0 94 * is tracked internally via index 32. On Intel, (AMD doesn't support fixed 95 * counters), this mirrors how fixed counters are mapped to PERF_GLOBAL_CTRL 96 * and similar MSRs, i.e. tracking fixed counters at base index 32 reduces the 97 * amount of boilerplate needed to iterate over PMCs *and* simplifies common 98 * enable/disable/reset operations. 99 * 100 * WARNING! This helper is only for lookups that are initiated by KVM, it is 101 * NOT safe for guest lookups, e.g. will do the wrong thing if passed a raw 102 * ECX value from RDPMC (fixed counters are accessed by setting bit 30 in ECX 103 * for RDPMC, not by adding 32 to the fixed counter index). 104 */ 105 static inline struct kvm_pmc *kvm_pmc_idx_to_pmc(struct kvm_pmu *pmu, int idx) 106 { 107 if (idx < pmu->nr_arch_gp_counters) 108 return &pmu->gp_counters[idx]; 109 110 idx -= KVM_FIXED_PMC_BASE_IDX; 111 if (idx >= 0 && idx < pmu->nr_arch_fixed_counters) 112 return &pmu->fixed_counters[idx]; 113 114 return NULL; 115 } 116 117 #define kvm_for_each_pmc(pmu, pmc, i, bitmap) \ 118 for_each_set_bit(i, bitmap, X86_PMC_IDX_MAX) \ 119 if (!(pmc = kvm_pmc_idx_to_pmc(pmu, i))) \ 120 continue; \ 121 else \ 122 123 static inline u64 pmc_bitmask(struct kvm_pmc *pmc) 124 { 125 struct kvm_pmu *pmu = pmc_to_pmu(pmc); 126 127 return pmu->counter_bitmask[pmc->type]; 128 } 129 130 static inline u64 pmc_read_counter(struct kvm_pmc *pmc) 131 { 132 u64 counter, enabled, running; 133 134 if (kvm_vcpu_has_mediated_pmu(pmc->vcpu)) 135 return pmc->counter & pmc_bitmask(pmc); 136 137 counter = pmc->counter + pmc->emulated_counter; 138 139 if (pmc->perf_event && !pmc->is_paused) 140 counter += perf_event_read_value(pmc->perf_event, 141 &enabled, &running); 142 /* FIXME: Scaling needed? */ 143 return counter & pmc_bitmask(pmc); 144 } 145 146 void pmc_write_counter(struct kvm_pmc *pmc, u64 val); 147 148 static inline bool pmc_is_gp(struct kvm_pmc *pmc) 149 { 150 return pmc->type == KVM_PMC_GP; 151 } 152 153 static inline bool pmc_is_fixed(struct kvm_pmc *pmc) 154 { 155 return pmc->type == KVM_PMC_FIXED; 156 } 157 158 static inline bool kvm_valid_perf_global_ctrl(struct kvm_pmu *pmu, 159 u64 data) 160 { 161 return !(pmu->global_ctrl_rsvd & data); 162 } 163 164 /* returns general purpose PMC with the specified MSR. Note that it can be 165 * used for both PERFCTRn and EVNTSELn; that is why it accepts base as a 166 * parameter to tell them apart. 167 */ 168 static inline struct kvm_pmc *get_gp_pmc(struct kvm_pmu *pmu, u32 msr, 169 u32 base) 170 { 171 if (msr >= base && msr < base + pmu->nr_arch_gp_counters) { 172 u32 index = array_index_nospec(msr - base, 173 pmu->nr_arch_gp_counters); 174 175 return &pmu->gp_counters[index]; 176 } 177 178 return NULL; 179 } 180 181 /* returns fixed PMC with the specified MSR */ 182 static inline struct kvm_pmc *get_fixed_pmc(struct kvm_pmu *pmu, u32 msr) 183 { 184 int base = MSR_CORE_PERF_FIXED_CTR0; 185 186 if (msr >= base && msr < base + pmu->nr_arch_fixed_counters) { 187 u32 index = array_index_nospec(msr - base, 188 pmu->nr_arch_fixed_counters); 189 190 return &pmu->fixed_counters[index]; 191 } 192 193 return NULL; 194 } 195 196 static inline bool pmc_is_locally_enabled(struct kvm_pmc *pmc) 197 { 198 struct kvm_pmu *pmu = pmc_to_pmu(pmc); 199 200 if (pmc_is_fixed(pmc)) 201 return fixed_ctrl_field(pmu->fixed_ctr_ctrl, 202 pmc->idx - KVM_FIXED_PMC_BASE_IDX) & 203 (INTEL_FIXED_0_KERNEL | INTEL_FIXED_0_USER); 204 205 if (!(pmc->eventsel & ARCH_PERFMON_EVENTSEL_ENABLE)) 206 return false; 207 208 if (!test_bit(pmc->idx, pmu->pmc_has_mode_specific_enables)) 209 return true; 210 211 return !kvm_pmu_call(pmc_is_disabled_in_current_mode)(pmc); 212 } 213 214 extern struct x86_pmu_capability kvm_pmu_cap; 215 216 void kvm_init_pmu_capability(struct kvm_pmu_ops *pmu_ops); 217 218 void kvm_pmu_recalc_pmc_emulation(struct kvm_pmu *pmu, struct kvm_pmc *pmc); 219 void kvm_pmu_handle_event(struct kvm_vcpu *vcpu); 220 221 static inline void kvm_pmu_request_counter_reprogram(struct kvm_pmc *pmc) 222 { 223 kvm_pmu_recalc_pmc_emulation(pmc_to_pmu(pmc), pmc); 224 225 set_bit(pmc->idx, pmc_to_pmu(pmc)->reprogram_pmi); 226 kvm_make_request(KVM_REQ_PMU, pmc->vcpu); 227 } 228 229 static inline void __kvm_pmu_reprogram_counters(struct kvm_pmu *pmu, 230 u64 counters, 231 bool defer) 232 { 233 if (!counters) 234 return; 235 236 atomic64_or(counters, &pmu->__reprogram_pmi); 237 if (defer) 238 kvm_make_request(KVM_REQ_PMU, pmu_to_vcpu(pmu)); 239 else 240 kvm_pmu_handle_event(pmu_to_vcpu(pmu)); 241 } 242 243 static inline void kvm_pmu_request_counters_reprogram(struct kvm_pmu *pmu, 244 u64 counters) 245 { 246 __kvm_pmu_reprogram_counters(pmu, counters, true); 247 } 248 249 /* 250 * Check if a PMC is enabled by comparing it against global_ctrl bits. 251 * 252 * If the vPMU doesn't have global_ctrl MSR, all vPMCs are enabled. 253 */ 254 static inline bool pmc_is_globally_enabled(struct kvm_pmc *pmc) 255 { 256 struct kvm_pmu *pmu = pmc_to_pmu(pmc); 257 258 if (!kvm_pmu_has_perf_global_ctrl(pmu)) 259 return true; 260 261 return test_bit(pmc->idx, (unsigned long *)&pmu->global_ctrl); 262 } 263 264 static inline bool kvm_pmu_is_fastpath_emulation_allowed(struct kvm_vcpu *vcpu) 265 { 266 struct kvm_pmu *pmu = vcpu_to_pmu(vcpu); 267 268 return !kvm_vcpu_has_mediated_pmu(vcpu) || 269 !bitmap_intersects(pmu->pmc_counting_instructions, 270 (unsigned long *)&pmu->global_ctrl, 271 X86_PMC_IDX_MAX); 272 } 273 274 void kvm_pmu_deliver_pmi(struct kvm_vcpu *vcpu); 275 int kvm_pmu_rdpmc(struct kvm_vcpu *vcpu, unsigned pmc, u64 *data); 276 int kvm_pmu_check_rdpmc_early(struct kvm_vcpu *vcpu, unsigned int idx); 277 bool kvm_pmu_is_valid_msr(struct kvm_vcpu *vcpu, u32 msr); 278 int kvm_pmu_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info); 279 int kvm_pmu_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info); 280 void kvm_pmu_refresh(struct kvm_vcpu *vcpu); 281 void kvm_pmu_init(struct kvm_vcpu *vcpu); 282 void kvm_pmu_cleanup(struct kvm_vcpu *vcpu); 283 void kvm_pmu_destroy(struct kvm_vcpu *vcpu); 284 int kvm_vm_ioctl_set_pmu_event_filter(struct kvm *kvm, void __user *argp); 285 void kvm_pmu_instruction_retired(struct kvm_vcpu *vcpu); 286 void kvm_pmu_branch_retired(struct kvm_vcpu *vcpu); 287 void kvm_mediated_pmu_load(struct kvm_vcpu *vcpu); 288 void kvm_mediated_pmu_put(struct kvm_vcpu *vcpu); 289 290 bool is_vmware_backdoor_pmc(u32 pmc_idx); 291 bool kvm_need_perf_global_ctrl_intercept(struct kvm_vcpu *vcpu); 292 bool kvm_need_rdpmc_intercept(struct kvm_vcpu *vcpu); 293 294 extern struct kvm_pmu_ops intel_pmu_ops; 295 extern struct kvm_pmu_ops amd_pmu_ops; 296 #endif /* __KVM_X86_PMU_H */ 297