1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Kernel-based Virtual Machine driver for Linux 4 * 5 * Macros and functions to access KVM PTEs (also known as SPTEs) 6 * 7 * Copyright (C) 2006 Qumranet, Inc. 8 * Copyright 2020 Red Hat, Inc. and/or its affiliates. 9 */ 10 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 11 12 #include <linux/kvm_host.h> 13 #include "mmu.h" 14 #include "mmu_internal.h" 15 #include "x86.h" 16 #include "spte.h" 17 18 #include <asm/e820/api.h> 19 #include <asm/memtype.h> 20 #include <asm/vmx.h> 21 22 bool __read_mostly enable_mmio_caching = true; 23 static bool __ro_after_init allow_mmio_caching; 24 module_param_named(mmio_caching, enable_mmio_caching, bool, 0444); 25 EXPORT_SYMBOL_GPL(enable_mmio_caching); 26 27 bool __read_mostly kvm_ad_enabled; 28 29 u64 __read_mostly shadow_host_writable_mask; 30 u64 __read_mostly shadow_mmu_writable_mask; 31 u64 __read_mostly shadow_nx_mask; 32 u64 __read_mostly shadow_x_mask; /* mutual exclusive with nx_mask */ 33 u64 __read_mostly shadow_user_mask; 34 u64 __read_mostly shadow_accessed_mask; 35 u64 __read_mostly shadow_dirty_mask; 36 u64 __read_mostly shadow_mmio_value; 37 u64 __read_mostly shadow_mmio_mask; 38 u64 __read_mostly shadow_mmio_access_mask; 39 u64 __read_mostly shadow_present_mask; 40 u64 __read_mostly shadow_memtype_mask; 41 u64 __read_mostly shadow_me_value; 42 u64 __read_mostly shadow_me_mask; 43 u64 __read_mostly shadow_acc_track_mask; 44 45 u64 __read_mostly shadow_nonpresent_or_rsvd_mask; 46 u64 __read_mostly shadow_nonpresent_or_rsvd_lower_gfn_mask; 47 48 static u8 __init kvm_get_host_maxphyaddr(void) 49 { 50 /* 51 * boot_cpu_data.x86_phys_bits is reduced when MKTME or SME are detected 52 * in CPU detection code, but the processor treats those reduced bits as 53 * 'keyID' thus they are not reserved bits. Therefore KVM needs to look at 54 * the physical address bits reported by CPUID, i.e. the raw MAXPHYADDR, 55 * when reasoning about CPU behavior with respect to MAXPHYADDR. 56 */ 57 if (likely(boot_cpu_data.extended_cpuid_level >= 0x80000008)) 58 return cpuid_eax(0x80000008) & 0xff; 59 60 /* 61 * Quite weird to have VMX or SVM but not MAXPHYADDR; probably a VM with 62 * custom CPUID. Proceed with whatever the kernel found since these features 63 * aren't virtualizable (SME/SEV also require CPUIDs higher than 0x80000008). 64 */ 65 return boot_cpu_data.x86_phys_bits; 66 } 67 68 void __init kvm_mmu_spte_module_init(void) 69 { 70 /* 71 * Snapshot userspace's desire to allow MMIO caching. Whether or not 72 * KVM can actually enable MMIO caching depends on vendor-specific 73 * hardware capabilities and other module params that can't be resolved 74 * until the vendor module is loaded, i.e. enable_mmio_caching can and 75 * will change when the vendor module is (re)loaded. 76 */ 77 allow_mmio_caching = enable_mmio_caching; 78 79 kvm_host.maxphyaddr = kvm_get_host_maxphyaddr(); 80 } 81 82 static u64 generation_mmio_spte_mask(u64 gen) 83 { 84 u64 mask; 85 86 WARN_ON_ONCE(gen & ~MMIO_SPTE_GEN_MASK); 87 88 mask = (gen << MMIO_SPTE_GEN_LOW_SHIFT) & MMIO_SPTE_GEN_LOW_MASK; 89 mask |= (gen << MMIO_SPTE_GEN_HIGH_SHIFT) & MMIO_SPTE_GEN_HIGH_MASK; 90 return mask; 91 } 92 93 u64 make_mmio_spte(struct kvm_vcpu *vcpu, u64 gfn, unsigned int access) 94 { 95 u64 gen = kvm_vcpu_memslots(vcpu)->generation & MMIO_SPTE_GEN_MASK; 96 u64 spte = generation_mmio_spte_mask(gen); 97 u64 gpa = gfn << PAGE_SHIFT; 98 99 WARN_ON_ONCE(!vcpu->kvm->arch.shadow_mmio_value); 100 101 access &= shadow_mmio_access_mask; 102 spte |= vcpu->kvm->arch.shadow_mmio_value | access; 103 spte |= gpa | shadow_nonpresent_or_rsvd_mask; 104 spte |= (gpa & shadow_nonpresent_or_rsvd_mask) 105 << SHADOW_NONPRESENT_OR_RSVD_MASK_LEN; 106 107 return spte; 108 } 109 110 static bool kvm_is_mmio_pfn(kvm_pfn_t pfn) 111 { 112 if (pfn_valid(pfn)) 113 return !is_zero_pfn(pfn) && PageReserved(pfn_to_page(pfn)) && 114 /* 115 * Some reserved pages, such as those from NVDIMM 116 * DAX devices, are not for MMIO, and can be mapped 117 * with cached memory type for better performance. 118 * However, the above check misconceives those pages 119 * as MMIO, and results in KVM mapping them with UC 120 * memory type, which would hurt the performance. 121 * Therefore, we check the host memory type in addition 122 * and only treat UC/UC-/WC pages as MMIO. 123 */ 124 (!pat_enabled() || pat_pfn_immune_to_uc_mtrr(pfn)); 125 126 return !e820__mapped_raw_any(pfn_to_hpa(pfn), 127 pfn_to_hpa(pfn + 1) - 1, 128 E820_TYPE_RAM); 129 } 130 131 /* 132 * Returns true if the SPTE needs to be updated atomically due to having bits 133 * that may be changed without holding mmu_lock, and for which KVM must not 134 * lose information. E.g. KVM must not drop Dirty bit information. The caller 135 * is responsible for checking if the SPTE is shadow-present, and for 136 * determining whether or not the caller cares about non-leaf SPTEs. 137 */ 138 bool spte_needs_atomic_update(u64 spte) 139 { 140 /* SPTEs can be made Writable bit by KVM's fast page fault handler. */ 141 if (!is_writable_pte(spte) && is_mmu_writable_spte(spte)) 142 return true; 143 144 /* 145 * A/D-disabled SPTEs can be access-tracked by aging, and access-tracked 146 * SPTEs can be restored by KVM's fast page fault handler. 147 */ 148 if (!spte_ad_enabled(spte)) 149 return true; 150 151 /* 152 * Dirty and Accessed bits can be set by the CPU. Ignore the Accessed 153 * bit, as KVM tolerates false negatives/positives, e.g. KVM doesn't 154 * invalidate TLBs when aging SPTEs, and so it's safe to clobber the 155 * Accessed bit (and rare in practice). 156 */ 157 return is_writable_pte(spte) && !(spte & shadow_dirty_mask); 158 } 159 160 bool make_spte(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp, 161 const struct kvm_memory_slot *slot, 162 unsigned int pte_access, gfn_t gfn, kvm_pfn_t pfn, 163 u64 old_spte, bool prefetch, bool synchronizing, 164 bool host_writable, u64 *new_spte) 165 { 166 int level = sp->role.level; 167 u64 spte = SPTE_MMU_PRESENT_MASK; 168 bool wrprot = false; 169 170 /* 171 * For the EPT case, shadow_present_mask has no RWX bits set if 172 * exec-only page table entries are supported. In that case, 173 * ACC_USER_MASK and shadow_user_mask are used to represent 174 * read access. See FNAME(gpte_access) in paging_tmpl.h. 175 */ 176 WARN_ON_ONCE((pte_access | shadow_present_mask) == SHADOW_NONPRESENT_VALUE); 177 178 if (sp->role.ad_disabled) 179 spte |= SPTE_TDP_AD_DISABLED; 180 else if (kvm_mmu_page_ad_need_write_protect(sp)) 181 spte |= SPTE_TDP_AD_WRPROT_ONLY; 182 183 spte |= shadow_present_mask; 184 if (!prefetch || synchronizing) 185 spte |= shadow_accessed_mask; 186 187 /* 188 * For simplicity, enforce the NX huge page mitigation even if not 189 * strictly necessary. KVM could ignore the mitigation if paging is 190 * disabled in the guest, as the guest doesn't have any page tables to 191 * abuse. But to safely ignore the mitigation, KVM would have to 192 * ensure a new MMU is loaded (or all shadow pages zapped) when CR0.PG 193 * is toggled on, and that's a net negative for performance when TDP is 194 * enabled. When TDP is disabled, KVM will always switch to a new MMU 195 * when CR0.PG is toggled, but leveraging that to ignore the mitigation 196 * would tie make_spte() further to vCPU/MMU state, and add complexity 197 * just to optimize a mode that is anything but performance critical. 198 */ 199 if (level > PG_LEVEL_4K && (pte_access & ACC_EXEC_MASK) && 200 is_nx_huge_page_enabled(vcpu->kvm)) { 201 pte_access &= ~ACC_EXEC_MASK; 202 } 203 204 if (pte_access & ACC_EXEC_MASK) 205 spte |= shadow_x_mask; 206 else 207 spte |= shadow_nx_mask; 208 209 if (pte_access & ACC_USER_MASK) 210 spte |= shadow_user_mask; 211 212 if (level > PG_LEVEL_4K) 213 spte |= PT_PAGE_SIZE_MASK; 214 215 if (shadow_memtype_mask) 216 spte |= kvm_x86_call(get_mt_mask)(vcpu, gfn, 217 kvm_is_mmio_pfn(pfn)); 218 if (host_writable) 219 spte |= shadow_host_writable_mask; 220 else 221 pte_access &= ~ACC_WRITE_MASK; 222 223 if (shadow_me_value && !kvm_is_mmio_pfn(pfn)) 224 spte |= shadow_me_value; 225 226 spte |= (u64)pfn << PAGE_SHIFT; 227 228 if (pte_access & ACC_WRITE_MASK) { 229 /* 230 * Unsync shadow pages that are reachable by the new, writable 231 * SPTE. Write-protect the SPTE if the page can't be unsync'd, 232 * e.g. it's write-tracked (upper-level SPs) or has one or more 233 * shadow pages and unsync'ing pages is not allowed. 234 * 235 * When overwriting an existing leaf SPTE, and the old SPTE was 236 * writable, skip trying to unsync shadow pages as any relevant 237 * shadow pages must already be unsync, i.e. the hash lookup is 238 * unnecessary (and expensive). Note, this relies on KVM not 239 * changing PFNs without first zapping the old SPTE, which is 240 * guaranteed by both the shadow MMU and the TDP MMU. 241 */ 242 if ((!is_last_spte(old_spte, level) || !is_writable_pte(old_spte)) && 243 mmu_try_to_unsync_pages(vcpu->kvm, slot, gfn, synchronizing, prefetch)) 244 wrprot = true; 245 else 246 spte |= PT_WRITABLE_MASK | shadow_mmu_writable_mask | 247 shadow_dirty_mask; 248 } 249 250 if (prefetch && !synchronizing) 251 spte = mark_spte_for_access_track(spte); 252 253 WARN_ONCE(is_rsvd_spte(&vcpu->arch.mmu->shadow_zero_check, spte, level), 254 "spte = 0x%llx, level = %d, rsvd bits = 0x%llx", spte, level, 255 get_rsvd_bits(&vcpu->arch.mmu->shadow_zero_check, spte, level)); 256 257 /* 258 * Mark the memslot dirty *after* modifying it for access tracking. 259 * Unlike folios, memslots can be safely marked dirty out of mmu_lock, 260 * i.e. in the fast page fault handler. 261 */ 262 if ((spte & PT_WRITABLE_MASK) && kvm_slot_dirty_track_enabled(slot)) { 263 /* Enforced by kvm_mmu_hugepage_adjust. */ 264 WARN_ON_ONCE(level > PG_LEVEL_4K); 265 mark_page_dirty_in_slot(vcpu->kvm, slot, gfn); 266 } 267 268 *new_spte = spte; 269 return wrprot; 270 } 271 272 static u64 modify_spte_protections(u64 spte, u64 set, u64 clear) 273 { 274 bool is_access_track = is_access_track_spte(spte); 275 276 if (is_access_track) 277 spte = restore_acc_track_spte(spte); 278 279 KVM_MMU_WARN_ON(set & clear); 280 spte = (spte | set) & ~clear; 281 282 if (is_access_track) 283 spte = mark_spte_for_access_track(spte); 284 285 return spte; 286 } 287 288 static u64 make_spte_executable(u64 spte) 289 { 290 return modify_spte_protections(spte, shadow_x_mask, shadow_nx_mask); 291 } 292 293 static u64 make_spte_nonexecutable(u64 spte) 294 { 295 return modify_spte_protections(spte, shadow_nx_mask, shadow_x_mask); 296 } 297 298 /* 299 * Construct an SPTE that maps a sub-page of the given huge page SPTE where 300 * `index` identifies which sub-page. 301 * 302 * This is used during huge page splitting to build the SPTEs that make up the 303 * new page table. 304 */ 305 u64 make_small_spte(struct kvm *kvm, u64 huge_spte, 306 union kvm_mmu_page_role role, int index) 307 { 308 u64 child_spte = huge_spte; 309 310 KVM_BUG_ON(!is_shadow_present_pte(huge_spte) || !is_large_pte(huge_spte), kvm); 311 312 /* 313 * The child_spte already has the base address of the huge page being 314 * split. So we just have to OR in the offset to the page at the next 315 * lower level for the given index. 316 */ 317 child_spte |= (index * KVM_PAGES_PER_HPAGE(role.level)) << PAGE_SHIFT; 318 319 if (role.level == PG_LEVEL_4K) { 320 child_spte &= ~PT_PAGE_SIZE_MASK; 321 322 /* 323 * When splitting to a 4K page where execution is allowed, mark 324 * the page executable as the NX hugepage mitigation no longer 325 * applies. 326 */ 327 if ((role.access & ACC_EXEC_MASK) && is_nx_huge_page_enabled(kvm)) 328 child_spte = make_spte_executable(child_spte); 329 } 330 331 return child_spte; 332 } 333 334 u64 make_huge_spte(struct kvm *kvm, u64 small_spte, int level) 335 { 336 u64 huge_spte; 337 338 KVM_BUG_ON(!is_shadow_present_pte(small_spte) || level == PG_LEVEL_4K, kvm); 339 340 huge_spte = small_spte | PT_PAGE_SIZE_MASK; 341 342 /* 343 * huge_spte already has the address of the sub-page being collapsed 344 * from small_spte, so just clear the lower address bits to create the 345 * huge page address. 346 */ 347 huge_spte &= KVM_HPAGE_MASK(level) | ~PAGE_MASK; 348 349 if (is_nx_huge_page_enabled(kvm)) 350 huge_spte = make_spte_nonexecutable(huge_spte); 351 352 return huge_spte; 353 } 354 355 u64 make_nonleaf_spte(u64 *child_pt, bool ad_disabled) 356 { 357 u64 spte = SPTE_MMU_PRESENT_MASK; 358 359 spte |= __pa(child_pt) | shadow_present_mask | PT_WRITABLE_MASK | 360 shadow_user_mask | shadow_x_mask | shadow_me_value; 361 362 if (ad_disabled) 363 spte |= SPTE_TDP_AD_DISABLED; 364 else 365 spte |= shadow_accessed_mask; 366 367 return spte; 368 } 369 370 u64 mark_spte_for_access_track(u64 spte) 371 { 372 if (spte_ad_enabled(spte)) 373 return spte & ~shadow_accessed_mask; 374 375 if (is_access_track_spte(spte)) 376 return spte; 377 378 check_spte_writable_invariants(spte); 379 380 WARN_ONCE(spte & (SHADOW_ACC_TRACK_SAVED_BITS_MASK << 381 SHADOW_ACC_TRACK_SAVED_BITS_SHIFT), 382 "Access Tracking saved bit locations are not zero\n"); 383 384 spte |= (spte & SHADOW_ACC_TRACK_SAVED_BITS_MASK) << 385 SHADOW_ACC_TRACK_SAVED_BITS_SHIFT; 386 spte &= ~(shadow_acc_track_mask | shadow_accessed_mask); 387 388 return spte; 389 } 390 391 void kvm_mmu_set_mmio_spte_mask(u64 mmio_value, u64 mmio_mask, u64 access_mask) 392 { 393 BUG_ON((u64)(unsigned)access_mask != access_mask); 394 WARN_ON(mmio_value & shadow_nonpresent_or_rsvd_lower_gfn_mask); 395 396 /* 397 * Reset to the original module param value to honor userspace's desire 398 * to (dis)allow MMIO caching. Update the param itself so that 399 * userspace can see whether or not KVM is actually using MMIO caching. 400 */ 401 enable_mmio_caching = allow_mmio_caching; 402 if (!enable_mmio_caching) 403 mmio_value = 0; 404 405 /* 406 * The mask must contain only bits that are carved out specifically for 407 * the MMIO SPTE mask, e.g. to ensure there's no overlap with the MMIO 408 * generation. 409 */ 410 if (WARN_ON(mmio_mask & ~SPTE_MMIO_ALLOWED_MASK)) 411 mmio_value = 0; 412 413 /* 414 * Disable MMIO caching if the MMIO value collides with the bits that 415 * are used to hold the relocated GFN when the L1TF mitigation is 416 * enabled. This should never fire as there is no known hardware that 417 * can trigger this condition, e.g. SME/SEV CPUs that require a custom 418 * MMIO value are not susceptible to L1TF. 419 */ 420 if (WARN_ON(mmio_value & (shadow_nonpresent_or_rsvd_mask << 421 SHADOW_NONPRESENT_OR_RSVD_MASK_LEN))) 422 mmio_value = 0; 423 424 /* 425 * The masked MMIO value must obviously match itself and a frozen SPTE 426 * must not get a false positive. Frozen SPTEs and MMIO SPTEs should 427 * never collide as MMIO must set some RWX bits, and frozen SPTEs must 428 * not set any RWX bits. 429 */ 430 if (WARN_ON((mmio_value & mmio_mask) != mmio_value) || 431 WARN_ON(mmio_value && (FROZEN_SPTE & mmio_mask) == mmio_value)) 432 mmio_value = 0; 433 434 if (!mmio_value) 435 enable_mmio_caching = false; 436 437 shadow_mmio_value = mmio_value; 438 shadow_mmio_mask = mmio_mask; 439 shadow_mmio_access_mask = access_mask; 440 } 441 EXPORT_SYMBOL_GPL(kvm_mmu_set_mmio_spte_mask); 442 443 void kvm_mmu_set_me_spte_mask(u64 me_value, u64 me_mask) 444 { 445 /* shadow_me_value must be a subset of shadow_me_mask */ 446 if (WARN_ON(me_value & ~me_mask)) 447 me_value = me_mask = 0; 448 449 shadow_me_value = me_value; 450 shadow_me_mask = me_mask; 451 } 452 EXPORT_SYMBOL_GPL(kvm_mmu_set_me_spte_mask); 453 454 void kvm_mmu_set_ept_masks(bool has_ad_bits, bool has_exec_only) 455 { 456 kvm_ad_enabled = has_ad_bits; 457 458 shadow_user_mask = VMX_EPT_READABLE_MASK; 459 shadow_accessed_mask = VMX_EPT_ACCESS_BIT; 460 shadow_dirty_mask = VMX_EPT_DIRTY_BIT; 461 shadow_nx_mask = 0ull; 462 shadow_x_mask = VMX_EPT_EXECUTABLE_MASK; 463 /* VMX_EPT_SUPPRESS_VE_BIT is needed for W or X violation. */ 464 shadow_present_mask = 465 (has_exec_only ? 0ull : VMX_EPT_READABLE_MASK) | VMX_EPT_SUPPRESS_VE_BIT; 466 /* 467 * EPT overrides the host MTRRs, and so KVM must program the desired 468 * memtype directly into the SPTEs. Note, this mask is just the mask 469 * of all bits that factor into the memtype, the actual memtype must be 470 * dynamically calculated, e.g. to ensure host MMIO is mapped UC. 471 */ 472 shadow_memtype_mask = VMX_EPT_MT_MASK | VMX_EPT_IPAT_BIT; 473 shadow_acc_track_mask = VMX_EPT_RWX_MASK; 474 shadow_host_writable_mask = EPT_SPTE_HOST_WRITABLE; 475 shadow_mmu_writable_mask = EPT_SPTE_MMU_WRITABLE; 476 477 /* 478 * EPT Misconfigurations are generated if the value of bits 2:0 479 * of an EPT paging-structure entry is 110b (write/execute). 480 */ 481 kvm_mmu_set_mmio_spte_mask(VMX_EPT_MISCONFIG_WX_VALUE, 482 VMX_EPT_RWX_MASK | VMX_EPT_SUPPRESS_VE_BIT, 0); 483 } 484 EXPORT_SYMBOL_GPL(kvm_mmu_set_ept_masks); 485 486 void kvm_mmu_reset_all_pte_masks(void) 487 { 488 u8 low_phys_bits; 489 u64 mask; 490 491 kvm_ad_enabled = true; 492 493 /* 494 * If the CPU has 46 or less physical address bits, then set an 495 * appropriate mask to guard against L1TF attacks. Otherwise, it is 496 * assumed that the CPU is not vulnerable to L1TF. 497 * 498 * Some Intel CPUs address the L1 cache using more PA bits than are 499 * reported by CPUID. Use the PA width of the L1 cache when possible 500 * to achieve more effective mitigation, e.g. if system RAM overlaps 501 * the most significant bits of legal physical address space. 502 */ 503 shadow_nonpresent_or_rsvd_mask = 0; 504 low_phys_bits = boot_cpu_data.x86_phys_bits; 505 if (boot_cpu_has_bug(X86_BUG_L1TF) && 506 !WARN_ON_ONCE(boot_cpu_data.x86_cache_bits >= 507 52 - SHADOW_NONPRESENT_OR_RSVD_MASK_LEN)) { 508 low_phys_bits = boot_cpu_data.x86_cache_bits 509 - SHADOW_NONPRESENT_OR_RSVD_MASK_LEN; 510 shadow_nonpresent_or_rsvd_mask = 511 rsvd_bits(low_phys_bits, boot_cpu_data.x86_cache_bits - 1); 512 } 513 514 shadow_nonpresent_or_rsvd_lower_gfn_mask = 515 GENMASK_ULL(low_phys_bits - 1, PAGE_SHIFT); 516 517 shadow_user_mask = PT_USER_MASK; 518 shadow_accessed_mask = PT_ACCESSED_MASK; 519 shadow_dirty_mask = PT_DIRTY_MASK; 520 shadow_nx_mask = PT64_NX_MASK; 521 shadow_x_mask = 0; 522 shadow_present_mask = PT_PRESENT_MASK; 523 524 /* 525 * For shadow paging and NPT, KVM uses PAT entry '0' to encode WB 526 * memtype in the SPTEs, i.e. relies on host MTRRs to provide the 527 * correct memtype (WB is the "weakest" memtype). 528 */ 529 shadow_memtype_mask = 0; 530 shadow_acc_track_mask = 0; 531 shadow_me_mask = 0; 532 shadow_me_value = 0; 533 534 shadow_host_writable_mask = DEFAULT_SPTE_HOST_WRITABLE; 535 shadow_mmu_writable_mask = DEFAULT_SPTE_MMU_WRITABLE; 536 537 /* 538 * Set a reserved PA bit in MMIO SPTEs to generate page faults with 539 * PFEC.RSVD=1 on MMIO accesses. 64-bit PTEs (PAE, x86-64, and EPT 540 * paging) support a maximum of 52 bits of PA, i.e. if the CPU supports 541 * 52-bit physical addresses then there are no reserved PA bits in the 542 * PTEs and so the reserved PA approach must be disabled. 543 */ 544 if (kvm_host.maxphyaddr < 52) 545 mask = BIT_ULL(51) | PT_PRESENT_MASK; 546 else 547 mask = 0; 548 549 kvm_mmu_set_mmio_spte_mask(mask, mask, ACC_WRITE_MASK | ACC_USER_MASK); 550 } 551