xref: /linux/arch/x86/kvm/mmu.h (revision 87c9c16317882dd6dbbc07e349bc3223e14f3244)
1 /* SPDX-License-Identifier: GPL-2.0 */
2 #ifndef __KVM_X86_MMU_H
3 #define __KVM_X86_MMU_H
4 
5 #include <linux/kvm_host.h>
6 #include "kvm_cache_regs.h"
7 #include "cpuid.h"
8 
9 #define PT64_PT_BITS 9
10 #define PT64_ENT_PER_PAGE (1 << PT64_PT_BITS)
11 #define PT32_PT_BITS 10
12 #define PT32_ENT_PER_PAGE (1 << PT32_PT_BITS)
13 
14 #define PT_WRITABLE_SHIFT 1
15 #define PT_USER_SHIFT 2
16 
17 #define PT_PRESENT_MASK (1ULL << 0)
18 #define PT_WRITABLE_MASK (1ULL << PT_WRITABLE_SHIFT)
19 #define PT_USER_MASK (1ULL << PT_USER_SHIFT)
20 #define PT_PWT_MASK (1ULL << 3)
21 #define PT_PCD_MASK (1ULL << 4)
22 #define PT_ACCESSED_SHIFT 5
23 #define PT_ACCESSED_MASK (1ULL << PT_ACCESSED_SHIFT)
24 #define PT_DIRTY_SHIFT 6
25 #define PT_DIRTY_MASK (1ULL << PT_DIRTY_SHIFT)
26 #define PT_PAGE_SIZE_SHIFT 7
27 #define PT_PAGE_SIZE_MASK (1ULL << PT_PAGE_SIZE_SHIFT)
28 #define PT_PAT_MASK (1ULL << 7)
29 #define PT_GLOBAL_MASK (1ULL << 8)
30 #define PT64_NX_SHIFT 63
31 #define PT64_NX_MASK (1ULL << PT64_NX_SHIFT)
32 
33 #define PT_PAT_SHIFT 7
34 #define PT_DIR_PAT_SHIFT 12
35 #define PT_DIR_PAT_MASK (1ULL << PT_DIR_PAT_SHIFT)
36 
37 #define PT32_DIR_PSE36_SIZE 4
38 #define PT32_DIR_PSE36_SHIFT 13
39 #define PT32_DIR_PSE36_MASK \
40 	(((1ULL << PT32_DIR_PSE36_SIZE) - 1) << PT32_DIR_PSE36_SHIFT)
41 
42 #define PT64_ROOT_5LEVEL 5
43 #define PT64_ROOT_4LEVEL 4
44 #define PT32_ROOT_LEVEL 2
45 #define PT32E_ROOT_LEVEL 3
46 
47 static __always_inline u64 rsvd_bits(int s, int e)
48 {
49 	BUILD_BUG_ON(__builtin_constant_p(e) && __builtin_constant_p(s) && e < s);
50 
51 	if (__builtin_constant_p(e))
52 		BUILD_BUG_ON(e > 63);
53 	else
54 		e &= 63;
55 
56 	if (e < s)
57 		return 0;
58 
59 	return ((2ULL << (e - s)) - 1) << s;
60 }
61 
62 void kvm_mmu_set_mmio_spte_mask(u64 mmio_value, u64 mmio_mask, u64 access_mask);
63 void kvm_mmu_set_ept_masks(bool has_ad_bits, bool has_exec_only);
64 
65 void
66 reset_shadow_zero_bits_mask(struct kvm_vcpu *vcpu, struct kvm_mmu *context);
67 
68 void kvm_init_mmu(struct kvm_vcpu *vcpu, bool reset_roots);
69 void kvm_init_shadow_npt_mmu(struct kvm_vcpu *vcpu, u32 cr0, u32 cr4, u32 efer,
70 			     gpa_t nested_cr3);
71 void kvm_init_shadow_ept_mmu(struct kvm_vcpu *vcpu, bool execonly,
72 			     bool accessed_dirty, gpa_t new_eptp);
73 bool kvm_can_do_async_pf(struct kvm_vcpu *vcpu);
74 int kvm_handle_page_fault(struct kvm_vcpu *vcpu, u64 error_code,
75 				u64 fault_address, char *insn, int insn_len);
76 
77 int kvm_mmu_load(struct kvm_vcpu *vcpu);
78 void kvm_mmu_unload(struct kvm_vcpu *vcpu);
79 void kvm_mmu_sync_roots(struct kvm_vcpu *vcpu);
80 
81 static inline int kvm_mmu_reload(struct kvm_vcpu *vcpu)
82 {
83 	if (likely(vcpu->arch.mmu->root_hpa != INVALID_PAGE))
84 		return 0;
85 
86 	return kvm_mmu_load(vcpu);
87 }
88 
89 static inline unsigned long kvm_get_pcid(struct kvm_vcpu *vcpu, gpa_t cr3)
90 {
91 	BUILD_BUG_ON((X86_CR3_PCID_MASK & PAGE_MASK) != 0);
92 
93 	return kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE)
94 	       ? cr3 & X86_CR3_PCID_MASK
95 	       : 0;
96 }
97 
98 static inline unsigned long kvm_get_active_pcid(struct kvm_vcpu *vcpu)
99 {
100 	return kvm_get_pcid(vcpu, kvm_read_cr3(vcpu));
101 }
102 
103 static inline void kvm_mmu_load_pgd(struct kvm_vcpu *vcpu)
104 {
105 	u64 root_hpa = vcpu->arch.mmu->root_hpa;
106 
107 	if (!VALID_PAGE(root_hpa))
108 		return;
109 
110 	static_call(kvm_x86_load_mmu_pgd)(vcpu, root_hpa,
111 					  vcpu->arch.mmu->shadow_root_level);
112 }
113 
114 int kvm_tdp_page_fault(struct kvm_vcpu *vcpu, gpa_t gpa, u32 error_code,
115 		       bool prefault);
116 
117 static inline int kvm_mmu_do_page_fault(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa,
118 					u32 err, bool prefault)
119 {
120 #ifdef CONFIG_RETPOLINE
121 	if (likely(vcpu->arch.mmu->page_fault == kvm_tdp_page_fault))
122 		return kvm_tdp_page_fault(vcpu, cr2_or_gpa, err, prefault);
123 #endif
124 	return vcpu->arch.mmu->page_fault(vcpu, cr2_or_gpa, err, prefault);
125 }
126 
127 /*
128  * Currently, we have two sorts of write-protection, a) the first one
129  * write-protects guest page to sync the guest modification, b) another one is
130  * used to sync dirty bitmap when we do KVM_GET_DIRTY_LOG. The differences
131  * between these two sorts are:
132  * 1) the first case clears MMU-writable bit.
133  * 2) the first case requires flushing tlb immediately avoiding corrupting
134  *    shadow page table between all vcpus so it should be in the protection of
135  *    mmu-lock. And the another case does not need to flush tlb until returning
136  *    the dirty bitmap to userspace since it only write-protects the page
137  *    logged in the bitmap, that means the page in the dirty bitmap is not
138  *    missed, so it can flush tlb out of mmu-lock.
139  *
140  * So, there is the problem: the first case can meet the corrupted tlb caused
141  * by another case which write-protects pages but without flush tlb
142  * immediately. In order to making the first case be aware this problem we let
143  * it flush tlb if we try to write-protect a spte whose MMU-writable bit
144  * is set, it works since another case never touches MMU-writable bit.
145  *
146  * Anyway, whenever a spte is updated (only permission and status bits are
147  * changed) we need to check whether the spte with MMU-writable becomes
148  * readonly, if that happens, we need to flush tlb. Fortunately,
149  * mmu_spte_update() has already handled it perfectly.
150  *
151  * The rules to use MMU-writable and PT_WRITABLE_MASK:
152  * - if we want to see if it has writable tlb entry or if the spte can be
153  *   writable on the mmu mapping, check MMU-writable, this is the most
154  *   case, otherwise
155  * - if we fix page fault on the spte or do write-protection by dirty logging,
156  *   check PT_WRITABLE_MASK.
157  *
158  * TODO: introduce APIs to split these two cases.
159  */
160 static inline bool is_writable_pte(unsigned long pte)
161 {
162 	return pte & PT_WRITABLE_MASK;
163 }
164 
165 static inline bool is_write_protection(struct kvm_vcpu *vcpu)
166 {
167 	return kvm_read_cr0_bits(vcpu, X86_CR0_WP);
168 }
169 
170 /*
171  * Check if a given access (described through the I/D, W/R and U/S bits of a
172  * page fault error code pfec) causes a permission fault with the given PTE
173  * access rights (in ACC_* format).
174  *
175  * Return zero if the access does not fault; return the page fault error code
176  * if the access faults.
177  */
178 static inline u8 permission_fault(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
179 				  unsigned pte_access, unsigned pte_pkey,
180 				  unsigned pfec)
181 {
182 	int cpl = static_call(kvm_x86_get_cpl)(vcpu);
183 	unsigned long rflags = static_call(kvm_x86_get_rflags)(vcpu);
184 
185 	/*
186 	 * If CPL < 3, SMAP prevention are disabled if EFLAGS.AC = 1.
187 	 *
188 	 * If CPL = 3, SMAP applies to all supervisor-mode data accesses
189 	 * (these are implicit supervisor accesses) regardless of the value
190 	 * of EFLAGS.AC.
191 	 *
192 	 * This computes (cpl < 3) && (rflags & X86_EFLAGS_AC), leaving
193 	 * the result in X86_EFLAGS_AC. We then insert it in place of
194 	 * the PFERR_RSVD_MASK bit; this bit will always be zero in pfec,
195 	 * but it will be one in index if SMAP checks are being overridden.
196 	 * It is important to keep this branchless.
197 	 */
198 	unsigned long smap = (cpl - 3) & (rflags & X86_EFLAGS_AC);
199 	int index = (pfec >> 1) +
200 		    (smap >> (X86_EFLAGS_AC_BIT - PFERR_RSVD_BIT + 1));
201 	bool fault = (mmu->permissions[index] >> pte_access) & 1;
202 	u32 errcode = PFERR_PRESENT_MASK;
203 
204 	WARN_ON(pfec & (PFERR_PK_MASK | PFERR_RSVD_MASK));
205 	if (unlikely(mmu->pkru_mask)) {
206 		u32 pkru_bits, offset;
207 
208 		/*
209 		* PKRU defines 32 bits, there are 16 domains and 2
210 		* attribute bits per domain in pkru.  pte_pkey is the
211 		* index of the protection domain, so pte_pkey * 2 is
212 		* is the index of the first bit for the domain.
213 		*/
214 		pkru_bits = (vcpu->arch.pkru >> (pte_pkey * 2)) & 3;
215 
216 		/* clear present bit, replace PFEC.RSVD with ACC_USER_MASK. */
217 		offset = (pfec & ~1) +
218 			((pte_access & PT_USER_MASK) << (PFERR_RSVD_BIT - PT_USER_SHIFT));
219 
220 		pkru_bits &= mmu->pkru_mask >> offset;
221 		errcode |= -pkru_bits & PFERR_PK_MASK;
222 		fault |= (pkru_bits != 0);
223 	}
224 
225 	return -(u32)fault & errcode;
226 }
227 
228 void kvm_zap_gfn_range(struct kvm *kvm, gfn_t gfn_start, gfn_t gfn_end);
229 
230 int kvm_arch_write_log_dirty(struct kvm_vcpu *vcpu);
231 
232 int kvm_mmu_post_init_vm(struct kvm *kvm);
233 void kvm_mmu_pre_destroy_vm(struct kvm *kvm);
234 
235 #endif
236