1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef __KVM_X86_MMU_H 3 #define __KVM_X86_MMU_H 4 5 #include <linux/kvm_host.h> 6 #include "kvm_cache_regs.h" 7 #include "cpuid.h" 8 9 #define PT64_PT_BITS 9 10 #define PT64_ENT_PER_PAGE (1 << PT64_PT_BITS) 11 #define PT32_PT_BITS 10 12 #define PT32_ENT_PER_PAGE (1 << PT32_PT_BITS) 13 14 #define PT_WRITABLE_SHIFT 1 15 #define PT_USER_SHIFT 2 16 17 #define PT_PRESENT_MASK (1ULL << 0) 18 #define PT_WRITABLE_MASK (1ULL << PT_WRITABLE_SHIFT) 19 #define PT_USER_MASK (1ULL << PT_USER_SHIFT) 20 #define PT_PWT_MASK (1ULL << 3) 21 #define PT_PCD_MASK (1ULL << 4) 22 #define PT_ACCESSED_SHIFT 5 23 #define PT_ACCESSED_MASK (1ULL << PT_ACCESSED_SHIFT) 24 #define PT_DIRTY_SHIFT 6 25 #define PT_DIRTY_MASK (1ULL << PT_DIRTY_SHIFT) 26 #define PT_PAGE_SIZE_SHIFT 7 27 #define PT_PAGE_SIZE_MASK (1ULL << PT_PAGE_SIZE_SHIFT) 28 #define PT_PAT_MASK (1ULL << 7) 29 #define PT_GLOBAL_MASK (1ULL << 8) 30 #define PT64_NX_SHIFT 63 31 #define PT64_NX_MASK (1ULL << PT64_NX_SHIFT) 32 33 #define PT_PAT_SHIFT 7 34 #define PT_DIR_PAT_SHIFT 12 35 #define PT_DIR_PAT_MASK (1ULL << PT_DIR_PAT_SHIFT) 36 37 #define PT32_DIR_PSE36_SIZE 4 38 #define PT32_DIR_PSE36_SHIFT 13 39 #define PT32_DIR_PSE36_MASK \ 40 (((1ULL << PT32_DIR_PSE36_SIZE) - 1) << PT32_DIR_PSE36_SHIFT) 41 42 #define PT64_ROOT_5LEVEL 5 43 #define PT64_ROOT_4LEVEL 4 44 #define PT32_ROOT_LEVEL 2 45 #define PT32E_ROOT_LEVEL 3 46 47 #define KVM_MMU_CR4_ROLE_BITS (X86_CR4_PSE | X86_CR4_PAE | X86_CR4_LA57 | \ 48 X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE) 49 50 #define KVM_MMU_CR0_ROLE_BITS (X86_CR0_PG | X86_CR0_WP) 51 #define KVM_MMU_EFER_ROLE_BITS (EFER_LME | EFER_NX) 52 53 static __always_inline u64 rsvd_bits(int s, int e) 54 { 55 BUILD_BUG_ON(__builtin_constant_p(e) && __builtin_constant_p(s) && e < s); 56 57 if (__builtin_constant_p(e)) 58 BUILD_BUG_ON(e > 63); 59 else 60 e &= 63; 61 62 if (e < s) 63 return 0; 64 65 return ((2ULL << (e - s)) - 1) << s; 66 } 67 68 void kvm_mmu_set_mmio_spte_mask(u64 mmio_value, u64 mmio_mask, u64 access_mask); 69 void kvm_mmu_set_ept_masks(bool has_ad_bits, bool has_exec_only); 70 71 void kvm_init_mmu(struct kvm_vcpu *vcpu); 72 void kvm_init_shadow_npt_mmu(struct kvm_vcpu *vcpu, unsigned long cr0, 73 unsigned long cr4, u64 efer, gpa_t nested_cr3); 74 void kvm_init_shadow_ept_mmu(struct kvm_vcpu *vcpu, bool execonly, 75 int huge_page_level, bool accessed_dirty, 76 gpa_t new_eptp); 77 bool kvm_can_do_async_pf(struct kvm_vcpu *vcpu); 78 int kvm_handle_page_fault(struct kvm_vcpu *vcpu, u64 error_code, 79 u64 fault_address, char *insn, int insn_len); 80 81 int kvm_mmu_load(struct kvm_vcpu *vcpu); 82 void kvm_mmu_unload(struct kvm_vcpu *vcpu); 83 void kvm_mmu_free_obsolete_roots(struct kvm_vcpu *vcpu); 84 void kvm_mmu_sync_roots(struct kvm_vcpu *vcpu); 85 void kvm_mmu_sync_prev_roots(struct kvm_vcpu *vcpu); 86 87 static inline int kvm_mmu_reload(struct kvm_vcpu *vcpu) 88 { 89 if (likely(vcpu->arch.mmu->root.hpa != INVALID_PAGE)) 90 return 0; 91 92 return kvm_mmu_load(vcpu); 93 } 94 95 static inline unsigned long kvm_get_pcid(struct kvm_vcpu *vcpu, gpa_t cr3) 96 { 97 BUILD_BUG_ON((X86_CR3_PCID_MASK & PAGE_MASK) != 0); 98 99 return kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE) 100 ? cr3 & X86_CR3_PCID_MASK 101 : 0; 102 } 103 104 static inline unsigned long kvm_get_active_pcid(struct kvm_vcpu *vcpu) 105 { 106 return kvm_get_pcid(vcpu, kvm_read_cr3(vcpu)); 107 } 108 109 static inline void kvm_mmu_load_pgd(struct kvm_vcpu *vcpu) 110 { 111 u64 root_hpa = vcpu->arch.mmu->root.hpa; 112 113 if (!VALID_PAGE(root_hpa)) 114 return; 115 116 static_call(kvm_x86_load_mmu_pgd)(vcpu, root_hpa, 117 vcpu->arch.mmu->shadow_root_level); 118 } 119 120 struct kvm_page_fault { 121 /* arguments to kvm_mmu_do_page_fault. */ 122 const gpa_t addr; 123 const u32 error_code; 124 const bool prefetch; 125 126 /* Derived from error_code. */ 127 const bool exec; 128 const bool write; 129 const bool present; 130 const bool rsvd; 131 const bool user; 132 133 /* Derived from mmu and global state. */ 134 const bool is_tdp; 135 const bool nx_huge_page_workaround_enabled; 136 137 /* 138 * Whether a >4KB mapping can be created or is forbidden due to NX 139 * hugepages. 140 */ 141 bool huge_page_disallowed; 142 143 /* 144 * Maximum page size that can be created for this fault; input to 145 * FNAME(fetch), __direct_map and kvm_tdp_mmu_map. 146 */ 147 u8 max_level; 148 149 /* 150 * Page size that can be created based on the max_level and the 151 * page size used by the host mapping. 152 */ 153 u8 req_level; 154 155 /* 156 * Page size that will be created based on the req_level and 157 * huge_page_disallowed. 158 */ 159 u8 goal_level; 160 161 /* Shifted addr, or result of guest page table walk if addr is a gva. */ 162 gfn_t gfn; 163 164 /* The memslot containing gfn. May be NULL. */ 165 struct kvm_memory_slot *slot; 166 167 /* Outputs of kvm_faultin_pfn. */ 168 kvm_pfn_t pfn; 169 hva_t hva; 170 bool map_writable; 171 }; 172 173 int kvm_tdp_page_fault(struct kvm_vcpu *vcpu, struct kvm_page_fault *fault); 174 175 extern int nx_huge_pages; 176 static inline bool is_nx_huge_page_enabled(void) 177 { 178 return READ_ONCE(nx_huge_pages); 179 } 180 181 static inline int kvm_mmu_do_page_fault(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa, 182 u32 err, bool prefetch) 183 { 184 struct kvm_page_fault fault = { 185 .addr = cr2_or_gpa, 186 .error_code = err, 187 .exec = err & PFERR_FETCH_MASK, 188 .write = err & PFERR_WRITE_MASK, 189 .present = err & PFERR_PRESENT_MASK, 190 .rsvd = err & PFERR_RSVD_MASK, 191 .user = err & PFERR_USER_MASK, 192 .prefetch = prefetch, 193 .is_tdp = likely(vcpu->arch.mmu->page_fault == kvm_tdp_page_fault), 194 .nx_huge_page_workaround_enabled = is_nx_huge_page_enabled(), 195 196 .max_level = KVM_MAX_HUGEPAGE_LEVEL, 197 .req_level = PG_LEVEL_4K, 198 .goal_level = PG_LEVEL_4K, 199 }; 200 #ifdef CONFIG_RETPOLINE 201 if (fault.is_tdp) 202 return kvm_tdp_page_fault(vcpu, &fault); 203 #endif 204 return vcpu->arch.mmu->page_fault(vcpu, &fault); 205 } 206 207 /* 208 * Check if a given access (described through the I/D, W/R and U/S bits of a 209 * page fault error code pfec) causes a permission fault with the given PTE 210 * access rights (in ACC_* format). 211 * 212 * Return zero if the access does not fault; return the page fault error code 213 * if the access faults. 214 */ 215 static inline u8 permission_fault(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, 216 unsigned pte_access, unsigned pte_pkey, 217 u64 access) 218 { 219 /* strip nested paging fault error codes */ 220 unsigned int pfec = access; 221 unsigned long rflags = static_call(kvm_x86_get_rflags)(vcpu); 222 223 /* 224 * For explicit supervisor accesses, SMAP is disabled if EFLAGS.AC = 1. 225 * For implicit supervisor accesses, SMAP cannot be overridden. 226 * 227 * SMAP works on supervisor accesses only, and not_smap can 228 * be set or not set when user access with neither has any bearing 229 * on the result. 230 * 231 * We put the SMAP checking bit in place of the PFERR_RSVD_MASK bit; 232 * this bit will always be zero in pfec, but it will be one in index 233 * if SMAP checks are being disabled. 234 */ 235 u64 implicit_access = access & PFERR_IMPLICIT_ACCESS; 236 bool not_smap = ((rflags & X86_EFLAGS_AC) | implicit_access) == X86_EFLAGS_AC; 237 int index = (pfec + (not_smap << PFERR_RSVD_BIT)) >> 1; 238 bool fault = (mmu->permissions[index] >> pte_access) & 1; 239 u32 errcode = PFERR_PRESENT_MASK; 240 241 WARN_ON(pfec & (PFERR_PK_MASK | PFERR_RSVD_MASK)); 242 if (unlikely(mmu->pkru_mask)) { 243 u32 pkru_bits, offset; 244 245 /* 246 * PKRU defines 32 bits, there are 16 domains and 2 247 * attribute bits per domain in pkru. pte_pkey is the 248 * index of the protection domain, so pte_pkey * 2 is 249 * is the index of the first bit for the domain. 250 */ 251 pkru_bits = (vcpu->arch.pkru >> (pte_pkey * 2)) & 3; 252 253 /* clear present bit, replace PFEC.RSVD with ACC_USER_MASK. */ 254 offset = (pfec & ~1) + 255 ((pte_access & PT_USER_MASK) << (PFERR_RSVD_BIT - PT_USER_SHIFT)); 256 257 pkru_bits &= mmu->pkru_mask >> offset; 258 errcode |= -pkru_bits & PFERR_PK_MASK; 259 fault |= (pkru_bits != 0); 260 } 261 262 return -(u32)fault & errcode; 263 } 264 265 void kvm_zap_gfn_range(struct kvm *kvm, gfn_t gfn_start, gfn_t gfn_end); 266 267 int kvm_arch_write_log_dirty(struct kvm_vcpu *vcpu); 268 269 int kvm_mmu_post_init_vm(struct kvm *kvm); 270 void kvm_mmu_pre_destroy_vm(struct kvm *kvm); 271 272 static inline bool kvm_shadow_root_allocated(struct kvm *kvm) 273 { 274 /* 275 * Read shadow_root_allocated before related pointers. Hence, threads 276 * reading shadow_root_allocated in any lock context are guaranteed to 277 * see the pointers. Pairs with smp_store_release in 278 * mmu_first_shadow_root_alloc. 279 */ 280 return smp_load_acquire(&kvm->arch.shadow_root_allocated); 281 } 282 283 #ifdef CONFIG_X86_64 284 static inline bool is_tdp_mmu_enabled(struct kvm *kvm) { return kvm->arch.tdp_mmu_enabled; } 285 #else 286 static inline bool is_tdp_mmu_enabled(struct kvm *kvm) { return false; } 287 #endif 288 289 static inline bool kvm_memslots_have_rmaps(struct kvm *kvm) 290 { 291 return !is_tdp_mmu_enabled(kvm) || kvm_shadow_root_allocated(kvm); 292 } 293 294 static inline gfn_t gfn_to_index(gfn_t gfn, gfn_t base_gfn, int level) 295 { 296 /* KVM_HPAGE_GFN_SHIFT(PG_LEVEL_4K) must be 0. */ 297 return (gfn >> KVM_HPAGE_GFN_SHIFT(level)) - 298 (base_gfn >> KVM_HPAGE_GFN_SHIFT(level)); 299 } 300 301 static inline unsigned long 302 __kvm_mmu_slot_lpages(struct kvm_memory_slot *slot, unsigned long npages, 303 int level) 304 { 305 return gfn_to_index(slot->base_gfn + npages - 1, 306 slot->base_gfn, level) + 1; 307 } 308 309 static inline unsigned long 310 kvm_mmu_slot_lpages(struct kvm_memory_slot *slot, int level) 311 { 312 return __kvm_mmu_slot_lpages(slot, slot->npages, level); 313 } 314 315 static inline void kvm_update_page_stats(struct kvm *kvm, int level, int count) 316 { 317 atomic64_add(count, &kvm->stat.pages[level - 1]); 318 } 319 320 gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u64 access, 321 struct x86_exception *exception); 322 323 static inline gpa_t kvm_translate_gpa(struct kvm_vcpu *vcpu, 324 struct kvm_mmu *mmu, 325 gpa_t gpa, u64 access, 326 struct x86_exception *exception) 327 { 328 if (mmu != &vcpu->arch.nested_mmu) 329 return gpa; 330 return translate_nested_gpa(vcpu, gpa, access, exception); 331 } 332 #endif 333