1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef __KVM_X86_MMU_H 3 #define __KVM_X86_MMU_H 4 5 #include <linux/kvm_host.h> 6 #include "kvm_cache_regs.h" 7 #include "cpuid.h" 8 9 extern bool __read_mostly enable_mmio_caching; 10 11 #define PT_WRITABLE_SHIFT 1 12 #define PT_USER_SHIFT 2 13 14 #define PT_PRESENT_MASK (1ULL << 0) 15 #define PT_WRITABLE_MASK (1ULL << PT_WRITABLE_SHIFT) 16 #define PT_USER_MASK (1ULL << PT_USER_SHIFT) 17 #define PT_PWT_MASK (1ULL << 3) 18 #define PT_PCD_MASK (1ULL << 4) 19 #define PT_ACCESSED_SHIFT 5 20 #define PT_ACCESSED_MASK (1ULL << PT_ACCESSED_SHIFT) 21 #define PT_DIRTY_SHIFT 6 22 #define PT_DIRTY_MASK (1ULL << PT_DIRTY_SHIFT) 23 #define PT_PAGE_SIZE_SHIFT 7 24 #define PT_PAGE_SIZE_MASK (1ULL << PT_PAGE_SIZE_SHIFT) 25 #define PT_PAT_MASK (1ULL << 7) 26 #define PT_GLOBAL_MASK (1ULL << 8) 27 #define PT64_NX_SHIFT 63 28 #define PT64_NX_MASK (1ULL << PT64_NX_SHIFT) 29 30 #define PT_PAT_SHIFT 7 31 #define PT_DIR_PAT_SHIFT 12 32 #define PT_DIR_PAT_MASK (1ULL << PT_DIR_PAT_SHIFT) 33 34 #define PT64_ROOT_5LEVEL 5 35 #define PT64_ROOT_4LEVEL 4 36 #define PT32_ROOT_LEVEL 2 37 #define PT32E_ROOT_LEVEL 3 38 39 #define KVM_MMU_CR4_ROLE_BITS (X86_CR4_PSE | X86_CR4_PAE | X86_CR4_LA57 | \ 40 X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE) 41 42 #define KVM_MMU_CR0_ROLE_BITS (X86_CR0_PG | X86_CR0_WP) 43 #define KVM_MMU_EFER_ROLE_BITS (EFER_LME | EFER_NX) 44 45 static __always_inline u64 rsvd_bits(int s, int e) 46 { 47 BUILD_BUG_ON(__builtin_constant_p(e) && __builtin_constant_p(s) && e < s); 48 49 if (__builtin_constant_p(e)) 50 BUILD_BUG_ON(e > 63); 51 else 52 e &= 63; 53 54 if (e < s) 55 return 0; 56 57 return ((2ULL << (e - s)) - 1) << s; 58 } 59 60 /* 61 * The number of non-reserved physical address bits irrespective of features 62 * that repurpose legal bits, e.g. MKTME. 63 */ 64 extern u8 __read_mostly shadow_phys_bits; 65 66 static inline gfn_t kvm_mmu_max_gfn(void) 67 { 68 /* 69 * Note that this uses the host MAXPHYADDR, not the guest's. 70 * EPT/NPT cannot support GPAs that would exceed host.MAXPHYADDR; 71 * assuming KVM is running on bare metal, guest accesses beyond 72 * host.MAXPHYADDR will hit a #PF(RSVD) and never cause a vmexit 73 * (either EPT Violation/Misconfig or #NPF), and so KVM will never 74 * install a SPTE for such addresses. If KVM is running as a VM 75 * itself, on the other hand, it might see a MAXPHYADDR that is less 76 * than hardware's real MAXPHYADDR. Using the host MAXPHYADDR 77 * disallows such SPTEs entirely and simplifies the TDP MMU. 78 */ 79 int max_gpa_bits = likely(tdp_enabled) ? shadow_phys_bits : 52; 80 81 return (1ULL << (max_gpa_bits - PAGE_SHIFT)) - 1; 82 } 83 84 static inline u8 kvm_get_shadow_phys_bits(void) 85 { 86 /* 87 * boot_cpu_data.x86_phys_bits is reduced when MKTME or SME are detected 88 * in CPU detection code, but the processor treats those reduced bits as 89 * 'keyID' thus they are not reserved bits. Therefore KVM needs to look at 90 * the physical address bits reported by CPUID. 91 */ 92 if (likely(boot_cpu_data.extended_cpuid_level >= 0x80000008)) 93 return cpuid_eax(0x80000008) & 0xff; 94 95 /* 96 * Quite weird to have VMX or SVM but not MAXPHYADDR; probably a VM with 97 * custom CPUID. Proceed with whatever the kernel found since these features 98 * aren't virtualizable (SME/SEV also require CPUIDs higher than 0x80000008). 99 */ 100 return boot_cpu_data.x86_phys_bits; 101 } 102 103 u8 kvm_mmu_get_max_tdp_level(void); 104 105 void kvm_mmu_set_mmio_spte_mask(u64 mmio_value, u64 mmio_mask, u64 access_mask); 106 void kvm_mmu_set_me_spte_mask(u64 me_value, u64 me_mask); 107 void kvm_mmu_set_ept_masks(bool has_ad_bits, bool has_exec_only); 108 109 void kvm_init_mmu(struct kvm_vcpu *vcpu); 110 void kvm_init_shadow_npt_mmu(struct kvm_vcpu *vcpu, unsigned long cr0, 111 unsigned long cr4, u64 efer, gpa_t nested_cr3); 112 void kvm_init_shadow_ept_mmu(struct kvm_vcpu *vcpu, bool execonly, 113 int huge_page_level, bool accessed_dirty, 114 gpa_t new_eptp); 115 bool kvm_can_do_async_pf(struct kvm_vcpu *vcpu); 116 int kvm_handle_page_fault(struct kvm_vcpu *vcpu, u64 error_code, 117 u64 fault_address, char *insn, int insn_len); 118 void __kvm_mmu_refresh_passthrough_bits(struct kvm_vcpu *vcpu, 119 struct kvm_mmu *mmu); 120 121 int kvm_mmu_load(struct kvm_vcpu *vcpu); 122 void kvm_mmu_unload(struct kvm_vcpu *vcpu); 123 void kvm_mmu_free_obsolete_roots(struct kvm_vcpu *vcpu); 124 void kvm_mmu_sync_roots(struct kvm_vcpu *vcpu); 125 void kvm_mmu_sync_prev_roots(struct kvm_vcpu *vcpu); 126 void kvm_mmu_track_write(struct kvm_vcpu *vcpu, gpa_t gpa, const u8 *new, 127 int bytes); 128 129 static inline int kvm_mmu_reload(struct kvm_vcpu *vcpu) 130 { 131 if (likely(vcpu->arch.mmu->root.hpa != INVALID_PAGE)) 132 return 0; 133 134 return kvm_mmu_load(vcpu); 135 } 136 137 static inline unsigned long kvm_get_pcid(struct kvm_vcpu *vcpu, gpa_t cr3) 138 { 139 BUILD_BUG_ON((X86_CR3_PCID_MASK & PAGE_MASK) != 0); 140 141 return kvm_is_cr4_bit_set(vcpu, X86_CR4_PCIDE) 142 ? cr3 & X86_CR3_PCID_MASK 143 : 0; 144 } 145 146 static inline unsigned long kvm_get_active_pcid(struct kvm_vcpu *vcpu) 147 { 148 return kvm_get_pcid(vcpu, kvm_read_cr3(vcpu)); 149 } 150 151 static inline unsigned long kvm_get_active_cr3_lam_bits(struct kvm_vcpu *vcpu) 152 { 153 if (!guest_can_use(vcpu, X86_FEATURE_LAM)) 154 return 0; 155 156 return kvm_read_cr3(vcpu) & (X86_CR3_LAM_U48 | X86_CR3_LAM_U57); 157 } 158 159 static inline void kvm_mmu_load_pgd(struct kvm_vcpu *vcpu) 160 { 161 u64 root_hpa = vcpu->arch.mmu->root.hpa; 162 163 if (!VALID_PAGE(root_hpa)) 164 return; 165 166 static_call(kvm_x86_load_mmu_pgd)(vcpu, root_hpa, 167 vcpu->arch.mmu->root_role.level); 168 } 169 170 static inline void kvm_mmu_refresh_passthrough_bits(struct kvm_vcpu *vcpu, 171 struct kvm_mmu *mmu) 172 { 173 /* 174 * When EPT is enabled, KVM may passthrough CR0.WP to the guest, i.e. 175 * @mmu's snapshot of CR0.WP and thus all related paging metadata may 176 * be stale. Refresh CR0.WP and the metadata on-demand when checking 177 * for permission faults. Exempt nested MMUs, i.e. MMUs for shadowing 178 * nEPT and nNPT, as CR0.WP is ignored in both cases. Note, KVM does 179 * need to refresh nested_mmu, a.k.a. the walker used to translate L2 180 * GVAs to GPAs, as that "MMU" needs to honor L2's CR0.WP. 181 */ 182 if (!tdp_enabled || mmu == &vcpu->arch.guest_mmu) 183 return; 184 185 __kvm_mmu_refresh_passthrough_bits(vcpu, mmu); 186 } 187 188 /* 189 * Check if a given access (described through the I/D, W/R and U/S bits of a 190 * page fault error code pfec) causes a permission fault with the given PTE 191 * access rights (in ACC_* format). 192 * 193 * Return zero if the access does not fault; return the page fault error code 194 * if the access faults. 195 */ 196 static inline u8 permission_fault(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, 197 unsigned pte_access, unsigned pte_pkey, 198 u64 access) 199 { 200 /* strip nested paging fault error codes */ 201 unsigned int pfec = access; 202 unsigned long rflags = static_call(kvm_x86_get_rflags)(vcpu); 203 204 /* 205 * For explicit supervisor accesses, SMAP is disabled if EFLAGS.AC = 1. 206 * For implicit supervisor accesses, SMAP cannot be overridden. 207 * 208 * SMAP works on supervisor accesses only, and not_smap can 209 * be set or not set when user access with neither has any bearing 210 * on the result. 211 * 212 * We put the SMAP checking bit in place of the PFERR_RSVD_MASK bit; 213 * this bit will always be zero in pfec, but it will be one in index 214 * if SMAP checks are being disabled. 215 */ 216 u64 implicit_access = access & PFERR_IMPLICIT_ACCESS; 217 bool not_smap = ((rflags & X86_EFLAGS_AC) | implicit_access) == X86_EFLAGS_AC; 218 int index = (pfec | (not_smap ? PFERR_RSVD_MASK : 0)) >> 1; 219 u32 errcode = PFERR_PRESENT_MASK; 220 bool fault; 221 222 kvm_mmu_refresh_passthrough_bits(vcpu, mmu); 223 224 fault = (mmu->permissions[index] >> pte_access) & 1; 225 226 WARN_ON(pfec & (PFERR_PK_MASK | PFERR_RSVD_MASK)); 227 if (unlikely(mmu->pkru_mask)) { 228 u32 pkru_bits, offset; 229 230 /* 231 * PKRU defines 32 bits, there are 16 domains and 2 232 * attribute bits per domain in pkru. pte_pkey is the 233 * index of the protection domain, so pte_pkey * 2 is 234 * is the index of the first bit for the domain. 235 */ 236 pkru_bits = (vcpu->arch.pkru >> (pte_pkey * 2)) & 3; 237 238 /* clear present bit, replace PFEC.RSVD with ACC_USER_MASK. */ 239 offset = (pfec & ~1) | ((pte_access & PT_USER_MASK) ? PFERR_RSVD_MASK : 0); 240 241 pkru_bits &= mmu->pkru_mask >> offset; 242 errcode |= -pkru_bits & PFERR_PK_MASK; 243 fault |= (pkru_bits != 0); 244 } 245 246 return -(u32)fault & errcode; 247 } 248 249 bool __kvm_mmu_honors_guest_mtrrs(bool vm_has_noncoherent_dma); 250 251 static inline bool kvm_mmu_honors_guest_mtrrs(struct kvm *kvm) 252 { 253 return __kvm_mmu_honors_guest_mtrrs(kvm_arch_has_noncoherent_dma(kvm)); 254 } 255 256 void kvm_zap_gfn_range(struct kvm *kvm, gfn_t gfn_start, gfn_t gfn_end); 257 258 int kvm_arch_write_log_dirty(struct kvm_vcpu *vcpu); 259 260 int kvm_mmu_post_init_vm(struct kvm *kvm); 261 void kvm_mmu_pre_destroy_vm(struct kvm *kvm); 262 263 static inline bool kvm_shadow_root_allocated(struct kvm *kvm) 264 { 265 /* 266 * Read shadow_root_allocated before related pointers. Hence, threads 267 * reading shadow_root_allocated in any lock context are guaranteed to 268 * see the pointers. Pairs with smp_store_release in 269 * mmu_first_shadow_root_alloc. 270 */ 271 return smp_load_acquire(&kvm->arch.shadow_root_allocated); 272 } 273 274 #ifdef CONFIG_X86_64 275 extern bool tdp_mmu_enabled; 276 #else 277 #define tdp_mmu_enabled false 278 #endif 279 280 static inline bool kvm_memslots_have_rmaps(struct kvm *kvm) 281 { 282 return !tdp_mmu_enabled || kvm_shadow_root_allocated(kvm); 283 } 284 285 static inline gfn_t gfn_to_index(gfn_t gfn, gfn_t base_gfn, int level) 286 { 287 /* KVM_HPAGE_GFN_SHIFT(PG_LEVEL_4K) must be 0. */ 288 return (gfn >> KVM_HPAGE_GFN_SHIFT(level)) - 289 (base_gfn >> KVM_HPAGE_GFN_SHIFT(level)); 290 } 291 292 static inline unsigned long 293 __kvm_mmu_slot_lpages(struct kvm_memory_slot *slot, unsigned long npages, 294 int level) 295 { 296 return gfn_to_index(slot->base_gfn + npages - 1, 297 slot->base_gfn, level) + 1; 298 } 299 300 static inline unsigned long 301 kvm_mmu_slot_lpages(struct kvm_memory_slot *slot, int level) 302 { 303 return __kvm_mmu_slot_lpages(slot, slot->npages, level); 304 } 305 306 static inline void kvm_update_page_stats(struct kvm *kvm, int level, int count) 307 { 308 atomic64_add(count, &kvm->stat.pages[level - 1]); 309 } 310 311 gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u64 access, 312 struct x86_exception *exception); 313 314 static inline gpa_t kvm_translate_gpa(struct kvm_vcpu *vcpu, 315 struct kvm_mmu *mmu, 316 gpa_t gpa, u64 access, 317 struct x86_exception *exception) 318 { 319 if (mmu != &vcpu->arch.nested_mmu) 320 return gpa; 321 return translate_nested_gpa(vcpu, gpa, access, exception); 322 } 323 #endif 324