1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef __KVM_X86_LAPIC_H 3 #define __KVM_X86_LAPIC_H 4 5 #include <kvm/iodev.h> 6 7 #include <linux/kvm_host.h> 8 9 #include "hyperv.h" 10 #include "smm.h" 11 12 #define KVM_APIC_INIT 0 13 #define KVM_APIC_SIPI 1 14 15 #define APIC_SHORT_MASK 0xc0000 16 #define APIC_DEST_NOSHORT 0x0 17 #define APIC_DEST_MASK 0x800 18 19 #define APIC_BUS_CYCLE_NS_DEFAULT 1 20 21 #define APIC_BROADCAST 0xFF 22 #define X2APIC_BROADCAST 0xFFFFFFFFul 23 24 enum lapic_mode { 25 LAPIC_MODE_DISABLED = 0, 26 LAPIC_MODE_INVALID = X2APIC_ENABLE, 27 LAPIC_MODE_XAPIC = MSR_IA32_APICBASE_ENABLE, 28 LAPIC_MODE_X2APIC = MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE, 29 }; 30 31 enum lapic_lvt_entry { 32 LVT_TIMER, 33 LVT_THERMAL_MONITOR, 34 LVT_PERFORMANCE_COUNTER, 35 LVT_LINT0, 36 LVT_LINT1, 37 LVT_ERROR, 38 LVT_CMCI, 39 40 KVM_APIC_MAX_NR_LVT_ENTRIES, 41 }; 42 43 #define APIC_LVTx(x) ((x) == LVT_CMCI ? APIC_LVTCMCI : APIC_LVTT + 0x10 * (x)) 44 45 struct kvm_timer { 46 struct hrtimer timer; 47 s64 period; /* unit: ns */ 48 ktime_t target_expiration; 49 u32 timer_mode; 50 u32 timer_mode_mask; 51 u64 tscdeadline; 52 u64 expired_tscdeadline; 53 u32 timer_advance_ns; 54 atomic_t pending; /* accumulated triggered timers */ 55 bool hv_timer_in_use; 56 }; 57 58 struct kvm_lapic { 59 unsigned long base_address; 60 struct kvm_io_device dev; 61 struct kvm_timer lapic_timer; 62 u32 divide_count; 63 struct kvm_vcpu *vcpu; 64 bool apicv_active; 65 bool sw_enabled; 66 bool irr_pending; 67 bool lvt0_in_nmi_mode; 68 /* Number of bits set in ISR. */ 69 s16 isr_count; 70 /* The highest vector set in ISR; if -1 - invalid, must scan ISR. */ 71 int highest_isr_cache; 72 /** 73 * APIC register page. The layout matches the register layout seen by 74 * the guest 1:1, because it is accessed by the vmx microcode. 75 * Note: Only one register, the TPR, is used by the microcode. 76 */ 77 void *regs; 78 gpa_t vapic_addr; 79 struct gfn_to_hva_cache vapic_cache; 80 unsigned long pending_events; 81 unsigned int sipi_vector; 82 int nr_lvt_entries; 83 }; 84 85 struct dest_map; 86 87 int kvm_create_lapic(struct kvm_vcpu *vcpu); 88 void kvm_free_lapic(struct kvm_vcpu *vcpu); 89 90 int kvm_apic_has_interrupt(struct kvm_vcpu *vcpu); 91 void kvm_apic_ack_interrupt(struct kvm_vcpu *vcpu, int vector); 92 int kvm_apic_accept_pic_intr(struct kvm_vcpu *vcpu); 93 int kvm_apic_accept_events(struct kvm_vcpu *vcpu); 94 void kvm_lapic_reset(struct kvm_vcpu *vcpu, bool init_event); 95 u64 kvm_lapic_get_cr8(struct kvm_vcpu *vcpu); 96 void kvm_lapic_set_tpr(struct kvm_vcpu *vcpu, unsigned long cr8); 97 void kvm_lapic_set_eoi(struct kvm_vcpu *vcpu); 98 void kvm_apic_set_version(struct kvm_vcpu *vcpu); 99 void kvm_apic_after_set_mcg_cap(struct kvm_vcpu *vcpu); 100 bool kvm_apic_match_dest(struct kvm_vcpu *vcpu, struct kvm_lapic *source, 101 int shorthand, unsigned int dest, int dest_mode); 102 int kvm_apic_compare_prio(struct kvm_vcpu *vcpu1, struct kvm_vcpu *vcpu2); 103 void kvm_apic_clear_irr(struct kvm_vcpu *vcpu, int vec); 104 bool __kvm_apic_update_irr(u32 *pir, void *regs, int *max_irr); 105 bool kvm_apic_update_irr(struct kvm_vcpu *vcpu, u32 *pir, int *max_irr); 106 void kvm_apic_update_ppr(struct kvm_vcpu *vcpu); 107 int kvm_apic_set_irq(struct kvm_vcpu *vcpu, struct kvm_lapic_irq *irq, 108 struct dest_map *dest_map); 109 int kvm_apic_local_deliver(struct kvm_lapic *apic, int lvt_type); 110 void kvm_apic_update_apicv(struct kvm_vcpu *vcpu); 111 int kvm_alloc_apic_access_page(struct kvm *kvm); 112 void kvm_inhibit_apic_access_page(struct kvm_vcpu *vcpu); 113 114 bool kvm_irq_delivery_to_apic_fast(struct kvm *kvm, struct kvm_lapic *src, 115 struct kvm_lapic_irq *irq, int *r, struct dest_map *dest_map); 116 void kvm_apic_send_ipi(struct kvm_lapic *apic, u32 icr_low, u32 icr_high); 117 118 int kvm_apic_set_base(struct kvm_vcpu *vcpu, u64 value, bool host_initiated); 119 int kvm_apic_get_state(struct kvm_vcpu *vcpu, struct kvm_lapic_state *s); 120 int kvm_apic_set_state(struct kvm_vcpu *vcpu, struct kvm_lapic_state *s); 121 int kvm_lapic_find_highest_irr(struct kvm_vcpu *vcpu); 122 123 u64 kvm_get_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu); 124 void kvm_set_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu, u64 data); 125 126 void kvm_apic_write_nodecode(struct kvm_vcpu *vcpu, u32 offset); 127 void kvm_apic_set_eoi_accelerated(struct kvm_vcpu *vcpu, int vector); 128 129 int kvm_lapic_set_vapic_addr(struct kvm_vcpu *vcpu, gpa_t vapic_addr); 130 void kvm_lapic_sync_from_vapic(struct kvm_vcpu *vcpu); 131 void kvm_lapic_sync_to_vapic(struct kvm_vcpu *vcpu); 132 133 int kvm_x2apic_icr_write(struct kvm_lapic *apic, u64 data); 134 int kvm_x2apic_msr_write(struct kvm_vcpu *vcpu, u32 msr, u64 data); 135 int kvm_x2apic_msr_read(struct kvm_vcpu *vcpu, u32 msr, u64 *data); 136 137 int kvm_hv_vapic_msr_write(struct kvm_vcpu *vcpu, u32 msr, u64 data); 138 int kvm_hv_vapic_msr_read(struct kvm_vcpu *vcpu, u32 msr, u64 *data); 139 140 int kvm_lapic_set_pv_eoi(struct kvm_vcpu *vcpu, u64 data, unsigned long len); 141 void kvm_lapic_exit(void); 142 143 u64 kvm_lapic_readable_reg_mask(struct kvm_lapic *apic); 144 145 #define VEC_POS(v) ((v) & (32 - 1)) 146 #define REG_POS(v) (((v) >> 5) << 4) 147 148 static inline void kvm_lapic_clear_vector(int vec, void *bitmap) 149 { 150 clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec)); 151 } 152 153 static inline void kvm_lapic_set_vector(int vec, void *bitmap) 154 { 155 set_bit(VEC_POS(vec), (bitmap) + REG_POS(vec)); 156 } 157 158 static inline void kvm_lapic_set_irr(int vec, struct kvm_lapic *apic) 159 { 160 kvm_lapic_set_vector(vec, apic->regs + APIC_IRR); 161 /* 162 * irr_pending must be true if any interrupt is pending; set it after 163 * APIC_IRR to avoid race with apic_clear_irr 164 */ 165 apic->irr_pending = true; 166 } 167 168 static inline u32 __kvm_lapic_get_reg(char *regs, int reg_off) 169 { 170 return *((u32 *) (regs + reg_off)); 171 } 172 173 static inline u32 kvm_lapic_get_reg(struct kvm_lapic *apic, int reg_off) 174 { 175 return __kvm_lapic_get_reg(apic->regs, reg_off); 176 } 177 178 DECLARE_STATIC_KEY_FALSE(kvm_has_noapic_vcpu); 179 180 static inline bool lapic_in_kernel(struct kvm_vcpu *vcpu) 181 { 182 if (static_branch_unlikely(&kvm_has_noapic_vcpu)) 183 return vcpu->arch.apic; 184 return true; 185 } 186 187 extern struct static_key_false_deferred apic_hw_disabled; 188 189 static inline bool kvm_apic_hw_enabled(struct kvm_lapic *apic) 190 { 191 if (static_branch_unlikely(&apic_hw_disabled.key)) 192 return apic->vcpu->arch.apic_base & MSR_IA32_APICBASE_ENABLE; 193 return true; 194 } 195 196 extern struct static_key_false_deferred apic_sw_disabled; 197 198 static inline bool kvm_apic_sw_enabled(struct kvm_lapic *apic) 199 { 200 if (static_branch_unlikely(&apic_sw_disabled.key)) 201 return apic->sw_enabled; 202 return true; 203 } 204 205 static inline bool kvm_apic_present(struct kvm_vcpu *vcpu) 206 { 207 return lapic_in_kernel(vcpu) && kvm_apic_hw_enabled(vcpu->arch.apic); 208 } 209 210 static inline int kvm_lapic_enabled(struct kvm_vcpu *vcpu) 211 { 212 return kvm_apic_present(vcpu) && kvm_apic_sw_enabled(vcpu->arch.apic); 213 } 214 215 static inline int apic_x2apic_mode(struct kvm_lapic *apic) 216 { 217 return apic->vcpu->arch.apic_base & X2APIC_ENABLE; 218 } 219 220 static inline bool kvm_vcpu_apicv_active(struct kvm_vcpu *vcpu) 221 { 222 return lapic_in_kernel(vcpu) && vcpu->arch.apic->apicv_active; 223 } 224 225 static inline bool kvm_apic_has_pending_init_or_sipi(struct kvm_vcpu *vcpu) 226 { 227 return lapic_in_kernel(vcpu) && vcpu->arch.apic->pending_events; 228 } 229 230 static inline bool kvm_apic_init_sipi_allowed(struct kvm_vcpu *vcpu) 231 { 232 return !is_smm(vcpu) && 233 !kvm_x86_call(apic_init_signal_blocked)(vcpu); 234 } 235 236 static inline bool kvm_lowest_prio_delivery(struct kvm_lapic_irq *irq) 237 { 238 return (irq->delivery_mode == APIC_DM_LOWEST || 239 irq->msi_redir_hint); 240 } 241 242 static inline int kvm_lapic_latched_init(struct kvm_vcpu *vcpu) 243 { 244 return lapic_in_kernel(vcpu) && test_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events); 245 } 246 247 bool kvm_apic_pending_eoi(struct kvm_vcpu *vcpu, int vector); 248 249 void kvm_wait_lapic_expire(struct kvm_vcpu *vcpu); 250 251 void kvm_bitmap_or_dest_vcpus(struct kvm *kvm, struct kvm_lapic_irq *irq, 252 unsigned long *vcpu_bitmap); 253 254 bool kvm_intr_is_single_vcpu_fast(struct kvm *kvm, struct kvm_lapic_irq *irq, 255 struct kvm_vcpu **dest_vcpu); 256 int kvm_vector_to_index(u32 vector, u32 dest_vcpus, 257 const unsigned long *bitmap, u32 bitmap_size); 258 void kvm_lapic_switch_to_sw_timer(struct kvm_vcpu *vcpu); 259 void kvm_lapic_switch_to_hv_timer(struct kvm_vcpu *vcpu); 260 void kvm_lapic_expired_hv_timer(struct kvm_vcpu *vcpu); 261 bool kvm_lapic_hv_timer_in_use(struct kvm_vcpu *vcpu); 262 void kvm_lapic_restart_hv_timer(struct kvm_vcpu *vcpu); 263 bool kvm_can_use_hv_timer(struct kvm_vcpu *vcpu); 264 265 static inline enum lapic_mode kvm_apic_mode(u64 apic_base) 266 { 267 return apic_base & (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE); 268 } 269 270 static inline enum lapic_mode kvm_get_apic_mode(struct kvm_vcpu *vcpu) 271 { 272 return kvm_apic_mode(vcpu->arch.apic_base); 273 } 274 275 static inline u8 kvm_xapic_id(struct kvm_lapic *apic) 276 { 277 return kvm_lapic_get_reg(apic, APIC_ID) >> 24; 278 } 279 280 #endif 281