1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef __KVM_X86_LAPIC_H 3 #define __KVM_X86_LAPIC_H 4 5 #include <kvm/iodev.h> 6 7 #include <linux/kvm_host.h> 8 9 #define KVM_APIC_INIT 0 10 #define KVM_APIC_SIPI 1 11 #define KVM_APIC_LVT_NUM 6 12 13 #define KVM_APIC_SHORT_MASK 0xc0000 14 #define KVM_APIC_DEST_MASK 0x800 15 16 #define APIC_BUS_CYCLE_NS 1 17 #define APIC_BUS_FREQUENCY (1000000000ULL / APIC_BUS_CYCLE_NS) 18 19 enum lapic_mode { 20 LAPIC_MODE_DISABLED = 0, 21 LAPIC_MODE_INVALID = X2APIC_ENABLE, 22 LAPIC_MODE_XAPIC = MSR_IA32_APICBASE_ENABLE, 23 LAPIC_MODE_X2APIC = MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE, 24 }; 25 26 struct kvm_timer { 27 struct hrtimer timer; 28 s64 period; /* unit: ns */ 29 ktime_t target_expiration; 30 u32 timer_mode; 31 u32 timer_mode_mask; 32 u64 tscdeadline; 33 u64 expired_tscdeadline; 34 atomic_t pending; /* accumulated triggered timers */ 35 bool hv_timer_in_use; 36 }; 37 38 struct kvm_lapic { 39 unsigned long base_address; 40 struct kvm_io_device dev; 41 struct kvm_timer lapic_timer; 42 u32 divide_count; 43 struct kvm_vcpu *vcpu; 44 bool sw_enabled; 45 bool irr_pending; 46 bool lvt0_in_nmi_mode; 47 /* Number of bits set in ISR. */ 48 s16 isr_count; 49 /* The highest vector set in ISR; if -1 - invalid, must scan ISR. */ 50 int highest_isr_cache; 51 /** 52 * APIC register page. The layout matches the register layout seen by 53 * the guest 1:1, because it is accessed by the vmx microcode. 54 * Note: Only one register, the TPR, is used by the microcode. 55 */ 56 void *regs; 57 gpa_t vapic_addr; 58 struct gfn_to_hva_cache vapic_cache; 59 unsigned long pending_events; 60 unsigned int sipi_vector; 61 }; 62 63 struct dest_map; 64 65 int kvm_create_lapic(struct kvm_vcpu *vcpu); 66 void kvm_free_lapic(struct kvm_vcpu *vcpu); 67 68 int kvm_apic_has_interrupt(struct kvm_vcpu *vcpu); 69 int kvm_apic_accept_pic_intr(struct kvm_vcpu *vcpu); 70 int kvm_get_apic_interrupt(struct kvm_vcpu *vcpu); 71 void kvm_apic_accept_events(struct kvm_vcpu *vcpu); 72 void kvm_lapic_reset(struct kvm_vcpu *vcpu, bool init_event); 73 u64 kvm_lapic_get_cr8(struct kvm_vcpu *vcpu); 74 void kvm_lapic_set_tpr(struct kvm_vcpu *vcpu, unsigned long cr8); 75 void kvm_lapic_set_eoi(struct kvm_vcpu *vcpu); 76 void kvm_lapic_set_base(struct kvm_vcpu *vcpu, u64 value); 77 u64 kvm_lapic_get_base(struct kvm_vcpu *vcpu); 78 void kvm_apic_set_version(struct kvm_vcpu *vcpu); 79 int kvm_lapic_reg_write(struct kvm_lapic *apic, u32 reg, u32 val); 80 int kvm_lapic_reg_read(struct kvm_lapic *apic, u32 offset, int len, 81 void *data); 82 bool kvm_apic_match_dest(struct kvm_vcpu *vcpu, struct kvm_lapic *source, 83 int short_hand, unsigned int dest, int dest_mode); 84 85 bool __kvm_apic_update_irr(u32 *pir, void *regs, int *max_irr); 86 bool kvm_apic_update_irr(struct kvm_vcpu *vcpu, u32 *pir, int *max_irr); 87 void kvm_apic_update_ppr(struct kvm_vcpu *vcpu); 88 int kvm_apic_set_irq(struct kvm_vcpu *vcpu, struct kvm_lapic_irq *irq, 89 struct dest_map *dest_map); 90 int kvm_apic_local_deliver(struct kvm_lapic *apic, int lvt_type); 91 92 bool kvm_irq_delivery_to_apic_fast(struct kvm *kvm, struct kvm_lapic *src, 93 struct kvm_lapic_irq *irq, int *r, struct dest_map *dest_map); 94 95 u64 kvm_get_apic_base(struct kvm_vcpu *vcpu); 96 int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info); 97 int kvm_apic_get_state(struct kvm_vcpu *vcpu, struct kvm_lapic_state *s); 98 int kvm_apic_set_state(struct kvm_vcpu *vcpu, struct kvm_lapic_state *s); 99 enum lapic_mode kvm_get_apic_mode(struct kvm_vcpu *vcpu); 100 int kvm_lapic_find_highest_irr(struct kvm_vcpu *vcpu); 101 102 u64 kvm_get_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu); 103 void kvm_set_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu, u64 data); 104 105 void kvm_apic_write_nodecode(struct kvm_vcpu *vcpu, u32 offset); 106 void kvm_apic_set_eoi_accelerated(struct kvm_vcpu *vcpu, int vector); 107 108 int kvm_lapic_set_vapic_addr(struct kvm_vcpu *vcpu, gpa_t vapic_addr); 109 void kvm_lapic_sync_from_vapic(struct kvm_vcpu *vcpu); 110 void kvm_lapic_sync_to_vapic(struct kvm_vcpu *vcpu); 111 112 int kvm_x2apic_msr_write(struct kvm_vcpu *vcpu, u32 msr, u64 data); 113 int kvm_x2apic_msr_read(struct kvm_vcpu *vcpu, u32 msr, u64 *data); 114 115 int kvm_hv_vapic_msr_write(struct kvm_vcpu *vcpu, u32 msr, u64 data); 116 int kvm_hv_vapic_msr_read(struct kvm_vcpu *vcpu, u32 msr, u64 *data); 117 118 static inline bool kvm_hv_vapic_assist_page_enabled(struct kvm_vcpu *vcpu) 119 { 120 return vcpu->arch.hyperv.hv_vapic & HV_X64_MSR_VP_ASSIST_PAGE_ENABLE; 121 } 122 123 int kvm_lapic_enable_pv_eoi(struct kvm_vcpu *vcpu, u64 data); 124 void kvm_lapic_init(void); 125 void kvm_lapic_exit(void); 126 127 #define VEC_POS(v) ((v) & (32 - 1)) 128 #define REG_POS(v) (((v) >> 5) << 4) 129 130 static inline void kvm_lapic_set_vector(int vec, void *bitmap) 131 { 132 set_bit(VEC_POS(vec), (bitmap) + REG_POS(vec)); 133 } 134 135 static inline void kvm_lapic_set_irr(int vec, struct kvm_lapic *apic) 136 { 137 kvm_lapic_set_vector(vec, apic->regs + APIC_IRR); 138 /* 139 * irr_pending must be true if any interrupt is pending; set it after 140 * APIC_IRR to avoid race with apic_clear_irr 141 */ 142 apic->irr_pending = true; 143 } 144 145 static inline u32 kvm_lapic_get_reg(struct kvm_lapic *apic, int reg_off) 146 { 147 return *((u32 *) (apic->regs + reg_off)); 148 } 149 150 static inline void kvm_lapic_set_reg(struct kvm_lapic *apic, int reg_off, u32 val) 151 { 152 *((u32 *) (apic->regs + reg_off)) = val; 153 } 154 155 extern struct static_key kvm_no_apic_vcpu; 156 157 static inline bool lapic_in_kernel(struct kvm_vcpu *vcpu) 158 { 159 if (static_key_false(&kvm_no_apic_vcpu)) 160 return vcpu->arch.apic; 161 return true; 162 } 163 164 extern struct static_key_deferred apic_hw_disabled; 165 166 static inline int kvm_apic_hw_enabled(struct kvm_lapic *apic) 167 { 168 if (static_key_false(&apic_hw_disabled.key)) 169 return apic->vcpu->arch.apic_base & MSR_IA32_APICBASE_ENABLE; 170 return MSR_IA32_APICBASE_ENABLE; 171 } 172 173 extern struct static_key_deferred apic_sw_disabled; 174 175 static inline bool kvm_apic_sw_enabled(struct kvm_lapic *apic) 176 { 177 if (static_key_false(&apic_sw_disabled.key)) 178 return apic->sw_enabled; 179 return true; 180 } 181 182 static inline bool kvm_apic_present(struct kvm_vcpu *vcpu) 183 { 184 return lapic_in_kernel(vcpu) && kvm_apic_hw_enabled(vcpu->arch.apic); 185 } 186 187 static inline int kvm_lapic_enabled(struct kvm_vcpu *vcpu) 188 { 189 return kvm_apic_present(vcpu) && kvm_apic_sw_enabled(vcpu->arch.apic); 190 } 191 192 static inline int apic_x2apic_mode(struct kvm_lapic *apic) 193 { 194 return apic->vcpu->arch.apic_base & X2APIC_ENABLE; 195 } 196 197 static inline bool kvm_vcpu_apicv_active(struct kvm_vcpu *vcpu) 198 { 199 return vcpu->arch.apic && vcpu->arch.apicv_active; 200 } 201 202 static inline bool kvm_apic_has_events(struct kvm_vcpu *vcpu) 203 { 204 return lapic_in_kernel(vcpu) && vcpu->arch.apic->pending_events; 205 } 206 207 static inline bool kvm_lowest_prio_delivery(struct kvm_lapic_irq *irq) 208 { 209 return (irq->delivery_mode == APIC_DM_LOWEST || 210 irq->msi_redir_hint); 211 } 212 213 static inline int kvm_lapic_latched_init(struct kvm_vcpu *vcpu) 214 { 215 return lapic_in_kernel(vcpu) && test_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events); 216 } 217 218 bool kvm_apic_pending_eoi(struct kvm_vcpu *vcpu, int vector); 219 220 void wait_lapic_expire(struct kvm_vcpu *vcpu); 221 222 bool kvm_intr_is_single_vcpu_fast(struct kvm *kvm, struct kvm_lapic_irq *irq, 223 struct kvm_vcpu **dest_vcpu); 224 int kvm_vector_to_index(u32 vector, u32 dest_vcpus, 225 const unsigned long *bitmap, u32 bitmap_size); 226 void kvm_lapic_switch_to_sw_timer(struct kvm_vcpu *vcpu); 227 void kvm_lapic_switch_to_hv_timer(struct kvm_vcpu *vcpu); 228 void kvm_lapic_expired_hv_timer(struct kvm_vcpu *vcpu); 229 bool kvm_lapic_hv_timer_in_use(struct kvm_vcpu *vcpu); 230 void kvm_lapic_restart_hv_timer(struct kvm_vcpu *vcpu); 231 232 static inline enum lapic_mode kvm_apic_mode(u64 apic_base) 233 { 234 return apic_base & (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE); 235 } 236 237 #endif 238