1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef __KVM_X86_LAPIC_H 3 #define __KVM_X86_LAPIC_H 4 5 #include <kvm/iodev.h> 6 7 #include <asm/apic.h> 8 9 #include <linux/kvm_host.h> 10 11 #include "hyperv.h" 12 #include "smm.h" 13 14 #define KVM_APIC_INIT 0 15 #define KVM_APIC_SIPI 1 16 17 #define APIC_SHORT_MASK 0xc0000 18 #define APIC_DEST_NOSHORT 0x0 19 #define APIC_DEST_MASK 0x800 20 21 #define APIC_BUS_CYCLE_NS_DEFAULT 1 22 23 #define APIC_BROADCAST 0xFF 24 #define X2APIC_BROADCAST 0xFFFFFFFFul 25 26 #define X2APIC_MSR(r) (APIC_BASE_MSR + ((r) >> 4)) 27 28 enum lapic_mode { 29 LAPIC_MODE_DISABLED = 0, 30 LAPIC_MODE_INVALID = X2APIC_ENABLE, 31 LAPIC_MODE_XAPIC = MSR_IA32_APICBASE_ENABLE, 32 LAPIC_MODE_X2APIC = MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE, 33 }; 34 35 /* 36 * Track the mode of the optimized logical map, as the rules for decoding the 37 * destination vary per mode. Enabling the optimized logical map requires all 38 * software-enabled local APIs to be in the same mode, each addressable APIC to 39 * be mapped to only one MDA, and each MDA to map to at most one APIC. 40 */ 41 enum kvm_apic_logical_mode { 42 /* All local APICs are software disabled. */ 43 KVM_APIC_MODE_SW_DISABLED, 44 /* All software enabled local APICs in xAPIC cluster addressing mode. */ 45 KVM_APIC_MODE_XAPIC_CLUSTER, 46 /* All software enabled local APICs in xAPIC flat addressing mode. */ 47 KVM_APIC_MODE_XAPIC_FLAT, 48 /* All software enabled local APICs in x2APIC mode. */ 49 KVM_APIC_MODE_X2APIC, 50 /* 51 * Optimized map disabled, e.g. not all local APICs in the same logical 52 * mode, same logical ID assigned to multiple APICs, etc. 53 */ 54 KVM_APIC_MODE_MAP_DISABLED, 55 }; 56 57 struct kvm_apic_map { 58 struct rcu_head rcu; 59 enum kvm_apic_logical_mode logical_mode; 60 u32 max_apic_id; 61 union { 62 struct kvm_lapic *xapic_flat_map[8]; 63 struct kvm_lapic *xapic_cluster_map[16][4]; 64 }; 65 struct kvm_lapic *phys_map[]; 66 }; 67 68 enum lapic_lvt_entry { 69 LVT_TIMER, 70 LVT_THERMAL_MONITOR, 71 LVT_PERFORMANCE_COUNTER, 72 LVT_LINT0, 73 LVT_LINT1, 74 LVT_ERROR, 75 LVT_CMCI, 76 77 KVM_APIC_MAX_NR_LVT_ENTRIES, 78 }; 79 80 #define APIC_LVTx(x) ((x) == LVT_CMCI ? APIC_LVTCMCI : APIC_LVTT + 0x10 * (x)) 81 82 struct kvm_timer { 83 struct hrtimer timer; 84 s64 period; /* unit: ns */ 85 ktime_t target_expiration; 86 u32 timer_mode; 87 u32 timer_mode_mask; 88 u64 tscdeadline; 89 u64 expired_tscdeadline; 90 u32 timer_advance_ns; 91 atomic_t pending; /* accumulated triggered timers */ 92 bool hv_timer_in_use; 93 }; 94 95 struct kvm_lapic { 96 unsigned long base_address; 97 struct kvm_io_device dev; 98 struct kvm_timer lapic_timer; 99 u32 divide_count; 100 struct kvm_vcpu *vcpu; 101 bool apicv_active; 102 bool sw_enabled; 103 bool irr_pending; 104 bool lvt0_in_nmi_mode; 105 /* Select registers in the vAPIC cannot be read/written. */ 106 bool guest_apic_protected; 107 /* Number of bits set in ISR. */ 108 s16 isr_count; 109 /* The highest vector set in ISR; if -1 - invalid, must scan ISR. */ 110 int highest_isr_cache; 111 /** 112 * APIC register page. The layout matches the register layout seen by 113 * the guest 1:1, because it is accessed by the vmx microcode. 114 * Note: Only one register, the TPR, is used by the microcode. 115 */ 116 void *regs; 117 gpa_t vapic_addr; 118 struct gfn_to_hva_cache vapic_cache; 119 unsigned long pending_events; 120 unsigned int sipi_vector; 121 int nr_lvt_entries; 122 }; 123 124 struct rtc_status; 125 126 int kvm_create_lapic(struct kvm_vcpu *vcpu); 127 void kvm_free_lapic(struct kvm_vcpu *vcpu); 128 129 int kvm_apic_has_interrupt(struct kvm_vcpu *vcpu); 130 void kvm_apic_ack_interrupt(struct kvm_vcpu *vcpu, int vector); 131 int kvm_apic_accept_pic_intr(struct kvm_vcpu *vcpu); 132 int kvm_apic_accept_events(struct kvm_vcpu *vcpu); 133 void kvm_lapic_reset(struct kvm_vcpu *vcpu, bool init_event); 134 u64 kvm_lapic_get_cr8(struct kvm_vcpu *vcpu); 135 void kvm_lapic_set_tpr(struct kvm_vcpu *vcpu, unsigned long cr8); 136 void kvm_lapic_update_cr8_intercept(struct kvm_vcpu *vcpu); 137 void kvm_lapic_set_eoi(struct kvm_vcpu *vcpu); 138 void kvm_apic_set_version(struct kvm_vcpu *vcpu); 139 void kvm_apic_after_set_mcg_cap(struct kvm_vcpu *vcpu); 140 bool kvm_apic_match_dest(struct kvm_vcpu *vcpu, struct kvm_lapic *source, 141 int shorthand, unsigned int dest, int dest_mode); 142 void kvm_apic_clear_irr(struct kvm_vcpu *vcpu, int vec); 143 bool __kvm_apic_update_irr(unsigned long *pir, void *regs, int *max_irr); 144 bool kvm_apic_update_irr(struct kvm_vcpu *vcpu, unsigned long *pir, int *max_irr); 145 void kvm_apic_update_ppr(struct kvm_vcpu *vcpu); 146 int kvm_apic_set_irq(struct kvm_vcpu *vcpu, struct kvm_lapic_irq *irq, 147 struct rtc_status *rtc_status); 148 int kvm_apic_local_deliver(struct kvm_lapic *apic, int lvt_type); 149 void kvm_apic_update_apicv(struct kvm_vcpu *vcpu); 150 int kvm_alloc_apic_access_page(struct kvm *kvm); 151 void kvm_inhibit_apic_access_page(struct kvm_vcpu *vcpu); 152 153 bool kvm_irq_delivery_to_apic_fast(struct kvm *kvm, struct kvm_lapic *src, 154 struct kvm_lapic_irq *irq, int *r); 155 int __kvm_irq_delivery_to_apic(struct kvm *kvm, struct kvm_lapic *src, 156 struct kvm_lapic_irq *irq, 157 struct rtc_status *rtc_status); 158 159 static inline int kvm_irq_delivery_to_apic(struct kvm *kvm, 160 struct kvm_lapic *src, 161 struct kvm_lapic_irq *irq) 162 { 163 return __kvm_irq_delivery_to_apic(kvm, src, irq, NULL); 164 } 165 166 void kvm_apic_send_ipi(struct kvm_lapic *apic, u32 icr_low, u32 icr_high); 167 int kvm_pv_send_ipi(struct kvm *kvm, unsigned long ipi_bitmap_low, 168 unsigned long ipi_bitmap_high, u32 min, 169 unsigned long icr, int op_64_bit); 170 171 int kvm_apic_set_base(struct kvm_vcpu *vcpu, u64 value, bool host_initiated); 172 int kvm_apic_get_state(struct kvm_vcpu *vcpu, struct kvm_lapic_state *s); 173 int kvm_apic_set_state(struct kvm_vcpu *vcpu, struct kvm_lapic_state *s); 174 int kvm_lapic_find_highest_irr(struct kvm_vcpu *vcpu); 175 176 u64 kvm_get_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu); 177 void kvm_set_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu, u64 data); 178 179 void kvm_apic_write_nodecode(struct kvm_vcpu *vcpu, u32 offset); 180 void kvm_apic_set_eoi_accelerated(struct kvm_vcpu *vcpu, int vector); 181 182 int kvm_lapic_set_vapic_addr(struct kvm_vcpu *vcpu, gpa_t vapic_addr); 183 void kvm_lapic_sync_from_vapic(struct kvm_vcpu *vcpu); 184 void kvm_lapic_sync_to_vapic(struct kvm_vcpu *vcpu); 185 186 int kvm_x2apic_icr_write_fast(struct kvm_lapic *apic, u64 data); 187 int kvm_x2apic_msr_write(struct kvm_vcpu *vcpu, u32 msr, u64 data); 188 int kvm_x2apic_msr_read(struct kvm_vcpu *vcpu, u32 msr, u64 *data); 189 190 int kvm_hv_vapic_msr_write(struct kvm_vcpu *vcpu, u32 msr, u64 data); 191 int kvm_hv_vapic_msr_read(struct kvm_vcpu *vcpu, u32 msr, u64 *data); 192 193 int kvm_lapic_set_pv_eoi(struct kvm_vcpu *vcpu, u64 data, unsigned long len); 194 void kvm_lapic_exit(void); 195 196 u64 kvm_x2apic_disable_read_intercept_reg_mask(struct kvm_vcpu *vcpu); 197 198 static inline void kvm_lapic_set_irr(int vec, struct kvm_lapic *apic) 199 { 200 apic_set_vector(vec, apic->regs + APIC_IRR); 201 /* 202 * irr_pending must be true if any interrupt is pending; set it after 203 * APIC_IRR to avoid race with apic_clear_irr 204 */ 205 apic->irr_pending = true; 206 } 207 208 static inline u32 kvm_lapic_get_reg(struct kvm_lapic *apic, int reg_off) 209 { 210 return apic_get_reg(apic->regs, reg_off); 211 } 212 213 DECLARE_STATIC_KEY_FALSE(kvm_has_noapic_vcpu); 214 215 static inline bool lapic_in_kernel(struct kvm_vcpu *vcpu) 216 { 217 if (static_branch_unlikely(&kvm_has_noapic_vcpu)) 218 return vcpu->arch.apic; 219 return true; 220 } 221 222 extern struct static_key_false_deferred apic_hw_disabled; 223 224 static inline bool kvm_apic_hw_enabled(struct kvm_lapic *apic) 225 { 226 if (static_branch_unlikely(&apic_hw_disabled.key)) 227 return apic->vcpu->arch.apic_base & MSR_IA32_APICBASE_ENABLE; 228 return true; 229 } 230 231 extern struct static_key_false_deferred apic_sw_disabled; 232 233 static inline bool kvm_apic_sw_enabled(struct kvm_lapic *apic) 234 { 235 if (static_branch_unlikely(&apic_sw_disabled.key)) 236 return apic->sw_enabled; 237 return true; 238 } 239 240 static inline bool kvm_apic_present(struct kvm_vcpu *vcpu) 241 { 242 return lapic_in_kernel(vcpu) && kvm_apic_hw_enabled(vcpu->arch.apic); 243 } 244 245 static inline int kvm_lapic_enabled(struct kvm_vcpu *vcpu) 246 { 247 return kvm_apic_present(vcpu) && kvm_apic_sw_enabled(vcpu->arch.apic); 248 } 249 250 static inline int apic_x2apic_mode(struct kvm_lapic *apic) 251 { 252 return apic->vcpu->arch.apic_base & X2APIC_ENABLE; 253 } 254 255 static inline bool kvm_vcpu_apicv_active(struct kvm_vcpu *vcpu) 256 { 257 return lapic_in_kernel(vcpu) && vcpu->arch.apic->apicv_active; 258 } 259 260 static inline bool kvm_apic_has_pending_init_or_sipi(struct kvm_vcpu *vcpu) 261 { 262 return lapic_in_kernel(vcpu) && vcpu->arch.apic->pending_events; 263 } 264 265 static inline bool kvm_apic_init_sipi_allowed(struct kvm_vcpu *vcpu) 266 { 267 return !is_smm(vcpu) && 268 !kvm_x86_call(apic_init_signal_blocked)(vcpu); 269 } 270 271 static inline int kvm_lapic_latched_init(struct kvm_vcpu *vcpu) 272 { 273 return lapic_in_kernel(vcpu) && test_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events); 274 } 275 276 static inline u16 kvm_lapic_irq_dest_mode(bool dest_mode_logical) 277 { 278 return dest_mode_logical ? APIC_DEST_LOGICAL : APIC_DEST_PHYSICAL; 279 } 280 281 bool kvm_apic_pending_eoi(struct kvm_vcpu *vcpu, int vector); 282 283 bool kvm_lapic_suppress_eoi_broadcast(struct kvm_lapic *apic); 284 285 void kvm_wait_lapic_expire(struct kvm_vcpu *vcpu); 286 287 void kvm_bitmap_or_dest_vcpus(struct kvm *kvm, struct kvm_lapic_irq *irq, 288 unsigned long *vcpu_bitmap); 289 290 bool kvm_intr_is_single_vcpu(struct kvm *kvm, struct kvm_lapic_irq *irq, 291 struct kvm_vcpu **dest_vcpu); 292 void kvm_lapic_switch_to_sw_timer(struct kvm_vcpu *vcpu); 293 void kvm_lapic_switch_to_hv_timer(struct kvm_vcpu *vcpu); 294 void kvm_lapic_expired_hv_timer(struct kvm_vcpu *vcpu); 295 bool kvm_lapic_hv_timer_in_use(struct kvm_vcpu *vcpu); 296 void kvm_lapic_restart_hv_timer(struct kvm_vcpu *vcpu); 297 298 static inline enum lapic_mode kvm_apic_mode(u64 apic_base) 299 { 300 return apic_base & (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE); 301 } 302 303 static inline enum lapic_mode kvm_get_apic_mode(struct kvm_vcpu *vcpu) 304 { 305 return kvm_apic_mode(vcpu->arch.apic_base); 306 } 307 308 static inline u8 kvm_xapic_id(struct kvm_lapic *apic) 309 { 310 return kvm_lapic_get_reg(apic, APIC_ID) >> 24; 311 } 312 313 #endif 314