1 2 /* 3 * Local APIC virtualization 4 * 5 * Copyright (C) 2006 Qumranet, Inc. 6 * Copyright (C) 2007 Novell 7 * Copyright (C) 2007 Intel 8 * Copyright 2009 Red Hat, Inc. and/or its affiliates. 9 * 10 * Authors: 11 * Dor Laor <dor.laor@qumranet.com> 12 * Gregory Haskins <ghaskins@novell.com> 13 * Yaozu (Eddie) Dong <eddie.dong@intel.com> 14 * 15 * Based on Xen 3.1 code, Copyright (c) 2004, Intel Corporation. 16 * 17 * This work is licensed under the terms of the GNU GPL, version 2. See 18 * the COPYING file in the top-level directory. 19 */ 20 21 #include <linux/kvm_host.h> 22 #include <linux/kvm.h> 23 #include <linux/mm.h> 24 #include <linux/highmem.h> 25 #include <linux/smp.h> 26 #include <linux/hrtimer.h> 27 #include <linux/io.h> 28 #include <linux/export.h> 29 #include <linux/math64.h> 30 #include <linux/slab.h> 31 #include <asm/processor.h> 32 #include <asm/msr.h> 33 #include <asm/page.h> 34 #include <asm/current.h> 35 #include <asm/apicdef.h> 36 #include <asm/delay.h> 37 #include <linux/atomic.h> 38 #include <linux/jump_label.h> 39 #include "kvm_cache_regs.h" 40 #include "irq.h" 41 #include "trace.h" 42 #include "x86.h" 43 #include "cpuid.h" 44 #include "hyperv.h" 45 46 #ifndef CONFIG_X86_64 47 #define mod_64(x, y) ((x) - (y) * div64_u64(x, y)) 48 #else 49 #define mod_64(x, y) ((x) % (y)) 50 #endif 51 52 #define PRId64 "d" 53 #define PRIx64 "llx" 54 #define PRIu64 "u" 55 #define PRIo64 "o" 56 57 /* #define apic_debug(fmt,arg...) printk(KERN_WARNING fmt,##arg) */ 58 #define apic_debug(fmt, arg...) 59 60 /* 14 is the version for Xeon and Pentium 8.4.8*/ 61 #define APIC_VERSION (0x14UL | ((KVM_APIC_LVT_NUM - 1) << 16)) 62 #define LAPIC_MMIO_LENGTH (1 << 12) 63 /* followed define is not in apicdef.h */ 64 #define APIC_SHORT_MASK 0xc0000 65 #define APIC_DEST_NOSHORT 0x0 66 #define APIC_DEST_MASK 0x800 67 #define MAX_APIC_VECTOR 256 68 #define APIC_VECTORS_PER_REG 32 69 70 #define APIC_BROADCAST 0xFF 71 #define X2APIC_BROADCAST 0xFFFFFFFFul 72 73 static inline int apic_test_vector(int vec, void *bitmap) 74 { 75 return test_bit(VEC_POS(vec), (bitmap) + REG_POS(vec)); 76 } 77 78 bool kvm_apic_pending_eoi(struct kvm_vcpu *vcpu, int vector) 79 { 80 struct kvm_lapic *apic = vcpu->arch.apic; 81 82 return apic_test_vector(vector, apic->regs + APIC_ISR) || 83 apic_test_vector(vector, apic->regs + APIC_IRR); 84 } 85 86 static inline void apic_clear_vector(int vec, void *bitmap) 87 { 88 clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec)); 89 } 90 91 static inline int __apic_test_and_set_vector(int vec, void *bitmap) 92 { 93 return __test_and_set_bit(VEC_POS(vec), (bitmap) + REG_POS(vec)); 94 } 95 96 static inline int __apic_test_and_clear_vector(int vec, void *bitmap) 97 { 98 return __test_and_clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec)); 99 } 100 101 struct static_key_deferred apic_hw_disabled __read_mostly; 102 struct static_key_deferred apic_sw_disabled __read_mostly; 103 104 static inline int apic_enabled(struct kvm_lapic *apic) 105 { 106 return kvm_apic_sw_enabled(apic) && kvm_apic_hw_enabled(apic); 107 } 108 109 #define LVT_MASK \ 110 (APIC_LVT_MASKED | APIC_SEND_PENDING | APIC_VECTOR_MASK) 111 112 #define LINT_MASK \ 113 (LVT_MASK | APIC_MODE_MASK | APIC_INPUT_POLARITY | \ 114 APIC_LVT_REMOTE_IRR | APIC_LVT_LEVEL_TRIGGER) 115 116 static inline u8 kvm_xapic_id(struct kvm_lapic *apic) 117 { 118 return kvm_lapic_get_reg(apic, APIC_ID) >> 24; 119 } 120 121 static inline u32 kvm_x2apic_id(struct kvm_lapic *apic) 122 { 123 return apic->vcpu->vcpu_id; 124 } 125 126 static inline bool kvm_apic_map_get_logical_dest(struct kvm_apic_map *map, 127 u32 dest_id, struct kvm_lapic ***cluster, u16 *mask) { 128 switch (map->mode) { 129 case KVM_APIC_MODE_X2APIC: { 130 u32 offset = (dest_id >> 16) * 16; 131 u32 max_apic_id = map->max_apic_id; 132 133 if (offset <= max_apic_id) { 134 u8 cluster_size = min(max_apic_id - offset + 1, 16U); 135 136 *cluster = &map->phys_map[offset]; 137 *mask = dest_id & (0xffff >> (16 - cluster_size)); 138 } else { 139 *mask = 0; 140 } 141 142 return true; 143 } 144 case KVM_APIC_MODE_XAPIC_FLAT: 145 *cluster = map->xapic_flat_map; 146 *mask = dest_id & 0xff; 147 return true; 148 case KVM_APIC_MODE_XAPIC_CLUSTER: 149 *cluster = map->xapic_cluster_map[(dest_id >> 4) & 0xf]; 150 *mask = dest_id & 0xf; 151 return true; 152 default: 153 /* Not optimized. */ 154 return false; 155 } 156 } 157 158 static void kvm_apic_map_free(struct rcu_head *rcu) 159 { 160 struct kvm_apic_map *map = container_of(rcu, struct kvm_apic_map, rcu); 161 162 kvfree(map); 163 } 164 165 static void recalculate_apic_map(struct kvm *kvm) 166 { 167 struct kvm_apic_map *new, *old = NULL; 168 struct kvm_vcpu *vcpu; 169 int i; 170 u32 max_id = 255; /* enough space for any xAPIC ID */ 171 172 mutex_lock(&kvm->arch.apic_map_lock); 173 174 kvm_for_each_vcpu(i, vcpu, kvm) 175 if (kvm_apic_present(vcpu)) 176 max_id = max(max_id, kvm_x2apic_id(vcpu->arch.apic)); 177 178 new = kvzalloc(sizeof(struct kvm_apic_map) + 179 sizeof(struct kvm_lapic *) * ((u64)max_id + 1), GFP_KERNEL); 180 181 if (!new) 182 goto out; 183 184 new->max_apic_id = max_id; 185 186 kvm_for_each_vcpu(i, vcpu, kvm) { 187 struct kvm_lapic *apic = vcpu->arch.apic; 188 struct kvm_lapic **cluster; 189 u16 mask; 190 u32 ldr; 191 u8 xapic_id; 192 u32 x2apic_id; 193 194 if (!kvm_apic_present(vcpu)) 195 continue; 196 197 xapic_id = kvm_xapic_id(apic); 198 x2apic_id = kvm_x2apic_id(apic); 199 200 /* Hotplug hack: see kvm_apic_match_physical_addr(), ... */ 201 if ((apic_x2apic_mode(apic) || x2apic_id > 0xff) && 202 x2apic_id <= new->max_apic_id) 203 new->phys_map[x2apic_id] = apic; 204 /* 205 * ... xAPIC ID of VCPUs with APIC ID > 0xff will wrap-around, 206 * prevent them from masking VCPUs with APIC ID <= 0xff. 207 */ 208 if (!apic_x2apic_mode(apic) && !new->phys_map[xapic_id]) 209 new->phys_map[xapic_id] = apic; 210 211 ldr = kvm_lapic_get_reg(apic, APIC_LDR); 212 213 if (apic_x2apic_mode(apic)) { 214 new->mode |= KVM_APIC_MODE_X2APIC; 215 } else if (ldr) { 216 ldr = GET_APIC_LOGICAL_ID(ldr); 217 if (kvm_lapic_get_reg(apic, APIC_DFR) == APIC_DFR_FLAT) 218 new->mode |= KVM_APIC_MODE_XAPIC_FLAT; 219 else 220 new->mode |= KVM_APIC_MODE_XAPIC_CLUSTER; 221 } 222 223 if (!kvm_apic_map_get_logical_dest(new, ldr, &cluster, &mask)) 224 continue; 225 226 if (mask) 227 cluster[ffs(mask) - 1] = apic; 228 } 229 out: 230 old = rcu_dereference_protected(kvm->arch.apic_map, 231 lockdep_is_held(&kvm->arch.apic_map_lock)); 232 rcu_assign_pointer(kvm->arch.apic_map, new); 233 mutex_unlock(&kvm->arch.apic_map_lock); 234 235 if (old) 236 call_rcu(&old->rcu, kvm_apic_map_free); 237 238 kvm_make_scan_ioapic_request(kvm); 239 } 240 241 static inline void apic_set_spiv(struct kvm_lapic *apic, u32 val) 242 { 243 bool enabled = val & APIC_SPIV_APIC_ENABLED; 244 245 kvm_lapic_set_reg(apic, APIC_SPIV, val); 246 247 if (enabled != apic->sw_enabled) { 248 apic->sw_enabled = enabled; 249 if (enabled) { 250 static_key_slow_dec_deferred(&apic_sw_disabled); 251 recalculate_apic_map(apic->vcpu->kvm); 252 } else 253 static_key_slow_inc(&apic_sw_disabled.key); 254 } 255 } 256 257 static inline void kvm_apic_set_xapic_id(struct kvm_lapic *apic, u8 id) 258 { 259 kvm_lapic_set_reg(apic, APIC_ID, id << 24); 260 recalculate_apic_map(apic->vcpu->kvm); 261 } 262 263 static inline void kvm_apic_set_ldr(struct kvm_lapic *apic, u32 id) 264 { 265 kvm_lapic_set_reg(apic, APIC_LDR, id); 266 recalculate_apic_map(apic->vcpu->kvm); 267 } 268 269 static inline void kvm_apic_set_x2apic_id(struct kvm_lapic *apic, u32 id) 270 { 271 u32 ldr = ((id >> 4) << 16) | (1 << (id & 0xf)); 272 273 WARN_ON_ONCE(id != apic->vcpu->vcpu_id); 274 275 kvm_lapic_set_reg(apic, APIC_ID, id); 276 kvm_lapic_set_reg(apic, APIC_LDR, ldr); 277 recalculate_apic_map(apic->vcpu->kvm); 278 } 279 280 static inline int apic_lvt_enabled(struct kvm_lapic *apic, int lvt_type) 281 { 282 return !(kvm_lapic_get_reg(apic, lvt_type) & APIC_LVT_MASKED); 283 } 284 285 static inline int apic_lvt_vector(struct kvm_lapic *apic, int lvt_type) 286 { 287 return kvm_lapic_get_reg(apic, lvt_type) & APIC_VECTOR_MASK; 288 } 289 290 static inline int apic_lvtt_oneshot(struct kvm_lapic *apic) 291 { 292 return apic->lapic_timer.timer_mode == APIC_LVT_TIMER_ONESHOT; 293 } 294 295 static inline int apic_lvtt_period(struct kvm_lapic *apic) 296 { 297 return apic->lapic_timer.timer_mode == APIC_LVT_TIMER_PERIODIC; 298 } 299 300 static inline int apic_lvtt_tscdeadline(struct kvm_lapic *apic) 301 { 302 return apic->lapic_timer.timer_mode == APIC_LVT_TIMER_TSCDEADLINE; 303 } 304 305 static inline int apic_lvt_nmi_mode(u32 lvt_val) 306 { 307 return (lvt_val & (APIC_MODE_MASK | APIC_LVT_MASKED)) == APIC_DM_NMI; 308 } 309 310 void kvm_apic_set_version(struct kvm_vcpu *vcpu) 311 { 312 struct kvm_lapic *apic = vcpu->arch.apic; 313 struct kvm_cpuid_entry2 *feat; 314 u32 v = APIC_VERSION; 315 316 if (!lapic_in_kernel(vcpu)) 317 return; 318 319 feat = kvm_find_cpuid_entry(apic->vcpu, 0x1, 0); 320 if (feat && (feat->ecx & (1 << (X86_FEATURE_X2APIC & 31)))) 321 v |= APIC_LVR_DIRECTED_EOI; 322 kvm_lapic_set_reg(apic, APIC_LVR, v); 323 } 324 325 static const unsigned int apic_lvt_mask[KVM_APIC_LVT_NUM] = { 326 LVT_MASK , /* part LVTT mask, timer mode mask added at runtime */ 327 LVT_MASK | APIC_MODE_MASK, /* LVTTHMR */ 328 LVT_MASK | APIC_MODE_MASK, /* LVTPC */ 329 LINT_MASK, LINT_MASK, /* LVT0-1 */ 330 LVT_MASK /* LVTERR */ 331 }; 332 333 static int find_highest_vector(void *bitmap) 334 { 335 int vec; 336 u32 *reg; 337 338 for (vec = MAX_APIC_VECTOR - APIC_VECTORS_PER_REG; 339 vec >= 0; vec -= APIC_VECTORS_PER_REG) { 340 reg = bitmap + REG_POS(vec); 341 if (*reg) 342 return __fls(*reg) + vec; 343 } 344 345 return -1; 346 } 347 348 static u8 count_vectors(void *bitmap) 349 { 350 int vec; 351 u32 *reg; 352 u8 count = 0; 353 354 for (vec = 0; vec < MAX_APIC_VECTOR; vec += APIC_VECTORS_PER_REG) { 355 reg = bitmap + REG_POS(vec); 356 count += hweight32(*reg); 357 } 358 359 return count; 360 } 361 362 int __kvm_apic_update_irr(u32 *pir, void *regs) 363 { 364 u32 i, vec; 365 u32 pir_val, irr_val; 366 int max_irr = -1; 367 368 for (i = vec = 0; i <= 7; i++, vec += 32) { 369 pir_val = READ_ONCE(pir[i]); 370 irr_val = *((u32 *)(regs + APIC_IRR + i * 0x10)); 371 if (pir_val) { 372 irr_val |= xchg(&pir[i], 0); 373 *((u32 *)(regs + APIC_IRR + i * 0x10)) = irr_val; 374 } 375 if (irr_val) 376 max_irr = __fls(irr_val) + vec; 377 } 378 379 return max_irr; 380 } 381 EXPORT_SYMBOL_GPL(__kvm_apic_update_irr); 382 383 int kvm_apic_update_irr(struct kvm_vcpu *vcpu, u32 *pir) 384 { 385 struct kvm_lapic *apic = vcpu->arch.apic; 386 387 return __kvm_apic_update_irr(pir, apic->regs); 388 } 389 EXPORT_SYMBOL_GPL(kvm_apic_update_irr); 390 391 static inline int apic_search_irr(struct kvm_lapic *apic) 392 { 393 return find_highest_vector(apic->regs + APIC_IRR); 394 } 395 396 static inline int apic_find_highest_irr(struct kvm_lapic *apic) 397 { 398 int result; 399 400 /* 401 * Note that irr_pending is just a hint. It will be always 402 * true with virtual interrupt delivery enabled. 403 */ 404 if (!apic->irr_pending) 405 return -1; 406 407 result = apic_search_irr(apic); 408 ASSERT(result == -1 || result >= 16); 409 410 return result; 411 } 412 413 static inline void apic_clear_irr(int vec, struct kvm_lapic *apic) 414 { 415 struct kvm_vcpu *vcpu; 416 417 vcpu = apic->vcpu; 418 419 if (unlikely(vcpu->arch.apicv_active)) { 420 /* need to update RVI */ 421 apic_clear_vector(vec, apic->regs + APIC_IRR); 422 kvm_x86_ops->hwapic_irr_update(vcpu, 423 apic_find_highest_irr(apic)); 424 } else { 425 apic->irr_pending = false; 426 apic_clear_vector(vec, apic->regs + APIC_IRR); 427 if (apic_search_irr(apic) != -1) 428 apic->irr_pending = true; 429 } 430 } 431 432 static inline void apic_set_isr(int vec, struct kvm_lapic *apic) 433 { 434 struct kvm_vcpu *vcpu; 435 436 if (__apic_test_and_set_vector(vec, apic->regs + APIC_ISR)) 437 return; 438 439 vcpu = apic->vcpu; 440 441 /* 442 * With APIC virtualization enabled, all caching is disabled 443 * because the processor can modify ISR under the hood. Instead 444 * just set SVI. 445 */ 446 if (unlikely(vcpu->arch.apicv_active)) 447 kvm_x86_ops->hwapic_isr_update(vcpu, vec); 448 else { 449 ++apic->isr_count; 450 BUG_ON(apic->isr_count > MAX_APIC_VECTOR); 451 /* 452 * ISR (in service register) bit is set when injecting an interrupt. 453 * The highest vector is injected. Thus the latest bit set matches 454 * the highest bit in ISR. 455 */ 456 apic->highest_isr_cache = vec; 457 } 458 } 459 460 static inline int apic_find_highest_isr(struct kvm_lapic *apic) 461 { 462 int result; 463 464 /* 465 * Note that isr_count is always 1, and highest_isr_cache 466 * is always -1, with APIC virtualization enabled. 467 */ 468 if (!apic->isr_count) 469 return -1; 470 if (likely(apic->highest_isr_cache != -1)) 471 return apic->highest_isr_cache; 472 473 result = find_highest_vector(apic->regs + APIC_ISR); 474 ASSERT(result == -1 || result >= 16); 475 476 return result; 477 } 478 479 static inline void apic_clear_isr(int vec, struct kvm_lapic *apic) 480 { 481 struct kvm_vcpu *vcpu; 482 if (!__apic_test_and_clear_vector(vec, apic->regs + APIC_ISR)) 483 return; 484 485 vcpu = apic->vcpu; 486 487 /* 488 * We do get here for APIC virtualization enabled if the guest 489 * uses the Hyper-V APIC enlightenment. In this case we may need 490 * to trigger a new interrupt delivery by writing the SVI field; 491 * on the other hand isr_count and highest_isr_cache are unused 492 * and must be left alone. 493 */ 494 if (unlikely(vcpu->arch.apicv_active)) 495 kvm_x86_ops->hwapic_isr_update(vcpu, 496 apic_find_highest_isr(apic)); 497 else { 498 --apic->isr_count; 499 BUG_ON(apic->isr_count < 0); 500 apic->highest_isr_cache = -1; 501 } 502 } 503 504 int kvm_lapic_find_highest_irr(struct kvm_vcpu *vcpu) 505 { 506 /* This may race with setting of irr in __apic_accept_irq() and 507 * value returned may be wrong, but kvm_vcpu_kick() in __apic_accept_irq 508 * will cause vmexit immediately and the value will be recalculated 509 * on the next vmentry. 510 */ 511 return apic_find_highest_irr(vcpu->arch.apic); 512 } 513 EXPORT_SYMBOL_GPL(kvm_lapic_find_highest_irr); 514 515 static int __apic_accept_irq(struct kvm_lapic *apic, int delivery_mode, 516 int vector, int level, int trig_mode, 517 struct dest_map *dest_map); 518 519 int kvm_apic_set_irq(struct kvm_vcpu *vcpu, struct kvm_lapic_irq *irq, 520 struct dest_map *dest_map) 521 { 522 struct kvm_lapic *apic = vcpu->arch.apic; 523 524 return __apic_accept_irq(apic, irq->delivery_mode, irq->vector, 525 irq->level, irq->trig_mode, dest_map); 526 } 527 528 static int pv_eoi_put_user(struct kvm_vcpu *vcpu, u8 val) 529 { 530 531 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.pv_eoi.data, &val, 532 sizeof(val)); 533 } 534 535 static int pv_eoi_get_user(struct kvm_vcpu *vcpu, u8 *val) 536 { 537 538 return kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.pv_eoi.data, val, 539 sizeof(*val)); 540 } 541 542 static inline bool pv_eoi_enabled(struct kvm_vcpu *vcpu) 543 { 544 return vcpu->arch.pv_eoi.msr_val & KVM_MSR_ENABLED; 545 } 546 547 static bool pv_eoi_get_pending(struct kvm_vcpu *vcpu) 548 { 549 u8 val; 550 if (pv_eoi_get_user(vcpu, &val) < 0) 551 apic_debug("Can't read EOI MSR value: 0x%llx\n", 552 (unsigned long long)vcpu->arch.pv_eoi.msr_val); 553 return val & 0x1; 554 } 555 556 static void pv_eoi_set_pending(struct kvm_vcpu *vcpu) 557 { 558 if (pv_eoi_put_user(vcpu, KVM_PV_EOI_ENABLED) < 0) { 559 apic_debug("Can't set EOI MSR value: 0x%llx\n", 560 (unsigned long long)vcpu->arch.pv_eoi.msr_val); 561 return; 562 } 563 __set_bit(KVM_APIC_PV_EOI_PENDING, &vcpu->arch.apic_attention); 564 } 565 566 static void pv_eoi_clr_pending(struct kvm_vcpu *vcpu) 567 { 568 if (pv_eoi_put_user(vcpu, KVM_PV_EOI_DISABLED) < 0) { 569 apic_debug("Can't clear EOI MSR value: 0x%llx\n", 570 (unsigned long long)vcpu->arch.pv_eoi.msr_val); 571 return; 572 } 573 __clear_bit(KVM_APIC_PV_EOI_PENDING, &vcpu->arch.apic_attention); 574 } 575 576 static int apic_has_interrupt_for_ppr(struct kvm_lapic *apic, u32 ppr) 577 { 578 int highest_irr; 579 if (kvm_x86_ops->sync_pir_to_irr && apic->vcpu->arch.apicv_active) 580 highest_irr = kvm_x86_ops->sync_pir_to_irr(apic->vcpu); 581 else 582 highest_irr = apic_find_highest_irr(apic); 583 if (highest_irr == -1 || (highest_irr & 0xF0) <= ppr) 584 return -1; 585 return highest_irr; 586 } 587 588 static bool __apic_update_ppr(struct kvm_lapic *apic, u32 *new_ppr) 589 { 590 u32 tpr, isrv, ppr, old_ppr; 591 int isr; 592 593 old_ppr = kvm_lapic_get_reg(apic, APIC_PROCPRI); 594 tpr = kvm_lapic_get_reg(apic, APIC_TASKPRI); 595 isr = apic_find_highest_isr(apic); 596 isrv = (isr != -1) ? isr : 0; 597 598 if ((tpr & 0xf0) >= (isrv & 0xf0)) 599 ppr = tpr & 0xff; 600 else 601 ppr = isrv & 0xf0; 602 603 apic_debug("vlapic %p, ppr 0x%x, isr 0x%x, isrv 0x%x", 604 apic, ppr, isr, isrv); 605 606 *new_ppr = ppr; 607 if (old_ppr != ppr) 608 kvm_lapic_set_reg(apic, APIC_PROCPRI, ppr); 609 610 return ppr < old_ppr; 611 } 612 613 static void apic_update_ppr(struct kvm_lapic *apic) 614 { 615 u32 ppr; 616 617 if (__apic_update_ppr(apic, &ppr) && 618 apic_has_interrupt_for_ppr(apic, ppr) != -1) 619 kvm_make_request(KVM_REQ_EVENT, apic->vcpu); 620 } 621 622 void kvm_apic_update_ppr(struct kvm_vcpu *vcpu) 623 { 624 apic_update_ppr(vcpu->arch.apic); 625 } 626 EXPORT_SYMBOL_GPL(kvm_apic_update_ppr); 627 628 static void apic_set_tpr(struct kvm_lapic *apic, u32 tpr) 629 { 630 kvm_lapic_set_reg(apic, APIC_TASKPRI, tpr); 631 apic_update_ppr(apic); 632 } 633 634 static bool kvm_apic_broadcast(struct kvm_lapic *apic, u32 mda) 635 { 636 return mda == (apic_x2apic_mode(apic) ? 637 X2APIC_BROADCAST : APIC_BROADCAST); 638 } 639 640 static bool kvm_apic_match_physical_addr(struct kvm_lapic *apic, u32 mda) 641 { 642 if (kvm_apic_broadcast(apic, mda)) 643 return true; 644 645 if (apic_x2apic_mode(apic)) 646 return mda == kvm_x2apic_id(apic); 647 648 /* 649 * Hotplug hack: Make LAPIC in xAPIC mode also accept interrupts as if 650 * it were in x2APIC mode. Hotplugged VCPUs start in xAPIC mode and 651 * this allows unique addressing of VCPUs with APIC ID over 0xff. 652 * The 0xff condition is needed because writeable xAPIC ID. 653 */ 654 if (kvm_x2apic_id(apic) > 0xff && mda == kvm_x2apic_id(apic)) 655 return true; 656 657 return mda == kvm_xapic_id(apic); 658 } 659 660 static bool kvm_apic_match_logical_addr(struct kvm_lapic *apic, u32 mda) 661 { 662 u32 logical_id; 663 664 if (kvm_apic_broadcast(apic, mda)) 665 return true; 666 667 logical_id = kvm_lapic_get_reg(apic, APIC_LDR); 668 669 if (apic_x2apic_mode(apic)) 670 return ((logical_id >> 16) == (mda >> 16)) 671 && (logical_id & mda & 0xffff) != 0; 672 673 logical_id = GET_APIC_LOGICAL_ID(logical_id); 674 675 switch (kvm_lapic_get_reg(apic, APIC_DFR)) { 676 case APIC_DFR_FLAT: 677 return (logical_id & mda) != 0; 678 case APIC_DFR_CLUSTER: 679 return ((logical_id >> 4) == (mda >> 4)) 680 && (logical_id & mda & 0xf) != 0; 681 default: 682 apic_debug("Bad DFR vcpu %d: %08x\n", 683 apic->vcpu->vcpu_id, kvm_lapic_get_reg(apic, APIC_DFR)); 684 return false; 685 } 686 } 687 688 /* The KVM local APIC implementation has two quirks: 689 * 690 * - Real hardware delivers interrupts destined to x2APIC ID > 0xff to LAPICs 691 * in xAPIC mode if the "destination & 0xff" matches its xAPIC ID. 692 * KVM doesn't do that aliasing. 693 * 694 * - in-kernel IOAPIC messages have to be delivered directly to 695 * x2APIC, because the kernel does not support interrupt remapping. 696 * In order to support broadcast without interrupt remapping, x2APIC 697 * rewrites the destination of non-IPI messages from APIC_BROADCAST 698 * to X2APIC_BROADCAST. 699 * 700 * The broadcast quirk can be disabled with KVM_CAP_X2APIC_API. This is 701 * important when userspace wants to use x2APIC-format MSIs, because 702 * APIC_BROADCAST (0xff) is a legal route for "cluster 0, CPUs 0-7". 703 */ 704 static u32 kvm_apic_mda(struct kvm_vcpu *vcpu, unsigned int dest_id, 705 struct kvm_lapic *source, struct kvm_lapic *target) 706 { 707 bool ipi = source != NULL; 708 709 if (!vcpu->kvm->arch.x2apic_broadcast_quirk_disabled && 710 !ipi && dest_id == APIC_BROADCAST && apic_x2apic_mode(target)) 711 return X2APIC_BROADCAST; 712 713 return dest_id; 714 } 715 716 bool kvm_apic_match_dest(struct kvm_vcpu *vcpu, struct kvm_lapic *source, 717 int short_hand, unsigned int dest, int dest_mode) 718 { 719 struct kvm_lapic *target = vcpu->arch.apic; 720 u32 mda = kvm_apic_mda(vcpu, dest, source, target); 721 722 apic_debug("target %p, source %p, dest 0x%x, " 723 "dest_mode 0x%x, short_hand 0x%x\n", 724 target, source, dest, dest_mode, short_hand); 725 726 ASSERT(target); 727 switch (short_hand) { 728 case APIC_DEST_NOSHORT: 729 if (dest_mode == APIC_DEST_PHYSICAL) 730 return kvm_apic_match_physical_addr(target, mda); 731 else 732 return kvm_apic_match_logical_addr(target, mda); 733 case APIC_DEST_SELF: 734 return target == source; 735 case APIC_DEST_ALLINC: 736 return true; 737 case APIC_DEST_ALLBUT: 738 return target != source; 739 default: 740 apic_debug("kvm: apic: Bad dest shorthand value %x\n", 741 short_hand); 742 return false; 743 } 744 } 745 EXPORT_SYMBOL_GPL(kvm_apic_match_dest); 746 747 int kvm_vector_to_index(u32 vector, u32 dest_vcpus, 748 const unsigned long *bitmap, u32 bitmap_size) 749 { 750 u32 mod; 751 int i, idx = -1; 752 753 mod = vector % dest_vcpus; 754 755 for (i = 0; i <= mod; i++) { 756 idx = find_next_bit(bitmap, bitmap_size, idx + 1); 757 BUG_ON(idx == bitmap_size); 758 } 759 760 return idx; 761 } 762 763 static void kvm_apic_disabled_lapic_found(struct kvm *kvm) 764 { 765 if (!kvm->arch.disabled_lapic_found) { 766 kvm->arch.disabled_lapic_found = true; 767 printk(KERN_INFO 768 "Disabled LAPIC found during irq injection\n"); 769 } 770 } 771 772 static bool kvm_apic_is_broadcast_dest(struct kvm *kvm, struct kvm_lapic **src, 773 struct kvm_lapic_irq *irq, struct kvm_apic_map *map) 774 { 775 if (kvm->arch.x2apic_broadcast_quirk_disabled) { 776 if ((irq->dest_id == APIC_BROADCAST && 777 map->mode != KVM_APIC_MODE_X2APIC)) 778 return true; 779 if (irq->dest_id == X2APIC_BROADCAST) 780 return true; 781 } else { 782 bool x2apic_ipi = src && *src && apic_x2apic_mode(*src); 783 if (irq->dest_id == (x2apic_ipi ? 784 X2APIC_BROADCAST : APIC_BROADCAST)) 785 return true; 786 } 787 788 return false; 789 } 790 791 /* Return true if the interrupt can be handled by using *bitmap as index mask 792 * for valid destinations in *dst array. 793 * Return false if kvm_apic_map_get_dest_lapic did nothing useful. 794 * Note: we may have zero kvm_lapic destinations when we return true, which 795 * means that the interrupt should be dropped. In this case, *bitmap would be 796 * zero and *dst undefined. 797 */ 798 static inline bool kvm_apic_map_get_dest_lapic(struct kvm *kvm, 799 struct kvm_lapic **src, struct kvm_lapic_irq *irq, 800 struct kvm_apic_map *map, struct kvm_lapic ***dst, 801 unsigned long *bitmap) 802 { 803 int i, lowest; 804 805 if (irq->shorthand == APIC_DEST_SELF && src) { 806 *dst = src; 807 *bitmap = 1; 808 return true; 809 } else if (irq->shorthand) 810 return false; 811 812 if (!map || kvm_apic_is_broadcast_dest(kvm, src, irq, map)) 813 return false; 814 815 if (irq->dest_mode == APIC_DEST_PHYSICAL) { 816 if (irq->dest_id > map->max_apic_id) { 817 *bitmap = 0; 818 } else { 819 *dst = &map->phys_map[irq->dest_id]; 820 *bitmap = 1; 821 } 822 return true; 823 } 824 825 *bitmap = 0; 826 if (!kvm_apic_map_get_logical_dest(map, irq->dest_id, dst, 827 (u16 *)bitmap)) 828 return false; 829 830 if (!kvm_lowest_prio_delivery(irq)) 831 return true; 832 833 if (!kvm_vector_hashing_enabled()) { 834 lowest = -1; 835 for_each_set_bit(i, bitmap, 16) { 836 if (!(*dst)[i]) 837 continue; 838 if (lowest < 0) 839 lowest = i; 840 else if (kvm_apic_compare_prio((*dst)[i]->vcpu, 841 (*dst)[lowest]->vcpu) < 0) 842 lowest = i; 843 } 844 } else { 845 if (!*bitmap) 846 return true; 847 848 lowest = kvm_vector_to_index(irq->vector, hweight16(*bitmap), 849 bitmap, 16); 850 851 if (!(*dst)[lowest]) { 852 kvm_apic_disabled_lapic_found(kvm); 853 *bitmap = 0; 854 return true; 855 } 856 } 857 858 *bitmap = (lowest >= 0) ? 1 << lowest : 0; 859 860 return true; 861 } 862 863 bool kvm_irq_delivery_to_apic_fast(struct kvm *kvm, struct kvm_lapic *src, 864 struct kvm_lapic_irq *irq, int *r, struct dest_map *dest_map) 865 { 866 struct kvm_apic_map *map; 867 unsigned long bitmap; 868 struct kvm_lapic **dst = NULL; 869 int i; 870 bool ret; 871 872 *r = -1; 873 874 if (irq->shorthand == APIC_DEST_SELF) { 875 *r = kvm_apic_set_irq(src->vcpu, irq, dest_map); 876 return true; 877 } 878 879 rcu_read_lock(); 880 map = rcu_dereference(kvm->arch.apic_map); 881 882 ret = kvm_apic_map_get_dest_lapic(kvm, &src, irq, map, &dst, &bitmap); 883 if (ret) 884 for_each_set_bit(i, &bitmap, 16) { 885 if (!dst[i]) 886 continue; 887 if (*r < 0) 888 *r = 0; 889 *r += kvm_apic_set_irq(dst[i]->vcpu, irq, dest_map); 890 } 891 892 rcu_read_unlock(); 893 return ret; 894 } 895 896 /* 897 * This routine tries to handler interrupts in posted mode, here is how 898 * it deals with different cases: 899 * - For single-destination interrupts, handle it in posted mode 900 * - Else if vector hashing is enabled and it is a lowest-priority 901 * interrupt, handle it in posted mode and use the following mechanism 902 * to find the destinaiton vCPU. 903 * 1. For lowest-priority interrupts, store all the possible 904 * destination vCPUs in an array. 905 * 2. Use "guest vector % max number of destination vCPUs" to find 906 * the right destination vCPU in the array for the lowest-priority 907 * interrupt. 908 * - Otherwise, use remapped mode to inject the interrupt. 909 */ 910 bool kvm_intr_is_single_vcpu_fast(struct kvm *kvm, struct kvm_lapic_irq *irq, 911 struct kvm_vcpu **dest_vcpu) 912 { 913 struct kvm_apic_map *map; 914 unsigned long bitmap; 915 struct kvm_lapic **dst = NULL; 916 bool ret = false; 917 918 if (irq->shorthand) 919 return false; 920 921 rcu_read_lock(); 922 map = rcu_dereference(kvm->arch.apic_map); 923 924 if (kvm_apic_map_get_dest_lapic(kvm, NULL, irq, map, &dst, &bitmap) && 925 hweight16(bitmap) == 1) { 926 unsigned long i = find_first_bit(&bitmap, 16); 927 928 if (dst[i]) { 929 *dest_vcpu = dst[i]->vcpu; 930 ret = true; 931 } 932 } 933 934 rcu_read_unlock(); 935 return ret; 936 } 937 938 /* 939 * Add a pending IRQ into lapic. 940 * Return 1 if successfully added and 0 if discarded. 941 */ 942 static int __apic_accept_irq(struct kvm_lapic *apic, int delivery_mode, 943 int vector, int level, int trig_mode, 944 struct dest_map *dest_map) 945 { 946 int result = 0; 947 struct kvm_vcpu *vcpu = apic->vcpu; 948 949 trace_kvm_apic_accept_irq(vcpu->vcpu_id, delivery_mode, 950 trig_mode, vector); 951 switch (delivery_mode) { 952 case APIC_DM_LOWEST: 953 vcpu->arch.apic_arb_prio++; 954 case APIC_DM_FIXED: 955 if (unlikely(trig_mode && !level)) 956 break; 957 958 /* FIXME add logic for vcpu on reset */ 959 if (unlikely(!apic_enabled(apic))) 960 break; 961 962 result = 1; 963 964 if (dest_map) { 965 __set_bit(vcpu->vcpu_id, dest_map->map); 966 dest_map->vectors[vcpu->vcpu_id] = vector; 967 } 968 969 if (apic_test_vector(vector, apic->regs + APIC_TMR) != !!trig_mode) { 970 if (trig_mode) 971 kvm_lapic_set_vector(vector, apic->regs + APIC_TMR); 972 else 973 apic_clear_vector(vector, apic->regs + APIC_TMR); 974 } 975 976 if (vcpu->arch.apicv_active) 977 kvm_x86_ops->deliver_posted_interrupt(vcpu, vector); 978 else { 979 kvm_lapic_set_irr(vector, apic); 980 981 kvm_make_request(KVM_REQ_EVENT, vcpu); 982 kvm_vcpu_kick(vcpu); 983 } 984 break; 985 986 case APIC_DM_REMRD: 987 result = 1; 988 vcpu->arch.pv.pv_unhalted = 1; 989 kvm_make_request(KVM_REQ_EVENT, vcpu); 990 kvm_vcpu_kick(vcpu); 991 break; 992 993 case APIC_DM_SMI: 994 result = 1; 995 kvm_make_request(KVM_REQ_SMI, vcpu); 996 kvm_vcpu_kick(vcpu); 997 break; 998 999 case APIC_DM_NMI: 1000 result = 1; 1001 kvm_inject_nmi(vcpu); 1002 kvm_vcpu_kick(vcpu); 1003 break; 1004 1005 case APIC_DM_INIT: 1006 if (!trig_mode || level) { 1007 result = 1; 1008 /* assumes that there are only KVM_APIC_INIT/SIPI */ 1009 apic->pending_events = (1UL << KVM_APIC_INIT); 1010 /* make sure pending_events is visible before sending 1011 * the request */ 1012 smp_wmb(); 1013 kvm_make_request(KVM_REQ_EVENT, vcpu); 1014 kvm_vcpu_kick(vcpu); 1015 } else { 1016 apic_debug("Ignoring de-assert INIT to vcpu %d\n", 1017 vcpu->vcpu_id); 1018 } 1019 break; 1020 1021 case APIC_DM_STARTUP: 1022 apic_debug("SIPI to vcpu %d vector 0x%02x\n", 1023 vcpu->vcpu_id, vector); 1024 result = 1; 1025 apic->sipi_vector = vector; 1026 /* make sure sipi_vector is visible for the receiver */ 1027 smp_wmb(); 1028 set_bit(KVM_APIC_SIPI, &apic->pending_events); 1029 kvm_make_request(KVM_REQ_EVENT, vcpu); 1030 kvm_vcpu_kick(vcpu); 1031 break; 1032 1033 case APIC_DM_EXTINT: 1034 /* 1035 * Should only be called by kvm_apic_local_deliver() with LVT0, 1036 * before NMI watchdog was enabled. Already handled by 1037 * kvm_apic_accept_pic_intr(). 1038 */ 1039 break; 1040 1041 default: 1042 printk(KERN_ERR "TODO: unsupported delivery mode %x\n", 1043 delivery_mode); 1044 break; 1045 } 1046 return result; 1047 } 1048 1049 int kvm_apic_compare_prio(struct kvm_vcpu *vcpu1, struct kvm_vcpu *vcpu2) 1050 { 1051 return vcpu1->arch.apic_arb_prio - vcpu2->arch.apic_arb_prio; 1052 } 1053 1054 static bool kvm_ioapic_handles_vector(struct kvm_lapic *apic, int vector) 1055 { 1056 return test_bit(vector, apic->vcpu->arch.ioapic_handled_vectors); 1057 } 1058 1059 static void kvm_ioapic_send_eoi(struct kvm_lapic *apic, int vector) 1060 { 1061 int trigger_mode; 1062 1063 /* Eoi the ioapic only if the ioapic doesn't own the vector. */ 1064 if (!kvm_ioapic_handles_vector(apic, vector)) 1065 return; 1066 1067 /* Request a KVM exit to inform the userspace IOAPIC. */ 1068 if (irqchip_split(apic->vcpu->kvm)) { 1069 apic->vcpu->arch.pending_ioapic_eoi = vector; 1070 kvm_make_request(KVM_REQ_IOAPIC_EOI_EXIT, apic->vcpu); 1071 return; 1072 } 1073 1074 if (apic_test_vector(vector, apic->regs + APIC_TMR)) 1075 trigger_mode = IOAPIC_LEVEL_TRIG; 1076 else 1077 trigger_mode = IOAPIC_EDGE_TRIG; 1078 1079 kvm_ioapic_update_eoi(apic->vcpu, vector, trigger_mode); 1080 } 1081 1082 static int apic_set_eoi(struct kvm_lapic *apic) 1083 { 1084 int vector = apic_find_highest_isr(apic); 1085 1086 trace_kvm_eoi(apic, vector); 1087 1088 /* 1089 * Not every write EOI will has corresponding ISR, 1090 * one example is when Kernel check timer on setup_IO_APIC 1091 */ 1092 if (vector == -1) 1093 return vector; 1094 1095 apic_clear_isr(vector, apic); 1096 apic_update_ppr(apic); 1097 1098 if (test_bit(vector, vcpu_to_synic(apic->vcpu)->vec_bitmap)) 1099 kvm_hv_synic_send_eoi(apic->vcpu, vector); 1100 1101 kvm_ioapic_send_eoi(apic, vector); 1102 kvm_make_request(KVM_REQ_EVENT, apic->vcpu); 1103 return vector; 1104 } 1105 1106 /* 1107 * this interface assumes a trap-like exit, which has already finished 1108 * desired side effect including vISR and vPPR update. 1109 */ 1110 void kvm_apic_set_eoi_accelerated(struct kvm_vcpu *vcpu, int vector) 1111 { 1112 struct kvm_lapic *apic = vcpu->arch.apic; 1113 1114 trace_kvm_eoi(apic, vector); 1115 1116 kvm_ioapic_send_eoi(apic, vector); 1117 kvm_make_request(KVM_REQ_EVENT, apic->vcpu); 1118 } 1119 EXPORT_SYMBOL_GPL(kvm_apic_set_eoi_accelerated); 1120 1121 static void apic_send_ipi(struct kvm_lapic *apic) 1122 { 1123 u32 icr_low = kvm_lapic_get_reg(apic, APIC_ICR); 1124 u32 icr_high = kvm_lapic_get_reg(apic, APIC_ICR2); 1125 struct kvm_lapic_irq irq; 1126 1127 irq.vector = icr_low & APIC_VECTOR_MASK; 1128 irq.delivery_mode = icr_low & APIC_MODE_MASK; 1129 irq.dest_mode = icr_low & APIC_DEST_MASK; 1130 irq.level = (icr_low & APIC_INT_ASSERT) != 0; 1131 irq.trig_mode = icr_low & APIC_INT_LEVELTRIG; 1132 irq.shorthand = icr_low & APIC_SHORT_MASK; 1133 irq.msi_redir_hint = false; 1134 if (apic_x2apic_mode(apic)) 1135 irq.dest_id = icr_high; 1136 else 1137 irq.dest_id = GET_APIC_DEST_FIELD(icr_high); 1138 1139 trace_kvm_apic_ipi(icr_low, irq.dest_id); 1140 1141 apic_debug("icr_high 0x%x, icr_low 0x%x, " 1142 "short_hand 0x%x, dest 0x%x, trig_mode 0x%x, level 0x%x, " 1143 "dest_mode 0x%x, delivery_mode 0x%x, vector 0x%x, " 1144 "msi_redir_hint 0x%x\n", 1145 icr_high, icr_low, irq.shorthand, irq.dest_id, 1146 irq.trig_mode, irq.level, irq.dest_mode, irq.delivery_mode, 1147 irq.vector, irq.msi_redir_hint); 1148 1149 kvm_irq_delivery_to_apic(apic->vcpu->kvm, apic, &irq, NULL); 1150 } 1151 1152 static u32 apic_get_tmcct(struct kvm_lapic *apic) 1153 { 1154 ktime_t remaining, now; 1155 s64 ns; 1156 u32 tmcct; 1157 1158 ASSERT(apic != NULL); 1159 1160 /* if initial count is 0, current count should also be 0 */ 1161 if (kvm_lapic_get_reg(apic, APIC_TMICT) == 0 || 1162 apic->lapic_timer.period == 0) 1163 return 0; 1164 1165 now = ktime_get(); 1166 remaining = ktime_sub(apic->lapic_timer.target_expiration, now); 1167 if (ktime_to_ns(remaining) < 0) 1168 remaining = 0; 1169 1170 ns = mod_64(ktime_to_ns(remaining), apic->lapic_timer.period); 1171 tmcct = div64_u64(ns, 1172 (APIC_BUS_CYCLE_NS * apic->divide_count)); 1173 1174 return tmcct; 1175 } 1176 1177 static void __report_tpr_access(struct kvm_lapic *apic, bool write) 1178 { 1179 struct kvm_vcpu *vcpu = apic->vcpu; 1180 struct kvm_run *run = vcpu->run; 1181 1182 kvm_make_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu); 1183 run->tpr_access.rip = kvm_rip_read(vcpu); 1184 run->tpr_access.is_write = write; 1185 } 1186 1187 static inline void report_tpr_access(struct kvm_lapic *apic, bool write) 1188 { 1189 if (apic->vcpu->arch.tpr_access_reporting) 1190 __report_tpr_access(apic, write); 1191 } 1192 1193 static u32 __apic_read(struct kvm_lapic *apic, unsigned int offset) 1194 { 1195 u32 val = 0; 1196 1197 if (offset >= LAPIC_MMIO_LENGTH) 1198 return 0; 1199 1200 switch (offset) { 1201 case APIC_ARBPRI: 1202 apic_debug("Access APIC ARBPRI register which is for P6\n"); 1203 break; 1204 1205 case APIC_TMCCT: /* Timer CCR */ 1206 if (apic_lvtt_tscdeadline(apic)) 1207 return 0; 1208 1209 val = apic_get_tmcct(apic); 1210 break; 1211 case APIC_PROCPRI: 1212 apic_update_ppr(apic); 1213 val = kvm_lapic_get_reg(apic, offset); 1214 break; 1215 case APIC_TASKPRI: 1216 report_tpr_access(apic, false); 1217 /* fall thru */ 1218 default: 1219 val = kvm_lapic_get_reg(apic, offset); 1220 break; 1221 } 1222 1223 return val; 1224 } 1225 1226 static inline struct kvm_lapic *to_lapic(struct kvm_io_device *dev) 1227 { 1228 return container_of(dev, struct kvm_lapic, dev); 1229 } 1230 1231 int kvm_lapic_reg_read(struct kvm_lapic *apic, u32 offset, int len, 1232 void *data) 1233 { 1234 unsigned char alignment = offset & 0xf; 1235 u32 result; 1236 /* this bitmask has a bit cleared for each reserved register */ 1237 static const u64 rmask = 0x43ff01ffffffe70cULL; 1238 1239 if ((alignment + len) > 4) { 1240 apic_debug("KVM_APIC_READ: alignment error %x %d\n", 1241 offset, len); 1242 return 1; 1243 } 1244 1245 if (offset > 0x3f0 || !(rmask & (1ULL << (offset >> 4)))) { 1246 apic_debug("KVM_APIC_READ: read reserved register %x\n", 1247 offset); 1248 return 1; 1249 } 1250 1251 result = __apic_read(apic, offset & ~0xf); 1252 1253 trace_kvm_apic_read(offset, result); 1254 1255 switch (len) { 1256 case 1: 1257 case 2: 1258 case 4: 1259 memcpy(data, (char *)&result + alignment, len); 1260 break; 1261 default: 1262 printk(KERN_ERR "Local APIC read with len = %x, " 1263 "should be 1,2, or 4 instead\n", len); 1264 break; 1265 } 1266 return 0; 1267 } 1268 EXPORT_SYMBOL_GPL(kvm_lapic_reg_read); 1269 1270 static int apic_mmio_in_range(struct kvm_lapic *apic, gpa_t addr) 1271 { 1272 return kvm_apic_hw_enabled(apic) && 1273 addr >= apic->base_address && 1274 addr < apic->base_address + LAPIC_MMIO_LENGTH; 1275 } 1276 1277 static int apic_mmio_read(struct kvm_vcpu *vcpu, struct kvm_io_device *this, 1278 gpa_t address, int len, void *data) 1279 { 1280 struct kvm_lapic *apic = to_lapic(this); 1281 u32 offset = address - apic->base_address; 1282 1283 if (!apic_mmio_in_range(apic, address)) 1284 return -EOPNOTSUPP; 1285 1286 kvm_lapic_reg_read(apic, offset, len, data); 1287 1288 return 0; 1289 } 1290 1291 static void update_divide_count(struct kvm_lapic *apic) 1292 { 1293 u32 tmp1, tmp2, tdcr; 1294 1295 tdcr = kvm_lapic_get_reg(apic, APIC_TDCR); 1296 tmp1 = tdcr & 0xf; 1297 tmp2 = ((tmp1 & 0x3) | ((tmp1 & 0x8) >> 1)) + 1; 1298 apic->divide_count = 0x1 << (tmp2 & 0x7); 1299 1300 apic_debug("timer divide count is 0x%x\n", 1301 apic->divide_count); 1302 } 1303 1304 static void limit_periodic_timer_frequency(struct kvm_lapic *apic) 1305 { 1306 /* 1307 * Do not allow the guest to program periodic timers with small 1308 * interval, since the hrtimers are not throttled by the host 1309 * scheduler. 1310 */ 1311 if (apic_lvtt_period(apic) && apic->lapic_timer.period) { 1312 s64 min_period = min_timer_period_us * 1000LL; 1313 1314 if (apic->lapic_timer.period < min_period) { 1315 pr_info_ratelimited( 1316 "kvm: vcpu %i: requested %lld ns " 1317 "lapic timer period limited to %lld ns\n", 1318 apic->vcpu->vcpu_id, 1319 apic->lapic_timer.period, min_period); 1320 apic->lapic_timer.period = min_period; 1321 } 1322 } 1323 } 1324 1325 static void apic_update_lvtt(struct kvm_lapic *apic) 1326 { 1327 u32 timer_mode = kvm_lapic_get_reg(apic, APIC_LVTT) & 1328 apic->lapic_timer.timer_mode_mask; 1329 1330 if (apic->lapic_timer.timer_mode != timer_mode) { 1331 if (apic_lvtt_tscdeadline(apic) != (timer_mode == 1332 APIC_LVT_TIMER_TSCDEADLINE)) { 1333 hrtimer_cancel(&apic->lapic_timer.timer); 1334 kvm_lapic_set_reg(apic, APIC_TMICT, 0); 1335 apic->lapic_timer.period = 0; 1336 apic->lapic_timer.tscdeadline = 0; 1337 } 1338 apic->lapic_timer.timer_mode = timer_mode; 1339 limit_periodic_timer_frequency(apic); 1340 } 1341 } 1342 1343 static void apic_timer_expired(struct kvm_lapic *apic) 1344 { 1345 struct kvm_vcpu *vcpu = apic->vcpu; 1346 struct swait_queue_head *q = &vcpu->wq; 1347 struct kvm_timer *ktimer = &apic->lapic_timer; 1348 1349 if (atomic_read(&apic->lapic_timer.pending)) 1350 return; 1351 1352 atomic_inc(&apic->lapic_timer.pending); 1353 kvm_set_pending_timer(vcpu); 1354 1355 /* 1356 * For x86, the atomic_inc() is serialized, thus 1357 * using swait_active() is safe. 1358 */ 1359 if (swait_active(q)) 1360 swake_up(q); 1361 1362 if (apic_lvtt_tscdeadline(apic)) 1363 ktimer->expired_tscdeadline = ktimer->tscdeadline; 1364 } 1365 1366 /* 1367 * On APICv, this test will cause a busy wait 1368 * during a higher-priority task. 1369 */ 1370 1371 static bool lapic_timer_int_injected(struct kvm_vcpu *vcpu) 1372 { 1373 struct kvm_lapic *apic = vcpu->arch.apic; 1374 u32 reg = kvm_lapic_get_reg(apic, APIC_LVTT); 1375 1376 if (kvm_apic_hw_enabled(apic)) { 1377 int vec = reg & APIC_VECTOR_MASK; 1378 void *bitmap = apic->regs + APIC_ISR; 1379 1380 if (vcpu->arch.apicv_active) 1381 bitmap = apic->regs + APIC_IRR; 1382 1383 if (apic_test_vector(vec, bitmap)) 1384 return true; 1385 } 1386 return false; 1387 } 1388 1389 void wait_lapic_expire(struct kvm_vcpu *vcpu) 1390 { 1391 struct kvm_lapic *apic = vcpu->arch.apic; 1392 u64 guest_tsc, tsc_deadline; 1393 1394 if (!lapic_in_kernel(vcpu)) 1395 return; 1396 1397 if (apic->lapic_timer.expired_tscdeadline == 0) 1398 return; 1399 1400 if (!lapic_timer_int_injected(vcpu)) 1401 return; 1402 1403 tsc_deadline = apic->lapic_timer.expired_tscdeadline; 1404 apic->lapic_timer.expired_tscdeadline = 0; 1405 guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc()); 1406 trace_kvm_wait_lapic_expire(vcpu->vcpu_id, guest_tsc - tsc_deadline); 1407 1408 /* __delay is delay_tsc whenever the hardware has TSC, thus always. */ 1409 if (guest_tsc < tsc_deadline) 1410 __delay(min(tsc_deadline - guest_tsc, 1411 nsec_to_cycles(vcpu, lapic_timer_advance_ns))); 1412 } 1413 1414 static void start_sw_tscdeadline(struct kvm_lapic *apic) 1415 { 1416 u64 guest_tsc, tscdeadline = apic->lapic_timer.tscdeadline; 1417 u64 ns = 0; 1418 ktime_t expire; 1419 struct kvm_vcpu *vcpu = apic->vcpu; 1420 unsigned long this_tsc_khz = vcpu->arch.virtual_tsc_khz; 1421 unsigned long flags; 1422 ktime_t now; 1423 1424 if (unlikely(!tscdeadline || !this_tsc_khz)) 1425 return; 1426 1427 local_irq_save(flags); 1428 1429 now = ktime_get(); 1430 guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc()); 1431 if (likely(tscdeadline > guest_tsc)) { 1432 ns = (tscdeadline - guest_tsc) * 1000000ULL; 1433 do_div(ns, this_tsc_khz); 1434 expire = ktime_add_ns(now, ns); 1435 expire = ktime_sub_ns(expire, lapic_timer_advance_ns); 1436 hrtimer_start(&apic->lapic_timer.timer, 1437 expire, HRTIMER_MODE_ABS_PINNED); 1438 } else 1439 apic_timer_expired(apic); 1440 1441 local_irq_restore(flags); 1442 } 1443 1444 static void start_sw_period(struct kvm_lapic *apic) 1445 { 1446 if (!apic->lapic_timer.period) 1447 return; 1448 1449 if (apic_lvtt_oneshot(apic) && 1450 ktime_after(ktime_get(), 1451 apic->lapic_timer.target_expiration)) { 1452 apic_timer_expired(apic); 1453 return; 1454 } 1455 1456 hrtimer_start(&apic->lapic_timer.timer, 1457 apic->lapic_timer.target_expiration, 1458 HRTIMER_MODE_ABS_PINNED); 1459 } 1460 1461 static void update_target_expiration(struct kvm_lapic *apic, uint32_t old_divisor) 1462 { 1463 ktime_t now, remaining; 1464 u64 ns_remaining_old, ns_remaining_new; 1465 1466 apic->lapic_timer.period = (u64)kvm_lapic_get_reg(apic, APIC_TMICT) 1467 * APIC_BUS_CYCLE_NS * apic->divide_count; 1468 limit_periodic_timer_frequency(apic); 1469 1470 now = ktime_get(); 1471 remaining = ktime_sub(apic->lapic_timer.target_expiration, now); 1472 if (ktime_to_ns(remaining) < 0) 1473 remaining = 0; 1474 1475 ns_remaining_old = ktime_to_ns(remaining); 1476 ns_remaining_new = mul_u64_u32_div(ns_remaining_old, 1477 apic->divide_count, old_divisor); 1478 1479 apic->lapic_timer.tscdeadline += 1480 nsec_to_cycles(apic->vcpu, ns_remaining_new) - 1481 nsec_to_cycles(apic->vcpu, ns_remaining_old); 1482 apic->lapic_timer.target_expiration = ktime_add_ns(now, ns_remaining_new); 1483 } 1484 1485 static bool set_target_expiration(struct kvm_lapic *apic) 1486 { 1487 ktime_t now; 1488 u64 tscl = rdtsc(); 1489 1490 now = ktime_get(); 1491 apic->lapic_timer.period = (u64)kvm_lapic_get_reg(apic, APIC_TMICT) 1492 * APIC_BUS_CYCLE_NS * apic->divide_count; 1493 1494 if (!apic->lapic_timer.period) { 1495 apic->lapic_timer.tscdeadline = 0; 1496 return false; 1497 } 1498 1499 limit_periodic_timer_frequency(apic); 1500 1501 apic_debug("%s: bus cycle is %" PRId64 "ns, now 0x%016" 1502 PRIx64 ", " 1503 "timer initial count 0x%x, period %lldns, " 1504 "expire @ 0x%016" PRIx64 ".\n", __func__, 1505 APIC_BUS_CYCLE_NS, ktime_to_ns(now), 1506 kvm_lapic_get_reg(apic, APIC_TMICT), 1507 apic->lapic_timer.period, 1508 ktime_to_ns(ktime_add_ns(now, 1509 apic->lapic_timer.period))); 1510 1511 apic->lapic_timer.tscdeadline = kvm_read_l1_tsc(apic->vcpu, tscl) + 1512 nsec_to_cycles(apic->vcpu, apic->lapic_timer.period); 1513 apic->lapic_timer.target_expiration = ktime_add_ns(now, apic->lapic_timer.period); 1514 1515 return true; 1516 } 1517 1518 static void advance_periodic_target_expiration(struct kvm_lapic *apic) 1519 { 1520 apic->lapic_timer.tscdeadline += 1521 nsec_to_cycles(apic->vcpu, apic->lapic_timer.period); 1522 apic->lapic_timer.target_expiration = 1523 ktime_add_ns(apic->lapic_timer.target_expiration, 1524 apic->lapic_timer.period); 1525 } 1526 1527 bool kvm_lapic_hv_timer_in_use(struct kvm_vcpu *vcpu) 1528 { 1529 if (!lapic_in_kernel(vcpu)) 1530 return false; 1531 1532 return vcpu->arch.apic->lapic_timer.hv_timer_in_use; 1533 } 1534 EXPORT_SYMBOL_GPL(kvm_lapic_hv_timer_in_use); 1535 1536 static void cancel_hv_timer(struct kvm_lapic *apic) 1537 { 1538 WARN_ON(preemptible()); 1539 WARN_ON(!apic->lapic_timer.hv_timer_in_use); 1540 kvm_x86_ops->cancel_hv_timer(apic->vcpu); 1541 apic->lapic_timer.hv_timer_in_use = false; 1542 } 1543 1544 static bool start_hv_timer(struct kvm_lapic *apic) 1545 { 1546 struct kvm_timer *ktimer = &apic->lapic_timer; 1547 int r; 1548 1549 WARN_ON(preemptible()); 1550 if (!kvm_x86_ops->set_hv_timer) 1551 return false; 1552 1553 if (!apic_lvtt_period(apic) && atomic_read(&ktimer->pending)) 1554 return false; 1555 1556 if (!ktimer->tscdeadline) 1557 return false; 1558 1559 r = kvm_x86_ops->set_hv_timer(apic->vcpu, ktimer->tscdeadline); 1560 if (r < 0) 1561 return false; 1562 1563 ktimer->hv_timer_in_use = true; 1564 hrtimer_cancel(&ktimer->timer); 1565 1566 /* 1567 * Also recheck ktimer->pending, in case the sw timer triggered in 1568 * the window. For periodic timer, leave the hv timer running for 1569 * simplicity, and the deadline will be recomputed on the next vmexit. 1570 */ 1571 if (!apic_lvtt_period(apic) && (r || atomic_read(&ktimer->pending))) { 1572 if (r) 1573 apic_timer_expired(apic); 1574 return false; 1575 } 1576 1577 trace_kvm_hv_timer_state(apic->vcpu->vcpu_id, true); 1578 return true; 1579 } 1580 1581 static void start_sw_timer(struct kvm_lapic *apic) 1582 { 1583 struct kvm_timer *ktimer = &apic->lapic_timer; 1584 1585 WARN_ON(preemptible()); 1586 if (apic->lapic_timer.hv_timer_in_use) 1587 cancel_hv_timer(apic); 1588 if (!apic_lvtt_period(apic) && atomic_read(&ktimer->pending)) 1589 return; 1590 1591 if (apic_lvtt_period(apic) || apic_lvtt_oneshot(apic)) 1592 start_sw_period(apic); 1593 else if (apic_lvtt_tscdeadline(apic)) 1594 start_sw_tscdeadline(apic); 1595 trace_kvm_hv_timer_state(apic->vcpu->vcpu_id, false); 1596 } 1597 1598 static void restart_apic_timer(struct kvm_lapic *apic) 1599 { 1600 preempt_disable(); 1601 if (!start_hv_timer(apic)) 1602 start_sw_timer(apic); 1603 preempt_enable(); 1604 } 1605 1606 void kvm_lapic_expired_hv_timer(struct kvm_vcpu *vcpu) 1607 { 1608 struct kvm_lapic *apic = vcpu->arch.apic; 1609 1610 preempt_disable(); 1611 /* If the preempt notifier has already run, it also called apic_timer_expired */ 1612 if (!apic->lapic_timer.hv_timer_in_use) 1613 goto out; 1614 WARN_ON(swait_active(&vcpu->wq)); 1615 cancel_hv_timer(apic); 1616 apic_timer_expired(apic); 1617 1618 if (apic_lvtt_period(apic) && apic->lapic_timer.period) { 1619 advance_periodic_target_expiration(apic); 1620 restart_apic_timer(apic); 1621 } 1622 out: 1623 preempt_enable(); 1624 } 1625 EXPORT_SYMBOL_GPL(kvm_lapic_expired_hv_timer); 1626 1627 void kvm_lapic_switch_to_hv_timer(struct kvm_vcpu *vcpu) 1628 { 1629 restart_apic_timer(vcpu->arch.apic); 1630 } 1631 EXPORT_SYMBOL_GPL(kvm_lapic_switch_to_hv_timer); 1632 1633 void kvm_lapic_switch_to_sw_timer(struct kvm_vcpu *vcpu) 1634 { 1635 struct kvm_lapic *apic = vcpu->arch.apic; 1636 1637 preempt_disable(); 1638 /* Possibly the TSC deadline timer is not enabled yet */ 1639 if (apic->lapic_timer.hv_timer_in_use) 1640 start_sw_timer(apic); 1641 preempt_enable(); 1642 } 1643 EXPORT_SYMBOL_GPL(kvm_lapic_switch_to_sw_timer); 1644 1645 void kvm_lapic_restart_hv_timer(struct kvm_vcpu *vcpu) 1646 { 1647 struct kvm_lapic *apic = vcpu->arch.apic; 1648 1649 WARN_ON(!apic->lapic_timer.hv_timer_in_use); 1650 restart_apic_timer(apic); 1651 } 1652 1653 static void start_apic_timer(struct kvm_lapic *apic) 1654 { 1655 atomic_set(&apic->lapic_timer.pending, 0); 1656 1657 if ((apic_lvtt_period(apic) || apic_lvtt_oneshot(apic)) 1658 && !set_target_expiration(apic)) 1659 return; 1660 1661 restart_apic_timer(apic); 1662 } 1663 1664 static void apic_manage_nmi_watchdog(struct kvm_lapic *apic, u32 lvt0_val) 1665 { 1666 bool lvt0_in_nmi_mode = apic_lvt_nmi_mode(lvt0_val); 1667 1668 if (apic->lvt0_in_nmi_mode != lvt0_in_nmi_mode) { 1669 apic->lvt0_in_nmi_mode = lvt0_in_nmi_mode; 1670 if (lvt0_in_nmi_mode) { 1671 apic_debug("Receive NMI setting on APIC_LVT0 " 1672 "for cpu %d\n", apic->vcpu->vcpu_id); 1673 atomic_inc(&apic->vcpu->kvm->arch.vapics_in_nmi_mode); 1674 } else 1675 atomic_dec(&apic->vcpu->kvm->arch.vapics_in_nmi_mode); 1676 } 1677 } 1678 1679 int kvm_lapic_reg_write(struct kvm_lapic *apic, u32 reg, u32 val) 1680 { 1681 int ret = 0; 1682 1683 trace_kvm_apic_write(reg, val); 1684 1685 switch (reg) { 1686 case APIC_ID: /* Local APIC ID */ 1687 if (!apic_x2apic_mode(apic)) 1688 kvm_apic_set_xapic_id(apic, val >> 24); 1689 else 1690 ret = 1; 1691 break; 1692 1693 case APIC_TASKPRI: 1694 report_tpr_access(apic, true); 1695 apic_set_tpr(apic, val & 0xff); 1696 break; 1697 1698 case APIC_EOI: 1699 apic_set_eoi(apic); 1700 break; 1701 1702 case APIC_LDR: 1703 if (!apic_x2apic_mode(apic)) 1704 kvm_apic_set_ldr(apic, val & APIC_LDR_MASK); 1705 else 1706 ret = 1; 1707 break; 1708 1709 case APIC_DFR: 1710 if (!apic_x2apic_mode(apic)) { 1711 kvm_lapic_set_reg(apic, APIC_DFR, val | 0x0FFFFFFF); 1712 recalculate_apic_map(apic->vcpu->kvm); 1713 } else 1714 ret = 1; 1715 break; 1716 1717 case APIC_SPIV: { 1718 u32 mask = 0x3ff; 1719 if (kvm_lapic_get_reg(apic, APIC_LVR) & APIC_LVR_DIRECTED_EOI) 1720 mask |= APIC_SPIV_DIRECTED_EOI; 1721 apic_set_spiv(apic, val & mask); 1722 if (!(val & APIC_SPIV_APIC_ENABLED)) { 1723 int i; 1724 u32 lvt_val; 1725 1726 for (i = 0; i < KVM_APIC_LVT_NUM; i++) { 1727 lvt_val = kvm_lapic_get_reg(apic, 1728 APIC_LVTT + 0x10 * i); 1729 kvm_lapic_set_reg(apic, APIC_LVTT + 0x10 * i, 1730 lvt_val | APIC_LVT_MASKED); 1731 } 1732 apic_update_lvtt(apic); 1733 atomic_set(&apic->lapic_timer.pending, 0); 1734 1735 } 1736 break; 1737 } 1738 case APIC_ICR: 1739 /* No delay here, so we always clear the pending bit */ 1740 kvm_lapic_set_reg(apic, APIC_ICR, val & ~(1 << 12)); 1741 apic_send_ipi(apic); 1742 break; 1743 1744 case APIC_ICR2: 1745 if (!apic_x2apic_mode(apic)) 1746 val &= 0xff000000; 1747 kvm_lapic_set_reg(apic, APIC_ICR2, val); 1748 break; 1749 1750 case APIC_LVT0: 1751 apic_manage_nmi_watchdog(apic, val); 1752 case APIC_LVTTHMR: 1753 case APIC_LVTPC: 1754 case APIC_LVT1: 1755 case APIC_LVTERR: 1756 /* TODO: Check vector */ 1757 if (!kvm_apic_sw_enabled(apic)) 1758 val |= APIC_LVT_MASKED; 1759 1760 val &= apic_lvt_mask[(reg - APIC_LVTT) >> 4]; 1761 kvm_lapic_set_reg(apic, reg, val); 1762 1763 break; 1764 1765 case APIC_LVTT: 1766 if (!kvm_apic_sw_enabled(apic)) 1767 val |= APIC_LVT_MASKED; 1768 val &= (apic_lvt_mask[0] | apic->lapic_timer.timer_mode_mask); 1769 kvm_lapic_set_reg(apic, APIC_LVTT, val); 1770 apic_update_lvtt(apic); 1771 break; 1772 1773 case APIC_TMICT: 1774 if (apic_lvtt_tscdeadline(apic)) 1775 break; 1776 1777 hrtimer_cancel(&apic->lapic_timer.timer); 1778 kvm_lapic_set_reg(apic, APIC_TMICT, val); 1779 start_apic_timer(apic); 1780 break; 1781 1782 case APIC_TDCR: { 1783 uint32_t old_divisor = apic->divide_count; 1784 1785 if (val & 4) 1786 apic_debug("KVM_WRITE:TDCR %x\n", val); 1787 kvm_lapic_set_reg(apic, APIC_TDCR, val); 1788 update_divide_count(apic); 1789 if (apic->divide_count != old_divisor && 1790 apic->lapic_timer.period) { 1791 hrtimer_cancel(&apic->lapic_timer.timer); 1792 update_target_expiration(apic, old_divisor); 1793 restart_apic_timer(apic); 1794 } 1795 break; 1796 } 1797 case APIC_ESR: 1798 if (apic_x2apic_mode(apic) && val != 0) { 1799 apic_debug("KVM_WRITE:ESR not zero %x\n", val); 1800 ret = 1; 1801 } 1802 break; 1803 1804 case APIC_SELF_IPI: 1805 if (apic_x2apic_mode(apic)) { 1806 kvm_lapic_reg_write(apic, APIC_ICR, 0x40000 | (val & 0xff)); 1807 } else 1808 ret = 1; 1809 break; 1810 default: 1811 ret = 1; 1812 break; 1813 } 1814 if (ret) 1815 apic_debug("Local APIC Write to read-only register %x\n", reg); 1816 return ret; 1817 } 1818 EXPORT_SYMBOL_GPL(kvm_lapic_reg_write); 1819 1820 static int apic_mmio_write(struct kvm_vcpu *vcpu, struct kvm_io_device *this, 1821 gpa_t address, int len, const void *data) 1822 { 1823 struct kvm_lapic *apic = to_lapic(this); 1824 unsigned int offset = address - apic->base_address; 1825 u32 val; 1826 1827 if (!apic_mmio_in_range(apic, address)) 1828 return -EOPNOTSUPP; 1829 1830 /* 1831 * APIC register must be aligned on 128-bits boundary. 1832 * 32/64/128 bits registers must be accessed thru 32 bits. 1833 * Refer SDM 8.4.1 1834 */ 1835 if (len != 4 || (offset & 0xf)) { 1836 /* Don't shout loud, $infamous_os would cause only noise. */ 1837 apic_debug("apic write: bad size=%d %lx\n", len, (long)address); 1838 return 0; 1839 } 1840 1841 val = *(u32*)data; 1842 1843 /* too common printing */ 1844 if (offset != APIC_EOI) 1845 apic_debug("%s: offset 0x%x with length 0x%x, and value is " 1846 "0x%x\n", __func__, offset, len, val); 1847 1848 kvm_lapic_reg_write(apic, offset & 0xff0, val); 1849 1850 return 0; 1851 } 1852 1853 void kvm_lapic_set_eoi(struct kvm_vcpu *vcpu) 1854 { 1855 kvm_lapic_reg_write(vcpu->arch.apic, APIC_EOI, 0); 1856 } 1857 EXPORT_SYMBOL_GPL(kvm_lapic_set_eoi); 1858 1859 /* emulate APIC access in a trap manner */ 1860 void kvm_apic_write_nodecode(struct kvm_vcpu *vcpu, u32 offset) 1861 { 1862 u32 val = 0; 1863 1864 /* hw has done the conditional check and inst decode */ 1865 offset &= 0xff0; 1866 1867 kvm_lapic_reg_read(vcpu->arch.apic, offset, 4, &val); 1868 1869 /* TODO: optimize to just emulate side effect w/o one more write */ 1870 kvm_lapic_reg_write(vcpu->arch.apic, offset, val); 1871 } 1872 EXPORT_SYMBOL_GPL(kvm_apic_write_nodecode); 1873 1874 void kvm_free_lapic(struct kvm_vcpu *vcpu) 1875 { 1876 struct kvm_lapic *apic = vcpu->arch.apic; 1877 1878 if (!vcpu->arch.apic) 1879 return; 1880 1881 hrtimer_cancel(&apic->lapic_timer.timer); 1882 1883 if (!(vcpu->arch.apic_base & MSR_IA32_APICBASE_ENABLE)) 1884 static_key_slow_dec_deferred(&apic_hw_disabled); 1885 1886 if (!apic->sw_enabled) 1887 static_key_slow_dec_deferred(&apic_sw_disabled); 1888 1889 if (apic->regs) 1890 free_page((unsigned long)apic->regs); 1891 1892 kfree(apic); 1893 } 1894 1895 /* 1896 *---------------------------------------------------------------------- 1897 * LAPIC interface 1898 *---------------------------------------------------------------------- 1899 */ 1900 u64 kvm_get_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu) 1901 { 1902 struct kvm_lapic *apic = vcpu->arch.apic; 1903 1904 if (!lapic_in_kernel(vcpu) || 1905 !apic_lvtt_tscdeadline(apic)) 1906 return 0; 1907 1908 return apic->lapic_timer.tscdeadline; 1909 } 1910 1911 void kvm_set_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu, u64 data) 1912 { 1913 struct kvm_lapic *apic = vcpu->arch.apic; 1914 1915 if (!lapic_in_kernel(vcpu) || apic_lvtt_oneshot(apic) || 1916 apic_lvtt_period(apic)) 1917 return; 1918 1919 hrtimer_cancel(&apic->lapic_timer.timer); 1920 apic->lapic_timer.tscdeadline = data; 1921 start_apic_timer(apic); 1922 } 1923 1924 void kvm_lapic_set_tpr(struct kvm_vcpu *vcpu, unsigned long cr8) 1925 { 1926 struct kvm_lapic *apic = vcpu->arch.apic; 1927 1928 apic_set_tpr(apic, ((cr8 & 0x0f) << 4) 1929 | (kvm_lapic_get_reg(apic, APIC_TASKPRI) & 4)); 1930 } 1931 1932 u64 kvm_lapic_get_cr8(struct kvm_vcpu *vcpu) 1933 { 1934 u64 tpr; 1935 1936 tpr = (u64) kvm_lapic_get_reg(vcpu->arch.apic, APIC_TASKPRI); 1937 1938 return (tpr & 0xf0) >> 4; 1939 } 1940 1941 void kvm_lapic_set_base(struct kvm_vcpu *vcpu, u64 value) 1942 { 1943 u64 old_value = vcpu->arch.apic_base; 1944 struct kvm_lapic *apic = vcpu->arch.apic; 1945 1946 if (!apic) 1947 value |= MSR_IA32_APICBASE_BSP; 1948 1949 vcpu->arch.apic_base = value; 1950 1951 if ((old_value ^ value) & MSR_IA32_APICBASE_ENABLE) 1952 kvm_update_cpuid(vcpu); 1953 1954 if (!apic) 1955 return; 1956 1957 /* update jump label if enable bit changes */ 1958 if ((old_value ^ value) & MSR_IA32_APICBASE_ENABLE) { 1959 if (value & MSR_IA32_APICBASE_ENABLE) { 1960 kvm_apic_set_xapic_id(apic, vcpu->vcpu_id); 1961 static_key_slow_dec_deferred(&apic_hw_disabled); 1962 } else { 1963 static_key_slow_inc(&apic_hw_disabled.key); 1964 recalculate_apic_map(vcpu->kvm); 1965 } 1966 } 1967 1968 if ((old_value ^ value) & X2APIC_ENABLE) { 1969 if (value & X2APIC_ENABLE) { 1970 kvm_apic_set_x2apic_id(apic, vcpu->vcpu_id); 1971 kvm_x86_ops->set_virtual_x2apic_mode(vcpu, true); 1972 } else 1973 kvm_x86_ops->set_virtual_x2apic_mode(vcpu, false); 1974 } 1975 1976 apic->base_address = apic->vcpu->arch.apic_base & 1977 MSR_IA32_APICBASE_BASE; 1978 1979 if ((value & MSR_IA32_APICBASE_ENABLE) && 1980 apic->base_address != APIC_DEFAULT_PHYS_BASE) 1981 pr_warn_once("APIC base relocation is unsupported by KVM"); 1982 1983 /* with FSB delivery interrupt, we can restart APIC functionality */ 1984 apic_debug("apic base msr is 0x%016" PRIx64 ", and base address is " 1985 "0x%lx.\n", apic->vcpu->arch.apic_base, apic->base_address); 1986 1987 } 1988 1989 void kvm_lapic_reset(struct kvm_vcpu *vcpu, bool init_event) 1990 { 1991 struct kvm_lapic *apic; 1992 int i; 1993 1994 apic_debug("%s\n", __func__); 1995 1996 ASSERT(vcpu); 1997 apic = vcpu->arch.apic; 1998 ASSERT(apic != NULL); 1999 2000 /* Stop the timer in case it's a reset to an active apic */ 2001 hrtimer_cancel(&apic->lapic_timer.timer); 2002 2003 if (!init_event) { 2004 kvm_lapic_set_base(vcpu, APIC_DEFAULT_PHYS_BASE | 2005 MSR_IA32_APICBASE_ENABLE); 2006 kvm_apic_set_xapic_id(apic, vcpu->vcpu_id); 2007 } 2008 kvm_apic_set_version(apic->vcpu); 2009 2010 for (i = 0; i < KVM_APIC_LVT_NUM; i++) 2011 kvm_lapic_set_reg(apic, APIC_LVTT + 0x10 * i, APIC_LVT_MASKED); 2012 apic_update_lvtt(apic); 2013 if (kvm_vcpu_is_reset_bsp(vcpu) && 2014 kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_LINT0_REENABLED)) 2015 kvm_lapic_set_reg(apic, APIC_LVT0, 2016 SET_APIC_DELIVERY_MODE(0, APIC_MODE_EXTINT)); 2017 apic_manage_nmi_watchdog(apic, kvm_lapic_get_reg(apic, APIC_LVT0)); 2018 2019 kvm_lapic_set_reg(apic, APIC_DFR, 0xffffffffU); 2020 apic_set_spiv(apic, 0xff); 2021 kvm_lapic_set_reg(apic, APIC_TASKPRI, 0); 2022 if (!apic_x2apic_mode(apic)) 2023 kvm_apic_set_ldr(apic, 0); 2024 kvm_lapic_set_reg(apic, APIC_ESR, 0); 2025 kvm_lapic_set_reg(apic, APIC_ICR, 0); 2026 kvm_lapic_set_reg(apic, APIC_ICR2, 0); 2027 kvm_lapic_set_reg(apic, APIC_TDCR, 0); 2028 kvm_lapic_set_reg(apic, APIC_TMICT, 0); 2029 for (i = 0; i < 8; i++) { 2030 kvm_lapic_set_reg(apic, APIC_IRR + 0x10 * i, 0); 2031 kvm_lapic_set_reg(apic, APIC_ISR + 0x10 * i, 0); 2032 kvm_lapic_set_reg(apic, APIC_TMR + 0x10 * i, 0); 2033 } 2034 apic->irr_pending = vcpu->arch.apicv_active; 2035 apic->isr_count = vcpu->arch.apicv_active ? 1 : 0; 2036 apic->highest_isr_cache = -1; 2037 update_divide_count(apic); 2038 atomic_set(&apic->lapic_timer.pending, 0); 2039 if (kvm_vcpu_is_bsp(vcpu)) 2040 kvm_lapic_set_base(vcpu, 2041 vcpu->arch.apic_base | MSR_IA32_APICBASE_BSP); 2042 vcpu->arch.pv_eoi.msr_val = 0; 2043 apic_update_ppr(apic); 2044 if (vcpu->arch.apicv_active) { 2045 kvm_x86_ops->apicv_post_state_restore(vcpu); 2046 kvm_x86_ops->hwapic_irr_update(vcpu, -1); 2047 kvm_x86_ops->hwapic_isr_update(vcpu, -1); 2048 } 2049 2050 vcpu->arch.apic_arb_prio = 0; 2051 vcpu->arch.apic_attention = 0; 2052 2053 apic_debug("%s: vcpu=%p, id=0x%x, base_msr=" 2054 "0x%016" PRIx64 ", base_address=0x%0lx.\n", __func__, 2055 vcpu, kvm_lapic_get_reg(apic, APIC_ID), 2056 vcpu->arch.apic_base, apic->base_address); 2057 } 2058 2059 /* 2060 *---------------------------------------------------------------------- 2061 * timer interface 2062 *---------------------------------------------------------------------- 2063 */ 2064 2065 static bool lapic_is_periodic(struct kvm_lapic *apic) 2066 { 2067 return apic_lvtt_period(apic); 2068 } 2069 2070 int apic_has_pending_timer(struct kvm_vcpu *vcpu) 2071 { 2072 struct kvm_lapic *apic = vcpu->arch.apic; 2073 2074 if (apic_enabled(apic) && apic_lvt_enabled(apic, APIC_LVTT)) 2075 return atomic_read(&apic->lapic_timer.pending); 2076 2077 return 0; 2078 } 2079 2080 int kvm_apic_local_deliver(struct kvm_lapic *apic, int lvt_type) 2081 { 2082 u32 reg = kvm_lapic_get_reg(apic, lvt_type); 2083 int vector, mode, trig_mode; 2084 2085 if (kvm_apic_hw_enabled(apic) && !(reg & APIC_LVT_MASKED)) { 2086 vector = reg & APIC_VECTOR_MASK; 2087 mode = reg & APIC_MODE_MASK; 2088 trig_mode = reg & APIC_LVT_LEVEL_TRIGGER; 2089 return __apic_accept_irq(apic, mode, vector, 1, trig_mode, 2090 NULL); 2091 } 2092 return 0; 2093 } 2094 2095 void kvm_apic_nmi_wd_deliver(struct kvm_vcpu *vcpu) 2096 { 2097 struct kvm_lapic *apic = vcpu->arch.apic; 2098 2099 if (apic) 2100 kvm_apic_local_deliver(apic, APIC_LVT0); 2101 } 2102 2103 static const struct kvm_io_device_ops apic_mmio_ops = { 2104 .read = apic_mmio_read, 2105 .write = apic_mmio_write, 2106 }; 2107 2108 static enum hrtimer_restart apic_timer_fn(struct hrtimer *data) 2109 { 2110 struct kvm_timer *ktimer = container_of(data, struct kvm_timer, timer); 2111 struct kvm_lapic *apic = container_of(ktimer, struct kvm_lapic, lapic_timer); 2112 2113 apic_timer_expired(apic); 2114 2115 if (lapic_is_periodic(apic)) { 2116 advance_periodic_target_expiration(apic); 2117 hrtimer_add_expires_ns(&ktimer->timer, ktimer->period); 2118 return HRTIMER_RESTART; 2119 } else 2120 return HRTIMER_NORESTART; 2121 } 2122 2123 int kvm_create_lapic(struct kvm_vcpu *vcpu) 2124 { 2125 struct kvm_lapic *apic; 2126 2127 ASSERT(vcpu != NULL); 2128 apic_debug("apic_init %d\n", vcpu->vcpu_id); 2129 2130 apic = kzalloc(sizeof(*apic), GFP_KERNEL); 2131 if (!apic) 2132 goto nomem; 2133 2134 vcpu->arch.apic = apic; 2135 2136 apic->regs = (void *)get_zeroed_page(GFP_KERNEL); 2137 if (!apic->regs) { 2138 printk(KERN_ERR "malloc apic regs error for vcpu %x\n", 2139 vcpu->vcpu_id); 2140 goto nomem_free_apic; 2141 } 2142 apic->vcpu = vcpu; 2143 2144 hrtimer_init(&apic->lapic_timer.timer, CLOCK_MONOTONIC, 2145 HRTIMER_MODE_ABS_PINNED); 2146 apic->lapic_timer.timer.function = apic_timer_fn; 2147 2148 /* 2149 * APIC is created enabled. This will prevent kvm_lapic_set_base from 2150 * thinking that APIC satet has changed. 2151 */ 2152 vcpu->arch.apic_base = MSR_IA32_APICBASE_ENABLE; 2153 static_key_slow_inc(&apic_sw_disabled.key); /* sw disabled at reset */ 2154 kvm_lapic_reset(vcpu, false); 2155 kvm_iodevice_init(&apic->dev, &apic_mmio_ops); 2156 2157 return 0; 2158 nomem_free_apic: 2159 kfree(apic); 2160 nomem: 2161 return -ENOMEM; 2162 } 2163 2164 int kvm_apic_has_interrupt(struct kvm_vcpu *vcpu) 2165 { 2166 struct kvm_lapic *apic = vcpu->arch.apic; 2167 u32 ppr; 2168 2169 if (!apic_enabled(apic)) 2170 return -1; 2171 2172 __apic_update_ppr(apic, &ppr); 2173 return apic_has_interrupt_for_ppr(apic, ppr); 2174 } 2175 2176 int kvm_apic_accept_pic_intr(struct kvm_vcpu *vcpu) 2177 { 2178 u32 lvt0 = kvm_lapic_get_reg(vcpu->arch.apic, APIC_LVT0); 2179 int r = 0; 2180 2181 if (!kvm_apic_hw_enabled(vcpu->arch.apic)) 2182 r = 1; 2183 if ((lvt0 & APIC_LVT_MASKED) == 0 && 2184 GET_APIC_DELIVERY_MODE(lvt0) == APIC_MODE_EXTINT) 2185 r = 1; 2186 return r; 2187 } 2188 2189 void kvm_inject_apic_timer_irqs(struct kvm_vcpu *vcpu) 2190 { 2191 struct kvm_lapic *apic = vcpu->arch.apic; 2192 2193 if (atomic_read(&apic->lapic_timer.pending) > 0) { 2194 kvm_apic_local_deliver(apic, APIC_LVTT); 2195 if (apic_lvtt_tscdeadline(apic)) 2196 apic->lapic_timer.tscdeadline = 0; 2197 if (apic_lvtt_oneshot(apic)) { 2198 apic->lapic_timer.tscdeadline = 0; 2199 apic->lapic_timer.target_expiration = 0; 2200 } 2201 atomic_set(&apic->lapic_timer.pending, 0); 2202 } 2203 } 2204 2205 int kvm_get_apic_interrupt(struct kvm_vcpu *vcpu) 2206 { 2207 int vector = kvm_apic_has_interrupt(vcpu); 2208 struct kvm_lapic *apic = vcpu->arch.apic; 2209 u32 ppr; 2210 2211 if (vector == -1) 2212 return -1; 2213 2214 /* 2215 * We get here even with APIC virtualization enabled, if doing 2216 * nested virtualization and L1 runs with the "acknowledge interrupt 2217 * on exit" mode. Then we cannot inject the interrupt via RVI, 2218 * because the process would deliver it through the IDT. 2219 */ 2220 2221 apic_clear_irr(vector, apic); 2222 if (test_bit(vector, vcpu_to_synic(vcpu)->auto_eoi_bitmap)) { 2223 /* 2224 * For auto-EOI interrupts, there might be another pending 2225 * interrupt above PPR, so check whether to raise another 2226 * KVM_REQ_EVENT. 2227 */ 2228 apic_update_ppr(apic); 2229 } else { 2230 /* 2231 * For normal interrupts, PPR has been raised and there cannot 2232 * be a higher-priority pending interrupt---except if there was 2233 * a concurrent interrupt injection, but that would have 2234 * triggered KVM_REQ_EVENT already. 2235 */ 2236 apic_set_isr(vector, apic); 2237 __apic_update_ppr(apic, &ppr); 2238 } 2239 2240 return vector; 2241 } 2242 2243 static int kvm_apic_state_fixup(struct kvm_vcpu *vcpu, 2244 struct kvm_lapic_state *s, bool set) 2245 { 2246 if (apic_x2apic_mode(vcpu->arch.apic)) { 2247 u32 *id = (u32 *)(s->regs + APIC_ID); 2248 2249 if (vcpu->kvm->arch.x2apic_format) { 2250 if (*id != vcpu->vcpu_id) 2251 return -EINVAL; 2252 } else { 2253 if (set) 2254 *id >>= 24; 2255 else 2256 *id <<= 24; 2257 } 2258 } 2259 2260 return 0; 2261 } 2262 2263 int kvm_apic_get_state(struct kvm_vcpu *vcpu, struct kvm_lapic_state *s) 2264 { 2265 memcpy(s->regs, vcpu->arch.apic->regs, sizeof(*s)); 2266 return kvm_apic_state_fixup(vcpu, s, false); 2267 } 2268 2269 int kvm_apic_set_state(struct kvm_vcpu *vcpu, struct kvm_lapic_state *s) 2270 { 2271 struct kvm_lapic *apic = vcpu->arch.apic; 2272 int r; 2273 2274 2275 kvm_lapic_set_base(vcpu, vcpu->arch.apic_base); 2276 /* set SPIV separately to get count of SW disabled APICs right */ 2277 apic_set_spiv(apic, *((u32 *)(s->regs + APIC_SPIV))); 2278 2279 r = kvm_apic_state_fixup(vcpu, s, true); 2280 if (r) 2281 return r; 2282 memcpy(vcpu->arch.apic->regs, s->regs, sizeof *s); 2283 2284 recalculate_apic_map(vcpu->kvm); 2285 kvm_apic_set_version(vcpu); 2286 2287 apic_update_ppr(apic); 2288 hrtimer_cancel(&apic->lapic_timer.timer); 2289 apic_update_lvtt(apic); 2290 apic_manage_nmi_watchdog(apic, kvm_lapic_get_reg(apic, APIC_LVT0)); 2291 update_divide_count(apic); 2292 start_apic_timer(apic); 2293 apic->irr_pending = true; 2294 apic->isr_count = vcpu->arch.apicv_active ? 2295 1 : count_vectors(apic->regs + APIC_ISR); 2296 apic->highest_isr_cache = -1; 2297 if (vcpu->arch.apicv_active) { 2298 kvm_x86_ops->apicv_post_state_restore(vcpu); 2299 kvm_x86_ops->hwapic_irr_update(vcpu, 2300 apic_find_highest_irr(apic)); 2301 kvm_x86_ops->hwapic_isr_update(vcpu, 2302 apic_find_highest_isr(apic)); 2303 } 2304 kvm_make_request(KVM_REQ_EVENT, vcpu); 2305 if (ioapic_in_kernel(vcpu->kvm)) 2306 kvm_rtc_eoi_tracking_restore_one(vcpu); 2307 2308 vcpu->arch.apic_arb_prio = 0; 2309 2310 return 0; 2311 } 2312 2313 void __kvm_migrate_apic_timer(struct kvm_vcpu *vcpu) 2314 { 2315 struct hrtimer *timer; 2316 2317 if (!lapic_in_kernel(vcpu)) 2318 return; 2319 2320 timer = &vcpu->arch.apic->lapic_timer.timer; 2321 if (hrtimer_cancel(timer)) 2322 hrtimer_start_expires(timer, HRTIMER_MODE_ABS_PINNED); 2323 } 2324 2325 /* 2326 * apic_sync_pv_eoi_from_guest - called on vmexit or cancel interrupt 2327 * 2328 * Detect whether guest triggered PV EOI since the 2329 * last entry. If yes, set EOI on guests's behalf. 2330 * Clear PV EOI in guest memory in any case. 2331 */ 2332 static void apic_sync_pv_eoi_from_guest(struct kvm_vcpu *vcpu, 2333 struct kvm_lapic *apic) 2334 { 2335 bool pending; 2336 int vector; 2337 /* 2338 * PV EOI state is derived from KVM_APIC_PV_EOI_PENDING in host 2339 * and KVM_PV_EOI_ENABLED in guest memory as follows: 2340 * 2341 * KVM_APIC_PV_EOI_PENDING is unset: 2342 * -> host disabled PV EOI. 2343 * KVM_APIC_PV_EOI_PENDING is set, KVM_PV_EOI_ENABLED is set: 2344 * -> host enabled PV EOI, guest did not execute EOI yet. 2345 * KVM_APIC_PV_EOI_PENDING is set, KVM_PV_EOI_ENABLED is unset: 2346 * -> host enabled PV EOI, guest executed EOI. 2347 */ 2348 BUG_ON(!pv_eoi_enabled(vcpu)); 2349 pending = pv_eoi_get_pending(vcpu); 2350 /* 2351 * Clear pending bit in any case: it will be set again on vmentry. 2352 * While this might not be ideal from performance point of view, 2353 * this makes sure pv eoi is only enabled when we know it's safe. 2354 */ 2355 pv_eoi_clr_pending(vcpu); 2356 if (pending) 2357 return; 2358 vector = apic_set_eoi(apic); 2359 trace_kvm_pv_eoi(apic, vector); 2360 } 2361 2362 void kvm_lapic_sync_from_vapic(struct kvm_vcpu *vcpu) 2363 { 2364 u32 data; 2365 2366 if (test_bit(KVM_APIC_PV_EOI_PENDING, &vcpu->arch.apic_attention)) 2367 apic_sync_pv_eoi_from_guest(vcpu, vcpu->arch.apic); 2368 2369 if (!test_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention)) 2370 return; 2371 2372 if (kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.apic->vapic_cache, &data, 2373 sizeof(u32))) 2374 return; 2375 2376 apic_set_tpr(vcpu->arch.apic, data & 0xff); 2377 } 2378 2379 /* 2380 * apic_sync_pv_eoi_to_guest - called before vmentry 2381 * 2382 * Detect whether it's safe to enable PV EOI and 2383 * if yes do so. 2384 */ 2385 static void apic_sync_pv_eoi_to_guest(struct kvm_vcpu *vcpu, 2386 struct kvm_lapic *apic) 2387 { 2388 if (!pv_eoi_enabled(vcpu) || 2389 /* IRR set or many bits in ISR: could be nested. */ 2390 apic->irr_pending || 2391 /* Cache not set: could be safe but we don't bother. */ 2392 apic->highest_isr_cache == -1 || 2393 /* Need EOI to update ioapic. */ 2394 kvm_ioapic_handles_vector(apic, apic->highest_isr_cache)) { 2395 /* 2396 * PV EOI was disabled by apic_sync_pv_eoi_from_guest 2397 * so we need not do anything here. 2398 */ 2399 return; 2400 } 2401 2402 pv_eoi_set_pending(apic->vcpu); 2403 } 2404 2405 void kvm_lapic_sync_to_vapic(struct kvm_vcpu *vcpu) 2406 { 2407 u32 data, tpr; 2408 int max_irr, max_isr; 2409 struct kvm_lapic *apic = vcpu->arch.apic; 2410 2411 apic_sync_pv_eoi_to_guest(vcpu, apic); 2412 2413 if (!test_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention)) 2414 return; 2415 2416 tpr = kvm_lapic_get_reg(apic, APIC_TASKPRI) & 0xff; 2417 max_irr = apic_find_highest_irr(apic); 2418 if (max_irr < 0) 2419 max_irr = 0; 2420 max_isr = apic_find_highest_isr(apic); 2421 if (max_isr < 0) 2422 max_isr = 0; 2423 data = (tpr & 0xff) | ((max_isr & 0xf0) << 8) | (max_irr << 24); 2424 2425 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apic->vapic_cache, &data, 2426 sizeof(u32)); 2427 } 2428 2429 int kvm_lapic_set_vapic_addr(struct kvm_vcpu *vcpu, gpa_t vapic_addr) 2430 { 2431 if (vapic_addr) { 2432 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, 2433 &vcpu->arch.apic->vapic_cache, 2434 vapic_addr, sizeof(u32))) 2435 return -EINVAL; 2436 __set_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention); 2437 } else { 2438 __clear_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention); 2439 } 2440 2441 vcpu->arch.apic->vapic_addr = vapic_addr; 2442 return 0; 2443 } 2444 2445 int kvm_x2apic_msr_write(struct kvm_vcpu *vcpu, u32 msr, u64 data) 2446 { 2447 struct kvm_lapic *apic = vcpu->arch.apic; 2448 u32 reg = (msr - APIC_BASE_MSR) << 4; 2449 2450 if (!lapic_in_kernel(vcpu) || !apic_x2apic_mode(apic)) 2451 return 1; 2452 2453 if (reg == APIC_ICR2) 2454 return 1; 2455 2456 /* if this is ICR write vector before command */ 2457 if (reg == APIC_ICR) 2458 kvm_lapic_reg_write(apic, APIC_ICR2, (u32)(data >> 32)); 2459 return kvm_lapic_reg_write(apic, reg, (u32)data); 2460 } 2461 2462 int kvm_x2apic_msr_read(struct kvm_vcpu *vcpu, u32 msr, u64 *data) 2463 { 2464 struct kvm_lapic *apic = vcpu->arch.apic; 2465 u32 reg = (msr - APIC_BASE_MSR) << 4, low, high = 0; 2466 2467 if (!lapic_in_kernel(vcpu) || !apic_x2apic_mode(apic)) 2468 return 1; 2469 2470 if (reg == APIC_DFR || reg == APIC_ICR2) { 2471 apic_debug("KVM_APIC_READ: read x2apic reserved register %x\n", 2472 reg); 2473 return 1; 2474 } 2475 2476 if (kvm_lapic_reg_read(apic, reg, 4, &low)) 2477 return 1; 2478 if (reg == APIC_ICR) 2479 kvm_lapic_reg_read(apic, APIC_ICR2, 4, &high); 2480 2481 *data = (((u64)high) << 32) | low; 2482 2483 return 0; 2484 } 2485 2486 int kvm_hv_vapic_msr_write(struct kvm_vcpu *vcpu, u32 reg, u64 data) 2487 { 2488 struct kvm_lapic *apic = vcpu->arch.apic; 2489 2490 if (!lapic_in_kernel(vcpu)) 2491 return 1; 2492 2493 /* if this is ICR write vector before command */ 2494 if (reg == APIC_ICR) 2495 kvm_lapic_reg_write(apic, APIC_ICR2, (u32)(data >> 32)); 2496 return kvm_lapic_reg_write(apic, reg, (u32)data); 2497 } 2498 2499 int kvm_hv_vapic_msr_read(struct kvm_vcpu *vcpu, u32 reg, u64 *data) 2500 { 2501 struct kvm_lapic *apic = vcpu->arch.apic; 2502 u32 low, high = 0; 2503 2504 if (!lapic_in_kernel(vcpu)) 2505 return 1; 2506 2507 if (kvm_lapic_reg_read(apic, reg, 4, &low)) 2508 return 1; 2509 if (reg == APIC_ICR) 2510 kvm_lapic_reg_read(apic, APIC_ICR2, 4, &high); 2511 2512 *data = (((u64)high) << 32) | low; 2513 2514 return 0; 2515 } 2516 2517 int kvm_lapic_enable_pv_eoi(struct kvm_vcpu *vcpu, u64 data) 2518 { 2519 u64 addr = data & ~KVM_MSR_ENABLED; 2520 if (!IS_ALIGNED(addr, 4)) 2521 return 1; 2522 2523 vcpu->arch.pv_eoi.msr_val = data; 2524 if (!pv_eoi_enabled(vcpu)) 2525 return 0; 2526 return kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.pv_eoi.data, 2527 addr, sizeof(u8)); 2528 } 2529 2530 void kvm_apic_accept_events(struct kvm_vcpu *vcpu) 2531 { 2532 struct kvm_lapic *apic = vcpu->arch.apic; 2533 u8 sipi_vector; 2534 unsigned long pe; 2535 2536 if (!lapic_in_kernel(vcpu) || !apic->pending_events) 2537 return; 2538 2539 /* 2540 * INITs are latched while in SMM. Because an SMM CPU cannot 2541 * be in KVM_MP_STATE_INIT_RECEIVED state, just eat SIPIs 2542 * and delay processing of INIT until the next RSM. 2543 */ 2544 if (is_smm(vcpu)) { 2545 WARN_ON_ONCE(vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED); 2546 if (test_bit(KVM_APIC_SIPI, &apic->pending_events)) 2547 clear_bit(KVM_APIC_SIPI, &apic->pending_events); 2548 return; 2549 } 2550 2551 pe = xchg(&apic->pending_events, 0); 2552 if (test_bit(KVM_APIC_INIT, &pe)) { 2553 kvm_lapic_reset(vcpu, true); 2554 kvm_vcpu_reset(vcpu, true); 2555 if (kvm_vcpu_is_bsp(apic->vcpu)) 2556 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; 2557 else 2558 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED; 2559 } 2560 if (test_bit(KVM_APIC_SIPI, &pe) && 2561 vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) { 2562 /* evaluate pending_events before reading the vector */ 2563 smp_rmb(); 2564 sipi_vector = apic->sipi_vector; 2565 apic_debug("vcpu %d received sipi with vector # %x\n", 2566 vcpu->vcpu_id, sipi_vector); 2567 kvm_vcpu_deliver_sipi_vector(vcpu, sipi_vector); 2568 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; 2569 } 2570 } 2571 2572 void kvm_lapic_init(void) 2573 { 2574 /* do not patch jump label more than once per second */ 2575 jump_label_rate_limit(&apic_hw_disabled, HZ); 2576 jump_label_rate_limit(&apic_sw_disabled, HZ); 2577 } 2578 2579 void kvm_lapic_exit(void) 2580 { 2581 static_key_deferred_flush(&apic_hw_disabled); 2582 static_key_deferred_flush(&apic_sw_disabled); 2583 } 2584