1 2 /* 3 * Local APIC virtualization 4 * 5 * Copyright (C) 2006 Qumranet, Inc. 6 * Copyright (C) 2007 Novell 7 * Copyright (C) 2007 Intel 8 * Copyright 2009 Red Hat, Inc. and/or its affiliates. 9 * 10 * Authors: 11 * Dor Laor <dor.laor@qumranet.com> 12 * Gregory Haskins <ghaskins@novell.com> 13 * Yaozu (Eddie) Dong <eddie.dong@intel.com> 14 * 15 * Based on Xen 3.1 code, Copyright (c) 2004, Intel Corporation. 16 * 17 * This work is licensed under the terms of the GNU GPL, version 2. See 18 * the COPYING file in the top-level directory. 19 */ 20 21 #include <linux/kvm_host.h> 22 #include <linux/kvm.h> 23 #include <linux/mm.h> 24 #include <linux/highmem.h> 25 #include <linux/smp.h> 26 #include <linux/hrtimer.h> 27 #include <linux/io.h> 28 #include <linux/module.h> 29 #include <linux/math64.h> 30 #include <linux/slab.h> 31 #include <asm/processor.h> 32 #include <asm/msr.h> 33 #include <asm/page.h> 34 #include <asm/current.h> 35 #include <asm/apicdef.h> 36 #include <linux/atomic.h> 37 #include <linux/jump_label.h> 38 #include "kvm_cache_regs.h" 39 #include "irq.h" 40 #include "trace.h" 41 #include "x86.h" 42 #include "cpuid.h" 43 44 #ifndef CONFIG_X86_64 45 #define mod_64(x, y) ((x) - (y) * div64_u64(x, y)) 46 #else 47 #define mod_64(x, y) ((x) % (y)) 48 #endif 49 50 #define PRId64 "d" 51 #define PRIx64 "llx" 52 #define PRIu64 "u" 53 #define PRIo64 "o" 54 55 #define APIC_BUS_CYCLE_NS 1 56 57 /* #define apic_debug(fmt,arg...) printk(KERN_WARNING fmt,##arg) */ 58 #define apic_debug(fmt, arg...) 59 60 #define APIC_LVT_NUM 6 61 /* 14 is the version for Xeon and Pentium 8.4.8*/ 62 #define APIC_VERSION (0x14UL | ((APIC_LVT_NUM - 1) << 16)) 63 #define LAPIC_MMIO_LENGTH (1 << 12) 64 /* followed define is not in apicdef.h */ 65 #define APIC_SHORT_MASK 0xc0000 66 #define APIC_DEST_NOSHORT 0x0 67 #define APIC_DEST_MASK 0x800 68 #define MAX_APIC_VECTOR 256 69 #define APIC_VECTORS_PER_REG 32 70 71 #define APIC_BROADCAST 0xFF 72 #define X2APIC_BROADCAST 0xFFFFFFFFul 73 74 #define VEC_POS(v) ((v) & (32 - 1)) 75 #define REG_POS(v) (((v) >> 5) << 4) 76 77 static inline void apic_set_reg(struct kvm_lapic *apic, int reg_off, u32 val) 78 { 79 *((u32 *) (apic->regs + reg_off)) = val; 80 } 81 82 static inline int apic_test_vector(int vec, void *bitmap) 83 { 84 return test_bit(VEC_POS(vec), (bitmap) + REG_POS(vec)); 85 } 86 87 bool kvm_apic_pending_eoi(struct kvm_vcpu *vcpu, int vector) 88 { 89 struct kvm_lapic *apic = vcpu->arch.apic; 90 91 return apic_test_vector(vector, apic->regs + APIC_ISR) || 92 apic_test_vector(vector, apic->regs + APIC_IRR); 93 } 94 95 static inline void apic_set_vector(int vec, void *bitmap) 96 { 97 set_bit(VEC_POS(vec), (bitmap) + REG_POS(vec)); 98 } 99 100 static inline void apic_clear_vector(int vec, void *bitmap) 101 { 102 clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec)); 103 } 104 105 static inline int __apic_test_and_set_vector(int vec, void *bitmap) 106 { 107 return __test_and_set_bit(VEC_POS(vec), (bitmap) + REG_POS(vec)); 108 } 109 110 static inline int __apic_test_and_clear_vector(int vec, void *bitmap) 111 { 112 return __test_and_clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec)); 113 } 114 115 struct static_key_deferred apic_hw_disabled __read_mostly; 116 struct static_key_deferred apic_sw_disabled __read_mostly; 117 118 static inline int apic_enabled(struct kvm_lapic *apic) 119 { 120 return kvm_apic_sw_enabled(apic) && kvm_apic_hw_enabled(apic); 121 } 122 123 #define LVT_MASK \ 124 (APIC_LVT_MASKED | APIC_SEND_PENDING | APIC_VECTOR_MASK) 125 126 #define LINT_MASK \ 127 (LVT_MASK | APIC_MODE_MASK | APIC_INPUT_POLARITY | \ 128 APIC_LVT_REMOTE_IRR | APIC_LVT_LEVEL_TRIGGER) 129 130 static inline int kvm_apic_id(struct kvm_lapic *apic) 131 { 132 return (kvm_apic_get_reg(apic, APIC_ID) >> 24) & 0xff; 133 } 134 135 static void recalculate_apic_map(struct kvm *kvm) 136 { 137 struct kvm_apic_map *new, *old = NULL; 138 struct kvm_vcpu *vcpu; 139 int i; 140 141 new = kzalloc(sizeof(struct kvm_apic_map), GFP_KERNEL); 142 143 mutex_lock(&kvm->arch.apic_map_lock); 144 145 if (!new) 146 goto out; 147 148 new->ldr_bits = 8; 149 /* flat mode is default */ 150 new->cid_shift = 8; 151 new->cid_mask = 0; 152 new->lid_mask = 0xff; 153 new->broadcast = APIC_BROADCAST; 154 155 kvm_for_each_vcpu(i, vcpu, kvm) { 156 struct kvm_lapic *apic = vcpu->arch.apic; 157 158 if (!kvm_apic_present(vcpu)) 159 continue; 160 161 if (apic_x2apic_mode(apic)) { 162 new->ldr_bits = 32; 163 new->cid_shift = 16; 164 new->cid_mask = new->lid_mask = 0xffff; 165 new->broadcast = X2APIC_BROADCAST; 166 } else if (kvm_apic_get_reg(apic, APIC_LDR)) { 167 if (kvm_apic_get_reg(apic, APIC_DFR) == 168 APIC_DFR_CLUSTER) { 169 new->cid_shift = 4; 170 new->cid_mask = 0xf; 171 new->lid_mask = 0xf; 172 } else { 173 new->cid_shift = 8; 174 new->cid_mask = 0; 175 new->lid_mask = 0xff; 176 } 177 } 178 179 /* 180 * All APICs have to be configured in the same mode by an OS. 181 * We take advatage of this while building logical id loockup 182 * table. After reset APICs are in software disabled mode, so if 183 * we find apic with different setting we assume this is the mode 184 * OS wants all apics to be in; build lookup table accordingly. 185 */ 186 if (kvm_apic_sw_enabled(apic)) 187 break; 188 } 189 190 kvm_for_each_vcpu(i, vcpu, kvm) { 191 struct kvm_lapic *apic = vcpu->arch.apic; 192 u16 cid, lid; 193 u32 ldr, aid; 194 195 if (!kvm_apic_present(vcpu)) 196 continue; 197 198 aid = kvm_apic_id(apic); 199 ldr = kvm_apic_get_reg(apic, APIC_LDR); 200 cid = apic_cluster_id(new, ldr); 201 lid = apic_logical_id(new, ldr); 202 203 if (aid < ARRAY_SIZE(new->phys_map)) 204 new->phys_map[aid] = apic; 205 if (lid && cid < ARRAY_SIZE(new->logical_map)) 206 new->logical_map[cid][ffs(lid) - 1] = apic; 207 } 208 out: 209 old = rcu_dereference_protected(kvm->arch.apic_map, 210 lockdep_is_held(&kvm->arch.apic_map_lock)); 211 rcu_assign_pointer(kvm->arch.apic_map, new); 212 mutex_unlock(&kvm->arch.apic_map_lock); 213 214 if (old) 215 kfree_rcu(old, rcu); 216 217 kvm_vcpu_request_scan_ioapic(kvm); 218 } 219 220 static inline void apic_set_spiv(struct kvm_lapic *apic, u32 val) 221 { 222 bool enabled = val & APIC_SPIV_APIC_ENABLED; 223 224 apic_set_reg(apic, APIC_SPIV, val); 225 226 if (enabled != apic->sw_enabled) { 227 apic->sw_enabled = enabled; 228 if (enabled) { 229 static_key_slow_dec_deferred(&apic_sw_disabled); 230 recalculate_apic_map(apic->vcpu->kvm); 231 } else 232 static_key_slow_inc(&apic_sw_disabled.key); 233 } 234 } 235 236 static inline void kvm_apic_set_id(struct kvm_lapic *apic, u8 id) 237 { 238 apic_set_reg(apic, APIC_ID, id << 24); 239 recalculate_apic_map(apic->vcpu->kvm); 240 } 241 242 static inline void kvm_apic_set_ldr(struct kvm_lapic *apic, u32 id) 243 { 244 apic_set_reg(apic, APIC_LDR, id); 245 recalculate_apic_map(apic->vcpu->kvm); 246 } 247 248 static inline int apic_lvt_enabled(struct kvm_lapic *apic, int lvt_type) 249 { 250 return !(kvm_apic_get_reg(apic, lvt_type) & APIC_LVT_MASKED); 251 } 252 253 static inline int apic_lvt_vector(struct kvm_lapic *apic, int lvt_type) 254 { 255 return kvm_apic_get_reg(apic, lvt_type) & APIC_VECTOR_MASK; 256 } 257 258 static inline int apic_lvtt_oneshot(struct kvm_lapic *apic) 259 { 260 return apic->lapic_timer.timer_mode == APIC_LVT_TIMER_ONESHOT; 261 } 262 263 static inline int apic_lvtt_period(struct kvm_lapic *apic) 264 { 265 return apic->lapic_timer.timer_mode == APIC_LVT_TIMER_PERIODIC; 266 } 267 268 static inline int apic_lvtt_tscdeadline(struct kvm_lapic *apic) 269 { 270 return apic->lapic_timer.timer_mode == APIC_LVT_TIMER_TSCDEADLINE; 271 } 272 273 static inline int apic_lvt_nmi_mode(u32 lvt_val) 274 { 275 return (lvt_val & (APIC_MODE_MASK | APIC_LVT_MASKED)) == APIC_DM_NMI; 276 } 277 278 void kvm_apic_set_version(struct kvm_vcpu *vcpu) 279 { 280 struct kvm_lapic *apic = vcpu->arch.apic; 281 struct kvm_cpuid_entry2 *feat; 282 u32 v = APIC_VERSION; 283 284 if (!kvm_vcpu_has_lapic(vcpu)) 285 return; 286 287 feat = kvm_find_cpuid_entry(apic->vcpu, 0x1, 0); 288 if (feat && (feat->ecx & (1 << (X86_FEATURE_X2APIC & 31)))) 289 v |= APIC_LVR_DIRECTED_EOI; 290 apic_set_reg(apic, APIC_LVR, v); 291 } 292 293 static const unsigned int apic_lvt_mask[APIC_LVT_NUM] = { 294 LVT_MASK , /* part LVTT mask, timer mode mask added at runtime */ 295 LVT_MASK | APIC_MODE_MASK, /* LVTTHMR */ 296 LVT_MASK | APIC_MODE_MASK, /* LVTPC */ 297 LINT_MASK, LINT_MASK, /* LVT0-1 */ 298 LVT_MASK /* LVTERR */ 299 }; 300 301 static int find_highest_vector(void *bitmap) 302 { 303 int vec; 304 u32 *reg; 305 306 for (vec = MAX_APIC_VECTOR - APIC_VECTORS_PER_REG; 307 vec >= 0; vec -= APIC_VECTORS_PER_REG) { 308 reg = bitmap + REG_POS(vec); 309 if (*reg) 310 return fls(*reg) - 1 + vec; 311 } 312 313 return -1; 314 } 315 316 static u8 count_vectors(void *bitmap) 317 { 318 int vec; 319 u32 *reg; 320 u8 count = 0; 321 322 for (vec = 0; vec < MAX_APIC_VECTOR; vec += APIC_VECTORS_PER_REG) { 323 reg = bitmap + REG_POS(vec); 324 count += hweight32(*reg); 325 } 326 327 return count; 328 } 329 330 void kvm_apic_update_irr(struct kvm_vcpu *vcpu, u32 *pir) 331 { 332 u32 i, pir_val; 333 struct kvm_lapic *apic = vcpu->arch.apic; 334 335 for (i = 0; i <= 7; i++) { 336 pir_val = xchg(&pir[i], 0); 337 if (pir_val) 338 *((u32 *)(apic->regs + APIC_IRR + i * 0x10)) |= pir_val; 339 } 340 } 341 EXPORT_SYMBOL_GPL(kvm_apic_update_irr); 342 343 static inline void apic_set_irr(int vec, struct kvm_lapic *apic) 344 { 345 apic_set_vector(vec, apic->regs + APIC_IRR); 346 /* 347 * irr_pending must be true if any interrupt is pending; set it after 348 * APIC_IRR to avoid race with apic_clear_irr 349 */ 350 apic->irr_pending = true; 351 } 352 353 static inline int apic_search_irr(struct kvm_lapic *apic) 354 { 355 return find_highest_vector(apic->regs + APIC_IRR); 356 } 357 358 static inline int apic_find_highest_irr(struct kvm_lapic *apic) 359 { 360 int result; 361 362 /* 363 * Note that irr_pending is just a hint. It will be always 364 * true with virtual interrupt delivery enabled. 365 */ 366 if (!apic->irr_pending) 367 return -1; 368 369 kvm_x86_ops->sync_pir_to_irr(apic->vcpu); 370 result = apic_search_irr(apic); 371 ASSERT(result == -1 || result >= 16); 372 373 return result; 374 } 375 376 static inline void apic_clear_irr(int vec, struct kvm_lapic *apic) 377 { 378 struct kvm_vcpu *vcpu; 379 380 vcpu = apic->vcpu; 381 382 if (unlikely(kvm_apic_vid_enabled(vcpu->kvm))) { 383 /* try to update RVI */ 384 apic_clear_vector(vec, apic->regs + APIC_IRR); 385 kvm_make_request(KVM_REQ_EVENT, vcpu); 386 } else { 387 apic->irr_pending = false; 388 apic_clear_vector(vec, apic->regs + APIC_IRR); 389 if (apic_search_irr(apic) != -1) 390 apic->irr_pending = true; 391 } 392 } 393 394 static inline void apic_set_isr(int vec, struct kvm_lapic *apic) 395 { 396 struct kvm_vcpu *vcpu; 397 398 if (__apic_test_and_set_vector(vec, apic->regs + APIC_ISR)) 399 return; 400 401 vcpu = apic->vcpu; 402 403 /* 404 * With APIC virtualization enabled, all caching is disabled 405 * because the processor can modify ISR under the hood. Instead 406 * just set SVI. 407 */ 408 if (unlikely(kvm_apic_vid_enabled(vcpu->kvm))) 409 kvm_x86_ops->hwapic_isr_update(vcpu->kvm, vec); 410 else { 411 ++apic->isr_count; 412 BUG_ON(apic->isr_count > MAX_APIC_VECTOR); 413 /* 414 * ISR (in service register) bit is set when injecting an interrupt. 415 * The highest vector is injected. Thus the latest bit set matches 416 * the highest bit in ISR. 417 */ 418 apic->highest_isr_cache = vec; 419 } 420 } 421 422 static inline int apic_find_highest_isr(struct kvm_lapic *apic) 423 { 424 int result; 425 426 /* 427 * Note that isr_count is always 1, and highest_isr_cache 428 * is always -1, with APIC virtualization enabled. 429 */ 430 if (!apic->isr_count) 431 return -1; 432 if (likely(apic->highest_isr_cache != -1)) 433 return apic->highest_isr_cache; 434 435 result = find_highest_vector(apic->regs + APIC_ISR); 436 ASSERT(result == -1 || result >= 16); 437 438 return result; 439 } 440 441 static inline void apic_clear_isr(int vec, struct kvm_lapic *apic) 442 { 443 struct kvm_vcpu *vcpu; 444 if (!__apic_test_and_clear_vector(vec, apic->regs + APIC_ISR)) 445 return; 446 447 vcpu = apic->vcpu; 448 449 /* 450 * We do get here for APIC virtualization enabled if the guest 451 * uses the Hyper-V APIC enlightenment. In this case we may need 452 * to trigger a new interrupt delivery by writing the SVI field; 453 * on the other hand isr_count and highest_isr_cache are unused 454 * and must be left alone. 455 */ 456 if (unlikely(kvm_apic_vid_enabled(vcpu->kvm))) 457 kvm_x86_ops->hwapic_isr_update(vcpu->kvm, 458 apic_find_highest_isr(apic)); 459 else { 460 --apic->isr_count; 461 BUG_ON(apic->isr_count < 0); 462 apic->highest_isr_cache = -1; 463 } 464 } 465 466 int kvm_lapic_find_highest_irr(struct kvm_vcpu *vcpu) 467 { 468 int highest_irr; 469 470 /* This may race with setting of irr in __apic_accept_irq() and 471 * value returned may be wrong, but kvm_vcpu_kick() in __apic_accept_irq 472 * will cause vmexit immediately and the value will be recalculated 473 * on the next vmentry. 474 */ 475 if (!kvm_vcpu_has_lapic(vcpu)) 476 return 0; 477 highest_irr = apic_find_highest_irr(vcpu->arch.apic); 478 479 return highest_irr; 480 } 481 482 static int __apic_accept_irq(struct kvm_lapic *apic, int delivery_mode, 483 int vector, int level, int trig_mode, 484 unsigned long *dest_map); 485 486 int kvm_apic_set_irq(struct kvm_vcpu *vcpu, struct kvm_lapic_irq *irq, 487 unsigned long *dest_map) 488 { 489 struct kvm_lapic *apic = vcpu->arch.apic; 490 491 return __apic_accept_irq(apic, irq->delivery_mode, irq->vector, 492 irq->level, irq->trig_mode, dest_map); 493 } 494 495 static int pv_eoi_put_user(struct kvm_vcpu *vcpu, u8 val) 496 { 497 498 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.pv_eoi.data, &val, 499 sizeof(val)); 500 } 501 502 static int pv_eoi_get_user(struct kvm_vcpu *vcpu, u8 *val) 503 { 504 505 return kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.pv_eoi.data, val, 506 sizeof(*val)); 507 } 508 509 static inline bool pv_eoi_enabled(struct kvm_vcpu *vcpu) 510 { 511 return vcpu->arch.pv_eoi.msr_val & KVM_MSR_ENABLED; 512 } 513 514 static bool pv_eoi_get_pending(struct kvm_vcpu *vcpu) 515 { 516 u8 val; 517 if (pv_eoi_get_user(vcpu, &val) < 0) 518 apic_debug("Can't read EOI MSR value: 0x%llx\n", 519 (unsigned long long)vcpu->arch.pv_eoi.msr_val); 520 return val & 0x1; 521 } 522 523 static void pv_eoi_set_pending(struct kvm_vcpu *vcpu) 524 { 525 if (pv_eoi_put_user(vcpu, KVM_PV_EOI_ENABLED) < 0) { 526 apic_debug("Can't set EOI MSR value: 0x%llx\n", 527 (unsigned long long)vcpu->arch.pv_eoi.msr_val); 528 return; 529 } 530 __set_bit(KVM_APIC_PV_EOI_PENDING, &vcpu->arch.apic_attention); 531 } 532 533 static void pv_eoi_clr_pending(struct kvm_vcpu *vcpu) 534 { 535 if (pv_eoi_put_user(vcpu, KVM_PV_EOI_DISABLED) < 0) { 536 apic_debug("Can't clear EOI MSR value: 0x%llx\n", 537 (unsigned long long)vcpu->arch.pv_eoi.msr_val); 538 return; 539 } 540 __clear_bit(KVM_APIC_PV_EOI_PENDING, &vcpu->arch.apic_attention); 541 } 542 543 void kvm_apic_update_tmr(struct kvm_vcpu *vcpu, u32 *tmr) 544 { 545 struct kvm_lapic *apic = vcpu->arch.apic; 546 int i; 547 548 for (i = 0; i < 8; i++) 549 apic_set_reg(apic, APIC_TMR + 0x10 * i, tmr[i]); 550 } 551 552 static void apic_update_ppr(struct kvm_lapic *apic) 553 { 554 u32 tpr, isrv, ppr, old_ppr; 555 int isr; 556 557 old_ppr = kvm_apic_get_reg(apic, APIC_PROCPRI); 558 tpr = kvm_apic_get_reg(apic, APIC_TASKPRI); 559 isr = apic_find_highest_isr(apic); 560 isrv = (isr != -1) ? isr : 0; 561 562 if ((tpr & 0xf0) >= (isrv & 0xf0)) 563 ppr = tpr & 0xff; 564 else 565 ppr = isrv & 0xf0; 566 567 apic_debug("vlapic %p, ppr 0x%x, isr 0x%x, isrv 0x%x", 568 apic, ppr, isr, isrv); 569 570 if (old_ppr != ppr) { 571 apic_set_reg(apic, APIC_PROCPRI, ppr); 572 if (ppr < old_ppr) 573 kvm_make_request(KVM_REQ_EVENT, apic->vcpu); 574 } 575 } 576 577 static void apic_set_tpr(struct kvm_lapic *apic, u32 tpr) 578 { 579 apic_set_reg(apic, APIC_TASKPRI, tpr); 580 apic_update_ppr(apic); 581 } 582 583 static int kvm_apic_broadcast(struct kvm_lapic *apic, u32 dest) 584 { 585 return dest == (apic_x2apic_mode(apic) ? 586 X2APIC_BROADCAST : APIC_BROADCAST); 587 } 588 589 int kvm_apic_match_physical_addr(struct kvm_lapic *apic, u32 dest) 590 { 591 return kvm_apic_id(apic) == dest || kvm_apic_broadcast(apic, dest); 592 } 593 594 int kvm_apic_match_logical_addr(struct kvm_lapic *apic, u32 mda) 595 { 596 int result = 0; 597 u32 logical_id; 598 599 if (kvm_apic_broadcast(apic, mda)) 600 return 1; 601 602 if (apic_x2apic_mode(apic)) { 603 logical_id = kvm_apic_get_reg(apic, APIC_LDR); 604 return logical_id & mda; 605 } 606 607 logical_id = GET_APIC_LOGICAL_ID(kvm_apic_get_reg(apic, APIC_LDR)); 608 609 switch (kvm_apic_get_reg(apic, APIC_DFR)) { 610 case APIC_DFR_FLAT: 611 if (logical_id & mda) 612 result = 1; 613 break; 614 case APIC_DFR_CLUSTER: 615 if (((logical_id >> 4) == (mda >> 0x4)) 616 && (logical_id & mda & 0xf)) 617 result = 1; 618 break; 619 default: 620 apic_debug("Bad DFR vcpu %d: %08x\n", 621 apic->vcpu->vcpu_id, kvm_apic_get_reg(apic, APIC_DFR)); 622 break; 623 } 624 625 return result; 626 } 627 628 int kvm_apic_match_dest(struct kvm_vcpu *vcpu, struct kvm_lapic *source, 629 int short_hand, unsigned int dest, int dest_mode) 630 { 631 int result = 0; 632 struct kvm_lapic *target = vcpu->arch.apic; 633 634 apic_debug("target %p, source %p, dest 0x%x, " 635 "dest_mode 0x%x, short_hand 0x%x\n", 636 target, source, dest, dest_mode, short_hand); 637 638 ASSERT(target); 639 switch (short_hand) { 640 case APIC_DEST_NOSHORT: 641 if (dest_mode == 0) 642 /* Physical mode. */ 643 result = kvm_apic_match_physical_addr(target, dest); 644 else 645 /* Logical mode. */ 646 result = kvm_apic_match_logical_addr(target, dest); 647 break; 648 case APIC_DEST_SELF: 649 result = (target == source); 650 break; 651 case APIC_DEST_ALLINC: 652 result = 1; 653 break; 654 case APIC_DEST_ALLBUT: 655 result = (target != source); 656 break; 657 default: 658 apic_debug("kvm: apic: Bad dest shorthand value %x\n", 659 short_hand); 660 break; 661 } 662 663 return result; 664 } 665 666 bool kvm_irq_delivery_to_apic_fast(struct kvm *kvm, struct kvm_lapic *src, 667 struct kvm_lapic_irq *irq, int *r, unsigned long *dest_map) 668 { 669 struct kvm_apic_map *map; 670 unsigned long bitmap = 1; 671 struct kvm_lapic **dst; 672 int i; 673 bool ret = false; 674 675 *r = -1; 676 677 if (irq->shorthand == APIC_DEST_SELF) { 678 *r = kvm_apic_set_irq(src->vcpu, irq, dest_map); 679 return true; 680 } 681 682 if (irq->shorthand) 683 return false; 684 685 rcu_read_lock(); 686 map = rcu_dereference(kvm->arch.apic_map); 687 688 if (!map) 689 goto out; 690 691 if (irq->dest_id == map->broadcast) 692 goto out; 693 694 ret = true; 695 696 if (irq->dest_mode == 0) { /* physical mode */ 697 if (irq->dest_id >= ARRAY_SIZE(map->phys_map)) 698 goto out; 699 700 dst = &map->phys_map[irq->dest_id]; 701 } else { 702 u32 mda = irq->dest_id << (32 - map->ldr_bits); 703 u16 cid = apic_cluster_id(map, mda); 704 705 if (cid >= ARRAY_SIZE(map->logical_map)) 706 goto out; 707 708 dst = map->logical_map[cid]; 709 710 bitmap = apic_logical_id(map, mda); 711 712 if (irq->delivery_mode == APIC_DM_LOWEST) { 713 int l = -1; 714 for_each_set_bit(i, &bitmap, 16) { 715 if (!dst[i]) 716 continue; 717 if (l < 0) 718 l = i; 719 else if (kvm_apic_compare_prio(dst[i]->vcpu, dst[l]->vcpu) < 0) 720 l = i; 721 } 722 723 bitmap = (l >= 0) ? 1 << l : 0; 724 } 725 } 726 727 for_each_set_bit(i, &bitmap, 16) { 728 if (!dst[i]) 729 continue; 730 if (*r < 0) 731 *r = 0; 732 *r += kvm_apic_set_irq(dst[i]->vcpu, irq, dest_map); 733 } 734 out: 735 rcu_read_unlock(); 736 return ret; 737 } 738 739 /* 740 * Add a pending IRQ into lapic. 741 * Return 1 if successfully added and 0 if discarded. 742 */ 743 static int __apic_accept_irq(struct kvm_lapic *apic, int delivery_mode, 744 int vector, int level, int trig_mode, 745 unsigned long *dest_map) 746 { 747 int result = 0; 748 struct kvm_vcpu *vcpu = apic->vcpu; 749 750 trace_kvm_apic_accept_irq(vcpu->vcpu_id, delivery_mode, 751 trig_mode, vector); 752 switch (delivery_mode) { 753 case APIC_DM_LOWEST: 754 vcpu->arch.apic_arb_prio++; 755 case APIC_DM_FIXED: 756 /* FIXME add logic for vcpu on reset */ 757 if (unlikely(!apic_enabled(apic))) 758 break; 759 760 result = 1; 761 762 if (dest_map) 763 __set_bit(vcpu->vcpu_id, dest_map); 764 765 if (kvm_x86_ops->deliver_posted_interrupt) 766 kvm_x86_ops->deliver_posted_interrupt(vcpu, vector); 767 else { 768 apic_set_irr(vector, apic); 769 770 kvm_make_request(KVM_REQ_EVENT, vcpu); 771 kvm_vcpu_kick(vcpu); 772 } 773 break; 774 775 case APIC_DM_REMRD: 776 result = 1; 777 vcpu->arch.pv.pv_unhalted = 1; 778 kvm_make_request(KVM_REQ_EVENT, vcpu); 779 kvm_vcpu_kick(vcpu); 780 break; 781 782 case APIC_DM_SMI: 783 apic_debug("Ignoring guest SMI\n"); 784 break; 785 786 case APIC_DM_NMI: 787 result = 1; 788 kvm_inject_nmi(vcpu); 789 kvm_vcpu_kick(vcpu); 790 break; 791 792 case APIC_DM_INIT: 793 if (!trig_mode || level) { 794 result = 1; 795 /* assumes that there are only KVM_APIC_INIT/SIPI */ 796 apic->pending_events = (1UL << KVM_APIC_INIT); 797 /* make sure pending_events is visible before sending 798 * the request */ 799 smp_wmb(); 800 kvm_make_request(KVM_REQ_EVENT, vcpu); 801 kvm_vcpu_kick(vcpu); 802 } else { 803 apic_debug("Ignoring de-assert INIT to vcpu %d\n", 804 vcpu->vcpu_id); 805 } 806 break; 807 808 case APIC_DM_STARTUP: 809 apic_debug("SIPI to vcpu %d vector 0x%02x\n", 810 vcpu->vcpu_id, vector); 811 result = 1; 812 apic->sipi_vector = vector; 813 /* make sure sipi_vector is visible for the receiver */ 814 smp_wmb(); 815 set_bit(KVM_APIC_SIPI, &apic->pending_events); 816 kvm_make_request(KVM_REQ_EVENT, vcpu); 817 kvm_vcpu_kick(vcpu); 818 break; 819 820 case APIC_DM_EXTINT: 821 /* 822 * Should only be called by kvm_apic_local_deliver() with LVT0, 823 * before NMI watchdog was enabled. Already handled by 824 * kvm_apic_accept_pic_intr(). 825 */ 826 break; 827 828 default: 829 printk(KERN_ERR "TODO: unsupported delivery mode %x\n", 830 delivery_mode); 831 break; 832 } 833 return result; 834 } 835 836 int kvm_apic_compare_prio(struct kvm_vcpu *vcpu1, struct kvm_vcpu *vcpu2) 837 { 838 return vcpu1->arch.apic_arb_prio - vcpu2->arch.apic_arb_prio; 839 } 840 841 static void kvm_ioapic_send_eoi(struct kvm_lapic *apic, int vector) 842 { 843 if (!(kvm_apic_get_reg(apic, APIC_SPIV) & APIC_SPIV_DIRECTED_EOI) && 844 kvm_ioapic_handles_vector(apic->vcpu->kvm, vector)) { 845 int trigger_mode; 846 if (apic_test_vector(vector, apic->regs + APIC_TMR)) 847 trigger_mode = IOAPIC_LEVEL_TRIG; 848 else 849 trigger_mode = IOAPIC_EDGE_TRIG; 850 kvm_ioapic_update_eoi(apic->vcpu, vector, trigger_mode); 851 } 852 } 853 854 static int apic_set_eoi(struct kvm_lapic *apic) 855 { 856 int vector = apic_find_highest_isr(apic); 857 858 trace_kvm_eoi(apic, vector); 859 860 /* 861 * Not every write EOI will has corresponding ISR, 862 * one example is when Kernel check timer on setup_IO_APIC 863 */ 864 if (vector == -1) 865 return vector; 866 867 apic_clear_isr(vector, apic); 868 apic_update_ppr(apic); 869 870 kvm_ioapic_send_eoi(apic, vector); 871 kvm_make_request(KVM_REQ_EVENT, apic->vcpu); 872 return vector; 873 } 874 875 /* 876 * this interface assumes a trap-like exit, which has already finished 877 * desired side effect including vISR and vPPR update. 878 */ 879 void kvm_apic_set_eoi_accelerated(struct kvm_vcpu *vcpu, int vector) 880 { 881 struct kvm_lapic *apic = vcpu->arch.apic; 882 883 trace_kvm_eoi(apic, vector); 884 885 kvm_ioapic_send_eoi(apic, vector); 886 kvm_make_request(KVM_REQ_EVENT, apic->vcpu); 887 } 888 EXPORT_SYMBOL_GPL(kvm_apic_set_eoi_accelerated); 889 890 static void apic_send_ipi(struct kvm_lapic *apic) 891 { 892 u32 icr_low = kvm_apic_get_reg(apic, APIC_ICR); 893 u32 icr_high = kvm_apic_get_reg(apic, APIC_ICR2); 894 struct kvm_lapic_irq irq; 895 896 irq.vector = icr_low & APIC_VECTOR_MASK; 897 irq.delivery_mode = icr_low & APIC_MODE_MASK; 898 irq.dest_mode = icr_low & APIC_DEST_MASK; 899 irq.level = icr_low & APIC_INT_ASSERT; 900 irq.trig_mode = icr_low & APIC_INT_LEVELTRIG; 901 irq.shorthand = icr_low & APIC_SHORT_MASK; 902 if (apic_x2apic_mode(apic)) 903 irq.dest_id = icr_high; 904 else 905 irq.dest_id = GET_APIC_DEST_FIELD(icr_high); 906 907 trace_kvm_apic_ipi(icr_low, irq.dest_id); 908 909 apic_debug("icr_high 0x%x, icr_low 0x%x, " 910 "short_hand 0x%x, dest 0x%x, trig_mode 0x%x, level 0x%x, " 911 "dest_mode 0x%x, delivery_mode 0x%x, vector 0x%x\n", 912 icr_high, icr_low, irq.shorthand, irq.dest_id, 913 irq.trig_mode, irq.level, irq.dest_mode, irq.delivery_mode, 914 irq.vector); 915 916 kvm_irq_delivery_to_apic(apic->vcpu->kvm, apic, &irq, NULL); 917 } 918 919 static u32 apic_get_tmcct(struct kvm_lapic *apic) 920 { 921 ktime_t remaining; 922 s64 ns; 923 u32 tmcct; 924 925 ASSERT(apic != NULL); 926 927 /* if initial count is 0, current count should also be 0 */ 928 if (kvm_apic_get_reg(apic, APIC_TMICT) == 0 || 929 apic->lapic_timer.period == 0) 930 return 0; 931 932 remaining = hrtimer_get_remaining(&apic->lapic_timer.timer); 933 if (ktime_to_ns(remaining) < 0) 934 remaining = ktime_set(0, 0); 935 936 ns = mod_64(ktime_to_ns(remaining), apic->lapic_timer.period); 937 tmcct = div64_u64(ns, 938 (APIC_BUS_CYCLE_NS * apic->divide_count)); 939 940 return tmcct; 941 } 942 943 static void __report_tpr_access(struct kvm_lapic *apic, bool write) 944 { 945 struct kvm_vcpu *vcpu = apic->vcpu; 946 struct kvm_run *run = vcpu->run; 947 948 kvm_make_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu); 949 run->tpr_access.rip = kvm_rip_read(vcpu); 950 run->tpr_access.is_write = write; 951 } 952 953 static inline void report_tpr_access(struct kvm_lapic *apic, bool write) 954 { 955 if (apic->vcpu->arch.tpr_access_reporting) 956 __report_tpr_access(apic, write); 957 } 958 959 static u32 __apic_read(struct kvm_lapic *apic, unsigned int offset) 960 { 961 u32 val = 0; 962 963 if (offset >= LAPIC_MMIO_LENGTH) 964 return 0; 965 966 switch (offset) { 967 case APIC_ID: 968 if (apic_x2apic_mode(apic)) 969 val = kvm_apic_id(apic); 970 else 971 val = kvm_apic_id(apic) << 24; 972 break; 973 case APIC_ARBPRI: 974 apic_debug("Access APIC ARBPRI register which is for P6\n"); 975 break; 976 977 case APIC_TMCCT: /* Timer CCR */ 978 if (apic_lvtt_tscdeadline(apic)) 979 return 0; 980 981 val = apic_get_tmcct(apic); 982 break; 983 case APIC_PROCPRI: 984 apic_update_ppr(apic); 985 val = kvm_apic_get_reg(apic, offset); 986 break; 987 case APIC_TASKPRI: 988 report_tpr_access(apic, false); 989 /* fall thru */ 990 default: 991 val = kvm_apic_get_reg(apic, offset); 992 break; 993 } 994 995 return val; 996 } 997 998 static inline struct kvm_lapic *to_lapic(struct kvm_io_device *dev) 999 { 1000 return container_of(dev, struct kvm_lapic, dev); 1001 } 1002 1003 static int apic_reg_read(struct kvm_lapic *apic, u32 offset, int len, 1004 void *data) 1005 { 1006 unsigned char alignment = offset & 0xf; 1007 u32 result; 1008 /* this bitmask has a bit cleared for each reserved register */ 1009 static const u64 rmask = 0x43ff01ffffffe70cULL; 1010 1011 if ((alignment + len) > 4) { 1012 apic_debug("KVM_APIC_READ: alignment error %x %d\n", 1013 offset, len); 1014 return 1; 1015 } 1016 1017 if (offset > 0x3f0 || !(rmask & (1ULL << (offset >> 4)))) { 1018 apic_debug("KVM_APIC_READ: read reserved register %x\n", 1019 offset); 1020 return 1; 1021 } 1022 1023 result = __apic_read(apic, offset & ~0xf); 1024 1025 trace_kvm_apic_read(offset, result); 1026 1027 switch (len) { 1028 case 1: 1029 case 2: 1030 case 4: 1031 memcpy(data, (char *)&result + alignment, len); 1032 break; 1033 default: 1034 printk(KERN_ERR "Local APIC read with len = %x, " 1035 "should be 1,2, or 4 instead\n", len); 1036 break; 1037 } 1038 return 0; 1039 } 1040 1041 static int apic_mmio_in_range(struct kvm_lapic *apic, gpa_t addr) 1042 { 1043 return kvm_apic_hw_enabled(apic) && 1044 addr >= apic->base_address && 1045 addr < apic->base_address + LAPIC_MMIO_LENGTH; 1046 } 1047 1048 static int apic_mmio_read(struct kvm_io_device *this, 1049 gpa_t address, int len, void *data) 1050 { 1051 struct kvm_lapic *apic = to_lapic(this); 1052 u32 offset = address - apic->base_address; 1053 1054 if (!apic_mmio_in_range(apic, address)) 1055 return -EOPNOTSUPP; 1056 1057 apic_reg_read(apic, offset, len, data); 1058 1059 return 0; 1060 } 1061 1062 static void update_divide_count(struct kvm_lapic *apic) 1063 { 1064 u32 tmp1, tmp2, tdcr; 1065 1066 tdcr = kvm_apic_get_reg(apic, APIC_TDCR); 1067 tmp1 = tdcr & 0xf; 1068 tmp2 = ((tmp1 & 0x3) | ((tmp1 & 0x8) >> 1)) + 1; 1069 apic->divide_count = 0x1 << (tmp2 & 0x7); 1070 1071 apic_debug("timer divide count is 0x%x\n", 1072 apic->divide_count); 1073 } 1074 1075 static void apic_timer_expired(struct kvm_lapic *apic) 1076 { 1077 struct kvm_vcpu *vcpu = apic->vcpu; 1078 wait_queue_head_t *q = &vcpu->wq; 1079 1080 /* 1081 * Note: KVM_REQ_PENDING_TIMER is implicitly checked in 1082 * vcpu_enter_guest. 1083 */ 1084 if (atomic_read(&apic->lapic_timer.pending)) 1085 return; 1086 1087 atomic_inc(&apic->lapic_timer.pending); 1088 /* FIXME: this code should not know anything about vcpus */ 1089 kvm_make_request(KVM_REQ_PENDING_TIMER, vcpu); 1090 1091 if (waitqueue_active(q)) 1092 wake_up_interruptible(q); 1093 } 1094 1095 static void start_apic_timer(struct kvm_lapic *apic) 1096 { 1097 ktime_t now; 1098 atomic_set(&apic->lapic_timer.pending, 0); 1099 1100 if (apic_lvtt_period(apic) || apic_lvtt_oneshot(apic)) { 1101 /* lapic timer in oneshot or periodic mode */ 1102 now = apic->lapic_timer.timer.base->get_time(); 1103 apic->lapic_timer.period = (u64)kvm_apic_get_reg(apic, APIC_TMICT) 1104 * APIC_BUS_CYCLE_NS * apic->divide_count; 1105 1106 if (!apic->lapic_timer.period) 1107 return; 1108 /* 1109 * Do not allow the guest to program periodic timers with small 1110 * interval, since the hrtimers are not throttled by the host 1111 * scheduler. 1112 */ 1113 if (apic_lvtt_period(apic)) { 1114 s64 min_period = min_timer_period_us * 1000LL; 1115 1116 if (apic->lapic_timer.period < min_period) { 1117 pr_info_ratelimited( 1118 "kvm: vcpu %i: requested %lld ns " 1119 "lapic timer period limited to %lld ns\n", 1120 apic->vcpu->vcpu_id, 1121 apic->lapic_timer.period, min_period); 1122 apic->lapic_timer.period = min_period; 1123 } 1124 } 1125 1126 hrtimer_start(&apic->lapic_timer.timer, 1127 ktime_add_ns(now, apic->lapic_timer.period), 1128 HRTIMER_MODE_ABS); 1129 1130 apic_debug("%s: bus cycle is %" PRId64 "ns, now 0x%016" 1131 PRIx64 ", " 1132 "timer initial count 0x%x, period %lldns, " 1133 "expire @ 0x%016" PRIx64 ".\n", __func__, 1134 APIC_BUS_CYCLE_NS, ktime_to_ns(now), 1135 kvm_apic_get_reg(apic, APIC_TMICT), 1136 apic->lapic_timer.period, 1137 ktime_to_ns(ktime_add_ns(now, 1138 apic->lapic_timer.period))); 1139 } else if (apic_lvtt_tscdeadline(apic)) { 1140 /* lapic timer in tsc deadline mode */ 1141 u64 guest_tsc, tscdeadline = apic->lapic_timer.tscdeadline; 1142 u64 ns = 0; 1143 struct kvm_vcpu *vcpu = apic->vcpu; 1144 unsigned long this_tsc_khz = vcpu->arch.virtual_tsc_khz; 1145 unsigned long flags; 1146 1147 if (unlikely(!tscdeadline || !this_tsc_khz)) 1148 return; 1149 1150 local_irq_save(flags); 1151 1152 now = apic->lapic_timer.timer.base->get_time(); 1153 guest_tsc = kvm_x86_ops->read_l1_tsc(vcpu, native_read_tsc()); 1154 if (likely(tscdeadline > guest_tsc)) { 1155 ns = (tscdeadline - guest_tsc) * 1000000ULL; 1156 do_div(ns, this_tsc_khz); 1157 hrtimer_start(&apic->lapic_timer.timer, 1158 ktime_add_ns(now, ns), HRTIMER_MODE_ABS); 1159 } else 1160 apic_timer_expired(apic); 1161 1162 local_irq_restore(flags); 1163 } 1164 } 1165 1166 static void apic_manage_nmi_watchdog(struct kvm_lapic *apic, u32 lvt0_val) 1167 { 1168 int nmi_wd_enabled = apic_lvt_nmi_mode(kvm_apic_get_reg(apic, APIC_LVT0)); 1169 1170 if (apic_lvt_nmi_mode(lvt0_val)) { 1171 if (!nmi_wd_enabled) { 1172 apic_debug("Receive NMI setting on APIC_LVT0 " 1173 "for cpu %d\n", apic->vcpu->vcpu_id); 1174 apic->vcpu->kvm->arch.vapics_in_nmi_mode++; 1175 } 1176 } else if (nmi_wd_enabled) 1177 apic->vcpu->kvm->arch.vapics_in_nmi_mode--; 1178 } 1179 1180 static int apic_reg_write(struct kvm_lapic *apic, u32 reg, u32 val) 1181 { 1182 int ret = 0; 1183 1184 trace_kvm_apic_write(reg, val); 1185 1186 switch (reg) { 1187 case APIC_ID: /* Local APIC ID */ 1188 if (!apic_x2apic_mode(apic)) 1189 kvm_apic_set_id(apic, val >> 24); 1190 else 1191 ret = 1; 1192 break; 1193 1194 case APIC_TASKPRI: 1195 report_tpr_access(apic, true); 1196 apic_set_tpr(apic, val & 0xff); 1197 break; 1198 1199 case APIC_EOI: 1200 apic_set_eoi(apic); 1201 break; 1202 1203 case APIC_LDR: 1204 if (!apic_x2apic_mode(apic)) 1205 kvm_apic_set_ldr(apic, val & APIC_LDR_MASK); 1206 else 1207 ret = 1; 1208 break; 1209 1210 case APIC_DFR: 1211 if (!apic_x2apic_mode(apic)) { 1212 apic_set_reg(apic, APIC_DFR, val | 0x0FFFFFFF); 1213 recalculate_apic_map(apic->vcpu->kvm); 1214 } else 1215 ret = 1; 1216 break; 1217 1218 case APIC_SPIV: { 1219 u32 mask = 0x3ff; 1220 if (kvm_apic_get_reg(apic, APIC_LVR) & APIC_LVR_DIRECTED_EOI) 1221 mask |= APIC_SPIV_DIRECTED_EOI; 1222 apic_set_spiv(apic, val & mask); 1223 if (!(val & APIC_SPIV_APIC_ENABLED)) { 1224 int i; 1225 u32 lvt_val; 1226 1227 for (i = 0; i < APIC_LVT_NUM; i++) { 1228 lvt_val = kvm_apic_get_reg(apic, 1229 APIC_LVTT + 0x10 * i); 1230 apic_set_reg(apic, APIC_LVTT + 0x10 * i, 1231 lvt_val | APIC_LVT_MASKED); 1232 } 1233 atomic_set(&apic->lapic_timer.pending, 0); 1234 1235 } 1236 break; 1237 } 1238 case APIC_ICR: 1239 /* No delay here, so we always clear the pending bit */ 1240 apic_set_reg(apic, APIC_ICR, val & ~(1 << 12)); 1241 apic_send_ipi(apic); 1242 break; 1243 1244 case APIC_ICR2: 1245 if (!apic_x2apic_mode(apic)) 1246 val &= 0xff000000; 1247 apic_set_reg(apic, APIC_ICR2, val); 1248 break; 1249 1250 case APIC_LVT0: 1251 apic_manage_nmi_watchdog(apic, val); 1252 case APIC_LVTTHMR: 1253 case APIC_LVTPC: 1254 case APIC_LVT1: 1255 case APIC_LVTERR: 1256 /* TODO: Check vector */ 1257 if (!kvm_apic_sw_enabled(apic)) 1258 val |= APIC_LVT_MASKED; 1259 1260 val &= apic_lvt_mask[(reg - APIC_LVTT) >> 4]; 1261 apic_set_reg(apic, reg, val); 1262 1263 break; 1264 1265 case APIC_LVTT: { 1266 u32 timer_mode = val & apic->lapic_timer.timer_mode_mask; 1267 1268 if (apic->lapic_timer.timer_mode != timer_mode) { 1269 apic->lapic_timer.timer_mode = timer_mode; 1270 hrtimer_cancel(&apic->lapic_timer.timer); 1271 } 1272 1273 if (!kvm_apic_sw_enabled(apic)) 1274 val |= APIC_LVT_MASKED; 1275 val &= (apic_lvt_mask[0] | apic->lapic_timer.timer_mode_mask); 1276 apic_set_reg(apic, APIC_LVTT, val); 1277 break; 1278 } 1279 1280 case APIC_TMICT: 1281 if (apic_lvtt_tscdeadline(apic)) 1282 break; 1283 1284 hrtimer_cancel(&apic->lapic_timer.timer); 1285 apic_set_reg(apic, APIC_TMICT, val); 1286 start_apic_timer(apic); 1287 break; 1288 1289 case APIC_TDCR: 1290 if (val & 4) 1291 apic_debug("KVM_WRITE:TDCR %x\n", val); 1292 apic_set_reg(apic, APIC_TDCR, val); 1293 update_divide_count(apic); 1294 break; 1295 1296 case APIC_ESR: 1297 if (apic_x2apic_mode(apic) && val != 0) { 1298 apic_debug("KVM_WRITE:ESR not zero %x\n", val); 1299 ret = 1; 1300 } 1301 break; 1302 1303 case APIC_SELF_IPI: 1304 if (apic_x2apic_mode(apic)) { 1305 apic_reg_write(apic, APIC_ICR, 0x40000 | (val & 0xff)); 1306 } else 1307 ret = 1; 1308 break; 1309 default: 1310 ret = 1; 1311 break; 1312 } 1313 if (ret) 1314 apic_debug("Local APIC Write to read-only register %x\n", reg); 1315 return ret; 1316 } 1317 1318 static int apic_mmio_write(struct kvm_io_device *this, 1319 gpa_t address, int len, const void *data) 1320 { 1321 struct kvm_lapic *apic = to_lapic(this); 1322 unsigned int offset = address - apic->base_address; 1323 u32 val; 1324 1325 if (!apic_mmio_in_range(apic, address)) 1326 return -EOPNOTSUPP; 1327 1328 /* 1329 * APIC register must be aligned on 128-bits boundary. 1330 * 32/64/128 bits registers must be accessed thru 32 bits. 1331 * Refer SDM 8.4.1 1332 */ 1333 if (len != 4 || (offset & 0xf)) { 1334 /* Don't shout loud, $infamous_os would cause only noise. */ 1335 apic_debug("apic write: bad size=%d %lx\n", len, (long)address); 1336 return 0; 1337 } 1338 1339 val = *(u32*)data; 1340 1341 /* too common printing */ 1342 if (offset != APIC_EOI) 1343 apic_debug("%s: offset 0x%x with length 0x%x, and value is " 1344 "0x%x\n", __func__, offset, len, val); 1345 1346 apic_reg_write(apic, offset & 0xff0, val); 1347 1348 return 0; 1349 } 1350 1351 void kvm_lapic_set_eoi(struct kvm_vcpu *vcpu) 1352 { 1353 if (kvm_vcpu_has_lapic(vcpu)) 1354 apic_reg_write(vcpu->arch.apic, APIC_EOI, 0); 1355 } 1356 EXPORT_SYMBOL_GPL(kvm_lapic_set_eoi); 1357 1358 /* emulate APIC access in a trap manner */ 1359 void kvm_apic_write_nodecode(struct kvm_vcpu *vcpu, u32 offset) 1360 { 1361 u32 val = 0; 1362 1363 /* hw has done the conditional check and inst decode */ 1364 offset &= 0xff0; 1365 1366 apic_reg_read(vcpu->arch.apic, offset, 4, &val); 1367 1368 /* TODO: optimize to just emulate side effect w/o one more write */ 1369 apic_reg_write(vcpu->arch.apic, offset, val); 1370 } 1371 EXPORT_SYMBOL_GPL(kvm_apic_write_nodecode); 1372 1373 void kvm_free_lapic(struct kvm_vcpu *vcpu) 1374 { 1375 struct kvm_lapic *apic = vcpu->arch.apic; 1376 1377 if (!vcpu->arch.apic) 1378 return; 1379 1380 hrtimer_cancel(&apic->lapic_timer.timer); 1381 1382 if (!(vcpu->arch.apic_base & MSR_IA32_APICBASE_ENABLE)) 1383 static_key_slow_dec_deferred(&apic_hw_disabled); 1384 1385 if (!apic->sw_enabled) 1386 static_key_slow_dec_deferred(&apic_sw_disabled); 1387 1388 if (apic->regs) 1389 free_page((unsigned long)apic->regs); 1390 1391 kfree(apic); 1392 } 1393 1394 /* 1395 *---------------------------------------------------------------------- 1396 * LAPIC interface 1397 *---------------------------------------------------------------------- 1398 */ 1399 1400 u64 kvm_get_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu) 1401 { 1402 struct kvm_lapic *apic = vcpu->arch.apic; 1403 1404 if (!kvm_vcpu_has_lapic(vcpu) || apic_lvtt_oneshot(apic) || 1405 apic_lvtt_period(apic)) 1406 return 0; 1407 1408 return apic->lapic_timer.tscdeadline; 1409 } 1410 1411 void kvm_set_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu, u64 data) 1412 { 1413 struct kvm_lapic *apic = vcpu->arch.apic; 1414 1415 if (!kvm_vcpu_has_lapic(vcpu) || apic_lvtt_oneshot(apic) || 1416 apic_lvtt_period(apic)) 1417 return; 1418 1419 hrtimer_cancel(&apic->lapic_timer.timer); 1420 apic->lapic_timer.tscdeadline = data; 1421 start_apic_timer(apic); 1422 } 1423 1424 void kvm_lapic_set_tpr(struct kvm_vcpu *vcpu, unsigned long cr8) 1425 { 1426 struct kvm_lapic *apic = vcpu->arch.apic; 1427 1428 if (!kvm_vcpu_has_lapic(vcpu)) 1429 return; 1430 1431 apic_set_tpr(apic, ((cr8 & 0x0f) << 4) 1432 | (kvm_apic_get_reg(apic, APIC_TASKPRI) & 4)); 1433 } 1434 1435 u64 kvm_lapic_get_cr8(struct kvm_vcpu *vcpu) 1436 { 1437 u64 tpr; 1438 1439 if (!kvm_vcpu_has_lapic(vcpu)) 1440 return 0; 1441 1442 tpr = (u64) kvm_apic_get_reg(vcpu->arch.apic, APIC_TASKPRI); 1443 1444 return (tpr & 0xf0) >> 4; 1445 } 1446 1447 void kvm_lapic_set_base(struct kvm_vcpu *vcpu, u64 value) 1448 { 1449 u64 old_value = vcpu->arch.apic_base; 1450 struct kvm_lapic *apic = vcpu->arch.apic; 1451 1452 if (!apic) { 1453 value |= MSR_IA32_APICBASE_BSP; 1454 vcpu->arch.apic_base = value; 1455 return; 1456 } 1457 1458 if (!kvm_vcpu_is_bsp(apic->vcpu)) 1459 value &= ~MSR_IA32_APICBASE_BSP; 1460 vcpu->arch.apic_base = value; 1461 1462 /* update jump label if enable bit changes */ 1463 if ((old_value ^ value) & MSR_IA32_APICBASE_ENABLE) { 1464 if (value & MSR_IA32_APICBASE_ENABLE) 1465 static_key_slow_dec_deferred(&apic_hw_disabled); 1466 else 1467 static_key_slow_inc(&apic_hw_disabled.key); 1468 recalculate_apic_map(vcpu->kvm); 1469 } 1470 1471 if ((old_value ^ value) & X2APIC_ENABLE) { 1472 if (value & X2APIC_ENABLE) { 1473 u32 id = kvm_apic_id(apic); 1474 u32 ldr = ((id >> 4) << 16) | (1 << (id & 0xf)); 1475 kvm_apic_set_ldr(apic, ldr); 1476 kvm_x86_ops->set_virtual_x2apic_mode(vcpu, true); 1477 } else 1478 kvm_x86_ops->set_virtual_x2apic_mode(vcpu, false); 1479 } 1480 1481 apic->base_address = apic->vcpu->arch.apic_base & 1482 MSR_IA32_APICBASE_BASE; 1483 1484 if ((value & MSR_IA32_APICBASE_ENABLE) && 1485 apic->base_address != APIC_DEFAULT_PHYS_BASE) 1486 pr_warn_once("APIC base relocation is unsupported by KVM"); 1487 1488 /* with FSB delivery interrupt, we can restart APIC functionality */ 1489 apic_debug("apic base msr is 0x%016" PRIx64 ", and base address is " 1490 "0x%lx.\n", apic->vcpu->arch.apic_base, apic->base_address); 1491 1492 } 1493 1494 void kvm_lapic_reset(struct kvm_vcpu *vcpu) 1495 { 1496 struct kvm_lapic *apic; 1497 int i; 1498 1499 apic_debug("%s\n", __func__); 1500 1501 ASSERT(vcpu); 1502 apic = vcpu->arch.apic; 1503 ASSERT(apic != NULL); 1504 1505 /* Stop the timer in case it's a reset to an active apic */ 1506 hrtimer_cancel(&apic->lapic_timer.timer); 1507 1508 kvm_apic_set_id(apic, vcpu->vcpu_id); 1509 kvm_apic_set_version(apic->vcpu); 1510 1511 for (i = 0; i < APIC_LVT_NUM; i++) 1512 apic_set_reg(apic, APIC_LVTT + 0x10 * i, APIC_LVT_MASKED); 1513 apic->lapic_timer.timer_mode = 0; 1514 apic_set_reg(apic, APIC_LVT0, 1515 SET_APIC_DELIVERY_MODE(0, APIC_MODE_EXTINT)); 1516 1517 apic_set_reg(apic, APIC_DFR, 0xffffffffU); 1518 apic_set_spiv(apic, 0xff); 1519 apic_set_reg(apic, APIC_TASKPRI, 0); 1520 kvm_apic_set_ldr(apic, 0); 1521 apic_set_reg(apic, APIC_ESR, 0); 1522 apic_set_reg(apic, APIC_ICR, 0); 1523 apic_set_reg(apic, APIC_ICR2, 0); 1524 apic_set_reg(apic, APIC_TDCR, 0); 1525 apic_set_reg(apic, APIC_TMICT, 0); 1526 for (i = 0; i < 8; i++) { 1527 apic_set_reg(apic, APIC_IRR + 0x10 * i, 0); 1528 apic_set_reg(apic, APIC_ISR + 0x10 * i, 0); 1529 apic_set_reg(apic, APIC_TMR + 0x10 * i, 0); 1530 } 1531 apic->irr_pending = kvm_apic_vid_enabled(vcpu->kvm); 1532 apic->isr_count = kvm_apic_vid_enabled(vcpu->kvm); 1533 apic->highest_isr_cache = -1; 1534 update_divide_count(apic); 1535 atomic_set(&apic->lapic_timer.pending, 0); 1536 if (kvm_vcpu_is_bsp(vcpu)) 1537 kvm_lapic_set_base(vcpu, 1538 vcpu->arch.apic_base | MSR_IA32_APICBASE_BSP); 1539 vcpu->arch.pv_eoi.msr_val = 0; 1540 apic_update_ppr(apic); 1541 1542 vcpu->arch.apic_arb_prio = 0; 1543 vcpu->arch.apic_attention = 0; 1544 1545 apic_debug("%s: vcpu=%p, id=%d, base_msr=" 1546 "0x%016" PRIx64 ", base_address=0x%0lx.\n", __func__, 1547 vcpu, kvm_apic_id(apic), 1548 vcpu->arch.apic_base, apic->base_address); 1549 } 1550 1551 /* 1552 *---------------------------------------------------------------------- 1553 * timer interface 1554 *---------------------------------------------------------------------- 1555 */ 1556 1557 static bool lapic_is_periodic(struct kvm_lapic *apic) 1558 { 1559 return apic_lvtt_period(apic); 1560 } 1561 1562 int apic_has_pending_timer(struct kvm_vcpu *vcpu) 1563 { 1564 struct kvm_lapic *apic = vcpu->arch.apic; 1565 1566 if (kvm_vcpu_has_lapic(vcpu) && apic_enabled(apic) && 1567 apic_lvt_enabled(apic, APIC_LVTT)) 1568 return atomic_read(&apic->lapic_timer.pending); 1569 1570 return 0; 1571 } 1572 1573 int kvm_apic_local_deliver(struct kvm_lapic *apic, int lvt_type) 1574 { 1575 u32 reg = kvm_apic_get_reg(apic, lvt_type); 1576 int vector, mode, trig_mode; 1577 1578 if (kvm_apic_hw_enabled(apic) && !(reg & APIC_LVT_MASKED)) { 1579 vector = reg & APIC_VECTOR_MASK; 1580 mode = reg & APIC_MODE_MASK; 1581 trig_mode = reg & APIC_LVT_LEVEL_TRIGGER; 1582 return __apic_accept_irq(apic, mode, vector, 1, trig_mode, 1583 NULL); 1584 } 1585 return 0; 1586 } 1587 1588 void kvm_apic_nmi_wd_deliver(struct kvm_vcpu *vcpu) 1589 { 1590 struct kvm_lapic *apic = vcpu->arch.apic; 1591 1592 if (apic) 1593 kvm_apic_local_deliver(apic, APIC_LVT0); 1594 } 1595 1596 static const struct kvm_io_device_ops apic_mmio_ops = { 1597 .read = apic_mmio_read, 1598 .write = apic_mmio_write, 1599 }; 1600 1601 static enum hrtimer_restart apic_timer_fn(struct hrtimer *data) 1602 { 1603 struct kvm_timer *ktimer = container_of(data, struct kvm_timer, timer); 1604 struct kvm_lapic *apic = container_of(ktimer, struct kvm_lapic, lapic_timer); 1605 1606 apic_timer_expired(apic); 1607 1608 if (lapic_is_periodic(apic)) { 1609 hrtimer_add_expires_ns(&ktimer->timer, ktimer->period); 1610 return HRTIMER_RESTART; 1611 } else 1612 return HRTIMER_NORESTART; 1613 } 1614 1615 int kvm_create_lapic(struct kvm_vcpu *vcpu) 1616 { 1617 struct kvm_lapic *apic; 1618 1619 ASSERT(vcpu != NULL); 1620 apic_debug("apic_init %d\n", vcpu->vcpu_id); 1621 1622 apic = kzalloc(sizeof(*apic), GFP_KERNEL); 1623 if (!apic) 1624 goto nomem; 1625 1626 vcpu->arch.apic = apic; 1627 1628 apic->regs = (void *)get_zeroed_page(GFP_KERNEL); 1629 if (!apic->regs) { 1630 printk(KERN_ERR "malloc apic regs error for vcpu %x\n", 1631 vcpu->vcpu_id); 1632 goto nomem_free_apic; 1633 } 1634 apic->vcpu = vcpu; 1635 1636 hrtimer_init(&apic->lapic_timer.timer, CLOCK_MONOTONIC, 1637 HRTIMER_MODE_ABS); 1638 apic->lapic_timer.timer.function = apic_timer_fn; 1639 1640 /* 1641 * APIC is created enabled. This will prevent kvm_lapic_set_base from 1642 * thinking that APIC satet has changed. 1643 */ 1644 vcpu->arch.apic_base = MSR_IA32_APICBASE_ENABLE; 1645 kvm_lapic_set_base(vcpu, 1646 APIC_DEFAULT_PHYS_BASE | MSR_IA32_APICBASE_ENABLE); 1647 1648 static_key_slow_inc(&apic_sw_disabled.key); /* sw disabled at reset */ 1649 kvm_lapic_reset(vcpu); 1650 kvm_iodevice_init(&apic->dev, &apic_mmio_ops); 1651 1652 return 0; 1653 nomem_free_apic: 1654 kfree(apic); 1655 nomem: 1656 return -ENOMEM; 1657 } 1658 1659 int kvm_apic_has_interrupt(struct kvm_vcpu *vcpu) 1660 { 1661 struct kvm_lapic *apic = vcpu->arch.apic; 1662 int highest_irr; 1663 1664 if (!kvm_vcpu_has_lapic(vcpu) || !apic_enabled(apic)) 1665 return -1; 1666 1667 apic_update_ppr(apic); 1668 highest_irr = apic_find_highest_irr(apic); 1669 if ((highest_irr == -1) || 1670 ((highest_irr & 0xF0) <= kvm_apic_get_reg(apic, APIC_PROCPRI))) 1671 return -1; 1672 return highest_irr; 1673 } 1674 1675 int kvm_apic_accept_pic_intr(struct kvm_vcpu *vcpu) 1676 { 1677 u32 lvt0 = kvm_apic_get_reg(vcpu->arch.apic, APIC_LVT0); 1678 int r = 0; 1679 1680 if (!kvm_apic_hw_enabled(vcpu->arch.apic)) 1681 r = 1; 1682 if ((lvt0 & APIC_LVT_MASKED) == 0 && 1683 GET_APIC_DELIVERY_MODE(lvt0) == APIC_MODE_EXTINT) 1684 r = 1; 1685 return r; 1686 } 1687 1688 void kvm_inject_apic_timer_irqs(struct kvm_vcpu *vcpu) 1689 { 1690 struct kvm_lapic *apic = vcpu->arch.apic; 1691 1692 if (!kvm_vcpu_has_lapic(vcpu)) 1693 return; 1694 1695 if (atomic_read(&apic->lapic_timer.pending) > 0) { 1696 kvm_apic_local_deliver(apic, APIC_LVTT); 1697 if (apic_lvtt_tscdeadline(apic)) 1698 apic->lapic_timer.tscdeadline = 0; 1699 atomic_set(&apic->lapic_timer.pending, 0); 1700 } 1701 } 1702 1703 int kvm_get_apic_interrupt(struct kvm_vcpu *vcpu) 1704 { 1705 int vector = kvm_apic_has_interrupt(vcpu); 1706 struct kvm_lapic *apic = vcpu->arch.apic; 1707 1708 if (vector == -1) 1709 return -1; 1710 1711 /* 1712 * We get here even with APIC virtualization enabled, if doing 1713 * nested virtualization and L1 runs with the "acknowledge interrupt 1714 * on exit" mode. Then we cannot inject the interrupt via RVI, 1715 * because the process would deliver it through the IDT. 1716 */ 1717 1718 apic_set_isr(vector, apic); 1719 apic_update_ppr(apic); 1720 apic_clear_irr(vector, apic); 1721 return vector; 1722 } 1723 1724 void kvm_apic_post_state_restore(struct kvm_vcpu *vcpu, 1725 struct kvm_lapic_state *s) 1726 { 1727 struct kvm_lapic *apic = vcpu->arch.apic; 1728 1729 kvm_lapic_set_base(vcpu, vcpu->arch.apic_base); 1730 /* set SPIV separately to get count of SW disabled APICs right */ 1731 apic_set_spiv(apic, *((u32 *)(s->regs + APIC_SPIV))); 1732 memcpy(vcpu->arch.apic->regs, s->regs, sizeof *s); 1733 /* call kvm_apic_set_id() to put apic into apic_map */ 1734 kvm_apic_set_id(apic, kvm_apic_id(apic)); 1735 kvm_apic_set_version(vcpu); 1736 1737 apic_update_ppr(apic); 1738 hrtimer_cancel(&apic->lapic_timer.timer); 1739 update_divide_count(apic); 1740 start_apic_timer(apic); 1741 apic->irr_pending = true; 1742 apic->isr_count = kvm_apic_vid_enabled(vcpu->kvm) ? 1743 1 : count_vectors(apic->regs + APIC_ISR); 1744 apic->highest_isr_cache = -1; 1745 if (kvm_x86_ops->hwapic_irr_update) 1746 kvm_x86_ops->hwapic_irr_update(vcpu, 1747 apic_find_highest_irr(apic)); 1748 kvm_x86_ops->hwapic_isr_update(vcpu->kvm, apic_find_highest_isr(apic)); 1749 kvm_make_request(KVM_REQ_EVENT, vcpu); 1750 kvm_rtc_eoi_tracking_restore_one(vcpu); 1751 } 1752 1753 void __kvm_migrate_apic_timer(struct kvm_vcpu *vcpu) 1754 { 1755 struct hrtimer *timer; 1756 1757 if (!kvm_vcpu_has_lapic(vcpu)) 1758 return; 1759 1760 timer = &vcpu->arch.apic->lapic_timer.timer; 1761 if (hrtimer_cancel(timer)) 1762 hrtimer_start_expires(timer, HRTIMER_MODE_ABS); 1763 } 1764 1765 /* 1766 * apic_sync_pv_eoi_from_guest - called on vmexit or cancel interrupt 1767 * 1768 * Detect whether guest triggered PV EOI since the 1769 * last entry. If yes, set EOI on guests's behalf. 1770 * Clear PV EOI in guest memory in any case. 1771 */ 1772 static void apic_sync_pv_eoi_from_guest(struct kvm_vcpu *vcpu, 1773 struct kvm_lapic *apic) 1774 { 1775 bool pending; 1776 int vector; 1777 /* 1778 * PV EOI state is derived from KVM_APIC_PV_EOI_PENDING in host 1779 * and KVM_PV_EOI_ENABLED in guest memory as follows: 1780 * 1781 * KVM_APIC_PV_EOI_PENDING is unset: 1782 * -> host disabled PV EOI. 1783 * KVM_APIC_PV_EOI_PENDING is set, KVM_PV_EOI_ENABLED is set: 1784 * -> host enabled PV EOI, guest did not execute EOI yet. 1785 * KVM_APIC_PV_EOI_PENDING is set, KVM_PV_EOI_ENABLED is unset: 1786 * -> host enabled PV EOI, guest executed EOI. 1787 */ 1788 BUG_ON(!pv_eoi_enabled(vcpu)); 1789 pending = pv_eoi_get_pending(vcpu); 1790 /* 1791 * Clear pending bit in any case: it will be set again on vmentry. 1792 * While this might not be ideal from performance point of view, 1793 * this makes sure pv eoi is only enabled when we know it's safe. 1794 */ 1795 pv_eoi_clr_pending(vcpu); 1796 if (pending) 1797 return; 1798 vector = apic_set_eoi(apic); 1799 trace_kvm_pv_eoi(apic, vector); 1800 } 1801 1802 void kvm_lapic_sync_from_vapic(struct kvm_vcpu *vcpu) 1803 { 1804 u32 data; 1805 1806 if (test_bit(KVM_APIC_PV_EOI_PENDING, &vcpu->arch.apic_attention)) 1807 apic_sync_pv_eoi_from_guest(vcpu, vcpu->arch.apic); 1808 1809 if (!test_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention)) 1810 return; 1811 1812 kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.apic->vapic_cache, &data, 1813 sizeof(u32)); 1814 1815 apic_set_tpr(vcpu->arch.apic, data & 0xff); 1816 } 1817 1818 /* 1819 * apic_sync_pv_eoi_to_guest - called before vmentry 1820 * 1821 * Detect whether it's safe to enable PV EOI and 1822 * if yes do so. 1823 */ 1824 static void apic_sync_pv_eoi_to_guest(struct kvm_vcpu *vcpu, 1825 struct kvm_lapic *apic) 1826 { 1827 if (!pv_eoi_enabled(vcpu) || 1828 /* IRR set or many bits in ISR: could be nested. */ 1829 apic->irr_pending || 1830 /* Cache not set: could be safe but we don't bother. */ 1831 apic->highest_isr_cache == -1 || 1832 /* Need EOI to update ioapic. */ 1833 kvm_ioapic_handles_vector(vcpu->kvm, apic->highest_isr_cache)) { 1834 /* 1835 * PV EOI was disabled by apic_sync_pv_eoi_from_guest 1836 * so we need not do anything here. 1837 */ 1838 return; 1839 } 1840 1841 pv_eoi_set_pending(apic->vcpu); 1842 } 1843 1844 void kvm_lapic_sync_to_vapic(struct kvm_vcpu *vcpu) 1845 { 1846 u32 data, tpr; 1847 int max_irr, max_isr; 1848 struct kvm_lapic *apic = vcpu->arch.apic; 1849 1850 apic_sync_pv_eoi_to_guest(vcpu, apic); 1851 1852 if (!test_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention)) 1853 return; 1854 1855 tpr = kvm_apic_get_reg(apic, APIC_TASKPRI) & 0xff; 1856 max_irr = apic_find_highest_irr(apic); 1857 if (max_irr < 0) 1858 max_irr = 0; 1859 max_isr = apic_find_highest_isr(apic); 1860 if (max_isr < 0) 1861 max_isr = 0; 1862 data = (tpr & 0xff) | ((max_isr & 0xf0) << 8) | (max_irr << 24); 1863 1864 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apic->vapic_cache, &data, 1865 sizeof(u32)); 1866 } 1867 1868 int kvm_lapic_set_vapic_addr(struct kvm_vcpu *vcpu, gpa_t vapic_addr) 1869 { 1870 if (vapic_addr) { 1871 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, 1872 &vcpu->arch.apic->vapic_cache, 1873 vapic_addr, sizeof(u32))) 1874 return -EINVAL; 1875 __set_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention); 1876 } else { 1877 __clear_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention); 1878 } 1879 1880 vcpu->arch.apic->vapic_addr = vapic_addr; 1881 return 0; 1882 } 1883 1884 int kvm_x2apic_msr_write(struct kvm_vcpu *vcpu, u32 msr, u64 data) 1885 { 1886 struct kvm_lapic *apic = vcpu->arch.apic; 1887 u32 reg = (msr - APIC_BASE_MSR) << 4; 1888 1889 if (!irqchip_in_kernel(vcpu->kvm) || !apic_x2apic_mode(apic)) 1890 return 1; 1891 1892 if (reg == APIC_ICR2) 1893 return 1; 1894 1895 /* if this is ICR write vector before command */ 1896 if (reg == APIC_ICR) 1897 apic_reg_write(apic, APIC_ICR2, (u32)(data >> 32)); 1898 return apic_reg_write(apic, reg, (u32)data); 1899 } 1900 1901 int kvm_x2apic_msr_read(struct kvm_vcpu *vcpu, u32 msr, u64 *data) 1902 { 1903 struct kvm_lapic *apic = vcpu->arch.apic; 1904 u32 reg = (msr - APIC_BASE_MSR) << 4, low, high = 0; 1905 1906 if (!irqchip_in_kernel(vcpu->kvm) || !apic_x2apic_mode(apic)) 1907 return 1; 1908 1909 if (reg == APIC_DFR || reg == APIC_ICR2) { 1910 apic_debug("KVM_APIC_READ: read x2apic reserved register %x\n", 1911 reg); 1912 return 1; 1913 } 1914 1915 if (apic_reg_read(apic, reg, 4, &low)) 1916 return 1; 1917 if (reg == APIC_ICR) 1918 apic_reg_read(apic, APIC_ICR2, 4, &high); 1919 1920 *data = (((u64)high) << 32) | low; 1921 1922 return 0; 1923 } 1924 1925 int kvm_hv_vapic_msr_write(struct kvm_vcpu *vcpu, u32 reg, u64 data) 1926 { 1927 struct kvm_lapic *apic = vcpu->arch.apic; 1928 1929 if (!kvm_vcpu_has_lapic(vcpu)) 1930 return 1; 1931 1932 /* if this is ICR write vector before command */ 1933 if (reg == APIC_ICR) 1934 apic_reg_write(apic, APIC_ICR2, (u32)(data >> 32)); 1935 return apic_reg_write(apic, reg, (u32)data); 1936 } 1937 1938 int kvm_hv_vapic_msr_read(struct kvm_vcpu *vcpu, u32 reg, u64 *data) 1939 { 1940 struct kvm_lapic *apic = vcpu->arch.apic; 1941 u32 low, high = 0; 1942 1943 if (!kvm_vcpu_has_lapic(vcpu)) 1944 return 1; 1945 1946 if (apic_reg_read(apic, reg, 4, &low)) 1947 return 1; 1948 if (reg == APIC_ICR) 1949 apic_reg_read(apic, APIC_ICR2, 4, &high); 1950 1951 *data = (((u64)high) << 32) | low; 1952 1953 return 0; 1954 } 1955 1956 int kvm_lapic_enable_pv_eoi(struct kvm_vcpu *vcpu, u64 data) 1957 { 1958 u64 addr = data & ~KVM_MSR_ENABLED; 1959 if (!IS_ALIGNED(addr, 4)) 1960 return 1; 1961 1962 vcpu->arch.pv_eoi.msr_val = data; 1963 if (!pv_eoi_enabled(vcpu)) 1964 return 0; 1965 return kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.pv_eoi.data, 1966 addr, sizeof(u8)); 1967 } 1968 1969 void kvm_apic_accept_events(struct kvm_vcpu *vcpu) 1970 { 1971 struct kvm_lapic *apic = vcpu->arch.apic; 1972 u8 sipi_vector; 1973 unsigned long pe; 1974 1975 if (!kvm_vcpu_has_lapic(vcpu) || !apic->pending_events) 1976 return; 1977 1978 pe = xchg(&apic->pending_events, 0); 1979 1980 if (test_bit(KVM_APIC_INIT, &pe)) { 1981 kvm_lapic_reset(vcpu); 1982 kvm_vcpu_reset(vcpu); 1983 if (kvm_vcpu_is_bsp(apic->vcpu)) 1984 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; 1985 else 1986 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED; 1987 } 1988 if (test_bit(KVM_APIC_SIPI, &pe) && 1989 vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) { 1990 /* evaluate pending_events before reading the vector */ 1991 smp_rmb(); 1992 sipi_vector = apic->sipi_vector; 1993 apic_debug("vcpu %d received sipi with vector # %x\n", 1994 vcpu->vcpu_id, sipi_vector); 1995 kvm_vcpu_deliver_sipi_vector(vcpu, sipi_vector); 1996 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; 1997 } 1998 } 1999 2000 void kvm_lapic_init(void) 2001 { 2002 /* do not patch jump label more than once per second */ 2003 jump_label_rate_limit(&apic_hw_disabled, HZ); 2004 jump_label_rate_limit(&apic_sw_disabled, HZ); 2005 } 2006