1 2 /* 3 * Local APIC virtualization 4 * 5 * Copyright (C) 2006 Qumranet, Inc. 6 * Copyright (C) 2007 Novell 7 * Copyright (C) 2007 Intel 8 * Copyright 2009 Red Hat, Inc. and/or its affiliates. 9 * 10 * Authors: 11 * Dor Laor <dor.laor@qumranet.com> 12 * Gregory Haskins <ghaskins@novell.com> 13 * Yaozu (Eddie) Dong <eddie.dong@intel.com> 14 * 15 * Based on Xen 3.1 code, Copyright (c) 2004, Intel Corporation. 16 * 17 * This work is licensed under the terms of the GNU GPL, version 2. See 18 * the COPYING file in the top-level directory. 19 */ 20 21 #include <linux/kvm_host.h> 22 #include <linux/kvm.h> 23 #include <linux/mm.h> 24 #include <linux/highmem.h> 25 #include <linux/smp.h> 26 #include <linux/hrtimer.h> 27 #include <linux/io.h> 28 #include <linux/module.h> 29 #include <linux/math64.h> 30 #include <linux/slab.h> 31 #include <asm/processor.h> 32 #include <asm/msr.h> 33 #include <asm/page.h> 34 #include <asm/current.h> 35 #include <asm/apicdef.h> 36 #include <linux/atomic.h> 37 #include "kvm_cache_regs.h" 38 #include "irq.h" 39 #include "trace.h" 40 #include "x86.h" 41 #include "cpuid.h" 42 43 #ifndef CONFIG_X86_64 44 #define mod_64(x, y) ((x) - (y) * div64_u64(x, y)) 45 #else 46 #define mod_64(x, y) ((x) % (y)) 47 #endif 48 49 #define PRId64 "d" 50 #define PRIx64 "llx" 51 #define PRIu64 "u" 52 #define PRIo64 "o" 53 54 #define APIC_BUS_CYCLE_NS 1 55 56 /* #define apic_debug(fmt,arg...) printk(KERN_WARNING fmt,##arg) */ 57 #define apic_debug(fmt, arg...) 58 59 #define APIC_LVT_NUM 6 60 /* 14 is the version for Xeon and Pentium 8.4.8*/ 61 #define APIC_VERSION (0x14UL | ((APIC_LVT_NUM - 1) << 16)) 62 #define LAPIC_MMIO_LENGTH (1 << 12) 63 /* followed define is not in apicdef.h */ 64 #define APIC_SHORT_MASK 0xc0000 65 #define APIC_DEST_NOSHORT 0x0 66 #define APIC_DEST_MASK 0x800 67 #define MAX_APIC_VECTOR 256 68 69 #define VEC_POS(v) ((v) & (32 - 1)) 70 #define REG_POS(v) (((v) >> 5) << 4) 71 72 static unsigned int min_timer_period_us = 500; 73 module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR); 74 75 static inline u32 apic_get_reg(struct kvm_lapic *apic, int reg_off) 76 { 77 return *((u32 *) (apic->regs + reg_off)); 78 } 79 80 static inline void apic_set_reg(struct kvm_lapic *apic, int reg_off, u32 val) 81 { 82 *((u32 *) (apic->regs + reg_off)) = val; 83 } 84 85 static inline int apic_test_and_set_vector(int vec, void *bitmap) 86 { 87 return test_and_set_bit(VEC_POS(vec), (bitmap) + REG_POS(vec)); 88 } 89 90 static inline int apic_test_and_clear_vector(int vec, void *bitmap) 91 { 92 return test_and_clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec)); 93 } 94 95 static inline int apic_test_vector(int vec, void *bitmap) 96 { 97 return test_bit(VEC_POS(vec), (bitmap) + REG_POS(vec)); 98 } 99 100 static inline void apic_set_vector(int vec, void *bitmap) 101 { 102 set_bit(VEC_POS(vec), (bitmap) + REG_POS(vec)); 103 } 104 105 static inline void apic_clear_vector(int vec, void *bitmap) 106 { 107 clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec)); 108 } 109 110 static inline int apic_hw_enabled(struct kvm_lapic *apic) 111 { 112 return (apic)->vcpu->arch.apic_base & MSR_IA32_APICBASE_ENABLE; 113 } 114 115 static inline int apic_sw_enabled(struct kvm_lapic *apic) 116 { 117 return apic_get_reg(apic, APIC_SPIV) & APIC_SPIV_APIC_ENABLED; 118 } 119 120 static inline int apic_enabled(struct kvm_lapic *apic) 121 { 122 return apic_sw_enabled(apic) && apic_hw_enabled(apic); 123 } 124 125 #define LVT_MASK \ 126 (APIC_LVT_MASKED | APIC_SEND_PENDING | APIC_VECTOR_MASK) 127 128 #define LINT_MASK \ 129 (LVT_MASK | APIC_MODE_MASK | APIC_INPUT_POLARITY | \ 130 APIC_LVT_REMOTE_IRR | APIC_LVT_LEVEL_TRIGGER) 131 132 static inline int kvm_apic_id(struct kvm_lapic *apic) 133 { 134 return (apic_get_reg(apic, APIC_ID) >> 24) & 0xff; 135 } 136 137 static inline int apic_lvt_enabled(struct kvm_lapic *apic, int lvt_type) 138 { 139 return !(apic_get_reg(apic, lvt_type) & APIC_LVT_MASKED); 140 } 141 142 static inline int apic_lvt_vector(struct kvm_lapic *apic, int lvt_type) 143 { 144 return apic_get_reg(apic, lvt_type) & APIC_VECTOR_MASK; 145 } 146 147 static inline int apic_lvtt_oneshot(struct kvm_lapic *apic) 148 { 149 return ((apic_get_reg(apic, APIC_LVTT) & 150 apic->lapic_timer.timer_mode_mask) == APIC_LVT_TIMER_ONESHOT); 151 } 152 153 static inline int apic_lvtt_period(struct kvm_lapic *apic) 154 { 155 return ((apic_get_reg(apic, APIC_LVTT) & 156 apic->lapic_timer.timer_mode_mask) == APIC_LVT_TIMER_PERIODIC); 157 } 158 159 static inline int apic_lvtt_tscdeadline(struct kvm_lapic *apic) 160 { 161 return ((apic_get_reg(apic, APIC_LVTT) & 162 apic->lapic_timer.timer_mode_mask) == 163 APIC_LVT_TIMER_TSCDEADLINE); 164 } 165 166 static inline int apic_lvt_nmi_mode(u32 lvt_val) 167 { 168 return (lvt_val & (APIC_MODE_MASK | APIC_LVT_MASKED)) == APIC_DM_NMI; 169 } 170 171 void kvm_apic_set_version(struct kvm_vcpu *vcpu) 172 { 173 struct kvm_lapic *apic = vcpu->arch.apic; 174 struct kvm_cpuid_entry2 *feat; 175 u32 v = APIC_VERSION; 176 177 if (!irqchip_in_kernel(vcpu->kvm)) 178 return; 179 180 feat = kvm_find_cpuid_entry(apic->vcpu, 0x1, 0); 181 if (feat && (feat->ecx & (1 << (X86_FEATURE_X2APIC & 31)))) 182 v |= APIC_LVR_DIRECTED_EOI; 183 apic_set_reg(apic, APIC_LVR, v); 184 } 185 186 static inline int apic_x2apic_mode(struct kvm_lapic *apic) 187 { 188 return apic->vcpu->arch.apic_base & X2APIC_ENABLE; 189 } 190 191 static unsigned int apic_lvt_mask[APIC_LVT_NUM] = { 192 LVT_MASK , /* part LVTT mask, timer mode mask added at runtime */ 193 LVT_MASK | APIC_MODE_MASK, /* LVTTHMR */ 194 LVT_MASK | APIC_MODE_MASK, /* LVTPC */ 195 LINT_MASK, LINT_MASK, /* LVT0-1 */ 196 LVT_MASK /* LVTERR */ 197 }; 198 199 static int find_highest_vector(void *bitmap) 200 { 201 u32 *word = bitmap; 202 int word_offset = MAX_APIC_VECTOR >> 5; 203 204 while ((word_offset != 0) && (word[(--word_offset) << 2] == 0)) 205 continue; 206 207 if (likely(!word_offset && !word[0])) 208 return -1; 209 else 210 return fls(word[word_offset << 2]) - 1 + (word_offset << 5); 211 } 212 213 static inline int apic_test_and_set_irr(int vec, struct kvm_lapic *apic) 214 { 215 apic->irr_pending = true; 216 return apic_test_and_set_vector(vec, apic->regs + APIC_IRR); 217 } 218 219 static inline int apic_search_irr(struct kvm_lapic *apic) 220 { 221 return find_highest_vector(apic->regs + APIC_IRR); 222 } 223 224 static inline int apic_find_highest_irr(struct kvm_lapic *apic) 225 { 226 int result; 227 228 if (!apic->irr_pending) 229 return -1; 230 231 result = apic_search_irr(apic); 232 ASSERT(result == -1 || result >= 16); 233 234 return result; 235 } 236 237 static inline void apic_clear_irr(int vec, struct kvm_lapic *apic) 238 { 239 apic->irr_pending = false; 240 apic_clear_vector(vec, apic->regs + APIC_IRR); 241 if (apic_search_irr(apic) != -1) 242 apic->irr_pending = true; 243 } 244 245 int kvm_lapic_find_highest_irr(struct kvm_vcpu *vcpu) 246 { 247 struct kvm_lapic *apic = vcpu->arch.apic; 248 int highest_irr; 249 250 /* This may race with setting of irr in __apic_accept_irq() and 251 * value returned may be wrong, but kvm_vcpu_kick() in __apic_accept_irq 252 * will cause vmexit immediately and the value will be recalculated 253 * on the next vmentry. 254 */ 255 if (!apic) 256 return 0; 257 highest_irr = apic_find_highest_irr(apic); 258 259 return highest_irr; 260 } 261 262 static int __apic_accept_irq(struct kvm_lapic *apic, int delivery_mode, 263 int vector, int level, int trig_mode); 264 265 int kvm_apic_set_irq(struct kvm_vcpu *vcpu, struct kvm_lapic_irq *irq) 266 { 267 struct kvm_lapic *apic = vcpu->arch.apic; 268 269 return __apic_accept_irq(apic, irq->delivery_mode, irq->vector, 270 irq->level, irq->trig_mode); 271 } 272 273 static inline int apic_find_highest_isr(struct kvm_lapic *apic) 274 { 275 int result; 276 277 result = find_highest_vector(apic->regs + APIC_ISR); 278 ASSERT(result == -1 || result >= 16); 279 280 return result; 281 } 282 283 static void apic_update_ppr(struct kvm_lapic *apic) 284 { 285 u32 tpr, isrv, ppr, old_ppr; 286 int isr; 287 288 old_ppr = apic_get_reg(apic, APIC_PROCPRI); 289 tpr = apic_get_reg(apic, APIC_TASKPRI); 290 isr = apic_find_highest_isr(apic); 291 isrv = (isr != -1) ? isr : 0; 292 293 if ((tpr & 0xf0) >= (isrv & 0xf0)) 294 ppr = tpr & 0xff; 295 else 296 ppr = isrv & 0xf0; 297 298 apic_debug("vlapic %p, ppr 0x%x, isr 0x%x, isrv 0x%x", 299 apic, ppr, isr, isrv); 300 301 if (old_ppr != ppr) { 302 apic_set_reg(apic, APIC_PROCPRI, ppr); 303 if (ppr < old_ppr) 304 kvm_make_request(KVM_REQ_EVENT, apic->vcpu); 305 } 306 } 307 308 static void apic_set_tpr(struct kvm_lapic *apic, u32 tpr) 309 { 310 apic_set_reg(apic, APIC_TASKPRI, tpr); 311 apic_update_ppr(apic); 312 } 313 314 int kvm_apic_match_physical_addr(struct kvm_lapic *apic, u16 dest) 315 { 316 return dest == 0xff || kvm_apic_id(apic) == dest; 317 } 318 319 int kvm_apic_match_logical_addr(struct kvm_lapic *apic, u8 mda) 320 { 321 int result = 0; 322 u32 logical_id; 323 324 if (apic_x2apic_mode(apic)) { 325 logical_id = apic_get_reg(apic, APIC_LDR); 326 return logical_id & mda; 327 } 328 329 logical_id = GET_APIC_LOGICAL_ID(apic_get_reg(apic, APIC_LDR)); 330 331 switch (apic_get_reg(apic, APIC_DFR)) { 332 case APIC_DFR_FLAT: 333 if (logical_id & mda) 334 result = 1; 335 break; 336 case APIC_DFR_CLUSTER: 337 if (((logical_id >> 4) == (mda >> 0x4)) 338 && (logical_id & mda & 0xf)) 339 result = 1; 340 break; 341 default: 342 apic_debug("Bad DFR vcpu %d: %08x\n", 343 apic->vcpu->vcpu_id, apic_get_reg(apic, APIC_DFR)); 344 break; 345 } 346 347 return result; 348 } 349 350 int kvm_apic_match_dest(struct kvm_vcpu *vcpu, struct kvm_lapic *source, 351 int short_hand, int dest, int dest_mode) 352 { 353 int result = 0; 354 struct kvm_lapic *target = vcpu->arch.apic; 355 356 apic_debug("target %p, source %p, dest 0x%x, " 357 "dest_mode 0x%x, short_hand 0x%x\n", 358 target, source, dest, dest_mode, short_hand); 359 360 ASSERT(target); 361 switch (short_hand) { 362 case APIC_DEST_NOSHORT: 363 if (dest_mode == 0) 364 /* Physical mode. */ 365 result = kvm_apic_match_physical_addr(target, dest); 366 else 367 /* Logical mode. */ 368 result = kvm_apic_match_logical_addr(target, dest); 369 break; 370 case APIC_DEST_SELF: 371 result = (target == source); 372 break; 373 case APIC_DEST_ALLINC: 374 result = 1; 375 break; 376 case APIC_DEST_ALLBUT: 377 result = (target != source); 378 break; 379 default: 380 apic_debug("kvm: apic: Bad dest shorthand value %x\n", 381 short_hand); 382 break; 383 } 384 385 return result; 386 } 387 388 /* 389 * Add a pending IRQ into lapic. 390 * Return 1 if successfully added and 0 if discarded. 391 */ 392 static int __apic_accept_irq(struct kvm_lapic *apic, int delivery_mode, 393 int vector, int level, int trig_mode) 394 { 395 int result = 0; 396 struct kvm_vcpu *vcpu = apic->vcpu; 397 398 switch (delivery_mode) { 399 case APIC_DM_LOWEST: 400 vcpu->arch.apic_arb_prio++; 401 case APIC_DM_FIXED: 402 /* FIXME add logic for vcpu on reset */ 403 if (unlikely(!apic_enabled(apic))) 404 break; 405 406 if (trig_mode) { 407 apic_debug("level trig mode for vector %d", vector); 408 apic_set_vector(vector, apic->regs + APIC_TMR); 409 } else 410 apic_clear_vector(vector, apic->regs + APIC_TMR); 411 412 result = !apic_test_and_set_irr(vector, apic); 413 trace_kvm_apic_accept_irq(vcpu->vcpu_id, delivery_mode, 414 trig_mode, vector, !result); 415 if (!result) { 416 if (trig_mode) 417 apic_debug("level trig mode repeatedly for " 418 "vector %d", vector); 419 break; 420 } 421 422 kvm_make_request(KVM_REQ_EVENT, vcpu); 423 kvm_vcpu_kick(vcpu); 424 break; 425 426 case APIC_DM_REMRD: 427 apic_debug("Ignoring delivery mode 3\n"); 428 break; 429 430 case APIC_DM_SMI: 431 apic_debug("Ignoring guest SMI\n"); 432 break; 433 434 case APIC_DM_NMI: 435 result = 1; 436 kvm_inject_nmi(vcpu); 437 kvm_vcpu_kick(vcpu); 438 break; 439 440 case APIC_DM_INIT: 441 if (!trig_mode || level) { 442 result = 1; 443 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED; 444 kvm_make_request(KVM_REQ_EVENT, vcpu); 445 kvm_vcpu_kick(vcpu); 446 } else { 447 apic_debug("Ignoring de-assert INIT to vcpu %d\n", 448 vcpu->vcpu_id); 449 } 450 break; 451 452 case APIC_DM_STARTUP: 453 apic_debug("SIPI to vcpu %d vector 0x%02x\n", 454 vcpu->vcpu_id, vector); 455 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) { 456 result = 1; 457 vcpu->arch.sipi_vector = vector; 458 vcpu->arch.mp_state = KVM_MP_STATE_SIPI_RECEIVED; 459 kvm_make_request(KVM_REQ_EVENT, vcpu); 460 kvm_vcpu_kick(vcpu); 461 } 462 break; 463 464 case APIC_DM_EXTINT: 465 /* 466 * Should only be called by kvm_apic_local_deliver() with LVT0, 467 * before NMI watchdog was enabled. Already handled by 468 * kvm_apic_accept_pic_intr(). 469 */ 470 break; 471 472 default: 473 printk(KERN_ERR "TODO: unsupported delivery mode %x\n", 474 delivery_mode); 475 break; 476 } 477 return result; 478 } 479 480 int kvm_apic_compare_prio(struct kvm_vcpu *vcpu1, struct kvm_vcpu *vcpu2) 481 { 482 return vcpu1->arch.apic_arb_prio - vcpu2->arch.apic_arb_prio; 483 } 484 485 static void apic_set_eoi(struct kvm_lapic *apic) 486 { 487 int vector = apic_find_highest_isr(apic); 488 /* 489 * Not every write EOI will has corresponding ISR, 490 * one example is when Kernel check timer on setup_IO_APIC 491 */ 492 if (vector == -1) 493 return; 494 495 apic_clear_vector(vector, apic->regs + APIC_ISR); 496 apic_update_ppr(apic); 497 498 if (!(apic_get_reg(apic, APIC_SPIV) & APIC_SPIV_DIRECTED_EOI) && 499 kvm_ioapic_handles_vector(apic->vcpu->kvm, vector)) { 500 int trigger_mode; 501 if (apic_test_vector(vector, apic->regs + APIC_TMR)) 502 trigger_mode = IOAPIC_LEVEL_TRIG; 503 else 504 trigger_mode = IOAPIC_EDGE_TRIG; 505 kvm_ioapic_update_eoi(apic->vcpu->kvm, vector, trigger_mode); 506 } 507 kvm_make_request(KVM_REQ_EVENT, apic->vcpu); 508 } 509 510 static void apic_send_ipi(struct kvm_lapic *apic) 511 { 512 u32 icr_low = apic_get_reg(apic, APIC_ICR); 513 u32 icr_high = apic_get_reg(apic, APIC_ICR2); 514 struct kvm_lapic_irq irq; 515 516 irq.vector = icr_low & APIC_VECTOR_MASK; 517 irq.delivery_mode = icr_low & APIC_MODE_MASK; 518 irq.dest_mode = icr_low & APIC_DEST_MASK; 519 irq.level = icr_low & APIC_INT_ASSERT; 520 irq.trig_mode = icr_low & APIC_INT_LEVELTRIG; 521 irq.shorthand = icr_low & APIC_SHORT_MASK; 522 if (apic_x2apic_mode(apic)) 523 irq.dest_id = icr_high; 524 else 525 irq.dest_id = GET_APIC_DEST_FIELD(icr_high); 526 527 trace_kvm_apic_ipi(icr_low, irq.dest_id); 528 529 apic_debug("icr_high 0x%x, icr_low 0x%x, " 530 "short_hand 0x%x, dest 0x%x, trig_mode 0x%x, level 0x%x, " 531 "dest_mode 0x%x, delivery_mode 0x%x, vector 0x%x\n", 532 icr_high, icr_low, irq.shorthand, irq.dest_id, 533 irq.trig_mode, irq.level, irq.dest_mode, irq.delivery_mode, 534 irq.vector); 535 536 kvm_irq_delivery_to_apic(apic->vcpu->kvm, apic, &irq); 537 } 538 539 static u32 apic_get_tmcct(struct kvm_lapic *apic) 540 { 541 ktime_t remaining; 542 s64 ns; 543 u32 tmcct; 544 545 ASSERT(apic != NULL); 546 547 /* if initial count is 0, current count should also be 0 */ 548 if (apic_get_reg(apic, APIC_TMICT) == 0) 549 return 0; 550 551 remaining = hrtimer_get_remaining(&apic->lapic_timer.timer); 552 if (ktime_to_ns(remaining) < 0) 553 remaining = ktime_set(0, 0); 554 555 ns = mod_64(ktime_to_ns(remaining), apic->lapic_timer.period); 556 tmcct = div64_u64(ns, 557 (APIC_BUS_CYCLE_NS * apic->divide_count)); 558 559 return tmcct; 560 } 561 562 static void __report_tpr_access(struct kvm_lapic *apic, bool write) 563 { 564 struct kvm_vcpu *vcpu = apic->vcpu; 565 struct kvm_run *run = vcpu->run; 566 567 kvm_make_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu); 568 run->tpr_access.rip = kvm_rip_read(vcpu); 569 run->tpr_access.is_write = write; 570 } 571 572 static inline void report_tpr_access(struct kvm_lapic *apic, bool write) 573 { 574 if (apic->vcpu->arch.tpr_access_reporting) 575 __report_tpr_access(apic, write); 576 } 577 578 static u32 __apic_read(struct kvm_lapic *apic, unsigned int offset) 579 { 580 u32 val = 0; 581 582 if (offset >= LAPIC_MMIO_LENGTH) 583 return 0; 584 585 switch (offset) { 586 case APIC_ID: 587 if (apic_x2apic_mode(apic)) 588 val = kvm_apic_id(apic); 589 else 590 val = kvm_apic_id(apic) << 24; 591 break; 592 case APIC_ARBPRI: 593 apic_debug("Access APIC ARBPRI register which is for P6\n"); 594 break; 595 596 case APIC_TMCCT: /* Timer CCR */ 597 if (apic_lvtt_tscdeadline(apic)) 598 return 0; 599 600 val = apic_get_tmcct(apic); 601 break; 602 603 case APIC_TASKPRI: 604 report_tpr_access(apic, false); 605 /* fall thru */ 606 default: 607 apic_update_ppr(apic); 608 val = apic_get_reg(apic, offset); 609 break; 610 } 611 612 return val; 613 } 614 615 static inline struct kvm_lapic *to_lapic(struct kvm_io_device *dev) 616 { 617 return container_of(dev, struct kvm_lapic, dev); 618 } 619 620 static int apic_reg_read(struct kvm_lapic *apic, u32 offset, int len, 621 void *data) 622 { 623 unsigned char alignment = offset & 0xf; 624 u32 result; 625 /* this bitmask has a bit cleared for each reserver register */ 626 static const u64 rmask = 0x43ff01ffffffe70cULL; 627 628 if ((alignment + len) > 4) { 629 apic_debug("KVM_APIC_READ: alignment error %x %d\n", 630 offset, len); 631 return 1; 632 } 633 634 if (offset > 0x3f0 || !(rmask & (1ULL << (offset >> 4)))) { 635 apic_debug("KVM_APIC_READ: read reserved register %x\n", 636 offset); 637 return 1; 638 } 639 640 result = __apic_read(apic, offset & ~0xf); 641 642 trace_kvm_apic_read(offset, result); 643 644 switch (len) { 645 case 1: 646 case 2: 647 case 4: 648 memcpy(data, (char *)&result + alignment, len); 649 break; 650 default: 651 printk(KERN_ERR "Local APIC read with len = %x, " 652 "should be 1,2, or 4 instead\n", len); 653 break; 654 } 655 return 0; 656 } 657 658 static int apic_mmio_in_range(struct kvm_lapic *apic, gpa_t addr) 659 { 660 return apic_hw_enabled(apic) && 661 addr >= apic->base_address && 662 addr < apic->base_address + LAPIC_MMIO_LENGTH; 663 } 664 665 static int apic_mmio_read(struct kvm_io_device *this, 666 gpa_t address, int len, void *data) 667 { 668 struct kvm_lapic *apic = to_lapic(this); 669 u32 offset = address - apic->base_address; 670 671 if (!apic_mmio_in_range(apic, address)) 672 return -EOPNOTSUPP; 673 674 apic_reg_read(apic, offset, len, data); 675 676 return 0; 677 } 678 679 static void update_divide_count(struct kvm_lapic *apic) 680 { 681 u32 tmp1, tmp2, tdcr; 682 683 tdcr = apic_get_reg(apic, APIC_TDCR); 684 tmp1 = tdcr & 0xf; 685 tmp2 = ((tmp1 & 0x3) | ((tmp1 & 0x8) >> 1)) + 1; 686 apic->divide_count = 0x1 << (tmp2 & 0x7); 687 688 apic_debug("timer divide count is 0x%x\n", 689 apic->divide_count); 690 } 691 692 static void start_apic_timer(struct kvm_lapic *apic) 693 { 694 ktime_t now; 695 atomic_set(&apic->lapic_timer.pending, 0); 696 697 if (apic_lvtt_period(apic) || apic_lvtt_oneshot(apic)) { 698 /* lapic timer in oneshot or peroidic mode */ 699 now = apic->lapic_timer.timer.base->get_time(); 700 apic->lapic_timer.period = (u64)apic_get_reg(apic, APIC_TMICT) 701 * APIC_BUS_CYCLE_NS * apic->divide_count; 702 703 if (!apic->lapic_timer.period) 704 return; 705 /* 706 * Do not allow the guest to program periodic timers with small 707 * interval, since the hrtimers are not throttled by the host 708 * scheduler. 709 */ 710 if (apic_lvtt_period(apic)) { 711 s64 min_period = min_timer_period_us * 1000LL; 712 713 if (apic->lapic_timer.period < min_period) { 714 pr_info_ratelimited( 715 "kvm: vcpu %i: requested %lld ns " 716 "lapic timer period limited to %lld ns\n", 717 apic->vcpu->vcpu_id, 718 apic->lapic_timer.period, min_period); 719 apic->lapic_timer.period = min_period; 720 } 721 } 722 723 hrtimer_start(&apic->lapic_timer.timer, 724 ktime_add_ns(now, apic->lapic_timer.period), 725 HRTIMER_MODE_ABS); 726 727 apic_debug("%s: bus cycle is %" PRId64 "ns, now 0x%016" 728 PRIx64 ", " 729 "timer initial count 0x%x, period %lldns, " 730 "expire @ 0x%016" PRIx64 ".\n", __func__, 731 APIC_BUS_CYCLE_NS, ktime_to_ns(now), 732 apic_get_reg(apic, APIC_TMICT), 733 apic->lapic_timer.period, 734 ktime_to_ns(ktime_add_ns(now, 735 apic->lapic_timer.period))); 736 } else if (apic_lvtt_tscdeadline(apic)) { 737 /* lapic timer in tsc deadline mode */ 738 u64 guest_tsc, tscdeadline = apic->lapic_timer.tscdeadline; 739 u64 ns = 0; 740 struct kvm_vcpu *vcpu = apic->vcpu; 741 unsigned long this_tsc_khz = vcpu->arch.virtual_tsc_khz; 742 unsigned long flags; 743 744 if (unlikely(!tscdeadline || !this_tsc_khz)) 745 return; 746 747 local_irq_save(flags); 748 749 now = apic->lapic_timer.timer.base->get_time(); 750 guest_tsc = kvm_x86_ops->read_l1_tsc(vcpu); 751 if (likely(tscdeadline > guest_tsc)) { 752 ns = (tscdeadline - guest_tsc) * 1000000ULL; 753 do_div(ns, this_tsc_khz); 754 } 755 hrtimer_start(&apic->lapic_timer.timer, 756 ktime_add_ns(now, ns), HRTIMER_MODE_ABS); 757 758 local_irq_restore(flags); 759 } 760 } 761 762 static void apic_manage_nmi_watchdog(struct kvm_lapic *apic, u32 lvt0_val) 763 { 764 int nmi_wd_enabled = apic_lvt_nmi_mode(apic_get_reg(apic, APIC_LVT0)); 765 766 if (apic_lvt_nmi_mode(lvt0_val)) { 767 if (!nmi_wd_enabled) { 768 apic_debug("Receive NMI setting on APIC_LVT0 " 769 "for cpu %d\n", apic->vcpu->vcpu_id); 770 apic->vcpu->kvm->arch.vapics_in_nmi_mode++; 771 } 772 } else if (nmi_wd_enabled) 773 apic->vcpu->kvm->arch.vapics_in_nmi_mode--; 774 } 775 776 static int apic_reg_write(struct kvm_lapic *apic, u32 reg, u32 val) 777 { 778 int ret = 0; 779 780 trace_kvm_apic_write(reg, val); 781 782 switch (reg) { 783 case APIC_ID: /* Local APIC ID */ 784 if (!apic_x2apic_mode(apic)) 785 apic_set_reg(apic, APIC_ID, val); 786 else 787 ret = 1; 788 break; 789 790 case APIC_TASKPRI: 791 report_tpr_access(apic, true); 792 apic_set_tpr(apic, val & 0xff); 793 break; 794 795 case APIC_EOI: 796 apic_set_eoi(apic); 797 break; 798 799 case APIC_LDR: 800 if (!apic_x2apic_mode(apic)) 801 apic_set_reg(apic, APIC_LDR, val & APIC_LDR_MASK); 802 else 803 ret = 1; 804 break; 805 806 case APIC_DFR: 807 if (!apic_x2apic_mode(apic)) 808 apic_set_reg(apic, APIC_DFR, val | 0x0FFFFFFF); 809 else 810 ret = 1; 811 break; 812 813 case APIC_SPIV: { 814 u32 mask = 0x3ff; 815 if (apic_get_reg(apic, APIC_LVR) & APIC_LVR_DIRECTED_EOI) 816 mask |= APIC_SPIV_DIRECTED_EOI; 817 apic_set_reg(apic, APIC_SPIV, val & mask); 818 if (!(val & APIC_SPIV_APIC_ENABLED)) { 819 int i; 820 u32 lvt_val; 821 822 for (i = 0; i < APIC_LVT_NUM; i++) { 823 lvt_val = apic_get_reg(apic, 824 APIC_LVTT + 0x10 * i); 825 apic_set_reg(apic, APIC_LVTT + 0x10 * i, 826 lvt_val | APIC_LVT_MASKED); 827 } 828 atomic_set(&apic->lapic_timer.pending, 0); 829 830 } 831 break; 832 } 833 case APIC_ICR: 834 /* No delay here, so we always clear the pending bit */ 835 apic_set_reg(apic, APIC_ICR, val & ~(1 << 12)); 836 apic_send_ipi(apic); 837 break; 838 839 case APIC_ICR2: 840 if (!apic_x2apic_mode(apic)) 841 val &= 0xff000000; 842 apic_set_reg(apic, APIC_ICR2, val); 843 break; 844 845 case APIC_LVT0: 846 apic_manage_nmi_watchdog(apic, val); 847 case APIC_LVTTHMR: 848 case APIC_LVTPC: 849 case APIC_LVT1: 850 case APIC_LVTERR: 851 /* TODO: Check vector */ 852 if (!apic_sw_enabled(apic)) 853 val |= APIC_LVT_MASKED; 854 855 val &= apic_lvt_mask[(reg - APIC_LVTT) >> 4]; 856 apic_set_reg(apic, reg, val); 857 858 break; 859 860 case APIC_LVTT: 861 if ((apic_get_reg(apic, APIC_LVTT) & 862 apic->lapic_timer.timer_mode_mask) != 863 (val & apic->lapic_timer.timer_mode_mask)) 864 hrtimer_cancel(&apic->lapic_timer.timer); 865 866 if (!apic_sw_enabled(apic)) 867 val |= APIC_LVT_MASKED; 868 val &= (apic_lvt_mask[0] | apic->lapic_timer.timer_mode_mask); 869 apic_set_reg(apic, APIC_LVTT, val); 870 break; 871 872 case APIC_TMICT: 873 if (apic_lvtt_tscdeadline(apic)) 874 break; 875 876 hrtimer_cancel(&apic->lapic_timer.timer); 877 apic_set_reg(apic, APIC_TMICT, val); 878 start_apic_timer(apic); 879 break; 880 881 case APIC_TDCR: 882 if (val & 4) 883 apic_debug("KVM_WRITE:TDCR %x\n", val); 884 apic_set_reg(apic, APIC_TDCR, val); 885 update_divide_count(apic); 886 break; 887 888 case APIC_ESR: 889 if (apic_x2apic_mode(apic) && val != 0) { 890 apic_debug("KVM_WRITE:ESR not zero %x\n", val); 891 ret = 1; 892 } 893 break; 894 895 case APIC_SELF_IPI: 896 if (apic_x2apic_mode(apic)) { 897 apic_reg_write(apic, APIC_ICR, 0x40000 | (val & 0xff)); 898 } else 899 ret = 1; 900 break; 901 default: 902 ret = 1; 903 break; 904 } 905 if (ret) 906 apic_debug("Local APIC Write to read-only register %x\n", reg); 907 return ret; 908 } 909 910 static int apic_mmio_write(struct kvm_io_device *this, 911 gpa_t address, int len, const void *data) 912 { 913 struct kvm_lapic *apic = to_lapic(this); 914 unsigned int offset = address - apic->base_address; 915 u32 val; 916 917 if (!apic_mmio_in_range(apic, address)) 918 return -EOPNOTSUPP; 919 920 /* 921 * APIC register must be aligned on 128-bits boundary. 922 * 32/64/128 bits registers must be accessed thru 32 bits. 923 * Refer SDM 8.4.1 924 */ 925 if (len != 4 || (offset & 0xf)) { 926 /* Don't shout loud, $infamous_os would cause only noise. */ 927 apic_debug("apic write: bad size=%d %lx\n", len, (long)address); 928 return 0; 929 } 930 931 val = *(u32*)data; 932 933 /* too common printing */ 934 if (offset != APIC_EOI) 935 apic_debug("%s: offset 0x%x with length 0x%x, and value is " 936 "0x%x\n", __func__, offset, len, val); 937 938 apic_reg_write(apic, offset & 0xff0, val); 939 940 return 0; 941 } 942 943 void kvm_lapic_set_eoi(struct kvm_vcpu *vcpu) 944 { 945 struct kvm_lapic *apic = vcpu->arch.apic; 946 947 if (apic) 948 apic_reg_write(vcpu->arch.apic, APIC_EOI, 0); 949 } 950 EXPORT_SYMBOL_GPL(kvm_lapic_set_eoi); 951 952 void kvm_free_lapic(struct kvm_vcpu *vcpu) 953 { 954 if (!vcpu->arch.apic) 955 return; 956 957 hrtimer_cancel(&vcpu->arch.apic->lapic_timer.timer); 958 959 if (vcpu->arch.apic->regs) 960 free_page((unsigned long)vcpu->arch.apic->regs); 961 962 kfree(vcpu->arch.apic); 963 } 964 965 /* 966 *---------------------------------------------------------------------- 967 * LAPIC interface 968 *---------------------------------------------------------------------- 969 */ 970 971 u64 kvm_get_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu) 972 { 973 struct kvm_lapic *apic = vcpu->arch.apic; 974 if (!apic) 975 return 0; 976 977 if (apic_lvtt_oneshot(apic) || apic_lvtt_period(apic)) 978 return 0; 979 980 return apic->lapic_timer.tscdeadline; 981 } 982 983 void kvm_set_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu, u64 data) 984 { 985 struct kvm_lapic *apic = vcpu->arch.apic; 986 if (!apic) 987 return; 988 989 if (apic_lvtt_oneshot(apic) || apic_lvtt_period(apic)) 990 return; 991 992 hrtimer_cancel(&apic->lapic_timer.timer); 993 apic->lapic_timer.tscdeadline = data; 994 start_apic_timer(apic); 995 } 996 997 void kvm_lapic_set_tpr(struct kvm_vcpu *vcpu, unsigned long cr8) 998 { 999 struct kvm_lapic *apic = vcpu->arch.apic; 1000 1001 if (!apic) 1002 return; 1003 apic_set_tpr(apic, ((cr8 & 0x0f) << 4) 1004 | (apic_get_reg(apic, APIC_TASKPRI) & 4)); 1005 } 1006 1007 u64 kvm_lapic_get_cr8(struct kvm_vcpu *vcpu) 1008 { 1009 struct kvm_lapic *apic = vcpu->arch.apic; 1010 u64 tpr; 1011 1012 if (!apic) 1013 return 0; 1014 tpr = (u64) apic_get_reg(apic, APIC_TASKPRI); 1015 1016 return (tpr & 0xf0) >> 4; 1017 } 1018 1019 void kvm_lapic_set_base(struct kvm_vcpu *vcpu, u64 value) 1020 { 1021 struct kvm_lapic *apic = vcpu->arch.apic; 1022 1023 if (!apic) { 1024 value |= MSR_IA32_APICBASE_BSP; 1025 vcpu->arch.apic_base = value; 1026 return; 1027 } 1028 1029 if (!kvm_vcpu_is_bsp(apic->vcpu)) 1030 value &= ~MSR_IA32_APICBASE_BSP; 1031 1032 vcpu->arch.apic_base = value; 1033 if (apic_x2apic_mode(apic)) { 1034 u32 id = kvm_apic_id(apic); 1035 u32 ldr = ((id & ~0xf) << 16) | (1 << (id & 0xf)); 1036 apic_set_reg(apic, APIC_LDR, ldr); 1037 } 1038 apic->base_address = apic->vcpu->arch.apic_base & 1039 MSR_IA32_APICBASE_BASE; 1040 1041 /* with FSB delivery interrupt, we can restart APIC functionality */ 1042 apic_debug("apic base msr is 0x%016" PRIx64 ", and base address is " 1043 "0x%lx.\n", apic->vcpu->arch.apic_base, apic->base_address); 1044 1045 } 1046 1047 void kvm_lapic_reset(struct kvm_vcpu *vcpu) 1048 { 1049 struct kvm_lapic *apic; 1050 int i; 1051 1052 apic_debug("%s\n", __func__); 1053 1054 ASSERT(vcpu); 1055 apic = vcpu->arch.apic; 1056 ASSERT(apic != NULL); 1057 1058 /* Stop the timer in case it's a reset to an active apic */ 1059 hrtimer_cancel(&apic->lapic_timer.timer); 1060 1061 apic_set_reg(apic, APIC_ID, vcpu->vcpu_id << 24); 1062 kvm_apic_set_version(apic->vcpu); 1063 1064 for (i = 0; i < APIC_LVT_NUM; i++) 1065 apic_set_reg(apic, APIC_LVTT + 0x10 * i, APIC_LVT_MASKED); 1066 apic_set_reg(apic, APIC_LVT0, 1067 SET_APIC_DELIVERY_MODE(0, APIC_MODE_EXTINT)); 1068 1069 apic_set_reg(apic, APIC_DFR, 0xffffffffU); 1070 apic_set_reg(apic, APIC_SPIV, 0xff); 1071 apic_set_reg(apic, APIC_TASKPRI, 0); 1072 apic_set_reg(apic, APIC_LDR, 0); 1073 apic_set_reg(apic, APIC_ESR, 0); 1074 apic_set_reg(apic, APIC_ICR, 0); 1075 apic_set_reg(apic, APIC_ICR2, 0); 1076 apic_set_reg(apic, APIC_TDCR, 0); 1077 apic_set_reg(apic, APIC_TMICT, 0); 1078 for (i = 0; i < 8; i++) { 1079 apic_set_reg(apic, APIC_IRR + 0x10 * i, 0); 1080 apic_set_reg(apic, APIC_ISR + 0x10 * i, 0); 1081 apic_set_reg(apic, APIC_TMR + 0x10 * i, 0); 1082 } 1083 apic->irr_pending = false; 1084 update_divide_count(apic); 1085 atomic_set(&apic->lapic_timer.pending, 0); 1086 if (kvm_vcpu_is_bsp(vcpu)) 1087 vcpu->arch.apic_base |= MSR_IA32_APICBASE_BSP; 1088 apic_update_ppr(apic); 1089 1090 vcpu->arch.apic_arb_prio = 0; 1091 vcpu->arch.apic_attention = 0; 1092 1093 apic_debug(KERN_INFO "%s: vcpu=%p, id=%d, base_msr=" 1094 "0x%016" PRIx64 ", base_address=0x%0lx.\n", __func__, 1095 vcpu, kvm_apic_id(apic), 1096 vcpu->arch.apic_base, apic->base_address); 1097 } 1098 1099 bool kvm_apic_present(struct kvm_vcpu *vcpu) 1100 { 1101 return vcpu->arch.apic && apic_hw_enabled(vcpu->arch.apic); 1102 } 1103 1104 int kvm_lapic_enabled(struct kvm_vcpu *vcpu) 1105 { 1106 return kvm_apic_present(vcpu) && apic_sw_enabled(vcpu->arch.apic); 1107 } 1108 1109 /* 1110 *---------------------------------------------------------------------- 1111 * timer interface 1112 *---------------------------------------------------------------------- 1113 */ 1114 1115 static bool lapic_is_periodic(struct kvm_timer *ktimer) 1116 { 1117 struct kvm_lapic *apic = container_of(ktimer, struct kvm_lapic, 1118 lapic_timer); 1119 return apic_lvtt_period(apic); 1120 } 1121 1122 int apic_has_pending_timer(struct kvm_vcpu *vcpu) 1123 { 1124 struct kvm_lapic *lapic = vcpu->arch.apic; 1125 1126 if (lapic && apic_enabled(lapic) && apic_lvt_enabled(lapic, APIC_LVTT)) 1127 return atomic_read(&lapic->lapic_timer.pending); 1128 1129 return 0; 1130 } 1131 1132 int kvm_apic_local_deliver(struct kvm_lapic *apic, int lvt_type) 1133 { 1134 u32 reg = apic_get_reg(apic, lvt_type); 1135 int vector, mode, trig_mode; 1136 1137 if (apic_hw_enabled(apic) && !(reg & APIC_LVT_MASKED)) { 1138 vector = reg & APIC_VECTOR_MASK; 1139 mode = reg & APIC_MODE_MASK; 1140 trig_mode = reg & APIC_LVT_LEVEL_TRIGGER; 1141 return __apic_accept_irq(apic, mode, vector, 1, trig_mode); 1142 } 1143 return 0; 1144 } 1145 1146 void kvm_apic_nmi_wd_deliver(struct kvm_vcpu *vcpu) 1147 { 1148 struct kvm_lapic *apic = vcpu->arch.apic; 1149 1150 if (apic) 1151 kvm_apic_local_deliver(apic, APIC_LVT0); 1152 } 1153 1154 static struct kvm_timer_ops lapic_timer_ops = { 1155 .is_periodic = lapic_is_periodic, 1156 }; 1157 1158 static const struct kvm_io_device_ops apic_mmio_ops = { 1159 .read = apic_mmio_read, 1160 .write = apic_mmio_write, 1161 }; 1162 1163 int kvm_create_lapic(struct kvm_vcpu *vcpu) 1164 { 1165 struct kvm_lapic *apic; 1166 1167 ASSERT(vcpu != NULL); 1168 apic_debug("apic_init %d\n", vcpu->vcpu_id); 1169 1170 apic = kzalloc(sizeof(*apic), GFP_KERNEL); 1171 if (!apic) 1172 goto nomem; 1173 1174 vcpu->arch.apic = apic; 1175 1176 apic->regs = (void *)get_zeroed_page(GFP_KERNEL); 1177 if (!apic->regs) { 1178 printk(KERN_ERR "malloc apic regs error for vcpu %x\n", 1179 vcpu->vcpu_id); 1180 goto nomem_free_apic; 1181 } 1182 apic->vcpu = vcpu; 1183 1184 hrtimer_init(&apic->lapic_timer.timer, CLOCK_MONOTONIC, 1185 HRTIMER_MODE_ABS); 1186 apic->lapic_timer.timer.function = kvm_timer_fn; 1187 apic->lapic_timer.t_ops = &lapic_timer_ops; 1188 apic->lapic_timer.kvm = vcpu->kvm; 1189 apic->lapic_timer.vcpu = vcpu; 1190 1191 apic->base_address = APIC_DEFAULT_PHYS_BASE; 1192 vcpu->arch.apic_base = APIC_DEFAULT_PHYS_BASE; 1193 1194 kvm_lapic_reset(vcpu); 1195 kvm_iodevice_init(&apic->dev, &apic_mmio_ops); 1196 1197 return 0; 1198 nomem_free_apic: 1199 kfree(apic); 1200 nomem: 1201 return -ENOMEM; 1202 } 1203 1204 int kvm_apic_has_interrupt(struct kvm_vcpu *vcpu) 1205 { 1206 struct kvm_lapic *apic = vcpu->arch.apic; 1207 int highest_irr; 1208 1209 if (!apic || !apic_enabled(apic)) 1210 return -1; 1211 1212 apic_update_ppr(apic); 1213 highest_irr = apic_find_highest_irr(apic); 1214 if ((highest_irr == -1) || 1215 ((highest_irr & 0xF0) <= apic_get_reg(apic, APIC_PROCPRI))) 1216 return -1; 1217 return highest_irr; 1218 } 1219 1220 int kvm_apic_accept_pic_intr(struct kvm_vcpu *vcpu) 1221 { 1222 u32 lvt0 = apic_get_reg(vcpu->arch.apic, APIC_LVT0); 1223 int r = 0; 1224 1225 if (!apic_hw_enabled(vcpu->arch.apic)) 1226 r = 1; 1227 if ((lvt0 & APIC_LVT_MASKED) == 0 && 1228 GET_APIC_DELIVERY_MODE(lvt0) == APIC_MODE_EXTINT) 1229 r = 1; 1230 return r; 1231 } 1232 1233 void kvm_inject_apic_timer_irqs(struct kvm_vcpu *vcpu) 1234 { 1235 struct kvm_lapic *apic = vcpu->arch.apic; 1236 1237 if (apic && atomic_read(&apic->lapic_timer.pending) > 0) { 1238 if (kvm_apic_local_deliver(apic, APIC_LVTT)) 1239 atomic_dec(&apic->lapic_timer.pending); 1240 } 1241 } 1242 1243 int kvm_get_apic_interrupt(struct kvm_vcpu *vcpu) 1244 { 1245 int vector = kvm_apic_has_interrupt(vcpu); 1246 struct kvm_lapic *apic = vcpu->arch.apic; 1247 1248 if (vector == -1) 1249 return -1; 1250 1251 apic_set_vector(vector, apic->regs + APIC_ISR); 1252 apic_update_ppr(apic); 1253 apic_clear_irr(vector, apic); 1254 return vector; 1255 } 1256 1257 void kvm_apic_post_state_restore(struct kvm_vcpu *vcpu) 1258 { 1259 struct kvm_lapic *apic = vcpu->arch.apic; 1260 1261 apic->base_address = vcpu->arch.apic_base & 1262 MSR_IA32_APICBASE_BASE; 1263 kvm_apic_set_version(vcpu); 1264 1265 apic_update_ppr(apic); 1266 hrtimer_cancel(&apic->lapic_timer.timer); 1267 update_divide_count(apic); 1268 start_apic_timer(apic); 1269 apic->irr_pending = true; 1270 kvm_make_request(KVM_REQ_EVENT, vcpu); 1271 } 1272 1273 void __kvm_migrate_apic_timer(struct kvm_vcpu *vcpu) 1274 { 1275 struct kvm_lapic *apic = vcpu->arch.apic; 1276 struct hrtimer *timer; 1277 1278 if (!apic) 1279 return; 1280 1281 timer = &apic->lapic_timer.timer; 1282 if (hrtimer_cancel(timer)) 1283 hrtimer_start_expires(timer, HRTIMER_MODE_ABS); 1284 } 1285 1286 void kvm_lapic_sync_from_vapic(struct kvm_vcpu *vcpu) 1287 { 1288 u32 data; 1289 void *vapic; 1290 1291 if (!test_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention)) 1292 return; 1293 1294 vapic = kmap_atomic(vcpu->arch.apic->vapic_page); 1295 data = *(u32 *)(vapic + offset_in_page(vcpu->arch.apic->vapic_addr)); 1296 kunmap_atomic(vapic); 1297 1298 apic_set_tpr(vcpu->arch.apic, data & 0xff); 1299 } 1300 1301 void kvm_lapic_sync_to_vapic(struct kvm_vcpu *vcpu) 1302 { 1303 u32 data, tpr; 1304 int max_irr, max_isr; 1305 struct kvm_lapic *apic; 1306 void *vapic; 1307 1308 if (!test_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention)) 1309 return; 1310 1311 apic = vcpu->arch.apic; 1312 tpr = apic_get_reg(apic, APIC_TASKPRI) & 0xff; 1313 max_irr = apic_find_highest_irr(apic); 1314 if (max_irr < 0) 1315 max_irr = 0; 1316 max_isr = apic_find_highest_isr(apic); 1317 if (max_isr < 0) 1318 max_isr = 0; 1319 data = (tpr & 0xff) | ((max_isr & 0xf0) << 8) | (max_irr << 24); 1320 1321 vapic = kmap_atomic(vcpu->arch.apic->vapic_page); 1322 *(u32 *)(vapic + offset_in_page(vcpu->arch.apic->vapic_addr)) = data; 1323 kunmap_atomic(vapic); 1324 } 1325 1326 void kvm_lapic_set_vapic_addr(struct kvm_vcpu *vcpu, gpa_t vapic_addr) 1327 { 1328 vcpu->arch.apic->vapic_addr = vapic_addr; 1329 if (vapic_addr) 1330 __set_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention); 1331 else 1332 __clear_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention); 1333 } 1334 1335 int kvm_x2apic_msr_write(struct kvm_vcpu *vcpu, u32 msr, u64 data) 1336 { 1337 struct kvm_lapic *apic = vcpu->arch.apic; 1338 u32 reg = (msr - APIC_BASE_MSR) << 4; 1339 1340 if (!irqchip_in_kernel(vcpu->kvm) || !apic_x2apic_mode(apic)) 1341 return 1; 1342 1343 /* if this is ICR write vector before command */ 1344 if (msr == 0x830) 1345 apic_reg_write(apic, APIC_ICR2, (u32)(data >> 32)); 1346 return apic_reg_write(apic, reg, (u32)data); 1347 } 1348 1349 int kvm_x2apic_msr_read(struct kvm_vcpu *vcpu, u32 msr, u64 *data) 1350 { 1351 struct kvm_lapic *apic = vcpu->arch.apic; 1352 u32 reg = (msr - APIC_BASE_MSR) << 4, low, high = 0; 1353 1354 if (!irqchip_in_kernel(vcpu->kvm) || !apic_x2apic_mode(apic)) 1355 return 1; 1356 1357 if (apic_reg_read(apic, reg, 4, &low)) 1358 return 1; 1359 if (msr == 0x830) 1360 apic_reg_read(apic, APIC_ICR2, 4, &high); 1361 1362 *data = (((u64)high) << 32) | low; 1363 1364 return 0; 1365 } 1366 1367 int kvm_hv_vapic_msr_write(struct kvm_vcpu *vcpu, u32 reg, u64 data) 1368 { 1369 struct kvm_lapic *apic = vcpu->arch.apic; 1370 1371 if (!irqchip_in_kernel(vcpu->kvm)) 1372 return 1; 1373 1374 /* if this is ICR write vector before command */ 1375 if (reg == APIC_ICR) 1376 apic_reg_write(apic, APIC_ICR2, (u32)(data >> 32)); 1377 return apic_reg_write(apic, reg, (u32)data); 1378 } 1379 1380 int kvm_hv_vapic_msr_read(struct kvm_vcpu *vcpu, u32 reg, u64 *data) 1381 { 1382 struct kvm_lapic *apic = vcpu->arch.apic; 1383 u32 low, high = 0; 1384 1385 if (!irqchip_in_kernel(vcpu->kvm)) 1386 return 1; 1387 1388 if (apic_reg_read(apic, reg, 4, &low)) 1389 return 1; 1390 if (reg == APIC_ICR) 1391 apic_reg_read(apic, APIC_ICR2, 4, &high); 1392 1393 *data = (((u64)high) << 32) | low; 1394 1395 return 0; 1396 } 1397