1 // SPDX-License-Identifier: LGPL-2.1-or-later 2 /* 3 * Copyright (C) 2001 MandrakeSoft S.A. 4 * Copyright 2010 Red Hat, Inc. and/or its affiliates. 5 * 6 * MandrakeSoft S.A. 7 * 43, rue d'Aboukir 8 * 75002 Paris - France 9 * http://www.linux-mandrake.com/ 10 * http://www.mandrakesoft.com/ 11 * 12 * Yunhong Jiang <yunhong.jiang@intel.com> 13 * Yaozu (Eddie) Dong <eddie.dong@intel.com> 14 * Based on Xen 3.1 code. 15 */ 16 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 17 18 #include <linux/kvm_host.h> 19 #include <linux/kvm.h> 20 #include <linux/mm.h> 21 #include <linux/highmem.h> 22 #include <linux/smp.h> 23 #include <linux/hrtimer.h> 24 #include <linux/io.h> 25 #include <linux/slab.h> 26 #include <linux/export.h> 27 #include <linux/nospec.h> 28 #include <asm/processor.h> 29 #include <asm/page.h> 30 #include <asm/current.h> 31 32 #include "ioapic.h" 33 #include "lapic.h" 34 #include "irq.h" 35 #include "trace.h" 36 #include "x86.h" 37 38 static int ioapic_service(struct kvm_ioapic *vioapic, int irq, 39 bool line_status); 40 41 static unsigned long ioapic_read_indirect(struct kvm_ioapic *ioapic) 42 { 43 unsigned long result = 0; 44 45 switch (ioapic->ioregsel) { 46 case IOAPIC_REG_VERSION: 47 result = ((((IOAPIC_NUM_PINS - 1) & 0xff) << 16) 48 | (IOAPIC_VERSION_ID & 0xff)); 49 break; 50 51 case IOAPIC_REG_APIC_ID: 52 case IOAPIC_REG_ARB_ID: 53 result = ((ioapic->id & 0xf) << 24); 54 break; 55 56 default: 57 { 58 u32 redir_index = (ioapic->ioregsel - 0x10) >> 1; 59 u64 redir_content = ~0ULL; 60 61 if (redir_index < IOAPIC_NUM_PINS) { 62 u32 index = array_index_nospec( 63 redir_index, IOAPIC_NUM_PINS); 64 65 redir_content = ioapic->redirtbl[index].bits; 66 } 67 68 result = (ioapic->ioregsel & 0x1) ? 69 (redir_content >> 32) & 0xffffffff : 70 redir_content & 0xffffffff; 71 break; 72 } 73 } 74 75 return result; 76 } 77 78 static void rtc_irq_eoi_tracking_reset(struct kvm_ioapic *ioapic) 79 { 80 ioapic->rtc_status.pending_eoi = 0; 81 bitmap_zero(ioapic->rtc_status.map, KVM_MAX_VCPU_IDS); 82 } 83 84 static void kvm_rtc_eoi_tracking_restore_all(struct kvm_ioapic *ioapic); 85 86 static void rtc_status_pending_eoi_check_valid(struct kvm_ioapic *ioapic) 87 { 88 if (WARN_ON_ONCE(ioapic->rtc_status.pending_eoi < 0)) 89 kvm_rtc_eoi_tracking_restore_all(ioapic); 90 } 91 92 static void __rtc_irq_eoi_tracking_restore_one(struct kvm_vcpu *vcpu) 93 { 94 bool new_val, old_val; 95 struct kvm_ioapic *ioapic = vcpu->kvm->arch.vioapic; 96 struct rtc_status *status = &ioapic->rtc_status; 97 union kvm_ioapic_redirect_entry *e; 98 99 e = &ioapic->redirtbl[RTC_GSI]; 100 if (!kvm_apic_match_dest(vcpu, NULL, APIC_DEST_NOSHORT, 101 e->fields.dest_id, 102 kvm_lapic_irq_dest_mode(!!e->fields.dest_mode))) 103 return; 104 105 new_val = kvm_apic_pending_eoi(vcpu, e->fields.vector); 106 old_val = test_bit(vcpu->vcpu_id, status->map); 107 108 if (new_val == old_val) 109 return; 110 111 if (new_val) { 112 __set_bit(vcpu->vcpu_id, status->map); 113 status->vectors[vcpu->vcpu_id] = e->fields.vector; 114 ioapic->rtc_status.pending_eoi++; 115 } else { 116 __clear_bit(vcpu->vcpu_id, status->map); 117 ioapic->rtc_status.pending_eoi--; 118 rtc_status_pending_eoi_check_valid(ioapic); 119 } 120 } 121 122 void kvm_rtc_eoi_tracking_restore_one(struct kvm_vcpu *vcpu) 123 { 124 struct kvm_ioapic *ioapic = vcpu->kvm->arch.vioapic; 125 126 spin_lock(&ioapic->lock); 127 __rtc_irq_eoi_tracking_restore_one(vcpu); 128 spin_unlock(&ioapic->lock); 129 } 130 131 static void kvm_rtc_eoi_tracking_restore_all(struct kvm_ioapic *ioapic) 132 { 133 struct kvm_vcpu *vcpu; 134 unsigned long i; 135 136 if (RTC_GSI >= IOAPIC_NUM_PINS) 137 return; 138 139 rtc_irq_eoi_tracking_reset(ioapic); 140 kvm_for_each_vcpu(i, vcpu, ioapic->kvm) 141 __rtc_irq_eoi_tracking_restore_one(vcpu); 142 } 143 144 static void rtc_irq_eoi(struct kvm_ioapic *ioapic, struct kvm_vcpu *vcpu, 145 int vector) 146 { 147 struct rtc_status *status = &ioapic->rtc_status; 148 149 /* RTC special handling */ 150 if (test_bit(vcpu->vcpu_id, status->map) && 151 (vector == status->vectors[vcpu->vcpu_id]) && 152 (test_and_clear_bit(vcpu->vcpu_id, status->map))) { 153 --ioapic->rtc_status.pending_eoi; 154 rtc_status_pending_eoi_check_valid(ioapic); 155 } 156 } 157 158 static bool rtc_irq_check_coalesced(struct kvm_ioapic *ioapic) 159 { 160 if (ioapic->rtc_status.pending_eoi > 0) 161 return true; /* coalesced */ 162 163 return false; 164 } 165 166 static void ioapic_lazy_update_eoi(struct kvm_ioapic *ioapic, int irq) 167 { 168 unsigned long i; 169 struct kvm_vcpu *vcpu; 170 union kvm_ioapic_redirect_entry *entry = &ioapic->redirtbl[irq]; 171 172 kvm_for_each_vcpu(i, vcpu, ioapic->kvm) { 173 if (!kvm_apic_match_dest(vcpu, NULL, APIC_DEST_NOSHORT, 174 entry->fields.dest_id, 175 entry->fields.dest_mode) || 176 kvm_apic_pending_eoi(vcpu, entry->fields.vector)) 177 continue; 178 179 /* 180 * If no longer has pending EOI in LAPICs, update 181 * EOI for this vector. 182 */ 183 rtc_irq_eoi(ioapic, vcpu, entry->fields.vector); 184 break; 185 } 186 } 187 188 static int ioapic_set_irq(struct kvm_ioapic *ioapic, unsigned int irq, 189 int irq_level, bool line_status) 190 { 191 union kvm_ioapic_redirect_entry entry; 192 u32 mask = 1 << irq; 193 u32 old_irr; 194 int edge, ret; 195 196 entry = ioapic->redirtbl[irq]; 197 edge = (entry.fields.trig_mode == IOAPIC_EDGE_TRIG); 198 199 if (!irq_level) { 200 ioapic->irr &= ~mask; 201 ret = 1; 202 goto out; 203 } 204 205 /* 206 * AMD SVM AVIC accelerate EOI write iff the interrupt is edge 207 * triggered, in which case the in-kernel IOAPIC will not be able 208 * to receive the EOI. In this case, we do a lazy update of the 209 * pending EOI when trying to set IOAPIC irq. 210 */ 211 if (edge && kvm_apicv_activated(ioapic->kvm)) 212 ioapic_lazy_update_eoi(ioapic, irq); 213 214 /* 215 * Return 0 for coalesced interrupts; for edge-triggered interrupts, 216 * this only happens if a previous edge has not been delivered due 217 * to masking. For level interrupts, the remote_irr field tells 218 * us if the interrupt is waiting for an EOI. 219 * 220 * RTC is special: it is edge-triggered, but userspace likes to know 221 * if it has been already ack-ed via EOI because coalesced RTC 222 * interrupts lead to time drift in Windows guests. So we track 223 * EOI manually for the RTC interrupt. 224 */ 225 if (irq == RTC_GSI && line_status && 226 rtc_irq_check_coalesced(ioapic)) { 227 ret = 0; 228 goto out; 229 } 230 231 old_irr = ioapic->irr; 232 ioapic->irr |= mask; 233 if (edge) { 234 ioapic->irr_delivered &= ~mask; 235 if (old_irr == ioapic->irr) { 236 ret = 0; 237 goto out; 238 } 239 } 240 241 ret = ioapic_service(ioapic, irq, line_status); 242 243 out: 244 trace_kvm_ioapic_set_irq(entry.bits, irq, ret == 0); 245 return ret; 246 } 247 248 static void kvm_ioapic_inject_all(struct kvm_ioapic *ioapic, unsigned long irr) 249 { 250 u32 idx; 251 252 rtc_irq_eoi_tracking_reset(ioapic); 253 for_each_set_bit(idx, &irr, IOAPIC_NUM_PINS) 254 ioapic_set_irq(ioapic, idx, 1, true); 255 256 kvm_rtc_eoi_tracking_restore_all(ioapic); 257 } 258 259 260 void kvm_ioapic_scan_entry(struct kvm_vcpu *vcpu, ulong *ioapic_handled_vectors) 261 { 262 struct kvm_ioapic *ioapic = vcpu->kvm->arch.vioapic; 263 struct rtc_status *status = &ioapic->rtc_status; 264 union kvm_ioapic_redirect_entry *e; 265 int index; 266 267 spin_lock(&ioapic->lock); 268 269 /* Make sure we see any missing RTC EOI */ 270 if (test_bit(vcpu->vcpu_id, status->map)) 271 __set_bit(status->vectors[vcpu->vcpu_id], 272 ioapic_handled_vectors); 273 274 for (index = 0; index < IOAPIC_NUM_PINS; index++) { 275 e = &ioapic->redirtbl[index]; 276 if (e->fields.trig_mode == IOAPIC_LEVEL_TRIG || 277 kvm_irq_has_notifier(ioapic->kvm, KVM_IRQCHIP_IOAPIC, index) || 278 index == RTC_GSI) { 279 u16 dm = kvm_lapic_irq_dest_mode(!!e->fields.dest_mode); 280 281 kvm_scan_ioapic_irq(vcpu, e->fields.dest_id, dm, 282 e->fields.vector, ioapic_handled_vectors); 283 } 284 } 285 spin_unlock(&ioapic->lock); 286 } 287 288 void kvm_arch_post_irq_ack_notifier_list_update(struct kvm *kvm) 289 { 290 if (!ioapic_in_kernel(kvm)) 291 return; 292 kvm_make_scan_ioapic_request(kvm); 293 } 294 295 void kvm_register_irq_mask_notifier(struct kvm *kvm, int irq, 296 struct kvm_irq_mask_notifier *kimn) 297 { 298 struct kvm_ioapic *ioapic = kvm->arch.vioapic; 299 300 mutex_lock(&kvm->irq_lock); 301 kimn->irq = irq; 302 hlist_add_head_rcu(&kimn->link, &ioapic->mask_notifier_list); 303 mutex_unlock(&kvm->irq_lock); 304 } 305 306 void kvm_unregister_irq_mask_notifier(struct kvm *kvm, int irq, 307 struct kvm_irq_mask_notifier *kimn) 308 { 309 mutex_lock(&kvm->irq_lock); 310 hlist_del_rcu(&kimn->link); 311 mutex_unlock(&kvm->irq_lock); 312 synchronize_srcu(&kvm->irq_srcu); 313 } 314 315 void kvm_fire_mask_notifiers(struct kvm *kvm, unsigned irqchip, unsigned pin, 316 bool mask) 317 { 318 struct kvm_ioapic *ioapic = kvm->arch.vioapic; 319 struct kvm_irq_mask_notifier *kimn; 320 int idx, gsi; 321 322 idx = srcu_read_lock(&kvm->irq_srcu); 323 gsi = kvm_irq_map_chip_pin(kvm, irqchip, pin); 324 if (gsi != -1) 325 hlist_for_each_entry_srcu(kimn, &ioapic->mask_notifier_list, link, 326 srcu_read_lock_held(&kvm->irq_srcu)) 327 if (kimn->irq == gsi) 328 kimn->func(kimn, mask); 329 srcu_read_unlock(&kvm->irq_srcu, idx); 330 } 331 332 static void ioapic_write_indirect(struct kvm_ioapic *ioapic, u32 val) 333 { 334 unsigned index; 335 bool mask_before, mask_after; 336 union kvm_ioapic_redirect_entry *e; 337 int old_remote_irr, old_delivery_status, old_dest_id, old_dest_mode; 338 DECLARE_BITMAP(vcpu_bitmap, KVM_MAX_VCPUS); 339 340 switch (ioapic->ioregsel) { 341 case IOAPIC_REG_VERSION: 342 /* Writes are ignored. */ 343 break; 344 345 case IOAPIC_REG_APIC_ID: 346 ioapic->id = (val >> 24) & 0xf; 347 break; 348 349 case IOAPIC_REG_ARB_ID: 350 break; 351 352 default: 353 index = (ioapic->ioregsel - 0x10) >> 1; 354 355 if (index >= IOAPIC_NUM_PINS) 356 return; 357 index = array_index_nospec(index, IOAPIC_NUM_PINS); 358 e = &ioapic->redirtbl[index]; 359 mask_before = e->fields.mask; 360 /* Preserve read-only fields */ 361 old_remote_irr = e->fields.remote_irr; 362 old_delivery_status = e->fields.delivery_status; 363 old_dest_id = e->fields.dest_id; 364 old_dest_mode = e->fields.dest_mode; 365 if (ioapic->ioregsel & 1) { 366 e->bits &= 0xffffffff; 367 e->bits |= (u64) val << 32; 368 } else { 369 e->bits &= ~0xffffffffULL; 370 e->bits |= (u32) val; 371 } 372 e->fields.remote_irr = old_remote_irr; 373 e->fields.delivery_status = old_delivery_status; 374 375 /* 376 * Some OSes (Linux, Xen) assume that Remote IRR bit will 377 * be cleared by IOAPIC hardware when the entry is configured 378 * as edge-triggered. This behavior is used to simulate an 379 * explicit EOI on IOAPICs that don't have the EOI register. 380 */ 381 if (e->fields.trig_mode == IOAPIC_EDGE_TRIG) 382 e->fields.remote_irr = 0; 383 384 mask_after = e->fields.mask; 385 if (mask_before != mask_after) 386 kvm_fire_mask_notifiers(ioapic->kvm, KVM_IRQCHIP_IOAPIC, index, mask_after); 387 if (e->fields.trig_mode == IOAPIC_LEVEL_TRIG && 388 ioapic->irr & (1 << index) && !e->fields.mask && !e->fields.remote_irr) { 389 /* 390 * Pending status in irr may be outdated: the IRQ line may have 391 * already been deasserted by a device while the IRQ was masked. 392 * This occurs, for instance, if the interrupt is handled in a 393 * Linux guest as a oneshot interrupt (IRQF_ONESHOT). In this 394 * case the guest acknowledges the interrupt to the device in 395 * its threaded irq handler, i.e. after the EOI but before 396 * unmasking, so at the time of unmasking the IRQ line is 397 * already down but our pending irr bit is still set. In such 398 * cases, injecting this pending interrupt to the guest is 399 * buggy: the guest will receive an extra unwanted interrupt. 400 * 401 * So we need to check here if the IRQ is actually still pending. 402 * As we are generally not able to probe the IRQ line status 403 * directly, we do it through irqfd resampler. Namely, we clear 404 * the pending status and notify the resampler that this interrupt 405 * is done, without actually injecting it into the guest. If the 406 * IRQ line is actually already deasserted, we are done. If it is 407 * still asserted, a new interrupt will be shortly triggered 408 * through irqfd and injected into the guest. 409 * 410 * If, however, it's not possible to resample (no irqfd resampler 411 * registered for this irq), then unconditionally inject this 412 * pending interrupt into the guest, so the guest will not miss 413 * an interrupt, although may get an extra unwanted interrupt. 414 */ 415 if (kvm_notify_irqfd_resampler(ioapic->kvm, KVM_IRQCHIP_IOAPIC, index)) 416 ioapic->irr &= ~(1 << index); 417 else 418 ioapic_service(ioapic, index, false); 419 } 420 if (e->fields.delivery_mode == APIC_DM_FIXED) { 421 struct kvm_lapic_irq irq; 422 423 irq.vector = e->fields.vector; 424 irq.delivery_mode = e->fields.delivery_mode << 8; 425 irq.dest_mode = 426 kvm_lapic_irq_dest_mode(!!e->fields.dest_mode); 427 irq.level = false; 428 irq.trig_mode = e->fields.trig_mode; 429 irq.shorthand = APIC_DEST_NOSHORT; 430 irq.dest_id = e->fields.dest_id; 431 irq.msi_redir_hint = false; 432 bitmap_zero(vcpu_bitmap, KVM_MAX_VCPUS); 433 kvm_bitmap_or_dest_vcpus(ioapic->kvm, &irq, 434 vcpu_bitmap); 435 if (old_dest_mode != e->fields.dest_mode || 436 old_dest_id != e->fields.dest_id) { 437 /* 438 * Update vcpu_bitmap with vcpus specified in 439 * the previous request as well. This is done to 440 * keep ioapic_handled_vectors synchronized. 441 */ 442 irq.dest_id = old_dest_id; 443 irq.dest_mode = 444 kvm_lapic_irq_dest_mode( 445 !!old_dest_mode); 446 kvm_bitmap_or_dest_vcpus(ioapic->kvm, &irq, 447 vcpu_bitmap); 448 } 449 kvm_make_scan_ioapic_request_mask(ioapic->kvm, 450 vcpu_bitmap); 451 } else { 452 kvm_make_scan_ioapic_request(ioapic->kvm); 453 } 454 break; 455 } 456 } 457 458 static int ioapic_service(struct kvm_ioapic *ioapic, int irq, bool line_status) 459 { 460 union kvm_ioapic_redirect_entry *entry = &ioapic->redirtbl[irq]; 461 struct kvm_lapic_irq irqe; 462 int ret; 463 464 if (entry->fields.mask || 465 (entry->fields.trig_mode == IOAPIC_LEVEL_TRIG && 466 entry->fields.remote_irr)) 467 return -1; 468 469 irqe.dest_id = entry->fields.dest_id; 470 irqe.vector = entry->fields.vector; 471 irqe.dest_mode = kvm_lapic_irq_dest_mode(!!entry->fields.dest_mode); 472 irqe.trig_mode = entry->fields.trig_mode; 473 irqe.delivery_mode = entry->fields.delivery_mode << 8; 474 irqe.level = 1; 475 irqe.shorthand = APIC_DEST_NOSHORT; 476 irqe.msi_redir_hint = false; 477 478 if (irqe.trig_mode == IOAPIC_EDGE_TRIG) 479 ioapic->irr_delivered |= 1 << irq; 480 481 if (irq == RTC_GSI && line_status) { 482 /* 483 * pending_eoi cannot ever become negative (see 484 * rtc_status_pending_eoi_check_valid) and the caller 485 * ensures that it is only called if it is >= zero, namely 486 * if rtc_irq_check_coalesced returns false). 487 */ 488 WARN_ON_ONCE(ioapic->rtc_status.pending_eoi); 489 ret = __kvm_irq_delivery_to_apic(ioapic->kvm, NULL, &irqe, 490 &ioapic->rtc_status); 491 ioapic->rtc_status.pending_eoi = (ret < 0 ? 0 : ret); 492 } else 493 ret = kvm_irq_delivery_to_apic(ioapic->kvm, NULL, &irqe); 494 495 if (ret && irqe.trig_mode == IOAPIC_LEVEL_TRIG) 496 entry->fields.remote_irr = 1; 497 498 return ret; 499 } 500 501 int kvm_ioapic_set_irq(struct kvm_kernel_irq_routing_entry *e, struct kvm *kvm, 502 int irq_source_id, int level, bool line_status) 503 { 504 struct kvm_ioapic *ioapic = kvm->arch.vioapic; 505 int irq = e->irqchip.pin; 506 int ret, irq_level; 507 508 if (WARN_ON_ONCE(irq < 0 || irq >= IOAPIC_NUM_PINS)) 509 return -1; 510 511 spin_lock(&ioapic->lock); 512 irq_level = __kvm_irq_line_state(&ioapic->irq_states[irq], 513 irq_source_id, level); 514 ret = ioapic_set_irq(ioapic, irq, irq_level, line_status); 515 516 spin_unlock(&ioapic->lock); 517 518 return ret; 519 } 520 521 static void kvm_ioapic_eoi_inject_work(struct work_struct *work) 522 { 523 int i; 524 struct kvm_ioapic *ioapic = container_of(work, struct kvm_ioapic, 525 eoi_inject.work); 526 spin_lock(&ioapic->lock); 527 for (i = 0; i < IOAPIC_NUM_PINS; i++) { 528 union kvm_ioapic_redirect_entry *ent = &ioapic->redirtbl[i]; 529 530 if (ent->fields.trig_mode != IOAPIC_LEVEL_TRIG) 531 continue; 532 533 if (ioapic->irr & (1 << i) && !ent->fields.remote_irr) 534 ioapic_service(ioapic, i, false); 535 } 536 spin_unlock(&ioapic->lock); 537 } 538 539 #define IOAPIC_SUCCESSIVE_IRQ_MAX_COUNT 10000 540 static void kvm_ioapic_update_eoi_one(struct kvm_vcpu *vcpu, 541 struct kvm_ioapic *ioapic, 542 int trigger_mode, 543 int pin) 544 { 545 struct kvm_lapic *apic = vcpu->arch.apic; 546 union kvm_ioapic_redirect_entry *ent = &ioapic->redirtbl[pin]; 547 548 /* 549 * We are dropping lock while calling ack notifiers because ack 550 * notifier callbacks for assigned devices call into IOAPIC 551 * recursively. Since remote_irr is cleared only after call 552 * to notifiers if the same vector will be delivered while lock 553 * is dropped it will be put into irr and will be delivered 554 * after ack notifier returns. 555 */ 556 spin_unlock(&ioapic->lock); 557 kvm_notify_acked_irq(ioapic->kvm, KVM_IRQCHIP_IOAPIC, pin); 558 spin_lock(&ioapic->lock); 559 560 if (trigger_mode != IOAPIC_LEVEL_TRIG || 561 kvm_lapic_suppress_eoi_broadcast(apic)) 562 return; 563 564 ent->fields.remote_irr = 0; 565 if (!ent->fields.mask && (ioapic->irr & (1 << pin))) { 566 ++ioapic->irq_eoi[pin]; 567 if (ioapic->irq_eoi[pin] == IOAPIC_SUCCESSIVE_IRQ_MAX_COUNT) { 568 /* 569 * Real hardware does not deliver the interrupt 570 * immediately during eoi broadcast, and this 571 * lets a buggy guest make slow progress 572 * even if it does not correctly handle a 573 * level-triggered interrupt. Emulate this 574 * behavior if we detect an interrupt storm. 575 */ 576 schedule_delayed_work(&ioapic->eoi_inject, HZ / 100); 577 ioapic->irq_eoi[pin] = 0; 578 trace_kvm_ioapic_delayed_eoi_inj(ent->bits); 579 } else { 580 ioapic_service(ioapic, pin, false); 581 } 582 } else { 583 ioapic->irq_eoi[pin] = 0; 584 } 585 } 586 587 void kvm_ioapic_update_eoi(struct kvm_vcpu *vcpu, int vector, int trigger_mode) 588 { 589 int i; 590 struct kvm_ioapic *ioapic = vcpu->kvm->arch.vioapic; 591 592 spin_lock(&ioapic->lock); 593 rtc_irq_eoi(ioapic, vcpu, vector); 594 for (i = 0; i < IOAPIC_NUM_PINS; i++) { 595 union kvm_ioapic_redirect_entry *ent = &ioapic->redirtbl[i]; 596 597 if (ent->fields.vector != vector) 598 continue; 599 kvm_ioapic_update_eoi_one(vcpu, ioapic, trigger_mode, i); 600 } 601 spin_unlock(&ioapic->lock); 602 } 603 604 static inline struct kvm_ioapic *to_ioapic(struct kvm_io_device *dev) 605 { 606 return container_of(dev, struct kvm_ioapic, dev); 607 } 608 609 static inline int ioapic_in_range(struct kvm_ioapic *ioapic, gpa_t addr) 610 { 611 return ((addr >= ioapic->base_address && 612 (addr < ioapic->base_address + IOAPIC_MEM_LENGTH))); 613 } 614 615 static int ioapic_mmio_read(struct kvm_vcpu *vcpu, struct kvm_io_device *this, 616 gpa_t addr, int len, void *val) 617 { 618 struct kvm_ioapic *ioapic = to_ioapic(this); 619 u32 result; 620 if (!ioapic_in_range(ioapic, addr)) 621 return -EOPNOTSUPP; 622 623 addr &= 0xff; 624 spin_lock(&ioapic->lock); 625 switch (addr) { 626 case IOAPIC_REG_SELECT: 627 result = ioapic->ioregsel; 628 break; 629 630 case IOAPIC_REG_WINDOW: 631 result = ioapic_read_indirect(ioapic); 632 break; 633 634 default: 635 result = 0; 636 break; 637 } 638 spin_unlock(&ioapic->lock); 639 640 switch (len) { 641 case 8: 642 *(u64 *) val = result; 643 break; 644 case 1: 645 case 2: 646 case 4: 647 memcpy(val, (char *)&result, len); 648 break; 649 default: 650 printk(KERN_WARNING "ioapic: wrong length %d\n", len); 651 } 652 return 0; 653 } 654 655 static int ioapic_mmio_write(struct kvm_vcpu *vcpu, struct kvm_io_device *this, 656 gpa_t addr, int len, const void *val) 657 { 658 struct kvm_ioapic *ioapic = to_ioapic(this); 659 u32 data; 660 if (!ioapic_in_range(ioapic, addr)) 661 return -EOPNOTSUPP; 662 663 switch (len) { 664 case 8: 665 case 4: 666 data = *(u32 *) val; 667 break; 668 case 2: 669 data = *(u16 *) val; 670 break; 671 case 1: 672 data = *(u8 *) val; 673 break; 674 default: 675 printk(KERN_WARNING "ioapic: Unsupported size %d\n", len); 676 return 0; 677 } 678 679 addr &= 0xff; 680 spin_lock(&ioapic->lock); 681 switch (addr) { 682 case IOAPIC_REG_SELECT: 683 ioapic->ioregsel = data & 0xFF; /* 8-bit register */ 684 break; 685 686 case IOAPIC_REG_WINDOW: 687 ioapic_write_indirect(ioapic, data); 688 break; 689 690 default: 691 break; 692 } 693 spin_unlock(&ioapic->lock); 694 return 0; 695 } 696 697 static void kvm_ioapic_reset(struct kvm_ioapic *ioapic) 698 { 699 int i; 700 701 cancel_delayed_work_sync(&ioapic->eoi_inject); 702 for (i = 0; i < IOAPIC_NUM_PINS; i++) 703 ioapic->redirtbl[i].fields.mask = 1; 704 ioapic->base_address = IOAPIC_DEFAULT_BASE_ADDRESS; 705 ioapic->ioregsel = 0; 706 ioapic->irr = 0; 707 ioapic->irr_delivered = 0; 708 ioapic->id = 0; 709 memset(ioapic->irq_eoi, 0x00, sizeof(ioapic->irq_eoi)); 710 rtc_irq_eoi_tracking_reset(ioapic); 711 } 712 713 static const struct kvm_io_device_ops ioapic_mmio_ops = { 714 .read = ioapic_mmio_read, 715 .write = ioapic_mmio_write, 716 }; 717 718 int kvm_ioapic_init(struct kvm *kvm) 719 { 720 struct kvm_ioapic *ioapic; 721 int ret; 722 723 ioapic = kzalloc_obj(struct kvm_ioapic, GFP_KERNEL_ACCOUNT); 724 if (!ioapic) 725 return -ENOMEM; 726 spin_lock_init(&ioapic->lock); 727 INIT_DELAYED_WORK(&ioapic->eoi_inject, kvm_ioapic_eoi_inject_work); 728 INIT_HLIST_HEAD(&ioapic->mask_notifier_list); 729 kvm->arch.vioapic = ioapic; 730 kvm_ioapic_reset(ioapic); 731 kvm_iodevice_init(&ioapic->dev, &ioapic_mmio_ops); 732 ioapic->kvm = kvm; 733 mutex_lock(&kvm->slots_lock); 734 ret = kvm_io_bus_register_dev(kvm, KVM_MMIO_BUS, ioapic->base_address, 735 IOAPIC_MEM_LENGTH, &ioapic->dev); 736 mutex_unlock(&kvm->slots_lock); 737 if (ret < 0) { 738 kvm->arch.vioapic = NULL; 739 kfree(ioapic); 740 } 741 742 return ret; 743 } 744 745 void kvm_ioapic_destroy(struct kvm *kvm) 746 { 747 struct kvm_ioapic *ioapic = kvm->arch.vioapic; 748 749 if (!ioapic) 750 return; 751 752 cancel_delayed_work_sync(&ioapic->eoi_inject); 753 mutex_lock(&kvm->slots_lock); 754 kvm_io_bus_unregister_dev(kvm, KVM_MMIO_BUS, &ioapic->dev); 755 mutex_unlock(&kvm->slots_lock); 756 kvm->arch.vioapic = NULL; 757 kfree(ioapic); 758 } 759 760 void kvm_get_ioapic(struct kvm *kvm, struct kvm_ioapic_state *state) 761 { 762 struct kvm_ioapic *ioapic = kvm->arch.vioapic; 763 764 spin_lock(&ioapic->lock); 765 memcpy(state, ioapic, sizeof(struct kvm_ioapic_state)); 766 state->irr &= ~ioapic->irr_delivered; 767 spin_unlock(&ioapic->lock); 768 } 769 770 void kvm_set_ioapic(struct kvm *kvm, struct kvm_ioapic_state *state) 771 { 772 struct kvm_ioapic *ioapic = kvm->arch.vioapic; 773 774 spin_lock(&ioapic->lock); 775 memcpy(ioapic, state, sizeof(struct kvm_ioapic_state)); 776 ioapic->irr = 0; 777 ioapic->irr_delivered = 0; 778 kvm_make_scan_ioapic_request(kvm); 779 kvm_ioapic_inject_all(ioapic, state->irr); 780 spin_unlock(&ioapic->lock); 781 } 782